GlobalEdge: CSI and TCI related MAC CE intial commit

cmake_targets/CMakeLists.txt

@@ -249,6 +249,7 @@ add_boolean_option(UE_AUTOTEST_TRACE   False "Activate UE autotest specific logs
 add_boolean_option(UE_DEBUG_TRACE      False "Activate UE debug trace")
 add_boolean_option(UE_TIMING_TRACE     False "Activate UE timing trace")
 add_boolean_option(DEBUG_CONSOLE       False "makes debugging easier, disables stdout/stderr buffering")
+add_boolean_option(GES_SUPPORT       True "To enable the GES Code")
 
 set (OCP_ITTI ${OPENAIR_DIR}/common/utils/ocp_itti)
 add_library(ITTI

openair2/LAYER2/NR_MAC_COMMON/nr_mac.h

@@ -137,6 +137,66 @@ typedef struct {
     uint8_t R2: 6;
 } __attribute__ ((__packed__)) NR_SINGLE_ENTRY_PHR_MAC_CE;
 
+#ifdef GES_SUPPORT
+
+// SP ZP CSI-RS Resource Set Activation/Deactivation MAC CE
+// 38.321 ch. 6.1.3.19
+typedef struct {
+    uint8_t BWPID: 2;       // octet 1 [1:0]
+    uint8_t CELLID: 5;      // octet 1 [6:2]
+    uint8_t A_D: 1;         // octet 1 [7]
+    uint8_t CSIRS_RSC_ID: 4; // octet 2 [3:0]
+    uint8_t R: 4            // octet 2 [7:4]
+} __attribute__ ((__packed__)) NR_MAC_CE_SP_ZP_CSI_RS_RES_SET;
+
+//TS 38.321 Sec 6.1.3.15, TCI State indicaton for UE-Specific PDCCH MAC CE
+typedef struct {
+    uint8_t CoresetId1: 3;   //Octect 1 [2:0]
+    uint8_t ServingCellId: 5; //Octect 1 [7:3]
+    uint8_t TciStateId: 7;   //Octect 2 [6:0]
+    uint8_t CoresetId2: 1;   //Octect 2 [7]
+} __attribute__ ((__packed__)) NR_TCI_PDCCH;
+
+//TS 38.321 Sec 6.1.3.14, TCI State activation/deactivation for UE Specific PDSCH MAC CE
+typedef struct {
+    uint8_t BWP_Id: 2;       //Octect 1 [1:0]
+    uint8_t ServingCellId: 5; //Octect 1 [6:2]
+    uint8_t R: 1;            //Octect 1 [7]
+    uint8_t T[];             //Octects 2 to MAX TCI States/8
+} __attribute__ ((__packed__)) NR_TCI_PDSCH_APERIODIC_CSI;
+
+//TS 6.1.3.16, SP CSI reporting on PUCCH Activation/Deactivation MAC CE
+typedef struct {
+    uint8_t BWP_Id: 2;			//Octect 1 [1:0]
+    uint8_t ServingCellId: 5; //Octect 1 [6:2]
+    uint8_t R1: 1;				//Octect 1 [7]
+    uint8_t S0: 1;				//Octect 2 [0]
+    uint8_t S1: 1;				//Octect 2 [1]
+    uint8_t S2: 1;				//Octect 2 [2]
+    uint8_t S3: 1;				//Octect 2 [3]
+    uint8_t R2: 4;				//Octect 2 [7:4]
+} __attribute__ ((__packed__)) NR_PUCCH_CSI_REPORTING;
+
+
+//TS 38.321 sec 6.1.3.12
+//SP CSI-RS / CSI-IM Resource Set Activation/Deactivation MAC CE
+typedef struct {
+    uint8_t BWP_ID: 2;
+    uint8_t SCID: 5;
+    uint8_t A_D: 1;
+    uint8_t SP_CSI_RSID: 6;
+    uint8_t IM: 1;
+    uint8_t R1: 1;
+    uint8_t SP_CSI_IMID: 6;
+    uint8_t R2: 2;
+    struct TCI_S {
+        uint8_t TCI_STATE_ID: 6;
+        uint8_t R: 2;
+    } __attribute__ ((__packed__)) TCI_STATE;
+} __attribute__ ((__packed__)) CSI_RS_CSI_IM_ACT_DEACT_MAC_CE;
+
+#endif
+
 //* RAR MAC subheader // TS 38.321 ch. 6.1.5, 6.2.2 *//
 // - E: The Extension field is a flag indicating if the MAC subPDU including this MAC subheader is the last MAC subPDU or not in the MAC PDU
 // - T: The Type field is a flag indicating whether the MAC subheader contains a Random Access Preamble ID or a Backoff Indicator (0, BI) (1, RAPID)

openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c

@@ -47,6 +47,12 @@
 ////////////////////////////////////////////////////////
 /////* DLSCH MAC PDU generation (6.1.2 TS 38.321) */////
 ////////////////////////////////////////////////////////
+#ifdef GES_SUPPORT
+#define OCTET 8
+#define HALFWORD 16
+#define WORD 32
+//#define SIZE_OF_POINTER sizeof (void *)
+#endif
 
 int nr_generate_dlsch_pdu(module_id_t module_idP,
                           unsigned char *sdus_payload,
@@ -67,6 +73,14 @@ int nr_generate_dlsch_pdu(module_id_t module_idP,
     // MAC CEs
     uint8_t mac_header_control_elements[16], *ce_ptr;
     ce_ptr = &mac_header_control_elements[0];
+#ifdef GES_SUPPORT
+    uint16_t UE_id = 0; //TODO need to get as a function parameter or need to invoke api to UE_id using module Id and RNTI
+    gNB_MAC_INST *gNB_mac = RC.nrmac[module_idP];
+    NR_UE_list_t *UE_list = &gNB_mac->UE_list;
+    NR_UE_sched_ctrl_t *ue_sched_ctl = NULL;
+    //NR_CellGroupConfig_t *config = UE_list->secondaryCellGroup[UE_id];
+    ue_sched_ctl = &(UE_list->UE_sched_ctrl[UE_id]);
+#endif
 
     // 1) Compute MAC CE and related subheaders
 
@@ -132,6 +146,173 @@ int nr_generate_dlsch_pdu(module_id_t module_idP,
         mac_pdu_ptr += (unsigned char) mac_ce_size;
     }
 
+#ifdef GES_SUPPORT
+
+    //TS 38.321 Sec 6.1.3.15 TCI State indication for UE Specific PDCCH MAC CE SubPDU generation
+    if (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.is_scheduled) {
+        //filling subheader
+        mac_pdu_ptr->R = 0;
+        mac_pdu_ptr->LCID = DL_SCH_LCID_TCI_STATE_IND_UE_SPEC_PDCCH;
+        mac_pdu_ptr++;
+        //Creating the instance of CE structure
+        NR_TCI_PDCCH  nr_UESpec_TCI_StateInd_PDCCH;
+        //filling the CE structre
+        nr_UESpec_TCI_StateInd_PDCCH.CoresetId1 = ((ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0xF) >> 1; //extracting MSB 3 bits from LS nibble
+        nr_UESpec_TCI_StateInd_PDCCH.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.servingCellId) & 0x1F; //extracting LSB 5 Bits
+        nr_UESpec_TCI_StateInd_PDCCH.TciStateId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.tciStateId) & 0x7F; //extracting LSB 7 bits
+        nr_UESpec_TCI_StateInd_PDCCH.CoresetId2 = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0x1; //extracting LSB 1 bit
+        LOG_D(MAC, "NR MAC CE TCI state indication for UE Specific PDCCH = %d \n", nr_UESpec_TCI_StateInd_PDCCH.TciStateId);
+        mac_ce_size = sizeof(NR_TCI_PDCCH);
+        // Copying  bytes for MAC CEs to the mac pdu pointer
+        memcpy((void *) mac_pdu_ptr, (void *)&nr_UESpec_TCI_StateInd_PDCCH, mac_ce_size);
+        //incrementing the PDU pointer
+        mac_pdu_ptr += (unsigned char) mac_ce_size;
+    }
+
+    //TS 38.321 Sec 6.1.3.16, SP CSI reporting on PUCCH Activation/Deactivation MAC CE
+    if (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.is_scheduled) {
+        //filling the subheader
+        mac_pdu_ptr->R = 0;
+        mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_REP_PUCCH_ACT;
+        mac_pdu_ptr++;
+        //creating the instance of CE structure
+        NR_PUCCH_CSI_REPORTING nr_PUCCH_CSI_reportingActDeact;
+        //filling the CE structure
+        nr_PUCCH_CSI_reportingActDeact.BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.bwpId) & 0x3; //extracting LSB 2 bibs
+        nr_PUCCH_CSI_reportingActDeact.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.servingCellId) & 0x1F; //extracting LSB 5 bits
+        nr_PUCCH_CSI_reportingActDeact.S0 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[0];
+        nr_PUCCH_CSI_reportingActDeact.S1 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[1];
+        nr_PUCCH_CSI_reportingActDeact.S2 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[2];
+        nr_PUCCH_CSI_reportingActDeact.S3 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[3];
+        nr_PUCCH_CSI_reportingActDeact.R2 = 0;
+        mac_ce_size = sizeof(NR_PUCCH_CSI_REPORTING);
+        // Copying MAC CE data to the mac pdu pointer
+        memcpy((void *) mac_pdu_ptr, (void *)&nr_PUCCH_CSI_reportingActDeact, mac_ce_size);
+        //incrementing the PDU pointer
+        mac_pdu_ptr += (unsigned char) mac_ce_size;
+    }
+
+    //TS 38.321 Sec 6.1.3.14, TCI State activation/deactivation for UE Specific PDSCH MAC CE
+    if (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.is_scheduled) {
+        //Computing the number of octects to be allocated for Flexible array member
+        //of MAC CE structure
+        uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.highestTciStateActivated) / 8 + 1; //Calculating the number of octects for allocating the memory
+
+        //filling the subheader
+        ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0;
+        ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0;
+        ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_TCI_STATE_ACT_UE_SPEC_PDSCH;
+        ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t);
+        last_size = 2;
+        //Incrementing the PDU pointer
+        mac_pdu_ptr += last_size;
+        //allocating memory for CE Structure
+        NR_TCI_PDSCH_APERIODIC_CSI *nr_UESpec_TCI_StateInd_PDSCH = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t));
+        //initializing to zero
+        memset((void *)nr_UESpec_TCI_StateInd_PDSCH, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t));
+        //filling the CE Structure
+        nr_UESpec_TCI_StateInd_PDSCH->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.bwpId) & 0x3; //extracting LSB 2 Bits
+        nr_UESpec_TCI_StateInd_PDSCH->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.servingCellId) & 0x1F; //extracting LSB 5 bits
+        for(i = 0; i < (num_octects * 8); i++) {
+            if(ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.tciStateActDeact[i])
+                nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] = nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] | (1 << (i % 8));
+        }
+        mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t);
+        //Copying  bytes for MAC CEs to the mac pdu pointer
+        memcpy((void *) mac_pdu_ptr, (void *)nr_UESpec_TCI_StateInd_PDSCH, mac_ce_size);
+        //incrementing the mac pdu pointer
+        mac_pdu_ptr += (unsigned char) mac_ce_size;
+        //freeing the allocated memory
+        free(nr_UESpec_TCI_StateInd_PDSCH);
+    }
+
+    //TS38.321 Sec 6.1.3.13 Aperiodic CSI Trigger State Subselection MAC CE
+    if (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.is_scheduled) {
+        //Computing the number of octects to be allocated for Flexible array member
+        //of MAC CE structure
+        uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.highestTriggerStateSelected) / 8 + 1; //Calculating the number of octects for allocating the memory
+
+        //filling the subheader
+        ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0;
+        ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0;
+        ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_APERIODIC_CSI_TRI_STATE_SUBSEL;
+        ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t);
+        last_size = 2;
+        //Incrementing the PDU pointer
+        mac_pdu_ptr += last_size;
+        //allocating memory for CE structure
+        NR_TCI_PDSCH_APERIODIC_CSI *nr_Aperiodic_CSI_Trigger = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t));
+        //initializing to zero
+        memset((void *)nr_Aperiodic_CSI_Trigger, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t));
+        //filling the CE Structure
+        nr_Aperiodic_CSI_Trigger->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.bwpId) & 0x3; //extracting LSB 2 bits
+        nr_Aperiodic_CSI_Trigger->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.servingCellId) & 0x1F; //extracting LSB 5 bits
+        nr_Aperiodic_CSI_Trigger->R = 0;
+        for(i = 0; i < (num_octects * 8); i++) {
+            if(ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.triggerStateSelection[i])
+                nr_Aperiodic_CSI_Trigger->T[i / 8] = nr_Aperiodic_CSI_Trigger->T[i / 8] | (1 << (i % 8));
+        }
+        mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t);
+        // Copying  bytes for MAC CEs to the mac pdu pointer
+        memcpy((void *) mac_pdu_ptr, (void *)nr_Aperiodic_CSI_Trigger, mac_ce_size);
+        //incrementing the mac pdu pointer
+        mac_pdu_ptr += (unsigned char) mac_ce_size;
+        //freeing the allocated memory
+        free(nr_Aperiodic_CSI_Trigger);
+    }
+
+    if (ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.is_scheduled) {
+        ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0;
+        ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_SP_ZP_CSI_RS_RES_SET_ACT;
+        mac_pdu_ptr++;
+        ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->A_D = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.act_deact;
+        ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CELLID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id & 0x1F; //5 bits
+        ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->BWPID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid & 0x3; //2 bits
+        ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CSIRS_RSC_ID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id & 0xF; //4 bits
+        ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->R = 0;
+        LOG_D(MAC, "NR MAC CE of ZP CSIRS Serv cell ID = %d BWPID= %d Rsc set ID = %d\n", ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id, ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid, ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id);
+        mac_ce_size = sizeof(NR_MAC_CE_SP_ZP_CSI_RS_RES_SET);
+        mac_pdu_ptr += (unsigned char) mac_ce_size;
+    }
+
+    if (ue_sched_ctl->UE_mac_ce_ctrl.csi_im.is_scheduled) {
+        mac_pdu_ptr->R = 0;
+        mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT;
+        mac_pdu_ptr++;
+        CSI_RS_CSI_IM_ACT_DEACT_MAC_CE csi_rs_im_act_deact_ce;
+        csi_rs_im_act_deact_ce.A_D = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.act_deact;
+        csi_rs_im_act_deact_ce.SCID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.serv_cellid & 0x3F;//gNB_PHY -> ssb_pdu.ssb_pdu_rel15.PhysCellId;
+        csi_rs_im_act_deact_ce.BWP_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.bwp_id;
+        csi_rs_im_act_deact_ce.R1 = 0;
+        csi_rs_im_act_deact_ce.IM = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.im;// IF set CSI IM Rsc id will presesent else CSI IM RSC ID is abscent
+        csi_rs_im_act_deact_ce.SP_CSI_RSID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nzp_csi_rsc_id;
+
+        if ( csi_rs_im_act_deact_ce.IM ) { //is_scheduled if IM is 1 else this field will not present
+            csi_rs_im_act_deact_ce.R2 = 0;
+            csi_rs_im_act_deact_ce.SP_CSI_IMID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.csi_im_rsc_id;
+            mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE );
+        } else {
+            mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE ) - 1;
+        }
+
+        memcpy ((void *) mac_pdu_ptr, (void *) & ( csi_rs_im_act_deact_ce), mac_ce_size);
+        mac_pdu_ptr += (unsigned char) mac_ce_size;
+
+        if (csi_rs_im_act_deact_ce.A_D ) { //Following IE is_scheduled only if A/D is 1
+            mac_ce_size = sizeof ( struct TCI_S);
+
+            for ( i = 0; i < ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nb_tci_resource_set_id; i++) {
+                csi_rs_im_act_deact_ce.TCI_STATE.R = 0;
+                csi_rs_im_act_deact_ce.TCI_STATE.TCI_STATE_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.tci_state_id [i] & 0x7F;
+                memcpy ((void *) mac_pdu_ptr, (void *) & (csi_rs_im_act_deact_ce.TCI_STATE), mac_ce_size);
+                mac_pdu_ptr += (unsigned char) mac_ce_size;
+            }
+
+        }
+    }
+
+#endif
+
     // 2) Generation of DLSCH MAC subPDUs including subheaders and MAC SDUs
     for (i = 0; i < num_sdus; i++) {
         LOG_D(MAC, "[gNB] Generate DLSCH header num sdu %d len sdu %d\n", num_sdus, sdu_lengths[i]);

openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h

@@ -179,9 +179,80 @@ typedef struct {
     uint8_t num_sf_allocation_pattern;
 } NR_COMMON_channels_t;
 
+#ifdef GES_SUPPORT
+
+// SP ZP CSI-RS Resource Set Activation/Deactivation MAC CE
+typedef struct sp_zp_csirs {
+    bool is_scheduled;     //ZP CSI-RS ACT/Deact MAC CE is scheduled
+    bool act_deact;        //Activation/Deactivation indication
+    uint8_t serv_cell_id;  //Identity of Serving cell for which MAC CE applies
+    uint8_t bwpid;         //Downlink BWP id
+    uint8_t rsc_id;        //SP ZP CSI-RS resource set
+} sp_zp_csirs_t;
+
+//SP CSI-RS / CSI-IM Resource Set Activation/Deactivation MAC CE
+#define MAX_CSI_RESOURCE_SET 64
+typedef struct csi_rs_im {
+    bool is_scheduled;
+    bool act_deact;
+    uint8_t serv_cellid;
+    uint8_t bwp_id;
+    bool im;
+    uint8_t csi_im_rsc_id;
+    uint8_t nzp_csi_rsc_id;
+    uint8_t nb_tci_resource_set_id;
+    uint8_t tci_state_id [ MAX_CSI_RESOURCE_SET ];
+} csi_rs_im_t;
+
+typedef struct pdcchStateInd {
+    bool is_scheduled;
+    uint8_t servingCellId;
+    uint8_t coresetId;
+    uint8_t tciStateId;
+} pdcchStateInd_t;
+
+typedef struct SPCSIReportingpucch {
+    bool is_scheduled;
+    uint8_t servingCellId;
+    uint8_t bwpId;
+    bool s0tos3_actDeact[4];
+} SPCSIReportingpucch_t;
+
+#define MAX_APERIODIC_TRIGGER_STATES 128 //38.331                               
+typedef struct aperiodicCSI_triggerStateSelection {
+    bool is_scheduled;
+    uint8_t servingCellId;
+    uint8_t bwpId;
+    uint8_t highestTriggerStateSelected;
+    bool triggerStateSelection[MAX_APERIODIC_TRIGGER_STATES];
+} aperiodicCSI_triggerStateSelection_t;
+
+#define MAX_TCI_STATES 128 //38.331                                             
+typedef struct pdschTciStatesActDeact {
+    bool is_scheduled;
+    uint8_t servingCellId;
+    uint8_t bwpId;
+    uint8_t highestTciStateActivated;
+    bool tciStateActDeact[MAX_TCI_STATES];
+} pdschTciStatesActDeact_t;
+
+typedef struct UE_info {
+    sp_zp_csirs_t sp_zp_csi_rs;
+    csi_rs_im_t csi_im;
+    pdcchStateInd_t pdcch_state_ind;
+    SPCSIReportingpucch_t SP_CSI_reporting_pucch;
+    aperiodicCSI_triggerStateSelection_t aperi_CSI_trigger;
+    pdschTciStatesActDeact_t pdsch_TCI_States_ActDeact;
+} NR_UE_mac_ce_ctrl_t;
+
+#endif
+
 /*! \brief scheduling control information set through an API (not used)*/
 typedef struct {
     int dummy;
+#ifdef GES_SUPPORT
+    NR_UE_mac_ce_ctrl_t UE_mac_ce_ctrl;// MAC CE related information
+#endif
 } NR_UE_sched_ctrl_t;
 
 /*! \brief UE list used by gNB to order UEs/CC for scheduling*/