Merge remote-tracking branch 'origin/ntn-phy-test' into integration_2026_w12 (!3970)

Fix for NTN phy-test mode

- Corrected the initialisation of ntn params changed flag. Before this change on
  UE, Phy-test was not running in NTN mode.
- Removed the assert wrt slot > 64 to run FR2-NTN in phy-test
- SIB2, 19 required only in SA mode like SIB1
- Introduced new method to schedule a slot in UL/DL in Phy-test mode. Dmod/ Umod
  option in the command line with a value.
  - This ensures that the slot n (in slots per frame) will be scheduled if
    n % value == 0
  - For ex: --Dmod 1 means every slot will be scheduled
  - --Dmod 2 means every 2nd slot will be scheduled, like 0,2,4,6 until the
    slots per frame 1.
  - this can be used for testing FDD FR2 where slots go beyond 64 which is a
    limitation of -D/-U option.
This commit is contained in:
Jaroslava Fiedlerova
2026-03-17 14:25:40 +01:00
7 changed files with 36 additions and 9 deletions
+2
View File
@@ -55,5 +55,7 @@
#define CONFIG_HLP_ULBW_PHYTEST "Set the number of PRBs used for ULSCH in PHYTEST mode\n"
#define CONFIG_HLP_DLBM_PHYTEST "Bitmap for DLSCH slots in period (slot 0 starts at LSB)\n"
#define CONFIG_HLP_ULBM_PHYTEST "Bitmap for ULSCH slots in period (slot 0 starts at LSB)\n"
#define CONFIG_HLP_DLMOD_PHYTEST "For-DLSCH, if val is n, every nth slot in slots per frame will be scheduled. \n"
#define CONFIG_HLP_ULMOD_PHYTEST "For ULSCH, if val is n, every nth slot in slots per frame will be scheduled. \n"
void wait_gNBs(void);
#endif
+4
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@@ -25,6 +25,8 @@
{"T" , CONFIG_HLP_ULBW_PHYTEST, 0, .uptr=&target_ul_bw, .defintval=0, TYPE_UINT, 0}, \
{"D" , CONFIG_HLP_DLBM_PHYTEST, 0, .u64ptr=&dlsch_slot_bitmap, .defint64val=0, TYPE_UINT64, 0}, \
{"U" , CONFIG_HLP_ULBM_PHYTEST, 0, .u64ptr=&ulsch_slot_bitmap, .defint64val=0, TYPE_UINT64, 0}, \
{"Dmod" , CONFIG_HLP_DLMOD_PHYTEST, 0, .uptr=&dlsch_slot_modval, .defintval=0, TYPE_UINT, 0}, \
{"Umod" , CONFIG_HLP_ULMOD_PHYTEST, 0, .uptr=&ulsch_slot_modval, .defintval=0, TYPE_UINT, 0}, \
{"usrp-tx-thread-config", CONFIG_HLP_USRP_THREAD, 0, .iptr=&usrp_tx_thread, .defstrval=0, TYPE_INT, 0}, \
{"uecap_file", CONFIG_HLP_UECAP_FILE, 0, .strptr=&uecap_file, .defstrval="./uecap_ports1.xml", TYPE_STRING, 0}, \
}
@@ -39,6 +41,8 @@ extern uint32_t target_ul_bw;
extern uint64_t dlsch_slot_bitmap;
extern uint64_t ulsch_slot_bitmap;
extern char *uecap_file;
extern uint32_t dlsch_slot_modval;
extern uint32_t ulsch_slot_modval;
// In nr-gnb.c
extern void init_gNB();
-2
View File
@@ -177,8 +177,6 @@ void init_nr_ue_vars(PHY_VARS_NR_UE *ue, uint8_t UE_id)
ue->dci_thres = 0;
ue->target_Nid_cell = -1;
ue->nrUE_config.ntn_config.params_changed = false;
// initialize all signal buffers
init_nr_ue_signal(ue, nb_connected_gNB);