Merge remote-tracking branch 'origin/enable_ta_for_phytest' into develop_integration_2020_w26
This commit is contained in:
@@ -361,7 +361,6 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
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int CC_id, UE_id = 0;
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int CC_id, UE_id = 0;
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gNB_MAC_INST *gNB = RC.nrmac[module_idP];
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gNB_MAC_INST *gNB = RC.nrmac[module_idP];
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NR_UE_list_t *UE_list = &gNB->UE_list;
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NR_UE_list_t *UE_list = &gNB->UE_list;
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NR_UE_sched_ctrl_t *ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
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NR_COMMON_channels_t *cc = gNB->common_channels;
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NR_COMMON_channels_t *cc = gNB->common_channels;
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NR_sched_pucch *pucch_sched = (NR_sched_pucch*) malloc(sizeof(NR_sched_pucch));
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NR_sched_pucch *pucch_sched = (NR_sched_pucch*) malloc(sizeof(NR_sched_pucch));
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@@ -407,8 +406,13 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
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schedule_nr_mib(module_idP, frame_txP, slot_txP);
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schedule_nr_mib(module_idP, frame_txP, slot_txP);
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}
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}
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// Phytest scheduling
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if (get_softmodem_params()->phy_test) {
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NR_UE_sched_ctrl_t *ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
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// TbD once RACH is available, start ta_timer when UE is connected
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// TbD once RACH is available, start ta_timer when UE is connected
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if (ue_sched_ctl->ta_timer) ue_sched_ctl->ta_timer--;
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if (ue_sched_ctl->ta_timer)
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ue_sched_ctl->ta_timer--;
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if (ue_sched_ctl->ta_timer == 0) {
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if (ue_sched_ctl->ta_timer == 0) {
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gNB->ta_command = ue_sched_ctl->ta_update;
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gNB->ta_command = ue_sched_ctl->ta_update;
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@@ -421,16 +425,15 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
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gNB->ta_len = 2;
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gNB->ta_len = 2;
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}
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}
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if (get_softmodem_params()->phy_test == 0)
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if (slot_txP == 1){
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nr_schedule_RA(module_idP, frame_txP, slot_txP);
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// Phytest scheduling
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if (get_softmodem_params()->phy_test && slot_txP==1){
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nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, pucch_sched, NULL);
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nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, pucch_sched, NULL);
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// resetting ta flag
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// resetting ta flag
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gNB->ta_len = 0;
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gNB->ta_len = 0;
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}
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}
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}
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if (get_softmodem_params()->phy_test == 0)
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nr_schedule_RA(module_idP, frame_txP, slot_txP);
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/*
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/*
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// Allocate CCEs for good after scheduling is done
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// Allocate CCEs for good after scheduling is done
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@@ -33,10 +33,10 @@ gNBs =
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# downlinkConfigCommon
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# downlinkConfigCommon
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#frequencyInfoDL
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#frequencyInfoDL
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# this is 3600 MHz + 43 PRBs@30kHz SCS (same as initial BWP)
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# this is 3600 MHz + 43 PRBs@30kHz SCS (same as initial BWP)
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absoluteFrequencySSB = 633032;
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absoluteFrequencySSB = 641032;
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dl_frequencyBand = 78;
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dl_frequencyBand = 78;
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# this is 3480 MHz
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# this is 3600 MHz
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dl_absoluteFrequencyPointA = 632000;
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dl_absoluteFrequencyPointA = 640000;
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#scs-SpecificCarrierList
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#scs-SpecificCarrierList
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dl_offstToCarrier = 0;
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dl_offstToCarrier = 0;
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# subcarrierSpacing
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# subcarrierSpacing
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@@ -153,7 +153,7 @@ gNBs =
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# ssb_PositionsInBurs_BitmapPR
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# ssb_PositionsInBurs_BitmapPR
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# 1=short, 2=medium, 3=long
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# 1=short, 2=medium, 3=long
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ssb_PositionsInBurst_PR = 2;
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ssb_PositionsInBurst_PR = 2;
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ssb_PositionsInBurst_Bitmap = 255;
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ssb_PositionsInBurst_Bitmap = 1;
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# ssb_periodicityServingCell
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# ssb_periodicityServingCell
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# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
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# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
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@@ -243,6 +243,7 @@ RUs = (
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max_rxgain = 114;
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max_rxgain = 114;
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eNB_instances = [0];
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eNB_instances = [0];
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sdr_addrs = "type=x300";
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sdr_addrs = "type=x300";
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clock_src = "external";
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}
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}
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);
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);
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