diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
index 8090f00ae3..dd36eb9baf 100644
--- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
+++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
@@ -513,45 +513,79 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id,
       module_id, UE_id, frame, slot, num_slots_per_tdd, &sched_ctrl->pucch_sched_idx);
   AssertFatal(sched_ctrl->pucch_sched_idx >= 0, "no uplink slot for PUCCH found!\n");
 
-  // Time-domain allocation
-  sched_ctrl->time_domain_allocation = 2;
-
-  // Freq-demain allocation
   uint8_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map;
+  const int current_harq_pid = sched_ctrl->current_harq_pid;
+  NR_UE_harq_t *harq = &sched_ctrl->harq_processes[current_harq_pid];
+  NR_UE_ret_info_t *retInfo = &sched_ctrl->retInfo[current_harq_pid];
   const uint16_t bwpSize = NRRIV2BW(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, 275);
   int rbStart = NRRIV2PRBOFFSET(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, 275);
-  while (rbStart < bwpSize && vrb_map[rbStart]) rbStart++;
-  int rbSize = 1;
-  while (rbStart + rbSize < bwpSize && !vrb_map[rbStart + rbSize]) rbSize++;
-  DevAssert(rbSize >= 3); /* just ensure we have at least 3 RBs */
-  sched_ctrl->rbSize = rbSize;
-  sched_ctrl->rbStart = rbStart;
+
+  if (harq->round != 0) { /* retransmission */
+    sched_ctrl->time_domain_allocation = retInfo->time_domain_allocation;
+
+    /* ensure that there is a free place for RB allocation */
+    int rbSize = 0;
+    while (rbSize < retInfo->rbSize) {
+      rbStart += rbSize; /* last iteration rbSize was not enough, skip it */
+      rbSize = 0;
+      while (rbStart < bwpSize && vrb_map[rbStart]) rbStart++;
+      if (rbStart >= bwpSize) {
+        LOG_E(MAC,
+              "cannot allocate retransmission for UE %d/RNTI %04x: no resources\n",
+              UE_id,
+              rnti);
+        return;
+      }
+      while (rbStart + rbSize < bwpSize
+             && !vrb_map[rbStart + rbSize]
+             && rbSize < retInfo->rbSize)
+        rbSize++;
+    }
+    sched_ctrl->rbSize = retInfo->rbSize;
+    sched_ctrl->rbStart = rbStart;
+
+    /* MCS etc: just reuse from previous scheduling opportunity */
+    sched_ctrl->mcsTableIdx = retInfo->mcsTableIdx;
+    sched_ctrl->mcs = retInfo->mcs;
+    sched_ctrl->numDmrsCdmGrpsNoData = retInfo->numDmrsCdmGrpsNoData;
+  } else {
+    // Time-domain allocation
+    sched_ctrl->time_domain_allocation = 2;
+
+    // Freq-demain allocation
+    while (rbStart < bwpSize && vrb_map[rbStart]) rbStart++;
+    int rbSize = 1;
+    while (rbStart + rbSize < bwpSize && !vrb_map[rbStart + rbSize]) rbSize++;
+    DevAssert(rbSize >= 3); /* just ensure we have at least 3 RBs */
+    sched_ctrl->rbSize = rbSize;
+    sched_ctrl->rbStart = rbStart;
+
+    // modulation scheme
+    sched_ctrl->mcsTableIdx = 0;
+    sched_ctrl->mcs = 9;
+    sched_ctrl->numDmrsCdmGrpsNoData = 1;
+
+    uint8_t N_PRB_DMRS =
+        getN_PRB_DMRS(sched_ctrl->active_bwp, sched_ctrl->numDmrsCdmGrpsNoData);
+    int nrOfSymbols = getNrOfSymbols(sched_ctrl->active_bwp,
+                                     sched_ctrl->time_domain_allocation);
+    const uint32_t TBS =
+        nr_compute_tbs(nr_get_Qm_dl(sched_ctrl->mcs, sched_ctrl->mcsTableIdx),
+                       nr_get_code_rate_dl(sched_ctrl->mcs, sched_ctrl->mcsTableIdx),
+                       sched_ctrl->rbSize,
+                       nrOfSymbols,
+                       N_PRB_DMRS, // FIXME // This should be multiplied by the
+                                   // number of dmrs symbols
+                       0 /* N_PRB_oh, 0 for initialBWP */,
+                       0 /* tb_scaling */,
+                       1 /* nrOfLayers */)
+        >> 3;
+    AssertFatal(TBS != 0, "TBS is zero but requested %d RBs!\n", sched_ctrl->rbSize);
+  }
 
   /* mark the corresponding RBs as used */
   for (int rb = 0; rb < sched_ctrl->rbSize; rb++)
     vrb_map[rb + sched_ctrl->rbStart] = 1;
-
-  // modulation scheme
-  sched_ctrl->mcsTableIdx = 0;
-  sched_ctrl->mcs = 9;
-  sched_ctrl->numDmrsCdmGrpsNoData = 1;
-
-  uint8_t N_PRB_DMRS =
-      getN_PRB_DMRS(sched_ctrl->active_bwp, sched_ctrl->numDmrsCdmGrpsNoData);
-  int nrOfSymbols = getNrOfSymbols(sched_ctrl->active_bwp,
-                                   sched_ctrl->time_domain_allocation);
-  const uint32_t TBS =
-      nr_compute_tbs(nr_get_Qm_dl(sched_ctrl->mcs, sched_ctrl->mcsTableIdx),
-                     nr_get_code_rate_dl(sched_ctrl->mcs, sched_ctrl->mcsTableIdx),
-                     sched_ctrl->rbSize,
-                     nrOfSymbols,
-                     N_PRB_DMRS, // FIXME // This should be multiplied by the
-                                 // number of dmrs symbols
-                     0 /* N_PRB_oh, 0 for initialBWP */,
-                     0 /* tb_scaling */,
-                     1 /* nrOfLayers */)
-      >> 3;
-  AssertFatal(TBS != 0, "TBS is zero but requested %d RBs!\n", sched_ctrl->rbSize);
 }
 
 void nr_schedule_ue_spec(module_id_t module_id,