Merge remote-tracking branch 'origin/NR_SA_F1AP_5GRECORDS' into develop-NR_SA_F1AP_5GRECORDS-lts2
# Conflicts: # cmake_targets/CMakeLists.txt # cmake_targets/build_oai # cmake_targets/tools/build_helper # executables/nr-gnb.c # openair1/PHY/INIT/nr_init_ru.c # openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c # openair1/PHY/NR_TRANSPORT/nr_ulsch.c # openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c # openair1/PHY/NR_UE_TRANSPORT/nr_prach.c # openair1/SCHED_NR/phy_procedures_nr_gNB.c # openair1/SCHED_NR_UE/pucch_uci_ue_nr.c # openair2/F1AP/f1ap_du_rrc_message_transfer.c # openair2/F1AP/f1ap_du_rrc_message_transfer.h # openair2/F1AP/f1ap_du_task.c # openair2/GNB_APP/gnb_app.c # openair2/LAYER2/NR_MAC_UE/nr_ue_scheduler.c # openair2/LAYER2/NR_MAC_gNB/config.c # openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c # openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c # openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c # openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_uci.c # openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c # openair2/LAYER2/nr_pdcp/nr_pdcp_entity.c # openair2/LAYER2/nr_pdcp/nr_pdcp_oai_api.c # openair2/RRC/LTE/rrc_eNB_GTPV1U.c # openair2/RRC/NR/L2_nr_interface.c # openair2/RRC/NR/MESSAGES/asn1_msg.c # openair2/RRC/NR/rrc_gNB.c # openair2/RRC/NR/rrc_gNB_NGAP.c # openair2/RRC/NR_UE/rrc_UE.c # openair3/NAS/NR_UE/nr_nas_msg_sim.c # openair3/ocp-gtpu/gtp_itf.cpp # targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp
This commit is contained in:
@@ -385,14 +385,14 @@ static int trx_usrp_write(openair0_device *device,
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#if defined(__x86_64) || defined(__i386__)
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#ifdef __AVX2__
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nsamps2 = (nsamps+7)>>3;
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__m256i buff_tx[8][nsamps2];
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__m256i buff_tx[cc<2?2:cc][nsamps2];
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#else
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nsamps2 = (nsamps+3)>>2;
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__m128i buff_tx[8][nsamps2];
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__m128i buff_tx[cc<2?2:cc][nsamps2];
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#endif
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#elif defined(__arm__)
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nsamps2 = (nsamps+3)>>2;
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int16x8_t buff_tx[8][nsamps2];
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int16x8_t buff_tx[cc<2?2:cc][nsamps2];
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#else
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#error Unsupported CPU architecture, USRP device cannot be built
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#endif
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@@ -523,14 +523,14 @@ void *trx_usrp_write_thread(void * arg){
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#if defined(__x86_64) || defined(__i386__)
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#ifdef __AVX2__
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nsamps2 = (nsamps+7)>>3;
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__m256i buff_tx[8][nsamps2];
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__m256i buff_tx[cc<2?2:cc][nsamps2];
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#else
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nsamps2 = (nsamps+3)>>2;
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__m128i buff_tx[8][nsamps2];
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__m128i buff_tx[cc<2?2:cc][nsamps2];
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#endif
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#elif defined(__arm__)
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nsamps2 = (nsamps+3)>>2;
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int16x8_t buff_tx[8][nsamps2];
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int16x8_t buff_tx[cc<2?2:cc][nsamps2];
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#else
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#error Unsupported CPU architecture, USRP device cannot be built
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#endif
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@@ -582,7 +582,6 @@ void *trx_usrp_write_thread(void * arg){
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VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_USRP_SEND_RETURN, ret );
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VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_WRITE_THREAD, 0 );
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if(0) break;
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}
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return NULL;
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@@ -625,14 +624,14 @@ static int trx_usrp_read(openair0_device *device, openair0_timestamp *ptimestamp
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#if defined(__x86_64) || defined(__i386__)
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#ifdef __AVX2__
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nsamps2 = (nsamps+7)>>3;
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__m256i buff_tmp[4][nsamps2];
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__m256i buff_tmp[cc<2 ? 2 : cc][nsamps2];
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#else
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nsamps2 = (nsamps+3)>>2;
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__m128i buff_tmp[4][nsamps2];
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__m128i buff_tmp[cc<2 ? 2 : cc][nsamps2];
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#endif
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#elif defined(__arm__)
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nsamps2 = (nsamps+3)>>2;
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int16x8_t buff_tmp[4][nsamps2];
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int16x8_t buff_tmp[cc<2 ? 2 : cc][nsamps2];
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#endif
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int rxshift;
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@@ -645,44 +644,33 @@ static int trx_usrp_read(openair0_device *device, openair0_timestamp *ptimestamp
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rxshift=2;
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break;
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default:
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AssertFatal(1==0,"Shouldn't be here\n");
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}
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if (cc>1) {
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AssertFatal(1==0,"Shouldn't be here\n");
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}
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samples_received=0;
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while (samples_received != nsamps) {
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if (cc>1) {
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// receive multiple channels (e.g. RF A and RF B)
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std::vector<void *> buff_ptrs;
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std::vector<void *> buff_ptrs;
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samples_received=0;
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while (samples_received != nsamps) {
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for (int i=0; i<cc; i++) buff_ptrs.push_back(buff_tmp[i]+samples_received);
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samples_received += s->rx_stream->recv(buff_ptrs,nsamps-samples_received, s->rx_md);
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if ((s->wait_for_first_pps == 0) && (s->rx_md.error_code!=uhd::rx_metadata_t::ERROR_CODE_NONE))
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break;
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if ((s->wait_for_first_pps == 1) && (samples_received != nsamps)) {
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printf("sleep...\n"); //usleep(100);
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}
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}
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if (samples_received == nsamps) s->wait_for_first_pps=0;
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} else {
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samples_received += s->rx_stream->recv(buff_ptrs, nsamps, s->rx_md);
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} else {
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// receive a single channel (e.g. from connector RF A)
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samples_received=0;
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while (samples_received != nsamps) {
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samples_received += s->rx_stream->recv((void*)((int32_t*)buff_tmp[0]+samples_received),
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nsamps-samples_received, s->rx_md);
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if ((s->wait_for_first_pps == 0) && (s->rx_md.error_code!=uhd::rx_metadata_t::ERROR_CODE_NONE))
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break;
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if ((s->wait_for_first_pps == 1) && (samples_received != nsamps)) {
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printf("sleep...\n"); //usleep(100);
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}
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}
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if (samples_received == nsamps) s->wait_for_first_pps=0;
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if ((s->wait_for_first_pps == 0) && (s->rx_md.error_code!=uhd::rx_metadata_t::ERROR_CODE_NONE))
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break;
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if ((s->wait_for_first_pps == 1) && (samples_received != nsamps)) {
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printf("sleep...\n"); //usleep(100);
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}
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}
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if (samples_received == nsamps) s->wait_for_first_pps=0;
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// bring RX data into 12 LSBs for softmodem RX
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for (int i=0; i<cc; i++) {
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@@ -1271,7 +1259,7 @@ extern "C" {
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gain - gain_range.stop());
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gain=gain_range.stop();
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}
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s->usrp->set_rx_gain(gain,i);
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LOG_I(HW,"RX Gain %d %f (%f) => %f (max %f)\n",i,
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openair0_cfg[0].rx_gain[i],openair0_cfg[0].rx_gain_offset[i],
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@@ -1313,12 +1301,12 @@ extern "C" {
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LOG_I(HW,"rx_max_num_samps %zu\n",
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s->usrp->get_rx_stream(stream_args_rx)->get_max_num_samps());
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for (int i = 0; i<openair0_cfg[0].rx_num_channels; i++) {
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LOG_I(HW,"setting rx channel %d\n",i);
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stream_args_rx.channels.push_back(i);
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}
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s->rx_stream = s->usrp->get_rx_stream(stream_args_rx);
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uhd::stream_args_t stream_args_tx("sc16", "sc16");
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