Add documentation on UL-heavy TDD patterns
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@@ -38,7 +38,7 @@ The actual scheduler implementation can be found in functions `pf_dl()` and
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[`gNB_scheduler_ulsch.c`](../../openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c)
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[`gNB_scheduler_ulsch.c`](../../openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c)
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(for UL), respectively.
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(for UL), respectively.
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## PDDCH aggregation level
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## PDCCH aggregation level
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PDCCH aggregation level is selected using closed loop controller, where DL HARQ
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PDCCH aggregation level is selected using closed loop controller, where DL HARQ
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feedback is the controller feedback signal. It is used to increment `pdcch_cl_adjust`
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feedback is the controller feedback signal. It is used to increment `pdcch_cl_adjust`
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@@ -60,7 +60,7 @@ in aggregation level 2 which translates to `uess_agg_levels` set to `[0, 2, 0,
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Say we have 90% PDCCH success rate at aggregation level 1, `pdcch_cl_adjust` will stay at 0
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Say we have 90% PDCCH success rate at aggregation level 1, `pdcch_cl_adjust` will stay at 0
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for most of the time. 2 consecutive PDCCH failures will not result in increasing the aggregation
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for most of the time. 2 consecutive PDCCH failures will not result in increasing the aggregation
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level (because (0.05 + 0.05) * 4 = 0.4 which is closer to 0 than to 1). If PDCCH fails 3 times
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level (because (0.05 + 0.05) * 4 = 0.4 which is closer to 0 than to 1). If PDCCH fails 3 times
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in a row the aggregation level will change to 2 and hopefully back to 1 once more PDDCH successes
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in a row the aggregation level will change to 2 and hopefully back to 1 once more PDCCH successes
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happen.
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happen.
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### Example 2
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### Example 2
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@@ -402,3 +402,13 @@ pattern2: {
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nrofUplinkSymbols2 = 0;
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nrofUplinkSymbols2 = 0;
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};
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};
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```
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```
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#### UL-heavy TDD patterns
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"UL-heavy TDD patterns", i.e., TDD patterns that have many UL slots are
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supported. Examples for such patterns would be DSUUU or DDDSUUUUUU.
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Note that you should increase the aggregation level candidates as described in
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[the corresponding section above](#pdcch-aggregation-level). This is because the
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scheduler has to schedule multiple DCIs in a single DL slots for multiple UL
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slots. As a suggestion, you could try `uess_agg_levels = [4, 2, 2, 0, 0]`.
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