From 449da9ac1733626174347ea82dee4bb6767f779a Mon Sep 17 00:00:00 2001 From: Florian Kaltenberger Date: Wed, 23 Jan 2019 12:15:54 +0100 Subject: [PATCH 1/4] adding detection of multiple PSS. --- openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c | 8 +-- openair1/PHY/NR_UE_TRANSPORT/pss_nr.c | 89 ++++++++++++++++++-------- openair2/RRC/NR_UE/rrc_UE.c | 37 ++++++----- 3 files changed, 84 insertions(+), 50 deletions(-) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c b/openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c index 3e5df2e242..7b8da35f96 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c @@ -712,10 +712,10 @@ int nr_rx_pbch( PHY_VARS_NR_UE *ue, #ifdef DEBUG_PBCH printf("xtra_byte %x payload %x\n", xtra_byte, payload); - for (i=0; i<(NR_POLAR_PBCH_PAYLOAD_BITS>>3); i++){ - // printf("unscrambling pbch_a[%d] = %x \n", i,pbch_a[i]); - printf("[PBCH] decoder payload[%d] = %x\n",i,decoded_output[i]); - } + for (int i=0; i<(NR_POLAR_PBCH_PAYLOAD_BITS>>3); i++){ + // printf("unscrambling pbch_a[%d] = %x \n", i,pbch_a[i]); + printf("[PBCH] decoder payload[%d] = %x\n",i,decoded_output[i]); + } #endif ue->dl_indication.rx_ind = &ue->rx_ind; // hang on rx_ind instance diff --git a/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c b/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c index 01481d3612..cef55df281 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c +++ b/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c @@ -803,25 +803,47 @@ static inline int64_t abs64(int64_t x) #define DOT_PRODUCT_SCALING_SHIFT (17) +int max3(int64_t a, int64_t b, int64_t c) { + if (a>b) { + if (a>c) { + return(0); + } + else { + return(2); + } + } + else { + if (b>c) { + return(1); + } + else { + return(2); + } + } +} + + int pss_search_time_nr(int **rxdata, ///rx data in time domain NR_DL_FRAME_PARMS *frame_parms, int *eNB_id) { - unsigned int n, ar, peak_position, pss_source; - int64_t peak_value; + uint8_t L_max = 4; + unsigned int m, n, ar, n_peaks=0; + unsigned int peak_position[3*L_max], pss_source[3*L_max]; + int64_t peak_value, threshold; int64_t result; int64_t avg[NUMBER_PSS_SEQUENCE]; - + uint8_t found_peak=0; unsigned int length = (NR_NUMBER_OF_SUBFRAMES_PER_FRAME*frame_parms->samples_per_subframe); /* 1 frame for now, it should be 2 TODO_NR */ AssertFatal(length>0,"illegal length %d\n",length); for (int i = 0; i < NUMBER_PSS_SEQUENCE; i++) AssertFatal(pss_corr_ue[i] != NULL,"pss_corr_ue[%d] not yet allocated! Exiting.\n", i); - - peak_value = 0; - peak_position = 0; - pss_source = 0; + for (int i=0;i<4;i++) { + peak_position[i] = length; //max possible value + pss_source[i] = 0; + } int maxval=0; for (int i=0;i<2*(frame_parms->ofdm_symbol_size);i++) { @@ -844,9 +866,9 @@ int pss_search_time_nr(int **rxdata, ///rx data in time domain memset(pss_corr_ue[pss_index],0,length*sizeof(int64_t)); } - for (n=0; n < length; n+=4) { // + for (int pss_index = 0; pss_index < NUMBER_PSS_SEQUENCE; pss_index++) { - for (int pss_index = 0; pss_index < NUMBER_PSS_SEQUENCE; pss_index++) { + for (n=0; n < length; n+=4) { // if ( n < (length - frame_parms->ofdm_symbol_size)) { @@ -870,27 +892,40 @@ int pss_search_time_nr(int **rxdata, ///rx data in time domain /* calculate the absolute value of sync_corr[n] */ avg[pss_index]+=pss_corr_ue[pss_index][n]; - if (pss_corr_ue[pss_index][n] > peak_value) { - peak_value = pss_corr_ue[pss_index][n]; - peak_position = n; - pss_source = pss_index; - -#ifdef DEBUG_PSS_NR - printf("pss_index %d: n %6d peak_value %15llu\n", pss_index, n, (unsigned long long)pss_corr_ue[pss_index][n]); -#endif - } + } + + avg[pss_index]/=(length/4); + } + + threshold = 10*avg[max3(avg[0],avg[1],avg[2])]; + peak_value = threshold; + + for (n=0; n < length; n+=4) { + + m = max3(pss_corr_ue[0][n],pss_corr_ue[1][n],pss_corr_ue[2][n]); + + if (pss_corr_ue[m][n] > peak_value) { + peak_value = pss_corr_ue[m][n]; + peak_position[n_peaks] = n; + pss_source[n_peaks] = m; + found_peak = 1; + } + + if ((peak_position[n_peaks]+4*(frame_parms->ofdm_symbol_size+frame_parms->nb_prefix_samples)message.choice.mib->systemFrameNumber.buf != 0){ - if ((dec_rval.code != RC_OK) || (dec_rval.consumed == 0)) { - printf("NR_CellGroupConfig decode error\n"); - for (i=0; imessage.choice.mib; - //memcpy( (void *)mib, - // (void *)&bcch_message->message.choice.mib, - // sizeof(NR_MIB_t) ); - - nr_rrc_mac_config_req_ue( 0, 0, 0, mib, NULL, NULL, NULL); + if ((dec_rval.code != RC_OK) || (dec_rval.consumed == 0)) { + printf("NR_BCCH_BCH decode error\n"); + for (i=0; imessage.choice.mib; + //memcpy( (void *)mib, + // (void *)&bcch_message->message.choice.mib, + // sizeof(NR_MIB_t) ); + + nr_rrc_mac_config_req_ue( 0, 0, 0, mib, NULL, NULL, NULL); } return 0; From 61e36839e5e91aa9c0b617d2ee69fd1ea1e0855b Mon Sep 17 00:00:00 2001 From: Guy De Souza Date: Mon, 11 Feb 2019 10:34:25 +0100 Subject: [PATCH 2/4] DMRS shift disabling on gNB --- openair1/PHY/MODULATION/slot_fep_nr.c | 4 ++-- openair1/PHY/NR_TRANSPORT/nr_dci.c | 6 +++--- openair1/PHY/NR_TRANSPORT/nr_tbs_tools.c | 2 +- openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c | 4 ++-- openair1/SIMULATION/NR_PHY/dlsim.c | 2 +- openair2/LAYER2/NR_MAC_gNB/main.c | 2 +- 6 files changed, 10 insertions(+), 10 deletions(-) diff --git a/openair1/PHY/MODULATION/slot_fep_nr.c b/openair1/PHY/MODULATION/slot_fep_nr.c index 0815055889..078deca514 100644 --- a/openair1/PHY/MODULATION/slot_fep_nr.c +++ b/openair1/PHY/MODULATION/slot_fep_nr.c @@ -55,8 +55,8 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue, unsigned int frame_length_samples = frame_parms->samples_per_subframe * 10; unsigned int rx_offset; NR_UE_PDCCH *pdcch_vars = ue->pdcch_vars[ue->current_thread_id[Ns>>1]][0]; - uint16_t coreset_start_subcarrier = frame_parms->first_carrier_offset;//+((int)floor(frame_parms->ssb_start_subcarrier/NR_NB_SC_PER_RB)+pdcch_vars->coreset[0].rb_offset)*NR_NB_SC_PER_RB; - uint16_t nb_rb_coreset = 24; + uint16_t coreset_start_subcarrier = frame_parms->first_carrier_offset + pdcch_vars->coreset[0].rb_offset*NR_NB_SC_PER_RB;//+((int)floor(frame_parms->ssb_start_subcarrier/NR_NB_SC_PER_RB)+pdcch_vars->coreset[0].rb_offset)*NR_NB_SC_PER_RB; + uint16_t nb_rb_coreset = pdcch_vars->coreset[0].rb_offset; uint16_t bwp_start_subcarrier = frame_parms->first_carrier_offset;//+516; uint16_t nb_rb_pdsch = 50; uint8_t p=0; diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.c b/openair1/PHY/NR_TRANSPORT/nr_dci.c index 5d376c21a6..b4004083fe 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.c @@ -32,7 +32,7 @@ #include "nr_dci.h" -//#define DEBUG_PDCCH_DMRS +#define DEBUG_PDCCH_DMRS #define DEBUG_DCI #define DEBUG_CHANNEL_CODING @@ -207,12 +207,12 @@ uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars, /// DMRS QPSK modulation /*There is a need to shift from which index the pregenerated DMRS sequence is used * see 38211 r15.2.0 section 7.4.1.3.2: assumption is the reference point for k refers to the DMRS sequence*/ - if (pdcch_params.config_type == NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG) { + /*if (pdcch_params.config_type == NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG) { for (int symb=cset_start_symb; symb>5; dmrs_offset = (pdcch_params.rb_offset*3)&0x1f; LOG_I(PHY, "PDCCH DMRS offset %d\n", dmrs_offset); - } + }*/ // DMRS shift currently disable for compatibility with the OAI UE for (int symb=cset_start_symb; symbcoreset_id = 1; - coreset->frequency_domain_resources = 0x1E0000000000;//0x1FFFE0000000; // 96 RB starting from CRB0 + coreset->frequency_domain_resources = 0x1E000000000;//0x1FFFE0000000; // 96 RB starting from CRB0 coreset->duration = 2; coreset->cce_reg_mapping_type = NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED; coreset->reg_bundle_size = 6; From 932ad9ed64e09fc5204bd9a4c17a6f9005a50fb3 Mon Sep 17 00:00:00 2001 From: Guy De Souza Date: Mon, 11 Feb 2019 16:08:15 +0100 Subject: [PATCH 3/4] Revert "DMRS shift disabling on gNB" This reverts commit 61e36839e5e91aa9c0b617d2ee69fd1ea1e0855b. --- openair1/PHY/MODULATION/slot_fep_nr.c | 4 ++-- openair1/PHY/NR_TRANSPORT/nr_dci.c | 6 +++--- openair1/PHY/NR_TRANSPORT/nr_tbs_tools.c | 2 +- openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c | 4 ++-- openair1/SIMULATION/NR_PHY/dlsim.c | 2 +- openair2/LAYER2/NR_MAC_gNB/main.c | 2 +- 6 files changed, 10 insertions(+), 10 deletions(-) diff --git a/openair1/PHY/MODULATION/slot_fep_nr.c b/openair1/PHY/MODULATION/slot_fep_nr.c index 078deca514..0815055889 100644 --- a/openair1/PHY/MODULATION/slot_fep_nr.c +++ b/openair1/PHY/MODULATION/slot_fep_nr.c @@ -55,8 +55,8 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue, unsigned int frame_length_samples = frame_parms->samples_per_subframe * 10; unsigned int rx_offset; NR_UE_PDCCH *pdcch_vars = ue->pdcch_vars[ue->current_thread_id[Ns>>1]][0]; - uint16_t coreset_start_subcarrier = frame_parms->first_carrier_offset + pdcch_vars->coreset[0].rb_offset*NR_NB_SC_PER_RB;//+((int)floor(frame_parms->ssb_start_subcarrier/NR_NB_SC_PER_RB)+pdcch_vars->coreset[0].rb_offset)*NR_NB_SC_PER_RB; - uint16_t nb_rb_coreset = pdcch_vars->coreset[0].rb_offset; + uint16_t coreset_start_subcarrier = frame_parms->first_carrier_offset;//+((int)floor(frame_parms->ssb_start_subcarrier/NR_NB_SC_PER_RB)+pdcch_vars->coreset[0].rb_offset)*NR_NB_SC_PER_RB; + uint16_t nb_rb_coreset = 24; uint16_t bwp_start_subcarrier = frame_parms->first_carrier_offset;//+516; uint16_t nb_rb_pdsch = 50; uint8_t p=0; diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.c b/openair1/PHY/NR_TRANSPORT/nr_dci.c index b4004083fe..5d376c21a6 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.c @@ -32,7 +32,7 @@ #include "nr_dci.h" -#define DEBUG_PDCCH_DMRS +//#define DEBUG_PDCCH_DMRS #define DEBUG_DCI #define DEBUG_CHANNEL_CODING @@ -207,12 +207,12 @@ uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars, /// DMRS QPSK modulation /*There is a need to shift from which index the pregenerated DMRS sequence is used * see 38211 r15.2.0 section 7.4.1.3.2: assumption is the reference point for k refers to the DMRS sequence*/ - /*if (pdcch_params.config_type == NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG) { + if (pdcch_params.config_type == NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG) { for (int symb=cset_start_symb; symb>5; dmrs_offset = (pdcch_params.rb_offset*3)&0x1f; LOG_I(PHY, "PDCCH DMRS offset %d\n", dmrs_offset); - }*/ // DMRS shift currently disable for compatibility with the OAI UE + } for (int symb=cset_start_symb; symbcoreset_id = 1; - coreset->frequency_domain_resources = 0x1E000000000;//0x1FFFE0000000; // 96 RB starting from CRB0 + coreset->frequency_domain_resources = 0x1E0000000000;//0x1FFFE0000000; // 96 RB starting from CRB0 coreset->duration = 2; coreset->cce_reg_mapping_type = NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED; coreset->reg_bundle_size = 6; From 7ee8af50e927287e4d385a0db36c98444f72d300 Mon Sep 17 00:00:00 2001 From: Guy De Souza Date: Wed, 13 Feb 2019 10:24:15 +0100 Subject: [PATCH 4/4] Arithmetic exception fix --- openair1/PHY/NR_TRANSPORT/nr_dci_tools.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c index f8d4c20813..59adce5fb5 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c @@ -67,7 +67,7 @@ void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m C = N_reg/(bsize*R); } - tmp = L * (( Y + (m*N_cce)/(L*M_s_max) + n_CI ) % (N_cce/L)); + tmp = L * (( Y + (m*N_cce)/(L*M_s_max) + n_CI ) % CEILIDIV(N_cce,L)); LOG_I(PHY, "CCE list generation for candidate %d: bundle size %d ilv size %d tmp %d\n", m, bsize, R, tmp); for (uint8_t cce_idx=0; cce_idx