From 271303c57ab328eaf76e4a394829ba63028e76ca Mon Sep 17 00:00:00 2001 From: Guy De Souza Date: Fri, 3 Aug 2018 09:59:12 +0200 Subject: [PATCH] fill_dci for 1_0 RA_RNTI --- .../nfapi/public_inc/nfapi_nr_interface.h | 83 ++++++------------- openair1/PHY/INIT/nr_init.c | 2 +- openair1/PHY/NR_REFSIG/nr_gold.c | 2 +- openair1/PHY/NR_TRANSPORT/nr_dci.c | 14 ++-- openair1/PHY/NR_TRANSPORT/nr_dci_tools.c | 60 +++++++++++--- openair1/PHY/defs_gNB.h | 10 +-- openair1/PHY/defs_nr_common.h | 14 ++-- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 9 +- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 22 ++--- 9 files changed, 108 insertions(+), 108 deletions(-) diff --git a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h index 576f024be5..17bd564f2f 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h @@ -299,72 +299,28 @@ typedef enum { } nfapi_nr_coreset_precoder_granularity_type_e; // P7 Sub Structures -//formats 0_0 and 0_1 + typedef struct { nfapi_tl_t tl; -uint8_t cce_idx; -uint8_t aggregation_level; -uint16_t rnti; -uint8_t rnti_type; - -uint8_t dci_format; //1 bit -uint16_t frequency_domain_resource_assignment; //up to 9 bits -uint8_t time_domain_resource_assignment; //0, 1, 2, 3 or 4 bits +uint8_t format_indicator; //1 bit +uint16_t frequency_domain_assignment; //up to 9 bits +uint8_t time_domain_assignment; // 4 bits uint8_t frequency_hopping_flag; //1 bit -uint8_t mcs; //5 bits -uint8_t new_data_indicator; //1 bit -uint8_t redundancy_version; //2 bits -uint8_t harq_process; //4 bits -uint8_t tpc; //2 bits -uint16_t padding; -uint8_t ul_sul_indicator; //0 or 1 bit - -uint8_t carrier_indicator; //0 or 3 bits -uint8_t bwp_indicator; //0, 1 or 2 bits -uint8_t downlink_assignment_index1; //1 or 2 bits -uint8_t downlink_assignment_index2; //0 or 2 bits -uint8_t srs_resource_indicator; -uint8_t precoding_information; -uint8_t antenna_ports; -uint8_t srs_request; -uint8_t csi_request; -uint8_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits -uint8_t ptrs_dmrs_association; -uint8_t beta_offset_indicator; //0 or 2 bits -uint8_t dmrs_sequence_initialization; //0 or 1 bit -uint8_t ul_sch_indicator; //1 bit - -} nfapi_nr_ul_config_dci_ul_pdu_rel15_t; -//#define NFAPI_NR_UL_CONFIG_REQUEST_DCI_UL_PDU_REL15_TAG 0x???? - -//formats 1_0, 1_1, 2_0, 2_1, 2_2 and 2_3 -typedef struct { - -nfapi_tl_t tl; - -uint8_t cce_idx; -uint8_t aggregation_level; -uint16_t rnti; -uint8_t rnti_type; - -uint8_t dci_format; //1 bit -uint16_t frequency_domain_resource_assignment; //up to 9 bits uint8_t ra_preamble_index; //6 bits -uint8_t ul_sul_indicator; //1 bit uint8_t ss_pbch_index; //6 bits uint8_t prach_mask_index; //4 bits -uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits -uint8_t time_domain_resource_assignment; //0, 1, 2, 3 or 4 bits uint8_t vrb_to_prb_mapping; //0 or 1 bit uint8_t mcs; //5 bits -uint8_t new_data_indicator; //1 bit -uint8_t redundancy_version; //2 bits -uint8_t harq_process; //4 bits -uint8_t downlink_assignment_index; //0, 2 or 4 bits +uint8_t ndi; //1 bit +uint8_t rv; //2 bits +uint8_t harq_pid; //4 bits +uint8_t dai; //0, 2 or 4 bits +uint8_t dai1; //1 or 2 bits +uint8_t dai2; //0 or 2 bits uint8_t tpc; //2 bits uint8_t pucch_resource_indicator; //3 bits uint8_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits @@ -378,13 +334,18 @@ uint8_t bwp_indicator; //0, 1 or 2 bits uint8_t prb_bundling_size_indicator; //0 or 1 bits uint8_t rate_matching_indicator; //0, 1 or 2 bits uint8_t zp_csi_rs_trigger; //0, 1 or 2 bits -uint8_t antenna_ports; //4, 5 or 6 bits uint8_t transmission_configuration_indication; //0 or 3 bits uint8_t srs_request; //2 bits uint8_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits uint8_t cbgfi; //CBG Flushing Out Information: 0 or 1 bit uint8_t dmrs_sequence_initialization; //0 or 1 bit +uint8_t srs_resource_indicator; +uint8_t precoding_information; +uint8_t csi_request; +uint8_t ptrs_dmrs_association; +uint8_t beta_offset_indicator; //0 or 2 bits + uint8_t slot_format_indicator_count; uint8_t *slot_format_indicators; @@ -394,11 +355,18 @@ uint16_t *pre_emption_indications; //14 bit uint8_t block_number_count; uint8_t *block_numbers; +uint8_t ul_sul_indicator; //0 or 1 bit +uint8_t antenna_ports; + +uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits +uint16_t padding; + } nfapi_nr_dl_config_dci_dl_pdu_rel15_t; //#define NFAPI_NR_DL_CONFIG_REQUEST_DCI_DL_PDU_REL15_TAG 0x???? typedef struct{ + nfapi_tl_t tl; uint8_t coreset_id; uint64_t frequency_domain_resources; uint8_t duration; @@ -413,6 +381,7 @@ typedef struct{ } nfapi_nr_coreset_t; typedef struct{ + nfapi_tl_t tl; uint8_t search_space_id; uint8_t coreset_id; uint8_t search_space_type; @@ -435,6 +404,8 @@ typedef struct { uint8_t rnti; uint8_t rnti_type; uint8_t dci_format; + uint8_t config_type; + uint8_t search_space_type; uint8_t aggregation_level; uint8_t n_rb; uint8_t n_symb; @@ -442,13 +413,11 @@ typedef struct { uint8_t cr_mapping_type; uint8_t mux_pattern; uint8_t precoder_granularity; - uint8_t config_type; uint8_t first_slot; uint8_t first_symbol; uint8_t nb_ss_sets_per_slot; uint8_t nb_slots; uint8_t sfn_mod2; - uint8_t search_space_type; uint16_t scrambling_id; nfapi_bf_vector_t bf_vector; } nfapi_nr_dl_config_pdcch_parameters_rel15_t; diff --git a/openair1/PHY/INIT/nr_init.c b/openair1/PHY/INIT/nr_init.c index d76b92eed2..ef7a9235d0 100644 --- a/openair1/PHY/INIT/nr_init.c +++ b/openair1/PHY/INIT/nr_init.c @@ -128,7 +128,7 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, pdcch_dmrs[slot] = (uint32_t **)malloc16(fp->symbols_per_slot*sizeof(uint32_t*)); AssertFatal(pdcch_dmrs[slot]!=NULL, "NR init: pdcch_dmrs for slot %d - malloc failed\n", slot); for (int symb=0; symbsymbols_per_slot; symb++){ - pdcch_dmrs[slot][symb] = (uint32_t *)malloc16(NR_MAX_PDCCH_DMRS_LENGTH_DWORD*sizeof(uint32_t)); + pdcch_dmrs[slot][symb] = (uint32_t *)malloc16(NR_MAX_PDCCH_DMRS_INIT_LENGTH_DWORD*sizeof(uint32_t)); AssertFatal(pdcch_dmrs[slot][symb]!=NULL, "NR init: pdcch_dmrs for slot %d symbol %d - malloc failed\n", slot, symb); } } diff --git a/openair1/PHY/NR_REFSIG/nr_gold.c b/openair1/PHY/NR_REFSIG/nr_gold.c index 19137dd1a7..b8197744ec 100644 --- a/openair1/PHY/NR_REFSIG/nr_gold.c +++ b/openair1/PHY/NR_REFSIG/nr_gold.c @@ -67,7 +67,7 @@ void nr_init_pdcch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid) reset = 1; x2 = ((1<<17) * (14*slot+symb+1) * ((Nid<<1)+1) + (Nid<<1))&(((uint32_t)1<<31)-1); - for (uint32_t n=0; n>1 ) ); // Freq domain assignment -- hopping scenario to be updated + size += nr_get_dci_size(NFAPI_NR_DL_DCI_FORMAT_1_0, rnti_type, bwp, config) - size; // Padding to match 1_0 size // UL/SUL indicator assumed to be 0 - // Padding break; case NFAPI_NR_UL_DCI_FORMAT_0_1: @@ -81,7 +81,7 @@ uint16_t nr_get_dci_size(nfapi_nr_dci_format_e format, /// fixed: Format identifier 1, VRB2PRB 1, MCS 5, NDI 1, RV 2, HARQ PID 4, DAI 2, PUCCH TPC 2, PUCCH RInd 3, PDSCH to HARQ TInd 3 Time Domain assgnmt 4 -- 28 size += 28; size += (uint8_t)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); // Freq domain assignment - // Time domain assignment + break; case NFAPI_NR_DL_DCI_FORMAT_1_1: @@ -160,7 +160,7 @@ uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars, nfapi_nr_config_request_t config) { - uint16_t mod_dmrs[NR_MAX_PDCCH_DMRS_LENGTH<<1]; + uint16_t mod_dmrs[NR_MAX_PDCCH_DMRS_LENGTH>>1]; uint8_t idx=0; uint16_t a; int k,l,k_prime,dci_idx, dmrs_idx; @@ -181,7 +181,6 @@ uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars, mod_dmrs[i<<1] = nr_mod_table[(NR_MOD_TABLE_QPSK_OFFSET + idx)<<1]; mod_dmrs[(i<<1)+1] = nr_mod_table[((NR_MOD_TABLE_QPSK_OFFSET + idx)<<1) + 1]; #ifdef DEBUG_PDCCH_DMRS - printf("DMRS modulation\n"); printf("i %d idx %d gold seq %d b0-b1 %d-%d mod_dmrs %d %d\n", i, idx, gold_pdcch_dmrs[(i<<1)>>5], (((gold_pdcch_dmrs[(i<<1)>>5])>>((i<<1)&0x1f))&1), (((gold_pdcch_dmrs[((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1), mod_dmrs[(i<<1)], mod_dmrs[(i<<1)+1]); #endif @@ -192,8 +191,8 @@ uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars, // scrambling uint32_t scrambled_payload[4]; - uint32_t Nid = (dci_alloc.search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC)? pdcch_params.scrambling_id : config.sch_config.physical_cell_id.value; - uint32_t n_RNTI = (dci_alloc.search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC)? dci_alloc.rnti : 0; + uint32_t Nid = (pdcch_params.search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC)? pdcch_params.scrambling_id : config.sch_config.physical_cell_id.value; + uint32_t n_RNTI = (pdcch_params.search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC)? pdcch_params.rnti : 0; nr_pdcch_scrambling(dci_alloc.dci_pdu, dci_alloc.size, Nid, n_RNTI, scrambled_payload); // QPSK modulation @@ -203,8 +202,7 @@ uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars, mod_dci[i<<1] = nr_mod_table[(NR_MOD_TABLE_QPSK_OFFSET + idx)<<1]; mod_dci[(i<<1)+1] = nr_mod_table[((NR_MOD_TABLE_QPSK_OFFSET + idx)<<1) + 1]; #ifdef DEBUG_DCI - printf("DCI modulation\n"); - printf("i %d idx %d b0-b1 %d-%d mod_dmrs %d %d\n", i, idx, (((scrambled_payload[(i<<1)>>5])>>((i<<1)&0x1f))&1), + printf("i %d idx %d b0-b1 %d-%d mod_dci %d %d\n", i, idx, (((scrambled_payload[(i<<1)>>5])>>((i<<1)&0x1f))&1), (((scrambled_payload[((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1), mod_dci[(i<<1)], mod_dci[(i<<1)+1]); #endif } diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c index e6c286452b..c2ac37a23f 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c @@ -33,20 +33,60 @@ #include "nr_dci.h" void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB, - int frame, - int subframe, - gNB_rxtx_proc_t *proc, - NR_gNB_DCI_ALLOC_t *dci_alloc, - nfapi_nr_dl_config_request_pdu_t *pdu) + int frame, + int subframe, + gNB_rxtx_proc_t *proc, + NR_gNB_DCI_ALLOC_t *dci_alloc, + nfapi_nr_dl_config_request_pdu_t *pdu) { NR_DL_FRAME_PARMS *fp = &gNB->frame_parms; - uint32_t *dci_pdu = &dci_alloc->dci_pdu[0]; - nfapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15 = &pdu->dci_dl_pdu.dci_dl_pdu_rel15; + uint32_t *dci_pdu = dci_alloc->dci_pdu; + nfapi_nr_dl_config_dci_dl_pdu_rel15_t *pdu_rel15 = &pdu->dci_dl_pdu.dci_dl_pdu_rel15; + nfapi_nr_dl_config_pdcch_parameters_rel15_t *params_rel15 = &pdu->dci_dl_pdu.pdcch_params_rel15; nfapi_nr_config_request_t *cfg = &gNB->gNB_config; - dci_alloc->L = rel15->aggregation_level; + uint16_t N_RB = fp->initial_bwp_dl.N_RB; + uint8_t fsize = 0; - if (rel15->dci_format == NFAPI_NR_DL_DCI_FORMAT_1_0) { + /// Payload generation + switch(params_rel15->dci_format) { + + case NFAPI_NR_DL_DCI_FORMAT_1_0: + switch(params_rel15->rnti_type) { + case NFAPI_NR_RNTI_RA: + // Freq domain assignment + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + for (int i=0; ifrequency_domain_assignment>>(fsize-i))&1)<time_domain_assignment>>(4-i))&1)<mcs>>(5-i))&1)<tb_scaling>>(2-i))&1)<pdcch_params, (void*)params_rel15, sizeof(nfapi_nr_dl_config_pdcch_parameters_rel15_t)); + dci_alloc->size = nr_get_dci_size(NFAPI_NR_DL_DCI_FORMAT_1_0, + NFAPI_NR_RNTI_RA, + &fp->initial_bwp_dl, + cfg); + + + +/* if (rel15->dci_format == NFAPI_NR_DL_DCI_FORMAT_1_0) { dci_alloc->format = NFAPI_NR_DL_DCI_FORMAT_1_0; dci_alloc->size = nr_get_dci_size(rel15->dci_format, rel15->rnti_type, &fp->initial_bwp_params_dl ,cfg); if (rel15->rnti_type == NFAPI_NR_RNTI_C @@ -87,7 +127,7 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB, dci_alloc->size = nr_get_dci_size(rel15->dci_format, rel15->rnti_type, &fp->initial_bwp_params_dl ,cfg); } else { AssertFatal(1==0, "[nr_fill_dci_and_dlsch] Incorrect DCI Format(%d)",rel15->dci_format); - } + }*/ return; } diff --git a/openair1/PHY/defs_gNB.h b/openair1/PHY/defs_gNB.h index 60fa298318..e699b76203 100644 --- a/openair1/PHY/defs_gNB.h +++ b/openair1/PHY/defs_gNB.h @@ -47,18 +47,10 @@ typedef struct { } NR_gNB_PBCH; typedef struct { - /// Length of DCI in bits + /// Length of DCI payload in bits uint8_t size; /// Aggregation level uint8_t L; - /// rnti - uint16_t rnti; - /// rnti type - nfapi_nr_rnti_type_e rnti_type; - /// search space type - nfapi_nr_search_space_type_e search_space_type; - /// Format - nfapi_nr_dci_format_e format; /// PDCCH parameters nfapi_nr_dl_config_pdcch_parameters_rel15_t pdcch_params; /// CCE list diff --git a/openair1/PHY/defs_nr_common.h b/openair1/PHY/defs_nr_common.h index 8c5c24cb7c..ebcb29ee6b 100644 --- a/openair1/PHY/defs_nr_common.h +++ b/openair1/PHY/defs_nr_common.h @@ -62,11 +62,15 @@ #define NR_PBCH_DMRS_LENGTH 144 // in mod symbols #define NR_PBCH_DMRS_LENGTH_DWORD 10 // ceil(2(QPSK)*NR_PBCH_DMRS_LENGTH/32) -#define NR_MAX_PDCCH_DMRS_LENGTH ((NR_MAX_NB_RB<<1)*3) // 3 symbols *2(QPSK) -#define NR_MAX_PDCCH_DMRS_LENGTH_DWORD 52 // ceil(NR_MAX_PDCCH_DMRS_LENGTH/32) +/*These max values are for the gold sequences which are generated at init for the + * full carrier bandwidth*/ +#define NR_MAX_PDCCH_DMRS_INIT_LENGTH ((NR_MAX_NB_RB<<1)*3) // 3 symbols *2(QPSK) +#define NR_MAX_PDCCH_DMRS_INIT_LENGTH_DWORD 52 // ceil(NR_MAX_PDCCH_DMRS_LENGTH/32) +/*used for the resource mapping*/ +#define NR_MAX_PDCCH_DMRS_LENGTH 576 // 16(L)*2(QPSK)*3(3 DMRS symbs per REG)*6(REG per CCE) #define NR_MAX_DCI_PAYLOAD_SIZE 64 -#define NR_MAX_DCI_SIZE 200 //random values +#define NR_MAX_DCI_SIZE 1728 //16(L)*2(QPSK)*9(12 RE per REG - 3(DMRS))*6(REG per CCE) #define NR_MAX_NUM_BWP 4 @@ -220,8 +224,8 @@ typedef struct NR_DL_FRAME_PARMS { t_nrPolar_params pbch_polar_params; //BWP params - NR_BWP_PARMS initial_bwp_params_dl; - NR_BWP_PARMS initial_bwp_params_ul; + NR_BWP_PARMS initial_bwp_dl; + NR_BWP_PARMS initial_bwp_ul; } NR_DL_FRAME_PARMS; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index c3a65cb7ca..0983acf891 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -417,12 +417,9 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, schedule_nr_mib(module_idP, frameP, subframeP); } - if (phy_test == 0) { - - } - else { - void nr_schedule_css_dlsch_phytest(module_idP, frameP, subframeP); - } + // Phytest scheduling/ option not activated because of pending bug + nr_schedule_css_dlsch_phytest(module_idP, frameP, subframeP); + /* // Allocate CCEs for good after scheduling is done diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index fe479915e0..bf3dd514b9 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -41,8 +41,8 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP, { uint8_t CC_id; - gNB_MAC_INST *gNB_mac = RC.mac[module_idP]; - NR_COMMON_channels_t *cc = gNB_mac->common_channels; + gNB_MAC_INST *nr_mac = RC.nrmac[module_idP]; + NR_COMMON_channels_t *cc = nr_mac->common_channels; nfapi_nr_dl_config_request_body_t *dl_req; nfapi_nr_dl_config_request_pdu_t *dl_config_pdu; @@ -53,7 +53,7 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP, nfapi_nr_config_request_t *cfg = &gNB->gNB_config; NR_DL_FRAME_PARMS *fp = &gNB->frame_parms; - dl_req = &gNB_mac->DL_req[CC_id].dl_config_request_body; + dl_req = &nr_mac->DL_req[CC_id].dl_config_request_body; dl_config_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu]; memset((void*)dl_config_pdu,0,sizeof(nfapi_nr_dl_config_request_pdu_t)); dl_config_pdu->pdu_type = NFAPI_NR_DL_CONFIG_DCI_DL_PDU_TYPE; @@ -61,33 +61,33 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP, nfapi_nr_dl_config_dci_dl_pdu_rel15_t *pdu_rel15 = &dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel15; nfapi_nr_dl_config_pdcch_parameters_rel15_t *params_rel15 = &dl_config_pdu->dci_dl_pdu.pdcch_params_rel15; + nr_configure_css_dci_from_mib(&gNB->pdcch_type0_params, kHz30, kHz30, nr_FR1, 0, 0, fp->slots_per_frame, cfg->rf_config.dl_channel_bandwidth.value); + memcpy((void*)params_rel15, (void*)&gNB->pdcch_type0_params, sizeof(nfapi_nr_dl_config_pdcch_parameters_rel15_t)); - pdu_rel15->frequency_domain_resource_assignment = 5; - pdu_rel15->time_domain_resource_assignment = 2; + pdu_rel15->frequency_domain_assignment = 5; + pdu_rel15->time_domain_assignment = 2; pdu_rel15->vrb_to_prb_mapping = 0; pdu_rel15->tb_scaling = 1; - LOG_I(PHY, "DCI type 1 payload: freq_alloc %d, time_alloc %d, vrb to prb %d, tb_scaling %d\n", - pdu_rel15->frequency_domain_resource_assignment, - pdu_rel15->time_domain_resource_assignment, + LOG_I(MAC, "DCI type 1 payload: freq_alloc %d, time_alloc %d, vrb to prb %d, tb_scaling %d\n", + pdu_rel15->frequency_domain_assignment, + pdu_rel15->time_domain_assignment, pdu_rel15->vrb_to_prb_mapping, pdu_rel15->tb_scaling); params_rel15->rnti = 0x03; params_rel15->rnti_type = NFAPI_NR_RNTI_RA; params_rel15->dci_format = NFAPI_NR_DL_DCI_FORMAT_1_0; - params_rel15->aggregation_level = 4; - LOG_I(PHY, "DCI type 1 params: rmsi_pdcch_config, rnti %d, rnti_type %d, dci_format, L %d\n \ + LOG_I(MAC, "DCI type 1 params: rmsi_pdcch_config %d, rnti %d, rnti_type %d, dci_format %d\n \ coreset params: mux_pattern %d, n_rb %d, n_symb %d, rb_offset %d \n \ ss params : nb_ss_sets_per_slot %d, first symb %d, nb_slots %d, sfn_mod2 %d, first slot %d\n", 0, params_rel15->rnti, params_rel15->rnti_type, params_rel15->dci_format, - params_rel15->aggregation_level, params_rel15->mux_pattern, params_rel15->n_rb, params_rel15->n_symb,