From c73a922c8dd96dc5b192bfc5869a5718b45420dd Mon Sep 17 00:00:00 2001 From: frobinet Date: Fri, 16 Nov 2018 15:40:32 +0100 Subject: [PATCH 1/3] SYRTEM SDR platform : - remove size limitation of 307200 in trx_read_func (SYRIQ library) - update to new openair0 interface (./targets/ARCH/COMMON/common_lib.h) - add gNB band22 configuration file (./targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band22.tm1.106PRB.adrv9371zc706.conf) please read ./targets/ARCH/ADRV9371_ZC706/SYRTEM_IQ_QuickStart.readme for more details --- cmake_targets/build_oai | 21 +- oaienv | 3 +- targets/ARCH/ADRV9371_ZC706/Makefile | 63 ---- .../SYRTEM_IQ_QuickStart.readme | 126 +++++++ .../SYRTEM_IQ_uninstall_previous_SW.sh | 28 ++ .../USERSPACE/PROFILES/ADRV9371-W_test.ini | 337 ------------------ ....PRB100.NR40.adrv9371-zc706_HWgain15dB.ini | 89 ----- ....PRB100.NR80.adrv9371-zc706_HWgain15dB.ini | 89 ----- ...7.tm1.PRB100.adrv9371-zc706_HWgain15dB.ini | 89 ----- .../USERSPACE/PROFILES/profile1-osc.ini | 85 ----- .../USERSPACE/PROFILES/profile20MHz.txt | 285 --------------- .../USERSPACE/PROFILES/profileNR40MHz.txt | 245 ------------- .../USERSPACE/PROFILES/profileNR80MHz.txt | 197 ---------- .../PROFILES/profile_rx30_Tx60_syr.txt | 285 --------------- ...e.band7.tm1.PRB100.NR40.adrv9371-zc706.ini | 89 ----- ...e.band7.tm1.PRB100.NR80.adrv9371-zc706.ini | 89 ----- .../ue.band7.tm1.PRB100.adrv9371-zc706.ini | 89 ----- ...7.tm1.PRB100.adrv9371-zc706_HWgain15dB.ini | 89 ----- .../ue.band7.tm1.PRB25.adrv9371-zc706.ini | 85 ----- .../ue.band7.tm1.PRB50.adrv9371-zc706.ini | 85 ----- targets/ARCH/ADRV9371_ZC706/readme.txt | 17 - .../ADRV9371_ZC706/slib/libadrv9371_zc706.so | Bin 260713 -> 0 bytes .../gnb.band22.tm1.106PRB.adrv9371zc706.conf | 289 +++++++++++++++ targets/RT/USER/lte-hwlat.c | 26 +- targets/RT/USER/nr-softmodem.c | 2 +- 25 files changed, 474 insertions(+), 2328 deletions(-) delete mode 100755 targets/ARCH/ADRV9371_ZC706/Makefile create mode 100755 targets/ARCH/ADRV9371_ZC706/SYRTEM_IQ_QuickStart.readme create mode 100755 targets/ARCH/ADRV9371_ZC706/SYRTEM_IQ_uninstall_previous_SW.sh delete mode 100644 targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ADRV9371-W_test.ini delete mode 100644 targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/gnb.band7.tm1.PRB100.NR40.adrv9371-zc706_HWgain15dB.ini delete mode 100644 targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/gnb.band7.tm1.PRB100.NR80.adrv9371-zc706_HWgain15dB.ini delete mode 100644 targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/gnb.band7.tm1.PRB100.adrv9371-zc706_HWgain15dB.ini delete mode 100644 targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile1-osc.ini delete mode 100644 targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile20MHz.txt delete mode 100644 targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profileNR40MHz.txt delete mode 100644 targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profileNR80MHz.txt delete mode 100644 targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile_rx30_Tx60_syr.txt delete mode 100644 targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.NR40.adrv9371-zc706.ini delete mode 100644 targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.NR80.adrv9371-zc706.ini delete mode 100644 targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.adrv9371-zc706.ini delete mode 100644 targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.adrv9371-zc706_HWgain15dB.ini delete mode 100644 targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB25.adrv9371-zc706.ini delete mode 100644 targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB50.adrv9371-zc706.ini delete mode 100644 targets/ARCH/ADRV9371_ZC706/readme.txt delete mode 100755 targets/ARCH/ADRV9371_ZC706/slib/libadrv9371_zc706.so create mode 100644 targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band22.tm1.106PRB.adrv9371zc706.conf diff --git a/cmake_targets/build_oai b/cmake_targets/build_oai index 56f5300051..82cdba228f 100755 --- a/cmake_targets/build_oai +++ b/cmake_targets/build_oai @@ -516,10 +516,10 @@ function main() { install_usrp_uhd_driver $UHD_IMAGES_DIR fi fi - if [ "$HW" == "OAI_ADRV9371_ZC706" ] ; then - echo_info "\nInstalling packages for ADRV9371_ZC706 support" - check_install_libiio_driver - fi +# if [ "$HW" == "OAI_ADRV9371_ZC706" ] ; then +# echo_info "\nInstalling packages for ADRV9371_ZC706 support" +# check_install_libiio_driver +# fi if [ "$HW" == "OAI_BLADERF" ] ; then echo_info "installing packages for BLADERF support" check_install_bladerf_driver @@ -836,9 +836,18 @@ function main() { echo_info "liboai_device.so is linked to EXMIMO device library" elif [ "$HW" == "OAI_ADRV9371_ZC706" ] ; then - ln -sf $OPENAIR_DIR/targets/ARCH/ADRV9371_ZC706/slib/libadrv9371_zc706.so liboai_device.so + SYRIQ_KVER=$(uname -r) + SYRIQ_KMAJ=$(echo $SYRIQ_KVER | sed -e 's/^\([0-9][0-9]*\)\.[0-9][0-9]*\.[0-9][0-9]*.*/\1/') + SYRIQ_KMIN=$(echo $SYRIQ_KVER | sed -e 's/^[0-9][0-9]*\.\([0-9][0-9]*\)\.[0-9][0-9]*.*/\1/') + #echo $SYRIQ_KMAJ$SYRIQ_KMIN + if [ "$SYRIQ_KMAJ$SYRIQ_KMIN" == "319" ] || [ "$SYRIQ_KMAJ$SYRIQ_KMIN" == "410" ] || [ "$SYRIQ_KMAJ$SYRIQ_KMIN" == "415" ] ; then +# echo "Kernel $SYRIQ_KMAJ.$SYRIQ_KMIN detected" + ln -sf /usr/local/lib/syriq/libadrv9371zc706.so liboai_device.so + else + echo_error "== FAILED == Unexpected Kernel $SYRIQ_KMAJ.$SYRIQ_KMIN" + fi + echo_info "liboai_device.so is linked to ADRV9371_ZC706 device library for Kernel $SYRIQ_KMAJ.$SYRIQ_KMIN" - echo_info "liboai_device.so is linked to ADRV9371_ZC706 device library" elif [ "$HW" == "OAI_USRP" ] ; then compilations \ $build_dir oai_usrpdevif \ diff --git a/oaienv b/oaienv index d9a540697b..4cee684b3d 100644 --- a/oaienv +++ b/oaienv @@ -18,5 +18,6 @@ alias oailte='cd $OPENAIR_TARGETS/RT/USER' alias oais='cd $OPENAIR_TARGETS/SIMU/USER' alias oaiex='cd $OPENAIR_TARGETS/SIMU/EXAMPLES' -export IIOD_REMOTE=192.168.121.32 +#export IIOD_REMOTE=192.168.121.32 +export IIOD_REMOTE=192.168.1.11 diff --git a/targets/ARCH/ADRV9371_ZC706/Makefile b/targets/ARCH/ADRV9371_ZC706/Makefile deleted file mode 100755 index 5684c7b3bc..0000000000 --- a/targets/ARCH/ADRV9371_ZC706/Makefile +++ /dev/null @@ -1,63 +0,0 @@ -# Creates shared library - -CC= gcc -CFLAGS+= -DADRV9371_ZC706 -DHWLAT -O0 -g3 -Wall -fmessage-length=0 -fPIC - -DROOT= ./USERSPACE -DIR= $(DROOT)/LIB - -IFLAGS+= -I$(DIR)/ \ - -I$(DROOT)/libini/ \ - -I../COMMON/ \ - -I/usr/include/ - -LDFLAGS+= -L/usr/lib/x86/64-linux-gnu/ \ - -lm -liio -ldl -lriffa - -OUTDIR= ./slib -TARGET= libadrv9371_zc706.so - -SRC= $(DIR)/adrv9371_dump.c \ - $(DIR)/adrv9371_helper.c \ - $(DIR)/adrv9371_self_test.c \ - $(DIR)/adrv9371_zc706_lib.c \ - $(DIR)/adrv9371_zc706_riffa_lib.c \ - $(DIR)/adrv9371_zc706_stats.c \ - $(DIR)/hw_init.c \ - $(DROOT)/libini/libini.c - -OBJ= $(OUTDIR)/adrv9371_dump.o \ - $(OUTDIR)/adrv9371_helper.o \ - $(OUTDIR)/adrv9371_self_test.o \ - $(OUTDIR)/adrv9371_zc706_lib.o \ - $(OUTDIR)/adrv9371_zc706_riffa_lib.o \ - $(OUTDIR)/adrv9371_zc706_stats.o \ - $(OUTDIR)/hw_init.o \ - $(OUTDIR)/libini.o - -all: lib - -dir: - mkdir -p $(OUTDIR) - -env: - set PATH=/usr/lib/:${PATH} - -obj: dir env - $(CC) -c $(CFLAGS) $(IFLAGS) $(SRC) - mv *.o $(OUTDIR) - -lib: dir obj - $(CC) -shared $(OBJ) -o $(OUTDIR)/$(TARGET) $(LDFLAGS) - -# exec: env -# $(CC) $(CFLAGS) $(IFLAGS) main.c $(SRC) -o lib.exe $(LDFLAGS) -lpthread - -.PHONY: clean - -clean: - rm -f $(OUTDIR)/*.o $(OUTDIR)/*~ - -rm: clean - rm -f $(OUTDIR)/$(TARGET) - rmdir $(OUTDIR) \ No newline at end of file diff --git a/targets/ARCH/ADRV9371_ZC706/SYRTEM_IQ_QuickStart.readme b/targets/ARCH/ADRV9371_ZC706/SYRTEM_IQ_QuickStart.readme new file mode 100755 index 0000000000..46a77ce272 --- /dev/null +++ b/targets/ARCH/ADRV9371_ZC706/SYRTEM_IQ_QuickStart.readme @@ -0,0 +1,126 @@ +/* ********** ********** ********** ********** ********** ********** ********** */ +Requirements: +------------- +- Previous kernel module/libraries shall be uninstalled !!! + - cf. command line below "SYRTEM_IQ_uninstall_previous_SW.sh" +./SYRTEM_IQ_unload_previous_SW.sh +- You shall have SYRIQ1.4.6nr.tar.gz +- Ubuntu kernel version is restricted to: + - Kernel 4.15.0-20-lowlatency (Ubuntu 18.04) + - Kernel 4.10.0-42-lowlatency (Ubuntu 17.04) + - Kernel 3.19.0-61-lowlatency (Ubuntu 14.04) +- ADRV9371+ZC706 PCIe board shall be switched on +- PC shall be reboot once ADRV9371+ZC706 PCIe board is switched on + +mkdir eur_oai_develop-nr +cd eur_oai_develop-nr + +git clone https://gitlab.eurecom.fr/oai/openairinterface5g.git +cd openairinterface5g + +git checkout 375-syrtem-adrv9371zc706_update + +./targets/ARCH/ADRV9371_ZC706/SYRTEM_IQ_uninstall_previous_SW.sh +-> Reading package lists... Done +-> Building dependency tree +-> Reading state information... Done +-> linux-headers-4.15.0-20-lowlatency is already the newest version (4.15.0-20.21). +-> 0 upgraded, 0 newly installed, 0 to remove and 327 not upgraded. +-> Previous SYRIQ is loaded! + -> previous SYRIQ is unloaded! + -> previous SYRIQ is uninstall! +-> Previous SYRIQ uninstallation is done + + + + +/* ********** ********** ********** ********** ********** ********** ********** */ +UE: +--- +configuration: +-------------- +sudo apt update +sudo apt-get update + +tar -xvzf SYRIQ1.4.6nr.tar.gz +./SYRIQplatformR1.4.6nr_install.sh +sudo reboot + +sudo lspci -vv | grep Xilinx +sudo lspci -vv -s 02:00.0 | grep LnkSta +sudo lspci -vv -s 03:00.0 | grep LnkSta +sudo lspci -vv -s 02:00.0 | grep Interr +sudo lspci -vv -s 03:00.0 | grep Interr + +sudo gedit /usr/local/etc/syriq/cpu-irq.sh +echo '1' > /proc/irq/49/smp_affinity_list +echo '5' > /proc/irq/48/smp_affinity_list + +gedit oaienv +export IIOD_REMOTE=192.168.1.11 + + + +compilation: +------------ +sudo cset shield --reset +cd eur_oai_develop-nr/openairinterface5g/ +source oaienv + +sudo -E ./cmake_targets/build_oai -c --nrUE -w ADRV9371_ZC706 -I +sudo -E ./cmake_targets/build_oai -c --nrUE -w ADRV9371_ZC706 + + + +run: +---- +source oaienv +sudo -E /usr/local/etc/syriq/cpu-irq.sh + +sudo -E cset shield -e ./targets/bin/nr-uesoftmodem.Rel15 -- --numerology 1 -r 106 -C 3510000000 --loop-memory --rf-config-file /usr/local/etc/syriq/ue.band22.tm1.PRB100.NR40.dat + + + + + +/* ********** ********** ********** ********** ********** ********** ********** */ +gNB: +---- +configuration: +-------------- +sudo apt update +sudo apt-get update + +tar -xvzf SYRIQ1.4.6nr.tar.gz +./SYRIQplatformR1.4.6nr_install.sh +sudo reboot + +sudo lspci -vv | grep Xilinx +sudo lspci -vv -s 02:00.0 | grep LnkSta +sudo lspci -vv -s 02:00.0 | grep Interr + +sudo gedit /usr/local/etc/syriq/cpu-irq.sh +echo '1' > /proc/irq/46/smp_affinity_list + +gedit oaienv +export IIOD_REMOTE=192.168.1.21 + + + +compilation: +------------ +sudo cset shield --reset +cd eur_oai_develop-nr/openairinterface5g/ +source oaienv + +sudo -E ./cmake_targets/build_oai -c --gNB -w ADRV9371_ZC706 -I +sudo -E ./cmake_targets/build_oai -c --gNB -w ADRV9371_ZC706 + + + +run: +---- +source oaienv +sudo -E /usr/local/etc/syriq/cpu-irq.sh + +sudo -E cset shield -e ./targets/bin/nr-softmodem.Rel15 -- -O $OPENAIR_DIR/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band22.tm1.106PRB.adrv9371zc706.conf --rf-config-file /usr/local/etc/syriq/gnb.band22.tm1.PRB100.NR40_hwgain15.dat diff --git a/targets/ARCH/ADRV9371_ZC706/SYRTEM_IQ_uninstall_previous_SW.sh b/targets/ARCH/ADRV9371_ZC706/SYRTEM_IQ_uninstall_previous_SW.sh new file mode 100755 index 0000000000..6651a3beb8 --- /dev/null +++ b/targets/ARCH/ADRV9371_ZC706/SYRTEM_IQ_uninstall_previous_SW.sh @@ -0,0 +1,28 @@ +# Previous SYRIQ uninstall +#!/bin/sh +MODULE="riffa" +KERNEL_VERSION=$(uname -r) +RHR=/etc/redhat-release + +sudo apt-get install -y --allow-unauthenticated linux-headers-`uname -r` + +if lsmod | grep "$MODULE" &> /dev/null ; then + echo "Previous SYRIQ is loaded!" + sudo rmmod $MODULE + echo " -> previous SYRIQ is unloaded!" + sudo rm -f /usr/local/lib/libriffa.so* + sudo rm -f /usr/local/include/riffa.h + sudo rm -f /usr/local/include/riffa_driver.h + sudo rm -f /etc/ld.so.conf.d/riffa.conf + sudo rm -rf /lib/modules/$KERNEL_VERSION/kernel/drivers/riffa + sudo rm -f /etc/udev/rules.d/99-riffa.rules + sudo sed -i '/riffa/d' /etc/modules + sudo ldconfig + sudo depmod + echo " -> previous SYRIQ is uninstall!" + echo "Previous SYRIQ uninstallation is done" + exit 0 +else + echo "Previous SYRIQ is not loaded!" + exit 1 +fi diff --git a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ADRV9371-W_test.ini b/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ADRV9371-W_test.ini deleted file mode 100644 index c1861b2e8d..0000000000 --- a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ADRV9371-W_test.ini +++ /dev/null @@ -1,337 +0,0 @@ -[IIO Oscilloscope] -plugin.DMM.detached=0 -plugin.Debug.detached=0 -plugin.AD9371 Advanced.detached=0 -plugin.AD9371.detached=0 -startup_version_check=0 -test=1 - -[IIO Oscilloscope - Capture Window1] -fru_connect = 1 -test.message = Please ensure:\n • 30.72 MHz -> REF_CLK_IN (0dBm)\n • Rx1 <-> Tx1\n • Rx2 <-> Tx2 -domain=fft -sample_count=400 -fft_size=16384 -fft_avg=8 -fft_pwr_offset=0.000000 -graph_type=Lines -show_grid=1 -enable_auto_scale=1 -x_axis_min=-67.583626 -x_axis_max=67.576126 -y_axis_min=-130 -y_axis_max=3 -show_capture_options = 1 - -axi-ad9371-rx-obs-hpc.expanded=1 -axi-ad9371-rx-obs-hpc.active=0 -axi-ad9371-rx-obs-hpc.trigger_enabled=0 -axi-ad9371-rx-obs-hpc.voltage0_i.enabled=0 -axi-ad9371-rx-obs-hpc.voltage0_q.enabled=0 - -axi-ad9371-rx-hpc.expanded=1 -axi-ad9371-rx-hpc.active=1 -axi-ad9371-rx-hpc.voltage0_i.enabled=1 -axi-ad9371-rx-hpc.voltage0_q.enabled=1 -axi-ad9371-rx-hpc.voltage1_i.enabled=0 -axi-ad9371-rx-hpc.voltage1_q.enabled=0 - -marker_type = Single Tone Markers -marker.0 = 9525 -marker.1 = 8192 -marker.2 = 10859 -marker.3 = 12193 -marker.4 = 13526 -marker.5 = 14859 -capture_started=0 - -[DMM] -device_list = ad7291 0 -device_list = ad9371-phy 0 -device_list = xadc 0 -running = No - -# temp between 20C and 55C (in 0.25C units) -test.ad7291.in_temp0_raw.int = 80 220 - -# See the production testing wiki docs [1] for how these values are calculated. -# [1]: (https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/testing#voltage) - -# scale = 0.610351562 -# All nominal voltages +/- 2.5% - -# 0 INPUT_VOLTAGE 12V - V(Drop Diode) 56/10 -test.ad7291.in_voltage0_raw.int = 2710 2850 - -# 1 VOUT2_1V3_DIG 1 -test.ad7291.in_voltage1_raw.int = 2077 2183 - -# 2 VDD_IF 10/10 -test.ad7291.in_voltage2_raw.int = 1997 2099 - -# 3 VOUT3_3V3 10/10 -test.ad7291.in_voltage3_raw.int = 2636 2770 - -# 5 VOUT4_1V8 1 -test.ad7291.in_voltage5_raw.int = 2875 3023 - -# 7 VOUT1_1V3_ANLG 1 -test.ad7291.in_voltage7_raw.int = 2077 2183 - - -# Test AD9528 lock status - Requires 30.720 MHz reference clock! -test.ad9528-1.pll1_reference_clk_a_present.int = 1 1 -test.ad9528-1.pll1_locked.int = 1 1 -test.ad9528-1.pll2_locked.int = 1 1 - - -[AD9371] -ad9371-phy.in_voltage2_rf_port_select = INTERNALCALS -ad9371-phy.in_voltage2_temp_comp_gain = 0.00 dB -ad9371-phy.out_altvoltage1_TX_LO_frequency = 2500000000 -ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = 2600000000 -ad9371-phy.out_voltage1_hardwaregain = -10.000000 dB -ad9371-phy.out_voltage1_lo_leakage_tracking_en = 1 -ad9371-phy.out_voltage1_quadrature_tracking_en = 1 -ad9371-phy.in_voltage0_gain_control_mode = automatic -ad9371-phy.in_voltage0_quadrature_tracking_en = 1 -ad9371-phy.in_voltage0_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage1_quadrature_tracking_en = 1 -ad9371-phy.in_voltage1_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage1_gain_control_mode = automatic -ad9371-phy.out_altvoltage0_RX_LO_frequency = 2600000000 -ad9371-phy.out_voltage0_lo_leakage_tracking_en = 1 -ad9371-phy.out_voltage0_hardwaregain = -10.000000 dB -ad9371-phy.out_voltage0_quadrature_tracking_en = 1 -ad9371-phy.ensm_mode = radio_on -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_scale = 0.251160 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_frequency = 10001402 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_frequency = 1001265 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_frequency = 10001402 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_scale = 0.251160 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_frequency = 10001402 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_scale = 0.251160 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_frequency = 40001860 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_frequency = 1001265 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_scale = 0.251160 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_frequency = 10001402 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_frequency = 40001860 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_scale = 0.000000 -dds_mode_tx1 = 0 -dds_mode_tx2 = 0 -SYNC_RELOAD = 1 - -# test receiver at 1GHz to 5 GHz -# SEQ FIRST INCREMENT LAST - i 1000000000 5000000000 5000000000 - -[IIO Oscilloscope - Capture Window1] -# wait for device to settle -marker_type = Peak Markers -capture_started = 0 -cycle = 1000 -axi-ad9371-rx-hpc.voltage0_i.enabled=1 -axi-ad9371-rx-hpc.voltage0_q.enabled=1 -axi-ad9371-rx-hpc.voltage1_i.enabled=0 -axi-ad9371-rx-hpc.voltage1_q.enabled=0 -cycle = 1000 - -[AD9371] -ad9371-phy.out_altvoltage1_TX_LO_frequency = -ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = {{} + {100000000}} -ad9371-phy.out_altvoltage0_RX_LO_frequency = {{} + {100000000}} -dds_mode_tx1 = 0 -dds_mode_tx2 = 0 -SYNC_RELOAD = 1 - -[IIO Oscilloscope - Capture Window1] -# wait for device to settle -capture_started = 1 -cycle = 3000 - -[AD9371] -# channels should be off, so RSSI should be low -test.ad9371-phy.in_voltage0_rssi.int = 44 45 -test.ad9371-phy.in_voltage1_rssi.int = 44 45 - -# and gain is high -test.ad9371-phy.in_voltage0_hardwaregain.double = 30.0 31.0 -test.ad9371-phy.in_voltage0_hardwaregain.double = 30.0 31.0 - -# set Tx and Rx to be the same -ad9371-phy.out_altvoltage0_RX_LO_frequency = -dds_mode_tx1 = 1 -dds_mode_tx2 = 1 -SYNC_RELOAD = 1 - -[IIO Oscilloscope - Capture Window1] -# wait for device to settle -marker_type = Single Tone Markers -cycle = 3000 - -[AD9371] - -ad9371-phy.out_voltage0_hardwaregain = 0.000000 dB -ad9371-phy.out_voltage1_hardwaregain = 0.000000 dB - -# channels should be on, so RSSI should be high -test.ad9371-phy.in_voltage0_rssi.int = 3 12 -test.ad9371-phy.in_voltage1_rssi.int = 3 12 - -# and gain is low -test.ad9371-phy.in_voltage0_hardwaregain.double = 15.0 29.0 -test.ad9371-phy.in_voltage0_hardwaregain.double = 15.0 29.0 - - - -[IIO Oscilloscope - Capture Window1] -cycle = 1000 -capture_started = 1 -cycle = 3000 -save_png = ADRV9371_rx1_.png -save_markers = markers.log - -#look at the markers - Fundamental -test.marker.0 = -12.0 -4.0 -# DC -test.marker.1 = -100.0 -60.0 -# 2st Harmonic -test.marker.2 = -110.0 -75.0 -# 3nd Harmonic -test.marker.3 = -110.0 -75.0 -# 4th Harmonic -test.marker.4 = -110.0 -75.0 -# 4th Harmonic -test.marker.5 = -110.0 -65.0 - -capture_started = 0 -cycle = 1000 - -axi-ad9371-rx-hpc.voltage0_i.enabled=0 -axi-ad9371-rx-hpc.voltage0_q.enabled=0 -axi-ad9371-rx-hpc.voltage1_i.enabled=1 -axi-ad9371-rx-hpc.voltage1_q.enabled=1 - -cycle = 1000 -capture_started = 1 -cycle = 3000 -save_png = ADRV9371_rx2_.png -save_markers = markers.log - -#look at the markers - Fundamental -test.marker.0 = -12.0 -4.0 -# DC -test.marker.1 = -100.0 -60.0 -# 2st Harmonic -test.marker.2 = -110.0 -75.0 -# 3nd Harmonic -test.marker.3 = -110.0 -75.0 -# 4th Harmonic -test.marker.4 = -110.0 -75.0 -# 4th Harmonic -test.marker.5 = -110.0 -65.0 - - - -[IIO Oscilloscope - Capture Window1] -capture_started = 0 -test.message = Please ensure:\n • ORX1 <-> Tx1\n • ORX22 <-> Tx2 - -axi-ad9371-rx-hpc.expanded=1 -axi-ad9371-rx-hpc.active=0 -axi-ad9371-rx-hpc.voltage0_i.enabled=0 -axi-ad9371-rx-hpc.voltage0_q.enabled=0 -axi-ad9371-rx-hpc.voltage1_i.enabled=0 -axi-ad9371-rx-hpc.voltage1_q.enabled=0 - -axi-ad9371-rx-obs-hpc.expanded=1 -axi-ad9371-rx-obs-hpc.active=1 -axi-ad9371-rx-obs-hpc.voltage0_i.enabled=1 -axi-ad9371-rx-obs-hpc.voltage0_q.enabled=1 -cycle = 1000 - -# test observer path at 1GHz to 5 GHz -# SEQ FIRST INCREMENT LAST - i 1000000000 1000000000 5000000000 - -[AD9371] -# set Tx and Rx to be the same -ad9371-phy.out_altvoltage1_TX_LO_frequency = -ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = {{} + {1000000}} -ad9371-phy.out_altvoltage0_RX_LO_frequency = -dds_mode_tx1 = 1 -dds_mode_tx2 = 1 -ad9371-phy.out_voltage0_hardwaregain = -10.000000 dB -ad9371-phy.out_voltage1_hardwaregain = -10.000000 dB -ad9371-phy.in_voltage2_rf_port_select = ORX1_TX_LO -ad9371-phy.in_voltage2_gain_control_mode = manual -ad9371-phy.in_voltage2_hardwaregain = 18.000000 dB - -[IIO Oscilloscope - Capture Window1] -capture_started = 1 -cycle = 3000 -save_png = ADRV9371_ob1_.png -save_markers = markers.log - -#look at the markers - Fundamental -test.marker.0 = -15.0 -5.0 -# DC -test.marker.1 = -100.0 -75.0 -# 2st Harmonic -test.marker.2 = -110.0 -75.0 -# 3nd Harmonic -test.marker.3 = -110.0 -75.0 -# 4th Harmonic -test.marker.4 = -110.0 -75.0 -# 4th Harmonic -test.marker.5 = -110.0 -65.0 - -[AD9371] - -ad9371-phy.in_voltage2_rf_port_select = ORX2_TX_LO - - -[IIO Oscilloscope - Capture Window1] -cycle = 1000 -capture_started = 1 -cycle = 3000 -save_png = ADRV9371_ob2_.png -save_markers = markers.log - -#look at the markers - Fundamental -test.marker.0 = -15.0 -4.0 -# DC -test.marker.1 = -100.0 -75.0 -# 2st Harmonic -test.marker.2 = -110.0 -75.0 -# 3nd Harmonic -test.marker.3 = -110.0 -75.0 -# 4th Harmonic -test.marker.4 = -110.0 -75.0 -# 4th Harmonic -test.marker.5 = -110.0 -65.0 - - - -[IIO Oscilloscope - Capture Window1] -test.message = All tests passed - Ship it -quit = 1 diff --git a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/gnb.band7.tm1.PRB100.NR40.adrv9371-zc706_HWgain15dB.ini b/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/gnb.band7.tm1.PRB100.NR40.adrv9371-zc706_HWgain15dB.ini deleted file mode 100644 index d5b0b8f3b6..0000000000 --- a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/gnb.band7.tm1.PRB100.NR40.adrv9371-zc706_HWgain15dB.ini +++ /dev/null @@ -1,89 +0,0 @@ -[AD9371] -ad9371-phy.in_voltage2_rf_port_select = OFF -ad9371-phy.in_voltage2_hardwaregain = -156.000000 dB -ad9371-phy.in_voltage2_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_voltage0_lo_leakage_tracking_en = 0 -ad9371-phy.out_voltage0_hardwaregain = 0.000000 dB -ad9371-phy.out_voltage0_quadrature_tracking_en = 1 -ad9371-phy.out_voltage1_hardwaregain = 0.000000 dB -ad9371-phy.out_voltage1_lo_leakage_tracking_en = 0 -ad9371-phy.out_voltage1_quadrature_tracking_en = 1 -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_altvoltage1_TX_LO_frequency = 2680000000 -ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = 2560000000 -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage0_gain_control_mode = manual -ad9371-phy.in_voltage0_quadrature_tracking_en = 1 -ad9371-phy.in_voltage0_hardwaregain = 15.000000 dB -ad9371-phy.in_voltage0_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage1_quadrature_tracking_en = 1 -ad9371-phy.in_voltage1_hardwaregain = 15.000000 dB -ad9371-phy.in_voltage1_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage1_gain_control_mode = manual -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_altvoltage0_RX_LO_frequency = 2560000000 -ad9371-phy.calibrate_rx_qec_en = 0 -ad9371-phy.calibrate_tx_lol_en = 0 -ad9371-phy.calibrate_vswr_en = 0 -ad9371-phy.calibrate_tx_qec_en = 0 -ad9371-phy.calibrate_clgc_en = 0 -ad9371-phy.ensm_mode = radio_on -ad9371-phy.calibrate_tx_lol_ext_en = 0 -ad9371-phy.calibrate_dpd_en = 0 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_scale = 0.501160 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_frequency = 1999718 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_frequency = 1000327 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_frequency = 7999809 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_scale = 0.251160 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_frequency = 7999809 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_scale = 0.251160 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_frequency = 19998117 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_frequency = 1000327 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_scale = 0.501160 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_frequency = 1999718 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_frequency = 19998117 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_scale = 0.000000 -load_myk_profile_file = /targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profileNR40MHz.txt -dds_mode_tx1 = 1 -dds_mode_tx2 = 1 -dac_buf_filename = /usr/local/lib/osc/waveforms/LTE20.mat -tx_channel_0 = 1 -tx_channel_1 = 1 -tx_channel_2 = 0 -tx_channel_3 = 0 -global_settings_show = 1 -tx_show = 1 -rx_show = 1 -obs_show = 1 -fpga_show = 1 - -[ADRV9371_ZC706] -# NO_DEBUG=0; DEBUG=1 -debug_mode = 0 -# 20MHz 40MHz 80MHz=1; 10MHz=2; 5MHz=4 -interpolation_decimation_factor = 1 -# is taken into account only if "ad9371-phy.in_voltage0_gain_control_mode = manual" -rx_gain_offset = 46 diff --git a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/gnb.band7.tm1.PRB100.NR80.adrv9371-zc706_HWgain15dB.ini b/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/gnb.band7.tm1.PRB100.NR80.adrv9371-zc706_HWgain15dB.ini deleted file mode 100644 index 65006f3365..0000000000 --- a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/gnb.band7.tm1.PRB100.NR80.adrv9371-zc706_HWgain15dB.ini +++ /dev/null @@ -1,89 +0,0 @@ -[AD9371] -ad9371-phy.in_voltage2_rf_port_select = OFF -ad9371-phy.in_voltage2_hardwaregain = -156.000000 dB -ad9371-phy.in_voltage2_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_voltage0_lo_leakage_tracking_en = 0 -ad9371-phy.out_voltage0_hardwaregain = 0.000000 dB -ad9371-phy.out_voltage0_quadrature_tracking_en = 1 -ad9371-phy.out_voltage1_hardwaregain = 0.000000 dB -ad9371-phy.out_voltage1_lo_leakage_tracking_en = 0 -ad9371-phy.out_voltage1_quadrature_tracking_en = 1 -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_altvoltage1_TX_LO_frequency = 2680000000 -ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = 2560000000 -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage0_gain_control_mode = manual -ad9371-phy.in_voltage0_quadrature_tracking_en = 1 -ad9371-phy.in_voltage0_hardwaregain = 15.000000 dB -ad9371-phy.in_voltage0_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage1_quadrature_tracking_en = 1 -ad9371-phy.in_voltage1_hardwaregain = 15.000000 dB -ad9371-phy.in_voltage1_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage1_gain_control_mode = manual -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_altvoltage0_RX_LO_frequency = 2560000000 -ad9371-phy.calibrate_rx_qec_en = 0 -ad9371-phy.calibrate_tx_lol_en = 0 -ad9371-phy.calibrate_vswr_en = 0 -ad9371-phy.calibrate_tx_qec_en = 0 -ad9371-phy.calibrate_clgc_en = 0 -ad9371-phy.ensm_mode = radio_on -ad9371-phy.calibrate_tx_lol_ext_en = 0 -ad9371-phy.calibrate_dpd_en = 0 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_scale = 0.501160 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_frequency = 1999718 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_frequency = 1000327 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_frequency = 7999809 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_scale = 0.251160 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_frequency = 7999809 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_scale = 0.251160 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_frequency = 19998117 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_frequency = 1000327 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_scale = 0.501160 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_frequency = 1999718 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_frequency = 19998117 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_scale = 0.000000 -load_myk_profile_file = /targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profileNR80MHz.txt -dds_mode_tx1 = 1 -dds_mode_tx2 = 1 -dac_buf_filename = /usr/local/lib/osc/waveforms/LTE20.mat -tx_channel_0 = 1 -tx_channel_1 = 1 -tx_channel_2 = 0 -tx_channel_3 = 0 -global_settings_show = 1 -tx_show = 1 -rx_show = 1 -obs_show = 1 -fpga_show = 1 - -[ADRV9371_ZC706] -# NO_DEBUG=0; DEBUG=1 -debug_mode = 0 -# 20MHz 40MHz 80MHz=1; 10MHz=2; 5MHz=4 -interpolation_decimation_factor = 1 -# is taken into account only if "ad9371-phy.in_voltage0_gain_control_mode = manual" -rx_gain_offset = 46 diff --git a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/gnb.band7.tm1.PRB100.adrv9371-zc706_HWgain15dB.ini b/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/gnb.band7.tm1.PRB100.adrv9371-zc706_HWgain15dB.ini deleted file mode 100644 index 63074daad5..0000000000 --- a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/gnb.band7.tm1.PRB100.adrv9371-zc706_HWgain15dB.ini +++ /dev/null @@ -1,89 +0,0 @@ -[AD9371] -ad9371-phy.in_voltage2_rf_port_select = OFF -ad9371-phy.in_voltage2_hardwaregain = -156.000000 dB -ad9371-phy.in_voltage2_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_voltage0_lo_leakage_tracking_en = 0 -ad9371-phy.out_voltage0_hardwaregain = 0.000000 dB -ad9371-phy.out_voltage0_quadrature_tracking_en = 1 -ad9371-phy.out_voltage1_hardwaregain = 0.000000 dB -ad9371-phy.out_voltage1_lo_leakage_tracking_en = 0 -ad9371-phy.out_voltage1_quadrature_tracking_en = 1 -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_altvoltage1_TX_LO_frequency = 2680000000 -ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = 2560000000 -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage0_gain_control_mode = manual -ad9371-phy.in_voltage0_quadrature_tracking_en = 1 -ad9371-phy.in_voltage0_hardwaregain = 15.000000 dB -ad9371-phy.in_voltage0_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage1_quadrature_tracking_en = 1 -ad9371-phy.in_voltage1_hardwaregain = 15.000000 dB -ad9371-phy.in_voltage1_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage1_gain_control_mode = manual -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_altvoltage0_RX_LO_frequency = 2560000000 -ad9371-phy.calibrate_rx_qec_en = 0 -ad9371-phy.calibrate_tx_lol_en = 0 -ad9371-phy.calibrate_vswr_en = 0 -ad9371-phy.calibrate_tx_qec_en = 0 -ad9371-phy.calibrate_clgc_en = 0 -ad9371-phy.ensm_mode = radio_on -ad9371-phy.calibrate_tx_lol_ext_en = 0 -ad9371-phy.calibrate_dpd_en = 0 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_scale = 0.501160 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_frequency = 1999718 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_frequency = 1000327 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_frequency = 7999809 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_scale = 0.251160 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_frequency = 7999809 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_scale = 0.251160 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_frequency = 19998117 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_frequency = 1000327 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_scale = 0.501160 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_frequency = 1999718 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_frequency = 19998117 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_scale = 0.000000 -load_myk_profile_file = ./targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile20MHz.txt -dds_mode_tx1 = 1 -dds_mode_tx2 = 1 -dac_buf_filename = /usr/local/lib/osc/waveforms/LTE20.mat -tx_channel_0 = 1 -tx_channel_1 = 1 -tx_channel_2 = 0 -tx_channel_3 = 0 -global_settings_show = 1 -tx_show = 1 -rx_show = 1 -obs_show = 1 -fpga_show = 1 - -[ADRV9371_ZC706] -# NO_DEBUG=0; DEBUG=1 -debug_mode = 0 -# 20MHz 40MHz 80MHz=1; 10MHz=2; 5MHz=4 -interpolation_decimation_factor = 1 -# is taken into account only if "ad9371-phy.in_voltage0_gain_control_mode = manual" -rx_gain_offset = 46 diff --git a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile1-osc.ini b/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile1-osc.ini deleted file mode 100644 index 4282cfffdd..0000000000 --- a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile1-osc.ini +++ /dev/null @@ -1,85 +0,0 @@ -[AD9371] -ad9371-phy.in_voltage2_rf_port_select = OFF -ad9371-phy.in_voltage2_hardwaregain = -156.000000 dB -ad9371-phy.in_voltage2_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_voltage0_lo_leakage_tracking_en = 0 -ad9371-phy.out_voltage0_hardwaregain = -10.000000 dB -ad9371-phy.out_voltage0_quadrature_tracking_en = 1 -ad9371-phy.out_voltage1_hardwaregain = -10.000000 dB -ad9371-phy.out_voltage1_lo_leakage_tracking_en = 0 -ad9371-phy.out_voltage1_quadrature_tracking_en = 1 -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_altvoltage1_TX_LO_frequency = 2685000000 -ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = 2565000000 -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage0_gain_control_mode = automatic -ad9371-phy.in_voltage0_quadrature_tracking_en = 1 -ad9371-phy.in_voltage0_hardwaregain = 30.000000 dB -ad9371-phy.in_voltage0_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage1_quadrature_tracking_en = 1 -ad9371-phy.in_voltage1_hardwaregain = 30.000000 dB -ad9371-phy.in_voltage1_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage1_gain_control_mode = automatic -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_altvoltage0_RX_LO_frequency = 2565000000 -ad9371-phy.calibrate_rx_qec_en = 0 -ad9371-phy.calibrate_tx_lol_en = 0 -ad9371-phy.calibrate_vswr_en = 0 -ad9371-phy.calibrate_tx_qec_en = 0 -ad9371-phy.calibrate_clgc_en = 0 -ad9371-phy.ensm_mode = radio_on -ad9371-phy.calibrate_tx_lol_ext_en = 0 -ad9371-phy.calibrate_dpd_en = 0 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_scale = 0.501160 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_frequency = 1999718 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_frequency = 1000327 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_frequency = 7999809 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_scale = 0.251160 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_frequency = 7999809 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_scale = 0.251160 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_frequency = 19998117 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_frequency = 1000327 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_scale = 0.501160 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_frequency = 1999718 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_frequency = 19998117 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_scale = 0.000000 -load_myk_profile_file = /targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile_rx30_Tx60_syr.txt -dds_mode_tx1 = 1 -dds_mode_tx2 = 1 -dac_buf_filename = /usr/local/lib/osc/waveforms/LTE20.mat -tx_channel_0 = 1 -tx_channel_1 = 1 -tx_channel_2 = 0 -tx_channel_3 = 0 -global_settings_show = 1 -tx_show = 1 -rx_show = 1 -obs_show = 1 -fpga_show = 1 - -[ADRV9371_ZC706] -debug_mode = 0 -interpolation_decimation_factor = 2 diff --git a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile20MHz.txt b/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile20MHz.txt deleted file mode 100644 index ac20ab2663..0000000000 --- a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile20MHz.txt +++ /dev/null @@ -1,285 +0,0 @@ - - - - - - - - - - - - - - - - - - - - 0 - 2 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34 - 278 - 425 - -5 - 0 - - - diff --git a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profileNR80MHz.txt b/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profileNR80MHz.txt deleted file mode 100644 index 3db078ce38..0000000000 --- a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profileNR80MHz.txt +++ /dev/null @@ -1,197 +0,0 @@ - - - - - - - - - - - - - - - - - - - - 1 - -1 - -1 - 3 - -2 - -11 - 17 - 33 - -64 - -83 - 175 - 193 - -399 - -414 - 801 - 831 - -1477 - -1589 - 2632 - 3042 - -5102 - -7664 - 9765 - 32678 - 32678 - 9765 - -7664 - -5102 - 3042 - 2632 - -1589 - -1477 - 831 - 801 - -414 - -399 - 193 - 175 - -83 - -64 - 33 - 17 - -11 - -2 - 3 - -1 - -1 - 1 - - - - 563 - 372 - 201 - 98 - 1280 - 328 - 1550 - 171 - 1317 - 66 - 804 - 33 - 48 - 39 - 23 - 189 - - - - - - - - - - - - - - - -62 - 147 - -188 - 22 - 500 - -1359 - 2233 - -2368 - 656 - 2432 - -9845 - 24506 - 24506 - -9845 - 2432 - 656 - -2368 - 2233 - -1359 - 500 - 22 - -188 - 147 - -62 - - - - 491 - 375 - 201 - 98 - 1280 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- -2322 - -5354 - 3885 - 17211 - 17211 - 3885 - -5354 - -2322 - 2957 - 1742 - -1615 - -1154 - 900 - 730 - -499 - -429 - 240 - 242 - -122 - -118 - - - diff --git a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.NR40.adrv9371-zc706.ini b/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.NR40.adrv9371-zc706.ini deleted file mode 100644 index 8dfe8d6589..0000000000 --- a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.NR40.adrv9371-zc706.ini +++ /dev/null @@ -1,89 +0,0 @@ -[AD9371] -ad9371-phy.in_voltage2_rf_port_select = OFF -ad9371-phy.in_voltage2_hardwaregain = -156.000000 dB -ad9371-phy.in_voltage2_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_voltage0_lo_leakage_tracking_en = 0 -ad9371-phy.out_voltage0_hardwaregain = 0.000000 dB -ad9371-phy.out_voltage0_quadrature_tracking_en = 1 -ad9371-phy.out_voltage1_hardwaregain = 0.000000 dB -ad9371-phy.out_voltage1_lo_leakage_tracking_en = 0 -ad9371-phy.out_voltage1_quadrature_tracking_en = 1 -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_altvoltage1_TX_LO_frequency = 2560000000 -ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = 2680000000 -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage0_gain_control_mode = manual -ad9371-phy.in_voltage0_quadrature_tracking_en = 1 -ad9371-phy.in_voltage0_hardwaregain = 30.000000 dB -ad9371-phy.in_voltage0_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage1_quadrature_tracking_en = 1 -ad9371-phy.in_voltage1_hardwaregain = 30.000000 dB -ad9371-phy.in_voltage1_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage1_gain_control_mode = manual -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_altvoltage0_RX_LO_frequency = 2680000000 -ad9371-phy.calibrate_rx_qec_en = 0 -ad9371-phy.calibrate_tx_lol_en = 0 -ad9371-phy.calibrate_vswr_en = 0 -ad9371-phy.calibrate_tx_qec_en = 0 -ad9371-phy.calibrate_clgc_en = 0 -ad9371-phy.ensm_mode = radio_on -ad9371-phy.calibrate_tx_lol_ext_en = 0 -ad9371-phy.calibrate_dpd_en = 0 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_scale = 0.501160 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_frequency = 1999718 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_frequency = 1000327 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_frequency = 7999809 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_scale = 0.251160 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_frequency = 7999809 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_scale = 0.251160 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_frequency = 19998117 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_frequency = 1000327 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_scale = 0.501160 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_frequency = 1999718 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_frequency = 19998117 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_scale = 0.000000 -load_myk_profile_file = /targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profileNR40MHz.txt -dds_mode_tx1 = 1 -dds_mode_tx2 = 1 -dac_buf_filename = /usr/local/lib/osc/waveforms/LTE20.mat -tx_channel_0 = 1 -tx_channel_1 = 1 -tx_channel_2 = 0 -tx_channel_3 = 0 -global_settings_show = 1 -tx_show = 1 -rx_show = 1 -obs_show = 1 -fpga_show = 1 - -[ADRV9371_ZC706] -# NO_DEBUG=0; DEBUG=1 -debug_mode = 0 -# 20MHz 40MHz 80MHz=1; 10MHz=2; 5MHz=4 -interpolation_decimation_factor = 1 -# is taken into account only if "ad9371-phy.in_voltage0_gain_control_mode = manual" -rx_gain_offset = 43 diff --git a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.NR80.adrv9371-zc706.ini b/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.NR80.adrv9371-zc706.ini deleted file mode 100644 index 007499c8eb..0000000000 --- a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.NR80.adrv9371-zc706.ini +++ /dev/null @@ -1,89 +0,0 @@ -[AD9371] -ad9371-phy.in_voltage2_rf_port_select = OFF -ad9371-phy.in_voltage2_hardwaregain = -156.000000 dB -ad9371-phy.in_voltage2_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_voltage0_lo_leakage_tracking_en = 0 -ad9371-phy.out_voltage0_hardwaregain = 0.000000 dB -ad9371-phy.out_voltage0_quadrature_tracking_en = 1 -ad9371-phy.out_voltage1_hardwaregain = 0.000000 dB -ad9371-phy.out_voltage1_lo_leakage_tracking_en = 0 -ad9371-phy.out_voltage1_quadrature_tracking_en = 1 -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_altvoltage1_TX_LO_frequency = 2560000000 -ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = 2680000000 -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage0_gain_control_mode = manual -ad9371-phy.in_voltage0_quadrature_tracking_en = 1 -ad9371-phy.in_voltage0_hardwaregain = 30.000000 dB -ad9371-phy.in_voltage0_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage1_quadrature_tracking_en = 1 -ad9371-phy.in_voltage1_hardwaregain = 30.000000 dB -ad9371-phy.in_voltage1_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage1_gain_control_mode = manual -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_altvoltage0_RX_LO_frequency = 2680000000 -ad9371-phy.calibrate_rx_qec_en = 0 -ad9371-phy.calibrate_tx_lol_en = 0 -ad9371-phy.calibrate_vswr_en = 0 -ad9371-phy.calibrate_tx_qec_en = 0 -ad9371-phy.calibrate_clgc_en = 0 -ad9371-phy.ensm_mode = radio_on -ad9371-phy.calibrate_tx_lol_ext_en = 0 -ad9371-phy.calibrate_dpd_en = 0 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_scale = 0.501160 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_frequency = 1999718 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_frequency = 1000327 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_frequency = 7999809 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_scale = 0.251160 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_frequency = 7999809 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_scale = 0.251160 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_frequency = 19998117 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_frequency = 1000327 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_scale = 0.501160 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_frequency = 1999718 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_frequency = 19998117 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_scale = 0.000000 -load_myk_profile_file = /targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profileNR80MHz.txt -dds_mode_tx1 = 1 -dds_mode_tx2 = 1 -dac_buf_filename = /usr/local/lib/osc/waveforms/LTE20.mat -tx_channel_0 = 1 -tx_channel_1 = 1 -tx_channel_2 = 0 -tx_channel_3 = 0 -global_settings_show = 1 -tx_show = 1 -rx_show = 1 -obs_show = 1 -fpga_show = 1 - -[ADRV9371_ZC706] -# NO_DEBUG=0; DEBUG=1 -debug_mode = 0 -# 20MHz 40MHz 80MHz=1; 10MHz=2; 5MHz=4 -interpolation_decimation_factor = 1 -# is taken into account only if "ad9371-phy.in_voltage0_gain_control_mode = manual" -rx_gain_offset = 53 diff --git a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.adrv9371-zc706.ini b/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.adrv9371-zc706.ini deleted file mode 100644 index 34a98d4a77..0000000000 --- a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.adrv9371-zc706.ini +++ /dev/null @@ -1,89 +0,0 @@ -[AD9371] -ad9371-phy.in_voltage2_rf_port_select = OFF -ad9371-phy.in_voltage2_hardwaregain = -156.000000 dB -ad9371-phy.in_voltage2_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_voltage0_lo_leakage_tracking_en = 0 -ad9371-phy.out_voltage0_hardwaregain = 0.000000 dB -ad9371-phy.out_voltage0_quadrature_tracking_en = 1 -ad9371-phy.out_voltage1_hardwaregain = 0.000000 dB -ad9371-phy.out_voltage1_lo_leakage_tracking_en = 0 -ad9371-phy.out_voltage1_quadrature_tracking_en = 1 -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_altvoltage1_TX_LO_frequency = 2560000000 -ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = 2680000000 -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage0_gain_control_mode = manual -ad9371-phy.in_voltage0_quadrature_tracking_en = 1 -ad9371-phy.in_voltage0_hardwaregain = 25.000000 dB -ad9371-phy.in_voltage0_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage1_quadrature_tracking_en = 1 -ad9371-phy.in_voltage1_hardwaregain = 25.000000 dB -ad9371-phy.in_voltage1_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage1_gain_control_mode = manual -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_altvoltage0_RX_LO_frequency = 2680000000 -ad9371-phy.calibrate_rx_qec_en = 0 -ad9371-phy.calibrate_tx_lol_en = 0 -ad9371-phy.calibrate_vswr_en = 0 -ad9371-phy.calibrate_tx_qec_en = 0 -ad9371-phy.calibrate_clgc_en = 0 -ad9371-phy.ensm_mode = radio_on -ad9371-phy.calibrate_tx_lol_ext_en = 0 -ad9371-phy.calibrate_dpd_en = 0 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_scale = 0.501160 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_frequency = 1999718 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_frequency = 1000327 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_frequency = 7999809 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_scale = 0.251160 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_frequency = 7999809 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_scale = 0.251160 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_frequency = 19998117 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_frequency = 1000327 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_scale = 0.501160 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_frequency = 1999718 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_frequency = 19998117 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_scale = 0.000000 -load_myk_profile_file = /targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile20MHz.txt -dds_mode_tx1 = 1 -dds_mode_tx2 = 1 -dac_buf_filename = /usr/local/lib/osc/waveforms/LTE20.mat -tx_channel_0 = 1 -tx_channel_1 = 1 -tx_channel_2 = 0 -tx_channel_3 = 0 -global_settings_show = 1 -tx_show = 1 -rx_show = 1 -obs_show = 1 -fpga_show = 1 - -[ADRV9371_ZC706] -# NO_DEBUG=0; DEBUG=1 -debug_mode = 0 -# 20MHz 40MHz 80MHz=1; 10MHz=2; 5MHz=4 -interpolation_decimation_factor = 1 -# is taken into account only if "ad9371-phy.in_voltage0_gain_control_mode = manual" -rx_gain_offset = 69 diff --git a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.adrv9371-zc706_HWgain15dB.ini b/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.adrv9371-zc706_HWgain15dB.ini deleted file mode 100644 index e12de4edbe..0000000000 --- a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.adrv9371-zc706_HWgain15dB.ini +++ /dev/null @@ -1,89 +0,0 @@ -[AD9371] -ad9371-phy.in_voltage2_rf_port_select = OFF -ad9371-phy.in_voltage2_hardwaregain = -156.000000 dB -ad9371-phy.in_voltage2_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_voltage0_lo_leakage_tracking_en = 0 -ad9371-phy.out_voltage0_hardwaregain = 0.000000 dB -ad9371-phy.out_voltage0_quadrature_tracking_en = 1 -ad9371-phy.out_voltage1_hardwaregain = 0.000000 dB -ad9371-phy.out_voltage1_lo_leakage_tracking_en = 0 -ad9371-phy.out_voltage1_quadrature_tracking_en = 1 -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_altvoltage1_TX_LO_frequency = 2560000000 -ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = 2680000000 -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage0_gain_control_mode = manual -ad9371-phy.in_voltage0_quadrature_tracking_en = 1 -ad9371-phy.in_voltage0_hardwaregain = 15.000000 dB -ad9371-phy.in_voltage0_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage1_quadrature_tracking_en = 1 -ad9371-phy.in_voltage1_hardwaregain = 15.000000 dB -ad9371-phy.in_voltage1_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage1_gain_control_mode = manual -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_altvoltage0_RX_LO_frequency = 2680000000 -ad9371-phy.calibrate_rx_qec_en = 0 -ad9371-phy.calibrate_tx_lol_en = 0 -ad9371-phy.calibrate_vswr_en = 0 -ad9371-phy.calibrate_tx_qec_en = 0 -ad9371-phy.calibrate_clgc_en = 0 -ad9371-phy.ensm_mode = radio_on -ad9371-phy.calibrate_tx_lol_ext_en = 0 -ad9371-phy.calibrate_dpd_en = 0 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_scale = 0.501160 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_frequency = 1999718 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_frequency = 1000327 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_frequency = 7999809 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_scale = 0.251160 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_frequency = 7999809 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_scale = 0.251160 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_frequency = 19998117 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_frequency = 1000327 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_scale = 0.501160 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_frequency = 1999718 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_frequency = 19998117 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_scale = 0.000000 -load_myk_profile_file = /targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile20MHz.txt -dds_mode_tx1 = 1 -dds_mode_tx2 = 1 -dac_buf_filename = /usr/local/lib/osc/waveforms/LTE20.mat -tx_channel_0 = 1 -tx_channel_1 = 1 -tx_channel_2 = 0 -tx_channel_3 = 0 -global_settings_show = 1 -tx_show = 1 -rx_show = 1 -obs_show = 1 -fpga_show = 1 - -[ADRV9371_ZC706] -# NO_DEBUG=0; DEBUG=1 -debug_mode = 0 -# 20MHz 40MHz 80MHz=1; 10MHz=2; 5MHz=4 -interpolation_decimation_factor = 1 -# is taken into account only if "ad9371-phy.in_voltage0_gain_control_mode = manual" -rx_gain_offset = 30 diff --git a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB25.adrv9371-zc706.ini b/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB25.adrv9371-zc706.ini deleted file mode 100644 index bcdbf7716a..0000000000 --- a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB25.adrv9371-zc706.ini +++ /dev/null @@ -1,85 +0,0 @@ -[AD9371] -ad9371-phy.in_voltage2_rf_port_select = OFF -ad9371-phy.in_voltage2_hardwaregain = -156.000000 dB -ad9371-phy.in_voltage2_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_voltage0_lo_leakage_tracking_en = 0 -ad9371-phy.out_voltage0_hardwaregain = -10.000000 dB -ad9371-phy.out_voltage0_quadrature_tracking_en = 1 -ad9371-phy.out_voltage1_hardwaregain = -10.000000 dB -ad9371-phy.out_voltage1_lo_leakage_tracking_en = 0 -ad9371-phy.out_voltage1_quadrature_tracking_en = 1 -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_altvoltage1_TX_LO_frequency = 2535000000 -ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = 2655000000 -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage0_gain_control_mode = automatic -ad9371-phy.in_voltage0_quadrature_tracking_en = 1 -ad9371-phy.in_voltage0_hardwaregain = 30.000000 dB -ad9371-phy.in_voltage0_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage1_quadrature_tracking_en = 1 -ad9371-phy.in_voltage1_hardwaregain = 30.000000 dB -ad9371-phy.in_voltage1_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage1_gain_control_mode = automatic -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_altvoltage0_RX_LO_frequency = 2655000000 -ad9371-phy.calibrate_rx_qec_en = 0 -ad9371-phy.calibrate_tx_lol_en = 0 -ad9371-phy.calibrate_vswr_en = 0 -ad9371-phy.calibrate_tx_qec_en = 0 -ad9371-phy.calibrate_clgc_en = 0 -ad9371-phy.ensm_mode = radio_on -ad9371-phy.calibrate_tx_lol_ext_en = 0 -ad9371-phy.calibrate_dpd_en = 0 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_scale = 0.501160 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_frequency = 1999718 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_frequency = 1000327 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_frequency = 7999809 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_scale = 0.251160 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_frequency = 7999809 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_scale = 0.251160 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_frequency = 19998117 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_frequency = 1000327 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_scale = 0.501160 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_frequency = 1999718 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_frequency = 19998117 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_scale = 0.000000 -load_myk_profile_file = /targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile_rx30_Tx60_syr.txt -dds_mode_tx1 = 1 -dds_mode_tx2 = 1 -dac_buf_filename = /usr/local/lib/osc/waveforms/LTE20.mat -tx_channel_0 = 1 -tx_channel_1 = 1 -tx_channel_2 = 0 -tx_channel_3 = 0 -global_settings_show = 1 -tx_show = 1 -rx_show = 1 -obs_show = 1 -fpga_show = 1 - -[ADRV9371_ZC706] -debug_mode = 0 -interpolation_decimation_factor = 4 diff --git a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB50.adrv9371-zc706.ini b/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB50.adrv9371-zc706.ini deleted file mode 100644 index a23a765503..0000000000 --- a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB50.adrv9371-zc706.ini +++ /dev/null @@ -1,85 +0,0 @@ -[AD9371] -ad9371-phy.in_voltage2_rf_port_select = OFF -ad9371-phy.in_voltage2_hardwaregain = -156.000000 dB -ad9371-phy.in_voltage2_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_voltage0_lo_leakage_tracking_en = 0 -ad9371-phy.out_voltage0_hardwaregain = -10.000000 dB -ad9371-phy.out_voltage0_quadrature_tracking_en = 1 -ad9371-phy.out_voltage1_hardwaregain = -10.000000 dB -ad9371-phy.out_voltage1_lo_leakage_tracking_en = 0 -ad9371-phy.out_voltage1_quadrature_tracking_en = 1 -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_altvoltage1_TX_LO_frequency = 2535000000 -ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = 2655000000 -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage0_gain_control_mode = automatic -ad9371-phy.in_voltage0_quadrature_tracking_en = 1 -ad9371-phy.in_voltage0_hardwaregain = 30.000000 dB -ad9371-phy.in_voltage0_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.in_voltage1_quadrature_tracking_en = 1 -ad9371-phy.in_voltage1_hardwaregain = 30.000000 dB -ad9371-phy.in_voltage1_temp_comp_gain = 0.00 dB -ad9371-phy.in_voltage1_gain_control_mode = automatic -ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO -ad9371-phy.out_altvoltage0_RX_LO_frequency = 2655000000 -ad9371-phy.calibrate_rx_qec_en = 0 -ad9371-phy.calibrate_tx_lol_en = 0 -ad9371-phy.calibrate_vswr_en = 0 -ad9371-phy.calibrate_tx_qec_en = 0 -ad9371-phy.calibrate_clgc_en = 0 -ad9371-phy.ensm_mode = radio_on -ad9371-phy.calibrate_tx_lol_ext_en = 0 -ad9371-phy.calibrate_dpd_en = 0 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_scale = 0.501160 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_frequency = 1999718 -axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_frequency = 1000327 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_frequency = 7999809 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_scale = 0.251160 -axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_frequency = 7999809 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_scale = 0.251160 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_frequency = 19998117 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_scale = 0.000000 -axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_frequency = 1000327 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_phase = 0 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_scale = 0.501160 -axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_frequency = 1999718 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_frequency = 19998117 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_raw = 1 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_phase = 90000 -axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_scale = 0.000000 -load_myk_profile_file = /targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile_rx30_Tx60_syr.txt -dds_mode_tx1 = 1 -dds_mode_tx2 = 1 -dac_buf_filename = /usr/local/lib/osc/waveforms/LTE20.mat -tx_channel_0 = 1 -tx_channel_1 = 1 -tx_channel_2 = 0 -tx_channel_3 = 0 -global_settings_show = 1 -tx_show = 1 -rx_show = 1 -obs_show = 1 -fpga_show = 1 - -[ADRV9371_ZC706] -debug_mode = 0 -interpolation_decimation_factor = 2 diff --git a/targets/ARCH/ADRV9371_ZC706/readme.txt b/targets/ARCH/ADRV9371_ZC706/readme.txt deleted file mode 100644 index 05b3bc1b7d..0000000000 --- a/targets/ARCH/ADRV9371_ZC706/readme.txt +++ /dev/null @@ -1,17 +0,0 @@ -Common command line: --------------------- -cd /openairinterface5g/ -source oaienv - -HWLAT application: ------------------- -./cmake_targets/build_oai -c -C -w ADRV9371_ZC706 --HWLAT -./cmake_targets/lte-hwlat/build/lte-hwlat - -LTE-SOFTMODEM application: --------------------------- -./cmake_targets/build_oai -c --eNB --UE --noS1 -w ADRV9371_ZC706 -sudo su -source oaienv -source ./targets/bin/init_nas_nos1 UE -./cmake_targets/lte_noS1_build_oai/build/lte-softmodem-nos1 -U -C 2680000000 -r100 --ue-scan-carrier --ue-txgain 0 --ue-rxgain 5 -S -A 6 --ue-max-power -25 --phy-test -g 7 --rf-config-file ./targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.adrv9371-zc706_HWgain15dB.ini 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"gNB-Eurecom-5GNRBox"); +# Asn1_verbosity, choice in: none, info, annoying +Asn1_verbosity = "none"; + +gNBs = +( + { + ////////// Identification parameters: + gNB_ID = 0xe00; + + cell_type = "CELL_MACRO_GNB"; + + gNB_name = "gNB-Eurecom-5GNRBox"; + + // Tracking area code, 0x0000 and 0xfffe are reserved values + tracking_area_code = 1; + + plmn_list = ({mcc = 208; mnc = 93; mnc_length = 2;}); + + tr_s_preference = "local_mac" + + ////////// Physical parameters: + + component_carriers = ( + { + node_function = "3GPP_gNODEB"; + node_timing = "synch_to_ext_device"; + node_synch_ref = 0; + frame_type = "FDD"; + DL_prefix_type = "NORMAL"; + UL_prefix_type = "NORMAL"; + eutra_band = 22; + downlink_frequency = 3510000000L; + uplink_frequency_offset = -120000000; + Nid_cell = 0; + N_RB_DL = 106; + nb_antenna_ports = 1; + nb_antennas_tx = 1; + nb_antennas_rx = 1; + tx_gain = 90; + rx_gain = 125; + MIB_subCarrierSpacingCommon = 30; + MIB_ssb_SubcarrierOffset = 0; + MIB_dmrs_TypeA_Position = 2; + pdcch_ConfigSIB1 = 0; + SIB1_frequencyOffsetSSB = "khz5"; + SIB1_ssb_PeriodicityServingCell = 5; + SIB1_ss_PBCH_BlockPower = -60; + absoluteFrequencySSB = 0; + DL_FreqBandIndicatorNR = 15; + DL_absoluteFrequencyPointA = 15; + DL_offsetToCarrier = 15; + DL_SCS_SubcarrierSpacing = "kHz30"; + DL_SCS_SpecificCarrier_k0 = 0; + DL_carrierBandwidth = 15; + DL_locationAndBandwidth = 15; + DL_BWP_SubcarrierSpacing = "kHz30"; + DL_BWP_prefix_type = "NORMAL"; + UL_FreqBandIndicatorNR = 15; + UL_absoluteFrequencyPointA = 13; + UL_additionalSpectrumEmission = 3; + UL_p_Max = -1; + UL_frequencyShift7p5khz = "TRUE"; + UL_offsetToCarrier = 10; + UL_SCS_SubcarrierSpacing = "kHz30"; + UL_SCS_SpecificCarrier_k0 = 0; + UL_carrierBandwidth = 15; + UL_locationAndBandwidth = 15; + UL_BWP_SubcarrierSpacing = "kHz30"; + UL_BWP_prefix_type = "NORMAL"; + UL_timeAlignmentTimerCommon = "infinity"; + ServingCellConfigCommon_n_TimingAdvanceOffset = "n0" + ServingCellConfigCommon_ssb_PositionsInBurst_PR = "shortBitmap"; + ServingCellConfigCommon_ssb_periodicityServingCell = 10; + ServingCellConfigCommon_dmrs_TypeA_Position = 2; + NIA_SubcarrierSpacing = "kHz15"; + ServingCellConfigCommon_ss_PBCH_BlockPower = -60; + referenceSubcarrierSpacing = "kHz15"; + dl_UL_TransmissionPeriodicity = "ms0p5"; + nrofDownlinkSlots = 10; + nrofDownlinkSymbols = 10; + nrofUplinkSlots = 10; + nrofUplinkSymbols = 10; + rach_totalNumberOfRA_Preambles = 63; + rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_choice = "oneEighth"; + rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneEighth = 4; + rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneFourth = 8; + rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_oneHalf = 16; + rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_one = 24; + rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_two = 32; + rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_four = 8; + rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_eight = 4; + rach_ssb_perRACH_OccasionAndCB_PreamblesPerSSB_sixteen = 2; + rach_groupBconfigured = "ENABLE"; + rach_ra_Msg3SizeGroupA = 56; + rach_messagePowerOffsetGroupB = "dB0"; + rach_numberOfRA_PreamblesGroupA = 32; + rach_ra_ContentionResolutionTimer = 8; + rsrp_ThresholdSSB = 64; + rsrp_ThresholdSSB_SUL = 64; + prach_RootSequenceIndex_choice = "l839"; + prach_RootSequenceIndex_l839 = 0; + prach_RootSequenceIndex_l139 = 0; + prach_msg1_SubcarrierSpacing = "kHz30"; + restrictedSetConfig = "unrestrictedSet"; + msg3_transformPrecoding = "ENABLE"; + prach_ConfigurationIndex = 10; + prach_msg1_FDM = "one"; + prach_msg1_FrequencyStart = 10; + zeroCorrelationZoneConfig = 10; + preambleReceivedTargetPower = -150; + preambleTransMax = 6; + powerRampingStep = "dB0"; + ra_ResponseWindow = 8; + groupHoppingEnabledTransformPrecoding = "ENABLE"; + msg3_DeltaPreamble = 0; + p0_NominalWithGrant = 0; + PUSCH_TimeDomainResourceAllocation_k2 = 0; + PUSCH_TimeDomainResourceAllocation_mappingType = "typeA"; + PUSCH_TimeDomainResourceAllocation_startSymbolAndLength = 0; + pucch_ResourceCommon = 0; + pucch_GroupHopping = "neither"; + hoppingId = 0; + p0_nominal = -30; + PDSCH_TimeDomainResourceAllocation_k0 = 2; + PDSCH_TimeDomainResourceAllocation_mappingType = "typeA"; + PDSCH_TimeDomainResourceAllocation_startSymbolAndLength = 0; + rateMatchPatternId = 0; + RateMatchPattern_patternType = "bitmaps"; + symbolsInResourceBlock = "oneSlot"; + periodicityAndPattern = 2; + RateMatchPattern_controlResourceSet = 5; + RateMatchPattern_subcarrierSpacing = "kHz30"; + RateMatchPattern_mode = "dynamic"; + controlResourceSetZero = 0; + searchSpaceZero = 0; + searchSpaceSIB1 = 10; + searchSpaceOtherSystemInformation = 10; + pagingSearchSpace = 10; + ra_SearchSpace = 10; + PDCCH_common_controlResourceSetId = 5; + PDCCH_common_ControlResourceSet_duration = 2; + PDCCH_cce_REG_MappingType = "nonInterleaved"; + PDCCH_reg_BundleSize = 3; + PDCCH_interleaverSize = 3; + PDCCH_shiftIndex = 10; + PDCCH_precoderGranularity = "sameAsREG-bundle"; + PDCCH_TCI_StateId = 32; + tci_PresentInDCI = "ENABLE"; + PDCCH_DMRS_ScramblingID = 0; + SearchSpaceId = 10; + commonSearchSpaces_controlResourceSetId = 5; + SearchSpace_monitoringSlotPeriodicityAndOffset_choice = "sl1"; + SearchSpace_monitoringSlotPeriodicityAndOffset_value = 0; + SearchSpace_duration = 2; + SearchSpace_nrofCandidates_aggregationLevel1 = 0; + SearchSpace_nrofCandidates_aggregationLevel2 = 0; + SearchSpace_nrofCandidates_aggregationLevel4 = 0; + SearchSpace_nrofCandidates_aggregationLevel8 = 0; + SearchSpace_nrofCandidates_aggregationLevel16 = 0; + SearchSpace_searchSpaceType = "common"; + Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel1 = 1; + Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel2 = 1; + Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel4 = 1; + Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel8 = 1; + Common_dci_Format2_0_nrofCandidates_SFI_aggregationLevel16 = 1; + Common_dci_Format2_3_monitoringPeriodicity = 1; + Common_dci_Format2_3_nrofPDCCH_Candidates = 1; + ue_Specific__dci_Formats = "formats0-0-And-1-0"; + RateMatchPatternLTE_CRS_carrierFreqDL = 6; + RateMatchPatternLTE_CRS_carrierBandwidthDL = 6; + RateMatchPatternLTE_CRS_nrofCRS_Ports = 1; + RateMatchPatternLTE_CRS_v_Shift = 0; + RateMatchPatternLTE_CRS_radioframeAllocationPeriod = 1; + RateMatchPatternLTE_CRS_radioframeAllocationOffset = 0; + RateMatchPatternLTE_CRS_subframeAllocation_choice = "oneFrame"; + } + ); + + + srb1_parameters : + { + # timer_poll_retransmit = (ms) [5, 10, 15, 20,... 250, 300, 350, ... 500] + timer_poll_retransmit = 80; + + # timer_reordering = (ms) [0,5, ... 100, 110, 120, ... ,200] + timer_reordering = 35; + + # timer_reordering = (ms) [0,5, ... 250, 300, 350, ... ,500] + timer_status_prohibit = 0; + + # poll_pdu = [4, 8, 16, 32 , 64, 128, 256, infinity(>10000)] + poll_pdu = 4; + + # poll_byte = (kB) [25,50,75,100,125,250,375,500,750,1000,1250,1500,2000,3000,infinity(>10000)] + poll_byte = 99999; + + # max_retx_threshold = [1, 2, 3, 4 , 6, 8, 16, 32] + max_retx_threshold = 4; + } + + # ------- SCTP definitions + SCTP : + { + # Number of streams to use in input/output + SCTP_INSTREAMS = 2; + SCTP_OUTSTREAMS = 2; + }; + + + ////////// MME parameters: + mme_ip_address = ( { ipv4 = "192.168.12.26"; + ipv6 = "192:168:30::17"; + active = "yes"; + preference = "ipv4"; + } + ); + + NETWORK_INTERFACES : + { + + GNB_INTERFACE_NAME_FOR_S1_MME = "eth0"; + GNB_IPV4_ADDRESS_FOR_S1_MME = "192.168.12.111/24"; + GNB_INTERFACE_NAME_FOR_S1U = "eth0"; + GNB_IPV4_ADDRESS_FOR_S1U = "192.168.12.111/24"; + GNB_PORT_FOR_S1U = 2152; # Spec 2152 + }; + } +); + +MACRLCs = ( + { + num_cc = 1; + tr_s_preference = "local_L1"; + tr_n_preference = "local_RRC"; + } +); + +L1s = ( + { + num_cc = 1; + tr_n_preference = "local_mac"; + } +); + +RUs = ( + { + local_rf = "yes" + nb_tx = 1 + nb_rx = 1 + att_tx = 0 + att_rx = 0; + bands = [7]; + max_pdschReferenceSignalPower = -27; + max_rxgain = 114; + eNB_instances = [0]; + sdr_addrs = "addr=192.168.10.2,second_addr=192.168.20.2,mgmt_addr=192.168.100.8"; + + } +); + +NETWORK_CONTROLLER : +{ + FLEXRAN_ENABLED = "no"; + FLEXRAN_INTERFACE_NAME = "lo"; + FLEXRAN_IPV4_ADDRESS = "127.0.0.1"; + FLEXRAN_PORT = 2210; + FLEXRAN_CACHE = "/mnt/oai_agent_cache"; + FLEXRAN_AWAIT_RECONF = "no"; +}; + + log_config : + { + global_log_level ="info"; + global_log_verbosity ="medium"; + hw_log_level ="info"; + hw_log_verbosity ="medium"; + phy_log_level ="info"; + phy_log_verbosity ="medium"; + mac_log_level ="info"; + mac_log_verbosity ="high"; + rlc_log_level ="info"; + rlc_log_verbosity ="medium"; + pdcp_log_level ="info"; + pdcp_log_verbosity ="medium"; + rrc_log_level ="info"; + rrc_log_verbosity ="medium"; + }; + diff --git a/targets/RT/USER/lte-hwlat.c b/targets/RT/USER/lte-hwlat.c index 9f5a3306aa..3fb4b0e99e 100755 --- a/targets/RT/USER/lte-hwlat.c +++ b/targets/RT/USER/lte-hwlat.c @@ -57,9 +57,9 @@ #include "LAYER2/MAC/extern.h" #include "LAYER2/MAC/proto.h" -#define RIFFA_CHANNEL_TESTER 0 -#define RIFFA_CHANNEL_TESTER2 0 -#define RIFFA_CHANNEL_DATA1 1 +#define SYRIQ_CHANNEL_TESTER 0 +#define SYRIQ_CHANNEL_TESTER2 0 +#define SYRIQ_CHANNEL_DATA1 1 volatile int oai_exit = 0; @@ -346,7 +346,7 @@ int main(void) int c = 0; int numIter = 0; int fpga_loop = 0; -#if RIFFA_CHANNEL_DATA1 +#if SYRIQ_CHANNEL_DATA1 uint64_t first_ts = 0; uint8_t is_first_ts = 0; uint64_t trx_read_cnt = 0; @@ -383,7 +383,7 @@ int main(void) #endif const char *openair_dir = getenv("OPENAIR_DIR"); - const char *ini_file = "/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.adrv9371-zc706_HWgain15dB.ini"; + const char *ini_file = "/usr/local/etc/syriq/ue.band7.tm1.PRB100.NR20.dat"; int readBlockSize; void* rxp[nb_antennas_rx]; @@ -726,9 +726,9 @@ int main(void) //#endif /* ********** ********** */ -/* RIFFA_CHANNEL_DATA1 */ +/* SYRIQ_CHANNEL_DATA1 */ /* ********** ********** */ -#if RIFFA_CHANNEL_DATA1 +#if SYRIQ_CHANNEL_DATA1 // rf_device.trx_get_stats_func( &rf_device ); @@ -766,12 +766,12 @@ int main(void) // break; // } // } - printf("RIFFA CHANNEL DATA1 done !!!\n"); + printf("SYRIQ CHANNEL DATA1 done !!!\n"); sleep(1); return(0); #endif /* ********** ********** */ -/* RIFFA_CHANNEL_DATA1 */ +/* SYRIQ_CHANNEL_DATA1 */ /* ********** ********** */ @@ -809,9 +809,9 @@ int main(void) if (ret > 0) { /* ********** ********** */ -/* RIFFA_CHANNEL_TESTER */ +/* SYRIQ_CHANNEL_TESTER */ /* ********** ********** */ -#if RIFFA_CHANNEL_TESTER +#if SYRIQ_CHANNEL_TESTER failure = 0; for (i = 0; i < ret; i++) { @@ -843,9 +843,9 @@ int main(void) } #endif /* ********** ********** */ -/* RIFFA_CHANNEL_TESTER2*/ +/* SYRIQ_CHANNEL_TESTER2*/ /* ********** ********** */ -#if RIFFA_CHANNEL_TESTER2 +#if SYRIQ_CHANNEL_TESTER2 // printf("* ret=%d timestamp=%ld (%ld)\n", ret, timestamp, (timestamp%307200)); failure = 0; for (i = 0; i < ret; i++) diff --git a/targets/RT/USER/nr-softmodem.c b/targets/RT/USER/nr-softmodem.c index 481386a7c8..8b5b7f6e28 100644 --- a/targets/RT/USER/nr-softmodem.c +++ b/targets/RT/USER/nr-softmodem.c @@ -164,7 +164,7 @@ double bw = 10.0e6; static int tx_max_power[MAX_NUM_CCs]; /* = {0,0}*/; -char rf_config_file[1024]="./targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/gnb.band7.tm1.PRB100.NR40.adrv9371-zc706_HWgain15dB.ini"; +char rf_config_file[1024]="/usr/local/etc/syriq/ue.band7.tm1.PRB100.NR40.dat"; int chain_offset=0; int phy_test = 0; From bea2318921990e397f290b56a4c49185bef9ae6a Mon Sep 17 00:00:00 2001 From: frobinet Date: Fri, 16 Nov 2018 16:16:51 +0100 Subject: [PATCH 2/3] targets/ARCH/ADRV9371_ZC706/SYRTEM_IQ_QuickStart.readme update --- targets/ARCH/ADRV9371_ZC706/SYRTEM_IQ_QuickStart.readme | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/targets/ARCH/ADRV9371_ZC706/SYRTEM_IQ_QuickStart.readme b/targets/ARCH/ADRV9371_ZC706/SYRTEM_IQ_QuickStart.readme index 46a77ce272..d7f6585a75 100755 --- a/targets/ARCH/ADRV9371_ZC706/SYRTEM_IQ_QuickStart.readme +++ b/targets/ARCH/ADRV9371_ZC706/SYRTEM_IQ_QuickStart.readme @@ -18,7 +18,9 @@ cd eur_oai_develop-nr git clone https://gitlab.eurecom.fr/oai/openairinterface5g.git cd openairinterface5g -git checkout 375-syrtem-adrv9371zc706_update +git checkout 375-syrtem-sdr-platform +or +git checkout develop-nr (after merge request accepted) ./targets/ARCH/ADRV9371_ZC706/SYRTEM_IQ_uninstall_previous_SW.sh -> Reading package lists... Done From 854c61dffaff36deebe816b23fb783268e29b11d Mon Sep 17 00:00:00 2001 From: Agustin Date: Tue, 20 Nov 2018 09:11:56 +0100 Subject: [PATCH 3/3] NR development PUCCH bug fixes --- cmake_targets/CMakeLists.txt | 1 + .../nfapi/public_inc/fapi_nr_ue_interface.h | 86 ++++++++++ openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c | 160 ++++++++++++------ openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h | 4 +- openair1/SCHED_NR_UE/fapi_nr_ue_l1.c | 53 +++++- openair1/SCHED_NR_UE/harq_nr.c | 2 +- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 7 +- openair1/SCHED_NR_UE/pucch_uci_ue_nr.c | 14 +- .../NR_UE_PHY/unit_tests/src/pss_util_test.c | 4 +- .../NR_UE_PHY/unit_tests/src/pucch_uci_test.c | 37 ++-- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 146 ++++++++++++++++ openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c | 76 +++++---- 12 files changed, 477 insertions(+), 113 deletions(-) diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index e40f72d91e..b16eeb15cb 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -1343,6 +1343,7 @@ set(PHY_SRC_UE ${OPENAIR1_DIR}/PHY/TOOLS/time_meas.c ${OPENAIR1_DIR}/PHY/TOOLS/lut.c ${OPENAIR1_DIR}/PHY/INIT/nr_init_ue.c + # ${OPENAIR1_DIR}/SIMULATION/NR_UE_PHY/unit_tests/src/pucch_uci_test.c ${PHY_POLARSRC} ${PHY_LDPCSRC} ) diff --git a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h index c071b6b70c..1396faced8 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h @@ -21,6 +21,7 @@ #include "stddef.h" #include "platform_types.h" #include "fapi_nr_ue_constants.h" +#include "PHY/impl_defs_nr.h" /* typedef unsigned int uint32_t; @@ -150,6 +151,10 @@ typedef struct { typedef struct { uint16_t rnti; uint8_t dci_format; + // n_CCE index of first CCE for PDCCH reception + int n_CCE; + // N_CCE is L, or number of CCEs for DCI + int N_CCE; fapi_nr_dci_pdu_rel15_t dci; } fapi_nr_dci_indication_pdu_t; @@ -232,11 +237,92 @@ typedef struct { uint16_t root_sequence_index; uint16_t rsrp_threshold_ssb; uint16_t rsrp_threshold_sul; + uint16_t prach_freq_offset; } fapi_nr_ul_config_prach_pdu; typedef struct { + pucch_format_nr_t format; /* format 0 1 2 3 4 */ + uint8_t initialCyclicShift; /* x x */ + uint8_t nrofSymbols; /* x x x x x */ + uint8_t startingSymbolIndex; /* x x x x x */ + uint8_t timeDomainOCC; /* x */ + uint8_t nrofPRBs; /* x x */ + uint16_t startingPRB; /* maxNrofPhysicalResourceBlocks = 275 */ + uint8_t occ_length; /* x */ + uint8_t occ_Index; /* x */ + + feature_status_t intraSlotFrequencyHopping; + uint16_t secondHopPRB; + + /* + -- Enabling inter-slot frequency hopping when PUCCH Format 1, 3 or 4 is repeated over multiple slots. + -- The field is not applicable for format 2. + */ + feature_status_t interslotFrequencyHopping; + /* + -- Enabling 2 DMRS symbols per hop of a PUCCH Format 3 or 4 if both hops are more than X symbols when FH is enabled (X=4). + -- Enabling 4 DMRS sybmols for a PUCCH Format 3 or 4 with more than 2X+1 symbols when FH is disabled (X=4). + -- Corresponds to L1 parameter 'PUCCH-F3-F4-additional-DMRS' (see 38.213, section 9.2.1) + -- The field is not applicable for format 1 and 2. + */ + enable_feature_t additionalDMRS; + /* + -- Max coding rate to determine how to feedback UCI on PUCCH for format 2, 3 or 4 + -- Corresponds to L1 parameter 'PUCCH-F2-maximum-coderate', 'PUCCH-F3-maximum-coderate' and 'PUCCH-F4-maximum-coderate' + -- (see 38.213, section 9.2.5) + -- The field is not applicable for format 1. + */ + PUCCH_MaxCodeRate_t maxCodeRate; + /* + -- Number of slots with the same PUCCH F1, F3 or F4. When the field is absent the UE applies the value n1. + -- Corresponds to L1 parameter 'PUCCH-F1-number-of-slots', 'PUCCH-F3-number-of-slots' and 'PUCCH-F4-number-of-slots' + -- (see 38.213, section 9.2.6) + -- The field is not applicable for format 2. + */ + uint8_t nrofSlots; + /* + -- Enabling pi/2 BPSK for UCI symbols instead of QPSK for PUCCH. + -- Corresponds to L1 parameter 'PUCCH-PF3-PF4-pi/2PBSK' (see 38.213, section 9.2.5) + -- The field is not applicable for format 1 and 2. + */ + feature_status_t pi2PBSK; + /* + -- Enabling simultaneous transmission of CSI and HARQ-ACK feedback with or without SR with PUCCH Format 2, 3 or 4 + -- Corresponds to L1 parameter 'PUCCH-F2-Simultaneous-HARQ-ACK-CSI', 'PUCCH-F3-Simultaneous-HARQ-ACK-CSI' and + -- 'PUCCH-F4-Simultaneous-HARQ-ACK-CSI' (see 38.213, section 9.2.5) + -- When the field is absent the UE applies the value OFF + -- The field is not applicable for format 1. + */ + enable_feature_t simultaneousHARQ_ACK_CSI; + /* + -- Configuration of group- and sequence hopping for all the PUCCH formats 0, 1, 3 and 4. "neither" implies neither group + -- or sequence hopping is enabled. "enable" enables group hopping and disables sequence hopping. "disable"” disables group + -- hopping and enables sequence hopping. Corresponds to L1 parameter 'PUCCH-GroupHopping' (see 38.211, section 6.4.1.3) + pucch-GroupHopping ENUMERATED { neither, enable, disable }, + */ + pucch_GroupHopping_t pucch_GroupHopping; + /* + -- Cell-Specific scrambling ID for group hoppping and sequence hopping if enabled. + -- Corresponds to L1 parameter 'HoppingID' (see 38.211, section 6.3.2.2) + hoppingId BIT STRING (SIZE (10)) OPTIONAL, -- Need R + */ + uint16_t hoppingId; + /* + -- Power control parameter P0 for PUCCH transmissions. Value in dBm. Only even values (step size 2) allowed. + -- Corresponds to L1 parameter 'p0-nominal-pucch' (see 38.213, section 7.2) + p0-nominal INTEGER (-202..24) OPTIONAL, -- Need R + */ + int8_t p0_nominal; + + int8_t deltaF_PUCCH_f[NUMBER_PUCCH_FORMAT_NR]; + uint8_t p0_PUCCH_Id; /* INTEGER (1..8) */ + int8_t p0_PUCCH_Value; + // pathlossReferenceRSs SEQUENCE (SIZE (1..maxNrofPUCCH-PathlossReferenceRSs)) OF PUCCH-PathlossReferenceRS OPTIONAL, -- Need M + int8_t twoPUCCH_PC_AdjustmentStates; + } fapi_nr_ul_config_pucch_pdu; + typedef enum {pusch_freq_hopping_disabled = 0 , pusch_freq_hopping_enabled = 1}pusch_freq_hopping_t; typedef struct{ uint8_t aperiodicSRS_ResourceTrigger; diff --git a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c index fc053aaef0..e2accc340b 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c +++ b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c @@ -41,7 +41,7 @@ #include "common/utils/LOG/vcd_signal_dumper.h" #include "T.h" -#ifndef NR_UNIT_TEST +#ifdef NR_UNIT_TEST #define DEBUG_PUCCH_TX #define DEBUG_NR_PUCCH_TX #endif @@ -216,7 +216,7 @@ void nr_generate_pucch0(PHY_VARS_NR_UE *ue, // we proceed to calculate alpha according to TS 38.211 Subclause 6.3.2.2.2 for (int l=0; l>15))); // Re part of DMRS base sequence shifted by alpha r_u_v_alpha_delta_dmrs_im[n] = (int16_t)(((((int32_t)(round(32767*cos(alpha*n))) * table_5_2_2_2_2_Im[u][n])>>15) + (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Re[u][n])>>15))); // Im part of DMRS base sequence shifted by alpha + r_u_v_alpha_delta_dmrs_re[n] = (int16_t)(((int32_t)(amp*r_u_v_alpha_delta_dmrs_re[n]))>>15); + r_u_v_alpha_delta_dmrs_im[n] = (int16_t)(((int32_t)(amp*r_u_v_alpha_delta_dmrs_im[n]))>>15); // PUCCH sequence = DM-RS sequence multiplied by d(0) y_n_re[n] = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*d_re)>>15) - (((int32_t)(r_u_v_alpha_delta_im[n])*d_im)>>15))); // Re part of y(n) @@ -438,13 +440,17 @@ void nr_generate_pucch1(PHY_VARS_NR_UE *ue, uint8_t mprime = 0; if (intraSlotFrequencyHopping == 0) { // intra-slot hopping disabled #ifdef DEBUG_NR_PUCCH_TX - printf("\t [nr_generate_pucch1] block-wise spread with the orthogonal sequence wi(m) if intraSlotFrequencyHopping = %d\n", + printf("\t [nr_generate_pucch1] block-wise spread with the orthogonal sequence wi(m) if intraSlotFrequencyHopping = %d, intra-slot hopping disabled\n", intraSlotFrequencyHopping); #endif N_SF_mprime_PUCCH_1 = table_6_3_2_4_1_1_N_SF_mprime_PUCCH_1_noHop[nrofSymbols-1]; // only if intra-slot hopping not enabled (PUCCH) N_SF_mprime_PUCCH_DMRS_1 = table_6_4_1_3_1_1_1_N_SF_mprime_PUCCH_1_noHop[nrofSymbols-1]; // only if intra-slot hopping not enabled (DM-RS) N_SF_mprime0_PUCCH_1 = table_6_3_2_4_1_1_N_SF_mprime_PUCCH_1_noHop[nrofSymbols-1]; // only if intra-slot hopping not enabled mprime = 0 (PUCCH) N_SF_mprime0_PUCCH_DMRS_1 = table_6_4_1_3_1_1_1_N_SF_mprime_PUCCH_1_noHop[nrofSymbols-1]; // only if intra-slot hopping not enabled mprime = 0 (DM-RS) + #ifdef DEBUG_NR_PUCCH_TX + printf("\t [nr_generate_pucch1] w_index = %d, N_SF_mprime_PUCCH_1 = %d, N_SF_mprime_PUCCH_DMRS_1 = %d, N_SF_mprime0_PUCCH_1 = %d, N_SF_mprime0_PUCCH_DMRS_1 = %d\n", + w_index, N_SF_mprime_PUCCH_1,N_SF_mprime_PUCCH_DMRS_1,N_SF_mprime0_PUCCH_1,N_SF_mprime0_PUCCH_DMRS_1); + #endif for (int m=0; m < N_SF_mprime_PUCCH_1; m++){ for (int n=0; n<12 ; n++){ z_re[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n] = (int16_t)((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m])*y_n_re[n])>>15) @@ -452,8 +458,8 @@ void nr_generate_pucch1(PHY_VARS_NR_UE *ue, z_im[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n] = (int16_t)((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m])*y_n_im[n])>>15) + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*y_n_re[n])>>15)); #ifdef DEBUG_NR_PUCCH_TX - printf("\t\t z_pucch[%d] \t= ((%d \t* %d \t-%d \t* %d), (%d \t* %d \t+%d \t*%d)) = (%d,%d)\n", - (mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n, + printf("\t [nr_generate_pucch1] block-wise spread with wi(m) (mprime=%d, m=%d, n=%d) z[%d] = ((%d * %d - %d * %d), (%d * %d + %d * %d)) = (%d,%d)\n", + mprime, m, n, (mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n, table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m],y_n_re[n],table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m],y_n_im[n], table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m],y_n_im[n],table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m],y_n_re[n], z_re[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],z_im[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); @@ -462,26 +468,34 @@ void nr_generate_pucch1(PHY_VARS_NR_UE *ue, } for (int m=0; m < N_SF_mprime_PUCCH_DMRS_1; m++){ for (int n=0; n<12 ; n++){ - z_dmrs_re[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = (int16_t)((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m])*r_u_v_alpha_delta_re[n])>>15) - - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*r_u_v_alpha_delta_im[n])>>15)); - z_dmrs_im[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = (int16_t)((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m])*r_u_v_alpha_delta_im[n])>>15) - + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*r_u_v_alpha_delta_re[n])>>15)); + z_dmrs_re[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = (int16_t)((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m])*r_u_v_alpha_delta_dmrs_re[n])>>15) + - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*r_u_v_alpha_delta_dmrs_im[n])>>15)); + z_dmrs_im[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = (int16_t)((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m])*r_u_v_alpha_delta_dmrs_im[n])>>15) + + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*r_u_v_alpha_delta_dmrs_re[n])>>15)); #ifdef DEBUG_NR_PUCCH_TX - printf("\t\t z_dm-rs[%d] = ((),()) =(%d,%d)\n", - (mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n,z_dmrs_re[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],z_dmrs_im[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); + printf("\t [nr_generate_pucch1] block-wise spread with wi(m) (mprime=%d, m=%d, n=%d) z[%d] = ((%d * %d - %d * %d), (%d * %d + %d * %d)) = (%d,%d)\n", + mprime, m, n, (mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n, + table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m],r_u_v_alpha_delta_dmrs_re[n],table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m],r_u_v_alpha_delta_dmrs_im[n], + table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m],r_u_v_alpha_delta_dmrs_im[n],table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m],r_u_v_alpha_delta_dmrs_re[n], + z_dmrs_re[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],z_dmrs_im[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); #endif } } } if (intraSlotFrequencyHopping == 1) { // intra-slot hopping enabled #ifdef DEBUG_NR_PUCCH_TX - printf("\t [nr_generate_pucch1] block-wise spread with the orthogonal sequence wi(m) if intraSlotFrequencyHopping = %d\n", + printf("\t [nr_generate_pucch1] block-wise spread with the orthogonal sequence wi(m) if intraSlotFrequencyHopping = %d, intra-slot hopping enabled\n", intraSlotFrequencyHopping); #endif N_SF_mprime_PUCCH_1 = table_6_3_2_4_1_1_N_SF_mprime_PUCCH_1_m0Hop[nrofSymbols-1]; // only if intra-slot hopping enabled mprime = 0 (PUCCH) N_SF_mprime_PUCCH_DMRS_1 = table_6_4_1_3_1_1_1_N_SF_mprime_PUCCH_1_m0Hop[nrofSymbols-1]; // only if intra-slot hopping enabled mprime = 0 (DM-RS) N_SF_mprime0_PUCCH_1 = table_6_3_2_4_1_1_N_SF_mprime_PUCCH_1_m0Hop[nrofSymbols-1]; // only if intra-slot hopping enabled mprime = 0 (PUCCH) N_SF_mprime0_PUCCH_DMRS_1 = table_6_4_1_3_1_1_1_N_SF_mprime_PUCCH_1_m0Hop[nrofSymbols-1]; // only if intra-slot hopping enabled mprime = 0 (DM-RS) + #ifdef DEBUG_NR_PUCCH_TX + printf("\t [nr_generate_pucch1] w_index = %d, N_SF_mprime_PUCCH_1 = %d, N_SF_mprime_PUCCH_DMRS_1 = %d, N_SF_mprime0_PUCCH_1 = %d, N_SF_mprime0_PUCCH_DMRS_1 = %d\n", + w_index, N_SF_mprime_PUCCH_1,N_SF_mprime_PUCCH_DMRS_1,N_SF_mprime0_PUCCH_1,N_SF_mprime0_PUCCH_DMRS_1); + #endif + for (int m=0; m < N_SF_mprime_PUCCH_1; m++){ for (mprime = 0; mprime<2; mprime++){ // mprime can get values {0,1} for (int m=0; m < N_SF_mprime_PUCCH_1; m++){ for (int n=0; n<12 ; n++){ @@ -489,19 +503,34 @@ void nr_generate_pucch1(PHY_VARS_NR_UE *ue, - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*y_n_im[n])>>15)); z_im[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n] = (int16_t)((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m])*y_n_im[n])>>15) + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*y_n_re[n])>>15)); +#ifdef DEBUG_NR_PUCCH_TX + printf("\t [nr_generate_pucch1] block-wise spread with wi(m) (mprime=%d, m=%d, n=%d) z[%d] = ((%d * %d - %d * %d), (%d * %d + %d * %d)) = (%d,%d)\n", + mprime, m, n, (mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n, + table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m],y_n_re[n],table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m],y_n_im[n], + table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m],y_n_im[n],table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m],y_n_re[n], + z_re[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],z_im[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); +#endif } } for (int m=0; m < N_SF_mprime_PUCCH_DMRS_1; m++){ for (int n=0; n<12 ; n++){ - z_dmrs_re[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = (int16_t)((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m])*r_u_v_alpha_delta_re[n])>>15) - - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*r_u_v_alpha_delta_im[n])>>15)); - z_dmrs_im[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = (int16_t)((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m])*r_u_v_alpha_delta_im[n])>>15) - + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*r_u_v_alpha_delta_re[n])>>15)); + z_dmrs_re[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = (int16_t)((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m])*r_u_v_alpha_delta_dmrs_re[n])>>15) + - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*r_u_v_alpha_delta_dmrs_im[n])>>15)); + z_dmrs_im[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = (int16_t)((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m])*r_u_v_alpha_delta_dmrs_im[n])>>15) + + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*r_u_v_alpha_delta_dmrs_re[n])>>15)); +#ifdef DEBUG_NR_PUCCH_TX + printf("\t [nr_generate_pucch1] block-wise spread with wi(m) (mprime=%d, m=%d, n=%d) z[%d] = ((%d * %d - %d * %d), (%d * %d + %d * %d)) = (%d,%d)\n", + mprime, m, n, (mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n, + table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m],r_u_v_alpha_delta_dmrs_re[n],table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m],r_u_v_alpha_delta_dmrs_im[n], + table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m],r_u_v_alpha_delta_dmrs_im[n],table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m],r_u_v_alpha_delta_dmrs_re[n], + z_dmrs_re[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],z_dmrs_im[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); +#endif } } N_SF_mprime_PUCCH_1 = table_6_3_2_4_1_1_N_SF_mprime_PUCCH_1_m1Hop[nrofSymbols-1]; // only if intra-slot hopping enabled mprime = 1 (PUCCH) N_SF_mprime_PUCCH_DMRS_1 = table_6_4_1_3_1_1_1_N_SF_mprime_PUCCH_1_m1Hop[nrofSymbols-1]; // only if intra-slot hopping enabled mprime = 1 (DM-RS) } + } } if ((intraSlotFrequencyHopping == 1) && (l>i)&1); btilde[i] = (((B>>i)&1) ^ c); #ifdef DEBUG_NR_PUCCH_TX - printf("\t\t\t btilde[%d]=%lx from scrambled bit %d\n",i,btilde[i],((B>>i)&1)); + //printf("\t\t\t btilde[%d]=%lx from scrambled bit %d\n",i,btilde[i],((B>>i)&1)); #endif } #ifdef DEBUG_NR_PUCCH_TX @@ -948,6 +977,7 @@ void nr_uci_encoding(uint64_t payload, } //#if 0 void nr_generate_pucch2(PHY_VARS_NR_UE *ue, + uint16_t crnti, int32_t **txdataF, NR_DL_FRAME_PARMS *frame_parms, PUCCH_CONFIG_DEDICATED *pucch_config_dedicated, @@ -982,7 +1012,11 @@ void nr_generate_pucch2(PHY_VARS_NR_UE *ue, */ uint8_t *btilde = malloc(sizeof(int8_t)*M_bit); - uint16_t rnti=0xff, n_id=0; + // rnti is given by the C-RNTI + uint16_t rnti=crnti, n_id=0; +#ifdef DEBUG_NR_PUCCH_TX + printf("\t [nr_generate_pucch2] rnti = %d ,\n",rnti); +#endif /* * Implementing TS 38.211 Subclause 6.3.2.5.1 scrambling format 2 @@ -1064,7 +1098,7 @@ void nr_generate_pucch2(PHY_VARS_NR_UE *ue, ((int16_t *)&txdataF[0][re_offset])[0] = d_re[i+k]; ((int16_t *)&txdataF[0][re_offset])[1] = d_im[i+k]; #ifdef DEBUG_NR_PUCCH_TX - printf("\t [nr_generate_pucch1] (n=%d,i=%d) mapping PUCCH to RE \t amp=%d \tofdm_symbol_size=%d \tN_RB_DL=%d \tfirst_carrier_offset=%d \tz_pucch[%d]=txptr(%d)=(x_n(l=%d,n=%d)=(%d,%d))\n", + printf("\t [nr_generate_pucch2] (n=%d,i=%d) mapping PUCCH to RE \t amp=%d \tofdm_symbol_size=%d \tN_RB_DL=%d \tfirst_carrier_offset=%d \tz_pucch[%d]=txptr(%d)=(x_n(l=%d,n=%d)=(%d,%d))\n", n,i,amp,frame_parms->ofdm_symbol_size,frame_parms->N_RB_DL,frame_parms->first_carrier_offset,i+k,re_offset, l,n,((int16_t *)&txdataF[0][re_offset])[0],((int16_t *)&txdataF[0][re_offset])[1]); #endif @@ -1075,7 +1109,7 @@ void nr_generate_pucch2(PHY_VARS_NR_UE *ue, ((int16_t *)&txdataF[0][re_offset])[1] = (int16_t)((int32_t)(amp*ONE_OVER_SQRT2*(1-(2*((uint8_t)((s>>((2*m)+1))&1)))))>>15); m++; #ifdef DEBUG_NR_PUCCH_TX - printf("\t [nr_generate_pucch1] (n=%d,i=%d) mapping DM-RS to RE \t amp=%d \tofdm_symbol_size=%d \tN_RB_DL=%d \tfirst_carrier_offset=%d \tz_dm-rs[%d]=txptr(%d)=(x_n(l=%d,n=%d)=(%d,%d))\n", + printf("\t [nr_generate_pucch2] (n=%d,i=%d) mapping DM-RS to RE \t amp=%d \tofdm_symbol_size=%d \tN_RB_DL=%d \tfirst_carrier_offset=%d \tz_dm-rs[%d]=txptr(%d)=(x_n(l=%d,n=%d)=(%d,%d))\n", n,i,amp,frame_parms->ofdm_symbol_size,frame_parms->N_RB_DL,frame_parms->first_carrier_offset,i+kk,re_offset, l,n,((int16_t *)&txdataF[0][re_offset])[0],((int16_t *)&txdataF[0][re_offset])[1]); #endif @@ -1089,6 +1123,7 @@ void nr_generate_pucch2(PHY_VARS_NR_UE *ue, } //#if 0 void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue, + uint16_t crnti, int32_t **txdataF, NR_DL_FRAME_PARMS *frame_parms, pucch_format_nr_t fmt, @@ -1123,11 +1158,14 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue, if (startingPRB != startingPRB_intraSlotHopping){ intraSlotFrequencyHopping=1; #ifdef DEBUG_NR_PUCCH_TX - printf("\t [nr_generate_pucch1] intraSlotFrequencyHopping=%d \n",intraSlotFrequencyHopping); + printf("\t [nr_generate_pucch3_4] intraSlotFrequencyHopping=%d \n",intraSlotFrequencyHopping); #endif } // add_dmrs indicates if we are using or not Additional DM-RS for formats 3 and 4. From higher layers. FIXME!!! uint8_t add_dmrs = 0; + //nrofPRB = 2; // only for test purposes + if (fmt == pucch_format4_nr) nrofPRB = 1; + nr_uci_encoding(payload,nr_bit,fmt,is_pi_over_2_bpsk_enabled,nrofSymbols,nrofPRB,n_SF_PUCCH_s,intraSlotFrequencyHopping,add_dmrs,&b,&M_bit); /* @@ -1144,7 +1182,11 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue, */ uint8_t *btilde = malloc(sizeof(int8_t)*M_bit); - uint16_t rnti=0xff, n_id=0; + // rnti is given by the C-RNTI + uint16_t rnti=crnti, n_id=0; +#ifdef DEBUG_NR_PUCCH_TX + printf("\t [nr_generate_pucch3_4] rnti = %d ,\n",rnti); +#endif /* * Implementing TS 38.211 Subclause 6.3.2.6.1 scrambling formats 3 and 4 @@ -1226,27 +1268,27 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue, // Re part orthogonal sequences w_n(k) for PUCCH format 4 when N_SF_PUCCH4 = 2 (Table 6.3.2.6.3-1) // k={0,..11} n={0,1,2,3} // parameter PUCCH-F4-preDFT-OCC-index set of {0,1,2,3} -> n - uint16_t table_6_3_2_6_3_1_Wi_Re[2][12] = {{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, + uint16_t table_6_3_2_6_3_1_Wn_Re[2][12] = {{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, {1, 1, 1, 1, 1, 1,-1,-1,-1,-1,-1,-1}}; // Im part orthogonal sequences w_n(k) for PUCCH format 4 when N_SF_PUCCH4 = 2 (Table 6.3.2.6.3-1) // k={0,..11} n={0,1} - uint16_t table_6_3_2_6_3_1_Wi_Im[2][12] = {{0,0,0,0,0,0,0,0,0,0,0,0}, + uint16_t table_6_3_2_6_3_1_Wn_Im[2][12] = {{0,0,0,0,0,0,0,0,0,0,0,0}, {0,0,0,0,0,0,0,0,0,0,0,0}}; // Re part orthogonal sequences w_n(k) for PUCCH format 4 when N_SF_PUCCH4 = 4 (Table 6.3.2.6.3-2) // k={0,..11} n={0,1,2.3} - uint16_t table_6_3_2_6_3_2_Wi_Re[4][12] = {{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, + uint16_t table_6_3_2_6_3_2_Wn_Re[4][12] = {{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, {1, 1, 1, 0, 0, 0,-1,-1,-1, 0, 0, 0}, {1, 1, 1,-1,-1,-1, 1, 1, 1,-1,-1,-1}, {1, 1, 1, 0, 0, 0,-1,-1,-1, 0, 0, 0}}; // Im part orthogonal sequences w_n(k) for PUCCH format 4 when N_SF_PUCCH4 = 4 (Table 6.3.2.6.3-2) // k={0,..11} n={0,1,2,3} - uint16_t table_6_3_2_6_3_2_Wi_Im[4][12] = {{0,0,0, 0, 0, 0,0,0,0, 0, 0, 0}, - {0,0,0,-1,-1,-1,0,0,0, 1, 1, 1}, - {0,0,0, 0, 0, 0,0,0,0, 0, 0, 0}, - {0,0,0, 1, 1, 1,0,0,0,-1,-1,-1}}; + uint16_t table_6_3_2_6_3_2_Wn_Im[4][12] = {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0,-1,-1,-1, 0, 0, 0, 1, 1, 1}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 1, 1, 1, 0, 0, 0,-1,-1,-1}}; uint8_t occ_Length = occ_length_format4; // higher layer parameter occ-Length uint8_t occ_Index = occ_index_format4; // higher layer parameter occ-Index - +//occ_Index = 1; //only for testing purposes; to be removed FIXME!!! if (fmt == pucch_format3_nr){ // no block-wise spreading for format 3 n_SF_PUCCH_s = 1; for (int l=0; l < floor(m_symbol/(12*nrofPRB)); l++){ @@ -1265,23 +1307,27 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue, for (int l=0; l < floor((n_SF_PUCCH_s*m_symbol)/(12*nrofPRB)); l++){ for (int k=0; k < (12*nrofPRB); k++){ if (n_SF_PUCCH_s == 2){ - y_n_re[l*(12*nrofPRB)+k] = (uint16_t)(((uint32_t)d_re[l*(12*nrofPRB/n_SF_PUCCH_s)+k%(12*nrofPRB/n_SF_PUCCH_s)] * table_6_3_2_6_3_1_Wi_Re[occ_Index][k]) - - ((uint32_t)d_im[l*(12*nrofPRB/n_SF_PUCCH_s)+k%(12*nrofPRB/n_SF_PUCCH_s)] * table_6_3_2_6_3_1_Wi_Im[occ_Index][k])); - y_n_im[l*(12*nrofPRB)+k] = (uint16_t)(((uint32_t)d_im[l*(12*nrofPRB/n_SF_PUCCH_s)+k%(12*nrofPRB/n_SF_PUCCH_s)] * table_6_3_2_6_3_1_Wi_Re[occ_Index][k]) - + ((uint32_t)d_re[l*(12*nrofPRB/n_SF_PUCCH_s)+k%(12*nrofPRB/n_SF_PUCCH_s)] * table_6_3_2_6_3_1_Wi_Im[occ_Index][k])); + y_n_re[l*(12*nrofPRB)+k] = (uint16_t)(((uint32_t)d_re[l*(12*nrofPRB/n_SF_PUCCH_s)+k%(12*nrofPRB/n_SF_PUCCH_s)] * table_6_3_2_6_3_1_Wn_Re[occ_Index][k]) + - ((uint32_t)d_im[l*(12*nrofPRB/n_SF_PUCCH_s)+k%(12*nrofPRB/n_SF_PUCCH_s)] * table_6_3_2_6_3_1_Wn_Im[occ_Index][k])); + y_n_im[l*(12*nrofPRB)+k] = (uint16_t)(((uint32_t)d_im[l*(12*nrofPRB/n_SF_PUCCH_s)+k%(12*nrofPRB/n_SF_PUCCH_s)] * table_6_3_2_6_3_1_Wn_Re[occ_Index][k]) + + ((uint32_t)d_re[l*(12*nrofPRB/n_SF_PUCCH_s)+k%(12*nrofPRB/n_SF_PUCCH_s)] * table_6_3_2_6_3_1_Wn_Im[occ_Index][k])); #ifdef DEBUG_NR_PUCCH_TX - printf("\t [nr_generate_pucch3_4] block-wise spreading for format 4 (n_SF_PUCCH_s 2): (l,k)=(%d,%d)\ty_n(%d) = \t(d_re=%d, d_im=%d)\n", - l,k,l*(12*nrofPRB)+k,y_n_re[l*(12*nrofPRB)+k],y_n_im[l*(12*nrofPRB)+k]); + printf("\t [nr_generate_pucch3_4] block-wise spreading for format 4 (n_SF_PUCCH_s 2) (occ_Index=%d): (l,k)=(%d,%d)\ty_n(%d) = \t(d_re=%d, d_im=%d)\n", + occ_Index,l,k,l*(12*nrofPRB)+k,y_n_re[l*(12*nrofPRB)+k],y_n_im[l*(12*nrofPRB)+k]); +// printf("\t\t d_re[l*(12*nrofPRB/n_SF_PUCCH_s)+k%(12*nrofPRB/n_SF_PUCCH_s)] = %d\n",d_re[l*(12*nrofPRB/n_SF_PUCCH_s)+k%(12*nrofPRB/n_SF_PUCCH_s)]); +// printf("\t\t d_im[l*(12*nrofPRB/n_SF_PUCCH_s)+k%(12*nrofPRB/n_SF_PUCCH_s)] = %d\n",d_im[l*(12*nrofPRB/n_SF_PUCCH_s)+k%(12*nrofPRB/n_SF_PUCCH_s)]); +// printf("\t\t table_6_3_2_6_3_1_Wn_Re[%d][%d] = %d\n",occ_Index,k,table_6_3_2_6_3_1_Wn_Re[occ_Index][k]); +// printf("\t\t table_6_3_2_6_3_1_Wn_Im[%d][%d] = %d\n",occ_Index,k,table_6_3_2_6_3_1_Wn_Im[occ_Index][k]); #endif } if (n_SF_PUCCH_s == 4){ - y_n_re[l*(12*nrofPRB)+k] = (uint16_t)(((uint32_t)d_re[l*(12*nrofPRB/n_SF_PUCCH_s)+k%(12*nrofPRB/n_SF_PUCCH_s)] * table_6_3_2_6_3_2_Wi_Re[occ_Index][k]) - - ((uint32_t)d_im[l*(12*nrofPRB/n_SF_PUCCH_s)+k%(12*nrofPRB/n_SF_PUCCH_s)] * table_6_3_2_6_3_2_Wi_Im[occ_Index][k])); - y_n_im[l*(12*nrofPRB)+k] = (uint16_t)(((uint32_t)d_im[l*(12*nrofPRB/n_SF_PUCCH_s)+k%(12*nrofPRB/n_SF_PUCCH_s)] * table_6_3_2_6_3_2_Wi_Re[occ_Index][k]) - + ((uint32_t)d_re[l*(12*nrofPRB/n_SF_PUCCH_s)+k%(12*nrofPRB/n_SF_PUCCH_s)] * table_6_3_2_6_3_2_Wi_Im[occ_Index][k])); + y_n_re[l*(12*nrofPRB)+k] = (uint16_t)(((uint32_t)d_re[l*(12*nrofPRB/n_SF_PUCCH_s)+k%(12*nrofPRB/n_SF_PUCCH_s)] * table_6_3_2_6_3_2_Wn_Re[occ_Index][k]) + - ((uint32_t)d_im[l*(12*nrofPRB/n_SF_PUCCH_s)+k%(12*nrofPRB/n_SF_PUCCH_s)] * table_6_3_2_6_3_2_Wn_Im[occ_Index][k])); + y_n_im[l*(12*nrofPRB)+k] = (uint16_t)(((uint32_t)d_im[l*(12*nrofPRB/n_SF_PUCCH_s)+k%(12*nrofPRB/n_SF_PUCCH_s)] * table_6_3_2_6_3_2_Wn_Re[occ_Index][k]) + + ((uint32_t)d_re[l*(12*nrofPRB/n_SF_PUCCH_s)+k%(12*nrofPRB/n_SF_PUCCH_s)] * table_6_3_2_6_3_2_Wn_Im[occ_Index][k])); #ifdef DEBUG_NR_PUCCH_TX - printf("\t [nr_generate_pucch3_4] block-wise spreading for format 4 (n_SF_PUCCH_s 4): (l,k)=(%d,%d)\ty_n(%d) = \t(d_re=%d, d_im=%d)\n", - l,k,l*(12*nrofPRB)+k,y_n_re[l*(12*nrofPRB)+k],y_n_im[l*(12*nrofPRB)+k]); + printf("\t [nr_generate_pucch3_4] block-wise spreading for format 4 (n_SF_PUCCH_s 4) (occ_Index=%d): (l,k)=(%d,%d)\ty_n(%d) = \t(d_re=%d, d_im=%d)\n", + occ_Index,l,k,l*(12*nrofPRB)+k,y_n_re[l*(12*nrofPRB)+k],y_n_im[l*(12*nrofPRB)+k]); #endif } } @@ -1293,14 +1339,20 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue, */ int16_t *z_re = malloc(sizeof(int16_t)*4*M_bit); // 4 is the maximum number n_SF_PUCCH_s int16_t *z_im = malloc(sizeof(int16_t)*4*M_bit); - # define M_PI 3.14159265358979323846 // pi + #define M_PI 3.14159265358979323846 // pi //int16_t inv_sqrt_nrofPRBs = (int16_t)round(32767/sqrt(12*nrofPRB)); for (int l=0; l>15) +// + (((int32_t)y_n_im[l*(12*nrofPRB)+m] * (int16_t)round(32767 * sin(2*M_PI*m*k/(12*nrofPRB))))>>15)))>>15); +// z_im_tmp[m] = (int16_t)(((int32_t)round(32767/sqrt(12*nrofPRB))*(int16_t)((((int32_t)y_n_im[l*(12*nrofPRB)+m] * (int16_t)round(32767 * cos(2*M_PI*m*k/(12*nrofPRB))))>>15) +// - (((int32_t)y_n_re[l*(12*nrofPRB)+m] * (int16_t)round(32767 * sin(2*M_PI*m*k/(12*nrofPRB))))>>15)))>>15); z_re[l*(12*nrofPRB)+k] = z_re[l*(12*nrofPRB)+k] + (int16_t)(((int32_t)round(32767/sqrt(12*nrofPRB))*(int16_t)((((int32_t)y_n_re[l*(12*nrofPRB)+m] * (int16_t)round(32767 * cos(2*M_PI*m*k/(12*nrofPRB))))>>15) + (((int32_t)y_n_im[l*(12*nrofPRB)+m] * (int16_t)round(32767 * sin(2*M_PI*m*k/(12*nrofPRB))))>>15)))>>15); @@ -1308,12 +1360,14 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue, + (int16_t)(((int32_t)round(32767/sqrt(12*nrofPRB))*(int16_t)((((int32_t)y_n_im[l*(12*nrofPRB)+m] * (int16_t)round(32767 * cos(2*M_PI*m*k/(12*nrofPRB))))>>15) - (((int32_t)y_n_re[l*(12*nrofPRB)+m] * (int16_t)round(32767 * sin(2*M_PI*m*k/(12*nrofPRB))))>>15)))>>15); #ifdef DEBUG_NR_PUCCH_TX - printf("\t [nr_generate_pucch3_4] transform precoding for formats 3 and 4: (l,k,m)=(%d,%d,%d)\tz(%d) = \t(%d, %d)\n", - l,k,m,l*(12*nrofPRB)+k,z_re[l*(12*nrofPRB)+k],z_im[l*(12*nrofPRB)+k]); +// printf("\t\t z_re_tmp[%d] = %d\n",m,z_re_tmp[m]); +// printf("\t\t z_im_tmp[%d] = %d\n",m,z_im_tmp[m]); +// printf("\t [nr_generate_pucch3_4] transform precoding for formats 3 and 4: (l,k,m)=(%d,%d,%d)\tz(%d) = \t(%d, %d)\n", +// l,k,m,l*(12*nrofPRB)+k,z_re[l*(12*nrofPRB)+k],z_im[l*(12*nrofPRB)+k]); #endif } #ifdef DEBUG_NR_PUCCH_TX - printf("\t\t\t [nr_generate_pucch3_4] transform precoding for formats 3 and 4: (l,k)=(%d,%d)\tz(%d) = \t(%d, %d)\n", + printf("\t [nr_generate_pucch3_4] transform precoding for formats 3 and 4: (l,k)=(%d,%d)\tz(%d) = \t(%d, %d)\n", l,k,l*(12*nrofPRB)+k,z_re[l*(12*nrofPRB)+k],z_im[l*(12*nrofPRB)+k]); #endif } @@ -1480,13 +1534,9 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue, ((int16_t *)&txdataF[0][re_offset])[1] = (int16_t)((((int32_t)(32767*cos(alpha*((n+j)%N_ZC)))*r_u_v_base_im[n+j])>>15) + (((int32_t)(32767*sin(alpha*((n+j)%N_ZC)))*r_u_v_base_re[n+j])>>15)); #ifdef DEBUG_NR_PUCCH_TX - printf("\t [nr_generate_pucch3_4] (l=%d,rb=%d,n=%d,j=%d) mapping DM-RS to RE \t amp=%d \tofdm_symbol_size=%d \tN_RB_DL=%d \tfirst_carrier_offset=%d \tz_dm-rs[%d]=txptr(%d)=(r_u_v(l=%d,n=%d)=(%d,%d)) \t\t debug1=%d,debug2=%d,debug3=%d,debug4=%d\n", + printf("\t [nr_generate_pucch3_4] (l=%d,rb=%d,n=%d,j=%d) mapping DM-RS to RE \t amp=%d \tofdm_symbol_size=%d \tN_RB_DL=%d \tfirst_carrier_offset=%d \tz_dm-rs[%d]=txptr(%d)=(r_u_v(l=%d,n=%d)=(%d,%d))\n", l,rb,n,j,amp,frame_parms->ofdm_symbol_size,frame_parms->N_RB_DL,frame_parms->first_carrier_offset,n+j,re_offset, - l,n,((int16_t *)&txdataF[0][re_offset])[0],((int16_t *)&txdataF[0][re_offset])[1], - (((int32_t)(32767*cos(alpha*((n+j)%N_ZC)))*r_u_v_base_re[n+j])>>15), - (((int32_t)(32767*sin(alpha*((n+j)%N_ZC)))*r_u_v_base_im[n+j])>>15), - (((int32_t)(32767*cos(alpha*((n+j)%N_ZC)))*r_u_v_base_im[n+j])>>15), - (((int32_t)(32767*sin(alpha*((n+j)%N_ZC)))*r_u_v_base_re[n+j])>>15)); + l,n,((int16_t *)&txdataF[0][re_offset])[0],((int16_t *)&txdataF[0][re_offset])[1]); #endif } re_offset++; diff --git a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h index 5d3d394b58..eb10c27857 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h +++ b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h @@ -82,6 +82,7 @@ void nr_generate_pucch1(PHY_VARS_NR_UE *ue, uint8_t timeDomainOCC, uint8_t nr_bit); void nr_generate_pucch2(PHY_VARS_NR_UE *ue, + uint16_t crnti, int32_t **txdataF, NR_DL_FRAME_PARMS *frame_parms, PUCCH_CONFIG_DEDICATED *pucch_config_dedicated, @@ -94,6 +95,7 @@ void nr_generate_pucch2(PHY_VARS_NR_UE *ue, uint16_t startingPRB, uint8_t nr_bit); void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue, + uint16_t crnti, int32_t **txdataF, NR_DL_FRAME_PARMS *frame_parms, pucch_format_nr_t fmt, @@ -397,7 +399,7 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue, */ int16_t table_6_3_2_4_1_2_Wi_Re[8][7][7] = { {{0,0,0,0,0,0,0}, {0,0,0,0,0,0,0}, {0,0,0,0,0,0,0}, {0,0,0,0,0,0,0}, {0,0,0,0,0,0,0}, {0,0,0,0,0,0,0}, {0,0,0,0,0,0,0}}, - {{0,0,0,0,0,0,0}, {0,0,0,0,0,0,0}, {0,0,0,0,0,0,0}, {0,0,0,0,0,0,0}, {0,0,0,0,0,0,0}, {0,0,0,0,0,0,0}, {0,0,0,0,0,0,0}}, + {{32767,0,0,0,0,0,0}, {0,0,0,0,0,0,0}, {0,0,0,0,0,0,0}, {0,0,0,0,0,0,0}, {0,0,0,0,0,0,0}, {0,0,0,0,0,0,0}, {0,0,0,0,0,0,0}}, {{32767,32767,0,0,0,0,0}, {32767,-32767,0,0,0,0,0}, {0,0,0,0,0,0,0}, {0,0,0,0,0,0,0}, {0,0,0,0,0,0,0}, {0,0,0,0,0,0,0}, {0,0,0,0,0,0,0}}, {{32767,32767,32767,0,0,0,0}, {32767,-16384,-16384,0,0,0,0}, {32767,-16384,-16384,0,0,0,0}, {0,0,0,0,0,0,0}, {0,0,0,0,0,0,0}, {0,0,0,0,0,0,0}, {0,0,0,0,0,0,0}}, {{32767,32767,32767,32767,0,0,0}, {32767,-32767,32767,-32767,0,0,0}, {32767,32767,-32767,-32767,0,0,0}, {32767,-32767,-32767,32767,0,0,0}, {0,0,0,0,0,0,0}, {0,0,0,0,0,0,0}, {0,0,0,0,0,0,0}}, diff --git a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c index fd19e71b1b..6f79b38d3d 100644 --- a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c +++ b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c @@ -37,6 +37,7 @@ //#include "PHY/phy_vars_nr_ue.h" #include "PHY/defs_nr_UE.h" +#include "PHY/impl_defs_nr.h" extern PHY_VARS_NR_UE ***PHY_vars_UE_g; int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ @@ -51,10 +52,14 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ NR_UE_PDCCH *pdcch_vars2 = PHY_vars_UE_g[module_id][cc_id]->pdcch_vars[0][0]; NR_UE_DLSCH_t *dlsch0 = PHY_vars_UE_g[module_id][cc_id]->dlsch[0][0]; NR_UE_ULSCH_t *ulsch0 = PHY_vars_UE_g[module_id][cc_id]->ulsch[0]; + NR_DL_FRAME_PARMS frame_parms = PHY_vars_UE_g[module_id][cc_id]->frame_parms; + PRACH_RESOURCES_t *prach_resources = PHY_vars_UE_g[module_id][cc_id]->prach_resources[0]; +// PUCCH_ConfigCommon_nr_t *pucch_config_common = PHY_vars_UE_g[module_id][cc_id]->pucch_config_common_nr[0]; +// PUCCH_Config_t *pucch_config_dedicated = PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0]; + if(scheduled_response->dl_config != NULL){ fapi_nr_dl_config_request_t *dl_config = scheduled_response->dl_config; - for(i=0; inumber_pdus; ++i){ if(dl_config->dl_config_list[i].pdu_type == FAPI_NR_DL_CONFIG_TYPE_DCI){ @@ -143,6 +148,52 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ ulsch0->harq_processes[current_harq_pid]->rvidx = pusch_config_pdu->rv; ulsch0->f_pusch = pusch_config_pdu->absolute_delta_PUSCH; } + if(ul_config->ul_config_list[i].pdu_type == FAPI_NR_UL_CONFIG_TYPE_PUCCH){ + // pucch config pdu + fapi_nr_ul_config_pucch_pdu *pucch_config_pdu = &ul_config->ul_config_list[i].pucch_config_pdu; + uint8_t pucch_resource_id = 0; //FIXME!!! + uint8_t format = 1; // FIXME!!! + PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.initialCyclicShift = pucch_config_pdu->initialCyclicShift; + PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.nrofSymbols = pucch_config_pdu->nrofSymbols; + PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.startingSymbolIndex = pucch_config_pdu->startingSymbolIndex; + PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.nrofPRBs = pucch_config_pdu->nrofPRBs; + PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->startingPRB = pucch_config_pdu->startingPRB; + PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.timeDomainOCC = pucch_config_pdu->timeDomainOCC; + PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.occ_length = pucch_config_pdu->occ_length; + PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.occ_Index = pucch_config_pdu->occ_Index; + PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->intraSlotFrequencyHopping = pucch_config_pdu->intraSlotFrequencyHopping; + PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->secondHopPRB = pucch_config_pdu->secondHopPRB; // Not sure this parameter is used + PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].formatConfig[format-1]->additionalDMRS = pucch_config_pdu->additionalDMRS; // At this point we need to know which format is going to be used + PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].formatConfig[format-1]->pi2PBSK = pucch_config_pdu->pi2PBSK; + PHY_vars_UE_g[module_id][cc_id]->pucch_config_common_nr[0].pucch_GroupHopping = pucch_config_pdu->pucch_GroupHopping; + PHY_vars_UE_g[module_id][cc_id]->pucch_config_common_nr[0].hoppingId = pucch_config_pdu->hoppingId; + PHY_vars_UE_g[module_id][cc_id]->pucch_config_common_nr[0].p0_nominal = pucch_config_pdu->p0_nominal; +/* pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.initialCyclicShift = pucch_config_pdu->initialCyclicShift; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.nrofSymbols = pucch_config_pdu->nrofSymbols; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.startingSymbolIndex = pucch_config_pdu->startingSymbolIndex; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.nrofPRBs = pucch_config_pdu->nrofPRBs; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->startingPRB = pucch_config_pdu->startingPRB; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.timeDomainOCC = pucch_config_pdu->timeDomainOCC; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.occ_length = pucch_config_pdu->occ_length; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.occ_Index = pucch_config_pdu->occ_Index; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->intraSlotFrequencyHopping = pucch_config_pdu->intraSlotFrequencyHopping; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->secondHopPRB = pucch_config_pdu->secondHopPRB; // Not sure this parameter is used + pucch_config_dedicated->formatConfig[format-1]->additionalDMRS = pucch_config_pdu->additionalDMRS; // At this point we need to know which format is going to be used + pucch_config_dedicated->formatConfig[format-1]->pi2PBSK = pucch_config_pdu->pi2PBSK; + pucch_config_common->pucch_GroupHopping = pucch_config_pdu->pucch_GroupHopping; + pucch_config_common->hoppingId = pucch_config_pdu->hoppingId; + pucch_config_common->p0_nominal = pucch_config_pdu->p0_nominal;*/ + } + if(ul_config->ul_config_list[i].pdu_type == FAPI_NR_UL_CONFIG_TYPE_PRACH){ + // prach config pdu + fapi_nr_ul_config_prach_pdu *prach_config_pdu = &ul_config->ul_config_list[i].prach_config_pdu; + frame_parms.prach_config_common.rootSequenceIndex = prach_config_pdu->root_sequence_index; + frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex = prach_config_pdu->prach_configuration_index; + frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig = prach_config_pdu->zero_correlation_zone_config; + frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag = prach_config_pdu->restrictedset_config; + frame_parms.prach_config_common.prach_ConfigInfo.prach_FreqOffset = prach_config_pdu->prach_freq_offset; + prach_resources->ra_PreambleIndex = prach_config_pdu->preamble_index; + } } }else{ diff --git a/openair1/SCHED_NR_UE/harq_nr.c b/openair1/SCHED_NR_UE/harq_nr.c index 796b87cc59..93a3f998cf 100644 --- a/openair1/SCHED_NR_UE/harq_nr.c +++ b/openair1/SCHED_NR_UE/harq_nr.c @@ -373,7 +373,7 @@ void config_downlink_harq_process(PHY_VARS_NR_UE *ue, int gNB_id, int TB_id, int { NR_UE_DLSCH_t *dlsch; - //dlsch = (NR_UE_DLSCH_t *)malloc16(sizeof(NR_UE_DLSCH_t)); + dlsch = (NR_UE_DLSCH_t *)malloc16(sizeof(NR_UE_DLSCH_t)); if (dlsch != NULL) { diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index eee5cbae95..4044a1434b 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -3903,8 +3903,11 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id,PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t * crc_scrambled_values, ptr_nr_dci_info_extracted);//&nr_dci_info_extracted); - ue->dci_ind.dci_list[i].rnti = dci_alloc_rx[i].rnti; - ue->dci_ind.dci_list[i].dci_format = dci_alloc_rx[i].format; + ue->dci_ind.dci_list[i].rnti = dci_alloc_rx[i].rnti; + ue->dci_ind.dci_list[i].dci_format = dci_alloc_rx[i].format; + ue->dci_ind.dci_list[i].n_CCE = dci_alloc_rx[i].firstCCE; + ue->dci_ind.dci_list[i].N_CCE = (int)dci_alloc_rx[i].L; + ue->dci_ind.number_of_dcis = ue->dci_ind.number_of_dcis + 1; memcpy(&ue->dci_ind.dci_list[i].dci, &nr_dci_info_extracted, sizeof(fapi_nr_dci_pdu_rel15_t) ); //printf(">>> example mcs=%d\n",nr_dci_info_extracted.mcs); diff --git a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c index 5b56cd4bd0..bc23c5a974 100644 --- a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c +++ b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c @@ -178,7 +178,7 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ int ri_status = 0; int csi_status = 0; - int initial_pucch_id = NB_INITIAL_PUCCH_RESOURCE;; + int initial_pucch_id = NB_INITIAL_PUCCH_RESOURCE; int pucch_resource_set = MAX_NB_OF_PUCCH_RESOURCE_SETS; int pucch_resource_id = MAX_NB_OF_PUCCH_RESOURCES; int pucch_resource_indicator = MAX_PUCCH_RESOURCE_INDICATOR; @@ -587,7 +587,9 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ } case pucch_format2_nr: { - nr_generate_pucch2(ue,ue->common_vars.txdataF, + nr_generate_pucch2(ue, + ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti, + ue->common_vars.txdataF, &ue->frame_parms, &ue->pucch_config_dedicated_nr[gNB_id], pucch_payload, @@ -603,7 +605,9 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ case pucch_format3_nr: case pucch_format4_nr: { - nr_generate_pucch3_4(ue,ue->common_vars.txdataF, + nr_generate_pucch3_4(ue, + ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti, + ue->common_vars.txdataF, &ue->frame_parms, format, &ue->pucch_config_dedicated_nr[gNB_id], @@ -871,6 +875,10 @@ boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size else { /* see TS 38.213 9.2.1 PUCCH Resource Sets */ int delta_PRI = harq_status->pucch_resource_indicator; + // n_CCE can be obtained from ue->dci_ind.dci_list[i].n_CCE. FIXME!!! + // N_CCE can be obtained from ue->dci_ind.dci_list[i].N_CCE. FIXME!!! + //int n_CCE = ue->dci_ind.dci_list[0].n_CCE; + //int N_CCE = ue->dci_ind.dci_list[0].N_CCE; int n_CCE_0 = harq_status->n_CCE; int N_CCE_0 = harq_status->N_CCE; if (N_CCE_0 == 0) { diff --git a/openair1/SIMULATION/NR_UE_PHY/unit_tests/src/pss_util_test.c b/openair1/SIMULATION/NR_UE_PHY/unit_tests/src/pss_util_test.c index 1531a82314..c33571c6ea 100644 --- a/openair1/SIMULATION/NR_UE_PHY/unit_tests/src/pss_util_test.c +++ b/openair1/SIMULATION/NR_UE_PHY/unit_tests/src/pss_util_test.c @@ -70,7 +70,7 @@ static nfapi_config_request_t* config =&config_t; /*************** FUNCTIONS ****************************************/ -void phy_init_nr_top(NR_DL_FRAME_PARMS *frame_parms); +//void phy_init_nr_top(NR_DL_FRAME_PARMS *frame_parms); int init_nr_ue_signal(PHY_VARS_NR_UE *ue, int nb_connected_eNB, uint8_t abstraction_flag); /******************************************************************* @@ -262,7 +262,7 @@ int init_test(unsigned char N_tx, unsigned char N_rx, unsigned char transmission PHY_vars_UE->frame_parms.Nid_cell = (3 * N_ID_1_NUMBER) + N_ID_2_NUMBER; /* set to unvalid value */ - phy_init_nr_top(frame_parms); + //phy_init_nr_top(frame_parms); if (init_nr_ue_signal(PHY_vars_UE, 1, 0) != 0) { diff --git a/openair1/SIMULATION/NR_UE_PHY/unit_tests/src/pucch_uci_test.c b/openair1/SIMULATION/NR_UE_PHY/unit_tests/src/pucch_uci_test.c index 9d5f31f9f9..ff15dec6a4 100644 --- a/openair1/SIMULATION/NR_UE_PHY/unit_tests/src/pucch_uci_test.c +++ b/openair1/SIMULATION/NR_UE_PHY/unit_tests/src/pucch_uci_test.c @@ -180,7 +180,7 @@ int test_pucch_basic_error(PHY_VARS_NR_UE *ue, int gNB_id, UE_nr_rxtx_proc_t *pr } /* set a tx slot with no ack */ - NR_UE_HARQ_STATUS_t *harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[TST_DL_HARQ_PID_FIRST]->harq_ack; + NR_UE_HARQ_STATUS_t *harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[TST_DL_HARQ_PID_FIRST].harq_ack; harq_status->slot_for_feedback_ack = proc->nr_tti_tx; @@ -267,7 +267,7 @@ int test_pucch_common_config_single_transport_block(PHY_VARS_NR_UE *ue, int gNB_ common_pucch_configuration(ue, gNB_id, TST_PUCCH_COMMON_CONFIG_INDEX_OK); /* set a tx slot with no ack */ - NR_UE_HARQ_STATUS_t *harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[TST_DL_HARQ_PID_FIRST]->harq_ack; + NR_UE_HARQ_STATUS_t *harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[TST_DL_HARQ_PID_FIRST].harq_ack; harq_status->ack = DL_ACK; @@ -292,7 +292,7 @@ int test_pucch_common_config_single_transport_block(PHY_VARS_NR_UE *ue, int gNB_ ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->current_harq_pid = TST_DL_HARQ_PID_SECOND; - harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[TST_DL_HARQ_PID_SECOND]->harq_ack; + harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[TST_DL_HARQ_PID_SECOND].harq_ack; harq_status->n_CCE = 2; harq_status->N_CCE = 4; @@ -316,7 +316,7 @@ int test_pucch_common_config_single_transport_block(PHY_VARS_NR_UE *ue, int gNB_ v_return = -1; } - ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[TST_DL_HARQ_PID_FIRST]->harq_ack.ack = DL_NACK; + ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[TST_DL_HARQ_PID_FIRST].harq_ack.ack = DL_NACK; printf("\n => Test : PUCCH format from common config in dedicated mode: two negative downlink ACKnowledgments \n"); @@ -467,7 +467,8 @@ void init_pucch_dedicated_configuration(PHY_VARS_NR_UE *ue, uint8_t gNB_id) case 4: p_resource->format_parameters.nrofSymbols = 4+j; p_resource->format_parameters.occ_length = 10+j; - p_resource->format_parameters.occ_Index = 11+j; +// p_resource->format_parameters.occ_Index = 11+j; + p_resource->format_parameters.occ_Index = 0; break; default: LOG_E(PHY,"Unknown format : at line %d in function %s of file %s \n", LINE_FILE , __func__, __FILE__); @@ -555,7 +556,7 @@ int test_pucch_dedicated_single_transport_block(PHY_VARS_NR_UE *ue, int gNB_id, int v_return = 0; int reset_harq = FALSE; int dl_harq_pid[TST_NB_STEP_SINGLE_TRANSPORT_BLOCK] = {TST_DL_HARQ_PID_FIRST, TST_DL_HARQ_PID_SECOND, TST_DL_HARQ_PID_THIRD, TST_DL_HARQ_PID_FOURTH }; - int pucch_resource_indicator[TST_NB_STEP_SINGLE_TRANSPORT_BLOCK][2] = { { 0, 5 }, { 1, 0 } , { 1, 3 } , { 5, 7 } }; + int pucch_resource_indicator[TST_NB_STEP_SINGLE_TRANSPORT_BLOCK][2] = { { 0, 4 }, { 1, 0 } , { 1, 3 } , { 5, 7 } }; NR_UE_HARQ_STATUS_t *harq_status; ue->PDSCH_Config.maxNrofCodeWordsScheduledByDCI = nb_code_n1; @@ -564,7 +565,7 @@ int test_pucch_dedicated_single_transport_block(PHY_VARS_NR_UE *ue, int gNB_id, ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->current_harq_pid = TST_DL_HARQ_PID_FIRST; - harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[TST_DL_HARQ_PID_FIRST]->harq_ack; + harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[TST_DL_HARQ_PID_FIRST].harq_ack; harq_status->slot_for_feedback_ack = proc->nr_tti_tx; harq_status->send_harq_status = 1; @@ -583,7 +584,7 @@ int test_pucch_dedicated_single_transport_block(PHY_VARS_NR_UE *ue, int gNB_id, /* set a tx slot with no ack */ ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->current_harq_pid = dl_harq_pid[i]; - NR_UE_HARQ_STATUS_t *harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[dl_harq_pid[i]]->harq_ack; + NR_UE_HARQ_STATUS_t *harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[dl_harq_pid[i]].harq_ack; harq_status->slot_for_feedback_ack = proc->nr_tti_tx; harq_status->send_harq_status = 1; @@ -617,7 +618,7 @@ int test_pucch_dedicated_single_transport_block(PHY_VARS_NR_UE *ue, int gNB_id, /* set a tx slot with no ack */ ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->current_harq_pid = dl_harq_pid[i]; - NR_UE_HARQ_STATUS_t *harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[dl_harq_pid[i]]->harq_ack; + NR_UE_HARQ_STATUS_t *harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[dl_harq_pid[i]].harq_ack; harq_status->slot_for_feedback_ack = proc->nr_tti_tx; harq_status->send_harq_status = 1; @@ -681,7 +682,7 @@ int test_pucch_dedicated_two_transport_blocks(PHY_VARS_NR_UE *ue, int gNB_id, UE /* set a tx slot with no ack */ ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][code_word]->current_harq_pid = dl_harq_pid[i]; - NR_UE_HARQ_STATUS_t *harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][code_word]->harq_processes[dl_harq_pid[i]]->harq_ack; + NR_UE_HARQ_STATUS_t *harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][code_word]->harq_processes[dl_harq_pid[i]].harq_ack; harq_status->slot_for_feedback_ack = proc->nr_tti_tx; harq_status->send_harq_status = 1; @@ -696,7 +697,7 @@ int test_pucch_dedicated_two_transport_blocks(PHY_VARS_NR_UE *ue, int gNB_id, UE reset_harq = TRUE; } - harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[dl_harq_pid[i]]->harq_ack; + harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[dl_harq_pid[i]].harq_ack; harq_status->pucch_resource_indicator = pucch_resource_indicator[i][j]; @@ -724,7 +725,7 @@ int test_pucch_dedicated_two_transport_blocks(PHY_VARS_NR_UE *ue, int gNB_id, UE /* set a tx slot with no ack */ ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][code_word]->current_harq_pid = dl_harq_pid[i]; - NR_UE_HARQ_STATUS_t *harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][code_word]->harq_processes[dl_harq_pid[i]]->harq_ack; + NR_UE_HARQ_STATUS_t *harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][code_word]->harq_processes[dl_harq_pid[i]].harq_ack; harq_status->slot_for_feedback_ack = proc->nr_tti_tx; harq_status->send_harq_status = 1; @@ -733,7 +734,7 @@ int test_pucch_dedicated_two_transport_blocks(PHY_VARS_NR_UE *ue, int gNB_id, UE for (int j = 0 ; j < 2; j++) { - harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[dl_harq_pid[i]]->harq_ack; + harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[dl_harq_pid[i]].harq_ack; harq_status->pucch_resource_indicator = pucch_resource_indicator[i][j]; } @@ -758,7 +759,7 @@ int test_pucch_dedicated_two_transport_blocks(PHY_VARS_NR_UE *ue, int gNB_id, UE /* set a tx slot with no ack */ ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][code_word]->current_harq_pid = dl_harq_pid[i]; - NR_UE_HARQ_STATUS_t *harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][code_word]->harq_processes[dl_harq_pid[i]]->harq_ack; + NR_UE_HARQ_STATUS_t *harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][code_word]->harq_processes[dl_harq_pid[i]].harq_ack; harq_status->slot_for_feedback_ack = proc->nr_tti_tx; harq_status->send_harq_status = 1; @@ -767,7 +768,7 @@ int test_pucch_dedicated_two_transport_blocks(PHY_VARS_NR_UE *ue, int gNB_id, UE for (int j = 0 ; j < 2; j++) { - harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[dl_harq_pid[i]]->harq_ack; + harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[dl_harq_pid[i]].harq_ack; harq_status->pucch_resource_indicator = pucch_resource_indicator[i][j]; } @@ -977,7 +978,7 @@ int test_sr_ack_dedicated(PHY_VARS_NR_UE *ue, int gNB_id, UE_nr_rxtx_proc_t *pro ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->current_harq_pid = TST_DL_HARQ_PID_FIRST; - harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[TST_DL_HARQ_PID_FIRST]->harq_ack; + harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[TST_DL_HARQ_PID_FIRST].harq_ack; harq_status->slot_for_feedback_ack = proc->nr_tti_tx; harq_status->send_harq_status = 1; @@ -1016,7 +1017,7 @@ int test_sr_ack_dedicated(PHY_VARS_NR_UE *ue, int gNB_id, UE_nr_rxtx_proc_t *pro ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->current_harq_pid = TST_DL_HARQ_PID_SECOND; - harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[TST_DL_HARQ_PID_SECOND]->harq_ack; + harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[TST_DL_HARQ_PID_SECOND].harq_ack; harq_status->slot_for_feedback_ack = proc->nr_tti_tx; harq_status->send_harq_status = 1; @@ -1091,7 +1092,7 @@ int test_csi_dedicated(PHY_VARS_NR_UE *ue, int gNB_id, UE_nr_rxtx_proc_t *proc) ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->current_harq_pid = TST_DL_HARQ_PID_FIRST; - harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[TST_DL_HARQ_PID_FIRST]->harq_ack; + harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[TST_DL_HARQ_PID_FIRST].harq_ack; harq_status->slot_for_feedback_ack = proc->nr_tti_tx; harq_status->send_harq_status = 1; diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 7e5e00c066..448af8651b 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -46,6 +46,152 @@ uint32_t get_ssb_slot(uint32_t ssb_index){ // return first_symbol(case, freq, ssb_index) / 14 } +uint8_t table_9_2_2_1[16][8]={ +{0,12,2, 0, 0,3,0,0}, +{0,12,2, 0, 0,4,8,0}, +{0,12,2, 3, 0,4,8,0}, +{1,10,4, 0, 0,6,0,0}, +{1,10,4, 0, 0,3,6,9}, +{1,10,4, 2, 0,3,6,9}, +{1,10,4, 4, 0,3,6,9}, +{1,4, 10,0, 0,6,0,0}, +{1,4, 10,0, 0,3,6,9}, +{1,4, 10,2, 0,3,6,9}, +{1,4, 10,4, 0,3,6,9}, +{1,0, 14,0, 0,6,0,0}, +{1,0, 14,0, 0,3,6,9}, +{1,0, 14,2, 0,3,6,9}, +{1,0, 14,4, 0,3,6,9}, +{1,0, 14,26,0,3,0,0} +}; +int8_t nr_ue_process_dlsch(module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_indication_t *dci_ind, void *pduP, uint32_t pdu_len){ + + NR_UE_MAC_INST_t *mac = get_mac_inst(module_id); + fapi_nr_ul_config_request_t *ul_config = &mac->ul_config_request; + fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request; + nr_phy_config_t *phy_config = &mac->phy_config; + + //ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.rnti = rnti; + // First we need to verify if DCI ind contains a ul-sch to be perfomred. If it does, we will handle a PUSCH in the UL_CONFIG_REQ. + ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUCCH; + for (int i=0; i<10; i++) { + if (dci_ind->dci_list[i].dci_format < 2) ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH; + } + if (ul_config->ul_config_list[ul_config->number_pdus].pdu_type == FAPI_NR_UL_CONFIG_TYPE_PUSCH) { + // fill in the elements in config request inside P5 message + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.bandwidth_part_ind = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.number_rbs = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.start_rb = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.frame_offset = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.number_symbols = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.start_symbol = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.pusch_freq_hopping = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.mcs = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.ndi = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.rv = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.harq_process_nbr = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.accumulated_delta_PUSCH = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.absolute_delta_PUSCH = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.n_layers = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.tpmi = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.n_dmrs_cdm_groups = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.dmrs_ports[4] = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.n_front_load_symb = 0; + //ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.srs_config = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.csi_reportTriggerSize = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.maxCodeBlockGroupsPerTransportBlock = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.ptrs_dmrs_association_port = 0; + ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.beta_offset_ind = 0; + } else { // If DCI ind is not format 0_0 or 0_1, we will handle a PUCCH in the UL_CONFIG_REQ + ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUCCH; + // If we handle PUCCH common + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.format = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][0]; /* format 0 1 2 3 4 */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.initialCyclicShift = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][4]; /* x x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSymbols = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][2]; /* x x x x x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.startingSymbolIndex = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][1]; /* x x x x x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.timeDomainOCC = 0; /* x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofPRBs = 0; /* x x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.startingPRB = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][3]; /* maxNrofPhysicalResourceBlocks = 275 */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.occ_length = 0; /* x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.occ_Index = 0; /* x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.intraSlotFrequencyHopping = 0; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.secondHopPRB = 0; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = 0; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS = 0; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate = 0; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots = 0; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK = 0; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI = 0; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pucch_GroupHopping = phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_group_hopping; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.hoppingId = phy_config->config_req.ul_bwp_common.pucch_config_common.hopping_id; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_nominal = phy_config->config_req.ul_bwp_common.pucch_config_common.p0_nominal; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.deltaF_PUCCH_f[NUMBER_PUCCH_FORMAT_NR] = 0; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_PUCCH_Id = 0; /* INTEGER (1..8) */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_PUCCH_Value = 0; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.twoPUCCH_PC_AdjustmentStates = 0; + // If we handle PUCCH dedicated + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.format = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].format; /* format 0 1 2 3 4 */ + switch (ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.format){ + case pucch_format1_nr: + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.inter_slot_frequency_hopping; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.additional_dmrs; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.max_code_rate; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.number_of_slots; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.pi2bpsk; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.simultaneous_harq_ack_csi; + break; + case pucch_format2_nr: + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.inter_slot_frequency_hopping; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.additional_dmrs; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.max_code_rate; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.number_of_slots; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.pi2bpsk; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.simultaneous_harq_ack_csi; + break; + case pucch_format3_nr: + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.inter_slot_frequency_hopping; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.additional_dmrs; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.max_code_rate; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.number_of_slots; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.pi2bpsk; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.simultaneous_harq_ack_csi; + break; + case pucch_format4_nr: + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.inter_slot_frequency_hopping; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.additional_dmrs; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.max_code_rate; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.number_of_slots; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.pi2bpsk; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.simultaneous_harq_ack_csi; + break; + default: + break; + } + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.initialCyclicShift = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].initial_cyclic_shift; /* x x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSymbols = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].number_of_symbols; /* x x x x x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.startingSymbolIndex = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].starting_symbol_index; /* x x x x x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.timeDomainOCC = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].time_domain_occ; /* x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofPRBs = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].number_of_prbs; /* x x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.startingPRB = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].starting_prb; /* maxNrofPhysicalResourceBlocks = 275 */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.occ_length = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].occ_length; /* x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.occ_Index = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].occ_index; /* x */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.intraSlotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].intra_slot_frequency_hopping; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.secondHopPRB = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].second_hop_prb; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pucch_GroupHopping = phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_group_hopping; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.hoppingId = phy_config->config_req.ul_bwp_common.pucch_config_common.hopping_id; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_nominal = phy_config->config_req.ul_bwp_common.pucch_config_common.p0_nominal; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.deltaF_PUCCH_f[NUMBER_PUCCH_FORMAT_NR] = 0; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_PUCCH_Id = 0; /* INTEGER (1..8) */ + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_PUCCH_Value = 0; + ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.twoPUCCH_PC_AdjustmentStates = 0; + + } + if(mac->if_module != NULL && mac->if_module->ul_indication != NULL){ + mac->if_module->ul_indication(&mac->scheduled_response); + } + return 0; +} + int8_t nr_ue_decode_mib( module_id_t module_id, int cc_id, diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c index 7f4975defc..282a15ca47 100644 --- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c @@ -64,6 +64,18 @@ int8_t handle_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_d return nr_ue_process_dci(module_id, cc_id, gNB_index, dci, rnti, dci_type); +} +// L2 Abstraction Layer +int8_t handle_dlsch (module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_indication_t *dci_ind, uint8_t *pduP, uint32_t pdu_len){ + +// return 0; + return nr_ue_process_dlsch( module_id, + cc_id, + gNB_index, + &dci_ind, + pduP, + pdu_len); + } int8_t nr_ue_ul_indication(nr_uplink_indication_t *ul_info){ @@ -115,36 +127,6 @@ int8_t nr_ue_dl_indication(nr_downlink_indication_t *dl_info){ // clean up scheduled_response structure - if(dl_info->rx_ind != NULL){ - printf("[L2][IF MODULE][DL INDICATION][RX_IND]\n"); - for(i=0; irx_ind->number_pdus; ++i){ - switch(dl_info->rx_ind->rx_indication_body[i].pdu_type){ - case FAPI_NR_RX_PDU_TYPE_MIB: - ret_mask |= (handle_bcch_bch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, - (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.pdu, - (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.additional_bits, - (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.ssb_index, - (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.ssb_length, - (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.cell_id )) << FAPI_NR_RX_PDU_TYPE_MIB; - break; - case FAPI_NR_RX_PDU_TYPE_SIB: - ret_mask |= (handle_bcch_dlsch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, - (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.sibs_mask, - (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.pdu, - (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.pdu_length )) << FAPI_NR_RX_PDU_TYPE_SIB; - break; - case FAPI_NR_RX_PDU_TYPE_DLSCH: - ret_mask |= (0) << FAPI_NR_RX_PDU_TYPE_DLSCH; - break; - default: - - break; - - } - } - } - - if(dl_info->dci_ind != NULL){ printf("[L2][IF MODULE][DL INDICATION][DCI_IND]\n"); @@ -208,6 +190,40 @@ int8_t nr_ue_dl_indication(nr_downlink_indication_t *dl_info){ } } + if(dl_info->rx_ind != NULL){ + printf("[L2][IF MODULE][DL INDICATION][RX_IND]\n"); + for(i=0; irx_ind->number_pdus; ++i){ + switch(dl_info->rx_ind->rx_indication_body[i].pdu_type){ + case FAPI_NR_RX_PDU_TYPE_MIB: + ret_mask |= (handle_bcch_bch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, + (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.pdu, + (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.additional_bits, + (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.ssb_index, + (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.ssb_length, + (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.cell_id )) << FAPI_NR_RX_PDU_TYPE_MIB; + break; + case FAPI_NR_RX_PDU_TYPE_SIB: + ret_mask |= (handle_bcch_dlsch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, + (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.sibs_mask, + (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.pdu, + (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.pdu_length )) << FAPI_NR_RX_PDU_TYPE_SIB; + break; + case FAPI_NR_RX_PDU_TYPE_DLSCH: +// ret_mask |= (0) << FAPI_NR_RX_PDU_TYPE_DLSCH; + ret_mask |= (handle_dlsch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, &dl_info->dci_ind, + (dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu, + (dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu_length)) << FAPI_NR_RX_PDU_TYPE_DLSCH; + + break; + default: + + break; + + } + } + } + + AssertFatal( nr_ue_if_module_inst[module_id] != NULL, "IF module is void!\n" ); nr_ue_if_module_inst[module_id]->scheduled_response(&mac->scheduled_response);