From 2b698b77e45dc42805c9738c3f185c2c5de31880 Mon Sep 17 00:00:00 2001 From: Melissa Elkadi Date: Fri, 11 Jun 2021 12:39:01 -0700 Subject: [PATCH] CFRA procedure success commit pt. 2 This commit includes the changes made to gNB. All of these changes were cherry picked from the Eurecom/develop branch to ensure the CFRA procedure is working. Without these changes there were several seg. faults. --- .../LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c | 16 +- .../LAYER2/NR_MAC_gNB/gNB_scheduler_uci.c | 137 ++++++++--------- .../LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c | 140 +++++++++++++----- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 2 +- 4 files changed, 165 insertions(+), 130 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c index eaec52bf70..5199123785 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c @@ -454,8 +454,8 @@ void pf_dl(module_id_t module_id, } /* Find PUCCH occasion: if it fails, undo CCE allocation (undoing PUCCH * allocation after CCE alloc fail would be more complex) */ - const bool alloc = nr_acknack_scheduling(module_id, UE_id, frame, slot); - if (!alloc) { + const int alloc = nr_acknack_scheduling(module_id, UE_id, frame, slot); + if (alloc < 0) { LOG_W(MAC, "%s(): could not find PUCCH for UE %d/%04x@%d.%d\n", __func__, @@ -547,8 +547,8 @@ void pf_dl(module_id_t module_id, /* Find PUCCH occasion: if it fails, undo CCE allocation (undoing PUCCH * allocation after CCE alloc fail would be more complex) */ - const bool alloc = nr_acknack_scheduling(module_id, UE_id, frame, slot); - if (!alloc) { + const int alloc = nr_acknack_scheduling(module_id, UE_id, frame, slot); + if (alloc < 0) { LOG_W(MAC, "%s(): could not find PUCCH for UE %d/%04x@%d.%d\n", __func__, @@ -824,14 +824,6 @@ void nr_schedule_ue_spec(module_id_t module_id, pdsch_pdu->mcsIndex[0] = sched_ctrl->mcs; pdsch_pdu->mcsTable[0] = sched_ctrl->mcsTableIdx; pdsch_pdu->rvIndex[0] = nr_rv_round_map[harq->round]; - if (NFAPI_MODE == NFAPI_MODE_VNF){ // done since uplink isnt operational yet which means harq structures dont get filled properly - pdsch_pdu->rvIndex[0] = nr_rv_round_map[harq_rounds]; - if (harq_rounds % 5 == 0 && harq_rounds!=0){ - harq_rounds = 0; - harq_pid = (harq_pid + 1) % 16; - } - harq_rounds++; - } pdsch_pdu->TBSize[0] = TBS; pdsch_pdu->dataScramblingId = *scc->physCellId; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_uci.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_uci.c index fc1fa04948..360ef7c565 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_uci.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_uci.c @@ -427,10 +427,14 @@ void handle_nr_uci_pucch_2_3_4(module_id_t mod_id, // function to update pucch scheduling parameters in UE list when a USS DL is scheduled -bool nr_acknack_scheduling(int mod_id, - int UE_id, - frame_t frame, - sub_frame_t slot) +// this function returns an index to NR_sched_pucch structure +// currently this structure contains PUCCH0 at index 0 and PUCCH2 at index 1 +// if the function returns -1 it was not possible to schedule acknack +// when current pucch is ready to be scheduled nr_fill_nfapi_pucch is called +int nr_acknack_scheduling(int mod_id, + int UE_id, + frame_t frame, + sub_frame_t slot) { const NR_ServingCellConfigCommon_t *scc = RC.nrmac[mod_id]->common_channels->ServingCellConfigCommon; const int n_slots_frame = nr_slots_per_frame[*scc->ssbSubcarrierSpacing]; @@ -440,6 +444,7 @@ bool nr_acknack_scheduling(int mod_id, const int nr_slots_period = tdd->nrofDownlinkSlots + tdd->nrofUplinkSlots + nr_mix_slots; const int first_ul_slot_tdd = tdd->nrofDownlinkSlots + nr_slots_period * (slot / nr_slots_period); const int CC_id = 0; + NR_sched_pucch_t *csi_pucch; AssertFatal(slot < first_ul_slot_tdd + (tdd->nrofUplinkSymbols != 0), "cannot handle multiple TDD periods (yet): slot %d first_ul_slot_tdd %d nrofUplinkSlots %ld\n", @@ -452,55 +457,34 @@ bool nr_acknack_scheduling(int mod_id, * * we do not multiplex with CSI, which is always in pucch_sched[2] * * SR uses format 0 and is allocated in the first UL (mixed) slot (and not * later) - * * that the PUCCH resource set 0 (for up to 2 bits) points to the first N - * PUCCH resources, where N is the number of resources in the PUCCH - * resource set. This is used in pucch_index_used, which counts the used - * resources by index, and not by their ID! */ + * * each UE has dedicated PUCCH Format 0 resources, and we use index 0! */ NR_UE_sched_ctrl_t *sched_ctrl = &RC.nrmac[mod_id]->UE_info.UE_sched_ctrl[UE_id]; NR_sched_pucch_t *pucch = &sched_ctrl->sched_pucch[0]; AssertFatal(pucch->csi_bits == 0, "%s(): csi_bits %d in sched_pucch[0]\n", __func__, pucch->csi_bits); - - const int max_acknacks = 2; - AssertFatal(pucch->dai_c + pucch->sr_flag <= max_acknacks, - "illegal number of bits in PUCCH of UE %d\n", - UE_id); /* if the currently allocated PUCCH of this UE is full, allocate it */ - if (NFAPI_MODE == NFAPI_MODE_VNF) - pucch->sr_flag = 1; pucch->dai_c = 1; - if (pucch->sr_flag + pucch->dai_c == max_acknacks) { + if (pucch->dai_c == 2) { /* advance the UL slot information in PUCCH by one so we won't schedule in * the same slot again */ const int f = pucch->frame; const int s = pucch->ul_slot; - if(NFAPI_MODE == NFAPI_MODE_VNF){ - gNB_MAC_INST *gNB = RC.nrmac[mod_id]; - gNB->UL_tti_req_ahead[0][7].SFN = f;//Added to set the UL_tti_req_ahead SFN in VNF mode for slot 7 - gNB->UL_tti_req_ahead[0][8].SFN = f;//Added to set the UL_tti_req_ahead SFN in VNF mode for slot 8 - gNB->UL_tti_req_ahead[0][9].SFN = f;//Added to set the UL_tti_req_ahead SFN in VNF mode for slot 9 - gNB->UL_tti_req[0] = &gNB->UL_tti_req_ahead[0][slot]; - } nr_fill_nfapi_pucch(mod_id, frame, slot, pucch, UE_id); memset(pucch, 0, sizeof(*pucch)); pucch->frame = s == n_slots_frame - 1 ? (f + 1) % 1024 : f; pucch->ul_slot = (s + 1) % n_slots_frame; // we assume that only two indices over the array sched_pucch exist - const NR_sched_pucch_t *csi_pucch = &sched_ctrl->sched_pucch[2]; + csi_pucch = &sched_ctrl->sched_pucch[1]; // skip the CSI PUCCH if it is present and if in the next frame/slot + // and if we don't multiplex if (csi_pucch->csi_bits > 0 && csi_pucch->frame == pucch->frame - && csi_pucch->ul_slot == pucch->ul_slot) { - AssertFatal(!csi_pucch->simultaneous_harqcsi, - "%s(): %d.%d cannot handle simultaneous_harqcsi, but found for UE %d\n", - __func__, - pucch->frame, - pucch->ul_slot, - UE_id); + && csi_pucch->ul_slot == pucch->ul_slot + && !csi_pucch->simultaneous_harqcsi) { nr_fill_nfapi_pucch(mod_id, frame, slot, csi_pucch, UE_id); + memset(csi_pucch, 0, sizeof(*csi_pucch)); pucch->frame = s >= n_slots_frame - 2 ? (f + 1) % 1024 : f; - printf("pucch frame filled. \n"); pucch->ul_slot = (s + 2) % n_slots_frame; } } @@ -511,16 +495,15 @@ bool nr_acknack_scheduling(int mod_id, if ((pucch->frame == frame && (pucch->ul_slot >= first_ul_slot_tdd + nr_ulmix_slots)) || (pucch->frame == frame + 1)) - return false; + return -1; // this is hardcoded for now as ue specific NR_SearchSpace__searchSpaceType_PR ss_type = NR_SearchSpace__searchSpaceType_PR_ue_Specific; uint8_t pdsch_to_harq_feedback[8]; get_pdsch_to_harq_feedback(mod_id, UE_id, ss_type, pdsch_to_harq_feedback); - /* there is a scheduled SR or HARQ. Check whether we can use it for this - * ACKNACK */ - if (pucch->sr_flag + pucch->dai_c > 0) { + /* there is a HARQ. Check whether we can use it for this ACKNACK */ + if (pucch->dai_c > 0) { /* this UE already has a PUCCH occasion */ DevAssert(pucch->frame == frame); @@ -546,23 +529,19 @@ bool nr_acknack_scheduling(int mod_id, pucch->timing_indicator = i; pucch->dai_c++; // retain old resource indicator, and we are good - return true; + return 0; } /* we need to find a new PUCCH occasion */ - NR_PUCCH_Config_t *pucch_Config = sched_ctrl->active_ubwp->bwp_Dedicated->pucch_Config->choice.setup; - DevAssert(pucch_Config->resourceToAddModList->list.count > 0); - DevAssert(pucch_Config->resourceSetToAddModList->list.count > 0); - const int n_res = pucch_Config->resourceSetToAddModList->list.array[0]->resourceList.list.count; - int *pucch_index_used = RC.nrmac[mod_id]->pucch_index_used[sched_ctrl->active_ubwp->bwp_Id]; - /* if time information is outdated (e.g., last PUCCH occasion in last frame), * set to first possible UL occasion in this frame. Note that if such UE is * scheduled a lot and used all AckNacks, pucch->frame might have been * wrapped around to next frame */ if (frame != pucch->frame || pucch->ul_slot < first_ul_slot_tdd) { - DevAssert(pucch->sr_flag + pucch->dai_c == 0); + AssertFatal(pucch->sr_flag + pucch->dai_c == 0, + "expected no SR/AckNack for UE %d in %4d.%2d, but has %d/%d for %4d.%2d\n", + UE_id, frame, slot, pucch->sr_flag, pucch->dai_c, pucch->frame, pucch->ul_slot); AssertFatal(frame + 1 != pucch->frame, "frame wrap around not handled in %s() yet\n", __func__); @@ -570,22 +549,6 @@ bool nr_acknack_scheduling(int mod_id, pucch->ul_slot = first_ul_slot_tdd; } - // increase to first slot in which PUCCH resources are available - while (pucch_index_used[pucch->ul_slot] >= n_res) { - pucch->ul_slot++; - /* if there is no free resource anymore, abort search */ - if ((pucch->frame == frame - && pucch->ul_slot >= first_ul_slot_tdd + nr_ulmix_slots) - || (pucch->frame == frame + 1)) { - LOG_E(MAC, - "%4d.%2d no free PUCCH resources anymore while searching for UE %d\n", - frame, - slot, - UE_id); - return false; - } - } - // advance ul_slot if it is not reachable by UE pucch->ul_slot = max(pucch->ul_slot, slot + pdsch_to_harq_feedback[0]); @@ -604,37 +567,57 @@ bool nr_acknack_scheduling(int mod_id, slot, UE_id, pucch->ul_slot); - return false; + return -1; } + + // is there already CSI in this slot? + csi_pucch = &sched_ctrl->sched_pucch[1]; + if (csi_pucch->csi_bits > 0 + && csi_pucch->frame == pucch->frame + && csi_pucch->ul_slot == pucch->ul_slot) { + // skip the CSI PUCCH if it is present and if in the next frame/slot + // and if we don't multiplex + // FIXME currently we support at most 11 bits in pucch2 so skip also in that case + if(!csi_pucch->simultaneous_harqcsi + || ((csi_pucch->csi_bits + csi_pucch->dai_c) >= 11)) { + nr_fill_nfapi_pucch(mod_id, frame, slot, csi_pucch, UE_id); + memset(csi_pucch, 0, sizeof(*csi_pucch)); + /* advance the UL slot information in PUCCH by one so we won't schedule in + * the same slot again */ + const int f = pucch->frame; + const int s = pucch->ul_slot; + memset(pucch, 0, sizeof(*pucch)); + pucch->frame = s == n_slots_frame - 1 ? (f + 1) % 1024 : f; + pucch->ul_slot = (s + 1) % n_slots_frame; + return nr_acknack_scheduling(mod_id, UE_id, frame, slot); + } + // multiplexing harq and csi in a pucch + else { + csi_pucch->timing_indicator = i; + csi_pucch->dai_c++; + return 1; + } + } + pucch->timing_indicator = i; // index in the list of timing indicators pucch->dai_c++; - const int pucch_res = pucch_index_used[pucch->ul_slot]; - pucch->resource_indicator = pucch_res; - pucch_index_used[pucch->ul_slot] += 1; - AssertFatal(pucch_index_used[pucch->ul_slot] <= n_res, - "UE %d in %4d.%2d: pucch_index_used is %d (%d available)\n", - UE_id, - pucch->frame, - pucch->ul_slot, - pucch_index_used[pucch->ul_slot], - n_res); + pucch->resource_indicator = 0; // each UE has dedicated PUCCH resources /* verify that at that slot and symbol, resources are free. We only do this * for initialCyclicShift 0 (we assume it always has that one), so other * initialCyclicShifts can overlap with ICS 0!*/ - const NR_PUCCH_Resource_t *resource = - pucch_Config->resourceToAddModList->list.array[pucch_res]; + const NR_PUCCH_Config_t *pucch_Config = sched_ctrl->active_ubwp->bwp_Dedicated->pucch_Config->choice.setup; + const NR_PUCCH_Resource_t *resource = pucch_Config->resourceToAddModList->list.array[pucch->resource_indicator]; DevAssert(resource->format.present == NR_PUCCH_Resource__format_PR_format0); if (resource->format.choice.format0->initialCyclicShift == 0) { uint16_t *vrb_map_UL = &RC.nrmac[mod_id]->common_channels[CC_id].vrb_map_UL[pucch->ul_slot * MAX_BWP_SIZE]; const uint16_t symb = 1 << resource->format.choice.format0->startingSymbolIndex; - AssertFatal((vrb_map_UL[resource->startingPRB] & symb) == 0, - "symbol %x is not free for PUCCH alloc in vrb_map_UL at RB %ld and slot %d\n", - symb, resource->startingPRB, pucch->ul_slot); + if ((vrb_map_UL[resource->startingPRB] & symb) != 0) + LOG_W(MAC, "symbol 0x%x is not free for PUCCH alloc in vrb_map_UL at RB %ld and slot %d.%d\n", symb, resource->startingPRB, pucch->frame, pucch->ul_slot); vrb_map_UL[resource->startingPRB] |= symb; } - return true; + return 0; } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c index 44993bf294..99dca6b269 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c @@ -396,7 +396,7 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP, T_BUFFER(sduP, sdu_lenP)); UE_info->mac_stats[UE_id].ulsch_total_bytes_rx += sdu_lenP; - LOG_D(MAC, "[gNB %d][PUSCH %d] CC_id %d %d.%d Received ULSCH sdu from PHY (rnti %x, UE_id %d) ul_cqi %d sduP %p\n", + LOG_D(NR_MAC, "[gNB %d][PUSCH %d] CC_id %d %d.%d Received ULSCH sdu from PHY (rnti %x, UE_id %d) ul_cqi %d sduP %p\n", gnb_mod_idP, harq_pid, CC_idP, @@ -432,7 +432,7 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP, #endif if (sduP != NULL){ - LOG_D(MAC, "Received PDU at MAC gNB \n"); + LOG_D(NR_MAC, "Received PDU at MAC gNB \n"); const uint32_t tb_size = UE_scheduling_control->ul_harq_processes[harq_pid].sched_pusch.tb_size; UE_scheduling_control->sched_ul_bytes -= tb_size; @@ -441,19 +441,19 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP, nr_process_mac_pdu(gnb_mod_idP, current_rnti, CC_idP, frameP, sduP, sdu_lenP); } - else { - NR_UE_ul_harq_t *cur_harq = &UE_scheduling_control->ul_harq_processes[harq_pid]; - /* reduce sched_ul_bytes when cur_harq->round == 3 */ - if (cur_harq->round == 3){ - const uint32_t tb_size = UE_scheduling_control->ul_harq_processes[harq_pid].sched_pusch.tb_size; - UE_scheduling_control->sched_ul_bytes -= tb_size; - if (UE_scheduling_control->sched_ul_bytes < 0) - UE_scheduling_control->sched_ul_bytes = 0; + } else if(sduP) { + + bool no_sig = true; + for (int k = 0; k < sdu_lenP; k++) { + if(sduP[k]!=0) { + no_sig = false; + break; } } - } else { - if (!sduP) // check that CRC passed - return; + + if(no_sig) { + LOG_W(NR_MAC, "No signal\n"); + } T(T_GNB_MAC_UL_PDU_WITH_DATA, T_INT(gnb_mod_idP), T_INT(CC_idP), T_INT(rntiP), T_INT(frameP), T_INT(slotP), T_INT(-1) /* harq_pid */, @@ -467,38 +467,93 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP, if (ra->state != WAIT_Msg3) continue; - // random access pusch with TC-RNTI - if (ra->rnti != current_rnti) { - LOG_W(MAC, - "expected TC-RNTI %04x to match current RNTI %04x\n", + if(no_sig) { + LOG_W(NR_MAC, "Random Access %i failed at state %i\n", i, ra->state); + //nr_mac_remove_ra_rnti(gnb_mod_idP, ra->rnti); + nr_clear_ra_proc(gnb_mod_idP, CC_idP, frameP); + } else { + + // random access pusch with TC-RNTI + if (ra->rnti != current_rnti) { + LOG_W(NR_MAC, + "expected TC_RNTI %04x to match current RNTI %04x\n", + ra->rnti, + current_rnti); + + if( (frameP==ra->Msg3_frame) && (slotP==ra->Msg3_slot) ) { + LOG_W(NR_MAC, "Random Access %i failed at state %i\n", i, ra->state); + //nr_mac_remove_ra_rnti(gnb_mod_idP, ra->rnti); + nr_clear_ra_proc(gnb_mod_idP, CC_idP, frameP); + } + + continue; + } + + const int UE_id = add_new_nr_ue(gnb_mod_idP, ra->rnti, ra->secondaryCellGroup); + UE_info->UE_beam_index[UE_id] = ra->beam_id; + + // re-initialize ta update variables after RA procedure completion + UE_info->UE_sched_ctrl[UE_id].ta_frame = frameP; + + LOG_I(NR_MAC, + "reset RA state information for RA-RNTI %04x/index %d\n", ra->rnti, - current_rnti); - continue; + i); + + LOG_I(NR_MAC, + "[gNB %d][RAPROC] PUSCH with TC_RNTI %x received correctly, " + "adding UE MAC Context UE_id %d/RNTI %04x\n", + gnb_mod_idP, + current_rnti, + UE_id, + ra->rnti); + + if(ra->cfra) { + + LOG_I(NR_MAC, "(ue %i, rnti 0x%04x) CFRA procedure succeeded!\n", UE_id, ra->rnti); + //nr_mac_remove_ra_rnti(gnb_mod_idP, ra->rnti); + nr_clear_ra_proc(gnb_mod_idP, CC_idP, frameP); + UE_info->active[UE_id] = true; + + } else { + + LOG_I(NR_MAC,"[RAPROC] RA-Msg3 received (sdu_lenP %d)\n",sdu_lenP); + LOG_D(NR_MAC,"[RAPROC] Received Msg3:\n"); + for (int k = 0; k < sdu_lenP; k++) { + LOG_D(NR_MAC,"(%i): 0x%x\n",k,sduP[k]); + } + + // UE Contention Resolution Identity + // Store the first 48 bits belonging to the uplink CCCH SDU within Msg3 to fill in Msg4 + // First byte corresponds to R/LCID MAC sub-header + memcpy(ra->cont_res_id, &sduP[1], sizeof(uint8_t) * 6); + + nr_process_mac_pdu(gnb_mod_idP, current_rnti, CC_idP, frameP, sduP, sdu_lenP); + + ra->state = Msg4; + ra->Msg4_frame = ( frameP +2 ) % 1024; + ra->Msg4_slot = 1; + LOG_I(NR_MAC, "Scheduling RA-Msg4 for TC_RNTI %04x (state %d, frame %d, slot %d)\n", ra->rnti, ra->state, ra->Msg4_frame, ra->Msg4_slot); + + } + return; + } - const int UE_id = add_new_nr_ue(gnb_mod_idP, ra->rnti, ra->secondaryCellGroup); - UE_info->UE_beam_index[UE_id] = ra->beam_id; - LOG_I(MAC, - "[gNB %d][RAPROC] PUSCH with TC_RNTI %x received correctly, " - "adding UE MAC Context UE_id %d/RNTI %04x\n", - gnb_mod_idP, - current_rnti, - UE_id, - ra->rnti); - // re-initialize ta update variables afrer RA procedure completion - UE_info->UE_sched_ctrl[UE_id].ta_frame = frameP; + } + } else { + for (int i = 0; i < NR_NB_RA_PROC_MAX; ++i) { + NR_RA_t *ra = &gNB_mac->common_channels[CC_idP].ra[i]; + if (ra->state != WAIT_Msg3) + continue; - free(ra->preambles.preamble_list); - ra->state = RA_IDLE; - LOG_I(MAC, - "reset RA state information for RA-RNTI %04x/index %d\n", - ra->rnti, - i); - - return; + LOG_W(NR_MAC, "Random Access %i failed at state %i\n", i, ra->state); + //nr_mac_remove_ra_rnti(gnb_mod_idP, ra->rnti); + nr_clear_ra_proc(gnb_mod_idP, CC_idP, frameP); } } } + long get_K2(NR_BWP_Uplink_t *ubwp, int time_domain_assignment, int mu) { DevAssert(ubwp); const NR_PUSCH_TimeDomainResourceAllocation_t *tda_list = ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[time_domain_assignment]; @@ -810,12 +865,16 @@ bool nr_simple_ulsch_preprocessor(module_id_t module_id, uint16_t *vrb_map_UL = &RC.nrmac[module_id]->common_channels[CC_id].vrb_map_UL[sched_slot * MAX_BWP_SIZE]; const uint16_t bwpSize = NRRIV2BW(sched_ctrl->active_ubwp->bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE); + const int startSymbolAndLength = tdaList->list.array[tda]->startSymbolAndLength; + int startSymbolIndex, nrOfSymbols; + SLIV2SL(startSymbolAndLength, &startSymbolIndex, &nrOfSymbols); + const uint16_t symb = ((1 << nrOfSymbols) - 1) << startSymbolIndex; int st = 0, e = 0, len = 0; for (int i = 0; i < bwpSize; i++) { - while (vrb_map_UL[i] == 1) + while ((vrb_map_UL[i] & symb) != 0 && i < bwpSize) i++; st = i; - while (vrb_map_UL[i] == 0) + while ((vrb_map_UL[i] & symb) == 0 && i < bwpSize) i++; if (i - st > len) { len = i - st; @@ -824,6 +883,7 @@ bool nr_simple_ulsch_preprocessor(module_id_t module_id, } st = e - len + 1; + uint8_t rballoc_mask[bwpSize]; /* Calculate mask: if any RB in vrb_map_UL is blocked (1), the current RB will be 0 */ diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index 3502a11580..ee17a230bb 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -189,7 +189,7 @@ void nr_csi_meas_reporting(int Mod_idP, frame_t frameP, sub_frame_t slotP); -bool nr_acknack_scheduling(int Mod_idP, +int nr_acknack_scheduling(int Mod_idP, int UE_id, frame_t frameP, sub_frame_t slotP);