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more debugging of RA procedure for eMTC

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This commit is contained in:
Raymond Knopp
2017-11-19 12:09:52 +01:00
parent 97097a8c49
commit 2d97eb4b34
5 changed files with 368 additions and 373 deletions
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openair1/PHY/LTE_TRANSPORT/dci_tools.c
+18 -6
View File
@@ -1065,7 +1065,7 @@ fill_dci_and_dlsch (PHY_VARS_eNB * eNB, eNB_rxtx_proc_t * proc, DCI_ALLOC_t * dc
dlsch0->subframe_tx[subframe] = 1; dlsch0->subframe_tx[subframe] = 1;
if (dlsch0->rnti != rel8->rnti) { // if rnti of dlsch is not the same as in the config, this is a new entry if (dlsch0->rnti != rel8->rnti) { // if rnti of dlsch is not the same as in the config, this is a new entry
dlsch0_harq->round = 0; dlsch0_harq->round = 0;
dlsch0->harq_mask = 0; dlsch0->harq_mask =0;
} }
if ((dlsch0->harq_mask & (1 << rel8->harq_process)) > 0) { if ((dlsch0->harq_mask & (1 << rel8->harq_process)) > 0) {
if (rel8->new_data_indicator_1 != dlsch0_harq->ndi) if (rel8->new_data_indicator_1 != dlsch0_harq->ndi)
@@ -2353,30 +2353,42 @@ fill_mdci_and_dlsch (PHY_VARS_eNB * eNB, eNB_rxtx_proc_t * proc, mDCI_ALLOC_t *
dlsch0_harq->dl_power_off = 1; dlsch0_harq->dl_power_off = 1;
dlsch0->active = 1;
dlsch0->harq_mask |= (1 << rel13->harq_process);
dlsch0->subframe_tx[subframe] = 1;
if (dlsch0->rnti != rel13->rnti) { // if rnti of dlsch is not the same as in the config, this is a new entry
dlsch0_harq->round = 0;
dlsch0->harq_mask =0;
}
if ((dlsch0->harq_mask & (1 << rel13->harq_process)) > 0) {
if (rel13->new_data_indicator != dlsch0_harq->ndi)
dlsch0_harq->round = 0;
} else { // process is inactive, so activate and set round to 0
dlsch0_harq->round = 0;
}
dlsch0_harq->ndi = rel13->new_data_indicator;
if (dlsch0_harq->round == 0) { if (dlsch0_harq->round == 0) {
dlsch0_harq->status = ACTIVE; dlsch0_harq->status = ACTIVE;
// printf("Setting DLSCH process %d to ACTIVE\n",rel8->harq_process);
// MCS and TBS don't change across HARQ rounds // MCS and TBS don't change across HARQ rounds
dlsch0_harq->mcs = rel13->mcs;
dlsch0_harq->TBS = TBStable[get_I_TBS (dlsch0_harq->mcs)][dlsch0_harq->nb_rb - 1]; dlsch0_harq->TBS = TBStable[get_I_TBS (dlsch0_harq->mcs)][dlsch0_harq->nb_rb - 1];
} }
dlsch0->active = 1;
dlsch0->harq_mask |= (1 << rel13->harq_process);
dlsch0->harq_ids[(subframe + 2) % 10] = rel13->harq_process; dlsch0->harq_ids[(subframe + 2) % 10] = rel13->harq_process;
dlsch0_harq->frame = (subframe >= 8) ? ((frame + 1) & 1023) : frame; dlsch0_harq->frame = (subframe >= 8) ? ((frame + 1) & 1023) : frame;
dlsch0_harq->subframe = (subframe + 2) % 10; dlsch0_harq->subframe = (subframe + 2) % 10;
dlsch0->harq_ids[dlsch0_harq->subframe] = rel13->harq_process;
dlsch0_harq->pdsch_start = rel13->start_symbol; dlsch0_harq->pdsch_start = rel13->start_symbol;
LOG_I(PHY,"Setting DLSCH harq %d to active for %d.%d\n",rel13->harq_process,dlsch0_harq->frame,dlsch0_harq->subframe); LOG_I(PHY,"Setting DLSCH harq %d to active for %d.%d\n",rel13->harq_process,dlsch0_harq->frame,dlsch0_harq->subframe);
dlsch0->rnti = rel13->rnti; dlsch0->rnti = rel13->rnti;
dlsch0_harq->Qm = get_Qm(rel13->mcs);
openair1/PHY/LTE_TRANSPORT/edci.c
+320 -346
View File
@@ -49,52 +49,50 @@
//#define DEBUG_PHY //#define DEBUG_PHY
#ifdef Rel14 #ifdef Rel14
void void generate_edci_top(PHY_VARS_eNB * eNB, int frame, int subframe)
generate_edci_top (PHY_VARS_eNB * eNB, int frame, int subframe)
{ {
} }
void void mpdcch_scrambling(LTE_DL_FRAME_PARMS * frame_parms, mDCI_ALLOC_t * mdci, uint16_t i, uint8_t * e, uint32_t length)
mpdcch_scrambling (LTE_DL_FRAME_PARMS * frame_parms, mDCI_ALLOC_t * mdci, uint16_t i, uint8_t * e, uint32_t length)
{ {
int n; int n;
uint8_t reset; uint8_t reset;
uint32_t x1, x2, s = 0; uint32_t x1, x2, s = 0;
uint8_t Nacc = 4; uint8_t Nacc = 4;
uint16_t j0, j, idelta; uint16_t j0, j, idelta;
uint16_t i0 = mdci->i0; uint16_t i0 = mdci->i0;
// Note: we could actually not do anything if i-i0 < Nacc, save it for later // Note: we could actually not do anything if i-i0 < Nacc, save it for later
reset = 1; reset = 1;
// x1 is set in lte_gold_generic // x1 is set in lte_gold_generic
if ((mdci->rnti == 0xFFFE) || (mdci->ce_mode == 2)) // CEModeB Note: also for mdci->rnti==SC_RNTI if ((mdci->rnti == 0xFFFE) || (mdci->ce_mode == 2)) // CEModeB Note: also for mdci->rnti==SC_RNTI
Nacc = frame_parms->frame_type == FDD ? 4 : 10; Nacc = frame_parms->frame_type == FDD ? 4 : 10;
else else
Nacc = 1; Nacc = 1;
if (frame_parms->frame_type == FDD || Nacc == 1) if (frame_parms->frame_type == FDD || Nacc == 1)
idelta = 0; idelta = 0;
else else
idelta = Nacc - 2; idelta = Nacc - 2;
j0 = (i0 + idelta) / Nacc; j0 = (i0 + idelta) / Nacc;
j = (i - i0) / Nacc; j = (i - i0) / Nacc;
// rule for BL/CE UEs from Section 6.8.B2 in 36.211 // rule for BL/CE UEs from Section 6.8.B2 in 36.211
x2 = ((((j0 + j) * Nacc) % 10) << 9) + mdci->dmrs_scrambling_init; x2 = ((((j0 + j) * Nacc) % 10) << 9) + mdci->dmrs_scrambling_init;
for (n = 0; n < length; n++) { for (n = 0; n < length; n++) {
if ((i & 0x1f) == 0) { if ((i & 0x1f) == 0) {
s = lte_gold_generic (&x1, &x2, reset); s = lte_gold_generic(&x1, &x2, reset);
//printf("lte_gold[%d]=%x\n",i,s); //printf("lte_gold[%d]=%x\n",i,s);
reset = 0; reset = 0;
}
e[i] = (e[i] & 1) ^ ((s >> (i & 0x1f)) & 1);
} }
e[i] = (e[i] & 1) ^ ((s >> (i & 0x1f)) & 1);
}
} }
// this table is the allocation of modulated MPDCCH format 5 symbols to REs, antenna ports 107,108 // this table is the allocation of modulated MPDCCH format 5 symbols to REs, antenna ports 107,108
@@ -105,33 +103,30 @@ mpdcch_scrambling (LTE_DL_FRAME_PARMS * frame_parms, mDCI_ALLOC_t * mdci, uint16
static uint16_t mpdcch5ss1p107108tab[864]; static uint16_t mpdcch5ss1p107108tab[864];
static uint16_t mpdcch5ss1p109110tab[864]; static uint16_t mpdcch5ss1p109110tab[864];
void init_mpdcch5ss1tab_normal_regular_subframe_evenNRBDL(PHY_VARS_eNB *eNB) { void init_mpdcch5ss1tab_normal_regular_subframe_evenNRBDL(PHY_VARS_eNB * eNB)
int l,k,kmod,re107108=0,re109110=0; {
int l, k, kmod, re107108 = 0, re109110 = 0;
LOG_I(PHY,"Inititalizing mpdcchss15tab for normal prefix, normal prefix, no PSS/SSS/PBCH, even N_RB_DL\n"); LOG_I(PHY, "Inititalizing mpdcchss15tab for normal prefix, normal prefix, no PSS/SSS/PBCH, even N_RB_DL\n");
for (l=1;l<14;l++) { for (l = 1; l < 14; l++) {
for (k=0;k<72;k++){ for (k = 0; k < 72; k++) {
kmod = k % 12; kmod = k % 12;
if (((l!=5) && (l!=6) && (l!=12) && (l!=13))|| if (((l != 5) && (l != 6) && (l != 12) && (l != 13)) || (kmod == 2) || (kmod == 3) || (kmod == 4) || (kmod == 7) || (kmod == 8) || (kmod == 9)) {
(kmod==2) || (kmod==3) || (kmod==4) || mpdcch5ss1p109110tab[re109110] = (l * eNB->frame_parms.ofdm_symbol_size) + k;
(kmod==7) || (kmod==8) || (kmod==9)) { mpdcch5ss1p107108tab[re107108] = mpdcch5ss1p109110tab[re109110];
mpdcch5ss1p109110tab[re109110]=(l*eNB->frame_parms.ofdm_symbol_size)+k; re107108++;
mpdcch5ss1p107108tab[re107108]=mpdcch5ss1p109110tab[re109110]; re109110++;
re107108++; printf("l %d, k %d (kmod %d) => re %d\n", l, k, kmod, re107108);
re109110++; } else if ((kmod == 0) || (kmod == 5) || (kmod == 10)) {
printf("l %d, k %d (kmod %d) => re %d\n",l,k,kmod,re107108); mpdcch5ss1p109110tab[re109110++] = (l * eNB->frame_parms.ofdm_symbol_size) + k;
} } else if ((kmod == 1) || (kmod == 6) || (kmod == 11)) {
else if ((kmod==0)||(kmod==5)||(kmod==10)) { mpdcch5ss1p107108tab[re107108++] = (l * eNB->frame_parms.ofdm_symbol_size) + k;
mpdcch5ss1p109110tab[re109110++]=(l*eNB->frame_parms.ofdm_symbol_size)+k; printf("l %d, k %d (kmod %d) => re %d\n", l, k, kmod, re107108);
} }
else if ((kmod==1)||(kmod==6)||(kmod==11)) { }
mpdcch5ss1p107108tab[re107108++]=(l*eNB->frame_parms.ofdm_symbol_size)+k;
printf("l %d, k %d (kmod %d) => re %d\n",l,k,kmod,re107108);
}
} }
} AssertFatal(re107108 == 864, "RE count not equal to 864 (%d)\n", re107108);
AssertFatal(re107108==864,"RE count not equal to 864 (%d)\n",re107108);
} }
// this table is the allocation of modulated MPDCCH format 5 symbols to REs, antenna ports 107,108 // this table is the allocation of modulated MPDCCH format 5 symbols to REs, antenna ports 107,108
@@ -141,32 +136,29 @@ void init_mpdcch5ss1tab_normal_regular_subframe_evenNRBDL(PHY_VARS_eNB *eNB) {
// Total = 576+216 = 792 REs = 1584 bits // Total = 576+216 = 792 REs = 1584 bits
static uint16_t mpdcch5ss2p107108tab[792]; static uint16_t mpdcch5ss2p107108tab[792];
static uint16_t mpdcch5ss2p109110tab[792]; static uint16_t mpdcch5ss2p109110tab[792];
void init_mpdcch5ss2tab_normal_regular_subframe_evenNRBDL(PHY_VARS_eNB *eNB) { void init_mpdcch5ss2tab_normal_regular_subframe_evenNRBDL(PHY_VARS_eNB * eNB)
int l,k,kmod,re107108=0,re109110=0; {
int l, k, kmod, re107108 = 0, re109110 = 0;
LOG_I(PHY,"Inititalizing mpdcch5ss2tab for normal prefix, normal prefix, no PSS/SSS/PBCH, even N_RB_DL\n"); LOG_I(PHY, "Inititalizing mpdcch5ss2tab for normal prefix, normal prefix, no PSS/SSS/PBCH, even N_RB_DL\n");
for (l=2;l<14;l++) { for (l = 2; l < 14; l++) {
for (k=0;k<72;k++){ for (k = 0; k < 72; k++) {
kmod = k % 12; kmod = k % 12;
if (((l!=5) && (l!=6) && (l!=12) && (l!=13))|| if (((l != 5) && (l != 6) && (l != 12) && (l != 13)) || (kmod == 2) || (kmod == 3) || (kmod == 4) || (kmod == 7) || (kmod == 8) || (kmod == 9)) {
(kmod==2) || (kmod==3) || (kmod==4) || mpdcch5ss2p109110tab[re109110] = (l * eNB->frame_parms.ofdm_symbol_size) + k;
(kmod==7) || (kmod==8) || (kmod==9)) { mpdcch5ss2p107108tab[re107108] = mpdcch5ss2p109110tab[re109110];
mpdcch5ss2p109110tab[re109110]=(l*eNB->frame_parms.ofdm_symbol_size)+k; re107108++;
mpdcch5ss2p107108tab[re107108]=mpdcch5ss2p109110tab[re109110]; re109110++;
re107108++; printf("l %d, k %d (kmod %d) => re %d\n", l, k, kmod, re107108);
re109110++; } else if ((kmod == 0) || (kmod == 5) || (kmod == 10)) {
printf("l %d, k %d (kmod %d) => re %d\n",l,k,kmod,re107108); mpdcch5ss2p109110tab[re109110++] = (l * eNB->frame_parms.ofdm_symbol_size) + k;
} } else if ((kmod == 1) || (kmod == 6) || (kmod == 11)) {
else if ((kmod==0)||(kmod==5)||(kmod==10)) { mpdcch5ss2p107108tab[re107108++] = (l * eNB->frame_parms.ofdm_symbol_size) + k;
mpdcch5ss2p109110tab[re109110++]=(l*eNB->frame_parms.ofdm_symbol_size)+k; printf("l %d, k %d (kmod %d) => re %d\n", l, k, kmod, re107108);
} }
else if ((kmod==1)||(kmod==6)||(kmod==11)) { }
mpdcch5ss2p107108tab[re107108++]=(l*eNB->frame_parms.ofdm_symbol_size)+k;
printf("l %d, k %d (kmod %d) => re %d\n",l,k,kmod,re107108);
}
} }
} AssertFatal(re107108 == 792, "RE count not equal to 792\n");
AssertFatal(re107108==792,"RE count not equal to 792\n");
} }
// this table is the allocation of modulated MPDCCH format 5 symbols to REs, antenna ports 107,108 // this table is the allocation of modulated MPDCCH format 5 symbols to REs, antenna ports 107,108
@@ -176,32 +168,29 @@ void init_mpdcch5ss2tab_normal_regular_subframe_evenNRBDL(PHY_VARS_eNB *eNB) {
// Total = 504+216 = 720 REs = 1440 bits // Total = 504+216 = 720 REs = 1440 bits
static uint16_t mpdcch5ss3p107108tab[720]; static uint16_t mpdcch5ss3p107108tab[720];
static uint16_t mpdcch5ss3p109110tab[720]; static uint16_t mpdcch5ss3p109110tab[720];
void init_mpdcch5ss3tab_normal_regular_subframe_evenNRBDL(PHY_VARS_eNB *eNB) { void init_mpdcch5ss3tab_normal_regular_subframe_evenNRBDL(PHY_VARS_eNB * eNB)
int l,k,kmod,re107108=0,re109110=0; {
int l, k, kmod, re107108 = 0, re109110 = 0;
LOG_I(PHY,"Inititalizing mpdcch5ss3tab for normal prefix, normal prefix, no PSS/SSS/PBCH, even N_RB_DL\n"); LOG_I(PHY, "Inititalizing mpdcch5ss3tab for normal prefix, normal prefix, no PSS/SSS/PBCH, even N_RB_DL\n");
for (l=3;l<14;l++) { for (l = 3; l < 14; l++) {
for (k=0;k<72;k++){ for (k = 0; k < 72; k++) {
kmod = k % 12; kmod = k % 12;
if (((l!=5) && (l!=6) && (l!=12) && (l!=13))|| if (((l != 5) && (l != 6) && (l != 12) && (l != 13)) || (kmod == 2) || (kmod == 3) || (kmod == 4) || (kmod == 7) || (kmod == 8) || (kmod == 9)) {
(kmod==2) || (kmod==3) || (kmod==4) || mpdcch5ss3p109110tab[re109110] = (l * eNB->frame_parms.ofdm_symbol_size) + k;
(kmod==7) || (kmod==8) || (kmod==9)) { mpdcch5ss3p107108tab[re107108] = mpdcch5ss3p109110tab[re109110];
mpdcch5ss3p109110tab[re109110]=(l*eNB->frame_parms.ofdm_symbol_size)+k; re107108++;
mpdcch5ss3p107108tab[re107108]=mpdcch5ss3p109110tab[re109110]; re109110++;
re107108++; printf("l %d, k %d (kmod %d) => re %d\n", l, k, kmod, re107108);
re109110++; } else if ((kmod == 0) || (kmod == 5) || (kmod == 10)) {
printf("l %d, k %d (kmod %d) => re %d\n",l,k,kmod,re107108); mpdcch5ss3p109110tab[re109110++] = (l * eNB->frame_parms.ofdm_symbol_size) + k;
} } else if ((kmod == 1) || (kmod == 6) || (kmod == 11)) {
else if ((kmod==0)||(kmod==5)||(kmod==10)) { mpdcch5ss3p107108tab[re107108++] = (l * eNB->frame_parms.ofdm_symbol_size) + k;
mpdcch5ss3p109110tab[re109110++]=(l*eNB->frame_parms.ofdm_symbol_size)+k; printf("l %d, k %d (kmod %d) => re %d\n", l, k, kmod, re107108);
} }
else if ((kmod==1)||(kmod==6)||(kmod==11)) { }
mpdcch5ss3p107108tab[re107108++]=(l*eNB->frame_parms.ofdm_symbol_size)+k;
printf("l %d, k %d (kmod %d) => re %d\n",l,k,kmod,re107108);
}
} }
} AssertFatal(re107108 == 720, "RE count not equal to 792\n");
AssertFatal(re107108==720,"RE count not equal to 792\n");
} }
// this table is the allocation of modulated MPDCCH format 3 symbols to REs, antenna ports 107,108 // this table is the allocation of modulated MPDCCH format 3 symbols to REs, antenna ports 107,108
@@ -212,22 +201,22 @@ void init_mpdcch5ss3tab_normal_regular_subframe_evenNRBDL(PHY_VARS_eNB *eNB) {
static uint16_t mpdcch3ss1p107108tab[576]; static uint16_t mpdcch3ss1p107108tab[576];
static uint16_t mpdcch3ss1p109110tab[576]; static uint16_t mpdcch3ss1p109110tab[576];
void init_mpdcch3ss1tab_normal_regular_subframe_evenNRBDL(PHY_VARS_eNB *eNB) { void init_mpdcch3ss1tab_normal_regular_subframe_evenNRBDL(PHY_VARS_eNB * eNB)
int l,k,kmod,re; {
int l, k, kmod, re;
LOG_I(PHY,"Inititalizing mpdcch3ss1tab for normal prefix, normal prefix, no PSS/SSS/PBCH, even N_RB_DL\n"); LOG_I(PHY, "Inititalizing mpdcch3ss1tab for normal prefix, normal prefix, no PSS/SSS/PBCH, even N_RB_DL\n");
for (l=1,re=0;l<14;l++) { for (l = 1, re = 0; l < 14; l++) {
for (k=0;k<48;k++){ for (k = 0; k < 48; k++) {
kmod = k % 12; kmod = k % 12;
if (((l!=5) && (l!=6) && (l!=12) && (l!=13)) || if (((l != 5) && (l != 6) && (l != 12) && (l != 13)) || (((l == 5) || (l == 6) || (l == 12) || (l == 13)) && (kmod != 0) && (kmod != 5) && (kmod != 10))) {
(((l==5)||(l==6)||(l==12)||(l==13))&&(kmod!=0)&&(kmod!=5)&&(kmod!=10))) { mpdcch3ss1p109110tab[re] = (l * eNB->frame_parms.ofdm_symbol_size) + k;
mpdcch3ss1p109110tab[re]=(l*eNB->frame_parms.ofdm_symbol_size)+k; mpdcch3ss1p107108tab[re] = 1 + mpdcch3ss1p109110tab[re];
mpdcch3ss1p107108tab[re]=1+mpdcch3ss1p109110tab[re]; re++;
re++; }
} }
} }
} AssertFatal(re == 576, "RE count not equal to 864\n");
AssertFatal(re==576,"RE count not equal to 864\n");
} }
// this table is the allocation of modulated MPDCCH format 2 symbols to REs, antenna ports 107,108 // this table is the allocation of modulated MPDCCH format 2 symbols to REs, antenna ports 107,108
@@ -237,256 +226,241 @@ void init_mpdcch3ss1tab_normal_regular_subframe_evenNRBDL(PHY_VARS_eNB *eNB) {
// Total = 216+72 = 288 = 8CCE*36RE/CCE // Total = 216+72 = 288 = 8CCE*36RE/CCE
static uint16_t mpdcch2ss1p107108tab[288]; static uint16_t mpdcch2ss1p107108tab[288];
static uint16_t mpdcch2ss1p109110tab[288]; static uint16_t mpdcch2ss1p109110tab[288];
void init_mpdcch2ss1tab_normal_regular_subframe_evenNRBDL(PHY_VARS_eNB *eNB) { void init_mpdcch2ss1tab_normal_regular_subframe_evenNRBDL(PHY_VARS_eNB * eNB)
int l,k,kmod,re; {
int l, k, kmod, re;
LOG_I(PHY,"Inititalizing mpdcch2ss1tab for normal prefix, normal prefix, no PSS/SSS/PBCH, even N_RB_DL\n"); LOG_I(PHY, "Inititalizing mpdcch2ss1tab for normal prefix, normal prefix, no PSS/SSS/PBCH, even N_RB_DL\n");
for (l=1,re=0;l<14;l++) { for (l = 1, re = 0; l < 14; l++) {
for (k=0;k<24;k++){ for (k = 0; k < 24; k++) {
kmod = k % 12; kmod = k % 12;
if (((l!=5) && (l!=6) && (l!=12) && (l!=13)) || if (((l != 5) && (l != 6) && (l != 12) && (l != 13)) || (((l == 5) || (l == 6) || (l == 12) || (l == 13)) && (kmod != 0) && (kmod != 5) && (kmod != 10))) {
(((l==5)||(l==6)||(l==12)||(l==13))&&(kmod!=0)&&(kmod!=5)&&(kmod!=10))) { mpdcch2ss1p109110tab[re] = (l * eNB->frame_parms.ofdm_symbol_size) + k;
mpdcch2ss1p109110tab[re]=(l*eNB->frame_parms.ofdm_symbol_size)+k; mpdcch2ss1p107108tab[re] = 1 + mpdcch2ss1p109110tab[re];
mpdcch2ss1p107108tab[re]=1+mpdcch2ss1p109110tab[re]; re++;
re++; }
} }
} }
} AssertFatal(re == 288, "RE count not equal to 288\n");
AssertFatal(re==288,"RE count not equal to 288\n");
} }
extern uint8_t *generate_dci0(uint8_t *dci, extern uint8_t *generate_dci0(uint8_t * dci, uint8_t * e, uint8_t DCI_LENGTH, uint8_t bitsperCCE, uint8_t aggregation_level, uint16_t rnti);
uint8_t *e,
uint8_t DCI_LENGTH,
uint8_t bitsperCCE,
uint8_t aggregation_level,
uint16_t rnti);
uint16_t mpdcch_dmrs_tab[12*6]; uint16_t mpdcch_dmrs_tab[12 * 6];
void init_mpdcch_dmrs_tab(uint16_t oss) { void init_mpdcch_dmrs_tab(uint16_t oss)
int re = 5*oss;
int pos = 0;
for (int symb=0;symb<4;symb++) {
for (int prb=0;prb<6;prb++,re+=12) {
mpdcch_dmrs_tab[pos++] = re;
mpdcch_dmrs_tab[pos++] = re+5;
mpdcch_dmrs_tab[pos++] = re+10;
}
if (symb == 0) re=6*oss;
else if (symb == 1) re=12*oss;
else if (symb == 2) re=13*oss;
}
}
void
generate_mdci_top (PHY_VARS_eNB * eNB, int frame, int subframe, int16_t amp, int32_t ** txdataF)
{ {
LTE_eNB_MPDCCH *mpdcch= &eNB->mpdcch_vars[subframe&1]; int re = 5 * oss;
mDCI_ALLOC_t *mdci; int pos = 0;
int coded_bits;
LTE_DL_FRAME_PARMS *fp=&eNB->frame_parms;
int i;
int gain_lin_QPSK;
uint8_t bitsperCCE;
uint16_t *mpdcchtab;
uint32_t x1, x2, s = 0; for (int symb = 0; symb < 4; symb++) {
uint8_t Nacc = 4; for (int prb = 0; prb < 6; prb++, re += 12) {
uint16_t j0, j, idelta; mpdcch_dmrs_tab[pos++] = re;
uint16_t i0; mpdcch_dmrs_tab[pos++] = re + 5;
mpdcch_dmrs_tab[pos++] = re + 10;
int off; }
if (symb == 0)
// Assumption: only handle a single MPDCCH per narrowband re = 6 * oss;
else if (symb == 1)
LOG_I(PHY,"generate_mdci_top: num_dci %d\n",mpdcch->num_dci); re = 12 * oss;
else if (symb == 2)
for (i=0;i<mpdcch->num_dci;i++) { re = 13 * oss;
mdci = &mpdcch->mdci_alloc[i];
AssertFatal (fp->frame_type == FDD, "TDD is not yet supported for MPDCCH\n");
AssertFatal (fp->Ncp == NORMAL, "Extended Prefix not yet supported for MPDCCH\n");
AssertFatal (mdci->L <= 24, "L is %d\n", mdci->L);
AssertFatal (fp->N_RB_DL == 50 || fp->N_RB_DL == 100, "Only N_RB_DL=50,100 for MPDCCH\n");
// Force MPDDCH format 5
AssertFatal (mdci->number_of_prb_pairs == 6, "2 or 4 PRB pairs not support yet for MPDCCH\n");
// These are to avoid unimplemented things
AssertFatal (mdci->ce_mode == 1, "CE mode (%d) B not activated yet\n",mdci->ce_mode);
AssertFatal (mdci->L == 24, "Only 2+4 and aggregation 24 for now\n");
LOG_I(PHY,"mdci %d: rnti %x, L %d, prb_pairs %d, ce_mode %d, i0 %d, ss %d \n",
i,mdci->rnti,mdci->L,mdci->number_of_prb_pairs,mdci->ce_mode,mdci->i0,mdci->start_symbol);
i0 = mdci->i0;
// antenna index
int a_index = mdci->rnti & 3;
if ((mdci->start_symbol == 1) && (a_index<2)) {
mpdcchtab = mpdcch5ss1p107108tab;
bitsperCCE = 72;
}
else if ((mdci->start_symbol == 1) && (a_index>1)) {
mpdcchtab = mpdcch5ss1p109110tab;
bitsperCCE = 72;
}
else if ((mdci->start_symbol == 2) && (a_index<2)) {
mpdcchtab = mpdcch5ss2p107108tab;
bitsperCCE = 66;
}
else if ((mdci->start_symbol == 2) && (a_index>1)) {
mpdcchtab = mpdcch5ss2p109110tab;
bitsperCCE = 66;
}
else if ((mdci->start_symbol == 3) && (a_index<2)) {
mpdcchtab = mpdcch5ss2p107108tab;
bitsperCCE = 60;
}
else if ((mdci->start_symbol == 3) && (a_index<2)) {
mpdcchtab = mpdcch5ss2p109110tab;
bitsperCCE = 60;
}
else
AssertFatal(1==0,"Illegal combination start_symbol %d, a_index %d\n",mdci->start_symbol,a_index);
// Note: We only have to run this every Nacc subframes during repetitions, data and scrambling are constant, but we do it for now to simplify during testing
generate_dci0(mdci->dci_pdu,
mpdcch->e+(bitsperCCE*mdci->firstCCE),
mdci->dci_length,
mdci->L,
bitsperCCE,
mdci->rnti);
coded_bits = bitsperCCE * mdci->L;
// scrambling
uint16_t absSF = (frame * 10) + subframe;
AssertFatal (absSF < 10240, "Absolute subframe %d = %d*10 + %d > 10239\n", absSF, frame, subframe);
mpdcch_scrambling(fp,
mdci,
absSF,
mpdcch->e+(bitsperCCE*mdci->firstCCE),
coded_bits);
// Modulation for PDCCH
if (fp->nb_antenna_ports_eNB == 1)
gain_lin_QPSK = (int16_t) ((amp * ONE_OVER_SQRT2_Q15) >> 15);
else
gain_lin_QPSK = amp / 2;
uint8_t *e_ptr = mpdcch->e;
// if (mdci->transmission_type==0) nprime=mdci->rnti&3; // for Localized 2+4 we use 6.8B.5 rule
// map directly to one antenna port for now
// Note: aside from the antenna port mapping, there is no difference between localized and distributed transmission for MPDCCH format 5
// first RE of narrowband
// mpdcchtab5 below contains the mapping from each coded symbol to relative RE avoiding the DMRS
int nb_i0;
switch (fp->N_RB_DL) {
case 6:
case 25:
nb_i0=0;
break;
case 15:
case 50:
case 75:
nb_i0=1;
break;
case 100:
nb_i0=2;
break;
default:
AssertFatal(1==0,"Illegal N_RB_DL %d\n",fp->N_RB_DL);
break;
} }
int re_offset = fp->first_carrier_offset + (12*nb_i0) + mdci->narrowband * 12 * 6; }
if (re_offset > fp->ofdm_symbol_size)
re_offset -= (fp->ofdm_symbol_size - 1);
int32_t *txF = &txdataF[0][re_offset];
int32_t yIQ;
for (i = 0; i < (coded_bits >> 1); i++) { void generate_mdci_top(PHY_VARS_eNB * eNB, int frame, int subframe, int16_t amp, int32_t ** txdataF)
// QPSK modulation to yIQ {
((int16_t *) & yIQ)[0] = (*e_ptr == 1) ? -gain_lin_QPSK : gain_lin_QPSK;
e_ptr++; LTE_eNB_MPDCCH *mpdcch = &eNB->mpdcch_vars[subframe & 1];
((int16_t *) & yIQ)[1] = (*e_ptr == 1) ? -gain_lin_QPSK : gain_lin_QPSK; mDCI_ALLOC_t *mdci;
e_ptr++; int coded_bits;
txF[mpdcchtab[i + ((bitsperCCE>>1) * mdci->firstCCE)]] = yIQ; LTE_DL_FRAME_PARMS *fp = &eNB->frame_parms;
//LOG_I(PHY,"Frame %d, subframe %d: mpdcch pos %d: %d => (%d,%d)\n", int i;
// frame,subframe,i,mpdcchtab[i + ((bitsperCCE>>2) * mdci->firstCCE)],((int16_t *) & yIQ)[0],((int16_t *) & yIQ)[1]); int gain_lin_QPSK;
uint8_t bitsperCCE;
uint16_t *mpdcchtab;
uint32_t x1, x2, s = 0;
uint8_t Nacc = 4;
uint16_t j0, j, idelta;
uint16_t i0;
int off;
// Assumption: only handle a single MPDCCH per narrowband
LOG_I(PHY, "generate_mdci_top: num_dci %d\n", mpdcch->num_dci);
for (i = 0; i < mpdcch->num_dci; i++) {
mdci = &mpdcch->mdci_alloc[i];
AssertFatal(fp->frame_type == FDD, "TDD is not yet supported for MPDCCH\n");
AssertFatal(fp->Ncp == NORMAL, "Extended Prefix not yet supported for MPDCCH\n");
AssertFatal(mdci->L <= 24, "L is %d\n", mdci->L);
AssertFatal(fp->N_RB_DL == 50 || fp->N_RB_DL == 100, "Only N_RB_DL=50,100 for MPDCCH\n");
// Force MPDDCH format 5
AssertFatal(mdci->number_of_prb_pairs == 6, "2 or 4 PRB pairs not support yet for MPDCCH\n");
// These are to avoid unimplemented things
AssertFatal(mdci->ce_mode == 1, "CE mode (%d) B not activated yet\n", mdci->ce_mode);
AssertFatal(mdci->L == 24, "Only 2+4 and aggregation 24 for now\n");
LOG_I(PHY, "mdci %d: rnti %x, L %d, prb_pairs %d, ce_mode %d, i0 %d, ss %d \n", i, mdci->rnti, mdci->L, mdci->number_of_prb_pairs, mdci->ce_mode, mdci->i0, mdci->start_symbol);
i0 = mdci->i0;
// antenna index
int a_index = mdci->rnti & 3;
if ((mdci->start_symbol == 1) && (a_index < 2)) {
mpdcchtab = mpdcch5ss1p107108tab;
bitsperCCE = 72;
} else if ((mdci->start_symbol == 1) && (a_index > 1)) {
mpdcchtab = mpdcch5ss1p109110tab;
bitsperCCE = 72;
} else if ((mdci->start_symbol == 2) && (a_index < 2)) {
mpdcchtab = mpdcch5ss2p107108tab;
bitsperCCE = 66;
} else if ((mdci->start_symbol == 2) && (a_index > 1)) {
mpdcchtab = mpdcch5ss2p109110tab;
bitsperCCE = 66;
} else if ((mdci->start_symbol == 3) && (a_index < 2)) {
mpdcchtab = mpdcch5ss2p107108tab;
bitsperCCE = 60;
} else if ((mdci->start_symbol == 3) && (a_index < 2)) {
mpdcchtab = mpdcch5ss2p109110tab;
bitsperCCE = 60;
} else
AssertFatal(1 == 0, "Illegal combination start_symbol %d, a_index %d\n", mdci->start_symbol, a_index);
// Note: We only have to run this every Nacc subframes during repetitions, data and scrambling are constant, but we do it for now to simplify during testing
generate_dci0(mdci->dci_pdu, mpdcch->e + (bitsperCCE * mdci->firstCCE), mdci->dci_length, mdci->L, bitsperCCE, mdci->rnti);
coded_bits = bitsperCCE * mdci->L;
// scrambling
uint16_t absSF = (frame * 10) + subframe;
AssertFatal(absSF < 10240, "Absolute subframe %d = %d*10 + %d > 10239\n", absSF, frame, subframe);
mpdcch_scrambling(fp, mdci, absSF, mpdcch->e + (bitsperCCE * mdci->firstCCE), coded_bits);
// Modulation for PDCCH
if (fp->nb_antenna_ports_eNB == 1)
gain_lin_QPSK = (int16_t) ((amp * ONE_OVER_SQRT2_Q15) >> 15);
else
gain_lin_QPSK = amp / 2;
uint8_t *e_ptr = mpdcch->e;
// if (mdci->transmission_type==0) nprime=mdci->rnti&3; // for Localized 2+4 we use 6.8B.5 rule
// map directly to one antenna port for now
// Note: aside from the antenna port mapping, there is no difference between localized and distributed transmission for MPDCCH format 5
// first RE of narrowband
// mpdcchtab5 below contains the mapping from each coded symbol to relative RE avoiding the DMRS
int nb_i0;
switch (fp->N_RB_DL) {
case 6:
case 25:
nb_i0 = 0;
break;
case 15:
case 50:
case 75:
nb_i0 = 1;
break;
case 100:
nb_i0 = 2;
break;
default:
AssertFatal(1 == 0, "Illegal N_RB_DL %d\n", fp->N_RB_DL);
break;
}
int re_offset = fp->first_carrier_offset + (12 * nb_i0) + mdci->narrowband * 12 * 6;
if (re_offset > fp->ofdm_symbol_size)
re_offset -= (fp->ofdm_symbol_size - 1);
int32_t *txF = &txdataF[0][re_offset];
int32_t yIQ;
for (i = 0; i < (coded_bits >> 1); i++) {
// QPSK modulation to yIQ
((int16_t *) & yIQ)[0] = (*e_ptr == 1) ? -gain_lin_QPSK : gain_lin_QPSK;
e_ptr++;
((int16_t *) & yIQ)[1] = (*e_ptr == 1) ? -gain_lin_QPSK : gain_lin_QPSK;
e_ptr++;
txF[mpdcchtab[i + ((bitsperCCE >> 1) * mdci->firstCCE)]] = yIQ;
//LOG_I(PHY,"Frame %d, subframe %d: mpdcch pos %d: %d => (%d,%d)\n",
// frame,subframe,i,mpdcchtab[i + ((bitsperCCE>>2) * mdci->firstCCE)],((int16_t *) & yIQ)[0],((int16_t *) & yIQ)[1]);
}
if (a_index > 1)
off = 0;
else
off = 1;
// pilot scrambling initiatlization (note: this is for a single repetition)
// x1 is set in lte_gold_generic
// rule for BL/CE UEs from Section 6.10.3A.1 in 36.211
if ((mdci->rnti == 0xFFFE) || (mdci->ce_mode == 2)) // CEModeB Note: also for mdci->rnti==SC_RNTI
Nacc = fp->frame_type == FDD ? 4 : 10;
else
Nacc = 1;
if (fp->frame_type == FDD || Nacc == 1)
idelta = 0;
else
idelta = Nacc - 2;
j0 = (i0 + idelta) / Nacc;
j = (i - i0) / Nacc;
uint32_t a = ((((j0 + j) * Nacc) % 10) + 1);
uint32_t b = ((mdci->dmrs_scrambling_init << 1) + 1) << 16;
x2 = a * b;
LOG_I(PHY, "mpdcch_dmrs cinit %d\n", x2);
// add MPDCCH pilots
int reset = 1;
for (i = 0; i < (24 * 6); i += 2) {
if ((i & 0x1f) == 0) {
s = lte_gold_generic(&x1, &x2, reset);
reset = 0;
}
((int16_t *) & yIQ)[0] = (((s >> (i & 0x1f)) & 1) == 1) ? -gain_lin_QPSK : gain_lin_QPSK;
((int16_t *) & yIQ)[1] = (((s >> ((i + 1) & 0x1f)) & 1) == 1) ? -gain_lin_QPSK : gain_lin_QPSK;
txF[off + mpdcch_dmrs_tab[(i >> 1)]] = yIQ;
LOG_D(PHY, "mpdcch_dmrs pos %d: %d => (%d,%d)\n", i, off + mpdcch_dmrs_tab[(i >> 1)], ((int16_t *) & yIQ)[0], ((int16_t *) & yIQ)[1]);
}
} }
if (a_index>1) off=0;
else off=1;
// pilot scrambling initiatlization (note: this is for a single repetition)
// x1 is set in lte_gold_generic
// rule for BL/CE UEs from Section 6.10.3A.1 in 36.211
if ((mdci->rnti == 0xFFFE) || (mdci->ce_mode == 2)) // CEModeB Note: also for mdci->rnti==SC_RNTI
Nacc = fp->frame_type == FDD ? 4 : 10;
else
Nacc = 1;
if (fp->frame_type == FDD || Nacc == 1)
idelta = 0;
else
idelta = Nacc - 2;
j0 = (i0 + idelta) / Nacc;
j = (i - i0) / Nacc;
uint32_t a = ((((j0 + j) * Nacc) % 10)+1);
uint32_t b = ((mdci->dmrs_scrambling_init<<1)+1) << 16;
x2 = a*b;
LOG_I(PHY,"mpdcch_dmrs cinit %d\n",x2);
// add MPDCCH pilots
int reset = 1;
for (i=0; i < (24*6) ; i+=2) {
if ((i & 0x1f) == 0) {
s = lte_gold_generic (&x1, &x2, reset);
reset = 0;
}
((int16_t *) & yIQ)[0] = (((s>>(i & 0x1f))&1) == 1) ? -gain_lin_QPSK : gain_lin_QPSK;
((int16_t *) & yIQ)[1] = (((s>>((i+1) & 0x1f))&1) == 1) ? -gain_lin_QPSK : gain_lin_QPSK;
txF[off+mpdcch_dmrs_tab[(i>>1)]] = yIQ;
LOG_I(PHY,"mpdcch_dmrs pos %d: %d => (%d,%d)\n",i,off+mpdcch_dmrs_tab[(i>>1)],((int16_t *) & yIQ)[0],((int16_t *) & yIQ)[1]);
}
}
} }
void init_mpdcch(PHY_VARS_eNB *eNB) { void init_mpdcch(PHY_VARS_eNB * eNB)
{
init_mpdcch5ss1tab_normal_regular_subframe_evenNRBDL(eNB); init_mpdcch5ss1tab_normal_regular_subframe_evenNRBDL(eNB);
init_mpdcch5ss2tab_normal_regular_subframe_evenNRBDL(eNB); init_mpdcch5ss2tab_normal_regular_subframe_evenNRBDL(eNB);
init_mpdcch5ss3tab_normal_regular_subframe_evenNRBDL(eNB); init_mpdcch5ss3tab_normal_regular_subframe_evenNRBDL(eNB);
init_mpdcch3ss1tab_normal_regular_subframe_evenNRBDL(eNB); init_mpdcch3ss1tab_normal_regular_subframe_evenNRBDL(eNB);
init_mpdcch2ss1tab_normal_regular_subframe_evenNRBDL(eNB); init_mpdcch2ss1tab_normal_regular_subframe_evenNRBDL(eNB);
init_mpdcch_dmrs_tab(eNB->frame_parms.ofdm_symbol_size); init_mpdcch_dmrs_tab(eNB->frame_parms.ofdm_symbol_size);
} }
#endif #endif
openair1/SCHED/fapi_l1.c
+9 -3
View File
@@ -214,7 +214,10 @@ void handle_nfapi_dlsch_pdu(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,
dlsch0->i0 = 0xFFFF; dlsch0->i0 = 0xFFFF;
#endif #endif
dlsch0->active = 1;
harq_pid = dlsch0->harq_ids[proc->subframe_tx]; harq_pid = dlsch0->harq_ids[proc->subframe_tx];
dlsch0->harq_mask |= (1<<harq_pid);
AssertFatal((harq_pid>=0) && (harq_pid<8),"harq_pid %d not in 0...7\n",harq_pid); AssertFatal((harq_pid>=0) && (harq_pid<8),"harq_pid %d not in 0...7\n",harq_pid);
dlsch0_harq = dlsch0->harq_processes[harq_pid]; dlsch0_harq = dlsch0->harq_processes[harq_pid];
dlsch1_harq = dlsch1->harq_processes[harq_pid]; dlsch1_harq = dlsch1->harq_processes[harq_pid];
@@ -232,8 +235,11 @@ void handle_nfapi_dlsch_pdu(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,
computeRhoB_eNB(&eNB->pdsch_config_dedicated[UE_id],&(eNB->frame_parms.pdsch_config_common),eNB->frame_parms.nb_antenna_ports_eNB,dlsch1,dlsch1_harq->dl_power_off); computeRhoB_eNB(&eNB->pdsch_config_dedicated[UE_id],&(eNB->frame_parms.pdsch_config_common),eNB->frame_parms.nb_antenna_ports_eNB,dlsch1,dlsch1_harq->dl_power_off);
} }
#ifndef Rel14
dlsch0_harq->pdsch_start = eNB->pdcch_vars[proc->subframe_tx & 1].num_pdcch_symbols; dlsch0_harq->pdsch_start = eNB->pdcch_vars[proc->subframe_tx & 1].num_pdcch_symbols;
#else
dlsch0_harq->pdsch_start = rel10->pdsch_start;
#endif
if (dlsch0_harq->round==0) { //get pointer to SDU if this a new SDU if (dlsch0_harq->round==0) { //get pointer to SDU if this a new SDU
AssertFatal(sdu!=NULL,"NFAPI: frame %d, subframe %d: programming dlsch for round 0, rnti %x, UE_id %d, harq_pid %d : sdu is null for pdu_index %d\n", AssertFatal(sdu!=NULL,"NFAPI: frame %d, subframe %d: programming dlsch for round 0, rnti %x, UE_id %d, harq_pid %d : sdu is null for pdu_index %d\n",
proc->frame_tx,proc->subframe_tx,rel8->rnti,UE_id,harq_pid, proc->frame_tx,proc->subframe_tx,rel8->rnti,UE_id,harq_pid,
@@ -618,7 +624,7 @@ void schedule_response(Sched_Rsp_t *Sched_INFO)
eNB->mpdcch_vars[subframe&1].num_dci = 0; eNB->mpdcch_vars[subframe&1].num_dci = 0;
#endif #endif
LOG_I(PHY,"NFAPI: Frame %d, Subframe %d (ul_subframe %d): received %d dl_pdu, %d tx_req, %d hi_dci0_config_req, %d UL_config \n", LOG_D(PHY,"NFAPI: Frame %d, Subframe %d (ul_subframe %d): received %d dl_pdu, %d tx_req, %d hi_dci0_config_req, %d UL_config \n",
frame,subframe,ul_subframe,number_dl_pdu,TX_req->tx_request_body.number_of_pdus,number_hi_dci0_pdu,number_ul_pdu); frame,subframe,ul_subframe,number_dl_pdu,TX_req->tx_request_body.number_of_pdus,number_hi_dci0_pdu,number_ul_pdu);
@@ -638,7 +644,7 @@ void schedule_response(Sched_Rsp_t *Sched_INFO)
} }
for (i=0;i<number_dl_pdu;i++) { for (i=0;i<number_dl_pdu;i++) {
dl_config_pdu = &DL_req->dl_config_request_body.dl_config_pdu_list[i]; dl_config_pdu = &DL_req->dl_config_request_body.dl_config_pdu_list[i];
LOG_I(PHY,"NFAPI: dl_pdu %d : type %d\n",i,dl_config_pdu->pdu_type); LOG_D(PHY,"NFAPI: dl_pdu %d : type %d\n",i,dl_config_pdu->pdu_type);
switch (dl_config_pdu->pdu_type) { switch (dl_config_pdu->pdu_type) {
case NFAPI_DL_CONFIG_DCI_DL_PDU_TYPE: case NFAPI_DL_CONFIG_DCI_DL_PDU_TYPE:
handle_nfapi_dci_dl_pdu(eNB,proc,dl_config_pdu); handle_nfapi_dci_dl_pdu(eNB,proc,dl_config_pdu);
openair1/SCHED/phy_procedures_lte_eNb.c
+17 -14
View File
@@ -407,27 +407,30 @@ phy_procedures_eNB_TX (PHY_VARS_eNB * eNB, eNB_rxtx_proc_t * proc, relaying_type
for (UE_id = 0; UE_id < NUMBER_OF_UE_MAX; UE_id++) { for (UE_id = 0; UE_id < NUMBER_OF_UE_MAX; UE_id++) {
dlsch0 = eNB->dlsch[(uint8_t) UE_id][0]; dlsch0 = eNB->dlsch[(uint8_t) UE_id][0];
dlsch1 = eNB->dlsch[(uint8_t) UE_id][1]; dlsch1 = eNB->dlsch[(uint8_t) UE_id][1];
//if (dlsch0 && (dlsch0->rnti > 0) && (dlsch0->rnti!=0xFFFF))
if ((dlsch0) && (dlsch0->rnti > 0) && (dlsch0->active == 1)) { if ((dlsch0) && (dlsch0->rnti > 0) && (dlsch0->active == 1)) {
// get harq_pid // get harq_pid
harq_pid = dlsch0->harq_ids[subframe]; harq_pid = dlsch0->harq_ids[subframe];
AssertFatal (harq_pid >= 0, "harq_pid is negative\n"); if (harq_pid >=0 && harq_pid < 8) {
// generate pdsch // generate pdsch
LOG_I(PHY,"SFN %d.%d: DLSCH for rnti %x is active, harq_pid %d => SFN %d.%d\n", if ((dlsch0->rnti !=0xFFFF)) {
frame, LOG_I(PHY,"SFN %d.%d: DLSCH %d for rnti %x is active, harq_pid %d => SFN %d.%d\n",
subframe, frame,
dlsch0->rnti, subframe,
harq_pid, UE_id,
dlsch0->harq_processes[harq_pid]->frame, dlsch0->rnti,
dlsch0->harq_processes[harq_pid]->subframe); harq_pid,
if ((dlsch0->harq_processes[harq_pid]->status == ACTIVE) && (dlsch0->harq_processes[harq_pid]->frame == frame) && (dlsch0->harq_processes[harq_pid]->subframe == subframe)) dlsch0->harq_processes[harq_pid]->frame,
pdsch_procedures (eNB, proc, harq_pid, dlsch0, dlsch1, &eNB->UE_stats[(uint32_t) UE_id], 0); dlsch0->harq_processes[harq_pid]->subframe);
}
if ((dlsch0->harq_processes[harq_pid]->status == ACTIVE) && (dlsch0->harq_processes[harq_pid]->frame == frame) && (dlsch0->harq_processes[harq_pid]->subframe == subframe))
pdsch_procedures (eNB, proc, harq_pid, dlsch0, dlsch1, &eNB->UE_stats[(uint32_t) UE_id], 0);
}
} }
else if ((dlsch0) && (dlsch0->rnti > 0) && (dlsch0->active == 0)) { else if ((dlsch0) && (dlsch0->rnti > 0) && (dlsch0->active == 0)) {
// clear subframe TX flag since UE is not scheduled for PDSCH in this subframe (so that we don't look for PUCCH later) // clear subframe TX flag since UE is not scheduled for PDSCH in this subframe (so that we don't look for PUCCH later)
@@ -1078,7 +1081,7 @@ pusch_procedures (PHY_VARS_eNB * eNB, eNB_rxtx_proc_t * proc)
ulsch->cyclicShift = (ulsch_harq->n_DMRS2 + fp->pusch_config_common.ul_ReferenceSignalsPUSCH.cyclicShift + nPRS) % 12; ulsch->cyclicShift = (ulsch_harq->n_DMRS2 + fp->pusch_config_common.ul_ReferenceSignalsPUSCH.cyclicShift + nPRS) % 12;
LOG_D (PHY, LOG_I (PHY,
"[eNB %d][PUSCH %d] Frame %d Subframe %d Demodulating PUSCH: dci_alloc %d, rar_alloc %d, round %d, first_rb %d, nb_rb %d, Qm %d, TBS %d, rv %d, cyclic_shift %d (n_DMRS2 %d, cyclicShift_common %d, nprs %d), O_ACK %d, beta_cqi %d \n", "[eNB %d][PUSCH %d] Frame %d Subframe %d Demodulating PUSCH: dci_alloc %d, rar_alloc %d, round %d, first_rb %d, nb_rb %d, Qm %d, TBS %d, rv %d, cyclic_shift %d (n_DMRS2 %d, cyclicShift_common %d, nprs %d), O_ACK %d, beta_cqi %d \n",
eNB->Mod_id, harq_pid, frame, subframe, eNB->Mod_id, harq_pid, frame, subframe,
ulsch_harq->dci_alloc, ulsch_harq->dci_alloc,
@@ -1103,7 +1106,7 @@ pusch_procedures (PHY_VARS_eNB * eNB, eNB_rxtx_proc_t * proc)
stop_meas (&eNB->ulsch_decoding_stats); stop_meas (&eNB->ulsch_decoding_stats);
LOG_D (PHY, "[eNB %d][PUSCH %d] frame %d subframe %d RNTI %x RX power (%d,%d) N0 (%d,%d) dB ACK (%d,%d), decoding iter %d\n", eNB->Mod_id, harq_pid, frame, subframe, ulsch->rnti, dB_fixed (eNB->pusch_vars[i]->ulsch_power[0]), dB_fixed (eNB->pusch_vars[i]->ulsch_power[1]), 20, //eNB->measurements.n0_power_dB[0], LOG_I (PHY, "[eNB %d][PUSCH %d] frame %d subframe %d RNTI %x RX power (%d,%d) N0 (%d,%d) dB ACK (%d,%d), decoding iter %d\n", eNB->Mod_id, harq_pid, frame, subframe, ulsch->rnti, dB_fixed (eNB->pusch_vars[i]->ulsch_power[0]), dB_fixed (eNB->pusch_vars[i]->ulsch_power[1]), 20, //eNB->measurements.n0_power_dB[0],
20, //eNB->measurements.n0_power_dB[1], 20, //eNB->measurements.n0_power_dB[1],
ulsch_harq->o_ACK[0], ulsch_harq->o_ACK[1], ret); ulsch_harq->o_ACK[0], ulsch_harq->o_ACK[1], ret);
openair2/LAYER2/MAC/eNB_scheduler_RA.c
+4 -4
View File
@@ -85,9 +85,9 @@ add_msg3 (module_id_t module_idP, int CC_id, RA_TEMPLATE * RA_template, frame_t
#ifdef Rel14 #ifdef Rel14
if (RA_template->rach_resource_type > 0) { if (RA_template->rach_resource_type > 0) {
LOG_D (MAC, "[eNB %d][RAPROC] Frame %d, Subframe %d : CC_id %d CE level %d is active, Msg3 in (%d,%d)\n", LOG_I (MAC, "[eNB %d][RAPROC] Frame %d, Subframe %d : CC_id %d CE level %d is active, Msg3 in (%d,%d)\n",
module_idP, frameP, subframeP, CC_id, RA_template->rach_resource_type - 1, RA_template->Msg3_frame, RA_template->Msg3_subframe); module_idP, frameP, subframeP, CC_id, RA_template->rach_resource_type - 1, RA_template->Msg3_frame, RA_template->Msg3_subframe);
LOG_D (MAC, "Frame %d, Subframe %d Adding Msg3 UL Config Request for (%d,%d) : (%d,%d)\n", LOG_I (MAC, "Frame %d, Subframe %d Adding Msg3 UL Config Request for (%d,%d) : (%d,%d)\n",
frameP, subframeP, RA_template->Msg3_frame, RA_template->Msg3_subframe, RA_template->msg3_nb_rb, RA_template->msg3_round); frameP, subframeP, RA_template->Msg3_frame, RA_template->Msg3_subframe, RA_template->msg3_nb_rb, RA_template->msg3_round);
ul_config_pdu = &ul_req_body->ul_config_pdu_list[ul_req_body->number_of_pdus]; ul_config_pdu = &ul_req_body->ul_config_pdu_list[ul_req_body->number_of_pdus];
@@ -371,10 +371,10 @@ generate_Msg2 (module_id_t module_idP, int CC_idP, frame_t frameP, sub_frame_t s
dl_config_pdu->dlsch_pdu.dlsch_pdu_rel13.drms_table_flag = 0; dl_config_pdu->dlsch_pdu.dlsch_pdu_rel13.drms_table_flag = 0;
dl_req->number_pdu++; dl_req->number_pdu++;
// Program UL processing for Msg3, same as regular LTE fill_rar_br (eNB, CC_idP, RA_template, frameP, subframeP, cc[CC_idP].RAR_pdu.payload, RA_template->rach_resource_type - 1) ;
// Program UL processing for Msg3, same as regular LTE
get_Msg3alloc (&cc[CC_idP], subframeP, frameP, &RA_template->Msg3_frame, &RA_template->Msg3_subframe); get_Msg3alloc (&cc[CC_idP], subframeP, frameP, &RA_template->Msg3_frame, &RA_template->Msg3_subframe);
add_msg3 (module_idP, CC_idP, RA_template, frameP, subframeP); add_msg3 (module_idP, CC_idP, RA_template, frameP, subframeP);
fill_rar_br (eNB, CC_idP, RA_template, frameP, subframeP, cc[CC_idP].RAR_pdu.payload, RA_template->rach_resource_type - 1);
// DL request // DL request
LOG_I (MAC, "[eNB %d][RAPROC] Frame %d, Subframe %d : In generate_Msg2, Programming TX Req %d\n", module_idP, frameP, subframeP); LOG_I (MAC, "[eNB %d][RAPROC] Frame %d, Subframe %d : In generate_Msg2, Programming TX Req %d\n", module_idP, frameP, subframeP);
eNB->TX_req[CC_idP].sfn_sf = (frameP << 4) + subframeP; eNB->TX_req[CC_idP].sfn_sf = (frameP << 4) + subframeP;