From da524268c2489bad3fe4911456f1e7ceb36d27ec Mon Sep 17 00:00:00 2001 From: Rakesh Date: Mon, 14 Oct 2019 19:25:35 +0200 Subject: [PATCH 001/553] Adding VCD traces in gNB --- common/utils/LOG/vcd_signal_dumper.c | 23 ++++- common/utils/LOG/vcd_signal_dumper.h | 23 +++++ common/utils/T/T_defs.h | 2 +- common/utils/T/T_messages.txt | 98 +++++++++++++++++++ openair1/PHY/NR_TRANSPORT/nr_dlsch.c | 7 +- openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c | 4 +- openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c | 5 +- .../PHY/NR_UE_TRANSPORT/nr_initial_sync.c | 2 + .../PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c | 18 +++- openair1/PHY/NR_UE_TRANSPORT/pss_nr.c | 4 + openair1/SCHED_NR/phy_procedures_nr_gNB.c | 19 ++-- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 4 +- targets/RT/USER/gNB_usrp.gtkw | 67 +++++++------ 13 files changed, 228 insertions(+), 48 deletions(-) diff --git a/common/utils/LOG/vcd_signal_dumper.c b/common/utils/LOG/vcd_signal_dumper.c index d25b78be04..4722cc4c4e 100644 --- a/common/utils/LOG/vcd_signal_dumper.c +++ b/common/utils/LOG/vcd_signal_dumper.c @@ -503,7 +503,28 @@ const char* eurecomFunctionsNames[] = { "pdcch_tx", /*NR softmodem signal*/ "gNB_thread_rxtx0", - "gNB_thread_rxtx1" + "gNB_thread_rxtx1", + "gNB_ulsch_decoding", + "gNB_pdsch_codeword_scrambling", + "gNB_dlsch_encoding", + "gNB_pdsch_modulation", + "gNB_pdcch_tx", + "phy_procedures_gNB_tx", + "phy_procedures_gNB_common_tx", + "phy_procedures_gNB_uespec_rx", + "nr_rx_pusch", + "nr_ulsch_procedures_rx", + "macxface_gNB_dlsch_ulsch_scheduler", + + /*NR ue-softmodem signal*/ + "nr_ue_ulsch_encoding", + "nr_segmentation", + "ldpc_encoder_optim", + "nr_rate_matching_ldpc", + "nr_interleaving_ldpc", + "pss_synchro_nr", + "pss_search_time_nr", + "nr_initial_ue_sync" }; struct vcd_module_s vcd_modules[] = { diff --git a/common/utils/LOG/vcd_signal_dumper.h b/common/utils/LOG/vcd_signal_dumper.h index a7c4c10fe3..e753b9f9e5 100644 --- a/common/utils/LOG/vcd_signal_dumper.h +++ b/common/utils/LOG/vcd_signal_dumper.h @@ -496,6 +496,29 @@ typedef enum { /*NR softmodem signal*/ VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_PROC_RXTX0, VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_PROC_RXTX1, + VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_gNB_ULSCH_DECODING, + VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_PDSCH_CODEWORD_SCRAMBLING, + VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_DLSCH_ENCODING, + VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_PDSCH_MODULATION, + VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_gNB_PDCCH_TX, + VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_TX, + VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_COMMON_TX, + VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_UESPEC_RX, + VCD_SIGNAL_DUMPER_FUNCTIONS_NR_RX_PUSCH, + VCD_SIGNAL_DUMPER_FUNCTIONS_NR_ULSCH_PROCEDURES_RX, + VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_DLSCH_ULSCH_SCHEDULER, + +/* NR ue-softmodem signal*/ + VCD_SIGNAL_DUMPER_FUNCTIONS_NR_UE_ULSCH_ENCODING, + VCD_SIGNAL_DUMPER_FUNCTIONS_NR_SEGMENTATION, + VCD_SIGNAL_DUMPER_FUNCTIONS_LDPC_ENCODER_OPTIM, + VCD_SIGNAL_DUMPER_FUNCTIONS_NR_RATE_MATCHING_LDPC, + VCD_SIGNAL_DUMPER_FUNCTIONS_NR_INTERLEAVING_LDPC, + VCD_SIGNAL_DUMPER_FUNCTIONS_PSS_SYNCHRO_NR, + VCD_SIGNAL_DUMPER_FUNCTIONS_PSS_SEARCH_TIME_NR, + VCD_SIGNAL_DUMPER_FUNCTIONS_NR_INITIAL_UE_SYNC, + + VCD_SIGNAL_DUMPER_FUNCTIONS_END } vcd_signal_dump_functions; diff --git a/common/utils/T/T_defs.h b/common/utils/T/T_defs.h index 4f2b10c3ae..9c2dc6c277 100644 --- a/common/utils/T/T_defs.h +++ b/common/utils/T/T_defs.h @@ -73,7 +73,7 @@ typedef struct { } T_cache_t; /* number of VCD functions (to be kept up to date! see in T_messages.txt) */ -#define VCD_NUM_FUNCTIONS (237)//(232) +#define VCD_NUM_FUNCTIONS (256)//(232) /* number of VCD variables (to be kept up to date! see in T_messages.txt) */ #define VCD_NUM_VARIABLES (185) diff --git a/common/utils/T/T_messages.txt b/common/utils/T/T_messages.txt index 0b10b6e25e..046d643deb 100644 --- a/common/utils/T/T_messages.txt +++ b/common/utils/T/T_messages.txt @@ -3240,3 +3240,101 @@ ID = VCD_FUNCTION_gNB_PROC_RXTX1 GROUP = ALL:VCD:ENB:VCD_FUNCTION FORMAT = int,value VCD_NAME = gNB_thread_rxtx1 +ID = VCD_FUNCTION_PHY_gNB_ULSCH_DECODING + DESC = VCD function PHY_gNB_ULSCH_DECODING + GROUP = ALL:VCD:ENB:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = gNB_ulsch_decoding +ID = VCD_FUNCTION_gNB_PDSCH_CODEWORD_SCRAMBLING + DESC = VCD function gNB_PDSCH_CODEWORD_SCRAMBLING + GROUP = ALL:VCD:ENB:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = gNB_pdsch_codeword_scrambling +ID = VCD_FUNCTION_gNB_DLSCH_ENCODING + DESC = VCD function gNB_DLSCH_ENCODING + GROUP = ALL:VCD:ENB:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = gNB_dlsch_encoding +ID = VCD_FUNCTION_gNB_PDSCH_MODULATION + DESC = VCD function gNB_PDSCH_MODULATION + GROUP = ALL:VCD:ENB:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = gNB_pdsch_modulation +ID = VCD_FUNCTION_PHY_gNB_PDCCH_TX + DESC = VCD function PHY_gNB_PDCCH_TX + GROUP = ALL:VCD:ENB:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = gNB_pdcch_tx +ID = VCD_FUNCTION_PHY_PROCEDURES_gNB_TX + DESC = VCD function PHY_PROCEDURES_gNB_TX + GROUP = ALL:VCD:ENB:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = phy_procedures_gNB_tx +ID = VCD_FUNCTION_PHY_PROCEDURES_gNB_COMMON_TX + DESC = VCD function PHY_PROCEDURES_gNB_COMMON_TX + GROUP = ALL:VCD:ENB:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = phy_procedures_gNB_common_tx +ID = VCD_FUNCTION_PHY_PROCEDURES_gNB_UESPEC_RX + DESC = VCD function PHY_PROCEDURES_gNB_UESPEC_RX + GROUP = ALL:VCD:ENB:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = phy_procedures_gNB_uespec_rx +ID = VCD_FUNCTION_NR_RX_PUSCH + DESC = VCD function NR_RX_PUSCH + GROUP = ALL:VCD:ENB:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = nr_rx_pusch +ID = VCD_FUNCTION_NR_ULSCH_PROCEDURES_RX + DESC = VCD function NR_ULSCH_PROCEDURES_RX + GROUP = ALL:VCD:ENB:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = nr_ulsch_procedures_rx +ID = VCD_FUNCTION_gNB_DLSCH_ULSCH_SCHEDULER + DESC = VCD function gNB_DLSCH_ULSCH_SCHEDULER + GROUP = ALL:VCD:ENB:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = macxface_gNB_dlsch_ulsch_scheduler + + #function for nrUE +ID = VCD_FUNCTION_NR_UE_ULSCH_ENCODING + DESC = VCD function NR_UE_ULSCH_ENCODING + GROUP = ALL:VCD:UE:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = nr_ue_ulsch_encoding +ID = VCD_FUNCTION_NR_SEGMENTATION + DESC = VCD function NR_SEGMENTATION + GROUP = ALL:VCD:UE:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = nr_segmentation +ID = VCD_FUNCTION_LDPC_ENCODER_OPTIM + DESC = VCD function LDPC_ENCODER_OPTIM + GROUP = ALL:VCD:UE:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = ldpc_encoder_optim +ID = VCD_FUNCTION_NR_RATE_MATCHING_LDPC + DESC = VCD function NR_RATE_MATCHING_LDPC + GROUP = ALL:VCD:UE:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = nr_rate_matching_ldpc +ID = VCD_FUNCTION_NR_INTERLEAVING_LDPC + DESC = VCD function NR_INTERLEAVING_LDPC + GROUP = ALL:VCD:UE:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = nr_interleaving_ldpc +ID = VCD_FUNCTION_PSS_SYNCHRO_NR + DESC = VCD function PSS_SYNCHRO_NR + GROUP = ALL:VCD:UE:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = pss_synchro_nr +ID = VCD_FUNCTION_PSS_SEARCH_TIME_NR + DESC = VCD function PSS_SEARCH_TIME_NR + GROUP = ALL:VCD:UE:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = pss_search_time_nr +ID = VCD_FUNCTION_NR_INITIAL_UE_SYNC + DESC = VCD function NR_INITIAL_UE_SYNC + GROUP = ALL:VCD:UE:VCD_FUNCTION + FORMAT = int,value + VCD_NAME = nr_initial_ue_sync + diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch.c index aa75bd6555..ad37b41922 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch.c @@ -34,6 +34,7 @@ #include "nr_dci.h" #include "nr_sch_dmrs.h" #include "PHY/MODULATION/nr_modulation.h" +#include "common/utils/LOG/vcd_signal_dumper.h" //#define DEBUG_DLSCH //#define DEBUG_DLSCH_MAPPING @@ -47,7 +48,7 @@ void nr_pdsch_codeword_scrambling(uint8_t *in, uint8_t reset, b_idx; uint32_t x1, x2, s=0; - + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_PDSCH_CODEWORD_SCRAMBLING, 1); reset = 1; x2 = (n_RNTI<<15) + (q<<14) + Nid; @@ -62,7 +63,7 @@ void nr_pdsch_codeword_scrambling(uint8_t *in, *out ^= (((in[i])&1) ^ ((s>>b_idx)&1))<>8; i++) { /// Modulation start_meas(dlsch_modulation_stats); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_PDSCH_MODULATION, 1); for (int q=0; qnb_codewords; q++) nr_modulation(scrambled_output[q], encoded_length, Qm, mod_symbs[q]); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_PDSCH_MODULATION, 0); stop_meas(dlsch_modulation_stats); #ifdef DEBUG_DLSCH printf("PDSCH Modulation: Qm %d(%d)\n", Qm, nb_symbols); diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c index 04098a8440..039b7c07e8 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c @@ -302,7 +302,7 @@ int nr_dlsch_encoding(unsigned char *a,int frame, } */ - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING, VCD_FUNCTION_IN); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_DLSCH_ENCODING, VCD_FUNCTION_IN); A = rel15.transport_block_size; @@ -462,7 +462,7 @@ int nr_dlsch_encoding(unsigned char *a,int frame, r_offset += E; } - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING, VCD_FUNCTION_OUT); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_DLSCH_ENCODING, VCD_FUNCTION_OUT); return 0; } diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c index 2dd26e5242..16e1825269 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c @@ -348,7 +348,8 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, } // harq_process->trials[nfapi_ulsch_pdu_rel15->round]++; - + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_gNB_ULSCH_DECODING,1); harq_process->TBS = nr_compute_tbs(mcs, nb_rb, number_symbols, nb_re_dmrs, length_dmrs, n_layers); A = harq_process->TBS; @@ -717,6 +718,6 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, } ulsch->last_iteration_cnt = ret; - + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_gNB_ULSCH_DECODING,0); return(ret); } diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c b/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c index fc4fff1c40..e96f7245ac 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c @@ -222,6 +222,7 @@ int nr_initial_sync(UE_nr_rxtx_proc_t *proc, PHY_VARS_NR_UE *ue, runmode_t mode, // FK: added N_RB_DL paramter here as this function shares code with the gNB where it is needed. We should rewrite this function for the UE. nr_init_frame_parms_ue(fp,NR_MU_1,NORMAL,fp->N_RB_DL,n_ssb_crb,0); LOG_D(PHY,"nr_initial sync ue RB_DL %d\n", fp->N_RB_DL); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_INITIAL_UE_SYNC, VCD_FUNCTION_IN); @@ -480,6 +481,7 @@ int nr_initial_sync(UE_nr_rxtx_proc_t *proc, PHY_VARS_NR_UE *ue, runmode_t mode, } // exit_fun("debug exit"); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_INITIAL_UE_SYNC, VCD_FUNCTION_OUT); return ret; } diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c index c56f22fd20..bf1cf14b69 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c @@ -246,7 +246,7 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch, } */ - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING, VCD_FUNCTION_IN); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_UE_ULSCH_ENCODING, VCD_FUNCTION_IN); LOG_D(PHY,"ulsch coding nb_rb %d nb_symb_sch %d nb_re_dmrs %d, length_dmrs %d\n", nb_rb,nb_symb_sch, nb_re_dmrs,length_dmrs); @@ -290,6 +290,7 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch, ///////////////////////// b---->| block segmentation |---->c ///////////////////////// /////////// + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_SEGMENTATION, VCD_FUNCTION_IN); nr_segmentation(harq_process->b, harq_process->c, harq_process->B, @@ -297,6 +298,7 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch, &harq_process->K, pz, &harq_process->F); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_SEGMENTATION, VCD_FUNCTION_OUT); F = harq_process->F; Coderate = (float) A /(float) G; @@ -352,7 +354,11 @@ opp_enabled=0; } printf("\n");*/ + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_LDPC_ENCODER_OPTIM, VCD_FUNCTION_IN); + ldpc_encoder_optim_8seg(harq_process->c,harq_process->d,Kr,BG,harq_process->C,NULL,NULL,NULL,NULL); + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_LDPC_ENCODER_OPTIM, VCD_FUNCTION_OUT); //stop_meas(te_stats); //printf("end ldpc encoder -- output\n"); @@ -394,6 +400,7 @@ opp_enabled=0; E = nr_get_E(G, harq_process->C, mod_order, harq_process->Nl, r); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_RATE_MATCHING_LDPC, VCD_FUNCTION_IN); nr_rate_matching_ldpc(Ilbrm, Tbslbrm, BG, @@ -403,6 +410,7 @@ opp_enabled=0; harq_process->C, harq_process->rvidx, E); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_RATE_MATCHING_LDPC, VCD_FUNCTION_OUT); @@ -421,10 +429,14 @@ opp_enabled=0; //stop_meas(rm_stats); //start_meas(i_stats); - nr_interleaving_ldpc(E, + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_INTERLEAVING_LDPC, VCD_FUNCTION_IN); + + nr_interleaving_ldpc(E, mod_order, harq_process->e+r_offset, harq_process->f+r_offset); + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_INTERLEAVING_LDPC, VCD_FUNCTION_OUT); //stop_meas(i_stats); @@ -445,7 +457,7 @@ opp_enabled=0; memcpy(ulsch->g,harq_process->f,G); // g is the concatenated code block - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING, VCD_FUNCTION_OUT); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_UE_ULSCH_ENCODING, VCD_FUNCTION_OUT); return(0); } diff --git a/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c b/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c index c9fb300706..208413729b 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c +++ b/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c @@ -669,6 +669,7 @@ int pss_synchro_nr(PHY_VARS_NR_UE *PHY_vars_UE, int is, int rate_change) int **rxdata = NULL; int fo_flag = PHY_vars_UE->UE_fo_compensation; // flag to enable freq offset estimation and compensation + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PSS_SYNCHRO_NR, VCD_FUNCTION_IN); #ifdef DBG_PSS_NR LOG_M("rxdata0_rand.m","rxd0_rand", &PHY_vars_UE->common_vars.rxdata[0][0], frame_parms->samples_per_frame, 1, 1); @@ -707,6 +708,7 @@ int pss_synchro_nr(PHY_VARS_NR_UE *PHY_vars_UE, int is, int rate_change) #endif + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PSS_SEARCH_TIME_NR, VCD_FUNCTION_IN); synchro_position = pss_search_time_nr(rxdata, frame_parms, fo_flag, @@ -714,6 +716,7 @@ int pss_synchro_nr(PHY_VARS_NR_UE *PHY_vars_UE, int is, int rate_change) (int *)&PHY_vars_UE->common_vars.eNb_id, (int *)&PHY_vars_UE->common_vars.freq_offset); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PSS_SEARCH_TIME_NR, VCD_FUNCTION_OUT); #if TEST_SYNCHRO_TIMING_PSS @@ -746,6 +749,7 @@ int pss_synchro_nr(PHY_VARS_NR_UE *PHY_vars_UE, int is, int rate_change) } #endif + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PSS_SYNCHRO_NR, VCD_FUNCTION_OUT); return synchro_position; } diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index 46318b7a45..a31b9977cb 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -162,7 +162,7 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB, if ((cfg->subframe_config.duplex_mode.value == TDD) && (nr_slot_select(cfg,slot)==SF_UL)) return; - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_ENB_TX+offset,1); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_TX+offset,1); if (do_meas==1) start_meas(&gNB->phy_proc_tx); @@ -171,12 +171,12 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB, memset(gNB->common_vars.txdataF[aa],0,fp->samples_per_slot_wCP*sizeof(int32_t)); } - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_COMMON_TX,1); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_COMMON_TX,1); if (nfapi_mode == 0 || nfapi_mode == 1) { if (!(frame%ssb_frame_periodicity)) // generate SSB only for given frames according to SSB periodicity nr_common_signal_procedures(gNB,frame, slot); } - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_COMMON_TX,0); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_COMMON_TX,0); num_dci = gNB->pdcch_vars.num_dci; num_pdsch_rnti = gNB->pdcch_vars.num_pdsch_rnti; @@ -185,12 +185,12 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB, LOG_D(PHY, "[gNB %d] Frame %d slot %d \ Calling nr_generate_dci_top (number of DCI %d)\n", gNB->Mod_id, frame, slot, num_dci); - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_PDCCH_TX,1); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_gNB_PDCCH_TX,1); nr_generate_dci_top(gNB->pdcch_vars.dci_alloc[i], gNB->nr_gold_pdcch_dmrs[slot], gNB->common_vars.txdataF[0], AMP, *fp, *cfg); - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_PDCCH_TX,0); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_gNB_PDCCH_TX,0); } for (int i=0; iUL_tti_req; int num_pusch_pdu = UL_tti_req->n_pdus; + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_UESPEC_RX,1); LOG_I(PHY,"phy_procedures_gNB_uespec_RX frame %d, slot %d, num_pusch_pdu %d\n",frame_rx,slot_rx,num_pusch_pdu); for (int i = 0; i < num_pusch_pdu; i++) { @@ -370,11 +371,17 @@ void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) uint8_t symbol_end = symbol_start + pusch_pdu->nr_of_symbols; for(uint8_t symbol = symbol_start; symbol < symbol_end; symbol++) { + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_RX_PUSCH,1); nr_rx_pusch(gNB, UE_id, frame_rx, slot_rx, symbol, harq_pid); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_RX_PUSCH,0); } + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_ULSCH_PROCEDURES_RX,1); nr_ulsch_procedures(gNB, frame_rx, slot_rx, UE_id, harq_pid); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_ULSCH_PROCEDURES_RX,0); nr_fill_rx_indication(gNB, frame_rx, slot_rx, UE_id, harq_pid); // indicate SDU to MAC } } } + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_UESPEC_RX,0); } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index d82b1767f9..14a0773eb3 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -309,7 +309,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, NR_COMMON_channels_t *cc = RC.nrmac[module_idP]->common_channels; start_meas(&RC.nrmac[module_idP]->eNB_scheduler); - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ULSCH_SCHEDULER,VCD_FUNCTION_IN); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_DLSCH_ULSCH_SCHEDULER,VCD_FUNCTION_IN); RC.nrmac[module_idP]->frame = frame_rxP; RC.nrmac[module_idP]->slot = slot_rxP; @@ -387,5 +387,5 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, stop_meas(&RC.nrmac[module_idP]->eNB_scheduler); - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ULSCH_SCHEDULER,VCD_FUNCTION_OUT); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_DLSCH_ULSCH_SCHEDULER,VCD_FUNCTION_OUT); } diff --git a/targets/RT/USER/gNB_usrp.gtkw b/targets/RT/USER/gNB_usrp.gtkw index 069d1765a9..896dad1076 100644 --- a/targets/RT/USER/gNB_usrp.gtkw +++ b/targets/RT/USER/gNB_usrp.gtkw @@ -1,15 +1,15 @@ [*] -[*] GTKWave Analyzer v3.3.61 (w)1999-2014 BSI -[*] Sat May 18 17:25:11 2019 +[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI +[*] Mon Oct 14 17:19:14 2019 [*] -[dumpfile] "/tmp/openair_dump_gNB40.vcd" -[dumpfile_mtime] "Sat May 18 17:11:31 2019" -[dumpfile_size] 53148516 -[savefile] "/home/caracal/raymond/openairinterface5g/targets/RT/USER/gNB_usrp.gtkw" -[timestart] 11552775390 +[dumpfile] "/tmp/openair_dump_eNB.vcd" +[dumpfile_mtime] "Mon Oct 14 12:36:08 2019" +[dumpfile_size] 655399 +[savefile] "/home/rakesh/nr_fapi_for_push/openairinterface5g/targets/RT/USER/gNB_usrp.gtkw" +[timestart] 0 [size] 1840 795 [pos] -1 -1 -*-13.848083 11552814436 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-30.415869 243000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [sst_width] 386 [signals_width] 344 [sst_expanded] 1 @@ -24,44 +24,53 @@ variables.frame_number_TX1_UE[63:0] functions.ue_gain_control @420 variables.frame_number_RX1_UE[63:0] -@25 -variables.trx_ts_ue[63:0] @24 +variables.trx_ts_ue[63:0] variables.trx_ts[63:0] variables.trx_tst[63:0] +@22 +variables.frame_number_RX0_UE[63:0] +@24 variables.frame_number_RX0_RU[63:0] variables.tti_number_RX0_RU[63:0] variables.frame_number_TX0_RU[63:0] variables.tti_number_TX0_RU[63:0] @28 functions.mac_schedule_dlsch -functions.macxface_eNB_dlsch_ulsch_scheduler -@24 -variables.frame_number_RX0_gNB[63:0] -variables.slot_number_RX0_gNB[63:0] -variables.frame_number_TX0_gNB[63:0] -variables.slot_number_TX0_gNB[63:0] -@28 -functions.gNB_thread_rxtx0 -@24 -variables.frame_number_RX1_gNB[63:0] -variables.slot_number_RX1_gNB[63:0] -variables.frame_number_TX1_gNB[63:0] -variables.slot_number_TX1_gNB[63:0] -@28 +functions.macxface_gNB_dlsch_ulsch_scheduler functions.gNB_thread_rxtx1 -functions.phy_enb_pdcch_tx -functions.phy_eNB_dlsch_encoding functions.phy_eNB_dlsch_encoding_w functions.generate_dlsch -@420 -variables.frame_number_RX0_UE[63:0] -@28 functions.phy_procedures_ru_feprx0 functions.phy_procedures_ru_feprx1 functions.phy_procedures_ru_feptx_ofdm0 functions.phy_procedures_ru_feptx_ofdm1 functions.phy_procedures_ru_feptx_prec0 functions.phy_procedures_ru_feptx_prec1 +functions.phy_procedures_gNB_common_tx +functions.phy_procedures_gNB_tx +functions.gNB_pdcch_tx +functions.gNB_dlsch_encoding +functions.gNB_pdsch_codeword_scrambling +functions.gNB_pdsch_modulation +functions.phy_procedures_gNB_uespec_rx +functions.nr_rx_pusch +functions.nr_ulsch_procedures_rx +functions.gNB_ulsch_decoding +@24 +variables.frame_number_RX0_gNB[63:0] +variables.frame_number_RX1_gNB[63:0] +variables.frame_number_TX0_gNB[63:0] +@421 +variables.frame_number_RX0_UE[63:0] +@24 +variables.slot_number_RX0_gNB[63:0] +variables.slot_number_TX0_gNB[63:0] +@28 +functions.gNB_thread_rxtx0 +@24 +variables.slot_number_RX1_gNB[63:0] +variables.frame_number_TX1_gNB[63:0] +variables.slot_number_TX1_gNB[63:0] [pattern_trace] 1 [pattern_trace] 0 From 666db5675d91779dbacfe9baf7c797789560bcd9 Mon Sep 17 00:00:00 2001 From: Rakesh Date: Mon, 14 Oct 2019 21:02:22 +0200 Subject: [PATCH 002/553] build fail fixes for nrUE --- openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c | 1 + openair1/PHY/NR_UE_TRANSPORT/pss_nr.c | 1 + 2 files changed, 2 insertions(+) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c b/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c index e96f7245ac..23815cfe96 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c @@ -38,6 +38,7 @@ #include "PHY/NR_UE_ESTIMATION/nr_estimation.h" //#include "SCHED/defs.h" //#include "SCHED/extern.h" +#include "common/utils/LOG/vcd_signal_dumper.h" #include "common_lib.h" #include diff --git a/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c b/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c index 208413729b..16e668f8cb 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c +++ b/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c @@ -38,6 +38,7 @@ #include "PHY/defs_nr_UE.h" #include "PHY/NR_REFSIG/ss_pbch_nr.h" +#include "common/utils/LOG/vcd_signal_dumper.h" #define DEFINE_VARIABLES_PSS_NR_H #include "PHY/NR_REFSIG/pss_nr.h" From 9133aeddc43a77ab52085d544a9196615c3af5f2 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Tue, 12 Nov 2019 20:03:21 +0100 Subject: [PATCH 003/553] gtkw file --- targets/RT/USER/gNB_usrp.gtkw | 77 +++++++++++++++++------------------ 1 file changed, 38 insertions(+), 39 deletions(-) diff --git a/targets/RT/USER/gNB_usrp.gtkw b/targets/RT/USER/gNB_usrp.gtkw index 896dad1076..4d0e668240 100644 --- a/targets/RT/USER/gNB_usrp.gtkw +++ b/targets/RT/USER/gNB_usrp.gtkw @@ -1,15 +1,15 @@ [*] -[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI -[*] Mon Oct 14 17:19:14 2019 +[*] GTKWave Analyzer v3.3.61 (w)1999-2014 BSI +[*] Tue Oct 15 11:26:28 2019 [*] -[dumpfile] "/tmp/openair_dump_eNB.vcd" -[dumpfile_mtime] "Mon Oct 14 12:36:08 2019" -[dumpfile_size] 655399 -[savefile] "/home/rakesh/nr_fapi_for_push/openairinterface5g/targets/RT/USER/gNB_usrp.gtkw" -[timestart] 0 -[size] 1840 795 +[dumpfile] "/home/caracal/rakesh/openair_dump_gNB_nr_vcd.vcd" +[dumpfile_mtime] "Mon Oct 14 19:40:52 2019" +[dumpfile_size] 45402472 +[savefile] "/home/caracal/rakesh/nr_fapi_for_push/openairinterface5g/targets/RT/USER/gNB_usrp.gtkw" +[timestart] 31585150000 +[size] 1920 960 [pos] -1 -1 -*-30.415869 243000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-21.745718 31593090000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [sst_width] 386 [signals_width] 344 [sst_expanded] 1 @@ -30,47 +30,46 @@ variables.trx_ts[63:0] variables.trx_tst[63:0] @22 variables.frame_number_RX0_UE[63:0] +@420 +variables.frame_number_RX0_UE[63:0] @24 variables.frame_number_RX0_RU[63:0] variables.tti_number_RX0_RU[63:0] -variables.frame_number_TX0_RU[63:0] -variables.tti_number_TX0_RU[63:0] +variables.frame_number_RX0_gNB[63:0] +variables.slot_number_RX0_gNB[63:0] +variables.slot_number_RX1_gNB[63:0] +variables.frame_number_RX1_gNB[63:0] @28 -functions.mac_schedule_dlsch -functions.macxface_gNB_dlsch_ulsch_scheduler -functions.gNB_thread_rxtx1 -functions.phy_eNB_dlsch_encoding_w -functions.generate_dlsch functions.phy_procedures_ru_feprx0 functions.phy_procedures_ru_feprx1 -functions.phy_procedures_ru_feptx_ofdm0 -functions.phy_procedures_ru_feptx_ofdm1 -functions.phy_procedures_ru_feptx_prec0 -functions.phy_procedures_ru_feptx_prec1 +functions.phy_procedures_gNB_uespec_rx +functions.nr_rx_pusch +functions.nr_ulsch_procedures_rx +functions.gNB_ulsch_decoding +@24 +variables.frame_number_TX0_RU[63:0] +variables.frame_number_TX0_gNB[63:0] +variables.frame_number_TX1_gNB[63:0] +variables.tti_number_TX0_RU[63:0] +variables.slot_number_TX0_gNB[63:0] +variables.slot_number_TX1_gNB[63:0] +@29 +functions.mac_schedule_dlsch +@28 +functions.macxface_gNB_dlsch_ulsch_scheduler +functions.gNB_thread_rxtx0 +functions.gNB_thread_rxtx1 +functions.generate_dlsch functions.phy_procedures_gNB_common_tx functions.phy_procedures_gNB_tx functions.gNB_pdcch_tx functions.gNB_dlsch_encoding functions.gNB_pdsch_codeword_scrambling functions.gNB_pdsch_modulation -functions.phy_procedures_gNB_uespec_rx -functions.nr_rx_pusch -functions.nr_ulsch_procedures_rx -functions.gNB_ulsch_decoding -@24 -variables.frame_number_RX0_gNB[63:0] -variables.frame_number_RX1_gNB[63:0] -variables.frame_number_TX0_gNB[63:0] -@421 -variables.frame_number_RX0_UE[63:0] -@24 -variables.slot_number_RX0_gNB[63:0] -variables.slot_number_TX0_gNB[63:0] -@28 -functions.gNB_thread_rxtx0 -@24 -variables.slot_number_RX1_gNB[63:0] -variables.frame_number_TX1_gNB[63:0] -variables.slot_number_TX1_gNB[63:0] +functions.phy_procedures_ru_feptx_ofdm0 +functions.phy_procedures_ru_feptx_ofdm1 +functions.phy_procedures_ru_feptx_prec0 +functions.phy_procedures_ru_feptx_prec1 +functions.phy_eNB_dlsch_encoding_w [pattern_trace] 1 [pattern_trace] 0 From 1996bdaa34256b79c21a29daaee97ba42cc0ff21 Mon Sep 17 00:00:00 2001 From: Bo Zhao Date: Tue, 20 Aug 2019 17:23:33 +0200 Subject: [PATCH 004/553] Fix for DFT of different preamble formats according to specifications --- openair1/PHY/NR_TRANSPORT/nr_prach.c | 36 ++++++++++++++-------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index 268f2f5fcf..373e8532c8 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -201,13 +201,13 @@ void rx_nr_prach_ru(RU_t *ru, dft2048(prach2+4096*3,rxsigF[aa]+4096*3,1); reps+=2; } - if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xc2) { + if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xB4) { dft2048(prach2+4096*4,rxsigF[aa]+4096*4,1); dft2048(prach2+4096*5,rxsigF[aa]+4096*5,1); reps+=2; } - if (prach_fmt == 0xc2) { - for (int i=6;i<11;i++) dft2048(prach2+(3072*i),rxsigF[aa]+(3072*i),1); + if (prach_fmt == 0xB4) { + for (int i=6;i<11;i++) dft2048(prach2+(4096*i),rxsigF[aa]+(4096*i),1); reps+=6; } } else { @@ -223,8 +223,8 @@ void rx_nr_prach_ru(RU_t *ru, reps++; } if (prach_fmt == 2) { - dft36864(prach2+(98304*2),rxsigF[aa]+(98304*2),1); - dft36864(prach2+(98304*3),rxsigF[aa]+(98304*3),1); + dft36864(prach2+(73728*2),rxsigF[aa]+(73728*2),1); + dft36864(prach2+(73728*3),rxsigF[aa]+(73728*3),1); reps+=2; } if (prach_fmt == 3) { @@ -243,12 +243,12 @@ void rx_nr_prach_ru(RU_t *ru, dft1536(prach2+3072*3,rxsigF[aa]+3072*3,1); reps+=2; } - if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xc2) { + if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xB4) { dft1536(prach2+3072*4,rxsigF[aa]+3072*4,1); dft1536(prach2+3072*5,rxsigF[aa]+3072*5,1); reps+=2; } - if (prach_fmt == 0xc2) { + if (prach_fmt == 0xB4) { for (int i=6;i<11;i++) dft1536(prach2+(3072*i),rxsigF[aa]+(3072*i),1); reps+=6; } @@ -258,20 +258,20 @@ void rx_nr_prach_ru(RU_t *ru, if (fp->threequarter_fs==0) { prach2 = prach[aa] + (Ncp<<3); dftlen=98304; - //80,90,100 MHz @ 61.44 Ms/s + //80,90,100 MHz @ 122.88 Ms/s if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) dft98304(prach2,rxsigF[aa],1); if (prach_fmt == 1 || prach_fmt == 2) { dft98304(prach2+196608,rxsigF[aa]+196608,1); reps++; } - if (prach_fmt == 1 || prach_fmt == 2) { - dft98304(prach2+196608,rxsigF[aa]+196608,1); - dft98304(prach2+(196608*2),rxsigF[aa]+(196608*2),1); + if (prach_fmt == 2) { + dft98304(prach2+196608*2,rxsigF[aa]+196608*2,1); + dft98304(prach2+(196608*3),rxsigF[aa]+(196608*3),1); reps+=2; } if (prach_fmt == 3) { - dft24576(prach2+(2*49152),rxsigF[aa]+(2*49152),1); + for (int i=0;i<4;i++) dft24576(prach2+(i*2*24576),rxsigF[aa]+(i*2*24576),1); reps=4; dftlen=24576; } @@ -288,19 +288,19 @@ void rx_nr_prach_ru(RU_t *ru, dft4096(prach2+8192*3,rxsigF[aa]+8192*3,1); reps+=2; } - if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xc2) { + if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xB4) { dft4096(prach2+8192*4,rxsigF[aa]+8192*4,1); dft4096(prach2+8192*5,rxsigF[aa]+8192*5,1); reps+=2; } - if (prach_fmt == 0xc2) { + if (prach_fmt == 0xB4) { for (int i=6;i<11;i++) dft4096(prach2+(8192*i),rxsigF[aa]+(8192*i),1); reps+=6; } } else { AssertFatal(fp->N_RB_UL <= 217,"cannot do more than 217 PRBs with 3/4 sampling\n"); prach2 = prach[aa] + (6*Ncp); - // 80 MHz @ 46.08 Ms/s + // 80 MHz @ 92.16 Ms/s dftlen=73728; if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) { dft73728(prach2,rxsigF[aa],1); @@ -311,7 +311,7 @@ void rx_nr_prach_ru(RU_t *ru, reps++; } if (prach_fmt == 3) { - dft73728(prach2+(4*73728),rxsigF[aa]+(4*73728),1); + for (int i=0;i<4;i++) dft18432(prach2+(i*2*18432),rxsigF[aa]+(i*2*18432),1); reps=4; dftlen=18432; } @@ -329,12 +329,12 @@ void rx_nr_prach_ru(RU_t *ru, dft3072(prach2+6144*3,rxsigF[aa]+6144*3,1); reps+=2; } - if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xc2) { + if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xB4) { dft3072(prach2+6144*4,rxsigF[aa]+6144*4,1); dft3072(prach2+6144*5,rxsigF[aa]+6144*5,1); reps+=2; } - if (prach_fmt == 0xc2) { + if (prach_fmt == 0xB4) { for (int i=6;i<11;i++) dft3072(prach2+(6144*i),rxsigF[aa]+(6144*i),1); reps+=6; } From 21bb011b7a22206615ff1b542363c135a14d5fb2 Mon Sep 17 00:00:00 2001 From: Bo Zhao Date: Wed, 21 Aug 2019 11:06:59 +0200 Subject: [PATCH 005/553] Conversion from the peak detection to the TA value, considering the numerology, N_RB and the sampling rate --- openair1/PHY/NR_TRANSPORT/nr_prach.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index 373e8532c8..8bcd3f2662 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -626,6 +626,32 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, } }// preamble_index + + // The conversion from *max_preamble_delay from TA value is done here. + // It is normalized to the 30.72 Ms/s, considering the numerology, N_RB and the sampling rate + // See table 6.3.3.1 -1 and -2 in 38211. + + // Format 0, 1, 2: 24576 samples @ 30.72 Ms/s, 98304 samples @ 122.88 Ms/s + // By solving: + // max_preamble_delay * ( (24576*(fs/30.72M)) / 1024 ) / fs = TA * 16 * 64 / 2^mu * Tc + + // Format 3: 6144 samples @ 30.72 Ms/s, 24576 samples @ 122.88 Ms/s + // By solving: + // max_preamble_delay * ( (6144*(fs/30.72M)) / 1024 ) / fs = TA * 16 * 64 / 2^mu * Tc + + // Format >3: 2048/2^mu samples @ 30.72 Ms/s, 2048/2^mu * 4 samples @ 122.88 Ms/s + // By solving: + // max_preamble_delay * ( (2048/2^mu*(fs/30.72M)) / 256 ) / fs = TA * 16 * 64 / 2^mu * Tc + uint16_t *TA = max_preamble_delay; + int mu = fp->numerology_index; + if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) + *TA = *TA*3*(1< 3) + *TA = *TA/2; + + if (LOG_DUMPFLAG(PRACH)) { int en = dB_fixed(signal_energy((int32_t*)&rxsigF[0][0],840)); if (en>60) { From 42c698fd93fe49f639aacb52c15050e367ef08b3 Mon Sep 17 00:00:00 2001 From: Bo Zhao Date: Wed, 21 Aug 2019 11:49:10 +0200 Subject: [PATCH 006/553] Bug fix: preamble energy and delay used in the peak detection should be scalar instead of array --- openair1/SIMULATION/NR_PHY/prachsim.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/openair1/SIMULATION/NR_PHY/prachsim.c b/openair1/SIMULATION/NR_PHY/prachsim.c index 74a286863b..3771aa3b3e 100644 --- a/openair1/SIMULATION/NR_PHY/prachsim.c +++ b/openair1/SIMULATION/NR_PHY/prachsim.c @@ -112,7 +112,7 @@ int main(int argc, char **argv) int N_RB_UL=273; uint32_t prach_errors=0; uint8_t subframe=9; - uint16_t preamble_energy_list[64],preamble_tx=50,preamble_delay_list[64]; + uint16_t preamble_energy, preamble_tx=50, preamble_delay; uint16_t preamble_max,preamble_energy_max; PRACH_RESOURCES_t prach_resources; //uint8_t prach_fmt; @@ -599,17 +599,17 @@ int main(int argc, char **argv) 0, subframe, &preamble_rx, - preamble_energy_list, - preamble_delay_list); - + &preamble_energy, + &preamble_delay); + printf("preamble_rx %d\n", preamble_rx); if (preamble_rx!=preamble_tx) prach_errors++; else { - delay_avg += (double)preamble_delay_list[preamble_tx]; + delay_avg += (double)preamble_delay; } if (n_frames==1) { - printf("preamble %d (tx %d) : energy %d, delay %d\n",preamble_rx,preamble_tx,preamble_energy_list[0],preamble_delay_list[0]); + printf("preamble %d (tx %d) : energy %d, delay %d\n",preamble_rx,preamble_tx,preamble_energy,preamble_delay); LOG_M("prach0.m","prach0", &txdata[0][subframe*frame_parms->samples_per_slot<<1],frame_parms->samples_per_slot<<1,1,1); From 0ae6685dbb3fb12e1ddb8686b58e9111c4ae60c5 Mon Sep 17 00:00:00 2001 From: Bo Zhao Date: Wed, 21 Aug 2019 11:58:57 +0200 Subject: [PATCH 007/553] Bug fix: use NR prach table init function --- openair1/PHY/INIT/nr_init_ue.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/openair1/PHY/INIT/nr_init_ue.c b/openair1/PHY/INIT/nr_init_ue.c index d16858aed4..a559b35e7e 100644 --- a/openair1/PHY/INIT/nr_init_ue.c +++ b/openair1/PHY/INIT/nr_init_ue.c @@ -940,7 +940,11 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue, // enable MIB/SIB decoding by default ue->decode_MIB = 1; ue->decode_SIB = 1; - init_prach_tables(839); + + ue->ssb_periodicity = 5; // initialization of ssb periodicity to 5ms according to TS38.213 section 4.1 + + init_nr_prach_tables(839); + return 0; } From 2cd49c3e24faa8bb67d942763fee3c5e1fd23755 Mon Sep 17 00:00:00 2001 From: Bo Zhao Date: Wed, 21 Aug 2019 14:20:18 +0200 Subject: [PATCH 008/553] Bug fix: remove the hardcoded tx preamble index --- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 1a5498dc4c..d76c2592f2 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -2402,7 +2402,7 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t e int frame_tx = proc->frame_tx; int nr_tti_tx = proc->nr_tti_tx; int prach_power; - uint16_t preamble_tx=50; + uint16_t preamble_tx=ue->prach_resources[0]->ra_PreambleIndex; PRACH_RESOURCES_t prach_resources; VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_IN); From f2eb21415637d01f9a5e80f57501b5147d095877 Mon Sep 17 00:00:00 2001 From: Bo Zhao Date: Wed, 21 Aug 2019 14:32:11 +0200 Subject: [PATCH 009/553] 1. assertion relax for preamble format 3; 2. memset bugfix for RB=106; 3. repetition bugfix for format A3 and B3 --- openair1/PHY/NR_UE_TRANSPORT/nr_prach.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c index 9af68a9bc5..abf849202e 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c @@ -280,7 +280,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, * *********************************************************/ - AssertFatal(prach_fmt>3,"prach_fmt<=3: Fix this for other formats\n"); + AssertFatal(prach_fmt>=3,"prach_fmt<=3: Fix this for other formats\n"); int dftlen=2048; if (fp->N_RB_UL >= 137) dftlen=4096; if (fp->threequarter_fs==1) dftlen=(3*dftlen)/4; @@ -325,9 +325,9 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, memset((void*)prachF,0,4*18432); break; - case 106: + /*case 106: memset((void*)prachF,0,4*24576); - break; + break;*/ } int mu = 1; // numerology is hardcoded. FIXME!!! @@ -470,7 +470,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, // here we have |empty | Prach2048 | Prach2048| empty2048 | empty2048 | empty2048 | empty2048 memmove(prach2+(2048<<2),prach2,(2048<<3)); // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | empty2048 | empty2048 - memmove(prach2+((2048<<1)*3),prach2,(2048<<3)); + memmove(prach2+(2048<<3),prach2,(2048<<3)); // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048 memmove(prach,prach+(2048<<1),(Ncp<<2)); // here we have |Prefix | Prach2048 | @@ -566,7 +566,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, // here we have |empty | Prach1536 | Prach1536| empty1536 | empty1536 | empty1536 | empty1536 memmove(prach2+(1536<<2),prach2,(1536<<3)); // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | empty1536 | empty1536 - memmove(prach2+((1536<<1)*3),prach2,(1536<<3)); + memmove(prach2+(1536<<3),prach2,(1536<<3)); // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536 memmove(prach,prach+(1536<<1),(Ncp<<2)); // here we have |Prefix | Prach1536 | @@ -666,7 +666,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, // here we have |empty | Prach4096 | Prach4096| empty4096 | empty4096 | empty4096 | empty4096 memmove(prach2+(4096<<2),prach2,(4096<<3)); // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | empty4096 | empty4096 - memmove(prach2+((4096<<1)*3),prach2,(4096<<3)); + memmove(prach2+(4096<<3),prach2,(4096<<3)); // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096 memmove(prach,prach+(4096<<1),(Ncp<<2)); // here we have |Prefix | Prach4096 | @@ -751,7 +751,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, // here we have |empty | Prach3072 | Prach3072| empty3072 | empty3072 | empty3072 | empty3072 memmove(prach2+(3072<<2),prach2,(3072<<3)); // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | empty3072 | empty3072 - memmove(prach2+((3072<<1)*3),prach2,(3072<<3)); + memmove(prach2+(3072<<3),prach2,(3072<<3)); // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072 memmove(prach,prach+(3072<<1),(Ncp<<2)); // here we have |Prefix | Prach3072 | From ac12245252a7c084119960cad419be62b0da3010 Mon Sep 17 00:00:00 2001 From: Bo Zhao Date: Wed, 28 Aug 2019 15:55:05 +0200 Subject: [PATCH 010/553] Bugfix: 1. fix the initial memory allocation; 2. correct the generation of the prach signal according to specs --- openair1/PHY/INIT/nr_init_ru.c | 6 ++++- openair1/PHY/NR_UE_TRANSPORT/nr_prach.c | 29 ++++++++++++++----------- openair1/SIMULATION/NR_PHY/prachsim.c | 4 ++-- 3 files changed, 23 insertions(+), 16 deletions(-) diff --git a/openair1/PHY/INIT/nr_init_ru.c b/openair1/PHY/INIT/nr_init_ru.c index 2dcf035866..ecf558d4ca 100644 --- a/openair1/PHY/INIT/nr_init_ru.c +++ b/openair1/PHY/INIT/nr_init_ru.c @@ -39,6 +39,9 @@ int nr_phy_init_RU(RU_t *ru) { int p; int re; + // For memory allocation of ru->prach_rxsigF + int mu = fp->numerology_index; + LOG_I(PHY,"Initializing RU signal buffers (if_south %s) nb_tx %d\n",ru_if_types[ru->if_south],ru->nb_tx); nfapi_nr_config_request_scf_t *cfg; @@ -107,7 +110,8 @@ int nr_phy_init_RU(RU_t *ru) { ru->prach_rxsigF = (int16_t**)malloc(ru->nb_rx * sizeof(int16_t*)); for (i=0; inb_rx; i++) { - ru->prach_rxsigF[i] = (int16_t*)malloc16_clear( fp->ofdm_symbol_size*12*2*sizeof(int16_t) ); + // for preamble format 1 and 2, more memory should be allocated + ru->prach_rxsigF[i] = (int16_t*)malloc16_clear( fp->ofdm_symbol_size*12*(1<rxsigF[%d] = %p\n",i,ru->prach_rxsigF[i]); } diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c index abf849202e..a98820b69c 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c @@ -337,7 +337,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, break; case 1: - Ncp = 2*21024; + Ncp = 21024; break; case 2: @@ -400,7 +400,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, if (prach_fmt == 0) { //24576 samples @ 30.72 Ms/s, 49152 samples @ 61.44 Ms/s idft49152(prachF,prach2,1); // here we have |empty | Prach49152| - memmove(prach,prach+(49152<<1),(Ncp<<3)); + memmove(prach,prach+(49152<<1),(Ncp<<2)); // here we have |Prefix | Prach49152| prach_len = 49152+Ncp; dftlen=49152; @@ -409,7 +409,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, idft49152(prachF,prach2,1); memmove(prach2+(49152<<1),prach2,(49152<<2)); // here we have |empty | Prach49152 | Prach49152| - memmove(prach,prach+(49152<<2),(Ncp<<3)); + memmove(prach,prach+(49152<<2),(Ncp<<2)); // here we have |Prefix | Prach49152 | Prach49152| prach_len = (49152*2)+Ncp; dftlen=49152; @@ -420,7 +420,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, // here we have |empty | Prach49152 | Prach49152| empty49152 | empty49152 memmove(prach2+(49152<<2),prach2,(49152<<3)); // here we have |empty | Prach49152 | Prach49152| Prach49152 | Prach49152 - memmove(prach,prach+(49152<<3),(Ncp<<3)); + memmove(prach,prach+(49152<<3),(Ncp<<2)); // here we have |Prefix | Prach49152 | Prach49152| Prach49152 | Prach49152 prach_len = (49152*4)+Ncp; dftlen=49152; @@ -431,7 +431,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, // here we have |empty | Prach12288 | Prach12288| empty12288 | empty12288 memmove(prach2+(12288<<2),prach2,(12288<<3)); // here we have |empty | Prach12288 | Prach12288| Prach12288 | Prach12288 - memmove(prach,prach+(12288<<3),(Ncp<<3)); + memmove(prach,prach+(12288<<3),(Ncp<<2)); // here we have |Prefix | Prach12288 | Prach12288| Prach12288 | Prach12288 prach_len = (12288*4)+Ncp; dftlen=12288; @@ -540,11 +540,14 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, idft1536(prachF,prach2,1); dftlen=1536; // here we have |empty | Prach1536 | - if (prach_fmt != 0xc0) - memmove(prach2+(1536<<1),prach2,(1536<<2)); + if (prach_fmt != 0xc0) { + memmove(prach2+(1536<<1),prach2,(1536<<2)); + prach_len = (1536*2)+Ncp; + } + else prach_len = (1536*1)+Ncp; memmove(prach,prach+(1536<<1),(Ncp<<2)); // here we have |Prefix | Prach1536 | Prach1536 (if ! 0xc0) | - prach_len = (1536*2)+Ncp; + } else if (prach_fmt == 0xa2 || prach_fmt == 0xb2) { // 6x1536 idft1536(prachF,prach2,1); @@ -631,7 +634,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, // here we have |empty | Prach24576 | Prach24576| Prach24576 | Prach24576 memmove(prach,prach+(24576<<3),(Ncp<<2)); // here we have |Prefix | Prach24576 | Prach24576| Prach24576 | Prach24576 - prach_len = (24576*4)+(Ncp<<1); + prach_len = (24576*4)+Ncp; } else if (prach_fmt == 0xa1 || prach_fmt == 0xb1 || prach_fmt == 0xc0) { idft4096(prachF,prach2,1); @@ -696,7 +699,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, idft73728(prachF,prach2,1); dftlen=73728; // here we have |empty | Prach73728| - memmove(prach,prach+(73728<<1),(Ncp<<4)); + memmove(prach,prach+(73728<<1),(Ncp<<2)); // here we have |Prefix | Prach73728| prach_len = (73728*1)+Ncp; } @@ -705,7 +708,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, dftlen=73728; memmove(prach2+(73728<<1),prach2,(73728<<2)); // here we have |empty | Prach73728 | Prach73728| - memmove(prach,prach+(73728<<2),(Ncp<<4)); + memmove(prach,prach+(73728<<2),(Ncp<<2)); // here we have |Prefix | Prach73728 | Prach73728| prach_len = (73728*2)+Ncp; } @@ -716,7 +719,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, // here we have |empty | Prach73728 | Prach73728| empty73728 | empty73728 memmove(prach2+(73728<<2),prach2,(73728<<3)); // here we have |empty | Prach73728 | Prach73728| Prach73728 | Prach73728 - memmove(prach,prach+(73728<<3),(Ncp<<4)); + memmove(prach,prach+(73728<<3),(Ncp<<2)); // here we have |Prefix | Prach73728 | Prach73728| Prach73728 | Prach73728 prach_len = (73728*4)+Ncp; } @@ -727,7 +730,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, // here we have |empty | Prach18432 | Prach18432| empty18432 | empty18432 memmove(prach2+(18432<<2),prach2,(18432<<3)); // here we have |empty | Prach18432 | Prach18432| Prach18432 | Prach18432 - memmove(prach,prach+(18432<<3),(Ncp<<4)); + memmove(prach,prach+(18432<<3),(Ncp<<2)); // here we have |Prefix | Prach18432 | Prach18432| Prach18432 | Prach18432 prach_len = (18432*4)+Ncp; } diff --git a/openair1/SIMULATION/NR_PHY/prachsim.c b/openair1/SIMULATION/NR_PHY/prachsim.c index 3771aa3b3e..71715c98be 100644 --- a/openair1/SIMULATION/NR_PHY/prachsim.c +++ b/openair1/SIMULATION/NR_PHY/prachsim.c @@ -530,7 +530,7 @@ int main(int argc, char **argv) // multipath channel dump_nr_prach_config(&gNB->frame_parms,subframe); - for (i=0; i<2*frame_parms->samples_per_slot<<1; i++) { + for (i=0; isamples_per_slot<<1; i++) { for (aa=0; aa<1; aa++) { if (awgn_flag == 0) { s_re[aa][i] = ((double)(((short *)&txdata[aa][subframe*frame_parms->samples_per_slot<<1]))[(i<<1)]); @@ -573,7 +573,7 @@ int main(int argc, char **argv) if (awgn_flag == 0) { multipath_tv_channel(UE2gNB,s_re,s_im,r_re,r_im, - 2*frame_parms->samples_per_slot<<1,0); + frame_parms->samples_per_slot<<1,0); } if (n_frames==1) { From 7ea608720f31df1c86231dba9ce57efe4c3fcfaa Mon Sep 17 00:00:00 2001 From: Bo Zhao Date: Wed, 28 Aug 2019 15:58:38 +0200 Subject: [PATCH 011/553] Extend the length of the channel processing to 32 bits --- .../SIMULATION/TOOLS/multipath_tv_channel.c | 18 +++++++++++------- openair1/SIMULATION/TOOLS/sim.h | 2 +- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/openair1/SIMULATION/TOOLS/multipath_tv_channel.c b/openair1/SIMULATION/TOOLS/multipath_tv_channel.c index f4835570bf..d344992586 100644 --- a/openair1/SIMULATION/TOOLS/multipath_tv_channel.c +++ b/openair1/SIMULATION/TOOLS/multipath_tv_channel.c @@ -27,18 +27,20 @@ #include "SIMULATION/RF/rf.h" #include -void tv_channel(channel_desc_t *desc,double complex ***H,uint16_t length); +void tv_channel(channel_desc_t *desc,double complex ***H,uint32_t length); double frand_a_b(double a, double b); -void tv_conv(double complex **h, double complex *x, double complex *y, uint16_t nb_samples, uint8_t nb_taps, int delay); +void tv_conv(double complex **h, double complex *x, double complex *y, uint32_t nb_samples, uint8_t nb_taps, int delay); void multipath_tv_channel(channel_desc_t *desc, double **tx_sig_re, double **tx_sig_im, double **rx_sig_re, double **rx_sig_im, - uint16_t length, - uint8_t keep_channel) { - double complex **tx,**rx,* **H_t,*rx_temp; //, *tv_H_t; + uint32_t length, + uint8_t keep_channel) +{ + + double complex **tx,**rx,***H_t,*rx_temp;//, *tv_H_t; double path_loss = pow(10,desc->path_loss_dB/20); int i,j,k,dd; dd = abs(desc->channel_offset); @@ -126,7 +128,8 @@ void multipath_tv_channel(channel_desc_t *desc, } //TODO: make phi_rad a parameter of this function -void tv_channel(channel_desc_t *desc,double complex ***H,uint16_t length) { +void tv_channel(channel_desc_t *desc,double complex ***H,uint32_t length){ + int i,j,p,l,k; double *alpha,*phi_rad,pi=acos(-1),*w_Hz; alpha = (double *)calloc(desc->nb_paths,sizeof(double)); @@ -193,7 +196,8 @@ void tv_channel(channel_desc_t *desc,double complex ***H,uint16_t length) { } // time varying convolution -void tv_conv(double complex **h, double complex *x, double complex *y, uint16_t nb_samples, uint8_t nb_taps, int dd) { +void tv_conv(double complex **h, double complex *x, double complex *y, uint32_t nb_samples, uint8_t nb_taps, int dd){ + int i,j; for(i=0; i<((int)nb_samples-dd); i++) { diff --git a/openair1/SIMULATION/TOOLS/sim.h b/openair1/SIMULATION/TOOLS/sim.h index 0bc5975d99..4b1b7edcdd 100644 --- a/openair1/SIMULATION/TOOLS/sim.h +++ b/openair1/SIMULATION/TOOLS/sim.h @@ -426,7 +426,7 @@ void multipath_tv_channel(channel_desc_t *desc, double **tx_sig_im, double **rx_sig_re, double **rx_sig_im, - uint16_t length, + uint32_t length, uint8_t keep_channel); /**@} */ From 5aec9ab5055304fd5008871755884a070d9f8687 Mon Sep 17 00:00:00 2001 From: Bo Zhao Date: Fri, 30 Aug 2019 10:31:47 +0200 Subject: [PATCH 012/553] Solve the uninitialized conditional jump and invalid read/write errors from the valgrind log --- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 2 ++ openair1/SIMULATION/NR_PHY/prachsim.c | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index d76c2592f2..e8e3ac66ee 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -2412,6 +2412,8 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t e ue->prach_resources[eNB_id] = &prach_resources; ue->prach_resources[eNB_id]->ra_PreambleIndex = preamble_tx; ue->prach_resources[eNB_id]->ra_TDD_map_index = 0; + ue->prach_resources[eNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER = 10; + ue->prach_resources[eNB_id]->ra_RNTI = 93; } if (ue->mac_enabled==1){ diff --git a/openair1/SIMULATION/NR_PHY/prachsim.c b/openair1/SIMULATION/NR_PHY/prachsim.c index 71715c98be..33c00e82f4 100644 --- a/openair1/SIMULATION/NR_PHY/prachsim.c +++ b/openair1/SIMULATION/NR_PHY/prachsim.c @@ -101,7 +101,7 @@ int main(int argc, char **argv) uint8_t hs_flag=0; int n_frames=1; channel_desc_t *UE2gNB; - uint32_t nsymb,tx_lev; //,tx_lev_dB; + uint32_t nsymb,tx_lev=10000; //,tx_lev_dB; // int8_t interf1=-19,interf2=-19; NR_DL_FRAME_PARMS *frame_parms; @@ -613,7 +613,7 @@ int main(int argc, char **argv) LOG_M("prach0.m","prach0", &txdata[0][subframe*frame_parms->samples_per_slot<<1],frame_parms->samples_per_slot<<1,1,1); - LOG_M("prachF0.m","prachF0", &gNB->prach_vars.prachF[0],24576,1,1); + LOG_M("prachF0.m","prachF0", &gNB->prach_vars.prachF[0],1024,1,1); LOG_M("rxsig0.m","rxs0", &gNB->common_vars.rxdata[0][subframe*frame_parms->samples_per_slot<<1], frame_parms->samples_per_slot<<1,1,1); From e0e8bbcfdb38474865785fb3c08127b5a3b66041 Mon Sep 17 00:00:00 2001 From: Guido Casati Date: Mon, 19 Aug 2019 17:57:36 +0200 Subject: [PATCH 013/553] RACH MAC procedure (RA initiation and Preamble selection) - Updated PRACH procedures and general code formatting - gNB msg1 handling and RAR generation - general bug fixing - formatting - missing headers - RAR handling. --- cmake_targets/CMakeLists.txt | 31 +- executables/nr-gnb.c | 2 +- executables/nr-ru.c | 2 +- executables/nr-ue.c | 4 +- executables/nr-uesoftmodem.c | 4 +- executables/nr-uesoftmodem.h | 2 +- .../nfapi/public_inc/fapi_nr_ue_constants.h | 1 + openair1/PHY/INIT/nr_init.c | 1 - openair1/PHY/NR_TRANSPORT/nr_prach_common.c | 32 +- openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h | 2 +- openair1/PHY/NR_UE_TRANSPORT/nr_prach.c | 10 - openair1/PHY/TOOLS/nr_phy_scope.h | 2 +- openair1/PHY/defs_nr_UE.h | 10 +- openair1/PHY/defs_nr_common.h | 23 + openair1/SCHED_NR_UE/defs.h | 14 +- openair1/SCHED_NR_UE/fapi_nr_ue_l1.c | 2 +- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 519 ++++++------- openair1/SCHED_NR_UE/pucch_uci_ue_nr.c | 2 +- openair1/SIMULATION/NR_PHY/dlsim.c | 10 +- openair1/SIMULATION/NR_PHY/prachsim.c | 5 +- openair1/SIMULATION/NR_PHY/ulsim.c | 5 +- openair2/GNB_APP/gnb_config.c | 3 +- openair2/LAYER2/MAC/eNB_scheduler.c | 2 +- openair2/LAYER2/NR_MAC_COMMON/nr_mac.h | 35 + .../nr_mac_common.h | 2 + openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h | 26 +- openair2/LAYER2/NR_MAC_UE/config_ue.c | 4 +- openair2/LAYER2/NR_MAC_UE/mac_defs.h | 109 ++- openair2/LAYER2/NR_MAC_UE/mac_proto.h | 36 +- openair2/LAYER2/NR_MAC_UE/main_ue_nr.c | 2 +- openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c | 155 ++++ openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 726 ++++++++++++++++++ openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 26 +- openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c | 157 ++++ openair2/LAYER2/NR_MAC_gNB/config.c | 2 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 12 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 553 ++++++++++++- .../LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c | 6 +- .../LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c | 7 +- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 4 +- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 181 ++++- .../LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c | 2 +- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 96 ++- openair2/LAYER2/NR_MAC_gNB/main.c | 4 +- openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 181 +++-- openair2/NR_PHY_INTERFACE/NR_IF_Module.c | 27 +- openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c | 38 +- openair2/RRC/NR/L2_nr_interface.c | 36 +- openair2/RRC/NR_UE/rrc_UE.c | 2 +- openair2/RRC/NR_UE/rrc_defs.h | 4 +- 50 files changed, 2576 insertions(+), 545 deletions(-) rename openair2/LAYER2/{NR_MAC_gNB => NR_MAC_COMMON}/nr_mac_common.h (98%) create mode 100644 openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c create mode 100644 openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c create mode 100644 openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index b84ffd38a0..76f2a485ea 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -1605,7 +1605,7 @@ add_library(PHY_MEX ${PHY_MEX_UE} ${CONFIG_LIB}) #Layer 2 library ##################### set(MAC_DIR ${OPENAIR2_DIR}/LAYER2/MAC) -set(NR_MAC_DIR ${OPENAIR2_DIR}/LAYER2/NR_MAC_gNB) +set(NR_GNB_MAC_DIR ${OPENAIR2_DIR}/LAYER2/NR_MAC_gNB) set(NR_UE_MAC_DIR ${OPENAIR2_DIR}/LAYER2/NR_MAC_UE) set(PHY_INTERFACE_DIR ${OPENAIR2_DIR}/PHY_INTERFACE) set(NR_PHY_INTERFACE_DIR ${OPENAIR2_DIR}/NR_PHY_INTERFACE) @@ -1757,14 +1757,17 @@ set (MAC_SRC set (MAC_NR_SRC ${NR_PHY_INTERFACE_DIR}/NR_IF_Module.c - ${NR_MAC_DIR}/main.c - ${NR_MAC_DIR}/config.c - ${NR_MAC_DIR}/gNB_scheduler.c - ${NR_MAC_DIR}/gNB_scheduler_bch.c - ${NR_MAC_DIR}/gNB_scheduler_dlsch.c - ${NR_MAC_DIR}/gNB_scheduler_ulsch.c - ${NR_MAC_DIR}/gNB_scheduler_primitives.c - ${NR_MAC_DIR}/gNB_scheduler_phytest.c + ${NR_GNB_MAC_DIR}/main.c + ${NR_GNB_MAC_DIR}/config.c + ${NR_GNB_MAC_DIR}/gNB_scheduler.c + ${NR_GNB_MAC_DIR}/gNB_scheduler_bch.c + ${NR_GNB_MAC_DIR}/gNB_scheduler_dlsch.c + ${NR_GNB_MAC_DIR}/gNB_scheduler_ulsch.c + ${NR_GNB_MAC_DIR}/gNB_scheduler_primitives.c + ${NR_GNB_MAC_DIR}/gNB_scheduler_phytest.c + ${NR_GNB_MAC_DIR}/gNB_scheduler_RA.c + ${NR_UE_MAC_DIR}/nr_l1_helpers.c + ${NR_UE_MAC_DIR}/nr_ra_procedures.c ) @@ -1776,7 +1779,6 @@ set (MAC_SRC_UE ${MAC_DIR}/l1_helpers.c ${MAC_DIR}/rar_tools_ue.c ${MAC_DIR}/config_ue.c - ) set (MAC_NR_SRC_UE @@ -1786,6 +1788,9 @@ set (MAC_NR_SRC_UE ${NR_UE_MAC_DIR}/main_ue_nr.c ${NR_UE_MAC_DIR}/nr_ue_procedures.c ${NR_UE_MAC_DIR}/nr_ue_dci_configuration.c + ${NR_UE_MAC_DIR}/nr_l1_helpers.c + ${NR_UE_MAC_DIR}/nr_ra_procedures.c + ${NR_UE_MAC_DIR}/rar_tools_nrUE.c ) set (ENB_APP_SRC @@ -1849,7 +1854,7 @@ add_library( NR_L2_UE ${NR_L2_SRC_UE} ${MAC_NR_SRC_UE} ) add_library( MAC_NR_COMMON ${OPENAIR2_DIR}/LAYER2/NR_MAC_COMMON/nr_mac_common.c ${OPENAIR2_DIR}/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c) include_directories("${OPENAIR2_DIR}/NR_UE_PHY_INTERFACE") -include_directories("${OPENAIR2_DIR}/LAYER2/NR_MAC_UE") +include_directories("${OPENAIR2_DIR}/LAYER2") include_directories("${OPENAIR1_DIR}/SCHED_NR_UE") #include_directories("${NFAPI_USER_DIR}"") @@ -2636,9 +2641,9 @@ add_executable(nr-uesoftmodem target_link_libraries (nr-uesoftmodem -Wl,--start-group RRC_LIB NR_RRC_LIB SECU_CN SECU_OSA UTIL HASHTABLE SCTP_CLIENT UDP SCHED_RU_LIB SCHED_UE_LIB SCHED_NR_UE_LIB + PHY_COMMON PHY_NR_COMMON PHY_UE PHY_NR_UE PHY_RU LFDS NR_L2_UE L2_UE MAC_NR_COMMON NFAPI_COMMON_LIB NFAPI_LIB NFAPI_PNF_LIB + NFAPI_USER_LIB S1AP_LIB S1AP_ENB ${MSC_LIB} ${RAL_LIB} ${NAS_UE_LIB} ${ITTI_LIB} ${FLPT_MSG_LIB} ${ASYNC_IF_LIB} LFDS7 ${ATLAS_LIBRARIES} - PHY_COMMON PHY_NR_COMMON PHY_UE PHY_NR_UE PHY_RU LFDS L2_UE NR_L2_UE MAC_NR_COMMON S1AP_LIB S1AP_ENB - NFAPI_COMMON_LIB NFAPI_LIB NFAPI_PNF_LIB NFAPI_USER_LIB -Wl,--end-group z dl) target_link_libraries (nr-uesoftmodem ${LIBXML2_LIBRARIES}) diff --git a/executables/nr-gnb.c b/executables/nr-gnb.c index 0302697e5b..dedee9b651 100644 --- a/executables/nr-gnb.c +++ b/executables/nr-gnb.c @@ -63,7 +63,7 @@ #include "LAYER2/MAC/mac.h" -#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" +#include "NR_MAC_COMMON/nr_mac_extern.h" #include "LAYER2/MAC/mac_proto.h" #include "RRC/LTE/rrc_extern.h" #include "PHY_INTERFACE/phy_interface.h" diff --git a/executables/nr-ru.c b/executables/nr-ru.c index 42d7a2a48a..1e6ae12e09 100644 --- a/executables/nr-ru.c +++ b/executables/nr-ru.c @@ -72,7 +72,7 @@ #include "SCHED_NR/sched_nr.h" #include "LAYER2/MAC/mac.h" -#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" +#include "NR_MAC_COMMON/nr_mac_extern.h" #include "LAYER2/MAC/mac_proto.h" #include "RRC/LTE/rrc_extern.h" #include "PHY_INTERFACE/phy_interface.h" diff --git a/executables/nr-ue.c b/executables/nr-ue.c index d8eda68d05..bbdcd0c29c 100644 --- a/executables/nr-ue.c +++ b/executables/nr-ue.c @@ -21,7 +21,7 @@ #include "executables/thread-common.h" #include "executables/nr-uesoftmodem.h" -#include "LAYER2/NR_MAC_UE/mac.h" +#include "NR_MAC_UE/mac.h" //#include "RRC/LTE/rrc_extern.h" #include "PHY_INTERFACE/phy_interface_extern.h" @@ -32,7 +32,7 @@ #include "PHY/phy_extern_nr_ue.h" #include "PHY/INIT/phy_init.h" #include "PHY/MODULATION/modulation_UE.h" -#include "LAYER2/NR_MAC_UE/mac_proto.h" +#include "NR_MAC_UE/mac_proto.h" #include "RRC/NR_UE/rrc_proto.h" //#ifndef NO_RAT_NR diff --git a/executables/nr-uesoftmodem.c b/executables/nr-uesoftmodem.c index fb0f18f2f5..e2f32529a1 100644 --- a/executables/nr-uesoftmodem.c +++ b/executables/nr-uesoftmodem.c @@ -72,8 +72,8 @@ unsigned short config_frames[4] = {2,9,11,13}; #include "PHY/INIT/phy_init.h" #include "system.h" #include -#include -#include +#include "NR_MAC_UE/mac_defs.h" +#include "NR_MAC_UE/mac_proto.h" #include #include diff --git a/executables/nr-uesoftmodem.h b/executables/nr-uesoftmodem.h index 891b97514c..3438f31373 100644 --- a/executables/nr-uesoftmodem.h +++ b/executables/nr-uesoftmodem.h @@ -4,7 +4,7 @@ #include #include "PHY/defs_nr_UE.h" #include "SIMULATION/ETH_TRANSPORT/proto.h" -#include +#include "NR_MAC_gNB/mac_proto.h" /***************************************************************************************************************************************/ /* command line options definitions, CMDLINE_XXXX_DESC macros are used to initialize paramdef_t arrays which are then used as argument diff --git a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h index cbcd26c3e3..4b0720078a 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h @@ -18,6 +18,7 @@ #define FAPI_NR_RX_PDU_TYPE_SIB 0x02 #define FAPI_NR_RX_PDU_TYPE_DLSCH 0x03 #define FAPI_NR_DCI_IND 0x04 +#define FAPI_NR_RX_PDU_TYPE_RAR 0x05 #define FAPI_NR_SIBS_MASK_SIB1 0x1 diff --git a/openair1/PHY/INIT/nr_init.c b/openair1/PHY/INIT/nr_init.c index df9747104a..3c93442c8d 100644 --- a/openair1/PHY/INIT/nr_init.c +++ b/openair1/PHY/INIT/nr_init.c @@ -38,7 +38,6 @@ #include "PHY/NR_TRANSPORT/nr_ulsch.h" #include "PHY/NR_REFSIG/nr_refsig.h" #include "SCHED_NR/fapi_nr_l1.h" -#include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h" #include "nfapi_nr_interface.h" /* diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c index e1b80a87a2..82ad498c2a 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c @@ -110,23 +110,25 @@ void nr_fill_du(uint8_t prach_fmt) int is_nr_prach_subframe(NR_DL_FRAME_PARMS *frame_parms,uint32_t frame, uint8_t subframe) { uint8_t prach_ConfigIndex = frame_parms->prach_config_common.prach_ConfigInfo.prach_ConfigIndex; - /* + // For FR1 paired - if (((frame%table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][2]) == table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][3]) && - ((table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][4]&(1<frame_type == FDD && frame_parms->freq_range == nr_FR1){ + if (((frame%table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][2]) == table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][3]) && + ((table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][4]&(1<frame_type == TDD && frame_parms->freq_range == nr_FR1) { // For FR1 unpaired - if (((frame%table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][2]) == table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][3]) && - ((table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][4]&(1< #include #include -#include +#include "LAYER2/NR_MAC_gNB/nr_mac_gNB.h" #include "common/ran_context.h" #include #include diff --git a/openair1/PHY/defs_nr_UE.h b/openair1/PHY/defs_nr_UE.h index 1ad0c7529e..e88bfd7768 100644 --- a/openair1/PHY/defs_nr_UE.h +++ b/openair1/PHY/defs_nr_UE.h @@ -930,7 +930,7 @@ typedef struct { uint8_t pucch_sel[10]; uint8_t pucch_payload[22]; - UE_MODE_t UE_mode[NUMBER_OF_CONNECTED_eNB_MAX]; + UE_MODE_t UE_mode[NUMBER_OF_CONNECTED_gNB_MAX]; /// cell-specific reference symbols uint32_t lte_gold_table[7][20][2][14]; @@ -967,10 +967,10 @@ typedef struct { - unsigned char ulsch_Msg3_active[NUMBER_OF_CONNECTED_eNB_MAX]; - uint32_t ulsch_Msg3_frame[NUMBER_OF_CONNECTED_eNB_MAX]; - unsigned char ulsch_Msg3_subframe[NUMBER_OF_CONNECTED_eNB_MAX]; - PRACH_RESOURCES_t *prach_resources[NUMBER_OF_CONNECTED_eNB_MAX]; + unsigned char ulsch_Msg3_active[NUMBER_OF_CONNECTED_gNB_MAX]; + uint32_t ulsch_Msg3_frame[NUMBER_OF_CONNECTED_gNB_MAX]; + unsigned char ulsch_Msg3_subframe[NUMBER_OF_CONNECTED_gNB_MAX]; + NR_PRACH_RESOURCES_t *prach_resources[NUMBER_OF_CONNECTED_gNB_MAX]; int turbo_iterations, turbo_cntl_iterations; /// \brief ?. /// - first index: eNB [0..NUMBER_OF_CONNECTED_eNB_MAX[ (hard coded) diff --git a/openair1/PHY/defs_nr_common.h b/openair1/PHY/defs_nr_common.h index 487b28473f..5241f5736d 100644 --- a/openair1/PHY/defs_nr_common.h +++ b/openair1/PHY/defs_nr_common.h @@ -223,6 +223,29 @@ typedef struct { NR_PRACH_CONFIG_INFO prach_ConfigInfo; } NR_PRACH_CONFIG_COMMON; +typedef struct { + /// Preamble index for PRACH (0-63) + uint8_t ra_PreambleIndex; + /// RACH MaskIndex + uint8_t ra_RACH_MaskIndex; + /// Target received power at eNB (-120 ... -82 dBm) + uint32_t ra_PREAMBLE_RECEIVED_TARGET_POWER; + /// PRACH index for TDD (0 ... 6) depending on TDD configuration and prachConfigIndex + uint8_t ra_TDD_map_index; + /// RA Preamble Power Ramping Step in dB + uint32_t RA_PREAMBLE_POWER_RAMPING_STEP; + /// + uint8_t RA_PREAMBLE_BACKOFF; + /// + uint8_t RA_SCALING_FACTOR_BI; + /// + uint8_t RA_PCMAX; + /// Corresponding RA-RNTI for UL-grant + uint16_t ra_RNTI; + /// Pointer to Msg3 payload for UL-grant + uint8_t *Msg3; +} NR_PRACH_RESOURCES_t; + typedef struct NR_DL_FRAME_PARMS { /// frequency range nr_frequency_range_e freq_range; diff --git a/openair1/SCHED_NR_UE/defs.h b/openair1/SCHED_NR_UE/defs.h index e34ce2b6de..c6aea2ec08 100644 --- a/openair1/SCHED_NR_UE/defs.h +++ b/openair1/SCHED_NR_UE/defs.h @@ -218,6 +218,15 @@ void ra_failed(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index); */ void ra_succeeded(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index); +/*! \brief UE PRACH procedures. + @param + @param + @param + */ +void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t gNB_id, runmode_t mode); + +int is_nr_prach_subframe(NR_DL_FRAME_PARMS *frame_parms, uint32_t frame, uint8_t subframe); + #if 0 /*! \brief Compute ACK/NACK information for PUSCH/PUCCH for UE transmission in subframe n. This function implements table 10.1-1 of 36.213, p. 69. @param frame_parms Pointer to DL frame parameter descriptor @@ -322,13 +331,14 @@ uint16_t nr_get_n1_pucch(PHY_VARS_NR_UE *phy_vars_ue, uint8_t SR); #endif + /*! \brief This function retrieves the PHY UE mode. It is used as a helper function for the UE MAC. @param Mod_id Local UE index on which to act @param CC_id Component Carrier Index - @param eNB_index ID of eNB + @param gNB_index ID of gNB @returns UE mode */ -UE_MODE_t get_ue_mode(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index); +UE_MODE_t get_nrUE_mode(uint8_t Mod_id,uint8_t CC_id,uint8_t gNB_index); /*! \brief This function implements the power control mechanism for PUCCH from 36.213. @param phy_vars_ue PHY variables diff --git a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c index c6a830a8da..7dbb68cf31 100644 --- a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c +++ b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c @@ -58,7 +58,7 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response) NR_UE_DLSCH_t *dlsch0 = PHY_vars_UE_g[module_id][cc_id]->dlsch[thread_id][0][0]; NR_UE_ULSCH_t *ulsch0 = PHY_vars_UE_g[module_id][cc_id]->ulsch[thread_id][0][0]; //NR_DL_FRAME_PARMS frame_parms = PHY_vars_UE_g[module_id][cc_id]->frame_parms; - PRACH_RESOURCES_t *prach_resources = PHY_vars_UE_g[module_id][cc_id]->prach_resources[0]; + NR_PRACH_RESOURCES_t *prach_resources = PHY_vars_UE_g[module_id][cc_id]->prach_resources[0]; // PUCCH_ConfigCommon_nr_t *pucch_config_common = PHY_vars_UE_g[module_id][cc_id]->pucch_config_common_nr[0]; // PUCCH_Config_t *pucch_config_dedicated = PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0]; diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index e8e3ac66ee..5a292661fd 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -66,6 +66,7 @@ #endif #include "LAYER2/NR_MAC_UE/mac_defs.h" +#include "LAYER2/NR_MAC_UE/mac_proto.h" #include "common/utils/LOG/log.h" #ifdef EMOS @@ -308,51 +309,6 @@ void nr_dump_dlsch_ra(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id, write_output("dlsch_mag2.m","dlschmag2",ue->pdsch_vars_ra[0]->dl_ch_magb0,300*nsymb,1,1); } -void phy_reset_ue(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index) -{ - - // This flushes ALL DLSCH and ULSCH harq buffers of ALL connected eNBs...add the eNB_index later - // for more flexibility - - uint8_t i,j,k,s; - PHY_VARS_NR_UE *ue = PHY_vars_UE_g[Mod_id][CC_id]; - - //[NUMBER_OF_RX_THREAD=2][NUMBER_OF_CONNECTED_eNB_MAX][2]; - for(int l=0; ldlsch[l][i][j]) { - for(k=0; kdlsch[l][i][j]->harq_processes[k]; k++) { - ue->dlsch[l][i][j]->harq_processes[k]->status = SCH_IDLE; - for (s=0; s<10; s++) { - // reset ACK/NACK bit to DTX for all nr_tti_rxs s = 0..9 - ue->dlsch[l][i][j]->harq_ack[s].ack = 2; - ue->dlsch[l][i][j]->harq_ack[s].send_harq_status = 0; - ue->dlsch[l][i][j]->harq_ack[s].vDAI_UL = 0xff; - ue->dlsch[l][i][j]->harq_ack[s].vDAI_DL = 0xff; - } - } - } - } - - //UL HARQ - if(ue->ulsch[i]) { - for(k=0; kulsch[i]->harq_processes[k]; k++) { - ue->ulsch[i]->harq_processes[k]->status = SCH_IDLE; - //Set NDIs for all UL HARQs to 0 - // ue->ulsch[i]->harq_processes[k]->Ndi = 0; - - } - } - - // flush Msg3 buffer - ue->ulsch_Msg3_active[i] = 0; - - } - } -} - void ra_failed(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index) { @@ -388,25 +344,6 @@ void ra_succeeded(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index) } -} - -UE_MODE_t get_ue_mode(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index) -{ - - return(PHY_vars_UE_g[Mod_id][CC_id]->UE_mode[eNB_index]); - -} -void nr_process_timing_advance_rar(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint16_t timing_advance) { - - ue->timing_advance = timing_advance*4; - - -#ifdef DEBUG_PHY_PROC - /* TODO: fix this log, what is 'HW timing advance'? */ - /*LOG_I(PHY,"[UE %d] AbsoluteSubFrame %d.%d, received (rar) timing_advance %d, HW timing advance %d\n",ue->Mod_id,proc->frame_rx, proc->nr_tti_rx_rx, ue->timing_advance);*/ - LOG_I(PHY,"[UE %d] AbsoluteSubFrame %d.%d, received (rar) timing_advance %d\n",ue->Mod_id,proc->frame_rx, proc->nr_tti_rx, ue->timing_advance); -#endif - } uint8_t nr_is_SR_TXOp(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id) @@ -1399,6 +1336,9 @@ void ulsch_common_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_ #endif +UE_MODE_t get_nrUE_mode(uint8_t Mod_id,uint8_t CC_id,uint8_t gNB_id){ // TBR generate enum for NR + return(PHY_vars_UE_g[Mod_id][CC_id]->UE_mode[gNB_id]); +} void nr_process_timing_advance(module_id_t Mod_id, uint8_t CC_id, uint8_t ta_command, uint8_t mu, uint16_t bwp_ul_NB_RB){ @@ -1421,7 +1361,23 @@ void nr_process_timing_advance(module_id_t Mod_id, uint8_t CC_id, uint8_t ta_com LOG_D(PHY, "[UE %d] Got timing advance command %u from MAC, new value is %u\n", Mod_id, ta_command, PHY_vars_UE_g[Mod_id][CC_id]->timing_advance); } +void nr_process_timing_advance_rar(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint16_t timing_advance) { + +/* TODO TBR FIX THIS + +ue->timing_advance = timing_advance*4; + +#ifdef DEBUG_PHY_PROC + // TODO: fix this log, what is 'HW timing advance'? + //LOG_I(PHY,"[UE %d] AbsoluteSubFrame %d.%d, received (rar) timing_advance %d, HW timing advance %d\n",ue->Mod_id,proc->frame_rx, proc->nr_tti_rx_rx, ue->timing_advance); + LOG_I(PHY,"[UE %d] AbsoluteSubFrame %d.%d, received (rar) timing_advance %d\n",ue->Mod_id,proc->frame_rx, proc->nr_tti_rx, ue->timing_advance); +#endif + */ + +} + #if 0 + void ue_ulsch_uespec_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t eNB_id, @@ -2329,11 +2285,12 @@ void ue_pucch_procedures(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t gNB_id, - uint8_t thread_id) -{ + uint8_t thread_id){ //int32_t ulsch_start=0; int slot_tx = proc->nr_tti_tx; int frame_tx = proc->frame_tx; + uint8_t harq_pid = 0; // TBR + runmode_t mode = normal_txrx; // TBR set proper mode VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX,VCD_FUNCTION_IN); @@ -2343,15 +2300,12 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, start_meas(&ue->phy_proc_tx); #endif - uint8_t harq_pid = 0; //temporary implementation - nr_ue_ulsch_procedures(ue, harq_pid, slot_tx, thread_id, gNB_id); - /* if (ue->UE_mode[eNB_id] == PUSCH) { // check if we need to use PUCCH 1a/1b @@ -2361,7 +2315,6 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, } // UE_mode==PUSCH */ - nr_ue_pusch_common_procedures(ue, harq_pid, slot_tx, @@ -2369,23 +2322,20 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, gNB_id, &ue->frame_parms); - //LOG_M("txdata.m","txs",ue->common_vars.txdata[0],1228800,1,1); - -/* - if ((ue->UE_mode[eNB_id] == PRACH) && - (ue->frame_parms.prach_config_common.prach_Config_enabled==1)) { + /* RACH */ + if ((ue->UE_mode[gNB_id] == PRACH) && (ue->frame_parms.prach_config_common.prach_Config_enabled == 1)) { // check if we have PRACH opportunity - - if (is_prach_subframe(&ue->frame_parms,frame_tx,nr_tti_tx)) { - - ue_prach_procedures(ue,proc,eNB_id,abstraction_flag,mode); + if (is_nr_prach_subframe(&ue->frame_parms, frame_tx, slot_tx)) { + // TBR TODO FIX this works only for TDD but it enters phy_procedures_nrUE_TX only when mode is FDD + printf("the value of is_nr_prach subframe is %d\n", is_nr_prach_subframe(&ue->frame_parms, frame_tx, slot_tx)); // TBR debug + nr_ue_prach_procedures(ue, proc, gNB_id, mode); } - } // mode is PRACH - else { - ue->generate_prach=0; } -*/ + else { + ue->generate_nr_prach = 0; + } +/* RACH */ LOG_I(PHY,"****** end TX-Chain for AbsSubframe %d.%d ******\n", frame_tx, slot_tx); @@ -2396,139 +2346,6 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, } - -void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t abstraction_flag,runmode_t mode) { - - int frame_tx = proc->frame_tx; - int nr_tti_tx = proc->nr_tti_tx; - int prach_power; - uint16_t preamble_tx=ue->prach_resources[0]->ra_PreambleIndex; - PRACH_RESOURCES_t prach_resources; - - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_IN); - - ue->generate_nr_prach=0; - if (ue->mac_enabled==0){ - ue->prach_resources[eNB_id] = &prach_resources; - ue->prach_resources[eNB_id]->ra_PreambleIndex = preamble_tx; - ue->prach_resources[eNB_id]->ra_TDD_map_index = 0; - ue->prach_resources[eNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER = 10; - ue->prach_resources[eNB_id]->ra_RNTI = 93; - } - - if (ue->mac_enabled==1){ - - // ask L2 for RACH transport - if ((mode != rx_calib_ue) && (mode != rx_calib_ue_med) && (mode != rx_calib_ue_byp) && (mode != no_L2_connect) ) { - LOG_D(PHY,"Getting PRACH resources\n"); - //ue->prach_resources[eNB_id] = mac_xface->ue_get_rach(ue->Mod_id,ue->CC_id,frame_tx,eNB_id,nr_tti_tx); - // LOG_D(PHY,"Got prach_resources for eNB %d address %p, RRCCommon %p\n",eNB_id,ue->prach_resources[eNB_id],UE_mac_inst[ue->Mod_id].radioResourceConfigCommon); - // LOG_D(PHY,"Prach resources %p\n",ue->prach_resources[eNB_id]); - } -} - -if (ue->prach_resources[eNB_id]!=NULL) { - - ue->generate_nr_prach=1; - ue->prach_cnt=0; -#ifdef SMBV -ue->prach_resources[eNB_id]->ra_PreambleIndex = preamble_tx; -#endif - -#ifdef OAI_EMU - ue->prach_PreambleIndex=ue->prach_resources[eNB_id]->ra_PreambleIndex; -#endif - - if (abstraction_flag == 0) { - - LOG_I(PHY,"mode %d\n",mode); - - if ((ue->mac_enabled==1) && (mode != calib_prach_tx)) { - - ue->tx_power_dBm[nr_tti_tx] = ue->prach_resources[eNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER+get_nr_PL(ue,eNB_id); - } - else { - ue->tx_power_dBm[nr_tti_tx] = ue->tx_power_max_dBm; - ue->prach_resources[eNB_id]->ra_PreambleIndex = preamble_tx; - } - - LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d : Generating PRACH, preamble %d,PL %d, P0_PRACH %d, TARGET_RECEIVED_POWER %d dBm, PRACH TDD Resource index %d, RA-RNTI %d\n", - ue->Mod_id, - frame_tx, - nr_tti_tx, - ue->prach_resources[eNB_id]->ra_PreambleIndex, - get_nr_PL(ue,eNB_id), - ue->tx_power_dBm[nr_tti_tx], - ue->prach_resources[eNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER, - ue->prach_resources[eNB_id]->ra_TDD_map_index, - ue->prach_resources[eNB_id]->ra_RNTI); - - ue->tx_total_RE[nr_tti_tx] = 96; - -#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706) - ue->prach_vars[eNB_id]->amp = get_tx_amp(ue->tx_power_dBm[nr_tti_tx], - ue->tx_power_max_dBm, - ue->frame_parms.N_RB_UL, - 6); -#else - ue->prach_vars[eNB_id]->amp = AMP; -#endif - if ((mode == calib_prach_tx) && (((proc->frame_tx&0xfffe)%100)==0)) - LOG_D(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d : PRACH TX power %d dBm, amp %d\n", - ue->Mod_id, - proc->frame_rx, - proc->nr_tti_tx, - ue->tx_power_dBm[nr_tti_tx], - ue->prach_vars[eNB_id]->amp); - - - // start_meas(&ue->tx_prach); - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GENERATE_PRACH, VCD_FUNCTION_IN); - -// prach_power = generate_nr_prach(ue,eNB_id,nr_tti_tx,frame_tx); -prach_power = generate_nr_prach(ue,0,9,0); //subframe number hardcoded according to the simulator - - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GENERATE_PRACH, VCD_FUNCTION_OUT); - // stop_meas(&ue->tx_prach); - LOG_D(PHY,"[UE %d][RAPROC] PRACH PL %d dB, power %d dBm, digital power %d dB (amp %d)\n", - ue->Mod_id, - get_nr_PL(ue,eNB_id), - ue->tx_power_dBm[nr_tti_tx], - dB_fixed(prach_power), - ue->prach_vars[eNB_id]->amp); - }/* else { - UE_transport_info[ue->Mod_id][ue->CC_id].cntl.prach_flag=1; - UE_transport_info[ue->Mod_id][ue->CC_id].cntl.prach_id=ue->prach_resources[eNB_id]->ra_PreambleIndex; - }*/ // commented for compiling as abstraction flag is 0 - - if (ue->mac_enabled==1){ - //mac_xface->Msg1_transmitted(ue->Mod_id,ue->CC_id,frame_tx,eNB_id); - } - -LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d: Generating PRACH (eNB %d) preamble index %d for UL, TX power %d dBm (PL %d dB), l3msg \n", - ue->Mod_id,frame_tx,nr_tti_tx,eNB_id, - ue->prach_resources[eNB_id]->ra_PreambleIndex, - ue->prach_resources[eNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER+get_nr_PL(ue,eNB_id), - get_nr_PL(ue,eNB_id)); - -} - - -// if we're calibrating the PRACH kill the pointer to its resources so that the RA protocol doesn't continue -if (mode == calib_prach_tx) - ue->prach_resources[eNB_id]=NULL; - -LOG_D(PHY,"[UE %d] frame %d nr_tti_rx %d : generate_nr_prach %d, prach_cnt %d\n", - ue->Mod_id,frame_tx,nr_tti_tx,ue->generate_nr_prach,ue->prach_cnt); - -ue->prach_cnt++; - -if (ue->prach_cnt==3) - ue->generate_nr_prach=0; - -VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_OUT); -} - /* void phy_procedures_UE_S_TX(PHY_VARS_NR_UE *ue,uint8_t eNB_id,uint8_t abstraction_flag,relaying_type_t r_type) { @@ -3349,19 +3166,17 @@ void nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB } // CRNTI active } } -#if 0 -void process_rar(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB_id, runmode_t mode, int abstraction_flag) { +/*void nr_process_rar(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB_id, runmode_t mode, int abstraction_flag) { // TBR todo int frame_rx = proc->frame_rx; int nr_tti_rx = proc->nr_tti_rx; int timing_advance; NR_UE_DLSCH_t *dlsch0 = ue->dlsch_ra[eNB_id]; int harq_pid = 0; uint8_t *rar; - /* - uint8_t next1_thread_id = ue->current_thread_id[nr_tti_rx]== (RX_NB_TH-1) ? 0:(ue->current_thread_id[nr_tti_rx]+1); - uint8_t next2_thread_id = next1_thread_id== (RX_NB_TH-1) ? 0:(next1_thread_id+1); - */ + + // uint8_t next1_thread_id = ue->current_thread_id[nr_tti_rx]== (RX_NB_TH-1) ? 0:(ue->current_thread_id[nr_tti_rx]+1); + // uint8_t next2_thread_id = next1_thread_id== (RX_NB_TH-1) ? 0:(next1_thread_id+1); LOG_D(PHY,"[UE %d][RAPROC] Frame %d nr_tti_rx %d Received RAR mode %d\n", ue->Mod_id, @@ -3377,28 +3192,24 @@ void process_rar(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB_id, runmod nr_tti_rx, ue->prach_resources[eNB_id]->ra_PreambleIndex); - /* timing_advance = mac_xface->ue_process_rar(ue->Mod_id, - ue->CC_id, - frame_rx, - ue->prach_resources[eNB_id]->ra_RNTI, - dlsch0->harq_processes[0]->b, - &ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->crnti, - ue->prach_resources[eNB_id]->ra_PreambleIndex, - dlsch0->harq_processes[0]->b); // alter the 'b' buffer so it contains only the selected RAR header and RAR payload - */ - /* - ue->pdcch_vars[next1_thread_id][eNB_id]->crnti = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->crnti; - ue->pdcch_vars[next2_thread_id][eNB_id]->crnti = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->crnti; - */ + // TBR restore + // timing_advance = nr_ue_process_rar(ue->Mod_id, ue->CC_id, frame_rx, + // ue->prach_resources[eNB_id]->ra_RNTI, dlsch0->harq_processes[0]->b, + // &ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->crnti, + // ue->prach_resources[eNB_id]->ra_PreambleIndex, dlsch0->harq_processes[0]->b); // alter the 'b' buffer so it contains only the selected RAR header and RAR payload + + // ue->pdcch_vars[next1_thread_id][eNB_id]->crnti = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->crnti; + // ue->pdcch_vars[next2_thread_id][eNB_id]->crnti = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->crnti; if (timing_advance!=0xffff) { - LOG_D(PHY,"[UE %d][RAPROC] Frame %d nr_tti_rx %d Got rnti %x and timing advance %d from RAR\n", - ue->Mod_id, - frame_rx, - nr_tti_rx, - ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->crnti, - timing_advance); + // TBR restore + // LOG_D(PHY,"[UE %d][RAPROC] Frame %d nr_tti_rx %d Got rnti %x and timing advance %d from RAR\n", + // ue->Mod_id, + // frame_rx, + // nr_tti_rx, + // ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->crnti, + // timing_advance); // remember this c-rnti is still a tc-rnti @@ -3409,11 +3220,12 @@ void process_rar(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB_id, runmod if (mode!=debug_prach) { ue->ulsch_Msg3_active[eNB_id]=1; - nr_get_Msg3_alloc(&ue->frame_parms, - nr_tti_rx, - frame_rx, - &ue->ulsch_Msg3_frame[eNB_id], - &ue->ulsch_Msg3_subframe[eNB_id]); + // TBR nr_get_Msg3_alloc has to be fixed + // nr_get_Msg3_alloc(&ue->frame_parms, + // nr_tti_rx, + // frame_rx, + // &ue->ulsch_Msg3_frame[eNB_id], + // &ue->ulsch_Msg3_subframe[eNB_id]); LOG_D(PHY,"[UE %d][RAPROC] Got Msg3_alloc Frame %d nr_tti_rx %d: Msg3_frame %d, Msg3_subframe %d\n", ue->Mod_id, @@ -3424,11 +3236,11 @@ void process_rar(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB_id, runmod harq_pid = nr_subframe2harq_pid(&ue->frame_parms, ue->ulsch_Msg3_frame[eNB_id], ue->ulsch_Msg3_subframe[eNB_id]); - ue->ulsch[eNB_id]->harq_processes[harq_pid]->round = 0; + //ue->ulsch[eNB_id]->harq_processes[harq_pid]->round = 0; // TODO TBR fix this when HARQ is ready ue->UE_mode[eNB_id] = RA_RESPONSE; // ue->Msg3_timer[eNB_id] = 10; - ue->ulsch[eNB_id]->power_offset = 6; + //ue->ulsch[eNB_id]->power_offset = 6; // TODO TBR fix this ue->ulsch_no_allocation_counter[eNB_id] = 0; } } else { // PRACH preamble doesn't match RAR @@ -3443,9 +3255,7 @@ void process_rar(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB_id, runmod timing_advance = ((((uint16_t)(rar[0]&0x7f))<<4) + (rar[1]>>4)); nr_process_timing_advance_rar(ue,proc,timing_advance); } - -} -#endif +}*/ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, @@ -3540,13 +3350,13 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, if (frame_rx < *dlsch_errors) *dlsch_errors=0; - if (pdsch==RA_PDSCH) { + if (pdsch == RA_PDSCH) { if (ue->prach_resources[eNB_id]!=NULL) - dlsch0->rnti = ue->prach_resources[eNB_id]->ra_RNTI; + dlsch0->rnti = ue->prach_resources[eNB_id]->ra_RNTI; else { - LOG_E(PHY,"[UE %d] Frame %d, nr_tti_rx %d: FATAL, prach_resources is NULL\n",ue->Mod_id,frame_rx,nr_tti_rx); - //mac_xface->macphy_exit("prach_resources is NULL"); - return; + LOG_E(PHY,"[UE %d] Frame %d, nr_tti_rx %d: FATAL, prach_resources is NULL\n", ue->Mod_id, frame_rx, nr_tti_rx); + //mac_xface->macphy_exit("prach_resources is NULL"); + return; } } @@ -3734,7 +3544,15 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, dl_indication.proc=proc; //dl_indication.rx_ind->number_pdus - rx_ind.rx_indication_body[0].pdu_type = FAPI_NR_RX_PDU_TYPE_DLSCH; + switch (pdsch) { + case RA_PDSCH: + rx_ind.rx_indication_body[0].pdu_type = FAPI_NR_RX_PDU_TYPE_RAR; + break; + case PDSCH: + rx_ind.rx_indication_body[0].pdu_type = FAPI_NR_RX_PDU_TYPE_DLSCH; + break; + } + rx_ind.rx_indication_body[0].pdsch_pdu.pdu = dlsch0->harq_processes[harq_pid]->b; rx_ind.rx_indication_body[0].pdsch_pdu.pdu_length = dlsch0->harq_processes[harq_pid]->TBS>>3; LOG_D(PHY, "PDU length in bits: %d, in bytes: %d \n", dlsch0->harq_processes[harq_pid]->TBS, rx_ind.rx_indication_body[0].pdsch_pdu.pdu_length); @@ -4367,11 +4185,11 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, if ((ue->dlsch_SI[eNB_id]) && (ue->dlsch_SI[eNB_id]->active == 1)) { VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC_SI, VCD_FUNCTION_IN); nr_ue_pdsch_procedures(ue, - proc, - eNB_id, - SI_PDSCH, - ue->dlsch_SI[eNB_id], - NULL); + proc, + eNB_id, + SI_PDSCH, + ue->dlsch_SI[eNB_id], + NULL); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC_SI, VCD_FUNCTION_OUT); } @@ -4380,11 +4198,11 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, if ((ue->dlsch_p[eNB_id]) && (ue->dlsch_p[eNB_id]->active == 1)) { VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC_P, VCD_FUNCTION_IN); nr_ue_pdsch_procedures(ue, - proc, - eNB_id, - P_PDSCH, - ue->dlsch_p[eNB_id], - NULL); + proc, + eNB_id, + P_PDSCH, + ue->dlsch_p[eNB_id], + NULL); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC_P, VCD_FUNCTION_OUT); } @@ -4393,13 +4211,37 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, if ((ue->dlsch_ra[eNB_id]) && (ue->dlsch_ra[eNB_id]->active == 1)) { VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC_RA, VCD_FUNCTION_IN); nr_ue_pdsch_procedures(ue, - proc, - eNB_id, - RA_PDSCH, - ue->dlsch_ra[eNB_id], - NULL); + proc, + eNB_id, + RA_PDSCH, + ue->dlsch_ra[eNB_id], + NULL); - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC_RA, VCD_FUNCTION_OUT); + // #if UE_TIMING_TRACE + // start_meas(&ue->dlsch_procedures_stat[ue->current_thread_id[nr_tti_rx]]); + // #endif + + nr_ue_dlsch_procedures(ue, + proc, + eNB_id, + RA_PDSCH, + ue->dlsch_ra[eNB_id], + NULL, + &ue->dlsch_ra_errors[eNB_id], + mode); + + // #if UE_TIMING_TRACE + // stop_meas(&ue->dlsch_procedures_stat[ue->current_thread_id[nr_tti_rx]]); + #if DISABLE_LOG_X + printf("[SFN %d] Slot1: Pdsch Proc %5.2f\n", nr_tti_rx, ue->pdsch_procedures_stat[ue->current_thread_id[nr_tti_rx]].p_time/(cpuf*1000.0)); + printf("[SFN %d] Slot0 Slot1: Dlsch Proc %5.2f\n", nr_tti_rx, ue->dlsch_procedures_stat[ue->current_thread_id[ nr_tti_rx]].p_time/(cpuf*1000.0)); + #else + LOG_D(PHY, "[SFN %d] Slot1: Pdsch Proc %5.2f\n", nr_tti_rx, ue->pdsch_procedures_stat[ue->current_thread_id[ nr_tti_rx]].p_time/(cpuf*1000.0)); + LOG_D(PHY, "[SFN %d] Slot0 Slot1: Dlsch Proc %5.2f\n", nr_tti_rx, ue->dlsch_procedures_stat[ue->current_thread_id[ nr_tti_rx]].p_time/(cpuf*1000.0)); + #endif + // #endif + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC_RA, VCD_FUNCTION_OUT); } // do procedures for C-RNTI @@ -4639,3 +4481,134 @@ uint8_t nr_is_ri_TXOp(PHY_VARS_NR_UE *ue, return(0); } +void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t gNB_id, runmode_t mode) { + /* TBR + // here params are hardcoded */ + int frame_tx = proc->frame_tx, nr_tti_tx = proc->nr_tti_tx, prach_power; + uint16_t preamble_tx=ue->prach_resources[0]->ra_PreambleIndex; //uint16_t preamble_tx=50; // TBR + NR_PRACH_RESOURCES_t prach_resources; + uint8_t mod_id = ue->Mod_id; + NR_UE_MAC_INST_t *nr_UE_mac_inst = get_mac_inst(mod_id); + UE_MODE_t UE_mode = get_nrUE_mode(mod_id, ue->CC_id, gNB_id); + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_IN); + + ue->generate_nr_prach = 0; + if (ue->mac_enabled == 0){ + ue->prach_resources[gNB_id] = &prach_resources; // TBR double check pointer + ue->prach_resources[gNB_id]->ra_PreambleIndex = preamble_tx; + ue->prach_resources[gNB_id]->ra_TDD_map_index = 0; + // ue->prach_resources[gNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER = 10; // TBR + // ue->prach_resources[gNB_id]->ra_RNTI = 93; // TBR + } else { + // ask L2 for RACH transport + /* TBR + // check if these modes are active */ + if ((mode != rx_calib_ue) && (mode != rx_calib_ue_med) && (mode != rx_calib_ue_byp) && (mode != no_L2_connect) ) { + LOG_D(PHY,"Getting PRACH resources. Frame %d Slot %d \n", frame_tx, nr_tti_tx); + ue->prach_resources[gNB_id] = nr_ue_get_rach(mod_id, ue->CC_id, UE_mode, frame_tx, gNB_id, nr_tti_tx); + // LOG_D(PHY,"Got prach_resources for gNB %d address %p, RRCCommon %p\n", gNB_id, ue->prach_resources[gNB_id], UE_mac_inst[ue->Mod_id].radioResourceConfigCommon); // TBR update this + } + } + + if (ue->prach_resources[gNB_id]!=NULL) { + + ue->generate_nr_prach = 1; + ue->prach_cnt = 0; + + #ifdef SMBV // TBR + ue->prach_resources[gNB_id]->ra_PreambleIndex = preamble_tx; + #endif + + #ifdef OAI_EMU // TBR + ue->prach_PreambleIndex=ue->prach_resources[gNB_id]->ra_PreambleIndex; + #endif + + // if (abstraction_flag == 0) { // TBR + + LOG_I(PHY,"mode %d\n",mode); + + if ((ue->mac_enabled==1) && (mode != calib_prach_tx)) { + /* TODO TBR + // check if ra_PREAMBLE_RECEIVED_TARGET_POWER is filled id */ + ue->tx_power_dBm[nr_tti_tx] = ue->prach_resources[gNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER + get_nr_PL(ue,gNB_id); + /* TODO TBR + DEBUG ONLY */ + printf("ue->tx_power_dBm[nr_tti_tx] %d ue->prach_resources[gNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER %d get_nr_PL(ue,gNB_id) %d\n", ue->tx_power_dBm[nr_tti_tx], ue->prach_resources[gNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER, get_nr_PL(ue,gNB_id)); + } else { + ue->tx_power_dBm[nr_tti_tx] = ue->tx_power_max_dBm; + ue->prach_resources[gNB_id]->ra_PreambleIndex = preamble_tx; /* TODO TBR this is hardcoded */ + } + + LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d : Generating PRACH, preamble %d,PL %d, P0_PRACH %d, TARGET_RECEIVED_POWER %d dBm, PRACH TDD Resource index %d, RA-RNTI %d\n", ue->Mod_id, + frame_tx, + nr_tti_tx, + ue->prach_resources[gNB_id]->ra_PreambleIndex, + get_nr_PL(ue,gNB_id), + ue->tx_power_dBm[nr_tti_tx], + ue->prach_resources[gNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER, + ue->prach_resources[gNB_id]->ra_TDD_map_index, + ue->prach_resources[gNB_id]->ra_RNTI); + + ue->tx_total_RE[nr_tti_tx] = 96; /* TODO TBR this is hardcoded */ + + #if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706) + ue->prach_vars[gNB_id]->amp = get_tx_amp(ue->tx_power_dBm[nr_tti_tx], /* TODO TBR get_tx_amp is still valid for NR ? */ + ue->tx_power_max_dBm, + ue->frame_parms.N_RB_UL, + 6); /* TODO TBR why 6 ? */ + #else + ue->prach_vars[gNB_id]->amp = AMP; /* TODO TBR where does this come from ? */ + #endif + + if ((mode == calib_prach_tx) && (((proc->frame_tx&0xfffe)%100)==0)) /* TODO TBR double check where calibration prach tx is handled */ + LOG_D(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d : PRACH TX power %d dBm, amp %d\n", + ue->Mod_id, + proc->frame_rx, + proc->nr_tti_tx, + ue->tx_power_dBm[nr_tti_tx], + ue->prach_vars[gNB_id]->amp); + + // start_meas(&ue->tx_prach); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GENERATE_PRACH, VCD_FUNCTION_IN); + + // prach_power = generate_nr_prach(ue,gNB_id,nr_tti_tx,frame_tx); + prach_power = generate_nr_prach(ue,0,9,0); //subframe number hardcoded according to the simulator /* TODO TBR this is hardcoded */ + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GENERATE_PRACH, VCD_FUNCTION_OUT); + // stop_meas(&ue->tx_prach); + LOG_D(PHY,"[UE %d][RAPROC] PRACH PL %d dB, power %d dBm, digital power %d dB (amp %d)\n", + ue->Mod_id, + get_nr_PL(ue,gNB_id), + ue->tx_power_dBm[nr_tti_tx], + dB_fixed(prach_power), + ue->prach_vars[gNB_id]->amp); + // } else { + // UE_transport_info[ue->Mod_id][ue->CC_id].cntl.prach_flag=1; + // UE_transport_info[ue->Mod_id][ue->CC_id].cntl.prach_id=ue->prach_resources[eNB_id]->ra_PreambleIndex; + // } // commented for compiling as abstraction flag is 0 + + if (ue->mac_enabled == 1) + // nr_Msg1_transmitted(ue->Mod_id, ue->CC_id, frame_tx, gNB_id); TBR + + + LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d: Generating PRACH (eNB %d) preamble index %d for UL, TX power %d dBm (PL %d dB), l3msg \n", + ue->Mod_id,frame_tx,nr_tti_tx,gNB_id, + ue->prach_resources[gNB_id]->ra_PreambleIndex, + ue->prach_resources[gNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER+get_nr_PL(ue,gNB_id), + get_nr_PL(ue,gNB_id)); + } + + // if we're calibrating the PRACH kill the pointer to its resources so that the RA protocol doesn't continue + if (mode == calib_prach_tx) + ue->prach_resources[gNB_id]=NULL; + + LOG_D(PHY,"[UE %d] frame %d nr_tti_rx %d : generate_nr_prach %d, prach_cnt %d\n", ue->Mod_id,frame_tx,nr_tti_tx,ue->generate_nr_prach,ue->prach_cnt); + + ue->prach_cnt++; + + if (ue->prach_cnt == 3) + ue->generate_nr_prach = 0; + + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_OUT); +} \ No newline at end of file diff --git a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c index 326c617dfb..eb2ce3598f 100644 --- a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c +++ b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c @@ -37,7 +37,7 @@ #include "PHY/defs_nr_UE.h" #include #include -#include "openair2/LAYER2/NR_MAC_UE/mac_proto.h" +#include "LAYER2/NR_MAC_UE/mac_proto.h" #ifndef NO_RAT_NR diff --git a/openair1/SIMULATION/NR_PHY/dlsim.c b/openair1/SIMULATION/NR_PHY/dlsim.c index 473c86bed0..cc3517215e 100644 --- a/openair1/SIMULATION/NR_PHY/dlsim.c +++ b/openair1/SIMULATION/NR_PHY/dlsim.c @@ -28,11 +28,9 @@ #include "common/ran_context.h" #include "common/config/config_userapi.h" #include "common/utils/LOG/log.h" -#include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h" -#include "openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h" -#include "openair2/LAYER2/NR_MAC_UE/mac_defs.h" -#include "openair2/LAYER2/NR_MAC_UE/mac_extern.h" -#include "openair2/LAYER2/NR_MAC_UE/mac_proto.h" +#include "LAYER2/NR_MAC_gNB/nr_mac_gNB.h" +#include "LAYER2/NR_MAC_UE/mac_defs.h" +#include "LAYER2/NR_MAC_UE/mac_extern.h" #include "PHY/defs_gNB.h" #include "PHY/defs_nr_common.h" #include "PHY/defs_nr_UE.h" @@ -55,7 +53,7 @@ #include "LAYER2/NR_MAC_UE/mac_proto.h" //#include "LAYER2/NR_MAC_gNB/mac_proto.h" //#include "openair2/LAYER2/NR_MAC_UE/mac_proto.h" -#include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h" +#include "LAYER2/NR_MAC_gNB/mac_proto.h" #include "NR_asn_constant.h" #include "RRC/NR/MESSAGES/asn1_msg.h" #include "openair1/SIMULATION/RF/rf.h" diff --git a/openair1/SIMULATION/NR_PHY/prachsim.c b/openair1/SIMULATION/NR_PHY/prachsim.c index 33c00e82f4..fac5d599c8 100644 --- a/openair1/SIMULATION/NR_PHY/prachsim.c +++ b/openair1/SIMULATION/NR_PHY/prachsim.c @@ -114,7 +114,7 @@ int main(int argc, char **argv) uint8_t subframe=9; uint16_t preamble_energy, preamble_tx=50, preamble_delay; uint16_t preamble_max,preamble_energy_max; - PRACH_RESOURCES_t prach_resources; + NR_PRACH_RESOURCES_t prach_resources; //uint8_t prach_fmt; //int N_ZC; int delay = 0; @@ -518,8 +518,7 @@ int main(int argc, char **argv) 0); //Nf */ //commented for testing purpose UE_nr_rxtx_proc_t proc={0}; - nr_ue_prach_procedures(UE,&proc,0,0,0); - + nr_ue_prach_procedures(UE,&proc,0,0); /* tx_lev_dB not used later, no need to set */ //tx_lev_dB = (unsigned int) dB_fixed(tx_lev); diff --git a/openair1/SIMULATION/NR_PHY/ulsim.c b/openair1/SIMULATION/NR_PHY/ulsim.c index 2c397090ba..e53e288602 100644 --- a/openair1/SIMULATION/NR_PHY/ulsim.c +++ b/openair1/SIMULATION/NR_PHY/ulsim.c @@ -52,8 +52,9 @@ #include "openair1/SIMULATION/TOOLS/sim.h" #include "openair1/SIMULATION/RF/rf.h" #include "openair1/SIMULATION/NR_PHY/nr_unitary_defs.h" -#include "openair2/LAYER2/NR_MAC_UE/mac_proto.h" -#include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h" +#include "openair1/SIMULATION/NR_PHY/nr_dummy_functions.c" +#include "LAYER2/NR_MAC_UE/mac_proto.h" +#include "LAYER2/NR_MAC_gNB/mac_proto.h" //#define DEBUG_ULSIM diff --git a/openair2/GNB_APP/gnb_config.c b/openair2/GNB_APP/gnb_config.c index 9845adbeaa..1c8657aec1 100644 --- a/openair2/GNB_APP/gnb_config.c +++ b/openair2/GNB_APP/gnb_config.c @@ -54,7 +54,8 @@ #include "common/config/config_userapi.h" //#include "RRC_config_tools.h" #include "gnb_paramdef.h" -#include "LAYER2/NR_MAC_gNB/mac_proto.h" +#include "NR_MAC_gNB/mac_proto.h" + #include "NR_asn_constant.h" #include "executables/thread-common.h" #include "NR_SCS-SpecificCarrier.h" diff --git a/openair2/LAYER2/MAC/eNB_scheduler.c b/openair2/LAYER2/MAC/eNB_scheduler.c index 8d497c80d3..433a490c19 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler.c +++ b/openair2/LAYER2/MAC/eNB_scheduler.c @@ -35,7 +35,7 @@ #include "LAYER2/MAC/mac_extern.h" #include "LAYER2/MAC/mac_proto.h" -#include "LAYER2/NR_MAC_gNB/mac_proto.h" +#include "NR_MAC_gNB/mac_proto.h" #include "common/utils/LOG/log.h" #include "nfapi/oai_integration/vendor_ext.h" #include "common/utils/LOG/vcd_signal_dumper.h" diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h index 7202f2e520..bbccb9f707 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h @@ -41,6 +41,10 @@ #define NR_BCCH_BCH 5 // MIB +#define CCCH_PAYLOAD_SIZE_MAX 128 + +#define RAR_PAYLOAD_SIZE_MAX 128 + // For both DL/UL-SCH // Except: // - UL/DL-SCH: fixed-size MAC CE(known by LCID) @@ -66,6 +70,12 @@ // F: lenght of L is 0:8 or 1:16 bits wide // R: Reserved bit, set to zero. +typedef enum { + RA_IDLE = 0, + WAIT_RAR = 1, + WAIT_CONTENTION_RESOLUTION = 2 +} RA_state_t; + typedef struct { uint8_t LCID:6; // octet 1 [5:0] uint8_t F:1; // octet 1 [6] @@ -92,6 +102,31 @@ typedef struct { uint8_t TAGID:2; // octet 1 [7:6] } __attribute__ ((__packed__)) NR_MAC_CE_TA; +// /*! \brief CCCH payload */ // TBR +// typedef struct { +// uint8_t payload[CCCH_PAYLOAD_SIZE_MAX]; +// } __attribute__ ((__packed__)) CCCH_PDU; +// +// /*! \brief RAR payload */ // TBR +// typedef struct { +// uint8_t payload[RAR_PAYLOAD_SIZE_MAX]; +// } __attribute__ ((__packed__)) RAR_PDU; + +/*!\brief MAC header of Random Access Response for Random access preamble identifier (RAPID) */ +typedef struct { + uint8_t RAPID:6; + uint8_t T:1; + uint8_t E:1; +} __attribute__ ((__packed__)) NR_RA_HEADER_RAPID; + +/*!\brief MAC header of Random Access Response for backoff indicator (BI)*/ +typedef struct { + uint8_t BI:4; + uint8_t R:2; + uint8_t T:1; + uint8_t E:1; +} __attribute__ ((__packed__)) NR_RA_HEADER_BI; + // 38.321 ch6.2.1, 38.331 #define DL_SCH_LCID_CCCH 0x00 #define DL_SCH_LCID_DCCH 0x01 diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_common.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h similarity index 98% rename from openair2/LAYER2/NR_MAC_gNB/nr_mac_common.h rename to openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h index 6b043963b0..1891bd0ee9 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_common.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h @@ -32,6 +32,8 @@ #ifndef __LAYER2_NR_MAC_COMMON_H__ #define __LAYER2_NR_MAC_COMMON_H__ +#include "NR_PDSCH-Config.h" + uint16_t config_bandwidth(int mu, int nb_rb, int nr_band); uint64_t from_nrarfcn(int nr_bandP, uint8_t scs_index, uint32_t dl_nrarfcn); diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h index 10df4567c4..4bc462f759 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h @@ -19,12 +19,12 @@ * contact@openairinterface.org */ -/*! \file extern.h +/*! \file nr_mac_extern.h * \brief NR mac externs -* \author G. Casati +* \author Navid Nikaein, Raymond Knopp, Guido Casati * \date 2019 * \version 1.0 -* \email guido.casati@iis.fraunhofer.de +* \email navid.nikaein@eurecom.fr, guido.casati@iis.fraunhofer.de * @ingroup _mac */ @@ -32,10 +32,11 @@ #ifndef __NR_MAC_EXTERN_H__ #define __NR_MAC_EXTERN_H__ -//#include "PHY/defs_common.h" -#include "nr_mac.h" -#include "RRC/LTE/rrc_defs.h" +#include "RRC/LTE/rrc_defs.h" // TBR #include "common/ran_context.h" +#include "nr_mac.h" + +/*#include "PHY/defs_common.h"*/ /* extern const uint32_t BSR_TABLE[BSR_TABLE_SIZE]; extern const uint32_t Extended_BSR_TABLE[BSR_TABLE_SIZE]; @@ -43,8 +44,6 @@ extern const uint8_t cqi2fmt0_agg[MAX_SUPPORTED_BW][CQI_VALUE_RANGE]; extern const uint8_t cqi2fmt1x_agg[MAX_SUPPORTED_BW][CQI_VALUE_RANGE]; extern const uint8_t cqi2fmt2x_agg[MAX_SUPPORTED_BW][CQI_VALUE_RANGE]; extern UE_RRC_INST *UE_rrc_inst; -extern eNB_ULSCH_INFO eNB_ulsch_info[NUMBER_OF_eNB_MAX][MAX_NUM_CCs][MAX_MOBILES_PER_ENB]; // eNBxUE = 8x8 -extern eNB_DLSCH_INFO eNB_dlsch_info[NUMBER_OF_eNB_MAX][MAX_NUM_CCs][MAX_MOBILES_PER_ENB]; // eNBxUE = 8x8 extern int cqi_to_mcs[16]; extern uint32_t RRC_CONNECTION_FLAG; extern uint8_t rb_table[34]; @@ -52,6 +51,9 @@ extern mac_rlc_am_muilist_t rlc_am_mui; extern SCHEDULER_MODES global_scheduler_mode; extern unsigned char NB_UE_INST;*/ + +extern eNB_ULSCH_INFO eNB_ulsch_info[NUMBER_OF_eNB_MAX][MAX_NUM_CCs][MAX_MOBILES_PER_ENB]; // eNBxUE = 8x8 +extern eNB_DLSCH_INFO eNB_dlsch_info[NUMBER_OF_eNB_MAX][MAX_NUM_CCs][MAX_MOBILES_PER_ENB]; // eNBxUE = 8x8 extern unsigned char NB_INST; extern unsigned char NB_eNB_INST; extern unsigned char NB_RN_INST; @@ -61,8 +63,15 @@ extern unsigned short NODE_ID[1]; extern RAN_CONTEXT_t RC; extern int phy_test; extern uint8_t nfapi_mode; +extern mac_rlc_am_muilist_t rlc_am_mui; +extern SCHEDULER_MODES global_scheduler_mode; /*#if defined(PRE_SCD_THREAD) +extern int cqi_to_mcs[16]; +extern uint32_t RRC_CONNECTION_FLAG; +extern uint8_t rb_table[34]; + +#if defined(PRE_SCD_THREAD) extern uint16_t pre_nb_rbs_required[2][MAX_NUM_CCs][NUMBER_OF_UE_MAX]; extern uint8_t dlsch_ue_select_tbl_in_use; extern uint8_t new_dlsch_ue_select_tbl_in_use; @@ -70,4 +79,5 @@ extern boolean_t pre_scd_activeUE[NUMBER_OF_UE_MAX]; extern eNB_UE_STATS pre_scd_eNB_UE_stats[MAX_NUM_CCs][NUMBER_OF_UE_MAX]; #endif*/ + #endif //DEF_H diff --git a/openair2/LAYER2/NR_MAC_UE/config_ue.c b/openair2/LAYER2/NR_MAC_UE/config_ue.c index c983023034..6250b53dd3 100755 --- a/openair2/LAYER2/NR_MAC_UE/config_ue.c +++ b/openair2/LAYER2/NR_MAC_UE/config_ue.c @@ -31,11 +31,11 @@ */ //#include "mac_defs.h" -#include "mac_proto.h" +#include "NR_MAC_UE/mac_proto.h" #include "NR_MAC-CellGroupConfig.h" -#include "../NR_MAC_gNB/nr_mac_common.h" +#include "LAYER2/NR_MAC_COMMON/nr_mac_common.h" #include "SCHED_NR/phy_frame_config_nr.h" int set_tdd_config_nr_ue(fapi_nr_config_request_t *cfg, diff --git a/openair2/LAYER2/NR_MAC_UE/mac_defs.h b/openair2/LAYER2/NR_MAC_UE/mac_defs.h index 37d1b1216d..ef733020e0 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_defs.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_defs.h @@ -37,6 +37,20 @@ #include #include #include "platform_types.h" + +/* PHY */ +#include "PHY/defs_nr_common.h" + +/* IF */ +#include "NR_IF_Module.h" +#include "fapi_nr_ue_interface.h" + +/* MAC */ +#include "LAYER2/NR_MAC_COMMON/nr_mac.h" +#include "LAYER2/NR_MAC_COMMON/nr_mac_common.h" +#include "LAYER2/MAC/mac.h" // TBR + +/* RRC */ #include "NR_DRX-Config.h" #include "NR_SchedulingRequestConfig.h" #include "NR_BSR-Config.h" @@ -48,12 +62,11 @@ #include "NR_PhysicalCellGroupConfig.h" #include "NR_SpCellConfig.h" #include "NR_ServingCellConfig.h" -#include "fapi_nr_ue_interface.h" -#include "NR_IF_Module.h" -#include "../NR_MAC_gNB/nr_mac_common.h" -#include "PHY/defs_nr_common.h" + +#include "NR_MAC_COMMON/nr_mac_extern.h" #define NB_NR_UE_MAC_INST 1 +#define MAX_NUM_BWP 2 typedef enum { SFN_C_MOD_2_EQ_0, @@ -61,14 +74,6 @@ typedef enum { SFN_C_IMPOSSIBLE } SFN_C_TYPE; - -#define MAX_NUM_BWP 2 - -typedef enum { - RA_IDLE=0, - WAIT_RAR=1, - WAIT_CONTENTION_RESOLUTION=2 -} RA_state_t; /*!\brief Top level UE MAC structure */ typedef struct { @@ -76,13 +81,13 @@ typedef struct { NR_ServingCellConfig_t *scd; int servCellIndex; //// MAC config - NR_DRX_Config_t *drx_Config; + NR_DRX_Config_t *drx_Config; NR_SchedulingRequestConfig_t *schedulingRequestConfig; - NR_BSR_Config_t *bsr_Config; - NR_TAG_Config_t *tag_Config; - NR_PHR_Config_t *phr_Config; - NR_RNTI_Value_t *cs_RNTI; - NR_MIB_t *mib; + NR_BSR_Config_t *bsr_Config; + NR_TAG_Config_t *tag_Config; + NR_PHR_Config_t *phr_Config; + NR_RNTI_Value_t *cs_RNTI; + NR_MIB_t *mib; NR_BWP_Downlink_t *DLbwp[MAX_NUM_BWP]; NR_BWP_Uplink_t *ULbwp[MAX_NUM_BWP]; @@ -95,15 +100,67 @@ typedef struct { SFN_C_TYPE type0_pdcch_ss_sfn_c; uint32_t type0_pdcch_ss_n_c; uint32_t type0_pdcch_consecutive_slots; - /// state of RA procedure - RA_state_t ra_state; - /// RA-rnti - uint16_t ra_rnti; - /// Temporary CRNTI - uint16_t t_crnti; - /// CRNTI - uint16_t crnti; + /* PDUs */ + /// Outgoing CCCH pdu for PHY + CCCH_PDU CCCH_pdu; + + /* Random Access parameters */ + /// state of RA procedure + RA_state_t ra_state; // TBR + /// RACH ConfigCommon + NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon; + /// RA-rnti + uint16_t ra_rnti; // TBR + /// Temporary CRNTI + uint16_t t_crnti; // TBR + /// CRNTI + uint16_t crnti; // TBR + /// number of attempt for rach + uint8_t RA_attempt_number; + /// Random-access procedure flag + uint8_t RA_active; + /// Random-access window counter + int8_t RA_window_cnt; + /// Random-access Msg3 size in bytes + uint8_t RA_Msg3_size; + /// Random-access prachMaskIndex + uint8_t RA_prachMaskIndex; + /// Flag indicating Preamble set (A,B) used for first Msg3 transmission + uint8_t RA_usedGroupA; + /// Random-access Resources + NR_PRACH_RESOURCES_t RA_prach_resources; + /// BeamfailurerecoveryConfig + NR_BeamFailureRecoveryConfig_t RA_BeamFailureRecoveryConfig; + /// Preamble Tx Counter + uint8_t RA_PREAMBLE_TRANSMISSION_COUNTER; + /// Preamble Power Ramping Counter + uint8_t RA_PREAMBLE_POWER_RAMPING_COUNTER; + /// Random-access backoff counter + int16_t RA_backoff_cnt; + /// Random-access variable for window calculation (frame of last change in window counter) + uint32_t RA_tx_frame; + /// Random-access variable for window calculation (subframe of last change in window counter) + uint8_t RA_tx_subframe; + /// Random-access Group B maximum path-loss + /// Random-access variable for backoff (frame of last change in backoff counter) + uint32_t RA_backoff_frame; + /// Random-access variable for backoff (subframe of last change in backoff counter) + uint8_t RA_backoff_subframe; + /// Random-access Group B maximum path-loss + uint16_t RA_maxPL; + /// Random-access Contention Resolution Timer active flag + uint8_t RA_contention_resolution_timer_active; + /// Random-access Contention Resolution Timer count value + uint8_t RA_contention_resolution_cnt; + /// Msg3 Delta Preamble + int8_t deltaPreamble_Msg3; + /// Flag to monitor if matching RAPID was received in RAR + uint8_t RA_RAPID_found; + /// UE_Mode variable should be used in the case of Phy_stub operation since we won't have access to PHY_VARS_UE + /// where the UE_mode originally is for the full stack operation mode. The transitions between the states of the UE_Mode + /// will be triggered within phy_stub_ue.c in this case + UE_MODE_t UE_mode[NUMBER_OF_CONNECTED_gNB_MAX]; //// FAPI-like interface message fapi_nr_tx_request_t tx_request; diff --git a/openair2/LAYER2/NR_MAC_UE/mac_proto.h b/openair2/LAYER2/NR_MAC_UE/mac_proto.h index 36d285e320..061b1fa399 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_proto.h @@ -124,8 +124,6 @@ uint32_t get_ssb_slot(uint32_t ssb_index); uint32_t mr_ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, uint8_t eNB_id, uint16_t rnti, sub_frame_t subframe); - - /* \brief Get payload (MAC PDU) from UE PHY @param module_idP Instance id of UE in machine @param CC_id Component Carrier index @@ -170,5 +168,39 @@ int set_tdd_config_nr_ue(fapi_nr_config_request_t *cfg, int mu, int nrofDownlinkSlots, int nrofDownlinkSymbols, int nrofUplinkSlots, int nrofUplinkSymbols); +/** \brief Function for UE/PHY to compute PUSCH transmit power in power-control procedure. + @param Mod_id Module id of UE + @returns Po_NOMINAL_PUSCH (PREAMBLE_RECEIVED_TARGET_POWER+DELTA_PREAMBLE +*/ +int8_t nr_get_Po_NOMINAL_PUSCH(module_id_t module_idP, uint8_t CC_id); + +/** \brief Function to compute DELTA_PREAMBLE from 38.321 subclause 7.3 + (for RA power ramping procedure and Msg3 PUSCH power control policy) + @param Mod_id Module id of UE + @returns DELTA_PREAMBLE +*/ +int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id); + +/* \brief Function called by PHY to process the received RAR and check that the preamble matches what was sent by the gNB. It provides the timing advance and t-CRNTI. +@param Mod_id Index of UE instance +@param CC_id Index to a component carrier +@param frame Frame index +@param ra_rnti RA_RNTI value +@param dlsch_buffer Pointer to dlsch_buffer containing RAR PDU +@param t_crnti Pointer to PHY variable containing the T_CRNTI +@param preamble_index Preamble Index used by PHY to transmit the PRACH. This should match the received RAR to trigger the rest of +random-access procedure +@param selected_rar_buffer the output buffer for storing the selected RAR header and RAR payload +@returns timing advance or 0xffff if preamble doesn't match +*/ +uint16_t nr_ue_process_rar(const module_id_t mod_id, + const int CC_id, + const frame_t frameP, + const rnti_t ra_rnti, + uint8_t * const dlsch_buffer, + rnti_t * const t_crnti, + const uint8_t preamble_index, + uint8_t * selected_rar_buffer); + #endif /** @}*/ diff --git a/openair2/LAYER2/NR_MAC_UE/main_ue_nr.c b/openair2/LAYER2/NR_MAC_UE/main_ue_nr.c index be1e852360..c057f5ee02 100644 --- a/openair2/LAYER2/NR_MAC_UE/main_ue_nr.c +++ b/openair2/LAYER2/NR_MAC_UE/main_ue_nr.c @@ -31,8 +31,8 @@ */ //#include "defs.h" -#include "mac_proto.h" #include "executables/nr-softmodem.h" +#include "NR_MAC_UE/mac_proto.h" static NR_UE_MAC_INST_t *nr_ue_mac_inst; diff --git a/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c b/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c new file mode 100644 index 0000000000..85c8cf8935 --- /dev/null +++ b/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c @@ -0,0 +1,155 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file nr_l1_helper.c +* \brief PHY helper function adapted to NR +* \author Guido Casati +* \date 2019 +* \version 1.0 +* \email guido.casati@iis.fraunhofer.de +* @ingroup _mac + +*/ + +#include "PHY/defs_common.h" // TBR +#include "PHY/defs_nr_common.h" + +#include "mac_defs.h" +#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" + +/* 38.321 subclause 7.3 - return values are in dB */ +int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id){ + + NR_UE_MAC_INST_t *nrUE_mac_inst = get_mac_inst(mod_id); + NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = nrUE_mac_inst->nr_rach_ConfigCommon; + + AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); + + NR_SubcarrierSpacing_t scs = nr_rach_ConfigCommon->msg1_SubcarrierSpacing; + uint8_t preambleFormat, prachConfigIndex; + lte_frame_type_t frame_type = TDD; // TODO TBR retrieve frame type. Currently hardcoded to TDD. + // was nr_UE_mac_inst[mod_id].tdd_Config + nr_frequency_range_e fr = nr_FR1; // TODO TBR retrieve frame type. Currently hardcoded to FR1. + int mu; + + switch (scs){ + case NR_SubcarrierSpacing_kHz15: + mu = 0; + break; + + case NR_SubcarrierSpacing_kHz30: + mu = 1; + break; + + case NR_SubcarrierSpacing_kHz60: + mu = 2; + break; + + case NR_SubcarrierSpacing_kHz120: + mu = 3; + break; + + case NR_SubcarrierSpacing_kHz240: + mu = 4; + break; + + case NR_SubcarrierSpacing_spare3: + mu = 5; + break; + + case NR_SubcarrierSpacing_spare2: + mu = 6; + break; + + case NR_SubcarrierSpacing_spare1: + mu = 7; + break; + + default: + AssertFatal(1 == 0,"Unknown msg1_SubcarrierSpacing %d\n", scs); + } + + prachConfigIndex = nr_rach_ConfigCommon->rach_ConfigGeneric.prach_ConfigurationIndex; + preambleFormat = get_nr_prach_fmt(prachConfigIndex,frame_type,fr); + + switch (preambleFormat) { + // long preamble formats + case 0: + case 3: + return 0; + + case 1: + return -3; + + case 2: + return -6; + + // short preamble formats + case 0xa1: + case 0xb1: + return 8 + 3*mu; + + case 0xa2: + case 0xb2: + case 0xc2: + return 5 + 3*mu; + + case 0xa3: + case 0xb3: + return 3 + 3*mu; + + case 0xb4: + return 3*mu; + + case 0xc0: + return 5 + 3*mu; + + default: + AssertFatal(1 == 0, "[UE %d] ue_procedures.c: FATAL, Illegal preambleFormat %d, prachConfigIndex %d\n", mod_id, preambleFormat, prachConfigIndex); + } + return; +} + +int8_t nr_get_Po_NOMINAL_PUSCH(module_id_t mod_id, uint8_t CC_id){ + + NR_UE_MAC_INST_t *nr_UE_mac_inst = get_mac_inst(mod_id); + NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = nr_UE_mac_inst->nr_rach_ConfigCommon; + NR_PRACH_RESOURCES_t *prach_resources = &nr_UE_mac_inst->RA_prach_resources; + + //AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); + AssertFatal(nr_rach_ConfigCommon != NULL, "[UE %d] CCid %d FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id, CC_id); + + int8_t receivedTargerPower = nr_rach_ConfigCommon->rach_ConfigGeneric.preambleReceivedTargetPower + nr_get_DELTA_PREAMBLE(mod_id, CC_id) + (nr_UE_mac_inst->RA_PREAMBLE_POWER_RAMPING_COUNTER - 1) * prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP; + + return receivedTargerPower; + //return (-120 + (nr_rach_ConfigCommon->rach_ConfigGeneric.preambleReceivedTargetPower << 1) + nr_get_DELTA_PREAMBLE(mod_id, CC_id) ); +} + +/*int8_t get_deltaP_rampup(module_id_t module_idP, uint8_t CC_id){ // TBR + + AssertFatal(CC_id == 0, + "Transmission on secondary CCs is not supported yet\n"); + + LOG_D(MAC, "[PUSCH]%d dB\n", + nrUE_mac_inst->RA_PREAMBLE_TRANSMISSION_COUNTER << 1); + return ((int8_t) + (nrUE_mac_inst->RA_PREAMBLE_TRANSMISSION_COUNTER << 1)); +}*/ \ No newline at end of file diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c new file mode 100644 index 0000000000..501f96b771 --- /dev/null +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -0,0 +1,726 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file ra_procedures.c + * \brief Routines for UE MAC-layer Random Access procedures (TS 38.321, Release 15) + * \author R. Knopp, Navid Nikaein, Guido Casati + * \date 2019 + * \version 0.1 + * \company Eurecom + * \email: knopp@eurecom.fr navid.nikaein@eurecom.fr, guido.casati@iis.fraunhofer.de + * \note + * \warning + */ + +#include "mac.h" +// TBR missing NR_nr_UE_mac_inst in mac.h + +/* +#include "common/utils/LOG/vcd_signal_dumper.h" +#include "PHY_INTERFACE/phy_interface_extern.h" +#include "SCHED_UE/sched_UE.h" +#include "COMMON/mac_rrc_primitives.h" +#include "RRC/LTE/rrc_extern.h" +#include "RRC/L2_INTERFACE/openair_rrc_L2_interface.h" +#include "common/utils/LOG/log.h" +#include "UTIL/OPT/opt.h" +#include "OCG.h" +#include "OCG_extern.h" +#include "PHY/LTE_ESTIMATION/lte_estimation.h"*/ + +/* Tools */ +#include "SIMULATION/TOOLS/sim.h" // for taus + +/* RRC */ +#include "NR_RACH-ConfigCommon.h" + +/* PHY */ +#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" +#include "PHY/defs_common.h" +#include "PHY/defs_nr_common.h" + +/* MAC */ +#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" +#include "NR_MAC_COMMON/nr_mac.h" +#include "LAYER2/NR_MAC_UE/mac_proto.h" + +extern UE_MODE_t get_nrUE_mode(uint8_t Mod_id, uint8_t CC_id, uint8_t gNB_id); + +extern int64_t table_6_3_3_2_2_prachConfig_Index [256][9]; +extern int64_t table_6_3_3_2_3_prachConfig_Index [256][9]; + +//extern uint8_t nfapi_mode; // TBR + +// This routine implements Section 5.1.2 (UE Random Access Resource Selection) +// and Section 5.1.3 (Random Access Preamble Transmission) from 3GPP TS 38.321 +void nr_get_prach_resources(module_id_t mod_id, + int CC_id, + uint8_t gNB_id, + uint8_t t_id, + uint8_t first_Msg3, + NR_RACH_ConfigDedicated_t * rach_ConfigDedicated){ + + NR_UE_MAC_INST_t *nr_UE_mac_inst = get_mac_inst(mod_id); + NR_PRACH_RESOURCES_t *prach_resources = &nr_UE_mac_inst->RA_prach_resources; + NR_BeamFailureRecoveryConfig_t *beam_failure_recovery_config = &nr_UE_mac_inst->RA_BeamFailureRecoveryConfig; + NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = nr_UE_mac_inst->nr_rach_ConfigCommon; + + int messagePowerOffsetGroupB, messageSizeGroupA, PLThreshold, sizeOfRA_PreamblesGroupA, numberOfRA_Preambles, frequencyStart, i, deltaPreamble_Msg3; + uint8_t noGroupB = 0, s_id, f_id, ul_carrier_id, msg1_FDM, prach_ConfigIndex, SFN_nbr, Msg3_size; + NR_RSRP_Range_t rsrp_ThresholdSSB; + + /* TBR retrieve following params + // currently hardcoded */ + prach_resources->ra_PreambleIndex = 51; + + /*uint8_t Msg3_size = nr_UE_mac_inst->RA_Msg3_size; + uint8_t f_id = 0, num_prach = 0;*/ + + /*AssertFatal(CC_id == 0, + "Transmission on secondary CCs is not supported yet\n"); + AssertFatal(nr_UE_mac_inst->nr_rach_ConfigCommon != NULL, + "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", + mod_id);*/ + + /////////////////////////////////////////////////////////// + //////////* UE Random Access Resource Selection *////////// + /////////////////////////////////////////////////////////// + + //numberOfRA_Preambles = (1 + nr_rach_ConfigCommon->preambleInfo.numberOfRA_Preambles) << 2; + numberOfRA_Preambles = nr_rach_ConfigCommon->totalNumberOfRA_Preambles; + rsrp_ThresholdSSB = *nr_rach_ConfigCommon->rsrp_ThresholdSSB; + nr_UE_mac_inst->nr_rach_ConfigCommon->rach_ConfigGeneric.prach_ConfigurationIndex; + + /* TBR switch initialisation cases + - RA initiated by beam failure recovery operation (subclause 5.17 TS 38.321) + - SSB selection, set prach_resources->ra_PreambleIndex + - RA initiated by PDCCH: ra_PreambleIndex provided by PDCCH && ra_PreambleIndex != 0b000000 + - set REAMBLE_INDEX to ra_PreambleIndex + - select the SSB signalled by PDCCH + - RA initiated for SI request: + - SSB selection, set prach_resources->ra_PreambleIndex */ + + // if (rach_ConfigDedicated) { // This is for network controlled Mobility + // // TBR operation for contention-free RA resources when: + // // - available SSB with SS-RSRP above rsrp-ThresholdSSB: SSB selection + // // - availalbe CSI-RS with CSI-RSRP above rsrp-ThresholdCSI-RS: CSI-RS selection + // prach_resources->ra_PreambleIndex = rach_ConfigDedicated->ra_PreambleIndex; + // return; + // } + + /* Contention-based RA preamble selection: + - TBR selection of SSB with SS-RSRP above rsrp-ThresholdSSB else select any SSB */ + if (!nr_rach_ConfigCommon->groupBconfigured) { + noGroupB = 1; + } else { + /* RA preambles group B is configured + // - Defining the number of RA preambles in RA Preamble Group A for each SSB */ + //sizeOfRA_PreamblesGroupA = (nr_rach_ConfigCommon->preambleInfo.preamblesGroupAConfig->sizeOfRA_PreamblesGroupA + 1) << 2; + sizeOfRA_PreamblesGroupA = nr_rach_ConfigCommon->groupBconfigured->numberOfRA_PreamblesGroupA; + switch (nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA){ + /* - Threshold to determine the groups of RA preambles */ + case 0: + messageSizeGroupA = 56; + break; + case 1: + messageSizeGroupA = 144; + break; + case 2: + messageSizeGroupA = 208; + break; + case 3: + messageSizeGroupA = 256; + break; + case 4: + messageSizeGroupA = 282; + break; + case 5: + messageSizeGroupA = 480; + break; + case 6: + messageSizeGroupA = 640; + break; + case 7: + messageSizeGroupA = 800; + break; + case 8: + messageSizeGroupA = 1000; + break; + case 9: + messageSizeGroupA = 72; + break; + default: + AssertFatal(1 == 0,"Unknown ra_Msg3SizeGroupA %d\n", nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA); + /* TBR cases 10 -15*/ + } + + /* - Power offset for preamble selection */ + /* TBR: what value to use as default? */ + messagePowerOffsetGroupB = -9999; + switch (nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB){ + case 0: + messagePowerOffsetGroupB = -9999; + break; + case 1: + messagePowerOffsetGroupB = 0; + break; + case 2: + messagePowerOffsetGroupB = 5; + break; + case 3: + messagePowerOffsetGroupB = 8; + break; + case 4: + messagePowerOffsetGroupB = 10; + break; + case 5: + messagePowerOffsetGroupB = 12; + break; + case 6: + messagePowerOffsetGroupB = 15; + break; + case 7: + messagePowerOffsetGroupB = 18; + break; + default: + AssertFatal(1 == 0,"Unknown messagePowerOffsetGroupB %d\n", nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB); + } + + // TBR Msg3-DeltaPreamble should be provided from higher layers, otherwise is 0 + nr_UE_mac_inst->deltaPreamble_Msg3 = 0; + deltaPreamble_Msg3 = nr_UE_mac_inst->deltaPreamble_Msg3; + } + + PLThreshold = prach_resources->RA_PCMAX - nr_rach_ConfigCommon->rach_ConfigGeneric.preambleReceivedTargetPower - deltaPreamble_Msg3 - messagePowerOffsetGroupB; + // PLThreshold = prach_resources->RA_PCMAX - nr_get_DELTA_PREAMBLE(mod_id, CC_id) - nr_get_Po_NOMINAL_PUSCH(mod_id, CC_id) - messagePowerOffsetGroupB; + // TBR Note Pcmax is set to 0 here, we have to fix this + + /* Msg3 has not been transmitted yet */ + if (first_Msg3 == 1) { + if (noGroupB == 1) { + // use Group A preamble + prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles; + prach_resources->ra_RACH_MaskIndex = 0; + nr_UE_mac_inst->RA_usedGroupA = 1; + } else if ((Msg3_size < messageSizeGroupA) && (get_PL(mod_id, 0, gNB_id) > PLThreshold)) { + // TBR update get_PL to NR + // TBR add condition for initiation by CCCH + // Group B is configured and RA preamble Group A is used + prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; + prach_resources->ra_RACH_MaskIndex = 0; + nr_UE_mac_inst->RA_usedGroupA = 1; + } else { + // Group B preamble is configured and used + // the first sizeOfRA_PreamblesGroupA RA preambles belong to RA Preambles Group A + // the remaining belong to RA Preambles Group B + prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); + prach_resources->ra_RACH_MaskIndex = 0; + nr_UE_mac_inst->RA_usedGroupA = 0; + } + + //TBR check why this is here + // prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = nr_get_Po_NOMINAL_PUSCH(mod_id, CC_id); + } else { + // Msg3 is being retransmitted + if (nr_UE_mac_inst->RA_usedGroupA == 1) { + if (nr_rach_ConfigCommon->groupBconfigured){ + prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; + } else { + prach_resources->ra_PreambleIndex = (taus()) & 0x3f; // TBR check this + prach_resources->ra_RACH_MaskIndex = 0; + } + } else { + // TBR FIXME nr_rach_ConfigCommon->preambleInfo.preamblesGroupAConfig may be zero + prach_resources->ra_PreambleIndex = + sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); + prach_resources->ra_RACH_MaskIndex = 0; + } + } + + // TBR determine next available PRACH occasion + // - if RA initiated for SI request and ra_AssociationPeriodIndex and si-RequestPeriod are configured + // - else if SSB is selected above + // - else if CSI-RS is selected above + + /* // choose random PRACH resource in TDD + if (nr_UE_mac_inst->tdd_Config) { + num_prach = get_num_prach_tdd(mod_id); + + if ((num_prach > 0) && (num_prach < 6)) + prach_resources->ra_TDD_map_index = (taus() % num_prach); + + f_id = get_fid_prach_tdd(mod_id, nr_UE_mac_inst [mod_id].RA_prach_resources->ra_TDD_map_index); + }*/ + + ///////////////////////////////////////////////////////////////////////////// + //////////* Random Access Preamble Transmission (5.1.3 TS 38.321) *////////// + ///////////////////////////////////////////////////////////////////////////// + + // TBR condition on notification of suspending power ramping counter from lower layer (5.1.3 TS 38.321) + // TBR check if SSB or CSI-RS have not changed since the selection in the last RA Preamble tranmission + if (nr_UE_mac_inst->RA_PREAMBLE_TRANSMISSION_COUNTER >1) + nr_UE_mac_inst->RA_PREAMBLE_TRANSMISSION_COUNTER++; + + //prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = nr_rach_ConfigCommon->rach_ConfigGeneric.preambleReceivedTargetPower + + // nr_get_DELTA_PREAMBLE(mod_id, CC_id) + (nr_UE_mac_inst->RA_PREAMBLE_POWER_RAMPING_COUNTER - 1) * prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP; // TBR + prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = nr_get_Po_NOMINAL_PUSCH(mod_id, CC_id); + + /* RA-RNTI computation (associated to PRACH occasion in which the RA Preamble is transmitted) + // 1) this does not apply to contention-free RA Preamble for beam failure recovery request + // 2) getting star_symb, SFN_nbr from table 6.3.3.2-3 (TDD and FR1 scenario) + // 3) TBR extend this (e.g. f_id selection, ul_carrier_id are hardcoded) */ + + ul_carrier_id = 0; // UL carrier used for RA preamble transmission, hardcoded for NUL carrier + f_id = 0; + //frequencyStart = nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FrequencyStart; + + switch (nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FDM){ + case 0: + msg1_FDM = 1; + break; + case 1: + msg1_FDM = 2; + break; + case 2: + msg1_FDM = 4; + break; + case 3: + msg1_FDM = 8; + break; + default: + AssertFatal(1 == 0,"Unknown msg1_FDM %d\n", nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FDM); + } + + prach_ConfigIndex = nr_rach_ConfigCommon->rach_ConfigGeneric.prach_ConfigurationIndex; + + // TBR this is for TDD FR1 only + SFN_nbr = table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][4]; + s_id = table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][5]; // starting symbol of the PRACH occasion + + // pick the first slot of the PRACH occasion in a system frame (0 <= t_id <= 80) + for (i = 0; i < 10; i++){ + if (((SFN_nbr & (1 << i)) >> i) == 1){ + t_id = 2*i; + break; + } + } + + prach_resources->ra_RNTI = 1 + s_id + 14 * t_id + 1120 * f_id + 8960 * ul_carrier_id; +} + +void nr_Msg1_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id){ + #if 0 //TBR + AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); + + // start contention resolution timer + nr_UE_mac_inst->RA_attempt_number++; + + if (opt_enabled) { + trace_pdu(DIRECTION_UPLINK, NULL, 0, mod_id, WS_NO_RNTI, nr_UE_mac_inst->RA_prach_resources->ra_PreambleIndex, nr_UE_mac_inst->txFrame, nr_UE_mac_inst->txSubframe, 0, nr_UE_mac_inst->RA_attempt_number); + LOG_D(OPT, "[UE %d][RAPROC] TX MSG1 Frame %d trace pdu for rnti %x with size %d\n", mod_id, frameP, 1, nr_UE_mac_inst->RA_Msg3_size); + } + #endif +} + + +void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id){ + #if 0 // TBR + AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); + + LOG_D(MAC,"[UE %d][RAPROC] Frame %d : Msg3_tx: Setting contention resolution timer\n", mod_id, frameP); + + // start contention resolution timer + nr_UE_mac_inst->RA_contention_resolution_cnt = 0; + nr_UE_mac_inst->RA_contention_resolution_timer_active = 1; + + if (opt_enabled) { + trace_pdu(DIRECTION_UPLINK, &nr_UE_mac_inst->CCCH_pdu.payload[0], nr_UE_mac_inst->RA_Msg3_size, mod_id, WS_C_RNTI, nr_UE_mac_inst->crnti, nr_UE_mac_inst->txFrame, nr_UE_mac_inst->txSubframe, 0, 0); + LOG_D(OPT, "[UE %d][RAPROC] MSG3 Frame %d trace pdu Preamble %d with size %d\n", mod_id, frameP, nr_UE_mac_inst->crnti /*nr_UE_mac_inst->RA_prach_resources->ra_PreambleIndex */, nr_UE_mac_inst->RA_Msg3_size); + } + #endif +} + +///////////////////////////////////////////////////////////////////////// +///////* Random Access Preamble Initialization (5.1.1 TS 38.321) */////// +///////////////////////////////////////////////////////////////////////// +/// Handling inizialization by PDCCH order, MAC entity or RRC (TS 38.300) +/// Only one RA procedure is ongoing at any point in time in a MAC entity +/// the RA procedure on a SCell shall only be initiated by PDCCH order + +NR_PRACH_RESOURCES_t *nr_ue_get_rach(module_id_t mod_id, + int CC_id, + UE_MODE_t UE_mode, + frame_t frame, + uint8_t gNB_id, + int nr_tti_tx){ + + NR_UE_MAC_INST_t *nr_UE_mac_inst = get_mac_inst(mod_id); + uint8_t size_sdu = 0, Nb_tb = 1, lcid = CCCH, dcch_header_len = 0, ulsch_buff[MAX_ULSCH_PAYLOAD_BYTES]; + // UE_MODE_t UE_mode; + uint16_t Size16, sdu_lengths; + NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = (struct NR_RACH_ConfigCommon_t *) NULL; + NR_PRACH_RESOURCES_t *prach_resources = &nr_UE_mac_inst->RA_prach_resources; + int32_t frame_diff = 0; + + // Modification for phy_stub_ue operation // TBR + // if(nfapi_mode == 3) { // phy_stub_ue mode + // UE_mode = nr_UE_mac_inst->UE_mode[CC_id]; + // LOG_D(MAC, "ue_get_rach, UE_mode: %d", UE_mode); + // } + // else // Full stack mode + // UE_mode = get_nrUE_mode(mod_id, CC_id, gNB_id); // TBR + + AssertFatal(CC_id == 0,"Transmission on secondary CCs is not supported yet\n"); + + if (UE_mode == PRACH) { + LOG_D(MAC, "ue_get_rach, RA_active value: %d", nr_UE_mac_inst->RA_active); + if (nr_UE_mac_inst->nr_rach_ConfigCommon) { + nr_rach_ConfigCommon = nr_UE_mac_inst->nr_rach_ConfigCommon; + printf("nr_rach_ConfigCommon from MAC nr_UE_mac_inst\n"); /* TBR DEBUG only */ + } else return NULL; + + /* TBR moved below + size_sdu = mac_rrc_nr_data_req(mod_id, + CC_id, + frame, + CCCH, + 1, + &nr_UE_mac_inst->CCCH_pdu.payload[sizeof(SCH_SUBHEADER_SHORT) + 1], gNB_id, 0);*/ + + if (nr_UE_mac_inst->RA_active == 0) { + /* RA not active - checking if RRC is ready to initiate the RA procedure */ + + LOG_I(MAC, "RA not active\n"); + + /* TBR flush Msg3 Buffer + this was done like this but at PHY level + for(i=0; iulsch_Msg3_active[i] = 0; + } + */ + + nr_UE_mac_inst->RA_PREAMBLE_TRANSMISSION_COUNTER = 1; + nr_UE_mac_inst->RA_PREAMBLE_POWER_RAMPING_COUNTER = 1; + prach_resources->RA_PREAMBLE_BACKOFF = 0; + + /* TBR: if carrier to use is explicitly signalled do RA CARRIER SELECTION (SUL, NUL) this will set PCMAX */ + prach_resources->RA_PCMAX = 0; + + /* TBR: BWP operation (subclause 5.15 TS 38.321) */ + + /* Set RA_PREAMBLE_POWER_RAMPING_STEP */ + switch (nr_rach_ConfigCommon->rach_ConfigGeneric.powerRampingStep){ // in dB + case 0: + prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP = 0; + break; + case 1: + prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP = 2; + break; + case 2: + prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP = 4; + break; + case 3: + prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP = 6; + break; + } + + prach_resources->RA_SCALING_FACTOR_BI = 1; + + /* TBR: initialization by beam failure recovery */ + + /* TBR: initialization by handover */ + + /* size_sdu = mac_rrc_nr_data_req(mod_id, + CC_id, + frame, + CCCH, + Nb_tb, + &nr_UE_mac_inst->CCCH_pdu.payload[sizeof(NR_MAC_SUBHEADER_SHORT) + 1]); */ + // TBR mac_rrc_nr_data_req is a GNB func + // use nr_mac_rrc_data_ind_ue instead + + // TBR fix CCCH PDU payload + Size16 = (uint16_t) size_sdu; + + /* TBR FIX THIS + + // LOG_D(MAC,"[UE %d] Frame %d: Requested RRCConnectionRequest, got %d bytes\n",mod_id,frame,size_sdu); + LOG_I(RRC, + "[MSC_MSG][FRAME %05d][RRC_UE][MOD %02d][][--- MAC_DATA_REQ (RRCConnectionRequest gNB %d) --->][MAC_UE][MOD %02d][]\n", + frame, mod_id, gNB_id, mod_id); + LOG_I(MAC, + "[UE %d] Frame %d: Requested RRCConnectionRequest, got %d bytes\n", + mod_id, frame, size_sdu); + + nr_UE_mac_inst->RA_RAPID_found = 0; + // TBR which frame and slot ? + nr_UE_mac_inst->RA_tx_frame = frame; + nr_UE_mac_inst->RA_tx_subframe = nr_tti_tx; + nr_UE_mac_inst->RA_backoff_frame = frame; + nr_UE_mac_inst->RA_backoff_subframe = nr_tti_tx;*/ + + /*if (size_sdu > 0) { */ + /* TBR initialisation by RRC + // PDU from CCCH */ + + LOG_I(MAC, "[UE %d] Frame %d: Initialisation Random Access Procedure\n", mod_id, frame); + + // TBR + /*nr_UE_mac_inst->RA_Msg3_size = size_sdu + sizeof(SCH_SUBHEADER_SHORT) + sizeof(SCH_SUBHEADER_SHORT); + nr_UE_mac_inst->RA_prachMaskIndex = 0; + prach_resources->Msg3 = nr_UE_mac_inst->CCCH_pdu.payload; + nr_UE_mac_inst->RA_backoff_cnt = 0; // add the backoff condition here if we have it from a previous RA reponse which failed (i.e. backoff indicator) + + AssertFatal(nr_rach_ConfigCommon != NULL, + "[UE %d] FATAL Frame %d: nr_rach_ConfigCommon is NULL !!!\n", + mod_id, frame); + nr_UE_mac_inst->RA_window_cnt = 2 + nr_rach_ConfigCommon->ra_SupervisionInfo.ra_ResponseWindowSize; + + if (nr_UE_mac_inst->RA_window_cnt == 9) { + nr_UE_mac_inst->RA_window_cnt = 10; // Note: 9 subframe window doesn't exist, after 8 is 10! + }*/ + + // Fill in preamble and PRACH resources + nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 1, NULL); + + /*generate_ulsch_header((uint8_t *) & nr_UE_mac_inst->CCCH_pdu.payload[0], // mac header + 1, // num sdus + 0, // short pading + &Size16, // sdu length + &lcid, // sdu lcid + NULL, // power headroom + NULL, // crnti + NULL, // truncated bsr + NULL, // short bsr + NULL, // long_bsr + 1); //post_padding*/ + return (&nr_UE_mac_inst->RA_prach_resources); + + /*} else if (nr_UE_mac_inst->scheduling_info. + BSR_bytes[nr_UE_mac_inst->scheduling_info.LCGID[DCCH]] > 0) { + // This is for triggering a transmission on DCCH using PRACH (during handover, + // or sending SR for example) + + dcch_header_len = 2 + 2; /// SHORT Subheader + C-RNTI control element + LOG_USEDINLOG_VAR(mac_rlc_status_resp_t,rlc_status)=mac_rlc_status_ind(mod_id, + nr_UE_mac_inst->crnti, + gNB_id, frame, nr_tti_tx, + ENB_FLAG_NO, MBMS_FLAG_NO, DCCH, 6 + #if (RRC_VERSION >= MAKE_VERSION(14, 0, 0)) + ,0, 0 + #endif + ); + + if (nr_UE_mac_inst->crnti_before_ho) + LOG_D(MAC, + "[UE %d] Frame %d : UL-DCCH -> ULSCH, HO RRCConnectionReconfigurationComplete (%x, %x), RRC message has %d bytes to send throug PRACH (mac header len %d)\n", + mod_id, frame, + nr_UE_mac_inst->crnti, + nr_UE_mac_inst->crnti_before_ho, + rlc_status.bytes_in_buffer, dcch_header_len); + else + LOG_D(MAC, + "[UE %d] Frame %d : UL-DCCH -> ULSCH, RRC message has %d bytes to send through PRACH(mac header len %d)\n", + mod_id, frame, rlc_status.bytes_in_buffer, + dcch_header_len); + + sdu_lengths = mac_rlc_data_req(mod_id, nr_UE_mac_inst->crnti, + gNB_id, frame, ENB_FLAG_NO, MBMS_FLAG_NO, DCCH, 6, //not used + (char *) &ulsch_buff[0] + #if (RRC_VERSION >= MAKE_VERSION(14, 0, 0)) + ,0,0 + #endif + ); + + if(sdu_lengths > 0) + LOG_D(MAC, "[UE %d] TX Got %d bytes for DCCH\n", mod_id, sdu_lengths); + else + LOG_E(MAC, "[UE %d] TX DCCH error\n", mod_id ); + + update_bsr(mod_id, frame, nr_tti_tx, gNB_id); + nr_UE_mac_inst->scheduling_info.BSR[nr_UE_mac_inst-> + scheduling_info.LCGID[DCCH]] = locate_BsrIndexByBufferSize(BSR_TABLE, BSR_TABLE_SIZE, + nr_UE_mac_inst + [mod_id].scheduling_info.BSR_bytes + [nr_UE_mac_inst + [mod_id].scheduling_info.LCGID + [DCCH]]); + + //TBR: fill BSR infos in UL TBS + + //header_len +=2; + nr_UE_mac_inst->RA_active = 1; + nr_UE_mac_inst->RA_PREAMBLE_TRANSMISSION_COUNTER = + 1; + nr_UE_mac_inst->RA_Msg3_size = + size_sdu + dcch_header_len; + nr_UE_mac_inst->RA_prachMaskIndex = 0; + prach_resources->Msg3 = + ulsch_buff; + nr_UE_mac_inst->RA_backoff_cnt = 0; // add the backoff condition here if we have it from a previous RA reponse which failed (i.e. backoff indicator) + + AssertFatal(nr_rach_ConfigCommon != NULL, + "[UE %d] FATAL Frame %d: nr_rach_ConfigCommon is NULL !!!\n", + mod_id, frame); + nr_UE_mac_inst->RA_window_cnt = + 2 + + nr_rach_ConfigCommon->ra_SupervisionInfo. + ra_ResponseWindowSize; + + if (nr_UE_mac_inst->RA_window_cnt == 9) { + nr_UE_mac_inst->RA_window_cnt = 10; // Note: 9 subframe window doesn't exist, after 8 is 10! + } + + + nr_UE_mac_inst->RA_tx_frame = frame; + nr_UE_mac_inst->RA_tx_subframe = nr_tti_tx; + nr_UE_mac_inst->RA_backoff_frame = frame; + nr_UE_mac_inst->RA_backoff_subframe = nr_tti_tx; + // Fill in preamble and PRACH resource + nr_get_prach_resources(mod_id, CC_id, gNB_id, + nr_tti_tx, 1, NULL); + generate_ulsch_header((uint8_t *) ulsch_buff, // mac header + 1, // num sdus + 0, // short pading + &Size16, // sdu length + &lcid, // sdu lcid + NULL, // power headroom + &nr_UE_mac_inst->crnti, // crnti + NULL, // truncated bsr + NULL, // short bsr + NULL, // long_bsr + 0); //post_padding + + return (&nr_UE_mac_inst->RA_prach_resources); + }*/ + } else { // RACH is active + + //////////////////////////////////////////////////////////////// + /////* Random Access Response reception (5.1.4 TS 38.321) *///// + //////////////////////////////////////////////////////////////// + /// Handling ra_responseWindow, RA_PREAMBLE_TRANSMISSION_COUNTER + /// and RA_backoff_cnt + + LOG_D(MAC, "[MAC][UE %d][RAPROC] frame %d, subframe %d: RA Active, window cnt %d (RA_tx_frame %d, RA_tx_subframe %d)\n", + mod_id, frame, nr_tti_tx, nr_UE_mac_inst->RA_window_cnt, nr_UE_mac_inst->RA_tx_frame, nr_UE_mac_inst->RA_tx_subframe); + + // - TBR check + // compute backoff parameters + if (nr_UE_mac_inst->RA_backoff_cnt > 0){ + frame_diff = (sframe_t) frame - nr_UE_mac_inst->RA_backoff_frame; + if (frame_diff < 0) frame_diff = -frame_diff; + nr_UE_mac_inst->RA_backoff_cnt -= ((10 * frame_diff) + (nr_tti_tx - nr_UE_mac_inst->RA_backoff_subframe)); + nr_UE_mac_inst->RA_backoff_frame = frame; + nr_UE_mac_inst->RA_backoff_subframe = nr_tti_tx; + } + // - TBR check + + // - TBR check + // compute RA window parameters + if (nr_UE_mac_inst->RA_window_cnt > 0){ + frame_diff = (frame_t) frame - nr_UE_mac_inst->RA_tx_frame; + if (frame_diff < 0) frame_diff = -frame_diff; + nr_UE_mac_inst->RA_window_cnt -= ((10 * frame_diff) + (nr_tti_tx - nr_UE_mac_inst->RA_tx_subframe)); + LOG_D(MAC, "[MAC][UE %d][RAPROC] Frame %d, subframe %d: RA Active, adjusted window cnt %d\n", mod_id, frame, nr_tti_tx, nr_UE_mac_inst->RA_window_cnt); + } + // - TBR check + + //if ((nr_UE_mac_inst->RA_window_cnt <= 0) && (nr_UE_mac_inst->RA_backoff_cnt <= 0)){ + if ((nr_UE_mac_inst->RA_window_cnt <= 0) && (nr_UE_mac_inst->RA_RAPID_found == 0)){ // TODO TBR double check the condition + + LOG_I(MAC, "[MAC][UE %d][RAPROC] Frame %d: subframe %d: RAR reception not successful, (RA window count %d) \n", mod_id, frame, nr_tti_tx, nr_UE_mac_inst->RA_window_cnt); + + nr_UE_mac_inst->RA_PREAMBLE_TRANSMISSION_COUNTER++; + + // - TBR check RA_tx_frame RA_tx_subframe + nr_UE_mac_inst->RA_tx_frame = frame; + nr_UE_mac_inst->RA_tx_subframe = nr_tti_tx; + prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER += (prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP << 1); // 2dB increments in ASN.1 definition + // - TBR check ra_PREAMBLE_RECEIVED_TARGET_POWER increment + + int preambleTransMax = -1; + + switch (nr_rach_ConfigCommon->rach_ConfigGeneric.preambleTransMax) { + case NR_RACH_ConfigGeneric__preambleTransMax_n3: + preambleTransMax = 3; + break; + case NR_RACH_ConfigGeneric__preambleTransMax_n4: + preambleTransMax = 4; + break; + case NR_RACH_ConfigGeneric__preambleTransMax_n5: + preambleTransMax = 5; + break; + case NR_RACH_ConfigGeneric__preambleTransMax_n6: + preambleTransMax = 6; + break; + case NR_RACH_ConfigGeneric__preambleTransMax_n7: + preambleTransMax = 7; + break; + case NR_RACH_ConfigGeneric__preambleTransMax_n8: + preambleTransMax = 8; + break; + case NR_RACH_ConfigGeneric__preambleTransMax_n10: + preambleTransMax = 10; + break; + case NR_RACH_ConfigGeneric__preambleTransMax_n20: + preambleTransMax = 20; + break; + case NR_RACH_ConfigGeneric__preambleTransMax_n50: + preambleTransMax = 50; + break; + case NR_RACH_ConfigGeneric__preambleTransMax_n100: + preambleTransMax = 100; + break; + case NR_RACH_ConfigGeneric__preambleTransMax_n200: + preambleTransMax = 200; + break; + } + + if (nr_UE_mac_inst->RA_PREAMBLE_TRANSMISSION_COUNTER == preambleTransMax + 1){ + + LOG_D(MAC, "[UE %d] Frame %d: Maximum number of RACH attempts (%d)\n", mod_id, frame, preambleTransMax); + + // TBR select random backoff according to a uniform distribution between 0 and PREAMBLE_BACKOFF + // (rand() % prach_resources->RA_PREAMBLE_BACKOFF + + // TODO TBR send message to RRC + nr_UE_mac_inst->RA_PREAMBLE_TRANSMISSION_COUNTER = 1; + prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = nr_get_Po_NOMINAL_PUSCH(mod_id, CC_id); // TBR check if this is necessary + } + + // TBR ra_SupervisionInfo.ra_ResponseWindowSize is missing + // nr_UE_mac_inst->RA_window_cnt = 2 + nr_rach_ConfigCommon->ra_SupervisionInfo.ra_ResponseWindowSize; + nr_UE_mac_inst->RA_backoff_cnt = 0; + + // Fill in preamble and PRACH resources + nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 0, NULL); + return (&nr_UE_mac_inst->RA_prach_resources); + } + } + } else if (UE_mode == PUSCH) { + LOG_D(MAC, "[UE %d] FATAL: Should not have checked for RACH in PUSCH yet ...", mod_id); + AssertFatal(1 == 0, ""); + } + return NULL; +} \ No newline at end of file diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 55ac095398..e192bfb232 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -30,36 +30,36 @@ * \warning */ + +#include +#include + +/* exe */ #include "executables/nr-softmodem.h" -/* MAC related headers */ -#include "mac_proto.h" +/* MAC */ #include "mac_defs.h" -#include "LAYER2/NR_MAC_COMMON/nr_mac.h" -#include "mac_extern.h" +#include "NR_MAC_COMMON/nr_mac.h" +#include "NR_MAC_UE/mac_proto.h" +#include "NR_MAC_UE/mac_extern.h" #include "common/utils/nr/nr_common.h" -//#include "LAYER2/MAC/mac_vars.h" // TODO Note that mac_vars.h is not NR specific and this should be updated +//#include "LAYER2/MAC/mac_vars.h" // TBR Note that mac_vars.h is not NR specific and this should be updated // also, the use of the same should be updated in nr-softmodem and nr-uesoftmodem -/* PHY UE related headers*/ +/* PHY UE */ #include "SCHED_NR_UE/defs.h" - -#include "RRC/NR_UE/rrc_proto.h" -#include "assertions.h" #include "PHY/defs_nr_UE.h" /*Openair Packet Tracer */ #include "UTIL/OPT/opt.h" #include "OCG.h" -/* log utils */ +/* utils */ +#include "assertions.h" #include "common/utils/LOG/log.h" #include "common/utils/LOG/vcd_signal_dumper.h" -#include -#include - //#define ENABLE_MAC_PAYLOAD_DEBUG 1 #define DEBUG_EXTRACT_DCI 1 diff --git a/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c b/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c new file mode 100644 index 0000000000..bd7e96eda5 --- /dev/null +++ b/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c @@ -0,0 +1,157 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file rar_tools_nrUE.c + * \brief RA tools for NR UE + * \author Guido Casati + * \date 2019 + * \version 1.0 + * @ingroup _mac + + */ + +/* Sim */ +#include "SIMULATION/TOOLS/sim.h" + +/* Utils */ +#include "common/utils/LOG/log.h" +#include "OCG.h" +#include "OCG_extern.h" +#include "UTIL/OPT/opt.h" + +/* Common */ +#include "common/ran_context.h" + +/* MAC */ +#include "NR_MAC_UE/mac.h" +#include "NR_MAC_UE/mac_proto.h" +#include "NR_MAC_COMMON/nr_mac_extern.h" + +#define DEBUG_RAR + +uint16_t nr_ue_process_rar(const module_id_t mod_id, + const int CC_id, + const frame_t frameP, + const rnti_t ra_rnti, + uint8_t * const dlsch_buffer, + rnti_t * const t_crnti, + const uint8_t preamble_index, + uint8_t * selected_rar_buffer/*output argument for storing the selected RAR header and RAR payload*/){ + + NR_UE_MAC_INST_t *nrUE_mac_inst = get_mac_inst(mod_id); + + uint16_t ret = 0; // return value + + NR_RA_HEADER_RAPID *rarh = (NR_RA_HEADER_RAPID *) dlsch_buffer; + + // TODO TBR + + // NR_RAR_PDU *rar = (RAR_PDU *)(dlsch_buffer+1); + uint8_t *rar = (uint8_t *) (dlsch_buffer + 1); + + // get the last RAR payload for working with CMW500 + uint8_t n_rarpy = 0; // number of RAR payloads + uint8_t n_rarh = 0; // number of MAC RAR subheaders + uint8_t best_rx_rapid = -1; // the closest RAPID receive from all RARs + while (1) { + n_rarh++; + if (rarh->T == 1) { + n_rarpy++; + LOG_D(MAC, "RAPID %d\n", rarh->RAPID); + } + + if (rarh->RAPID == preamble_index) { + LOG_D(PHY, "Found RAR with the intended RAPID %d\n", + rarh->RAPID); + rar = (uint8_t *) (dlsch_buffer + n_rarh + (n_rarpy - 1) * 6); + nrUE_mac_inst->RA_RAPID_found = 1; + break; + } + + if (abs((int) rarh->RAPID - (int) preamble_index) < + abs((int) best_rx_rapid - (int) preamble_index)) { + best_rx_rapid = rarh->RAPID; + rar = (uint8_t *) (dlsch_buffer + n_rarh + (n_rarpy - 1) * 6); + } + + if (rarh->E == 0) { + LOG_I(PHY, "No RAR found with the intended RAPID. The closest RAPID in all RARs is %d\n", best_rx_rapid); + break; + } else { + rarh++; + } + }; + LOG_D(MAC, "number of RAR subheader %d; number of RAR pyloads %d\n", + n_rarh, n_rarpy); + + if (CC_id > 0) { + LOG_W(MAC, "Should not have received RAR on secondary CCs! \n"); + return (0xffff); + } + + LOG_I(MAC, + "[UE %d][RAPROC] Frame %d Received RAR (%02x|%02x.%02x.%02x.%02x.%02x.%02x) for preamble %d/%d\n", + mod_id, frameP, *(uint8_t *) rarh, rar[0], rar[1], rar[2], + rar[3], rar[4], rar[5], rarh->RAPID, preamble_index); +#ifdef DEBUG_RAR + LOG_D(MAC, "[UE %d][RAPROC] rarh->E %d\n", mod_id, rarh->E); + LOG_D(MAC, "[UE %d][RAPROC] rarh->T %d\n", mod_id, rarh->T); + LOG_D(MAC, "[UE %d][RAPROC] rarh->RAPID %d\n", mod_id, + rarh->RAPID); + + // LOG_I(MAC,"[UE %d][RAPROC] rar->R %d\n",mod_id,rar->R); + LOG_D(MAC, "[UE %d][RAPROC] rar->Timing_Advance_Command %d\n", + mod_id, (((uint16_t) (rar[0] & 0x7f)) << 4) + (rar[1] >> 4)); + // LOG_I(MAC,"[UE %d][RAPROC] rar->hopping_flag %d\n",mod_id,rar->hopping_flag); + // LOG_I(MAC,"[UE %d][RAPROC] rar->rb_alloc %d\n",mod_id,rar->rb_alloc); + // LOG_I(MAC,"[UE %d][RAPROC] rar->mcs %d\n",mod_id,rar->mcs); + // LOG_I(MAC,"[UE %d][RAPROC] rar->TPC %d\n",mod_id,rar->TPC); + // LOG_I(MAC,"[UE %d][RAPROC] rar->UL_delay %d\n",mod_id,rar->UL_delay); + // LOG_I(MAC,"[UE %d][RAPROC] rar->cqi_req %d\n",mod_id,rar->cqi_req); + LOG_D(MAC, "[UE %d][RAPROC] rar->t_crnti %x\n", mod_id, + (uint16_t) rar[5] + (rar[4] << 8)); +#endif + + if (opt_enabled) { + LOG_D(OPT, + "[UE %d][RAPROC] CC_id %d RAR Frame %d trace pdu for ra-RNTI %x\n", + mod_id, CC_id, frameP, ra_rnti); + /*trace_pdu(DIRECTION_DOWNLINK, (uint8_t *) dlsch_buffer, n_rarh + n_rarpy * 6, + mod_id, WS_RA_RNTI, ra_rnti, nrUE_mac_inst->rxFrame, + nrUE_mac_inst->rxSubframe, 0, 0);*/ // TODO TBR fix rxframe and subframe + } + + if (preamble_index == rarh->RAPID) { // TBR double check this + *t_crnti = (uint16_t) rar[5] + (rar[4] << 8); //rar->t_crnti; + nrUE_mac_inst->crnti = *t_crnti; //rar->t_crnti; + //return(rar->Timing_Advance_Command); + ret = ((((uint16_t) (rar[0] & 0x7f)) << 4) + (rar[1] >> 4)); + } else { + nrUE_mac_inst->crnti = 0; + ret = (0xffff); + } + + // move the selected RAR to the front of the RA_PDSCH buffer + memcpy(selected_rar_buffer + 0, (uint8_t *) rarh, 1); + memcpy(selected_rar_buffer + 1, (uint8_t *) rar, 6); + + return ret; +} diff --git a/openair2/LAYER2/NR_MAC_gNB/config.c b/openair2/LAYER2/NR_MAC_gNB/config.c index c911fbd56a..6f9f04c108 100644 --- a/openair2/LAYER2/NR_MAC_gNB/config.c +++ b/openair2/LAYER2/NR_MAC_gNB/config.c @@ -44,7 +44,7 @@ #include "SCHED_NR/phy_frame_config_nr.h" #include "NR_MIB.h" -#include "nr_mac_common.h" +#include "LAYER2/NR_MAC_COMMON/nr_mac_common.h" extern RAN_CONTEXT_t RC; //extern int l2_init_gNB(void); diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index ace9551d2f..5e7ad3848e 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -33,9 +33,9 @@ #include "assertions.h" #include "LAYER2/MAC/mac.h" -#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" +#include "NR_MAC_COMMON/nr_mac_extern.h" #include "LAYER2/MAC/mac_proto.h" -#include "LAYER2/NR_MAC_gNB/mac_proto.h" +#include "NR_MAC_gNB/mac_proto.h" #include "common/utils/LOG/log.h" #include "common/utils/LOG/vcd_signal_dumper.h" @@ -365,10 +365,10 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, schedule_nr_mib(module_idP, frame_txP, slot_txP); } - // TbD once RACH is available, start ta_timer when UE is connected + // TBR once RACH is available, start ta_timer when UE is connected if (ue_sched_ctl->ta_timer) ue_sched_ctl->ta_timer--; - if (ue_sched_ctl->ta_timer == 0) { + if (ue_sched_ctl->ta_timer == 0) { // TBR check phy_test (see below) gNB->ta_command = ue_sched_ctl->ta_update; /* if time is up, then set the timer to not send it for 5 frames // regardless of the TA value */ @@ -380,8 +380,10 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, } // Phytest scheduling - if (phy_test && slot_txP==1){ + if (phy_test && slot_txP==1){ // TBR check phy_test nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP,NULL); + // This schedules Random-Access for NR starting in subframeP + nr_schedule_RA(module_idP, frame_txP, slot_txP); // resetting ta flag gNB->ta_len = 0; } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index d74df15eac..f98aebfb0d 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -19,44 +19,541 @@ * contact@openairinterface.org */ -/*! \file gNB_scheduler_RA.c - * \brief primitives used for random access - * \author - * \date - * \email: +/*! \file gNB_scheduler_RA.c + * \brief primitives used for random access + * \author Guido Casati + * \date 2019 + * \email: guido.casati@iis.fraunhofer.de * \version */ -#include nr_mac_gNB.h +#include "platform_types.h" +#include "nr_mac_gNB.h" +#include "NR_MAC_gNB/mac_proto.h" +#include "NR_MAC_COMMON/nr_mac_extern.h" -void -schedule_RA(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP) -{ +/* Openair Packet Tracer */ +#include "UTIL/OPT/opt.h" - eNB_MAC_INST *mac = RC.mac[module_idP]; - COMMON_channels_t *cc = mac->common_channels; - RA_t *ra; +// void nr_add_subframe(uint16_t *frameP, uint16_t *slotP, int offset){ +// *frameP = (*frameP + ((*slotP + offset) / 10)) % 1024; +// *slotP = ((*slotP + offset) % 10); +// } // TBR fix + +// handles the event of MSG1 reception +// TBR remove sub_frame_t +void nr_initiate_ra_proc(module_id_t module_idP, + int CC_id, + frame_t frameP, + sub_frame_t slotP, + uint16_t preamble_index, + int16_t timing_offset, + uint16_t ra_rnti + #if (RRC_VERSION >= MAKE_VERSION(14, 0, 0)) // TBR + , uint8_t rach_resource_type + #endif + ){ uint8_t i; + uint16_t msg2_frame = frameP, msg2_slot = slotP; + int offset; + NR_COMMON_channels_t *cc = &RC.mac[module_idP]->common_channels[CC_id]; + NR_RA_t *ra = &cc->ra[0]; + static uint8_t failure_cnt = 0; + + /*#if (RRC_VERSION >= MAKE_VERSION(14, 0, 0)) + struct PRACH_ConfigSIB_v1310 *ext4_prach = NULL; + PRACH_ParametersListCE_r13_t *prach_ParametersListCE_r13 = NULL; + + static uint8_t failure_cnt = 0; + + if (cc->radioResourceConfigCommon_BR + && cc->radioResourceConfigCommon_BR->ext4) { + ext4_prach = cc->radioResourceConfigCommon_BR->ext4->prach_ConfigCommon_v1310; + prach_ParametersListCE_r13 = &ext4_prach->prach_ParametersListCE_r13; + } + #endif // #if (RRC_VERSION >= MAKE_VERSION(14, 0, 0)) */ + + LOG_D(MAC, "[gNB %d][RAPROC] CC_id %d Frame %d, Subframe %d Initiating RA procedure for preamble index %d\n", + module_idP, CC_id, frameP, slotP, preamble_index); + /*#if (RRC_VERSION >= MAKE_VERSION(14, 0, 0)) + LOG_D(MAC, + "[gNB %d][RAPROC] CC_id %d Frame %d, Subframe %d PRACH resource type %d\n", + module_idP, CC_id, frameP, slotP, rach_resource_type); + #endif*/ + + + + /*#if (RRC_VERSION >= MAKE_VERSION(13, 0, 0)) + if (prach_ParametersListCE_r13 && prach_ParametersListCE_r13->list.count < rach_resource_type) { + LOG_E(MAC,"[gNB %d][RAPROC] CC_id %d Received impossible PRACH resource type %d, + only %d CE levels configured\n", + module_idP, CC_id, rach_resource_type, + (int) prach_ParametersListCE_r13->list.count); + return; + } + #endif // #if (RRC_VERSION >= MAKE_VERSION(14, 0, 0)) */ + + /*VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_INITIATE_RA_PROC, 1); + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_INITIATE_RA_PROC, 0);*/ + + for (i = 0; i < NR_NB_RA_PROC_MAX; i++) { + if (ra[i].state == IDLE) { + int loop = 0; + LOG_D(MAC, "Frame %d, Subframe %d: Activating RA process %d\n", frameP, slotP, i); + ra[i].state = MSG2; + ra[i].timing_offset = timing_offset; + ra[i].preamble_subframe = slotP; + /*#if (RRC_VERSION >= MAKE_VERSION(14, 0, 0)) + ra[i].rach_resource_type = rach_resource_type; + ra[i].msg2_mpdcch_repetition_cnt = 0; + ra[i].msg4_mpdcch_repetition_cnt = 0; + #endif*/ + + /* TBR CHECK Fill in other TDD config. What about nfapi_mode? */ + // if(cc->tdd_Config!=NULL){ + // // switch(cc->tdd_Config->subframeAssignment){ // TBR missing tdd_Config + // // default: printf("%s:%d: TODO\n", __FILE__, __LINE__); abort(); + // // case 1 : + // // offset = 6; + // // break; + // // } + // }else{//FDD + // // DJP - this is because VNF is 2 subframes ahead of PNF and TX needs 4 subframes + // if (nfapi_mode) + // offset = 7; + // else + // offset = 5; + // } + + // nr_add_subframe(&msg2_frame, &msg2_slot, offset); // TBR + + ra[i].Msg2_frame = msg2_frame; + ra[i].Msg2_subframe = msg2_slot; + + LOG_D(MAC,"%s() Msg2[%04d%d] SFN/SF:%04d%d offset:%d\n", __FUNCTION__,ra[i].Msg2_frame,ra[i].Msg2_subframe,frameP,slotP,offset); + + ra[i].Msg2_subframe = (slotP + offset) % 10; + + /* TBR: find better procedure to allocate RNTI */ + do { + #if defined(USRP_REC_PLAY) // deterministic rnti in usrp record/playback mode + static int drnti[MAX_MOBILES_PER_GNB] = { 0xbda7, 0x71da, 0x9c40, 0xc350, 0x2710, 0x4e20, 0x7530, 0x1388, 0x3a98, 0x61a8, 0x88b8, 0xafc8, 0xd6d8, 0x1b58, 0x4268, 0x6978 }; + int j = 0; + int nb_ue = 0; + for (j = 0; j < MAX_MOBILES_PER_GNB; j++) { + if (UE_RNTI(module_idP, j) > 0) { + nb_ue++; + } else { + break; + } + } + if (nb_ue >= MAX_MOBILES_PER_GNB) { + printf("No more free RNTI available, increase MAX_MOBILES_PER_GNB\n"); + abort(); + } + ra[i].rnti = drnti[nb_ue]; + #else + ra[i].rnti = taus(); + #endif + loop++; + } + /* While loop + ** TBR: second condition is not correct, the rnti may be in use without + * being in the MAC yet. To be refined. + ** 1024 and 60000 arbirarily chosen, not coming from standard */ + while (loop != 100 /*&& !(find_nrUE_id(module_idP, ra[i].rnti) == -1 && ra[i].rnti >= 1024 && ra[i].rnti < 60000)*/); + // TBR nr_find_ue + + if (loop == 100) { + printf("%s:%d:%s: FATAL ERROR! contact the authors\n",__FILE__, __LINE__, __FUNCTION__); + abort(); + } + + ra[i].RA_rnti = ra_rnti; + ra[i].preamble_index = preamble_index; + failure_cnt = 0; + + LOG_D(MAC, "[gNB %d][RAPROC] CC_id %d Frame %d Activating RAR generation in Frame %d, subframe %d for process %d, rnti %x, state %d\n", module_idP, CC_id, frameP, ra[i].Msg2_frame, ra[i].Msg2_subframe, i, ra[i].rnti, ra[i].state); + + return; + } + } + + LOG_E(MAC, + "[gNB %d][RAPROC] FAILURE: CC_id %d Frame %d Initiating RA procedure for preamble index %d\n", + module_idP, CC_id, frameP, preamble_index); + + failure_cnt++; + + if(failure_cnt > 20) { + LOG_E(MAC,"[gNB %d][RAPROC] CC_id %d Frame %d Clear Random access information\n", module_idP, CC_id, frameP); + nr_clear_ra_proc(module_idP, CC_id, frameP); + } + +} + +void nr_schedule_RA(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ + + gNB_MAC_INST *mac = RC.mac[module_idP]; + NR_COMMON_channels_t *cc = mac->common_channels; + NR_RA_t *ra; + uint8_t i, CC_id = 0; start_meas(&mac->schedule_ra); + // for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { - for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { + for (i = 0; i < NR_NB_RA_PROC_MAX; i++) { - for (i = 0; i < NB_RA_PROC_MAX; i++) { + ra = (NR_RA_t *) & cc[CC_id].ra[i]; + LOG_D(MAC,"RA[state:%d]\n",ra->state); - ra = (RA_t *) & cc[CC_id].ra[i]; - //LOG_D(MAC,"RA[state:%d]\n",ra->state); - - if (ra->state == MSG2) - generate_Msg2(module_idP, CC_id, frameP, subframeP, ra); - else if (ra->state == MSG4) - generate_Msg4(module_idP, CC_id, frameP, subframeP, ra); - else if (ra->state == WAITMSG4ACK) - check_Msg4_retransmission(module_idP, CC_id, frameP, subframeP, ra); - - } // for i=0 .. N_RA_PROC-1 - } // CC_id - - stop_meas(&mac->schedule_ra); + switch (ra->state){ + case MSG2: + nr_generate_Msg2(module_idP, CC_id, frameP, slotP, ra); + break; + case MSG4: + generate_Msg4(module_idP, CC_id, frameP, slotP, ra); + break; + case WAITMSG4ACK: + check_Msg4_retransmission(module_idP, CC_id, frameP, slotP, ra); + break; + } + } // for i=0 .. N_RA_PROC-1 + // } // CC_id + stop_meas(&mac->schedule_ra); } + +void nr_generate_Msg2(module_id_t module_idP, int CC_idP, frame_t frameP, + sub_frame_t slotP, NR_RA_t * ra){ + + int first_rb, N_RB_DL; + + gNB_MAC_INST *mac = RC.mac[module_idP]; + NR_COMMON_channels_t *cc = mac->common_channels; + uint8_t *vrb_map = cc[CC_idP].vrb_map; + +// /* TBR - MIGRATE TO THE NEW NFAPI */ +// nfapi_nr_dl_tti_request_body_t *dl_req = &mac->DL_req[CC_idP].dl_config_request_body; +// nfapi_nr_dl_tti_request_pdu_t *dl_config_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu]; +// nfapi_tx_request_pdu_t *TX_req; +// +// /* TBR: BW should be retrieved from +// // NR_ServingCellConfigCommonSIB_t -> NR_BWP_DownlinkCommon_t -> NR_BWP_t +// N_RB_DL = to_prb(cc[CC_idP].mib->message.dl_Bandwidth); +// // Temporary hardcoded +// */ +// N_RB_DL = 106; +// +// if ((ra->Msg2_frame == frameP) && (ra->Msg2_subframe == slotP)) { +// +// LOG_D(MAC,"[gNB %d] CC_id %d Frame %d, slotP %d: +// Generating RAR DCI, state %d\n", +// module_idP, CC_idP, frameP, slotP, ra->state); +// +// // Allocate 4 PRBS starting in RB 0 +// // commented out because preprocessor is missing +// /*first_rb = 0; +// vrb_map[first_rb] = 1; +// vrb_map[first_rb + 1] = 1; +// vrb_map[first_rb + 2] = 1; +// vrb_map[first_rb + 3] = 1;*/ +// +// memset((void *) dl_config_pdu, 0, sizeof(nfapi_nr_dl_config_request_pdu_t)); +// +// dl_config_pdu->pdu_type = NFAPI_NR_DL_CONFIG_DCI_DL_PDU_TYPE; +// dl_config_pdu->pdu_size = (uint8_t) (2 + sizeof(nfapi_dl_config_dci_dl_pdu)); +// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tl.tag = NFAPI_DL_CONFIG_REQUEST_DCI_DL_PDU_REL8_TAG; +// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.dci_format = NFAPI_DL_DCI_FORMAT_1A; +// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level = 4; +// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti = ra->RA_rnti; +// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type = 2; // RA-RNTI : see Table 4-10 from SCF082 - nFAPI specifications +// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.transmission_power = 6000; // equal to RS power +// +// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.harq_process = 0; +// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tpc = 1; // no TPC +// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.new_data_indicator_1 = 1; +// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.mcs_1 = 0; +// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.redundancy_version_1 = 0; +// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.virtual_resource_block_assignment_flag = 0; +// +// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.resource_block_coding = getRIV(N_RB_DL, first_rb, 4); +// +// // This checks if the above DCI allocation is feasible in current subframe +// if (!nr_CCE_allocation_infeasible(module_idP, CC_idP, 0, slotP, +// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level, ra->RA_rnti)) { +// +// LOG_D(MAC, "Frame %d: Subframe %d : Adding common DCI for RA_RNTI %x\n", frameP, slotP, ra->RA_rnti); +// dl_req->number_dci++; +// dl_req->number_pdu++; +// +// dl_config_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu]; +// memset((void *) dl_config_pdu, 0, sizeof(nfapi_nr_dl_config_request_pdu_t)); +// dl_config_pdu->pdu_type = NFAPI_NR_DL_CONFIG_DCI_DL_PDU_TYPE; +// dl_config_pdu->pdu_size = (uint8_t) (2 + sizeof(nfapi_nr_dl_config_dlsch_pdu)); +// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.tl.tag = NFAPI_NR_DL_CONFIG_REQUEST_DLSCH_PDU_REL15_TAG; +// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.pdu_index = mac->pdu_index[CC_idP]; +// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.rnti = ra->RA_rnti; +// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.resource_allocation_type = 2; // format 1A/1B/1D +// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.virtual_resource_block_assignment_flag = 0; // localized +// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.resource_block_coding = getRIV(N_RB_DL, first_rb, 4); +// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.modulation = 2; //QPSK +// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.redundancy_version = 0; +// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.transport_blocks = 1; // first block +// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.transport_block_to_codeword_swap_flag = 0; +// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.transmission_scheme = (cc->p_eNB == 1) ? 0 : 1; +// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.number_of_layers = 1; +// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.number_of_subbands = 1; +// // dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.codebook_index = ; +// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.ue_category_capacity = 1; +// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.pa = 4; // 0 dB +// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.delta_power_offset_index = 0; +// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.ngap = 0; +// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.nprb = get_subbandsize(cc->mib->message.dl_Bandwidth); // ignored +// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.transmission_mode = (cc->p_eNB == 1) ? 1 : 2; +// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.num_bf_prb_per_subband = 1; +// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.num_bf_vector = 1; +// // dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.bf_vector = ; +// dl_req->number_pdu++; +// mac->DL_req[CC_idP].sfn_sf = frameP<<4 | slotP; +// +// // Program UL processing for Msg3 +// nr_get_Msg3alloc(&cc[CC_idP], slotP, frameP,&ra->Msg3_frame, &ra->Msg3_subframe); +// +// LOG_D(MAC, "Frame %d, Subframe %d: Setting Msg3 reception for Frame %d Subframe %d\n", +// frameP, slotP, ra->Msg3_frame, +// ra->Msg3_subframe); +// +// nr_fill_rar(module_idP, CC_idP, ra, frameP, cc[CC_idP].RAR_pdu.payload, N_RB_DL, 7); +// nr_add_msg3(module_idP, CC_idP, ra, frameP, slotP); +// ra->state = WAITMSG3; +// LOG_D(MAC,"[gNB %d][RAPROC] Frame %d, Subframe %d: state:WAITMSG3\n", module_idP, frameP, slotP); +// +// // DL request +// mac->TX_req[CC_idP].sfn_sf = (frameP << 4) + slotP; +// TX_req = &mac->TX_req[CC_idP].tx_request_body.tx_pdu_list[mac->TX_req[CC_idP].tx_request_body.number_of_pdus]; +// TX_req->pdu_length = 7; // This should be changed if we have more than 1 preamble +// TX_req->pdu_index = mac->pdu_index[CC_idP]++; +// TX_req->num_segments = 1; +// TX_req->segments[0].segment_length = 7; +// TX_req->segments[0].segment_data = cc[CC_idP].RAR_pdu.payload; +// mac->TX_req[CC_idP].tx_request_body.number_of_pdus++; +// +// /*if(RC.mac[module_idP]->scheduler_mode == SCHED_MODE_FAIR_RR){ +// set_dl_ue_select_msg2(CC_idP, 4, -1, ra->rnti); +// }*/ +// } // PDCCH CCE allocation is feasible +// } // Msg2 frame/subframe condition +} + +void nr_clear_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP){ + unsigned char i; + NR_RA_t *ra = (NR_RA_t *) &RC.mac[module_idP]->common_channels[CC_id].ra[0]; + for (i = 0; i < NR_NB_RA_PROC_MAX; i++){ + LOG_D(MAC,"[gNB %d][RAPROC] CC_id %d Frame %d Clear Random access information rnti %x\n", module_idP, CC_id, frameP, ra[i].rnti); + ra[i].state = IDLE; + ra[i].timing_offset = 0; + ra[i].RRC_timer = 20; + ra[i].rnti = 0; + ra[i].msg3_round = 0; + } +} + +unsigned short nr_fill_rar(const module_id_t mod_id, + const int CC_id, + NR_RA_t * ra, + const frame_t frameP, + uint8_t * const dlsch_buffer, + const uint16_t N_RB_UL, + const uint8_t input_buffer_length){ + + RA_HEADER_RAPID *rarh = (NR_RA_HEADER_RAPID *) dlsch_buffer; + uint8_t *rar = (uint8_t *) (dlsch_buffer + 1); + + /* E/T/RAPID subheader + - E = 0, one only RAR, first and last + - T = 1, E/T/RAPID subheader */ + rarh->E = 0; + rarh->T = 1; + rarh->RAPID = ra->preamble_index; // TBR Respond to Preamble 0 only for the moment + /* TBR handle MAC RAR BI subheader*/ + + /* TC-RNTI */ + // TBR double check + rar[5] = (uint8_t) (ra->rnti >> 8); + rar[6] = (uint8_t) (ra->rnti & 0xff); + // TBR double check + + /* Timing Advance Command */ + // TBR double check + //ra->timing_offset = 0; + //printf("ra->timing_offset %d\n", ra->timing_offset); // TBR remove + + ra->timing_offset /= 16; //T_A = N_TA/16, where N_TA should be on a 30.72Msps + rar[0] = (uint8_t) (ra->timing_offset >> (2 + 4)); // 7 MSBs of timing advance + divide by 4 + rar[1] = (uint8_t) (ra->timing_offset << (4 - 2)) & 0xf0; // 4 LSBs of timing advance + divide by 4 + // TBR double check + + // TBR double check + COMMON_channels_t *cc = &RC.mac[mod_id]->common_channels[CC_id]; + if(N_RB_UL == 25){ + ra->msg3_first_rb = 1; + }else{ + // if (cc->tdd_Config && N_RB_UL == 100) { // TBR missing tdd_Config + // ra->msg3_first_rb = 3; + // } else { + // ra->msg3_first_rb = 2; + // } + } + ra->msg3_nb_rb = 1; + // TBR double check + + /* UL Grant */ + // TBR fix this + uint16_t rballoc = nr_mac_compute_RIV(N_RB_UL, ra->msg3_first_rb, ra->msg3_nb_rb); // first PRB only for UL Grant + rar[1] |= (rballoc >> 7) & 7; // Hopping = 0 (bit 3), 3 MSBs of rballoc + rar[2] = ((uint8_t) (rballoc & 0xff)) << 1; // 7 LSBs of rballoc + ra->msg3_mcs = 10; + ra->msg3_TPC = 3; + ra->msg3_ULdelay = 0; + ra->msg3_cqireq = 0; + ra->msg3_round = 0; + rar[2] |= ((ra->msg3_mcs & 0x8) >> 3); // mcs 10 + rar[3] = (((ra->msg3_mcs & 0x7) << 5)) | ((ra->msg3_TPC & 7) << 2) | ((ra->msg3_ULdelay & 1) << 1) | (ra->msg3_cqireq & 1); + // TBR double check + + return ra->rnti; +} + +void nr_add_msg3(module_id_t module_idP, int CC_id, NR_RA_t *ra, frame_t frameP, sub_frame_t subframeP){ + + #if 0 + eNB_MAC_INST *mac = RC.mac[module_idP]; + COMMON_channels_t *cc = &mac->common_channels[CC_id]; + uint8_t j; + nfapi_ul_config_request_t *ul_req; + nfapi_ul_config_request_body_t *ul_req_body; + nfapi_ul_config_request_pdu_t *ul_config_pdu; + nfapi_hi_dci0_request_t *hi_dci0_req; + nfapi_hi_dci0_request_body_t *hi_dci0_req_body; + nfapi_hi_dci0_request_pdu_t *hi_dci0_pdu; + uint8_t sf_ahead_dl; + uint8_t rvseq[4] = {0, 2, 3, 1}; + ul_req = &mac->UL_req_tmp[CC_id][ra->Msg3_subframe]; + ul_req_body = &ul_req->ul_config_request_body; + AssertFatal(ra->state != IDLE, "RA is not active for RA %X\n", + ra->rnti); +#if (LTE_RRC_VERSION >= MAKE_VERSION(14, 0, 0)) + + if (ra->rach_resource_type > 0) { + LOG_D (MAC, "[eNB %d][RAPROC] Frame %d, Subframe %d : CC_id %d CE level %d is active, Msg3 in (%d,%d)\n", + module_idP, frameP, subframeP, CC_id, ra->rach_resource_type - 1, ra->Msg3_frame, ra->Msg3_subframe); + LOG_D (MAC, "Frame %d, Subframe %d Adding Msg3 UL Config Request for (%d,%d) : (%d,%d)\n", + frameP, subframeP, ra->Msg3_frame, ra->Msg3_subframe, ra->msg3_nb_rb, ra->msg3_round); + ul_config_pdu = &ul_req_body->ul_config_pdu_list[ul_req_body->number_of_pdus]; + memset ((void *) ul_config_pdu, 0, sizeof (nfapi_ul_config_request_pdu_t)); + ul_config_pdu->pdu_type = NFAPI_UL_CONFIG_ULSCH_PDU_TYPE; + ul_config_pdu->pdu_size = (uint8_t) (2 + sizeof (nfapi_ul_config_ulsch_pdu)); + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.handle = mac->ul_handle++; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.rnti = ra->rnti; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.resource_block_start = narrowband_to_first_rb (cc, ra->msg34_narrowband) + ra->msg3_first_rb; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.number_of_resource_blocks = ra->msg3_nb_rb; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.modulation_type = 2; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.cyclic_shift_2_for_drms = 0; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.frequency_hopping_enabled_flag = 0; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.frequency_hopping_bits = 0; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.new_data_indication = 0; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.redundancy_version = rvseq[ra->msg3_round]; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.harq_process_number = 0; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.ul_tx_mode = 0; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.current_tx_nb = 0; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.n_srs = 1; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.size = get_TBS_UL (ra->msg3_mcs, ra->msg3_nb_rb); + // Re13 fields + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel13.ue_type = ra->rach_resource_type > 2 ? 2 : 1; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel13.total_number_of_repetitions = 1; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel13.repetition_number = 1; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel13.initial_transmission_sf_io = (ra->Msg3_frame * 10) + ra->Msg3_subframe; + ul_req_body->number_of_pdus++; + } // if (ra->rach_resource_type>0) { + else +#endif + { + LOG_D(MAC, + "[eNB %d][RAPROC] Frame %d, Subframe %d : CC_id %d RA is active, Msg3 in (%d,%d)\n", + module_idP, frameP, subframeP, CC_id, ra->Msg3_frame, + ra->Msg3_subframe); + LOG_D(MAC, + "Frame %d, Subframe %d Adding Msg3 UL Config Request for (%d,%d) : (%d,%d,%d) for rnti: %d\n", + frameP, subframeP, ra->Msg3_frame, ra->Msg3_subframe, + ra->msg3_nb_rb, ra->msg3_first_rb, ra->msg3_round, ra->rnti); + ul_config_pdu = &ul_req_body->ul_config_pdu_list[ul_req_body->number_of_pdus]; + memset((void *) ul_config_pdu, 0, sizeof(nfapi_ul_config_request_pdu_t)); + ul_config_pdu->pdu_type = NFAPI_UL_CONFIG_ULSCH_PDU_TYPE; + ul_config_pdu->pdu_size = (uint8_t) (2 + sizeof(nfapi_ul_config_ulsch_pdu)); + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.tl.tag = NFAPI_UL_CONFIG_REQUEST_ULSCH_PDU_REL8_TAG; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.handle = mac->ul_handle++; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.rnti = ra->rnti; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.resource_block_start = ra->msg3_first_rb; + AssertFatal(ra->msg3_nb_rb > 0, "nb_rb = 0\n"); + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.number_of_resource_blocks = ra->msg3_nb_rb; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.modulation_type = 2; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.cyclic_shift_2_for_drms = 0; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.frequency_hopping_enabled_flag = 0; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.frequency_hopping_bits = 0; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.new_data_indication = 0; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.redundancy_version = rvseq[ra->msg3_round]; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.harq_process_number = subframe2harqpid(cc, ra->Msg3_frame, ra->Msg3_subframe); + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.ul_tx_mode = 0; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.current_tx_nb = 0; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.n_srs = 1; + ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.size = get_TBS_UL(10, ra->msg3_nb_rb); + ul_req_body->number_of_pdus++; + ul_req_body->tl.tag = NFAPI_UL_CONFIG_REQUEST_BODY_TAG; + ul_req->sfn_sf = ra->Msg3_frame<<4|ra->Msg3_subframe; + ul_req->header.message_id = NFAPI_UL_CONFIG_REQUEST; + + // save UL scheduling information for preprocessor + for (j = 0; j < ra->msg3_nb_rb; j++) + cc->vrb_map_UL[ra->msg3_first_rb + j] = 1; + + LOG_D(MAC, "MSG3: UL_CONFIG SFN/SF:%d number_of_pdus:%d ra->msg3_round:%d\n", NFAPI_SFNSF2DEC(ul_req->sfn_sf), ul_req_body->number_of_pdus, ra->msg3_round); + + if (ra->msg3_round != 0) { // program HI too + sf_ahead_dl = ul_subframe2_k_phich(cc, subframeP); + hi_dci0_req = &mac->HI_DCI0_req[CC_id][(subframeP+sf_ahead_dl)%10]; + hi_dci0_req_body = &hi_dci0_req->hi_dci0_request_body; + hi_dci0_pdu = &hi_dci0_req_body->hi_dci0_pdu_list[hi_dci0_req_body->number_of_dci + hi_dci0_req_body->number_of_hi]; + memset((void *) hi_dci0_pdu, 0, + sizeof(nfapi_hi_dci0_request_pdu_t)); + hi_dci0_pdu->pdu_type = NFAPI_HI_DCI0_HI_PDU_TYPE; + hi_dci0_pdu->pdu_size = 2 + sizeof(nfapi_hi_dci0_hi_pdu); + hi_dci0_pdu->hi_pdu.hi_pdu_rel8.tl.tag = NFAPI_HI_DCI0_REQUEST_HI_PDU_REL8_TAG; + hi_dci0_pdu->hi_pdu.hi_pdu_rel8.resource_block_start = ra->msg3_first_rb; + hi_dci0_pdu->hi_pdu.hi_pdu_rel8.cyclic_shift_2_for_drms = 0; + hi_dci0_pdu->hi_pdu.hi_pdu_rel8.hi_value = 0; + hi_dci0_req_body->number_of_hi++; + hi_dci0_req_body->sfnsf = sfnsf_add_subframe(ra->Msg3_frame, ra->Msg3_subframe, 0); + hi_dci0_req_body->tl.tag = NFAPI_HI_DCI0_REQUEST_BODY_TAG; + hi_dci0_req->sfn_sf = sfnsf_add_subframe(frameP, subframeP, sf_ahead_dl); + hi_dci0_req->header.message_id = NFAPI_HI_DCI0_REQUEST; + + if (NFAPI_MODE != NFAPI_MONOLITHIC) { + oai_nfapi_hi_dci0_req(hi_dci0_req); + hi_dci0_req_body->number_of_hi=0; + } + + LOG_D(MAC, "MSG3: HI_DCI0 SFN/SF:%d number_of_dci:%d number_of_hi:%d\n", NFAPI_SFNSF2DEC(hi_dci0_req->sfn_sf), hi_dci0_req_body->number_of_dci, hi_dci0_req_body->number_of_hi); + + // save UL scheduling information for preprocessor + for (j = 0; j < ra->msg3_nb_rb; j++) + cc->vrb_map_UL[ra->msg3_first_rb + j] = 1; + + LOG_D(MAC, + "[eNB %d][PUSCH-RA %x] CC_id %d Frame %d subframeP %d Scheduled (PHICH) RA (mcs %d, first rb %d, nb_rb %d,round %d)\n", + module_idP, ra->rnti, CC_id, frameP, subframeP, 10, 1, 1, + ra->msg3_round - 1); + } // if (ra->msg3_round != 0) { // program HI too + } // non-BL/CE UE case + #endif +} \ No newline at end of file diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c index 9555e1d046..024496c3d0 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c @@ -31,9 +31,9 @@ */ #include "assertions.h" -#include "LAYER2/NR_MAC_gNB/nr_mac_gNB.h" -#include "LAYER2/NR_MAC_gNB/mac_proto.h" -#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" +#include "NR_MAC_gNB/nr_mac_gNB.h" +#include "NR_MAC_gNB/mac_proto.h" +#include "NR_MAC_COMMON/nr_mac_extern.h" #include "common/utils/LOG/log.h" #include "common/utils/LOG/vcd_signal_dumper.h" #include "UTIL/OPT/opt.h" diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c index 5233270149..2999f4d8ee 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c @@ -34,9 +34,9 @@ #include "PHY/defs_nr_common.h" #include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" /*MAC*/ -#include "LAYER2/NR_MAC_COMMON/nr_mac.h" -#include "LAYER2/NR_MAC_gNB/nr_mac_gNB.h" -#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" +#include "NR_MAC_COMMON/nr_mac.h" +#include "NR_MAC_gNB/nr_mac_gNB.h" +#include "NR_MAC_COMMON/nr_mac_extern.h" #include "LAYER2/MAC/mac.h" /*NFAPI*/ @@ -97,6 +97,7 @@ int nr_generate_dlsch_pdu(module_id_t module_idP, } LOG_D(MAC, "NR MAC CE timing advance command = %d (%d) TAG ID = %d\n", timing_advance_cmd, ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND, tag_id); + mac_ce_size = sizeof(NR_MAC_CE_TA); // Copying bytes for MAC CEs to the mac pdu pointer diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 55a7385143..68f1021c68 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -30,8 +30,8 @@ #include "nr_mac_gNB.h" #include "SCHED_NR/sched_nr.h" -#include "mac_proto.h" -#include "nr_mac_common.h" +#include "NR_MAC_gNB/mac_proto.h" +#include "LAYER2/NR_MAC_COMMON/nr_mac_common.h" #include "PHY/NR_TRANSPORT/nr_dlsch.h" #include "PHY/NR_TRANSPORT/nr_dci.h" #include "executables/nr-softmodem.h" diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 9a9bfa0164..a94934c432 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -33,10 +33,10 @@ #include "assertions.h" #include "LAYER2/MAC/mac.h" -#include "LAYER2/NR_MAC_gNB/nr_mac_gNB.h" -#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" +#include "NR_MAC_gNB/nr_mac_gNB.h" +#include "NR_MAC_COMMON/nr_mac_extern.h" -#include "LAYER2/NR_MAC_gNB/mac_proto.h" +#include "NR_MAC_gNB/mac_proto.h" #include "common/utils/LOG/log.h" #include "common/utils/LOG/vcd_signal_dumper.h" #include "common/utils/nr/nr_common.h" @@ -1363,4 +1363,177 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){ } } } -*/ \ No newline at end of file +*/ + +/* TBR fix this +boolean_t nr_CCE_allocation_infeasible(int module_idP, int CC_idP, int format_flag, int slot, int aggregation, int rnti){ + + nfapi_dl_config_request_body_t *DL_req = &RC.mac[module_idP]->DL_req[CC_idP].dl_config_request_body; + nfapi_dl_config_request_pdu_t *dl_config_pdu = &DL_req->dl_config_pdu_list[DL_req->number_pdu]; + nfapi_hi_dci0_request_body_t *HI_DCI0_req = &RC.mac[module_idP]->HI_DCI0_req[CC_idP][slot].hi_dci0_request_body; + nfapi_hi_dci0_request_pdu_t *hi_dci0_pdu = &HI_DCI0_req->hi_dci0_pdu_list[HI_DCI0_req->number_of_dci + HI_DCI0_req->number_of_hi]; + + int ret; + boolean_t res = FALSE; + + if (format_flag != 2) { // DL DCI + if (DL_req->number_pdu == MAX_NUM_DL_PDU) { + LOG_W(MAC, + "Subframe %d: FAPI DL structure is full, skip scheduling UE %d\n", + slot, rnti); + } else { + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tl.tag = NFAPI_DL_CONFIG_REQUEST_DCI_DL_PDU_REL8_TAG; + dl_config_pdu->pdu_type = NFAPI_DL_CONFIG_DCI_DL_PDU_TYPE; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti = rnti; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type = (format_flag == 0) ? 2 : 1; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level = aggregation; + DL_req->number_pdu++; + + LOG_D(MAC, "Subframe %d: Checking CCE feasibility format %d : (%x,%d) (%x,%d,%d)\n", + slot, format_flag, rnti, aggregation, + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti, + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8. + aggregation_level, + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type); + + // ret = nr_allocate_CCEs(module_idP, CC_idP, 0, slot, 0); // TBR + + if (ret == -1) res = TRUE; + + DL_req->number_pdu--; + } + } else { // ue-specific UL DCI + if (HI_DCI0_req->number_of_dci + HI_DCI0_req->number_of_hi == MAX_NUM_HI_DCI0_PDU) { + LOG_W(MAC, "Subframe %d: FAPI UL structure is full, skip scheduling UE %d\n", slot, rnti); + } else { + hi_dci0_pdu->pdu_type = NFAPI_HI_DCI0_DCI_PDU_TYPE; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.tl.tag = NFAPI_HI_DCI0_REQUEST_DCI_PDU_REL8_TAG; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.rnti = rnti; + hi_dci0_pdu->dci_pdu.dci_pdu_rel8.aggregation_level = aggregation; + HI_DCI0_req->number_of_dci++; + // ret = nr_allocate_CCEs(module_idP, CC_idP, 0, slot, 0); // TBR + if (ret == -1) res = TRUE; + HI_DCI0_req->number_of_dci--; + } + } + + return res; +}*/ + +/* // TBR fix this +void nr_get_Msg3alloc(NR_COMMON_channels_t *cc, + sub_frame_t current_subframe, // TBR sub_frame_t + frame_t current_frame, + frame_t *frame, + sub_frame_t *subframe){ + // Fill in other TDD Configuration!!!! + + // TBR missing ‘tdd_Config’ in NR_COMMON_channels_t + if (cc->tdd_Config == NULL) { // FDD + *subframe = current_subframe + 6; + if (*subframe > 9) { + *subframe = *subframe - 10; + *frame = (current_frame + 1) & 1023; + } else { + *frame = current_frame; + } + } else { // TDD + if (cc->tdd_Config->subframeAssignment == 1) { + switch (current_subframe) { + + case 0: + *subframe = 7; + *frame = current_frame; + break; + + case 4: + *subframe = 2; + *frame = (current_frame + 1) & 1023; + break; + + case 5: + *subframe = 2; + *frame = (current_frame + 1) & 1023; + break; + + case 9: + *subframe = 7; + *frame = (current_frame + 1) & 1023; + break; + } + } else if (cc->tdd_Config->subframeAssignment == 3) { + switch (current_subframe) { + + case 0: + case 5: + case 6: + *subframe = 2; + *frame = (current_frame + 1) & 1023; + break; + + case 7: + *subframe = 3; + *frame = (current_frame + 1) & 1023; + break; + + case 8: + *subframe = 4; + *frame = (current_frame + 1) & 1023; + break; + + case 9: + *subframe = 2; + *frame = (current_frame + 2) & 1023; + break; + } + } else if (cc->tdd_Config->subframeAssignment == 4) { + switch (current_subframe) { + + case 0: + case 4: + case 5: + case 6: + *subframe = 2; + *frame = (current_frame + 1) & 1023; + break; + + case 7: + *subframe = 3; + *frame = (current_frame + 1) & 1023; + break; + + case 8: + case 9: + *subframe = 2; + *frame = (current_frame + 2) & 1023; + break; + } + } else if (cc->tdd_Config->subframeAssignment == 5) { + switch (current_subframe){ + case 0: + case 4: + case 5: + case 6: + *subframe = 2; + *frame = (current_frame + 1) & 1023; + break; + + case 7: + case 8: + case 9: + *subframe = 2; + *frame = (current_frame + 2) & 1023; + break; + } + } + } // else TDD +}*/ + +uint16_t nr_mac_compute_RIV(uint16_t N_RB_DL, uint16_t RBstart, uint16_t Lcrbs){ // TBR this is outdated + uint16_t RIV; + + if (Lcrbs <= (1 + (N_RB_DL >> 1))) RIV = (N_RB_DL * (Lcrbs - 1)) + RBstart; + else RIV = (N_RB_DL * (N_RB_DL + 1 - Lcrbs)) + (N_RB_DL - 1 - RBstart); + + return RIV; +} \ No newline at end of file diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c index 4ae679b8f5..604664f3ef 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c @@ -28,7 +28,7 @@ * @ingroup _mac */ -#include "LAYER2/NR_MAC_gNB/mac_proto.h" +#include "NR_MAC_gNB/mac_proto.h" /* * When data are received on PHY and transmitted to MAC diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index e0932e28e1..c2ca2dc1fe 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -31,8 +31,9 @@ #ifndef __LAYER2_NR_MAC_PROTO_H__ #define __LAYER2_NR_MAC_PROTO_H__ -#include "nr_mac_gNB.h" #include "PHY/defs_gNB.h" + +#include "LAYER2/NR_MAC_gNB/nr_mac_gNB.h" #include "NR_TAG-Id.h" void set_cset_offset(uint16_t); @@ -76,6 +77,61 @@ void nr_schedule_ue_spec(module_id_t module_idP, frame_t frameP, sub_frame_t slo void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP); +/////// Random Access MAC-PHY interface functions and primitives /////// + +void nr_schedule_RA(module_id_t module_idP, frame_t frameP, sub_frame_t slotP); + +/* \brief Function to indicate a received preamble on PRACH. It initiates the RA procedure. +@param module_idP Instance ID of gNB +@param preamble_index index of the received RA request +@param slotP Slot number on which to act +@param timing_offset Offset in samples of the received PRACH w.r.t. eNB timing. This is used to +@param rnti RA rnti corresponding to this PRACH preamble +@param rach_resource type (0=non BL/CE,1 CE level 0,2 CE level 1, 3 CE level 2,4 CE level 3) +*/ +void nr_initiate_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP, + uint16_t preamble_index, int16_t timing_offset, uint16_t rnti + #if (RRC_VERSION >= MAKE_VERSION(14, 0, 0)) + , uint8_t rach_resource_type + #endif + ); + +void nr_clear_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP); + +boolean_t nr_CCE_allocation_infeasible(int module_idP, + int CC_idP, + int common_flag, + int slot, + int aggregation, + int rnti); + +int nr_allocate_CCEs(int module_idP, int CC_idP, frame_t frameP, sub_frame_t slotP, int test_only); + +void nr_get_Msg3alloc(NR_COMMON_channels_t *cc, + sub_frame_t current_subframe, + frame_t current_frame, + frame_t *frame, + sub_frame_t *subframe); + +/* \brief Function in gNB to fill RAR pdu when requested by PHY. This provides a single RAR SDU for the moment and returns the t-CRNTI. +@param Mod_id Instance ID of gNB +@param dlsch_buffer Pointer to DLSCH input buffer +@param N_RB_UL Number of UL resource blocks +@returns t_CRNTI +*/ +unsigned short nr_fill_rar(const module_id_t module_idP, + const int CC_id, + NR_RA_t *ra, + const frame_t frameP, + uint8_t * const dlsch_buffer, + const uint16_t N_RB_UL, + const uint8_t input_buffer_length); + + +uint16_t nr_mac_compute_RIV(uint16_t N_RB_DL, uint16_t RBstart, uint16_t Lcrbs); + +/////// Phy test scheduler /////// + void nr_schedule_css_dlsch_phytest(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP); @@ -215,4 +271,42 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP, const uint16_t sdu_lenP, const uint16_t timing_advance, const uint8_t ul_cqi); +/* Random Access */ + +/* \brief Function called by PHY to retrieve information to be transmitted using the RA procedure. +If the UE is not in PUSCH mode for a particular eNB index, this is assumed to be an Msg3 and MAC +attempts to retrieves the CCCH message from RRC. If the UE is in PUSCH mode for a particular eNB +index and PUCCH format 0 (Scheduling Request) is not activated, the MAC may use this resource for +andom-access to transmit a BSR along with the C-RNTI control element (see 5.1.4 from 36.321) +@param mod_id Index of UE instance +@param CC_id Component Carrier Index +@param frame +@param gNB_id gNB index +@param nr_tti_tx slot for PRACH transmission +@returns A pointer to a PRACH_RESOURCES_t */ +NR_PRACH_RESOURCES_t *nr_ue_get_rach(module_id_t mod_id, + int CC_id, + UE_MODE_t UE_mode, + frame_t frame, + uint8_t gNB_id, + int nr_tti_tx); + +/* \brief Function implementing the routine for the selection of Random Access resources (5.1.2 TS 38.321). +@param module_idP Index of UE instance +@param CC_id Component Carrier Index +@param gNB_index gNB index +@param t_id +@param rach_ConfigDedicated +@returns A pointer to a PRACH_RESOURCES_t */ +void nr_get_prach_resources(module_id_t mod_id, + int CC_id, + uint8_t gNB_id, + uint8_t t_id, + uint8_t first_Msg3, + NR_RACH_ConfigDedicated_t * rach_ConfigDedicated); + +void nr_Msg1_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id); + +void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id); + #endif /*__LAYER2_NR_MAC_PROTO_H__*/ diff --git a/openair2/LAYER2/NR_MAC_gNB/main.c b/openair2/LAYER2/NR_MAC_gNB/main.c index ff552d0bfd..775116faf6 100644 --- a/openair2/LAYER2/NR_MAC_gNB/main.c +++ b/openair2/LAYER2/NR_MAC_gNB/main.c @@ -30,8 +30,8 @@ */ -#include "mac_proto.h" -#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" +#include "NR_MAC_gNB/mac_proto.h" +#include "NR_MAC_COMMON/nr_mac_extern.h" #include "assertions.h" #include "LAYER2/PDCP_v10.1.0/pdcp.h" diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index 5bc320d5e2..ad92fdb979 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -42,30 +42,95 @@ #include #include +/* Commmon */ +#include "targets/ARCH/COMMON/common_lib.h" +#include "COMMON/platform_constants.h" +#include "common/ran_context.h" + +/* RRC */ #include "NR_BCCH-BCH-Message.h" #include "NR_CellGroupConfig.h" #include "NR_ServingCellConfigCommon.h" #include "NR_MeasConfig.h" +/* PHY */ +#include "PHY/defs_gNB.h" +#include "PHY/TOOLS/time_meas.h" + +/* Interface */ #include "nfapi_nr_interface_scf.h" #include "NR_PHY_INTERFACE/NR_IF_Module.h" -#include "COMMON/platform_constants.h" -#include "common/ran_context.h" +/* MAC */ #include "LAYER2/MAC/mac.h" #include "LAYER2/MAC/mac_proto.h" #include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" -#include "PHY/defs_gNB.h" -#include "PHY/TOOLS/time_meas.h" -#include "targets/ARCH/COMMON/common_lib.h" - -#include "nr_mac_common.h" +#include "LAYER2/NR_MAC_COMMON/nr_mac_common.h" +#include "NR_TAG.h" +/* Defs */ #define MAX_NUM_BWP 2 #define MAX_NUM_CORESET 2 #define MAX_NUM_CCE 90 +/*!\brief Maximum number of random access process */ +#define NR_NB_RA_PROC_MAX 4 -#include "NR_TAG.h" +/*! \brief gNB template for the Random access information */ +typedef struct { + /// Flag to indicate this process is active + RA_state_t state; + /// Subframe where preamble was received + uint8_t preamble_subframe; + /// Subframe where Msg2 is to be sent + uint8_t Msg2_subframe; + /// Frame where Msg2 is to be sent + frame_t Msg2_frame; + /// Subframe where Msg3 is to be sent + sub_frame_t Msg3_subframe; + /// Frame where Msg3 is to be sent + frame_t Msg3_frame; + /// Subframe where Msg4 is to be sent + sub_frame_t Msg4_subframe; + /// Frame where Msg4 is to be sent + frame_t Msg4_frame; + /// harq_pid used for Msg4 transmission + uint8_t harq_pid; + /// UE RNTI allocated during RAR + rnti_t rnti; + /// RA RNTI allocated from received PRACH + uint16_t RA_rnti; + /// Received preamble_index + uint8_t preamble_index; + /// Received UE Contention Resolution Identifier + uint8_t cont_res_id[6]; + /// Timing offset indicated by PHY + int16_t timing_offset; + /// Timeout for RRC connection + int16_t RRC_timer; + /// Msg3 first RB + uint8_t msg3_first_rb; + /// Msg3 number of RB + uint8_t msg3_nb_rb; + /// Msg3 MCS + uint8_t msg3_mcs; + /// Msg3 TPC command + uint8_t msg3_TPC; + /// Msg3 ULdelay command + uint8_t msg3_ULdelay; + /// Msg3 cqireq command + uint8_t msg3_cqireq; + /// Round of Msg3 HARQ + uint8_t msg3_round; + /// TBS used for Msg4 + int msg4_TBsize; + /// MCS used for Msg4 + int msg4_mcs; + /// + int32_t crnti_rrc_mui; // TBR + /// + int8_t crnti_harq_pid; // TBR + +} NR_RA_t; /*! \brief gNB common channels */ typedef struct { @@ -93,7 +158,7 @@ typedef struct { /// Outgoing RAR pdu for PHY RAR_PDU RAR_pdu; /// Template for RA computations - RA_t ra[NB_RA_PROC_MAX]; + NR_RA_t ra[NR_NB_RA_PROC_MAX]; /// VRB map for common channels uint8_t vrb_map[100]; /// VRB map for common channels and retransmissions by PHICH @@ -107,9 +172,8 @@ typedef struct { int dummy; } NR_UE_sched_ctrl_t; -/*! \brief UE list used by eNB to order UEs/CC for scheduling*/ +/*! \brief UE list used by gNB to order UEs/CC for scheduling*/ typedef struct { - DLSCH_PDU DLSCH_pdu[4][MAX_MOBILES_PER_GNB]; /// scheduling control info UE_sched_ctrl_t UE_sched_ctrl[MAX_MOBILES_PER_GNB]; @@ -192,66 +256,63 @@ typedef struct gNB_MAC_INST_s { typedef struct { + uint8_t format_indicator; //1 bit + uint16_t frequency_domain_assignment; //up to 16 bits + uint8_t time_domain_assignment; // 4 bits + uint8_t frequency_hopping_flag; //1 bit -uint8_t format_indicator; //1 bit -uint16_t frequency_domain_assignment; //up to 16 bits -uint8_t time_domain_assignment; // 4 bits -uint8_t frequency_hopping_flag; //1 bit + uint8_t ra_preamble_index; //6 bits + uint8_t ss_pbch_index; //6 bits + uint8_t prach_mask_index; //4 bits -uint8_t ra_preamble_index; //6 bits -uint8_t ss_pbch_index; //6 bits -uint8_t prach_mask_index; //4 bits + uint8_t vrb_to_prb_mapping; //0 or 1 bit + uint8_t mcs; //5 bits + uint8_t ndi; //1 bit + uint8_t rv; //2 bits + uint8_t harq_pid; //4 bits + uint8_t dai; //0, 2 or 4 bits + uint8_t dai1; //1 or 2 bits + uint8_t dai2; //0 or 2 bits + uint8_t tpc; //2 bits + uint8_t pucch_resource_indicator; //3 bits + uint8_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits -uint8_t vrb_to_prb_mapping; //0 or 1 bit -uint8_t mcs; //5 bits -uint8_t ndi; //1 bit -uint8_t rv; //2 bits -uint8_t harq_pid; //4 bits -uint8_t dai; //0, 2 or 4 bits -uint8_t dai1; //1 or 2 bits -uint8_t dai2; //0 or 2 bits -uint8_t tpc; //2 bits -uint8_t pucch_resource_indicator; //3 bits -uint8_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits + uint8_t short_messages_indicator; //2 bits + uint8_t short_messages; //8 bits + uint8_t tb_scaling; //2 bits -uint8_t short_messages_indicator; //2 bits -uint8_t short_messages; //8 bits -uint8_t tb_scaling; //2 bits + uint8_t carrier_indicator; //0 or 3 bits + uint8_t bwp_indicator; //0, 1 or 2 bits + uint8_t prb_bundling_size_indicator; //0 or 1 bits + uint8_t rate_matching_indicator; //0, 1 or 2 bits + uint8_t zp_csi_rs_trigger; //0, 1 or 2 bits + uint8_t transmission_configuration_indication; //0 or 3 bits + uint8_t srs_request; //2 bits + uint8_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits + uint8_t cbgfi; //CBG Flushing Out Information: 0 or 1 bit + uint8_t dmrs_sequence_initialization; //0 or 1 bit -uint8_t carrier_indicator; //0 or 3 bits -uint8_t bwp_indicator; //0, 1 or 2 bits -uint8_t prb_bundling_size_indicator; //0 or 1 bits -uint8_t rate_matching_indicator; //0, 1 or 2 bits -uint8_t zp_csi_rs_trigger; //0, 1 or 2 bits -uint8_t transmission_configuration_indication; //0 or 3 bits -uint8_t srs_request; //2 bits -uint8_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits -uint8_t cbgfi; //CBG Flushing Out Information: 0 or 1 bit -uint8_t dmrs_sequence_initialization; //0 or 1 bit + uint8_t srs_resource_indicator; + uint8_t precoding_information; + uint8_t csi_request; + uint8_t ptrs_dmrs_association; + uint8_t beta_offset_indicator; //0 or 2 bits -uint8_t srs_resource_indicator; -uint8_t precoding_information; -uint8_t csi_request; -uint8_t ptrs_dmrs_association; -uint8_t beta_offset_indicator; //0 or 2 bits + uint8_t slot_format_indicator_count; + uint8_t *slot_format_indicators; -uint8_t slot_format_indicator_count; -uint8_t *slot_format_indicators; + uint8_t pre_emption_indication_count; + uint16_t *pre_emption_indications; //14 bit -uint8_t pre_emption_indication_count; -uint16_t *pre_emption_indications; //14 bit + uint8_t block_number_count; + uint8_t *block_numbers; -uint8_t block_number_count; -uint8_t *block_numbers; + uint8_t ul_sul_indicator; //0 or 1 bit + uint8_t antenna_ports; -uint8_t ul_sul_indicator; //0 or 1 bit -uint8_t antenna_ports; - -uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits -uint16_t padding; + uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits + uint16_t padding; } dci_pdu_rel15_t; - - #endif /*__LAYER2_NR_MAC_GNB_H__ */ diff --git a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c index 770e27dd60..6062995841 100644 --- a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c @@ -57,24 +57,19 @@ void handle_nr_rach(NR_UL_IND_t *UL_info) { AssertFatal(UL_info->rach_ind.rach_indication_body.number_of_preambles==1,"More than 1 preamble not supported\n"); UL_info->rach_ind.rach_indication_body.number_of_preambles=0; LOG_D(MAC,"UL_info[Frame %d, Slot %d] Calling initiate_ra_proc RACH:SFN/SF:%d\n",UL_info->frame,UL_info->slot, NFAPI_SFNSF2DEC(UL_info->rach_ind.sfn_sf)); - /* - initiate_ra_proc(UL_info->module_id, - UL_info->CC_id, - NFAPI_SFNSF2SFN(UL_info->rach_ind.sfn_sf), - NFAPI_SFNSF2SF(UL_info->rach_ind.sfn_sf), - UL_info->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.preamble, - UL_info->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.timing_advance, - UL_info->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.rnti -#if (NR_RRC_VERSION >= MAKE_VERSION(14, 0, 0)) || (LTE_RRC_VERSION >= MAKE_VERSION(14, 0, 0)) -//#if (RRC_VERSION >= MAKE_VERSION(14, 0, 0)) - ,0 -#endif - - ); - */ + nr_initiate_ra_proc(UL_info->module_id, + UL_info->CC_id, + NFAPI_SFNSF2SFN(UL_info->rach_ind.sfn_sf), + NFAPI_SFNSF2SF(UL_info->rach_ind.sfn_sf), + UL_info->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.preamble, + UL_info->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.timing_advance, + UL_info->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.rnti + #if (RRC_VERSION >= MAKE_VERSION(14, 0, 0)) // TBR + ,0 + #endif + ); } - } void handle_nr_sr(NR_UL_IND_t *UL_info) { diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c index 4e6c0d8979..3ac9a8a43f 100644 --- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c @@ -32,9 +32,9 @@ #include "PHY/defs_nr_UE.h" #include "NR_IF_Module.h" -#include "mac_proto.h" +#include "NR_MAC_UE/mac_proto.h" #include "assertions.h" -#include "LAYER2/NR_MAC_UE/mac_extern.h" +#include "NR_MAC_UE/mac_extern.h" #include "SCHED_NR_UE/fapi_nr_ue_l1.h" #include "executables/nr-softmodem.h" @@ -93,6 +93,14 @@ int8_t handle_dlsch (module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_n */ } +int8_t handle_rar (module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_indication_t *dci_ind, uint8_t *pduP, uint32_t pdu_len, frame_t frame, int slot, NR_UL_TIME_ALIGNMENT_t *ul_time_alignment){ + + if (IS_SOFTMODEM_NOS1 || IS_SOFTMODEM_RFSIM) + //nr_process_rar(ue,proc, gNB_index, mode); TBR + + return 0; +} + int nr_ue_ul_indication(nr_uplink_indication_t *ul_info){ NR_UE_L2_STATE_t ret; @@ -231,11 +239,11 @@ int nr_ue_dl_indication(nr_downlink_indication_t *dl_info, NR_UL_TIME_ALIGNMENT_ dl_info->rx_ind->rx_indication_body[i].mib_pdu.cell_id )) << FAPI_NR_RX_PDU_TYPE_MIB;*/ break; case FAPI_NR_RX_PDU_TYPE_SIB: - ret_mask |= (handle_bcch_dlsch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, - (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.sibs_mask, - (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.pdu, - (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.pdu_length )) << FAPI_NR_RX_PDU_TYPE_SIB; - break; + ret_mask |= (handle_bcch_dlsch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, + (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.sibs_mask, + (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.pdu, + (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.pdu_length )) << FAPI_NR_RX_PDU_TYPE_SIB; + break; case FAPI_NR_RX_PDU_TYPE_DLSCH: // ret_mask |= (0) << FAPI_NR_RX_PDU_TYPE_DLSCH; ret_mask |= (handle_dlsch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, dl_info->dci_ind, @@ -249,17 +257,17 @@ int nr_ue_dl_indication(nr_downlink_indication_t *dl_info, NR_UL_TIME_ALIGNMENT_ dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH; dl_config->number_pdus = dl_config->number_pdus + 1; */ + break; - /*ret_mask |= (handle_dlsch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, dl_info->dci_ind, - dl_info->rx_ind->rx_indication_body[i].pdsch_pdu.pdu, - dl_info->rx_ind->rx_indication_body[i].pdsch_pdu.pdu_length, dl_info->frame, dl_info->slot)) << FAPI_NR_RX_PDU_TYPE_DLSCH; + case FAPI_NR_RX_PDU_TYPE_RAR: + /*ret_mask |= (handle_rar(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, dl_info->dci_ind, + (dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu, + (dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu_length, + dl_info->frame, dl_info->slot,ul_time_alignment)) << FAPI_NR_RX_PDU_TYPE_RAR;*/ //TODO TBR + break; - */ - break; default: - - break; - + break; } } } diff --git a/openair2/RRC/NR/L2_nr_interface.c b/openair2/RRC/NR/L2_nr_interface.c index fb1ed160cb..8b2966e0c5 100644 --- a/openair2/RRC/NR/L2_nr_interface.c +++ b/openair2/RRC/NR/L2_nr_interface.c @@ -53,9 +53,8 @@ int8_t mac_rrc_nr_data_req(const module_id_t Mod_idP, uint8_t *const buffer_pP ){ asn_enc_rval_t enc_rval; - //SRB_INFO *Srb_info; - //uint8_t Sdu_size = 0; - uint8_t sfn_msb = (uint8_t)((frameP>>4)&0x3f); + uint8_t Sdu_size = 0; + uint8_t sfn_msb = (uint8_t)((frameP>>4)&0x3f); #ifdef DEBUG_RRC LOG_D(RRC,"[eNB %d] mac_rrc_data_req to SRB ID=%ld\n",Mod_idP,Srb_id); @@ -64,11 +63,15 @@ int8_t mac_rrc_nr_data_req(const module_id_t Mod_idP, gNB_RRC_INST *rrc; rrc_gNB_carrier_data_t *carrier; NR_BCCH_BCH_Message_t *mib; + NR_SRB_INFO * srb_info; + char payload_size, payload_pP; rrc = RC.nrrrc[Mod_idP]; carrier = &rrc->carrier; mib = &carrier->mib; + srb_info = &carrier->Srb0; + /* MIBCH */ if( (Srb_id & RAB_OFFSET ) == MIBCH) { mib->message.choice.mib->systemFrameNumber.buf[0] = sfn_msb << 2; enc_rval = uper_encode_to_buffer(&asn_DEF_NR_BCCH_BCH_Message, @@ -86,10 +89,31 @@ int8_t mac_rrc_nr_data_req(const module_id_t Mod_idP, return(3); } -//BCCH SIB1 SIBs + /* TODO BCCH SIB1 SIBs */ -//CCCH + /* CCCH */ // TBR lte code + if( (Srb_id & RAB_OFFSET ) == CCCH) { + //struct rrc_eNB_ue_context_s *ue_context_p = rrc_eNB_get_ue_context(RC.rrc[Mod_idP],rnti); + //if (ue_context_p == NULL) return(0); + //eNB_RRC_UE_t *ue_p = &ue_context_p->ue_context; + LOG_D(RRC,"[gNB %d] Frame %d CCCH request (Srb_id %d)\n", Mod_idP, frameP, Srb_id); + + // srb_info=&ue_p->Srb0; + + payload_size = srb_info->Tx_buffer.payload_size; + + // check if data is there for MAC + if (payload_size > 0) { + payload_pP = srb_info->Tx_buffer.Payload; + LOG_D(RRC,"[gNB %d] CCCH (%p) has %d bytes (dest: %p, src %p)\n", Mod_idP, srb_info, payload_size, buffer_pP, payload_pP); + // Fill buffer + memcpy(buffer_pP, payload_pP, payload_size); + Sdu_size = payload_size; + srb_info->Tx_buffer.payload_size = 0; + } + return Sdu_size; + } return(0); -} +} \ No newline at end of file diff --git a/openair2/RRC/NR_UE/rrc_UE.c b/openair2/RRC/NR_UE/rrc_UE.c index 38163a68b8..862cf48cec 100755 --- a/openair2/RRC/NR_UE/rrc_UE.c +++ b/openair2/RRC/NR_UE/rrc_UE.c @@ -42,7 +42,7 @@ #include "rrc_defs.h" #include "rrc_proto.h" #include "rrc_vars.h" -#include "mac_proto.h" +#include "LAYER2/NR_MAC_UE/mac_proto.h" extern int phy_test; diff --git a/openair2/RRC/NR_UE/rrc_defs.h b/openair2/RRC/NR_UE/rrc_defs.h index cb1207757d..6481fb0cea 100644 --- a/openair2/RRC/NR_UE/rrc_defs.h +++ b/openair2/RRC/NR_UE/rrc_defs.h @@ -39,8 +39,8 @@ #include "platform_types.h" -#include "LAYER2/NR_MAC_UE/mac.h" -#include "LAYER2/NR_MAC_COMMON/nr_mac.h" +#include "NR_MAC_UE/mac.h" +#include "NR_MAC_COMMON/nr_mac.h" #include "rrc_list.h" #include "NR_asn_constant.h" #include "NR_MeasConfig.h" From 083234133a4d5c9debb9f5abde03d9101ee4cc37 Mon Sep 17 00:00:00 2001 From: cig Date: Thu, 6 Feb 2020 15:35:20 +0100 Subject: [PATCH 014/553] Hardcoded prach config common parameters --- openair1/PHY/INIT/nr_parms.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/openair1/PHY/INIT/nr_parms.c b/openair1/PHY/INIT/nr_parms.c index 1ae0a47d59..edeb630dee 100644 --- a/openair1/PHY/INIT/nr_parms.c +++ b/openair1/PHY/INIT/nr_parms.c @@ -344,6 +344,14 @@ int nr_init_frame_parms_ue(NR_DL_FRAME_PARMS *fp, fp->ssb_start_subcarrier = (12 * config->ssb_table.ssb_offset_point_a + sco); + // TBR temporary hardcoded + fp->prach_config_common.rootSequenceIndex = 22; // 0 + fp->prach_config_common.prach_Config_enabled = 1; + fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig = 1; // 13 + fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex = 0; // 98 + fp->prach_config_common.prach_ConfigInfo.highSpeedFlag = 0; + fp->prach_config_common.prach_ConfigInfo.msg1_frequencystart = 0; + // definition of Lmax according to ts 38.213 section 4.1 if (fp->dl_CarrierFreq < 6e9) { if(fp->frame_type && (fp->ssb_type==2)) From e01dd43b7b4e1bef799a66856169d8bce2313c44 Mon Sep 17 00:00:00 2001 From: cig Date: Thu, 6 Feb 2020 15:36:01 +0100 Subject: [PATCH 015/553] Cleanup comments, removed UE files from gNB MAC library --- cmake_targets/CMakeLists.txt | 2 -- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 7 +++---- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index 76f2a485ea..b3918abaf6 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -1766,8 +1766,6 @@ set (MAC_NR_SRC ${NR_GNB_MAC_DIR}/gNB_scheduler_primitives.c ${NR_GNB_MAC_DIR}/gNB_scheduler_phytest.c ${NR_GNB_MAC_DIR}/gNB_scheduler_RA.c - ${NR_UE_MAC_DIR}/nr_l1_helpers.c - ${NR_UE_MAC_DIR}/nr_ra_procedures.c ) diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 5a292661fd..eedd2ad581 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -2289,8 +2289,8 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, //int32_t ulsch_start=0; int slot_tx = proc->nr_tti_tx; int frame_tx = proc->frame_tx; - uint8_t harq_pid = 0; // TBR - runmode_t mode = normal_txrx; // TBR set proper mode + uint8_t harq_pid = 0; + runmode_t mode = normal_txrx; VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX,VCD_FUNCTION_IN); @@ -2328,14 +2328,13 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, // check if we have PRACH opportunity if (is_nr_prach_subframe(&ue->frame_parms, frame_tx, slot_tx)) { // TBR TODO FIX this works only for TDD but it enters phy_procedures_nrUE_TX only when mode is FDD - printf("the value of is_nr_prach subframe is %d\n", is_nr_prach_subframe(&ue->frame_parms, frame_tx, slot_tx)); // TBR debug + printf(" is_nr_prach_subframe is %d\n", is_nr_prach_subframe(&ue->frame_parms, frame_tx, slot_tx)); // TBR debug nr_ue_prach_procedures(ue, proc, gNB_id, mode); } } else { ue->generate_nr_prach = 0; } -/* RACH */ LOG_I(PHY,"****** end TX-Chain for AbsSubframe %d.%d ******\n", frame_tx, slot_tx); From 36195ec31aadf09ceead2f9eaf942710eabb6377 Mon Sep 17 00:00:00 2001 From: cig Date: Thu, 6 Feb 2020 20:09:30 +0100 Subject: [PATCH 016/553] RA fixes and additions: - RA resource selection and transmission - MAC header structs for RA - RA procedure msg1 fixes - code cleanup --- openair1/PHY/NR_UE_TRANSPORT/nr_prach.c | 10 +- .../NR_UE_TRANSPORT/nr_transport_proto_ue.h | 4 +- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 133 +++--- openair1/SIMULATION/NR_PHY/prachsim.c | 3 +- openair2/LAYER2/NR_MAC_COMMON/nr_mac.h | 42 ++ openair2/LAYER2/NR_MAC_UE/mac_defs.h | 2 + openair2/LAYER2/NR_MAC_UE/mac_proto.h | 13 + openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c | 26 +- openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 428 ++++++------------ .../NR_MAC_UE/nr_ue_dci_configuration.c | 2 +- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 170 ++++++- openair2/RRC/NR_UE/L2_interface_ue.c | 11 + openair2/RRC/NR_UE/rrc_proto.h | 12 + 13 files changed, 471 insertions(+), 385 deletions(-) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c index 1e46cde82e..c144a37a06 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c @@ -56,7 +56,7 @@ extern int64_t table_6_3_3_2_4_prachConfig_Index [256][10]; extern uint16_t nr_du[838]; extern int16_t nr_ru[2*839]; -int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, uint16_t Nf ) +int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) { //lte_frame_type_t frame_type = ue->frame_parms.frame_type; @@ -66,13 +66,13 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, uint8_t prach_ConfigIndex = fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex; uint8_t Ncs_config = fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig; uint8_t restricted_set = fp->prach_config_common.prach_ConfigInfo.highSpeedFlag; - uint8_t preamble_index = ue->prach_resources[eNB_id]->ra_PreambleIndex; - //uint8_t tdd_mapindex = ue->prach_resources[eNB_id]->ra_TDD_map_index; - int16_t *prachF = ue->prach_vars[eNB_id]->prachF; + uint8_t preamble_index = ue->prach_resources[gNB_id]->ra_PreambleIndex; + //uint8_t tdd_mapindex = ue->prach_resources[gNB_id]->ra_TDD_map_index; + int16_t *prachF = ue->prach_vars[gNB_id]->prachF; int16_t prach_tmp[98304*2*4] __attribute__((aligned(32))); int16_t *prach = prach_tmp; int16_t *prach2; - int16_t amp = ue->prach_vars[eNB_id]->amp; + int16_t amp = ue->prach_vars[gNB_id]->amp; int16_t Ncp; uint16_t NCS=0; uint16_t *prach_root_sequence_map; diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h index e6b43c26ac..2bf268051c 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h @@ -1755,9 +1755,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, uint8_t is_crnti, uint8_t llr8_flag); - - -int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, uint16_t Nf ); +int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe); void *dlsch_thread(void *arg); /**@}*/ diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index eedd2ad581..9a3168a33e 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -210,9 +210,12 @@ void nr_dump_dlsch_SI(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id, exit(-1); } +#endif + #if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706) -//unsigned int gain_table[31] = {100,112,126,141,158,178,200,224,251,282,316,359,398,447,501,562,631,708,794,891,1000,1122,1258,1412,1585,1778,1995,2239,2512,2818,3162}; -/* +unsigned int gain_table[31] = {100,112,126,141,158,178,200,224,251,282,316,359,398,447,501,562,631,708,794,891,1000,1122,1258,1412,1585,1778,1995,2239,2512,2818,3162}; +#endif + unsigned int get_tx_amp_prach(int power_dBm, int power_max_dBm, int N_RB_UL) { @@ -250,9 +253,10 @@ void nr_dump_dlsch_SI(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id, else return(amp_x_100/gain_table[-gain_dB]); // 245 corresponds to the factor sqrt(25/6) } -*/ -unsigned int get_tx_amp(int power_dBm, int power_max_dBm, int N_RB_UL, int nb_rb) +#if 0 + +unsigned int get_tx_amp(int power_dBm, int power_max_dBm, int N_RB_UL, int nb_rb) // TbD { int gain_dB = power_dBm - power_max_dBm; @@ -269,8 +273,6 @@ unsigned int get_tx_amp(int power_dBm, int power_max_dBm, int N_RB_UL, int nb_rb return(0); } -#endif - void nr_dump_dlsch_ra(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t nr_tti_rx) { unsigned int coded_bits_per_codeword; @@ -4480,11 +4482,11 @@ uint8_t nr_is_ri_TXOp(PHY_VARS_NR_UE *ue, return(0); } -void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t gNB_id, runmode_t mode) { +void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t gNB_id, runmode_t runmode) { /* TBR // here params are hardcoded */ int frame_tx = proc->frame_tx, nr_tti_tx = proc->nr_tti_tx, prach_power; - uint16_t preamble_tx=ue->prach_resources[0]->ra_PreambleIndex; //uint16_t preamble_tx=50; // TBR + uint16_t preamble_tx = 50, pathloss; NR_PRACH_RESOURCES_t prach_resources; uint8_t mod_id = ue->Mod_id; NR_UE_MAC_INST_t *nr_UE_mac_inst = get_mac_inst(mod_id); @@ -4493,76 +4495,56 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_IN); ue->generate_nr_prach = 0; - if (ue->mac_enabled == 0){ - ue->prach_resources[gNB_id] = &prach_resources; // TBR double check pointer - ue->prach_resources[gNB_id]->ra_PreambleIndex = preamble_tx; - ue->prach_resources[gNB_id]->ra_TDD_map_index = 0; - // ue->prach_resources[gNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER = 10; // TBR - // ue->prach_resources[gNB_id]->ra_RNTI = 93; // TBR - } else { + if (ue->mac_enabled == 0){ + ue->prach_resources[gNB_id] = &prach_resources; // TBR double check pointer + ue->prach_resources[gNB_id]->ra_PreambleIndex = preamble_tx; + ue->prach_resources[gNB_id]->ra_TDD_map_index = 0; + ue->prach_resources[gNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER = 10; // TBR + ue->prach_resources[gNB_id]->ra_RNTI = 93; // TBR NR_UE_MAC_INST_t + } else { // ask L2 for RACH transport - /* TBR - // check if these modes are active */ - if ((mode != rx_calib_ue) && (mode != rx_calib_ue_med) && (mode != rx_calib_ue_byp) && (mode != no_L2_connect) ) { - LOG_D(PHY,"Getting PRACH resources. Frame %d Slot %d \n", frame_tx, nr_tti_tx); + if ((runmode != rx_calib_ue) && (runmode != rx_calib_ue_med) && (runmode != rx_calib_ue_byp) && (runmode != no_L2_connect) ) { + LOG_D(PHY, "Getting PRACH resources. Frame %d Slot %d \n", frame_tx, nr_tti_tx); ue->prach_resources[gNB_id] = nr_ue_get_rach(mod_id, ue->CC_id, UE_mode, frame_tx, gNB_id, nr_tti_tx); - // LOG_D(PHY,"Got prach_resources for gNB %d address %p, RRCCommon %p\n", gNB_id, ue->prach_resources[gNB_id], UE_mac_inst[ue->Mod_id].radioResourceConfigCommon); // TBR update this } } - if (ue->prach_resources[gNB_id]!=NULL) { + if (ue->prach_resources[gNB_id] != NULL) { ue->generate_nr_prach = 1; ue->prach_cnt = 0; + pathloss = get_nr_PL(ue, gNB_id); + LOG_I(PHY,"runmode %d\n",runmode); - #ifdef SMBV // TBR + if ((ue->mac_enabled == 1) && (runmode != calib_prach_tx)) { + // todo power control as per 38.213 ch 7.4 + ue->tx_power_dBm[nr_tti_tx] = ue->prach_resources[gNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER + pathloss; + ue->tx_power_dBm[nr_tti_tx] = ue->tx_power_max_dBm; ue->prach_resources[gNB_id]->ra_PreambleIndex = preamble_tx; - #endif + } - #ifdef OAI_EMU // TBR - ue->prach_PreambleIndex=ue->prach_resources[gNB_id]->ra_PreambleIndex; - #endif + LOG_D(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d : Generating PRACH, preamble %d, PL %d, P0_PRACH %d, TARGET_RECEIVED_POWER %d dBm, RA-RNTI %d\n", + ue->Mod_id, + frame_tx, + nr_tti_tx, + ue->prach_resources[gNB_id]->ra_PreambleIndex, + pathloss, + ue->tx_power_dBm[nr_tti_tx], + ue->prach_resources[gNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER, + ue->prach_resources[gNB_id]->ra_RNTI); - // if (abstraction_flag == 0) { // TBR - - LOG_I(PHY,"mode %d\n",mode); - - if ((ue->mac_enabled==1) && (mode != calib_prach_tx)) { - /* TODO TBR - // check if ra_PREAMBLE_RECEIVED_TARGET_POWER is filled id */ - ue->tx_power_dBm[nr_tti_tx] = ue->prach_resources[gNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER + get_nr_PL(ue,gNB_id); - /* TODO TBR - DEBUG ONLY */ - printf("ue->tx_power_dBm[nr_tti_tx] %d ue->prach_resources[gNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER %d get_nr_PL(ue,gNB_id) %d\n", ue->tx_power_dBm[nr_tti_tx], ue->prach_resources[gNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER, get_nr_PL(ue,gNB_id)); - } else { - ue->tx_power_dBm[nr_tti_tx] = ue->tx_power_max_dBm; - ue->prach_resources[gNB_id]->ra_PreambleIndex = preamble_tx; /* TODO TBR this is hardcoded */ - } - - LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d : Generating PRACH, preamble %d,PL %d, P0_PRACH %d, TARGET_RECEIVED_POWER %d dBm, PRACH TDD Resource index %d, RA-RNTI %d\n", ue->Mod_id, - frame_tx, - nr_tti_tx, - ue->prach_resources[gNB_id]->ra_PreambleIndex, - get_nr_PL(ue,gNB_id), - ue->tx_power_dBm[nr_tti_tx], - ue->prach_resources[gNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER, - ue->prach_resources[gNB_id]->ra_TDD_map_index, - ue->prach_resources[gNB_id]->ra_RNTI); - - ue->tx_total_RE[nr_tti_tx] = 96; /* TODO TBR this is hardcoded */ + ue->tx_total_RE[nr_tti_tx] = 96; /* todo TBR double check */ #if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706) - ue->prach_vars[gNB_id]->amp = get_tx_amp(ue->tx_power_dBm[nr_tti_tx], /* TODO TBR get_tx_amp is still valid for NR ? */ - ue->tx_power_max_dBm, - ue->frame_parms.N_RB_UL, - 6); /* TODO TBR why 6 ? */ + ue->prach_vars[gNB_id]->amp = get_tx_amp_prach(ue->tx_power_dBm[nr_tti_tx], + ue->tx_power_max_dBm, + ue->frame_parms.N_RB_UL); #else - ue->prach_vars[gNB_id]->amp = AMP; /* TODO TBR where does this come from ? */ + ue->prach_vars[gNB_id]->amp = AMP; #endif - if ((mode == calib_prach_tx) && (((proc->frame_tx&0xfffe)%100)==0)) /* TODO TBR double check where calibration prach tx is handled */ - LOG_D(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d : PRACH TX power %d dBm, amp %d\n", - ue->Mod_id, + if ((runmode == calib_prach_tx) && (((proc->frame_tx&0xfffe)%100)==0)) + LOG_D(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d : PRACH TX power %d dBm, amp %d\n", ue->Mod_id, proc->frame_rx, proc->nr_tti_tx, ue->tx_power_dBm[nr_tti_tx], @@ -4571,38 +4553,35 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t // start_meas(&ue->tx_prach); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GENERATE_PRACH, VCD_FUNCTION_IN); - // prach_power = generate_nr_prach(ue,gNB_id,nr_tti_tx,frame_tx); - prach_power = generate_nr_prach(ue,0,9,0); //subframe number hardcoded according to the simulator /* TODO TBR this is hardcoded */ + prach_power = generate_nr_prach(ue, gNB_id, nr_tti_tx); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GENERATE_PRACH, VCD_FUNCTION_OUT); - // stop_meas(&ue->tx_prach); - LOG_D(PHY,"[UE %d][RAPROC] PRACH PL %d dB, power %d dBm, digital power %d dB (amp %d)\n", + + LOG_D(PHY,"[UE %d][RAPROC] PRACH PL %d dB, power %d dBm, digital power %d dB (amp %d)\n", ue->Mod_id, get_nr_PL(ue,gNB_id), ue->tx_power_dBm[nr_tti_tx], dB_fixed(prach_power), ue->prach_vars[gNB_id]->amp); - // } else { - // UE_transport_info[ue->Mod_id][ue->CC_id].cntl.prach_flag=1; - // UE_transport_info[ue->Mod_id][ue->CC_id].cntl.prach_id=ue->prach_resources[eNB_id]->ra_PreambleIndex; - // } // commented for compiling as abstraction flag is 0 if (ue->mac_enabled == 1) - // nr_Msg1_transmitted(ue->Mod_id, ue->CC_id, frame_tx, gNB_id); TBR + nr_Msg1_transmitted(ue->Mod_id, ue->CC_id, frame_tx, gNB_id); - - LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d: Generating PRACH (eNB %d) preamble index %d for UL, TX power %d dBm (PL %d dB), l3msg \n", - ue->Mod_id,frame_tx,nr_tti_tx,gNB_id, + LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d: Generating PRACH (gNB %d) preamble index %d for UL, TX power %d dBm (PL %d dB) \n", + ue->Mod_id, + frame_tx, + nr_tti_tx, + gNB_id, ue->prach_resources[gNB_id]->ra_PreambleIndex, - ue->prach_resources[gNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER+get_nr_PL(ue,gNB_id), - get_nr_PL(ue,gNB_id)); + ue->tx_power_dBm[nr_tti_tx], + pathloss); } // if we're calibrating the PRACH kill the pointer to its resources so that the RA protocol doesn't continue - if (mode == calib_prach_tx) + if (runmode == calib_prach_tx) ue->prach_resources[gNB_id]=NULL; - LOG_D(PHY,"[UE %d] frame %d nr_tti_rx %d : generate_nr_prach %d, prach_cnt %d\n", ue->Mod_id,frame_tx,nr_tti_tx,ue->generate_nr_prach,ue->prach_cnt); + LOG_D(PHY,"[UE %d] frame %d nr_tti_rx %d : generate_nr_prach %d, prach_cnt %d\n", ue->Mod_id,frame_tx,nr_tti_tx, ue->generate_nr_prach, ue->prach_cnt); ue->prach_cnt++; diff --git a/openair1/SIMULATION/NR_PHY/prachsim.c b/openair1/SIMULATION/NR_PHY/prachsim.c index fac5d599c8..33ee14424c 100644 --- a/openair1/SIMULATION/NR_PHY/prachsim.c +++ b/openair1/SIMULATION/NR_PHY/prachsim.c @@ -514,8 +514,7 @@ int main(int argc, char **argv) /*tx_lev = generate_nr_prach(UE, 0, //gNB_id, - subframe, - 0); //Nf */ //commented for testing purpose + subframe); */ //commented for testing purpose UE_nr_rxtx_proc_t proc={0}; nr_ue_prach_procedures(UE,&proc,0,0); diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h index bbccb9f707..3c7cc4ac81 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h @@ -96,12 +96,53 @@ typedef struct { uint8_t R:2; // octet 1 [7:6] } __attribute__ ((__packed__)) NR_MAC_SUBHEADER_FIXED; +// BSR MAC CEs +// TS 38.321 ch. 6.1.3.1 +// Short BSR for a specific logical channel group ID +typedef struct { + uint8_t Buffer_size:5; // octet 1 LSB + uint8_t LcgID:3; // octet 1 MSB +} __attribute__ ((__packed__)) NR_BSR_SHORT; + +typedef NR_BSR_SHORT NR_BSR_SHORT_TRUNCATED; + +// Long BSR for all logical channel group ID +typedef struct { + uint8_t Buffer_size7:8; + uint8_t Buffer_size6:8; + uint8_t Buffer_size5:8; + uint8_t Buffer_size4:8; + uint8_t Buffer_size3:8; + uint8_t Buffer_size2:8; + uint8_t Buffer_size1:8; + uint8_t Buffer_size0:8; + uint8_t LcgID0:1; + uint8_t LcgID1:1; + uint8_t LcgID2:1; + uint8_t LcgID3:1; + uint8_t LcgID4:1; + uint8_t LcgID5:1; + uint8_t LcgID6:1; + uint8_t LcgID7:1; +} __attribute__ ((__packed__)) NR_BSR_LONG; + +typedef NR_BSR_LONG NR_BSR_LONG_TRUNCATED; + // 38.321 ch. 6.1.3.4 typedef struct { uint8_t TA_COMMAND:6; // octet 1 [5:0] uint8_t TAGID:2; // octet 1 [7:6] } __attribute__ ((__packed__)) NR_MAC_CE_TA; +// single Entry PHR MAC CE +// TS 38.321 ch. 6.1.3.8 +typedef struct { + uint8_t PH:6; + uint8_t R1:2; + uint8_t PCMAX:6; + uint8_t R2:6; +} __attribute__ ((__packed__)) NR_SINGLE_ENTRY_PHR_MAC_CE; + // /*! \brief CCCH payload */ // TBR // typedef struct { // uint8_t payload[CCCH_PAYLOAD_SIZE_MAX]; @@ -154,6 +195,7 @@ typedef struct { #define UL_SCH_LCID_SRB1 0x01 #define UL_SCH_LCID_SRB2 0x02 #define UL_SCH_LCID_SRB3 0x03 +#define UL_SCH_LCID_DTCH 0x04 #define UL_SCH_LCID_CCCH_MSG3 0x21 #define UL_SCH_LCID_RECOMMENDED_BITRATE_QUERY 0x35 #define UL_SCH_LCID_MULTI_ENTRY_PHR_4_OCT 0x36 diff --git a/openair2/LAYER2/NR_MAC_UE/mac_defs.h b/openair2/LAYER2/NR_MAC_UE/mac_defs.h index ef733020e0..8309afbb69 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_defs.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_defs.h @@ -100,10 +100,12 @@ typedef struct { SFN_C_TYPE type0_pdcch_ss_sfn_c; uint32_t type0_pdcch_ss_n_c; uint32_t type0_pdcch_consecutive_slots; + int rnti_type; /* PDUs */ /// Outgoing CCCH pdu for PHY CCCH_PDU CCCH_pdu; + ULSCH_PDU ulsch_pdu; /* Random Access parameters */ /// state of RA procedure diff --git a/openair2/LAYER2/NR_MAC_UE/mac_proto.h b/openair2/LAYER2/NR_MAC_UE/mac_proto.h index 061b1fa399..3e3704da6c 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_proto.h @@ -152,6 +152,19 @@ void nr_ue_process_mac_pdu(module_id_t module_idP, uint8_t gNB_index, NR_UL_TIME_ALIGNMENT_t *ul_time_alignment); + +unsigned char nr_generate_ulsch_pdu(uint8_t *sdus_payload, + uint8_t *pdu, + uint8_t num_sdus, + uint16_t *sdu_lengths, + uint8_t *sdu_lcids, + uint8_t power_headroom, + uint16_t crnti, + uint16_t truncated_bsr, + uint16_t short_bsr, + uint16_t long_bsr, + unsigned short post_padding); + int8_t nr_ue_process_dlsch(module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_indication_t *dci_ind, void *pduP, uint32_t pdu_len); void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_config,int frame,int slot); diff --git a/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c b/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c index 85c8cf8935..a3a00a84b8 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c @@ -35,7 +35,7 @@ #include "mac_defs.h" #include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" -/* 38.321 subclause 7.3 - return values are in dB */ +/* TS 38.321 subclause 7.3 - return DELTA_PREAMBLE values in dB */ int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id){ NR_UE_MAC_INST_t *nrUE_mac_inst = get_mac_inst(mod_id); @@ -43,13 +43,15 @@ int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id){ AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); - NR_SubcarrierSpacing_t scs = nr_rach_ConfigCommon->msg1_SubcarrierSpacing; uint8_t preambleFormat, prachConfigIndex; lte_frame_type_t frame_type = TDD; // TODO TBR retrieve frame type. Currently hardcoded to TDD. - // was nr_UE_mac_inst[mod_id].tdd_Config nr_frequency_range_e fr = nr_FR1; // TODO TBR retrieve frame type. Currently hardcoded to FR1. int mu; + // SCS configuration from msg1_SubcarrierSpacing and table 4.2-1 in TS 38.211 + + NR_SubcarrierSpacing_t scs = nr_rach_ConfigCommon->msg1_SubcarrierSpacing; + switch (scs){ case NR_SubcarrierSpacing_kHz15: mu = 0; @@ -87,6 +89,8 @@ int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id){ AssertFatal(1 == 0,"Unknown msg1_SubcarrierSpacing %d\n", scs); } + // Preamble formats given by prach_ConfigurationIndex and tables 6.3.3.2-2 and 6.3.3.2-2 in TS 38.211 + prachConfigIndex = nr_rach_ConfigCommon->rach_ConfigGeneric.prach_ConfigurationIndex; preambleFormat = get_nr_prach_fmt(prachConfigIndex,frame_type,fr); @@ -128,28 +132,16 @@ int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id){ return; } +/* TS 38.321 subclause 5.1.3 - RA preamble transmission - ra_PREAMBLE_RECEIVED_TARGET_POWER configuration */ int8_t nr_get_Po_NOMINAL_PUSCH(module_id_t mod_id, uint8_t CC_id){ NR_UE_MAC_INST_t *nr_UE_mac_inst = get_mac_inst(mod_id); NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = nr_UE_mac_inst->nr_rach_ConfigCommon; NR_PRACH_RESOURCES_t *prach_resources = &nr_UE_mac_inst->RA_prach_resources; - //AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); AssertFatal(nr_rach_ConfigCommon != NULL, "[UE %d] CCid %d FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id, CC_id); int8_t receivedTargerPower = nr_rach_ConfigCommon->rach_ConfigGeneric.preambleReceivedTargetPower + nr_get_DELTA_PREAMBLE(mod_id, CC_id) + (nr_UE_mac_inst->RA_PREAMBLE_POWER_RAMPING_COUNTER - 1) * prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP; return receivedTargerPower; - //return (-120 + (nr_rach_ConfigCommon->rach_ConfigGeneric.preambleReceivedTargetPower << 1) + nr_get_DELTA_PREAMBLE(mod_id, CC_id) ); -} - -/*int8_t get_deltaP_rampup(module_id_t module_idP, uint8_t CC_id){ // TBR - - AssertFatal(CC_id == 0, - "Transmission on secondary CCs is not supported yet\n"); - - LOG_D(MAC, "[PUSCH]%d dB\n", - nrUE_mac_inst->RA_PREAMBLE_TRANSMISSION_COUNTER << 1); - return ((int8_t) - (nrUE_mac_inst->RA_PREAMBLE_TRANSMISSION_COUNTER << 1)); -}*/ \ No newline at end of file +} \ No newline at end of file diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c index 501f96b771..b4708a6c81 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -67,7 +67,7 @@ extern UE_MODE_t get_nrUE_mode(uint8_t Mod_id, uint8_t CC_id, uint8_t gNB_id); extern int64_t table_6_3_3_2_2_prachConfig_Index [256][9]; extern int64_t table_6_3_3_2_3_prachConfig_Index [256][9]; -//extern uint8_t nfapi_mode; // TBR +//extern uint8_t nfapi_mode; // This routine implements Section 5.1.2 (UE Random Access Resource Selection) // and Section 5.1.3 (Random Access Preamble Transmission) from 3GPP TS 38.321 @@ -80,45 +80,29 @@ void nr_get_prach_resources(module_id_t mod_id, NR_UE_MAC_INST_t *nr_UE_mac_inst = get_mac_inst(mod_id); NR_PRACH_RESOURCES_t *prach_resources = &nr_UE_mac_inst->RA_prach_resources; - NR_BeamFailureRecoveryConfig_t *beam_failure_recovery_config = &nr_UE_mac_inst->RA_BeamFailureRecoveryConfig; NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = nr_UE_mac_inst->nr_rach_ConfigCommon; + // NR_BeamFailureRecoveryConfig_t *beam_failure_recovery_config = &nr_UE_mac_inst->RA_BeamFailureRecoveryConfig; // todo int messagePowerOffsetGroupB, messageSizeGroupA, PLThreshold, sizeOfRA_PreamblesGroupA, numberOfRA_Preambles, frequencyStart, i, deltaPreamble_Msg3; uint8_t noGroupB = 0, s_id, f_id, ul_carrier_id, msg1_FDM, prach_ConfigIndex, SFN_nbr, Msg3_size; - NR_RSRP_Range_t rsrp_ThresholdSSB; - /* TBR retrieve following params - // currently hardcoded */ - prach_resources->ra_PreambleIndex = 51; - - /*uint8_t Msg3_size = nr_UE_mac_inst->RA_Msg3_size; - uint8_t f_id = 0, num_prach = 0;*/ - - /*AssertFatal(CC_id == 0, - "Transmission on secondary CCs is not supported yet\n"); - AssertFatal(nr_UE_mac_inst->nr_rach_ConfigCommon != NULL, - "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", - mod_id);*/ + // NR_RSRP_Range_t rsrp_ThresholdSSB; // TBR todo /////////////////////////////////////////////////////////// //////////* UE Random Access Resource Selection *////////// /////////////////////////////////////////////////////////// - //numberOfRA_Preambles = (1 + nr_rach_ConfigCommon->preambleInfo.numberOfRA_Preambles) << 2; - numberOfRA_Preambles = nr_rach_ConfigCommon->totalNumberOfRA_Preambles; - rsrp_ThresholdSSB = *nr_rach_ConfigCommon->rsrp_ThresholdSSB; - nr_UE_mac_inst->nr_rach_ConfigCommon->rach_ConfigGeneric.prach_ConfigurationIndex; + // todo: switch initialisation cases + // - RA initiated by beam failure recovery operation (subclause 5.17 TS 38.321) + // -- SSB selection, set prach_resources->ra_PreambleIndex + // - RA initiated by PDCCH: ra_preamble_index provided by PDCCH && ra_PreambleIndex != 0b000000 + // -- TBR coming from dci_pdu_rel15[0].ra_preamble_index + // -- set PREAMBLE_INDEX to ra_preamble_index + // -- select the SSB signalled by PDCCH + // - RA initiated for SI request: + // -- SSB selection, set prach_resources->ra_PreambleIndex - /* TBR switch initialisation cases - - RA initiated by beam failure recovery operation (subclause 5.17 TS 38.321) - - SSB selection, set prach_resources->ra_PreambleIndex - - RA initiated by PDCCH: ra_PreambleIndex provided by PDCCH && ra_PreambleIndex != 0b000000 - - set REAMBLE_INDEX to ra_PreambleIndex - - select the SSB signalled by PDCCH - - RA initiated for SI request: - - SSB selection, set prach_resources->ra_PreambleIndex */ - - // if (rach_ConfigDedicated) { // This is for network controlled Mobility + // if (rach_ConfigDedicated) { // This is for network controlled Mobility // // TBR operation for contention-free RA resources when: // // - available SSB with SS-RSRP above rsrp-ThresholdSSB: SSB selection // // - availalbe CSI-RS with CSI-RSRP above rsrp-ThresholdCSI-RS: CSI-RS selection @@ -126,14 +110,19 @@ void nr_get_prach_resources(module_id_t mod_id, // return; // } - /* Contention-based RA preamble selection: - - TBR selection of SSB with SS-RSRP above rsrp-ThresholdSSB else select any SSB */ + //////////* Contention-based RA preamble selection *////////// + + // todo: selection of SSB with SS-RSRP above rsrp-ThresholdSSB else select any SSB + // rsrp_ThresholdSSB = *nr_rach_ConfigCommon->rsrp_ThresholdSSB; // TBR + + Msg3_size = nr_UE_mac_inst->RA_Msg3_size; + numberOfRA_Preambles = nr_rach_ConfigCommon->totalNumberOfRA_Preambles; + if (!nr_rach_ConfigCommon->groupBconfigured) { noGroupB = 1; } else { - /* RA preambles group B is configured + // RA preambles group B is configured // - Defining the number of RA preambles in RA Preamble Group A for each SSB */ - //sizeOfRA_PreamblesGroupA = (nr_rach_ConfigCommon->preambleInfo.preamblesGroupAConfig->sizeOfRA_PreamblesGroupA + 1) << 2; sizeOfRA_PreamblesGroupA = nr_rach_ConfigCommon->groupBconfigured->numberOfRA_PreamblesGroupA; switch (nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA){ /* - Threshold to determine the groups of RA preambles */ @@ -169,11 +158,11 @@ void nr_get_prach_resources(module_id_t mod_id, break; default: AssertFatal(1 == 0,"Unknown ra_Msg3SizeGroupA %d\n", nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA); - /* TBR cases 10 -15*/ + /* todo cases 10 -15*/ } - /* - Power offset for preamble selection */ - /* TBR: what value to use as default? */ + /* Power offset for preamble selection in dB */ + /* TBR: what value to use as default? Shall it be converted ? */ messagePowerOffsetGroupB = -9999; switch (nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB){ case 0: @@ -204,84 +193,58 @@ void nr_get_prach_resources(module_id_t mod_id, AssertFatal(1 == 0,"Unknown messagePowerOffsetGroupB %d\n", nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB); } - // TBR Msg3-DeltaPreamble should be provided from higher layers, otherwise is 0 + // todo Msg3-DeltaPreamble should be provided from higher layers, otherwise is 0 nr_UE_mac_inst->deltaPreamble_Msg3 = 0; deltaPreamble_Msg3 = nr_UE_mac_inst->deltaPreamble_Msg3; } PLThreshold = prach_resources->RA_PCMAX - nr_rach_ConfigCommon->rach_ConfigGeneric.preambleReceivedTargetPower - deltaPreamble_Msg3 - messagePowerOffsetGroupB; - // PLThreshold = prach_resources->RA_PCMAX - nr_get_DELTA_PREAMBLE(mod_id, CC_id) - nr_get_Po_NOMINAL_PUSCH(mod_id, CC_id) - messagePowerOffsetGroupB; - // TBR Note Pcmax is set to 0 here, we have to fix this /* Msg3 has not been transmitted yet */ if (first_Msg3 == 1) { if (noGroupB == 1) { // use Group A preamble prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles; - prach_resources->ra_RACH_MaskIndex = 0; nr_UE_mac_inst->RA_usedGroupA = 1; } else if ((Msg3_size < messageSizeGroupA) && (get_PL(mod_id, 0, gNB_id) > PLThreshold)) { - // TBR update get_PL to NR - // TBR add condition for initiation by CCCH // Group B is configured and RA preamble Group A is used + // - todo TBR update get_PL to NR get_nr_PL (needs PHY_VARS_NR_UE) + // - todo add condition on CCCH_sdu_size for initiation by CCCH prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; - prach_resources->ra_RACH_MaskIndex = 0; nr_UE_mac_inst->RA_usedGroupA = 1; } else { // Group B preamble is configured and used // the first sizeOfRA_PreamblesGroupA RA preambles belong to RA Preambles Group A // the remaining belong to RA Preambles Group B - prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA - + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); - prach_resources->ra_RACH_MaskIndex = 0; + prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); nr_UE_mac_inst->RA_usedGroupA = 0; } - - //TBR check why this is here - // prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = nr_get_Po_NOMINAL_PUSCH(mod_id, CC_id); - } else { - // Msg3 is being retransmitted + } else { // Msg3 is being retransmitted if (nr_UE_mac_inst->RA_usedGroupA == 1) { if (nr_rach_ConfigCommon->groupBconfigured){ prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; } else { prach_resources->ra_PreambleIndex = (taus()) & 0x3f; // TBR check this - prach_resources->ra_RACH_MaskIndex = 0; } } else { - // TBR FIXME nr_rach_ConfigCommon->preambleInfo.preamblesGroupAConfig may be zero - prach_resources->ra_PreambleIndex = - sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); - prach_resources->ra_RACH_MaskIndex = 0; + prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); } } - // TBR determine next available PRACH occasion - // - if RA initiated for SI request and ra_AssociationPeriodIndex and si-RequestPeriod are configured - // - else if SSB is selected above - // - else if CSI-RS is selected above - - /* // choose random PRACH resource in TDD - if (nr_UE_mac_inst->tdd_Config) { - num_prach = get_num_prach_tdd(mod_id); - - if ((num_prach > 0) && (num_prach < 6)) - prach_resources->ra_TDD_map_index = (taus() % num_prach); - - f_id = get_fid_prach_tdd(mod_id, nr_UE_mac_inst [mod_id].RA_prach_resources->ra_TDD_map_index); - }*/ + // todo determine next available PRACH occasion + // - if RA initiated for SI request and ra_AssociationPeriodIndex and si-RequestPeriod are configured + // - else if SSB is selected above + // - else if CSI-RS is selected above ///////////////////////////////////////////////////////////////////////////// //////////* Random Access Preamble Transmission (5.1.3 TS 38.321) *////////// ///////////////////////////////////////////////////////////////////////////// - // TBR condition on notification of suspending power ramping counter from lower layer (5.1.3 TS 38.321) - // TBR check if SSB or CSI-RS have not changed since the selection in the last RA Preamble tranmission - if (nr_UE_mac_inst->RA_PREAMBLE_TRANSMISSION_COUNTER >1) + // todo condition on notification of suspending power ramping counter from lower layer (5.1.3 TS 38.321) // TBR + // todo check if SSB or CSI-RS have not changed since the selection in the last RA Preamble tranmission + if (nr_UE_mac_inst->RA_PREAMBLE_TRANSMISSION_COUNTER > 1) nr_UE_mac_inst->RA_PREAMBLE_TRANSMISSION_COUNTER++; - //prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = nr_rach_ConfigCommon->rach_ConfigGeneric.preambleReceivedTargetPower + - // nr_get_DELTA_PREAMBLE(mod_id, CC_id) + (nr_UE_mac_inst->RA_PREAMBLE_POWER_RAMPING_COUNTER - 1) * prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP; // TBR prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = nr_get_Po_NOMINAL_PUSCH(mod_id, CC_id); /* RA-RNTI computation (associated to PRACH occasion in which the RA Preamble is transmitted) @@ -289,11 +252,7 @@ void nr_get_prach_resources(module_id_t mod_id, // 2) getting star_symb, SFN_nbr from table 6.3.3.2-3 (TDD and FR1 scenario) // 3) TBR extend this (e.g. f_id selection, ul_carrier_id are hardcoded) */ - ul_carrier_id = 0; // UL carrier used for RA preamble transmission, hardcoded for NUL carrier - f_id = 0; - //frequencyStart = nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FrequencyStart; - - switch (nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FDM){ + switch (nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FDM){ // todo this is not used case 0: msg1_FDM = 1; break; @@ -312,36 +271,41 @@ void nr_get_prach_resources(module_id_t mod_id, prach_ConfigIndex = nr_rach_ConfigCommon->rach_ConfigGeneric.prach_ConfigurationIndex; - // TBR this is for TDD FR1 only - SFN_nbr = table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][4]; - s_id = table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][5]; // starting symbol of the PRACH occasion + // ra_RNTI computation + // - todo: this is for TDD FR1 only + // - ul_carrier_id: UL carrier used for RA preamble transmission, hardcoded for NUL carrier + // - f_id: index of the PRACH occasion in the frequency domain + // - s_id is starting symbol of the PRACH occasion [0...14] + // - t_id is the first slot of the PRACH occasion in a system frame [0...80] - // pick the first slot of the PRACH occasion in a system frame (0 <= t_id <= 80) + ul_carrier_id = 0; // todo SUL + f_id = nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FrequencyStart; + SFN_nbr = table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][4]; + s_id = table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][5]; + + // Pick the first slot of the PRACH occasion in a system frame for (i = 0; i < 10; i++){ if (((SFN_nbr & (1 << i)) >> i) == 1){ t_id = 2*i; break; } } - prach_resources->ra_RNTI = 1 + s_id + 14 * t_id + 1120 * f_id + 8960 * ul_carrier_id; + + LOG_D(MAC, "Computed ra_RNTI is %d", prach_resources->ra_RNTI); } void nr_Msg1_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id){ - #if 0 //TBR + + NR_UE_MAC_INST_t *nr_UE_mac_inst = get_mac_inst(mod_id); + AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); - - // start contention resolution timer - nr_UE_mac_inst->RA_attempt_number++; - if (opt_enabled) { - trace_pdu(DIRECTION_UPLINK, NULL, 0, mod_id, WS_NO_RNTI, nr_UE_mac_inst->RA_prach_resources->ra_PreambleIndex, nr_UE_mac_inst->txFrame, nr_UE_mac_inst->txSubframe, 0, nr_UE_mac_inst->RA_attempt_number); - LOG_D(OPT, "[UE %d][RAPROC] TX MSG1 Frame %d trace pdu for rnti %x with size %d\n", mod_id, frameP, 1, nr_UE_mac_inst->RA_Msg3_size); - } - #endif + // Start contention resolution timer + nr_UE_mac_inst->RA_attempt_number++; // todo this is not used + } - void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id){ #if 0 // TBR AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); @@ -352,10 +316,6 @@ void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint nr_UE_mac_inst->RA_contention_resolution_cnt = 0; nr_UE_mac_inst->RA_contention_resolution_timer_active = 1; - if (opt_enabled) { - trace_pdu(DIRECTION_UPLINK, &nr_UE_mac_inst->CCCH_pdu.payload[0], nr_UE_mac_inst->RA_Msg3_size, mod_id, WS_C_RNTI, nr_UE_mac_inst->crnti, nr_UE_mac_inst->txFrame, nr_UE_mac_inst->txSubframe, 0, 0); - LOG_D(OPT, "[UE %d][RAPROC] MSG3 Frame %d trace pdu Preamble %d with size %d\n", mod_id, frameP, nr_UE_mac_inst->crnti /*nr_UE_mac_inst->RA_prach_resources->ra_PreambleIndex */, nr_UE_mac_inst->RA_Msg3_size); - } #endif } @@ -374,44 +334,35 @@ NR_PRACH_RESOURCES_t *nr_ue_get_rach(module_id_t mod_id, int nr_tti_tx){ NR_UE_MAC_INST_t *nr_UE_mac_inst = get_mac_inst(mod_id); - uint8_t size_sdu = 0, Nb_tb = 1, lcid = CCCH, dcch_header_len = 0, ulsch_buff[MAX_ULSCH_PAYLOAD_BYTES]; - // UE_MODE_t UE_mode; - uint16_t Size16, sdu_lengths; + uint8_t lcid = CCCH, dcch_header_len = 0, mac_sdus[MAX_NR_ULSCH_PAYLOAD_BYTES], * payload; + uint16_t size_sdu = 0; + unsigned short post_padding; NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = (struct NR_RACH_ConfigCommon_t *) NULL; NR_PRACH_RESOURCES_t *prach_resources = &nr_UE_mac_inst->RA_prach_resources; int32_t frame_diff = 0; - // Modification for phy_stub_ue operation // TBR - // if(nfapi_mode == 3) { // phy_stub_ue mode - // UE_mode = nr_UE_mac_inst->UE_mode[CC_id]; - // LOG_D(MAC, "ue_get_rach, UE_mode: %d", UE_mode); - // } - // else // Full stack mode - // UE_mode = get_nrUE_mode(mod_id, CC_id, gNB_id); // TBR + uint8_t sdu_lcids[NB_RB_MAX] = {0}; // TBR + uint16_t sdu_lengths[NB_RB_MAX] = {0}; // TBR + int TBS_bytes = 848, header_length_total, num_sdus, offset; // TBR AssertFatal(CC_id == 0,"Transmission on secondary CCs is not supported yet\n"); if (UE_mode == PRACH) { - LOG_D(MAC, "ue_get_rach, RA_active value: %d", nr_UE_mac_inst->RA_active); - if (nr_UE_mac_inst->nr_rach_ConfigCommon) { - nr_rach_ConfigCommon = nr_UE_mac_inst->nr_rach_ConfigCommon; - printf("nr_rach_ConfigCommon from MAC nr_UE_mac_inst\n"); /* TBR DEBUG only */ - } else return NULL; - /* TBR moved below - size_sdu = mac_rrc_nr_data_req(mod_id, - CC_id, - frame, - CCCH, - 1, - &nr_UE_mac_inst->CCCH_pdu.payload[sizeof(SCH_SUBHEADER_SHORT) + 1], gNB_id, 0);*/ + LOG_D(MAC, "nr_ue_get_rach, RA_active value: %d", nr_UE_mac_inst->RA_active); + + AssertFatal(nr_UE_mac_inst->nr_rach_ConfigCommon != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); + + if (nr_UE_mac_inst->nr_rach_ConfigCommon) { // TBR check the condition + nr_rach_ConfigCommon = nr_UE_mac_inst->nr_rach_ConfigCommon; + } else return NULL; if (nr_UE_mac_inst->RA_active == 0) { /* RA not active - checking if RRC is ready to initiate the RA procedure */ - LOG_I(MAC, "RA not active\n"); + LOG_I(MAC, "RA not active. Starting RA preamble initialization.\n"); - /* TBR flush Msg3 Buffer + /* TBR flush Msg3 Buffer this was done like this but at PHY level for(i=0; iRA_PREAMBLE_TRANSMISSION_COUNTER = 1; - nr_UE_mac_inst->RA_PREAMBLE_POWER_RAMPING_COUNTER = 1; - prach_resources->RA_PREAMBLE_BACKOFF = 0; - - /* TBR: if carrier to use is explicitly signalled do RA CARRIER SELECTION (SUL, NUL) this will set PCMAX */ - prach_resources->RA_PCMAX = 0; - - /* TBR: BWP operation (subclause 5.15 TS 38.321) */ + nr_UE_mac_inst->RA_RAPID_found = 0; /* Set RA_PREAMBLE_POWER_RAMPING_STEP */ switch (nr_rach_ConfigCommon->rach_ConfigGeneric.powerRampingStep){ // in dB @@ -445,187 +389,113 @@ NR_PRACH_RESOURCES_t *nr_ue_get_rach(module_id_t mod_id, break; } + prach_resources->RA_PREAMBLE_BACKOFF = 0; prach_resources->RA_SCALING_FACTOR_BI = 1; + prach_resources->RA_PCMAX = 0; // currently hardcoded to 0 - /* TBR: initialization by beam failure recovery */ + // todo: + // - check if carrier to use is explicitly signalled then do (1) RA CARRIER SELECTION (SUL, NUL) (2) set PCMAX + // - BWP operation (subclause 5.15 TS 38.321) + // - handle initialization by beam failure recovery + // - handle initialization by handover - /* TBR: initialization by handover */ + if (!IS_SOFTMODEM_NOS1){ + // todo mac_rrc_nr_data_req_ue + payload = &nr_UE_mac_inst->CCCH_pdu.payload; + size_sdu = (uint16_t) mac_rrc_nr_data_req_ue(mod_id, + CC_id, + frame, + CCCH, + payload[sizeof(NR_MAC_SUBHEADER_SHORT) + 1]); - /* size_sdu = mac_rrc_nr_data_req(mod_id, - CC_id, - frame, - CCCH, - Nb_tb, - &nr_UE_mac_inst->CCCH_pdu.payload[sizeof(NR_MAC_SUBHEADER_SHORT) + 1]); */ - // TBR mac_rrc_nr_data_req is a GNB func - // use nr_mac_rrc_data_ind_ue instead + LOG_D(MAC,"[UE %d] Frame %d: Requested RRCConnectionRequest, got %d bytes\n", mod_id,frame, size_sdu); - // TBR fix CCCH PDU payload - Size16 = (uint16_t) size_sdu; + // todo: else triggers a transmission on DCCH using PRACH (during handover, or sending SR for example) - /* TBR FIX THIS + } else { + // fill ulsch_buffer with random data + payload = (uint8_t *)nr_UE_mac_inst->ulsch_pdu.payload[0]; + for (int i = 0; i < TBS_bytes; i++){ + mac_sdus[i] = (unsigned char) (lrand48()&0xff); + } + //Sending SDUs with size 1 + //Initialize elements of sdu_lcids and sdu_lengths + sdu_lcids[0] = UL_SCH_LCID_DTCH; + sdu_lengths[0] = TBS_bytes - 3; + header_length_total += 2 + (sdu_lengths[0] >= 128); + size_sdu += sdu_lengths[0]; + num_sdus +=1; + } - // LOG_D(MAC,"[UE %d] Frame %d: Requested RRCConnectionRequest, got %d bytes\n",mod_id,frame,size_sdu); - LOG_I(RRC, - "[MSC_MSG][FRAME %05d][RRC_UE][MOD %02d][][--- MAC_DATA_REQ (RRCConnectionRequest gNB %d) --->][MAC_UE][MOD %02d][]\n", - frame, mod_id, gNB_id, mod_id); - LOG_I(MAC, - "[UE %d] Frame %d: Requested RRCConnectionRequest, got %d bytes\n", - mod_id, frame, size_sdu); - - nr_UE_mac_inst->RA_RAPID_found = 0; - // TBR which frame and slot ? + // TBR which frame and slot ? nr_UE_mac_inst->RA_tx_frame = frame; nr_UE_mac_inst->RA_tx_subframe = nr_tti_tx; nr_UE_mac_inst->RA_backoff_frame = frame; - nr_UE_mac_inst->RA_backoff_subframe = nr_tti_tx;*/ + nr_UE_mac_inst->RA_backoff_subframe = nr_tti_tx; - /*if (size_sdu > 0) { */ + if (size_sdu > 0) { // TBR size_sdu + MAC_Header_len + mac_ce_len /* TBR initialisation by RRC // PDU from CCCH */ LOG_I(MAC, "[UE %d] Frame %d: Initialisation Random Access Procedure\n", mod_id, frame); - // TBR - /*nr_UE_mac_inst->RA_Msg3_size = size_sdu + sizeof(SCH_SUBHEADER_SHORT) + sizeof(SCH_SUBHEADER_SHORT); + nr_UE_mac_inst->RA_PREAMBLE_TRANSMISSION_COUNTER = 1; + nr_UE_mac_inst->RA_PREAMBLE_POWER_RAMPING_COUNTER = 1; + nr_UE_mac_inst->RA_Msg3_size = size_sdu + sizeof(NR_MAC_SUBHEADER_SHORT) + sizeof(NR_MAC_SUBHEADER_SHORT); // TBR size_sdu + MAC_Header_len + mac_ce_len nr_UE_mac_inst->RA_prachMaskIndex = 0; - prach_resources->Msg3 = nr_UE_mac_inst->CCCH_pdu.payload; - nr_UE_mac_inst->RA_backoff_cnt = 0; // add the backoff condition here if we have it from a previous RA reponse which failed (i.e. backoff indicator) + // TBR todo: add the backoff condition here if we have it from a previous RA reponse which failed (i.e. backoff indicator) + nr_UE_mac_inst->RA_backoff_cnt = 0; + nr_UE_mac_inst->RA_active = 1; + prach_resources->Msg3 = payload; - AssertFatal(nr_rach_ConfigCommon != NULL, - "[UE %d] FATAL Frame %d: nr_rach_ConfigCommon is NULL !!!\n", - mod_id, frame); - nr_UE_mac_inst->RA_window_cnt = 2 + nr_rach_ConfigCommon->ra_SupervisionInfo.ra_ResponseWindowSize; - - if (nr_UE_mac_inst->RA_window_cnt == 9) { - nr_UE_mac_inst->RA_window_cnt = 10; // Note: 9 subframe window doesn't exist, after 8 is 10! - }*/ + // TBR todo double check window count + // nr_UE_mac_inst->RA_window_cnt = 2 + nr_rach_ConfigCommon->ra_SupervisionInfo.ra_ResponseWindowSize; + // if (nr_UE_mac_inst->RA_window_cnt == 9) { + // nr_UE_mac_inst->RA_window_cnt = 10; // Note: 9 subframe window doesn't exist, after 8 is 10! + // } // Fill in preamble and PRACH resources nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 1, NULL); - /*generate_ulsch_header((uint8_t *) & nr_UE_mac_inst->CCCH_pdu.payload[0], // mac header - 1, // num sdus - 0, // short pading - &Size16, // sdu length - &lcid, // sdu lcid - NULL, // power headroom - NULL, // crnti - NULL, // truncated bsr - NULL, // short bsr - NULL, // long_bsr - 1); //post_padding*/ - return (&nr_UE_mac_inst->RA_prach_resources); + offset = nr_generate_ulsch_pdu((uint8_t *) mac_sdus, // sdus buffer + (uint8_t *) payload, // logical channel payload + num_sdus, // num sdus + sdu_lengths, // sdu length + sdu_lcids, // sdu lcid + 0, // power headroom + 0, // crnti + 0, // truncated bsr + 0, // short bsr + 0, // long_bsr + 1); // post_padding - /*} else if (nr_UE_mac_inst->scheduling_info. - BSR_bytes[nr_UE_mac_inst->scheduling_info.LCGID[DCCH]] > 0) { - // This is for triggering a transmission on DCCH using PRACH (during handover, - // or sending SR for example) + // Padding: fill remainder of DLSCH with 0 + if (post_padding > 0){ + for (int j = 0; j < (TBS_bytes - offset); j++) + payload[offset + j] = 0; // mac_pdu[offset + j] = 0; + } - dcch_header_len = 2 + 2; /// SHORT Subheader + C-RNTI control element - LOG_USEDINLOG_VAR(mac_rlc_status_resp_t,rlc_status)=mac_rlc_status_ind(mod_id, - nr_UE_mac_inst->crnti, - gNB_id, frame, nr_tti_tx, - ENB_FLAG_NO, MBMS_FLAG_NO, DCCH, 6 - #if (RRC_VERSION >= MAKE_VERSION(14, 0, 0)) - ,0, 0 - #endif - ); - - if (nr_UE_mac_inst->crnti_before_ho) - LOG_D(MAC, - "[UE %d] Frame %d : UL-DCCH -> ULSCH, HO RRCConnectionReconfigurationComplete (%x, %x), RRC message has %d bytes to send throug PRACH (mac header len %d)\n", - mod_id, frame, - nr_UE_mac_inst->crnti, - nr_UE_mac_inst->crnti_before_ho, - rlc_status.bytes_in_buffer, dcch_header_len); - else - LOG_D(MAC, - "[UE %d] Frame %d : UL-DCCH -> ULSCH, RRC message has %d bytes to send through PRACH(mac header len %d)\n", - mod_id, frame, rlc_status.bytes_in_buffer, - dcch_header_len); - - sdu_lengths = mac_rlc_data_req(mod_id, nr_UE_mac_inst->crnti, - gNB_id, frame, ENB_FLAG_NO, MBMS_FLAG_NO, DCCH, 6, //not used - (char *) &ulsch_buff[0] - #if (RRC_VERSION >= MAKE_VERSION(14, 0, 0)) - ,0,0 - #endif - ); - - if(sdu_lengths > 0) - LOG_D(MAC, "[UE %d] TX Got %d bytes for DCCH\n", mod_id, sdu_lengths); - else - LOG_E(MAC, "[UE %d] TX DCCH error\n", mod_id ); - - update_bsr(mod_id, frame, nr_tti_tx, gNB_id); - nr_UE_mac_inst->scheduling_info.BSR[nr_UE_mac_inst-> - scheduling_info.LCGID[DCCH]] = locate_BsrIndexByBufferSize(BSR_TABLE, BSR_TABLE_SIZE, - nr_UE_mac_inst - [mod_id].scheduling_info.BSR_bytes - [nr_UE_mac_inst - [mod_id].scheduling_info.LCGID - [DCCH]]); - - //TBR: fill BSR infos in UL TBS - - //header_len +=2; - nr_UE_mac_inst->RA_active = 1; - nr_UE_mac_inst->RA_PREAMBLE_TRANSMISSION_COUNTER = - 1; - nr_UE_mac_inst->RA_Msg3_size = - size_sdu + dcch_header_len; - nr_UE_mac_inst->RA_prachMaskIndex = 0; - prach_resources->Msg3 = - ulsch_buff; - nr_UE_mac_inst->RA_backoff_cnt = 0; // add the backoff condition here if we have it from a previous RA reponse which failed (i.e. backoff indicator) - - AssertFatal(nr_rach_ConfigCommon != NULL, - "[UE %d] FATAL Frame %d: nr_rach_ConfigCommon is NULL !!!\n", - mod_id, frame); - nr_UE_mac_inst->RA_window_cnt = - 2 + - nr_rach_ConfigCommon->ra_SupervisionInfo. - ra_ResponseWindowSize; - - if (nr_UE_mac_inst->RA_window_cnt == 9) { - nr_UE_mac_inst->RA_window_cnt = 10; // Note: 9 subframe window doesn't exist, after 8 is 10! - } - - - nr_UE_mac_inst->RA_tx_frame = frame; - nr_UE_mac_inst->RA_tx_subframe = nr_tti_tx; - nr_UE_mac_inst->RA_backoff_frame = frame; - nr_UE_mac_inst->RA_backoff_subframe = nr_tti_tx; - // Fill in preamble and PRACH resource - nr_get_prach_resources(mod_id, CC_id, gNB_id, - nr_tti_tx, 1, NULL); - generate_ulsch_header((uint8_t *) ulsch_buff, // mac header - 1, // num sdus - 0, // short pading - &Size16, // sdu length - &lcid, // sdu lcid - NULL, // power headroom - &nr_UE_mac_inst->crnti, // crnti - NULL, // truncated bsr - NULL, // short bsr - NULL, // long_bsr - 0); //post_padding - - return (&nr_UE_mac_inst->RA_prach_resources); - }*/ + return (prach_resources); + } } else { // RACH is active //////////////////////////////////////////////////////////////// /////* Random Access Response reception (5.1.4 TS 38.321) *///// //////////////////////////////////////////////////////////////// - /// Handling ra_responseWindow, RA_PREAMBLE_TRANSMISSION_COUNTER - /// and RA_backoff_cnt + // Handling ra_responseWindow, RA_PREAMBLE_TRANSMISSION_COUNTER + // and RA_backoff_cnt + // todo: + // - handle beam failure recovery request + // - handle DL assignment on PDCCH for RA-RNTI LOG_D(MAC, "[MAC][UE %d][RAPROC] frame %d, subframe %d: RA Active, window cnt %d (RA_tx_frame %d, RA_tx_subframe %d)\n", mod_id, frame, nr_tti_tx, nr_UE_mac_inst->RA_window_cnt, nr_UE_mac_inst->RA_tx_frame, nr_UE_mac_inst->RA_tx_subframe); - // - TBR check + if (nr_UE_mac_inst->rnti_type = NR_RNTI_RA){ // add condition on BI + // TBR todo + } else { + prach_resources->RA_PREAMBLE_BACKOFF = 0; + } // compute backoff parameters if (nr_UE_mac_inst->RA_backoff_cnt > 0){ frame_diff = (sframe_t) frame - nr_UE_mac_inst->RA_backoff_frame; diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c index 677a27fb3d..d595116979 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c @@ -114,7 +114,7 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_ if (mac->ra_state == WAIT_RAR) { // check for RAR rel15 = &dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15; - rel15->rnti = 2;//get_RA_RNTI(mac,frame,slot); + rel15->rnti = 2;//get_RA_RNTI(mac,frame,slot); // TBR dl_config->number_pdus = dl_config->number_pdus + 1; } else if (mac->ra_state == WAIT_CONTENTION_RESOLUTION) { diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index e192bfb232..7c99ed36a6 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -2752,7 +2752,9 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, LOG_D(MAC,"tb_scaling %d (2 bits)=> %d (0x%lx)\n",dci_pdu_rel15->tb_scaling,dci_size-pos,*dci_pdu); #endif break; - + + mac->rnti_type = rnti_type; + case NR_RNTI_C: // indicating a DL DCI format 1bit @@ -3280,3 +3282,169 @@ void nr_ue_process_mac_pdu(module_id_t module_idP, AssertFatal(pdu_len >= 0, "[MAC] nr_ue_process_mac_pdu, residual mac pdu length < 0!\n"); } } + +//////////////////////////////////////////////////////// +/////* ULSCH MAC PDU generation (6.1.2 TS 38.321) *///// +//////////////////////////////////////////////////////// + +unsigned char nr_generate_ulsch_pdu(uint8_t *sdus_payload, + uint8_t *pdu, + uint8_t num_sdus, + uint16_t *sdu_lengths, + uint8_t *sdu_lcids, + uint8_t power_headroom, + uint16_t crnti, + uint16_t truncated_bsr, + uint16_t short_bsr, + uint16_t long_bsr, + unsigned short post_padding) { + + NR_MAC_SUBHEADER_FIXED *mac_pdu_ptr = (NR_MAC_SUBHEADER_FIXED *) pdu; + unsigned char first_element = 0, last_size = 0, i, mac_header_control_elements[16], *ce_ptr, bsr = 0; + int mac_ce_size, offset; + + LOG_D(MAC, "[UE] Generating ULSCH PDU : num_sdus %d\n", num_sdus); + + #ifdef DEBUG_HEADER_PARSING + + for (i = 0; i < num_sdus; i++) + LOG_D(MAC, "[UE] MAC subPDU %d (lcid %d length %d bytes \n", i, sdu_lcids[i], sdu_lengths[i]); + + #endif + + // Generating UL MAC subPDUs including MAC SDU and subheader + + for (i = 0; i < num_sdus; i++) { + LOG_D(MAC, "[UE] Generating UL MAC subPDUs for SDU with lenght %d ( num_sdus %d )\n", sdu_lengths[i], num_sdus); + + if (sdu_lcids[i] != UL_SCH_LCID_CCCH){ + if (sdu_lengths[i] < 128) { + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = sdu_lcids[i]; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = (unsigned char) sdu_lengths[i]; + last_size = 2; + } else { + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->F = 1; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->LCID = sdu_lcids[i]; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L1 = ((unsigned short) sdu_lengths[i] >> 8) & 0x7f; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L2 = (unsigned short) sdu_lengths[i] & 0xff; + last_size = 3; + } + } else { // UL CCCH SDU + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = sdu_lcids[i]; + } + + mac_pdu_ptr += last_size; + + // cycle through SDUs, compute each relevant and place ulsch_buffer in + memcpy((void *) mac_pdu_ptr, (void *) sdus_payload, sdu_lengths[i]); + sdus_payload += sdu_lengths[i]; + mac_pdu_ptr += sdu_lengths[i]; + } + + // Generating UL MAC subPDUs including MAC CEs (MAC CE and subheader) + + ce_ptr = &mac_header_control_elements[0]; + + if (power_headroom) { + // MAC CE fixed subheader + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = UL_SCH_LCID_SINGLE_ENTRY_PHR; + mac_pdu_ptr++; + + // PHR MAC CE (1 octet) + ((NR_SINGLE_ENTRY_PHR_MAC_CE *) ce_ptr)->PH = power_headroom; + ((NR_SINGLE_ENTRY_PHR_MAC_CE *) ce_ptr)->R1 = 0; + ((NR_SINGLE_ENTRY_PHR_MAC_CE *) ce_ptr)->PCMAX = 0; // todo + ((NR_SINGLE_ENTRY_PHR_MAC_CE *) ce_ptr)->R2 = 0; + + mac_ce_size = sizeof(NR_SINGLE_ENTRY_PHR_MAC_CE); + + // Copying bytes for PHR MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); + ce_ptr += mac_ce_size; + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + + if (crnti) { + // MAC CE fixed subheader + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = CRNTI; + mac_pdu_ptr++; + + // C-RNTI MAC CE (2 octets) + * (uint16_t *) ce_ptr = crnti; + mac_ce_size = sizeof(uint16_t); + + // Copying bytes for CRNTI MAC CE to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); + ce_ptr += mac_ce_size; + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + + if (truncated_bsr) { + // MAC CE fixed subheader + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = UL_SCH_LCID_S_TRUNCATED_BSR; + mac_pdu_ptr++; + + // Short truncated BSR MAC CE (1 octet) + ((NR_BSR_SHORT_TRUNCATED *) ce_ptr)-> Buffer_size = truncated_bsr; + ((NR_BSR_SHORT_TRUNCATED *) ce_ptr)-> LcgID = 0; // todo + mac_ce_size = sizeof(NR_BSR_SHORT_TRUNCATED); + + bsr = 1 ; + } else if (short_bsr) { + // MAC CE fixed subheader + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = UL_SCH_LCID_S_BSR; + mac_pdu_ptr++; + + // Short truncated BSR MAC CE (1 octet) + ((NR_BSR_SHORT *) ce_ptr)->Buffer_size = short_bsr; + ((NR_BSR_SHORT *) ce_ptr)->LcgID = 0; // todo + mac_ce_size = sizeof(NR_BSR_SHORT); + + bsr = 1 ; + } else if (long_bsr) { + // MAC CE variable subheader + // todo ch 6.1.3.1. TS 38.321 + // ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; + // ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; + // ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = UL_SCH_LCID_L_BSR; + // ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = 0; + // last_size = 2; + // mac_pdu_ptr += last_size; + + // Short truncated BSR MAC CE (1 octet) + // ((NR_BSR_LONG *) ce_ptr)->Buffer_size0 = short_bsr; + // ((NR_BSR_LONG *) ce_ptr)->LCGID0 = 0; + // mac_ce_size = sizeof(NR_BSR_LONG); // size is variable + } + + if (bsr){ + // Copying bytes for BSR MAC CE to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); + ce_ptr += mac_ce_size; + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + + // Compute final offset for padding + if (post_padding > 0) { + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = UL_SCH_LCID_PADDING; + mac_pdu_ptr++; + } else { + // no MAC subPDU with padding + } + + // compute final offset + offset = ((unsigned char *) mac_pdu_ptr - pdu); + + //printf("Offset %d \n", ((unsigned char *) mac_pdu_ptr - mac_pdu)); + + return offset; +} \ No newline at end of file diff --git a/openair2/RRC/NR_UE/L2_interface_ue.c b/openair2/RRC/NR_UE/L2_interface_ue.c index cb8ded1971..08976522b0 100644 --- a/openair2/RRC/NR_UE/L2_interface_ue.c +++ b/openair2/RRC/NR_UE/L2_interface_ue.c @@ -56,4 +56,15 @@ nr_mac_rrc_data_ind_ue( return(0); +} + +int8_t mac_rrc_nr_data_req_ue(const module_id_t Mod_idP, + const int CC_id, + const frame_t frameP, + const rb_id_t Srb_id, + uint8_t *const buffer_pP ){ + + // todo + + return 0; } \ No newline at end of file diff --git a/openair2/RRC/NR_UE/rrc_proto.h b/openair2/RRC/NR_UE/rrc_proto.h index 6e0d0a10de..7bc7e4b90c 100644 --- a/openair2/RRC/NR_UE/rrc_proto.h +++ b/openair2/RRC/NR_UE/rrc_proto.h @@ -102,6 +102,18 @@ int8_t nr_rrc_ue_decode_NR_DL_DCCH_Message(const module_id_t module_id, const ui \param pdu_len data length of pdu*/ int8_t nr_mac_rrc_data_ind_ue(const module_id_t module_id, const int CC_id, const uint8_t gNB_index, const channel_t channel, const uint8_t* pduP, const sdu_size_t pdu_len); +/**\brief + \param module_id module id + \param CC_id component carrier id + \param frame_t frameP + \param rb_id_t SRB id + \param buffer_pP pointer to buffer*/ +int8_t mac_rrc_nr_data_req_ue(const module_id_t Mod_idP, + const int CC_id, + const frame_t frameP, + const rb_id_t Srb_id, + uint8_t *const buffer_pP); + /** @}*/ #endif From 903a1ec6a8661500d283a0fc87ed26bd7630243b Mon Sep 17 00:00:00 2001 From: cig Date: Fri, 7 Feb 2020 19:16:34 +0100 Subject: [PATCH 017/553] Cleanup code, removed gNB headers in UE files --- executables/nr-uesoftmodem.h | 1 - .../PHY/NR_UE_TRANSPORT/nr_transport_ue.h | 2 -- openair1/PHY/TOOLS/nr_phy_scope.h | 1 - openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 21 +------------------ .../LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c | 13 ++++++------ openair2/RRC/NR/L2_nr_interface.c | 2 +- 6 files changed, 9 insertions(+), 31 deletions(-) diff --git a/executables/nr-uesoftmodem.h b/executables/nr-uesoftmodem.h index 3438f31373..77f55fa75b 100644 --- a/executables/nr-uesoftmodem.h +++ b/executables/nr-uesoftmodem.h @@ -4,7 +4,6 @@ #include #include "PHY/defs_nr_UE.h" #include "SIMULATION/ETH_TRANSPORT/proto.h" -#include "NR_MAC_gNB/mac_proto.h" /***************************************************************************************************************************************/ /* command line options definitions, CMDLINE_XXXX_DESC macros are used to initialize paramdef_t arrays which are then used as argument diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h index ca87ed1fae..f976da0a3a 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h @@ -42,8 +42,6 @@ #include "UTIL/LISTS/list.h" #endif -#include "LAYER2/NR_MAC_gNB/mac_proto.h" - //#include "../LTE_TRANSPORT/transport_common.h" // structures below implement 36-211 and 36-212 diff --git a/openair1/PHY/TOOLS/nr_phy_scope.h b/openair1/PHY/TOOLS/nr_phy_scope.h index 4877b93007..3df6b81a03 100644 --- a/openair1/PHY/TOOLS/nr_phy_scope.h +++ b/openair1/PHY/TOOLS/nr_phy_scope.h @@ -26,7 +26,6 @@ #include #include #include -#include "LAYER2/NR_MAC_gNB/nr_mac_gNB.h" #include "common/ran_context.h" #include #include diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 9a3168a33e..cb7625f10f 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -256,23 +256,6 @@ unsigned int gain_table[31] = {100,112,126,141,158,178,200,224,251,282,316,359,3 #if 0 -unsigned int get_tx_amp(int power_dBm, int power_max_dBm, int N_RB_UL, int nb_rb) // TbD -{ - - int gain_dB = power_dBm - power_max_dBm; - double gain_lin; - - gain_lin = pow(10,.1*gain_dB); - if ((nb_rb >0) && (nb_rb <= N_RB_UL)) { - return((int)(AMP*sqrt(gain_lin*N_RB_UL/(double)nb_rb))); - } - else { - LOG_E(PHY,"Illegal nb_rb/N_RB_UL combination (%d/%d)\n",nb_rb,N_RB_UL); - //mac_xface->macphy_exit(""); - } - return(0); -} - void nr_dump_dlsch_ra(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t nr_tti_rx) { unsigned int coded_bits_per_codeword; @@ -2329,8 +2312,6 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, // check if we have PRACH opportunity if (is_nr_prach_subframe(&ue->frame_parms, frame_tx, slot_tx)) { - // TBR TODO FIX this works only for TDD but it enters phy_procedures_nrUE_TX only when mode is FDD - printf(" is_nr_prach_subframe is %d\n", is_nr_prach_subframe(&ue->frame_parms, frame_tx, slot_tx)); // TBR debug nr_ue_prach_procedures(ue, proc, gNB_id, mode); } } @@ -4579,7 +4560,7 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t // if we're calibrating the PRACH kill the pointer to its resources so that the RA protocol doesn't continue if (runmode == calib_prach_tx) - ue->prach_resources[gNB_id]=NULL; + ue->prach_resources[gNB_id] = NULL; LOG_D(PHY,"[UE %d] frame %d nr_tti_rx %d : generate_nr_prach %d, prach_cnt %d\n", ue->Mod_id,frame_tx,nr_tti_tx, ue->generate_nr_prach, ue->prach_cnt); diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c index 2999f4d8ee..2342d83ed9 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c @@ -44,6 +44,9 @@ /*TAG*/ #include "NR_TAG-Id.h" +//////////////////////////////////////////////////////// +/////* DLSCH MAC PDU generation (6.1.2 TS 38.321) *///// +//////////////////////////////////////////////////////// int nr_generate_dlsch_pdu(module_id_t module_idP, unsigned char *sdus_payload, @@ -106,7 +109,6 @@ int nr_generate_dlsch_pdu(module_id_t module_idP, mac_pdu_ptr += (unsigned char) mac_ce_size; } - // Contention resolution fixed subheader and MAC CE if (ue_cont_res_id) { mac_pdu_ptr->R = 0; @@ -131,8 +133,7 @@ int nr_generate_dlsch_pdu(module_id_t module_idP, mac_pdu_ptr += (unsigned char) mac_ce_size; } - - // 2) Generation of DLSCH MAC SDU subheaders + // 2) Generation of DLSCH MAC subPDUs including subheaders and MAC SDUs for (i = 0; i < num_sdus; i++) { LOG_D(MAC, "[gNB] Generate DLSCH header num sdu %d len sdu %d\n", num_sdus, sdu_lengths[i]); @@ -153,14 +154,14 @@ int nr_generate_dlsch_pdu(module_id_t module_idP, mac_pdu_ptr += last_size; - // 3) cycle through SDUs, compute each relevant and place dlsch_buffer in + // 3) cycle through SDUs, compute each relevant and place dlsch_buffer in memcpy((void *) mac_pdu_ptr, (void *) dlsch_buffer_ptr, sdu_lengths[i]); dlsch_buffer_ptr+= sdu_lengths[i]; mac_pdu_ptr += sdu_lengths[i]; } // 4) Compute final offset for padding - if (post_padding > 0) { + if (post_padding > 0) { ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_PADDING; mac_pdu_ptr++; @@ -171,7 +172,7 @@ int nr_generate_dlsch_pdu(module_id_t module_idP, // compute final offset offset = ((unsigned char *) mac_pdu_ptr - mac_pdu); - + //printf("Offset %d \n", ((unsigned char *) mac_pdu_ptr - mac_pdu)); return offset; diff --git a/openair2/RRC/NR/L2_nr_interface.c b/openair2/RRC/NR/L2_nr_interface.c index 8b2966e0c5..ea1bccef97 100644 --- a/openair2/RRC/NR/L2_nr_interface.c +++ b/openair2/RRC/NR/L2_nr_interface.c @@ -91,7 +91,7 @@ int8_t mac_rrc_nr_data_req(const module_id_t Mod_idP, /* TODO BCCH SIB1 SIBs */ - /* CCCH */ // TBR lte code + /* CCCH */ if( (Srb_id & RAB_OFFSET ) == CCCH) { //struct rrc_eNB_ue_context_s *ue_context_p = rrc_eNB_get_ue_context(RC.rrc[Mod_idP],rnti); //if (ue_context_p == NULL) return(0); From ffa5911dc1e89c125bb87e862d08abb502752db4 Mon Sep 17 00:00:00 2001 From: cig Date: Sat, 8 Feb 2020 14:07:21 +0100 Subject: [PATCH 018/553] RA fixes --- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 178 ++++++----- openair2/LAYER2/NR_MAC_COMMON/nr_mac.h | 6 - openair2/LAYER2/NR_MAC_UE/mac_defs.h | 6 + openair2/LAYER2/NR_MAC_UE/mac_proto.h | 2 + openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c | 110 +++---- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 2 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 297 +++++++----------- openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 8 + openair2/NR_PHY_INTERFACE/NR_IF_Module.c | 6 +- openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c | 19 +- openair2/RRC/NR/rrc_gNB.c | 2 +- 11 files changed, 286 insertions(+), 350 deletions(-) diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index cb7625f10f..aba27b4dae 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -1325,13 +1325,8 @@ UE_MODE_t get_nrUE_mode(uint8_t Mod_id,uint8_t CC_id,uint8_t gNB_id){ // TBR gen return(PHY_vars_UE_g[Mod_id][CC_id]->UE_mode[gNB_id]); } -void nr_process_timing_advance(module_id_t Mod_id, uint8_t CC_id, uint8_t ta_command, uint8_t mu, uint16_t bwp_ul_NB_RB){ - - // 3GPP TS 38.213 p4.2 - // scale by the scs numerology - int factor_mu = 1 << mu; +uint16_t get_bw_scaling(uint16_t bwp_ul_NB_RB){ uint16_t bw_scaling; - // scale the 16 factor in N_TA calculation in 38.213 section 4.2 according to the used FFT size switch (bwp_ul_NB_RB) { case 106: bw_scaling = 16; break; @@ -1340,25 +1335,33 @@ void nr_process_timing_advance(module_id_t Mod_id, uint8_t CC_id, uint8_t ta_com case 273: bw_scaling = 32; break; default: abort(); } + return bw_scaling; +} + +void nr_process_timing_advance(module_id_t Mod_id, uint8_t CC_id, uint8_t ta_command, uint8_t mu, uint16_t bwp_ul_NB_RB){ + + // 3GPP TS 38.213 p4.2 + // scale by the scs numerology + int factor_mu = 1 << mu; + uint16_t bw_scaling = get_bw_scaling(bwp_ul_NB_RB); PHY_vars_UE_g[Mod_id][CC_id]->timing_advance += (ta_command - 31) * bw_scaling / factor_mu; LOG_D(PHY, "[UE %d] Got timing advance command %u from MAC, new value is %u\n", Mod_id, ta_command, PHY_vars_UE_g[Mod_id][CC_id]->timing_advance); } -void nr_process_timing_advance_rar(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint16_t timing_advance) { +void nr_process_timing_advance_rar(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint16_t ta_command) { -/* TODO TBR FIX THIS + int factor_mu = 1 << ue->frame_parms.numerology_index; + uint16_t bwp_ul_NB_RB = ue->frame_parms.N_RB_UL; + uint16_t bw_scaling = get_bw_scaling(bwp_ul_NB_RB); -ue->timing_advance = timing_advance*4; + // Transmission timing adjustment (TS 38.213 p4.2) + ue->timing_advance = bw_scaling / factor_mu; -#ifdef DEBUG_PHY_PROC - // TODO: fix this log, what is 'HW timing advance'? - //LOG_I(PHY,"[UE %d] AbsoluteSubFrame %d.%d, received (rar) timing_advance %d, HW timing advance %d\n",ue->Mod_id,proc->frame_rx, proc->nr_tti_rx_rx, ue->timing_advance); - LOG_I(PHY,"[UE %d] AbsoluteSubFrame %d.%d, received (rar) timing_advance %d\n",ue->Mod_id,proc->frame_rx, proc->nr_tti_rx, ue->timing_advance); -#endif - */ + // TBR todo handle TA application as per ch 4.2 TS 38.213 + LOG_D(PHY, "[UE %d] Frame %d Slot %d, Received (RAR) timing advance command %d new value is %u \n", ue->Mod_id, proc->frame_rx, proc->nr_tti_rx, ta_command, ue->timing_advance); } #if 0 @@ -3149,95 +3152,90 @@ void nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB } } -/*void nr_process_rar(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB_id, runmode_t mode, int abstraction_flag) { // TBR todo - int frame_rx = proc->frame_rx; - int nr_tti_rx = proc->nr_tti_rx; - int timing_advance; - NR_UE_DLSCH_t *dlsch0 = ue->dlsch_ra[eNB_id]; - int harq_pid = 0; - uint8_t *rar; +void nr_process_rar(nr_downlink_indication_t *dl_info) { - // uint8_t next1_thread_id = ue->current_thread_id[nr_tti_rx]== (RX_NB_TH-1) ? 0:(ue->current_thread_id[nr_tti_rx]+1); - // uint8_t next2_thread_id = next1_thread_id== (RX_NB_TH-1) ? 0:(next1_thread_id+1); + module_id_t module_id = dl_info->module_id; + int cc_id = dl_info->cc_id, frame_rx = dl_info->proc->frame_rx, nr_tti_rx = dl_info->proc->nr_tti_rx, ta_command, harq_pid = 0; + uint8_t gNB_index = dl_info->gNB_index, *rar; + fapi_nr_dci_indication_t *dci_ind = dl_info->dci_ind; + PHY_VARS_NR_UE *ue = PHY_vars_UE_g[module_id][cc_id]; + NR_UE_DLSCH_t *dlsch0 = ue->dlsch_ra[gNB_index]; + UE_MODE_t UE_mode = ue->UE_mode[gNB_index]; + NR_PRACH_RESOURCES_t *prach_resources = ue->prach_resources[gNB_index]; - LOG_D(PHY,"[UE %d][RAPROC] Frame %d nr_tti_rx %d Received RAR mode %d\n", - ue->Mod_id, - frame_rx, - nr_tti_rx, ue->UE_mode[eNB_id]); + uint8_t next1_thread_id = ue->current_thread_id[nr_tti_rx]== (RX_NB_TH-1) ? 0:(ue->current_thread_id[nr_tti_rx]+1); // TBR double check + uint8_t next2_thread_id = next1_thread_id== (RX_NB_TH-1) ? 0:(next1_thread_id+1); // TBR double check + LOG_D(PHY,"[UE %d][RAPROC] Frame %d subframe %d Received RAR mode %d\n", module_id, frame_rx, nr_tti_rx, UE_mode); if (ue->mac_enabled == 1) { - if ((ue->UE_mode[eNB_id] != PUSCH) && - (ue->prach_resources[eNB_id]->Msg3!=NULL)) { - LOG_D(PHY,"[UE %d][RAPROC] Frame %d nr_tti_rx %d Invoking MAC for RAR (current preamble %d)\n", - ue->Mod_id,frame_rx, - nr_tti_rx, - ue->prach_resources[eNB_id]->ra_PreambleIndex); - - // TBR restore - // timing_advance = nr_ue_process_rar(ue->Mod_id, ue->CC_id, frame_rx, - // ue->prach_resources[eNB_id]->ra_RNTI, dlsch0->harq_processes[0]->b, - // &ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->crnti, - // ue->prach_resources[eNB_id]->ra_PreambleIndex, dlsch0->harq_processes[0]->b); // alter the 'b' buffer so it contains only the selected RAR header and RAR payload - - // ue->pdcch_vars[next1_thread_id][eNB_id]->crnti = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->crnti; - // ue->pdcch_vars[next2_thread_id][eNB_id]->crnti = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->crnti; + if ((UE_mode != PUSCH) && (prach_resources->Msg3 != NULL)) { - if (timing_advance!=0xffff) { + LOG_D(PHY,"[UE %d][RAPROC] Frame %d subframe %d Invoking MAC for RAR (current preamble %d)\n", module_id, frame_rx, nr_tti_rx, prach_resources->ra_PreambleIndex); - // TBR restore - // LOG_D(PHY,"[UE %d][RAPROC] Frame %d nr_tti_rx %d Got rnti %x and timing advance %d from RAR\n", - // ue->Mod_id, - // frame_rx, - // nr_tti_rx, - // ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->crnti, - // timing_advance); + // TBR double check + // fix crnti + // ta_command = nr_ue_process_rar(ue->Mod_id, + // cc_id, + // frame_rx, + // prach_resources->ra_RNTI, + // dlsch0->harq_processes[0]->b, + // &ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][gNB_index]->crnti, + // prach_resources->ra_PreambleIndex, + // dlsch0->harq_processes[0]->b); // alter the 'b' buffer so it contains only the selected RAR header and RAR payload - // remember this c-rnti is still a tc-rnti + // ue->pdcch_vars[next1_thread_id][gNB_index]->crnti = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][gNB_index]->crnti; + // ue->pdcch_vars[next2_thread_id][gNB_index]->crnti = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][gNB_index]->crnti; - ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->crnti_is_temporary = 1; - - //timing_advance = 0; - nr_process_timing_advance_rar(ue,proc,timing_advance); - - if (mode!=debug_prach) { - ue->ulsch_Msg3_active[eNB_id]=1; - // TBR nr_get_Msg3_alloc has to be fixed - // nr_get_Msg3_alloc(&ue->frame_parms, - // nr_tti_rx, - // frame_rx, - // &ue->ulsch_Msg3_frame[eNB_id], - // &ue->ulsch_Msg3_subframe[eNB_id]); - - LOG_D(PHY,"[UE %d][RAPROC] Got Msg3_alloc Frame %d nr_tti_rx %d: Msg3_frame %d, Msg3_subframe %d\n", - ue->Mod_id, - frame_rx, - nr_tti_rx, - ue->ulsch_Msg3_frame[eNB_id], - ue->ulsch_Msg3_subframe[eNB_id]); - harq_pid = nr_subframe2harq_pid(&ue->frame_parms, - ue->ulsch_Msg3_frame[eNB_id], - ue->ulsch_Msg3_subframe[eNB_id]); - //ue->ulsch[eNB_id]->harq_processes[harq_pid]->round = 0; // TODO TBR fix this when HARQ is ready - - ue->UE_mode[eNB_id] = RA_RESPONSE; - // ue->Msg3_timer[eNB_id] = 10; - //ue->ulsch[eNB_id]->power_offset = 6; // TODO TBR fix this - ue->ulsch_no_allocation_counter[eNB_id] = 0; - } + // TBR double check + if (ta_command != 0xffff) { + // LOG_D(PHY,"[UE %d][RAPROC] Frame %d subframe %d Got rnti %x and timing advance %d from RAR\n", + // ue->Mod_id, + // frame_rx, + // nr_tti_rx, + // ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][gNB_index]->crnti, + // ta_command); + + // fix TBR : C-RNTI is still a TC-RNTI + // ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][gNB_index]->crnti_is_temporary = 1; + nr_process_timing_advance_rar(ue, dl_info->proc, ta_command); + + if (UE_mode != debug_prach) { + ue->ulsch_Msg3_active[gNB_index] = 1; + // nr_get_Msg3_alloc(&ue->frame_parms, + // nr_tti_rx, + // frame_rx, + // &ue->ulsch_Msg3_frame[gNB_index], + // &ue->ulsch_Msg3_subframe[gNB_index]); // TBR + LOG_D(PHY,"[UE %d][RAPROC] Got Msg3_alloc Frame %d subframe %d: Msg3_frame %d, Msg3_subframe %d\n", + ue->Mod_id, + frame_rx, + nr_tti_rx, + ue->ulsch_Msg3_frame[gNB_index], + ue->ulsch_Msg3_subframe[gNB_index]); + // todo TBR + // harq_pid = subframe2harq_pid(&ue->frame_parms, + // ue->ulsch_Msg3_frame[gNB_index], + // ue->ulsch_Msg3_subframe[gNB_index]); + // ue->ulsch[gNB_index]->harq_processes[harq_pid]->round = 0; + // ue->UE_mode[gNB_index] = RA_RESPONSE; + // ue->Msg3_timer[gNB_index] = 10; + // ue->ulsch[gNB_index].power_offset = 6; + // ue->ulsch_no_allocation_counter[gNB_index] = 0; + } } else { // PRACH preamble doesn't match RAR - LOG_W(PHY,"[UE %d][RAPROC] Received RAR preamble (%d) doesn't match !!!\n", - ue->Mod_id, - ue->prach_resources[eNB_id]->ra_PreambleIndex); + LOG_W(PHY,"[UE %d][RAPROC] Received RAR preamble (%d) doesn't match !!!\n", + ue->Mod_id, + prach_resources->ra_PreambleIndex); } } // mode != PUSCH - } - else { + } else { rar = dlsch0->harq_processes[0]->b+1; - timing_advance = ((((uint16_t)(rar[0]&0x7f))<<4) + (rar[1]>>4)); - nr_process_timing_advance_rar(ue,proc,timing_advance); + ta_command = ((((uint16_t)(rar[0]&0x7f))<<4) + (rar[1]>>4)); + nr_process_timing_advance_rar(ue, dl_info->proc, ta_command); } -}*/ +} + void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h index 3c7cc4ac81..2cb1dac75d 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h @@ -70,12 +70,6 @@ // F: lenght of L is 0:8 or 1:16 bits wide // R: Reserved bit, set to zero. -typedef enum { - RA_IDLE = 0, - WAIT_RAR = 1, - WAIT_CONTENTION_RESOLUTION = 2 -} RA_state_t; - typedef struct { uint8_t LCID:6; // octet 1 [5:0] uint8_t F:1; // octet 1 [6] diff --git a/openair2/LAYER2/NR_MAC_UE/mac_defs.h b/openair2/LAYER2/NR_MAC_UE/mac_defs.h index 8309afbb69..b3c5e078e7 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_defs.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_defs.h @@ -74,6 +74,12 @@ typedef enum { SFN_C_IMPOSSIBLE } SFN_C_TYPE; +typedef enum { + RA_IDLE = 0, + WAIT_RAR = 1, + WAIT_CONTENTION_RESOLUTION = 2 +} RA_state_t; + /*!\brief Top level UE MAC structure */ typedef struct { diff --git a/openair2/LAYER2/NR_MAC_UE/mac_proto.h b/openair2/LAYER2/NR_MAC_UE/mac_proto.h index 3e3704da6c..ab3b22794d 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_proto.h @@ -215,5 +215,7 @@ uint16_t nr_ue_process_rar(const module_id_t mod_id, const uint8_t preamble_index, uint8_t * selected_rar_buffer); +void nr_process_rar(nr_downlink_indication_t *dl_info); + #endif /** @}*/ diff --git a/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c b/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c index bd7e96eda5..2f81e78163 100644 --- a/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c +++ b/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c @@ -54,72 +54,64 @@ uint16_t nr_ue_process_rar(const module_id_t mod_id, uint8_t * const dlsch_buffer, rnti_t * const t_crnti, const uint8_t preamble_index, - uint8_t * selected_rar_buffer/*output argument for storing the selected RAR header and RAR payload*/){ + uint8_t * selected_rar_buffer){ NR_UE_MAC_INST_t *nrUE_mac_inst = get_mac_inst(mod_id); - - uint16_t ret = 0; // return value - NR_RA_HEADER_RAPID *rarh = (NR_RA_HEADER_RAPID *) dlsch_buffer; - - // TODO TBR - + uint16_t ret = 0; // NR_RAR_PDU *rar = (RAR_PDU *)(dlsch_buffer+1); uint8_t *rar = (uint8_t *) (dlsch_buffer + 1); - // get the last RAR payload for working with CMW500 - uint8_t n_rarpy = 0; // number of RAR payloads - uint8_t n_rarh = 0; // number of MAC RAR subheaders - uint8_t best_rx_rapid = -1; // the closest RAPID receive from all RARs + uint8_t n_rarpy = 0; // number of RAR payloads + uint8_t n_rarh = 0; // number of MAC RAR subheaders + uint8_t best_rx_rapid = -1; // the closest RAPID receive from all RARs + + AssertFatal(CC_id == 0, "RAR reception on secondary CCs is not supported yet\n"); + while (1) { - n_rarh++; - if (rarh->T == 1) { - n_rarpy++; - LOG_D(MAC, "RAPID %d\n", rarh->RAPID); - } + n_rarh++; + if (rarh->T == 1) { + n_rarpy++; + LOG_D(MAC, "RAPID %d\n", rarh->RAPID); + } - if (rarh->RAPID == preamble_index) { - LOG_D(PHY, "Found RAR with the intended RAPID %d\n", - rarh->RAPID); - rar = (uint8_t *) (dlsch_buffer + n_rarh + (n_rarpy - 1) * 6); - nrUE_mac_inst->RA_RAPID_found = 1; - break; - } + if (rarh->RAPID == preamble_index) { + LOG_D(PHY, "Found RAR with the intended RAPID %d\n", + rarh->RAPID); + rar = (uint8_t *) (dlsch_buffer + n_rarh + (n_rarpy - 1) * 6); + nrUE_mac_inst->RA_RAPID_found = 1; + break; + } - if (abs((int) rarh->RAPID - (int) preamble_index) < - abs((int) best_rx_rapid - (int) preamble_index)) { - best_rx_rapid = rarh->RAPID; - rar = (uint8_t *) (dlsch_buffer + n_rarh + (n_rarpy - 1) * 6); - } + if (abs((int) rarh->RAPID - (int) preamble_index) < + abs((int) best_rx_rapid - (int) preamble_index)) { + best_rx_rapid = rarh->RAPID; + rar = (uint8_t *) (dlsch_buffer + n_rarh + (n_rarpy - 1) * 6); + } - if (rarh->E == 0) { - LOG_I(PHY, "No RAR found with the intended RAPID. The closest RAPID in all RARs is %d\n", best_rx_rapid); - break; - } else { - rarh++; - } + if (rarh->E == 0) { + LOG_I(PHY, "No RAR found with the intended RAPID. The closest RAPID in all RARs is %d\n", best_rx_rapid); + break; + } else { + rarh++; + } }; LOG_D(MAC, "number of RAR subheader %d; number of RAR pyloads %d\n", - n_rarh, n_rarpy); - - if (CC_id > 0) { - LOG_W(MAC, "Should not have received RAR on secondary CCs! \n"); - return (0xffff); - } + n_rarh, n_rarpy); LOG_I(MAC, - "[UE %d][RAPROC] Frame %d Received RAR (%02x|%02x.%02x.%02x.%02x.%02x.%02x) for preamble %d/%d\n", - mod_id, frameP, *(uint8_t *) rarh, rar[0], rar[1], rar[2], - rar[3], rar[4], rar[5], rarh->RAPID, preamble_index); + "[UE %d][RAPROC] Frame %d Received RAR (%02x|%02x.%02x.%02x.%02x.%02x.%02x) for preamble %d/%d\n", + mod_id, frameP, *(uint8_t *) rarh, rar[0], rar[1], rar[2], + rar[3], rar[4], rar[5], rarh->RAPID, preamble_index); #ifdef DEBUG_RAR LOG_D(MAC, "[UE %d][RAPROC] rarh->E %d\n", mod_id, rarh->E); LOG_D(MAC, "[UE %d][RAPROC] rarh->T %d\n", mod_id, rarh->T); LOG_D(MAC, "[UE %d][RAPROC] rarh->RAPID %d\n", mod_id, - rarh->RAPID); + rarh->RAPID); // LOG_I(MAC,"[UE %d][RAPROC] rar->R %d\n",mod_id,rar->R); LOG_D(MAC, "[UE %d][RAPROC] rar->Timing_Advance_Command %d\n", - mod_id, (((uint16_t) (rar[0] & 0x7f)) << 4) + (rar[1] >> 4)); + mod_id, (((uint16_t) (rar[0] & 0x7f)) << 4) + (rar[1] >> 4)); // LOG_I(MAC,"[UE %d][RAPROC] rar->hopping_flag %d\n",mod_id,rar->hopping_flag); // LOG_I(MAC,"[UE %d][RAPROC] rar->rb_alloc %d\n",mod_id,rar->rb_alloc); // LOG_I(MAC,"[UE %d][RAPROC] rar->mcs %d\n",mod_id,rar->mcs); @@ -127,26 +119,26 @@ uint16_t nr_ue_process_rar(const module_id_t mod_id, // LOG_I(MAC,"[UE %d][RAPROC] rar->UL_delay %d\n",mod_id,rar->UL_delay); // LOG_I(MAC,"[UE %d][RAPROC] rar->cqi_req %d\n",mod_id,rar->cqi_req); LOG_D(MAC, "[UE %d][RAPROC] rar->t_crnti %x\n", mod_id, - (uint16_t) rar[5] + (rar[4] << 8)); + (uint16_t) rar[5] + (rar[4] << 8)); #endif if (opt_enabled) { - LOG_D(OPT, - "[UE %d][RAPROC] CC_id %d RAR Frame %d trace pdu for ra-RNTI %x\n", - mod_id, CC_id, frameP, ra_rnti); - /*trace_pdu(DIRECTION_DOWNLINK, (uint8_t *) dlsch_buffer, n_rarh + n_rarpy * 6, - mod_id, WS_RA_RNTI, ra_rnti, nrUE_mac_inst->rxFrame, - nrUE_mac_inst->rxSubframe, 0, 0);*/ // TODO TBR fix rxframe and subframe + LOG_D(OPT, + "[UE %d][RAPROC] CC_id %d RAR Frame %d trace pdu for ra-RNTI %x\n", + mod_id, CC_id, frameP, ra_rnti); + /*trace_pdu(DIRECTION_DOWNLINK, (uint8_t *) dlsch_buffer, n_rarh + n_rarpy * 6, + mod_id, WS_RA_RNTI, ra_rnti, nrUE_mac_inst->rxFrame, + nrUE_mac_inst->rxSubframe, 0, 0);*/ // TODO TBR fix rxframe and subframe } if (preamble_index == rarh->RAPID) { // TBR double check this - *t_crnti = (uint16_t) rar[5] + (rar[4] << 8); //rar->t_crnti; - nrUE_mac_inst->crnti = *t_crnti; //rar->t_crnti; - //return(rar->Timing_Advance_Command); - ret = ((((uint16_t) (rar[0] & 0x7f)) << 4) + (rar[1] >> 4)); + *t_crnti = (uint16_t) rar[5] + (rar[4] << 8); //rar->t_crnti; + nrUE_mac_inst->crnti = *t_crnti; //rar->t_crnti; + //return(rar->Timing_Advance_Command); + ret = ((((uint16_t) (rar[0] & 0x7f)) << 4) + (rar[1] >> 4)); } else { - nrUE_mac_inst->crnti = 0; - ret = (0xffff); + nrUE_mac_inst->crnti = 0; + ret = (0xffff); } // move the selected RAR to the front of the RA_PDSCH buffer @@ -154,4 +146,4 @@ uint16_t nr_ue_process_rar(const module_id_t mod_id, memcpy(selected_rar_buffer + 1, (uint8_t *) rar, 6); return ret; -} +} \ No newline at end of file diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index 5e7ad3848e..0573462ebd 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -380,7 +380,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, } // Phytest scheduling - if (phy_test && slot_txP==1){ // TBR check phy_test + if (phy_test && slot_txP==1){ nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP,NULL); // This schedules Random-Access for NR starting in subframeP nr_schedule_RA(module_idP, frame_txP, slot_txP); diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index f98aebfb0d..1645ba8574 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -28,168 +28,113 @@ */ #include "platform_types.h" + +/* MAC */ #include "nr_mac_gNB.h" #include "NR_MAC_gNB/mac_proto.h" #include "NR_MAC_COMMON/nr_mac_extern.h" -/* Openair Packet Tracer */ +/* Utils */ +#include "common/utils/LOG/log.h" +#include "common/utils/LOG/vcd_signal_dumper.h" #include "UTIL/OPT/opt.h" -// void nr_add_subframe(uint16_t *frameP, uint16_t *slotP, int offset){ -// *frameP = (*frameP + ((*slotP + offset) / 10)) % 1024; -// *slotP = ((*slotP + offset) % 10); -// } // TBR fix +extern RAN_CONTEXT_t RC; -// handles the event of MSG1 reception -// TBR remove sub_frame_t +void nr_add_subframe(uint16_t *frameP, uint16_t *slotP, int offset){ + *frameP = (*frameP + ((*slotP + offset) / 10)) % 1024; + *slotP = ((*slotP + offset) % 10); +} + +// TBR +// handles the event of msg1 reception +// todo: +// - offset computation +// - fix nr_add_subframe void nr_initiate_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP, uint16_t preamble_index, int16_t timing_offset, - uint16_t ra_rnti - #if (RRC_VERSION >= MAKE_VERSION(14, 0, 0)) // TBR - , uint8_t rach_resource_type - #endif - ){ + uint16_t ra_rnti){ uint8_t i; uint16_t msg2_frame = frameP, msg2_slot = slotP; int offset; - NR_COMMON_channels_t *cc = &RC.mac[module_idP]->common_channels[CC_id]; + gNB_MAC_INST *nr_mac = RC.nrmac[module_idP]; + NR_COMMON_channels_t *cc = &nr_mac->common_channels[CC_id]; NR_RA_t *ra = &cc->ra[0]; static uint8_t failure_cnt = 0; - /*#if (RRC_VERSION >= MAKE_VERSION(14, 0, 0)) - struct PRACH_ConfigSIB_v1310 *ext4_prach = NULL; - PRACH_ParametersListCE_r13_t *prach_ParametersListCE_r13 = NULL; - - static uint8_t failure_cnt = 0; + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_INITIATE_RA_PROC, 1); - if (cc->radioResourceConfigCommon_BR - && cc->radioResourceConfigCommon_BR->ext4) { - ext4_prach = cc->radioResourceConfigCommon_BR->ext4->prach_ConfigCommon_v1310; - prach_ParametersListCE_r13 = &ext4_prach->prach_ParametersListCE_r13; + LOG_D(MAC, "[gNB %d][RAPROC] CC_id %d Frame %d, Subframe %d Initiating RA procedure for preamble index %d\n", module_idP, CC_id, frameP, slotP, preamble_index); + + if (ra->state == RA_IDLE) { + int loop = 0; + LOG_D(MAC, "Frame %d, Subframe %d: Activating RA process \n", frameP, slotP); + ra->state = Msg2; + ra->timing_offset = timing_offset; + ra->preamble_subframe = slotP; + + // if(cc->tdd_Config!=NULL){ + // switch(cc->tdd_Config->subframeAssignment){ // TBR missing tdd_Config + // default: printf("%s:%d: TODO\n", __FILE__, __LINE__); abort(); + // case 1 : + // offset = 6; + // break; + // } + // }else{//FDD + // // DJP - this is because VNF is 2 subframes ahead of PNF and TX needs 4 subframes + // if (nfapi_mode) + // offset = 7; + // else + // offset = 5; + // } + + nr_add_subframe(&msg2_frame, &msg2_slot, offset); + + ra->Msg2_frame = msg2_frame; + ra->Msg2_subframe = msg2_slot; + + LOG_D(MAC, "%s() Msg2[%04d%d] SFN/SF:%04d%d offset:%d\n", __FUNCTION__, ra->Msg2_frame, ra->Msg2_subframe, frameP, slotP, offset); + + ra->Msg2_subframe = (slotP + offset) % 10; // TBR this is done twice ? + + do { + ra->rnti = taus(); // todo 5.1.3 TS 38.321 + loop++; } - #endif // #if (RRC_VERSION >= MAKE_VERSION(14, 0, 0)) */ - - LOG_D(MAC, "[gNB %d][RAPROC] CC_id %d Frame %d, Subframe %d Initiating RA procedure for preamble index %d\n", - module_idP, CC_id, frameP, slotP, preamble_index); - /*#if (RRC_VERSION >= MAKE_VERSION(14, 0, 0)) - LOG_D(MAC, - "[gNB %d][RAPROC] CC_id %d Frame %d, Subframe %d PRACH resource type %d\n", - module_idP, CC_id, frameP, slotP, rach_resource_type); - #endif*/ - - - - /*#if (RRC_VERSION >= MAKE_VERSION(13, 0, 0)) - if (prach_ParametersListCE_r13 && prach_ParametersListCE_r13->list.count < rach_resource_type) { - LOG_E(MAC,"[gNB %d][RAPROC] CC_id %d Received impossible PRACH resource type %d, - only %d CE levels configured\n", - module_idP, CC_id, rach_resource_type, - (int) prach_ParametersListCE_r13->list.count); - return; - } - #endif // #if (RRC_VERSION >= MAKE_VERSION(14, 0, 0)) */ - - /*VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_INITIATE_RA_PROC, 1); - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_INITIATE_RA_PROC, 0);*/ - - for (i = 0; i < NR_NB_RA_PROC_MAX; i++) { - if (ra[i].state == IDLE) { - int loop = 0; - LOG_D(MAC, "Frame %d, Subframe %d: Activating RA process %d\n", frameP, slotP, i); - ra[i].state = MSG2; - ra[i].timing_offset = timing_offset; - ra[i].preamble_subframe = slotP; - /*#if (RRC_VERSION >= MAKE_VERSION(14, 0, 0)) - ra[i].rach_resource_type = rach_resource_type; - ra[i].msg2_mpdcch_repetition_cnt = 0; - ra[i].msg4_mpdcch_repetition_cnt = 0; - #endif*/ - - /* TBR CHECK Fill in other TDD config. What about nfapi_mode? */ - // if(cc->tdd_Config!=NULL){ - // // switch(cc->tdd_Config->subframeAssignment){ // TBR missing tdd_Config - // // default: printf("%s:%d: TODO\n", __FILE__, __LINE__); abort(); - // // case 1 : - // // offset = 6; - // // break; - // // } - // }else{//FDD - // // DJP - this is because VNF is 2 subframes ahead of PNF and TX needs 4 subframes - // if (nfapi_mode) - // offset = 7; - // else - // offset = 5; - // } - - // nr_add_subframe(&msg2_frame, &msg2_slot, offset); // TBR - - ra[i].Msg2_frame = msg2_frame; - ra[i].Msg2_subframe = msg2_slot; - - LOG_D(MAC,"%s() Msg2[%04d%d] SFN/SF:%04d%d offset:%d\n", __FUNCTION__,ra[i].Msg2_frame,ra[i].Msg2_subframe,frameP,slotP,offset); - - ra[i].Msg2_subframe = (slotP + offset) % 10; - - /* TBR: find better procedure to allocate RNTI */ - do { - #if defined(USRP_REC_PLAY) // deterministic rnti in usrp record/playback mode - static int drnti[MAX_MOBILES_PER_GNB] = { 0xbda7, 0x71da, 0x9c40, 0xc350, 0x2710, 0x4e20, 0x7530, 0x1388, 0x3a98, 0x61a8, 0x88b8, 0xafc8, 0xd6d8, 0x1b58, 0x4268, 0x6978 }; - int j = 0; - int nb_ue = 0; - for (j = 0; j < MAX_MOBILES_PER_GNB; j++) { - if (UE_RNTI(module_idP, j) > 0) { - nb_ue++; - } else { - break; - } - } - if (nb_ue >= MAX_MOBILES_PER_GNB) { - printf("No more free RNTI available, increase MAX_MOBILES_PER_GNB\n"); - abort(); - } - ra[i].rnti = drnti[nb_ue]; - #else - ra[i].rnti = taus(); - #endif - loop++; - } - /* While loop - ** TBR: second condition is not correct, the rnti may be in use without - * being in the MAC yet. To be refined. - ** 1024 and 60000 arbirarily chosen, not coming from standard */ - while (loop != 100 /*&& !(find_nrUE_id(module_idP, ra[i].rnti) == -1 && ra[i].rnti >= 1024 && ra[i].rnti < 60000)*/); - // TBR nr_find_ue - - if (loop == 100) { - printf("%s:%d:%s: FATAL ERROR! contact the authors\n",__FILE__, __LINE__, __FUNCTION__); - abort(); - } - - ra[i].RA_rnti = ra_rnti; - ra[i].preamble_index = preamble_index; - failure_cnt = 0; - - LOG_D(MAC, "[gNB %d][RAPROC] CC_id %d Frame %d Activating RAR generation in Frame %d, subframe %d for process %d, rnti %x, state %d\n", module_idP, CC_id, frameP, ra[i].Msg2_frame, ra[i].Msg2_subframe, i, ra[i].rnti, ra[i].state); - - return; + // Range coming from 5.1.3 TS 38.321 + while (loop != 100 && !(find_nr_UE_id(module_idP, ra->rnti) == -1 && ra->rnti >= 1 && ra->rnti <= 17920)); + if (loop == 100) { + LOG_E(MAC,"%s:%d:%s: [RAPROC] initialisation random access aborted\n", __FILE__, __LINE__, __FUNCTION__); + abort(); } + + ra->RA_rnti = ra_rnti; + ra->preamble_index = preamble_index; + failure_cnt = 0; + + LOG_D(MAC, "[gNB %d][RAPROC] CC_id %d Frame %d Activating Msg2 generation in frame %d, slot %d for rnti %x\n", + module_idP, + CC_id, + frameP, + ra->Msg2_frame, + ra->Msg2_subframe, + ra->state); + + return; } + LOG_E(MAC, "[gNB %d][RAPROC] FAILURE: CC_id %d Frame %d initiating RA procedure for preamble index %d\n", module_idP, CC_id, frameP, preamble_index); - LOG_E(MAC, - "[gNB %d][RAPROC] FAILURE: CC_id %d Frame %d Initiating RA procedure for preamble index %d\n", - module_idP, CC_id, frameP, preamble_index); - failure_cnt++; if(failure_cnt > 20) { LOG_E(MAC,"[gNB %d][RAPROC] CC_id %d Frame %d Clear Random access information\n", module_idP, CC_id, frameP); nr_clear_ra_proc(module_idP, CC_id, frameP); } - + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_INITIATE_RA_PROC, 0); } void nr_schedule_RA(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ @@ -201,46 +146,40 @@ void nr_schedule_RA(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ start_meas(&mac->schedule_ra); - // for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { - - for (i = 0; i < NR_NB_RA_PROC_MAX; i++) { - - ra = (NR_RA_t *) & cc[CC_id].ra[i]; - LOG_D(MAC,"RA[state:%d]\n",ra->state); - - switch (ra->state){ - case MSG2: - nr_generate_Msg2(module_idP, CC_id, frameP, slotP, ra); - break; - case MSG4: - generate_Msg4(module_idP, CC_id, frameP, slotP, ra); - break; - case WAITMSG4ACK: - check_Msg4_retransmission(module_idP, CC_id, frameP, slotP, ra); - break; - } - } // for i=0 .. N_RA_PROC-1 - // } // CC_id + for (i = 0; i < NR_NB_RA_PROC_MAX; i++) { + ra = (NR_RA_t *) & cc[CC_id].ra[i]; + LOG_D(MAC,"RA[state:%d]\n",ra->state); + switch (ra->state){ + case Msg2: + nr_generate_Msg2(module_idP, CC_id, frameP, slotP, ra); + break; + case Msg4: + //generate_Msg4(module_idP, CC_id, frameP, slotP, ra); // TBR + break; + case WAIT_Msg4_ACK: + check_Msg4_retransmission(module_idP, CC_id, frameP, slotP, ra); + break; + } + } stop_meas(&mac->schedule_ra); } -void nr_generate_Msg2(module_id_t module_idP, int CC_idP, frame_t frameP, +void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP, NR_RA_t * ra){ int first_rb, N_RB_DL; - - gNB_MAC_INST *mac = RC.mac[module_idP]; - NR_COMMON_channels_t *cc = mac->common_channels; - uint8_t *vrb_map = cc[CC_idP].vrb_map; + gNB_MAC_INST *mac = RC.nrmac[module_idP]; + NR_COMMON_channels_t *cc = &mac->common_channels[CC_id]; + uint8_t *vrb_map = cc[CC_id].vrb_map; // /* TBR - MIGRATE TO THE NEW NFAPI */ -// nfapi_nr_dl_tti_request_body_t *dl_req = &mac->DL_req[CC_idP].dl_config_request_body; +// nfapi_nr_dl_tti_request_body_t *dl_req = &mac->DL_req[CC_id].dl_config_request_body; // nfapi_nr_dl_tti_request_pdu_t *dl_config_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu]; // nfapi_tx_request_pdu_t *TX_req; // // /* TBR: BW should be retrieved from // // NR_ServingCellConfigCommonSIB_t -> NR_BWP_DownlinkCommon_t -> NR_BWP_t -// N_RB_DL = to_prb(cc[CC_idP].mib->message.dl_Bandwidth); +// N_RB_DL = to_prb(cc[CC_id].mib->message.dl_Bandwidth); // // Temporary hardcoded // */ // N_RB_DL = 106; @@ -249,7 +188,7 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_idP, frame_t frameP, // // LOG_D(MAC,"[gNB %d] CC_id %d Frame %d, slotP %d: // Generating RAR DCI, state %d\n", -// module_idP, CC_idP, frameP, slotP, ra->state); +// module_idP, CC_id, frameP, slotP, ra->state); // // // Allocate 4 PRBS starting in RB 0 // // commented out because preprocessor is missing @@ -280,7 +219,7 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_idP, frame_t frameP, // dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.resource_block_coding = getRIV(N_RB_DL, first_rb, 4); // // // This checks if the above DCI allocation is feasible in current subframe -// if (!nr_CCE_allocation_infeasible(module_idP, CC_idP, 0, slotP, +// if (!nr_CCE_allocation_infeasible(module_idP, CC_id, 0, slotP, // dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level, ra->RA_rnti)) { // // LOG_D(MAC, "Frame %d: Subframe %d : Adding common DCI for RA_RNTI %x\n", frameP, slotP, ra->RA_rnti); @@ -292,7 +231,7 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_idP, frame_t frameP, // dl_config_pdu->pdu_type = NFAPI_NR_DL_CONFIG_DCI_DL_PDU_TYPE; // dl_config_pdu->pdu_size = (uint8_t) (2 + sizeof(nfapi_nr_dl_config_dlsch_pdu)); // dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.tl.tag = NFAPI_NR_DL_CONFIG_REQUEST_DLSCH_PDU_REL15_TAG; -// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.pdu_index = mac->pdu_index[CC_idP]; +// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.pdu_index = mac->pdu_index[CC_id]; // dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.rnti = ra->RA_rnti; // dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.resource_allocation_type = 2; // format 1A/1B/1D // dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.virtual_resource_block_assignment_flag = 0; // localized @@ -315,32 +254,32 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_idP, frame_t frameP, // dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.num_bf_vector = 1; // // dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.bf_vector = ; // dl_req->number_pdu++; -// mac->DL_req[CC_idP].sfn_sf = frameP<<4 | slotP; +// mac->DL_req[CC_id].sfn_sf = frameP<<4 | slotP; // // // Program UL processing for Msg3 -// nr_get_Msg3alloc(&cc[CC_idP], slotP, frameP,&ra->Msg3_frame, &ra->Msg3_subframe); +// nr_get_Msg3alloc(&cc[CC_id], slotP, frameP,&ra->Msg3_frame, &ra->Msg3_subframe); // // LOG_D(MAC, "Frame %d, Subframe %d: Setting Msg3 reception for Frame %d Subframe %d\n", // frameP, slotP, ra->Msg3_frame, // ra->Msg3_subframe); // -// nr_fill_rar(module_idP, CC_idP, ra, frameP, cc[CC_idP].RAR_pdu.payload, N_RB_DL, 7); -// nr_add_msg3(module_idP, CC_idP, ra, frameP, slotP); +// nr_fill_rar(module_idP, CC_id, ra, frameP, cc[CC_id].RAR_pdu.payload, N_RB_DL, 7); +// nr_add_msg3(module_idP, CC_id, ra, frameP, slotP); // ra->state = WAITMSG3; // LOG_D(MAC,"[gNB %d][RAPROC] Frame %d, Subframe %d: state:WAITMSG3\n", module_idP, frameP, slotP); // // // DL request -// mac->TX_req[CC_idP].sfn_sf = (frameP << 4) + slotP; -// TX_req = &mac->TX_req[CC_idP].tx_request_body.tx_pdu_list[mac->TX_req[CC_idP].tx_request_body.number_of_pdus]; +// mac->TX_req[CC_id].sfn_sf = (frameP << 4) + slotP; +// TX_req = &mac->TX_req[CC_id].tx_request_body.tx_pdu_list[mac->TX_req[CC_id].tx_request_body.number_of_pdus]; // TX_req->pdu_length = 7; // This should be changed if we have more than 1 preamble -// TX_req->pdu_index = mac->pdu_index[CC_idP]++; +// TX_req->pdu_index = mac->pdu_index[CC_id]++; // TX_req->num_segments = 1; // TX_req->segments[0].segment_length = 7; -// TX_req->segments[0].segment_data = cc[CC_idP].RAR_pdu.payload; -// mac->TX_req[CC_idP].tx_request_body.number_of_pdus++; +// TX_req->segments[0].segment_data = cc[CC_id].RAR_pdu.payload; +// mac->TX_req[CC_id].tx_request_body.number_of_pdus++; // // /*if(RC.mac[module_idP]->scheduler_mode == SCHED_MODE_FAIR_RR){ -// set_dl_ue_select_msg2(CC_idP, 4, -1, ra->rnti); +// set_dl_ue_select_msg2(CC_id, 4, -1, ra->rnti); // }*/ // } // PDCCH CCE allocation is feasible // } // Msg2 frame/subframe condition @@ -349,14 +288,12 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_idP, frame_t frameP, void nr_clear_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP){ unsigned char i; NR_RA_t *ra = (NR_RA_t *) &RC.mac[module_idP]->common_channels[CC_id].ra[0]; - for (i = 0; i < NR_NB_RA_PROC_MAX; i++){ - LOG_D(MAC,"[gNB %d][RAPROC] CC_id %d Frame %d Clear Random access information rnti %x\n", module_idP, CC_id, frameP, ra[i].rnti); - ra[i].state = IDLE; - ra[i].timing_offset = 0; - ra[i].RRC_timer = 20; - ra[i].rnti = 0; - ra[i].msg3_round = 0; - } + LOG_D(MAC,"[gNB %d][RAPROC] CC_id %d Frame %d Clear Random access information rnti %x\n", module_idP, CC_id, frameP, ra->rnti); + ra->state = IDLE; + ra->timing_offset = 0; + ra->RRC_timer = 20; + ra->rnti = 0; + ra->msg3_round = 0; } unsigned short nr_fill_rar(const module_id_t mod_id, diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index ad92fdb979..71d8aa7b15 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -75,6 +75,14 @@ /*!\brief Maximum number of random access process */ #define NR_NB_RA_PROC_MAX 4 +typedef enum { + RA_IDLE = 0, + Msg2 = 1, + WAIT_Msg3 = 2, + Msg4 = 3, + WAIT_Msg4_ACK = 4 +} RA_state_t; + /*! \brief gNB template for the Random access information */ typedef struct { /// Flag to indicate this process is active diff --git a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c index 6062995841..bde960a2e1 100644 --- a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c @@ -64,11 +64,7 @@ void handle_nr_rach(NR_UL_IND_t *UL_info) { NFAPI_SFNSF2SF(UL_info->rach_ind.sfn_sf), UL_info->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.preamble, UL_info->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.timing_advance, - UL_info->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.rnti - #if (RRC_VERSION >= MAKE_VERSION(14, 0, 0)) // TBR - ,0 - #endif - ); + UL_info->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.rnti); } } diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c index 3ac9a8a43f..d1ca2b02bd 100644 --- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c @@ -93,12 +93,15 @@ int8_t handle_dlsch (module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_n */ } -int8_t handle_rar (module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_indication_t *dci_ind, uint8_t *pduP, uint32_t pdu_len, frame_t frame, int slot, NR_UL_TIME_ALIGNMENT_t *ul_time_alignment){ - - if (IS_SOFTMODEM_NOS1 || IS_SOFTMODEM_RFSIM) - //nr_process_rar(ue,proc, gNB_index, mode); TBR +int8_t handle_rar (nr_downlink_indication_t *dl_info, + uint8_t *pduP, + uint32_t pdu_len, + NR_UL_TIME_ALIGNMENT_t *ul_time_alignment){ // TBR not used params + LOG_D(MAC, "handling RAR at MAC layer \n"); + nr_process_rar (dl_info); return 0; + } int nr_ue_ul_indication(nr_uplink_indication_t *ul_info){ @@ -260,10 +263,10 @@ int nr_ue_dl_indication(nr_downlink_indication_t *dl_info, NR_UL_TIME_ALIGNMENT_ break; case FAPI_NR_RX_PDU_TYPE_RAR: - /*ret_mask |= (handle_rar(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, dl_info->dci_ind, - (dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu, - (dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu_length, - dl_info->frame, dl_info->slot,ul_time_alignment)) << FAPI_NR_RX_PDU_TYPE_RAR;*/ //TODO TBR + ret_mask |= (handle_rar(dl_info, + (dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu, + (dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu_length, + ul_time_alignment)) << FAPI_NR_RX_PDU_TYPE_RAR; break; default: diff --git a/openair2/RRC/NR/rrc_gNB.c b/openair2/RRC/NR/rrc_gNB.c index d32c6d6f3c..189bf73aba 100644 --- a/openair2/RRC/NR/rrc_gNB.c +++ b/openair2/RRC/NR/rrc_gNB.c @@ -199,7 +199,7 @@ static void init_NR_SI(gNB_RRC_INST *rrc) { rrc->carrier.pdsch_AntennaPorts, (NR_ServingCellConfigCommon_t *)rrc->carrier.servingcellconfigcommon, 0, - 0, + 0, // TBR hardcoded rnti (NR_CellGroupConfig_t *)NULL ); From 986b5fb2475444566f226b558b16f90b24bf169b Mon Sep 17 00:00:00 2001 From: cig Date: Sat, 8 Feb 2020 18:32:42 +0100 Subject: [PATCH 019/553] Integrated nfapi_nr_dl_dci_pdu_t in DL DCI --- .../nfapi/public_inc/nfapi_nr_interface_scf.h | 68 ++++++++----------- openair1/PHY/NR_TRANSPORT/nr_dci.c | 20 +++--- openair1/PHY/NR_TRANSPORT/nr_dci_tools.c | 16 ++--- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 24 +++---- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 30 ++++---- 5 files changed, 76 insertions(+), 82 deletions(-) diff --git a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h index ee1550a5bb..8233be587c 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h @@ -622,22 +622,35 @@ typedef struct { //table 3-37 -#define DCI_PAYLOAD_BTYE_LEN 12 //? TS38.212 sec 7.3.1 +#define DCI_PAYLOAD_BYTE_LEN 8 // 12 ? TS38.212 sec 7.3.1 +#define MAX_DCI_CORESET 8 -typedef struct -{ - uint16_t rnti;// - uint16_t scrambling_id;// - uint16_t scrambling_rnti;/* */ - uint8_t cce_index;// - uint8_t aggregation_level;// - nfapi_nr_tx_precoding_and_beamforming_t* precoding_and_beamforming_list; - //tx power info - uint8_t beta_pdcch_1_0;/*PDCCH power value used for PDCCH Format 1_0 with CRC scrambled by SI-RNTI, PI-RNTI or RA-RNTI. This is ratio of -SSB/PBCH EPRE to PDCCH and PDCCH DMRS EPRE [TS38.213, sec 4.1] Value :0->17 */ - uint8_t power_control_offset_ss;//PDCCH power value used for all other PDCCH Formats. This is ratio of SSB/PBCH block EPRE to PDCCH and PDCCH DMRS EPRE [TS38.214, sec 4.1] Values: 0: -3dB, 1: 0dB, 2: 3dB, 3: 6dB - uint16_t payload_size_bits;//The total DCI length (in bits) including padding bits [TS38.212 sec 7.3.1] Range 0-> DCI_PAYLOAD_BTYE_LEN*8 - uint8_t payload[DCI_PAYLOAD_BTYE_LEN];//DCI payload, where the actual size is defined by PayloadSizeBits. The bit order is as following bit0-bit7 are mapped to first byte of MSB - LSB +typedef struct { + // The RNTI used for identifying the UE when receiving the PDU Value: 1 -> 65535. + uint16_t RNTI[MAX_DCI_CORESET]; + // For a UE-specific search space it equals the higher-layer parameter PDCCH-DMRSScrambling-ID if configured, + // otherwise it should be set to the phy cell ID. [TS38.211, sec 7.3.2.3] Value: 0->65535 + uint16_t ScramblingId[MAX_DCI_CORESET]; + // For a UE-specific search space where PDCCH-DMRSScrambling- ID is configured This param equals the CRNTI. + // Otherwise, it should be set to 0. [TS38.211, sec 7.3.2.3] Value: 0 -> 65535 + uint16_t ScramblingRNTI[MAX_DCI_CORESET]; + // CCE start Index used to send the DCI Value: 0->135 + uint8_t CceIndex[MAX_DCI_CORESET]; + // Aggregation level used [TS38.211, sec 7.3.2.1] Value: 1,2,4,8,16 + uint8_t AggregationLevel[MAX_DCI_CORESET]; + // Precoding and Beamforming structure See Table 3-43 + nfapi_nr_tx_precoding_and_beamforming_t precodingAndBeamforming[MAX_DCI_CORESET]; + // PDCCH power value used for PDCCH Format 1_0 with CRC scrambled by SI-RNTI, PI-RNTI or RA-RNTI. + // This is ratio of SSB/PBCH EPRE to PDCCH and PDCCH DMRS EPRE [TS38.213, sec 4.1] + // Value :0->17 Report title: 5G FAPI: PHY API Specification Issue date: 29 June 2019 Version: 222.10.17 68 Field Type Description representing -8 to 8 dB in 1dB steps + uint8_t beta_PDCCH_1_0[MAX_DCI_CORESET]; + // PDCCH power value used for all other PDCCH Formats. + // This is ratio of SSB/PBCH block EPRE to PDCCH and PDCCH DMRS EPRE [TS38.214, sec 4.1] Values: 0: -3dB,1: 0dB,2: 3dB,3: 6dB + uint8_t powerControlOffsetSS[MAX_DCI_CORESET]; + // The total DCI length (in bits) including padding bits [TS38.212 sec 7.3.1] Range 0->DCI_PAYLOAD_BYTE_LEN*8 + uint16_t PayloadSizeBits[MAX_DCI_CORESET]; + // DCI payload, where the actual size is defined by PayloadSizeBits. The bit order is as following bit0-bit7 are mapped to first byte of MSB - LSB + uint8_t Payload[MAX_DCI_CORESET][DCI_PAYLOAD_BYTE_LEN]; } nfapi_nr_dl_dci_pdu_t; @@ -652,9 +665,6 @@ typedef struct { uint16_t *beamIdx[275]; } nr_beamforming_t; -#define MAX_DCI_CORESET 8 -#define DCI_PAYLOAD_BYTE_LEN 8 - typedef struct { ///Bandwidth part size [TS38.213 sec12]. Number of contiguous PRBs allocated to the BWP,Value: 1->275 uint16_t BWPSize; @@ -684,26 +694,8 @@ typedef struct { uint8_t precoderGranularity; ///Number of DCIs in this CORESET.Value: 0->MaxDciPerSlot uint16_t numDlDci; - ///The RNTI used for identifying the UE when receiving the PDU Value: 1 -> 65535. - uint16_t RNTI[MAX_DCI_CORESET]; - ///For a UE-specific search space it equals the higher-layer parameter PDCCH-DMRSScrambling-ID if configured, otherwise it should be set to the phy cell ID. [TS38.211, sec 7.3.2.3] Value: 0->65535 - uint16_t ScramblingId[MAX_DCI_CORESET]; - ///For a UE-specific search space where PDCCH-DMRSScrambling- ID is configured This param equals the CRNTI. Otherwise, it should be set to 0. [TS38.211, sec 7.3.2.3] Value: 0 -> 65535 - uint16_t ScramblingRNTI[MAX_DCI_CORESET]; - ///CCE start Index used to send the DCI Value: 0->135 - uint8_t CceIndex[MAX_DCI_CORESET]; - ///Aggregation level used [TS38.211, sec 7.3.2.1] Value: 1,2,4,8,16 - uint8_t AggregationLevel[MAX_DCI_CORESET]; - ///Precoding and Beamforming structure See Table 3-43 - nfapi_nr_tx_precoding_and_beamforming_t precodingAndBeamforming[MAX_DCI_CORESET]; - ///PDCCH power value used for PDCCH Format 1_0 with CRC scrambled by SI-RNTI, PI-RNTI or RA-RNTI. This is ratio of SSB/PBCH EPRE to PDCCH and PDCCH DMRS EPRE [TS38.213, sec 4.1] Value :0->17 Report title: 5G FAPI: PHY API Specification Issue date: 29 June 2019 Version: 222.10.17 68 Field Type Description representing -8 to 8 dB in 1dB steps - uint8_t beta_PDCCH_1_0[MAX_DCI_CORESET]; - ///PDCCH power value used for all other PDCCH Formats. This is ratio of SSB/PBCH block EPRE to PDCCH and PDCCH DMRS EPRE [TS38.214, sec 4.1] Values: 0: -3dB,1: 0dB,2: 3dB,3: 6dB - uint8_t powerControlOffsetSS[MAX_DCI_CORESET]; -///The total DCI length (in bits) including padding bits [TS38.212 sec 7.3.1] Range 0->DCI_PAYLOAD_BTYE_LEN*8 - uint16_t PayloadSizeBits[MAX_DCI_CORESET]; - ///DCI payload, where the actual size is defined by PayloadSizeBits. The bit order is as following bit0-bit7 are mapped to first byte of MSB - LSB - uint8_t Payload[MAX_DCI_CORESET][DCI_PAYLOAD_BYTE_LEN]; + ///DL DCI PDU + nfapi_nr_dl_dci_pdu_t dci_pdu; } nfapi_nr_dl_tti_pdcch_pdu_rel15_t; typedef struct { diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.c b/openair1/PHY/NR_TRANSPORT/nr_dci.c index c269618743..0924740ae5 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.c @@ -206,8 +206,8 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, AssertFatal(pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED, "Interleaved CCE REG MAPPING not supported\n"); uint32_t dmrs_length = (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED)? - (n_rb*6) : (pdcch_pdu_rel15->AggregationLevel[d]*36/cset_nsymb); //2(QPSK)*3(per RB)*6(REG per CCE) - uint32_t encoded_length = pdcch_pdu_rel15->AggregationLevel[d]*108; //2(QPSK)*9(per RB)*6(REG per CCE) + (n_rb*6) : (pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]*36/cset_nsymb); //2(QPSK)*3(per RB)*6(REG per CCE) + uint32_t encoded_length = pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]*108; //2(QPSK)*9(per RB)*6(REG per CCE) LOG_D(PHY, "DMRS length per symbol %d\t DCI encoded length %d (precoder_granularity %d,reg_mapping %d)\n", dmrs_length, encoded_length,pdcch_pdu_rel15->precoderGranularity,pdcch_pdu_rel15->CceRegMappingType); dmrs_length += rb_offset*6; // To accommodate more DMRS symbols in case of rb offset @@ -228,18 +228,18 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, /// DCI payload processing // CRC attachment + Scrambling + Channel coding + Rate matching uint32_t encoder_output[NR_MAX_DCI_SIZE_DWORD]; - uint16_t n_RNTI = pdcch_pdu_rel15->RNTI[d]; - uint16_t Nid = pdcch_pdu_rel15->ScramblingId[d]; + uint16_t n_RNTI = pdcch_pdu_rel15->dci_pdu.RNTI[d]; + uint16_t Nid = pdcch_pdu_rel15->dci_pdu.ScramblingId[d]; t_nrPolar_params *currentPtr = nr_polar_params(NR_POLAR_DCI_MESSAGE_TYPE, - pdcch_pdu_rel15->PayloadSizeBits[d], - pdcch_pdu_rel15->AggregationLevel[d], + pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d], + pdcch_pdu_rel15->dci_pdu.AggregationLevel[d], 0,NULL); - polar_encoder_fast((uint64_t*)pdcch_pdu_rel15->Payload[d], encoder_output, n_RNTI,1,currentPtr); + polar_encoder_fast((uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[d], encoder_output, n_RNTI,1,currentPtr); #ifdef DEBUG_CHANNEL_CODING - printf("polar rnti %x,length %d, L %d\n",n_RNTI, pdcch_pdu_rel15->PayloadSizeBits[d],pdcch_pdu_rel15->AggregationLevel[d]); + printf("polar rnti %x,length %d, L %d\n",n_RNTI, pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d],pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]); printf("DCI PDU: [0]->0x%lx \t [1]->0x%lx\n", - ((uint64_t*)pdcch_pdu_rel15->Payload[d])[0], ((uint64_t*)pdcch_pdu_rel15->Payload[d])[1]); + ((uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[d])[0], ((uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[d])[1]); printf("Encoded Payload (length:%d dwords):\n", encoded_length>>5); for (int i=0; i>5; i++) @@ -272,7 +272,7 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, cset_start_sc -= frame_parms.ofdm_symbol_size; /*Reorder REG list for a freq first mapping*/ - uint8_t nb_regs = pdcch_pdu_rel15->AggregationLevel[d]*NR_NB_REG_PER_CCE; + uint8_t nb_regs = pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]*NR_NB_REG_PER_CCE; /*Mapping the encoded DCI along with the DMRS */ for (int reg_idx=0; reg_idxnumDlDci;d++) { - int L = pdcch_pdu_rel15->AggregationLevel[d]; + int L = pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]; if (pdcch_pdu_rel15->CoreSetType == NFAPI_NR_CSET_CONFIG_MIB_SIB1) AssertFatal(L>=4, "Invalid aggregation level for SIB1 configured PDCCH %d\n", L); @@ -151,10 +151,10 @@ void nr_fill_cce_list(PHY_VARS_gNB *gNB, uint8_t m) { C = N_reg/(bsize*R); } - LOG_D(PHY, "CCE list generation for candidate %d: bundle size %d ilv size %d CceIndex %d\n", m, bsize, R, pdcch_pdu_rel15->CceIndex[d]); + LOG_D(PHY, "CCE list generation for candidate %d: bundle size %d ilv size %d CceIndex %d\n", m, bsize, R, pdcch_pdu_rel15->dci_pdu.CceIndex[d]); for (uint8_t cce_idx=0; cce_idxcce_list[d][cce_idx]; - cce->cce_idx = pdcch_pdu_rel15->CceIndex[d] + cce_idx; + cce->cce_idx = pdcch_pdu_rel15->dci_pdu.CceIndex[d] + cce_idx; LOG_D(PHY, "cce_idx %d\n", cce->cce_idx); if (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) { @@ -210,12 +210,12 @@ void nr_fill_dci(PHY_VARS_gNB *gNB, for (int i=0;inumDlDci;i++) { - uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->Payload[i]; + uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[i]; - int dlsch_id = find_nr_dlsch(pdcch_pdu_rel15->RNTI[i],gNB,SEARCH_EXIST_OR_FREE); + int dlsch_id = find_nr_dlsch(pdcch_pdu_rel15->dci_pdu.RNTI[i],gNB,SEARCH_EXIST_OR_FREE); if( (dlsch_id<0) || (dlsch_id>=NUMBER_OF_NR_DLSCH_MAX) ){ - LOG_E(PHY,"illegal dlsch_id found!!! rnti %04x dlsch_id %d\n",(unsigned int)pdcch_pdu_rel15->RNTI[i],dlsch_id); + LOG_E(PHY,"illegal dlsch_id found!!! rnti %04x dlsch_id %d\n",(unsigned int)pdcch_pdu_rel15->dci_pdu.RNTI[i],dlsch_id); return; } @@ -228,7 +228,7 @@ void nr_fill_dci(PHY_VARS_gNB *gNB, "illegal harq_pid %d\n",harq_pid); dlsch->harq_mask |= (1<rnti = pdcch_pdu_rel15->RNTI[i]; + dlsch->rnti = pdcch_pdu_rel15->dci_pdu.RNTI[i]; nr_fill_cce_list(gNB,0); /* @@ -248,7 +248,7 @@ void nr_fill_ul_dci(PHY_VARS_gNB *gNB, for (int i=0;inumDlDci;i++) { - uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->Payload[i]; + uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[i]; // if there's no DL DCI then generate CCE list if (gNB->pdcch_pdu) nr_fill_cce_list(gNB,0); diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 68f1021c68..f392aec7ed 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -373,11 +373,11 @@ int configure_fapi_dl_pdu(int Mod_idP, bwp); pdcch_pdu_rel15->numDlDci = 1; - pdcch_pdu_rel15->AggregationLevel[0] = 4; - pdcch_pdu_rel15->RNTI[0]=UE_list->rnti[0]; - pdcch_pdu_rel15->CceIndex[0] = CCEIndex[0]; - pdcch_pdu_rel15->beta_PDCCH_1_0[0]=0; - pdcch_pdu_rel15->powerControlOffsetSS[0]=1; + pdcch_pdu_rel15->dci_pdu.AggregationLevel[0] = 4; + pdcch_pdu_rel15->dci_pdu.RNTI[0]=UE_list->rnti[0]; + pdcch_pdu_rel15->dci_pdu.CceIndex[0] = CCEIndex[0]; + pdcch_pdu_rel15->dci_pdu.beta_PDCCH_1_0[0]=0; + pdcch_pdu_rel15->dci_pdu.powerControlOffsetSS[0]=1; int dci_formats[2]; int rnti_types[2]; @@ -385,12 +385,12 @@ int configure_fapi_dl_pdu(int Mod_idP, dci_formats[0] = NR_DL_DCI_FORMAT_1_0; rnti_types[0] = NR_RNTI_C; - pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); + pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types); LOG_D(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \ coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n", - pdcch_pdu_rel15->RNTI[0], + pdcch_pdu_rel15->dci_pdu.RNTI[0], rnti_types[0], dci_formats[0], (unsigned long long)pdcch_pdu_rel15->FreqDomainResource, @@ -433,7 +433,7 @@ void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr dci_pdu_rel15->tpc = 2; LOG_D(MAC, "[gNB scheduler phytest] ULDCI type 0 payload: PDCCH CCEIndex %d, freq_alloc %d, time_alloc %d, freq_hop_flag %d, mcs %d tpc %d ndi %d rv %d\n", - pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci], + pdcch_pdu_rel15->dci_pdu.CceIndex[pdcch_pdu_rel15->numDlDci], dci_pdu_rel15->frequency_domain_assignment, dci_pdu_rel15->time_domain_assignment, dci_pdu_rel15->frequency_hopping_flag, @@ -825,13 +825,13 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET]; AssertFatal(CCEIndex>=0,"CCEIndex is negative \n"); - pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci] = CCEIndex; + pdcch_pdu_rel15->dci_pdu.CceIndex[pdcch_pdu_rel15->numDlDci] = CCEIndex; - LOG_D(PHY,"CCEIndex %d\n",pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci]); + LOG_D(PHY,"CCEIndex %d\n",pdcch_pdu_rel15->dci_pdu.CceIndex[pdcch_pdu_rel15->numDlDci]); config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); - pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); + pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types); -} +} \ No newline at end of file diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index a94934c432..f02032b1e7 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -497,7 +497,7 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, for (int i=0;inumDlDci;i++) { //pdcch-DMRS-ScramblingID AssertFatal(coreset0->pdcch_DMRS_ScramblingID != NULL,"coreset0->pdcch_DMRS_ScramblingID is null\n"); - pdcch_pdu->ScramblingId[i] = *coreset0->pdcch_DMRS_ScramblingID; + pdcch_pdu->dci_pdu.ScramblingId[i] = *coreset0->pdcch_DMRS_ScramblingID; } /// SearchSpace @@ -559,10 +559,10 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, for (int d=0;dnumDlDci;d++) { - uint64_t *dci_pdu = (uint64_t *)pdcch_pdu_rel15->Payload[d]; - AssertFatal(pdcch_pdu_rel15->PayloadSizeBits[d]<=64, "DCI sizes above 64 bits not yet supported"); + uint64_t *dci_pdu = (uint64_t *)pdcch_pdu_rel15->dci_pdu.Payload[d]; + AssertFatal(pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d]<=64, "DCI sizes above 64 bits not yet supported"); - int dci_size = pdcch_pdu_rel15->PayloadSizeBits[d]; + int dci_size = pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d]; /// Payload generation switch(dci_formats[d]) { @@ -1365,19 +1365,21 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){ } */ -/* TBR fix this -boolean_t nr_CCE_allocation_infeasible(int module_idP, int CC_idP, int format_flag, int slot, int aggregation, int rnti){ +/* +boolean_t nr_CCE_allocation_infeasible(int module_idP, int CC_id, int format_flag, int slot, int aggregation, int rnti){ - nfapi_dl_config_request_body_t *DL_req = &RC.mac[module_idP]->DL_req[CC_idP].dl_config_request_body; - nfapi_dl_config_request_pdu_t *dl_config_pdu = &DL_req->dl_config_pdu_list[DL_req->number_pdu]; - nfapi_hi_dci0_request_body_t *HI_DCI0_req = &RC.mac[module_idP]->HI_DCI0_req[CC_idP][slot].hi_dci0_request_body; + gNB_MAC_INST *mac = RC.nrmac[module_idP]; + nfapi_nr_dl_tti_request_body_t *dl_req = &mac->DL_req[CC_id].dl_config_request_body; + nfapi_nr_dl_tti_request_pdu_t *dl_config_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs]; + + nfapi_hi_dci0_request_body_t *HI_DCI0_req = &RC.mac[module_idP]->HI_DCI0_req[CC_id][slot].hi_dci0_request_body; nfapi_hi_dci0_request_pdu_t *hi_dci0_pdu = &HI_DCI0_req->hi_dci0_pdu_list[HI_DCI0_req->number_of_dci + HI_DCI0_req->number_of_hi]; int ret; boolean_t res = FALSE; if (format_flag != 2) { // DL DCI - if (DL_req->number_pdu == MAX_NUM_DL_PDU) { + if (dl_req->number_pdu == MAX_NUM_DL_PDU) { LOG_W(MAC, "Subframe %d: FAPI DL structure is full, skip scheduling UE %d\n", slot, rnti); @@ -1387,7 +1389,7 @@ boolean_t nr_CCE_allocation_infeasible(int module_idP, int CC_idP, int format_fl dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti = rnti; dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type = (format_flag == 0) ? 2 : 1; dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level = aggregation; - DL_req->number_pdu++; + dl_req->number_pdu++; LOG_D(MAC, "Subframe %d: Checking CCE feasibility format %d : (%x,%d) (%x,%d,%d)\n", slot, format_flag, rnti, aggregation, @@ -1396,11 +1398,11 @@ boolean_t nr_CCE_allocation_infeasible(int module_idP, int CC_idP, int format_fl aggregation_level, dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type); - // ret = nr_allocate_CCEs(module_idP, CC_idP, 0, slot, 0); // TBR + // ret = nr_allocate_CCEs(module_idP, CC_id, 0, slot, 0); // TBR if (ret == -1) res = TRUE; - DL_req->number_pdu--; + dl_req->number_pdu--; } } else { // ue-specific UL DCI if (HI_DCI0_req->number_of_dci + HI_DCI0_req->number_of_hi == MAX_NUM_HI_DCI0_PDU) { @@ -1411,7 +1413,7 @@ boolean_t nr_CCE_allocation_infeasible(int module_idP, int CC_idP, int format_fl hi_dci0_pdu->dci_pdu.dci_pdu_rel8.rnti = rnti; hi_dci0_pdu->dci_pdu.dci_pdu_rel8.aggregation_level = aggregation; HI_DCI0_req->number_of_dci++; - // ret = nr_allocate_CCEs(module_idP, CC_idP, 0, slot, 0); // TBR + // ret = nr_allocate_CCEs(module_idP, CC_id, 0, slot, 0); // TBR if (ret == -1) res = TRUE; HI_DCI0_req->number_of_dci--; } From 156defcd0bb2f1685588d06de9d052f1d9f103e8 Mon Sep 17 00:00:00 2001 From: cig Date: Sun, 9 Feb 2020 15:17:44 +0100 Subject: [PATCH 020/553] Fixes RAR generation, reception --- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 120 ++-- openair2/LAYER2/NR_MAC_COMMON/nr_mac.h | 24 +- openair2/LAYER2/NR_MAC_UE/mac_defs.h | 4 + openair2/LAYER2/NR_MAC_UE/mac_proto.h | 13 +- openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 237 ++++--- openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c | 150 ++-- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 1 - openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 670 +++++++++--------- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 72 +- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 24 +- openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 6 +- 11 files changed, 668 insertions(+), 653 deletions(-) diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index aba27b4dae..6f7c012670 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -1321,7 +1321,7 @@ void ulsch_common_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_ #endif -UE_MODE_t get_nrUE_mode(uint8_t Mod_id,uint8_t CC_id,uint8_t gNB_id){ // TBR generate enum for NR +UE_MODE_t get_nrUE_mode(uint8_t Mod_id,uint8_t CC_id,uint8_t gNB_id){ return(PHY_vars_UE_g[Mod_id][CC_id]->UE_mode[gNB_id]); } @@ -3152,19 +3152,47 @@ void nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB } } +// WIP TBR fix: +// - time domain indication hardcoded to 0 for k2 offset +// - extend TS 38.213 ch 8.3 Msg3 PUSCH +// - b buffer +// - ulsch power offset +// - UE_mode == PUSCH case (should be handled by TA updates) +// - harq +// - optimize: mu_pusch, j and table_6_1_2_1_1_2_time_dom_res_alloc_A are already defined in nr_ue_procedures void nr_process_rar(nr_downlink_indication_t *dl_info) { module_id_t module_id = dl_info->module_id; - int cc_id = dl_info->cc_id, frame_rx = dl_info->proc->frame_rx, nr_tti_rx = dl_info->proc->nr_tti_rx, ta_command, harq_pid = 0; + int cc_id = dl_info->cc_id, frame_rx = dl_info->proc->frame_rx, nr_tti_rx = dl_info->proc->nr_tti_rx, ta_command, k2, delta; uint8_t gNB_index = dl_info->gNB_index, *rar; fapi_nr_dci_indication_t *dci_ind = dl_info->dci_ind; PHY_VARS_NR_UE *ue = PHY_vars_UE_g[module_id][cc_id]; NR_UE_DLSCH_t *dlsch0 = ue->dlsch_ra[gNB_index]; UE_MODE_t UE_mode = ue->UE_mode[gNB_index]; NR_PRACH_RESOURCES_t *prach_resources = ue->prach_resources[gNB_index]; + uint16_t slots_per_frame = ue->frame_parms.slots_per_frame; - uint8_t next1_thread_id = ue->current_thread_id[nr_tti_rx]== (RX_NB_TH-1) ? 0:(ue->current_thread_id[nr_tti_rx]+1); // TBR double check - uint8_t next2_thread_id = next1_thread_id== (RX_NB_TH-1) ? 0:(next1_thread_id+1); // TBR double check + uint8_t mu_pusch = 1; + // definition table j Table 6.1.2.1.1-4 + uint8_t j = (mu_pusch==3)?3:(mu_pusch==2)?2:1; + uint8_t table_6_1_2_1_1_2_time_dom_res_alloc_A[16][3]={ // for PUSCH from TS 38.214 subclause 6.1.2.1.1 + {j, 0,14}, // row index 1 + {j, 0,12}, // row index 2 + {j, 0,10}, // row index 3 + {j, 2,10}, // row index 4 + {j, 4,10}, // row index 5 + {j, 4,8}, // row index 6 + {j, 4,6}, // row index 7 + {j+1,0,14}, // row index 8 + {j+1,0,12}, // row index 9 + {j+1,0,10}, // row index 10 + {j+2,0,14}, // row index 11 + {j+2,0,12}, // row index 12 + {j+2,0,10}, // row index 13 + {j, 8,6}, // row index 14 + {j+3,0,14}, // row index 15 + {j+3,0,10} // row index 16 + }; LOG_D(PHY,"[UE %d][RAPROC] Frame %d subframe %d Received RAR mode %d\n", module_id, frame_rx, nr_tti_rx, UE_mode); @@ -3173,66 +3201,75 @@ void nr_process_rar(nr_downlink_indication_t *dl_info) { LOG_D(PHY,"[UE %d][RAPROC] Frame %d subframe %d Invoking MAC for RAR (current preamble %d)\n", module_id, frame_rx, nr_tti_rx, prach_resources->ra_PreambleIndex); - // TBR double check - // fix crnti - // ta_command = nr_ue_process_rar(ue->Mod_id, - // cc_id, - // frame_rx, - // prach_resources->ra_RNTI, - // dlsch0->harq_processes[0]->b, - // &ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][gNB_index]->crnti, - // prach_resources->ra_PreambleIndex, - // dlsch0->harq_processes[0]->b); // alter the 'b' buffer so it contains only the selected RAR header and RAR payload + ta_command = nr_ue_process_rar(ue->Mod_id, + cc_id, + frame_rx, + dlsch0->harq_processes[0]->b, + &ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][gNB_index]->pdcch_config[0].rnti, + prach_resources->ra_PreambleIndex, + dlsch0->harq_processes[0]->b); // alter the 'b' buffer so it contains only the selected RAR header and RAR payload - // ue->pdcch_vars[next1_thread_id][gNB_index]->crnti = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][gNB_index]->crnti; - // ue->pdcch_vars[next2_thread_id][gNB_index]->crnti = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][gNB_index]->crnti; - - // TBR double check if (ta_command != 0xffff) { - // LOG_D(PHY,"[UE %d][RAPROC] Frame %d subframe %d Got rnti %x and timing advance %d from RAR\n", - // ue->Mod_id, - // frame_rx, - // nr_tti_rx, - // ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][gNB_index]->crnti, - // ta_command); + LOG_D(PHY,"[UE %d][RAPROC] Frame %d subframe %d Got Temporary C-RNTI %x and timing advance %d from RAR\n", + ue->Mod_id, + frame_rx, + nr_tti_rx, + ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][gNB_index]->pdcch_config[0].rnti, + ta_command); - // fix TBR : C-RNTI is still a TC-RNTI - // ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][gNB_index]->crnti_is_temporary = 1; nr_process_timing_advance_rar(ue, dl_info->proc, ta_command); if (UE_mode != debug_prach) { ue->ulsch_Msg3_active[gNB_index] = 1; - // nr_get_Msg3_alloc(&ue->frame_parms, - // nr_tti_rx, - // frame_rx, - // &ue->ulsch_Msg3_frame[gNB_index], - // &ue->ulsch_Msg3_subframe[gNB_index]); // TBR + // TS 38.213 ch 8.3 Msg3 PUSCH + // PUSCH time domain resource allocation A for normal CP + // TS 38.214 ch 6.1.2.1.1 + k2 = table_6_1_2_1_1_2_time_dom_res_alloc_A[0][0]; + switch (mu_pusch) { + case 0: + delta = 2; + break; + case 1: + delta = 3; + break; + case 2: + delta = 4; + break; + case 3: + delta = 6; + break; + } + + ue->ulsch_Msg3_subframe[gNB_index] = (nr_tti_rx + k2 + delta) % slots_per_frame; + if (nr_tti_rx + k2 + delta > slots_per_frame){ + ue->ulsch_Msg3_frame[gNB_index] = (frame_rx + 1) % 1024; + } else { + ue->ulsch_Msg3_frame[gNB_index] = frame_rx; + } + LOG_D(PHY,"[UE %d][RAPROC] Got Msg3_alloc Frame %d subframe %d: Msg3_frame %d, Msg3_subframe %d\n", ue->Mod_id, frame_rx, nr_tti_rx, ue->ulsch_Msg3_frame[gNB_index], ue->ulsch_Msg3_subframe[gNB_index]); - // todo TBR // harq_pid = subframe2harq_pid(&ue->frame_parms, // ue->ulsch_Msg3_frame[gNB_index], // ue->ulsch_Msg3_subframe[gNB_index]); // ue->ulsch[gNB_index]->harq_processes[harq_pid]->round = 0; - // ue->UE_mode[gNB_index] = RA_RESPONSE; // ue->Msg3_timer[gNB_index] = 10; // ue->ulsch[gNB_index].power_offset = 6; // ue->ulsch_no_allocation_counter[gNB_index] = 0; + ue->UE_mode[gNB_index] = RA_RESPONSE; } - } else { // PRACH preamble doesn't match RAR - LOG_W(PHY,"[UE %d][RAPROC] Received RAR preamble (%d) doesn't match !!!\n", - ue->Mod_id, - prach_resources->ra_PreambleIndex); + } else { + LOG_W(PHY,"[UE %d][RAPROC] Received RAR preamble (%d) doesn't match !!!\n", ue->Mod_id, prach_resources->ra_PreambleIndex); } - } // mode != PUSCH + } } else { - rar = dlsch0->harq_processes[0]->b+1; - ta_command = ((((uint16_t)(rar[0]&0x7f))<<4) + (rar[1]>>4)); - nr_process_timing_advance_rar(ue, dl_info->proc, ta_command); + // rar = dlsch0->harq_processes[0]->b+1; + // ta_command = ((((uint16_t)(rar[0]&0x7f))<<4) + (rar[1]>>4)); + // nr_process_timing_advance_rar(ue, dl_info->proc, ta_command); } } @@ -4468,7 +4505,6 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t uint16_t preamble_tx = 50, pathloss; NR_PRACH_RESOURCES_t prach_resources; uint8_t mod_id = ue->Mod_id; - NR_UE_MAC_INST_t *nr_UE_mac_inst = get_mac_inst(mod_id); UE_MODE_t UE_mode = get_nrUE_mode(mod_id, ue->CC_id, gNB_id); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_IN); diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h index 2cb1dac75d..82418f360e 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h @@ -147,14 +147,21 @@ typedef struct { // uint8_t payload[RAR_PAYLOAD_SIZE_MAX]; // } __attribute__ ((__packed__)) RAR_PDU; -/*!\brief MAC header of Random Access Response for Random access preamble identifier (RAPID) */ +//* RAR MAC subheader // TS 38.321 ch. 6.1.5, 6.2.2 *// +// - E: The Extension field is a flag indicating if the MAC subPDU including this MAC subheader is the last MAC subPDU or not in the MAC PDU +// - T: The Type field is a flag indicating whether the MAC subheader contains a Random Access Preamble ID or a Backoff Indicator (0, BI) (1, RAPID) +// - R: Reserved bit, set to "0" +// - BI: The Backoff Indicator field identifies the overload condition in the cell. +// - RAPID: The Random Access Preamble IDentifier field identifies the transmitted Random Access Preamble + +/*!\brief RAR MAC subheader with RAPID */ typedef struct { uint8_t RAPID:6; uint8_t T:1; uint8_t E:1; } __attribute__ ((__packed__)) NR_RA_HEADER_RAPID; -/*!\brief MAC header of Random Access Response for backoff indicator (BI)*/ +/*!\brief RAR MAC subheader with Backoff Indicator */ typedef struct { uint8_t BI:4; uint8_t R:2; @@ -162,6 +169,19 @@ typedef struct { uint8_t E:1; } __attribute__ ((__packed__)) NR_RA_HEADER_BI; +// TS 38.321 ch. 6.2.3 +typedef struct { + uint8_t R:1; // octet 1 [7] + uint8_t TA1:7; // octet 1 [7:0] + uint8_t TA2:5; // octet 2 [7:2] + uint8_t UL_GRANT_1:3; // octet 2 [2:0] + uint8_t UL_GRANT_2:8; // octet 3 [7:0] + uint8_t UL_GRANT_3:8; // octet 4 [7:0] + uint8_t UL_GRANT_4:8; // octet 5 [7:0] + uint8_t TCRNTI_1:8; // octet 6 [7:0] + uint8_t TCRNTI_2:8; // octet 7 [7:0] +} __attribute__ ((__packed__)) NR_MAC_RAR; + // 38.321 ch6.2.1, 38.331 #define DL_SCH_LCID_CCCH 0x00 #define DL_SCH_LCID_DCCH 0x01 diff --git a/openair2/LAYER2/NR_MAC_UE/mac_defs.h b/openair2/LAYER2/NR_MAC_UE/mac_defs.h index b3c5e078e7..5e223c5cd2 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_defs.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_defs.h @@ -145,6 +145,8 @@ typedef struct { /// Preamble Power Ramping Counter uint8_t RA_PREAMBLE_POWER_RAMPING_COUNTER; /// Random-access backoff counter + int16_t RA_backoff_indicator; + /// Random-access backoff counter int16_t RA_backoff_cnt; /// Random-access variable for window calculation (frame of last change in window counter) uint32_t RA_tx_frame; @@ -165,6 +167,8 @@ typedef struct { int8_t deltaPreamble_Msg3; /// Flag to monitor if matching RAPID was received in RAR uint8_t RA_RAPID_found; + /// Flag to monitor if BI was received in RAR + uint8_t RA_BI_found; /// UE_Mode variable should be used in the case of Phy_stub operation since we won't have access to PHY_VARS_UE /// where the UE_mode originally is for the full stack operation mode. The transitions between the states of the UE_Mode /// will be triggered within phy_stub_ue.c in this case diff --git a/openair2/LAYER2/NR_MAC_UE/mac_proto.h b/openair2/LAYER2/NR_MAC_UE/mac_proto.h index ab3b22794d..f78b09f5af 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_proto.h @@ -206,13 +206,12 @@ random-access procedure @param selected_rar_buffer the output buffer for storing the selected RAR header and RAR payload @returns timing advance or 0xffff if preamble doesn't match */ -uint16_t nr_ue_process_rar(const module_id_t mod_id, - const int CC_id, - const frame_t frameP, - const rnti_t ra_rnti, - uint8_t * const dlsch_buffer, - rnti_t * const t_crnti, - const uint8_t preamble_index, +uint16_t nr_ue_process_rar(module_id_t mod_id, + int CC_id, + frame_t frameP, + uint8_t * dlsch_buffer, + rnti_t * t_crnti, + uint8_t preamble_index, uint8_t * selected_rar_buffer); void nr_process_rar(nr_downlink_indication_t *dl_info); diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c index b4708a6c81..4f50115927 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -31,7 +31,6 @@ */ #include "mac.h" -// TBR missing NR_nr_UE_mac_inst in mac.h /* #include "common/utils/LOG/vcd_signal_dumper.h" @@ -69,6 +68,7 @@ extern int64_t table_6_3_3_2_3_prachConfig_Index [256][9]; //extern uint8_t nfapi_mode; +// WIP // This routine implements Section 5.1.2 (UE Random Access Resource Selection) // and Section 5.1.3 (Random Access Preamble Transmission) from 3GPP TS 38.321 void nr_get_prach_resources(module_id_t mod_id, @@ -78,15 +78,15 @@ void nr_get_prach_resources(module_id_t mod_id, uint8_t first_Msg3, NR_RACH_ConfigDedicated_t * rach_ConfigDedicated){ - NR_UE_MAC_INST_t *nr_UE_mac_inst = get_mac_inst(mod_id); - NR_PRACH_RESOURCES_t *prach_resources = &nr_UE_mac_inst->RA_prach_resources; - NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = nr_UE_mac_inst->nr_rach_ConfigCommon; - // NR_BeamFailureRecoveryConfig_t *beam_failure_recovery_config = &nr_UE_mac_inst->RA_BeamFailureRecoveryConfig; // todo + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + NR_PRACH_RESOURCES_t *prach_resources = &mac->RA_prach_resources; + NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = mac->nr_rach_ConfigCommon; + // NR_BeamFailureRecoveryConfig_t *beam_failure_recovery_config = &mac->RA_BeamFailureRecoveryConfig; // todo int messagePowerOffsetGroupB, messageSizeGroupA, PLThreshold, sizeOfRA_PreamblesGroupA, numberOfRA_Preambles, frequencyStart, i, deltaPreamble_Msg3; uint8_t noGroupB = 0, s_id, f_id, ul_carrier_id, msg1_FDM, prach_ConfigIndex, SFN_nbr, Msg3_size; - // NR_RSRP_Range_t rsrp_ThresholdSSB; // TBR todo + // NR_RSRP_Range_t rsrp_ThresholdSSB; // todo /////////////////////////////////////////////////////////// //////////* UE Random Access Resource Selection *////////// @@ -103,7 +103,7 @@ void nr_get_prach_resources(module_id_t mod_id, // -- SSB selection, set prach_resources->ra_PreambleIndex // if (rach_ConfigDedicated) { // This is for network controlled Mobility - // // TBR operation for contention-free RA resources when: + // // operation for contention-free RA resources when: // // - available SSB with SS-RSRP above rsrp-ThresholdSSB: SSB selection // // - availalbe CSI-RS with CSI-RSRP above rsrp-ThresholdCSI-RS: CSI-RS selection // prach_resources->ra_PreambleIndex = rach_ConfigDedicated->ra_PreambleIndex; @@ -111,11 +111,13 @@ void nr_get_prach_resources(module_id_t mod_id, // } //////////* Contention-based RA preamble selection *////////// + // todo + // - selection of SSB with SS-RSRP above rsrp-ThresholdSSB else select any SSB + // - todo determine next available PRACH occasion - // todo: selection of SSB with SS-RSRP above rsrp-ThresholdSSB else select any SSB - // rsrp_ThresholdSSB = *nr_rach_ConfigCommon->rsrp_ThresholdSSB; // TBR + // rsrp_ThresholdSSB = *nr_rach_ConfigCommon->rsrp_ThresholdSSB; - Msg3_size = nr_UE_mac_inst->RA_Msg3_size; + Msg3_size = mac->RA_Msg3_size; numberOfRA_Preambles = nr_rach_ConfigCommon->totalNumberOfRA_Preambles; if (!nr_rach_ConfigCommon->groupBconfigured) { @@ -194,8 +196,8 @@ void nr_get_prach_resources(module_id_t mod_id, } // todo Msg3-DeltaPreamble should be provided from higher layers, otherwise is 0 - nr_UE_mac_inst->deltaPreamble_Msg3 = 0; - deltaPreamble_Msg3 = nr_UE_mac_inst->deltaPreamble_Msg3; + mac->deltaPreamble_Msg3 = 0; + deltaPreamble_Msg3 = mac->deltaPreamble_Msg3; } PLThreshold = prach_resources->RA_PCMAX - nr_rach_ConfigCommon->rach_ConfigGeneric.preambleReceivedTargetPower - deltaPreamble_Msg3 - messagePowerOffsetGroupB; @@ -205,31 +207,27 @@ void nr_get_prach_resources(module_id_t mod_id, if (noGroupB == 1) { // use Group A preamble prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles; - nr_UE_mac_inst->RA_usedGroupA = 1; + mac->RA_usedGroupA = 1; } else if ((Msg3_size < messageSizeGroupA) && (get_PL(mod_id, 0, gNB_id) > PLThreshold)) { // Group B is configured and RA preamble Group A is used // - todo TBR update get_PL to NR get_nr_PL (needs PHY_VARS_NR_UE) // - todo add condition on CCCH_sdu_size for initiation by CCCH prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; - nr_UE_mac_inst->RA_usedGroupA = 1; + mac->RA_usedGroupA = 1; } else { // Group B preamble is configured and used // the first sizeOfRA_PreamblesGroupA RA preambles belong to RA Preambles Group A // the remaining belong to RA Preambles Group B prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); - nr_UE_mac_inst->RA_usedGroupA = 0; + mac->RA_usedGroupA = 0; } } else { // Msg3 is being retransmitted - if (nr_UE_mac_inst->RA_usedGroupA == 1) { - if (nr_rach_ConfigCommon->groupBconfigured){ - prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; - } else { - prach_resources->ra_PreambleIndex = (taus()) & 0x3f; // TBR check this - } - } else { - prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); - } + if (mac->RA_usedGroupA == 1) { + prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; + } else { + prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); } + } // todo determine next available PRACH occasion // - if RA initiated for SI request and ra_AssociationPeriodIndex and si-RequestPeriod are configured @@ -239,11 +237,12 @@ void nr_get_prach_resources(module_id_t mod_id, ///////////////////////////////////////////////////////////////////////////// //////////* Random Access Preamble Transmission (5.1.3 TS 38.321) *////////// ///////////////////////////////////////////////////////////////////////////// + // todo: + // - condition on notification of suspending power ramping counter from lower layer (5.1.3 TS 38.321) + // - check if SSB or CSI-RS have not changed since the selection in the last RA Preamble tranmission - // todo condition on notification of suspending power ramping counter from lower layer (5.1.3 TS 38.321) // TBR - // todo check if SSB or CSI-RS have not changed since the selection in the last RA Preamble tranmission - if (nr_UE_mac_inst->RA_PREAMBLE_TRANSMISSION_COUNTER > 1) - nr_UE_mac_inst->RA_PREAMBLE_TRANSMISSION_COUNTER++; + if (mac->RA_PREAMBLE_TRANSMISSION_COUNTER > 1) + mac->RA_PREAMBLE_TRANSMISSION_COUNTER++; prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = nr_get_Po_NOMINAL_PUSCH(mod_id, CC_id); @@ -278,7 +277,7 @@ void nr_get_prach_resources(module_id_t mod_id, // - s_id is starting symbol of the PRACH occasion [0...14] // - t_id is the first slot of the PRACH occasion in a system frame [0...80] - ul_carrier_id = 0; // todo SUL + ul_carrier_id = 0; // NUL f_id = nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FrequencyStart; SFN_nbr = table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][4]; s_id = table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][5]; @@ -295,15 +294,13 @@ void nr_get_prach_resources(module_id_t mod_id, LOG_D(MAC, "Computed ra_RNTI is %d", prach_resources->ra_RNTI); } +// todo: RA_attempt_number not used TBR void nr_Msg1_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id){ - - NR_UE_MAC_INST_t *nr_UE_mac_inst = get_mac_inst(mod_id); - AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); - + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + mac->ra_state == WAIT_RAR; // Start contention resolution timer - nr_UE_mac_inst->RA_attempt_number++; // todo this is not used - + mac->RA_attempt_number++; } void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id){ @@ -313,8 +310,8 @@ void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint LOG_D(MAC,"[UE %d][RAPROC] Frame %d : Msg3_tx: Setting contention resolution timer\n", mod_id, frameP); // start contention resolution timer - nr_UE_mac_inst->RA_contention_resolution_cnt = 0; - nr_UE_mac_inst->RA_contention_resolution_timer_active = 1; + mac->RA_contention_resolution_cnt = 0; + mac->RA_contention_resolution_timer_active = 1; #endif } @@ -326,6 +323,7 @@ void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint /// Only one RA procedure is ongoing at any point in time in a MAC entity /// the RA procedure on a SCell shall only be initiated by PDCCH order +// WIP NR_PRACH_RESOURCES_t *nr_ue_get_rach(module_id_t mod_id, int CC_id, UE_MODE_t UE_mode, @@ -333,31 +331,31 @@ NR_PRACH_RESOURCES_t *nr_ue_get_rach(module_id_t mod_id, uint8_t gNB_id, int nr_tti_tx){ - NR_UE_MAC_INST_t *nr_UE_mac_inst = get_mac_inst(mod_id); - uint8_t lcid = CCCH, dcch_header_len = 0, mac_sdus[MAX_NR_ULSCH_PAYLOAD_BYTES], * payload; + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + uint8_t lcid = CCCH, dcch_header_len = 0, mac_sdus[MAX_NR_ULSCH_PAYLOAD_BYTES], * payload, ra_ResponseWindow; uint16_t size_sdu = 0; unsigned short post_padding; NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = (struct NR_RACH_ConfigCommon_t *) NULL; - NR_PRACH_RESOURCES_t *prach_resources = &nr_UE_mac_inst->RA_prach_resources; + NR_PRACH_RESOURCES_t *prach_resources = &mac->RA_prach_resources; int32_t frame_diff = 0; uint8_t sdu_lcids[NB_RB_MAX] = {0}; // TBR uint16_t sdu_lengths[NB_RB_MAX] = {0}; // TBR - int TBS_bytes = 848, header_length_total, num_sdus, offset; // TBR + int TBS_bytes = 848, header_length_total, num_sdus, offset, preambleTransMax; // TBR AssertFatal(CC_id == 0,"Transmission on secondary CCs is not supported yet\n"); if (UE_mode == PRACH) { - LOG_D(MAC, "nr_ue_get_rach, RA_active value: %d", nr_UE_mac_inst->RA_active); + LOG_D(MAC, "nr_ue_get_rach, RA_active value: %d", mac->RA_active); - AssertFatal(nr_UE_mac_inst->nr_rach_ConfigCommon != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); + AssertFatal(mac->nr_rach_ConfigCommon != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); - if (nr_UE_mac_inst->nr_rach_ConfigCommon) { // TBR check the condition - nr_rach_ConfigCommon = nr_UE_mac_inst->nr_rach_ConfigCommon; + if (mac->nr_rach_ConfigCommon) { // TBR check the condition + nr_rach_ConfigCommon = mac->nr_rach_ConfigCommon; } else return NULL; - if (nr_UE_mac_inst->RA_active == 0) { + if (mac->RA_active == 0) { /* RA not active - checking if RRC is ready to initiate the RA procedure */ LOG_I(MAC, "RA not active. Starting RA preamble initialization.\n"); @@ -371,7 +369,7 @@ NR_PRACH_RESOURCES_t *nr_ue_get_rach(module_id_t mod_id, } */ - nr_UE_mac_inst->RA_RAPID_found = 0; + mac->RA_RAPID_found = 0; /* Set RA_PREAMBLE_POWER_RAMPING_STEP */ switch (nr_rach_ConfigCommon->rach_ConfigGeneric.powerRampingStep){ // in dB @@ -401,7 +399,7 @@ NR_PRACH_RESOURCES_t *nr_ue_get_rach(module_id_t mod_id, if (!IS_SOFTMODEM_NOS1){ // todo mac_rrc_nr_data_req_ue - payload = &nr_UE_mac_inst->CCCH_pdu.payload; + payload = &mac->CCCH_pdu.payload; size_sdu = (uint16_t) mac_rrc_nr_data_req_ue(mod_id, CC_id, frame, @@ -414,7 +412,7 @@ NR_PRACH_RESOURCES_t *nr_ue_get_rach(module_id_t mod_id, } else { // fill ulsch_buffer with random data - payload = (uint8_t *)nr_UE_mac_inst->ulsch_pdu.payload[0]; + payload = (uint8_t *)mac->ulsch_pdu.payload[0]; for (int i = 0; i < TBS_bytes; i++){ mac_sdus[i] = (unsigned char) (lrand48()&0xff); } @@ -427,11 +425,10 @@ NR_PRACH_RESOURCES_t *nr_ue_get_rach(module_id_t mod_id, num_sdus +=1; } - // TBR which frame and slot ? - nr_UE_mac_inst->RA_tx_frame = frame; - nr_UE_mac_inst->RA_tx_subframe = nr_tti_tx; - nr_UE_mac_inst->RA_backoff_frame = frame; - nr_UE_mac_inst->RA_backoff_subframe = nr_tti_tx; + mac->RA_tx_frame = frame; + mac->RA_tx_subframe = nr_tti_tx; + mac->RA_backoff_frame = frame; + mac->RA_backoff_subframe = nr_tti_tx; if (size_sdu > 0) { // TBR size_sdu + MAC_Header_len + mac_ce_len /* TBR initialisation by RRC @@ -439,20 +436,42 @@ NR_PRACH_RESOURCES_t *nr_ue_get_rach(module_id_t mod_id, LOG_I(MAC, "[UE %d] Frame %d: Initialisation Random Access Procedure\n", mod_id, frame); - nr_UE_mac_inst->RA_PREAMBLE_TRANSMISSION_COUNTER = 1; - nr_UE_mac_inst->RA_PREAMBLE_POWER_RAMPING_COUNTER = 1; - nr_UE_mac_inst->RA_Msg3_size = size_sdu + sizeof(NR_MAC_SUBHEADER_SHORT) + sizeof(NR_MAC_SUBHEADER_SHORT); // TBR size_sdu + MAC_Header_len + mac_ce_len - nr_UE_mac_inst->RA_prachMaskIndex = 0; + mac->RA_PREAMBLE_TRANSMISSION_COUNTER = 1; + mac->RA_PREAMBLE_POWER_RAMPING_COUNTER = 1; + mac->RA_Msg3_size = size_sdu + sizeof(NR_MAC_SUBHEADER_SHORT) + sizeof(NR_MAC_SUBHEADER_SHORT); // TBR size_sdu + MAC_Header_len + mac_ce_len + mac->RA_prachMaskIndex = 0; // TBR todo: add the backoff condition here if we have it from a previous RA reponse which failed (i.e. backoff indicator) - nr_UE_mac_inst->RA_backoff_cnt = 0; - nr_UE_mac_inst->RA_active = 1; + mac->RA_backoff_cnt = 0; + mac->RA_active = 1; prach_resources->Msg3 = payload; - // TBR todo double check window count - // nr_UE_mac_inst->RA_window_cnt = 2 + nr_rach_ConfigCommon->ra_SupervisionInfo.ra_ResponseWindowSize; - // if (nr_UE_mac_inst->RA_window_cnt == 9) { - // nr_UE_mac_inst->RA_window_cnt = 10; // Note: 9 subframe window doesn't exist, after 8 is 10! - // } + ra_ResponseWindow = nr_rach_ConfigCommon->rach_ConfigGeneric.ra_ResponseWindow; + switch (ra_ResponseWindow) { + case 0: + mac->RA_window_cnt = 1; + break; + case 1: + mac->RA_window_cnt = 2; + break; + case 2: + mac->RA_window_cnt = 4; + break; + case 3: + mac->RA_window_cnt = 8; + break; + case 4: + mac->RA_window_cnt = 10; + break; + case 5: + mac->RA_window_cnt = 20; + break; + case 6: + mac->RA_window_cnt = 40; + break; + case 7: + mac->RA_window_cnt = 80; + break; + } // Fill in preamble and PRACH resources nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 1, NULL); @@ -487,50 +506,29 @@ NR_PRACH_RESOURCES_t *nr_ue_get_rach(module_id_t mod_id, // todo: // - handle beam failure recovery request // - handle DL assignment on PDCCH for RA-RNTI + // - handle backoff and raResponseWindow params LOG_D(MAC, "[MAC][UE %d][RAPROC] frame %d, subframe %d: RA Active, window cnt %d (RA_tx_frame %d, RA_tx_subframe %d)\n", - mod_id, frame, nr_tti_tx, nr_UE_mac_inst->RA_window_cnt, nr_UE_mac_inst->RA_tx_frame, nr_UE_mac_inst->RA_tx_subframe); + mod_id, frame, nr_tti_tx, mac->RA_window_cnt, mac->RA_tx_frame, mac->RA_tx_subframe); - if (nr_UE_mac_inst->rnti_type = NR_RNTI_RA){ // add condition on BI - // TBR todo + if (mac->RA_BI_found){ + prach_resources->RA_PREAMBLE_BACKOFF = prach_resources->RA_SCALING_FACTOR_BI * mac->RA_backoff_indicator; } else { prach_resources->RA_PREAMBLE_BACKOFF = 0; } - // compute backoff parameters - if (nr_UE_mac_inst->RA_backoff_cnt > 0){ - frame_diff = (sframe_t) frame - nr_UE_mac_inst->RA_backoff_frame; - if (frame_diff < 0) frame_diff = -frame_diff; - nr_UE_mac_inst->RA_backoff_cnt -= ((10 * frame_diff) + (nr_tti_tx - nr_UE_mac_inst->RA_backoff_subframe)); - nr_UE_mac_inst->RA_backoff_frame = frame; - nr_UE_mac_inst->RA_backoff_subframe = nr_tti_tx; - } - // - TBR check - - // - TBR check - // compute RA window parameters - if (nr_UE_mac_inst->RA_window_cnt > 0){ - frame_diff = (frame_t) frame - nr_UE_mac_inst->RA_tx_frame; - if (frame_diff < 0) frame_diff = -frame_diff; - nr_UE_mac_inst->RA_window_cnt -= ((10 * frame_diff) + (nr_tti_tx - nr_UE_mac_inst->RA_tx_subframe)); - LOG_D(MAC, "[MAC][UE %d][RAPROC] Frame %d, subframe %d: RA Active, adjusted window cnt %d\n", mod_id, frame, nr_tti_tx, nr_UE_mac_inst->RA_window_cnt); - } - // - TBR check - //if ((nr_UE_mac_inst->RA_window_cnt <= 0) && (nr_UE_mac_inst->RA_backoff_cnt <= 0)){ - if ((nr_UE_mac_inst->RA_window_cnt <= 0) && (nr_UE_mac_inst->RA_RAPID_found == 0)){ // TODO TBR double check the condition - - LOG_I(MAC, "[MAC][UE %d][RAPROC] Frame %d: subframe %d: RAR reception not successful, (RA window count %d) \n", mod_id, frame, nr_tti_tx, nr_UE_mac_inst->RA_window_cnt); - - nr_UE_mac_inst->RA_PREAMBLE_TRANSMISSION_COUNTER++; + if (mac->RA_window_cnt > 0 && mac->RA_RAPID_found == 1) { + mac->ra_state == WAIT_CONTENTION_RESOLUTION; + } else { + LOG_I(MAC, "[MAC][UE %d][RAPROC] Frame %d: subframe %d: RAR reception not successful, (RA window count %d) \n", + mod_id, + frame, + nr_tti_tx, + mac->RA_window_cnt); - // - TBR check RA_tx_frame RA_tx_subframe - nr_UE_mac_inst->RA_tx_frame = frame; - nr_UE_mac_inst->RA_tx_subframe = nr_tti_tx; - prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER += (prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP << 1); // 2dB increments in ASN.1 definition - // - TBR check ra_PREAMBLE_RECEIVED_TARGET_POWER increment - - int preambleTransMax = -1; + mac->RA_PREAMBLE_TRANSMISSION_COUNTER++; + preambleTransMax = -1; switch (nr_rach_ConfigCommon->rach_ConfigGeneric.preambleTransMax) { case NR_RACH_ConfigGeneric__preambleTransMax_n3: preambleTransMax = 3; @@ -567,30 +565,39 @@ NR_PRACH_RESOURCES_t *nr_ue_get_rach(module_id_t mod_id, break; } - if (nr_UE_mac_inst->RA_PREAMBLE_TRANSMISSION_COUNTER == preambleTransMax + 1){ - + if (mac->RA_PREAMBLE_TRANSMISSION_COUNTER == preambleTransMax + 1){ LOG_D(MAC, "[UE %d] Frame %d: Maximum number of RACH attempts (%d)\n", mod_id, frame, preambleTransMax); - - // TBR select random backoff according to a uniform distribution between 0 and PREAMBLE_BACKOFF - // (rand() % prach_resources->RA_PREAMBLE_BACKOFF - - // TODO TBR send message to RRC - nr_UE_mac_inst->RA_PREAMBLE_TRANSMISSION_COUNTER = 1; - prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = nr_get_Po_NOMINAL_PUSCH(mod_id, CC_id); // TBR check if this is necessary + mac->RA_backoff_cnt = rand() % (prach_resources->RA_PREAMBLE_BACKOFF + 1); + mac->RA_PREAMBLE_TRANSMISSION_COUNTER = 1; + prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP << 1; // 2 dB increment + prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = nr_get_Po_NOMINAL_PUSCH(mod_id, CC_id); } - // TBR ra_SupervisionInfo.ra_ResponseWindowSize is missing - // nr_UE_mac_inst->RA_window_cnt = 2 + nr_rach_ConfigCommon->ra_SupervisionInfo.ra_ResponseWindowSize; - nr_UE_mac_inst->RA_backoff_cnt = 0; + // compute backoff parameters + // if (mac->RA_backoff_cnt > 0){ + // frame_diff = (sframe_t) frame - mac->RA_backoff_frame; + // if (frame_diff < 0) frame_diff = -frame_diff; + // mac->RA_backoff_frame = frame; + // mac->RA_backoff_subframe = nr_tti_tx; + // } + // compute RA window parameters + // if (mac->RA_window_cnt > 0){ + // frame_diff = (frame_t) frame - mac->RA_tx_frame; + // if (frame_diff < 0) frame_diff = -frame_diff; + // mac->RA_window_cnt -= ((10 * frame_diff) + (nr_tti_tx - mac->RA_tx_subframe)); + // LOG_D(MAC, "[MAC][UE %d][RAPROC] Frame %d, subframe %d: RA Active, adjusted window cnt %d\n", mod_id, frame, nr_tti_tx, mac->RA_window_cnt); + // } + mac->RA_tx_frame = frame; + mac->RA_tx_subframe = nr_tti_tx; // Fill in preamble and PRACH resources nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 0, NULL); - return (&nr_UE_mac_inst->RA_prach_resources); + return (&mac->RA_prach_resources); } } } else if (UE_mode == PUSCH) { - LOG_D(MAC, "[UE %d] FATAL: Should not have checked for RACH in PUSCH yet ...", mod_id); - AssertFatal(1 == 0, ""); + LOG_D(MAC, "[UE %d] FATAL: Should not have checked for RACH in PUSCH yet ...", mod_id); + AssertFatal(1 == 0, ""); } return NULL; } \ No newline at end of file diff --git a/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c b/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c index 2f81e78163..a9f304fe2b 100644 --- a/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c +++ b/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c @@ -47,103 +47,91 @@ #define DEBUG_RAR -uint16_t nr_ue_process_rar(const module_id_t mod_id, - const int CC_id, - const frame_t frameP, - const rnti_t ra_rnti, - uint8_t * const dlsch_buffer, - rnti_t * const t_crnti, - const uint8_t preamble_index, +// table 7.2-1 TS 38.321 +uint8_t table_7_2_1[16] = { + {5}, // row index 0 + {10}, // row index 1 + {20}, // row index 2 + {30}, // row index 3 + {40}, // row index 4 + {60}, // row index 5 + {80}, // row index 6 + {120}, // row index 7 + {160}, // row index 8 + {240}, // row index 9 + {320}, // row index 10 + {480}, // row index 11 + {960}, // row index 12 + {1920}, // row index 13 +}; + +// WIP todo: +// - UL grant +uint16_t nr_ue_process_rar(module_id_t mod_id, + int CC_id, + frame_t frameP, + uint8_t * dlsch_buffer, + rnti_t * t_crnti, + uint8_t preamble_index, uint8_t * selected_rar_buffer){ - NR_UE_MAC_INST_t *nrUE_mac_inst = get_mac_inst(mod_id); - NR_RA_HEADER_RAPID *rarh = (NR_RA_HEADER_RAPID *) dlsch_buffer; - uint16_t ret = 0; - // NR_RAR_PDU *rar = (RAR_PDU *)(dlsch_buffer+1); - uint8_t *rar = (uint8_t *) (dlsch_buffer + 1); - // get the last RAR payload for working with CMW500 - uint8_t n_rarpy = 0; // number of RAR payloads - uint8_t n_rarh = 0; // number of MAC RAR subheaders - uint8_t best_rx_rapid = -1; // the closest RAPID receive from all RARs + NR_UE_MAC_INST_t *ue_mac = get_mac_inst(mod_id); + NR_RA_HEADER_RAPID *rarh = (NR_RA_HEADER_RAPID *) dlsch_buffer; // RAR subheader pointer + NR_MAC_RAR *rar = (NR_MAC_RAR *) (dlsch_buffer + 1); // RAR subPDU pointer + uint8_t n_subPDUs = 0; // number of RAR payloads + uint8_t n_subheaders = 0; // number of MAC RAR subheaders + uint8_t best_rx_rapid = -1; // the closest RAPID receive from all RARs + uint16_t ta_command = 0; AssertFatal(CC_id == 0, "RAR reception on secondary CCs is not supported yet\n"); while (1) { - n_rarh++; + n_subheaders++; if (rarh->T == 1) { - n_rarpy++; - LOG_D(MAC, "RAPID %d\n", rarh->RAPID); - } - - if (rarh->RAPID == preamble_index) { - LOG_D(PHY, "Found RAR with the intended RAPID %d\n", - rarh->RAPID); - rar = (uint8_t *) (dlsch_buffer + n_rarh + (n_rarpy - 1) * 6); - nrUE_mac_inst->RA_RAPID_found = 1; - break; - } - - if (abs((int) rarh->RAPID - (int) preamble_index) < - abs((int) best_rx_rapid - (int) preamble_index)) { - best_rx_rapid = rarh->RAPID; - rar = (uint8_t *) (dlsch_buffer + n_rarh + (n_rarpy - 1) * 6); - } - - if (rarh->E == 0) { - LOG_I(PHY, "No RAR found with the intended RAPID. The closest RAPID in all RARs is %d\n", best_rx_rapid); - break; + n_subPDUs++; + LOG_D(MAC, "[UE %d][RAPROC] Got RAPID RAR subPDU %d\n", mod_id, rarh->RAPID); } else { - rarh++; + n_subPDUs++; + ue_mac->RA_backoff_indicator = table_7_2_1[((NR_RA_HEADER_BI *)rarh)->BI]; + ue_mac->RA_BI_found = 1; + LOG_D(MAC, "[UE %d][RAPROC] Got BI RAR subPDU %d\n", mod_id, ue_mac->RA_backoff_indicator); + } + if (rarh->RAPID == preamble_index) { + LOG_D(PHY, "[UE %d][RAPROC] Found RAR with the intended RAPID %d\n", rarh->RAPID); + rar = (NR_MAC_RAR *) (dlsch_buffer + n_subheaders + (n_subPDUs - 1) * sizeof(NR_MAC_RAR)); + ue_mac->RA_RAPID_found = 1; + break; + } + // if (abs((int) rarh->RAPID - (int) preamble_index) < abs((int) best_rx_rapid - (int) preamble_index)) { + // best_rx_rapid = rarh->RAPID; + // rar = (NR_MAC_RAR *) (dlsch_buffer + n_subheaders + (n_subPDUs - 1) * sizeof(NR_MAC_RAR)); + // } + if (rarh->E == 0) { + LOG_I(PHY, "No RAR found with the intended RAPID. The closest RAPID in all RARs is %d\n", best_rx_rapid); + break; + } else { + rarh += sizeof(NR_MAC_RAR) + 1; } }; - LOG_D(MAC, "number of RAR subheader %d; number of RAR pyloads %d\n", - n_rarh, n_rarpy); - LOG_I(MAC, - "[UE %d][RAPROC] Frame %d Received RAR (%02x|%02x.%02x.%02x.%02x.%02x.%02x) for preamble %d/%d\n", - mod_id, frameP, *(uint8_t *) rarh, rar[0], rar[1], rar[2], - rar[3], rar[4], rar[5], rarh->RAPID, preamble_index); -#ifdef DEBUG_RAR - LOG_D(MAC, "[UE %d][RAPROC] rarh->E %d\n", mod_id, rarh->E); - LOG_D(MAC, "[UE %d][RAPROC] rarh->T %d\n", mod_id, rarh->T); - LOG_D(MAC, "[UE %d][RAPROC] rarh->RAPID %d\n", mod_id, - rarh->RAPID); + LOG_D(MAC, "number of RAR subheader %d; number of RAR pyloads %d\n", n_subheaders, n_subPDUs); - // LOG_I(MAC,"[UE %d][RAPROC] rar->R %d\n",mod_id,rar->R); - LOG_D(MAC, "[UE %d][RAPROC] rar->Timing_Advance_Command %d\n", - mod_id, (((uint16_t) (rar[0] & 0x7f)) << 4) + (rar[1] >> 4)); - // LOG_I(MAC,"[UE %d][RAPROC] rar->hopping_flag %d\n",mod_id,rar->hopping_flag); - // LOG_I(MAC,"[UE %d][RAPROC] rar->rb_alloc %d\n",mod_id,rar->rb_alloc); - // LOG_I(MAC,"[UE %d][RAPROC] rar->mcs %d\n",mod_id,rar->mcs); - // LOG_I(MAC,"[UE %d][RAPROC] rar->TPC %d\n",mod_id,rar->TPC); - // LOG_I(MAC,"[UE %d][RAPROC] rar->UL_delay %d\n",mod_id,rar->UL_delay); - // LOG_I(MAC,"[UE %d][RAPROC] rar->cqi_req %d\n",mod_id,rar->cqi_req); - LOG_D(MAC, "[UE %d][RAPROC] rar->t_crnti %x\n", mod_id, - (uint16_t) rar[5] + (rar[4] << 8)); -#endif + LOG_I(MAC, "[UE %d][RAPROC] Frame %d Received RAR (%02x|%02x.%02x.%02x.%02x.%02x.%02x) for preamble %d/%d\n", + mod_id, frameP, *(uint8_t *) rarh, rar[0], rar[1], rar[2], rar[3], rar[4], rar[5], rarh->RAPID, preamble_index); - if (opt_enabled) { - LOG_D(OPT, - "[UE %d][RAPROC] CC_id %d RAR Frame %d trace pdu for ra-RNTI %x\n", - mod_id, CC_id, frameP, ra_rnti); - /*trace_pdu(DIRECTION_DOWNLINK, (uint8_t *) dlsch_buffer, n_rarh + n_rarpy * 6, - mod_id, WS_RA_RNTI, ra_rnti, nrUE_mac_inst->rxFrame, - nrUE_mac_inst->rxSubframe, 0, 0);*/ // TODO TBR fix rxframe and subframe - } - - if (preamble_index == rarh->RAPID) { // TBR double check this - *t_crnti = (uint16_t) rar[5] + (rar[4] << 8); //rar->t_crnti; - nrUE_mac_inst->crnti = *t_crnti; //rar->t_crnti; - //return(rar->Timing_Advance_Command); - ret = ((((uint16_t) (rar[0] & 0x7f)) << 4) + (rar[1] >> 4)); + if (ue_mac->RA_RAPID_found) { + *t_crnti = rar->TCRNTI_2 + (rar->TCRNTI_1 << 8); + ue_mac->t_crnti = *t_crnti; + ue_mac->rnti_type == NR_RNTI_TC; + ta_command = rar->TA2 + (rar->TA1 << 5); } else { - nrUE_mac_inst->crnti = 0; - ret = (0xffff); + ue_mac->t_crnti = 0; + ta_command = (0xffff); } // move the selected RAR to the front of the RA_PDSCH buffer - memcpy(selected_rar_buffer + 0, (uint8_t *) rarh, 1); - memcpy(selected_rar_buffer + 1, (uint8_t *) rar, 6); + memcpy((void *) (selected_rar_buffer + 0), (void *) rarh, 1); + memcpy((void *) (selected_rar_buffer + 1), (void *) rar, sizeof(NR_MAC_RAR)); - return ret; + return ta_command; } \ No newline at end of file diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index 0573462ebd..3258628b7f 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -382,7 +382,6 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, // Phytest scheduling if (phy_test && slot_txP==1){ nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP,NULL); - // This schedules Random-Access for NR starting in subframeP nr_schedule_RA(module_idP, frame_txP, slot_txP); // resetting ta flag gNB->ta_len = 0; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index 1645ba8574..074eda8ea8 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -78,7 +78,7 @@ void nr_initiate_ra_proc(module_id_t module_idP, ra->preamble_subframe = slotP; // if(cc->tdd_Config!=NULL){ - // switch(cc->tdd_Config->subframeAssignment){ // TBR missing tdd_Config + // switch(cc->tdd_Config->subframeAssignment){ // default: printf("%s:%d: TODO\n", __FILE__, __LINE__); abort(); // case 1 : // offset = 6; @@ -95,11 +95,11 @@ void nr_initiate_ra_proc(module_id_t module_idP, nr_add_subframe(&msg2_frame, &msg2_slot, offset); ra->Msg2_frame = msg2_frame; - ra->Msg2_subframe = msg2_slot; + ra->Msg2_slot = msg2_slot; - LOG_D(MAC, "%s() Msg2[%04d%d] SFN/SF:%04d%d offset:%d\n", __FUNCTION__, ra->Msg2_frame, ra->Msg2_subframe, frameP, slotP, offset); + LOG_D(MAC, "%s() Msg2[%04d%d] SFN/SF:%04d%d offset:%d\n", __FUNCTION__, ra->Msg2_frame, ra->Msg2_slot, frameP, slotP, offset); - ra->Msg2_subframe = (slotP + offset) % 10; // TBR this is done twice ? + ra->Msg2_slot = (slotP + offset) % 10; // TBR this is done twice ? do { ra->rnti = taus(); // todo 5.1.3 TS 38.321 @@ -121,7 +121,7 @@ void nr_initiate_ra_proc(module_id_t module_idP, CC_id, frameP, ra->Msg2_frame, - ra->Msg2_subframe, + ra->Msg2_slot, ra->state); return; @@ -137,157 +137,228 @@ void nr_initiate_ra_proc(module_id_t module_idP, VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_INITIATE_RA_PROC, 0); } +// WIP void nr_schedule_RA(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ + //uint8_t i = 0; + int CC_id = 0; gNB_MAC_INST *mac = RC.mac[module_idP]; - NR_COMMON_channels_t *cc = mac->common_channels; - NR_RA_t *ra; - uint8_t i, CC_id = 0; + NR_COMMON_channels_t *cc = &mac->common_channels[CC_id]; + NR_RA_t *ra = &cc->ra[0]; start_meas(&mac->schedule_ra); - for (i = 0; i < NR_NB_RA_PROC_MAX; i++) { - ra = (NR_RA_t *) & cc[CC_id].ra[i]; - LOG_D(MAC,"RA[state:%d]\n",ra->state); - switch (ra->state){ - case Msg2: - nr_generate_Msg2(module_idP, CC_id, frameP, slotP, ra); - break; - case Msg4: - //generate_Msg4(module_idP, CC_id, frameP, slotP, ra); // TBR - break; - case WAIT_Msg4_ACK: - check_Msg4_retransmission(module_idP, CC_id, frameP, slotP, ra); - break; - } + //for (i = 0; i < NR_NB_RA_PROC_MAX; i++) { + LOG_D(MAC,"RA[state:%d]\n",ra->state); + switch (ra->state){ + case Msg2: + //nr_generate_Msg2(module_idP, CC_id, frameP, slotP); + break; + case Msg4: + //generate_Msg4(module_idP, CC_id, frameP, slotP, ra); + break; + case WAIT_Msg4_ACK: + check_Msg4_retransmission(module_idP, CC_id, frameP, slotP, ra); + break; } + //} stop_meas(&mac->schedule_ra); } -void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, - sub_frame_t slotP, NR_RA_t * ra){ +// WIP +void nr_generate_Msg2(module_id_t module_idP, + int CC_id, + frame_t frameP, + sub_frame_t slotP){ - int first_rb, N_RB_DL; - gNB_MAC_INST *mac = RC.nrmac[module_idP]; - NR_COMMON_channels_t *cc = &mac->common_channels[CC_id]; - uint8_t *vrb_map = cc[CC_id].vrb_map; + int first_rb, UE_id = 0, dci_formats[2], rnti_types[2], CCEIndex, dlBWP_carrier_bandwidth, mcsIndex = 9; + int startSymbolAndLength = 0, StartSymbolIndex = -1, NrOfSymbols = 14, StartSymbolIndex_tmp, NrOfSymbols_tmp, x_Overhead, time_domain_assignment = 2; + int bwp_id = 1, coreset_id = 0, aggregation = 4, search_space = 0, N_RB_UL = 106; + gNB_MAC_INST *nr_mac = RC.nrmac[module_idP]; + NR_COMMON_channels_t *cc = &nr_mac->common_channels[0]; + NR_RA_t *ra = &cc->ra[0]; + NR_UE_list_t *UE_list = &nr_mac->UE_list; -// /* TBR - MIGRATE TO THE NEW NFAPI */ -// nfapi_nr_dl_tti_request_body_t *dl_req = &mac->DL_req[CC_id].dl_config_request_body; -// nfapi_nr_dl_tti_request_pdu_t *dl_config_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu]; -// nfapi_tx_request_pdu_t *TX_req; -// -// /* TBR: BW should be retrieved from -// // NR_ServingCellConfigCommonSIB_t -> NR_BWP_DownlinkCommon_t -> NR_BWP_t -// N_RB_DL = to_prb(cc[CC_id].mib->message.dl_Bandwidth); -// // Temporary hardcoded -// */ -// N_RB_DL = 106; -// -// if ((ra->Msg2_frame == frameP) && (ra->Msg2_subframe == slotP)) { -// -// LOG_D(MAC,"[gNB %d] CC_id %d Frame %d, slotP %d: -// Generating RAR DCI, state %d\n", -// module_idP, CC_id, frameP, slotP, ra->state); -// -// // Allocate 4 PRBS starting in RB 0 -// // commented out because preprocessor is missing -// /*first_rb = 0; -// vrb_map[first_rb] = 1; -// vrb_map[first_rb + 1] = 1; -// vrb_map[first_rb + 2] = 1; -// vrb_map[first_rb + 3] = 1;*/ -// -// memset((void *) dl_config_pdu, 0, sizeof(nfapi_nr_dl_config_request_pdu_t)); -// -// dl_config_pdu->pdu_type = NFAPI_NR_DL_CONFIG_DCI_DL_PDU_TYPE; -// dl_config_pdu->pdu_size = (uint8_t) (2 + sizeof(nfapi_dl_config_dci_dl_pdu)); -// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tl.tag = NFAPI_DL_CONFIG_REQUEST_DCI_DL_PDU_REL8_TAG; -// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.dci_format = NFAPI_DL_DCI_FORMAT_1A; -// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level = 4; -// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti = ra->RA_rnti; -// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type = 2; // RA-RNTI : see Table 4-10 from SCF082 - nFAPI specifications -// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.transmission_power = 6000; // equal to RS power -// -// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.harq_process = 0; -// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tpc = 1; // no TPC -// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.new_data_indicator_1 = 1; -// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.mcs_1 = 0; -// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.redundancy_version_1 = 0; -// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.virtual_resource_block_assignment_flag = 0; -// -// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.resource_block_coding = getRIV(N_RB_DL, first_rb, 4); -// -// // This checks if the above DCI allocation is feasible in current subframe -// if (!nr_CCE_allocation_infeasible(module_idP, CC_id, 0, slotP, -// dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level, ra->RA_rnti)) { -// -// LOG_D(MAC, "Frame %d: Subframe %d : Adding common DCI for RA_RNTI %x\n", frameP, slotP, ra->RA_rnti); -// dl_req->number_dci++; -// dl_req->number_pdu++; -// -// dl_config_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu]; -// memset((void *) dl_config_pdu, 0, sizeof(nfapi_nr_dl_config_request_pdu_t)); -// dl_config_pdu->pdu_type = NFAPI_NR_DL_CONFIG_DCI_DL_PDU_TYPE; -// dl_config_pdu->pdu_size = (uint8_t) (2 + sizeof(nfapi_nr_dl_config_dlsch_pdu)); -// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.tl.tag = NFAPI_NR_DL_CONFIG_REQUEST_DLSCH_PDU_REL15_TAG; -// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.pdu_index = mac->pdu_index[CC_id]; -// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.rnti = ra->RA_rnti; -// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.resource_allocation_type = 2; // format 1A/1B/1D -// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.virtual_resource_block_assignment_flag = 0; // localized -// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.resource_block_coding = getRIV(N_RB_DL, first_rb, 4); -// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.modulation = 2; //QPSK -// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.redundancy_version = 0; -// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.transport_blocks = 1; // first block -// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.transport_block_to_codeword_swap_flag = 0; -// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.transmission_scheme = (cc->p_eNB == 1) ? 0 : 1; -// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.number_of_layers = 1; -// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.number_of_subbands = 1; -// // dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.codebook_index = ; -// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.ue_category_capacity = 1; -// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.pa = 4; // 0 dB -// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.delta_power_offset_index = 0; -// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.ngap = 0; -// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.nprb = get_subbandsize(cc->mib->message.dl_Bandwidth); // ignored -// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.transmission_mode = (cc->p_eNB == 1) ? 1 : 2; -// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.num_bf_prb_per_subband = 1; -// dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.num_bf_vector = 1; -// // dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.bf_vector = ; -// dl_req->number_pdu++; -// mac->DL_req[CC_id].sfn_sf = frameP<<4 | slotP; -// -// // Program UL processing for Msg3 -// nr_get_Msg3alloc(&cc[CC_id], slotP, frameP,&ra->Msg3_frame, &ra->Msg3_subframe); -// -// LOG_D(MAC, "Frame %d, Subframe %d: Setting Msg3 reception for Frame %d Subframe %d\n", -// frameP, slotP, ra->Msg3_frame, -// ra->Msg3_subframe); -// -// nr_fill_rar(module_idP, CC_id, ra, frameP, cc[CC_id].RAR_pdu.payload, N_RB_DL, 7); -// nr_add_msg3(module_idP, CC_id, ra, frameP, slotP); -// ra->state = WAITMSG3; -// LOG_D(MAC,"[gNB %d][RAPROC] Frame %d, Subframe %d: state:WAITMSG3\n", module_idP, frameP, slotP); -// -// // DL request -// mac->TX_req[CC_id].sfn_sf = (frameP << 4) + slotP; -// TX_req = &mac->TX_req[CC_id].tx_request_body.tx_pdu_list[mac->TX_req[CC_id].tx_request_body.number_of_pdus]; -// TX_req->pdu_length = 7; // This should be changed if we have more than 1 preamble -// TX_req->pdu_index = mac->pdu_index[CC_id]++; -// TX_req->num_segments = 1; -// TX_req->segments[0].segment_length = 7; -// TX_req->segments[0].segment_data = cc[CC_id].RAR_pdu.payload; -// mac->TX_req[CC_id].tx_request_body.number_of_pdus++; -// -// /*if(RC.mac[module_idP]->scheduler_mode == SCHED_MODE_FAIR_RR){ -// set_dl_ue_select_msg2(CC_id, 4, -1, ra->rnti); -// }*/ -// } // PDCCH CCE allocation is feasible -// } // Msg2 frame/subframe condition + uint16_t rnti = ra->rnti, RA_rnti = ra->RA_rnti, numDlDci; + long locationAndBandwidth; + // uint8_t *vrb_map = cc[CC_id].vrb_map, CC_id; + + if ((ra->Msg2_frame == frameP) && (ra->Msg2_slot == slotP)) { + + // todo + // Allocate 4 PRBS starting in RB 0 + // first_rb = 0; + // vrb_map[first_rb] = 1; + // vrb_map[first_rb + 1] = 1; + // vrb_map[first_rb + 2] = 1; + // vrb_map[first_rb + 3] = 1; + + nfapi_nr_dl_tti_request_body_t *dl_req = &nr_mac->DL_req[CC_id].dl_tti_request_body; + nfapi_nr_dl_tti_request_pdu_t *dl_config_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs]; + nfapi_nr_pdu_t *tx_req = &nr_mac->TX_req[CC_id].pdu_list[nr_mac->TX_req[CC_id].Number_of_PDUs]; + + nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs]; + memset((void*)dl_tti_pdcch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t)); + dl_tti_pdcch_pdu->PDUType = NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE; + dl_tti_pdcch_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdcch_pdu)); + + nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs+1]; + memset((void *)dl_tti_pdsch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t)); + dl_tti_pdsch_pdu->PDUType = NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE; + dl_tti_pdsch_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdsch_pdu)); + + nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &dl_tti_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15; + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = &dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15; + nfapi_nr_dl_dci_pdu_t *dci_pdu = &pdcch_pdu_rel15->dci_pdu; + numDlDci = pdcch_pdu_rel15->numDlDci; + + // Checking if the DCI allocation is feasible in current subframe + if (dl_req->nPDUs == NFAPI_NR_MAX_DL_TTI_PDUS) { + LOG_I(MAC, "[RAPROC] Subframe %d: FAPI DL structure is full, skip scheduling UE %d\n", slotP, RA_rnti); + return; + } else { + LOG_D(MAC, "[RAPROC] Subframe %d: Checking CCE feasibility format : (%x,%d) \n", slotP, RA_rnti, aggregation); + CCEIndex = allocate_nr_CCEs(nr_mac, bwp_id, coreset_id, aggregation, search_space, UE_id, 0); + AssertFatal(CCEIndex > 0,"CCEIndex is negative\n"); + } + + LOG_D(MAC,"[gNB %d] [RAPROC] CC_id %d Frame %d, slotP %d: Generating RAR DCI, state %d\n", module_idP, CC_id, frameP, slotP, ra->state); + + NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; + locationAndBandwidth = scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth; + dlBWP_carrier_bandwidth = NRRIV2BW(locationAndBandwidth,275); + NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id]; + AssertFatal(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count == 1, + "downlinkBWP_ToAddModList has %d BWP!\n", secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count); + NR_BWP_Downlink_t *bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id - 1]; + + LOG_D(MAC, "[RAPROC] Scheduling common search space DCI type 1 dlBWP BW.firstRB %d.%d\n", dlBWP_carrier_bandwidth, + NRRIV2PRBOFFSET(locationAndBandwidth, 275)); + + pdsch_pdu_rel15->pduBitmap = 0; + pdsch_pdu_rel15->rnti = rnti; + pdsch_pdu_rel15->pduIndex = 0; + pdsch_pdu_rel15->BWPSize = NRRIV2BW(locationAndBandwidth,275); + pdsch_pdu_rel15->BWPStart = NRRIV2PRBOFFSET(locationAndBandwidth,275); + pdsch_pdu_rel15->SubcarrierSpacing = scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.subcarrierSpacing; + pdsch_pdu_rel15->CyclicPrefix = 0; + pdsch_pdu_rel15->NrOfCodewords = 1; + pdsch_pdu_rel15->targetCodeRate[0] = nr_get_code_rate_dl(mcsIndex,0); + pdsch_pdu_rel15->qamModOrder[0] = 2; + pdsch_pdu_rel15->mcsIndex[0] = mcsIndex; + pdsch_pdu_rel15->mcsTable[0] = 0; + pdsch_pdu_rel15->rvIndex[0] = 0; + pdsch_pdu_rel15->dataScramblingId = *scc->physCellId; + pdsch_pdu_rel15->nrOfLayers = 1; + pdsch_pdu_rel15->transmissionScheme = 0; + pdsch_pdu_rel15->refPoint = 0; + pdsch_pdu_rel15->dmrsConfigType = 0; + pdsch_pdu_rel15->dlDmrsScramblingId = *scc->physCellId; + pdsch_pdu_rel15->SCID = 0; + pdsch_pdu_rel15->numDmrsCdmGrpsNoData = 1; + pdsch_pdu_rel15->dmrsPorts = 1; + pdsch_pdu_rel15->resourceAlloc = 1; + pdsch_pdu_rel15->rbStart = 0; + pdsch_pdu_rel15->rbSize = 6; + pdsch_pdu_rel15->VRBtoPRBMapping = 1; + + for (int i=0; idownlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count; i++) { + startSymbolAndLength = scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->startSymbolAndLength; + SLIV2SL(startSymbolAndLength, &StartSymbolIndex_tmp, &NrOfSymbols_tmp); + if (NrOfSymbols_tmp < NrOfSymbols) { + NrOfSymbols = NrOfSymbols_tmp; + StartSymbolIndex = StartSymbolIndex_tmp; + } + } + + AssertFatal(StartSymbolIndex >= 0, "StartSymbolIndex is negative\n"); + pdsch_pdu_rel15->StartSymbolIndex = StartSymbolIndex; + pdsch_pdu_rel15->NrOfSymbols = NrOfSymbols; + pdsch_pdu_rel15->dlDmrsSymbPos = fill_dmrs_mask(NULL, scc->dmrs_TypeA_Position, NrOfSymbols); + + dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET]; + dci_pdu_rel15[0].frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize, + pdsch_pdu_rel15->rbStart, + NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth, 275)); + dci_pdu_rel15[0].time_domain_assignment = time_domain_assignment; + dci_pdu_rel15[0].vrb_to_prb_mapping = 1; + dci_pdu_rel15[0].mcs = pdsch_pdu_rel15->mcsIndex[0]; + dci_pdu_rel15[0].tb_scaling = 1; + dci_pdu_rel15[0].frequency_hopping_flag = 0; + dci_pdu_rel15[0].ra_preamble_index = ra->preamble_index; + dci_pdu_rel15[0].format_indicator = 1; + dci_pdu_rel15[0].ndi = 1; + dci_pdu_rel15[0].rv = 0; + dci_pdu_rel15[0].harq_pid = 0; + dci_pdu_rel15[0].dai = 2; + dci_pdu_rel15[0].tpc = 2; + dci_pdu_rel15[0].pucch_resource_indicator = 7; + dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator = 7; + + LOG_D(MAC, "[RAPROC] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n", + dci_pdu_rel15[0].frequency_domain_assignment, + pdsch_pdu_rel15->rbStart, + pdsch_pdu_rel15->rbSize, + NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275), + dci_pdu_rel15[0].time_domain_assignment, + dci_pdu_rel15[0].vrb_to_prb_mapping, + dci_pdu_rel15[0].mcs, + dci_pdu_rel15[0].tb_scaling, + dci_pdu_rel15[0].ndi, + dci_pdu_rel15[0].rv); + + nr_configure_pdcch(pdcch_pdu_rel15, 0, scc, bwp); + + LOG_D(MAC, "Frame %d: Subframe %d : Adding common DL DCI for RA_RNTI %x CCEIndex %d\n", frameP, slotP, RA_rnti, CCEIndex); + dci_pdu->RNTI[numDlDci] = RA_rnti; + dci_pdu->AggregationLevel[numDlDci] = aggregation; + dci_pdu->powerControlOffsetSS[numDlDci] = 0; + dci_pdu->CceIndex[numDlDci] = CCEIndex; + dci_pdu->beta_PDCCH_1_0[numDlDci] = 0; + dci_pdu->powerControlOffsetSS[numDlDci] = 1; + + dci_formats[0] = NR_DL_DCI_FORMAT_1_0; + rnti_types[0] = NR_RNTI_RA; + + LOG_D(MAC, "[RAPROC] DCI params: rnti %d, rnti_type %d, dci_format %d coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n", + pdcch_pdu_rel15->dci_pdu.RNTI[0], + rnti_types[0], + dci_formats[0], + (unsigned long long)pdcch_pdu_rel15->FreqDomainResource, + pdcch_pdu_rel15->StartSymbolIndex, + pdcch_pdu_rel15->DurationSymbols); + + dci_pdu->PayloadSizeBits[0] = nr_dci_size(dci_formats[0], rnti_types[0], pdcch_pdu_rel15->BWPSize); + fill_dci_pdu_rel15(pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); + pdcch_pdu_rel15->numDlDci++; + dl_req->nPDUs++; + + // Program UL processing for Msg3 + // nr_get_Msg3alloc(&cc[CC_id], slotP, frameP,&ra->Msg3_frame, &ra->Msg3_slot); + LOG_D(MAC, "Frame %d, Subframe %d: Setting Msg3 reception for Frame %d Subframe %d\n", frameP, slotP, ra->Msg3_frame, ra->Msg3_slot); + nr_fill_rar(ra, cc[CC_id].RAR_pdu.payload, N_RB_UL); + nr_add_msg3(module_idP, CC_id, frameP, slotP); + ra->state = WAIT_Msg3; + LOG_D(MAC,"[gNB %d][RAPROC] Frame %d, Subframe %d: RA state %d\n", module_idP, frameP, slotP, ra->state); + + x_Overhead = 0; + nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead); + + // DL TX request + tx_req->PDU_length = pdsch_pdu_rel15->TBSize[0]; + tx_req->PDU_index = nr_mac->pdu_index[CC_id]++; + tx_req->num_TLV = 1; + tx_req->TLVs[0].length = 8; + nr_mac->TX_req[CC_id].SFN = frameP; + nr_mac->TX_req[CC_id].Number_of_PDUs++; + nr_mac->TX_req[CC_id].Slot = slotP; + memcpy((void*)&tx_req->TLVs[0].value.direct[0], (void*)&cc[CC_id].RAR_pdu.payload[0], tx_req->TLVs[0].length); + } } void nr_clear_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP){ unsigned char i; - NR_RA_t *ra = (NR_RA_t *) &RC.mac[module_idP]->common_channels[CC_id].ra[0]; + NR_RA_t *ra = &RC.mac[module_idP]->common_channels[CC_id].ra[0]; LOG_D(MAC,"[gNB %d][RAPROC] CC_id %d Frame %d Clear Random access information rnti %x\n", module_idP, CC_id, frameP, ra->rnti); ra->state = IDLE; ra->timing_offset = 0; @@ -296,201 +367,160 @@ void nr_clear_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP){ ra->msg3_round = 0; } -unsigned short nr_fill_rar(const module_id_t mod_id, - const int CC_id, - NR_RA_t * ra, - const frame_t frameP, - uint8_t * const dlsch_buffer, - const uint16_t N_RB_UL, - const uint8_t input_buffer_length){ +// todo: +// - handle MAC RAR BI subheader +// - sending only 1 RAR subPDU +// - UL Grant +// - padding +void nr_fill_rar(NR_RA_t * ra, + uint8_t * dlsch_buffer, + uint16_t N_RB_UL){ - RA_HEADER_RAPID *rarh = (NR_RA_HEADER_RAPID *) dlsch_buffer; - uint8_t *rar = (uint8_t *) (dlsch_buffer + 1); + LOG_D(MAC, "[gNB] Generate RAR MAC PDU frame %d slot %d ", ra->Msg2_frame, ra-> Msg2_slot); + NR_RA_HEADER_RAPID *rarh = (NR_RA_HEADER_RAPID *) dlsch_buffer; + NR_MAC_RAR *rar = (NR_MAC_RAR *) (dlsch_buffer + 1); - /* E/T/RAPID subheader - - E = 0, one only RAR, first and last - - T = 1, E/T/RAPID subheader */ + // E/T/RAPID subheader + // E = 0, one only RAR, first and last + // T = 1, RAPID rarh->E = 0; rarh->T = 1; - rarh->RAPID = ra->preamble_index; // TBR Respond to Preamble 0 only for the moment - /* TBR handle MAC RAR BI subheader*/ + rarh->RAPID = ra->preamble_index; - /* TC-RNTI */ - // TBR double check - rar[5] = (uint8_t) (ra->rnti >> 8); - rar[6] = (uint8_t) (ra->rnti & 0xff); - // TBR double check + // RAR MAC payload + rar->R = 0; + rar->TA1 = (uint8_t) (ra->timing_offset >> 5); // 7 MSBs of timing advance + rar->TA2 = (uint8_t) (ra->timing_offset & 0x1f); // 5 LSBs of timing advance + rar->TCRNTI_1 = (uint8_t) (ra->rnti >> 8); // 8 MSBs of rnti + rar->TCRNTI_2 = (uint8_t) (ra->rnti & 0xff); // 8 LSBs of rnti - /* Timing Advance Command */ - // TBR double check - //ra->timing_offset = 0; - //printf("ra->timing_offset %d\n", ra->timing_offset); // TBR remove - - ra->timing_offset /= 16; //T_A = N_TA/16, where N_TA should be on a 30.72Msps - rar[0] = (uint8_t) (ra->timing_offset >> (2 + 4)); // 7 MSBs of timing advance + divide by 4 - rar[1] = (uint8_t) (ra->timing_offset << (4 - 2)) & 0xf0; // 4 LSBs of timing advance + divide by 4 - // TBR double check - - // TBR double check - COMMON_channels_t *cc = &RC.mac[mod_id]->common_channels[CC_id]; - if(N_RB_UL == 25){ - ra->msg3_first_rb = 1; - }else{ - // if (cc->tdd_Config && N_RB_UL == 100) { // TBR missing tdd_Config - // ra->msg3_first_rb = 3; - // } else { - // ra->msg3_first_rb = 2; - // } - } - ra->msg3_nb_rb = 1; - // TBR double check - - /* UL Grant */ - // TBR fix this - uint16_t rballoc = nr_mac_compute_RIV(N_RB_UL, ra->msg3_first_rb, ra->msg3_nb_rb); // first PRB only for UL Grant - rar[1] |= (rballoc >> 7) & 7; // Hopping = 0 (bit 3), 3 MSBs of rballoc - rar[2] = ((uint8_t) (rballoc & 0xff)) << 1; // 7 LSBs of rballoc - ra->msg3_mcs = 10; - ra->msg3_TPC = 3; - ra->msg3_ULdelay = 0; - ra->msg3_cqireq = 0; - ra->msg3_round = 0; - rar[2] |= ((ra->msg3_mcs & 0x8) >> 3); // mcs 10 - rar[3] = (((ra->msg3_mcs & 0x7) << 5)) | ((ra->msg3_TPC & 7) << 2) | ((ra->msg3_ULdelay & 1) << 1) | (ra->msg3_cqireq & 1); - // TBR double check - - return ra->rnti; + // uint16_t rballoc = nr_mac_compute_RIV(N_RB_UL, ra->msg3_first_rb, ra->msg3_nb_rb); // first PRB only for UL Grant + // uint32_t buffer = 0; + // rar->UL_GRANT_1 = (uint8_t) (buffer >> 24) & 0x7; + // rar->UL_GRANT_2 = (uint8_t) (buffer >> 16) & 0xFF; + // rar->UL_GRANT_3 = (uint8_t) (buffer >> 8) & 0xFF; + // rar->UL_GRANT_4 = (uint8_t) buffer & 0xff; } -void nr_add_msg3(module_id_t module_idP, int CC_id, NR_RA_t *ra, frame_t frameP, sub_frame_t subframeP){ +// WIP +void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP){ - #if 0 - eNB_MAC_INST *mac = RC.mac[module_idP]; - COMMON_channels_t *cc = &mac->common_channels[CC_id]; - uint8_t j; - nfapi_ul_config_request_t *ul_req; - nfapi_ul_config_request_body_t *ul_req_body; - nfapi_ul_config_request_pdu_t *ul_config_pdu; - nfapi_hi_dci0_request_t *hi_dci0_req; - nfapi_hi_dci0_request_body_t *hi_dci0_req_body; - nfapi_hi_dci0_request_pdu_t *hi_dci0_pdu; - uint8_t sf_ahead_dl; - uint8_t rvseq[4] = {0, 2, 3, 1}; - ul_req = &mac->UL_req_tmp[CC_id][ra->Msg3_subframe]; - ul_req_body = &ul_req->ul_config_request_body; - AssertFatal(ra->state != IDLE, "RA is not active for RA %X\n", - ra->rnti); -#if (LTE_RRC_VERSION >= MAKE_VERSION(14, 0, 0)) + gNB_MAC_INST *mac = RC.nrmac[module_idP]; + NR_COMMON_channels_t *cc = &mac->common_channels[CC_id]; + NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; + NR_RA_t *ra = &cc->ra[0]; + NR_UE_list_t *UE_list = &mac->UE_list; - if (ra->rach_resource_type > 0) { - LOG_D (MAC, "[eNB %d][RAPROC] Frame %d, Subframe %d : CC_id %d CE level %d is active, Msg3 in (%d,%d)\n", - module_idP, frameP, subframeP, CC_id, ra->rach_resource_type - 1, ra->Msg3_frame, ra->Msg3_subframe); - LOG_D (MAC, "Frame %d, Subframe %d Adding Msg3 UL Config Request for (%d,%d) : (%d,%d)\n", - frameP, subframeP, ra->Msg3_frame, ra->Msg3_subframe, ra->msg3_nb_rb, ra->msg3_round); - ul_config_pdu = &ul_req_body->ul_config_pdu_list[ul_req_body->number_of_pdus]; - memset ((void *) ul_config_pdu, 0, sizeof (nfapi_ul_config_request_pdu_t)); - ul_config_pdu->pdu_type = NFAPI_UL_CONFIG_ULSCH_PDU_TYPE; - ul_config_pdu->pdu_size = (uint8_t) (2 + sizeof (nfapi_ul_config_ulsch_pdu)); - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.handle = mac->ul_handle++; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.rnti = ra->rnti; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.resource_block_start = narrowband_to_first_rb (cc, ra->msg34_narrowband) + ra->msg3_first_rb; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.number_of_resource_blocks = ra->msg3_nb_rb; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.modulation_type = 2; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.cyclic_shift_2_for_drms = 0; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.frequency_hopping_enabled_flag = 0; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.frequency_hopping_bits = 0; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.new_data_indication = 0; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.redundancy_version = rvseq[ra->msg3_round]; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.harq_process_number = 0; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.ul_tx_mode = 0; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.current_tx_nb = 0; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.n_srs = 1; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.size = get_TBS_UL (ra->msg3_mcs, ra->msg3_nb_rb); - // Re13 fields - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel13.ue_type = ra->rach_resource_type > 2 ? 2 : 1; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel13.total_number_of_repetitions = 1; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel13.repetition_number = 1; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel13.initial_transmission_sf_io = (ra->Msg3_frame * 10) + ra->Msg3_subframe; - ul_req_body->number_of_pdus++; - } // if (ra->rach_resource_type>0) { - else -#endif - { - LOG_D(MAC, - "[eNB %d][RAPROC] Frame %d, Subframe %d : CC_id %d RA is active, Msg3 in (%d,%d)\n", - module_idP, frameP, subframeP, CC_id, ra->Msg3_frame, - ra->Msg3_subframe); - LOG_D(MAC, - "Frame %d, Subframe %d Adding Msg3 UL Config Request for (%d,%d) : (%d,%d,%d) for rnti: %d\n", - frameP, subframeP, ra->Msg3_frame, ra->Msg3_subframe, - ra->msg3_nb_rb, ra->msg3_first_rb, ra->msg3_round, ra->rnti); - ul_config_pdu = &ul_req_body->ul_config_pdu_list[ul_req_body->number_of_pdus]; - memset((void *) ul_config_pdu, 0, sizeof(nfapi_ul_config_request_pdu_t)); - ul_config_pdu->pdu_type = NFAPI_UL_CONFIG_ULSCH_PDU_TYPE; - ul_config_pdu->pdu_size = (uint8_t) (2 + sizeof(nfapi_ul_config_ulsch_pdu)); - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.tl.tag = NFAPI_UL_CONFIG_REQUEST_ULSCH_PDU_REL8_TAG; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.handle = mac->ul_handle++; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.rnti = ra->rnti; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.resource_block_start = ra->msg3_first_rb; - AssertFatal(ra->msg3_nb_rb > 0, "nb_rb = 0\n"); - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.number_of_resource_blocks = ra->msg3_nb_rb; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.modulation_type = 2; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.cyclic_shift_2_for_drms = 0; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.frequency_hopping_enabled_flag = 0; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.frequency_hopping_bits = 0; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.new_data_indication = 0; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.redundancy_version = rvseq[ra->msg3_round]; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.harq_process_number = subframe2harqpid(cc, ra->Msg3_frame, ra->Msg3_subframe); - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.ul_tx_mode = 0; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.current_tx_nb = 0; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.n_srs = 1; - ul_config_pdu->ulsch_pdu.ulsch_pdu_rel8.size = get_TBS_UL(10, ra->msg3_nb_rb); - ul_req_body->number_of_pdus++; - ul_req_body->tl.tag = NFAPI_UL_CONFIG_REQUEST_BODY_TAG; - ul_req->sfn_sf = ra->Msg3_frame<<4|ra->Msg3_subframe; - ul_req->header.message_id = NFAPI_UL_CONFIG_REQUEST; + nfapi_nr_ul_tti_request_t *ul_req = &mac->UL_tti_req[0]; + nfapi_nr_ul_dci_request_t *UL_dci_req = &mac->UL_dci_req[0]; + nfapi_nr_pusch_pdu_t *pusch_pdu = &ul_req->pdus_list[0].pusch_pdu; + nfapi_nr_ul_dci_request_pdus_t *ul_dci_request_pdu = &UL_dci_req->ul_dci_pdu_list[UL_dci_req->numPdus]; - // save UL scheduling information for preprocessor - for (j = 0; j < ra->msg3_nb_rb; j++) - cc->vrb_map_UL[ra->msg3_first_rb + j] = 1; + int UE_id = 0, CCEIndex, dci_formats[2], rnti_types[2], bwp_id = 1, coreset_id = 0, aggregation = 4, search_space = 1; - LOG_D(MAC, "MSG3: UL_CONFIG SFN/SF:%d number_of_pdus:%d ra->msg3_round:%d\n", NFAPI_SFNSF2DEC(ul_req->sfn_sf), ul_req_body->number_of_pdus, ra->msg3_round); + AssertFatal(ra->state != IDLE, "RA is not active for RA %X\n", ra->rnti); - if (ra->msg3_round != 0) { // program HI too - sf_ahead_dl = ul_subframe2_k_phich(cc, subframeP); - hi_dci0_req = &mac->HI_DCI0_req[CC_id][(subframeP+sf_ahead_dl)%10]; - hi_dci0_req_body = &hi_dci0_req->hi_dci0_request_body; - hi_dci0_pdu = &hi_dci0_req_body->hi_dci0_pdu_list[hi_dci0_req_body->number_of_dci + hi_dci0_req_body->number_of_hi]; - memset((void *) hi_dci0_pdu, 0, - sizeof(nfapi_hi_dci0_request_pdu_t)); - hi_dci0_pdu->pdu_type = NFAPI_HI_DCI0_HI_PDU_TYPE; - hi_dci0_pdu->pdu_size = 2 + sizeof(nfapi_hi_dci0_hi_pdu); - hi_dci0_pdu->hi_pdu.hi_pdu_rel8.tl.tag = NFAPI_HI_DCI0_REQUEST_HI_PDU_REL8_TAG; - hi_dci0_pdu->hi_pdu.hi_pdu_rel8.resource_block_start = ra->msg3_first_rb; - hi_dci0_pdu->hi_pdu.hi_pdu_rel8.cyclic_shift_2_for_drms = 0; - hi_dci0_pdu->hi_pdu.hi_pdu_rel8.hi_value = 0; - hi_dci0_req_body->number_of_hi++; - hi_dci0_req_body->sfnsf = sfnsf_add_subframe(ra->Msg3_frame, ra->Msg3_subframe, 0); - hi_dci0_req_body->tl.tag = NFAPI_HI_DCI0_REQUEST_BODY_TAG; - hi_dci0_req->sfn_sf = sfnsf_add_subframe(frameP, subframeP, sf_ahead_dl); - hi_dci0_req->header.message_id = NFAPI_HI_DCI0_REQUEST; + // if(N_RB_UL == 25) { + // ra->msg3_first_rb = 1; + // } else { + // if (cc->tdd_Config && N_RB_UL == 100) { + // ra->msg3_first_rb = 3; + // } else { + // ra->msg3_first_rb = 2; + // } + // } + // ra->msg3_nb_rb = 1; + // /* UL Grant */ + // ra->msg3_mcs = 10; + // ra->msg3_TPC = 3; + // ra->msg3_ULdelay = 0; + // ra->msg3_cqireq = 0; + // ra->msg3_round = 0; - if (NFAPI_MODE != NFAPI_MONOLITHIC) { - oai_nfapi_hi_dci0_req(hi_dci0_req); - hi_dci0_req_body->number_of_hi=0; - } + LOG_D(MAC, "[gNB %d][RAPROC] Frame %d, Subframe %d : CC_id %d RA is active, Msg3 in (%d,%d)\n", module_idP, frameP, slotP, CC_id, ra->Msg3_frame, ra->Msg3_slot); - LOG_D(MAC, "MSG3: HI_DCI0 SFN/SF:%d number_of_dci:%d number_of_hi:%d\n", NFAPI_SFNSF2DEC(hi_dci0_req->sfn_sf), hi_dci0_req_body->number_of_dci, hi_dci0_req_body->number_of_hi); + ul_req->SFN = ra->Msg3_frame << 4 | ra->Msg3_slot; // TBR + ul_req->Slot = slotP; + ul_req->n_pdus = 1; + ul_req->pdus_list[0].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE; + ul_req->pdus_list[0].pdu_size = sizeof(nfapi_nr_pusch_pdu_t); + memset(pusch_pdu, 0, sizeof(nfapi_nr_pusch_pdu_t)); - // save UL scheduling information for preprocessor - for (j = 0; j < ra->msg3_nb_rb; j++) - cc->vrb_map_UL[ra->msg3_first_rb + j] = 1; + memset((void*)ul_dci_request_pdu,0,sizeof(nfapi_nr_ul_dci_request_pdus_t)); + ul_dci_request_pdu->PDUType = NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE; + ul_dci_request_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdcch_pdu)); - LOG_D(MAC, - "[eNB %d][PUSCH-RA %x] CC_id %d Frame %d subframeP %d Scheduled (PHICH) RA (mcs %d, first rb %d, nb_rb %d,round %d)\n", - module_idP, ra->rnti, CC_id, frameP, subframeP, 10, 1, 1, - ra->msg3_round - 1); - } // if (ra->msg3_round != 0) { // program HI too - } // non-BL/CE UE case - #endif + nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &ul_dci_request_pdu->pdcch_pdu.pdcch_pdu_rel15; + + AssertFatal(UE_list->active[UE_id] >=0,"Cannot find UE_id %d is not active\n", UE_id); + + NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id]; + AssertFatal(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count == 1, + "downlinkBWP_ToAddModList has %d BWP!\n", secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count); + NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[bwp_id-1]; + NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; + LOG_D(MAC, "Frame %d, Subframe %d Adding Msg3 UL Config Request for (%d,%d) : (%d,%d,%d) for rnti: %d\n", + frameP, + slotP, + ra->Msg3_frame, + ra->Msg3_slot, + ra->msg3_nb_rb, + ra->msg3_first_rb, + ra->msg3_round, + ra->rnti); + + pusch_pdu->pdu_bit_map = PUSCH_PDU_BITMAP_PUSCH_DATA; + pusch_pdu->rnti = ra->rnti; + pusch_pdu->handle = 0; + pusch_pdu->bwp_size = NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275); + pusch_pdu->bwp_start = NRRIV2PRBOFFSET(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275); + pusch_pdu->subcarrier_spacing = ubwp->bwp_Common->genericParameters.subcarrierSpacing; + pusch_pdu->cyclic_prefix = 0; + pusch_pdu->mcs_index = 9; + pusch_pdu->mcs_table = 0; + pusch_pdu->target_code_rate = nr_get_code_rate_ul(pusch_pdu->mcs_index,pusch_pdu->mcs_table); + pusch_pdu->qam_mod_order = nr_get_Qm_ul(pusch_pdu->mcs_index,pusch_pdu->mcs_table); + pusch_pdu->transform_precoding = 0; + pusch_pdu->data_scrambling_id = 0; + pusch_pdu->nrOfLayers = 1; + pusch_pdu->ul_dmrs_symb_pos = 1; + pusch_pdu->dmrs_config_type = 0; + pusch_pdu->ul_dmrs_scrambling_id = 0; //If provided and the PUSCH is not a msg3 PUSCH, otherwise, L2 should set this to physical cell id. // TBR + pusch_pdu->scid = 0; //DMRS sequence initialization [TS38.211, sec 6.4.1.1.1]. Should match what is sent in DCI 0_1, otherwise set to 0. + pusch_pdu->resource_alloc = 1; //type 1 + //pusch_pdu->rb_bitmap;// for ressource alloc type 0 + pusch_pdu->rb_start = ra->msg3_first_rb; + pusch_pdu->rb_size = ra->msg3_nb_rb; + pusch_pdu->vrb_to_prb_mapping = 0; + pusch_pdu->frequency_hopping = 0; + //pusch_pdu->tx_direct_current_location;//The uplink Tx Direct Current location for the carrier. Only values in the value range of this field between 0 and 3299, which indicate the subcarrier index within the carrier corresponding 1o the numerology of the corresponding uplink BWP and value 3300, which indicates "Outside the carrier" and value 3301, which indicates "Undetermined position within the carrier" are used. [TS38.331, UplinkTxDirectCurrentBWP IE] + pusch_pdu->uplink_frequency_shift_7p5khz = 0; + //Resource Allocation in time domain + pusch_pdu->start_symbol_index = 2; + pusch_pdu->nr_of_symbols = 12; + //Optional Data only included if indicated in pduBitmap + pusch_pdu->pusch_data.rv_index = 0; + pusch_pdu->pusch_data.harq_process_id = 0; + pusch_pdu->pusch_data.new_data_indicator = 0; + pusch_pdu->pusch_data.tb_size = nr_compute_tbs(pusch_pdu->mcs_index, + pusch_pdu->target_code_rate, + pusch_pdu->rb_size, + pusch_pdu->nr_of_symbols, + 6, //nb_re_dmrs - not sure where this is coming from - its not in the FAPI + 0, //nb_rb_oh + pusch_pdu->nrOfLayers = 1); + pusch_pdu->pusch_data.num_cb = 0; + + CCEIndex = allocate_nr_CCEs(mac, bwp_id, coreset_id, aggregation, search_space, UE_id, 0); + AssertFatal(CCEIndex >= 0, "CCEIndex is negative\n"); + pdcch_pdu_rel15->dci_pdu.CceIndex[pdcch_pdu_rel15->numDlDci] = CCEIndex; + LOG_D(PHY, "CCEIndex %d\n", pdcch_pdu_rel15->dci_pdu.CceIndex[pdcch_pdu_rel15->numDlDci]); + + LOG_D(MAC,"Configuring ULDCI/PDCCH in %d.%d\n", frameP,slotP); + nr_configure_pdcch(pdcch_pdu_rel15, 1, scc, bwp); + + dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET]; + config_uldci(ubwp, pusch_pdu, pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); + pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[0] = nr_dci_size(dci_formats[0], rnti_types[0], pdcch_pdu_rel15->BWPSize); + fill_dci_pdu_rel15(pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); } \ No newline at end of file diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index f02032b1e7..55ef77dc29 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -1365,62 +1365,6 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){ } */ -/* -boolean_t nr_CCE_allocation_infeasible(int module_idP, int CC_id, int format_flag, int slot, int aggregation, int rnti){ - - gNB_MAC_INST *mac = RC.nrmac[module_idP]; - nfapi_nr_dl_tti_request_body_t *dl_req = &mac->DL_req[CC_id].dl_config_request_body; - nfapi_nr_dl_tti_request_pdu_t *dl_config_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs]; - - nfapi_hi_dci0_request_body_t *HI_DCI0_req = &RC.mac[module_idP]->HI_DCI0_req[CC_id][slot].hi_dci0_request_body; - nfapi_hi_dci0_request_pdu_t *hi_dci0_pdu = &HI_DCI0_req->hi_dci0_pdu_list[HI_DCI0_req->number_of_dci + HI_DCI0_req->number_of_hi]; - - int ret; - boolean_t res = FALSE; - - if (format_flag != 2) { // DL DCI - if (dl_req->number_pdu == MAX_NUM_DL_PDU) { - LOG_W(MAC, - "Subframe %d: FAPI DL structure is full, skip scheduling UE %d\n", - slot, rnti); - } else { - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tl.tag = NFAPI_DL_CONFIG_REQUEST_DCI_DL_PDU_REL8_TAG; - dl_config_pdu->pdu_type = NFAPI_DL_CONFIG_DCI_DL_PDU_TYPE; - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti = rnti; - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type = (format_flag == 0) ? 2 : 1; - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level = aggregation; - dl_req->number_pdu++; - - LOG_D(MAC, "Subframe %d: Checking CCE feasibility format %d : (%x,%d) (%x,%d,%d)\n", - slot, format_flag, rnti, aggregation, - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti, - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8. - aggregation_level, - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type); - - // ret = nr_allocate_CCEs(module_idP, CC_id, 0, slot, 0); // TBR - - if (ret == -1) res = TRUE; - - dl_req->number_pdu--; - } - } else { // ue-specific UL DCI - if (HI_DCI0_req->number_of_dci + HI_DCI0_req->number_of_hi == MAX_NUM_HI_DCI0_PDU) { - LOG_W(MAC, "Subframe %d: FAPI UL structure is full, skip scheduling UE %d\n", slot, rnti); - } else { - hi_dci0_pdu->pdu_type = NFAPI_HI_DCI0_DCI_PDU_TYPE; - hi_dci0_pdu->dci_pdu.dci_pdu_rel8.tl.tag = NFAPI_HI_DCI0_REQUEST_DCI_PDU_REL8_TAG; - hi_dci0_pdu->dci_pdu.dci_pdu_rel8.rnti = rnti; - hi_dci0_pdu->dci_pdu.dci_pdu_rel8.aggregation_level = aggregation; - HI_DCI0_req->number_of_dci++; - // ret = nr_allocate_CCEs(module_idP, CC_id, 0, slot, 0); // TBR - if (ret == -1) res = TRUE; - HI_DCI0_req->number_of_dci--; - } - } - - return res; -}*/ /* // TBR fix this void nr_get_Msg3alloc(NR_COMMON_channels_t *cc, @@ -1531,11 +1475,11 @@ void nr_get_Msg3alloc(NR_COMMON_channels_t *cc, } // else TDD }*/ -uint16_t nr_mac_compute_RIV(uint16_t N_RB_DL, uint16_t RBstart, uint16_t Lcrbs){ // TBR this is outdated - uint16_t RIV; - - if (Lcrbs <= (1 + (N_RB_DL >> 1))) RIV = (N_RB_DL * (Lcrbs - 1)) + RBstart; - else RIV = (N_RB_DL * (N_RB_DL + 1 - Lcrbs)) + (N_RB_DL - 1 - RBstart); - - return RIV; -} \ No newline at end of file +// uint16_t nr_mac_compute_RIV(uint16_t N_RB_DL, uint16_t RBstart, uint16_t Lcrbs){ // TBR +// uint16_t RIV; +// +// if (Lcrbs <= (1 + (N_RB_DL >> 1))) RIV = (N_RB_DL * (Lcrbs - 1)) + RBstart; +// else RIV = (N_RB_DL * (N_RB_DL + 1 - Lcrbs)) + (N_RB_DL - 1 - RBstart); +// +// return RIV; +// } \ No newline at end of file diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index c2ca2dc1fe..16b9924c83 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -98,13 +98,6 @@ void nr_initiate_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP, sub_ void nr_clear_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP); -boolean_t nr_CCE_allocation_infeasible(int module_idP, - int CC_idP, - int common_flag, - int slot, - int aggregation, - int rnti); - int nr_allocate_CCEs(int module_idP, int CC_idP, frame_t frameP, sub_frame_t slotP, int test_only); void nr_get_Msg3alloc(NR_COMMON_channels_t *cc, @@ -113,19 +106,14 @@ void nr_get_Msg3alloc(NR_COMMON_channels_t *cc, frame_t *frame, sub_frame_t *subframe); -/* \brief Function in gNB to fill RAR pdu when requested by PHY. This provides a single RAR SDU for the moment and returns the t-CRNTI. -@param Mod_id Instance ID of gNB -@param dlsch_buffer Pointer to DLSCH input buffer +/* \brief Function in gNB to fill RAR pdu when requested by PHY. +@param ra Instance of RA resources of gNB +@param dlsch_buffer Pointer to RAR input buffer @param N_RB_UL Number of UL resource blocks -@returns t_CRNTI */ -unsigned short nr_fill_rar(const module_id_t module_idP, - const int CC_id, - NR_RA_t *ra, - const frame_t frameP, - uint8_t * const dlsch_buffer, - const uint16_t N_RB_UL, - const uint8_t input_buffer_length); +void nr_fill_rar(NR_RA_t * ra, + uint8_t * dlsch_buffer, + uint16_t N_RB_UL); uint16_t nr_mac_compute_RIV(uint16_t N_RB_DL, uint16_t RBstart, uint16_t Lcrbs); diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index 71d8aa7b15..03aa639bae 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -90,15 +90,15 @@ typedef struct { /// Subframe where preamble was received uint8_t preamble_subframe; /// Subframe where Msg2 is to be sent - uint8_t Msg2_subframe; + uint8_t Msg2_slot; /// Frame where Msg2 is to be sent frame_t Msg2_frame; /// Subframe where Msg3 is to be sent - sub_frame_t Msg3_subframe; + sub_frame_t Msg3_slot; /// Frame where Msg3 is to be sent frame_t Msg3_frame; /// Subframe where Msg4 is to be sent - sub_frame_t Msg4_subframe; + sub_frame_t Msg4_slot; /// Frame where Msg4 is to be sent frame_t Msg4_frame; /// harq_pid used for Msg4 transmission From a70fa82ad8270b18efb67abc0777723b94070663 Mon Sep 17 00:00:00 2001 From: cig Date: Mon, 10 Feb 2020 09:13:55 +0100 Subject: [PATCH 021/553] Removed phy vars members from ue mac inst struct --- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 2 +- openair2/LAYER2/NR_MAC_UE/mac_defs.h | 6 ---- openair2/LAYER2/NR_MAC_UE/mac_proto.h | 2 +- openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c | 3 +- openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 34 +++++++++----------- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 18 ++++++----- 6 files changed, 29 insertions(+), 36 deletions(-) diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 6f7c012670..08626224b0 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -4520,7 +4520,7 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t // ask L2 for RACH transport if ((runmode != rx_calib_ue) && (runmode != rx_calib_ue_med) && (runmode != rx_calib_ue_byp) && (runmode != no_L2_connect) ) { LOG_D(PHY, "Getting PRACH resources. Frame %d Slot %d \n", frame_tx, nr_tti_tx); - ue->prach_resources[gNB_id] = nr_ue_get_rach(mod_id, ue->CC_id, UE_mode, frame_tx, gNB_id, nr_tti_tx); + nr_ue_get_rach(ue->prach_resources[gNB_id], mod_id, ue->CC_id, UE_mode, frame_tx, gNB_id, nr_tti_tx); } } diff --git a/openair2/LAYER2/NR_MAC_UE/mac_defs.h b/openair2/LAYER2/NR_MAC_UE/mac_defs.h index 5e223c5cd2..89e95c35f9 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_defs.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_defs.h @@ -136,8 +136,6 @@ typedef struct { uint8_t RA_prachMaskIndex; /// Flag indicating Preamble set (A,B) used for first Msg3 transmission uint8_t RA_usedGroupA; - /// Random-access Resources - NR_PRACH_RESOURCES_t RA_prach_resources; /// BeamfailurerecoveryConfig NR_BeamFailureRecoveryConfig_t RA_BeamFailureRecoveryConfig; /// Preamble Tx Counter @@ -169,10 +167,6 @@ typedef struct { uint8_t RA_RAPID_found; /// Flag to monitor if BI was received in RAR uint8_t RA_BI_found; - /// UE_Mode variable should be used in the case of Phy_stub operation since we won't have access to PHY_VARS_UE - /// where the UE_mode originally is for the full stack operation mode. The transitions between the states of the UE_Mode - /// will be triggered within phy_stub_ue.c in this case - UE_MODE_t UE_mode[NUMBER_OF_CONNECTED_gNB_MAX]; //// FAPI-like interface message fapi_nr_tx_request_t tx_request; diff --git a/openair2/LAYER2/NR_MAC_UE/mac_proto.h b/openair2/LAYER2/NR_MAC_UE/mac_proto.h index f78b09f5af..17dce1fc23 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_proto.h @@ -185,7 +185,7 @@ int set_tdd_config_nr_ue(fapi_nr_config_request_t *cfg, int mu, @param Mod_id Module id of UE @returns Po_NOMINAL_PUSCH (PREAMBLE_RECEIVED_TARGET_POWER+DELTA_PREAMBLE */ -int8_t nr_get_Po_NOMINAL_PUSCH(module_id_t module_idP, uint8_t CC_id); +int8_t nr_get_Po_NOMINAL_PUSCH(NR_PRACH_RESOURCES_t *prach_resources, module_id_t module_idP, uint8_t CC_id); /** \brief Function to compute DELTA_PREAMBLE from 38.321 subclause 7.3 (for RA power ramping procedure and Msg3 PUSCH power control policy) diff --git a/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c b/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c index a3a00a84b8..b11fc2cca2 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c @@ -133,11 +133,10 @@ int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id){ } /* TS 38.321 subclause 5.1.3 - RA preamble transmission - ra_PREAMBLE_RECEIVED_TARGET_POWER configuration */ -int8_t nr_get_Po_NOMINAL_PUSCH(module_id_t mod_id, uint8_t CC_id){ +int8_t nr_get_Po_NOMINAL_PUSCH(NR_PRACH_RESOURCES_t *prach_resources, module_id_t mod_id, uint8_t CC_id){ NR_UE_MAC_INST_t *nr_UE_mac_inst = get_mac_inst(mod_id); NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = nr_UE_mac_inst->nr_rach_ConfigCommon; - NR_PRACH_RESOURCES_t *prach_resources = &nr_UE_mac_inst->RA_prach_resources; AssertFatal(nr_rach_ConfigCommon != NULL, "[UE %d] CCid %d FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id, CC_id); diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c index 4f50115927..5a98327e00 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -61,8 +61,6 @@ #include "NR_MAC_COMMON/nr_mac.h" #include "LAYER2/NR_MAC_UE/mac_proto.h" -extern UE_MODE_t get_nrUE_mode(uint8_t Mod_id, uint8_t CC_id, uint8_t gNB_id); - extern int64_t table_6_3_3_2_2_prachConfig_Index [256][9]; extern int64_t table_6_3_3_2_3_prachConfig_Index [256][9]; @@ -76,10 +74,10 @@ void nr_get_prach_resources(module_id_t mod_id, uint8_t gNB_id, uint8_t t_id, uint8_t first_Msg3, + NR_PRACH_RESOURCES_t *prach_resources, NR_RACH_ConfigDedicated_t * rach_ConfigDedicated){ NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); - NR_PRACH_RESOURCES_t *prach_resources = &mac->RA_prach_resources; NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = mac->nr_rach_ConfigCommon; // NR_BeamFailureRecoveryConfig_t *beam_failure_recovery_config = &mac->RA_BeamFailureRecoveryConfig; // todo @@ -244,7 +242,7 @@ void nr_get_prach_resources(module_id_t mod_id, if (mac->RA_PREAMBLE_TRANSMISSION_COUNTER > 1) mac->RA_PREAMBLE_TRANSMISSION_COUNTER++; - prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = nr_get_Po_NOMINAL_PUSCH(mod_id, CC_id); + prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = nr_get_Po_NOMINAL_PUSCH(prach_resources, mod_id, CC_id); /* RA-RNTI computation (associated to PRACH occasion in which the RA Preamble is transmitted) // 1) this does not apply to contention-free RA Preamble for beam failure recovery request @@ -324,19 +322,19 @@ void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint /// the RA procedure on a SCell shall only be initiated by PDCCH order // WIP -NR_PRACH_RESOURCES_t *nr_ue_get_rach(module_id_t mod_id, - int CC_id, - UE_MODE_t UE_mode, - frame_t frame, - uint8_t gNB_id, - int nr_tti_tx){ +void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, + module_id_t mod_id, + int CC_id, + UE_MODE_t UE_mode, + frame_t frame, + uint8_t gNB_id, + int nr_tti_tx){ NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); uint8_t lcid = CCCH, dcch_header_len = 0, mac_sdus[MAX_NR_ULSCH_PAYLOAD_BYTES], * payload, ra_ResponseWindow; uint16_t size_sdu = 0; unsigned short post_padding; NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = (struct NR_RACH_ConfigCommon_t *) NULL; - NR_PRACH_RESOURCES_t *prach_resources = &mac->RA_prach_resources; int32_t frame_diff = 0; uint8_t sdu_lcids[NB_RB_MAX] = {0}; // TBR @@ -353,7 +351,7 @@ NR_PRACH_RESOURCES_t *nr_ue_get_rach(module_id_t mod_id, if (mac->nr_rach_ConfigCommon) { // TBR check the condition nr_rach_ConfigCommon = mac->nr_rach_ConfigCommon; - } else return NULL; + } else prach_resources = NULL; if (mac->RA_active == 0) { /* RA not active - checking if RRC is ready to initiate the RA procedure */ @@ -474,7 +472,7 @@ NR_PRACH_RESOURCES_t *nr_ue_get_rach(module_id_t mod_id, } // Fill in preamble and PRACH resources - nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 1, NULL); + nr_get_prach_resources(prach_resources, mod_id, CC_id, gNB_id, nr_tti_tx, 1, NULL); offset = nr_generate_ulsch_pdu((uint8_t *) mac_sdus, // sdus buffer (uint8_t *) payload, // logical channel payload @@ -494,7 +492,7 @@ NR_PRACH_RESOURCES_t *nr_ue_get_rach(module_id_t mod_id, payload[offset + j] = 0; // mac_pdu[offset + j] = 0; } - return (prach_resources); + return; } } else { // RACH is active @@ -570,7 +568,7 @@ NR_PRACH_RESOURCES_t *nr_ue_get_rach(module_id_t mod_id, mac->RA_backoff_cnt = rand() % (prach_resources->RA_PREAMBLE_BACKOFF + 1); mac->RA_PREAMBLE_TRANSMISSION_COUNTER = 1; prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP << 1; // 2 dB increment - prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = nr_get_Po_NOMINAL_PUSCH(mod_id, CC_id); + prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = nr_get_Po_NOMINAL_PUSCH(prach_resources, mod_id, CC_id); } // compute backoff parameters @@ -591,13 +589,13 @@ NR_PRACH_RESOURCES_t *nr_ue_get_rach(module_id_t mod_id, mac->RA_tx_frame = frame; mac->RA_tx_subframe = nr_tti_tx; // Fill in preamble and PRACH resources - nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 0, NULL); - return (&mac->RA_prach_resources); + nr_get_prach_resources(prach_resources, mod_id, CC_id, gNB_id, nr_tti_tx, 0, NULL); + return; } } } else if (UE_mode == PUSCH) { LOG_D(MAC, "[UE %d] FATAL: Should not have checked for RACH in PUSCH yet ...", mod_id); AssertFatal(1 == 0, ""); } - return NULL; + return prach_resources = NULL; } \ No newline at end of file diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index 16b9924c83..092a2df94c 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -271,13 +271,14 @@ andom-access to transmit a BSR along with the C-RNTI control element (see 5.1.4 @param frame @param gNB_id gNB index @param nr_tti_tx slot for PRACH transmission -@returns A pointer to a PRACH_RESOURCES_t */ -NR_PRACH_RESOURCES_t *nr_ue_get_rach(module_id_t mod_id, - int CC_id, - UE_MODE_t UE_mode, - frame_t frame, - uint8_t gNB_id, - int nr_tti_tx); +@returns void */ +void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, + module_id_t mod_id, + int CC_id, + UE_MODE_t UE_mode, + frame_t frame, + uint8_t gNB_id, + int nr_tti_tx); /* \brief Function implementing the routine for the selection of Random Access resources (5.1.2 TS 38.321). @param module_idP Index of UE instance @@ -285,12 +286,13 @@ NR_PRACH_RESOURCES_t *nr_ue_get_rach(module_id_t mod_id, @param gNB_index gNB index @param t_id @param rach_ConfigDedicated -@returns A pointer to a PRACH_RESOURCES_t */ +@returns void */ void nr_get_prach_resources(module_id_t mod_id, int CC_id, uint8_t gNB_id, uint8_t t_id, uint8_t first_Msg3, + NR_PRACH_RESOURCES_t *prach_resources, NR_RACH_ConfigDedicated_t * rach_ConfigDedicated); void nr_Msg1_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id); From 6149d825e2bf4b6006ae364295b293abeba33a32 Mon Sep 17 00:00:00 2001 From: cig Date: Mon, 10 Feb 2020 11:23:37 +0100 Subject: [PATCH 022/553] Msg3 transmitted, flush Msg3 buffer when RA is not active --- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 6 ++++++ openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 19 +++---------------- 2 files changed, 9 insertions(+), 16 deletions(-) diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 08626224b0..8afdd28ce9 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -4520,6 +4520,12 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t // ask L2 for RACH transport if ((runmode != rx_calib_ue) && (runmode != rx_calib_ue_med) && (runmode != rx_calib_ue_byp) && (runmode != no_L2_connect) ) { LOG_D(PHY, "Getting PRACH resources. Frame %d Slot %d \n", frame_tx, nr_tti_tx); + // flush Msg3 Buffer + if (ue->prach_resources[gNB_id]->Msg3 == NULL){ + for(int i = 0; iulsch_Msg3_active[i] = 0; + } + } nr_ue_get_rach(ue->prach_resources[gNB_id], mod_id, ue->CC_id, UE_mode, frame_tx, gNB_id, nr_tti_tx); } } diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c index 5a98327e00..472d1c0b1a 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -302,16 +302,12 @@ void nr_Msg1_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint } void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id){ - #if 0 // TBR AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); - - LOG_D(MAC,"[UE %d][RAPROC] Frame %d : Msg3_tx: Setting contention resolution timer\n", mod_id, frameP); - - // start contention resolution timer + LOG_D(MAC,"[UE %d][RAPROC] Frame %d : Msg3_tx: Starting contention resolution timer\n", mod_id, frameP); + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + // start contention resolution timer mac->RA_contention_resolution_cnt = 0; mac->RA_contention_resolution_timer_active = 1; - - #endif } ///////////////////////////////////////////////////////////////////////// @@ -358,15 +354,6 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, LOG_I(MAC, "RA not active. Starting RA preamble initialization.\n"); - /* TBR flush Msg3 Buffer - this was done like this but at PHY level - for(i=0; iulsch_Msg3_active[i] = 0; - } - */ - mac->RA_RAPID_found = 0; /* Set RA_PREAMBLE_POWER_RAMPING_STEP */ From 9653b954d3891eda58911dc99d069fa72be65557 Mon Sep 17 00:00:00 2001 From: cig Date: Mon, 10 Feb 2020 12:21:18 +0100 Subject: [PATCH 023/553] Contention resolution TS 38.321 ch 5.1.5 --- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 11 +++++ openair2/LAYER2/NR_MAC_UE/mac_proto.h | 4 ++ openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 46 ++++++++++++++++++++ 3 files changed, 61 insertions(+) diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 8afdd28ce9..3427181006 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -3273,6 +3273,17 @@ void nr_process_rar(nr_downlink_indication_t *dl_info) { } } +// if contention resolution fails, go back to UE mode PRACH +void nr_ra_failed(uint8_t Mod_id, uint8_t CC_id, uint8_t gNB_index) { + + PHY_VARS_NR_UE *ue = PHY_vars_UE_g[Mod_id][CC_id]; + ue->UE_mode[gNB_index] = PRACH; + + for (int i=0; i pdcch_vars[i][gNB_index]->pdcch_config[0].rnti = 0; + } + LOG_E(PHY,"[UE %d] [RAPROC] Random-access procedure fails, going back to PRACH\n", Mod_id); +} void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, diff --git a/openair2/LAYER2/NR_MAC_UE/mac_proto.h b/openair2/LAYER2/NR_MAC_UE/mac_proto.h index 17dce1fc23..24ffb7347f 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_proto.h @@ -216,5 +216,9 @@ uint16_t nr_ue_process_rar(module_id_t mod_id, void nr_process_rar(nr_downlink_indication_t *dl_info); +void ue_contention_resolution(module_id_t module_id, uint8_t gNB_index, int cc_id, frame_t tx_frame); + +void nr_ra_failed(uint8_t Mod_id, uint8_t CC_id, uint8_t gNB_index); + #endif /** @}*/ diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 7c99ed36a6..d83baffa33 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -728,6 +728,9 @@ NR_UE_L2_STATE_t nr_ue_scheduler(const module_id_t module_id, */ } + if (mac->RA_contention_resolution_timer_active == 1) { + ue_contention_resolution(module_id, gNB_index, cc_id, tx_frame); + } mac->scheduled_response.dl_config = dl_config; @@ -735,6 +738,49 @@ NR_UE_L2_STATE_t nr_ue_scheduler(const module_id_t module_id, return UE_CONNECTION_OK; } +//////////////////////////////////////////////////////////////////////////// +/////////* Random Access Contention Resolution (5.1.35 TS 38.321) *///////// +//////////////////////////////////////////////////////////////////////////// +// Handling contention resolution timer +// WIP todo: +// - beam failure recovery +// - RA completed + +void ue_contention_resolution(module_id_t module_id, uint8_t gNB_index, int cc_id, frame_t tx_frame){ + + NR_UE_MAC_INST_t *mac = get_mac_inst(module_id); + NR_RACH_ConfigCommon_t *rach_ConfigCommon; + + if (mac->RA_contention_resolution_timer_active == 1) { + if (mac->nr_rach_ConfigCommon) { + rach_ConfigCommon = &mac->nr_rach_ConfigCommon; + } else { + // LOG_E(MAC, "FATAL: radioResourceConfigCommon is NULL!!!\n"); + // VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_SCHEDULER,VCD_FUNCTION_OUT); + // stop_meas(&mac->ue_scheduler); + // AssertFatal(1 == 0, ""); + // #if UE_TIMING_TRACE + // stop_meas(&mac->ue_scheduler); + // #endif + } + + LOG_I(MAC, "Frame %d: Contention resolution timer %d/%ld\n", + tx_frame, + mac->RA_contention_resolution_cnt, + ((1 + rach_ConfigCommon->ra_ContentionResolutionTimer) << 3)); + mac->RA_contention_resolution_cnt++; + + if (mac->RA_contention_resolution_cnt == ((1 + rach_ConfigCommon->ra_ContentionResolutionTimer) << 3)) { + mac->t_crnti = 0; + mac->RA_active = 0; + mac->RA_contention_resolution_timer_active = 0; + // Signal PHY to quit RA procedure + LOG_E(MAC, "[UE %u] [RAPROC] Contention resolution timer expired, RA failed, discarded TC-RNTI\n", module_id); + nr_ra_failed(module_id, cc_id, gNB_index); + } + } +} + #if 0 uint16_t nr_dci_format_size (PHY_VARS_NR_UE *ue, uint8_t slot, From bbc0d1deeb98e077edf741ca506772758c8880c6 Mon Sep 17 00:00:00 2001 From: cig Date: Mon, 10 Feb 2020 13:12:42 +0100 Subject: [PATCH 024/553] Adapted get_nr_PL to be used in RA MAC procedures --- openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h | 2 +- openair1/PHY/NR_UE_ESTIMATION/nr_ue_measurements.c | 8 +++----- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 4 ++-- openair1/SCHED_NR_UE/pucch_power_control_ue_nr.c | 2 +- openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 3 +-- 5 files changed, 8 insertions(+), 11 deletions(-) diff --git a/openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h b/openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h index af06f9a98f..dcb8c675d9 100644 --- a/openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h +++ b/openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h @@ -90,6 +90,6 @@ void phy_adjust_gain_nr(PHY_VARS_NR_UE *ue, uint32_t rx_power_fil_dB, uint8_t eNB_id); -int16_t get_nr_PL(PHY_VARS_NR_UE *ue,uint8_t gNB_index); +int16_t get_nr_PL(uint8_t Mod_id, uint8_t CC_id, uint8_t gNB_index); #endif diff --git a/openair1/PHY/NR_UE_ESTIMATION/nr_ue_measurements.c b/openair1/PHY/NR_UE_ESTIMATION/nr_ue_measurements.c index aa1e2b5ade..860ca11d8c 100644 --- a/openair1/PHY/NR_UE_ESTIMATION/nr_ue_measurements.c +++ b/openair1/PHY/NR_UE_ESTIMATION/nr_ue_measurements.c @@ -55,8 +55,9 @@ void print_ints(char *s,int *x) } #endif -int16_t get_nr_PL(PHY_VARS_NR_UE *ue,uint8_t gNB_index) -{ +int16_t get_nr_PL(uint8_t Mod_id, uint8_t CC_id, uint8_t gNB_index){ + + PHY_VARS_NR_UE *ue = PHY_vars_UE_g[Mod_id][CC_id]; /* if (ue->frame_parms.mode1_flag == 1) @@ -75,9 +76,6 @@ int16_t get_nr_PL(PHY_VARS_NR_UE *ue,uint8_t gNB_index) //(ue->frame_parms.pdsch_config_common.referenceSignalPower*10))/10)); } - - - void nr_ue_measurements(PHY_VARS_NR_UE *ue, unsigned int subframe_offset, unsigned char N0_symbol, diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 3427181006..fef17f7bcf 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -4545,7 +4545,7 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t ue->generate_nr_prach = 1; ue->prach_cnt = 0; - pathloss = get_nr_PL(ue, gNB_id); + pathloss = get_nr_PL(mod_id, ue->CC_id, gNB_id); LOG_I(PHY,"runmode %d\n",runmode); if ((ue->mac_enabled == 1) && (runmode != calib_prach_tx)) { @@ -4591,7 +4591,7 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t LOG_D(PHY,"[UE %d][RAPROC] PRACH PL %d dB, power %d dBm, digital power %d dB (amp %d)\n", ue->Mod_id, - get_nr_PL(ue,gNB_id), + pathloss, ue->tx_power_dBm[nr_tti_tx], dB_fixed(prach_power), ue->prach_vars[gNB_id]->amp); diff --git a/openair1/SCHED_NR_UE/pucch_power_control_ue_nr.c b/openair1/SCHED_NR_UE/pucch_power_control_ue_nr.c index 9632291e67..b51c8afbb0 100644 --- a/openair1/SCHED_NR_UE/pucch_power_control_ue_nr.c +++ b/openair1/SCHED_NR_UE/pucch_power_control_ue_nr.c @@ -104,7 +104,7 @@ int16_t get_pucch_tx_power_ue(PHY_VARS_NR_UE *ue, int P_O_PUCCH = P_O_NOMINAL_PUCCH + P_O_UE_PUCCH; - int16_t PL = get_nr_PL(ue, gNB_id); /* LTE function because NR path loss not yet implemented FFS TODO NR */ + int16_t PL = get_nr_PL(ue->Mod_id, ue->CC_id, gNB_id); /* LTE function because NR path loss not yet implemented FFS TODO NR */ int16_t delta_F_PUCCH = power_config->deltaF_PUCCH_f[pucch_format]; diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c index 472d1c0b1a..e2eb4edf50 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -206,9 +206,8 @@ void nr_get_prach_resources(module_id_t mod_id, // use Group A preamble prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles; mac->RA_usedGroupA = 1; - } else if ((Msg3_size < messageSizeGroupA) && (get_PL(mod_id, 0, gNB_id) > PLThreshold)) { + } else if ((Msg3_size < messageSizeGroupA) && (get_nr_PL(mod_id, CC_id, gNB_id) > PLThreshold)) { // Group B is configured and RA preamble Group A is used - // - todo TBR update get_PL to NR get_nr_PL (needs PHY_VARS_NR_UE) // - todo add condition on CCCH_sdu_size for initiation by CCCH prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; mac->RA_usedGroupA = 1; From 99256c24ce64c1c940f360350d0604e4d7731efb Mon Sep 17 00:00:00 2001 From: cig Date: Mon, 10 Feb 2020 13:47:20 +0100 Subject: [PATCH 025/553] MAC CE contention resolution reception --- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 46 ++++---------------- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 29 ++++++++++++ 2 files changed, 38 insertions(+), 37 deletions(-) diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index fef17f7bcf..54b9096874 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -294,43 +294,6 @@ void nr_dump_dlsch_ra(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id, write_output("dlsch_mag2.m","dlschmag2",ue->pdsch_vars_ra[0]->dl_ch_magb0,300*nsymb,1,1); } -void ra_failed(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index) -{ - - // if contention resolution fails, go back to PRACH - PHY_vars_UE_g[Mod_id][CC_id]->UE_mode[eNB_index] = PRACH; - PHY_vars_UE_g[Mod_id][CC_id]->pdcch_vars[0][eNB_index]->crnti_is_temporary = 0; - PHY_vars_UE_g[Mod_id][CC_id]->pdcch_vars[0][eNB_index]->crnti = 0; - PHY_vars_UE_g[Mod_id][CC_id]->pdcch_vars[1][eNB_index]->crnti_is_temporary = 0; - PHY_vars_UE_g[Mod_id][CC_id]->pdcch_vars[1][eNB_index]->crnti = 0; - LOG_E(PHY,"[UE %d] Random-access procedure fails, going back to PRACH, setting SIStatus = 0, discard temporary C-RNTI and State RRC_IDLE\n",Mod_id); - //mac_xface->macphy_exit(""); -} - -void ra_succeeded(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index) -{ - - int i; - - LOG_I(PHY,"[UE %d][RAPROC] Random-access procedure succeeded. Set C-RNTI = Temporary C-RNTI\n",Mod_id); - - PHY_vars_UE_g[Mod_id][CC_id]->pdcch_vars[0][eNB_index]->crnti_is_temporary = 0; - PHY_vars_UE_g[Mod_id][CC_id]->pdcch_vars[1][eNB_index]->crnti_is_temporary = 0; - PHY_vars_UE_g[Mod_id][CC_id]->ulsch_Msg3_active[eNB_index] = 0; - PHY_vars_UE_g[Mod_id][CC_id]->UE_mode[eNB_index] = PUSCH; - - for (i=0; i<8; i++) { - if (PHY_vars_UE_g[Mod_id][CC_id]->ulsch[eNB_index]->harq_processes[i]) { - PHY_vars_UE_g[Mod_id][CC_id]->ulsch[eNB_index]->harq_processes[i]->status=IDLE; - PHY_vars_UE_g[Mod_id][CC_id]->dlsch[0][eNB_index][0]->harq_processes[i]->round=0; - PHY_vars_UE_g[Mod_id][CC_id]->dlsch[1][eNB_index][0]->harq_processes[i]->round=0; - PHY_vars_UE_g[Mod_id][CC_id]->ulsch[eNB_index]->harq_processes[i]->subframe_scheduling_flag=0; - } - } - - -} - uint8_t nr_is_SR_TXOp(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id) { @@ -3285,6 +3248,15 @@ void nr_ra_failed(uint8_t Mod_id, uint8_t CC_id, uint8_t gNB_index) { LOG_E(PHY,"[UE %d] [RAPROC] Random-access procedure fails, going back to PRACH\n", Mod_id); } +void nr_ra_succeeded(uint8_t Mod_id, + uint8_t CC_id, + uint8_t gNB_index){ + LOG_I(PHY,"[UE %d][RAPROC] RA procedure succeeded. UE set to PUSCH mode\n", Mod_id); + PHY_VARS_NR_UE *ue = PHY_vars_UE_g[Mod_id][CC_id]; + ue->ulsch_Msg3_active[gNB_index] = 0; + ue->UE_mode[gNB_index] = PUSCH; +} + void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB_id, diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index d83baffa33..580871a551 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -3101,6 +3101,7 @@ void nr_ue_process_mac_pdu(module_id_t module_idP, uint8_t *pdu_ptr = pduP, rx_lcid, done = 0; int pdu_len = mac_pdu_len; uint16_t mac_ce_len, mac_subheader_len, mac_sdu_len; + NR_UE_MAC_INST_t *mac = get_mac_inst(module_idP); //NR_UE_MAC_INST_t *UE_mac_inst = get_mac_inst(module_idP); //uint8_t scs = UE_mac_inst->mib->subCarrierSpacingCommon; @@ -3261,7 +3262,35 @@ void nr_ue_process_mac_pdu(module_id_t module_idP, break; case DL_SCH_LCID_CON_RES_ID: // 38.321 Ch6.1.3.3 + // WIP todo: handle CCCH_pdu mac_ce_len = 6; + + LOG_I(MAC, "[UE %d][RAPROC] Frame %d : received contention resolution msg: %x.%x.%x.%x.%x.%x, Terminating RA procedure\n", module_idP, frameP, pdu_ptr[0], pdu_ptr[1], pdu_ptr[2], pdu_ptr[3], pdu_ptr[4], pdu_ptr[5]); + + if (mac->RA_active == 1) { + LOG_I(MAC, "[UE %d][RAPROC] Frame %d : Clearing RA_active flag\n", module_idP, frameP); + mac->RA_active = 0; + // // check if RA procedure has finished completely (no contention) + // tx_sdu = &mac->CCCH_pdu.payload[3]; + // //Note: 3 assumes sizeof(SCH_SUBHEADER_SHORT) + PADDING CE, which is when UL-Grant has TBS >= 9 (64 bits) + // // (other possibility is 1 for TBS=7 (SCH_SUBHEADER_FIXED), or 2 for TBS=8 (SCH_SUBHEADER_FIXED+PADDING or // SCH_SUBHEADER_SHORT) + // for (i = 0; i < 6; i++) + // if (tx_sdu[i] != payload_ptr[i]) { + // LOG_E(MAC, "[UE %d][RAPROC] Contention detected, RA failed\n", module_idP); + // nr_ra_failed(module_idP, CC_id, eNB_index); + // mac->RA_contention_resolution_timer_active = 0; + // return; + // } + LOG_I(MAC, "[UE %d][RAPROC] Frame %d : Cleared contention resolution timer. Set C-RNTI to TC-RNTI\n", + module_idP, + frameP); + mac->RA_contention_resolution_timer_active = 0; + nr_ra_succeeded(module_idP, CC_id, gNB_index); + mac->crnti = mac->t_crnti; + mac->t_crnti = 0; + } + break; + break; case DL_SCH_LCID_PADDING: From 6c61fef362e3073947d5bec488ad8d34b56b7756 Mon Sep 17 00:00:00 2001 From: cig Date: Mon, 10 Feb 2020 13:50:28 +0100 Subject: [PATCH 026/553] Added RA_SUCCEEDED to RA_state_t --- openair2/LAYER2/NR_MAC_UE/mac_defs.h | 3 ++- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/openair2/LAYER2/NR_MAC_UE/mac_defs.h b/openair2/LAYER2/NR_MAC_UE/mac_defs.h index 89e95c35f9..ac87110527 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_defs.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_defs.h @@ -77,7 +77,8 @@ typedef enum { typedef enum { RA_IDLE = 0, WAIT_RAR = 1, - WAIT_CONTENTION_RESOLUTION = 2 + WAIT_CONTENTION_RESOLUTION = 2, + RA_SUCCEEDED = 3 } RA_state_t; /*!\brief Top level UE MAC structure */ diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 580871a551..472b410890 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -3288,6 +3288,7 @@ void nr_ue_process_mac_pdu(module_id_t module_idP, nr_ra_succeeded(module_idP, CC_id, gNB_index); mac->crnti = mac->t_crnti; mac->t_crnti = 0; + mac->ra_state = RA_SUCCEEDED; } break; From 98480e7102d60c36eb2ede8f6df6b5857f8b0250 Mon Sep 17 00:00:00 2001 From: cig Date: Mon, 10 Feb 2020 16:02:55 +0100 Subject: [PATCH 027/553] RA, Updated nr_ue_get_rach: - using LTE function mac_rrc_nr_data_req_ue in noS1 mode - cleanup code, comments - fixes RA procedure - Processing UL MAC PDU according to TS 38.321 ch 6.1: - introduced function for gNB side UL PDU processing - fixed bug in nr_ue_process_mac_pdu --- openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 106 ++++++++------ openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 3 - openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 19 +-- .../LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c | 134 ++++++++++++++++++ 4 files changed, 203 insertions(+), 59 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c index e2eb4edf50..812ef8fd26 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -78,7 +78,7 @@ void nr_get_prach_resources(module_id_t mod_id, NR_RACH_ConfigDedicated_t * rach_ConfigDedicated){ NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); - NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = mac->nr_rach_ConfigCommon; + NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon; // NR_BeamFailureRecoveryConfig_t *beam_failure_recovery_config = &mac->RA_BeamFailureRecoveryConfig; // todo int messagePowerOffsetGroupB, messageSizeGroupA, PLThreshold, sizeOfRA_PreamblesGroupA, numberOfRA_Preambles, frequencyStart, i, deltaPreamble_Msg3; @@ -90,15 +90,15 @@ void nr_get_prach_resources(module_id_t mod_id, //////////* UE Random Access Resource Selection *////////// /////////////////////////////////////////////////////////// - // todo: switch initialisation cases - // - RA initiated by beam failure recovery operation (subclause 5.17 TS 38.321) - // -- SSB selection, set prach_resources->ra_PreambleIndex - // - RA initiated by PDCCH: ra_preamble_index provided by PDCCH && ra_PreambleIndex != 0b000000 - // -- TBR coming from dci_pdu_rel15[0].ra_preamble_index - // -- set PREAMBLE_INDEX to ra_preamble_index - // -- select the SSB signalled by PDCCH - // - RA initiated for SI request: - // -- SSB selection, set prach_resources->ra_PreambleIndex + // todo: + // - switch initialisation cases + // -- RA initiated by beam failure recovery operation (subclause 5.17 TS 38.321) + // --- SSB selection, set prach_resources->ra_PreambleIndex + // -- RA initiated by PDCCH: ra_preamble_index provided by PDCCH && ra_PreambleIndex != 0b000000 + // --- set PREAMBLE_INDEX to ra_preamble_index + // --- select the SSB signalled by PDCCH + // -- RA initiated for SI request: + // --- SSB selection, set prach_resources->ra_PreambleIndex // if (rach_ConfigDedicated) { // This is for network controlled Mobility // // operation for contention-free RA resources when: @@ -109,12 +109,16 @@ void nr_get_prach_resources(module_id_t mod_id, // } //////////* Contention-based RA preamble selection *////////// - // todo + // todo: // - selection of SSB with SS-RSRP above rsrp-ThresholdSSB else select any SSB // - todo determine next available PRACH occasion // rsrp_ThresholdSSB = *nr_rach_ConfigCommon->rsrp_ThresholdSSB; + AssertFatal(mac->nr_rach_ConfigCommon != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); + + nr_rach_ConfigCommon = mac->nr_rach_ConfigCommon; + Msg3_size = mac->RA_Msg3_size; numberOfRA_Preambles = nr_rach_ConfigCommon->totalNumberOfRA_Preambles; @@ -162,7 +166,6 @@ void nr_get_prach_resources(module_id_t mod_id, } /* Power offset for preamble selection in dB */ - /* TBR: what value to use as default? Shall it be converted ? */ messagePowerOffsetGroupB = -9999; switch (nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB){ case 0: @@ -237,16 +240,16 @@ void nr_get_prach_resources(module_id_t mod_id, // todo: // - condition on notification of suspending power ramping counter from lower layer (5.1.3 TS 38.321) // - check if SSB or CSI-RS have not changed since the selection in the last RA Preamble tranmission + // - Extend RA_rnti computation (e.g. f_id selection, ul_carrier_id are hardcoded) if (mac->RA_PREAMBLE_TRANSMISSION_COUNTER > 1) mac->RA_PREAMBLE_TRANSMISSION_COUNTER++; prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = nr_get_Po_NOMINAL_PUSCH(prach_resources, mod_id, CC_id); - /* RA-RNTI computation (associated to PRACH occasion in which the RA Preamble is transmitted) + // RA-RNTI computation (associated to PRACH occasion in which the RA Preamble is transmitted) // 1) this does not apply to contention-free RA Preamble for beam failure recovery request // 2) getting star_symb, SFN_nbr from table 6.3.3.2-3 (TDD and FR1 scenario) - // 3) TBR extend this (e.g. f_id selection, ul_carrier_id are hardcoded) */ switch (nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FDM){ // todo this is not used case 0: @@ -287,6 +290,7 @@ void nr_get_prach_resources(module_id_t mod_id, } } prach_resources->ra_RNTI = 1 + s_id + 14 * t_id + 1120 * f_id + 8960 * ul_carrier_id; + mac->ra_rnti = prach_resources->ra_RNTI; LOG_D(MAC, "Computed ra_RNTI is %d", prach_resources->ra_RNTI); } @@ -317,6 +321,18 @@ void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint /// the RA procedure on a SCell shall only be initiated by PDCCH order // WIP +// todo TS 38.321: +// - check if carrier to use is explicitly signalled then do (1) RA CARRIER SELECTION (SUL, NUL) (2) set PCMAX +// - BWP operation (subclause 5.15 TS 38.321) +// - handle initialization by beam failure recovery +// - handle initialization by handover +// - handle transmission on DCCH using PRACH (during handover, or sending SR for example) +// - take into account MAC CEs in size_sdu (currently hardcoded size to 1 MAC subPDU and 1 padding subheader) +// - fix rrc data req logic +// - retrieve TBS +// - add mac_rrc_nr_data_req_ue, etc ... +// - add the backoff condition here if we have it from a previous RA reponse which failed (i.e. backoff indicator) + void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, module_id_t mod_id, int CC_id, @@ -326,15 +342,15 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, int nr_tti_tx){ NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); - uint8_t lcid = CCCH, dcch_header_len = 0, mac_sdus[MAX_NR_ULSCH_PAYLOAD_BYTES], * payload, ra_ResponseWindow; + uint8_t lcid = UL_SCH_LCID_CCCH_MSG3, dcch_header_len = 0, *mac_sdus, *payload, ra_ResponseWindow; uint16_t size_sdu = 0; unsigned short post_padding; NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = (struct NR_RACH_ConfigCommon_t *) NULL; int32_t frame_diff = 0; - uint8_t sdu_lcids[NB_RB_MAX] = {0}; // TBR - uint16_t sdu_lengths[NB_RB_MAX] = {0}; // TBR - int TBS_bytes = 848, header_length_total, num_sdus, offset, preambleTransMax; // TBR + uint8_t sdu_lcids[NB_RB_MAX] = {0}; + uint16_t sdu_lengths[NB_RB_MAX] = {0}; + int TBS_bytes = 848, header_length_total, num_sdus, offset, preambleTransMax, mac_ce_len; AssertFatal(CC_id == 0,"Transmission on secondary CCs is not supported yet\n"); @@ -344,7 +360,7 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, AssertFatal(mac->nr_rach_ConfigCommon != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); - if (mac->nr_rach_ConfigCommon) { // TBR check the condition + if (mac->nr_rach_ConfigCommon != NULL) { nr_rach_ConfigCommon = mac->nr_rach_ConfigCommon; } else prach_resources = NULL; @@ -375,38 +391,36 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, prach_resources->RA_SCALING_FACTOR_BI = 1; prach_resources->RA_PCMAX = 0; // currently hardcoded to 0 - // todo: - // - check if carrier to use is explicitly signalled then do (1) RA CARRIER SELECTION (SUL, NUL) (2) set PCMAX - // - BWP operation (subclause 5.15 TS 38.321) - // - handle initialization by beam failure recovery - // - handle initialization by handover + payload = &mac->CCCH_pdu.payload; + + mac_ce_len = 0; + num_sdus = 1; + post_padding = 1; if (!IS_SOFTMODEM_NOS1){ - // todo mac_rrc_nr_data_req_ue - payload = &mac->CCCH_pdu.payload; - size_sdu = (uint16_t) mac_rrc_nr_data_req_ue(mod_id, - CC_id, - frame, - CCCH, - payload[sizeof(NR_MAC_SUBHEADER_SHORT) + 1]); - + // initialisation by RRC + // CCCH PDU + mac_sdus = payload[sizeof(NR_MAC_SUBHEADER_SHORT)]; + size_sdu = (uint16_t) mac_rrc_data_req_ue(mod_id, + CC_id, + frame, + CCCH, + 1, + mac_sdus, + gNB_id, + 0); LOG_D(MAC,"[UE %d] Frame %d: Requested RRCConnectionRequest, got %d bytes\n", mod_id,frame, size_sdu); - - // todo: else triggers a transmission on DCCH using PRACH (during handover, or sending SR for example) - } else { // fill ulsch_buffer with random data - payload = (uint8_t *)mac->ulsch_pdu.payload[0]; for (int i = 0; i < TBS_bytes; i++){ mac_sdus[i] = (unsigned char) (lrand48()&0xff); } //Sending SDUs with size 1 //Initialize elements of sdu_lcids and sdu_lengths - sdu_lcids[0] = UL_SCH_LCID_DTCH; - sdu_lengths[0] = TBS_bytes - 3; + sdu_lcids[0] = lcid; + sdu_lengths[0] = TBS_bytes - 3 - post_padding - mac_ce_len; header_length_total += 2 + (sdu_lengths[0] >= 128); size_sdu += sdu_lengths[0]; - num_sdus +=1; } mac->RA_tx_frame = frame; @@ -414,17 +428,15 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, mac->RA_backoff_frame = frame; mac->RA_backoff_subframe = nr_tti_tx; - if (size_sdu > 0) { // TBR size_sdu + MAC_Header_len + mac_ce_len - /* TBR initialisation by RRC - // PDU from CCCH */ + if (size_sdu > 0) { LOG_I(MAC, "[UE %d] Frame %d: Initialisation Random Access Procedure\n", mod_id, frame); mac->RA_PREAMBLE_TRANSMISSION_COUNTER = 1; mac->RA_PREAMBLE_POWER_RAMPING_COUNTER = 1; - mac->RA_Msg3_size = size_sdu + sizeof(NR_MAC_SUBHEADER_SHORT) + sizeof(NR_MAC_SUBHEADER_SHORT); // TBR size_sdu + MAC_Header_len + mac_ce_len + mac->RA_Msg3_size = size_sdu + sizeof(NR_MAC_SUBHEADER_SHORT) + sizeof(NR_MAC_SUBHEADER_SHORT); mac->RA_prachMaskIndex = 0; - // TBR todo: add the backoff condition here if we have it from a previous RA reponse which failed (i.e. backoff indicator) + // todo: add the backoff condition here mac->RA_backoff_cnt = 0; mac->RA_active = 1; prach_resources->Msg3 = payload; @@ -461,7 +473,7 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, nr_get_prach_resources(prach_resources, mod_id, CC_id, gNB_id, nr_tti_tx, 1, NULL); offset = nr_generate_ulsch_pdu((uint8_t *) mac_sdus, // sdus buffer - (uint8_t *) payload, // logical channel payload + (uint8_t *) payload, // UL MAC pdu pointer num_sdus, // num sdus sdu_lengths, // sdu length sdu_lcids, // sdu lcid @@ -470,9 +482,9 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, 0, // truncated bsr 0, // short bsr 0, // long_bsr - 1); // post_padding + post_padding); // post_padding - // Padding: fill remainder of DLSCH with 0 + // Padding: fill remainder with 0 if (post_padding > 0){ for (int j = 0; j < (TBS_bytes - offset); j++) payload[offset + j] = 0; // mac_pdu[offset + j] = 0; diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 472b410890..4c05ea3c70 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -3290,9 +3290,6 @@ void nr_ue_process_mac_pdu(module_id_t module_idP, mac->t_crnti = 0; mac->ra_state = RA_SUCCEEDED; } - break; - - break; case DL_SCH_LCID_PADDING: done = 1; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index 074eda8ea8..208d45762f 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -46,11 +46,12 @@ void nr_add_subframe(uint16_t *frameP, uint16_t *slotP, int offset){ *slotP = ((*slotP + offset) % 10); } -// TBR +// WIP // handles the event of msg1 reception // todo: // - offset computation // - fix nr_add_subframe +// - msg2 time location void nr_initiate_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP, @@ -96,17 +97,15 @@ void nr_initiate_ra_proc(module_id_t module_idP, ra->Msg2_frame = msg2_frame; ra->Msg2_slot = msg2_slot; + // ra->Msg2_slot = (slotP + offset) % 10; LOG_D(MAC, "%s() Msg2[%04d%d] SFN/SF:%04d%d offset:%d\n", __FUNCTION__, ra->Msg2_frame, ra->Msg2_slot, frameP, slotP, offset); - ra->Msg2_slot = (slotP + offset) % 10; // TBR this is done twice ? - do { - ra->rnti = taus(); // todo 5.1.3 TS 38.321 + ra->rnti = (taus() % 65518) + 1; loop++; } - // Range coming from 5.1.3 TS 38.321 - while (loop != 100 && !(find_nr_UE_id(module_idP, ra->rnti) == -1 && ra->rnti >= 1 && ra->rnti <= 17920)); + while (loop != 100 && !(find_nr_UE_id(module_idP, ra->rnti) == -1 && ra->rnti >= 1 && ra->rnti <= 65519)); if (loop == 100) { LOG_E(MAC,"%s:%d:%s: [RAPROC] initialisation random access aborted\n", __FILE__, __LINE__, __FUNCTION__); abort(); @@ -137,7 +136,6 @@ void nr_initiate_ra_proc(module_id_t module_idP, VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_INITIATE_RA_PROC, 0); } -// WIP void nr_schedule_RA(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ //uint8_t i = 0; @@ -166,6 +164,7 @@ void nr_schedule_RA(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ } // WIP +// todo: fix void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, @@ -367,6 +366,7 @@ void nr_clear_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP){ ra->msg3_round = 0; } +// WIP // todo: // - handle MAC RAR BI subheader // - sending only 1 RAR subPDU @@ -403,6 +403,7 @@ void nr_fill_rar(NR_RA_t * ra, } // WIP +// todo: fix void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP){ gNB_MAC_INST *mac = RC.nrmac[module_idP]; @@ -439,7 +440,7 @@ void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t LOG_D(MAC, "[gNB %d][RAPROC] Frame %d, Subframe %d : CC_id %d RA is active, Msg3 in (%d,%d)\n", module_idP, frameP, slotP, CC_id, ra->Msg3_frame, ra->Msg3_slot); - ul_req->SFN = ra->Msg3_frame << 4 | ra->Msg3_slot; // TBR + ul_req->SFN = ra->Msg3_frame << 4 | ra->Msg3_slot; ul_req->Slot = slotP; ul_req->n_pdus = 1; ul_req->pdus_list[0].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE; @@ -485,7 +486,7 @@ void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t pusch_pdu->nrOfLayers = 1; pusch_pdu->ul_dmrs_symb_pos = 1; pusch_pdu->dmrs_config_type = 0; - pusch_pdu->ul_dmrs_scrambling_id = 0; //If provided and the PUSCH is not a msg3 PUSCH, otherwise, L2 should set this to physical cell id. // TBR + pusch_pdu->ul_dmrs_scrambling_id = 0; //If provided and the PUSCH is not a msg3 PUSCH, otherwise, L2 should set this to physical cell id. pusch_pdu->scid = 0; //DMRS sequence initialization [TS38.211, sec 6.4.1.1.1]. Should match what is sent in DCI 0_1, otherwise set to 0. pusch_pdu->resource_alloc = 1; //type 1 //pusch_pdu->rb_bitmap;// for ressource alloc type 0 diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c index 604664f3ef..cf8aafc345 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c @@ -70,3 +70,137 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP, UE_scheduling_control->ta_update = timing_advance; } } + +// WIP +// todo: complete +// TS 38.321 ch 6.1 Protocol Data Units - UL-SCH +void nr_process_mac_pdu(module_id_t module_idP, + uint8_t CC_id, + frame_t frameP, + uint8_t *pduP, + uint16_t mac_pdu_len, + uint8_t UE_id){ + + uint8_t *pdu_ptr = pduP, rx_lcid, done = 0; + int pdu_len = mac_pdu_len; + uint16_t mac_ce_len, mac_subheader_len, mac_sdu_len; + + // For both DL/UL-SCH + // Except: + // - UL/DL-SCH: fixed-size MAC CE(known by LCID) + // - UL/DL-SCH: padding + // - UL-SCH: MSG3 48-bits + // |0|1|2|3|4|5|6|7| bit-wise + // |R|F| LCID | + // | L | + // |0|1|2|3|4|5|6|7| bit-wise + // |R|F| LCID | + // | L | + // | L | + + // For both DL/UL-SCH + // For: + // - UL/DL-SCH: fixed-size MAC CE(known by LCID) + // - UL/DL-SCH: padding, for single/multiple 1-oct padding CE(s) + // - UL-SCH: MSG3 48-bits + // |0|1|2|3|4|5|6|7| bit-wise + // |R|R| LCID | + // LCID: The Logical Channel ID field identifies the logical channel instance of the corresponding MAC SDU or the type of the corresponding MAC CE or padding as described in Tables 6.2.1-1 and 6.2.1-2 for the DL-SCH and UL-SCH respectively. There is one LCID field per MAC subheader. The LCID field size is 6 bits; + // L: The Length field indicates the length of the corresponding MAC SDU or variable-sized MAC CE in bytes. There is one L field per MAC subheader except for subheaders corresponding to fixed-sized MAC CEs and padding. The size of the L field is indicated by the F field; + // F: lenght of L is 0:8 or 1:16 bits wide + // R: Reserved bit, set to zero. + + while (!done && pdu_len > 0){ + mac_ce_len = 0x0000; + mac_subheader_len = 0x0001; // default to fixed-length subheader = 1-oct + mac_sdu_len = 0x0000; + rx_lcid = ((NR_MAC_SUBHEADER_FIXED *)pdu_ptr)->LCID; + + switch(rx_lcid){ + // MAC CEs + case UL_SCH_LCID_RECOMMENDED_BITRATE_QUERY: + // 38.321 Ch6.1.3.20 + mac_ce_len = 2; + break; + case UL_SCH_LCID_MULTI_ENTRY_PHR_4_OCT: + // 38.321 Ch6.1.3.9 + // variable length + // todo + break; + case UL_SCH_LCID_CONFIGURED_GRANT_CONFIRMATION: + // 38.321 Ch6.1.3.7 + break; + case UL_SCH_LCID_MULTI_ENTRY_PHR_1_OCT: + // 38.321 Ch6.1.3.9 + // variable length + // todo + break; + case UL_SCH_LCID_SINGLE_ENTRY_PHR: + // 38.321 Ch6.1.3.8 + mac_ce_len = 2; + break; + case UL_SCH_LCID_C_RNTI: + // 38.321 Ch6.1.3.2 + mac_ce_len = 2; + break; + case UL_SCH_LCID_S_TRUNCATED_BSR: + // 38.321 Ch6.1.3.1 + // fixed length + mac_ce_len = 1; + break; + case UL_SCH_LCID_L_TRUNCATED_BSR: + // 38.321 Ch6.1.3.1 + // variable length + // todo + break; + case UL_SCH_LCID_S_BSR: + // 38.321 Ch6.1.3.1 + // fixed length + mac_ce_len = 1; + break; + case UL_SCH_LCID_L_BSR: + // 38.321 Ch6.1.3.1 + // variable length + // todo + break; + case UL_SCH_LCID_PADDING: + done = 1; + // end of MAC PDU, can ignore the rest. + break; + + // MAC SDUs + case UL_SCH_LCID_SRB1: + // todo + break; + case UL_SCH_LCID_SRB2: + // todo + break; + case UL_SCH_LCID_SRB3: + // todo + break; + case UL_SCH_LCID_CCCH_MSG3: + case UL_SCH_LCID_CCCH: + // todo + mac_subheader_len = 2; + break; + case UL_SCH_LCID_DTCH: + // todo + default: + if(((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->F){ + //mac_sdu_len |= (uint16_t)(((NR_MAC_SUBHEADER_LONG *)pdu_ptr)->L2)<<8; + mac_subheader_len = 3; + mac_sdu_len = ((uint16_t)(((NR_MAC_SUBHEADER_LONG *) pdu_ptr)->L1 & 0x7f) << 8) | ((uint16_t)((NR_MAC_SUBHEADER_LONG *) pdu_ptr)->L2 & 0xff); + + } else { + mac_sdu_len = (uint16_t)((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->L; + mac_subheader_len = 2; + } + // todo + break; + } + pdu_ptr += ( mac_subheader_len + mac_ce_len + mac_sdu_len ); + pdu_len -= ( mac_subheader_len + mac_ce_len + mac_sdu_len ); + + AssertFatal(pdu_len >= 0, "[MAC] nr_process_mac_pdu, residual mac pdu length < 0!\n"); + } +} \ No newline at end of file From 7e25d85f5cea59dd8f8d992a4d421e49e8a54b75 Mon Sep 17 00:00:00 2001 From: cig Date: Mon, 10 Feb 2020 17:30:14 +0100 Subject: [PATCH 028/553] Cleanup code, comments --- openair1/PHY/INIT/nr_parms.c | 2 +- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 46 ++++--- openair2/LAYER2/NR_MAC_COMMON/nr_mac.h | 10 -- openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h | 1 - openair2/LAYER2/NR_MAC_UE/mac_defs.h | 10 +- openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c | 8 +- openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 2 +- .../NR_MAC_UE/nr_ue_dci_configuration.c | 2 +- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 3 - openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 4 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 6 +- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 121 +----------------- openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 5 - openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c | 10 +- openair2/RRC/NR/rrc_gNB.c | 2 +- 15 files changed, 45 insertions(+), 187 deletions(-) diff --git a/openair1/PHY/INIT/nr_parms.c b/openair1/PHY/INIT/nr_parms.c index edeb630dee..70fa9e824f 100644 --- a/openair1/PHY/INIT/nr_parms.c +++ b/openair1/PHY/INIT/nr_parms.c @@ -344,7 +344,7 @@ int nr_init_frame_parms_ue(NR_DL_FRAME_PARMS *fp, fp->ssb_start_subcarrier = (12 * config->ssb_table.ssb_offset_point_a + sco); - // TBR temporary hardcoded + // WIP temporary hardcoded fp->prach_config_common.rootSequenceIndex = 22; // 0 fp->prach_config_common.prach_Config_enabled = 1; fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig = 1; // 13 diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 54b9096874..6191676d88 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -1313,6 +1313,8 @@ void nr_process_timing_advance(module_id_t Mod_id, uint8_t CC_id, uint8_t ta_com LOG_D(PHY, "[UE %d] Got timing advance command %u from MAC, new value is %u\n", Mod_id, ta_command, PHY_vars_UE_g[Mod_id][CC_id]->timing_advance); } +// WIP +// - todo: handle TA application as per ch 4.2 TS 38.213 void nr_process_timing_advance_rar(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint16_t ta_command) { int factor_mu = 1 << ue->frame_parms.numerology_index; @@ -1322,8 +1324,6 @@ void nr_process_timing_advance_rar(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, // Transmission timing adjustment (TS 38.213 p4.2) ue->timing_advance = bw_scaling / factor_mu; - // TBR todo handle TA application as per ch 4.2 TS 38.213 - LOG_D(PHY, "[UE %d] Frame %d Slot %d, Received (RAR) timing advance command %d new value is %u \n", ue->Mod_id, proc->frame_rx, proc->nr_tti_rx, ta_command, ue->timing_advance); } @@ -3115,7 +3115,7 @@ void nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB } } -// WIP TBR fix: +// WIP fix: // - time domain indication hardcoded to 0 for k2 offset // - extend TS 38.213 ch 8.3 Msg3 PUSCH // - b buffer @@ -4481,30 +4481,32 @@ uint8_t nr_is_ri_TXOp(PHY_VARS_NR_UE *ue, return(0); } +// WIP +// todo: +// - set tx_total_RE +// - power control as per 38.213 ch 7.4 void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t gNB_id, runmode_t runmode) { - /* TBR - // here params are hardcoded */ + int frame_tx = proc->frame_tx, nr_tti_tx = proc->nr_tti_tx, prach_power; uint16_t preamble_tx = 50, pathloss; - NR_PRACH_RESOURCES_t prach_resources; uint8_t mod_id = ue->Mod_id; UE_MODE_t UE_mode = get_nrUE_mode(mod_id, ue->CC_id, gNB_id); + NR_PRACH_RESOURCES_t * prach_resources = ue->prach_resources[gNB_id]; VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_IN); ue->generate_nr_prach = 0; if (ue->mac_enabled == 0){ - ue->prach_resources[gNB_id] = &prach_resources; // TBR double check pointer - ue->prach_resources[gNB_id]->ra_PreambleIndex = preamble_tx; - ue->prach_resources[gNB_id]->ra_TDD_map_index = 0; - ue->prach_resources[gNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER = 10; // TBR - ue->prach_resources[gNB_id]->ra_RNTI = 93; // TBR NR_UE_MAC_INST_t + prach_resources->ra_PreambleIndex = preamble_tx; + prach_resources->ra_TDD_map_index = 0; + prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = 10; + prach_resources->ra_RNTI = 0x1234; } else { // ask L2 for RACH transport if ((runmode != rx_calib_ue) && (runmode != rx_calib_ue_med) && (runmode != rx_calib_ue_byp) && (runmode != no_L2_connect) ) { LOG_D(PHY, "Getting PRACH resources. Frame %d Slot %d \n", frame_tx, nr_tti_tx); // flush Msg3 Buffer - if (ue->prach_resources[gNB_id]->Msg3 == NULL){ + if (prach_resources->Msg3 == NULL){ for(int i = 0; iulsch_Msg3_active[i] = 0; } @@ -4518,26 +4520,23 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t ue->generate_nr_prach = 1; ue->prach_cnt = 0; pathloss = get_nr_PL(mod_id, ue->CC_id, gNB_id); - LOG_I(PHY,"runmode %d\n",runmode); + LOG_D(PHY,"runmode %d\n",runmode); if ((ue->mac_enabled == 1) && (runmode != calib_prach_tx)) { - // todo power control as per 38.213 ch 7.4 - ue->tx_power_dBm[nr_tti_tx] = ue->prach_resources[gNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER + pathloss; - ue->tx_power_dBm[nr_tti_tx] = ue->tx_power_max_dBm; - ue->prach_resources[gNB_id]->ra_PreambleIndex = preamble_tx; + ue->tx_power_dBm[nr_tti_tx] = prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER + pathloss; } - LOG_D(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d : Generating PRACH, preamble %d, PL %d, P0_PRACH %d, TARGET_RECEIVED_POWER %d dBm, RA-RNTI %d\n", + LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d : Generating PRACH, preamble %d, PL %d, P0_PRACH %d, TARGET_RECEIVED_POWER %d dBm, RA-RNTI %d\n", ue->Mod_id, frame_tx, nr_tti_tx, - ue->prach_resources[gNB_id]->ra_PreambleIndex, + prach_resources->ra_PreambleIndex, pathloss, ue->tx_power_dBm[nr_tti_tx], - ue->prach_resources[gNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER, - ue->prach_resources[gNB_id]->ra_RNTI); + prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER, + prach_resources->ra_RNTI); - ue->tx_total_RE[nr_tti_tx] = 96; /* todo TBR double check */ + //ue->tx_total_RE[nr_tti_tx] = 96; // todo #if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706) ue->prach_vars[gNB_id]->amp = get_tx_amp_prach(ue->tx_power_dBm[nr_tti_tx], @@ -4554,7 +4553,6 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t ue->tx_power_dBm[nr_tti_tx], ue->prach_vars[gNB_id]->amp); - // start_meas(&ue->tx_prach); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GENERATE_PRACH, VCD_FUNCTION_IN); prach_power = generate_nr_prach(ue, gNB_id, nr_tti_tx); @@ -4576,7 +4574,7 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t frame_tx, nr_tti_tx, gNB_id, - ue->prach_resources[gNB_id]->ra_PreambleIndex, + prach_resources->ra_PreambleIndex, ue->tx_power_dBm[nr_tti_tx], pathloss); } diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h index 82418f360e..4c3db7cfe9 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h @@ -137,16 +137,6 @@ typedef struct { uint8_t R2:6; } __attribute__ ((__packed__)) NR_SINGLE_ENTRY_PHR_MAC_CE; -// /*! \brief CCCH payload */ // TBR -// typedef struct { -// uint8_t payload[CCCH_PAYLOAD_SIZE_MAX]; -// } __attribute__ ((__packed__)) CCCH_PDU; -// -// /*! \brief RAR payload */ // TBR -// typedef struct { -// uint8_t payload[RAR_PAYLOAD_SIZE_MAX]; -// } __attribute__ ((__packed__)) RAR_PDU; - //* RAR MAC subheader // TS 38.321 ch. 6.1.5, 6.2.2 *// // - E: The Extension field is a flag indicating if the MAC subPDU including this MAC subheader is the last MAC subPDU or not in the MAC PDU // - T: The Type field is a flag indicating whether the MAC subheader contains a Random Access Preamble ID or a Backoff Indicator (0, BI) (1, RAPID) diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h index 4bc462f759..7892dff6f0 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h @@ -32,7 +32,6 @@ #ifndef __NR_MAC_EXTERN_H__ #define __NR_MAC_EXTERN_H__ -#include "RRC/LTE/rrc_defs.h" // TBR #include "common/ran_context.h" #include "nr_mac.h" diff --git a/openair2/LAYER2/NR_MAC_UE/mac_defs.h b/openair2/LAYER2/NR_MAC_UE/mac_defs.h index ac87110527..9b53e0de3f 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_defs.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_defs.h @@ -48,7 +48,7 @@ /* MAC */ #include "LAYER2/NR_MAC_COMMON/nr_mac.h" #include "LAYER2/NR_MAC_COMMON/nr_mac_common.h" -#include "LAYER2/MAC/mac.h" // TBR +#include "LAYER2/MAC/mac.h" /* RRC */ #include "NR_DRX-Config.h" @@ -116,15 +116,15 @@ typedef struct { /* Random Access parameters */ /// state of RA procedure - RA_state_t ra_state; // TBR + RA_state_t ra_state; /// RACH ConfigCommon NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon; /// RA-rnti - uint16_t ra_rnti; // TBR + uint16_t ra_rnti; /// Temporary CRNTI - uint16_t t_crnti; // TBR + uint16_t t_crnti; /// CRNTI - uint16_t crnti; // TBR + uint16_t crnti; /// number of attempt for rach uint8_t RA_attempt_number; /// Random-access procedure flag diff --git a/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c b/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c index b11fc2cca2..20113f494c 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c @@ -29,12 +29,14 @@ */ -#include "PHY/defs_common.h" // TBR #include "PHY/defs_nr_common.h" #include "mac_defs.h" #include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" +// WIP todo: +//- frame_type and fr are hardcoded. Retireve from fp + /* TS 38.321 subclause 7.3 - return DELTA_PREAMBLE values in dB */ int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id){ @@ -44,8 +46,8 @@ int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id){ AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); uint8_t preambleFormat, prachConfigIndex; - lte_frame_type_t frame_type = TDD; // TODO TBR retrieve frame type. Currently hardcoded to TDD. - nr_frequency_range_e fr = nr_FR1; // TODO TBR retrieve frame type. Currently hardcoded to FR1. + lte_frame_type_t frame_type = TDD; + nr_frequency_range_e fr = nr_FR1; int mu; // SCS configuration from msg1_SubcarrierSpacing and table 4.2-1 in TS 38.211 diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c index 812ef8fd26..142ef097d0 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -295,7 +295,7 @@ void nr_get_prach_resources(module_id_t mod_id, LOG_D(MAC, "Computed ra_RNTI is %d", prach_resources->ra_RNTI); } -// todo: RA_attempt_number not used TBR +// TbD: RA_attempt_number not used void nr_Msg1_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id){ AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c index d595116979..421c8eb75b 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c @@ -114,7 +114,7 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_ if (mac->ra_state == WAIT_RAR) { // check for RAR rel15 = &dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15; - rel15->rnti = 2;//get_RA_RNTI(mac,frame,slot); // TBR + rel15->rnti = 2;//get_RA_RNTI(mac,frame,slot); // WIP dl_config->number_pdus = dl_config->number_pdus + 1; } else if (mac->ra_state == WAIT_CONTENTION_RESOLUTION) { diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 4c05ea3c70..8219a96ea2 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -44,9 +44,6 @@ #include "NR_MAC_UE/mac_extern.h" #include "common/utils/nr/nr_common.h" -//#include "LAYER2/MAC/mac_vars.h" // TBR Note that mac_vars.h is not NR specific and this should be updated - // also, the use of the same should be updated in nr-softmodem and nr-uesoftmodem - /* PHY UE */ #include "SCHED_NR_UE/defs.h" #include "PHY/defs_nr_UE.h" diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index 3258628b7f..a1119e6c10 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -365,10 +365,10 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, schedule_nr_mib(module_idP, frame_txP, slot_txP); } - // TBR once RACH is available, start ta_timer when UE is connected + // TbD once RACH is available, start ta_timer when UE is connected if (ue_sched_ctl->ta_timer) ue_sched_ctl->ta_timer--; - if (ue_sched_ctl->ta_timer == 0) { // TBR check phy_test (see below) + if (ue_sched_ctl->ta_timer == 0) { gNB->ta_command = ue_sched_ctl->ta_update; /* if time is up, then set the timer to not send it for 5 frames // regardless of the TA value */ diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index 208d45762f..dd268d5dd6 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -164,7 +164,9 @@ void nr_schedule_RA(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ } // WIP -// todo: fix +// todo: +// - fix me +// - get msg3 alloc (see nr_process_rar) void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, @@ -333,7 +335,7 @@ void nr_generate_Msg2(module_id_t module_idP, dl_req->nPDUs++; // Program UL processing for Msg3 - // nr_get_Msg3alloc(&cc[CC_id], slotP, frameP,&ra->Msg3_frame, &ra->Msg3_slot); + // nr_get_Msg3alloc(&cc[CC_id], slotP, frameP,&ra->Msg3_frame, &ra->Msg3_slot); // todo LOG_D(MAC, "Frame %d, Subframe %d: Setting Msg3 reception for Frame %d Subframe %d\n", frameP, slotP, ra->Msg3_frame, ra->Msg3_slot); nr_fill_rar(ra, cc[CC_id].RAR_pdu.payload, N_RB_UL); nr_add_msg3(module_idP, CC_id, frameP, slotP); diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 55ef77dc29..36430bd30e 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -1363,123 +1363,4 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){ } } } -*/ - - -/* // TBR fix this -void nr_get_Msg3alloc(NR_COMMON_channels_t *cc, - sub_frame_t current_subframe, // TBR sub_frame_t - frame_t current_frame, - frame_t *frame, - sub_frame_t *subframe){ - // Fill in other TDD Configuration!!!! - - // TBR missing ‘tdd_Config’ in NR_COMMON_channels_t - if (cc->tdd_Config == NULL) { // FDD - *subframe = current_subframe + 6; - if (*subframe > 9) { - *subframe = *subframe - 10; - *frame = (current_frame + 1) & 1023; - } else { - *frame = current_frame; - } - } else { // TDD - if (cc->tdd_Config->subframeAssignment == 1) { - switch (current_subframe) { - - case 0: - *subframe = 7; - *frame = current_frame; - break; - - case 4: - *subframe = 2; - *frame = (current_frame + 1) & 1023; - break; - - case 5: - *subframe = 2; - *frame = (current_frame + 1) & 1023; - break; - - case 9: - *subframe = 7; - *frame = (current_frame + 1) & 1023; - break; - } - } else if (cc->tdd_Config->subframeAssignment == 3) { - switch (current_subframe) { - - case 0: - case 5: - case 6: - *subframe = 2; - *frame = (current_frame + 1) & 1023; - break; - - case 7: - *subframe = 3; - *frame = (current_frame + 1) & 1023; - break; - - case 8: - *subframe = 4; - *frame = (current_frame + 1) & 1023; - break; - - case 9: - *subframe = 2; - *frame = (current_frame + 2) & 1023; - break; - } - } else if (cc->tdd_Config->subframeAssignment == 4) { - switch (current_subframe) { - - case 0: - case 4: - case 5: - case 6: - *subframe = 2; - *frame = (current_frame + 1) & 1023; - break; - - case 7: - *subframe = 3; - *frame = (current_frame + 1) & 1023; - break; - - case 8: - case 9: - *subframe = 2; - *frame = (current_frame + 2) & 1023; - break; - } - } else if (cc->tdd_Config->subframeAssignment == 5) { - switch (current_subframe){ - case 0: - case 4: - case 5: - case 6: - *subframe = 2; - *frame = (current_frame + 1) & 1023; - break; - - case 7: - case 8: - case 9: - *subframe = 2; - *frame = (current_frame + 2) & 1023; - break; - } - } - } // else TDD -}*/ - -// uint16_t nr_mac_compute_RIV(uint16_t N_RB_DL, uint16_t RBstart, uint16_t Lcrbs){ // TBR -// uint16_t RIV; -// -// if (Lcrbs <= (1 + (N_RB_DL >> 1))) RIV = (N_RB_DL * (Lcrbs - 1)) + RBstart; -// else RIV = (N_RB_DL * (N_RB_DL + 1 - Lcrbs)) + (N_RB_DL - 1 - RBstart); -// -// return RIV; -// } \ No newline at end of file +*/ \ No newline at end of file diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index 03aa639bae..524b4d67c5 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -133,11 +133,6 @@ typedef struct { int msg4_TBsize; /// MCS used for Msg4 int msg4_mcs; - /// - int32_t crnti_rrc_mui; // TBR - /// - int8_t crnti_harq_pid; // TBR - } NR_RA_t; /*! \brief gNB common channels */ diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c index d1ca2b02bd..f9967dba2e 100644 --- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c @@ -93,10 +93,7 @@ int8_t handle_dlsch (module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_n */ } -int8_t handle_rar (nr_downlink_indication_t *dl_info, - uint8_t *pduP, - uint32_t pdu_len, - NR_UL_TIME_ALIGNMENT_t *ul_time_alignment){ // TBR not used params +int8_t handle_rar (nr_downlink_indication_t *dl_info){ LOG_D(MAC, "handling RAR at MAC layer \n"); nr_process_rar (dl_info); @@ -263,10 +260,7 @@ int nr_ue_dl_indication(nr_downlink_indication_t *dl_info, NR_UL_TIME_ALIGNMENT_ break; case FAPI_NR_RX_PDU_TYPE_RAR: - ret_mask |= (handle_rar(dl_info, - (dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu, - (dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu_length, - ul_time_alignment)) << FAPI_NR_RX_PDU_TYPE_RAR; + ret_mask |= (handle_rar(dl_info)) << FAPI_NR_RX_PDU_TYPE_RAR; break; default: diff --git a/openair2/RRC/NR/rrc_gNB.c b/openair2/RRC/NR/rrc_gNB.c index 189bf73aba..b0989d843b 100644 --- a/openair2/RRC/NR/rrc_gNB.c +++ b/openair2/RRC/NR/rrc_gNB.c @@ -199,7 +199,7 @@ static void init_NR_SI(gNB_RRC_INST *rrc) { rrc->carrier.pdsch_AntennaPorts, (NR_ServingCellConfigCommon_t *)rrc->carrier.servingcellconfigcommon, 0, - 0, // TBR hardcoded rnti + 0, // WIP hardcoded rnti (NR_CellGroupConfig_t *)NULL ); From 9c79e7e353c30efef823f9465a5cdc04725f8b6a Mon Sep 17 00:00:00 2001 From: cig Date: Tue, 11 Feb 2020 14:45:44 +0100 Subject: [PATCH 029/553] Fixed compilation after rebase --- openair1/PHY/INIT/nr_init_ue.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/openair1/PHY/INIT/nr_init_ue.c b/openair1/PHY/INIT/nr_init_ue.c index a559b35e7e..39bc3afb45 100644 --- a/openair1/PHY/INIT/nr_init_ue.c +++ b/openair1/PHY/INIT/nr_init_ue.c @@ -941,8 +941,6 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue, ue->decode_MIB = 1; ue->decode_SIB = 1; - ue->ssb_periodicity = 5; // initialization of ssb periodicity to 5ms according to TS38.213 section 4.1 - init_nr_prach_tables(839); return 0; From 794348e0b9a344b26360f24ff69a9963e6c15f9d Mon Sep 17 00:00:00 2001 From: cig Date: Tue, 11 Feb 2020 14:50:03 +0100 Subject: [PATCH 030/553] Removed unnecessary return in gnb phytest scheduler (was followed by assert on same condition) --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index f392aec7ed..9b8f329400 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -528,8 +528,6 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, UE_id, 0); // m - if (CCEIndex == -1) return; - AssertFatal(CCEIndex>0,"CCEIndex is negative\n"); int CCEIndices[2]; CCEIndices[0] = CCEIndex; From 498ce5fede472ef95b471dc47417c5a41b83fb3c Mon Sep 17 00:00:00 2001 From: cig Date: Tue, 11 Feb 2020 16:41:59 +0100 Subject: [PATCH 031/553] Fixed wanrnings nrUE compilation --- openair1/PHY/TOOLS/nr_phy_scope.c | 6 +-- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 8 ++-- openair2/LAYER2/NR_MAC_UE/mac_proto.h | 42 +++++++++++++++++++ openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c | 6 +-- openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 38 +++++++++-------- .../NR_MAC_UE/nr_ue_dci_configuration.c | 1 + openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 38 +++++++++-------- openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c | 40 +++++++++--------- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 40 ------------------ 9 files changed, 116 insertions(+), 103 deletions(-) diff --git a/openair1/PHY/TOOLS/nr_phy_scope.c b/openair1/PHY/TOOLS/nr_phy_scope.c index 40803c30f4..e0fa894d92 100644 --- a/openair1/PHY/TOOLS/nr_phy_scope.c +++ b/openair1/PHY/TOOLS/nr_phy_scope.c @@ -157,9 +157,9 @@ void phy_scope_gNB(FD_phy_scope_gnb *form, { int i, arx; //int i,i2,arx,atx,ind,k; NR_DL_FRAME_PARMS *frame_parms = &phy_vars_gnb->frame_parms; - int nsymb_ce = 12*frame_parms->N_RB_UL*frame_parms->symbols_per_tti; + //int nsymb_ce = 12*frame_parms->N_RB_UL*frame_parms->symbols_per_tti; uint8_t nb_antennas_rx = frame_parms->nb_antennas_rx; - uint8_t nb_antennas_tx = 1; // frame_parms->nb_antennas_tx; // in LTE Rel. 8 and 9 only a single transmit antenna is assumed at the UE + //uint8_t nb_antennas_tx = 1; // frame_parms->nb_antennas_tx; // in LTE Rel. 8 and 9 only a single transmit antenna is assumed at the UE int16_t **rxsig_t, **rxsig_f; // int16_t **chest_t=NULL; // int16_t **chest_f=NULL; @@ -966,7 +966,7 @@ FD_stats_form * create_form_stats_form( void ) { } void startScope(scopeParms_t * p) { - FD_stats_form *form_stats=NULL,*form_stats_l2=NULL; + //FD_stats_form *form_stats=NULL,*form_stats_l2=NULL; char title[255]; fl_initialize (p->argc, p->argv, NULL, 0, 0); /* diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 6191676d88..801a135782 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -3127,8 +3127,8 @@ void nr_process_rar(nr_downlink_indication_t *dl_info) { module_id_t module_id = dl_info->module_id; int cc_id = dl_info->cc_id, frame_rx = dl_info->proc->frame_rx, nr_tti_rx = dl_info->proc->nr_tti_rx, ta_command, k2, delta; - uint8_t gNB_index = dl_info->gNB_index, *rar; - fapi_nr_dci_indication_t *dci_ind = dl_info->dci_ind; + uint8_t gNB_index = dl_info->gNB_index; // *rar; + //fapi_nr_dci_indication_t *dci_ind = dl_info->dci_ind; PHY_VARS_NR_UE *ue = PHY_vars_UE_g[module_id][cc_id]; NR_UE_DLSCH_t *dlsch0 = ue->dlsch_ra[gNB_index]; UE_MODE_t UE_mode = ue->UE_mode[gNB_index]; @@ -3182,7 +3182,7 @@ void nr_process_rar(nr_downlink_indication_t *dl_info) { nr_process_timing_advance_rar(ue, dl_info->proc, ta_command); - if (UE_mode != debug_prach) { + if (ue->mode != debug_prach) { ue->ulsch_Msg3_active[gNB_index] = 1; // TS 38.213 ch 8.3 Msg3 PUSCH // PUSCH time domain resource allocation A for normal CP @@ -3551,6 +3551,8 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, case PDSCH: rx_ind.rx_indication_body[0].pdu_type = FAPI_NR_RX_PDU_TYPE_DLSCH; break; + default: + break; } rx_ind.rx_indication_body[0].pdsch_pdu.pdu = dlsch0->harq_processes[harq_pid]->b; diff --git a/openair2/LAYER2/NR_MAC_UE/mac_proto.h b/openair2/LAYER2/NR_MAC_UE/mac_proto.h index 24ffb7347f..580e3c438d 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_proto.h @@ -194,6 +194,8 @@ int8_t nr_get_Po_NOMINAL_PUSCH(NR_PRACH_RESOURCES_t *prach_resources, module_id_ */ int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id); +/* Random Access */ + /* \brief Function called by PHY to process the received RAR and check that the preamble matches what was sent by the gNB. It provides the timing advance and t-CRNTI. @param Mod_id Index of UE instance @param CC_id Index to a component carrier @@ -220,5 +222,45 @@ void ue_contention_resolution(module_id_t module_id, uint8_t gNB_index, int cc_i void nr_ra_failed(uint8_t Mod_id, uint8_t CC_id, uint8_t gNB_index); +void nr_ra_succeeded(uint8_t Mod_id, uint8_t CC_id, uint8_t gNB_index); + +/* \brief Function called by PHY to retrieve information to be transmitted using the RA procedure. +If the UE is not in PUSCH mode for a particular eNB index, this is assumed to be an Msg3 and MAC +attempts to retrieves the CCCH message from RRC. If the UE is in PUSCH mode for a particular eNB +index and PUCCH format 0 (Scheduling Request) is not activated, the MAC may use this resource for +andom-access to transmit a BSR along with the C-RNTI control element (see 5.1.4 from 36.321) +@param mod_id Index of UE instance +@param CC_id Component Carrier Index +@param frame +@param gNB_id gNB index +@param nr_tti_tx slot for PRACH transmission +@returns void */ +void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, + module_id_t mod_id, + int CC_id, + UE_MODE_t UE_mode, + frame_t frame, + uint8_t gNB_id, + int nr_tti_tx); + +/* \brief Function implementing the routine for the selection of Random Access resources (5.1.2 TS 38.321). +@param module_idP Index of UE instance +@param CC_id Component Carrier Index +@param gNB_index gNB index +@param t_id +@param rach_ConfigDedicated +@returns void */ +void nr_get_prach_resources(module_id_t mod_id, + int CC_id, + uint8_t gNB_id, + uint8_t t_id, + uint8_t first_Msg3, + NR_PRACH_RESOURCES_t *prach_resources, + NR_RACH_ConfigDedicated_t * rach_ConfigDedicated); + +void nr_Msg1_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id); + +void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id); + #endif /** @}*/ diff --git a/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c b/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c index 20113f494c..e61e58c764 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c @@ -33,6 +33,7 @@ #include "mac_defs.h" #include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" +#include "LAYER2/NR_MAC_UE/mac_proto.h" // WIP todo: //- frame_type and fr are hardcoded. Retireve from fp @@ -52,7 +53,7 @@ int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id){ // SCS configuration from msg1_SubcarrierSpacing and table 4.2-1 in TS 38.211 - NR_SubcarrierSpacing_t scs = nr_rach_ConfigCommon->msg1_SubcarrierSpacing; + NR_SubcarrierSpacing_t scs = *nr_rach_ConfigCommon->msg1_SubcarrierSpacing; switch (scs){ case NR_SubcarrierSpacing_kHz15: @@ -88,7 +89,7 @@ int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id){ break; default: - AssertFatal(1 == 0,"Unknown msg1_SubcarrierSpacing %d\n", scs); + AssertFatal(1 == 0,"Unknown msg1_SubcarrierSpacing %lu\n", scs); } // Preamble formats given by prach_ConfigurationIndex and tables 6.3.3.2-2 and 6.3.3.2-2 in TS 38.211 @@ -131,7 +132,6 @@ int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id){ default: AssertFatal(1 == 0, "[UE %d] ue_procedures.c: FATAL, Illegal preambleFormat %d, prachConfigIndex %d\n", mod_id, preambleFormat, prachConfigIndex); } - return; } /* TS 38.321 subclause 5.1.3 - RA preamble transmission - ra_PREAMBLE_RECEIVED_TARGET_POWER configuration */ diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c index 142ef097d0..eaaa47df25 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -55,6 +55,7 @@ #include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" #include "PHY/defs_common.h" #include "PHY/defs_nr_common.h" +#include "PHY/NR_UE_ESTIMATION/nr_estimation.h" /* MAC */ #include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" @@ -81,7 +82,7 @@ void nr_get_prach_resources(module_id_t mod_id, NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon; // NR_BeamFailureRecoveryConfig_t *beam_failure_recovery_config = &mac->RA_BeamFailureRecoveryConfig; // todo - int messagePowerOffsetGroupB, messageSizeGroupA, PLThreshold, sizeOfRA_PreamblesGroupA, numberOfRA_Preambles, frequencyStart, i, deltaPreamble_Msg3; + int messagePowerOffsetGroupB, messageSizeGroupA, PLThreshold, sizeOfRA_PreamblesGroupA, numberOfRA_Preambles, i, deltaPreamble_Msg3; uint8_t noGroupB = 0, s_id, f_id, ul_carrier_id, msg1_FDM, prach_ConfigIndex, SFN_nbr, Msg3_size; // NR_RSRP_Range_t rsrp_ThresholdSSB; // todo @@ -120,7 +121,7 @@ void nr_get_prach_resources(module_id_t mod_id, nr_rach_ConfigCommon = mac->nr_rach_ConfigCommon; Msg3_size = mac->RA_Msg3_size; - numberOfRA_Preambles = nr_rach_ConfigCommon->totalNumberOfRA_Preambles; + numberOfRA_Preambles = *nr_rach_ConfigCommon->totalNumberOfRA_Preambles; if (!nr_rach_ConfigCommon->groupBconfigured) { noGroupB = 1; @@ -161,7 +162,7 @@ void nr_get_prach_resources(module_id_t mod_id, messageSizeGroupA = 72; break; default: - AssertFatal(1 == 0,"Unknown ra_Msg3SizeGroupA %d\n", nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA); + AssertFatal(1 == 0,"Unknown ra_Msg3SizeGroupA %lu\n", nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA); /* todo cases 10 -15*/ } @@ -193,7 +194,7 @@ void nr_get_prach_resources(module_id_t mod_id, messagePowerOffsetGroupB = 18; break; default: - AssertFatal(1 == 0,"Unknown messagePowerOffsetGroupB %d\n", nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB); + AssertFatal(1 == 0,"Unknown messagePowerOffsetGroupB %lu\n", nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB); } // todo Msg3-DeltaPreamble should be provided from higher layers, otherwise is 0 @@ -222,7 +223,9 @@ void nr_get_prach_resources(module_id_t mod_id, mac->RA_usedGroupA = 0; } } else { // Msg3 is being retransmitted - if (mac->RA_usedGroupA == 1) { + if (mac->RA_usedGroupA == 1 && noGroupB == 1) { + prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles; + } else if (mac->RA_usedGroupA == 1 && noGroupB == 0){ prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; } else { prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); @@ -265,7 +268,7 @@ void nr_get_prach_resources(module_id_t mod_id, msg1_FDM = 8; break; default: - AssertFatal(1 == 0,"Unknown msg1_FDM %d\n", nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FDM); + AssertFatal(1 == 0,"Unknown msg1_FDM %lu\n", nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FDM); } prach_ConfigIndex = nr_rach_ConfigCommon->rach_ConfigGeneric.prach_ConfigurationIndex; @@ -299,7 +302,7 @@ void nr_get_prach_resources(module_id_t mod_id, void nr_Msg1_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id){ AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); - mac->ra_state == WAIT_RAR; + mac->ra_state = WAIT_RAR; // Start contention resolution timer mac->RA_attempt_number++; } @@ -342,11 +345,11 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, int nr_tti_tx){ NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); - uint8_t lcid = UL_SCH_LCID_CCCH_MSG3, dcch_header_len = 0, *mac_sdus, *payload, ra_ResponseWindow; + uint8_t lcid = UL_SCH_LCID_CCCH_MSG3, *mac_sdus, *payload, ra_ResponseWindow; uint16_t size_sdu = 0; unsigned short post_padding; - NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = (struct NR_RACH_ConfigCommon_t *) NULL; - int32_t frame_diff = 0; + NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = (NR_RACH_ConfigCommon_t *) NULL; + // int32_t frame_diff = 0; uint8_t sdu_lcids[NB_RB_MAX] = {0}; uint16_t sdu_lengths[NB_RB_MAX] = {0}; @@ -391,7 +394,7 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, prach_resources->RA_SCALING_FACTOR_BI = 1; prach_resources->RA_PCMAX = 0; // currently hardcoded to 0 - payload = &mac->CCCH_pdu.payload; + payload = (uint8_t*) &mac->CCCH_pdu.payload; mac_ce_len = 0; num_sdus = 1; @@ -400,7 +403,7 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, if (!IS_SOFTMODEM_NOS1){ // initialisation by RRC // CCCH PDU - mac_sdus = payload[sizeof(NR_MAC_SUBHEADER_SHORT)]; + mac_sdus = &payload[sizeof(NR_MAC_SUBHEADER_SHORT)]; size_sdu = (uint16_t) mac_rrc_data_req_ue(mod_id, CC_id, frame, @@ -470,7 +473,7 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, } // Fill in preamble and PRACH resources - nr_get_prach_resources(prach_resources, mod_id, CC_id, gNB_id, nr_tti_tx, 1, NULL); + nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 1, prach_resources, NULL); offset = nr_generate_ulsch_pdu((uint8_t *) mac_sdus, // sdus buffer (uint8_t *) payload, // UL MAC pdu pointer @@ -514,7 +517,7 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, } if (mac->RA_window_cnt > 0 && mac->RA_RAPID_found == 1) { - mac->ra_state == WAIT_CONTENTION_RESOLUTION; + mac->ra_state = WAIT_CONTENTION_RESOLUTION; } else { LOG_I(MAC, "[MAC][UE %d][RAPROC] Frame %d: subframe %d: RAR reception not successful, (RA window count %d) \n", mod_id, @@ -565,7 +568,7 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, LOG_D(MAC, "[UE %d] Frame %d: Maximum number of RACH attempts (%d)\n", mod_id, frame, preambleTransMax); mac->RA_backoff_cnt = rand() % (prach_resources->RA_PREAMBLE_BACKOFF + 1); mac->RA_PREAMBLE_TRANSMISSION_COUNTER = 1; - prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP << 1; // 2 dB increment + prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP += prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP << 1; // 2 dB increment prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = nr_get_Po_NOMINAL_PUSCH(prach_resources, mod_id, CC_id); } @@ -587,7 +590,7 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, mac->RA_tx_frame = frame; mac->RA_tx_subframe = nr_tti_tx; // Fill in preamble and PRACH resources - nr_get_prach_resources(prach_resources, mod_id, CC_id, gNB_id, nr_tti_tx, 0, NULL); + nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 0, prach_resources, NULL); return; } } @@ -595,5 +598,6 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, LOG_D(MAC, "[UE %d] FATAL: Should not have checked for RACH in PUSCH yet ...", mod_id); AssertFatal(1 == 0, ""); } - return prach_resources = NULL; + prach_resources = NULL; + return; } \ No newline at end of file diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c index 421c8eb75b..8c3ccfce5e 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c @@ -35,6 +35,7 @@ #include "assertions.h" #include "LAYER2/NR_MAC_UE/mac_extern.h" #include "mac_defs.h" +#include "common/utils/nr/nr_common.h" #include #ifdef NR_PDCCH_DCI_TOOLS_DEBUG diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 8219a96ea2..0cd4c27c30 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -37,6 +37,9 @@ /* exe */ #include "executables/nr-softmodem.h" +/* RRC*/ +#include "RRC/NR_UE/rrc_proto.h" + /* MAC */ #include "mac_defs.h" #include "NR_MAC_COMMON/nr_mac.h" @@ -746,11 +749,11 @@ NR_UE_L2_STATE_t nr_ue_scheduler(const module_id_t module_id, void ue_contention_resolution(module_id_t module_id, uint8_t gNB_index, int cc_id, frame_t tx_frame){ NR_UE_MAC_INST_t *mac = get_mac_inst(module_id); - NR_RACH_ConfigCommon_t *rach_ConfigCommon; + NR_RACH_ConfigCommon_t *rach_ConfigCommon = (NR_RACH_ConfigCommon_t *) NULL; if (mac->RA_contention_resolution_timer_active == 1) { if (mac->nr_rach_ConfigCommon) { - rach_ConfigCommon = &mac->nr_rach_ConfigCommon; + rach_ConfigCommon = mac->nr_rach_ConfigCommon; } else { // LOG_E(MAC, "FATAL: radioResourceConfigCommon is NULL!!!\n"); // VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_SCHEDULER,VCD_FUNCTION_OUT); @@ -761,19 +764,21 @@ void ue_contention_resolution(module_id_t module_id, uint8_t gNB_index, int cc_i // #endif } - LOG_I(MAC, "Frame %d: Contention resolution timer %d/%ld\n", - tx_frame, - mac->RA_contention_resolution_cnt, - ((1 + rach_ConfigCommon->ra_ContentionResolutionTimer) << 3)); - mac->RA_contention_resolution_cnt++; + if (rach_ConfigCommon){ + LOG_I(MAC, "Frame %d: Contention resolution timer %d/%ld\n", + tx_frame, + mac->RA_contention_resolution_cnt, + ((1 + rach_ConfigCommon->ra_ContentionResolutionTimer) << 3)); + mac->RA_contention_resolution_cnt++; - if (mac->RA_contention_resolution_cnt == ((1 + rach_ConfigCommon->ra_ContentionResolutionTimer) << 3)) { - mac->t_crnti = 0; - mac->RA_active = 0; - mac->RA_contention_resolution_timer_active = 0; - // Signal PHY to quit RA procedure - LOG_E(MAC, "[UE %u] [RAPROC] Contention resolution timer expired, RA failed, discarded TC-RNTI\n", module_id); - nr_ra_failed(module_id, cc_id, gNB_index); + if (mac->RA_contention_resolution_cnt == ((1 + rach_ConfigCommon->ra_ContentionResolutionTimer) << 3)) { + mac->t_crnti = 0; + mac->RA_active = 0; + mac->RA_contention_resolution_timer_active = 0; + // Signal PHY to quit RA procedure + LOG_E(MAC, "[UE %u] [RAPROC] Contention resolution timer expired, RA failed, discarded TC-RNTI\n", module_id); + nr_ra_failed(module_id, cc_id, gNB_index); + } } } } @@ -1958,7 +1963,7 @@ int nr_ue_process_dci_indication_pdu(module_id_t module_id,int cc_id, int gNB_in dci->rnti,dci->dci_format,dci->n_CCE,dci->payloadSize,*(unsigned long long*)dci->payloadBits); nr_extract_dci_info(mac,dci->dci_format,dci->payloadSize,dci->rnti,(uint64_t *)dci->payloadBits,&dci_pdu_rel15); - nr_ue_process_dci(module_id, cc_id, gNB_index, &dci_pdu_rel15, dci->rnti, dci->dci_format); + return (nr_ue_process_dci(module_id, cc_id, gNB_index, &dci_pdu_rel15, dci->rnti, dci->dci_format)); } int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format){ @@ -2718,7 +2723,6 @@ void nr_ue_send_sdu(module_id_t module_idP, LOG_D(MAC, "Handling PDU frame %d slot %d\n", frameP, slotP); uint8_t * pduP = pdu; - NR_UE_MAC_INST_t *UE_mac_inst = get_mac_inst(module_idP); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_SEND_SDU, VCD_FUNCTION_IN); @@ -3370,7 +3374,7 @@ unsigned char nr_generate_ulsch_pdu(uint8_t *sdus_payload, unsigned short post_padding) { NR_MAC_SUBHEADER_FIXED *mac_pdu_ptr = (NR_MAC_SUBHEADER_FIXED *) pdu; - unsigned char first_element = 0, last_size = 0, i, mac_header_control_elements[16], *ce_ptr, bsr = 0; + unsigned char last_size = 0, i, mac_header_control_elements[16], *ce_ptr, bsr = 0; int mac_ce_size, offset; LOG_D(MAC, "[UE] Generating ULSCH PDU : num_sdus %d\n", num_sdus); diff --git a/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c b/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c index a9f304fe2b..f0ba789266 100644 --- a/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c +++ b/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c @@ -48,21 +48,21 @@ #define DEBUG_RAR // table 7.2-1 TS 38.321 -uint8_t table_7_2_1[16] = { - {5}, // row index 0 - {10}, // row index 1 - {20}, // row index 2 - {30}, // row index 3 - {40}, // row index 4 - {60}, // row index 5 - {80}, // row index 6 - {120}, // row index 7 - {160}, // row index 8 - {240}, // row index 9 - {320}, // row index 10 - {480}, // row index 11 - {960}, // row index 12 - {1920}, // row index 13 +uint16_t table_7_2_1[16] = { + 5, // row index 0 + 10, // row index 1 + 20, // row index 2 + 30, // row index 3 + 40, // row index 4 + 60, // row index 5 + 80, // row index 6 + 120, // row index 7 + 160, // row index 8 + 240, // row index 9 + 320, // row index 10 + 480, // row index 11 + 960, // row index 12 + 1920, // row index 13 }; // WIP todo: @@ -89,7 +89,7 @@ uint16_t nr_ue_process_rar(module_id_t mod_id, n_subheaders++; if (rarh->T == 1) { n_subPDUs++; - LOG_D(MAC, "[UE %d][RAPROC] Got RAPID RAR subPDU %d\n", mod_id, rarh->RAPID); + LOG_D(MAC, "[UE %d][RAPROC] Got RAPID RAR subPDU\n", mod_id); } else { n_subPDUs++; ue_mac->RA_backoff_indicator = table_7_2_1[((NR_RA_HEADER_BI *)rarh)->BI]; @@ -97,7 +97,7 @@ uint16_t nr_ue_process_rar(module_id_t mod_id, LOG_D(MAC, "[UE %d][RAPROC] Got BI RAR subPDU %d\n", mod_id, ue_mac->RA_backoff_indicator); } if (rarh->RAPID == preamble_index) { - LOG_D(PHY, "[UE %d][RAPROC] Found RAR with the intended RAPID %d\n", rarh->RAPID); + LOG_D(PHY, "[UE %d][RAPROC] Found RAR with the intended RAPID %d\n", mod_id, rarh->RAPID); rar = (NR_MAC_RAR *) (dlsch_buffer + n_subheaders + (n_subPDUs - 1) * sizeof(NR_MAC_RAR)); ue_mac->RA_RAPID_found = 1; break; @@ -116,13 +116,13 @@ uint16_t nr_ue_process_rar(module_id_t mod_id, LOG_D(MAC, "number of RAR subheader %d; number of RAR pyloads %d\n", n_subheaders, n_subPDUs); - LOG_I(MAC, "[UE %d][RAPROC] Frame %d Received RAR (%02x|%02x.%02x.%02x.%02x.%02x.%02x) for preamble %d/%d\n", - mod_id, frameP, *(uint8_t *) rarh, rar[0], rar[1], rar[2], rar[3], rar[4], rar[5], rarh->RAPID, preamble_index); + // LOG_I(MAC, "[UE %d][RAPROC] Frame %d Received RAR (%02x|%02x.%02x.%02x.%02x.%02x.%02x) for preamble %d/%d\n", + // mod_id, frameP, *(uint8_t *) rarh, rar[0], rar[1], rar[2], rar[3], rar[4], rar[5], rarh->RAPID, preamble_index); if (ue_mac->RA_RAPID_found) { *t_crnti = rar->TCRNTI_2 + (rar->TCRNTI_1 << 8); ue_mac->t_crnti = *t_crnti; - ue_mac->rnti_type == NR_RNTI_TC; + ue_mac->rnti_type = NR_RNTI_TC; ta_command = rar->TA2 + (rar->TA1 << 5); } else { ue_mac->t_crnti = 0; diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index 092a2df94c..89bb3e3f2c 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -259,44 +259,4 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP, const uint16_t sdu_lenP, const uint16_t timing_advance, const uint8_t ul_cqi); -/* Random Access */ - -/* \brief Function called by PHY to retrieve information to be transmitted using the RA procedure. -If the UE is not in PUSCH mode for a particular eNB index, this is assumed to be an Msg3 and MAC -attempts to retrieves the CCCH message from RRC. If the UE is in PUSCH mode for a particular eNB -index and PUCCH format 0 (Scheduling Request) is not activated, the MAC may use this resource for -andom-access to transmit a BSR along with the C-RNTI control element (see 5.1.4 from 36.321) -@param mod_id Index of UE instance -@param CC_id Component Carrier Index -@param frame -@param gNB_id gNB index -@param nr_tti_tx slot for PRACH transmission -@returns void */ -void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, - module_id_t mod_id, - int CC_id, - UE_MODE_t UE_mode, - frame_t frame, - uint8_t gNB_id, - int nr_tti_tx); - -/* \brief Function implementing the routine for the selection of Random Access resources (5.1.2 TS 38.321). -@param module_idP Index of UE instance -@param CC_id Component Carrier Index -@param gNB_index gNB index -@param t_id -@param rach_ConfigDedicated -@returns void */ -void nr_get_prach_resources(module_id_t mod_id, - int CC_id, - uint8_t gNB_id, - uint8_t t_id, - uint8_t first_Msg3, - NR_PRACH_RESOURCES_t *prach_resources, - NR_RACH_ConfigDedicated_t * rach_ConfigDedicated); - -void nr_Msg1_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id); - -void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id); - #endif /*__LAYER2_NR_MAC_PROTO_H__*/ From 3341846d4cf98918ad0fb5d8d7043896ec68342e Mon Sep 17 00:00:00 2001 From: cig Date: Tue, 11 Feb 2020 17:22:17 +0100 Subject: [PATCH 032/553] Handled uninitialised return value in get_tx_amp_prach --- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 30 ++++++++++----------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 801a135782..5d24700317 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -216,11 +216,9 @@ void nr_dump_dlsch_SI(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id, unsigned int gain_table[31] = {100,112,126,141,158,178,200,224,251,282,316,359,398,447,501,562,631,708,794,891,1000,1122,1258,1412,1585,1778,1995,2239,2512,2818,3162}; #endif - unsigned int get_tx_amp_prach(int power_dBm, int power_max_dBm, int N_RB_UL) - { +int get_tx_amp_prach(int power_dBm, int power_max_dBm, int N_RB_UL){ - int gain_dB = power_dBm - power_max_dBm; - int amp_x_100; + int gain_dB = power_dBm - power_max_dBm, amp_x_100 = -1; switch (N_RB_UL) { case 6: @@ -242,17 +240,19 @@ unsigned int gain_table[31] = {100,112,126,141,158,178,200,224,251,282,316,359,3 amp_x_100 = 408*AMP; // 408 = 100*sqrt(100/6) break; default: - LOG_E(PHY,"Unknown PRB size %d\n",N_RB_UL); - //mac_xface->macphy_exit(""); + LOG_E(PHY, "Unknown PRB size %d\n", N_RB_UL); + return (amp_x_100); break; } if (gain_dB < -30) { - return(amp_x_100/3162); - } else if (gain_dB>0) - return(amp_x_100); + return (amp_x_100/3162); + } else if (gain_dB > 0) + return (amp_x_100); else - return(amp_x_100/gain_table[-gain_dB]); // 245 corresponds to the factor sqrt(25/6) - } + return (amp_x_100/gain_table[-gain_dB]); // 245 corresponds to the factor sqrt(25/6) + + return (amp_x_100); +} #if 0 @@ -4489,7 +4489,7 @@ uint8_t nr_is_ri_TXOp(PHY_VARS_NR_UE *ue, // - power control as per 38.213 ch 7.4 void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t gNB_id, runmode_t runmode) { - int frame_tx = proc->frame_tx, nr_tti_tx = proc->nr_tti_tx, prach_power; + int frame_tx = proc->frame_tx, nr_tti_tx = proc->nr_tti_tx, prach_power, tx_amp; uint16_t preamble_tx = 50, pathloss; uint8_t mod_id = ue->Mod_id; UE_MODE_t UE_mode = get_nrUE_mode(mod_id, ue->CC_id, gNB_id); @@ -4541,9 +4541,9 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t //ue->tx_total_RE[nr_tti_tx] = 96; // todo #if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706) - ue->prach_vars[gNB_id]->amp = get_tx_amp_prach(ue->tx_power_dBm[nr_tti_tx], - ue->tx_power_max_dBm, - ue->frame_parms.N_RB_UL); + tx_amp = get_tx_amp_prach(ue->tx_power_dBm[nr_tti_tx], ue->tx_power_max_dBm, ue->frame_parms.N_RB_UL); + if (tx_amp != -1) + ue->prach_vars[gNB_id]->amp = tx_amp; #else ue->prach_vars[gNB_id]->amp = AMP; #endif From fdaf4ff92c3622e30793bf61b0e76f331032d2b8 Mon Sep 17 00:00:00 2001 From: cig Date: Tue, 11 Feb 2020 17:23:10 +0100 Subject: [PATCH 033/553] Fixed warnings gNB compilation --- executables/nr-ru.c | 1 - executables/nr-softmodem.c | 1 - openair1/PHY/NR_TRANSPORT/nr_dlsch.h | 2 +- openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c | 6 +- .../PHY/NR_TRANSPORT/nr_transport_proto.h | 10 +- openair1/SCHED_NR/nr_prach_procedures.c | 4 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 4 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 265 +++++++++--------- openair2/RRC/NR/L2_nr_interface.c | 6 +- openair2/RRC/NR/rrc_gNB_nsa.c | 2 +- 10 files changed, 146 insertions(+), 155 deletions(-) diff --git a/executables/nr-ru.c b/executables/nr-ru.c index 1e6ae12e09..5626e3383d 100644 --- a/executables/nr-ru.c +++ b/executables/nr-ru.c @@ -2154,7 +2154,6 @@ void init_NR_RU(char *rf_config_file) PHY_VARS_gNB *gNB0= (PHY_VARS_gNB *)NULL; NR_DL_FRAME_PARMS *fp = (NR_DL_FRAME_PARMS *)NULL; int i; - int CC_id; // create status mask RC.ru_mask = 0; pthread_mutex_init(&RC.ru_mutex,NULL); diff --git a/executables/nr-softmodem.c b/executables/nr-softmodem.c index 8a4440d4d6..044b055e72 100644 --- a/executables/nr-softmodem.c +++ b/executables/nr-softmodem.c @@ -778,7 +778,6 @@ int stop_L1L2(module_id_t gnb_id) { */ int restart_L1L2(module_id_t gnb_id) { RU_t *ru = RC.ru[gnb_id]; - int cc_id; MessageDef *msg_p = NULL; LOG_W(GNB_APP, "restarting nr-softmodem\n"); /* block threads */ diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch.h b/openair1/PHY/NR_TRANSPORT/nr_dlsch.h index f48905b68c..3a6851ee8f 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch.h +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch.h @@ -90,7 +90,7 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch, -void free_gNB_dlsch(NR_gNB_DLSCH_t **dlschptr,uint16_t N_RB); +void free_gNB_dlsch(NR_gNB_DLSCH_t **dlschptr, uint16_t N_RB); void clean_gNB_dlsch(NR_gNB_DLSCH_t *dlsch); diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c index 79c2011d94..cd38614373 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c @@ -50,7 +50,7 @@ //#define DEBUG_DLSCH_FREE 1 -void free_gNB_dlsch(NR_gNB_DLSCH_t **dlschptr,uint16_t N_RB) +void free_gNB_dlsch(NR_gNB_DLSCH_t **dlschptr, uint16_t N_RB) { int i; int r; @@ -132,7 +132,7 @@ void free_gNB_dlsch(NR_gNB_DLSCH_t **dlschptr,uint16_t N_RB) } free16(dlsch,sizeof(NR_gNB_DLSCH_t)); - dlsch = NULL; + *dlschptr = NULL; } } @@ -273,7 +273,7 @@ NR_gNB_DLSCH_t *new_gNB_dlsch(NR_DL_FRAME_PARMS *frame_parms, LOG_D(PHY,"new_gNB_dlsch exit flag %d, size of %ld\n", exit_flag, sizeof(NR_gNB_DLSCH_t)); - free_gNB_dlsch(dlsch,N_RB); + free_gNB_dlsch(&dlsch, N_RB); return(NULL); diff --git a/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h b/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h index e8216ea004..2947a544a6 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h +++ b/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h @@ -211,12 +211,4 @@ uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx); uint32_t nr_get_code_rate_ul(uint8_t Imcs, uint8_t table_idx); -uint32_t nr_get_code_rate_dl(uint8_t Imcs, uint8_t table_idx); - -void rx_nr_prach(PHY_VARS_gNB *gNB, - int frame, - int subframe, - uint16_t *max_preamble, - uint16_t *max_preamble_energy, - uint16_t *max_preamble_delay - ); +uint32_t nr_get_code_rate_dl(uint8_t Imcs, uint8_t table_idx); \ No newline at end of file diff --git a/openair1/SCHED_NR/nr_prach_procedures.c b/openair1/SCHED_NR/nr_prach_procedures.c index b9a8ba94f1..47e27924e5 100644 --- a/openair1/SCHED_NR/nr_prach_procedures.c +++ b/openair1/SCHED_NR/nr_prach_procedures.c @@ -32,7 +32,7 @@ #include "PHY/defs_gNB.h" #include "PHY/phy_extern.h" -#include "PHY/NR_TRANSPORT/nr_transport_proto.h" +#include "PHY/NR_TRANSPORT/nr_transport.h" #include "nfapi_nr_interface_scf.h" #include "fapi_nr_l1.h" #include "nfapi_pnf.h" @@ -47,7 +47,7 @@ #include "intertask_interface.h" -extern uint32_t nfapi_mode; +extern uint8_t nfapi_mode; extern int oai_nfapi_nr_rach_ind(nfapi_rach_indication_t *rach_ind); diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index a1119e6c10..b00dde1399 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -314,10 +314,10 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, //printf("gNB_dlsch_ulsch_scheduler frameRX %d slotRX %d frameTX %d slotTX %d\n",frame_rxP,slot_rxP,frame_txP,slot_txP); protocol_ctxt_t ctxt; - int CC_id, i = -1, UE_id = 0; + int CC_id, UE_id = 0; // i = -1 gNB_MAC_INST *gNB = RC.nrmac[module_idP]; NR_UE_list_t *UE_list = &gNB->UE_list; - rnti_t rnti; + // rnti_t rnti; UE_sched_ctrl_t *ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; NR_COMMON_channels_t *cc = gNB->common_channels; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index dd268d5dd6..3ac10210bc 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -37,7 +37,9 @@ /* Utils */ #include "common/utils/LOG/log.h" #include "common/utils/LOG/vcd_signal_dumper.h" +#include "common/utils/nr/nr_common.h" #include "UTIL/OPT/opt.h" +#include "SIMULATION/TOOLS/sim.h" // for taus extern RAN_CONTEXT_t RC; @@ -59,7 +61,6 @@ void nr_initiate_ra_proc(module_id_t module_idP, uint16_t preamble_index, int16_t timing_offset, uint16_t ra_rnti){ - uint8_t i; uint16_t msg2_frame = frameP, msg2_slot = slotP; int offset; gNB_MAC_INST *nr_mac = RC.nrmac[module_idP]; @@ -140,7 +141,7 @@ void nr_schedule_RA(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ //uint8_t i = 0; int CC_id = 0; - gNB_MAC_INST *mac = RC.mac[module_idP]; + gNB_MAC_INST *mac = RC.nrmac[module_idP]; NR_COMMON_channels_t *cc = &mac->common_channels[CC_id]; NR_RA_t *ra = &cc->ra[0]; @@ -156,13 +157,139 @@ void nr_schedule_RA(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ //generate_Msg4(module_idP, CC_id, frameP, slotP, ra); break; case WAIT_Msg4_ACK: - check_Msg4_retransmission(module_idP, CC_id, frameP, slotP, ra); + //check_Msg4_retransmission(module_idP, CC_id, frameP, slotP, ra); + break; + default: break; } //} stop_meas(&mac->schedule_ra); } +// WIP +// todo: fix +void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP){ + + gNB_MAC_INST *mac = RC.nrmac[module_idP]; + NR_COMMON_channels_t *cc = &mac->common_channels[CC_id]; + NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; + NR_RA_t *ra = &cc->ra[0]; + NR_UE_list_t *UE_list = &mac->UE_list; + + nfapi_nr_ul_tti_request_t *ul_req = &mac->UL_tti_req[0]; + nfapi_nr_ul_dci_request_t *UL_dci_req = &mac->UL_dci_req[0]; + nfapi_nr_pusch_pdu_t *pusch_pdu = &ul_req->pdus_list[0].pusch_pdu; + nfapi_nr_ul_dci_request_pdus_t *ul_dci_request_pdu = &UL_dci_req->ul_dci_pdu_list[UL_dci_req->numPdus]; + + int UE_id = 0, CCEIndex, dci_formats[2], rnti_types[2], bwp_id = 1, coreset_id = 0, aggregation = 4, search_space = 1; + + AssertFatal(ra->state != RA_IDLE, "RA is not active for RA %X\n", ra->rnti); + + // if(N_RB_UL == 25) { + // ra->msg3_first_rb = 1; + // } else { + // if (cc->tdd_Config && N_RB_UL == 100) { + // ra->msg3_first_rb = 3; + // } else { + // ra->msg3_first_rb = 2; + // } + // } + // ra->msg3_nb_rb = 1; + // /* UL Grant */ + // ra->msg3_mcs = 10; + // ra->msg3_TPC = 3; + // ra->msg3_ULdelay = 0; + // ra->msg3_cqireq = 0; + // ra->msg3_round = 0; + + LOG_D(MAC, "[gNB %d][RAPROC] Frame %d, Subframe %d : CC_id %d RA is active, Msg3 in (%d,%d)\n", module_idP, frameP, slotP, CC_id, ra->Msg3_frame, ra->Msg3_slot); + + ul_req->SFN = ra->Msg3_frame << 4 | ra->Msg3_slot; + ul_req->Slot = slotP; + ul_req->n_pdus = 1; + ul_req->pdus_list[0].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE; + ul_req->pdus_list[0].pdu_size = sizeof(nfapi_nr_pusch_pdu_t); + memset(pusch_pdu, 0, sizeof(nfapi_nr_pusch_pdu_t)); + + memset((void*)ul_dci_request_pdu,0,sizeof(nfapi_nr_ul_dci_request_pdus_t)); + ul_dci_request_pdu->PDUType = NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE; + ul_dci_request_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdcch_pdu)); + + nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &ul_dci_request_pdu->pdcch_pdu.pdcch_pdu_rel15; + + AssertFatal(UE_list->active[UE_id] >=0,"Cannot find UE_id %d is not active\n", UE_id); + + NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id]; + AssertFatal(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count == 1, + "downlinkBWP_ToAddModList has %d BWP!\n", secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count); + NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[bwp_id-1]; + NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; + LOG_D(MAC, "Frame %d, Subframe %d Adding Msg3 UL Config Request for (%d,%d) : (%d,%d,%d) for rnti: %d\n", + frameP, + slotP, + ra->Msg3_frame, + ra->Msg3_slot, + ra->msg3_nb_rb, + ra->msg3_first_rb, + ra->msg3_round, + ra->rnti); + + pusch_pdu->pdu_bit_map = PUSCH_PDU_BITMAP_PUSCH_DATA; + pusch_pdu->rnti = ra->rnti; + pusch_pdu->handle = 0; + pusch_pdu->bwp_size = NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275); + pusch_pdu->bwp_start = NRRIV2PRBOFFSET(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275); + pusch_pdu->subcarrier_spacing = ubwp->bwp_Common->genericParameters.subcarrierSpacing; + pusch_pdu->cyclic_prefix = 0; + pusch_pdu->mcs_index = 9; + pusch_pdu->mcs_table = 0; + pusch_pdu->target_code_rate = nr_get_code_rate_ul(pusch_pdu->mcs_index,pusch_pdu->mcs_table); + pusch_pdu->qam_mod_order = nr_get_Qm_ul(pusch_pdu->mcs_index,pusch_pdu->mcs_table); + pusch_pdu->transform_precoding = 0; + pusch_pdu->data_scrambling_id = 0; + pusch_pdu->nrOfLayers = 1; + pusch_pdu->ul_dmrs_symb_pos = 1; + pusch_pdu->dmrs_config_type = 0; + pusch_pdu->ul_dmrs_scrambling_id = 0; //If provided and the PUSCH is not a msg3 PUSCH, otherwise, L2 should set this to physical cell id. + pusch_pdu->scid = 0; //DMRS sequence initialization [TS38.211, sec 6.4.1.1.1]. Should match what is sent in DCI 0_1, otherwise set to 0. + pusch_pdu->resource_alloc = 1; //type 1 + //pusch_pdu->rb_bitmap;// for ressource alloc type 0 + pusch_pdu->rb_start = ra->msg3_first_rb; + pusch_pdu->rb_size = ra->msg3_nb_rb; + pusch_pdu->vrb_to_prb_mapping = 0; + pusch_pdu->frequency_hopping = 0; + //pusch_pdu->tx_direct_current_location;//The uplink Tx Direct Current location for the carrier. Only values in the value range of this field between 0 and 3299, which indicate the subcarrier index within the carrier corresponding 1o the numerology of the corresponding uplink BWP and value 3300, which indicates "Outside the carrier" and value 3301, which indicates "Undetermined position within the carrier" are used. [TS38.331, UplinkTxDirectCurrentBWP IE] + pusch_pdu->uplink_frequency_shift_7p5khz = 0; + //Resource Allocation in time domain + pusch_pdu->start_symbol_index = 2; + pusch_pdu->nr_of_symbols = 12; + //Optional Data only included if indicated in pduBitmap + pusch_pdu->pusch_data.rv_index = 0; + pusch_pdu->pusch_data.harq_process_id = 0; + pusch_pdu->pusch_data.new_data_indicator = 0; + pusch_pdu->pusch_data.tb_size = nr_compute_tbs(pusch_pdu->mcs_index, + pusch_pdu->target_code_rate, + pusch_pdu->rb_size, + pusch_pdu->nr_of_symbols, + 6, //nb_re_dmrs - not sure where this is coming from - its not in the FAPI + 0, //nb_rb_oh + pusch_pdu->nrOfLayers = 1); + pusch_pdu->pusch_data.num_cb = 0; + + CCEIndex = allocate_nr_CCEs(mac, bwp_id, coreset_id, aggregation, search_space, UE_id, 0); + AssertFatal(CCEIndex >= 0, "CCEIndex is negative\n"); + pdcch_pdu_rel15->dci_pdu.CceIndex[pdcch_pdu_rel15->numDlDci] = CCEIndex; + LOG_D(PHY, "CCEIndex %d\n", pdcch_pdu_rel15->dci_pdu.CceIndex[pdcch_pdu_rel15->numDlDci]); + + LOG_D(MAC,"Configuring ULDCI/PDCCH in %d.%d\n", frameP,slotP); + nr_configure_pdcch(pdcch_pdu_rel15, 1, scc, bwp); + + dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET]; + config_uldci(ubwp, pusch_pdu, pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); + pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[0] = nr_dci_size(dci_formats[0], rnti_types[0], pdcch_pdu_rel15->BWPSize); + fill_dci_pdu_rel15(pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); +} + // WIP // todo: // - fix me @@ -172,7 +299,7 @@ void nr_generate_Msg2(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ - int first_rb, UE_id = 0, dci_formats[2], rnti_types[2], CCEIndex, dlBWP_carrier_bandwidth, mcsIndex = 9; + int UE_id = 0, dci_formats[2], rnti_types[2], CCEIndex, dlBWP_carrier_bandwidth, mcsIndex = 9; int startSymbolAndLength = 0, StartSymbolIndex = -1, NrOfSymbols = 14, StartSymbolIndex_tmp, NrOfSymbols_tmp, x_Overhead, time_domain_assignment = 2; int bwp_id = 1, coreset_id = 0, aggregation = 4, search_space = 0, N_RB_UL = 106; gNB_MAC_INST *nr_mac = RC.nrmac[module_idP]; @@ -188,14 +315,13 @@ void nr_generate_Msg2(module_id_t module_idP, // todo // Allocate 4 PRBS starting in RB 0 - // first_rb = 0; + // int first_rb = 0; // vrb_map[first_rb] = 1; // vrb_map[first_rb + 1] = 1; // vrb_map[first_rb + 2] = 1; // vrb_map[first_rb + 3] = 1; nfapi_nr_dl_tti_request_body_t *dl_req = &nr_mac->DL_req[CC_id].dl_tti_request_body; - nfapi_nr_dl_tti_request_pdu_t *dl_config_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs]; nfapi_nr_pdu_t *tx_req = &nr_mac->TX_req[CC_id].pdu_list[nr_mac->TX_req[CC_id].Number_of_PDUs]; nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs]; @@ -358,8 +484,7 @@ void nr_generate_Msg2(module_id_t module_idP, } void nr_clear_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP){ - unsigned char i; - NR_RA_t *ra = &RC.mac[module_idP]->common_channels[CC_id].ra[0]; + NR_RA_t *ra = &RC.nrmac[module_idP]->common_channels[CC_id].ra[0]; LOG_D(MAC,"[gNB %d][RAPROC] CC_id %d Frame %d Clear Random access information rnti %x\n", module_idP, CC_id, frameP, ra->rnti); ra->state = IDLE; ra->timing_offset = 0; @@ -402,128 +527,4 @@ void nr_fill_rar(NR_RA_t * ra, // rar->UL_GRANT_2 = (uint8_t) (buffer >> 16) & 0xFF; // rar->UL_GRANT_3 = (uint8_t) (buffer >> 8) & 0xFF; // rar->UL_GRANT_4 = (uint8_t) buffer & 0xff; -} - -// WIP -// todo: fix -void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP){ - - gNB_MAC_INST *mac = RC.nrmac[module_idP]; - NR_COMMON_channels_t *cc = &mac->common_channels[CC_id]; - NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; - NR_RA_t *ra = &cc->ra[0]; - NR_UE_list_t *UE_list = &mac->UE_list; - - nfapi_nr_ul_tti_request_t *ul_req = &mac->UL_tti_req[0]; - nfapi_nr_ul_dci_request_t *UL_dci_req = &mac->UL_dci_req[0]; - nfapi_nr_pusch_pdu_t *pusch_pdu = &ul_req->pdus_list[0].pusch_pdu; - nfapi_nr_ul_dci_request_pdus_t *ul_dci_request_pdu = &UL_dci_req->ul_dci_pdu_list[UL_dci_req->numPdus]; - - int UE_id = 0, CCEIndex, dci_formats[2], rnti_types[2], bwp_id = 1, coreset_id = 0, aggregation = 4, search_space = 1; - - AssertFatal(ra->state != IDLE, "RA is not active for RA %X\n", ra->rnti); - - // if(N_RB_UL == 25) { - // ra->msg3_first_rb = 1; - // } else { - // if (cc->tdd_Config && N_RB_UL == 100) { - // ra->msg3_first_rb = 3; - // } else { - // ra->msg3_first_rb = 2; - // } - // } - // ra->msg3_nb_rb = 1; - // /* UL Grant */ - // ra->msg3_mcs = 10; - // ra->msg3_TPC = 3; - // ra->msg3_ULdelay = 0; - // ra->msg3_cqireq = 0; - // ra->msg3_round = 0; - - LOG_D(MAC, "[gNB %d][RAPROC] Frame %d, Subframe %d : CC_id %d RA is active, Msg3 in (%d,%d)\n", module_idP, frameP, slotP, CC_id, ra->Msg3_frame, ra->Msg3_slot); - - ul_req->SFN = ra->Msg3_frame << 4 | ra->Msg3_slot; - ul_req->Slot = slotP; - ul_req->n_pdus = 1; - ul_req->pdus_list[0].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE; - ul_req->pdus_list[0].pdu_size = sizeof(nfapi_nr_pusch_pdu_t); - memset(pusch_pdu, 0, sizeof(nfapi_nr_pusch_pdu_t)); - - memset((void*)ul_dci_request_pdu,0,sizeof(nfapi_nr_ul_dci_request_pdus_t)); - ul_dci_request_pdu->PDUType = NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE; - ul_dci_request_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdcch_pdu)); - - nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &ul_dci_request_pdu->pdcch_pdu.pdcch_pdu_rel15; - - AssertFatal(UE_list->active[UE_id] >=0,"Cannot find UE_id %d is not active\n", UE_id); - - NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id]; - AssertFatal(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count == 1, - "downlinkBWP_ToAddModList has %d BWP!\n", secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count); - NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[bwp_id-1]; - NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; - LOG_D(MAC, "Frame %d, Subframe %d Adding Msg3 UL Config Request for (%d,%d) : (%d,%d,%d) for rnti: %d\n", - frameP, - slotP, - ra->Msg3_frame, - ra->Msg3_slot, - ra->msg3_nb_rb, - ra->msg3_first_rb, - ra->msg3_round, - ra->rnti); - - pusch_pdu->pdu_bit_map = PUSCH_PDU_BITMAP_PUSCH_DATA; - pusch_pdu->rnti = ra->rnti; - pusch_pdu->handle = 0; - pusch_pdu->bwp_size = NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275); - pusch_pdu->bwp_start = NRRIV2PRBOFFSET(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275); - pusch_pdu->subcarrier_spacing = ubwp->bwp_Common->genericParameters.subcarrierSpacing; - pusch_pdu->cyclic_prefix = 0; - pusch_pdu->mcs_index = 9; - pusch_pdu->mcs_table = 0; - pusch_pdu->target_code_rate = nr_get_code_rate_ul(pusch_pdu->mcs_index,pusch_pdu->mcs_table); - pusch_pdu->qam_mod_order = nr_get_Qm_ul(pusch_pdu->mcs_index,pusch_pdu->mcs_table); - pusch_pdu->transform_precoding = 0; - pusch_pdu->data_scrambling_id = 0; - pusch_pdu->nrOfLayers = 1; - pusch_pdu->ul_dmrs_symb_pos = 1; - pusch_pdu->dmrs_config_type = 0; - pusch_pdu->ul_dmrs_scrambling_id = 0; //If provided and the PUSCH is not a msg3 PUSCH, otherwise, L2 should set this to physical cell id. - pusch_pdu->scid = 0; //DMRS sequence initialization [TS38.211, sec 6.4.1.1.1]. Should match what is sent in DCI 0_1, otherwise set to 0. - pusch_pdu->resource_alloc = 1; //type 1 - //pusch_pdu->rb_bitmap;// for ressource alloc type 0 - pusch_pdu->rb_start = ra->msg3_first_rb; - pusch_pdu->rb_size = ra->msg3_nb_rb; - pusch_pdu->vrb_to_prb_mapping = 0; - pusch_pdu->frequency_hopping = 0; - //pusch_pdu->tx_direct_current_location;//The uplink Tx Direct Current location for the carrier. Only values in the value range of this field between 0 and 3299, which indicate the subcarrier index within the carrier corresponding 1o the numerology of the corresponding uplink BWP and value 3300, which indicates "Outside the carrier" and value 3301, which indicates "Undetermined position within the carrier" are used. [TS38.331, UplinkTxDirectCurrentBWP IE] - pusch_pdu->uplink_frequency_shift_7p5khz = 0; - //Resource Allocation in time domain - pusch_pdu->start_symbol_index = 2; - pusch_pdu->nr_of_symbols = 12; - //Optional Data only included if indicated in pduBitmap - pusch_pdu->pusch_data.rv_index = 0; - pusch_pdu->pusch_data.harq_process_id = 0; - pusch_pdu->pusch_data.new_data_indicator = 0; - pusch_pdu->pusch_data.tb_size = nr_compute_tbs(pusch_pdu->mcs_index, - pusch_pdu->target_code_rate, - pusch_pdu->rb_size, - pusch_pdu->nr_of_symbols, - 6, //nb_re_dmrs - not sure where this is coming from - its not in the FAPI - 0, //nb_rb_oh - pusch_pdu->nrOfLayers = 1); - pusch_pdu->pusch_data.num_cb = 0; - - CCEIndex = allocate_nr_CCEs(mac, bwp_id, coreset_id, aggregation, search_space, UE_id, 0); - AssertFatal(CCEIndex >= 0, "CCEIndex is negative\n"); - pdcch_pdu_rel15->dci_pdu.CceIndex[pdcch_pdu_rel15->numDlDci] = CCEIndex; - LOG_D(PHY, "CCEIndex %d\n", pdcch_pdu_rel15->dci_pdu.CceIndex[pdcch_pdu_rel15->numDlDci]); - - LOG_D(MAC,"Configuring ULDCI/PDCCH in %d.%d\n", frameP,slotP); - nr_configure_pdcch(pdcch_pdu_rel15, 1, scc, bwp); - - dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET]; - config_uldci(ubwp, pusch_pdu, pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); - pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[0] = nr_dci_size(dci_formats[0], rnti_types[0], pdcch_pdu_rel15->BWPSize); - fill_dci_pdu_rel15(pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); } \ No newline at end of file diff --git a/openair2/RRC/NR/L2_nr_interface.c b/openair2/RRC/NR/L2_nr_interface.c index ea1bccef97..803c6953fe 100644 --- a/openair2/RRC/NR/L2_nr_interface.c +++ b/openair2/RRC/NR/L2_nr_interface.c @@ -64,7 +64,7 @@ int8_t mac_rrc_nr_data_req(const module_id_t Mod_idP, rrc_gNB_carrier_data_t *carrier; NR_BCCH_BCH_Message_t *mib; NR_SRB_INFO * srb_info; - char payload_size, payload_pP; + char payload_size, *payload_pP; rrc = RC.nrrrc[Mod_idP]; carrier = &rrc->carrier; @@ -96,7 +96,7 @@ int8_t mac_rrc_nr_data_req(const module_id_t Mod_idP, //struct rrc_eNB_ue_context_s *ue_context_p = rrc_eNB_get_ue_context(RC.rrc[Mod_idP],rnti); //if (ue_context_p == NULL) return(0); //eNB_RRC_UE_t *ue_p = &ue_context_p->ue_context; - LOG_D(RRC,"[gNB %d] Frame %d CCCH request (Srb_id %d)\n", Mod_idP, frameP, Srb_id); + LOG_D(RRC,"[gNB %d] Frame %d CCCH request (Srb_id %ld)\n", Mod_idP, frameP, Srb_id); // srb_info=&ue_p->Srb0; @@ -107,7 +107,7 @@ int8_t mac_rrc_nr_data_req(const module_id_t Mod_idP, payload_pP = srb_info->Tx_buffer.Payload; LOG_D(RRC,"[gNB %d] CCCH (%p) has %d bytes (dest: %p, src %p)\n", Mod_idP, srb_info, payload_size, buffer_pP, payload_pP); // Fill buffer - memcpy(buffer_pP, payload_pP, payload_size); + memcpy((void *)buffer_pP, (void*)payload_pP, payload_size); Sdu_size = payload_size; srb_info->Tx_buffer.payload_size = 0; } diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c index cf48aef459..c938b968b6 100644 --- a/openair2/RRC/NR/rrc_gNB_nsa.c +++ b/openair2/RRC/NR/rrc_gNB_nsa.c @@ -130,7 +130,7 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_ ue_context_p->ue_id_rnti = ue_context_p->ue_context.secondaryCellGroup->spCellConfig->reconfigurationWithSync->newUE_Identity; NR_CG_Config_t *CG_Config = calloc(1,sizeof(*CG_Config)); memset((void*)CG_Config,0,sizeof(*CG_Config)); - int CG_Config_size = generate_CG_Config(rrc,CG_Config,ue_context_p->ue_context.reconfig,ue_context_p->ue_context.rb_config); + //int CG_Config_size = generate_CG_Config(rrc,CG_Config,ue_context_p->ue_context.reconfig,ue_context_p->ue_context.rb_config); //X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).rrc_buffer_size = CG_Config_size; //Need to verify correct value for the buffer_size // Send to X2 entity to transport to MeNB From f7611d12a2194ab91f5fd869b3ebde02db407cc9 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Wed, 12 Feb 2020 18:06:30 +0100 Subject: [PATCH 034/553] prach tables in mac_common and function to read them --- openair1/PHY/NR_TRANSPORT/nr_prach.c | 3 - openair1/PHY/NR_TRANSPORT/nr_prach.h | 784 --------------- openair1/PHY/NR_TRANSPORT/nr_prach_common.c | 8 +- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 891 ++++++++++++++++++ openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h | 10 + 5 files changed, 905 insertions(+), 791 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index 8bcd3f2662..a9995cd0ea 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -43,9 +43,6 @@ extern uint16_t NCS_restricted_TypeB_delta_f_RA_5[14]; extern uint16_t NCS_unrestricted_delta_f_RA_15[16]; extern uint16_t prach_root_sequence_map_0_3[838]; extern uint16_t prach_root_sequence_map_abc[138]; -extern int64_t table_6_3_3_2_2_prachConfig_Index [256][9]; -extern int64_t table_6_3_3_2_3_prachConfig_Index [256][9]; -extern int64_t table_6_3_3_2_4_prachConfig_Index [256][10]; extern uint16_t nr_du[838]; extern int16_t nr_ru[2*839]; diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.h b/openair1/PHY/NR_TRANSPORT/nr_prach.h index 1e2b758035..5a8ed9116e 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.h +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.h @@ -105,787 +105,3 @@ uint16_t prach_root_sequence_map_abc[138] = { 51, 88 , 52, 87 , 53, 86 , 54, 85 , 55, 84 , 56, 83 , 57, 82 , 58, 81 , 59, 80 , 60, 79 , 61, 78 , 62, 77 , 63, 76 , 64, 75 , 65, 74 , 66, 73 , 67, 72 , 68, 71 , 69, 70 }; - -// Table 6.3.3.2-2: Random access configurations for FR1 and paired spectrum/supplementary uplink -// the column 5, (SFN_nbr is a bitmap where we set bit to '1' in the position of the subframe where the RACH can be sent. -// E.g. in row 4, and column 5 we have set value 512 ('1000000000') which means RACH can be sent at subframe 9. -// E.g. in row 20 and column 5 we have set value 66 ('0001000010') which means RACH can be sent at subframe 1 or 6 -int64_t table_6_3_3_2_2_prachConfig_Index [256][9] = { -//format, format, x, y, SFN_nbr, star_symb, slots_sfn, occ_slot, duration -{0, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{0, -1, 16, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{0, -1, 16, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{0, -1, 16, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{0, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{0, -1, 8, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{0, -1, 8, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{0, -1, 8, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{0, -1, 4, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{0, -1, 4, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{0, -1, 4, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{0, -1, 4, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{0, -1, 2, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{0, -1, 2, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{0, -1, 2, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{0, -1, 2, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{0, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 -{0, -1, 1, 0, 16, 0, -1, -1, 0}, // (subframe number) 4 -{0, -1, 1, 0, 128, 0, -1, -1, 0}, // (subframe number) 7 -{0, -1, 1, 0, 66, 0, -1, -1, 0}, // (subframe number) 1,6 -{0, -1, 1, 0, 132, 0, -1, -1, 0}, // (subframe number) 2,7 -{0, -1, 1, 0, 264, 0, -1, -1, 0}, // (subframe number) 3,8 -{0, -1, 1, 0, 146, 0, -1, -1, 0}, // (subframe number) 1,4,7 -{0, -1, 1, 0, 292, 0, -1, -1, 0}, // (subframe number) 2,5,8 -{0, -1, 1, 0, 584, 0, -1, -1, 0}, // (subframe number) 3, 6, 9 -{0, -1, 1, 0, 341, 0, -1, -1, 0}, // (subframe number) 0,2,4,6,8 -{0, -1, 1, 0, 682, 0, -1, -1, 0}, // (subframe number) 1,3,5,7,9 -{0, -1, 1, 0, 1023, 0, -1, -1, 0}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{1, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{1, -1, 16, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{1, -1, 16, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{1, -1, 16, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{1, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{1, -1, 8, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{1, -1, 8, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{1, -1, 8, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{1, -1, 4, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{1, -1, 4, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{1, -1, 4, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{1, -1, 4, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{1, -1, 2, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{1, -1, 2, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{1, -1, 2, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{1, -1, 2, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{1, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 -{1, -1, 1, 0, 16, 0, -1, -1, 0}, // (subframe number) 4 -{1, -1, 1, 0, 128, 0, -1, -1, 0}, // (subframe number) 7 -{1, -1, 1, 0, 66, 0, -1, -1, 0}, // (subframe number) 1,6 -{1, -1, 1, 0, 132, 0, -1, -1, 0}, // (subframe number) 2,7 -{1, -1, 1, 0, 264, 0, -1, -1, 0}, // (subframe number) 3,8 -{1, -1, 1, 0, 146, 0, -1, -1, 0}, // (subframe number) 1,4,7 -{1, -1, 1, 0, 292, 0, -1, -1, 0}, // (subframe number) 2,5,8 -{1, -1, 1, 0, 584, 0, -1, -1, 0}, // (subframe number) 3,6,9 -{2, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{2, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{2, -1, 4, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 -{2, -1, 2, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 -{2, -1, 2, 0, 32, 0, -1, -1, 0}, // (subframe number) 5 -{2, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 -{2, -1, 1, 0, 32, 0, -1, -1, 0}, // (subframe number) 5 -{3, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{3, -1, 16, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{3, -1, 16, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{3, -1, 16, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{3, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{3, -1, 8, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{3, -1, 8, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{3, -1, 4, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{3, -1, 4, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{3, -1, 4, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{3, -1, 4, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{3, -1, 2, 1, 2, 0, -1, -1, 0}, // (subframe number) 1 -{3, -1, 2, 1, 16, 0, -1, -1, 0}, // (subframe number) 4 -{3, -1, 2, 1, 128, 0, -1, -1, 0}, // (subframe number) 7 -{3, -1, 2, 1, 512, 0, -1, -1, 0}, // (subframe number) 9 -{3, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1 -{3, -1, 1, 0, 16, 0, -1, -1, 0}, // (subframe number) 4 -{3, -1, 1, 0, 128, 0, -1, -1, 0}, // (subframe number) 7 -{3, -1, 1, 0, 66, 0, -1, -1, 0}, // (subframe number) 1,6 -{3, -1, 1, 0, 132, 0, -1, -1, 0}, // (subframe number) 2,7 -{3, -1, 1, 0, 264, 0, -1, -1, 0}, // (subframe number) 3,8 -{3, -1, 1, 0, 146, 0, -1, -1, 0}, // (subframe number) 1,4,7 -{3, -1, 1, 0, 292, 0, -1, -1, 0}, // (subframe number) 2,5,8 -{3, -1, 1, 0, 584, 0, -1, -1, 0}, // (subframe number) 3, 6, 9 -{3, -1, 1, 0, 341, 0, -1, -1, 0}, // (subframe number) 0,2,4,6,8 -{3, -1, 1, 0, 682, 0, -1, -1, 0}, // (subframe number) 1,3,5,7,9 -{3, -1, 1, 0, 1023, 0, -1, -1, 0}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xa1, -1, 16, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9 -{0xa1, -1, 16, 1, 16, 0, 2, 6, 2}, // (subframe number) 4 -{0xa1, -1, 8, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9 -{0xa1, -1, 8, 1, 16, 0, 2, 6, 2}, // (subframe number) 4 -{0xa1, -1, 4, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9 -{0xa1, -1, 4, 1, 528, 0, 1, 6, 2}, // (subframe number) 4,9 -{0xa1, -1, 4, 0, 16, 0, 2, 6, 2}, // (subframe number) 4 -{0xa1, -1, 2, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9 -{0xa1, -1, 2, 0, 2, 0, 2, 6, 2}, // (subframe number) 1 -{0xa1, -1, 2, 0, 16, 0, 2, 6, 2}, // (subframe number) 4 -{0xa1, -1, 2, 0, 128, 0, 2, 6, 2}, // (subframe number) 7 -{0xa1, -1, 1, 0, 16, 0, 1, 6, 2}, // (subframe number) 4 -{0xa1, -1, 1, 0, 66, 0, 1, 6, 2}, // (subframe number) 1,6 -{0xa1, -1, 1, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9 -{0xa1, -1, 1, 0, 2, 0, 2, 6, 2}, // (subframe number) 1 -{0xa1, -1, 1, 0, 128, 0, 2, 6, 2}, // (subframe number) 7 -{0xa1, -1, 1, 0, 132, 0, 2, 6, 2}, // (subframe number) 2,7 -{0xa1, -1, 1, 0, 146, 0, 2, 6, 2}, // (subframe number) 1,4,7 -{0xa1, -1, 1, 0, 341, 0, 2, 6, 2}, // (subframe number) 0,2,4,6,8 -{0xa1, -1, 1, 0, 1023, 0, 2, 6, 2}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xa1, -1, 1, 0, 682, 0, 2, 6, 2}, // (subframe number) 1,3,5,7,9 -{0xa1, 0xb1, 2, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xa1, 0xb1, 2, 0, 16, 0, 2, 7, 2}, // (subframe number) 4 -{0xa1, 0xb1, 1, 0, 16, 0, 1, 7, 2}, // (subframe number) 4 -{0xa1, 0xb1, 1, 0, 66, 0, 1, 7, 2}, // (subframe number) 1,6 -{0xa1, 0xb1, 1, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xa1, 0xb1, 1, 0, 2, 0, 2, 7, 2}, // (subframe number) 1 -{0xa1, 0xb1, 1, 0, 128, 0, 2, 7, 2}, // (subframe number) 7 -{0xa1, 0xb1, 1, 0, 146, 0, 2, 7, 2}, // (subframe number) 1,4,7 -{0xa1, 0xb1, 1, 0, 341, 0, 2, 7, 2}, // (subframe number) 0,2,4,6,8 -{0xa2, -1, 16, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9 -{0xa2, -1, 16, 1, 16, 0, 2, 3, 4}, // (subframe number) 4 -{0xa2, -1, 8, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9 -{0xa2, -1, 8, 1, 16, 0, 2, 3, 4}, // (subframe number) 4 -{0xa2, -1, 4, 0, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9 -{0xa2, -1, 4, 0, 16, 0, 2, 3, 4}, // (subframe number) 4 -{0xa2, -1, 2, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9 -{0xa2, -1, 2, 0, 2, 0, 2, 3, 4}, // (subframe number) 1 -{0xa2, -1, 2, 0, 16, 0, 2, 3, 4}, // (subframe number) 4 -{0xa2, -1, 2, 0, 128, 0, 2, 3, 4}, // (subframe number) 7 -{0xa2, -1, 1, 0, 16, 0, 1, 3, 4}, // (subframe number) 4 -{0xa2, -1, 1, 0, 66, 0, 1, 3, 4}, // (subframe number) 1,6 -{0xa2, -1, 1, 0, 528, 0, 1, 3, 4}, // (subframe number) 4,9 -{0xa2, -1, 1, 0, 2, 0, 2, 3, 4}, // (subframe number) 1 -{0xa2, -1, 1, 0, 128, 0, 2, 3, 4}, // (subframe number) 7 -{0xa2, -1, 1, 0, 132, 0, 2, 3, 4}, // (subframe number) 2,7 -{0xa2, -1, 1, 0, 146, 0, 2, 3, 4}, // (subframe number) 1,4,7 -{0xa2, -1, 1, 0, 341, 0, 2, 3, 4}, // (subframe number) 0,2,4,6,8 -{0xa2, -1, 1, 0, 1023, 0, 2, 3, 4}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xa2, -1, 1, 0, 682, 0, 2, 3, 4}, // (subframe number) 1,3,5,7,9 -{0xa2, 0xb2, 2, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9 -{0xa2, 0xb2, 2, 0, 16, 0, 2, 3, 4}, // (subframe number) 4 -{0xa2, 0xb2, 1, 0, 16, 0, 1, 3, 4}, // (subframe number) 4 -{0xa2, 0xb2, 1, 0, 66, 0, 1, 3, 4}, // (subframe number) 1,6 -{0xa2, 0xb2, 1, 0, 528, 0, 1, 3, 4}, // (subframe number) 4,9 -{0xa2, 0xb2, 1, 0, 2, 0, 2, 3, 4}, // (subframe number) 1 -{0xa2, 0xb2, 1, 0, 128, 0, 2, 3, 4}, // (subframe number) 7 -{0xa2, 0xb2, 1, 0, 146, 0, 2, 3, 4}, // (subframe number) 1,4,7 -{0xa2, 0xb2, 1, 0, 341, 0, 2, 3, 4}, // (subframe number) 0,2,4,6,8 -{0xa2, 0xb2, 1, 0, 1023, 0, 2, 3, 4}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xa3, -1, 16, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xa3, -1, 16, 1, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xa3, -1, 8, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xa3, -1, 8, 1, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xa3, -1, 4, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xa3, -1, 4, 0, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xa3, -1, 2, 1, 580, 0, 2, 2, 6}, // (subframe number) 2,6,9 -{0xa3, -1, 2, 0, 2, 0, 2, 2, 6}, // (subframe number) 1 -{0xa3, -1, 2, 0, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xa3, -1, 2, 0, 128, 0, 2, 2, 6}, // (subframe number) 7 -{0xa3, -1, 1, 0, 16, 0, 1, 2, 6}, // (subframe number) 4 -{0xa3, -1, 1, 0, 66, 0, 1, 2, 6}, // (subframe number) 1,6 -{0xa3, -1, 1, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xa3, -1, 1, 0, 2, 0, 2, 2, 6}, // (subframe number) 1 -{0xa3, -1, 1, 0, 128, 0, 2, 2, 6}, // (subframe number) 7 -{0xa3, -1, 1, 0, 132, 0, 2, 2, 6}, // (subframe number) 2,7 -{0xa3, -1, 1, 0, 146, 0, 2, 2, 6}, // (subframe number) 1,4,7 -{0xa3, -1, 1, 0, 341, 0, 2, 2, 6}, // (subframe number) 0,2,4,6,8 -{0xa3, -1, 1, 0, 1023, 0, 2, 2, 6}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xa3, -1, 1, 0, 682, 0, 2, 2, 6}, // (subframe number) 1,3,5,7,9 -{0xa3, 0xb3, 2, 1, 580, 0, 2, 2, 6}, // (subframe number) 2,6,9 -{0xa3, 0xb3, 2, 0, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xa3, 0xb3, 1, 0, 16, 0, 1, 2, 6}, // (subframe number) 4 -{0xa3, 0xb3, 1, 0, 66, 0, 1, 2, 6}, // (subframe number) 1,6 -{0xa3, 0xb3, 1, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xa3, 0xb3, 1, 0, 2, 0, 2, 2, 6}, // (subframe number) 1 -{0xa3, 0xb3, 1, 0, 128, 0, 2, 2, 6}, // (subframe number) 7 -{0xa3, 0xb3, 1, 0, 146, 0, 2, 2, 6}, // (subframe number) 1,4,7 -{0xa3, 0xb3, 1, 0, 341, 0, 2, 2, 6}, // (subframe number) 0,2,4,6,8 -{0xa3, 0xb3, 1, 0, 1023, 0, 2, 2, 6}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xb1, -1, 16, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xb1, -1, 16, 1, 16, 0, 2, 7, 2}, // (subframe number) 4 -{0xb1, -1, 8, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xb1, -1, 8, 1, 16, 0, 2, 7, 2}, // (subframe number) 4 -{0xb1, -1, 4, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xb1, -1, 4, 1, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xb1, -1, 4, 0, 16, 0, 2, 7, 2}, // (subframe number) 4 -{0xb1, -1, 2, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xb1, -1, 2, 0, 2, 0, 2, 7, 2}, // (subframe number) 1 -{0xb1, -1, 2, 0, 16, 0, 2, 7, 2}, // (subframe number) 4 -{0xb1, -1, 2, 0, 128, 0, 2, 7, 2}, // (subframe number) 7 -{0xb1, -1, 1, 0, 16, 0, 1, 7, 2}, // (subframe number) 4 -{0xb1, -1, 1, 0, 66, 0, 1, 7, 2}, // (subframe number) 1,6 -{0xb1, -1, 1, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xb1, -1, 1, 0, 2, 0, 2, 7, 2}, // (subframe number) 1 -{0xb1, -1, 1, 0, 128, 0, 2, 7, 2}, // (subframe number) 7 -{0xb1, -1, 1, 0, 132, 0, 2, 7, 2}, // (subframe number) 2,7 -{0xb1, -1, 1, 0, 146, 0, 2, 7, 2}, // (subframe number) 1,4,7 -{0xb1, -1, 1, 0, 341, 0, 2, 7, 2}, // (subframe number) 0,2,4,6,8 -{0xb1, -1, 1, 0, 1023, 0, 2, 7, 2}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xb1, -1, 1, 0, 682, 0, 2, 7, 2}, // (subframe number) 1,3,5,7,9 -{0xb4, -1, 16, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9 -{0xb4, -1, 16, 1, 16, 0, 2, 1, 12}, // (subframe number) 4 -{0xb4, -1, 8, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9 -{0xb4, -1, 8, 1, 16, 0, 2, 1, 12}, // (subframe number) 4 -{0xb4, -1, 4, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9 -{0xb4, -1, 4, 0, 16, 0, 2, 1, 12}, // (subframe number) 4 -{0xb4, -1, 4, 1, 528, 0, 2, 1, 12}, // (subframe number) 4,9 -{0xb4, -1, 2, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9 -{0xb4, -1, 2, 0, 2, 0, 2, 1, 12}, // (subframe number) 1 -{0xb4, -1, 2, 0, 16, 0, 2, 1, 12}, // (subframe number) 4 -{0xb4, -1, 2, 0, 128, 0, 2, 1, 12}, // (subframe number) 7 -{0xb4, -1, 1, 0, 2, 0, 2, 1, 12}, // (subframe number) 1 -{0xb4, -1, 1, 0, 16, 0, 2, 1, 12}, // (subframe number) 4 -{0xb4, -1, 1, 0, 128, 0, 2, 1, 12}, // (subframe number) 7 -{0xb4, -1, 1, 0, 66, 0, 2, 1, 12}, // (subframe number) 1,6 -{0xb4, -1, 1, 0, 132, 0, 2, 1, 12}, // (subframe number) 2,7 -{0xb4, -1, 1, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9 -{0xb4, -1, 1, 0, 146, 0, 2, 1, 12}, // (subframe number) 1,4,7 -{0xb4, -1, 1, 0, 341, 0, 2, 1, 12}, // (subframe number) 0,2,4,6,8 -{0xb4, -1, 1, 0, 1023, 0, 2, 1, 12}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xb4, -1, 1, 0, 682, 0, 2, 1, 12}, // (subframe number) 1,3,5,7,9 -{0xc0, -1, 8, 1, 16, 0, 2, 7, 2}, // (subframe number) 4 -{0xc0, -1, 4, 1, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xc0, -1, 4, 0, 16, 0, 2, 7, 2}, // (subframe number) 4 -{0xc0, -1, 2, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xc0, -1, 2, 0, 2, 0, 2, 7, 2}, // (subframe number) 1 -{0xc0, -1, 2, 0, 16, 0, 2, 7, 2}, // (subframe number) 4 -{0xc0, -1, 2, 0, 128, 0, 2, 7, 2}, // (subframe number) 7 -{0xc0, -1, 1, 0, 16, 0, 1, 7, 2}, // (subframe number) 4 -{0xc0, -1, 1, 0, 66, 0, 1, 7, 2}, // (subframe number) 1,6 -{0xc0, -1, 1, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9 -{0xc0, -1, 1, 0, 2, 0, 2, 7, 2}, // (subframe number) 1 -{0xc0, -1, 1, 0, 128, 0, 2, 7, 2}, // (subframe number) 7 -{0xc0, -1, 1, 0, 132, 0, 2, 7, 2}, // (subframe number) 2,7 -{0xc0, -1, 1, 0, 146, 0, 2, 7, 2}, // (subframe number) 1,4,7 -{0xc0, -1, 1, 0, 341, 0, 2, 7, 2}, // (subframe number) 0,2,4,6,8 -{0xc0, -1, 1, 0, 1023, 0, 2, 7, 2}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xc0, -1, 1, 0, 682, 0, 2, 7, 2}, // (subframe number) 1,3,5,7,9 -{0xc2, -1, 16, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xc2, -1, 16, 1, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xc2, -1, 8, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xc2, -1, 8, 1, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xc2, -1, 4, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xc2, -1, 4, 0, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xc2, -1, 2, 1, 580, 0, 2, 2, 6}, // (subframe number) 2,6,9 -{0xc2, -1, 2, 0, 2, 0, 2, 2, 6}, // (subframe number) 1 -{0xc2, -1, 2, 0, 16, 0, 2, 2, 6}, // (subframe number) 4 -{0xc2, -1, 2, 0, 128, 0, 2, 2, 6}, // (subframe number) 7 -{0xc2, -1, 1, 0, 16, 0, 1, 2, 6}, // (subframe number) 4 -{0xc2, -1, 1, 0, 66, 0, 1, 2, 6}, // (subframe number) 1,6 -{0xc2, -1, 1, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9 -{0xc2, -1, 1, 0, 2, 0, 2, 2, 6}, // (subframe number) 1 -{0xc2, -1, 1, 0, 128, 0, 2, 2, 6}, // (subframe number) 7 -{0xc2, -1, 1, 0, 132, 0, 2, 2, 6}, // (subframe number) 2,7 -{0xc2, -1, 1, 0, 146, 0, 2, 2, 6}, // (subframe number) 1,4,7 -{0xc2, -1, 1, 0, 341, 0, 2, 2, 6}, // (subframe number) 0,2,4,6,8 -{0xc2, -1, 1, 0, 1023, 0, 2, 2, 6}, // (subframe number) 0,1,2,3,4,5,6,7,8,9 -{0xc2, -1, 1, 0, 682, 0, 2, 2, 6} // (subframe number) 1,3,5,7,9 -}; -// Table 6.3.3.2-3: Random access configurations for FR1 and unpaired spectrum -int64_t table_6_3_3_2_3_prachConfig_Index [256][9] = { -//format, format, x, y, SFN_nbr, star_symb, slots_sfn, occ_slot, duration -{0, -1, 16, 1, 512, 0, -1, -1, 0}, // (subrame number 9) -{0, -1, 8, 1, 512, 0, -1, -1, 0}, // (subrame number 9) -{0, -1, 4, 1, 512, 0, -1, -1, 0}, // (subrame number 9) -{0, -1, 2, 0, 512, 0, -1, -1, 0}, // (subrame number 9) -{0, -1, 2, 1, 512, 0, -1, -1, 0}, // (subrame number 9) -{0, -1, 2, 0, 16, 0, -1, -1, 0}, // (subrame number 4) -{0, -1, 2, 1, 16, 0, -1, -1, 0}, // (subrame number 4) -{0, -1, 1, 0, 512, 0, -1, -1, 0}, // (subrame number 9) -{0, -1, 1, 0, 256, 0, -1, -1, 0}, // (subrame number 8) -{0, -1, 1, 0, 128, 0, -1, -1, 0}, // (subrame number 7) -{0, -1, 1, 0, 64, 0, -1, -1, 0}, // (subrame number 6) -{0, -1, 1, 0, 32, 0, -1, -1, 0}, // (subrame number 5) -{0, -1, 1, 0, 16, 0, -1, -1, 0}, // (subrame number 4) -{0, -1, 1, 0, 8, 0, -1, -1, 0}, // (subrame number 3) -{0, -1, 1, 0, 4, 0, -1, -1, 0}, // (subrame number 2) -{0, -1, 1, 0, 66, 0, -1, -1, 0}, // (subrame number 1,6) -{0, -1, 1, 0, 66, 7, -1, -1, 0}, // (subrame number 1,6) -{0, -1, 1, 0, 528, 0, -1, -1, 0}, // (subrame number 4,9) -{0, -1, 1, 0, 264, 0, -1, -1, 0}, // (subrame number 3,8) -{0, -1, 1, 0, 132, 0, -1, -1, 0}, // (subrame number 2,7) -{0, -1, 1, 0, 768, 0, -1, -1, 0}, // (subrame number 8,9) -{0, -1, 1, 0, 784, 0, -1, -1, 0}, // (subrame number 4,8,9) -{0, -1, 1, 0, 536, 0, -1, -1, 0}, // (subrame number 3,4,9) -{0, -1, 1, 0, 896, 0, -1, -1, 0}, // (subrame number 7,8,9) -{0, -1, 1, 0, 792, 0, -1, -1, 0}, // (subrame number 3,4,8,9) -{0, -1, 1, 0, 960, 0, -1, -1, 0}, // (subrame number 6,7,8,9) -{0, -1, 1, 0, 594, 0, -1, -1, 0}, // (subrame number 1,4,6,9) -{0, -1, 1, 0, 682, 0, -1, -1, 0}, // (subrame number 1,3,5,7,9) -{1, -1, 16, 1, 128, 0, -1, -1, 0}, // (subrame number 7) -{1, -1, 8, 1, 128, 0, -1, -1, 0}, // (subrame number 7) -{1, -1, 4, 1, 128, 0, -1, -1, 0}, // (subrame number 7) -{1, -1, 2, 0, 128, 0, -1, -1, 0}, // (subrame number 7) -{1, -1, 2, 1, 128, 0, -1, -1, 0}, // (subrame number 7) -{1, -1, 1, 0, 128, 0, -1, -1, 0}, // (subrame number 7) -{2, -1, 16, 1, 64, 0, -1, -1, 0}, // (subrame number 6) -{2, -1, 8, 1, 64, 0, -1, -1, 0}, // (subrame number 6) -{2, -1, 4, 1, 64, 0, -1, -1, 0}, // (subrame number 6) -{2, -1, 2, 0, 64, 7, -1, -1, 0}, // (subrame number 6) -{2, -1, 2, 1, 64, 7, -1, -1, 0}, // (subrame number 6) -{2, -1, 1, 0, 64, 7, -1, -1, 0}, // (subrame number 6) -{3, -1, 16, 1, 512, 0, -1, -1, 0}, // (subrame number 9) -{3, -1, 8, 1, 512, 0, -1, -1, 0}, // (subrame number 9) -{3, -1, 4, 1, 512, 0, -1, -1, 0}, // (subrame number 9) -{3, -1, 2, 0, 512, 0, -1, -1, 0}, // (subrame number 9) -{3, -1, 2, 1, 512, 0, -1, -1, 0}, // (subrame number 9) -{3, -1, 2, 0, 16, 0, -1, -1, 0}, // (subrame number 4) -{3, -1, 2, 1, 16, 0, -1, -1, 0}, // (subrame number 4) -{3, -1, 1, 0, 512, 0, -1, -1, 0}, // (subrame number 9) -{3, -1, 1, 0, 256, 0, -1, -1, 0}, // (subrame number 8) -{3, -1, 1, 0, 128, 0, -1, -1, 0}, // (subrame number 7) -{3, -1, 1, 0, 64, 0, -1, -1, 0}, // (subrame number 6) -{3, -1, 1, 0, 32, 0, -1, -1, 0}, // (subrame number 5) -{3, -1, 1, 0, 16, 0, -1, -1, 0}, // (subrame number 4) -{3, -1, 1, 0, 8, 0, -1, -1, 0}, // (subrame number 3) -{3, -1, 1, 0, 4, 0, -1, -1, 0}, // (subrame number 2) -{3, -1, 1, 0, 66, 0, -1, -1, 0}, // (subrame number 1,6) -{3, -1, 1, 0, 66, 7, -1, -1, 0}, // (subrame number 1,6) -{3, -1, 1, 0, 528, 0, -1, -1, 0}, // (subrame number 4,9) -{3, -1, 1, 0, 264, 0, -1, -1, 0}, // (subrame number 3,8) -{3, -1, 1, 0, 132, 0, -1, -1, 0}, // (subrame number 2,7) -{3, -1, 1, 0, 768, 0, -1, -1, 0}, // (subrame number 8,9) -{3, -1, 1, 0, 784, 0, -1, -1, 0}, // (subrame number 4,8,9) -{3, -1, 1, 0, 536, 0, -1, -1, 0}, // (subrame number 3,4,9) -{3, -1, 1, 0, 896, 0, -1, -1, 0}, // (subrame number 7,8,9) -{3, -1, 1, 0, 792, 0, -1, -1, 0}, // (subrame number 3,4,8,9) -{3, -1, 1, 0, 594, 0, -1, -1, 0}, // (subrame number 1,4,6,9) -{3, -1, 1, 0, 682, 0, -1, -1, 0}, // (subrame number 1,3,5,7,9) -{0xa1, -1, 16, 1, 512, 0, 2, 6, 2}, // (subrame number 9) -{0xa1, -1, 8, 1, 512, 0, 2, 6, 2}, // (subrame number 9) -{0xa1, -1, 4, 1, 512, 0, 1, 6, 2}, // (subrame number 9) -{0xa1, -1, 2, 1, 512, 0, 1, 6, 2}, // (subrame number 9) -{0xa1, -1, 2, 1, 528, 7, 1, 3, 2}, // (subrame number 4,9) -{0xa1, -1, 2, 1, 640, 7, 1, 3, 2}, // (subrame number 7,9) -{0xa1, -1, 2, 1, 640, 0, 1, 6, 2}, // (subrame number 7,9) -{0xa1, -1, 2, 1, 768, 0, 2, 6, 2}, // (subrame number 8,9) -{0xa1, -1, 2, 1, 528, 0, 2, 6, 2}, // (subrame number 4,9) -{0xa1, -1, 2, 1, 924, 0, 1, 6, 2}, // (subrame number 2,3,4,7,8,9) -{0xa1, -1, 1, 0, 512, 0, 2, 6, 2}, // (subrame number 9) -{0xa1, -1, 1, 0, 512, 7, 1, 3, 2}, // (subrame number 9) -{0xa1, -1, 1, 0, 512, 0, 1, 6, 2}, // (subrame number 9) -{0xa1, -1, 1, 0, 768, 0, 2, 6, 2}, // (subrame number 8,9) -{0xa1, -1, 1, 0, 528, 0, 1, 6, 2}, // (subrame number 4,9) -{0xa1, -1, 1, 0, 640, 7, 1, 3, 2}, // (subrame number 7,9) -{0xa1, -1, 1, 0, 792, 0, 1, 6, 2}, // (subrame number 3,4,8,9) -{0xa1, -1, 1, 0, 792, 0, 2, 6, 2}, // (subrame number 3,4,8,9) -{0xa1, -1, 1, 0, 682, 0, 1, 6, 2}, // (subrame number 1,3,5,7,9) -{0xa1, -1, 1, 0, 1023, 7, 1, 3, 2}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xa2, -1, 16, 1, 512, 0, 2, 3, 4}, // (subrame number 9) -{0xa2, -1, 8, 1, 512, 0, 2, 3, 4}, // (subrame number 9) -{0xa2, -1, 4, 1, 512, 0, 1, 3, 4}, // (subrame number 9) -{0xa2, -1, 2, 1, 640, 0, 1, 3, 4}, // (subrame number 7,9) -{0xa2, -1, 2, 1, 768, 0, 2, 3, 4}, // (subrame number 8,9) -{0xa2, -1, 2, 1, 640, 9, 1, 1, 4}, // (subrame number 7,9) -{0xa2, -1, 2, 1, 528, 9, 1, 1, 4}, // (subrame number 4,9) -{0xa2, -1, 2, 1, 528, 0, 2, 3, 4}, // (subrame number 4,9) -{0xa2, -1, 16, 1, 924, 0, 1, 3, 4}, // (subrame number 2,3,4,7,8,9) -{0xa2, -1, 1, 0, 4, 0, 1, 3, 4}, // (subrame number 2) -{0xa2, -1, 1, 0, 128, 0, 1, 3, 4}, // (subrame number 7) -{0xa2, -1, 2, 1, 512, 0, 1, 3, 4}, // (subrame number 9) -{0xa2, -1, 1, 0, 512, 0, 2, 3, 4}, // (subrame number 9) -{0xa2, -1, 1, 0, 512, 9, 1, 1, 4}, // (subrame number 9) -{0xa2, -1, 1, 0, 512, 0, 1, 3, 4}, // (subrame number 9) -{0xa2, -1, 1, 0, 132, 0, 1, 3, 4}, // (subrame number 2,7) -{0xa2, -1, 1, 0, 768, 0, 2, 3, 4}, // (subrame number 8,9) -{0xa2, -1, 1, 0, 528, 0, 1, 3, 4}, // (subrame number 4,9) -{0xa2, -1, 1, 0, 640, 9, 1, 1, 4}, // (subrame number 7,9) -{0xa2, -1, 1, 0, 792, 0, 1, 3, 4}, // (subrame number 3,4,8,9) -{0xa2, -1, 1, 0, 792, 0, 2, 3, 4}, // (subrame number 3,4,8,9) -{0xa2, -1, 1, 0, 682, 0, 1, 3, 4}, // (subrame number 1,3,5,7,9) -{0xa2, -1, 1, 0, 1023, 9, 1, 1, 4}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xa3, -1, 16, 1, 512, 0, 2, 2, 6}, // (subrame number 9) -{0xa3, -1, 8, 1, 512, 0, 2, 2, 6}, // (subrame number 9) -{0xa3, -1, 4, 1, 512, 0, 1, 2, 6}, // (subrame number 9) -{0xa3, -1, 2, 1, 528, 7, 1, 1, 6}, // (subrame number 4,9) -{0xa3, -1, 2, 1, 640, 7, 1, 1, 6}, // (subrame number 7,9) -{0xa3, -1, 2, 1, 640, 0, 1, 2, 6}, // (subrame number 7,9) -{0xa3, -1, 2, 1, 528, 0, 2, 2, 6}, // (subrame number 4,9) -{0xa3, -1, 2, 1, 768, 0, 2, 2, 6}, // (subrame number 8,9) -{0xa3, -1, 2, 1, 924, 0, 1, 2, 6}, // (subrame number 2,3,4,7,8,9) -{0xa3, -1, 1, 0, 4, 0, 1, 2, 6}, // (subrame number 2) -{0xa3, -1, 1, 0, 128, 0, 1, 2, 6}, // (subrame number 7) -{0xa3, -1, 2, 1, 512, 0, 1, 2, 6}, // (subrame number 9) -{0xa3, -1, 1, 0, 512, 0, 2, 2, 6}, // (subrame number 9) -{0xa3, -1, 1, 0, 512, 7, 1, 1, 6}, // (subrame number 9) -{0xa3, -1, 1, 0, 512, 0, 1, 2, 6}, // (subrame number 9) -{0xa3, -1, 1, 0, 132, 0, 1, 2, 6}, // (subrame number 2,7) -{0xa3, -1, 1, 0, 768, 0, 2, 2, 6}, // (subrame number 8,9) -{0xa3, -1, 1, 0, 528, 0, 1, 2, 6}, // (subrame number 4,9) -{0xa3, -1, 1, 0, 640, 7, 1, 1, 6}, // (subrame number 7,9) -{0xa3, -1, 1, 0, 792, 0, 1, 2, 6}, // (subrame number 3,4,8,9) -{0xa3, -1, 1, 0, 792, 0, 2, 2, 6}, // (subrame number 3,4,8,9) -{0xa3, -1, 1, 0, 682, 0, 1, 2, 6}, // (subrame number 1,3,5,7,9) -{0xa3, -1, 1, 0, 1023, 7, 1, 1, 6}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xb1, -1, 4, 1, 512, 2, 1, 6, 2}, // (subrame number 9) -{0xb1, -1, 2, 1, 512, 2, 1, 6, 2}, // (subrame number 9) -{0xb1, -1, 2, 1, 640, 2, 1, 6, 2}, // (subrame number 7,9) -{0xb1, -1, 2, 1, 528, 8, 1, 3, 2}, // (subrame number 4,9) -{0xb1, -1, 2, 1, 528, 2, 2, 6, 2}, // (subrame number 4,9) -{0xb1, -1, 1, 0, 512, 2, 2, 6, 2}, // (subrame number 9) -{0xb1, -1, 1, 0, 512, 8, 1, 3, 2}, // (subrame number 9) -{0xb1, -1, 1, 0, 512, 2, 1, 6, 2}, // (subrame number 9) -{0xb1, -1, 1, 0, 768, 2, 2, 6, 2}, // (subrame number 8,9) -{0xb1, -1, 1, 0, 528, 2, 1, 6, 2}, // (subrame number 4,9) -{0xb1, -1, 1, 0, 640, 8, 1, 3, 2}, // (subrame number 7,9) -{0xb1, -1, 1, 0, 682, 2, 1, 6, 2}, // (subrame number 1,3,5,7,9) -{0xb4, -1, 16, 1, 512, 0, 2, 1, 12}, // (subrame number 9) -{0xb4, -1, 8, 1, 512, 0, 2, 1, 12}, // (subrame number 9) -{0xb4, -1, 4, 1, 512, 2, 1, 1, 12}, // (subrame number 9) -{0xb4, -1, 2, 1, 512, 0, 1, 1, 12}, // (subrame number 9) -{0xb4, -1, 2, 1, 512, 2, 1, 1, 12}, // (subrame number 9) -{0xb4, -1, 2, 1, 640, 2, 1, 1, 12}, // (subrame number 7,9) -{0xb4, -1, 2, 1, 528, 2, 1, 1, 12}, // (subrame number 4,9) -{0xb4, -1, 2, 1, 528, 0, 2, 1, 12}, // (subrame number 4,9) -{0xb4, -1, 2, 1, 768, 0, 2, 1, 12}, // (subrame number 8,9) -{0xb4, -1, 2, 1, 924, 0, 1, 1, 12}, // (subrame number 2,3,4,7,8,9) -{0xb4, -1, 1, 0, 2, 0, 1, 1, 12}, // (subrame number 1) -{0xb4, -1, 1, 0, 4, 0, 1, 1, 12}, // (subrame number 2) -{0xb4, -1, 1, 0, 16, 0, 1, 1, 12}, // (subrame number 4) -{0xb4, -1, 1, 0, 128, 0, 1, 1, 12}, // (subrame number 7) -{0xb4, -1, 1, 0, 512, 0, 1, 1, 12}, // (subrame number 9) -{0xb4, -1, 1, 0, 512, 2, 1, 1, 12}, // (subrame number 9) -{0xb4, -1, 1, 0, 512, 0, 2, 1, 12}, // (subrame number 9) -{0xb4, -1, 1, 0, 528, 2, 1, 1, 12}, // (subrame number 4,9) -{0xb4, -1, 1, 0, 640, 2, 1, 1, 12}, // (subrame number 7,9) -{0xb4, -1, 1, 0, 768, 0, 2, 1, 12}, // (subrame number 8,9) -{0xb4, -1, 1, 0, 792, 2, 1, 1, 12}, // (subrame number 3,4,8,9) -{0xb4, -1, 1, 0, 682, 2, 1, 1, 12}, // (subrame number 1,3,5,7,9) -{0xb4, -1, 1, 0, 1023, 0, 2, 1, 12}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xb4, -1, 1, 0, 1023, 2, 1, 1, 12}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xc0, -1, 16, 1, 512, 2, 2, 6, 2}, // (subrame number 9) -{0xc0, -1, 8, 1, 512, 2, 2, 6, 2}, // (subrame number 9) -{0xc0, -1, 4, 1, 512, 2, 1, 6, 2}, // (subrame number 9) -{0xc0, -1, 2, 1, 512, 2, 1, 6, 2}, // (subrame number 9) -{0xc0, -1, 2, 1, 768, 2, 2, 6, 2}, // (subrame number 8,9) -{0xc0, -1, 2, 1, 640, 2, 1, 6, 2}, // (subrame number 7,9) -{0xc0, -1, 2, 1, 640, 8, 1, 3, 2}, // (subrame number 7,9) -{0xc0, -1, 2, 1, 528, 8, 1, 3, 2}, // (subrame number 4,9) -{0xc0, -1, 2, 1, 528, 2, 2, 6, 2}, // (subrame number 4,9) -{0xc0, -1, 2, 1, 924, 2, 1, 6, 2}, // (subrame number 2,3,4,7,8,9) -{0xc0, -1, 1, 0, 512, 2, 2, 6, 2}, // (subrame number 9) -{0xc0, -1, 1, 0, 512, 8, 1, 3, 2}, // (subrame number 9) -{0xc0, -1, 1, 0, 512, 2, 1, 6, 2}, // (subrame number 9) -{0xc0, -1, 1, 0, 768, 2, 2, 6, 2}, // (subrame number 8,9) -{0xc0, -1, 1, 0, 528, 2, 1, 6, 2}, // (subrame number 4,9) -{0xc0, -1, 1, 0, 640, 8, 1, 3, 2}, // (subrame number 7,9) -{0xc0, -1, 1, 0, 792, 2, 1, 6, 2}, // (subrame number 3,4,8,9) -{0xc0, -1, 1, 0, 792, 2, 2, 6, 2}, // (subrame number 3,4,8,9) -{0xc0, -1, 1, 0, 682, 2, 1, 6, 2}, // (subrame number 1,3,5,7,9) -{0xc0, -1, 1, 0, 1023, 8, 1, 3, 2}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xc2, -1, 16, 1, 512, 2, 2, 2, 6}, // (subrame number 9) -{0xc2, -1, 8, 1, 512, 2, 2, 2, 6}, // (subrame number 9) -{0xc2, -1, 4, 1, 512, 2, 1, 2, 6}, // (subrame number 9) -{0xc2, -1, 2, 1, 512, 2, 1, 2, 6}, // (subrame number 9) -{0xc2, -1, 2, 1, 768, 2, 2, 2, 6}, // (subrame number 8,9) -{0xc2, -1, 2, 1, 640, 2, 1, 2, 6}, // (subrame number 7,9) -{0xc2, -1, 2, 1, 640, 8, 1, 1, 6}, // (subrame number 7,9) -{0xc2, -1, 2, 1, 528, 8, 1, 1, 6}, // (subrame number 4,9) -{0xc2, -1, 2, 1, 528, 2, 2, 2, 6}, // (subrame number 4,9) -{0xc2, -1, 2, 1, 924, 2, 1, 2, 6}, // (subrame number 2,3,4,7,8,9) -{0xc2, -1, 8, 1, 512, 8, 2, 1, 6}, // (subrame number 9) -{0xc2, -1, 4, 1, 512, 8, 1, 1, 6}, // (subrame number 9) -{0xc2, -1, 1, 0, 512, 2, 2, 2, 6}, // (subrame number 9) -{0xc2, -1, 1, 0, 512, 8, 1, 1, 6}, // (subrame number 9) -{0xc2, -1, 1, 0, 512, 2, 1, 2, 6}, // (subrame number 9) -{0xc2, -1, 1, 0, 768, 2, 2, 2, 6}, // (subrame number 8,9) -{0xc2, -1, 1, 0, 528, 2, 1, 2, 6}, // (subrame number 4,9) -{0xc2, -1, 1, 0, 640, 8, 1, 1, 6}, // (subrame number 7,9) -{0xc2, -1, 1, 0, 792, 2, 1, 2, 6}, // (subrame number 3,4,8,9) -{0xc2, -1, 1, 0, 792, 2, 2, 2, 6}, // (subrame number 3,4,8,9) -{0xc2, -1, 1, 0, 682, 2, 1, 2, 6}, // (subrame number 1,3,5,7,9) -{0xc2, -1, 1, 0, 1023, 8, 1, 1, 6}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xa1, 0xb1, 2, 1, 512, 2, 1, 6, 2}, // (subrame number 9) -{0xa1, 0xb1, 2, 1, 528, 8, 1, 3, 2}, // (subrame number 4,9) -{0xa1, 0xb1, 2, 1, 640, 8, 1, 3, 2}, // (subrame number 7,9) -{0xa1, 0xb1, 2, 1, 640, 2, 1, 6, 2}, // (subrame number 7,9) -{0xa1, 0xb1, 2, 1, 528, 2, 2, 6, 2}, // (subrame number 4,9) -{0xa1, 0xb1, 2, 1, 768, 2, 2, 6, 2}, // (subrame number 8,9) -{0xa1, 0xb1, 1, 0, 512, 2, 2, 6, 2}, // (subrame number 9) -{0xa1, 0xb1, 1, 0, 512, 8, 1, 3, 2}, // (subrame number 9) -{0xa1, 0xb1, 1, 0, 512, 2, 1, 6, 2}, // (subrame number 9) -{0xa1, 0xb1, 1, 0, 768, 2, 2, 6, 2}, // (subrame number 8,9) -{0xa1, 0xb1, 1, 0, 528, 2, 1, 6, 2}, // (subrame number 4,9) -{0xa1, 0xb1, 1, 0, 640, 8, 1, 3, 2}, // (subrame number 7,9) -{0xa1, 0xb1, 1, 0, 792, 2, 2, 6, 2}, // (subrame number 3,4,8,9) -{0xa1, 0xb1, 1, 0, 682, 2, 1, 6, 2}, // (subrame number 1,3,5,7,9) -{0xa1, 0xb1, 1, 0, 1023, 8, 1, 3, 2}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xa2, 0xb2, 2, 1, 512, 0, 1, 3, 4}, // (subrame number 9) -{0xa2, 0xb2, 2, 1, 528, 6, 1, 2, 4}, // (subrame number 4,9) -{0xa2, 0xb2, 2, 1, 640, 6, 1, 2, 4}, // (subrame number 7,9) -{0xa2, 0xb2, 2, 1, 528, 0, 2, 3, 4}, // (subrame number 4,9) -{0xa2, 0xb2, 2, 1, 768, 0, 2, 3, 4}, // (subrame number 8,9) -{0xa2, 0xb2, 1, 0, 512, 0, 2, 3, 4}, // (subrame number 9) -{0xa2, 0xb2, 1, 0, 512, 6, 1, 2, 4}, // (subrame number 9) -{0xa2, 0xb2, 1, 0, 512, 0, 1, 3, 4}, // (subrame number 9) -{0xa2, 0xb2, 1, 0, 768, 0, 2, 3, 4}, // (subrame number 8,9) -{0xa2, 0xb2, 1, 0, 528, 0, 1, 3, 4}, // (subrame number 4,9) -{0xa2, 0xb2, 1, 0, 640, 6, 1, 2, 4}, // (subrame number 7,9) -{0xa2, 0xb2, 1, 0, 792, 0, 1, 3, 4}, // (subrame number 3,4,8,9) -{0xa2, 0xb2, 1, 0, 792, 0, 2, 3, 4}, // (subrame number 3,4,8,9) -{0xa2, 0xb2, 1, 0, 682, 0, 1, 3, 4}, // (subrame number 1,3,5,7,9) -{0xa2, 0xb2, 1, 0, 1023, 6, 1, 2, 4}, // (subrame number 0,1,2,3,4,5,6,7,8,9) -{0xa3, 0xb3, 2, 1, 512, 0, 1, 2, 6}, // (subrame number 9) -{0xa3, 0xb3, 2, 1, 528, 2, 1, 2, 6}, // (subrame number 4,9) -{0xa3, 0xb3, 2, 1, 640, 0, 1, 2, 6}, // (subrame number 7,9) -{0xa3, 0xb3, 2, 1, 640, 2, 1, 2, 6}, // (subrame number 7,9) -{0xa3, 0xb3, 2, 1, 528, 0, 2, 2, 6}, // (subrame number 4,9) -{0xa3, 0xb3, 2, 1, 768, 0, 2, 2, 6}, // (subrame number 8,9) -{0xa3, 0xb3, 1, 0, 512, 0, 2, 2, 6}, // (subrame number 9) -{0xa3, 0xb3, 1, 0, 512, 2, 1, 2, 6}, // (subrame number 9) -{0xa3, 0xb3, 1, 0, 512, 0, 1, 2, 6}, // (subrame number 9) -{0xa3, 0xb3, 1, 0, 768, 0, 2, 2, 6}, // (subrame number 8,9) -{0xa3, 0xb3, 1, 0, 528, 0, 1, 2, 6}, // (subrame number 4,9) -{0xa3, 0xb3, 1, 0, 640, 2, 1, 2, 6}, // (subrame number 7,9) -{0xa3, 0xb3, 1, 0, 792, 0, 2, 2, 6}, // (subrame number 3,4,8,9) -{0xa3, 0xb3, 1, 0, 682, 0, 1, 2, 6}, // (subrame number 1,3,5,7,9) -{0xa3, 0xb3, 1, 0, 1023, 2, 1, 2, 6} // (subrame number 0,1,2,3,4,5,6,7,8,9) -}; -// Table 6.3.3.2-4: Random access configurations for FR2 and unpaired spectrum -int64_t table_6_3_3_2_4_prachConfig_Index [256][10] = { -//format, format, x, y, y, SFN_nbr, star_symb, slots_sfn, occ_slot, duration -{0xa1, -1, 16, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, -1, 16, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, -1, 8, 1, 2, 550293209600, 0, 2, 6, 2}, // (subframe number :9,19,29,39) -{0xa1, -1, 8, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, -1, 8, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, -1, 4, 1, -1, 567489872400, 0, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, -1, 4, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, -1, 4, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, -1, 2, 1, -1, 551911719040, 0, 2, 6, 2}, // (subframe number :7,15,23,31,39) -{0xa1, -1, 2, 1, -1, 567489872400, 0, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, -1, 2, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, -1, 2, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, -1, 1, 0, -1, 549756338176, 7, 1, 3, 2}, // (subframe number :19,39) -{0xa1, -1, 1, 0, -1, 168, 0, 1, 6, 2}, // (subframe number :3,5,7) -{0xa1, -1, 1, 0, -1, 567489331200, 7, 1, 3, 2}, // (subframe number :24,29,34,39) -{0xa1, -1, 1, 0, -1, 550293209600, 7, 2, 3, 2}, // (subframe number :9,19,29,39) -{0xa1, -1, 1, 0, -1, 687195422720, 0, 1, 6, 2}, // (subframe number :17,19,37,39) -{0xa1, -1, 1, 0, -1, 550293209600, 0, 2, 6, 2}, // (subframe number :9,19,29,39) -{0xa1, -1, 1, 0, -1, 567489872400, 0, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, -1, 1, 0, -1, 567489872400, 7, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, -1, 1, 0, -1, 10920, 7, 1, 3, 2}, // (subframe number :3,5,7,9,11,13) -{0xa1, -1, 1, 0, -1, 586405642240, 7, 1, 3, 2}, // (subframe number :23,27,31,35,39) -{0xa1, -1, 1, 0, -1, 551911719040, 0, 1, 6, 2}, // (subframe number :7,15,23,31,39) -{0xa1, -1, 1, 0, -1, 586405642240, 0, 1, 6, 2}, // (subframe number :23,27,31,35,39) -{0xa1, -1, 1, 0, -1, 965830828032, 7, 2, 3, 2}, // (subframe number :13,14,15, 29,30,31,37,38,39) -{0xa1, -1, 1, 0, -1, 586406201480, 7, 1, 3, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, -1, 1, 0, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, -1, 1, 0, -1, 733007751850, 0, 1, 6, 2}, // (subframe number :1,3,5,7,…,37,39) -{0xa1, -1, 1, 0, -1, 1099511627775, 7, 1, 3, 2}, // (subframe number :0,1,2,…,39) -{0xa2, -1, 16, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, -1, 16, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, -1, 8, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, -1, 8, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, -1, 8, 1, 2, 550293209600, 0, 2, 3, 4}, // (subframe number :9,19,29,39) -{0xa2, -1, 4, 1, -1, 567489872400, 0, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, -1, 4, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, -1, 4, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, -1, 2, 1, -1, 551911719040, 0, 2, 3, 4}, // (subframe number :7,15,23,31,39) -{0xa2, -1, 2, 1, -1, 567489872400, 0, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, -1, 2, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, -1, 2, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, -1, 1, 0, -1, 549756338176, 5, 1, 2, 4}, // (subframe number :19,39) -{0xa2, -1, 1, 0, -1, 168, 0, 1, 3, 4}, // (subframe number :3,5,7) -{0xa2, -1, 1, 0, -1, 567489331200, 5, 1, 2, 4}, // (subframe number :24,29,34,39) -{0xa2, -1, 1, 0, -1, 550293209600, 5, 2, 2, 4}, // (subframe number :9,19,29,39) -{0xa2, -1, 1, 0, -1, 687195422720, 0, 1, 3, 4}, // (subframe number :17,19,37,39) -{0xa2, -1, 1, 0, -1, 550293209600, 0, 2, 3, 4}, // (subframe number :9, 19, 29, 39) -{0xa2, -1, 1, 0, -1, 551911719040, 0, 1, 3, 4}, // (subframe number :7,15,23,31,39) -{0xa2, -1, 1, 0, -1, 586405642240, 5, 1, 2, 4}, // (subframe number :23,27,31,35,39) -{0xa2, -1, 1, 0, -1, 586405642240, 0, 1, 3, 4}, // (subframe number :23,27,31,35,39) -{0xa2, -1, 1, 0, -1, 10920, 5, 1, 2, 4}, // (subframe number :3,5,7,9,11,13) -{0xa2, -1, 1, 0, -1, 10920, 0, 1, 3, 4}, // (subframe number :3,5,7,9,11,13) -{0xa2, -1, 1, 0, -1, 567489872400, 5, 1, 2, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, -1, 1, 0, -1, 567489872400, 0, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, -1, 1, 0, -1, 965830828032, 5, 2, 2, 4}, // (subframe number :13,14,15, 29,30,31,37,38,39) -{0xa2, -1, 1, 0, -1, 586406201480, 5, 1, 2, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, -1, 1, 0, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, -1, 1, 0, -1, 733007751850, 0, 1, 3, 4}, // (subframe number :1,3,5,7,…,37,39) -{0xa2, -1, 1, 0, -1, 1099511627775, 5, 1, 2, 4}, // (subframe number :0,1,2,…,39) -{0xa3, -1, 16, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, -1, 16, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, -1, 8, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, -1, 8, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, -1, 8, 1, 2, 550293209600, 0, 2, 2, 6}, // (subframe number :9,19,29,39) -{0xa3, -1, 4, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, -1, 4, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, -1, 4, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, -1, 2, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, -1, 2, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, -1, 2, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, -1, 1, 0, -1, 549756338176, 7, 1, 1, 6}, // (subframe number :19,39) -{0xa3, -1, 1, 0, -1, 168, 0, 1, 2, 6}, // (subframe number :3,5,7) -{0xa3, -1, 1, 0, -1, 10752, 2, 1, 2, 6}, // (subframe number :9,11,13) -{0xa3, -1, 1, 0, -1, 567489331200, 7, 1, 1, 6}, // (subframe number :24,29,34,39) -{0xa3, -1, 1, 0, -1, 550293209600, 7, 2, 1, 6}, // (subframe number :9,19,29,39) -{0xa3, -1, 1, 0, -1, 687195422720, 0, 1, 2, 6}, // (subframe number :17,19,37,39) -{0xa3, -1, 1, 0, -1, 550293209600, 0, 2, 2, 6}, // (subframe number :9,19,29,39) -{0xa3, -1, 1, 0, -1, 551911719040, 0, 1, 2, 6}, // (subframe number :7,15,23,31,39) -{0xa3, -1, 1, 0, -1, 586405642240, 7, 1, 1, 6}, // (subframe number :23,27,31,35,39) -{0xa3, -1, 1, 0, -1, 586405642240, 0, 1, 2, 6}, // (subframe number :23,27,31,35,39) -{0xa3, -1, 1, 0, -1, 10920, 0, 1, 2, 6}, // (subframe number :3,5,7,9,11,13) -{0xa3, -1, 1, 0, -1, 10920, 7, 1, 1, 6}, // (subframe number :3,5,7,9,11,13) -{0xa3, -1, 1, 0, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, -1, 1, 0, -1, 567489872400, 7, 1, 1, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, -1, 1, 0, -1, 965830828032, 7, 2, 1, 6}, // (subframe number :13,14,15, 29,30,31,37,38,39) -{0xa3, -1, 1, 0, -1, 586406201480, 7, 1, 1, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, -1, 1, 0, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, -1, 1, 0, -1, 733007751850, 0, 1, 2, 6}, // (subframe number :1,3,5,7,…,37,39) -{0xa3, -1, 1, 0, -1, 1099511627775, 7, 1, 1, 6}, // (subframe number :0,1,2,…,39) -{0xb1, -1, 16, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb1, -1, 8, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb1, -1, 8, 1, 2, 550293209600, 2, 2, 6, 2}, // (subframe number :9,19,29,39) -{0xb1, -1, 4, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb1, -1, 2, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb1, -1, 2, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb1, -1, 1, 0, -1, 549756338176, 8, 1, 3, 2}, // (subframe number :19,39) -{0xb1, -1, 1, 0, -1, 168, 2, 1, 6, 2}, // (subframe number :3,5,7) -{0xb1, -1, 1, 0, -1, 567489331200, 8, 1, 3, 2}, // (subframe number :24,29,34,39) -{0xb1, -1, 1, 0, -1, 550293209600, 8, 2, 3, 2}, // (subframe number :9,19,29,39) -{0xb1, -1, 1, 0, -1, 687195422720, 2, 1, 6, 2}, // (subframe number :17,19,37,39) -{0xb1, -1, 1, 0, -1, 550293209600, 2, 2, 6, 2}, // (subframe number :9,19,29,39) -{0xb1, -1, 1, 0, -1, 551911719040, 2, 1, 6, 2}, // (subframe number :7,15,23,31,39) -{0xb1, -1, 1, 0, -1, 586405642240, 8, 1, 3, 2}, // (subframe number :23,27,31,35,39) -{0xb1, -1, 1, 0, -1, 586405642240, 2, 1, 6, 2}, // (subframe number :23,27,31,35,39) -{0xb1, -1, 1, 0, -1, 10920, 8, 1, 3, 2}, // (subframe number :3,5,7,9,11,13) -{0xb1, -1, 1, 0, -1, 567489872400, 8, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb1, -1, 1, 0, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb1, -1, 1, 0, -1, 586406201480, 8, 1, 3, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb1, -1, 1, 0, -1, 965830828032, 8, 2, 3, 2}, // (subframe number :13,14,15, 29,30,31,37,38,39) -{0xb1, -1, 1, 0, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb1, -1, 1, 0, -1, 733007751850, 2, 1, 6, 2}, // (subframe number :1,3,5,7,…,37,39) -{0xb1, -1, 1, 0, -1, 1099511627775, 8, 1, 3, 2}, // (subframe number :0,1,2,…,39) -{0xb4, -1, 16, 1, 2, 567489872400, 0, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb4, -1, 16, 1, 2, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb4, -1, 8, 1, 2, 567489872400, 0, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb4, -1, 8, 1, 2, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb4, -1, 8, 1, 2, 550293209600, 0, 2, 1, 12}, // (subframe number :9,19,29,39) -{0xb4, -1, 4, 1, -1, 567489872400, 0, 1, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb4, -1, 4, 1, -1, 567489872400, 0, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb4, -1, 4, 1, 2, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb4, -1, 2, 1, -1, 551911719040, 2, 2, 1, 12}, // (subframe number :7,15,23,31,39) -{0xb4, -1, 2, 1, -1, 567489872400, 0, 1, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb4, -1, 2, 1, -1, 567489872400, 0, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb4, -1, 2, 1, -1, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb4, -1, 1, 0, -1, 549756338176, 2, 2, 1, 12}, // (subframe number :19, 39) -{0xb4, -1, 1, 0, -1, 687195422720, 0, 1, 1, 12}, // (subframe number :17, 19, 37, 39) -{0xb4, -1, 1, 0, -1, 567489331200, 2, 1, 1, 12}, // (subframe number :24,29,34,39) -{0xb4, -1, 1, 0, -1, 550293209600, 2, 2, 1, 12}, // (subframe number :9,19,29,39) -{0xb4, -1, 1, 0, -1, 550293209600, 0, 2, 1, 12}, // (subframe number :9,19,29,39) -{0xb4, -1, 1, 0, -1, 551911719040, 0, 1, 1, 12}, // (subframe number :7,15,23,31,39) -{0xb4, -1, 1, 0, -1, 551911719040, 0, 2, 1, 12}, // (subframe number :7,15,23,31,39) -{0xb4, -1, 1, 0, -1, 586405642240, 0, 1, 1, 12}, // (subframe number :23,27,31,35,39) -{0xb4, -1, 1, 0, -1, 586405642240, 2, 2, 1, 12}, // (subframe number :23,27,31,35,39) -{0xb4, -1, 1, 0, -1, 698880, 0, 1, 1, 12}, // (subframe number :9,11,13,15,17,19) -{0xb4, -1, 1, 0, -1, 10920, 2, 1, 1, 12}, // (subframe number :3,5,7,9,11,13) -{0xb4, -1, 1, 0, -1, 567489872400, 0, 1, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb4, -1, 1, 0, -1, 567489872400, 2, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39) -{0xb4, -1, 1, 0, -1, 965830828032, 2, 2, 1, 12}, // (subframe number :13,14,15, 29,30,31,37,38,39) -{0xb4, -1, 1, 0, -1, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb4, -1, 1, 0, -1, 586406201480, 2, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xb4, -1, 1, 0, -1, 44739240, 2, 1, 1, 12}, // (subframe number :3, 5, 7, …, 23,25) -{0xb4, -1, 1, 0, -1, 44739240, 0, 2, 1, 12}, // (subframe number :3, 5, 7, …, 23,25) -{0xb4, -1, 1, 0, -1, 733007751850, 0, 1, 1, 12}, // (subframe number :1,3,5,7,…,37,39) -{0xb4, -1, 1, 0, -1, 1099511627775, 2, 1, 1, 12}, // (subframe number :0, 1, 2,…, 39) -{0xc0, -1, 16, 1, -1, 567489872400, 0, 2, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc0, -1, 16, 1, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc0, -1, 8, 1, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc0, -1, 8, 1, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc0, -1, 8, 1, 2, 550293209600, 0, 2, 7, 2}, // (subframe number :9,19,29,39) -{0xc0, -1, 4, 1, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc0, -1, 4, 1, -1, 567489872400, 0, 2, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc0, -1, 4, 1, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc0, -1, 2, 1, -1, 551911719040, 0, 2, 7, 2}, // (subframe number :7,15,23,31,39) -{0xc0, -1, 2, 1, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc0, -1, 2, 1, -1, 567489872400, 0, 2, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc0, -1, 2, 1, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc0, -1, 1, 0, -1, 549756338176, 8, 1, 3, 2}, // (subframe number :19,39) -{0xc0, -1, 1, 0, -1, 168, 0, 1, 7, 2}, // (subframe number :3,5,7) -{0xc0, -1, 1, 0, -1, 567489331200, 8, 1, 3, 2}, // (subframe number :24,29,34,39) -{0xc0, -1, 1, 0, -1, 550293209600, 8, 2, 3, 2}, // (subframe number :9,19,29,39) -{0xc0, -1, 1, 0, -1, 687195422720, 0, 1, 7, 2}, // (subframe number :17,19,37,39) -{0xc0, -1, 1, 0, -1, 550293209600, 0, 2, 7, 2}, // (subframe number :9,19,29,39) -{0xc0, -1, 1, 0, -1, 586405642240, 8, 1, 3, 2}, // (subframe number :23,27,31,35,39) -{0xc0, -1, 1, 0, -1, 551911719040, 0, 1, 7, 2}, // (subframe number :7,15,23,31,39) -{0xc0, -1, 1, 0, -1, 586405642240, 0, 1, 7, 2}, // (subframe number :23,27,31,35,39) -{0xc0, -1, 1, 0, -1, 10920, 8, 1, 3, 2}, // (subframe number :3,5,7,9,11,13) -{0xc0, -1, 1, 0, -1, 567489872400, 8, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc0, -1, 1, 0, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc0, -1, 1, 0, -1, 965830828032, 8, 2, 3, 2}, // (subframe number :13,14,15, 29,30,31,37,38,39) -{0xc0, -1, 1, 0, -1, 586406201480, 8, 1, 3, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc0, -1, 1, 0, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc0, -1, 1, 0, -1, 733007751850, 0, 1, 7, 2}, // (subframe number :1,3,5,7,…,37,39) -{0xc0, -1, 1, 0, -1, 1099511627775, 8, 1, 3, 2}, // (subframe number :0,1,2,…,39) -{0xc2, -1, 16, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc2, -1, 16, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc2, -1, 8, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc2, -1, 8, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc2, -1, 8, 1, 2, 550293209600, 0, 2, 2, 6}, // (subframe number :9,19,29,39) -{0xc2, -1, 4, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc2, -1, 4, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc2, -1, 4, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc2, -1, 2, 1, -1, 551911719040, 2, 2, 2, 6}, // (subframe number :7,15,23,31,39) -{0xc2, -1, 2, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc2, -1, 2, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc2, -1, 2, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc2, -1, 1, 0, -1, 549756338176, 2, 1, 2, 6}, // (subframe number :19,39) -{0xc2, -1, 1, 0, -1, 168, 0, 1, 2, 6}, // (subframe number :3,5,7) -{0xc2, -1, 1, 0, -1, 567489331200, 7, 1, 1, 6}, // (subframe number :24,29,34,39) -{0xc2, -1, 1, 0, -1, 550293209600, 7, 2, 1, 6}, // (subframe number :9,19,29,39) -{0xc2, -1, 1, 0, -1, 687195422720, 0, 1, 2, 6}, // (subframe number :17,19,37,39) -{0xc2, -1, 1, 0, -1, 550293209600, 2, 2, 2, 6}, // (subframe number :9,19,29,39) -{0xc2, -1, 1, 0, -1, 551911719040, 2, 1, 2, 6}, // (subframe number :7,15,23,31,39) -{0xc2, -1, 1, 0, -1, 10920, 7, 1, 1, 6}, // (subframe number :3,5,7,9,11,13) -{0xc2, -1, 1, 0, -1, 586405642240, 7, 2, 1, 6}, // (subframe number :23,27,31,35,39) -{0xc2, -1, 1, 0, -1, 586405642240, 0, 1, 2, 6}, // (subframe number :23,27,31,35,39) -{0xc2, -1, 1, 0, -1, 567489872400, 7, 2, 1, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc2, -1, 1, 0, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xc2, -1, 1, 0, -1, 965830828032, 7, 2, 1, 6}, // (subframe number :13,14,15, 29,30,31,37,38,39) -{0xc2, -1, 1, 0, -1, 586406201480, 7, 1, 1, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc2, -1, 1, 0, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xc2, -1, 1, 0, -1, 733007751850, 0, 1, 2, 6}, // (subframe number :1,3,5,7,…,37,39) -{0xc2, -1, 1, 0, -1, 1099511627775, 7, 1, 1, 6}, // (subframe number :0,1,2,…,39) -{0xa1, 0xb1, 16, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, 0xb1, 16, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, 0xb1, 8, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, 0xb1, 8, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, 0xb1, 4, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, 0xb1, 4, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, 0xb1, 2, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, 0xb1, 1, 0, -1, 549756338176, 8, 1, 3, 2}, // (subframe number :19,39) -{0xa1, 0xb1, 1, 0, -1, 550293209600, 8, 1, 3, 2}, // (subframe number :9,19,29,39) -{0xa1, 0xb1, 1, 0, -1, 687195422720, 2, 1, 6, 2}, // (subframe number :17,19,37,39) -{0xa1, 0xb1, 1, 0, -1, 550293209600, 2, 2, 6, 2}, // (subframe number :9,19,29,39) -{0xa1, 0xb1, 1, 0, -1, 586405642240, 8, 1, 3, 2}, // (subframe number :23,27,31,35,39) -{0xa1, 0xb1, 1, 0, -1, 551911719040, 2, 1, 6, 2}, // (subframe number :7,15,23,31,39) -{0xa1, 0xb1, 1, 0, -1, 586405642240, 2, 1, 6, 2}, // (subframe number :23,27,31,35,39) -{0xa1, 0xb1, 1, 0, -1, 567489872400, 8, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, 0xb1, 1, 0, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa1, 0xb1, 1, 0, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa1, 0xb1, 1, 0, -1, 733007751850, 2, 1, 6, 2}, // (subframe number :1,3,5,7,…,37,39) -{0xa2, 0xb2, 16, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, 0xb2, 16, 1, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, 0xb2, 8, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, 0xb2, 8, 1, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, 0xb2, 4, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, 0xb2, 4, 1, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, 0xb2, 2, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, 0xb2, 1, 0, -1, 549756338176, 6, 1, 2, 4}, // (subframe number :19,39) -{0xa2, 0xb2, 1, 0, -1, 550293209600, 6, 1, 2, 4}, // (subframe number :9,19,29,39) -{0xa2, 0xb2, 1, 0, -1, 687195422720, 2, 1, 3, 4}, // (subframe number :17,19,37,39) -{0xa2, 0xb2, 1, 0, -1, 550293209600, 2, 2, 3, 4}, // (subframe number :9,19,29,39) -{0xa2, 0xb2, 1, 0, -1, 586405642240, 6, 1, 2, 4}, // (subframe number :23,27,31,35,39) -{0xa2, 0xb2, 1, 0, -1, 551911719040, 2, 1, 3, 4}, // (subframe number :7,15,23,31,39) -{0xa2, 0xb2, 1, 0, -1, 586405642240, 2, 1, 3, 4}, // (subframe number :23,27,31,35,39) -{0xa2, 0xb2, 1, 0, -1, 567489872400, 6, 1, 2, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, 0xb2, 1, 0, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa2, 0xb2, 1, 0, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa2, 0xb2, 1, 0, -1, 733007751850, 2, 1, 3, 4}, // (subframe number :1,3,5,7,…,37,39) -{0xa3, 0xb3, 16, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, 0xb3, 16, 1, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, 0xb3, 8, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, 0xb3, 8, 1, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, 0xb3, 4, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, 0xb3, 4, 1, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, 0xb3, 2, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, 0xb3, 1, 0, -1, 549756338176, 2, 1, 2, 6}, // (subframe number :19,39) -{0xa3, 0xb3, 1, 0, -1, 550293209600, 2, 1, 2, 6}, // (subframe number :9,19,29,39) -{0xa3, 0xb3, 1, 0, -1, 687195422720, 2, 1, 2, 6}, // (subframe number :17,19,37,39) -{0xa3, 0xb3, 1, 0, -1, 550293209600, 2, 2, 2, 6}, // (subframe number :9,19,29,39) -{0xa3, 0xb3, 1, 0, -1, 551911719040, 2, 1, 2, 6}, // (subframe number :7,15,23,31,39) -{0xa3, 0xb3, 1, 0, -1, 586405642240, 2, 1, 2, 6}, // (subframe number :23,27,31,35,39) -{0xa3, 0xb3, 1, 0, -1, 586405642240, 2, 2, 2, 6}, // (subframe number :23,27,31,35,39) -{0xa3, 0xb3, 1, 0, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, 0xb3, 1, 0, -1, 567489872400, 2, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39) -{0xa3, 0xb3, 1, 0, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39) -{0xa3, 0xb3, 1, 0, -1, 733007751850, 2, 1, 2, 6} // (subframe number :1,3,5,7,…,37,39) -}; diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c index 82ad498c2a..b42f083766 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c @@ -111,7 +111,7 @@ int is_nr_prach_subframe(NR_DL_FRAME_PARMS *frame_parms,uint32_t frame, uint8_t uint8_t prach_ConfigIndex = frame_parms->prach_config_common.prach_ConfigInfo.prach_ConfigIndex; - // For FR1 paired +/* // For FR1 paired if (frame_parms->frame_type == FDD && frame_parms->freq_range == nr_FR1){ if (((frame%table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][2]) == table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][3]) && ((table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][4]&(1< 200) { //FR2 + int y2; + uint8_t slot_60khz; + x = table_6_3_3_2_4_prachConfig_Index[index][2]; + y = table_6_3_3_2_4_prachConfig_Index[index][3]; + y2 = table_6_3_3_2_4_prachConfig_Index[index][4]; + // checking n_sfn mod x = y + if ( (frame%x)==y || (frame%x)==y2 ) { + slot_60khz = slot >> (mu-2); // in table slots are numbered wrt 60kHz + s_map = table_6_3_3_2_4_prachConfig_Index[index][5]; + if ( (s_map>>slot_60khz)&0x01 ) { + if (mu == 3) { + if ( (table_6_3_3_2_4_prachConfig_Index[index][7] == 1) && (slot%2 == 1) ) + return 0; // no prach in odd slots @ 120kHz for 1 prach per 60khz slot + } + *start_symbol = table_6_3_3_2_4_prachConfig_Index[index][6]; + *N_t_slot = table_6_3_3_2_4_prachConfig_Index[index][8]; + *N_dur = table_6_3_3_2_4_prachConfig_Index[index][9]; + if (table_6_3_3_2_4_prachConfig_Index[index][1] != -1) + format2 = (uint8_t) table_6_3_3_2_4_prachConfig_Index[index][1]; + *format = ((uint8_t) table_6_3_3_2_4_prachConfig_Index[index][0]) | (format2<<8); + return 1; + } + else + return 0; // no prach in current slot + } + else + return 0; // no prach in current frame + } + else { + uint8_t subframe; + if (unpaired) { + x = table_6_3_3_2_3_prachConfig_Index[index][2]; + y = table_6_3_3_2_3_prachConfig_Index[index][3]; + if ( (frame%x)==y ) { + subframe = slot >> mu; + s_map = table_6_3_3_2_3_prachConfig_Index[index][4]; + if ( (s_map>>subframe)&0x01 ) { + if (mu == 1) { + if ( (table_6_3_3_2_3_prachConfig_Index[index][6] == 1) && (slot%2 == 1) ) + return 0; // no prach in odd slots @ 30kHz for 1 prach per subframe + } + *start_symbol = table_6_3_3_2_3_prachConfig_Index[index][5]; + *N_t_slot = table_6_3_3_2_3_prachConfig_Index[index][7]; + *N_dur = table_6_3_3_2_3_prachConfig_Index[index][8]; + if (table_6_3_3_2_3_prachConfig_Index[index][1] != -1) + format2 = (uint8_t) table_6_3_3_2_3_prachConfig_Index[index][1]; + *format = ((uint8_t) table_6_3_3_2_3_prachConfig_Index[index][0]) | (format2<<8); + return 1; + } + else + return 0; // no prach in current slot + } + else + return 0; // no prach in current frame + } + else { // FDD + x = table_6_3_3_2_2_prachConfig_Index[index][2]; + y = table_6_3_3_2_2_prachConfig_Index[index][3]; + if ( (frame%x)==y ) { + subframe = slot >> mu; + s_map = table_6_3_3_2_2_prachConfig_Index[index][4]; + if ( (s_map>>subframe)&0x01 ) { + if (mu == 1) { + if ( (table_6_3_3_2_2_prachConfig_Index[index][6] == 1) && (slot%2 == 1) ) + return 0; // no prach in odd slots @ 30kHz for 1 prach per subframe + } + *start_symbol = table_6_3_3_2_2_prachConfig_Index[index][5]; + *N_t_slot = table_6_3_3_2_2_prachConfig_Index[index][7]; + *N_dur = table_6_3_3_2_2_prachConfig_Index[index][8]; + if (table_6_3_3_2_2_prachConfig_Index[index][1] != -1) + format2 = (uint8_t) table_6_3_3_2_2_prachConfig_Index[index][1]; + *format = ((uint8_t) table_6_3_3_2_2_prachConfig_Index[index][0]) | (format2<<8); + return 1; + } + else + return 0; // no prach in current slot + } + else + return 0; // no prach in current frame + } + } +} + + nr_bandentry_t nr_bandtable[] = { {1, 1920000, 1980000, 2110000, 2170000, 20, 422000, 100}, {2, 1850000, 1910000, 1930000, 1990000, 20, 386000, 100}, diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h index 1891bd0ee9..191e0dca18 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h @@ -42,6 +42,16 @@ uint32_t to_nrarfcn(int nr_bandP, uint64_t dl_CarrierFreq, uint8_t scs_index, ui int16_t fill_dmrs_mask(NR_PDSCH_Config_t *pdsch_Config,int dmrs_TypeA_Position,int NrOfSymbols); +int get_nr_prach_info_from_index(uint8_t index, + int frame, + int slot, + uint64_t frequency, + uint8_t mu, + uint16_t *format, + uint8_t *start_symbol, + uint8_t *N_t_slot, + uint8_t *N_dur); + typedef enum { NR_DL_DCI_FORMAT_1_0 = 0, NR_DL_DCI_FORMAT_1_1, From eda3a76e13c7fd05bf360b57811aca6fae4c34ce Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Thu, 13 Feb 2020 09:12:02 +0100 Subject: [PATCH 035/553] fix in function to read prach tables --- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 26 +++++++------------ openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h | 3 ++- 2 files changed, 12 insertions(+), 17 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index d15b9cdaa1..97d647eed3 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -820,25 +820,19 @@ int64_t table_6_3_3_2_4_prachConfig_Index [256][10] = { int get_nr_prach_info_from_index(uint8_t index, int frame, int slot, - uint64_t frequency, + uint32_t pointa, uint8_t mu, + uint8_t unpaired, uint16_t *format, uint8_t *start_symbol, uint8_t *N_t_slot, uint8_t *N_dur) { - uint16_t band = 0; - int32_t offset = 0; - lte_frame_type_t unpaired = 0; + int x,y; int64_t s_map; uint8_t format2 = 0xff; - get_band(frequency, - &band, - &offset, - &unpaired); - - if (band > 200) { //FR2 + if (pointa > 2016666) { //FR2 int y2; uint8_t slot_60khz; x = table_6_3_3_2_4_prachConfig_Index[index][2]; @@ -850,8 +844,8 @@ int get_nr_prach_info_from_index(uint8_t index, s_map = table_6_3_3_2_4_prachConfig_Index[index][5]; if ( (s_map>>slot_60khz)&0x01 ) { if (mu == 3) { - if ( (table_6_3_3_2_4_prachConfig_Index[index][7] == 1) && (slot%2 == 1) ) - return 0; // no prach in odd slots @ 120kHz for 1 prach per 60khz slot + if ( (table_6_3_3_2_4_prachConfig_Index[index][7] == 1) && (slot%2 == 0) ) + return 0; // no prach in even slots @ 120kHz for 1 prach per 60khz slot } *start_symbol = table_6_3_3_2_4_prachConfig_Index[index][6]; *N_t_slot = table_6_3_3_2_4_prachConfig_Index[index][8]; @@ -877,8 +871,8 @@ int get_nr_prach_info_from_index(uint8_t index, s_map = table_6_3_3_2_3_prachConfig_Index[index][4]; if ( (s_map>>subframe)&0x01 ) { if (mu == 1) { - if ( (table_6_3_3_2_3_prachConfig_Index[index][6] == 1) && (slot%2 == 1) ) - return 0; // no prach in odd slots @ 30kHz for 1 prach per subframe + if ( (table_6_3_3_2_3_prachConfig_Index[index][6] == 1) && (slot%2 == 0) ) + return 0; // no prach in even slots @ 30kHz for 1 prach per subframe } *start_symbol = table_6_3_3_2_3_prachConfig_Index[index][5]; *N_t_slot = table_6_3_3_2_3_prachConfig_Index[index][7]; @@ -902,8 +896,8 @@ int get_nr_prach_info_from_index(uint8_t index, s_map = table_6_3_3_2_2_prachConfig_Index[index][4]; if ( (s_map>>subframe)&0x01 ) { if (mu == 1) { - if ( (table_6_3_3_2_2_prachConfig_Index[index][6] == 1) && (slot%2 == 1) ) - return 0; // no prach in odd slots @ 30kHz for 1 prach per subframe + if ( (table_6_3_3_2_2_prachConfig_Index[index][6] == 1) && (slot%2 == 0) ) + return 0; // no prach in even slots @ 30kHz for 1 prach per subframe } *start_symbol = table_6_3_3_2_2_prachConfig_Index[index][5]; *N_t_slot = table_6_3_3_2_2_prachConfig_Index[index][7]; diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h index 191e0dca18..8bff2cedc8 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h @@ -45,8 +45,9 @@ int16_t fill_dmrs_mask(NR_PDSCH_Config_t *pdsch_Config,int dmrs_TypeA_Position,i int get_nr_prach_info_from_index(uint8_t index, int frame, int slot, - uint64_t frequency, + uint32_t pointa, uint8_t mu, + uint8_t unpaired, uint16_t *format, uint8_t *start_symbol, uint8_t *N_t_slot, From a7ab50e8746d8c22250bc631a8303de23ea7a5a0 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Thu, 13 Feb 2020 13:50:44 +0100 Subject: [PATCH 036/553] scheduling PRACH and filling fapi PRACH PDU --- .../nfapi/public_inc/nfapi_nr_interface_scf.h | 4 +- openair1/PHY/NR_TRANSPORT/nr_prach.h | 12 -- openair1/PHY/NR_TRANSPORT/nr_prach_common.c | 8 +- openair1/SCHED_NR/phy_procedures_nr_gNB.c | 48 ++++--- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 46 +++++++ openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h | 2 + openair2/LAYER2/NR_MAC_gNB/config.c | 12 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 123 ++++++++++++++++-- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 10 +- openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 1 + 10 files changed, 214 insertions(+), 52 deletions(-) diff --git a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h index 8233be587c..ce8e83185e 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h @@ -1028,10 +1028,12 @@ typedef struct { uint16_t phys_cell_id; uint8_t num_prach_ocas; + // SCF PRACH PDU format field does not consider A1/B1 etc. possibilities + // We added 9 = A1/B1 10 = A2/B2 11 A3/B3 uint8_t prach_format; uint8_t num_ra; uint8_t prach_start_symbol; - uint16_t num_cs;// + uint16_t num_cs; nfapi_nr_ul_beamforming_t beamforming; } nfapi_nr_prach_pdu_t; diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.h b/openair1/PHY/NR_TRANSPORT/nr_prach.h index 5a8ed9116e..d158e04c79 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.h +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.h @@ -37,18 +37,6 @@ uint16_t nr_du[838]; /************************************* * The following tables defined for NR **************************************/ -// Table 6.3.3.1-5 (38.211) NCS for preamble formats with delta_f_RA = 1.25 KHz -uint16_t NCS_unrestricted_delta_f_RA_125[16] = {0,13,15,18,22,26,32,38,46,59,76,93,119,167,279,419}; -uint16_t NCS_restricted_TypeA_delta_f_RA_125[15] = {15,18,22,26,32,38,46,55,68,82,100,128,158,202,237}; // high-speed case set Type A -uint16_t NCS_restricted_TypeB_delta_f_RA_125[13] = {15,18,22,26,32,38,46,55,68,82,100,118,137}; // high-speed case set Type B - -// Table 6.3.3.1-6 (38.211) NCS for preamble formats with delta_f_RA = 5 KHz -uint16_t NCS_unrestricted_delta_f_RA_5[16] = {0,13,26,33,38,41,49,55,64,76,93,119,139,209,279,419}; -uint16_t NCS_restricted_TypeA_delta_f_RA_5[16] = {36,57,72,81,89,94,103,112,121,132,137,152,173,195,216,237}; // high-speed case set Type A -uint16_t NCS_restricted_TypeB_delta_f_RA_5[14] = {36,57,60,63,65,68,71,77,81,85,97,109,122,137}; // high-speed case set Type B - -// Table 6.3.3.1-7 (38.211) NCS for preamble formats with delta_f_RA = 15 * 2mu KHz where mu = {0,1,2,3} -uint16_t NCS_unrestricted_delta_f_RA_15[16] = {0,2,4,6,8,10,12,13,15,17,19,23,27,34,46,69}; //Table 6.3.3.1-3: Mapping from logical index i to sequence number u for preamble formats with L_RA = 839 uint16_t prach_root_sequence_map_0_3[838] = { diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c index b42f083766..67534ccce7 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c @@ -218,9 +218,9 @@ void compute_nr_prach_seq(uint16_t rootSequenceIndex, AssertFatal(zeroCorrelationZoneConfig<=15, "FATAL, Illegal Ncs_config for unrestricted format %"PRIu8"\n", zeroCorrelationZoneConfig ); - if (prach_fmt<3) NCS = NCS_unrestricted_delta_f_RA_125[zeroCorrelationZoneConfig]; + /* if (prach_fmt<3) NCS = NCS_unrestricted_delta_f_RA_125[zeroCorrelationZoneConfig]; if (prach_fmt==3) NCS = NCS_unrestricted_delta_f_RA_5[zeroCorrelationZoneConfig]; - if (prach_fmt>3) NCS = NCS_unrestricted_delta_f_RA_15[zeroCorrelationZoneConfig]; + if (prach_fmt>3) NCS = NCS_unrestricted_delta_f_RA_15[zeroCorrelationZoneConfig];*/ num_preambles = (NCS==0) ? 64 : ((64*NCS)/N_ZC); @@ -235,7 +235,7 @@ void compute_nr_prach_seq(uint16_t rootSequenceIndex, AssertFatal(zeroCorrelationZoneConfig<=14, "FATAL, Illegal Ncs_config for restricted format %"PRIu8"\n", zeroCorrelationZoneConfig ); - if (prach_fmt<3){ + /* if (prach_fmt<3){ if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_125[zeroCorrelationZoneConfig]; // for TypeA, this is hardcoded. FIXME if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_125[zeroCorrelationZoneConfig]; // for TypeB, this is hardcoded. FIXME } @@ -245,7 +245,7 @@ void compute_nr_prach_seq(uint16_t rootSequenceIndex, } if (prach_fmt>3){ - } + }*/ nr_fill_du(prach_fmt); diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index 60609bae3f..5cbe2816fd 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -391,34 +391,40 @@ void phy_procedures_gNB_common_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) { nfapi_nr_ul_tti_request_t *UL_tti_req = &gNB->UL_tti_req; - int num_pusch_pdu = UL_tti_req->n_pdus; + int num_pdus = UL_tti_req->n_pdus; - LOG_D(PHY,"phy_procedures_gNB_uespec_RX frame %d, slot %d, num_pusch_pdu %d\n",frame_rx,slot_rx,num_pusch_pdu); + LOG_D(PHY,"phy_procedures_gNB_uespec_RX frame %d, slot %d, num_pdus %d\n",frame_rx,slot_rx,num_pdus); gNB->UL_INFO.rx_ind.rx_indication_body.number_of_pdus = 0; - for (int i = 0; i < num_pusch_pdu; i++) { + for (int i = 0; i < num_pdus; i++) { switch (UL_tti_req->pdus_list[i].pdu_type) { - case NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE:{ - LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE\n",frame_rx,slot_rx); + case NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE: + LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE\n",frame_rx,slot_rx); - nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[0].pusch_pdu; - nr_fill_ulsch(gNB,frame_rx,slot_rx,pusch_pdu); + nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[0].pusch_pdu; + nr_fill_ulsch(gNB,frame_rx,slot_rx,pusch_pdu); + + uint8_t ULSCH_id = find_nr_ulsch(pusch_pdu->rnti,gNB,SEARCH_EXIST); + uint8_t harq_pid = pusch_pdu->pusch_data.harq_process_id; + uint8_t symbol_start = pusch_pdu->start_symbol_index; + uint8_t symbol_end = symbol_start + pusch_pdu->nr_of_symbols; - uint8_t ULSCH_id = find_nr_ulsch(pusch_pdu->rnti,gNB,SEARCH_EXIST); - uint8_t harq_pid = pusch_pdu->pusch_data.harq_process_id; - uint8_t symbol_start = pusch_pdu->start_symbol_index; - uint8_t symbol_end = symbol_start + pusch_pdu->nr_of_symbols; - - for(uint8_t symbol = symbol_start; symbol < symbol_end; symbol++) { - nr_rx_pusch(gNB, ULSCH_id, frame_rx, slot_rx, symbol, harq_pid); - } - //LOG_M("rxdataF_comp.m","rxF_comp",gNB->pusch_vars[0]->rxdataF_comp[0],6900,1,1); - //LOG_M("rxdataF_ext.m","rxF_ext",gNB->pusch_vars[0]->rxdataF_ext[0],6900,1,1); - nr_ulsch_procedures(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); - nr_fill_rx_indication(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); // indicate SDU to MAC - nr_fill_crc_indication(gNB, frame_rx, slot_rx, ULSCH_id, 0); - } + for(uint8_t symbol = symbol_start; symbol < symbol_end; symbol++) { + nr_rx_pusch(gNB, ULSCH_id, frame_rx, slot_rx, symbol, harq_pid); + } + //LOG_M("rxdataF_comp.m","rxF_comp",gNB->pusch_vars[0]->rxdataF_comp[0],6900,1,1); + //LOG_M("rxdataF_ext.m","rxF_ext",gNB->pusch_vars[0]->rxdataF_ext[0],6900,1,1); + nr_ulsch_procedures(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); + nr_fill_rx_indication(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); // indicate SDU to MAC + nr_fill_crc_indication(gNB, frame_rx, slot_rx, ULSCH_id, 0); + break; + case NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE: + LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE\n",frame_rx,slot_rx); + break; + case NFAPI_NR_UL_CONFIG_PRACH_PDU_TYPE: + LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PRACH_PDU_TYPE\n",frame_rx,slot_rx); + break; } } } diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index 97d647eed3..8c6e5f1d56 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -32,6 +32,52 @@ #include "LAYER2/NR_MAC_gNB/mac_proto.h" +// Table 6.3.3.1-5 (38.211) NCS for preamble formats with delta_f_RA = 1.25 KHz +uint16_t NCS_unrestricted_delta_f_RA_125[16] = {0,13,15,18,22,26,32,38,46,59,76,93,119,167,279,419}; +uint16_t NCS_restricted_TypeA_delta_f_RA_125[15] = {15,18,22,26,32,38,46,55,68,82,100,128,158,202,237}; // high-speed case set Type A +uint16_t NCS_restricted_TypeB_delta_f_RA_125[13] = {15,18,22,26,32,38,46,55,68,82,100,118,137}; // high-speed case set Type B + +// Table 6.3.3.1-6 (38.211) NCS for preamble formats with delta_f_RA = 5 KHz +uint16_t NCS_unrestricted_delta_f_RA_5[16] = {0,13,26,33,38,41,49,55,64,76,93,119,139,209,279,419}; +uint16_t NCS_restricted_TypeA_delta_f_RA_5[16] = {36,57,72,81,89,94,103,112,121,132,137,152,173,195,216,237}; // high-speed case set Type A +uint16_t NCS_restricted_TypeB_delta_f_RA_5[14] = {36,57,60,63,65,68,71,77,81,85,97,109,122,137}; // high-speed case set Type B + +// Table 6.3.3.1-7 (38.211) NCS for preamble formats with delta_f_RA = 15 * 2mu KHz where mu = {0,1,2,3} +uint16_t NCS_unrestricted_delta_f_RA_15[16] = {0,2,4,6,8,10,12,13,15,17,19,23,27,34,46,69}; + +uint16_t get_NCS(uint8_t index, uint16_t format0, uint8_t restricted_set_config) { + + if (format0 < 3) { + switch(restricted_set_config){ + case 0: + return(NCS_unrestricted_delta_f_RA_125[index]); + case 1: + return(NCS_restricted_TypeA_delta_f_RA_125[index]); + case 2: + return(NCS_restricted_TypeB_delta_f_RA_125[index]); + default: + AssertFatal(1==0,"Invalid restricted set config value %d",restricted_set_config); + } + } + else { + if (format0 == 3) { + switch(restricted_set_config){ + case 0: + return(NCS_unrestricted_delta_f_RA_5[index]); + case 1: + return(NCS_restricted_TypeA_delta_f_RA_5[index]); + case 2: + return(NCS_restricted_TypeB_delta_f_RA_5[index]); + default: + AssertFatal(1==0,"Invalid restricted set config value %d",restricted_set_config); + } + } + else + return(NCS_unrestricted_delta_f_RA_15[index]); + } +} + + // Table 6.3.3.2-2: Random access configurations for FR1 and paired spectrum/supplementary uplink // the column 5, (SFN_nbr is a bitmap where we set bit to '1' in the position of the subframe where the RACH can be sent. // E.g. in row 4, and column 5 we have set value 512 ('1000000000') which means RACH can be sent at subframe 9. diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h index 8bff2cedc8..eb9771d943 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h @@ -53,6 +53,8 @@ int get_nr_prach_info_from_index(uint8_t index, uint8_t *N_t_slot, uint8_t *N_dur); +uint16_t get_NCS(uint8_t index, uint16_t format, uint8_t restricted_set_config); + typedef enum { NR_DL_DCI_FORMAT_1_0 = 0, NR_DL_DCI_FORMAT_1_1, diff --git a/openair2/LAYER2/NR_MAC_gNB/config.c b/openair2/LAYER2/NR_MAC_gNB/config.c index 6f9f04c108..0e3dccbe52 100644 --- a/openair2/LAYER2/NR_MAC_gNB/config.c +++ b/openair2/LAYER2/NR_MAC_gNB/config.c @@ -122,13 +122,23 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm } } + lte_frame_type_t frame_type; + uint16_t band; + int32_t offset; + + get_band((cfg->carrier_config.dl_frequency.value)*1000, + &band, + &offset, + &frame_type); + + RC.nrmac[Mod_idP]->common_channels[0].frame_type = frame_type; // Cell configuration cfg->cell_config.phy_cell_id.value = *scc->physCellId; cfg->cell_config.phy_cell_id.tl.tag = NFAPI_NR_CONFIG_PHY_CELL_ID_TAG; cfg->num_tlv++; - cfg->cell_config.frame_duplex_type.value = 1; + cfg->cell_config.frame_duplex_type.value = frame_type; cfg->cell_config.frame_duplex_type.tl.tag = NFAPI_NR_CONFIG_FRAME_DUPLEX_TYPE_TAG; cfg->num_tlv++; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index a1119e6c10..eba50ef421 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -263,18 +263,122 @@ void schedule_nr_SRS(module_id_t module_idP, frame_t frameP, sub_frame_t subfram } */ -/* -void schedule_nr_prach(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP) { + +void schedule_nr_prach(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) { gNB_MAC_INST *gNB = RC.nrmac[module_idP]; + NR_COMMON_channels_t *cc = gNB->common_channels; + NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; + nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[module_idP]->UL_tti_req[0]; - // schedule PRACH for iniital BWP + uint8_t config_index = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.prach_ConfigurationIndex; + uint8_t mu,N_dur,N_t_slot,start_symbol; + uint16_t format; - if (is_initialBWP_prach_subframe(frameP,subframeP)<0) return; - - // fill FAPI + if (scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing) + mu = *scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing; + else + mu = scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing; + + // prach is scheduled according to configuration index and tables 6.3.3.2.2 to 6.3.3.2.4 + if ( get_nr_prach_info_from_index(config_index, + (int)frameP, + (int)slotP, + scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA, + mu, + cc->frame_type, + &format, + &start_symbol, + &N_t_slot, + &N_dur) ) { + + int fdm = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FDM; + uint16_t format0 = format&0xff; // first column of format from table + uint16_t format1 = (format>>8)&0xff; // second column of format from table + + UL_tti_req->SFN = frameP; + UL_tti_req->Slot = slotP; + for (int n=0; n<(1<pdus_list[UL_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PRACH_PDU_TYPE; + UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_size = sizeof(nfapi_nr_prach_pdu_t); + nfapi_nr_prach_pdu_t *prach_pdu = &UL_tti_req->pdus_list[UL_tti_req->n_pdus].prach_pdu; + memset(prach_pdu,0,sizeof(nfapi_nr_prach_pdu_t)); + UL_tti_req->n_pdus+=1; + + // filling the prach fapi structure + prach_pdu->phys_cell_id = *scc->physCellId; + prach_pdu->num_prach_ocas = N_t_slot; + prach_pdu->prach_start_symbol = start_symbol; + prach_pdu->num_ra = n; + prach_pdu->num_cs = get_NCS(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.zeroCorrelationZoneConfig, + format0, + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig); + // SCF PRACH PDU format field does not consider A1/B1 etc. possibilities + // We added 9 = A1/B1 10 = A2/B2 11 A3/B3 + if (format1!=0xff) { + switch(format0) { + case 0xa1: + prach_pdu->prach_format = 9; + break; + case 0xa2: + prach_pdu->prach_format = 10; + break; + case 0xa3: + prach_pdu->prach_format = 10; + break; + default: + AssertFatal(1==0,"Only formats A1/B1 A2/B2 A3/B3 are valid for dual format"); + } + } + else{ + switch(format0) { + case 0xa1: + prach_pdu->prach_format = 0; + break; + case 0xa2: + prach_pdu->prach_format = 1; + break; + case 0xa3: + prach_pdu->prach_format = 2; + break; + case 0xb1: + prach_pdu->prach_format = 3; + break; + case 0xb2: + prach_pdu->prach_format = 4; + break; + case 0xb3: + prach_pdu->prach_format = 5; + break; + case 0xb4: + prach_pdu->prach_format = 6; + break; + case 0xc0: + prach_pdu->prach_format = 7; + break; + case 0xc2: + prach_pdu->prach_format = 8; + break; + case 0: + // long formats are handled @ PHY + break; + case 1: + // long formats are handled @ PHY + break; + case 2: + // long formats are handled @ PHY + break; + case 3: + // long formats are handled @ PHY + break; + default: + AssertFatal(1==0,"Invalid PRACH format"); + } + } + } + } } -*/ + /* void copy_nr_ulreq(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) @@ -382,7 +486,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, // Phytest scheduling if (phy_test && slot_txP==1){ nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP,NULL); - nr_schedule_RA(module_idP, frame_txP, slot_txP); + //nr_schedule_RA(module_idP, frame_txP, slot_txP); // resetting ta flag gNB->ta_len = 0; } @@ -396,6 +500,9 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, } //is_nr_DL_slot if (is_nr_UL_slot(cc->ServingCellConfigCommon,slot_rxP)) { + + schedule_nr_prach(module_idP, frame_rxP, slot_rxP); + if (phy_test && slot_rxP==8){ nr_schedule_uss_ulsch_phytest(module_idP, frame_rxP, slot_rxP); } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 9b8f329400..9345705f3f 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -716,11 +716,11 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, UL_tti_req->SFN = frameP; UL_tti_req->Slot = slotP; - UL_tti_req->n_pdus = 1; - UL_tti_req->pdus_list[0].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE; - UL_tti_req->pdus_list[0].pdu_size = sizeof(nfapi_nr_pusch_pdu_t); - nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[0].pusch_pdu; + UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE; + UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_size = sizeof(nfapi_nr_pusch_pdu_t); + nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[UL_tti_req->n_pdus].pusch_pdu; memset(pusch_pdu,0,sizeof(nfapi_nr_pusch_pdu_t)); + UL_tti_req->n_pdus+=1; LOG_D(MAC, "Scheduling UE specific PUSCH\n"); //UL_tti_req = &nr_mac->UL_tti_req[CC_id]; @@ -832,4 +832,4 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types); -} \ No newline at end of file +} diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index 524b4d67c5..cdb11a7aa3 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -141,6 +141,7 @@ typedef struct { int p_gNB; int Ncp; int nr_band; + lte_frame_type_t frame_type; uint64_t dl_CarrierFreq; NR_BCCH_BCH_Message_t *mib; NR_ServingCellConfigCommon_t *ServingCellConfigCommon; From e8834e9620d255f9ebcfd0e7485d413f0e47d7d7 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Fri, 14 Feb 2020 05:44:12 +0100 Subject: [PATCH 037/553] added FAPI interfaces int gNB prach receiver functions (rx_nr_prach,rx_nr_prach_ru) and in indication to MAC. --- executables/nr-gnb.c | 6 +- .../nfapi/public_inc/nfapi_nr_interface_scf.h | 2 +- openair1/PHY/NR_TRANSPORT/nr_prach.c | 494 +++++++++--------- openair1/PHY/NR_TRANSPORT/nr_transport.h | 2 + .../PHY/NR_TRANSPORT/nr_transport_proto.h | 1 + openair1/PHY/defs_RU.h | 4 +- openair1/PHY/defs_gNB.h | 7 +- openair1/SCHED_NR/nr_prach_procedures.c | 71 ++- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 15 +- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 6 +- openair2/NR_PHY_INTERFACE/NR_IF_Module.c | 29 +- openair2/NR_PHY_INTERFACE/NR_IF_Module.h | 5 +- 12 files changed, 322 insertions(+), 320 deletions(-) diff --git a/executables/nr-gnb.c b/executables/nr-gnb.c index dedee9b651..7f85cabeb7 100644 --- a/executables/nr-gnb.c +++ b/executables/nr-gnb.c @@ -165,14 +165,14 @@ static inline int rxtx(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int frame_t if (gNB->UL_INFO.rx_ind.rx_indication_body.number_of_pdus|| gNB->UL_INFO.harq_ind.harq_indication_body.number_of_harqs || gNB->UL_INFO.crc_ind.crc_indication_body.number_of_crcs || - gNB->UL_INFO.rach_ind.rach_indication_body.number_of_preambles || + gNB->UL_INFO.rach_ind.number_of_pdus || gNB->UL_INFO.cqi_ind.number_of_cqis ) { - LOG_D(PHY, "UL_info[rx_ind:%05d:%d harqs:%05d:%d crcs:%05d:%d preambles:%05d:%d cqis:%d] RX:%04d%d TX:%04d%d \n", + LOG_D(PHY, "UL_info[rx_ind:%05d:%d harqs:%05d:%d crcs:%05d:%d rach_pdus:%0d.%d:%d cqis:%d] RX:%04d%d TX:%04d%d \n", NFAPI_SFNSF2DEC(gNB->UL_INFO.rx_ind.sfn_sf), gNB->UL_INFO.rx_ind.rx_indication_body.number_of_pdus, NFAPI_SFNSF2DEC(gNB->UL_INFO.harq_ind.sfn_sf), gNB->UL_INFO.harq_ind.harq_indication_body.number_of_harqs, NFAPI_SFNSF2DEC(gNB->UL_INFO.crc_ind.sfn_sf), gNB->UL_INFO.crc_ind.crc_indication_body.number_of_crcs, - NFAPI_SFNSF2DEC(gNB->UL_INFO.rach_ind.sfn_sf), gNB->UL_INFO.rach_ind.rach_indication_body.number_of_preambles, + gNB->UL_INFO.rach_ind.sfn, gNB->UL_INFO.rach_ind.slot,gNB->UL_INFO.rach_ind.number_of_pdus, gNB->UL_INFO.cqi_ind.number_of_cqis, frame_rx, slot_rx, frame_tx, slot_tx); diff --git a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h index 8233be587c..3be4f03dde 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h @@ -85,7 +85,7 @@ typedef enum { NFAPI_NR_PHY_MSG_TYPE_CRC_INDICATION= 0X86, NFAPI_NR_PHY_MSG_TYPE_UCI_INDICATION= 0X87, NFAPI_NR_PHY_MSG_TYPE_SRS_INDICATION= 0X88, - NFAPI_NR_PHY_MSG_TYPE_PACH_INDICATION= 0X89 + NFAPI_NR_PHY_MSG_TYPE_RACH_INDICATION= 0X89 //RESERVED 0X8a ~ 0xff } nfapi_nr_phy_msg_type_e; diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index 8bcd3f2662..77a1ac5229 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -50,22 +50,28 @@ extern uint16_t nr_du[838]; extern int16_t nr_ru[2*839]; void rx_nr_prach_ru(RU_t *ru, + nfapi_nr_prach_pdu_t *prach_pdu, int frame, - int subframe) { + int slot) { AssertFatal(ru!=NULL,"ru is null\n"); int16_t **rxsigF=NULL; - NR_DL_FRAME_PARMS *fp=ru->nr_frame_parms; - int16_t prach_ConfigIndex = fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex; + NR_DL_FRAME_PARMS *fp=&ru->frame_parms; + + int frame_type = ru->config.cell_config.frame_duplex_type.value; + int16_t *prach[ru->nb_rx]; - uint8_t prach_fmt = get_nr_prach_fmt(prach_ConfigIndex,fp->frame_type,fp->freq_range); + uint8_t prach_fmt = prach_pdu->prach_format; + int prach_sequence_length = ru->config.prach_config.prach_sequence_length.value; + + int msg1_frequencystart = ru->config.prach_config.num_prach_fd_occasions_list[0].k1.value; rxsigF = ru->prach_rxsigF; AssertFatal(ru->if_south == LOCAL_RF,"we shouldn't call this if if_south != LOCAL_RF\n"); for (int aa=0; aanb_rx; aa++) - prach[aa] = (int16_t*)&ru->common.rxdata[aa][(subframe*fp->samples_per_slot<<1)-ru->N_TA_offset]; + prach[aa] = (int16_t*)&ru->common.rxdata[aa][(slot*fp->samples_per_slot)-ru->N_TA_offset]; @@ -73,84 +79,88 @@ void rx_nr_prach_ru(RU_t *ru, int Ncp; int16_t *prach2; - - switch (prach_fmt) { - case 0: - Ncp = 3168; - break; - - case 1: - Ncp = 21024; - break; - - case 2: - Ncp = 4688; - break; - - case 3: - Ncp = 3168; - break; - - case 0xa1: - Ncp = 288/(1<N_RB_UL, ru->nb_rx, Ncp); + LOG_D(PHY,"rx_prach: Doing PRACH FFT for nb_rx:%d Ncp:%d\n",ru->nb_rx, Ncp); } AssertFatal(mu==1,"only 30 kHz SCS handled for now\n"); // Note: Assumes PUSCH SCS @ 30 kHz, take values for formats 0-2 and adjust for others below int kbar = 1; int K = 24; - if (prach_fmt == 3) { + if (prach_sequence_length == 0 && prach_fmt == 3) { K=4; kbar=10; } - else if (prach_fmt > 3) { + else if (prach_sequence_length == 1) { // Note: Assumes that PRACH SCS is same as PUSCH SCS K=1; kbar=2; } - int n_ra_prb = fp->prach_config_common.prach_ConfigInfo.msg1_frequencystart; + int n_ra_prb = msg1_frequencystart; int k = (12*n_ra_prb) - 6*fp->N_RB_UL; int N_ZC = (prach_fmt<4)?839:139; @@ -174,169 +184,178 @@ void rx_nr_prach_ru(RU_t *ru, //40 MHz @ 61.44 Ms/s //50 MHz @ 61.44 Ms/s prach2 = prach[aa] + (Ncp<<2); - if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) - dft49152(prach2,rxsigF[aa],1); - if (prach_fmt == 1 || prach_fmt == 2) { - dft49152(prach2+98304,rxsigF[aa]+98304,1); - reps++; + if (prach_sequence_length == 0) { + if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) + dft49152(prach2,rxsigF[aa],1); + if (prach_fmt == 1 || prach_fmt == 2) { + dft49152(prach2+98304,rxsigF[aa]+98304,1); + reps++; + } + if (prach_fmt == 2) { + dft49152(prach2+(98304*2),rxsigF[aa]+(98304*2),1); + dft49152(prach2+(98304*3),rxsigF[aa]+(98304*3),1); + reps+=2; + } + if (prach_fmt == 3) { + for (int i=0;i<4;i++) dft12288(prach2+(i*12288*2),rxsigF[aa]+(i*12288*2),1); + reps=4; + } } - if (prach_fmt == 2) { - dft49152(prach2+(98304*2),rxsigF[aa]+(98304*2),1); - dft49152(prach2+(98304*3),rxsigF[aa]+(98304*3),1); - reps+=2; - } - if (prach_fmt == 3) { - for (int i=0;i<4;i++) dft12288(prach2+(i*12288*2),rxsigF[aa]+(i*12288*2),1); - reps=4; - } - if (prach_fmt >3) { + else { dft2048(prach2,rxsigF[aa],1); - if (prach_fmt != 0xc0) { + if (prach_fmt != 7) { // !=C0 dft2048(prach2+4096,rxsigF[aa]+4096,1); reps++; } - } - if (prach_fmt == 0xa2 || prach_fmt == 0xa3 || prach_fmt == 0xb2 || prach_fmt == 0xb3 || prach_fmt == 0xb4 || prach_fmt == 0xc2) { + if (prach_fmt == 1 || prach_fmt == 2 || prach_fmt == 4 || prach_fmt == 5 || prach_fmt == 6 || prach_fmt == 8) { dft2048(prach2+4096*2,rxsigF[aa]+4096*2,1); dft2048(prach2+4096*3,rxsigF[aa]+4096*3,1); reps+=2; - } - if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xB4) { - dft2048(prach2+4096*4,rxsigF[aa]+4096*4,1); - dft2048(prach2+4096*5,rxsigF[aa]+4096*5,1); - reps+=2; - } - if (prach_fmt == 0xB4) { - for (int i=6;i<11;i++) dft2048(prach2+(4096*i),rxsigF[aa]+(4096*i),1); + } + if (prach_fmt == 2 || prach_fmt == 5 || prach_fmt == 6) { + dft2048(prach2+4096*4,rxsigF[aa]+4096*4,1); + dft2048(prach2+4096*5,rxsigF[aa]+4096*5,1); + reps+=2; + } + if (prach_fmt == 6) { + for (int i=6;i<11;i++) dft2048(prach2+(4096*i),rxsigF[aa]+(4096*i),1); reps+=6; + } } } else { // 40 MHz @ 46.08 Ms/s - prach2 = prach[aa] + (3*Ncp); - AssertFatal(fp->N_RB_UL <= 107,"cannot do 108..136 PRBs with 3/4 sampling\n"); - if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) { - dft36864(prach2,rxsigF[aa],1); - reps++; - } - if (prach_fmt == 1 || prach_fmt == 2) { - dft36864(prach2+73728,rxsigF[aa]+73728,1); - reps++; - } - if (prach_fmt == 2) { - dft36864(prach2+(73728*2),rxsigF[aa]+(73728*2),1); - dft36864(prach2+(73728*3),rxsigF[aa]+(73728*3),1); - reps+=2; - } - if (prach_fmt == 3) { - for (int i=0;i<4;i++) dft9216(prach2+(i*9216*2),rxsigF[aa]+(i*9216*2),1); - reps=4; - } - if (prach_fmt >3) { + if (prach_sequence_length == 0) { + prach2 = prach[aa] + (3*Ncp); + AssertFatal(fp->N_RB_UL <= 107,"cannot do 108..136 PRBs with 3/4 sampling\n"); + if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) { + dft36864(prach2,rxsigF[aa],1); + reps++; + } + if (prach_fmt == 1 || prach_fmt == 2) { + dft36864(prach2+73728,rxsigF[aa]+73728,1); + reps++; + } + if (prach_fmt == 2) { + dft36864(prach2+(73728*2),rxsigF[aa]+(73728*2),1); + dft36864(prach2+(73728*3),rxsigF[aa]+(73728*3),1); + reps+=2; + } + if (prach_fmt == 3) { + for (int i=0;i<4;i++) dft9216(prach2+(i*9216*2),rxsigF[aa]+(i*9216*2),1); + reps=4; + } + } else { dft1536(prach2,rxsigF[aa],1); if (prach_fmt != 0xc0) { dft1536(prach2+3072,rxsigF[aa]+3072,1); reps++; } - } - if (prach_fmt == 0xa2 || prach_fmt == 0xa3 || prach_fmt == 0xb2 || prach_fmt == 0xb3 || prach_fmt == 0xb4 || prach_fmt == 0xc2) { - dft1536(prach2+3072*2,rxsigF[aa]+3072*2,1); - dft1536(prach2+3072*3,rxsigF[aa]+3072*3,1); - reps+=2; - } - if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xB4) { - dft1536(prach2+3072*4,rxsigF[aa]+3072*4,1); - dft1536(prach2+3072*5,rxsigF[aa]+3072*5,1); - reps+=2; - } - if (prach_fmt == 0xB4) { - for (int i=6;i<11;i++) dft1536(prach2+(3072*i),rxsigF[aa]+(3072*i),1); - reps+=6; - } - } - } + + if (prach_fmt == 0xa2 || prach_fmt == 0xa3 || prach_fmt == 0xb2 || prach_fmt == 0xb3 || prach_fmt == 0xb4 || prach_fmt == 0xc2) { + dft1536(prach2+3072*2,rxsigF[aa]+3072*2,1); + dft1536(prach2+3072*3,rxsigF[aa]+3072*3,1); + reps+=2; + } + if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xB4) { + dft1536(prach2+3072*4,rxsigF[aa]+3072*4,1); + dft1536(prach2+3072*5,rxsigF[aa]+3072*5,1); + reps+=2; + } + if (prach_fmt == 0xB4) { + for (int i=6;i<11;i++) dft1536(prach2+(3072*i),rxsigF[aa]+(3072*i),1); + reps+=6; + } + } // short format + } // 3/4 sampling + } // <=50 MHz BW else if (fp->N_RB_UL <= 273) { if (fp->threequarter_fs==0) { prach2 = prach[aa] + (Ncp<<3); dftlen=98304; //80,90,100 MHz @ 122.88 Ms/s - if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) - dft98304(prach2,rxsigF[aa],1); - if (prach_fmt == 1 || prach_fmt == 2) { - dft98304(prach2+196608,rxsigF[aa]+196608,1); - reps++; + + if (prach_sequence_length == 0) { + if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) + dft98304(prach2,rxsigF[aa],1); + if (prach_fmt == 1 || prach_fmt == 2) { + dft98304(prach2+196608,rxsigF[aa]+196608,1); + reps++; + } + if (prach_fmt == 2) { + dft98304(prach2+196608*2,rxsigF[aa]+196608*2,1); + dft98304(prach2+(196608*3),rxsigF[aa]+(196608*3),1); + reps+=2; + } + if (prach_fmt == 3) { + for (int i=0;i<4;i++) dft24576(prach2+(i*2*24576),rxsigF[aa]+(i*2*24576),1); + reps=4; + dftlen=24576; + } } - if (prach_fmt == 2) { - dft98304(prach2+196608*2,rxsigF[aa]+196608*2,1); - dft98304(prach2+(196608*3),rxsigF[aa]+(196608*3),1); - reps+=2; - } - if (prach_fmt == 3) { - for (int i=0;i<4;i++) dft24576(prach2+(i*2*24576),rxsigF[aa]+(i*2*24576),1); - reps=4; - dftlen=24576; - } - if (prach_fmt >3) { + else { dftlen=4096; dft4096(prach2,rxsigF[aa],1); - if (prach_fmt != 0xc0) { + if (prach_fmt != 7) { //!=C0 dft4096(prach2+8192,rxsigF[aa]+8192,1); reps++; } - } - if (prach_fmt == 0xa2 || prach_fmt == 0xa3 || prach_fmt == 0xb2 || prach_fmt == 0xb3 || prach_fmt == 0xb4 || prach_fmt == 0xc2) { - dft4096(prach2+8192*2,rxsigF[aa]+8192*2,1); - dft4096(prach2+8192*3,rxsigF[aa]+8192*3,1); - reps+=2; - } - if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xB4) { - dft4096(prach2+8192*4,rxsigF[aa]+8192*4,1); - dft4096(prach2+8192*5,rxsigF[aa]+8192*5,1); - reps+=2; - } - if (prach_fmt == 0xB4) { - for (int i=6;i<11;i++) dft4096(prach2+(8192*i),rxsigF[aa]+(8192*i),1); - reps+=6; + + if (prach_fmt == 1 || prach_fmt == 2 || prach_fmt == 4 || prach_fmt == 5 || prach_fmt == 6 || prach_fmt == 8) { + dft4096(prach2+8192*2,rxsigF[aa]+8192*2,1); + dft4096(prach2+8192*3,rxsigF[aa]+8192*3,1); + reps+=2; + } + if (prach_fmt == 2 || prach_fmt == 5 || prach_fmt == 6) { + dft4096(prach2+8192*4,rxsigF[aa]+8192*4,1); + dft4096(prach2+8192*5,rxsigF[aa]+8192*5,1); + reps+=2; + } + if (prach_fmt == 6) { + for (int i=6;i<11;i++) dft4096(prach2+(8192*i),rxsigF[aa]+(8192*i),1); + reps+=6; + } } } else { AssertFatal(fp->N_RB_UL <= 217,"cannot do more than 217 PRBs with 3/4 sampling\n"); prach2 = prach[aa] + (6*Ncp); // 80 MHz @ 92.16 Ms/s dftlen=73728; - if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) { - dft73728(prach2,rxsigF[aa],1); - reps++; - } - if (prach_fmt == 1 || prach_fmt == 2) { - dft73728(prach2+(2*73728),rxsigF[aa]+(2*73728),1); - reps++; - } - if (prach_fmt == 3) { - for (int i=0;i<4;i++) dft18432(prach2+(i*2*18432),rxsigF[aa]+(i*2*18432),1); - reps=4; - dftlen=18432; - } - - if (prach_fmt >3) { + if (prach_sequence_length == 0) { + if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) { + dft73728(prach2,rxsigF[aa],1); + reps++; + } + if (prach_fmt == 1 || prach_fmt == 2) { + dft73728(prach2+(2*73728),rxsigF[aa]+(2*73728),1); + reps++; + } + if (prach_fmt == 3) { + for (int i=0;i<4;i++) dft18432(prach2+(i*2*18432),rxsigF[aa]+(i*2*18432),1); + reps=4; + dftlen=18432; + } + } else { dftlen=3072; dft3072(prach2,rxsigF[aa],1); - if (prach_fmt != 0xc0) { + if (prach_fmt != 7) { //!=C0 dft3072(prach2+6144,rxsigF[aa]+6144,1); reps++; } - } - if (prach_fmt == 0xa2 || prach_fmt == 0xa3 || prach_fmt == 0xb2 || prach_fmt == 0xb3 || prach_fmt == 0xb4 || prach_fmt == 0xc2) { - dft3072(prach2+6144*2,rxsigF[aa]+6144*2,1); - dft3072(prach2+6144*3,rxsigF[aa]+6144*3,1); - reps+=2; - } - if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xB4) { - dft3072(prach2+6144*4,rxsigF[aa]+6144*4,1); - dft3072(prach2+6144*5,rxsigF[aa]+6144*5,1); - reps+=2; - } - if (prach_fmt == 0xB4) { - for (int i=6;i<11;i++) dft3072(prach2+(6144*i),rxsigF[aa]+(6144*i),1); - reps+=6; + + if (prach_fmt == 1 || prach_fmt == 2 || prach_fmt == 4 || prach_fmt == 5 || prach_fmt == 6 || prach_fmt == 8) { + dft3072(prach2+6144*2,rxsigF[aa]+6144*2,1); + dft3072(prach2+6144*3,rxsigF[aa]+6144*3,1); + reps+=2; + } + if (prach_fmt == 2 || prach_fmt == 5 || prach_fmt == 6) { + dft3072(prach2+6144*4,rxsigF[aa]+6144*4,1); + dft3072(prach2+6144*5,rxsigF[aa]+6144*5,1); + reps+=2; + } + if (prach_fmt == 6) { + for (int i=6;i<11;i++) dft3072(prach2+(6144*i),rxsigF[aa]+(6144*i),1); + reps+=6; + } } } } @@ -359,6 +378,7 @@ void rx_nr_prach_ru(RU_t *ru, } void rx_nr_prach(PHY_VARS_gNB *gNB, + nfapi_nr_prach_pdu_t *prach_pdu, int frame, int subframe, uint16_t *max_preamble, @@ -369,11 +389,12 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, int i; + nfapi_nr_prach_config_t *cfg=&gNB->gNB_config.prach_config; NR_DL_FRAME_PARMS *fp; + lte_frame_type_t frame_type; uint16_t rootSequenceIndex; - uint8_t prach_ConfigIndex; - uint8_t Ncs_config; + int numrootSequenceIndex; uint8_t restricted_set; uint8_t n_ra_prb; int16_t *prachF=NULL; @@ -403,63 +424,47 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, int16_t prach_ifft_tmp[2048*2] __attribute__((aligned(32))); int32_t *prach_ifft=(int32_t*)NULL; - nr_frequency_range_e freq_range; - - AssertFatal(gNB!=NULL,"Can only be called from gNB\n"); - fp = &gNB->frame_parms; - nb_rx = fp->nb_antennas_rx; - - frame_type = fp->frame_type; - freq_range = fp->freq_range; - rootSequenceIndex = fp->prach_config_common.rootSequenceIndex; - prach_ConfigIndex = fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex; - Ncs_config = fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig; - restricted_set = fp->prach_config_common.prach_ConfigInfo.highSpeedFlag; - - - uint8_t prach_fmt = get_nr_prach_fmt(prach_ConfigIndex,frame_type,freq_range); - uint16_t N_ZC = (prach_fmt <4)?839:139; AssertFatal(gNB!=NULL,"gNB is null\n"); + fp = &gNB->frame_parms; + + nb_rx = gNB->gNB_config.carrier_config.num_rx_ant.value; + + frame_type = gNB->gNB_config.cell_config.frame_duplex_type.value; + rootSequenceIndex = cfg->num_prach_fd_occasions_list[0].prach_root_sequence_index.value; + numrootSequenceIndex = cfg->num_prach_fd_occasions_list[0].num_root_sequences.value; + NCS = cfg->num_prach_fd_occasions_list[0].prach_zero_corr_conf.value; + int prach_sequence_length = cfg->prach_sequence_length.value; + + int msg1_frequencystart = cfg->num_prach_fd_occasions_list[0].k1.value; + // int num_unused_root_sequences = cfg->num_prach_fd_occasions_list[0].num_unused_root_sequences.value; + // cfg->num_prach_fd_occasions_list[0].unused_root_sequences_list + + restricted_set = cfg->restricted_set_config.value; + + AssertFatal(prach_sequence_length == 1, "no support yet for long prachSequenceLength\n"); + + + uint8_t prach_fmt = prach_pdu->prach_format; + uint16_t N_ZC = (prach_sequence_length==0)?839:139; + + + prach_ifft = gNB->prach_vars.prach_ifft; prachF = gNB->prach_vars.prachF; if (LOG_DEBUGFLAG(PRACH)){ - if ((frame&1023) < 20) LOG_D(PHY,"PRACH (gNB) : running rx_prach for subframe %d, msg1_frequencystart %d, prach_ConfigIndex %d , rootSequenceIndex %d\n", subframe,fp->prach_config_common.prach_ConfigInfo.msg1_frequencystart,prach_ConfigIndex,rootSequenceIndex); + if ((frame&1023) < 20) LOG_D(PHY,"PRACH (gNB) : running rx_prach for subframe %d, msg1_frequencystart %d, rootSequenceIndex %d\n", subframe,msg1_frequencystart,rootSequenceIndex); } - - int restricted_Type = 0; //this is hardcoded ('0' for restricted_TypeA; and '1' for restricted_TypeB). FIXME - if (prach_fmt<3){ - if (restricted_set == 0) { - NCS = NCS_unrestricted_delta_f_RA_125[Ncs_config]; - } else { - if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_125[Ncs_config]; // for TypeA, this is hardcoded. FIXME - if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_125[Ncs_config]; // for TypeB, this is hardcoded. FIXME - } - } - if (prach_fmt==3){ - if (restricted_set == 0) { - NCS = NCS_unrestricted_delta_f_RA_5[Ncs_config]; - } else { - if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_5[Ncs_config]; // for TypeA, this is hardcoded. FIXME - if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_5[Ncs_config]; // for TypeB, this is hardcoded. FIXME - } - } - if (prach_fmt>3){ - NCS = NCS_unrestricted_delta_f_RA_15[Ncs_config]; - } - - AssertFatal(NCS!=99,"NCS has not been set\n"); - - if (gNB) start_meas(&gNB->rx_prach); + start_meas(&gNB->rx_prach); - prach_root_sequence_map = (prach_fmt<4) ? prach_root_sequence_map_0_3 : prach_root_sequence_map_abc; + prach_root_sequence_map = (cfg->prach_sequence_length.value==0) ? prach_root_sequence_map_0_3 : prach_root_sequence_map_abc; // PDP is oversampled, e.g. 1024 sample instead of 839 // Adapt the NCS (zero-correlation zones) with oversampling factor e.g. 1024/839 @@ -562,8 +567,8 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, // Compute DFT of RX signal (conjugate input, results in conjugate output) for each new rootSequenceIndex if (LOG_DEBUGFLAG(PRACH)) { int en = dB_fixed(signal_energy((int32_t*)&rxsigF[0][0],840)); - if (en>60) LOG_I(PHY,"frame %d, subframe %d : preamble index %d, NCS %d, NCS_config %d, N_ZC/NCS %d: offset %d, preamble shift %d , en %d)\n", - frame,subframe,preamble_index,NCS,Ncs_config,N_ZC/NCS,preamble_offset,preamble_shift,en); + if (en>60) LOG_I(PHY,"frame %d, subframe %d : preamble index %d, NCS %d, N_ZC/NCS %d: offset %d, preamble shift %d , en %d)\n", + frame,subframe,preamble_index,NCS,N_ZC/NCS,preamble_offset,preamble_shift,en); } if (new_dft == 1) { @@ -644,12 +649,11 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, // max_preamble_delay * ( (2048/2^mu*(fs/30.72M)) / 256 ) / fs = TA * 16 * 64 / 2^mu * Tc uint16_t *TA = max_preamble_delay; int mu = fp->numerology_index; - if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) - *TA = *TA*3*(1< 3) - *TA = *TA/2; + if (cfg->prach_sequence_length.value==0) { + if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) *TA = *TA*3*(1<rx_prach); + stop_meas(&gNB->rx_prach); } diff --git a/openair1/PHY/NR_TRANSPORT/nr_transport.h b/openair1/PHY/NR_TRANSPORT/nr_transport.h index be73875058..bce0b62f8c 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_transport.h +++ b/openair1/PHY/NR_TRANSPORT/nr_transport.h @@ -112,6 +112,7 @@ NR_gNB_DLSCH_t *new_gNB_dlsch(NR_DL_FRAME_PARMS *frame_parms, uint16_t N_RB); void rx_nr_prach(PHY_VARS_gNB *gNB, + nfapi_nr_prach_pdu_t *prach_pdu, int frame, int subframe, uint16_t *max_preamble, @@ -120,6 +121,7 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, ); void rx_nr_prach_ru(RU_t *ru, + nfapi_nr_prach_pdu_t *prach_pdu, int frame, int subframe); diff --git a/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h b/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h index e8216ea004..b34bd12d75 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h +++ b/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h @@ -214,6 +214,7 @@ uint32_t nr_get_code_rate_ul(uint8_t Imcs, uint8_t table_idx); uint32_t nr_get_code_rate_dl(uint8_t Imcs, uint8_t table_idx); void rx_nr_prach(PHY_VARS_gNB *gNB, + nfapi_nr_prach_pdu_t *prach_pdu, int frame, int subframe, uint16_t *max_preamble, diff --git a/openair1/PHY/defs_RU.h b/openair1/PHY/defs_RU.h index 10496ced20..6d2b7db638 100644 --- a/openair1/PHY/defs_RU.h +++ b/openair1/PHY/defs_RU.h @@ -38,7 +38,7 @@ #include "openairinterface5g_limits.h" #include "PHY/TOOLS/time_meas.h" #include "defs_common.h" - +#include "nfapi_nr_interface_scf.h" #define MAX_BANDS_PER_RRU 4 #define MAX_RRU_CONFIG_SIZE 1024 @@ -480,6 +480,8 @@ typedef struct RU_t_s { int att_tx; /// flag to indicate precoding operation in RU int do_precoding; + /// FAPI confiuration + nfapi_nr_config_request_scf_t config; /// Frame parameters struct LTE_DL_FRAME_PARMS *frame_parms; struct NR_DL_FRAME_PARMS *nr_frame_parms; diff --git a/openair1/PHY/defs_gNB.h b/openair1/PHY/defs_gNB.h index f291261336..d7dde57a11 100644 --- a/openair1/PHY/defs_gNB.h +++ b/openair1/PHY/defs_gNB.h @@ -582,6 +582,9 @@ typedef struct { int prach_I0; } PHY_MEASUREMENTS_gNB; +#define MAX_NUM_NR_RX_RACH_PDUS 4 +#define MAX_NUM_NR_RX_PRACH_PREAMBLES 4 + /// Top-level PHY Data Structure for gNB typedef struct PHY_VARS_gNB_s { /// Module ID indicator for this instance @@ -620,7 +623,9 @@ typedef struct PHY_VARS_gNB_s { /// NFAPI CQI information (raw component) nfapi_cqi_indication_raw_pdu_t cqi_raw_pdu_list[NFAPI_CQI_IND_MAX_PDU]; /// NFAPI PRACH information - nfapi_preamble_pdu_t preamble_list[MAX_NUM_RX_PRACH_PREAMBLES]; + nfapi_nr_prach_indication_pdu_t prach_pdu_indication_list[MAX_NUM_NR_RX_RACH_PDUS]; + /// NFAPI PRACH information + nfapi_nr_prach_indication_preamble_t preamble_list[MAX_NUM_NR_RX_PRACH_PREAMBLES]; //Sched_Rsp_t Sched_INFO; nfapi_nr_ul_tti_request_t UL_tti_req; diff --git a/openair1/SCHED_NR/nr_prach_procedures.c b/openair1/SCHED_NR/nr_prach_procedures.c index b9a8ba94f1..7c1c9f890a 100644 --- a/openair1/SCHED_NR/nr_prach_procedures.c +++ b/openair1/SCHED_NR/nr_prach_procedures.c @@ -52,12 +52,14 @@ extern uint32_t nfapi_mode; extern int oai_nfapi_nr_rach_ind(nfapi_rach_indication_t *rach_ind); -void L1_nr_prach_procedures(PHY_VARS_gNB *gNB,int frame,int subframe) { +void L1_nr_prach_procedures(PHY_VARS_gNB *gNB,int frame,int slot, + nfapi_nr_prach_pdu_t *prach_pdu) { + uint16_t max_preamble[4],max_preamble_energy[4],max_preamble_delay[4]; uint16_t i; - gNB->UL_INFO.rach_ind.rach_indication_body.number_of_preambles=0; + gNB->UL_INFO.rach_ind.number_of_pdus=0; RU_t *ru; int aa=0; @@ -75,16 +77,18 @@ void L1_nr_prach_procedures(PHY_VARS_gNB *gNB,int frame,int subframe) { } } + rx_nr_prach(gNB, + prach_pdu, frame, - subframe, + slot, &max_preamble[0], &max_preamble_energy[0], &max_preamble_delay[0] ); - LOG_D(PHY,"[RAPROC] Frame %d, subframe %d : Most likely preamble %d, energy %d dB delay %d (prach_energy counter %d)\n", - frame,subframe, + LOG_D(PHY,"[RAPROC] Frame %d, slot %d : Most likely preamble %d, energy %d dB delay %d (prach_energy counter %d)\n", + frame,slot, max_preamble[0], max_preamble_energy[0]/10, max_preamble_delay[0], @@ -93,49 +97,42 @@ void L1_nr_prach_procedures(PHY_VARS_gNB *gNB,int frame,int subframe) { if ((gNB->prach_energy_counter == 100) && (max_preamble_energy[0] > gNB->measurements.prach_I0+100)) { - LOG_I(PHY,"[gNB %d][RAPROC] Frame %d, subframe %d Initiating RA procedure with preamble %d, energy %d.%d dB, delay %d\n", + LOG_I(PHY,"[gNB %d][RAPROC] Frame %d, slot %d Initiating RA procedure with preamble %d, energy %d.%d dB, delay %d\n", gNB->Mod_id, frame, - subframe, + slot, max_preamble[0], max_preamble_energy[0]/10, max_preamble_energy[0]%10, max_preamble_delay[0]); - T(T_ENB_PHY_INITIATE_RA_PROCEDURE, T_INT(gNB->Mod_id), T_INT(frame), T_INT(subframe), + T(T_ENB_PHY_INITIATE_RA_PROCEDURE, T_INT(gNB->Mod_id), T_INT(frame), T_INT(slot), T_INT(max_preamble[0]), T_INT(max_preamble_energy[0]), T_INT(max_preamble_delay[0])); - gNB->UL_INFO.rach_ind.rach_indication_body.number_of_preambles = 1; - gNB->UL_INFO.rach_ind.rach_indication_body.preamble_list = &gNB->preamble_list[0]; - gNB->UL_INFO.rach_ind.rach_indication_body.tl.tag = NFAPI_RACH_INDICATION_BODY_TAG; - gNB->UL_INFO.rach_ind.header.message_id = NFAPI_RACH_INDICATION; - gNB->UL_INFO.rach_ind.sfn_sf = frame<<4 | subframe; + gNB->UL_INFO.rach_ind.number_of_pdus = 1; + gNB->UL_INFO.rach_ind.pdu_list = &gNB->prach_pdu_indication_list[0]; + gNB->UL_INFO.rach_ind.sfn = frame; + gNB->UL_INFO.rach_ind.slot = slot; - gNB->preamble_list[0].preamble_rel8.tl.tag = NFAPI_PREAMBLE_REL8_TAG; - gNB->preamble_list[0].preamble_rel8.timing_advance = max_preamble_delay[0]; - gNB->preamble_list[0].preamble_rel8.preamble = max_preamble[0]; - gNB->preamble_list[0].preamble_rel8.rnti = 1+subframe; // note: fid is implicitly 0 here - gNB->preamble_list[0].instance_length = 0; //don't know exactly what this is - - if (nfapi_mode == 1) { // If NFAPI PNF then we need to send the message to the VNF - - LOG_D(PHY,"Filling NFAPI indication for NR RACH : SFN_SF:%d TA %d, Preamble %d, rnti %x\n", - NFAPI_SFNSF2DEC(gNB->UL_INFO.rach_ind.sfn_sf), - gNB->preamble_list[0].preamble_rel8.timing_advance, - gNB->preamble_list[0].preamble_rel8.preamble, - gNB->preamble_list[0].preamble_rel8.rnti); - AssertFatal(1==0,"shouldn't be here yet..\n"); - //oai_nfapi_nr_rach_ind(&gNB->UL_INFO.rach_ind); - - gNB->UL_INFO.rach_ind.rach_indication_body.number_of_preambles = 0; - } - } // max_preamble_energy > prach_I0 + 100 - else { - gNB->measurements.prach_I0 = ((gNB->measurements.prach_I0*900)>>10) + ((max_preamble_energy[0]*124)>>10); - if (frame==0) LOG_I(PHY,"prach_I0 = %d.%d dB\n",gNB->measurements.prach_I0/10,gNB->measurements.prach_I0%10); - if (gNB->prach_energy_counter < 100) gNB->prach_energy_counter++; - } + gNB->prach_pdu_indication_list[0].phy_cell_id = gNB->gNB_config.cell_config.phy_cell_id.value; + gNB->prach_pdu_indication_list[0].symbol_index = prach_pdu->prach_start_symbol; + gNB->prach_pdu_indication_list[0].slot_index = slot; + gNB->prach_pdu_indication_list[0].freq_index = 0; // single frequency for now + gNB->prach_pdu_indication_list[0].avg_rssi = (max_preamble_energy[0]<631) ? (128+(max_preamble_energy[0]/5)) : 254; + gNB->prach_pdu_indication_list[0].avg_snr = 0xff; // invalid for now + + + gNB->prach_pdu_indication_list[0].num_preamble = 1; + gNB->prach_pdu_indication_list[0].preamble_list = gNB->preamble_list; + gNB->prach_pdu_indication_list[0].preamble_list[0].preamble_index = max_preamble[0]; + gNB->prach_pdu_indication_list[0].preamble_list[0].timing_advance = max_preamble_delay[0]; + gNB->prach_pdu_indication_list[0].preamble_list[0].preamble_pwr = 0xffffffff; + } + gNB->measurements.prach_I0 = ((gNB->measurements.prach_I0*900)>>10) + ((max_preamble_energy[0]*124)>>10); + if (frame==0) LOG_I(PHY,"prach_I0 = %d.%d dB\n",gNB->measurements.prach_I0/10,gNB->measurements.prach_I0%10); + if (gNB->prach_energy_counter < 100) gNB->prach_energy_counter++; + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_PRACH_RX,0); } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index dd268d5dd6..c23f361fc9 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -57,8 +57,9 @@ void nr_initiate_ra_proc(module_id_t module_idP, frame_t frameP, sub_frame_t slotP, uint16_t preamble_index, - int16_t timing_offset, - uint16_t ra_rnti){ + int16_t timing_offset){ + + uint16_t ra_rnti=157; uint8_t i; uint16_t msg2_frame = frameP, msg2_slot = slotP; int offset; @@ -186,14 +187,6 @@ void nr_generate_Msg2(module_id_t module_idP, if ((ra->Msg2_frame == frameP) && (ra->Msg2_slot == slotP)) { - // todo - // Allocate 4 PRBS starting in RB 0 - // first_rb = 0; - // vrb_map[first_rb] = 1; - // vrb_map[first_rb + 1] = 1; - // vrb_map[first_rb + 2] = 1; - // vrb_map[first_rb + 3] = 1; - nfapi_nr_dl_tti_request_body_t *dl_req = &nr_mac->DL_req[CC_id].dl_tti_request_body; nfapi_nr_dl_tti_request_pdu_t *dl_config_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs]; nfapi_nr_pdu_t *tx_req = &nr_mac->TX_req[CC_id].pdu_list[nr_mac->TX_req[CC_id].Number_of_PDUs]; @@ -526,4 +519,4 @@ void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t config_uldci(ubwp, pusch_pdu, pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[0] = nr_dci_size(dci_formats[0], rnti_types[0], pdcch_pdu_rel15->BWPSize); fill_dci_pdu_rel15(pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); -} \ No newline at end of file +} diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index 89bb3e3f2c..28177e2919 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -90,11 +90,7 @@ void nr_schedule_RA(module_id_t module_idP, frame_t frameP, sub_frame_t slotP); @param rach_resource type (0=non BL/CE,1 CE level 0,2 CE level 1, 3 CE level 2,4 CE level 3) */ void nr_initiate_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP, - uint16_t preamble_index, int16_t timing_offset, uint16_t rnti - #if (RRC_VERSION >= MAKE_VERSION(14, 0, 0)) - , uint8_t rach_resource_type - #endif - ); + uint16_t preamble_index, int16_t timing_offset); void nr_clear_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP); diff --git a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c index bde960a2e1..8a0763daca 100644 --- a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c @@ -53,18 +53,23 @@ extern uint8_t nfapi_mode; extern uint16_t sf_ahead; void handle_nr_rach(NR_UL_IND_t *UL_info) { - if (UL_info->rach_ind.rach_indication_body.number_of_preambles>0) { - AssertFatal(UL_info->rach_ind.rach_indication_body.number_of_preambles==1,"More than 1 preamble not supported\n"); - UL_info->rach_ind.rach_indication_body.number_of_preambles=0; - LOG_D(MAC,"UL_info[Frame %d, Slot %d] Calling initiate_ra_proc RACH:SFN/SF:%d\n",UL_info->frame,UL_info->slot, NFAPI_SFNSF2DEC(UL_info->rach_ind.sfn_sf)); - + if (UL_info->rach_ind.number_of_pdus>0) { + AssertFatal(UL_info->rach_ind.number_of_pdus==1,"More than 1 RACH pdu not supported\n"); + UL_info->rach_ind.number_of_pdus=0; + LOG_D(MAC,"UL_info[Frame %d, Slot %d] Calling initiate_ra_proc RACH:SFN/SLOT:%d/%d\n",UL_info->frame,UL_info->slot, UL_info->rach_ind.sfn,UL_info->rach_ind.slot); + + + if (UL_info->rach_ind.pdu_list[0].num_preamble>0) + AssertFatal(UL_info->rach_ind.pdu_list[0].num_preamble==1, + "More than 1 preamble not supported\n"); + nr_initiate_ra_proc(UL_info->module_id, UL_info->CC_id, - NFAPI_SFNSF2SFN(UL_info->rach_ind.sfn_sf), - NFAPI_SFNSF2SF(UL_info->rach_ind.sfn_sf), - UL_info->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.preamble, - UL_info->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.timing_advance, - UL_info->rach_ind.rach_indication_body.preamble_list[0].preamble_rel8.rnti); + UL_info->rach_ind.sfn, + UL_info->rach_ind.slot, + UL_info->rach_ind.pdu_list[0].preamble_list[0].preamble_index, + UL_info->rach_ind.pdu_list[0].preamble_list[0].timing_advance); + } } @@ -220,11 +225,11 @@ void NR_UL_indication(NR_UL_IND_t *UL_info) { NR_Sched_Rsp_t *sched_info = &Sched_INFO[module_id][CC_id]; NR_IF_Module_t *ifi = if_inst[module_id]; gNB_MAC_INST *mac = RC.nrmac[module_id]; - LOG_D(PHY,"SFN/SF:%d%d module_id:%d CC_id:%d UL_info[rx_ind:%d harqs:%d crcs:%d cqis:%d preambles:%d sr_ind:%d]\n", + LOG_D(PHY,"SFN/SF:%d%d module_id:%d CC_id:%d UL_info[rx_ind:%d harqs:%d crcs:%d cqis:%d rach_pdus:%d sr_ind:%d]\n", UL_info->frame,UL_info->slot, module_id,CC_id, UL_info->rx_ind.rx_indication_body.number_of_pdus, UL_info->harq_ind.harq_indication_body.number_of_harqs, UL_info->crc_ind.crc_indication_body.number_of_crcs, UL_info->cqi_ind.number_of_cqis, - UL_info->rach_ind.rach_indication_body.number_of_preambles, UL_info->sr_ind.sr_indication_body.number_of_srs); + UL_info->rach_ind.number_of_pdus, UL_info->sr_ind.sr_indication_body.number_of_srs); if (nfapi_mode != 1) { if (ifi->CC_mask==0) { diff --git a/openair2/NR_PHY_INTERFACE/NR_IF_Module.h b/openair2/NR_PHY_INTERFACE/NR_IF_Module.h index 14355781d0..eaf0811883 100644 --- a/openair2/NR_PHY_INTERFACE/NR_IF_Module.h +++ b/openair2/NR_PHY_INTERFACE/NR_IF_Module.h @@ -74,10 +74,7 @@ typedef struct { nfapi_cqi_indication_body_t cqi_ind; /// RACH indication list - nfapi_rach_indication_t rach_ind; - - /// RACH indication list for BR UEs - nfapi_rach_indication_t rach_ind_br; + nfapi_nr_rach_indication_t rach_ind; /// SRS indication list nfapi_srs_indication_body_t srs_ind; From 5eeb25e2901e05b5478bbe93f7128e476bd4eee1 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Fri, 14 Feb 2020 09:58:36 +0100 Subject: [PATCH 038/553] integration of remaining FAPI PRACH interfaces in L1 along with list handling for PRACH RX requests --- openair1/PHY/NR_TRANSPORT/nr_dlsch_tools.c | 53 -------------------- openair1/PHY/NR_TRANSPORT/nr_prach.c | 34 +++++++++++++ openair1/PHY/NR_TRANSPORT/nr_ulsch.c | 57 ++++++++++++++++++++++ openair1/PHY/defs_gNB.h | 11 +++++ openair1/SCHED_NR/fapi_nr_l1.c | 23 +++++++-- openair1/SCHED_NR/fapi_nr_l1.h | 2 +- openair1/SCHED_NR/phy_procedures_nr_gNB.c | 47 ++++++------------ 7 files changed, 137 insertions(+), 90 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch_tools.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch_tools.c index b302728027..070f8e9ca7 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch_tools.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch_tools.c @@ -274,25 +274,7 @@ int16_t find_nr_dlsch(uint16_t rnti, PHY_VARS_gNB *gNB,find_type_t type) { return first_free_index; } -int16_t find_nr_ulsch(uint16_t rnti, PHY_VARS_gNB *gNB,find_type_t type) { - uint16_t i; - int16_t first_free_index=-1; - - AssertFatal(gNB!=NULL,"gNB is null\n"); - for (i=0; iulsch[i]!=NULL,"gNB->ulsch[%d] is null\n",i); - AssertFatal(gNB->ulsch[i][0]!=NULL,"gNB->ulsch[%d][0] is null\n",i); - LOG_D(PHY,"searching for rnti %x : ulsch_index %d=> harq_mask %x, rnti %x, first_free_index %d\n", rnti,i,gNB->ulsch[i][0]->harq_mask,gNB->ulsch[i][0]->rnti,first_free_index); - if ((gNB->ulsch[i][0]->harq_mask >0) && - (gNB->ulsch[i][0]->rnti==rnti)) return i; - else if ((gNB->ulsch[i][0]->harq_mask == 0) && (first_free_index==-1)) first_free_index=i; - } - if (type == SEARCH_EXIST) return -1; - if (first_free_index != -1) - gNB->ulsch[first_free_index][0]->rnti = 0; - return first_free_index; -} void nr_fill_dlsch(PHY_VARS_gNB *gNB, int frame, @@ -316,40 +298,5 @@ void nr_fill_dlsch(PHY_VARS_gNB *gNB, } -void nr_fill_ulsch(PHY_VARS_gNB *gNB, - int frame, - int slot, - nfapi_nr_pusch_pdu_t *ulsch_pdu) { - - int ulsch_id = find_nr_ulsch(ulsch_pdu->rnti,gNB,SEARCH_EXIST_OR_FREE); - AssertFatal( (ulsch_id>=0) && (ulsch_idrnti,ulsch_id); - - NR_gNB_ULSCH_t *ulsch = gNB->ulsch[ulsch_id][0]; - int harq_pid = ulsch_pdu->pusch_data.harq_process_id; - ulsch->rnti = ulsch_pdu->rnti; - //ulsch->rnti_type; - ulsch->harq_mask |= 1<harq_process_id[slot] = harq_pid; - - nfapi_nr_ul_config_ulsch_pdu *rel15_ul = &ulsch->harq_processes[harq_pid]->ulsch_pdu; - - LOG_D(PHY,"Initializing nFAPI for ULSCH, UE %d, harq_pid %d\n",ulsch_id,harq_pid); - - - //FK this is still a bad hack. We need to replace the L1 FAPI structures with the new scf ones as well. - rel15_ul->rnti = ulsch_pdu->rnti; - rel15_ul->ulsch_pdu_rel15.start_rb = ulsch_pdu->rb_start; - rel15_ul->ulsch_pdu_rel15.number_rbs = ulsch_pdu->rb_size; - rel15_ul->ulsch_pdu_rel15.start_symbol = ulsch_pdu->start_symbol_index; - rel15_ul->ulsch_pdu_rel15.number_symbols = ulsch_pdu->nr_of_symbols; - rel15_ul->ulsch_pdu_rel15.length_dmrs = gNB->dmrs_UplinkConfig.pusch_maxLength; - rel15_ul->ulsch_pdu_rel15.Qm = ulsch_pdu->qam_mod_order; - rel15_ul->ulsch_pdu_rel15.mcs = ulsch_pdu->mcs_index; - rel15_ul->ulsch_pdu_rel15.rv = ulsch_pdu->pusch_data.rv_index; - rel15_ul->ulsch_pdu_rel15.n_layers = ulsch_pdu->nrOfLayers; - rel15_ul->ulsch_pdu_rel15.R = ulsch_pdu->target_code_rate; - -} diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index 394871c631..db1452d970 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -46,6 +46,40 @@ extern uint16_t prach_root_sequence_map_abc[138]; extern uint16_t nr_du[838]; extern int16_t nr_ru[2*839]; +int16_t find_nr_prach(PHY_VARS_gNB *gNB,int frame,int slot, int numRA, find_type_t type) { + + uint16_t i; + int16_t first_free_index=-1; + + AssertFatal(gNB!=NULL,"gNB is null\n"); + for (i=0; i %d.%d numRA %d\n", frame,slot,numRA,i, + gNB->prach_vars.list[i].frame,gNB->prach_vars.list[i].slot,gNB->prach_vars.list[i].pdu.num_ra); + if ((gNB->prach_vars.list[i].frame == frame) && + (gNB->prach_vars.list[i].slot == slot) && + (gNB->prach_vars.list[i].pdu.num_ra == numRA)) return i; + else if ((gNB->prach_vars.list[i].frame == -1) && (first_free_index==-1)) first_free_index=i; + } + if (type == SEARCH_EXIST) return -1; + + return first_free_index; +} + +void nr_fill_prach(PHY_VARS_gNB *gNB, + int SFN, + int Slot, + nfapi_nr_prach_pdu_t *prach_pdu) { + + int prach_id = find_nr_prach(gNB,SFN,Slot,prach_pdu->num_ra,SEARCH_EXIST); + AssertFatal( (prach_id>=0) && (prach_idnum_ra,prach_id); + + gNB->prach_vars.list[prach_id].frame=SFN; + gNB->prach_vars.list[prach_id].slot=Slot; + memcpy((void*)&gNB->prach_vars.list[prach_id].pdu,(void*)prach_pdu,sizeof(*prach_pdu)); + +} + void rx_nr_prach_ru(RU_t *ru, nfapi_nr_prach_pdu_t *prach_pdu, int frame, diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch.c index 2bc623a66c..f79377422f 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch.c @@ -35,6 +35,63 @@ #include "PHY/NR_TRANSPORT/nr_ulsch.h" #include "PHY/LTE_REFSIG/lte_refsig.h" +int16_t find_nr_ulsch(uint16_t rnti, PHY_VARS_gNB *gNB,find_type_t type) { + + uint16_t i; + int16_t first_free_index=-1; + + AssertFatal(gNB!=NULL,"gNB is null\n"); + for (i=0; iulsch[i]!=NULL,"gNB->ulsch[%d] is null\n",i); + AssertFatal(gNB->ulsch[i][0]!=NULL,"gNB->ulsch[%d][0] is null\n",i); + LOG_D(PHY,"searching for rnti %x : ulsch_index %d=> harq_mask %x, rnti %x, first_free_index %d\n", rnti,i,gNB->ulsch[i][0]->harq_mask,gNB->ulsch[i][0]->rnti,first_free_index); + if ((gNB->ulsch[i][0]->harq_mask >0) && + (gNB->ulsch[i][0]->rnti==rnti)) return i; + else if ((gNB->ulsch[i][0]->harq_mask == 0) && (first_free_index==-1)) first_free_index=i; + } + if (type == SEARCH_EXIST) return -1; + if (first_free_index != -1) + gNB->ulsch[first_free_index][0]->rnti = 0; + return first_free_index; +} + +void nr_fill_ulsch(PHY_VARS_gNB *gNB, + int frame, + int slot, + nfapi_nr_pusch_pdu_t *ulsch_pdu) { + + + int ulsch_id = find_nr_ulsch(ulsch_pdu->rnti,gNB,SEARCH_EXIST_OR_FREE); + AssertFatal( (ulsch_id>=0) && (ulsch_idrnti,ulsch_id); + + NR_gNB_ULSCH_t *ulsch = gNB->ulsch[ulsch_id][0]; + int harq_pid = ulsch_pdu->pusch_data.harq_process_id; + ulsch->rnti = ulsch_pdu->rnti; + //ulsch->rnti_type; + ulsch->harq_mask |= 1<harq_process_id[slot] = harq_pid; + + nfapi_nr_ul_config_ulsch_pdu *rel15_ul = &ulsch->harq_processes[harq_pid]->ulsch_pdu; + + LOG_D(PHY,"Initializing nFAPI for ULSCH, UE %d, harq_pid %d\n",ulsch_id,harq_pid); + + + //FK this is still a bad hack. We need to replace the L1 FAPI structures with the new scf ones as well. + rel15_ul->rnti = ulsch_pdu->rnti; + rel15_ul->ulsch_pdu_rel15.start_rb = ulsch_pdu->rb_start; + rel15_ul->ulsch_pdu_rel15.number_rbs = ulsch_pdu->rb_size; + rel15_ul->ulsch_pdu_rel15.start_symbol = ulsch_pdu->start_symbol_index; + rel15_ul->ulsch_pdu_rel15.number_symbols = ulsch_pdu->nr_of_symbols; + rel15_ul->ulsch_pdu_rel15.length_dmrs = gNB->dmrs_UplinkConfig.pusch_maxLength; + rel15_ul->ulsch_pdu_rel15.Qm = ulsch_pdu->qam_mod_order; + rel15_ul->ulsch_pdu_rel15.mcs = ulsch_pdu->mcs_index; + rel15_ul->ulsch_pdu_rel15.rv = ulsch_pdu->pusch_data.rv_index; + rel15_ul->ulsch_pdu_rel15.n_layers = ulsch_pdu->nrOfLayers; + rel15_ul->ulsch_pdu_rel15.R = ulsch_pdu->target_code_rate; + +} + void nr_ulsch_unscrambling(int16_t* llr, uint32_t size, uint8_t q, diff --git a/openair1/PHY/defs_gNB.h b/openair1/PHY/defs_gNB.h index d7dde57a11..4a78782f78 100644 --- a/openair1/PHY/defs_gNB.h +++ b/openair1/PHY/defs_gNB.h @@ -43,6 +43,8 @@ #include "PHY/CODING/nrLDPC_decoder/nrLDPC_decoder.h" #include "PHY/CODING/nrLDPC_decoder/nrLDPC_types.h" +#include "nfapi_nr_interface_scf.h" + #define MAX_NUM_RU_PER_gNB MAX_NUM_RU_PER_eNB typedef struct { @@ -148,6 +150,14 @@ typedef struct { int16_t sqrt_rho_b; } NR_gNB_DLSCH_t; +typedef struct { + int frame; + int slot; + nfapi_nr_prach_pdu_t pdu; +} gNB_PRACH_list_t; + +#define NUMBER_OF_NR_PRACH_MAX 8 + typedef struct { /// \brief ?. /// first index: ? [0..1023] (hard coded) @@ -158,6 +168,7 @@ typedef struct { int16_t **rxsigF; /// \brief local buffer to compute prach_ifft int32_t *prach_ifft; + gNB_PRACH_list_t list[NUMBER_OF_NR_PRACH_MAX]; } NR_gNB_PRACH; typedef struct { diff --git a/openair1/SCHED_NR/fapi_nr_l1.c b/openair1/SCHED_NR/fapi_nr_l1.c index 5c145a3230..2d58cadb10 100644 --- a/openair1/SCHED_NR/fapi_nr_l1.c +++ b/openair1/SCHED_NR/fapi_nr_l1.c @@ -145,10 +145,8 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){ gNB = RC.gNB[Mod_id]; uint8_t number_dl_pdu = DL_req->dl_tti_request_body.nPDUs; - // uint8_t number_ul_pdu = 0; uint8_t number_ul_dci_pdu = (UL_dci_req==NULL) ? 0 : UL_dci_req->numPdus; - - // if (UL_tti_req != NULL) number_ul_pdu = UL_tti_req->n_pdus; + uint8_t number_ul_tti_pdu = (UL_tti_req==NULL) ? 0 : UL_tti_req->n_pdus; LOG_D(PHY,"NFAPI: Sched_INFO:SFN/SLOT:%04d%d DL_req:SFN/SLO:%04d%d:dl_pdu:%d tx_req:SFN/SLOT:%04d%d:pdus:%d;\n", frame,slot, @@ -194,7 +192,7 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){ } } - if (UL_tti_req!=NULL) memcpy(&gNB->UL_tti_req,UL_tti_req,sizeof(nfapi_nr_ul_tti_request_t)); + // if (UL_tti_req!=NULL) memcpy(&gNB->UL_tti_req,UL_tti_req,sizeof(nfapi_nr_ul_tti_request_t)); for (int i=0;iul_dci_pdu_list[i]); } + for (int i = 0; i < number_ul_tti_pdu; i++) { + switch (UL_tti_req->pdus_list[i].pdu_type) { + case NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE: + LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE for %d.%d\n",frame,slot,UL_tti_req->SFN,UL_tti_req->Slot); + nr_fill_ulsch(gNB,frame,slot,&UL_tti_req->pdus_list[i].pusch_pdu); + break; + case NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE: + LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE for %d.%d\n",frame,slot,UL_tti_req->SFN,UL_tti_req->Slot); + // handle_nfapi_nr_pucch_pdu(gNB,frame,slot,UL_tti_req->pdus_list[i].pucch_pdu); + break; + case NFAPI_NR_UL_CONFIG_PRACH_PDU_TYPE: + LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PRACH_PDU_TYPE for %d.%d\n",frame,slot,UL_tti_req->SFN,UL_tti_req->Slot); + nr_fill_prach(gNB,UL_tti_req->SFN,UL_tti_req->Slot,UL_tti_req->pdus_list[i].prach_pdu); + break; + } + } + } diff --git a/openair1/SCHED_NR/fapi_nr_l1.h b/openair1/SCHED_NR/fapi_nr_l1.h index 5a55167c12..07509b3bb7 100644 --- a/openair1/SCHED_NR/fapi_nr_l1.h +++ b/openair1/SCHED_NR/fapi_nr_l1.h @@ -48,4 +48,4 @@ void handle_nr_nfapi_pdsch_pdu(PHY_VARS_gNB *gNB,int frame,int slot, void nr_fill_rx_indication(PHY_VARS_gNB *gNB, int frame, int slot_rx, int UE_id, uint8_t harq_pid); -void nr_fill_crc_indication(PHY_VARS_gNB *gNB, int frame, int slot_rx, int UE_id, uint8_t crc_flag); \ No newline at end of file +void nr_fill_crc_indication(PHY_VARS_gNB *gNB, int frame, int slot_rx, int UE_id, uint8_t crc_flag); diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index 5cbe2816fd..8fbe7c8ba8 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -390,41 +390,24 @@ void phy_procedures_gNB_common_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) { - nfapi_nr_ul_tti_request_t *UL_tti_req = &gNB->UL_tti_req; - int num_pdus = UL_tti_req->n_pdus; + LOG_D(PHY,"phy_procedures_gNB_uespec_RX frame %d, slot %d\n",frame_rx,slot_rx); - LOG_D(PHY,"phy_procedures_gNB_uespec_RX frame %d, slot %d, num_pdus %d\n",frame_rx,slot_rx,num_pdus); + for (int ULSCH_id=0;ULSCH_idulsch[ULSCH_id]; - gNB->UL_INFO.rx_ind.rx_indication_body.number_of_pdus = 0; - - for (int i = 0; i < num_pdus; i++) { - switch (UL_tti_req->pdus_list[i].pdu_type) { - case NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE: - LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE\n",frame_rx,slot_rx); - - nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[0].pusch_pdu; - nr_fill_ulsch(gNB,frame_rx,slot_rx,pusch_pdu); - - uint8_t ULSCH_id = find_nr_ulsch(pusch_pdu->rnti,gNB,SEARCH_EXIST); - uint8_t harq_pid = pusch_pdu->pusch_data.harq_process_id; - uint8_t symbol_start = pusch_pdu->start_symbol_index; - uint8_t symbol_end = symbol_start + pusch_pdu->nr_of_symbols; + if (ulsch->rnti > 0) { + uint8_t harq_pid = ulsch->harq_process_id[slot_rx]; + uint8_t symbol_start = ulsch->harq_processes[harq_pid]->ulsch_pdu.ulsch_pdu_rel15.start_symbol; + uint8_t symbol_end = symbol_start + ulsch->harq_processes[harq_pid]->ulsch_pdu.ulsch_pdu_rel15.number_symbols; - for(uint8_t symbol = symbol_start; symbol < symbol_end; symbol++) { - nr_rx_pusch(gNB, ULSCH_id, frame_rx, slot_rx, symbol, harq_pid); - } - //LOG_M("rxdataF_comp.m","rxF_comp",gNB->pusch_vars[0]->rxdataF_comp[0],6900,1,1); - //LOG_M("rxdataF_ext.m","rxF_ext",gNB->pusch_vars[0]->rxdataF_ext[0],6900,1,1); - nr_ulsch_procedures(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); - nr_fill_rx_indication(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); // indicate SDU to MAC - nr_fill_crc_indication(gNB, frame_rx, slot_rx, ULSCH_id, 0); - break; - case NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE: - LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE\n",frame_rx,slot_rx); - break; - case NFAPI_NR_UL_CONFIG_PRACH_PDU_TYPE: - LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PRACH_PDU_TYPE\n",frame_rx,slot_rx); - break; + for(uint8_t symbol = symbol_start; symbol < symbol_end; symbol++) { + nr_rx_pusch(gNB, ULSCH_id, frame_rx, slot_rx, symbol, harq_pid); + } + //LOG_M("rxdataF_comp.m","rxF_comp",gNB->pusch_vars[0]->rxdataF_comp[0],6900,1,1); + //LOG_M("rxdataF_ext.m","rxF_ext",gNB->pusch_vars[0]->rxdataF_ext[0],6900,1,1); + nr_ulsch_procedures(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); + nr_fill_rx_indication(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); // indicate SDU to MAC + nr_fill_crc_indication(gNB, frame_rx, slot_rx, ULSCH_id, 0); } } } From a248c44d318a293d4386e403f1526334dd18bf3c Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 14 Feb 2020 18:57:04 +0100 Subject: [PATCH 039/553] computation nb of root sequences in mac (plus some clean up in prach_common.c --- openair1/PHY/NR_TRANSPORT/nr_prach.c | 7 - openair1/PHY/NR_TRANSPORT/nr_prach_common.c | 215 ++---------------- .../PHY/NR_TRANSPORT/nr_transport_proto.h | 5 + .../NR_TRANSPORT/nr_transport_proto_common.h | 7 +- openair1/SCHED_NR/fapi_nr_l1.c | 3 +- openair1/SCHED_NR/phy_procedures_nr_gNB.c | 2 - openair2/GNB_APP/RRC_nr_paramsvalues.h | 2 +- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 118 ++++++++++ openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h | 6 + openair2/LAYER2/NR_MAC_gNB/config.c | 9 +- .../CONF/gnb.band78.tm1.106PRB.usrpn300.conf | 10 +- .../CONF/gnb.band78.tm1.106PRB.usrpx300.conf | 8 +- 12 files changed, 178 insertions(+), 214 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index db1452d970..822efba69d 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -34,13 +34,6 @@ #include "PHY/NR_TRANSPORT/nr_transport.h" #include "PHY/NR_TRANSPORT/nr_transport_proto_common.h" -extern uint16_t NCS_unrestricted_delta_f_RA_125[16]; -extern uint16_t NCS_restricted_TypeA_delta_f_RA_125[15]; -extern uint16_t NCS_restricted_TypeB_delta_f_RA_125[13]; -extern uint16_t NCS_unrestricted_delta_f_RA_5[16]; -extern uint16_t NCS_restricted_TypeA_delta_f_RA_5[16]; -extern uint16_t NCS_restricted_TypeB_delta_f_RA_5[14]; -extern uint16_t NCS_unrestricted_delta_f_RA_15[16]; extern uint16_t prach_root_sequence_map_0_3[838]; extern uint16_t prach_root_sequence_map_abc[138]; extern uint16_t nr_du[838]; diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c index 67534ccce7..65da6fc49f 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c @@ -37,10 +37,10 @@ #include "PHY/NR_TRANSPORT/nr_transport_proto_common.h" #include "common/utils/LOG/log.h" #include "common/utils/LOG/vcd_signal_dumper.h" - +#include "openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h" #include "T.h" -void init_nr_prach_tables(int N_ZC); + void dump_nr_prach_config(NR_DL_FRAME_PARMS *frame_parms,uint8_t subframe) { @@ -79,20 +79,10 @@ void dump_nr_prach_config(NR_DL_FRAME_PARMS *frame_parms,uint8_t subframe) { } // This function computes the du -void nr_fill_du(uint8_t prach_fmt) +void nr_fill_du(uint16_t N_ZC,uint16_t *prach_root_sequence_map) { uint16_t iu,u,p; - uint16_t N_ZC; - uint16_t *prach_root_sequence_map; - - if (prach_fmt<4) { - N_ZC = 839; - prach_root_sequence_map = prach_root_sequence_map_0_3; - } else { - N_ZC = 139; - prach_root_sequence_map = prach_root_sequence_map_abc; - } for (iu=0; iu<(N_ZC-1); iu++) { @@ -107,97 +97,39 @@ void nr_fill_du(uint8_t prach_fmt) } -int is_nr_prach_subframe(NR_DL_FRAME_PARMS *frame_parms,uint32_t frame, uint8_t subframe) { - uint8_t prach_ConfigIndex = frame_parms->prach_config_common.prach_ConfigInfo.prach_ConfigIndex; - -/* // For FR1 paired - if (frame_parms->frame_type == FDD && frame_parms->freq_range == nr_FR1){ - if (((frame%table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][2]) == table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][3]) && - ((table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][4]&(1<frame_type == TDD && frame_parms->freq_range == nr_FR1) { - // For FR1 unpaired - if (((frame%table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][2]) == table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][3]) && - ((table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][4]&(1<slots_per_subframe; - // when were in the last slot of the subframe and this is a PRACH subframe ,return 1 - if (((slot%fp->slots_per_subframe) == fp->slots_per_subframe-1)&& - (is_nr_prach_subframe(fp,frame,subframe))) return (1); - else return(0); -} - -uint16_t get_nr_prach_fmt(int prach_ConfigIndex,lte_frame_type_t frame_type, nr_frequency_range_e fr) +void compute_nr_prach_seq(nfapi_nr_config_request_scf_t *config, + uint8_t fd_occasion, + uint32_t **X_u) { - - /* if (frame_type==FDD) return (table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][0]); // if using table 6.3.3.2-2: Random access configurations for FR1 and paired spectrum/supplementary uplink - else if (fr==nr_FR1) return (table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][0]); // if using table 6.3.3.2-3: Random access configurations for FR1 and unpaired spectrum - else AssertFatal(1==0,"FR2 prach configuration not supported yet\n");*/ - // For FR2 not implemented. FIXME -} - -void compute_nr_prach_seq(uint16_t rootSequenceIndex, - uint8_t prach_ConfigIndex, - uint8_t zeroCorrelationZoneConfig, - uint8_t highSpeedFlag, - lte_frame_type_t frame_type, - nr_frequency_range_e fr, - uint32_t X_u[64][839]) -{ - // Compute DFT of x_u => X_u[k] = x_u(inv(u)*k)^* X_u[k] = exp(j\pi u*inv(u)*k*(inv(u)*k+1)/N_ZC) - unsigned int k,inv_u,i,NCS=0,num_preambles; + nfapi_nr_prach_config_t prach_config = config->prach_config; + unsigned int k,inv_u,i; int N_ZC; - uint8_t prach_fmt = get_nr_prach_fmt(prach_ConfigIndex,frame_type,fr); + uint16_t *prach_root_sequence_map; - uint16_t u, preamble_offset; - uint16_t n_shift_ra,n_shift_ra_bar, d_start,numshift; - uint8_t not_found; + uint16_t u; + uint8_t short_sequence = prach_config.prach_sequence_length.value; + uint8_t num_sequences = prach_config.num_prach_fd_occasions_list[fd_occasion].num_root_sequences.value; + uint8_t rootSequenceIndex = prach_config.num_prach_fd_occasions_list[fd_occasion].prach_root_sequence_index.value; VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_UE_COMPUTE_PRACH, VCD_FUNCTION_IN); #ifdef NR_PRACH_DEBUG - LOG_I(PHY,"compute_prach_seq: NCS_config %d, prach_fmt %x\n",zeroCorrelationZoneConfig, prach_fmt); + LOG_I(PHY,"compute_prach_seq: NCS_config %d, prach short sequence? %x\n",zeroCorrelationZoneConfig, prach_c); #endif - N_ZC = (prach_fmt < 4) ? 839 : 139; + N_ZC = (short_sequence) ? 139 : 839; //init_prach_tables(N_ZC); //moved to phy_init_lte_ue/eNB, since it takes to long in real-time init_nr_prach_tables(N_ZC); - if (prach_fmt < 4) { - prach_root_sequence_map = prach_root_sequence_map_0_3; - } else { + if (short_sequence) { // FIXME cannot be reached prach_root_sequence_map = prach_root_sequence_map_abc; + } else { + prach_root_sequence_map = prach_root_sequence_map_0_3; } @@ -205,114 +137,15 @@ void compute_nr_prach_seq(uint16_t rootSequenceIndex, LOG_I( PHY, "compute_prach_seq: done init prach_tables\n" ); #endif + for (i=0; i3) NCS = NCS_unrestricted_delta_f_RA_15[zeroCorrelationZoneConfig];*/ - - num_preambles = (NCS==0) ? 64 : ((64*NCS)/N_ZC); - - if (NCS>0) num_preambles++; - - preamble_offset = 0; - } else { - -#ifdef PRACH_DEBUG - LOG_I( PHY, "high speed prach : NCS_config %"PRIu8"\n", zeroCorrelationZoneConfig ); -#endif - - AssertFatal(zeroCorrelationZoneConfig<=14, - "FATAL, Illegal Ncs_config for restricted format %"PRIu8"\n", zeroCorrelationZoneConfig ); - /* if (prach_fmt<3){ - if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_125[zeroCorrelationZoneConfig]; // for TypeA, this is hardcoded. FIXME - if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_125[zeroCorrelationZoneConfig]; // for TypeB, this is hardcoded. FIXME - } - if (prach_fmt==3){ - if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_5[zeroCorrelationZoneConfig]; // for TypeA, this is hardcoded. FIXME - if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_5[zeroCorrelationZoneConfig]; // for TypeB, this is hardcoded. FIXME - } - if (prach_fmt>3){ - - }*/ - - nr_fill_du(prach_fmt); - - num_preambles = 64; // compute ZC sequence for 64 possible roots - // find first non-zero shift root (stored in preamble_offset) - not_found = 1; - preamble_offset = 0; - - while (not_found == 1) { - // current root depending on rootSequenceIndex - int index = (rootSequenceIndex + preamble_offset) % N_ZC; - - if (prach_fmt<4) { - // prach_root_sequence_map points to prach_root_sequence_map0_3 - DevAssert( index < sizeof(prach_root_sequence_map_0_3) / sizeof(prach_root_sequence_map_0_3[0]) ); - } else { - // prach_root_sequence_map points to prach_root_sequence_map4 - DevAssert( index < sizeof(prach_root_sequence_map_abc) / sizeof(prach_root_sequence_map_abc[0]) ); - } - - u = prach_root_sequence_map[index]; - - uint16_t n_group_ra = 0; - - if ( (nr_du[u]<(N_ZC/3)) && (nr_du[u]>=NCS) ) { - n_shift_ra = nr_du[u]/NCS; - d_start = (nr_du[u]<<1) + (n_shift_ra * NCS); - n_group_ra = N_ZC/d_start; - n_shift_ra_bar = max(0,(N_ZC-(nr_du[u]<<1)-(n_group_ra*d_start))/N_ZC); - } else if ( (nr_du[u]>=(N_ZC/3)) && (nr_du[u]<=((N_ZC - NCS)>>1)) ) { - n_shift_ra = (N_ZC - (nr_du[u]<<1))/NCS; - d_start = N_ZC - (nr_du[u]<<1) + (n_shift_ra * NCS); - n_group_ra = nr_du[u]/d_start; - n_shift_ra_bar = min(n_shift_ra,max(0,(nr_du[u]- (n_group_ra*d_start))/NCS)); - } else { - n_shift_ra = 0; - n_shift_ra_bar = 0; - } - - // This is the number of cyclic shifts for the current root u - numshift = (n_shift_ra*n_group_ra) + n_shift_ra_bar; - - // skip to next root and recompute parameters if numshift==0 - if (numshift>0) - not_found = 0; - else - preamble_offset++; - } - } - -#ifdef PRACH_DEBUG - - if (NCS>0) - LOG_I( PHY, "Initializing %u preambles for PRACH (NCS_config %"PRIu8", NCS %u, N_ZC/NCS %u)\n", - num_preambles, zeroCorrelationZoneConfig, NCS, N_ZC/NCS ); - -#endif - - for (i=0; iSFN,UL_tti_req->Slot); - nr_fill_prach(gNB,UL_tti_req->SFN,UL_tti_req->Slot,UL_tti_req->pdus_list[i].prach_pdu); + nfapi_nr_prach_pdu_t *prach_pdu = &UL_tti_req->pdus_list[i].prach_pdu; + nr_fill_prach(gNB,UL_tti_req->SFN,UL_tti_req->Slot,prach_pdu); break; } } diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index 8fbe7c8ba8..75daf0d5ab 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -208,8 +208,6 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB, // VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_ENB_RX,1); - - if (do_prach_rx(fp,frame,slot)) L1_nr_prach_procedures(gNB,frame,slot/fp->slots_per_subframe); */ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH_id, uint8_t harq_pid) diff --git a/openair2/GNB_APP/RRC_nr_paramsvalues.h b/openair2/GNB_APP/RRC_nr_paramsvalues.h index 82873f22b4..f94990d4d8 100644 --- a/openair2/GNB_APP/RRC_nr_paramsvalues.h +++ b/openair2/GNB_APP/RRC_nr_paramsvalues.h @@ -311,7 +311,7 @@ {GNB_CONFIG_STRING_RSRPTHRESHOLDSSB,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rsrp_ThresholdSSB,defint64val:19,TYPE_INT64,0/*82*/},\ {GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEXPR,NULL,0,uptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.present,defuintval:NR_RACH_ConfigCommon__prach_RootSequenceIndex_PR_l139,TYPE_UINT,0/*83*/},\ {GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEX,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.choice.l139,defint64val:0,TYPE_INT64,0/*84*/},\ -{GNB_CONFIG_STRING_MSG1SUBCARRIERSPACING,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig,defintval:NR_RACH_ConfigCommon__restrictedSetConfig_unrestrictedSet,TYPE_INT64,0/*85*/}, \ +{GNB_CONFIG_STRING_RESTRICTEDSETCONFIG,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig,defintval:NR_RACH_ConfigCommon__restrictedSetConfig_unrestrictedSet,TYPE_INT64,0/*85*/}, \ {GNB_CONFIG_STRING_INITIALULBWPK2_0,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->k2,defint64val:-1,TYPE_INT64,0/*86*/},\ {GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_0,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,/*87*/},\ {GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_0,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->startSymbolAndLength,defint64val:55,TYPE_INT64,0/*88*/},\ diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index 8c6e5f1d56..f6fac735dd 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -863,6 +863,19 @@ int64_t table_6_3_3_2_4_prachConfig_Index [256][10] = { }; +int get_format0(uint8_t index, + uint8_t unpaired){ + + uint16_t format; + if (unpaired) + format = table_6_3_3_2_3_prachConfig_Index[index][0]; + else + format = table_6_3_3_2_2_prachConfig_Index[index][0]; + + return format; +} + + int get_nr_prach_info_from_index(uint8_t index, int frame, int slot, @@ -962,6 +975,111 @@ int get_nr_prach_info_from_index(uint8_t index, } } +//Table 6.3.3.1-3: Mapping from logical index i to sequence number u for preamble formats with L_RA = 839 +uint16_t table_63313[838] = { +129, 710, 140, 699, 120, 719, 210, 629, 168, 671, 84 , 755, 105, 734, 93 , 746, 70 , 769, 60 , 779, +2 , 837, 1 , 838, 56 , 783, 112, 727, 148, 691, 80 , 759, 42 , 797, 40 , 799, 35 , 804, 73 , 766, +146, 693, 31 , 808, 28 , 811, 30 , 809, 27 , 812, 29 , 810, 24 , 815, 48 , 791, 68 , 771, 74 , 765, +178, 661, 136, 703, 86 , 753, 78 , 761, 43 , 796, 39 , 800, 20 , 819, 21 , 818, 95 , 744, 202, 637, +190, 649, 181, 658, 137, 702, 125, 714, 151, 688, 217, 622, 128, 711, 142, 697, 122, 717, 203, 636, +118, 721, 110, 729, 89 , 750, 103, 736, 61 , 778, 55 , 784, 15 , 824, 14 , 825, 12 , 827, 23 , 816, +34 , 805, 37 , 802, 46 , 793, 207, 632, 179, 660, 145, 694, 130, 709, 223, 616, 228, 611, 227, 612, +132, 707, 133, 706, 143, 696, 135, 704, 161, 678, 201, 638, 173, 666, 106, 733, 83 , 756, 91 , 748, +66 , 773, 53 , 786, 10 , 829, 9 , 830, 7 , 832, 8 , 831, 16 , 823, 47 , 792, 64 , 775, 57 , 782, +104, 735, 101, 738, 108, 731, 208, 631, 184, 655, 197, 642, 191, 648, 121, 718, 141, 698, 149, 690, +216, 623, 218, 621, 152, 687, 144, 695, 134, 705, 138, 701, 199, 640, 162, 677, 176, 663, 119, 720, +158, 681, 164, 675, 174, 665, 171, 668, 170, 669, 87 , 752, 169, 670, 88 , 751, 107, 732, 81 , 758, +82 , 757, 100, 739, 98 , 741, 71 , 768, 59 , 780, 65 , 774, 50 , 789, 49 , 790, 26 , 813, 17 , 822, +13 , 826, 6 , 833, 5 , 834, 33 , 806, 51 , 788, 75 , 764, 99 , 740, 96 , 743, 97 , 742, 166, 673, +172, 667, 175, 664, 187, 652, 163, 676, 185, 654, 200, 639, 114, 725, 189, 650, 115, 724, 194, 645, +195, 644, 192, 647, 182, 657, 157, 682, 156, 683, 211, 628, 154, 685, 123, 716, 139, 700, 212, 627, +153, 686, 213, 626, 215, 624, 150, 689, 225, 614, 224, 615, 221, 618, 220, 619, 127, 712, 147, 692, +124, 715, 193, 646, 205, 634, 206, 633, 116, 723, 160, 679, 186, 653, 167, 672, 79 , 760, 85 , 754, +77 , 762, 92 , 747, 58 , 781, 62 , 777, 69 , 770, 54 , 785, 36 , 803, 32 , 807, 25 , 814, 18 , 821, +11 , 828, 4 , 835, 3 , 836, 19 , 820, 22 , 817, 41 , 798, 38 , 801, 44 , 795, 52 , 787, 45 , 794, +63 , 776, 67 , 772, 72 , 767, 76 , 763, 94 , 745, 102, 737, 90 , 749, 109, 730, 165, 674, 111, 728, +209, 630, 204, 635, 117, 722, 188, 651, 159, 680, 198, 641, 113, 726, 183, 656, 180, 659, 177, 662, +196, 643, 155, 684, 214, 625, 126, 713, 131, 708, 219, 620, 222, 617, 226, 613, 230, 609, 232, 607, +262, 577, 252, 587, 418, 421, 416, 423, 413, 426, 411, 428, 376, 463, 395, 444, 283, 556, 285, 554, +379, 460, 390, 449, 363, 476, 384, 455, 388, 451, 386, 453, 361, 478, 387, 452, 360, 479, 310, 529, +354, 485, 328, 511, 315, 524, 337, 502, 349, 490, 335, 504, 324, 515, 323, 516, 320, 519, 334, 505, +359, 480, 295, 544, 385, 454, 292, 547, 291, 548, 381, 458, 399, 440, 380, 459, 397, 442, 369, 470, +377, 462, 410, 429, 407, 432, 281, 558, 414, 425, 247, 592, 277, 562, 271, 568, 272, 567, 264, 575, +259, 580, 237, 602, 239, 600, 244, 595, 243, 596, 275, 564, 278, 561, 250, 589, 246, 593, 417, 422, +248, 591, 394, 445, 393, 446, 370, 469, 365, 474, 300, 539, 299, 540, 364, 475, 362, 477, 298, 541, +312, 527, 313, 526, 314, 525, 353, 486, 352, 487, 343, 496, 327, 512, 350, 489, 326, 513, 319, 520, +332, 507, 333, 506, 348, 491, 347, 492, 322, 517, 330, 509, 338, 501, 341, 498, 340, 499, 342, 497, +301, 538, 366, 473, 401, 438, 371, 468, 408, 431, 375, 464, 249, 590, 269, 570, 238, 601, 234, 605, +257, 582, 273, 566, 255, 584, 254, 585, 245, 594, 251, 588, 412, 427, 372, 467, 282, 557, 403, 436, +396, 443, 392, 447, 391, 448, 382, 457, 389, 450, 294, 545, 297, 542, 311, 528, 344, 495, 345, 494, +318, 521, 331, 508, 325, 514, 321, 518, 346, 493, 339, 500, 351, 488, 306, 533, 289, 550, 400, 439, +378, 461, 374, 465, 415, 424, 270, 569, 241, 598, 231, 608, 260, 579, 268, 571, 276, 563, 409, 430, +398, 441, 290, 549, 304, 535, 308, 531, 358, 481, 316, 523, 293, 546, 288, 551, 284, 555, 368, 471, +253, 586, 256, 583, 263, 576, 242, 597, 274, 565, 402, 437, 383, 456, 357, 482, 329, 510, 317, 522, +307, 532, 286, 553, 287, 552, 266, 573, 261, 578, 236, 603, 303, 536, 356, 483, 355, 484, 405, 434, +404, 435, 406, 433, 235, 604, 267, 572, 302, 537, 309, 530, 265, 574, 233, 606, 367, 472, 296, 543, +336, 503, 305, 534, 373, 466, 280, 559, 279, 560, 419, 420, 240, 599, 258, 581, 229, 610 +}; + +uint8_t compute_nr_root_seq(NR_RACH_ConfigCommon_t *rach_config, + uint8_t nb_preambles, + uint8_t unpaired) { + + uint8_t config_index = rach_config->rach_ConfigGeneric.prach_ConfigurationIndex; + uint8_t ncs_index = rach_config->rach_ConfigGeneric.zeroCorrelationZoneConfig; + uint16_t format0 = get_format0(config_index, unpaired); + uint16_t NCS = get_NCS(ncs_index, format0, rach_config->restrictedSetConfig); + uint16_t L_ra = (rach_config->prach_RootSequenceIndex.present) ? 139 : 839; + uint16_t r,u,index,q,d_u,n_shift_ra,n_shift_ra_bar,d_start; + uint32_t w; + uint8_t found_preambles = 0; + uint8_t found_sequences = 0; + + if (rach_config->restrictedSetConfig == 0) { + if (NCS == 0) return nb_preambles; + else { + r = L_ra/NCS; + return (nb_preambles/r); + } + } + else{ + index = rach_config->prach_RootSequenceIndex.choice.l839; + while (found_preambles < nb_preambles) { + u = table_63313[index%(L_ra-1)]; + + q = 0; + while (((q*u)%L_ra) != 1) q++; + if (q < 420) d_u = q; + else d_u = L_ra - q; + + uint16_t n_group_ra = 0; + if (rach_config->restrictedSetConfig == 1) { + if ( (d_u<280) && (d_u>=NCS) ) { + n_shift_ra = d_u/NCS; + d_start = (d_u<<1) + (n_shift_ra * NCS); + n_group_ra = L_ra/d_start; + n_shift_ra_bar = max(0,(L_ra-(d_u<<1)-(n_group_ra*d_start))/L_ra); + } else if ( (d_u>=280) && (d_u<=((L_ra - NCS)>>1)) ) { + n_shift_ra = (L_ra - (d_u<<1))/NCS; + d_start = L_ra - (d_u<<1) + (n_shift_ra * NCS); + n_group_ra = d_u/d_start; + n_shift_ra_bar = min(n_shift_ra,max(0,(d_u- (n_group_ra*d_start))/NCS)); + } else { + n_shift_ra = 0; + n_shift_ra_bar = 0; + } + w = n_shift_ra*n_group_ra + n_shift_ra_bar; + found_preambles += w; + found_sequences++; + } + else { + AssertFatal(1==0,"Procedure to find nb of sequences for restricted type B not implemented yet"); + } + } + return found_sequences; + } +} + nr_bandentry_t nr_bandtable[] = { {1, 1920000, 1980000, 2110000, 2170000, 20, 422000, 100}, diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h index eb9771d943..48bd701157 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h @@ -53,6 +53,12 @@ int get_nr_prach_info_from_index(uint8_t index, uint8_t *N_t_slot, uint8_t *N_dur); +uint8_t compute_nr_root_seq(NR_RACH_ConfigCommon_t *rach_config, + uint8_t nb_preambles, + uint8_t unpaired); + +int get_format0(uint8_t index, uint8_t unpaired); + uint16_t get_NCS(uint8_t index, uint16_t format, uint8_t restricted_set_config); typedef enum { diff --git a/openair2/LAYER2/NR_MAC_gNB/config.c b/openair2/LAYER2/NR_MAC_gNB/config.c index 0e3dccbe52..33bd0adc6c 100644 --- a/openair2/LAYER2/NR_MAC_gNB/config.c +++ b/openair2/LAYER2/NR_MAC_gNB/config.c @@ -154,6 +154,10 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm // PRACH configuration + uint8_t nb_preambles = 64; + if(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->totalNumberOfRA_Preambles != NULL) + nb_preambles = *scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->totalNumberOfRA_Preambles; + cfg->prach_config.prach_sequence_length.value = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.present; cfg->prach_config.prach_sequence_length.tl.tag = NFAPI_NR_CONFIG_PRACH_SEQUENCE_LENGTH_TAG; cfg->num_tlv++; @@ -164,7 +168,6 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm cfg->prach_config.prach_sub_c_spacing.value = scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing; cfg->prach_config.prach_sub_c_spacing.tl.tag = NFAPI_NR_CONFIG_PRACH_SUB_C_SPACING_TAG; cfg->num_tlv++; - cfg->prach_config.restricted_set_config.value = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig; cfg->prach_config.restricted_set_config.tl.tag = NFAPI_NR_CONFIG_RESTRICTED_SET_CONFIG_TAG; cfg->num_tlv++; @@ -203,6 +206,10 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm cfg->prach_config.num_prach_fd_occasions_list[i].prach_zero_corr_conf.value = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.zeroCorrelationZoneConfig; cfg->prach_config.num_prach_fd_occasions_list[i].prach_zero_corr_conf.tl.tag = NFAPI_NR_CONFIG_PRACH_ZERO_CORR_CONF_TAG; cfg->num_tlv++; + cfg->prach_config.num_prach_fd_occasions_list[i].num_root_sequences.value = compute_nr_root_seq(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup, + nb_preambles, frame_type); + cfg->prach_config.num_prach_fd_occasions_list[i].num_root_sequences.tl.tag = NFAPI_NR_CONFIG_NUM_ROOT_SEQUENCES_TAG; + cfg->num_tlv++; //cfg->prach_config.num_prach_fd_occasions_list[i].num_unused_root_sequences.value = ??? } diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf index 4564907fa8..db88115cb0 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf @@ -105,8 +105,8 @@ gNBs = #1,2,4,8,10,20,40,80 ra_ResponseWindow = 4; #ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR -#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen - ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3; +#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4; #oneHalf (0..15) 4,8,12,16,...60,64 ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; #ra_ContentionResolutionTimer @@ -114,16 +114,16 @@ gNBs = ra_ContentionResolutionTimer = 7; rsrp_ThresholdSSB = 19; #prach-RootSequenceIndex_PR -#0 = 839, 1 = 139 - prach_RootSequenceIndex_PR = 1; +#1 = 839, 2 = 139 + prach_RootSequenceIndex_PR = 2; prach_RootSequenceIndex = 1; # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex # msg1_SubcarrierSpacing = 1, - # restrictedSetConfig # 0=unrestricted, 1=restricted type A, 2=restricted type B restrictedSetConfig = 0, + # pusch-ConfigCommon (up to 16 elements) initialULBWPk2_0 = 2; initialULBWPmappingType_0 = 1 diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpx300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpx300.conf index 06aa4f6f9f..bd8c5740dd 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpx300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpx300.conf @@ -105,8 +105,8 @@ gNBs = #1,2,4,8,10,20,40,80 ra_ResponseWindow = 4; #ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR -#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen - ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3; +#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4; #oneHalf (0..15) 4,8,12,16,...60,64 ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; #ra_ContentionResolutionTimer @@ -114,8 +114,8 @@ gNBs = ra_ContentionResolutionTimer = 7; rsrp_ThresholdSSB = 19; #prach-RootSequenceIndex_PR -#0 = 839, 1 = 139 - prach_RootSequenceIndex_PR = 1; +#1 = 839, 2 = 139 + prach_RootSequenceIndex_PR = 2; prach_RootSequenceIndex = 1; # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex # From 456d1f9df9dbbb30520a36435c9bc0ccebdd1a95 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Sun, 16 Feb 2020 22:48:53 +0100 Subject: [PATCH 040/553] added scheduling of PRACH RX procedures in gNB and RU entities. Initialization of prach sequences added to nr_init.c --- executables/nr-gnb.c | 9 +- executables/nr-ru.c | 8 ++ openair1/PHY/INIT/nr_init.c | 6 + openair1/PHY/INIT/nr_init_ru.c | 5 + openair1/PHY/NR_TRANSPORT/nr_prach.c | 108 +++++++++++++++--- openair1/PHY/NR_TRANSPORT/nr_prach_common.c | 14 +-- openair1/PHY/NR_TRANSPORT/nr_transport.h | 15 ++- .../NR_TRANSPORT/nr_transport_proto_common.h | 4 +- openair1/PHY/NR_TRANSPORT/nr_ulsch.c | 4 + openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c | 4 +- openair1/PHY/defs_RU.h | 12 ++ openair1/PHY/defs_gNB.h | 5 +- openair1/SCHED_NR/fapi_nr_l1.c | 9 +- openair1/SCHED_NR/phy_procedures_nr_gNB.c | 40 +++++-- openair1/SCHED_NR/sched_nr.h | 1 + openair2/LAYER2/NR_MAC_gNB/config.c | 2 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 2 +- 17 files changed, 197 insertions(+), 51 deletions(-) diff --git a/executables/nr-gnb.c b/executables/nr-gnb.c index 7f85cabeb7..dab0d100be 100644 --- a/executables/nr-gnb.c +++ b/executables/nr-gnb.c @@ -47,7 +47,7 @@ #include "SCHED/sched_eNB.h" #include "SCHED_NR/sched_nr.h" #include "SCHED_NR/fapi_nr_l1.h" -#include "PHY/LTE_TRANSPORT/transport_proto.h" +#include "PHY/NR_TRANSPORT/nr_transport.h" #undef MALLOC //there are two conflicting definitions, so we better make sure we don't use it at all //#undef FRAME_LENGTH_COMPLEX_SAMPLES //there are two conflicting definitions, so we better make sure we don't use it at all @@ -205,6 +205,13 @@ static inline int rxtx(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int frame_t if (rx_slot_type == NR_UPLINK_SLOT || rx_slot_type == NR_MIXED_SLOT) { // UE-specific RX processing for subframe n // TODO: check if this is correct for PARALLEL_RU_L1_TRX_SPLIT + + // Do PRACH RU processing + int prach_id=find_nr_prach(gNB,frame_rx,slot_rx,0,SEARCH_EXIST); + if (prach_id>=0) { + L1_nr_prach_procedures(gNB,frame_rx,slot_rx,&gNB->prach_vars.list[prach_id].pdu); + gNB->prach_vars.list[prach_id].frame=-1; + } phy_procedures_gNB_uespec_RX(gNB, frame_rx, slot_rx); } diff --git a/executables/nr-ru.c b/executables/nr-ru.c index 5626e3383d..74ea8b7e07 100644 --- a/executables/nr-ru.c +++ b/executables/nr-ru.c @@ -67,6 +67,7 @@ #include "PHY/defs_nr_common.h" #include "PHY/phy_extern.h" #include "PHY/LTE_TRANSPORT/transport_proto.h" +#include "PHY/NR_TRANSPORT/nr_transport.h" #include "PHY/INIT/phy_init.h" #include "SCHED/sched_eNB.h" #include "SCHED_NR/sched_nr.h" @@ -1529,6 +1530,13 @@ void *ru_thread( void *param ) { for (aa=0;aanb_rx;aa++) memcpy((void*)RC.gNB[0]->common_vars.rxdataF[aa], (void*)ru->common.rxdataF[aa], fp->symbols_per_slot*fp->ofdm_symbol_size*sizeof(int32_t)); + + // Do PRACH RU processing + int prach_id=find_nr_prach_ru(ru,proc->frame_rx,proc->tti_rx,SEARCH_EXIST); + if (prach_id>=0) { + rx_nr_prach_ru(ru,ru->prach_list[prach_id].fmt,proc->frame_rx,proc->tti_rx); + free_nr_ru_prach_entry(ru,prach_id); + } } // At this point, all information for subframe has been received on FH interface diff --git a/openair1/PHY/INIT/nr_init.c b/openair1/PHY/INIT/nr_init.c index 3c93442c8d..d010ce65d9 100644 --- a/openair1/PHY/INIT/nr_init.c +++ b/openair1/PHY/INIT/nr_init.c @@ -26,6 +26,7 @@ #include "PHY/INIT/phy_init.h" #include "PHY/CODING/nrPolar_tools/nr_polar_pbch_defs.h" #include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto_common.h" /*#include "RadioResourceConfigCommonSIB.h" #include "RadioResourceConfigDedicated.h" #include "TDD-Config.h" @@ -164,6 +165,7 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, gNB->pusch_config.pusch_TimeDomainResourceAllocation[i]->mappingType = typeB; } + // /// Transport init necessary for NR synchro init_nr_transport(gNB); @@ -218,6 +220,8 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, */ prach_vars->prach_ifft = (int32_t *)malloc16_clear(1024*2*sizeof(int32_t)); + init_prach_list(gNB); + int N_RB_UL = cfg->carrier_config.ul_grid_size[cfg->ssb_config.scs_common.value].value; printf("Before ULSCH init : %p\n",gNB->dlsch[0][0]->harq_processes[0]); @@ -458,6 +462,8 @@ void nr_phy_config_request(NR_PHY_Config_t *phy_config) { return; } + compute_nr_prach_seq(gNB_config,0,RC.gNB[Mod_id]->X_u); + RC.gNB[Mod_id]->configured = 1; LOG_I(PHY,"gNB %d configured\n",Mod_id); } diff --git a/openair1/PHY/INIT/nr_init_ru.c b/openair1/PHY/INIT/nr_init_ru.c index ecf558d4ca..26c118040a 100644 --- a/openair1/PHY/INIT/nr_init_ru.c +++ b/openair1/PHY/INIT/nr_init_ru.c @@ -50,6 +50,9 @@ int nr_phy_init_RU(RU_t *ru) { cfg = &RC.gNB[n]->gNB_config; if (cfg->carrier_config.num_tx_ant.value > ru->nb_log_antennas) ru->nb_log_antennas = cfg->carrier_config.num_tx_ant.value; } + // copy configuration from gNB[0] in to RU, assume that all gNB instances sharing RU use the same configuration (at least the parts that are needed by the RU, numerology and PRACH) + memcpy((void*)&ru->config,(void*)&RC.gNB[0]->gNB_config,sizeof(ru->config)); + AssertFatal(ru->nb_log_antennas > 0 && ru->nb_log_antennas < 13, "ru->nb_log_antennas %d ! \n",ru->nb_log_antennas); if (ru->if_south <= REMOTE_IF5) { // this means REMOTE_IF5 or LOCAL_RF, so allocate memory for time-domain signals // Time-domain signals @@ -148,6 +151,8 @@ int nr_phy_init_RU(RU_t *ru) { ru->common.sync_corr = (uint32_t*)malloc16_clear( LTE_NUMBER_OF_SUBFRAMES_PER_FRAME*sizeof(uint32_t)*fp->samples_per_subframe_wCP ); + init_prach_ru_list(ru); + return(0); } diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index 822efba69d..6e16625737 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -39,6 +39,12 @@ extern uint16_t prach_root_sequence_map_abc[138]; extern uint16_t nr_du[838]; extern int16_t nr_ru[2*839]; +void init_prach_list(PHY_VARS_gNB *gNB) { + + AssertFatal(gNB!=NULL,"gNB is null\n"); + for (int i=0; iprach_vars.list[i].frame=-1; +} + int16_t find_nr_prach(PHY_VARS_gNB *gNB,int frame,int slot, int numRA, find_type_t type) { uint16_t i; @@ -63,9 +69,9 @@ void nr_fill_prach(PHY_VARS_gNB *gNB, int Slot, nfapi_nr_prach_pdu_t *prach_pdu) { - int prach_id = find_nr_prach(gNB,SFN,Slot,prach_pdu->num_ra,SEARCH_EXIST); + int prach_id = find_nr_prach(gNB,SFN,Slot,prach_pdu->num_ra,SEARCH_EXIST_OR_FREE); AssertFatal( (prach_id>=0) && (prach_idnum_ra,prach_id); + "illegal or no prach_id found!!! numRA %d prach_id %d\n",prach_pdu->num_ra,prach_id); gNB->prach_vars.list[prach_id].frame=SFN; gNB->prach_vars.list[prach_id].slot=Slot; @@ -73,20 +79,76 @@ void nr_fill_prach(PHY_VARS_gNB *gNB, } +void init_prach_ru_list(RU_t *ru) { + + AssertFatal(ru!=NULL,"ruis null\n"); + for (int i=0; iprach_list[i].frame=-1; + pthread_mutex_init(&ru->prach_list_mutex,NULL); + +} + +int16_t find_nr_prach_ru(RU_t *ru,int frame,int slot, find_type_t type) { + + uint16_t i; + int16_t first_free_index=-1; + + AssertFatal(ru!=NULL,"ru is null\n"); + pthread_mutex_lock(&ru->prach_list_mutex); + for (i=0; i %d.%d\n", frame,slot,i, + ru->prach_list[i].frame,ru->prach_list[i].slot); + if ((ru->prach_list[i].frame == frame) && + (ru->prach_list[i].slot == slot)) { + pthread_mutex_unlock(&ru->prach_list_mutex); + return i; + } + else if ((ru->prach_list[i].frame == -1) && (first_free_index==-1)) first_free_index=i; + } + pthread_mutex_unlock(&ru->prach_list_mutex); + if (type == SEARCH_EXIST) return -1; + + return first_free_index; +} + +void nr_fill_prach_ru(RU_t *ru, + int SFN, + int Slot, + nfapi_nr_prach_pdu_t *prach_pdu) { + + int prach_id = find_nr_prach_ru(ru,SFN,Slot,SEARCH_EXIST_OR_FREE); + AssertFatal( (prach_id>=0) && (prach_idprach_list_mutex); + ru->prach_list[prach_id].frame = SFN; + ru->prach_list[prach_id].slot = Slot; + ru->prach_list[prach_id].fmt = prach_pdu->prach_format; + pthread_mutex_unlock(&ru->prach_list_mutex); + +} + +void free_nr_ru_prach_entry(RU_t *ru, + int prach_id) { + + pthread_mutex_lock(&ru->prach_list_mutex); + ru->prach_list[prach_id].frame=-1; + pthread_mutex_unlock(&ru->prach_list_mutex); + +} + +const char *prachfmt[]={"A1","A2","A3","B1","B2","B3","B4","C0","C2"}; + void rx_nr_prach_ru(RU_t *ru, - nfapi_nr_prach_pdu_t *prach_pdu, + int prach_fmt, int frame, int slot) { AssertFatal(ru!=NULL,"ru is null\n"); int16_t **rxsigF=NULL; - NR_DL_FRAME_PARMS *fp=&ru->frame_parms; - - int frame_type = ru->config.cell_config.frame_duplex_type.value; + NR_DL_FRAME_PARMS *fp=ru->nr_frame_parms; int16_t *prach[ru->nb_rx]; - uint8_t prach_fmt = prach_pdu->prach_format; int prach_sequence_length = ru->config.prach_config.prach_sequence_length.value; int msg1_frequencystart = ru->config.prach_config.num_prach_fd_occasions_list[0].k1.value; @@ -104,6 +166,9 @@ void rx_nr_prach_ru(RU_t *ru, int16_t *prach2; if (prach_sequence_length == 0) { + LOG_D(PHY,"PRACH (ru %d) in %d.%d, format %d, msg1_frequencyStart %d\n", + ru->idx,frame,slot,prach_fmt,msg1_frequencystart); + AssertFatal(prach_fmt<4,"Illegal prach format %d for length 839\n",prach_fmt); switch (prach_fmt) { case 0: Ncp = 3168; @@ -124,7 +189,11 @@ void rx_nr_prach_ru(RU_t *ru, } } else { + LOG_D(PHY,"PRACH (ru %d) in %d.%d, format %s, msg1_frequencyStart %d\n", + ru->idx,frame,slot,prachfmt[prach_fmt],msg1_frequencystart); + switch (prach_fmt) { + AssertFatal(prach_fmt<4,"Illegal prach format %d for length 139 (combined formats not supported yet)\n",prach_fmt); case 0: //A1 Ncp = 288/(1<gNB_config.prach_config; NR_DL_FRAME_PARMS *fp; - lte_frame_type_t frame_type; uint16_t rootSequenceIndex; int numrootSequenceIndex; uint8_t restricted_set; @@ -455,10 +523,9 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, nb_rx = gNB->gNB_config.carrier_config.num_rx_ant.value; - frame_type = gNB->gNB_config.cell_config.frame_duplex_type.value; rootSequenceIndex = cfg->num_prach_fd_occasions_list[0].prach_root_sequence_index.value; numrootSequenceIndex = cfg->num_prach_fd_occasions_list[0].num_root_sequences.value; - NCS = cfg->num_prach_fd_occasions_list[0].prach_zero_corr_conf.value; + NCS = prach_pdu->num_cs;//cfg->num_prach_fd_occasions_list[0].prach_zero_corr_conf.value; int prach_sequence_length = cfg->prach_sequence_length.value; int msg1_frequencystart = cfg->num_prach_fd_occasions_list[0].k1.value; @@ -473,7 +540,7 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, uint8_t prach_fmt = prach_pdu->prach_format; uint16_t N_ZC = (prach_sequence_length==0)?839:139; - + LOG_D(PHY,"L1 PRACH RX: rooSequenceIndex %d, numRootSeqeuences %d, NCS %d, N_ZC %d \n", rootSequenceIndex,numrootSequenceIndex,NCS,N_ZC); prach_ifft = gNB->prach_vars.prach_ifft; prachF = gNB->prach_vars.prachF; @@ -501,6 +568,9 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, *max_preamble_energy=0; + *max_preamble_delay=0; + *max_preamble=0; + for (preamble_index=0 ; preamble_index<64 ; preamble_index++) { if (LOG_DEBUGFLAG(PRACH)){ @@ -510,7 +580,7 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, if (restricted_set == 0) { // This is the relative offset in the root sequence table (5.7.2-4 from 36.211) for the given preamble index preamble_offset = ((NCS==0)? preamble_index : (preamble_index/(N_ZC/NCS))); - + if (preamble_offset != preamble_offset_old) { preamble_offset_old = preamble_offset; new_dft = 1; @@ -540,13 +610,6 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, // current root depending on rootSequenceIndex int index = (rootSequenceIndex + preamble_offset) % N_ZC; - if (prach_fmt<4) { - // prach_root_sequence_map points to prach_root_sequence_map0_3 - DevAssert( index < sizeof(prach_root_sequence_map_0_3) / sizeof(prach_root_sequence_map_0_3[0]) ); - } else { - // prach_root_sequence_map points to prach_root_sequence_map4 - DevAssert( index < sizeof(prach_root_sequence_map_abc) / sizeof(prach_root_sequence_map_abc[0]) ); - } u = prach_root_sequence_map[index]; uint16_t n_group_ra = 0; @@ -595,10 +658,17 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, frame,subframe,preamble_index,NCS,N_ZC/NCS,preamble_offset,preamble_shift,en); } + LOG_D(PHY,"PRACH RX preamble_index %d, preamble_offset %d\n",preamble_index,preamble_offset); + + if (new_dft == 1) { new_dft = 0; Xu=(int16_t*)gNB->X_u[preamble_offset-first_nonzero_root_idx]; + + LOG_D(PHY,"PRACH RX new dft preamble_offset-first_nonzero_root_idx %d\n",preamble_index,preamble_offset-first_nonzero_root_idx); + + memset(prach_ifft,0,((N_ZC==839) ? 2048 : 256)*sizeof(int32_t)); diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c index 65da6fc49f..b55501cc84 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c @@ -100,7 +100,7 @@ void nr_fill_du(uint16_t N_ZC,uint16_t *prach_root_sequence_map) void compute_nr_prach_seq(nfapi_nr_config_request_scf_t *config, uint8_t fd_occasion, - uint32_t **X_u) + uint32_t X_u[64][839]) { // Compute DFT of x_u => X_u[k] = x_u(inv(u)*k)^* X_u[k] = exp(j\pi u*inv(u)*k*(inv(u)*k+1)/N_ZC) nfapi_nr_prach_config_t prach_config = config->prach_config; @@ -115,9 +115,9 @@ void compute_nr_prach_seq(nfapi_nr_config_request_scf_t *config, VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_UE_COMPUTE_PRACH, VCD_FUNCTION_IN); -#ifdef NR_PRACH_DEBUG - LOG_I(PHY,"compute_prach_seq: NCS_config %d, prach short sequence? %x\n",zeroCorrelationZoneConfig, prach_c); -#endif + + LOG_D(PHY,"compute_prach_seq: NCS_config %d, prach short sequence %x, num_Seqeuences %d, rootSequenceIndex %d\n",prach_config.num_prach_fd_occasions_list[fd_occasion].prach_zero_corr_conf.value, short_sequence, num_sequences, rootSequenceIndex); + N_ZC = (short_sequence) ? 139 : 839; @@ -133,9 +133,9 @@ void compute_nr_prach_seq(nfapi_nr_config_request_scf_t *config, } -#ifdef PRACH_DEBUG - LOG_I( PHY, "compute_prach_seq: done init prach_tables\n" ); -#endif + + LOG_D( PHY, "compute_prach_seq: done init prach_tables\n" ); + for (i=0; iharq_mask |= 1<harq_process_id[slot] = harq_pid; + ulsch->harq_processes[harq_pid]->frame=frame; + ulsch->harq_processes[harq_pid]->slot=slot; + ulsch->harq_processes[harq_pid]->handled= 0; + ulsch->harq_processes[harq_pid]->status= NR_ACTIVE; nfapi_nr_ul_config_ulsch_pdu *rel15_ul = &ulsch->harq_processes[harq_pid]->ulsch_pdu; LOG_D(PHY,"Initializing nFAPI for ULSCH, UE %d, harq_pid %d\n",ulsch_id,harq_pid); diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c index 872342cd5b..60dbf107e6 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c @@ -220,13 +220,13 @@ void clean_gNB_ulsch(NR_gNB_ULSCH_t *ulsch) /// Nfapi ULSCH PDU //nfapi_nr_ul_config_ulsch_pdu ulsch_pdu; ulsch->harq_processes[i]->frame=0; - ulsch->harq_processes[i]->subframe=0; + ulsch->harq_processes[i]->slot=0; ulsch->harq_processes[i]->round=0; ulsch->harq_processes[i]->TPC=0; ulsch->harq_processes[i]->mimo_mode=0; ulsch->harq_processes[i]->dci_alloc=0; ulsch->harq_processes[i]->rar_alloc=0; - ulsch->harq_processes[i]->status=0; + ulsch->harq_processes[i]->status=NR_SCH_IDLE; ulsch->harq_processes[i]->subframe_scheduling_flag=0; ulsch->harq_processes[i]->subframe_cba_scheduling_flag=0; ulsch->harq_processes[i]->phich_active=0; diff --git a/openair1/PHY/defs_RU.h b/openair1/PHY/defs_RU.h index 6d2b7db638..4cdb4bec76 100644 --- a/openair1/PHY/defs_RU.h +++ b/openair1/PHY/defs_RU.h @@ -189,6 +189,14 @@ typedef struct RU_feptx_t_s{ int index; }RU_feptx_t; +typedef struct { + int frame; + int slot; + int fmt; +} RU_PRACH_list_t; + +#define NUMBER_OF_NR_RU_PRACH_MAX 8 + typedef struct RU_proc_t_s { /// Pointer to associated RU descriptor struct RU_t_s *ru; @@ -582,6 +590,10 @@ typedef struct RU_t_s { int32_t *bw_list[NUMBER_OF_eNB_MAX+1]; /// beamforming weight vectors int32_t **beam_weights[NUMBER_OF_eNB_MAX+1][15]; + /// prach commands + RU_PRACH_list_t prach_list[NUMBER_OF_NR_RU_PRACH_MAX]; + /// mutex for prach_list access + pthread_mutex_t prach_list_mutex; /// received frequency-domain signal for PRACH (IF4p5 RRU) int16_t **prach_rxsigF; /// received frequency-domain signal for PRACH BR (IF4p5 RRU) diff --git a/openair1/PHY/defs_gNB.h b/openair1/PHY/defs_gNB.h index 4a78782f78..b930031aff 100644 --- a/openair1/PHY/defs_gNB.h +++ b/openair1/PHY/defs_gNB.h @@ -47,6 +47,7 @@ #define MAX_NUM_RU_PER_gNB MAX_NUM_RU_PER_eNB + typedef struct { uint32_t pbch_a; uint32_t pbch_a_interleaved; @@ -176,8 +177,8 @@ typedef struct { nfapi_nr_ul_config_ulsch_pdu ulsch_pdu; /// Frame where current HARQ round was sent uint32_t frame; - /// Subframe where current HARQ round was sent - uint32_t subframe; + /// Slot where current HARQ round was sent + uint32_t slot; /// Index of current HARQ round for this DLSCH uint8_t round; /// Last TPC command diff --git a/openair1/SCHED_NR/fapi_nr_l1.c b/openair1/SCHED_NR/fapi_nr_l1.c index 1f658f2306..354b32d0a0 100644 --- a/openair1/SCHED_NR/fapi_nr_l1.c +++ b/openair1/SCHED_NR/fapi_nr_l1.c @@ -31,6 +31,7 @@ */ #include "fapi_nr_l1.h" #include "PHY/NR_TRANSPORT/nr_transport_proto.h" +#include "PHY/NR_TRANSPORT/nr_transport.h" #include "PHY/NR_TRANSPORT/nr_dlsch.h" #include "PHY/NR_TRANSPORT/nr_dci.h" @@ -148,10 +149,11 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){ uint8_t number_ul_dci_pdu = (UL_dci_req==NULL) ? 0 : UL_dci_req->numPdus; uint8_t number_ul_tti_pdu = (UL_tti_req==NULL) ? 0 : UL_tti_req->n_pdus; - LOG_D(PHY,"NFAPI: Sched_INFO:SFN/SLOT:%04d%d DL_req:SFN/SLO:%04d%d:dl_pdu:%d tx_req:SFN/SLOT:%04d%d:pdus:%d;\n", + LOG_D(PHY,"NFAPI: Sched_INFO:SFN/SLOT:%04d%d DL_req:SFN/SLO:%04d%d:dl_pdu:%d tx_req:SFN/SLOT:%04d%d:pdus:%d;ul_dci %d ul_tti %d\n", frame,slot, DL_req->SFN,DL_req->Slot,number_dl_pdu, - TX_req->SFN,TX_req->Slot,TX_req->Number_of_PDUs); + TX_req->SFN,TX_req->Slot,TX_req->Number_of_PDUs, + number_ul_dci_pdu,number_ul_tti_pdu); int pdcch_received=0; gNB->num_pdsch_rnti=0; @@ -204,7 +206,7 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){ switch (UL_tti_req->pdus_list[i].pdu_type) { case NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE: LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE for %d.%d\n",frame,slot,UL_tti_req->SFN,UL_tti_req->Slot); - nr_fill_ulsch(gNB,frame,slot,&UL_tti_req->pdus_list[i].pusch_pdu); + nr_fill_ulsch(gNB,UL_tti_req->SFN,UL_tti_req->Slot,&UL_tti_req->pdus_list[i].pusch_pdu); break; case NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE: LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE for %d.%d\n",frame,slot,UL_tti_req->SFN,UL_tti_req->Slot); @@ -214,6 +216,7 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){ LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PRACH_PDU_TYPE for %d.%d\n",frame,slot,UL_tti_req->SFN,UL_tti_req->Slot); nfapi_nr_prach_pdu_t *prach_pdu = &UL_tti_req->pdus_list[i].prach_pdu; nr_fill_prach(gNB,UL_tti_req->SFN,UL_tti_req->Slot,prach_pdu); + nr_fill_prach_ru(gNB->RU_list[0],UL_tti_req->SFN,UL_tti_req->Slot,prach_pdu); break; } } diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index 75daf0d5ab..d3b393ad26 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -373,6 +373,7 @@ void phy_procedures_gNB_common_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) for(symbol = 0; symbol < NR_SYMBOLS_PER_SLOT; symbol++) { // nr_slot_fep_ul(gNB, symbol, proc->slot_rx, 0, 0); + for (aa = 0; aa < gNB->frame_parms.nb_antennas_rx; aa++) { nr_slot_fep_ul(&gNB->frame_parms, gNB->common_vars.rxdata[aa], @@ -391,21 +392,36 @@ void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) LOG_D(PHY,"phy_procedures_gNB_uespec_RX frame %d, slot %d\n",frame_rx,slot_rx); for (int ULSCH_id=0;ULSCH_idulsch[ULSCH_id]; + NR_gNB_ULSCH_t *ulsch = gNB->ulsch[ULSCH_id][0]; + int harq_pid; + NR_UL_gNB_HARQ_t *ulsch_harq; - if (ulsch->rnti > 0) { - uint8_t harq_pid = ulsch->harq_process_id[slot_rx]; - uint8_t symbol_start = ulsch->harq_processes[harq_pid]->ulsch_pdu.ulsch_pdu_rel15.start_symbol; - uint8_t symbol_end = symbol_start + ulsch->harq_processes[harq_pid]->ulsch_pdu.ulsch_pdu_rel15.number_symbols; + if ((ulsch) && + (ulsch->rnti > 0)) { + // for for an active HARQ process + for (harq_pid=0;harq_pidharq_processes[harq_pid]; + AssertFatal(ulsch_harq!=NULL,"harq_pid %d is not allocated\n",harq_pid); + if ((ulsch_harq->status == NR_ACTIVE) && + (ulsch_harq->frame == frame_rx) && + (ulsch_harq->slot == slot_rx) && + (ulsch_harq->handled == 0)){ + + + uint8_t symbol_start = ulsch_harq->ulsch_pdu.ulsch_pdu_rel15.start_symbol; + uint8_t symbol_end = symbol_start + ulsch_harq->ulsch_pdu.ulsch_pdu_rel15.number_symbols; - for(uint8_t symbol = symbol_start; symbol < symbol_end; symbol++) { - nr_rx_pusch(gNB, ULSCH_id, frame_rx, slot_rx, symbol, harq_pid); + for(uint8_t symbol = symbol_start; symbol < symbol_end; symbol++) { + nr_rx_pusch(gNB, ULSCH_id, frame_rx, slot_rx, symbol, harq_pid); + } + //LOG_M("rxdataF_comp.m","rxF_comp",gNB->pusch_vars[0]->rxdataF_comp[0],6900,1,1); + //LOG_M("rxdataF_ext.m","rxF_ext",gNB->pusch_vars[0]->rxdataF_ext[0],6900,1,1); + nr_ulsch_procedures(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); + nr_fill_rx_indication(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); // indicate SDU to MAC + nr_fill_crc_indication(gNB, frame_rx, slot_rx, ULSCH_id, 0); + break; + } } - //LOG_M("rxdataF_comp.m","rxF_comp",gNB->pusch_vars[0]->rxdataF_comp[0],6900,1,1); - //LOG_M("rxdataF_ext.m","rxF_ext",gNB->pusch_vars[0]->rxdataF_ext[0],6900,1,1); - nr_ulsch_procedures(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); - nr_fill_rx_indication(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); // indicate SDU to MAC - nr_fill_crc_indication(gNB, frame_rx, slot_rx, ULSCH_id, 0); } } } diff --git a/openair1/SCHED_NR/sched_nr.h b/openair1/SCHED_NR/sched_nr.h index 5f54539b71..b393e9566e 100644 --- a/openair1/SCHED_NR/sched_nr.h +++ b/openair1/SCHED_NR/sched_nr.h @@ -39,6 +39,7 @@ void nr_set_ssb_first_subcarrier(nfapi_nr_config_request_scf_t *cfg, NR_DL_FRAME void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB, int frame_tx, int slot_tx, int do_meas); void phy_procedures_gNB_common_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx); void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx); +void L1_nr_prach_procedures(PHY_VARS_gNB *gNB,int frame,int slot,nfapi_nr_prach_pdu_t *prach_pdu); void nr_common_signal_procedures (PHY_VARS_gNB *gNB,int frame, int slot); void nr_feptx_ofdm(RU_t *ru,int frame_tx,int tti_tx); void nr_feptx_ofdm_2thread(RU_t *ru,int frame_tx,int tti_tx); diff --git a/openair2/LAYER2/NR_MAC_gNB/config.c b/openair2/LAYER2/NR_MAC_gNB/config.c index 33bd0adc6c..acb86f411f 100644 --- a/openair2/LAYER2/NR_MAC_gNB/config.c +++ b/openair2/LAYER2/NR_MAC_gNB/config.c @@ -158,7 +158,7 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm if(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->totalNumberOfRA_Preambles != NULL) nb_preambles = *scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->totalNumberOfRA_Preambles; - cfg->prach_config.prach_sequence_length.value = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.present; + cfg->prach_config.prach_sequence_length.value = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.present-1; cfg->prach_config.prach_sequence_length.tl.tag = NFAPI_NR_CONFIG_PRACH_SEQUENCE_LENGTH_TAG; cfg->num_tlv++; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index caa7be91a2..d599bc6df7 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -501,7 +501,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, if (is_nr_UL_slot(cc->ServingCellConfigCommon,slot_rxP)) { - schedule_nr_prach(module_idP, frame_rxP, slot_rxP); + schedule_nr_prach(module_idP, (frame_rxP+1)&1023, slot_rxP); if (phy_test && slot_rxP==8){ nr_schedule_uss_ulsch_phytest(module_idP, frame_rxP, slot_rxP); From 3c4ac034a58af098364324dbb711d080810d48f1 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Mon, 17 Feb 2020 09:24:25 +0100 Subject: [PATCH 041/553] small fixes --- openair1/PHY/INIT/nr_init_ru.c | 1 + openair2/LAYER2/NR_MAC_gNB/config.c | 4 ++-- .../CONF/gnb.band257.tm1.32PRB.usrpx300.conf | 8 ++++---- .../CONF/gnb.band257.tm1.66PRB.usrpn300.conf | 8 ++++---- .../CONF/gnb.band78.tm1.217PRB.usrpn300.conf | 8 ++++---- .../CONF/gnb.band78.tm1.217PRB.usrpx300.conf | 8 ++++---- .../CONF/gnb.band78.tm1.273PRB.usrpn300.conf | 8 ++++---- 7 files changed, 23 insertions(+), 22 deletions(-) diff --git a/openair1/PHY/INIT/nr_init_ru.c b/openair1/PHY/INIT/nr_init_ru.c index 26c118040a..23ec577f67 100644 --- a/openair1/PHY/INIT/nr_init_ru.c +++ b/openair1/PHY/INIT/nr_init_ru.c @@ -22,6 +22,7 @@ #include "phy_init.h" #include "SCHED/sched_common.h" #include "PHY/phy_extern.h" +#include "PHY/NR_TRANSPORT/nr_transport.h" #include "SIMULATION/TOOLS/sim.h" /*#include "RadioResourceConfigCommonSIB.h" #include "RadioResourceConfigDedicated.h" diff --git a/openair2/LAYER2/NR_MAC_gNB/config.c b/openair2/LAYER2/NR_MAC_gNB/config.c index acb86f411f..6954bce497 100644 --- a/openair2/LAYER2/NR_MAC_gNB/config.c +++ b/openair2/LAYER2/NR_MAC_gNB/config.c @@ -213,10 +213,10 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm //cfg->prach_config.num_prach_fd_occasions_list[i].num_unused_root_sequences.value = ??? } - cfg->prach_config.ssb_per_rach.value = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->present; + cfg->prach_config.ssb_per_rach.value = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->present-1; cfg->prach_config.ssb_per_rach.tl.tag = NFAPI_NR_CONFIG_SSB_PER_RACH_TAG; cfg->num_tlv++; - + // SSB Table Configuration int scs_scaling = 1<<(cfg->ssb_config.scs_common.value); if (scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA < 600000) diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.32PRB.usrpx300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.32PRB.usrpx300.conf index 1363be3bce..d5bc492644 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.32PRB.usrpx300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.32PRB.usrpx300.conf @@ -105,8 +105,8 @@ gNBs = #1,2,4,8,10,20,40,80 ra_ResponseWindow = 4; #ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR -#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen - ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3; +#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4; #oneHalf (0..15) 4,8,12,16,...60,64 ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; #ra_ContentionResolutionTimer @@ -114,8 +114,8 @@ gNBs = ra_ContentionResolutionTimer = 7; rsrp_ThresholdSSB = 19; #prach-RootSequenceIndex_PR -#0 = 839, 1 = 139 - prach_RootSequenceIndex_PR = 1; +#1 = 839, 2 = 139 + prach_RootSequenceIndex_PR = 2; prach_RootSequenceIndex = 1; # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex # diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.66PRB.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.66PRB.usrpn300.conf index 1fbc8e30ef..93a6c7fbc9 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.66PRB.usrpn300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.66PRB.usrpn300.conf @@ -105,8 +105,8 @@ gNBs = #1,2,4,8,10,20,40,80 ra_ResponseWindow = 4; #ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR -#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen - ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3; +#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4; #oneHalf (0..15) 4,8,12,16,...60,64 ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; #ra_ContentionResolutionTimer @@ -114,8 +114,8 @@ gNBs = ra_ContentionResolutionTimer = 7; rsrp_ThresholdSSB = 19; #prach-RootSequenceIndex_PR -#0 = 839, 1 = 139 - prach_RootSequenceIndex_PR = 1; +#1 = 839, 2 = 139 + prach_RootSequenceIndex_PR = 2; prach_RootSequenceIndex = 1; # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex # diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpn300.conf index b82c455ef4..56233555c0 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpn300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpn300.conf @@ -105,8 +105,8 @@ gNBs = #1,2,4,8,10,20,40,80 ra_ResponseWindow = 4; #ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR -#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen - ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3; +#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4; #oneHalf (0..15) 4,8,12,16,...60,64 ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; #ra_ContentionResolutionTimer @@ -114,8 +114,8 @@ gNBs = ra_ContentionResolutionTimer = 7; rsrp_ThresholdSSB = 19; #prach-RootSequenceIndex_PR -#0 = 839, 1 = 139 - prach_RootSequenceIndex_PR = 1; +#1 = 839, 2 = 139 + prach_RootSequenceIndex_PR = 2; prach_RootSequenceIndex = 1; # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex # diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpx300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpx300.conf index 4cbec5b86e..ea89675006 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpx300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpx300.conf @@ -105,8 +105,8 @@ gNBs = #1,2,4,8,10,20,40,80 ra_ResponseWindow = 4; #ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR -#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen - ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3; +#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4; #oneHalf (0..15) 4,8,12,16,...60,64 ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; #ra_ContentionResolutionTimer @@ -114,8 +114,8 @@ gNBs = ra_ContentionResolutionTimer = 7; rsrp_ThresholdSSB = 19; #prach-RootSequenceIndex_PR -#0 = 839, 1 = 139 - prach_RootSequenceIndex_PR = 1; +#1 = 839, 2 = 139 + prach_RootSequenceIndex_PR = 2; prach_RootSequenceIndex = 1; # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex # diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.273PRB.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.273PRB.usrpn300.conf index f5e2298a99..5c84d9879b 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.273PRB.usrpn300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.273PRB.usrpn300.conf @@ -105,8 +105,8 @@ gNBs = #1,2,4,8,10,20,40,80 ra_ResponseWindow = 4; #ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR -#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen - ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3; +#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4; #oneHalf (0..15) 4,8,12,16,...60,64 ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; #ra_ContentionResolutionTimer @@ -114,8 +114,8 @@ gNBs = ra_ContentionResolutionTimer = 7; rsrp_ThresholdSSB = 19; #prach-RootSequenceIndex_PR -#0 = 839, 1 = 139 - prach_RootSequenceIndex_PR = 1; +#1 = 839, 2 = 139 + prach_RootSequenceIndex_PR = 2; prach_RootSequenceIndex = 1; # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex # From fd81b1ec892e5b30051280084504d21c6c448cce Mon Sep 17 00:00:00 2001 From: Cedric Roux Date: Mon, 17 Feb 2020 12:02:28 +0100 Subject: [PATCH 042/553] fix --- openair2/RRC/NR/rrc_gNB_nsa.c | 1 + 1 file changed, 1 insertion(+) diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c index c938b968b6..18fc3d7e7c 100644 --- a/openair2/RRC/NR/rrc_gNB_nsa.c +++ b/openair2/RRC/NR/rrc_gNB_nsa.c @@ -131,6 +131,7 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_ NR_CG_Config_t *CG_Config = calloc(1,sizeof(*CG_Config)); memset((void*)CG_Config,0,sizeof(*CG_Config)); //int CG_Config_size = generate_CG_Config(rrc,CG_Config,ue_context_p->ue_context.reconfig,ue_context_p->ue_context.rb_config); + generate_CG_Config(rrc,CG_Config,ue_context_p->ue_context.reconfig,ue_context_p->ue_context.rb_config); //X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).rrc_buffer_size = CG_Config_size; //Need to verify correct value for the buffer_size // Send to X2 entity to transport to MeNB From bb3bee9f23b2f2a61230bc23504d31621e51e350 Mon Sep 17 00:00:00 2001 From: Cedric Roux Date: Mon, 17 Feb 2020 12:22:19 +0100 Subject: [PATCH 043/553] fix dftlen computation --- openair1/PHY/NR_TRANSPORT/nr_prach.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index 6e16625737..578e1d8726 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -278,8 +278,10 @@ void rx_nr_prach_ru(RU_t *ru, //50 MHz @ 61.44 Ms/s prach2 = prach[aa] + (Ncp<<2); if (prach_sequence_length == 0) { - if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) + if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) { + dftlen=49152; dft49152(prach2,rxsigF[aa],1); + } if (prach_fmt == 1 || prach_fmt == 2) { dft49152(prach2+98304,rxsigF[aa]+98304,1); reps++; @@ -290,11 +292,13 @@ void rx_nr_prach_ru(RU_t *ru, reps+=2; } if (prach_fmt == 3) { + dftlen=12288; for (int i=0;i<4;i++) dft12288(prach2+(i*12288*2),rxsigF[aa]+(i*12288*2),1); reps=4; } } else { + dftlen=2048; dft2048(prach2,rxsigF[aa],1); if (prach_fmt != 7) { // !=C0 dft2048(prach2+4096,rxsigF[aa]+4096,1); @@ -321,6 +325,7 @@ void rx_nr_prach_ru(RU_t *ru, prach2 = prach[aa] + (3*Ncp); AssertFatal(fp->N_RB_UL <= 107,"cannot do 108..136 PRBs with 3/4 sampling\n"); if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) { + dftlen=36864; dft36864(prach2,rxsigF[aa],1); reps++; } @@ -334,10 +339,12 @@ void rx_nr_prach_ru(RU_t *ru, reps+=2; } if (prach_fmt == 3) { + dftlen=9216; for (int i=0;i<4;i++) dft9216(prach2+(i*9216*2),rxsigF[aa]+(i*9216*2),1); reps=4; } } else { + dftlen=1536; dft1536(prach2,rxsigF[aa],1); if (prach_fmt != 0xc0) { dft1536(prach2+3072,rxsigF[aa]+3072,1); @@ -364,12 +371,13 @@ void rx_nr_prach_ru(RU_t *ru, else if (fp->N_RB_UL <= 273) { if (fp->threequarter_fs==0) { prach2 = prach[aa] + (Ncp<<3); - dftlen=98304; //80,90,100 MHz @ 122.88 Ms/s if (prach_sequence_length == 0) { - if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) + if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) { + dftlen=98304; dft98304(prach2,rxsigF[aa],1); + } if (prach_fmt == 1 || prach_fmt == 2) { dft98304(prach2+196608,rxsigF[aa]+196608,1); reps++; @@ -380,9 +388,9 @@ void rx_nr_prach_ru(RU_t *ru, reps+=2; } if (prach_fmt == 3) { + dftlen=24576; for (int i=0;i<4;i++) dft24576(prach2+(i*2*24576),rxsigF[aa]+(i*2*24576),1); reps=4; - dftlen=24576; } } else { @@ -412,9 +420,9 @@ void rx_nr_prach_ru(RU_t *ru, AssertFatal(fp->N_RB_UL <= 217,"cannot do more than 217 PRBs with 3/4 sampling\n"); prach2 = prach[aa] + (6*Ncp); // 80 MHz @ 92.16 Ms/s - dftlen=73728; if (prach_sequence_length == 0) { if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) { + dftlen=73728; dft73728(prach2,rxsigF[aa],1); reps++; } @@ -423,9 +431,9 @@ void rx_nr_prach_ru(RU_t *ru, reps++; } if (prach_fmt == 3) { + dftlen=18432; for (int i=0;i<4;i++) dft18432(prach2+(i*2*18432),rxsigF[aa]+(i*2*18432),1); reps=4; - dftlen=18432; } } else { dftlen=3072; From b12ca2eba1d671a8ec841bcc12ac0a73f000ace8 Mon Sep 17 00:00:00 2001 From: Cedric Roux Date: Mon, 17 Feb 2020 12:43:11 +0100 Subject: [PATCH 044/553] fix prach2 value --- openair1/PHY/NR_TRANSPORT/nr_prach.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index 578e1d8726..3a90bd312b 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -321,8 +321,8 @@ void rx_nr_prach_ru(RU_t *ru, } } else { // 40 MHz @ 46.08 Ms/s + prach2 = prach[aa] + (3*Ncp); if (prach_sequence_length == 0) { - prach2 = prach[aa] + (3*Ncp); AssertFatal(fp->N_RB_UL <= 107,"cannot do 108..136 PRBs with 3/4 sampling\n"); if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) { dftlen=36864; From 844da7953136773f72ece364cd9b9d2124046786 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Mon, 17 Feb 2020 14:19:42 +0100 Subject: [PATCH 045/553] added handling for N_TA_OFFSET computation and changed some use of FAPI configuration in RU (used ru->config instead of ru->gNB_list[0]->config) --- executables/nr-ru.c | 100 ++++++++++++++++++++++++--------- openair1/PHY/INIT/nr_init_ru.c | 3 +- 2 files changed, 73 insertions(+), 30 deletions(-) diff --git a/executables/nr-ru.c b/executables/nr-ru.c index 74ea8b7e07..4a2b22331b 100644 --- a/executables/nr-ru.c +++ b/executables/nr-ru.c @@ -307,7 +307,7 @@ void fh_if5_south_out(RU_t *ru, int frame, int slot, uint64_t timestamp) // southbound IF4p5 fronthaul void fh_if4p5_south_out(RU_t *ru, int frame, int slot, uint64_t timestamp) { - nfapi_nr_config_request_scf_t *cfg = &ru->gNB_list[0]->gNB_config; + nfapi_nr_config_request_scf_t *cfg = &ru->config; if (ru == RC.ru[0]) VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_TRX_TST, ru->proc.timestamp_tx&0xffffffff ); LOG_D(PHY,"Sending IF4p5 for frame %d subframe %d\n",ru->proc.frame_tx,ru->proc.tti_tx); @@ -516,7 +516,7 @@ void fh_if5_north_asynch_in(RU_t *ru,int *frame,int *slot) { void fh_if4p5_north_asynch_in(RU_t *ru,int *frame,int *slot) { NR_DL_FRAME_PARMS *fp = ru->nr_frame_parms; - nfapi_nr_config_request_scf_t *cfg = &ru->gNB_list[0]->gNB_config; + nfapi_nr_config_request_scf_t *cfg = &ru->config; RU_proc_t *proc = &ru->proc; uint16_t packet_type; uint32_t symbol_number,symbol_mask,symbol_mask_full=0; @@ -711,7 +711,7 @@ void rx_rf(RU_t *ru,int *frame,int *slot) { void tx_rf(RU_t *ru,int frame,int slot, uint64_t timestamp) { RU_proc_t *proc = &ru->proc; NR_DL_FRAME_PARMS *fp = ru->nr_frame_parms; - nfapi_nr_config_request_scf_t *cfg = &ru->gNB_list[0]->gNB_config; + nfapi_nr_config_request_scf_t *cfg = &ru->config; void *txp[ru->nb_tx]; unsigned int txs; int i,txsymb; @@ -798,7 +798,7 @@ void *ru_thread_asynch_rxtx( void *param ) { static int ru_thread_asynch_rxtx_status; RU_t *ru = (RU_t *)param; RU_proc_t *proc = &ru->proc; - nfapi_nr_config_request_scf_t *cfg = &ru->gNB_list[0]->gNB_config; + nfapi_nr_config_request_scf_t *cfg = &ru->config; int slot=0, frame=0; // wait for top-level synchronization and do one acquisition to get timestamp for setting frame/subframe wait_sync("ru_thread_asynch_rxtx"); @@ -1043,10 +1043,10 @@ int wakeup_prach_ru(RU_t *ru) { void fill_rf_config(RU_t *ru, char *rf_config_file) { int i; NR_DL_FRAME_PARMS *fp = ru->nr_frame_parms; - nfapi_nr_config_request_scf_t *gNB_config = &ru->gNB_list[0]->gNB_config; //tmp index + nfapi_nr_config_request_scf_t *config = &ru->config; //tmp index openair0_config_t *cfg = &ru->openair0_cfg; - int mu = gNB_config->ssb_config.scs_common.value; - int N_RB = gNB_config->carrier_config.dl_grid_size[gNB_config->ssb_config.scs_common.value].value; + int mu = config->ssb_config.scs_common.value; + int N_RB = config->carrier_config.dl_grid_size[config->ssb_config.scs_common.value].value; if (mu == NR_MU_0) { //or if LTE if(N_RB == 100) { @@ -1131,7 +1131,7 @@ void fill_rf_config(RU_t *ru, char *rf_config_file) { AssertFatal(0 == 1,"Numerology %d not supported for the moment\n",mu); } - if (gNB_config->cell_config.frame_duplex_type.value==TDD) + if (config->cell_config.frame_duplex_type.value==TDD) cfg->duplex_mode = duplex_mode_TDD; else //FDD cfg->duplex_mode = duplex_mode_FDD; @@ -1170,7 +1170,7 @@ int setup_RU_buffers(RU_t *ru) { int card,ant; //uint16_t N_TA_offset = 0; NR_DL_FRAME_PARMS *frame_parms; - //nfapi_nr_config_request_t *gNB_config = ru->gNB_list[0]->gNB_config; //tmp index + nfapi_nr_config_request_scf_t *config = &ru->config; if (ru) { frame_parms = ru->nr_frame_parms; @@ -1179,12 +1179,54 @@ int setup_RU_buffers(RU_t *ru) { printf("ru pointer is NULL\n"); return(-1); } + int mu = config->ssb_config.scs_common.value; + int N_RB = config->carrier_config.dl_grid_size[config->ssb_config.scs_common.value].value; - /* if (frame_parms->frame_type == TDD) { - if (frame_parms->N_RB_DL == 100) ru->N_TA_offset = 624; - else if (frame_parms->N_RB_DL == 50) ru->N_TA_offset = 624/2; - else if (frame_parms->N_RB_DL == 25) ru->N_TA_offset = 624/4; - } */ + + if (config->cell_config.frame_duplex_type.value == TDD) { + int N_TA_offset = config->carrier_config.uplink_frequency.value < 6000000 ? 400 : 431; // reference samples for 25600Tc @ 30.72 Ms/s for FR1, same @ 61.44 Ms/s for FR2 + + double factor=1; + + switch (mu) { + case 0: //15 kHz scs + AssertFatal(N_TA_offset == 400,"scs_common 15kHz only for FR1\n"); + if (N_RB <= 25) factor = .25; // 7.68 Ms/s + else if (N_RB <=50) factor = .5; // 15.36 Ms/s + else if (N_RB <=75) factor = 1.0; // 30.72 Ms/s + else if (N_RB <=100) factor = 1.0; // 30.72 Ms/s + else AssertFatal(1==0,"Too many PRBS for mu=0\n"); + break; + case 1: //30 kHz sc + AssertFatal(N_TA_offset == 400,"scs_common 30kHz only for FR1\n"); + if (N_RB <= 106) factor = 2.0; // 61.44 Ms/s + else if (N_RB <= 275) factor = 4.0; // 122.88 Ms/s + break; + case 2: //60 kHz scs + AssertFatal(1==0,"scs_common should not be 60 kHz\n"); + break; + case 3: //120 kHz scs + AssertFatal(N_TA_offset == 431,"scs_common 120kHz only for FR2\n"); + break; + case 4: //240 kHz scs + AssertFatal(1==0,"scs_common should not be 60 kHz\n"); + if (N_RB <= 32) factor = 1.0; // 61.44 Ms/s + else if (N_RB <= 66) factor = 2.0; // 122.88 Ms/s + else AssertFatal(1==0,"N_RB %d is too big for curretn FR2 implementation\n",N_RB); + break; + + if (N_RB == 100) ru->N_TA_offset = 624; + else if (N_RB == 50) ru->N_TA_offset = 624/2; + else if (N_RB == 25) ru->N_TA_offset = 624/4; + } + if (frame_parms->threequarter_fs == 1) factor = factor*.75; + ru->N_TA_offset = (int)(N_TA_offset * factor); + LOG_I(PHY,"RU %d Setting N_TA_offset to %d samples (factor %f, UL Freq %d, N_RB %d)\n",ru->idx,ru->N_TA_offset,factor, + config->carrier_config.uplink_frequency.value, N_RB); + } + else ru->N_TA_offset = 0; + + if (ru->openair0_cfg.mmapped_dma == 1) { // replace RX signal buffers with mmaped HW versions for (i=0; inb_rx; i++) { @@ -1397,7 +1439,7 @@ void *ru_thread( void *param ) { int i = 0; int aa; - nfapi_nr_config_request_scf_t *cfg = &ru->gNB_list[0]->gNB_config; + nfapi_nr_config_request_scf_t *cfg = &ru->config; // set default return value ru_thread_status = 0; @@ -1409,7 +1451,7 @@ void *ru_thread( void *param ) { if(emulate_rf) { fill_rf_config(ru,ru->rf_config_file); - nr_init_frame_parms(&ru->gNB_list[0]->gNB_config, fp); + nr_init_frame_parms(&ru->config, fp); nr_dump_frame_parms(fp); nr_phy_init_RU(ru); @@ -1429,8 +1471,10 @@ void *ru_thread( void *param ) { AssertFatal(ret==0,"Cannot connect to remote radio\n"); } + memcpy((void*)&ru->config,(void*)&RC.gNB[0]->gNB_config,sizeof(ru->config)); + if (ru->if_south == LOCAL_RF) { // configure RF parameters only - nr_init_frame_parms(&ru->gNB_list[0]->gNB_config, fp); + nr_init_frame_parms(&ru->config, fp); nr_dump_frame_parms(fp); fill_rf_config(ru,ru->rf_config_file); nr_phy_init_RU(ru); @@ -1907,7 +1951,7 @@ void configure_ru(int idx, RU_t *ru = RC.ru[idx]; RRU_config_t *config = (RRU_config_t *)arg; RRU_capabilities_t *capabilities = (RRU_capabilities_t *)arg; - nfapi_nr_config_request_scf_t *gNB_config = &ru->gNB_list[0]->gNB_config; + nfapi_nr_config_request_scf_t *cfg = &ru->config; int ret; LOG_I(PHY, "Received capabilities from RRU %d\n",idx); @@ -1930,15 +1974,15 @@ void configure_ru(int idx, //config->tdd_config_S[0] = ru->nr_frame_parms->tdd_config_S; config->att_tx[0] = ru->att_tx; config->att_rx[0] = ru->att_rx; - config->N_RB_DL[0] = gNB_config->carrier_config.dl_grid_size[gNB_config->ssb_config.scs_common.value].value; - config->N_RB_UL[0] = gNB_config->carrier_config.dl_grid_size[gNB_config->ssb_config.scs_common.value].value; + config->N_RB_DL[0] = cfg->carrier_config.dl_grid_size[cfg->ssb_config.scs_common.value].value; + config->N_RB_UL[0] = cfg->carrier_config.dl_grid_size[cfg->ssb_config.scs_common.value].value; config->threequarter_fs[0] = ru->nr_frame_parms->threequarter_fs; /* if (ru->if_south==REMOTE_IF4p5) { config->prach_FreqOffset[0] = ru->nr_frame_parms->prach_config_common.prach_ConfigInfo.prach_FreqOffset; config->prach_ConfigIndex[0] = ru->nr_frame_parms->prach_config_common.prach_ConfigInfo.prach_ConfigIndex; LOG_I(PHY,"REMOTE_IF4p5: prach_FrequOffset %d, prach_ConfigIndex %d\n", config->prach_FreqOffset[0],config->prach_ConfigIndex[0]);*/ - nr_init_frame_parms(&ru->gNB_list[0]->gNB_config, ru->nr_frame_parms); + nr_init_frame_parms(&ru->config, ru->nr_frame_parms); nr_phy_init_RU(ru); } @@ -1946,23 +1990,23 @@ void configure_rru(int idx, void *arg) { RRU_config_t *config = (RRU_config_t *)arg; RU_t *ru = RC.ru[idx]; - nfapi_nr_config_request_scf_t *gNB_config = &ru->gNB_list[0]->gNB_config; + nfapi_nr_config_request_scf_t *cfg = &ru->config; ru->nr_frame_parms->nr_band = config->band_list[0]; ru->nr_frame_parms->dl_CarrierFreq = config->tx_freq[0]; ru->nr_frame_parms->ul_CarrierFreq = config->rx_freq[0]; if (ru->nr_frame_parms->dl_CarrierFreq == ru->nr_frame_parms->ul_CarrierFreq) { - gNB_config->cell_config.frame_duplex_type.value = TDD; + cfg->cell_config.frame_duplex_type.value = TDD; //ru->nr_frame_parms->tdd_config = config->tdd_config[0]; //ru->nr_frame_parms->tdd_config_S = config->tdd_config_S[0]; } else - gNB_config->cell_config.frame_duplex_type.value = FDD; + cfg->cell_config.frame_duplex_type.value = FDD; ru->att_tx = config->att_tx[0]; ru->att_rx = config->att_rx[0]; - int mu = gNB_config->ssb_config.scs_common.value; - gNB_config->carrier_config.dl_grid_size[mu].value = config->N_RB_DL[0]; - gNB_config->carrier_config.dl_grid_size[mu].value = config->N_RB_UL[0]; + int mu = cfg->ssb_config.scs_common.value; + cfg->carrier_config.dl_grid_size[mu].value = config->N_RB_DL[0]; + cfg->carrier_config.dl_grid_size[mu].value = config->N_RB_UL[0]; ru->nr_frame_parms->threequarter_fs = config->threequarter_fs[0]; //ru->nr_frame_parms->pdsch_config_common.referenceSignalPower = ru->max_pdschReferenceSignalPower-config->att_tx[0]; @@ -1977,7 +2021,7 @@ void configure_rru(int idx, } fill_rf_config(ru,ru->rf_config_file); - nr_init_frame_parms(&ru->gNB_list[0]->gNB_config, ru->nr_frame_parms); + nr_init_frame_parms(&ru->config, ru->nr_frame_parms); nr_phy_init_RU(ru); } diff --git a/openair1/PHY/INIT/nr_init_ru.c b/openair1/PHY/INIT/nr_init_ru.c index 26c118040a..b6b1626c4b 100644 --- a/openair1/PHY/INIT/nr_init_ru.c +++ b/openair1/PHY/INIT/nr_init_ru.c @@ -47,11 +47,10 @@ int nr_phy_init_RU(RU_t *ru) { nfapi_nr_config_request_scf_t *cfg; ru->nb_log_antennas=0; for (int n=0;ngNB_config; + cfg = &ru->config; if (cfg->carrier_config.num_tx_ant.value > ru->nb_log_antennas) ru->nb_log_antennas = cfg->carrier_config.num_tx_ant.value; } // copy configuration from gNB[0] in to RU, assume that all gNB instances sharing RU use the same configuration (at least the parts that are needed by the RU, numerology and PRACH) - memcpy((void*)&ru->config,(void*)&RC.gNB[0]->gNB_config,sizeof(ru->config)); AssertFatal(ru->nb_log_antennas > 0 && ru->nb_log_antennas < 13, "ru->nb_log_antennas %d ! \n",ru->nb_log_antennas); if (ru->if_south <= REMOTE_IF5) { // this means REMOTE_IF5 or LOCAL_RF, so allocate memory for time-domain signals From 87a019a114d7e54f6e3c7264a0929f8d1b78d2ed Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Mon, 17 Feb 2020 16:09:41 +0100 Subject: [PATCH 046/553] bug fixing in nr_rx_prach_ru --- openair1/PHY/NR_TRANSPORT/nr_prach.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index 3a90bd312b..5384514e46 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -256,7 +256,7 @@ void rx_nr_prach_ru(RU_t *ru, int n_ra_prb = msg1_frequencystart; int k = (12*n_ra_prb) - 6*fp->N_RB_UL; - int N_ZC = (prach_fmt<4)?839:139; + int N_ZC = (prach_sequence_length==0)?839:139; if (k<0) k+=(fp->ofdm_symbol_size); @@ -315,7 +315,7 @@ void rx_nr_prach_ru(RU_t *ru, reps+=2; } if (prach_fmt == 6) { - for (int i=6;i<11;i++) dft2048(prach2+(4096*i),rxsigF[aa]+(4096*i),1); + for (int i=6;i<12;i++) dft2048(prach2+(4096*i),rxsigF[aa]+(4096*i),1); reps+=6; } } @@ -346,23 +346,23 @@ void rx_nr_prach_ru(RU_t *ru, } else { dftlen=1536; dft1536(prach2,rxsigF[aa],1); - if (prach_fmt != 0xc0) { + if (prach_fmt != 7) { dft1536(prach2+3072,rxsigF[aa]+3072,1); reps++; } - if (prach_fmt == 0xa2 || prach_fmt == 0xa3 || prach_fmt == 0xb2 || prach_fmt == 0xb3 || prach_fmt == 0xb4 || prach_fmt == 0xc2) { + if (prach_fmt == 1 || prach_fmt == 2 || prach_fmt == 4 || prach_fmt == 5 || prach_fmt == 6 || prach_fmt == 8) { dft1536(prach2+3072*2,rxsigF[aa]+3072*2,1); dft1536(prach2+3072*3,rxsigF[aa]+3072*3,1); reps+=2; } - if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xB4) { + if (prach_fmt == 2 || prach_fmt == 5 || prach_fmt == 6) { dft1536(prach2+3072*4,rxsigF[aa]+3072*4,1); dft1536(prach2+3072*5,rxsigF[aa]+3072*5,1); reps+=2; } - if (prach_fmt == 0xB4) { - for (int i=6;i<11;i++) dft1536(prach2+(3072*i),rxsigF[aa]+(3072*i),1); + if (prach_fmt == 6) { + for (int i=6;i<12;i++) dft1536(prach2+(3072*i),rxsigF[aa]+(3072*i),1); reps+=6; } } // short format @@ -412,7 +412,7 @@ void rx_nr_prach_ru(RU_t *ru, reps+=2; } if (prach_fmt == 6) { - for (int i=6;i<11;i++) dft4096(prach2+(8192*i),rxsigF[aa]+(8192*i),1); + for (int i=6;i<12;i++) dft4096(prach2+(8192*i),rxsigF[aa]+(8192*i),1); reps+=6; } } @@ -454,7 +454,7 @@ void rx_nr_prach_ru(RU_t *ru, reps+=2; } if (prach_fmt == 6) { - for (int i=6;i<11;i++) dft3072(prach2+(6144*i),rxsigF[aa]+(6144*i),1); + for (int i=6;i<12;i++) dft3072(prach2+(6144*i),rxsigF[aa]+(6144*i),1); reps+=6; } } From c46615dc8d4da61b802c366caecad92b91ebdf61 Mon Sep 17 00:00:00 2001 From: Cedric Roux Date: Mon, 17 Feb 2020 17:47:10 +0100 Subject: [PATCH 047/553] fix: add cast to int32_t before mul for prach_ifft_tmp --- openair1/PHY/NR_TRANSPORT/nr_prach.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index 5384514e46..b28e3b5774 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -700,13 +700,13 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, idft1024(prachF,prach_ifft_tmp,1); // compute energy and accumulate over receive antennas for (i=0;i<2048;i++) - prach_ifft[i] += (prach_ifft_tmp[i<<1]*prach_ifft_tmp[i<<1] + prach_ifft_tmp[1+(i<<1)]*prach_ifft_tmp[1+(i<<1)])>>10; + prach_ifft[i] += ((int32_t)prach_ifft_tmp[i<<1]*(int32_t)prach_ifft_tmp[i<<1] + (int32_t)prach_ifft_tmp[1+(i<<1)]*(int32_t)prach_ifft_tmp[1+(i<<1)])>>10; } else { idft256(prachF,prach_ifft_tmp,1); log2_ifft_size = 8; // compute energy and accumulate over receive antennas and repetitions for BR for (i=0;i<256;i++) - prach_ifft[i] += (prach_ifft_tmp[i<<1]*prach_ifft_tmp[(i<<1)] + prach_ifft_tmp[1+(i<<1)]*prach_ifft_tmp[1+(i<<1)])>>10; + prach_ifft[i] += ((int32_t)prach_ifft_tmp[i<<1]*(int32_t)prach_ifft_tmp[(i<<1)] + (int32_t)prach_ifft_tmp[1+(i<<1)]*(int32_t)prach_ifft_tmp[1+(i<<1)])>>10; } if (LOG_DUMPFLAG(PRACH)) { From 5fa07571ecdef295c6f82d0b0c566701f8968f86 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Mon, 17 Feb 2020 18:09:47 +0100 Subject: [PATCH 048/553] N_ZC -> dftlen in nr_prach.c:nr_rx_prach_ru() --- openair1/PHY/NR_TRANSPORT/nr_prach.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index 5384514e46..885c97599b 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -470,7 +470,7 @@ void rx_nr_prach_ru(RU_t *ru, for (int j=0;j Date: Tue, 18 Feb 2020 10:26:24 +0100 Subject: [PATCH 049/553] fix: use dftlen instead of N_ZC --- openair1/PHY/NR_TRANSPORT/nr_prach.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index b28e3b5774..9f9bb4694a 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -470,7 +470,7 @@ void rx_nr_prach_ru(RU_t *ru, for (int j=0;j Date: Tue, 18 Feb 2020 14:57:14 +0100 Subject: [PATCH 050/553] prach config common in UE --- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h | 2 + openair2/LAYER2/NR_MAC_UE/config_ue.c | 62 +++++++++++++++++-- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 2 - 3 files changed, 60 insertions(+), 6 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h index 48bd701157..ad62eb6bba 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h @@ -36,6 +36,8 @@ uint16_t config_bandwidth(int mu, int nb_rb, int nr_band); +void get_band(uint64_t downlink_frequency, uint16_t *current_band, int32_t *current_offset, lte_frame_type_t *current_type); + uint64_t from_nrarfcn(int nr_bandP, uint8_t scs_index, uint32_t dl_nrarfcn); uint32_t to_nrarfcn(int nr_bandP, uint64_t dl_CarrierFreq, uint8_t scs_index, uint32_t bw); diff --git a/openair2/LAYER2/NR_MAC_UE/config_ue.c b/openair2/LAYER2/NR_MAC_UE/config_ue.c index 6250b53dd3..1402bce161 100755 --- a/openair2/LAYER2/NR_MAC_UE/config_ue.c +++ b/openair2/LAYER2/NR_MAC_UE/config_ue.c @@ -32,9 +32,7 @@ //#include "mac_defs.h" #include "NR_MAC_UE/mac_proto.h" - #include "NR_MAC-CellGroupConfig.h" - #include "LAYER2/NR_MAC_COMMON/nr_mac_common.h" #include "SCHED_NR/phy_frame_config_nr.h" @@ -203,12 +201,20 @@ void config_common_ue(NR_UE_MAC_INST_t *mac, } } + lte_frame_type_t frame_type; + uint16_t band; + int32_t offset; + + get_band((cfg->carrier_config.dl_frequency)*1000, + &band, + &offset, + &frame_type); + // cell config cfg->cell_config.phy_cell_id = *scc->physCellId; - cfg->cell_config.frame_duplex_type = 1; - + cfg->cell_config.frame_duplex_type = frame_type; // SSB config cfg->ssb_config.ss_pbch_power = scc->ss_PBCH_BlockPower; @@ -270,6 +276,54 @@ void config_common_ue(NR_UE_MAC_INST_t *mac, LOG_I(PHY,"TDD has been properly configurated\n"); } + // PRACH configuration + + uint8_t nb_preambles = 64; + if(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->totalNumberOfRA_Preambles != NULL) + nb_preambles = *scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->totalNumberOfRA_Preambles; + + cfg->prach_config.prach_sequence_length = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.present-1; + + if (scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing) + cfg->prach_config.prach_sub_c_spacing = *scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing; + else + cfg->prach_config.prach_sub_c_spacing = scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing; + + cfg->prach_config.restricted_set_config = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig; + + switch (scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FDM) { + case 0 : + cfg->prach_config.num_prach_fd_occasions = 1; + break; + case 1 : + cfg->prach_config.num_prach_fd_occasions = 2; + break; + case 2 : + cfg->prach_config.num_prach_fd_occasions = 4; + break; + case 3 : + cfg->prach_config.num_prach_fd_occasions = 8; + break; + default: + AssertFatal(1==0,"msg1 FDM identifier %ld undefined (0,1,2,3) \n", scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FDM); + } + + cfg->prach_config.num_prach_fd_occasions_list = (fapi_nr_num_prach_fd_occasions_t *) malloc(cfg->prach_config.num_prach_fd_occasions*sizeof(fapi_nr_num_prach_fd_occasions_t)); + for (i=0; iprach_config.num_prach_fd_occasions; i++) { + cfg->prach_config.num_prach_fd_occasions_list[i].num_prach_fd_occasions = i; + if (cfg->prach_config.prach_sequence_length) + cfg->prach_config.num_prach_fd_occasions_list[i].prach_root_sequence_index = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.choice.l139; + else + cfg->prach_config.num_prach_fd_occasions_list[i].prach_root_sequence_index = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.choice.l839; + + cfg->prach_config.num_prach_fd_occasions_list[i].k1 = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FrequencyStart; + cfg->prach_config.num_prach_fd_occasions_list[i].prach_zero_corr_conf = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.zeroCorrelationZoneConfig; + cfg->prach_config.num_prach_fd_occasions_list[i].num_root_sequences = compute_nr_root_seq(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup, + nb_preambles, frame_type); + //cfg->prach_config.num_prach_fd_occasions_list[i].num_unused_root_sequences = ??? + } + + cfg->prach_config.ssb_per_rach = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->present-1; } diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index 28177e2919..4790925338 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -179,8 +179,6 @@ int get_spf(nfapi_nr_config_request_scf_t *cfg); int to_absslot(nfapi_nr_config_request_scf_t *cfg,int frame,int slot); -void get_band(uint64_t downlink_frequency, uint16_t *current_band, int32_t *current_offset, lte_frame_type_t *current_type); - void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, int x_overhead); /** \brief Computes Q based on I_MCS PDSCH and table_idx for downlink. Implements MCS Tables from 38.214. */ From 6cd7e61163d572ff4c66608d787758e5298e02d9 Mon Sep 17 00:00:00 2001 From: cig Date: Mon, 17 Feb 2020 21:31:22 +0100 Subject: [PATCH 051/553] UL grant tx and rx in RAR PDU. TS 38.213 ch 8.2, TS 38.321 ch 6.2.3 --- common/utils/nr/nr_common.c | 10 +- openair1/PHY/defs_nr_UE.h | 5 +- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 7 +- openair2/LAYER2/NR_MAC_UE/mac_defs.h | 2 + openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c | 85 +++++++++++-- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 116 +++++++++++------- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 1 - openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 3 +- 8 files changed, 174 insertions(+), 55 deletions(-) diff --git a/common/utils/nr/nr_common.c b/common/utils/nr/nr_common.c index cdbf59cd76..754ce530f4 100644 --- a/common/utils/nr/nr_common.c +++ b/common/utils/nr/nr_common.c @@ -50,6 +50,7 @@ int NRRIV2PRBOFFSET(int locationAndBandwidth,int N_RB) { else return(N_RB-1-tmp2); } +/* TS 38.214 ch. 6.1.2.2.2 - Resource allocation type 1 for DL and UL */ int PRBalloc_to_locationandbandwidth0(int NPRB,int RBstart,int BWPsize) { AssertFatal(NPRB>0 && (NPRB + RBstart <= BWPsize),"Illegal NPRB/RBstart Configuration (%d,%d)\n",NPRB,RBstart); if (NPRB <= 1+(BWPsize>>1)) return(BWPsize*(NPRB-1)+RBstart); @@ -59,14 +60,21 @@ int PRBalloc_to_locationandbandwidth0(int NPRB,int RBstart,int BWPsize) { int PRBalloc_to_locationandbandwidth(int NPRB,int RBstart) { return(PRBalloc_to_locationandbandwidth0(NPRB,RBstart,275)); } + /// Target code rate tables indexed by Imcs +/* TS 38.214 table 5.1.3.1-1 - MCS index table 1 for PDSCH */ uint16_t nr_target_code_rate_table1[29] = {120, 157, 193, 251, 308, 379, 449, 526, 602, 679, 340, 378, 434, 490, 553, \ 616, 658, 438, 466, 517, 567, 616, 666, 719, 772, 822, 873, 910, 948}; - // Imcs values 20 and 26 have been multiplied by 2 to avoid the floating point + +/* TS 38.214 table 5.1.3.1-2 - MCS index table 2 for PDSCH */ +// Imcs values 20 and 26 have been multiplied by 2 to avoid the floating point uint16_t nr_target_code_rate_table2[28] = {120, 193, 308, 449, 602, 378, 434, 490, 553, 616, 658, 466, 517, 567, \ 616, 666, 719, 772, 822, 873, 1365, 711, 754, 797, 841, 885, 1833, 948}; + +/* TS 38.214 table 5.1.3.1-3 - MCS index table 3 for PDSCH */ uint16_t nr_target_code_rate_table3[29] = {30, 40, 50, 64, 78, 99, 120, 157, 193, 251, 308, 379, 449, 526, 602, 340, \ 378, 434, 490, 553, 616, 438, 466, 517, 567, 616, 666, 719, 772}; + uint16_t nr_tbs_table[93] = {24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120, 128, 136, 144, 152, 160, 168, 176, 184, 192, 208, 224, 240, 256, 272, 288, 304, 320, \ 336, 352, 368, 384, 408, 432, 456, 480, 504, 528, 552, 576, 608, 640, 672, 704, 736, 768, 808, 848, 888, 928, 984, 1032, 1064, 1128, 1160, 1192, 1224, 1256, \ 1288, 1320, 1352, 1416, 1480, 1544, 1608, 1672, 1736, 1800, 1864, 1928, 2024, 2088, 2152, 2216, 2280, 2408, 2472, 2536, 2600, 2664, 2728, 2792, 2856, 2976, \ diff --git a/openair1/PHY/defs_nr_UE.h b/openair1/PHY/defs_nr_UE.h index e88bfd7768..845a2dfa69 100644 --- a/openair1/PHY/defs_nr_UE.h +++ b/openair1/PHY/defs_nr_UE.h @@ -965,11 +965,12 @@ typedef struct { char ulsch_no_allocation_counter[NUMBER_OF_CONNECTED_eNB_MAX]; - - unsigned char ulsch_Msg3_active[NUMBER_OF_CONNECTED_gNB_MAX]; uint32_t ulsch_Msg3_frame[NUMBER_OF_CONNECTED_gNB_MAX]; unsigned char ulsch_Msg3_subframe[NUMBER_OF_CONNECTED_gNB_MAX]; + uint8_t Msg3_startSymbol[NUMBER_OF_CONNECTED_gNB_MAX]; + uint8_t Msg3_Length[NUMBER_OF_CONNECTED_gNB_MAX]; + NR_PRACH_RESOURCES_t *prach_resources[NUMBER_OF_CONNECTED_gNB_MAX]; int turbo_iterations, turbo_cntl_iterations; /// \brief ?. diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 5d24700317..dcce63734a 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -3135,7 +3135,7 @@ void nr_process_rar(nr_downlink_indication_t *dl_info) { NR_PRACH_RESOURCES_t *prach_resources = ue->prach_resources[gNB_index]; uint16_t slots_per_frame = ue->frame_parms.slots_per_frame; - uint8_t mu_pusch = 1; + uint8_t mu_pusch = 1, sliv_S, sliv_L; // definition table j Table 6.1.2.1.1-4 uint8_t j = (mu_pusch==3)?3:(mu_pusch==2)?2:1; uint8_t table_6_1_2_1_1_2_time_dom_res_alloc_A[16][3]={ // for PUSCH from TS 38.214 subclause 6.1.2.1.1 @@ -3188,6 +3188,9 @@ void nr_process_rar(nr_downlink_indication_t *dl_info) { // PUSCH time domain resource allocation A for normal CP // TS 38.214 ch 6.1.2.1.1 k2 = table_6_1_2_1_1_2_time_dom_res_alloc_A[0][0]; + sliv_S = table_6_1_2_1_1_2_time_dom_res_alloc_A[0][1]; + sliv_L = table_6_1_2_1_1_2_time_dom_res_alloc_A[0][2]; + switch (mu_pusch) { case 0: delta = 2; @@ -3203,6 +3206,8 @@ void nr_process_rar(nr_downlink_indication_t *dl_info) { break; } + ue->Msg3_startSymbol[gNB_index] = sliv_S; + ue->Msg3_Length[gNB_index] = sliv_L; ue->ulsch_Msg3_subframe[gNB_index] = (nr_tti_rx + k2 + delta) % slots_per_frame; if (nr_tti_rx + k2 + delta > slots_per_frame){ ue->ulsch_Msg3_frame[gNB_index] = (frame_rx + 1) % 1024; diff --git a/openair2/LAYER2/NR_MAC_UE/mac_defs.h b/openair2/LAYER2/NR_MAC_UE/mac_defs.h index 9b53e0de3f..d0b64c1da6 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_defs.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_defs.h @@ -164,6 +164,8 @@ typedef struct { uint8_t RA_contention_resolution_cnt; /// Msg3 Delta Preamble int8_t deltaPreamble_Msg3; + /// Received TPC command (in dB) from RAR + int8_t Msg3_TPC; /// Flag to monitor if matching RAPID was received in RAR uint8_t RA_RAPID_found; /// Flag to monitor if BI was received in RAR diff --git a/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c b/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c index f0ba789266..6456bd4945 100644 --- a/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c +++ b/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c @@ -65,8 +65,33 @@ uint16_t table_7_2_1[16] = { 1920, // row index 13 }; +///////////////////////////////////// +// Random Access Response PDU // +// TS 38.213 ch 8.2 // +// TS 38.321 ch 6.2.3 // +///////////////////////////////////// +//| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |// bit-wise +//| E | T | R A P I D |// +//| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |// +//| R | T A |// +//| T A | UL grant |// +//| UL grant |// +//| UL grant |// +//| UL grant |// +//| T C - R N T I |// +//| T C - R N T I |// +///////////////////////////////////// +// UL grant (27 bits) // +///////////////////////////////////// +//| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |// bit-wise +//|-------------------|FHF|F_alloc|// +//| Freq allocation |// +//| F_alloc |Time allocation|// +//| MCS | TPC |CSI|// +///////////////////////////////////// // WIP todo: -// - UL grant +// - apply UL grant freq alloc & time alloc as per 8.2 TS 38.213 +// - apply tpc command, csi req, mcs uint16_t nr_ue_process_rar(module_id_t mod_id, int CC_id, frame_t frameP, @@ -81,7 +106,9 @@ uint16_t nr_ue_process_rar(module_id_t mod_id, uint8_t n_subPDUs = 0; // number of RAR payloads uint8_t n_subheaders = 0; // number of MAC RAR subheaders uint8_t best_rx_rapid = -1; // the closest RAPID receive from all RARs - uint16_t ta_command = 0; + unsigned char freq_hopping, msg3_t_alloc, mcs, tpc_command, csi_req; + uint16_t ta_command = 0, msg3_f_alloc, bwp_size; + int f_alloc, mask; AssertFatal(CC_id == 0, "RAR reception on secondary CCs is not supported yet\n"); @@ -102,12 +129,8 @@ uint16_t nr_ue_process_rar(module_id_t mod_id, ue_mac->RA_RAPID_found = 1; break; } - // if (abs((int) rarh->RAPID - (int) preamble_index) < abs((int) best_rx_rapid - (int) preamble_index)) { - // best_rx_rapid = rarh->RAPID; - // rar = (NR_MAC_RAR *) (dlsch_buffer + n_subheaders + (n_subPDUs - 1) * sizeof(NR_MAC_RAR)); - // } if (rarh->E == 0) { - LOG_I(PHY, "No RAR found with the intended RAPID. The closest RAPID in all RARs is %d\n", best_rx_rapid); + LOG_I(PHY, "No RAR found with the intended RAPID. \n"); break; } else { rarh += sizeof(NR_MAC_RAR) + 1; @@ -120,10 +143,58 @@ uint16_t nr_ue_process_rar(module_id_t mod_id, // mod_id, frameP, *(uint8_t *) rarh, rar[0], rar[1], rar[2], rar[3], rar[4], rar[5], rarh->RAPID, preamble_index); if (ue_mac->RA_RAPID_found) { + // TC-RNTI *t_crnti = rar->TCRNTI_2 + (rar->TCRNTI_1 << 8); ue_mac->t_crnti = *t_crnti; ue_mac->rnti_type = NR_RNTI_TC; + // TA command ta_command = rar->TA2 + (rar->TA1 << 5); + // CSI + csi_req = (unsigned char) (rar->UL_GRANT_4 & 0x01); + // TPC + tpc_command = (unsigned char) ((rar->UL_GRANT_4 >> 1) & 0x07); + switch (tpc_command){ + case 0: + ue_mac->Msg3_TPC = -6; + break; + case 1: + ue_mac->Msg3_TPC = -4; + break; + case 2: + ue_mac->Msg3_TPC = -2; + break; + case 3: + ue_mac->Msg3_TPC = 0; + break; + case 4: + ue_mac->Msg3_TPC = 2; + break; + case 5: + ue_mac->Msg3_TPC = 4; + break; + case 6: + ue_mac->Msg3_TPC = 6; + break; + case 7: + ue_mac->Msg3_TPC = 8; + break; + } + //MCS + mcs = (unsigned char) (rar->UL_GRANT_4 >> 4); + // time and frequency alloc + bwp_size = NRRIV2BW(ue_mac->ULbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275); + msg3_t_alloc = (unsigned char) (rar->UL_GRANT_3 & 0x07); + msg3_f_alloc = (uint16_t) ((rar->UL_GRANT_3 >> 4) | (rar->UL_GRANT_2 << 4) | ((rar->UL_GRANT_1 & 0x03) << 12)); + + if (bwp_size < 180) + mask = (1 << ((int) ceil(log2((bwp_size*(bwp_size+1))>>1)))) - 1; + else + mask = (1 << (28 - (int)(ceil(log2((bwp_size*(bwp_size+1))>>1))))) - 1; + + f_alloc = msg3_f_alloc & mask; + + // frequency hopping flag + freq_hopping = (unsigned char) (rar->UL_GRANT_1 >> 2); } else { ue_mac->t_crnti = 0; ta_command = (0xffff); diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index 7d2eb35121..ac8c6ec1a7 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -186,23 +186,6 @@ void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t AssertFatal(ra->state != RA_IDLE, "RA is not active for RA %X\n", ra->rnti); - // if(N_RB_UL == 25) { - // ra->msg3_first_rb = 1; - // } else { - // if (cc->tdd_Config && N_RB_UL == 100) { - // ra->msg3_first_rb = 3; - // } else { - // ra->msg3_first_rb = 2; - // } - // } - // ra->msg3_nb_rb = 1; - // /* UL Grant */ - // ra->msg3_mcs = 10; - // ra->msg3_TPC = 3; - // ra->msg3_ULdelay = 0; - // ra->msg3_cqireq = 0; - // ra->msg3_round = 0; - LOG_D(MAC, "[gNB %d][RAPROC] Frame %d, Subframe %d : CC_id %d RA is active, Msg3 in (%d,%d)\n", module_idP, frameP, slotP, CC_id, ra->Msg3_frame, ra->Msg3_slot); ul_req->SFN = ra->Msg3_frame << 4 | ra->Msg3_slot; @@ -456,7 +439,7 @@ void nr_generate_Msg2(module_id_t module_idP, // Program UL processing for Msg3 // nr_get_Msg3alloc(&cc[CC_id], slotP, frameP,&ra->Msg3_frame, &ra->Msg3_slot); // todo LOG_D(MAC, "Frame %d, Subframe %d: Setting Msg3 reception for Frame %d Subframe %d\n", frameP, slotP, ra->Msg3_frame, ra->Msg3_slot); - nr_fill_rar(ra, cc[CC_id].RAR_pdu.payload, N_RB_UL); + nr_fill_rar(module_idP, ra, cc[CC_id].RAR_pdu.payload, N_RB_UL); nr_add_msg3(module_idP, CC_id, frameP, slotP); ra->state = WAIT_Msg3; LOG_D(MAC,"[gNB %d][RAPROC] Frame %d, Subframe %d: RA state %d\n", module_idP, frameP, slotP, ra->state); @@ -486,40 +469,89 @@ void nr_clear_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP){ ra->msg3_round = 0; } + +///////////////////////////////////// +// Random Access Response PDU // +// TS 38.213 ch 8.2 // +// TS 38.321 ch 6.2.3 // +///////////////////////////////////// +//| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |// bit-wise +//| E | T | R A P I D |// +//| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |// +//| R | T A |// +//| T A | UL grant |// +//| UL grant |// +//| UL grant |// +//| UL grant |// +//| T C - R N T I |// +//| T C - R N T I |// +///////////////////////////////////// +// UL grant (27 bits) // +///////////////////////////////////// +//| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |// bit-wise +//|-------------------|FHF|F_alloc|// +//| Freq allocation |// +//| F_alloc |Time allocation|// +//| MCS | TPC |CSI|// +///////////////////////////////////// // WIP // todo: // - handle MAC RAR BI subheader // - sending only 1 RAR subPDU -// - UL Grant +// - UL Grant: hardcoded CSI, TPC, time alloc // - padding -void nr_fill_rar(NR_RA_t * ra, +void nr_fill_rar(uint8_t Mod_idP, + NR_RA_t * ra, uint8_t * dlsch_buffer, uint16_t N_RB_UL){ - LOG_D(MAC, "[gNB] Generate RAR MAC PDU frame %d slot %d ", ra->Msg2_frame, ra-> Msg2_slot); - NR_RA_HEADER_RAPID *rarh = (NR_RA_HEADER_RAPID *) dlsch_buffer; - NR_MAC_RAR *rar = (NR_MAC_RAR *) (dlsch_buffer + 1); + LOG_D(MAC, "[gNB] Generate RAR MAC PDU frame %d slot %d ", ra->Msg2_frame, ra-> Msg2_slot); + nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[Mod_idP]->UL_tti_req[0]; + nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[0].pusch_pdu; + NR_RA_HEADER_RAPID *rarh = (NR_RA_HEADER_RAPID *) dlsch_buffer; + NR_MAC_RAR *rar = (NR_MAC_RAR *) (dlsch_buffer + 1); + unsigned char frequency_hopping_flag = 0, csi_req = 0, tpc_command = 0, mcs = 9, t_alloc = 0; + uint8_t N_UL_Hop; + uint16_t ul_grant, f_alloc, prb_alloc; + int bwp_size; - // E/T/RAPID subheader - // E = 0, one only RAR, first and last - // T = 1, RAPID - rarh->E = 0; - rarh->T = 1; - rarh->RAPID = ra->preamble_index; + /// E/T/RAPID subheader /// + // E = 0, one only RAR, first and last + // T = 1, RAPID + rarh->E = 0; + rarh->T = 1; + rarh->RAPID = ra->preamble_index; - // RAR MAC payload - rar->R = 0; - rar->TA1 = (uint8_t) (ra->timing_offset >> 5); // 7 MSBs of timing advance - rar->TA2 = (uint8_t) (ra->timing_offset & 0x1f); // 5 LSBs of timing advance - rar->TCRNTI_1 = (uint8_t) (ra->rnti >> 8); // 8 MSBs of rnti - rar->TCRNTI_2 = (uint8_t) (ra->rnti & 0xff); // 8 LSBs of rnti + /// RAR MAC payload /// + rar->R = 0; - // uint16_t rballoc = nr_mac_compute_RIV(N_RB_UL, ra->msg3_first_rb, ra->msg3_nb_rb); // first PRB only for UL Grant - // uint32_t buffer = 0; - // rar->UL_GRANT_1 = (uint8_t) (buffer >> 24) & 0x7; - // rar->UL_GRANT_2 = (uint8_t) (buffer >> 16) & 0xFF; - // rar->UL_GRANT_3 = (uint8_t) (buffer >> 8) & 0xFF; - // rar->UL_GRANT_4 = (uint8_t) buffer & 0xff; + // TA command + rar->TA1 = (uint8_t) (ra->timing_offset >> 5); // 7 MSBs of timing advance + rar->TA2 = (uint8_t) (ra->timing_offset & 0x1f); // 5 LSBs of timing advance -} + // TC-RNTI + rar->TCRNTI_1 = (uint8_t) (ra->rnti >> 8); // 8 MSBs of rnti + rar->TCRNTI_2 = (uint8_t) (ra->rnti & 0xff); // 8 LSBs of rnti + // UL grant + + ra->msg3_mcs = mcs; + ra->msg3_TPC = tpc_command; + + bwp_size = pusch_pdu->bwp_size; + prb_alloc = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size, pusch_pdu->rb_start, bwp_size); + if (frequency_hopping_flag){ + // PUSCH with frequency hopping + } else { + N_UL_Hop = 0; + } + + f_alloc = (prb_alloc & 0xfff) | (N_UL_Hop << 12); + ul_grant = csi_req | (tpc_command << 1) | (mcs << 4) | (t_alloc << 8) | (f_alloc << 12) | (frequency_hopping_flag << 26); + + rar->UL_GRANT_1 = (uint8_t) (ul_grant >> 24) & 0x07; + rar->UL_GRANT_2 = (uint8_t) (ul_grant >> 16) & 0xff; + rar->UL_GRANT_3 = (uint8_t) (ul_grant >> 8) & 0xff; + rar->UL_GRANT_4 = (uint8_t) ul_grant & 0xff; + +} \ No newline at end of file diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 36430bd30e..ef2a2d9318 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -941,7 +941,6 @@ int to_absslot(nfapi_nr_config_request_scf_t *cfg,int frame,int slot) { } - int extract_startSymbol(int startSymbolAndLength) { int tmp = startSymbolAndLength/14; int tmp2 = startSymbolAndLength%14; diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index 4790925338..90d617d7e9 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -107,7 +107,8 @@ void nr_get_Msg3alloc(NR_COMMON_channels_t *cc, @param dlsch_buffer Pointer to RAR input buffer @param N_RB_UL Number of UL resource blocks */ -void nr_fill_rar(NR_RA_t * ra, +void nr_fill_rar(uint8_t Mod_idP, + NR_RA_t * ra, uint8_t * dlsch_buffer, uint16_t N_RB_UL); From 398a5e9063f4d409535b029d0c9f65c43b6acef6 Mon Sep 17 00:00:00 2001 From: cig Date: Tue, 18 Feb 2020 16:08:22 +0100 Subject: [PATCH 052/553] Bugfix in RAR MAC PDU: set correct fields order for little endian machine --- openair2/LAYER2/NR_MAC_COMMON/nr_mac.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h index 4c3db7cfe9..09426938cf 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h @@ -161,10 +161,10 @@ typedef struct { // TS 38.321 ch. 6.2.3 typedef struct { + uint8_t TA1:7; // octet 1 [6:0] uint8_t R:1; // octet 1 [7] - uint8_t TA1:7; // octet 1 [7:0] - uint8_t TA2:5; // octet 2 [7:2] uint8_t UL_GRANT_1:3; // octet 2 [2:0] + uint8_t TA2:5; // octet 2 [7:3] uint8_t UL_GRANT_2:8; // octet 3 [7:0] uint8_t UL_GRANT_3:8; // octet 4 [7:0] uint8_t UL_GRANT_4:8; // octet 5 [7:0] From dd2cefa457b6270c6e693c9deb0dc3236886aa41 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Wed, 19 Feb 2020 08:34:03 +0100 Subject: [PATCH 053/553] added longer prefix in PRACH symbol zero period for 15/30 kHz SCS. Both gNB and UE processing is modified. prachsim is functional again with new FAPI interfaces. --- executables/nr-ru.c | 6 +- openair1/PHY/INIT/nr_init.c | 2 +- openair1/PHY/NR_TRANSPORT/nr_prach.c | 274 ++++++++------ openair1/PHY/NR_TRANSPORT/nr_transport.h | 2 + openair1/PHY/NR_UE_TRANSPORT/nr_prach.c | 46 ++- openair1/PHY/defs_RU.h | 2 + openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 8 +- .../SIMULATION/NR_PHY/nr_dummy_functions.c | 339 ++++++++++++++++++ openair1/SIMULATION/NR_PHY/nr_unitary_defs.h | 11 + openair1/SIMULATION/NR_PHY/prachsim.c | 103 +++--- openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 2 +- openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c | 2 +- 12 files changed, 624 insertions(+), 173 deletions(-) diff --git a/executables/nr-ru.c b/executables/nr-ru.c index 4a2b22331b..ba860ece60 100644 --- a/executables/nr-ru.c +++ b/executables/nr-ru.c @@ -1578,7 +1578,11 @@ void *ru_thread( void *param ) { // Do PRACH RU processing int prach_id=find_nr_prach_ru(ru,proc->frame_rx,proc->tti_rx,SEARCH_EXIST); if (prach_id>=0) { - rx_nr_prach_ru(ru,ru->prach_list[prach_id].fmt,proc->frame_rx,proc->tti_rx); + rx_nr_prach_ru(ru, + ru->prach_list[prach_id].fmt, + ru->prach_list[prach_id].numRA, + ru->prach_list[prach_id].prachStartSymbol, + proc->frame_rx,proc->tti_rx); free_nr_ru_prach_entry(ru,prach_id); } } diff --git a/openair1/PHY/INIT/nr_init.c b/openair1/PHY/INIT/nr_init.c index d010ce65d9..b2262949c1 100644 --- a/openair1/PHY/INIT/nr_init.c +++ b/openair1/PHY/INIT/nr_init.c @@ -387,7 +387,7 @@ void nr_phy_config_request_sim(PHY_VARS_gNB *gNB, fp->dl_CarrierFreq = 3500000000;//from_nrarfcn(gNB_config->nfapi_config.rf_bands.rf_band[0],gNB_config->nfapi_config.nrarfcn.value); fp->ul_CarrierFreq = 3500000000;//fp->dl_CarrierFreq - (get_uldl_offset(gNB_config->nfapi_config.rf_bands.rf_band[0])*100000); fp->nr_band = 78; - fp->threequarter_fs= 0; +// fp->threequarter_fs= 0; gNB_config->carrier_config.dl_bandwidth.value = config_bandwidth(mu, N_RB_DL, fp->nr_band); diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index 9f9bb4694a..991084c485 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -120,9 +120,11 @@ void nr_fill_prach_ru(RU_t *ru, "illegal or no prach_id found!!! prach_id %d\n",prach_id); pthread_mutex_lock(&ru->prach_list_mutex); - ru->prach_list[prach_id].frame = SFN; - ru->prach_list[prach_id].slot = Slot; - ru->prach_list[prach_id].fmt = prach_pdu->prach_format; + ru->prach_list[prach_id].frame = SFN; + ru->prach_list[prach_id].slot = Slot; + ru->prach_list[prach_id].fmt = prach_pdu->prach_format; + ru->prach_list[prach_id].numRA = prach_pdu->num_ra; + ru->prach_list[prach_id].prachStartSymbol = prach_pdu->prach_start_symbol; pthread_mutex_unlock(&ru->prach_list_mutex); } @@ -139,7 +141,9 @@ void free_nr_ru_prach_entry(RU_t *ru, const char *prachfmt[]={"A1","A2","A3","B1","B2","B3","B4","C0","C2"}; void rx_nr_prach_ru(RU_t *ru, - int prach_fmt, + int prachFormat, + int numRA, + int prachStartSymbol, int frame, int slot) { @@ -151,7 +155,7 @@ void rx_nr_prach_ru(RU_t *ru, int16_t *prach[ru->nb_rx]; int prach_sequence_length = ru->config.prach_config.prach_sequence_length.value; - int msg1_frequencystart = ru->config.prach_config.num_prach_fd_occasions_list[0].k1.value; + int msg1_frequencystart = ru->config.prach_config.num_prach_fd_occasions_list[numRA].k1.value; rxsigF = ru->prach_rxsigF; @@ -167,9 +171,9 @@ void rx_nr_prach_ru(RU_t *ru, if (prach_sequence_length == 0) { LOG_D(PHY,"PRACH (ru %d) in %d.%d, format %d, msg1_frequencyStart %d\n", - ru->idx,frame,slot,prach_fmt,msg1_frequencystart); - AssertFatal(prach_fmt<4,"Illegal prach format %d for length 839\n",prach_fmt); - switch (prach_fmt) { + ru->idx,frame,slot,prachFormat,msg1_frequencystart); + AssertFatal(prachFormat<4,"Illegal prach format %d for length 839\n",prachFormat); + switch (prachFormat) { case 0: Ncp = 3168; break; @@ -189,11 +193,11 @@ void rx_nr_prach_ru(RU_t *ru, } } else { - LOG_D(PHY,"PRACH (ru %d) in %d.%d, format %s, msg1_frequencyStart %d\n", - ru->idx,frame,slot,prachfmt[prach_fmt],msg1_frequencystart); + LOG_D(PHY,"PRACH (ru %d) in %d.%d, format %s, msg1_frequencyStart %d,startSymbol %d\n", + ru->idx,frame,slot,prachfmt[prachFormat],msg1_frequencystart,prachStartSymbol); - switch (prach_fmt) { - AssertFatal(prach_fmt<4,"Illegal prach format %d for length 139 (combined formats not supported yet)\n",prach_fmt); + switch (prachFormat) { + AssertFatal(prachFormat<4,"Illegal prach format %d for length 139 (combined formats not supported yet)\n",prachFormat); case 0: //A1 Ncp = 288/(1<threequarter_fs==0) { //40 MHz @ 61.44 Ms/s //50 MHz @ 61.44 Ms/s - prach2 = prach[aa] + (Ncp<<2); + prach2 = prach[aa] + (Ncp<<2); // Ncp is for 30.72 Ms/s, so multiply by 2 for I/Q, and 2 to bring to 61.44 Ms/s if (prach_sequence_length == 0) { - if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) { + if (prachFormat == 0 || prachFormat == 1 || prachFormat == 2) { dftlen=49152; dft49152(prach2,rxsigF[aa],1); } - if (prach_fmt == 1 || prach_fmt == 2) { + if (prachFormat == 1 || prachFormat == 2) { dft49152(prach2+98304,rxsigF[aa]+98304,1); reps++; } - if (prach_fmt == 2) { + if (prachFormat == 2) { dft49152(prach2+(98304*2),rxsigF[aa]+(98304*2),1); dft49152(prach2+(98304*3),rxsigF[aa]+(98304*3),1); reps+=2; } - if (prach_fmt == 3) { + if (prachFormat == 3) { dftlen=12288; for (int i=0;i<4;i++) dft12288(prach2+(i*12288*2),rxsigF[aa]+(i*12288*2),1); reps=4; } - } + }// 839 sequence else { - dftlen=2048; - dft2048(prach2,rxsigF[aa],1); - if (prach_fmt != 7) { // !=C0 - dft2048(prach2+4096,rxsigF[aa]+4096,1); - reps++; - } - if (prach_fmt == 1 || prach_fmt == 2 || prach_fmt == 4 || prach_fmt == 5 || prach_fmt == 6 || prach_fmt == 8) { - dft2048(prach2+4096*2,rxsigF[aa]+4096*2,1); - dft2048(prach2+4096*3,rxsigF[aa]+4096*3,1); - reps+=2; - } - if (prach_fmt == 2 || prach_fmt == 5 || prach_fmt == 6) { - dft2048(prach2+4096*4,rxsigF[aa]+4096*4,1); - dft2048(prach2+4096*5,rxsigF[aa]+4096*5,1); - reps+=2; - } - if (prach_fmt == 6) { - for (int i=6;i<12;i++) dft2048(prach2+(4096*i),rxsigF[aa]+(4096*i),1); - reps+=6; + if ((mu==0 && + (prachStartSymbol == 0 || prachStartSymbol == 7)) || + (mu==1 && prachStartSymbol == 0)) prach2+=64; // 32 samples @ 61.44 Ms/s in first symbol of each half subframe (15/30 kHz only) + + if (mu==0) AssertFatal(1==0,"Shouldn't get here\n"); + else if (mu==1) { + dftlen=2048; + dft2048(prach2,rxsigF[aa],1); + if (prachFormat != 7) { // !=C0 + dft2048(prach2+4096,rxsigF[aa]+4096,1); + reps++; + } + if (prachFormat == 1 || prachFormat == 2 || prachFormat == 4 || prachFormat == 5 || prachFormat == 6 || prachFormat == 8) { + dft2048(prach2+4096*2,rxsigF[aa]+4096*2,1); + dft2048(prach2+4096*3,rxsigF[aa]+4096*3,1); + reps+=2; + } + if (prachFormat == 2 || prachFormat == 5 || prachFormat == 6) { + dft2048(prach2+4096*4,rxsigF[aa]+4096*4,1); + dft2048(prach2+4096*5,rxsigF[aa]+4096*5,1); + reps+=2; + } + if (prachFormat == 6) { + for (int i=6;i<12;i++) dft2048(prach2+(4096*i),rxsigF[aa]+(4096*i),1); + reps+=6; + } } + else if (mu==2) AssertFatal(1==0,"Shouldn't get here\n"); + else if (mu==3) AssertFatal(1==0,"Shouldn't get here\n"); + else if (mu==4) AssertFatal(1==0,"Shouldn't get here\n"); } - } else { + } else { // threequarter sampling // 40 MHz @ 46.08 Ms/s - prach2 = prach[aa] + (3*Ncp); + prach2 = prach[aa] + (3*Ncp); // 46.08 is 1.5 * 30.72, times 2 for I/Q if (prach_sequence_length == 0) { AssertFatal(fp->N_RB_UL <= 107,"cannot do 108..136 PRBs with 3/4 sampling\n"); - if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) { - dftlen=36864; + if (prachFormat == 0 || prachFormat == 1 || prachFormat == 2) { + dftlen=36864; dft36864(prach2,rxsigF[aa],1); reps++; } - if (prach_fmt == 1 || prach_fmt == 2) { + if (prachFormat == 1 || prachFormat == 2) { dft36864(prach2+73728,rxsigF[aa]+73728,1); reps++; } - if (prach_fmt == 2) { + if (prachFormat == 2) { dft36864(prach2+(73728*2),rxsigF[aa]+(73728*2),1); dft36864(prach2+(73728*3),rxsigF[aa]+(73728*3),1); reps+=2; } - if (prach_fmt == 3) { - dftlen=9216; + if (prachFormat == 3) { + dftlen=9216; for (int i=0;i<4;i++) dft9216(prach2+(i*9216*2),rxsigF[aa]+(i*9216*2),1); reps=4; } } else { - dftlen=1536; - dft1536(prach2,rxsigF[aa],1); - if (prach_fmt != 7) { - dft1536(prach2+3072,rxsigF[aa]+3072,1); - reps++; - } - - if (prach_fmt == 1 || prach_fmt == 2 || prach_fmt == 4 || prach_fmt == 5 || prach_fmt == 6 || prach_fmt == 8) { - dft1536(prach2+3072*2,rxsigF[aa]+3072*2,1); - dft1536(prach2+3072*3,rxsigF[aa]+3072*3,1); - reps+=2; - } - if (prach_fmt == 2 || prach_fmt == 5 || prach_fmt == 6) { - dft1536(prach2+3072*4,rxsigF[aa]+3072*4,1); - dft1536(prach2+3072*5,rxsigF[aa]+3072*5,1); - reps+=2; - } - if (prach_fmt == 6) { - for (int i=6;i<12;i++) dft1536(prach2+(3072*i),rxsigF[aa]+(3072*i),1); - reps+=6; - } + if ((mu==0 && + (prachStartSymbol == 0 || prachStartSymbol == 7)) || + (mu==1 && prachStartSymbol == 0)) prach2+=48; // 24 samples @ 43.08 Ms/s in first symbol of each half subframe (15/30 kHz only) + if (mu==0) AssertFatal(1==0,"Shouldn't get here\n"); + else if (mu==1) { + dftlen=1536; + dft1536(prach2,rxsigF[aa],1); + if (prachFormat != 7) { + dft1536(prach2+3072,rxsigF[aa]+3072,1); + reps++; + } + + if (prachFormat == 1 || prachFormat == 2 || prachFormat == 4 || prachFormat == 5 || prachFormat == 6 || prachFormat == 8) { + dft1536(prach2+3072*2,rxsigF[aa]+3072*2,1); + dft1536(prach2+3072*3,rxsigF[aa]+3072*3,1); + reps+=2; + } + if (prachFormat == 2 || prachFormat == 5 || prachFormat == 6) { + dft1536(prach2+3072*4,rxsigF[aa]+3072*4,1); + dft1536(prach2+3072*5,rxsigF[aa]+3072*5,1); + reps+=2; + } + if (prachFormat == 6) { + for (int i=6;i<12;i++) dft1536(prach2+(3072*i),rxsigF[aa]+(3072*i),1); + reps+=6; + } + }// mu==1 + else if (mu==2) AssertFatal(1==0,"Shouldn't get here\n"); + else if (mu==3) AssertFatal(1==0,"Shouldn't get here\n"); + else if (mu==4) AssertFatal(1==0,"Shouldn't get here\n"); } // short format } // 3/4 sampling } // <=50 MHz BW @@ -374,89 +397,109 @@ void rx_nr_prach_ru(RU_t *ru, //80,90,100 MHz @ 122.88 Ms/s if (prach_sequence_length == 0) { - if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) { + if (prachFormat == 0 || prachFormat == 1 || prachFormat == 2) { dftlen=98304; dft98304(prach2,rxsigF[aa],1); } - if (prach_fmt == 1 || prach_fmt == 2) { + if (prachFormat == 1 || prachFormat == 2) { dft98304(prach2+196608,rxsigF[aa]+196608,1); reps++; } - if (prach_fmt == 2) { + if (prachFormat == 2) { dft98304(prach2+196608*2,rxsigF[aa]+196608*2,1); dft98304(prach2+(196608*3),rxsigF[aa]+(196608*3),1); reps+=2; } - if (prach_fmt == 3) { + if (prachFormat == 3) { dftlen=24576; for (int i=0;i<4;i++) dft24576(prach2+(i*2*24576),rxsigF[aa]+(i*2*24576),1); reps=4; } } else { - dftlen=4096; - dft4096(prach2,rxsigF[aa],1); - if (prach_fmt != 7) { //!=C0 - dft4096(prach2+8192,rxsigF[aa]+8192,1); - reps++; - } - - if (prach_fmt == 1 || prach_fmt == 2 || prach_fmt == 4 || prach_fmt == 5 || prach_fmt == 6 || prach_fmt == 8) { - dft4096(prach2+8192*2,rxsigF[aa]+8192*2,1); - dft4096(prach2+8192*3,rxsigF[aa]+8192*3,1); - reps+=2; - } - if (prach_fmt == 2 || prach_fmt == 5 || prach_fmt == 6) { - dft4096(prach2+8192*4,rxsigF[aa]+8192*4,1); - dft4096(prach2+8192*5,rxsigF[aa]+8192*5,1); - reps+=2; - } - if (prach_fmt == 6) { - for (int i=6;i<12;i++) dft4096(prach2+(8192*i),rxsigF[aa]+(8192*i),1); - reps+=6; + if ((mu==0 && + (prachStartSymbol == 0 || prachStartSymbol == 7)) || + (mu==1 && prachStartSymbol == 0)) prach2+=128; // 64 samples @ 122.88 Ms/s in first symbol of each half subframe (15/30 kHz only) + + if (mu==0) AssertFatal(1==0,"Shouldn't get here\n"); + else if (mu==1) { + dftlen=4096; + dft4096(prach2,rxsigF[aa],1); + if (prachFormat != 7) { //!=C0 + dft4096(prach2+8192,rxsigF[aa]+8192,1); + reps++; + } + + if (prachFormat == 1 || prachFormat == 2 || prachFormat == 4 || prachFormat == 5 || prachFormat == 6 || prachFormat == 8) { + dft4096(prach2+8192*2,rxsigF[aa]+8192*2,1); + dft4096(prach2+8192*3,rxsigF[aa]+8192*3,1); + reps+=2; + } + if (prachFormat == 2 || prachFormat == 5 || prachFormat == 6) { + dft4096(prach2+8192*4,rxsigF[aa]+8192*4,1); + dft4096(prach2+8192*5,rxsigF[aa]+8192*5,1); + reps+=2; + } + if (prachFormat == 6) { + for (int i=6;i<12;i++) dft4096(prach2+(8192*i),rxsigF[aa]+(8192*i),1); + reps+=6; + } } + else if (mu==2) AssertFatal(1==0,"Shouldn't get here\n"); + else if (mu==3) AssertFatal(1==0,"Shouldn't get here\n"); + else if (mu==4) AssertFatal(1==0,"Shouldn't get here\n"); } } else { AssertFatal(fp->N_RB_UL <= 217,"cannot do more than 217 PRBs with 3/4 sampling\n"); prach2 = prach[aa] + (6*Ncp); // 80 MHz @ 92.16 Ms/s if (prach_sequence_length == 0) { - if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) { + if (prachFormat == 0 || prachFormat == 1 || prachFormat == 2) { dftlen=73728; dft73728(prach2,rxsigF[aa],1); reps++; } - if (prach_fmt == 1 || prach_fmt == 2) { + if (prachFormat == 1 || prachFormat == 2) { dft73728(prach2+(2*73728),rxsigF[aa]+(2*73728),1); reps++; } - if (prach_fmt == 3) { + if (prachFormat == 3) { dftlen=18432; for (int i=0;i<4;i++) dft18432(prach2+(i*2*18432),rxsigF[aa]+(i*2*18432),1); reps=4; } } else { - dftlen=3072; - dft3072(prach2,rxsigF[aa],1); - if (prach_fmt != 7) { //!=C0 - dft3072(prach2+6144,rxsigF[aa]+6144,1); - reps++; - } - - if (prach_fmt == 1 || prach_fmt == 2 || prach_fmt == 4 || prach_fmt == 5 || prach_fmt == 6 || prach_fmt == 8) { - dft3072(prach2+6144*2,rxsigF[aa]+6144*2,1); - dft3072(prach2+6144*3,rxsigF[aa]+6144*3,1); - reps+=2; - } - if (prach_fmt == 2 || prach_fmt == 5 || prach_fmt == 6) { - dft3072(prach2+6144*4,rxsigF[aa]+6144*4,1); - dft3072(prach2+6144*5,rxsigF[aa]+6144*5,1); - reps+=2; - } - if (prach_fmt == 6) { - for (int i=6;i<12;i++) dft3072(prach2+(6144*i),rxsigF[aa]+(6144*i),1); - reps+=6; + if ((mu==0 && + (prachStartSymbol == 0 || prachStartSymbol == 7)) || + (mu==1 && prachStartSymbol == 0)) prach2+=96; // 64 samples @ 122.88 Ms/s in first symbol of each half subframe (15/30 kHz only) + + if (mu==0) AssertFatal(1==0,"Shouldn't get here\n"); + else if (mu==1) { + dftlen=3072; + dft3072(prach2,rxsigF[aa],1); + if (prachFormat != 7) { //!=C0 + dft3072(prach2+6144,rxsigF[aa]+6144,1); + reps++; + } + + if (prachFormat == 1 || prachFormat == 2 || prachFormat == 4 || prachFormat == 5 || prachFormat == 6 || prachFormat == 8) { + dft3072(prach2+6144*2,rxsigF[aa]+6144*2,1); + dft3072(prach2+6144*3,rxsigF[aa]+6144*3,1); + reps+=2; + } + if (prachFormat == 2 || prachFormat == 5 || prachFormat == 6) { + dft3072(prach2+6144*4,rxsigF[aa]+6144*4,1); + dft3072(prach2+6144*5,rxsigF[aa]+6144*5,1); + reps+=2; + } + if (prachFormat == 6) { + for (int i=6;i<12;i++) dft3072(prach2+(6144*i),rxsigF[aa]+(6144*i),1); + reps+=6; + } } + else if (mu==2) AssertFatal(1==0,"Shouldn't get here\n"); + else if (mu==3) AssertFatal(1==0,"Shouldn't get here\n"); + else if (mu==4) AssertFatal(1==0,"Shouldn't get here\n"); } } } @@ -724,7 +767,6 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, for (i=0; i*max_preamble_energy) { *max_preamble_energy = levdB; *max_preamble_delay = i; // Note: This has to be normalized to the 30.72 Ms/s sampling rate diff --git a/openair1/PHY/NR_TRANSPORT/nr_transport.h b/openair1/PHY/NR_TRANSPORT/nr_transport.h index 59e81fd0c5..157e309228 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_transport.h +++ b/openair1/PHY/NR_TRANSPORT/nr_transport.h @@ -122,6 +122,8 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, void rx_nr_prach_ru(RU_t *ru, int prach_fmt, + int numRA, + int prachStartSymbol, int frame, int subframe); diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c index c144a37a06..34331a957d 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c @@ -41,6 +41,8 @@ #include "T.h" +#define NR_PRACH_DEBUG 1 + extern uint16_t NCS_unrestricted_delta_f_RA_125[16]; extern uint16_t NCS_restricted_TypeA_delta_f_RA_125[15]; extern uint16_t NCS_restricted_TypeB_delta_f_RA_125[13]; @@ -111,7 +113,7 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) #else //normal case (simulation) prach_start = subframe*(fp->samples_per_slot<<1)-ue->N_TA_offset; - LOG_D(PHY,"[UE %d] prach_start %d, rx_offset %d, hw_timing_advance %d, N_TA_offset %d\n", ue->Mod_id, + LOG_I(PHY,"[UE %d] prach_start %d, rx_offset %d, hw_timing_advance %d, N_TA_offset %d\n", ue->Mod_id, prach_start, ue->rx_offset, ue->hw_timing_advance, @@ -222,7 +224,7 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) #ifdef NR_PRACH_DEBUG if (NCS>0) - LOG_D(PHY,"Generate PRACH for RootSeqIndex %d, Preamble Index %d, PRACH Format %x, prach_ConfigIndex %d, NCS %d (NCS_config %d, N_ZC/NCS %d): Preamble_offset %d, Preamble_shift %d\n", + LOG_I(PHY,"Generate PRACH for RootSeqIndex %d, Preamble Index %d, PRACH Format %x, prach_ConfigIndex %d, NCS %d (NCS_config %d, N_ZC/NCS %d): Preamble_offset %d, Preamble_shift %d\n", rootSequenceIndex,preamble_index,prach_fmt,prach_ConfigIndex,NCS,Ncs_config,N_ZC/NCS, preamble_offset,preamble_shift); @@ -251,7 +253,7 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) k*=K; k+=kbar; - LOG_D(PHY,"placing prach in position %d\n",k); + LOG_I(PHY,"placing prach in position %d\n",k); k*=2; Xu = (int16_t*)ue->X_u[preamble_offset-first_nonzero_root_idx]; @@ -427,6 +429,7 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) dftlen=12288; } else if (prach_fmt == 0xa1 || prach_fmt == 0xb1 || prach_fmt == 0xc0) { + Ncp+=32; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling prach2 = prach+(Ncp<<1); idft2048(prachF,prach2,1); dftlen=2048; @@ -440,6 +443,8 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) // here we have |Prefix | Prach2048 | Prach2048 (if ! 0xc0) | } else if (prach_fmt == 0xa2 || prach_fmt == 0xb2) { // 6x2048 + Ncp+=32; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); idft2048(prachF,prach2,1); dftlen=2048; // here we have |empty | Prach2048 | @@ -452,6 +457,7 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) prach_len = (2048*4)+Ncp; } else if (prach_fmt == 0xa3 || prach_fmt == 0xb3) { // 6x2048 + Ncp+=32; prach2 = prach+(Ncp<<1); idft2048(prachF,prach2,1); dftlen=2048; @@ -467,6 +473,8 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) prach_len = (2048*6)+Ncp; } else if (prach_fmt == 0xb4) { // 12x2048 + Ncp+=32; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); idft2048(prachF,prach2,1); dftlen=2048; // here we have |empty | Prach2048 | @@ -527,19 +535,23 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) prach_len = (9216*4)+Ncp; } else if (prach_fmt == 0xa1 || prach_fmt == 0xb1 || prach_fmt == 0xc0) { + Ncp+=24; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); idft1536(prachF,prach2,1); dftlen=1536; // here we have |empty | Prach1536 | if (prach_fmt != 0xc0) { - memmove(prach2+(1536<<1),prach2,(1536<<2)); - prach_len = (1536*2)+Ncp; - } - else prach_len = (1536*1)+Ncp; + memmove(prach2+(1536<<1),prach2,(1536<<2)); + prach_len = (1536*2)+Ncp; + } + else prach_len = (1536*1)+Ncp; memmove(prach,prach+(1536<<1),(Ncp<<2)); // here we have |Prefix | Prach1536 | Prach1536 (if ! 0xc0) | } else if (prach_fmt == 0xa2 || prach_fmt == 0xb2) { // 6x1536 + Ncp+=24; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); idft1536(prachF,prach2,1); dftlen=1536; // here we have |empty | Prach1536 | @@ -552,6 +564,8 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) prach_len = (1536*4)+Ncp; } else if (prach_fmt == 0xa3 || prach_fmt == 0xb3) { // 6x1536 + Ncp+=24; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); idft1536(prachF,prach2,1); dftlen=1536; // here we have |empty | Prach1536 | @@ -566,6 +580,8 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) prach_len = (1536*6)+Ncp; } else if (prach_fmt == 0xb4) { // 12x1536 + Ncp+=24; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); idft1536(prachF,prach2,1); dftlen=1536; // here we have |empty | Prach1536 | @@ -627,6 +643,8 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) prach_len = (24576*4)+Ncp; } else if (prach_fmt == 0xa1 || prach_fmt == 0xb1 || prach_fmt == 0xc0) { + Ncp+=64; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); idft4096(prachF,prach2,1); dftlen=4096; // here we have |empty | Prach4096 | @@ -640,6 +658,8 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) } else if (prach_fmt == 0xa2 || prach_fmt == 0xb2) { // 4x4096 + Ncp+=64; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); idft4096(prachF,prach2,1); dftlen=4096; // here we have |empty | Prach4096 | @@ -652,6 +672,8 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) prach_len = (4096*4)+Ncp; } else if (prach_fmt == 0xa3 || prach_fmt == 0xb3) { // 6x4096 + Ncp+=64; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); idft4096(prachF,prach2,1); dftlen=4096; // here we have |empty | Prach4096 | @@ -666,6 +688,8 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) prach_len = (4096*6)+Ncp; } else if (prach_fmt == 0xb4) { // 12x4096 + Ncp+=64; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); idft4096(prachF,prach2,1); dftlen=4096; // here we have |empty | Prach4096 | @@ -725,6 +749,8 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) prach_len = (18432*4)+Ncp; } else if (prach_fmt == 0xa1 || prach_fmt == 0xb1 || prach_fmt == 0xc0) { + Ncp+=48; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); idft3072(prachF,prach2,1); dftlen=3072; // here we have |empty | Prach3072 | @@ -737,6 +763,8 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) // here we have |Prefix | Prach3072 | Prach3072 (if ! 0xc0) | } else if (prach_fmt == 0xa3 || prach_fmt == 0xb3) { // 6x3072 + Ncp+=48; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); idft3072(prachF,prach2,1); dftlen=3072; // here we have |empty | Prach3072 | @@ -751,6 +779,8 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) prach_len = (3072*6)+Ncp; } else if (prach_fmt == 0xa2 || prach_fmt == 0xb2) { // 4x3072 + Ncp+=48; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); idft3072(prachF,prach2,1); dftlen=3072; // here we have |empty | Prach3072 | @@ -763,6 +793,8 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) prach_len = (3072*4)+Ncp; } else if (prach_fmt == 0xb4) { // 12x3072 + Ncp+=48; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); idft3072(prachF,prach2,1); dftlen=3072; // here we have |empty | Prach3072 | diff --git a/openair1/PHY/defs_RU.h b/openair1/PHY/defs_RU.h index 4cdb4bec76..128a40b02e 100644 --- a/openair1/PHY/defs_RU.h +++ b/openair1/PHY/defs_RU.h @@ -193,6 +193,8 @@ typedef struct { int frame; int slot; int fmt; + int numRA; + int prachStartSymbol; } RU_PRACH_list_t; #define NUMBER_OF_NR_RU_PRACH_MAX 8 diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 5d24700317..a5cd433437 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -212,9 +212,7 @@ void nr_dump_dlsch_SI(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id, #endif -#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706) unsigned int gain_table[31] = {100,112,126,141,158,178,200,224,251,282,316,359,398,447,501,562,631,708,794,891,1000,1122,1258,1412,1585,1778,1995,2239,2512,2818,3162}; -#endif int get_tx_amp_prach(int power_dBm, int power_max_dBm, int N_RB_UL){ @@ -4490,7 +4488,7 @@ uint8_t nr_is_ri_TXOp(PHY_VARS_NR_UE *ue, void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t gNB_id, runmode_t runmode) { int frame_tx = proc->frame_tx, nr_tti_tx = proc->nr_tti_tx, prach_power, tx_amp; - uint16_t preamble_tx = 50, pathloss; + uint16_t /*preamble_tx = 50,*/ pathloss; uint8_t mod_id = ue->Mod_id; UE_MODE_t UE_mode = get_nrUE_mode(mod_id, ue->CC_id, gNB_id); NR_PRACH_RESOURCES_t * prach_resources = ue->prach_resources[gNB_id]; @@ -4499,7 +4497,7 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t ue->generate_nr_prach = 0; if (ue->mac_enabled == 0){ - prach_resources->ra_PreambleIndex = preamble_tx; + // prach_resources->ra_PreambleIndex = preamble_tx; prach_resources->ra_TDD_map_index = 0; prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = 10; prach_resources->ra_RNTI = 0x1234; @@ -4593,4 +4591,4 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t ue->generate_nr_prach = 0; VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_OUT); -} \ No newline at end of file +} diff --git a/openair1/SIMULATION/NR_PHY/nr_dummy_functions.c b/openair1/SIMULATION/NR_PHY/nr_dummy_functions.c index c9253aeedf..8aa5c3e81f 100644 --- a/openair1/SIMULATION/NR_PHY/nr_dummy_functions.c +++ b/openair1/SIMULATION/NR_PHY/nr_dummy_functions.c @@ -7,3 +7,342 @@ int32_t get_uldl_offset(int nr_bandP) { re NR_IF_Module_t *NR_IF_Module_init(int Mod_id) {return(NULL);} int dummy_nr_ue_dl_indication(nr_downlink_indication_t *dl_info) { return(0); } int dummy_nr_ue_ul_indication(nr_uplink_indication_t *ul_info) { return(0); } +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file ra_procedures.c + * \brief Routines for UE MAC-layer Random Access procedures (TS 38.321, Release 15) + * \author R. Knopp, Navid Nikaein, Guido Casati + * \date 2019 + * \version 0.1 + * \company Eurecom + * \email: knopp@eurecom.fr navid.nikaein@eurecom.fr, guido.casati@iis.fraunhofer.de + * \note + * \warning + */ + +#include "mac.h" + +/* +#include "common/utils/LOG/vcd_signal_dumper.h" +#include "PHY_INTERFACE/phy_interface_extern.h" +#include "SCHED_UE/sched_UE.h" +#include "COMMON/mac_rrc_primitives.h" +#include "RRC/LTE/rrc_extern.h" +#include "RRC/L2_INTERFACE/openair_rrc_L2_interface.h" +#include "common/utils/LOG/log.h" +#include "UTIL/OPT/opt.h" +#include "OCG.h" +#include "OCG_extern.h" +#include "PHY/LTE_ESTIMATION/lte_estimation.h"*/ + +/* Tools */ +#include "SIMULATION/TOOLS/sim.h" // for taus + +/* RRC */ +#include "NR_RACH-ConfigCommon.h" + +/* PHY */ +#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" +#include "PHY/defs_common.h" +#include "PHY/defs_nr_common.h" +#include "PHY/NR_UE_ESTIMATION/nr_estimation.h" + +/* MAC */ +#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" +#include "NR_MAC_COMMON/nr_mac.h" +#include "LAYER2/NR_MAC_UE/mac_proto.h" + +extern int64_t table_6_3_3_2_2_prachConfig_Index [256][9]; +extern int64_t table_6_3_3_2_3_prachConfig_Index [256][9]; + +//extern uint8_t nfapi_mode; + +// WIP +// This routine implements Section 5.1.2 (UE Random Access Resource Selection) +// and Section 5.1.3 (Random Access Preamble Transmission) from 3GPP TS 38.321 +void nr_get_prach_resources(module_id_t mod_id, + int CC_id, + uint8_t gNB_id, + uint8_t t_id, + uint8_t first_Msg3, + NR_PRACH_RESOURCES_t *prach_resources, + NR_RACH_ConfigDedicated_t * rach_ConfigDedicated){ + + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon; + // NR_BeamFailureRecoveryConfig_t *beam_failure_recovery_config = &mac->RA_BeamFailureRecoveryConfig; // todo + + int messagePowerOffsetGroupB, messageSizeGroupA, PLThreshold, sizeOfRA_PreamblesGroupA, numberOfRA_Preambles, i, deltaPreamble_Msg3; + uint8_t noGroupB = 0, s_id, f_id, ul_carrier_id, msg1_FDM, prach_ConfigIndex, SFN_nbr, Msg3_size; + + // NR_RSRP_Range_t rsrp_ThresholdSSB; // todo + + /////////////////////////////////////////////////////////// + //////////* UE Random Access Resource Selection *////////// + /////////////////////////////////////////////////////////// + + // todo: + // - switch initialisation cases + // -- RA initiated by beam failure recovery operation (subclause 5.17 TS 38.321) + // --- SSB selection, set prach_resources->ra_PreambleIndex + // -- RA initiated by PDCCH: ra_preamble_index provided by PDCCH && ra_PreambleIndex != 0b000000 + // --- set PREAMBLE_INDEX to ra_preamble_index + // --- select the SSB signalled by PDCCH + // -- RA initiated for SI request: + // --- SSB selection, set prach_resources->ra_PreambleIndex + + // if (rach_ConfigDedicated) { // This is for network controlled Mobility + // // operation for contention-free RA resources when: + // // - available SSB with SS-RSRP above rsrp-ThresholdSSB: SSB selection + // // - availalbe CSI-RS with CSI-RSRP above rsrp-ThresholdCSI-RS: CSI-RS selection + // prach_resources->ra_PreambleIndex = rach_ConfigDedicated->ra_PreambleIndex; + // return; + // } + + //////////* Contention-based RA preamble selection *////////// + // todo: + // - selection of SSB with SS-RSRP above rsrp-ThresholdSSB else select any SSB + // - todo determine next available PRACH occasion + + // rsrp_ThresholdSSB = *nr_rach_ConfigCommon->rsrp_ThresholdSSB; + + AssertFatal(mac->nr_rach_ConfigCommon != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); + + nr_rach_ConfigCommon = mac->nr_rach_ConfigCommon; + + Msg3_size = mac->RA_Msg3_size; + numberOfRA_Preambles = *nr_rach_ConfigCommon->totalNumberOfRA_Preambles; + + if (!nr_rach_ConfigCommon->groupBconfigured) { + noGroupB = 1; + } else { + // RA preambles group B is configured + // - Defining the number of RA preambles in RA Preamble Group A for each SSB */ + sizeOfRA_PreamblesGroupA = nr_rach_ConfigCommon->groupBconfigured->numberOfRA_PreamblesGroupA; + switch (nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA){ + /* - Threshold to determine the groups of RA preambles */ + case 0: + messageSizeGroupA = 56; + break; + case 1: + messageSizeGroupA = 144; + break; + case 2: + messageSizeGroupA = 208; + break; + case 3: + messageSizeGroupA = 256; + break; + case 4: + messageSizeGroupA = 282; + break; + case 5: + messageSizeGroupA = 480; + break; + case 6: + messageSizeGroupA = 640; + break; + case 7: + messageSizeGroupA = 800; + break; + case 8: + messageSizeGroupA = 1000; + break; + case 9: + messageSizeGroupA = 72; + break; + default: + AssertFatal(1 == 0,"Unknown ra_Msg3SizeGroupA %lu\n", nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA); + /* todo cases 10 -15*/ + } + + /* Power offset for preamble selection in dB */ + messagePowerOffsetGroupB = -9999; + switch (nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB){ + case 0: + messagePowerOffsetGroupB = -9999; + break; + case 1: + messagePowerOffsetGroupB = 0; + break; + case 2: + messagePowerOffsetGroupB = 5; + break; + case 3: + messagePowerOffsetGroupB = 8; + break; + case 4: + messagePowerOffsetGroupB = 10; + break; + case 5: + messagePowerOffsetGroupB = 12; + break; + case 6: + messagePowerOffsetGroupB = 15; + break; + case 7: + messagePowerOffsetGroupB = 18; + break; + default: + AssertFatal(1 == 0,"Unknown messagePowerOffsetGroupB %lu\n", nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB); + } + + // todo Msg3-DeltaPreamble should be provided from higher layers, otherwise is 0 + mac->deltaPreamble_Msg3 = 0; + deltaPreamble_Msg3 = mac->deltaPreamble_Msg3; + } + + PLThreshold = prach_resources->RA_PCMAX - nr_rach_ConfigCommon->rach_ConfigGeneric.preambleReceivedTargetPower - deltaPreamble_Msg3 - messagePowerOffsetGroupB; + + /* Msg3 has not been transmitted yet */ + if (first_Msg3 == 1) { + if (noGroupB == 1) { + // use Group A preamble + prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles; + mac->RA_usedGroupA = 1; + } else if ((Msg3_size < messageSizeGroupA) && (get_nr_PL(mod_id, CC_id, gNB_id) > PLThreshold)) { + // Group B is configured and RA preamble Group A is used + // - todo add condition on CCCH_sdu_size for initiation by CCCH + prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; + mac->RA_usedGroupA = 1; + } else { + // Group B preamble is configured and used + // the first sizeOfRA_PreamblesGroupA RA preambles belong to RA Preambles Group A + // the remaining belong to RA Preambles Group B + prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); + mac->RA_usedGroupA = 0; + } + } else { // Msg3 is being retransmitted + if (mac->RA_usedGroupA == 1 && noGroupB == 1) { + prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles; + } else if (mac->RA_usedGroupA == 1 && noGroupB == 0){ + prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; + } else { + prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); + } + } + + // todo determine next available PRACH occasion + // - if RA initiated for SI request and ra_AssociationPeriodIndex and si-RequestPeriod are configured + // - else if SSB is selected above + // - else if CSI-RS is selected above + + ///////////////////////////////////////////////////////////////////////////// + //////////* Random Access Preamble Transmission (5.1.3 TS 38.321) *////////// + ///////////////////////////////////////////////////////////////////////////// + // todo: + // - condition on notification of suspending power ramping counter from lower layer (5.1.3 TS 38.321) + // - check if SSB or CSI-RS have not changed since the selection in the last RA Preamble tranmission + // - Extend RA_rnti computation (e.g. f_id selection, ul_carrier_id are hardcoded) + + if (mac->RA_PREAMBLE_TRANSMISSION_COUNTER > 1) + mac->RA_PREAMBLE_TRANSMISSION_COUNTER++; + + prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = nr_get_Po_NOMINAL_PUSCH(prach_resources, mod_id, CC_id); + + // RA-RNTI computation (associated to PRACH occasion in which the RA Preamble is transmitted) + // 1) this does not apply to contention-free RA Preamble for beam failure recovery request + // 2) getting star_symb, SFN_nbr from table 6.3.3.2-3 (TDD and FR1 scenario) + + switch (nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FDM){ // todo this is not used + case 0: + msg1_FDM = 1; + break; + case 1: + msg1_FDM = 2; + break; + case 2: + msg1_FDM = 4; + break; + case 3: + msg1_FDM = 8; + break; + default: + AssertFatal(1 == 0,"Unknown msg1_FDM %lu\n", nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FDM); + } + + prach_ConfigIndex = nr_rach_ConfigCommon->rach_ConfigGeneric.prach_ConfigurationIndex; + + // ra_RNTI computation + // - todo: this is for TDD FR1 only + // - ul_carrier_id: UL carrier used for RA preamble transmission, hardcoded for NUL carrier + // - f_id: index of the PRACH occasion in the frequency domain + // - s_id is starting symbol of the PRACH occasion [0...14] + // - t_id is the first slot of the PRACH occasion in a system frame [0...80] + + ul_carrier_id = 0; // NUL + f_id = nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FrequencyStart; + SFN_nbr = table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][4]; + s_id = table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][5]; + + // Pick the first slot of the PRACH occasion in a system frame + for (i = 0; i < 10; i++){ + if (((SFN_nbr & (1 << i)) >> i) == 1){ + t_id = 2*i; + break; + } + } + prach_resources->ra_RNTI = 1 + s_id + 14 * t_id + 1120 * f_id + 8960 * ul_carrier_id; + mac->ra_rnti = prach_resources->ra_RNTI; + + LOG_D(MAC, "Computed ra_RNTI is %d", prach_resources->ra_RNTI); +} + +// TbD: RA_attempt_number not used +void nr_Msg1_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id){ + AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + mac->ra_state = WAIT_RAR; + // Start contention resolution timer + mac->RA_attempt_number++; +} + +void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id){ + AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); + LOG_D(MAC,"[UE %d][RAPROC] Frame %d : Msg3_tx: Starting contention resolution timer\n", mod_id, frameP); + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + // start contention resolution timer + mac->RA_contention_resolution_cnt = 0; + mac->RA_contention_resolution_timer_active = 1; +} + +///////////////////////////////////////////////////////////////////////// +///////* Random Access Preamble Initialization (5.1.1 TS 38.321) */////// +///////////////////////////////////////////////////////////////////////// +/// Handling inizialization by PDCCH order, MAC entity or RRC (TS 38.300) +/// Only one RA procedure is ongoing at any point in time in a MAC entity +/// the RA procedure on a SCell shall only be initiated by PDCCH order + +// WIP +// todo TS 38.321: +// - check if carrier to use is explicitly signalled then do (1) RA CARRIER SELECTION (SUL, NUL) (2) set PCMAX +// - BWP operation (subclause 5.15 TS 38.321) +// - handle initialization by beam failure recovery +// - handle initialization by handover +// - handle transmission on DCCH using PRACH (during handover, or sending SR for example) +// - take into account MAC CEs in size_sdu (currently hardcoded size to 1 MAC subPDU and 1 padding subheader) +// - fix rrc data req logic +// - retrieve TBS +// - add mac_rrc_nr_data_req_ue, etc ... +// - add the backoff condition here if we have it from a previous RA reponse which failed (i.e. backoff indicator) + + diff --git a/openair1/SIMULATION/NR_PHY/nr_unitary_defs.h b/openair1/SIMULATION/NR_PHY/nr_unitary_defs.h index 78596cc792..1b2a07514a 100644 --- a/openair1/SIMULATION/NR_PHY/nr_unitary_defs.h +++ b/openair1/SIMULATION/NR_PHY/nr_unitary_defs.h @@ -55,4 +55,15 @@ signed char quantize(double D, double x, unsigned char B) { return ((char) qxd); } +int8_t nr_ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, uint8_t eNB_id, uint16_t rnti, sub_frame_t subframe) { + AssertFatal(1==0,"Shouldn't be here ...\n"); + return 0; +} + +int oai_nfapi_rach_ind(nfapi_rach_indication_t *rach_ind) {return(0);} +NR_IF_Module_t *NR_IF_Module_init(int Mod_id){return(NULL);} +int oai_nfapi_ul_config_req(nfapi_ul_config_request_t *ul_config_req) { return(0); } + + + #endif diff --git a/openair1/SIMULATION/NR_PHY/prachsim.c b/openair1/SIMULATION/NR_PHY/prachsim.c index 33ee14424c..64df0bc1f2 100644 --- a/openair1/SIMULATION/NR_PHY/prachsim.c +++ b/openair1/SIMULATION/NR_PHY/prachsim.c @@ -42,11 +42,15 @@ #include "PHY/MODULATION/modulation_UE.h" #include "PHY/INIT/phy_init.h" #include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto_common.h" #include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" +#include "nr_unitary_defs.h" #include "OCG_vars.h" #include + + PHY_VARS_gNB *gNB; PHY_VARS_NR_UE *UE; RAN_CONTEXT_t RC; @@ -59,27 +63,33 @@ extern uint16_t prach_root_sequence_map0_3[838]; void dump_nr_prach_config(NR_DL_FRAME_PARMS *frame_parms,uint8_t subframe); uint16_t NB_UE_INST=1; -volatile int oai_exit=0; - -void exit_function(const char* file, const char* function, const int line,const char *s) { - const char * msg= s==NULL ? "no comment": s; - printf("Exiting at: %s:%d %s(), %s\n", file, line, function, msg); - exit(-1); -} -int8_t nr_ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, uint8_t eNB_id, uint16_t rnti, sub_frame_t subframe) { - AssertFatal(1==0,"Shouldn't be here ...\n"); - return 0; -} - -int oai_nfapi_rach_ind(nfapi_rach_indication_t *rach_ind) {return(0);} openair0_config_t openair0_cfg[MAX_CARDS]; uint8_t nfapi_mode=0; -NR_IF_Module_t *NR_IF_Module_init(int Mod_id){return(NULL);} -int oai_nfapi_ul_config_req(nfapi_ul_config_request_t *ul_config_req) { return(0); } +void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, + module_id_t mod_id, + int CC_id, + UE_MODE_t UE_mode, + frame_t frame, + uint8_t gNB_id, + int nr_tti_tx) { return;} + +void nr_Msg1_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id) { return;} + +uint16_t nr_ue_process_rar(module_id_t mod_id, + int CC_id, + frame_t frameP, + uint8_t * dlsch_buffer, + rnti_t * t_crnti, + uint8_t preamble_index, + uint8_t * selected_rar_buffer) { return 0;} + +int is_nr_prach_subframe(NR_DL_FRAME_PARMS *fp,uint32_t frame,uint8_t slot) { return(1);} + +int get_nr_prach_fmt(int prachConfigIndex,int frame_type,int fr) { return(0xa2); } int main(int argc, char **argv) { @@ -203,7 +213,7 @@ int main(int argc, char **argv) break; default: - msg("Unsupported channel model!\n"); + printf("Unsupported channel model!\n"); exit(-1); } @@ -219,13 +229,13 @@ int main(int argc, char **argv) case 's': snr0 = atof(optarg); - msg("Setting SNR0 to %f\n",snr0); + printf("Setting SNR0 to %f\n",snr0); break; case 'S': snr1 = atof(optarg); snr1set=1; - msg("Setting SNR1 to %f\n",snr1); + printf("Setting SNR1 to %f\n",snr1); break; case 'p': @@ -268,7 +278,7 @@ int main(int argc, char **argv) if ((transmission_mode!=1) && (transmission_mode!=2) && (transmission_mode!=6)) { - msg("Unsupported transmission mode %d\n",transmission_mode); + printf("Unsupported transmission mode %d\n",transmission_mode); exit(-1); } @@ -278,7 +288,7 @@ int main(int argc, char **argv) n_tx=atoi(optarg); if ((n_tx==0) || (n_tx>2)) { - msg("Unsupported number of tx antennas %d\n",n_tx); + printf("Unsupported number of tx antennas %d\n",n_tx); exit(-1); } @@ -288,7 +298,7 @@ int main(int argc, char **argv) n_rx=atoi(optarg); if ((n_rx==0) || (n_rx>2)) { - msg("Unsupported number of rx antennas %d\n",n_rx); + printf("Unsupported number of rx antennas %d\n",n_rx); exit(-1); } @@ -400,10 +410,24 @@ int main(int argc, char **argv) ru->nb_tx = n_tx; ru->nb_rx = n_rx; + gNB->gNB_config.carrier_config.num_tx_ant.value=1; + gNB->gNB_config.carrier_config.num_rx_ant.value=1; + gNB->gNB_config.prach_config.num_prach_fd_occasions_list = (nfapi_nr_num_prach_fd_occasions_t *) malloc(gNB->gNB_config.prach_config.num_prach_fd_occasions.value*sizeof(nfapi_nr_num_prach_fd_occasions_t)); + gNB->gNB_config.prach_config.num_prach_fd_occasions_list[0].prach_root_sequence_index.value = 1; + gNB->gNB_config.prach_config.num_prach_fd_occasions_list[0].num_root_sequences.value = 16; + gNB->gNB_config.prach_config.prach_sequence_length.value = 1; + gNB->gNB_config.prach_config.num_prach_fd_occasions_list[0].k1.value = 0; + gNB->gNB_config.prach_config.restricted_set_config.value = 0; + gNB->gNB_config.tdd_table.tdd_period.value = 6; + + memcpy((void*)&ru->config,(void*)&RC.gNB[0]->gNB_config,sizeof(ru->config)); + RC.nb_nr_L1_inst=1; phy_init_nr_gNB(gNB,0,0); nr_phy_init_RU(ru); - set_tdd_config_nr(&gNB->gNB_config, 5000, + + + set_tdd_config_nr(&gNB->gNB_config, 1, 7, 6, 2, 4); @@ -481,21 +505,9 @@ int main(int argc, char **argv) gNB->common_vars.rxdata = ru->common.rxdata; - compute_nr_prach_seq(gNB->frame_parms.prach_config_common.rootSequenceIndex, - gNB->frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex, - gNB->frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig, - gNB->frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag, - gNB->frame_parms.frame_type, - gNB->frame_parms.freq_range, - gNB->X_u); + compute_nr_prach_seq(&gNB->gNB_config,0,gNB->X_u); - compute_nr_prach_seq(UE->frame_parms.prach_config_common.rootSequenceIndex, - UE->frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex, - UE->frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig, - UE->frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag, - UE->frame_parms.frame_type, - UE->frame_parms.freq_range, - UE->X_u); + compute_nr_prach_seq(&gNB->gNB_config,0,UE->X_u); @@ -517,6 +529,7 @@ int main(int argc, char **argv) subframe); */ //commented for testing purpose UE_nr_rxtx_proc_t proc={0}; + proc.frame_tx=0;proc.nr_tti_tx=subframe; nr_ue_prach_procedures(UE,&proc,0,0); /* tx_lev_dB not used later, no need to set */ @@ -526,7 +539,7 @@ int main(int argc, char **argv) //LOG_M("txsig1.m","txs1", txdata[1],FRAME_LENGTH_COMPLEX_SAMPLES,1,1); // multipath channel - dump_nr_prach_config(&gNB->frame_parms,subframe); + // dump_nr_prach_config(&gNB->frame_parms,subframe); for (i=0; isamples_per_slot<<1; i++) { for (aa=0; aa<1; aa++) { @@ -589,18 +602,26 @@ int main(int argc, char **argv) } uint16_t preamble_rx; rx_nr_prach_ru(ru, + 1, 0, - subframe); + 0, + 0, + subframe<<1); gNB->prach_vars.rxsigF = ru->prach_rxsigF; + + nfapi_nr_prach_pdu_t prach_pdu; + prach_pdu.num_cs = 34; + prach_pdu.prach_format = 1; // A2 + rx_nr_prach(gNB, + &prach_pdu, 0, - subframe, + subframe<<1, &preamble_rx, &preamble_energy, &preamble_delay); - printf("preamble_rx %d\n", preamble_rx); - if (preamble_rx!=preamble_tx) + if (preamble_rx!=preamble_tx) prach_errors++; else { delay_avg += (double)preamble_delay; diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c index eaaa47df25..f928aeb572 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -600,4 +600,4 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, } prach_resources = NULL; return; -} \ No newline at end of file +} diff --git a/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c b/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c index f0ba789266..20864ccc97 100644 --- a/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c +++ b/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c @@ -134,4 +134,4 @@ uint16_t nr_ue_process_rar(module_id_t mod_id, memcpy((void *) (selected_rar_buffer + 1), (void *) rar, sizeof(NR_MAC_RAR)); return ta_command; -} \ No newline at end of file +} From 669ba2fafe2777e803eb2890a23318ff2f1239eb Mon Sep 17 00:00:00 2001 From: Cedric Roux Date: Wed, 19 Feb 2020 14:29:42 +0100 Subject: [PATCH 054/553] minor typo fix --- openair1/PHY/NR_TRANSPORT/nr_prach.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index 991084c485..388b721c46 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -360,7 +360,7 @@ void rx_nr_prach_ru(RU_t *ru, } else { if ((mu==0 && (prachStartSymbol == 0 || prachStartSymbol == 7)) || - (mu==1 && prachStartSymbol == 0)) prach2+=48; // 24 samples @ 43.08 Ms/s in first symbol of each half subframe (15/30 kHz only) + (mu==1 && prachStartSymbol == 0)) prach2+=48; // 24 samples @ 46.08 Ms/s in first symbol of each half subframe (15/30 kHz only) if (mu==0) AssertFatal(1==0,"Shouldn't get here\n"); else if (mu==1) { dftlen=1536; From eb18a90b7f2cef8d060ebcb7d420ae9c5375c653 Mon Sep 17 00:00:00 2001 From: Cedric Roux Date: Wed, 19 Feb 2020 14:37:07 +0100 Subject: [PATCH 055/553] bugfix: correct X_u computation for both 839 and 139 cases --- openair1/PHY/NR_TRANSPORT/nr_prach_common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c index b55501cc84..e881b91b84 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c @@ -157,8 +157,8 @@ void compute_nr_prach_seq(nfapi_nr_config_request_scf_t *config, // for the unrestricted case X_u[0] is the first root indicated by the rootSequenceIndex for (k=0; k Date: Fri, 21 Feb 2020 16:40:15 +0100 Subject: [PATCH 056/553] scheduling of msg2 and filling of fapi structures --- openair1/PHY/CODING/coding_defs.h | 1 + openair1/PHY/NR_TRANSPORT/nr_prach.c | 3 +- openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c | 2 +- .../PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c | 6 +- openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c | 1 + openair1/SCHED_NR/fapi_nr_l1.c | 2 +- openair1/SCHED_NR/nr_prach_procedures.c | 4 +- openair1/SCHED_NR/phy_procedures_nr_gNB.c | 4 +- openair1/SIMULATION/NR_PHY/dlschsim.c | 2 +- openair1/SIMULATION/NR_PHY/ulschsim.c | 2 +- openair1/SIMULATION/NR_PHY/ulsim.c | 2 +- openair2/GNB_APP/RRC_nr_paramsvalues.h | 2 +- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 4 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 124 +----- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 404 +++++++++++++----- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 18 +- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 262 +++++++----- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 28 +- .../LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c | 3 +- openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 6 +- openair2/NR_PHY_INTERFACE/NR_IF_Module.c | 2 + openair2/RRC/NR/rrc_gNB_reconfig.c | 93 ++-- .../CONF/gnb.band78.tm1.106PRB.usrpn300.conf | 8 +- .../CONF/gnb.band78.tm1.106PRB.usrpx300.conf | 7 +- .../CONF/gnb.band78.tm1.217PRB.usrpn300.conf | 7 +- .../CONF/gnb.band78.tm1.217PRB.usrpx300.conf | 7 +- .../CONF/gnb.band78.tm1.273PRB.usrpn300.conf | 7 +- 27 files changed, 583 insertions(+), 428 deletions(-) diff --git a/openair1/PHY/CODING/coding_defs.h b/openair1/PHY/CODING/coding_defs.h index 9b111309cd..da19ec40e2 100644 --- a/openair1/PHY/CODING/coding_defs.h +++ b/openair1/PHY/CODING/coding_defs.h @@ -463,6 +463,7 @@ uint32_t nr_compute_tbs(uint16_t Qm, uint16_t nb_symb_sch, uint16_t nb_dmrs_prb, uint16_t nb_rb_oh, + uint8_t tb_scaling, uint8_t Nl); uint32_t nr_compute_tbslbrm(uint16_t table, diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index 991084c485..4d6ded65a7 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -197,7 +197,6 @@ void rx_nr_prach_ru(RU_t *ru, ru->idx,frame,slot,prachfmt[prachFormat],msg1_frequencystart,prachStartSymbol); switch (prachFormat) { - AssertFatal(prachFormat<4,"Illegal prach format %d for length 139 (combined formats not supported yet)\n",prachFormat); case 0: //A1 Ncp = 288/(1<X_u[preamble_offset-first_nonzero_root_idx]; - LOG_D(PHY,"PRACH RX new dft preamble_offset-first_nonzero_root_idx %d\n",preamble_index,preamble_offset-first_nonzero_root_idx); + LOG_D(PHY,"PRACH RX new dft preamble_offset-first_nonzero_root_idx %d\n",preamble_offset-first_nonzero_root_idx); memset(prach_ifft,0,((N_ZC==839) ? 2048 : 256)*sizeof(int32_t)); diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c index 60dbf107e6..ca39b82edf 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c @@ -364,7 +364,7 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, } // harq_process->trials[nfapi_ulsch_pdu_rel15->round]++; - harq_process->TBS = nr_compute_tbs(Qm, R, nb_rb, number_symbols, nb_re_dmrs*length_dmrs, 0, n_layers); + harq_process->TBS = nr_compute_tbs(Qm, R, nb_rb, number_symbols, nb_re_dmrs*length_dmrs, 0, 0, n_layers); A = harq_process->TBS; ret = ulsch->max_ldpc_iterations + 1; diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c index 177640bacc..2f6f593bd6 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c @@ -319,7 +319,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, uint16_t nb_rb_oh = 0; // it was not computed at UE side even before and set to 0 in nr_compute_tbs - harq_process->TBS = nr_compute_tbs(harq_process->Qm,harq_process->R,nb_rb,nb_symb_sch,nb_re_dmrs*dmrs_length, nb_rb_oh, harq_process->Nl); + harq_process->TBS = nr_compute_tbs(harq_process->Qm,harq_process->R,nb_rb,nb_symb_sch,nb_re_dmrs*dmrs_length, nb_rb_oh, 0, harq_process->Nl); A = harq_process->TBS; ret = dlsch->max_ldpc_iterations + 1; @@ -858,7 +858,7 @@ uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue, uint16_t nb_rb_oh = 0; // it was not computed at UE side even before and set to 0 in nr_compute_tbs - harq_process->TBS = nr_compute_tbs(harq_process->Qm,harq_process->R,nb_rb,nb_symb_sch,nb_re_dmrs*length_dmrs, nb_rb_oh, harq_process->Nl); + harq_process->TBS = nr_compute_tbs(harq_process->Qm,harq_process->R,nb_rb,nb_symb_sch,nb_re_dmrs*length_dmrs, nb_rb_oh, 0, harq_process->Nl); A = harq_process->TBS; @@ -1431,7 +1431,7 @@ void nr_dlsch_decoding_process(void *arg) uint16_t nb_rb_oh = 0; // it was not computed at UE side even before and set to 0 in nr_compute_tbs - harq_process->TBS = nr_compute_tbs(harq_process->Qm,harq_process->R,nb_rb,nb_symb_sch,nb_re_dmrs*length_dmrs, nb_rb_oh, harq_process->Nl); + harq_process->TBS = nr_compute_tbs(harq_process->Qm,harq_process->R,nb_rb,nb_symb_sch,nb_re_dmrs*length_dmrs, nb_rb_oh, 0, harq_process->Nl); A = harq_process->TBS; //2072 for QPSK 1/3 diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c index dfdce058d8..51b101f47d 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c @@ -155,6 +155,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, harq_process_ul_ue->number_of_symbols, ulsch_ue->nb_re_dmrs*ulsch_ue->length_dmrs, 0, + 0, harq_process_ul_ue->Nl); //-----------------------------------------------------// diff --git a/openair1/SCHED_NR/fapi_nr_l1.c b/openair1/SCHED_NR/fapi_nr_l1.c index 354b32d0a0..33743104d2 100644 --- a/openair1/SCHED_NR/fapi_nr_l1.c +++ b/openair1/SCHED_NR/fapi_nr_l1.c @@ -149,7 +149,7 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){ uint8_t number_ul_dci_pdu = (UL_dci_req==NULL) ? 0 : UL_dci_req->numPdus; uint8_t number_ul_tti_pdu = (UL_tti_req==NULL) ? 0 : UL_tti_req->n_pdus; - LOG_D(PHY,"NFAPI: Sched_INFO:SFN/SLOT:%04d%d DL_req:SFN/SLO:%04d%d:dl_pdu:%d tx_req:SFN/SLOT:%04d%d:pdus:%d;ul_dci %d ul_tti %d\n", + LOG_D(PHY,"NFAPI: Sched_INFO:SFN/SLOT:%04d/%d DL_req:SFN/SLO:%04d/%d:dl_pdu:%d tx_req:SFN/SLOT:%04d/%d:pdus:%d;ul_dci %d ul_tti %d\n", frame,slot, DL_req->SFN,DL_req->Slot,number_dl_pdu, TX_req->SFN,TX_req->Slot,TX_req->Number_of_PDUs, diff --git a/openair1/SCHED_NR/nr_prach_procedures.c b/openair1/SCHED_NR/nr_prach_procedures.c index 6e60ead21d..855da5ac8a 100644 --- a/openair1/SCHED_NR/nr_prach_procedures.c +++ b/openair1/SCHED_NR/nr_prach_procedures.c @@ -116,9 +116,9 @@ void L1_nr_prach_procedures(PHY_VARS_gNB *gNB,int frame,int slot, gNB->UL_INFO.rach_ind.slot = slot; gNB->prach_pdu_indication_list[0].phy_cell_id = gNB->gNB_config.cell_config.phy_cell_id.value; - gNB->prach_pdu_indication_list[0].symbol_index = prach_pdu->prach_start_symbol; + gNB->prach_pdu_indication_list[0].symbol_index = prach_pdu->prach_start_symbol; // FIXME to be changed for multi-ssb (this is only the start symbol of first occasion) gNB->prach_pdu_indication_list[0].slot_index = slot; - gNB->prach_pdu_indication_list[0].freq_index = 0; // single frequency for now + gNB->prach_pdu_indication_list[0].freq_index = prach_pdu->num_ra; gNB->prach_pdu_indication_list[0].avg_rssi = (max_preamble_energy[0]<631) ? (128+(max_preamble_energy[0]/5)) : 254; gNB->prach_pdu_indication_list[0].avg_snr = 0xff; // invalid for now diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index d3b393ad26..61f2a8a1c9 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -160,7 +160,7 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB, if (gNB->pdcch_pdu || gNB->ul_dci_pdu) { - LOG_D(PHY, "[gNB %d] Frame %d slot %d Calling nr_generate_dci_top (number of UL/DL DCI %d/%d)\n", + LOG_I(PHY, "[gNB %d] Frame %d slot %d Calling nr_generate_dci_top (number of UL/DL DCI %d/%d)\n", gNB->Mod_id, frame, slot, gNB->ul_dci_pdu==NULL?0:gNB->ul_dci_pdu->pdcch_pdu.pdcch_pdu_rel15.numDlDci, gNB->pdcch_pdu==NULL?0:gNB->pdcch_pdu->pdcch_pdu_rel15.numDlDci); @@ -176,9 +176,9 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB, VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_PDCCH_TX,0); } - LOG_D(PHY, "PDSCH generation started (%d)\n", gNB->num_pdsch_rnti); for (int i=0; inum_pdsch_rnti; i++) { VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_GENERATE_DLSCH,1); + LOG_I(PHY, "PDSCH generation started (%d)\n", gNB->num_pdsch_rnti); nr_generate_pdsch(gNB->dlsch[i][0], gNB->nr_gold_pdsch_dmrs[slot], gNB->common_vars.txdataF, diff --git a/openair1/SIMULATION/NR_PHY/dlschsim.c b/openair1/SIMULATION/NR_PHY/dlschsim.c index 80b26c0bbd..8bfec90d13 100644 --- a/openair1/SIMULATION/NR_PHY/dlschsim.c +++ b/openair1/SIMULATION/NR_PHY/dlschsim.c @@ -442,7 +442,7 @@ int main(int argc, char **argv) mod_order = nr_get_Qm_dl(Imcs, mcs_table); rate = nr_get_code_rate_dl(Imcs, mcs_table); available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, 1); - TBS = nr_compute_tbs(mod_order,rate, nb_rb, nb_symb_sch, nb_re_dmrs*length_dmrs, 0, Nl); + TBS = nr_compute_tbs(mod_order,rate, nb_rb, nb_symb_sch, nb_re_dmrs*length_dmrs, 0, 0, Nl); printf("available bits %u TBS %u mod_order %d\n", available_bits, TBS, mod_order); //dlsch->harq_ids[subframe]= 0; rel15->rbSize = nb_rb; diff --git a/openair1/SIMULATION/NR_PHY/ulschsim.c b/openair1/SIMULATION/NR_PHY/ulschsim.c index 56e6e9936c..f6b7adb3ec 100644 --- a/openair1/SIMULATION/NR_PHY/ulschsim.c +++ b/openair1/SIMULATION/NR_PHY/ulschsim.c @@ -391,7 +391,7 @@ int main(int argc, char **argv) mod_order = nr_get_Qm_ul(Imcs, 0); code_rate = nr_get_code_rate_ul(Imcs, 0); available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, 1); - TBS = nr_compute_tbs(mod_order,code_rate, nb_rb, nb_symb_sch, nb_re_dmrs*length_dmrs, 0, Nl); + TBS = nr_compute_tbs(mod_order,code_rate, nb_rb, nb_symb_sch, nb_re_dmrs*length_dmrs, 0, 0, Nl); printf("\nAvailable bits %u TBS %u mod_order %d\n", available_bits, TBS, mod_order); diff --git a/openair1/SIMULATION/NR_PHY/ulsim.c b/openair1/SIMULATION/NR_PHY/ulsim.c index e53e288602..79e6f940ea 100644 --- a/openair1/SIMULATION/NR_PHY/ulsim.c +++ b/openair1/SIMULATION/NR_PHY/ulsim.c @@ -570,7 +570,7 @@ int main(int argc, char **argv) nb_re_dmrs = ((UE->dmrs_UplinkConfig.pusch_dmrs_type == pusch_dmrs_type1) ? 6 : 4) * number_dmrs_symbols; code_rate = nr_get_code_rate_ul(Imcs, 0); available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, 1); - TBS = nr_compute_tbs(mod_order, code_rate, nb_rb, nb_symb_sch, nb_re_dmrs*length_dmrs, 0, precod_nbr_layers); + TBS = nr_compute_tbs(mod_order, code_rate, nb_rb, nb_symb_sch, nb_re_dmrs*length_dmrs, 0, 0, precod_nbr_layers); printf("\n"); diff --git a/openair2/GNB_APP/RRC_nr_paramsvalues.h b/openair2/GNB_APP/RRC_nr_paramsvalues.h index f94990d4d8..fc90b93169 100644 --- a/openair2/GNB_APP/RRC_nr_paramsvalues.h +++ b/openair2/GNB_APP/RRC_nr_paramsvalues.h @@ -246,7 +246,7 @@ {GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_0,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[0]->startSymbolAndLength,defint64val:-1,TYPE_INT64,0/*17*/},\ {GNB_CONFIG_STRING_INITIALDLBWPK0_1,NULL,0,i64ptr:scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[1]->k0,defint64val:-1,TYPE_INT64,0/*18*/},\ {GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_1,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[1]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA,TYPE_INT64,0/*19*/},\ -{GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_0,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[1]->startSymbolAndLength,defint64val:53,TYPE_INT64,0/*20*/}, \ +{GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_1,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[1]->startSymbolAndLength,defint64val:53,TYPE_INT64,0/*20*/}, \ {GNB_CONFIG_STRING_INITIALDLBWPK0_2,NULL,0,i64ptr:scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[2]->k0,defint64val:-1,TYPE_INT64,0/*21*/},\ {GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_2,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[2]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA,TYPE_INT64,0/*22*/},\ {GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_2,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[2]->startSymbolAndLength,defint64val:54,TYPE_INT64,0/*23*/},\ diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index f6fac735dd..73051df613 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -1381,7 +1381,8 @@ int32_t get_nr_uldl_offset(int nr_bandP) void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, - int x_overhead) { + int x_overhead, + uint8_t tb_scaling) { LOG_D(MAC, "TBS calculation\n"); @@ -1411,6 +1412,7 @@ void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, N_sh_symb, N_PRB_DMRS, N_PRB_oh, + tb_scaling, pdsch_rel15->nrOfLayers)>>3; pdsch_rel15->targetCodeRate[0] = R; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index d599bc6df7..3a7648149f 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -264,122 +264,6 @@ void schedule_nr_SRS(module_id_t module_idP, frame_t frameP, sub_frame_t subfram */ -void schedule_nr_prach(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) { - - gNB_MAC_INST *gNB = RC.nrmac[module_idP]; - NR_COMMON_channels_t *cc = gNB->common_channels; - NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; - nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[module_idP]->UL_tti_req[0]; - - uint8_t config_index = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.prach_ConfigurationIndex; - uint8_t mu,N_dur,N_t_slot,start_symbol; - uint16_t format; - - if (scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing) - mu = *scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing; - else - mu = scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing; - - // prach is scheduled according to configuration index and tables 6.3.3.2.2 to 6.3.3.2.4 - if ( get_nr_prach_info_from_index(config_index, - (int)frameP, - (int)slotP, - scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA, - mu, - cc->frame_type, - &format, - &start_symbol, - &N_t_slot, - &N_dur) ) { - - int fdm = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FDM; - uint16_t format0 = format&0xff; // first column of format from table - uint16_t format1 = (format>>8)&0xff; // second column of format from table - - UL_tti_req->SFN = frameP; - UL_tti_req->Slot = slotP; - for (int n=0; n<(1<pdus_list[UL_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PRACH_PDU_TYPE; - UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_size = sizeof(nfapi_nr_prach_pdu_t); - nfapi_nr_prach_pdu_t *prach_pdu = &UL_tti_req->pdus_list[UL_tti_req->n_pdus].prach_pdu; - memset(prach_pdu,0,sizeof(nfapi_nr_prach_pdu_t)); - UL_tti_req->n_pdus+=1; - - // filling the prach fapi structure - prach_pdu->phys_cell_id = *scc->physCellId; - prach_pdu->num_prach_ocas = N_t_slot; - prach_pdu->prach_start_symbol = start_symbol; - prach_pdu->num_ra = n; - prach_pdu->num_cs = get_NCS(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.zeroCorrelationZoneConfig, - format0, - scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig); - // SCF PRACH PDU format field does not consider A1/B1 etc. possibilities - // We added 9 = A1/B1 10 = A2/B2 11 A3/B3 - if (format1!=0xff) { - switch(format0) { - case 0xa1: - prach_pdu->prach_format = 9; - break; - case 0xa2: - prach_pdu->prach_format = 10; - break; - case 0xa3: - prach_pdu->prach_format = 10; - break; - default: - AssertFatal(1==0,"Only formats A1/B1 A2/B2 A3/B3 are valid for dual format"); - } - } - else{ - switch(format0) { - case 0xa1: - prach_pdu->prach_format = 0; - break; - case 0xa2: - prach_pdu->prach_format = 1; - break; - case 0xa3: - prach_pdu->prach_format = 2; - break; - case 0xb1: - prach_pdu->prach_format = 3; - break; - case 0xb2: - prach_pdu->prach_format = 4; - break; - case 0xb3: - prach_pdu->prach_format = 5; - break; - case 0xb4: - prach_pdu->prach_format = 6; - break; - case 0xc0: - prach_pdu->prach_format = 7; - break; - case 0xc2: - prach_pdu->prach_format = 8; - break; - case 0: - // long formats are handled @ PHY - break; - case 1: - // long formats are handled @ PHY - break; - case 2: - // long formats are handled @ PHY - break; - case 3: - // long formats are handled @ PHY - break; - default: - AssertFatal(1==0,"Invalid PRACH format"); - } - } - } - } -} - - /* void copy_nr_ulreq(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) { @@ -483,10 +367,12 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, gNB->ta_len = 2; } + if (is_nr_DL_slot(cc->ServingCellConfigCommon,slot_rxP)) + nr_schedule_RA(module_idP, frame_txP, slot_txP); + // Phytest scheduling if (phy_test && slot_txP==1){ - nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP,NULL); - //nr_schedule_RA(module_idP, frame_txP, slot_txP); + //nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP,NULL); // resetting ta flag gNB->ta_len = 0; } @@ -504,7 +390,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, schedule_nr_prach(module_idP, (frame_rxP+1)&1023, slot_rxP); if (phy_test && slot_rxP==8){ - nr_schedule_uss_ulsch_phytest(module_idP, frame_rxP, slot_rxP); + //nr_schedule_uss_ulsch_phytest(module_idP, frame_rxP, slot_rxP); } } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index ac8c6ec1a7..c75b4698bb 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -42,66 +42,252 @@ #include "SIMULATION/TOOLS/sim.h" // for taus extern RAN_CONTEXT_t RC; +uint16_t nr_slots_per_frame[5] = {10, 20, 40, 80, 160}; -void nr_add_subframe(uint16_t *frameP, uint16_t *slotP, int offset){ - *frameP = (*frameP + ((*slotP + offset) / 10)) % 1024; - *slotP = ((*slotP + offset) % 10); +void schedule_nr_prach(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) { + + gNB_MAC_INST *gNB = RC.nrmac[module_idP]; + NR_COMMON_channels_t *cc = gNB->common_channels; + NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; + nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[module_idP]->UL_tti_req[0]; + + uint8_t config_index = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.prach_ConfigurationIndex; + uint8_t mu,N_dur,N_t_slot,start_symbol; + uint16_t format; + + if (scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing) + mu = *scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing; + else + mu = scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing; + + // prach is scheduled according to configuration index and tables 6.3.3.2.2 to 6.3.3.2.4 + if ( get_nr_prach_info_from_index(config_index, + (int)frameP, + (int)slotP, + scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA, + mu, + cc->frame_type, + &format, + &start_symbol, + &N_t_slot, + &N_dur) ) { + + int fdm = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FDM; + uint16_t format0 = format&0xff; // first column of format from table + uint16_t format1 = (format>>8)&0xff; // second column of format from table + + UL_tti_req->SFN = frameP; + UL_tti_req->Slot = slotP; + for (int n=0; n<(1<pdus_list[UL_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PRACH_PDU_TYPE; + UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_size = sizeof(nfapi_nr_prach_pdu_t); + nfapi_nr_prach_pdu_t *prach_pdu = &UL_tti_req->pdus_list[UL_tti_req->n_pdus].prach_pdu; + memset(prach_pdu,0,sizeof(nfapi_nr_prach_pdu_t)); + UL_tti_req->n_pdus+=1; + + // filling the prach fapi structure + prach_pdu->phys_cell_id = *scc->physCellId; + prach_pdu->num_prach_ocas = N_t_slot; + prach_pdu->prach_start_symbol = start_symbol; + prach_pdu->num_ra = n; + prach_pdu->num_cs = get_NCS(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.zeroCorrelationZoneConfig, + format0, + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig); + // SCF PRACH PDU format field does not consider A1/B1 etc. possibilities + // We added 9 = A1/B1 10 = A2/B2 11 A3/B3 + if (format1!=0xff) { + switch(format0) { + case 0xa1: + prach_pdu->prach_format = 9; + break; + case 0xa2: + prach_pdu->prach_format = 10; + break; + case 0xa3: + prach_pdu->prach_format = 10; + break; + default: + AssertFatal(1==0,"Only formats A1/B1 A2/B2 A3/B3 are valid for dual format"); + } + } + else{ + switch(format0) { + case 0xa1: + prach_pdu->prach_format = 0; + break; + case 0xa2: + prach_pdu->prach_format = 1; + break; + case 0xa3: + prach_pdu->prach_format = 2; + break; + case 0xb1: + prach_pdu->prach_format = 3; + break; + case 0xb2: + prach_pdu->prach_format = 4; + break; + case 0xb3: + prach_pdu->prach_format = 5; + break; + case 0xb4: + prach_pdu->prach_format = 6; + break; + case 0xc0: + prach_pdu->prach_format = 7; + break; + case 0xc2: + prach_pdu->prach_format = 8; + break; + case 0: + // long formats are handled @ PHY + break; + case 1: + // long formats are handled @ PHY + break; + case 2: + // long formats are handled @ PHY + break; + case 3: + // long formats are handled @ PHY + break; + default: + AssertFatal(1==0,"Invalid PRACH format"); + } + } + } + } } -// WIP -// handles the event of msg1 reception -// todo: -// - offset computation -// - fix nr_add_subframe -// - msg2 time location + +void nr_schedule_msg2(uint16_t rach_frame, uint16_t rach_slot, + uint16_t *msg2_frame, uint16_t *msg2_slot, + NR_ServingCellConfigCommon_t *scc, + uint16_t monitoring_slot_period, + uint16_t monitoring_offset){ + + // preferentially we schedule the msg2 in the mixed slot or in the last dl slot + // if they are allowed by search space configuration + + uint8_t mu = *scc->ssbSubcarrierSpacing; + uint8_t response_window = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.ra_ResponseWindow; + uint8_t slot_window; + // number of mixed slot or of last dl slot if there is no mixed slot + uint8_t last_dl_slot_period = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots; + // lenght of tdd period in slots + uint8_t tdd_period_slot = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots + scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots; + if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSymbols == 0) + last_dl_slot_period--; + if ((scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSymbols > 0) || (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols > 0)) + tdd_period_slot++; + + // computing start of next period + uint8_t start_next_period = (rach_slot-(rach_slot%tdd_period_slot)+tdd_period_slot)%nr_slots_per_frame[mu]; + *msg2_slot = start_next_period + last_dl_slot_period; // initializing scheduling of slot to next mixed (or last dl) slot + *msg2_frame = (*msg2_slot>(rach_slot))? rach_frame : (rach_frame +1); + + switch(response_window){ + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl1: + slot_window = 1; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl2: + slot_window = 2; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl4: + slot_window = 4; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl8: + slot_window = 8; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl10: + slot_window = 10; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl20: + slot_window = 20; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl40: + slot_window = 40; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl80: + slot_window = 80; + break; + default: + AssertFatal(1==0,"Invalid response window value %d\n",response_window); + } + AssertFatal(slot_window<=nr_slots_per_frame[mu],"Msg2 response window needs to be lower or equal to 10ms"); + + // slot and frame limit to transmit msg2 according to response window + uint8_t slot_limit = (rach_slot + slot_window)%nr_slots_per_frame[mu]; + uint8_t frame_limit = (slot_limit>(rach_slot))? rach_frame : (rach_frame +1); + + // go to previous slot if the current scheduled slot is beyond the response window + // and if the slot is not among the PDCCH monitored ones (38.213 10.1) + while ((*msg2_slot>slot_limit) || ((*msg2_frame*nr_slots_per_frame[mu]+*msg2_slot-monitoring_offset)%monitoring_slot_period !=0)) { + if((*msg2_slot%tdd_period_slot) > 0) + *msg2_slot--; + else + AssertFatal(1==0,"No available DL slot to schedule msg2 has been found"); + } +} + + void nr_initiate_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP, uint16_t preamble_index, + uint8_t freq_index, + uint8_t symbol, int16_t timing_offset){ - uint16_t ra_rnti=157; - uint16_t msg2_frame = frameP, msg2_slot = slotP; - int offset; + uint8_t ul_carrier_id = 0; // 0 for NUL 1 for SUL + NR_SearchSpace_t *ss; + + // ra_rnti from 5.1.3 in 38.321 + uint16_t ra_rnti=1+symbol+(slotP*14)+(freq_index*14*80)+(ul_carrier_id*14*80*8); + int bwp_id=1; + + uint16_t msg2_frame, msg2_slot,monitoring_slot_period,monitoring_offset; gNB_MAC_INST *nr_mac = RC.nrmac[module_idP]; + NR_UE_list_t *UE_list = &nr_mac->UE_list; + NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[0]; NR_COMMON_channels_t *cc = &nr_mac->common_channels[CC_id]; + NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; + NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; NR_RA_t *ra = &cc->ra[0]; - static uint8_t failure_cnt = 0; VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_INITIATE_RA_PROC, 1); - LOG_D(MAC, "[gNB %d][RAPROC] CC_id %d Frame %d, Subframe %d Initiating RA procedure for preamble index %d\n", module_idP, CC_id, frameP, slotP, preamble_index); + LOG_I(MAC, "[gNB %d][RAPROC] CC_id %d Frame %d, Subframe %d Initiating RA procedure for preamble index %d\n", module_idP, CC_id, frameP, slotP, preamble_index); if (ra->state == RA_IDLE) { int loop = 0; LOG_D(MAC, "Frame %d, Subframe %d: Activating RA process \n", frameP, slotP); ra->state = Msg2; ra->timing_offset = timing_offset; - ra->preamble_subframe = slotP; + ra->preamble_slot = slotP; - // if(cc->tdd_Config!=NULL){ - // switch(cc->tdd_Config->subframeAssignment){ - // default: printf("%s:%d: TODO\n", __FILE__, __LINE__); abort(); - // case 1 : - // offset = 6; - // break; - // } - // }else{//FDD - // // DJP - this is because VNF is 2 subframes ahead of PNF and TX needs 4 subframes - // if (nfapi_mode) - // offset = 7; - // else - // offset = 5; - // } + struct NR_PDCCH_ConfigCommon__commonSearchSpaceList *commonSearchSpaceList = bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList; + AssertFatal(commonSearchSpaceList->list.count>0, + "common SearchSpace list has 0 elements\n"); + // Common searchspace list + for (int i=0;ilist.count;i++) { + ss=commonSearchSpaceList->list.array[i]; + if(ss->searchSpaceId == *bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace) + ra->ra_ss=ss; + } - nr_add_subframe(&msg2_frame, &msg2_slot, offset); + // retrieving ra pdcch monitoring period and offset + find_monitoring_periodicity_offset_common(ra->ra_ss, + &monitoring_slot_period, + &monitoring_offset); + + nr_schedule_msg2(frameP, slotP, &msg2_frame, &msg2_slot, scc, monitoring_slot_period, monitoring_offset); ra->Msg2_frame = msg2_frame; ra->Msg2_slot = msg2_slot; - // ra->Msg2_slot = (slotP + offset) % 10; - LOG_D(MAC, "%s() Msg2[%04d%d] SFN/SF:%04d%d offset:%d\n", __FUNCTION__, ra->Msg2_frame, ra->Msg2_slot, frameP, slotP, offset); + LOG_D(MAC, "%s() Msg2[%04d%d] SFN/SF:%04d%d\n", __FUNCTION__, ra->Msg2_frame, ra->Msg2_slot, frameP, slotP); do { ra->rnti = (taus() % 65518) + 1; @@ -115,26 +301,19 @@ void nr_initiate_ra_proc(module_id_t module_idP, ra->RA_rnti = ra_rnti; ra->preamble_index = preamble_index; - failure_cnt = 0; - LOG_D(MAC, "[gNB %d][RAPROC] CC_id %d Frame %d Activating Msg2 generation in frame %d, slot %d for rnti %x\n", + LOG_I(MAC,"[gNB %d][RAPROC] CC_id %d Frame %d Activating Msg2 generation in frame %d, slot %d using RA rnti %x\n", module_idP, CC_id, frameP, ra->Msg2_frame, ra->Msg2_slot, - ra->state); + ra->RA_rnti); return; } LOG_E(MAC, "[gNB %d][RAPROC] FAILURE: CC_id %d Frame %d initiating RA procedure for preamble index %d\n", module_idP, CC_id, frameP, preamble_index); - failure_cnt++; - - if(failure_cnt > 20) { - LOG_E(MAC,"[gNB %d][RAPROC] CC_id %d Frame %d Clear Random access information\n", module_idP, CC_id, frameP); - nr_clear_ra_proc(module_idP, CC_id, frameP); - } VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_INITIATE_RA_PROC, 0); } @@ -152,14 +331,14 @@ void nr_schedule_RA(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ LOG_D(MAC,"RA[state:%d]\n",ra->state); switch (ra->state){ case Msg2: - //nr_generate_Msg2(module_idP, CC_id, frameP, slotP); - break; + nr_generate_Msg2(module_idP, CC_id, frameP, slotP); + break; case Msg4: - //generate_Msg4(module_idP, CC_id, frameP, slotP, ra); - break; + //generate_Msg4(module_idP, CC_id, frameP, slotP, ra); + break; case WAIT_Msg4_ACK: - //check_Msg4_retransmission(module_idP, CC_id, frameP, slotP, ra); - break; + //check_Msg4_retransmission(module_idP, CC_id, frameP, slotP, ra); + break; default: break; } @@ -167,6 +346,20 @@ void nr_schedule_RA(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ stop_meas(&mac->schedule_ra); } +void nr_get_Msg3alloc(NR_ServingCellConfigCommon_t *scc, + sub_frame_t current_slot, + frame_t current_frame, + NR_RA_t *ra) { + + // first simple version to schedule msg3 + // it is schedulend in mixed slot in the following frame + ra->Msg3_frame = current_frame+1; + ra->Msg3_slot = current_slot; + ra->msg3_nb_rb = 6; + ra->msg3_first_rb = 0; + +} + // WIP // todo: fix void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP){ @@ -176,30 +369,20 @@ void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; NR_RA_t *ra = &cc->ra[0]; NR_UE_list_t *UE_list = &mac->UE_list; - nfapi_nr_ul_tti_request_t *ul_req = &mac->UL_tti_req[0]; - nfapi_nr_ul_dci_request_t *UL_dci_req = &mac->UL_dci_req[0]; - nfapi_nr_pusch_pdu_t *pusch_pdu = &ul_req->pdus_list[0].pusch_pdu; - nfapi_nr_ul_dci_request_pdus_t *ul_dci_request_pdu = &UL_dci_req->ul_dci_pdu_list[UL_dci_req->numPdus]; - int UE_id = 0, CCEIndex, dci_formats[2], rnti_types[2], bwp_id = 1, coreset_id = 0, aggregation = 4, search_space = 1; + int UE_id = 0, bwp_id = 1; AssertFatal(ra->state != RA_IDLE, "RA is not active for RA %X\n", ra->rnti); LOG_D(MAC, "[gNB %d][RAPROC] Frame %d, Subframe %d : CC_id %d RA is active, Msg3 in (%d,%d)\n", module_idP, frameP, slotP, CC_id, ra->Msg3_frame, ra->Msg3_slot); - - ul_req->SFN = ra->Msg3_frame << 4 | ra->Msg3_slot; - ul_req->Slot = slotP; - ul_req->n_pdus = 1; - ul_req->pdus_list[0].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE; - ul_req->pdus_list[0].pdu_size = sizeof(nfapi_nr_pusch_pdu_t); + ul_req->SFN = ra->Msg3_frame; + ul_req->Slot = ra->Msg3_slot; + ul_req->pdus_list[ul_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE; + ul_req->pdus_list[ul_req->n_pdus].pdu_size = sizeof(nfapi_nr_pusch_pdu_t); + nfapi_nr_pusch_pdu_t *pusch_pdu = &ul_req->pdus_list[ul_req->n_pdus].pusch_pdu; memset(pusch_pdu, 0, sizeof(nfapi_nr_pusch_pdu_t)); - - memset((void*)ul_dci_request_pdu,0,sizeof(nfapi_nr_ul_dci_request_pdus_t)); - ul_dci_request_pdu->PDUType = NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE; - ul_dci_request_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdcch_pdu)); - - nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &ul_dci_request_pdu->pdcch_pdu.pdcch_pdu_rel15; + ul_req->n_pdus+=1; AssertFatal(UE_list->active[UE_id] >=0,"Cannot find UE_id %d is not active\n", UE_id); @@ -245,8 +428,8 @@ void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t //pusch_pdu->tx_direct_current_location;//The uplink Tx Direct Current location for the carrier. Only values in the value range of this field between 0 and 3299, which indicate the subcarrier index within the carrier corresponding 1o the numerology of the corresponding uplink BWP and value 3300, which indicates "Outside the carrier" and value 3301, which indicates "Undetermined position within the carrier" are used. [TS38.331, UplinkTxDirectCurrentBWP IE] pusch_pdu->uplink_frequency_shift_7p5khz = 0; //Resource Allocation in time domain - pusch_pdu->start_symbol_index = 2; - pusch_pdu->nr_of_symbols = 12; + pusch_pdu->start_symbol_index = 12; + pusch_pdu->nr_of_symbols = 2; //Optional Data only included if indicated in pduBitmap pusch_pdu->pusch_data.rv_index = 0; pusch_pdu->pusch_data.harq_process_id = 0; @@ -257,21 +440,9 @@ void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t pusch_pdu->nr_of_symbols, 6, //nb_re_dmrs - not sure where this is coming from - its not in the FAPI 0, //nb_rb_oh + 0, // to verify tb scaling pusch_pdu->nrOfLayers = 1); pusch_pdu->pusch_data.num_cb = 0; - - CCEIndex = allocate_nr_CCEs(mac, bwp_id, coreset_id, aggregation, search_space, UE_id, 0); - AssertFatal(CCEIndex >= 0, "CCEIndex is negative\n"); - pdcch_pdu_rel15->dci_pdu.CceIndex[pdcch_pdu_rel15->numDlDci] = CCEIndex; - LOG_D(PHY, "CCEIndex %d\n", pdcch_pdu_rel15->dci_pdu.CceIndex[pdcch_pdu_rel15->numDlDci]); - - LOG_D(MAC,"Configuring ULDCI/PDCCH in %d.%d\n", frameP,slotP); - nr_configure_pdcch(pdcch_pdu_rel15, 1, scc, bwp); - - dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET]; - config_uldci(ubwp, pusch_pdu, pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); - pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[0] = nr_dci_size(dci_formats[0], rnti_types[0], pdcch_pdu_rel15->BWPSize); - fill_dci_pdu_rel15(pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); } // WIP @@ -283,13 +454,14 @@ void nr_generate_Msg2(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ - int UE_id = 0, dci_formats[2], rnti_types[2], CCEIndex, dlBWP_carrier_bandwidth, mcsIndex = 9; - int startSymbolAndLength = 0, StartSymbolIndex = -1, NrOfSymbols = 14, StartSymbolIndex_tmp, NrOfSymbols_tmp, x_Overhead, time_domain_assignment = 2; - int bwp_id = 1, coreset_id = 0, aggregation = 4, search_space = 0, N_RB_UL = 106; + int UE_id = 0, dci_formats[2], rnti_types[2], CCEIndex, dlBWP_carrier_bandwidth, mcsIndex; + int startSymbolAndLength = 0, StartSymbolIndex = -1, NrOfSymbols = 14, StartSymbolIndex_tmp, NrOfSymbols_tmp, x_Overhead, time_domain_assignment; + int bwp_id = 1, coreset_id, aggregation , search_space_type = 0, N_RB_UL = 106; gNB_MAC_INST *nr_mac = RC.nrmac[module_idP]; NR_COMMON_channels_t *cc = &nr_mac->common_channels[0]; NR_RA_t *ra = &cc->ra[0]; NR_UE_list_t *UE_list = &nr_mac->UE_list; + NR_SearchSpace_t *ss = ra->ra_ss; uint16_t rnti = ra->rnti, RA_rnti = ra->RA_rnti, numDlDci; long locationAndBandwidth; @@ -315,17 +487,20 @@ void nr_generate_Msg2(module_id_t module_idP, nfapi_nr_dl_dci_pdu_t *dci_pdu = &pdcch_pdu_rel15->dci_pdu; numDlDci = pdcch_pdu_rel15->numDlDci; + aggregation = find_aggregation_level(ss); + coreset_id = *ss->controlResourceSetId; + // Checking if the DCI allocation is feasible in current subframe if (dl_req->nPDUs == NFAPI_NR_MAX_DL_TTI_PDUS) { LOG_I(MAC, "[RAPROC] Subframe %d: FAPI DL structure is full, skip scheduling UE %d\n", slotP, RA_rnti); return; } else { LOG_D(MAC, "[RAPROC] Subframe %d: Checking CCE feasibility format : (%x,%d) \n", slotP, RA_rnti, aggregation); - CCEIndex = allocate_nr_CCEs(nr_mac, bwp_id, coreset_id, aggregation, search_space, UE_id, 0); - AssertFatal(CCEIndex > 0,"CCEIndex is negative\n"); + CCEIndex = allocate_nr_CCEs(nr_mac, bwp_id, coreset_id, aggregation, search_space_type, UE_id, 0); + AssertFatal(CCEIndex >= 0,"CCEIndex is negative %d\n",CCEIndex); } - LOG_D(MAC,"[gNB %d] [RAPROC] CC_id %d Frame %d, slotP %d: Generating RAR DCI, state %d\n", module_idP, CC_id, frameP, slotP, ra->state); + LOG_I(MAC,"[gNB %d] [RAPROC] CC_id %d Frame %d, slotP %d: Generating RAR DCI, state %d\n", module_idP, CC_id, frameP, slotP, ra->state); NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; locationAndBandwidth = scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth; @@ -338,8 +513,10 @@ void nr_generate_Msg2(module_id_t module_idP, LOG_D(MAC, "[RAPROC] Scheduling common search space DCI type 1 dlBWP BW.firstRB %d.%d\n", dlBWP_carrier_bandwidth, NRRIV2PRBOFFSET(locationAndBandwidth, 275)); + mcsIndex = 0; // Qm>2 not allowed for RAR + pdsch_pdu_rel15->pduBitmap = 0; - pdsch_pdu_rel15->rnti = rnti; + pdsch_pdu_rel15->rnti = RA_rnti; pdsch_pdu_rel15->pduIndex = 0; pdsch_pdu_rel15->BWPSize = NRRIV2BW(locationAndBandwidth,275); pdsch_pdu_rel15->BWPStart = NRRIV2PRBOFFSET(locationAndBandwidth,275); @@ -363,7 +540,7 @@ void nr_generate_Msg2(module_id_t module_idP, pdsch_pdu_rel15->resourceAlloc = 1; pdsch_pdu_rel15->rbStart = 0; pdsch_pdu_rel15->rbSize = 6; - pdsch_pdu_rel15->VRBtoPRBMapping = 1; + pdsch_pdu_rel15->VRBtoPRBMapping = 0; // non interleaved for (int i=0; idownlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count; i++) { startSymbolAndLength = scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->startSymbolAndLength; @@ -371,34 +548,27 @@ void nr_generate_Msg2(module_id_t module_idP, if (NrOfSymbols_tmp < NrOfSymbols) { NrOfSymbols = NrOfSymbols_tmp; StartSymbolIndex = StartSymbolIndex_tmp; + time_domain_assignment = i; // this is short PDSCH added to the config to fit mixed slot } } AssertFatal(StartSymbolIndex >= 0, "StartSymbolIndex is negative\n"); + pdsch_pdu_rel15->StartSymbolIndex = StartSymbolIndex; pdsch_pdu_rel15->NrOfSymbols = NrOfSymbols; pdsch_pdu_rel15->dlDmrsSymbPos = fill_dmrs_mask(NULL, scc->dmrs_TypeA_Position, NrOfSymbols); + dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET]; dci_pdu_rel15[0].frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize, pdsch_pdu_rel15->rbStart, NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth, 275)); dci_pdu_rel15[0].time_domain_assignment = time_domain_assignment; - dci_pdu_rel15[0].vrb_to_prb_mapping = 1; + dci_pdu_rel15[0].vrb_to_prb_mapping = 0; dci_pdu_rel15[0].mcs = pdsch_pdu_rel15->mcsIndex[0]; dci_pdu_rel15[0].tb_scaling = 1; - dci_pdu_rel15[0].frequency_hopping_flag = 0; - dci_pdu_rel15[0].ra_preamble_index = ra->preamble_index; - dci_pdu_rel15[0].format_indicator = 1; - dci_pdu_rel15[0].ndi = 1; - dci_pdu_rel15[0].rv = 0; - dci_pdu_rel15[0].harq_pid = 0; - dci_pdu_rel15[0].dai = 2; - dci_pdu_rel15[0].tpc = 2; - dci_pdu_rel15[0].pucch_resource_indicator = 7; - dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator = 7; - LOG_D(MAC, "[RAPROC] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n", + LOG_D(MAC, "[RAPROC] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d \n", dci_pdu_rel15[0].frequency_domain_assignment, pdsch_pdu_rel15->rbStart, pdsch_pdu_rel15->rbSize, @@ -406,19 +576,20 @@ void nr_generate_Msg2(module_id_t module_idP, dci_pdu_rel15[0].time_domain_assignment, dci_pdu_rel15[0].vrb_to_prb_mapping, dci_pdu_rel15[0].mcs, - dci_pdu_rel15[0].tb_scaling, - dci_pdu_rel15[0].ndi, - dci_pdu_rel15[0].rv); + dci_pdu_rel15[0].tb_scaling); - nr_configure_pdcch(pdcch_pdu_rel15, 0, scc, bwp); + nr_configure_pdcch(pdcch_pdu_rel15, 0, ss, scc, bwp); LOG_D(MAC, "Frame %d: Subframe %d : Adding common DL DCI for RA_RNTI %x CCEIndex %d\n", frameP, slotP, RA_rnti, CCEIndex); - dci_pdu->RNTI[numDlDci] = RA_rnti; - dci_pdu->AggregationLevel[numDlDci] = aggregation; - dci_pdu->powerControlOffsetSS[numDlDci] = 0; - dci_pdu->CceIndex[numDlDci] = CCEIndex; - dci_pdu->beta_PDCCH_1_0[numDlDci] = 0; - dci_pdu->powerControlOffsetSS[numDlDci] = 1; + + dci_pdu->RNTI[numDlDci] = RA_rnti; + dci_pdu->ScramblingId[numDlDci] = *scc->physCellId; + dci_pdu->ScramblingRNTI[numDlDci] = 0; + dci_pdu->AggregationLevel[numDlDci] = aggregation; + dci_pdu->powerControlOffsetSS[numDlDci] = 0; + dci_pdu->CceIndex[numDlDci] = CCEIndex; + dci_pdu->beta_PDCCH_1_0[numDlDci] = 0; + dci_pdu->powerControlOffsetSS[numDlDci] = 1; dci_formats[0] = NR_DL_DCI_FORMAT_1_0; rnti_types[0] = NR_RNTI_RA; @@ -434,18 +605,19 @@ void nr_generate_Msg2(module_id_t module_idP, dci_pdu->PayloadSizeBits[0] = nr_dci_size(dci_formats[0], rnti_types[0], pdcch_pdu_rel15->BWPSize); fill_dci_pdu_rel15(pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); pdcch_pdu_rel15->numDlDci++; - dl_req->nPDUs++; + + dl_req->nPDUs+=2; // Program UL processing for Msg3 - // nr_get_Msg3alloc(&cc[CC_id], slotP, frameP,&ra->Msg3_frame, &ra->Msg3_slot); // todo - LOG_D(MAC, "Frame %d, Subframe %d: Setting Msg3 reception for Frame %d Subframe %d\n", frameP, slotP, ra->Msg3_frame, ra->Msg3_slot); - nr_fill_rar(module_idP, ra, cc[CC_id].RAR_pdu.payload, N_RB_UL); + nr_get_Msg3alloc(scc, slotP, frameP, ra); + LOG_I(MAC, "Frame %d, Subframe %d: Setting Msg3 reception for Frame %d Subframe %d\n", frameP, slotP, ra->Msg3_frame, ra->Msg3_slot); nr_add_msg3(module_idP, CC_id, frameP, slotP); + nr_fill_rar(module_idP, ra, cc[CC_id].RAR_pdu.payload, N_RB_UL); ra->state = WAIT_Msg3; LOG_D(MAC,"[gNB %d][RAPROC] Frame %d, Subframe %d: RA state %d\n", module_idP, frameP, slotP, ra->state); x_Overhead = 0; - nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead); + nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead, dci_pdu_rel15[0].tb_scaling); // DL TX request tx_req->PDU_length = pdsch_pdu_rel15->TBSize[0]; @@ -507,7 +679,7 @@ void nr_fill_rar(uint8_t Mod_idP, LOG_D(MAC, "[gNB] Generate RAR MAC PDU frame %d slot %d ", ra->Msg2_frame, ra-> Msg2_slot); nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[Mod_idP]->UL_tti_req[0]; - nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[0].pusch_pdu; + nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[UL_tti_req->n_pdus-1].pusch_pdu; NR_RA_HEADER_RAPID *rarh = (NR_RA_HEADER_RAPID *) dlsch_buffer; NR_MAC_RAR *rar = (NR_MAC_RAR *) (dlsch_buffer + 1); unsigned char frequency_hopping_flag = 0, csi_req = 0, tpc_command = 0, mcs = 9, t_alloc = 0; @@ -554,4 +726,4 @@ void nr_fill_rar(uint8_t Mod_idP, rar->UL_GRANT_3 = (uint8_t) (ul_grant >> 8) & 0xff; rar->UL_GRANT_4 = (uint8_t) ul_grant & 0xff; -} \ No newline at end of file +} diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 9345705f3f..f1916a9f67 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -272,6 +272,13 @@ int configure_fapi_dl_pdu(int Mod_idP, secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count); NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; + AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n"); + AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0, + "searchPsacesToAddModList is empty\n"); + NR_SearchSpace_t *ss; + // TO BE FIXED we are just selecting the first search space here (only one is configured) + ss=bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[0]; + dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs]; memset((void*)dl_tti_pdcch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t)); @@ -369,6 +376,7 @@ int configure_fapi_dl_pdu(int Mod_idP, nr_configure_pdcch(pdcch_pdu_rel15, 1, // ue-specific + ss, scc, bwp); @@ -398,7 +406,7 @@ int configure_fapi_dl_pdu(int Mod_idP, pdcch_pdu_rel15->DurationSymbols); int x_Overhead = 0; // should be 0 for initialBWP - nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead); + nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead,0); // Hardcode it for now TBS = dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15.TBSize[0]; @@ -710,6 +718,12 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[Mod_idP]->UL_tti_req[0]; nfapi_nr_ul_dci_request_t *UL_dci_req = &RC.nrmac[Mod_idP]->UL_dci_req[0]; + AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n"); + AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0, + "searchPsacesToAddModList is empty\n"); + NR_SearchSpace_t *ss; + // TO BE FIXED we are just selecting the first search space here (only one is configured) + ss=bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[0]; uint16_t rnti = UE_list->rnti[UE_id]; nfapi_nr_ul_dci_request_pdus_t *ul_dci_request_pdu; @@ -784,6 +798,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, pusch_pdu->nr_of_symbols, 6, //nb_re_dmrs - not sure where this is coming from - its not in the FAPI 0, //nb_rb_oh + 0, pusch_pdu->nrOfLayers = 1); pusch_pdu->pusch_data.num_cb = 0; //CBG not supported //pusch_pdu->pusch_data.cb_present_and_position; @@ -816,6 +831,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, LOG_D(MAC,"Configuring ULDCI/PDCCH in %d.%d\n", frameP,slotP); nr_configure_pdcch(pdcch_pdu_rel15, 1, // ue-specific, + ss, scc, bwp); diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index ef2a2d9318..7e92748c83 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -131,14 +131,33 @@ static inline uint8_t get_max_cces(uint8_t scs) { return (nr_max_number_of_cces_per_slot[scs]); } +int find_aggregation_level (NR_SearchSpace_t *ss){ + + int level = 0; + + if( ss->nrofCandidates->aggregationLevel1 != NR_SearchSpace__nrofCandidates__aggregationLevel1_n0) + level = 1; + if( ss->nrofCandidates->aggregationLevel2 != NR_SearchSpace__nrofCandidates__aggregationLevel2_n0) + level = 2; + if( ss->nrofCandidates->aggregationLevel4 != NR_SearchSpace__nrofCandidates__aggregationLevel4_n0) + level = 4; + if( ss->nrofCandidates->aggregationLevel8 != NR_SearchSpace__nrofCandidates__aggregationLevel8_n0) + level = 8; + if( ss->nrofCandidates->aggregationLevel16 != NR_SearchSpace__nrofCandidates__aggregationLevel16_n0) + level = 16; + + AssertFatal(level!=0,"Unable to find aggregation level"); + return level; + +} + int allocate_nr_CCEs(gNB_MAC_INST *nr_mac, int bwp_id, int coreset_id, int aggregation, int search_space, // 0 common, 1 ue-specific int UE_id, - int m - ) { + int m) { // uncomment these when we allocate for common search space // NR_COMMON_channels_t *cc = nr_mac->common_channels; // NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; @@ -150,14 +169,15 @@ int allocate_nr_CCEs(gNB_MAC_INST *nr_mac, NR_ControlResourceSet_t *coreset; + AssertFatal(UE_list->active[UE_id] >=0,"UE_id %d is not active\n",UE_id); + secondaryCellGroup = UE_list->secondaryCellGroup[UE_id]; + bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; + if (search_space == 1) { - AssertFatal(UE_list->active[UE_id] >=0,"UE_id %d is not active\n",UE_id); - secondaryCellGroup = UE_list->secondaryCellGroup[UE_id]; - bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; coreset = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[coreset_id]; } else { - AssertFatal(1==0,"Add code for common search space\n"); + coreset = bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet; } int *cce_list = nr_mac->cce_list[bwp_id][coreset_id]; @@ -413,63 +433,75 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, int ss_type, + NR_SearchSpace_t *ss, NR_ServingCellConfigCommon_t *scc, NR_BWP_Downlink_t *bwp){ + NR_ControlResourceSet_t *coreset = NULL; + if (bwp) { // This is not the InitialBWP - /// coreset - - //ControlResourceSetId - // pdcch_pdu->config_type = NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG; - AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList!=NULL, - "controlResourceSetToAddModList is null\n"); - AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.count>0, - "controlResourceSetToAddModList is empty\n"); - NR_ControlResourceSet_t *coreset0 = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[0]; - + NR_ControlResourceSet_t *temp_coreset; + NR_ControlResourceSetId_t coresetid = *ss->controlResourceSetId; + if (ss_type == 0) { // common search space + if (coresetid == 0){ + AssertFatal(1==0,"coreset0 currently not supported\n"); + } + else { + coreset = bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet; + AssertFatal(coresetid==coreset->controlResourceSetId,"ID of common ss coreset does not correspond to id set in the search space\n"); + } + } + else { + int n_list = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.count; + for (int i=0; ibwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[i]; + if (coresetid==temp_coreset->controlResourceSetId) { + coreset = temp_coreset; + break; + } + } + if(coreset==NULL) + AssertFatal(1==0,"Couldn't find coreset with id %ld\n",coresetid); + } pdcch_pdu->BWPSize = NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275); pdcch_pdu->BWPStart = NRRIV2PRBOFFSET(bwp->bwp_Common->genericParameters.locationAndBandwidth,275); pdcch_pdu->SubcarrierSpacing = bwp->bwp_Common->genericParameters.subcarrierSpacing; pdcch_pdu->CyclicPrefix = (bwp->bwp_Common->genericParameters.cyclicPrefix==NULL) ? 0 : *bwp->bwp_Common->genericParameters.cyclicPrefix; - pdcch_pdu->DurationSymbols = coreset0->duration; + + // first symbol + //AssertFatal(pdcch_scs==kHz15, "PDCCH SCS above 15kHz not allowed if a symbol above 2 is monitored"); + int sps = bwp->bwp_Common->genericParameters.cyclicPrefix == NULL ? 14 : 12; + + AssertFatal(ss->monitoringSymbolsWithinSlot!=NULL,"ss->monitoringSymbolsWithinSlot is null\n"); + AssertFatal(ss->monitoringSymbolsWithinSlot->buf!=NULL,"ss->monitoringSymbolsWithinSlot->buf is null\n"); - //frequencyDomainResources - /* uint8_t count=0, start=0, start_set=0; - // find coreset descriptor + // for SPS=14 8 MSBs in positions 13 downto 6 + uint16_t monitoringSymbolsWithinSlot = (ss->monitoringSymbolsWithinSlot->buf[0]<<(sps-8)) | + (ss->monitoringSymbolsWithinSlot->buf[1]>>(16-sps)); + + for (int i=0; i>(sps-1-i))&1) { + pdcch_pdu->StartSymbolIndex=i; + break; + } + } + + pdcch_pdu->DurationSymbols = coreset->duration; - uint64_t bitmap = (((uint64_t)coreset0->frequencyDomainResources.buf[0])<<37)| - (((uint64_t)coreset0->frequencyDomainResources.buf[1])<<29)| - (((uint64_t)coreset0->frequencyDomainResources.buf[2])<<21)| - (((uint64_t)coreset0->frequencyDomainResources.buf[3])<<13)| - (((uint64_t)coreset0->frequencyDomainResources.buf[4])<<5)| - (((uint64_t)coreset0->frequencyDomainResources.buf[5])>>3); - - for (int i=0; i<45; i++) - if ((bitmap>>(44-i))&1) { - count++; - if (!start_set) { - start = i; - start_set = 1; - } - } - pdcch_pdu->rb_offset = 6*start; - pdcch_pdu->n_rb = 6*count; - */ for (int i=0;i<6;i++) - pdcch_pdu->FreqDomainResource[i] = coreset0->frequencyDomainResources.buf[i]; - //duration - + pdcch_pdu->FreqDomainResource[i] = coreset->frequencyDomainResources.buf[i]; //cce-REG-MappingType - pdcch_pdu->CceRegMappingType = coreset0->cce_REG_MappingType.present == NR_ControlResourceSet__cce_REG_MappingType_PR_interleaved? + pdcch_pdu->CceRegMappingType = coreset->cce_REG_MappingType.present == NR_ControlResourceSet__cce_REG_MappingType_PR_interleaved? NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED : NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED; + if (pdcch_pdu->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) { - pdcch_pdu->RegBundleSize = (coreset0->cce_REG_MappingType.choice.interleaved->reg_BundleSize == NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n6) ? 6 : (2+coreset0->cce_REG_MappingType.choice.interleaved->reg_BundleSize); - pdcch_pdu->InterleaverSize = (coreset0->cce_REG_MappingType.choice.interleaved->interleaverSize==NR_ControlResourceSet__cce_REG_MappingType__interleaved__interleaverSize_n6) ? 6 : (2+coreset0->cce_REG_MappingType.choice.interleaved->interleaverSize); + pdcch_pdu->RegBundleSize = (coreset->cce_REG_MappingType.choice.interleaved->reg_BundleSize == NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n6) ? 6 : (2+coreset->cce_REG_MappingType.choice.interleaved->reg_BundleSize); + pdcch_pdu->InterleaverSize = (coreset->cce_REG_MappingType.choice.interleaved->interleaverSize==NR_ControlResourceSet__cce_REG_MappingType__interleaved__interleaverSize_n6) ? 6 : (2+coreset->cce_REG_MappingType.choice.interleaved->interleaverSize); AssertFatal(scc->physCellId != NULL,"scc->physCellId is null\n"); - pdcch_pdu->ShiftIndex = coreset0->cce_REG_MappingType.choice.interleaved->shiftIndex != NULL ? *coreset0->cce_REG_MappingType.choice.interleaved->shiftIndex : *scc->physCellId; + pdcch_pdu->ShiftIndex = coreset->cce_REG_MappingType.choice.interleaved->shiftIndex != NULL ? *coreset->cce_REG_MappingType.choice.interleaved->shiftIndex : *scc->physCellId; } else { pdcch_pdu->RegBundleSize = 0; @@ -480,65 +512,16 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, pdcch_pdu->CoreSetType = 1; //precoderGranularity - pdcch_pdu->precoderGranularity = coreset0->precoderGranularity; + pdcch_pdu->precoderGranularity = coreset->precoderGranularity; - //TCI states - // - /* - //TCI present - if (coreset0->tci_PresentInDCI != NULL) { - AssertFatal(coreset0->tci_StatesPDCCH_ToAddList != NULL,"tci_StatesPDCCH_ToAddList is null\n"); - AssertFatal(coreset0->tci_StatesPDCCH_ToAddList->list.count>0,"TCI state list is empty\n"); - for (int i=0;itci_StatesPDCCH_ToAddList->list.count;i++) { - - } - */ - - for (int i=0;inumDlDci;i++) { - //pdcch-DMRS-ScramblingID - AssertFatal(coreset0->pdcch_DMRS_ScramblingID != NULL,"coreset0->pdcch_DMRS_ScramblingID is null\n"); - pdcch_pdu->dci_pdu.ScramblingId[i] = *coreset0->pdcch_DMRS_ScramblingID; - } - - /// SearchSpace - - // first symbol - //AssertFatal(pdcch_scs==kHz15, "PDCCH SCS above 15kHz not allowed if a symbol above 2 is monitored"); - int sps = bwp->bwp_Common->genericParameters.cyclicPrefix == NULL ? 14 : 12; - - AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n"); - AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0, - "searchPsacesToAddModList is empty\n"); - NR_SearchSpace_t *ss; - int found=0; - int target_ss = NR_SearchSpace__searchSpaceType_PR_common; - if (ss_type == 1) { - target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific; - } - - for (int i=0;ibwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count;i++) { - ss=bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[i]; - AssertFatal(ss->controlResourceSetId != NULL,"ss->controlResourceSetId is null\n"); - AssertFatal(ss->searchSpaceType != NULL,"ss->searchSpaceType is null\n"); - if (*ss->controlResourceSetId == coreset0->controlResourceSetId && - ss->searchSpaceType->present == target_ss) { - found=1; - break; + if (ss_type) { + for (int i=0;inumDlDci;i++) { + //pdcch-DMRS-ScramblingID + AssertFatal(coreset->pdcch_DMRS_ScramblingID != NULL,"coreset0->pdcch_DMRS_ScramblingID is null\n"); + pdcch_pdu->dci_pdu.ScramblingId[i] = *coreset->pdcch_DMRS_ScramblingID; } } - AssertFatal(found==1,"Couldn't find a searchspace corresponding to coreset0\n"); - AssertFatal(ss->monitoringSymbolsWithinSlot!=NULL,"ss->monitoringSymbolsWithinSlot is null\n"); - AssertFatal(ss->monitoringSymbolsWithinSlot->buf!=NULL,"ss->monitoringSymbolsWithinSlot->buf is null\n"); - - // for SPS=14 8 MSBs in positions 13 downto 6, - uint16_t monitoringSymbolsWithinSlot = (ss->monitoringSymbolsWithinSlot->buf[0]<<(sps-8)) | - (ss->monitoringSymbolsWithinSlot->buf[1]>>(16-sps)); - - for (int i=0; i>(sps-1-i))&1) { - pdcch_pdu->StartSymbolIndex=i; - break; - } + } else { // this is for InitialBWP @@ -1060,6 +1043,81 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){ return -1; } + +void find_monitoring_periodicity_offset_common(NR_SearchSpace_t *ss, + uint16_t *slot_period, + uint16_t *offset) { + + + switch(ss->monitoringSlotPeriodicityAndOffset->present) { + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1: + *slot_period = 1; + *offset = 0; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl2: + *slot_period = 2; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl2; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl4: + *slot_period = 4; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl4; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl5: + *slot_period = 5; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl5; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl8: + *slot_period = 8; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl8; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl10: + *slot_period = 10; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl10; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl16: + *slot_period = 16; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl16; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl20: + *slot_period = 20; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl20; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl40: + *slot_period = 40; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl40; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl80: + *slot_period = 80; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl80; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl160: + *slot_period = 160; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl160; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl320: + *slot_period = 320; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl320; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl640: + *slot_period = 640; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl640; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1280: + *slot_period = 1280; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl1280; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl2560: + *slot_period = 2560; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl2560; + break; + default: + AssertFatal(1==0,"Invalid monitoring slot periodicity and offset value\n"); + break; + } +} + + + /*void fill_nfapi_coresets_and_searchspaces(NR_CellGroupConfig_t *cg, nfapi_nr_coreset_t *coreset, nfapi_nr_search_space_t *search_space) { @@ -1362,4 +1420,4 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){ } } } -*/ \ No newline at end of file +*/ diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index 90d617d7e9..c25ce20331 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -89,18 +89,17 @@ void nr_schedule_RA(module_id_t module_idP, frame_t frameP, sub_frame_t slotP); @param rnti RA rnti corresponding to this PRACH preamble @param rach_resource type (0=non BL/CE,1 CE level 0,2 CE level 1, 3 CE level 2,4 CE level 3) */ -void nr_initiate_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP, - uint16_t preamble_index, int16_t timing_offset); +void nr_initiate_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP, + uint16_t preamble_index, uint8_t freq_index, uint8_t symbol, int16_t timing_offset); void nr_clear_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP); int nr_allocate_CCEs(int module_idP, int CC_idP, frame_t frameP, sub_frame_t slotP, int test_only); -void nr_get_Msg3alloc(NR_COMMON_channels_t *cc, +void nr_get_Msg3alloc(NR_ServingCellConfigCommon_t *scc, sub_frame_t current_subframe, - frame_t current_frame, - frame_t *frame, - sub_frame_t *subframe); + frame_t current_frame, + NR_RA_t *ra); /* \brief Function in gNB to fill RAR pdu when requested by PHY. @param ra Instance of RA resources of gNB @@ -113,6 +112,8 @@ void nr_fill_rar(uint8_t Mod_idP, uint16_t N_RB_UL); +void schedule_nr_prach(module_id_t module_idP, frame_t frameP, sub_frame_t slotP); + uint16_t nr_mac_compute_RIV(uint16_t N_RB_DL, uint16_t RBstart, uint16_t Lcrbs); /////// Phy test scheduler /////// @@ -168,6 +169,7 @@ int nr_is_dci_opportunity(nfapi_nr_search_space_t search_space, void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, int ss_type, + NR_SearchSpace_t *ss, NR_ServingCellConfigCommon_t *scc, NR_BWP_Downlink_t *bwp); @@ -181,7 +183,8 @@ int get_spf(nfapi_nr_config_request_scf_t *cfg); int to_absslot(nfapi_nr_config_request_scf_t *cfg,int frame,int slot); void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, - int x_overhead); + int x_overhead, + uint8_t tb_scaling); /** \brief Computes Q based on I_MCS PDSCH and table_idx for downlink. Implements MCS Tables from 38.214. */ uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx); uint32_t nr_get_code_rate_dl(uint8_t Imcs, uint8_t table_idx); @@ -236,6 +239,17 @@ void config_nr_mib(int Mod_idP, int cellBarred, int intraFreqReselection); +void nr_generate_Msg2(module_id_t module_idP, + int CC_id, + frame_t frameP, + sub_frame_t slotP); + +int find_aggregation_level (NR_SearchSpace_t *ss); + +void find_monitoring_periodicity_offset_common(NR_SearchSpace_t *ss, + uint16_t *slot_period, + uint16_t *offset); + /* \brief Function to indicate a received SDU on ULSCH. @param Mod_id Instance ID of gNB @param CC_id Component carrier index diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c b/openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c index e4e3ac05df..df23b64e07 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c +++ b/openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c @@ -39,6 +39,7 @@ uint32_t nr_compute_tbs(uint16_t Qm, uint16_t nb_symb_sch, uint16_t nb_dmrs_prb, uint16_t nb_rb_oh, + uint8_t tb_scaling, uint8_t Nl) { @@ -54,7 +55,7 @@ uint32_t nr_compute_tbs(uint16_t Qm, scale = (R>1024)?11:10; // Intermediate number of information bits - Ninfo = (nb_re * R * Qm * Nl)>>scale; + Ninfo = ((nb_re * R * Qm * Nl)>>scale)>>tb_scaling; if (Ninfo <=3824) { n = max(3, floor(log2(Ninfo)) - 6); diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index cdb11a7aa3..977da561f8 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -87,8 +87,8 @@ typedef enum { typedef struct { /// Flag to indicate this process is active RA_state_t state; - /// Subframe where preamble was received - uint8_t preamble_subframe; + /// Slot where preamble was received + uint8_t preamble_slot; /// Subframe where Msg2 is to be sent uint8_t Msg2_slot; /// Frame where Msg2 is to be sent @@ -133,6 +133,8 @@ typedef struct { int msg4_TBsize; /// MCS used for Msg4 int msg4_mcs; + /// RA search space + NR_SearchSpace_t *ra_ss; } NR_RA_t; /*! \brief gNB common channels */ diff --git a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c index 8a0763daca..6ad19882e8 100644 --- a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c @@ -68,6 +68,8 @@ void handle_nr_rach(NR_UL_IND_t *UL_info) { UL_info->rach_ind.sfn, UL_info->rach_ind.slot, UL_info->rach_ind.pdu_list[0].preamble_list[0].preamble_index, + UL_info->rach_ind.pdu_list[0].freq_index, + UL_info->rach_ind.pdu_list[0].symbol_index, UL_info->rach_ind.pdu_list[0].preamble_list[0].timing_advance); } diff --git a/openair2/RRC/NR/rrc_gNB_reconfig.c b/openair2/RRC/NR/rrc_gNB_reconfig.c index 6d52f47a18..0dc0e83bd6 100644 --- a/openair2/RRC/NR/rrc_gNB_reconfig.c +++ b/openair2/RRC/NR/rrc_gNB_reconfig.c @@ -405,17 +405,45 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco bwp->bwp_Common->pdcch_ConfigCommon->present = NR_SetupRelease_PDCCH_ConfigCommon_PR_setup; bwp->bwp_Common->pdcch_ConfigCommon->choice.setup = calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup)); bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->controlResourceSetZero=NULL; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet=NULL; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->searchSpaceZero=NULL; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet)); + NR_ControlResourceSet_t *coreset = calloc(1,sizeof(*coreset)); + coreset->controlResourceSetId=1; + // frequencyDomainResources '11111111 11111111 00000000 00000000 00000000 00000'B, + coreset->frequencyDomainResources.buf = calloc(1,6); + coreset->frequencyDomainResources.buf[0] = 0xff; + coreset->frequencyDomainResources.buf[1] = 0xff; + coreset->frequencyDomainResources.buf[2] = 0; + coreset->frequencyDomainResources.buf[3] = 0; + coreset->frequencyDomainResources.buf[4] = 0; + coreset->frequencyDomainResources.buf[5] = 0; + coreset->frequencyDomainResources.size = 6; + coreset->frequencyDomainResources.bits_unused = 3; + coreset->duration=1; + coreset->cce_REG_MappingType.present = NR_ControlResourceSet__cce_REG_MappingType_PR_nonInterleaved; + coreset->precoderGranularity = NR_ControlResourceSet__precoderGranularity_sameAsREG_bundle; + + coreset->tci_StatesPDCCH_ToAddList=calloc(1,sizeof(*coreset->tci_StatesPDCCH_ToAddList)); + NR_TCI_StateId_t *tci[8]; + for (int i=0;i<8;i++) { + tci[i]=calloc(1,sizeof(*tci[i])); + *tci[i] = i; + ASN_SEQUENCE_ADD(&coreset->tci_StatesPDCCH_ToAddList->list,tci[i]); + } + coreset->tci_StatesPDCCH_ToReleaseList = NULL; + coreset->tci_PresentInDCI = NULL; + coreset->pdcch_DMRS_ScramblingID = NULL; + + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet = coreset; + + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->searchSpaceZero=NULL; bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList=NULL; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList)); NR_SearchSpace_t *ss=calloc(1,sizeof(*ss)); ss->searchSpaceId = 1; ss->controlResourceSetId=calloc(1,sizeof(*ss->controlResourceSetId)); - *ss->controlResourceSetId=0; + *ss->controlResourceSetId=1; ss->monitoringSlotPeriodicityAndOffset = calloc(1,sizeof(*ss->monitoringSlotPeriodicityAndOffset)); ss->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1; ss->duration=NULL; @@ -472,64 +500,13 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco bwp->bwp_Dedicated->pdcch_Config->present = NR_SetupRelease_PDCCH_Config_PR_setup; bwp->bwp_Dedicated->pdcch_Config->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup)); bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList)); - NR_ControlResourceSet_t *coreset0 = calloc(1,sizeof(*coreset0)); - coreset0->controlResourceSetId=1; - // frequencyDomainResources '11111111 11111111 00000000 00000000 00000000 00000'B, - coreset0->frequencyDomainResources.buf = calloc(1,6); - coreset0->frequencyDomainResources.buf[0] = 0xff; - coreset0->frequencyDomainResources.buf[1] = 0xff; - coreset0->frequencyDomainResources.buf[2] = 0; - coreset0->frequencyDomainResources.buf[3] = 0; - coreset0->frequencyDomainResources.buf[4] = 0; - coreset0->frequencyDomainResources.buf[5] = 0; - coreset0->frequencyDomainResources.size = 6; - coreset0->frequencyDomainResources.bits_unused = 3; - coreset0->duration=1; - coreset0->cce_REG_MappingType.present = NR_ControlResourceSet__cce_REG_MappingType_PR_nonInterleaved; - coreset0->precoderGranularity = NR_ControlResourceSet__precoderGranularity_sameAsREG_bundle; - coreset0->tci_StatesPDCCH_ToAddList=calloc(1,sizeof(*coreset0->tci_StatesPDCCH_ToAddList)); - NR_TCI_StateId_t *tci[8]; - for (int i=0;i<8;i++) { - tci[i]=calloc(1,sizeof(*tci[i])); - *tci[i] = i; - ASN_SEQUENCE_ADD(&coreset0->tci_StatesPDCCH_ToAddList->list,tci[i]); - } - coreset0->tci_StatesPDCCH_ToReleaseList = NULL; - coreset0->tci_PresentInDCI = NULL; - coreset0->pdcch_DMRS_ScramblingID = NULL; ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list, - coreset0); + coreset); bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList)); - NR_SearchSpace_t *ss3 = calloc(1,sizeof(*ss3)); + NR_SearchSpace_t *ss2 = calloc(1,sizeof(*ss2)); - ss3->searchSpaceId=3; - ss3->controlResourceSetId=calloc(1,sizeof(*ss3->controlResourceSetId)); - *ss3->controlResourceSetId=1; - ss3->monitoringSlotPeriodicityAndOffset=calloc(1,sizeof(*ss3->monitoringSlotPeriodicityAndOffset)); - ss3->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1; - ss3->monitoringSlotPeriodicityAndOffset->choice.sl1=(NULL_t)0; - ss3->duration=NULL; - ss3->monitoringSymbolsWithinSlot = calloc(1,sizeof(*ss3->monitoringSymbolsWithinSlot)); - ss3->monitoringSymbolsWithinSlot->buf = calloc(1,2); - ss3->monitoringSymbolsWithinSlot->size = 2; - ss3->monitoringSymbolsWithinSlot->bits_unused = 2; - ss3->monitoringSymbolsWithinSlot->buf[0]=0xc0; - ss3->monitoringSymbolsWithinSlot->buf[1]=0x0; - ss3->nrofCandidates=calloc(1,sizeof(*ss3->nrofCandidates)); - ss3->nrofCandidates->aggregationLevel1 = NR_SearchSpace__nrofCandidates__aggregationLevel1_n0; - ss3->nrofCandidates->aggregationLevel2 = NR_SearchSpace__nrofCandidates__aggregationLevel2_n0; - ss3->nrofCandidates->aggregationLevel4 = NR_SearchSpace__nrofCandidates__aggregationLevel4_n1; - ss3->nrofCandidates->aggregationLevel8 = NR_SearchSpace__nrofCandidates__aggregationLevel8_n0; - ss3->nrofCandidates->aggregationLevel16 = NR_SearchSpace__nrofCandidates__aggregationLevel16_n0; - ss3->searchSpaceType=calloc(1,sizeof(*ss3->searchSpaceType)); - ss3->searchSpaceType->present = NR_SearchSpace__searchSpaceType_PR_common; - ss3->searchSpaceType->choice.common = calloc(1,sizeof(*ss3->searchSpaceType->choice.common)); - ss3->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0=calloc(1,sizeof(*ss3->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0)); - ss3->searchSpaceType->choice.common->dci_Format2_0=NULL; - ss3->searchSpaceType->choice.common->dci_Format2_2=NULL; - ss3->searchSpaceType->choice.common->dci_Format2_3=NULL; ss2->searchSpaceId=2; ss2->controlResourceSetId=calloc(1,sizeof(*ss2->controlResourceSetId)); @@ -555,8 +532,6 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ss2->searchSpaceType->choice.ue_Specific = calloc(1,sizeof(*ss2->searchSpaceType->choice.ue_Specific)); ss2->searchSpaceType->choice.ue_Specific->dci_Formats=NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_0_And_1_0; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list, - ss3); ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list, ss2); diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf index db88115cb0..8221cdbda5 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf @@ -59,7 +59,7 @@ gNBs = #initialULBWPmappingType #0=typeA,1=typeB initialDLBWPmappingType_0 = 0; - #this is SS=2,L=3 + #this is SS=1,L=13 initialDLBWPstartSymbolAndLength_0 = 40; initialDLBWPk0_1 = 0; @@ -71,6 +71,12 @@ gNBs = initialDLBWPmappingType_2 = 0; #this is SS=1,L=12 initialDLBWPstartSymbolAndLength_2 = 54; + + initialDLBWPk0_3 = 0; + initialDLBWPmappingType_3 = 0; + #this is SS=1,L=5 + initialDLBWPstartSymbolAndLength_3 = 57; + #uplinkConfigCommon #frequencyInfoUL ul_frequencyBand = 78; diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpx300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpx300.conf index bd8c5740dd..688fae9b0f 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpx300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpx300.conf @@ -59,7 +59,7 @@ gNBs = #initialULBWPmappingType #0=typeA,1=typeB initialDLBWPmappingType_0 = 0; - #this is SS=2,L=3 + #this is SS=1,L=13 initialDLBWPstartSymbolAndLength_0 = 40; initialDLBWPk0_1 = 0; @@ -71,6 +71,11 @@ gNBs = initialDLBWPmappingType_2 = 0; #this is SS=1,L=12 initialDLBWPstartSymbolAndLength_2 = 54; + + initialDLBWPk0_3 = 0; + initialDLBWPmappingType_3 = 0; + #this is SS=1,L=5 + initialDLBWPstartSymbolAndLength_3 = 57; #uplinkConfigCommon #frequencyInfoUL ul_frequencyBand = 78; diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpn300.conf index 56233555c0..ae17efc9bd 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpn300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpn300.conf @@ -59,7 +59,7 @@ gNBs = #initialULBWPmappingType #0=typeA,1=typeB initialDLBWPmappingType_0 = 0; - #this is SS=2,L=3 + #this is SS=1,L=13 initialDLBWPstartSymbolAndLength_0 = 40; initialDLBWPk0_1 = 0; @@ -71,6 +71,11 @@ gNBs = initialDLBWPmappingType_2 = 0; #this is SS=1,L=12 initialDLBWPstartSymbolAndLength_2 = 54; + + initialDLBWPk0_3 = 0; + initialDLBWPmappingType_3 = 0; + #this is SS=1,L=5 + initialDLBWPstartSymbolAndLength_3 = 57; #uplinkConfigCommon #frequencyInfoUL ul_frequencyBand = 78; diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpx300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpx300.conf index ea89675006..c907dcfe8d 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpx300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpx300.conf @@ -59,7 +59,7 @@ gNBs = #initialULBWPmappingType #0=typeA,1=typeB initialDLBWPmappingType_0 = 0; - #this is SS=2,L=3 + #this is SS=1,L=13 initialDLBWPstartSymbolAndLength_0 = 40; initialDLBWPk0_1 = 0; @@ -71,6 +71,11 @@ gNBs = initialDLBWPmappingType_2 = 0; #this is SS=1,L=12 initialDLBWPstartSymbolAndLength_2 = 54; + + initialDLBWPk0_3 = 0; + initialDLBWPmappingType_3 = 0; + #this is SS=1,L=5 + initialDLBWPstartSymbolAndLength_3 = 57; #uplinkConfigCommon #frequencyInfoUL ul_frequencyBand = 78; diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.273PRB.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.273PRB.usrpn300.conf index 5c84d9879b..7c3a6e4ac0 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.273PRB.usrpn300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.273PRB.usrpn300.conf @@ -59,7 +59,7 @@ gNBs = #initialULBWPmappingType #0=typeA,1=typeB initialDLBWPmappingType_0 = 0; - #this is SS=2,L=3 + #this is SS=1,L=13 initialDLBWPstartSymbolAndLength_0 = 40; initialDLBWPk0_1 = 0; @@ -71,6 +71,11 @@ gNBs = initialDLBWPmappingType_2 = 0; #this is SS=1,L=12 initialDLBWPstartSymbolAndLength_2 = 54; + + initialDLBWPk0_3 = 0; + initialDLBWPmappingType_3 = 0; + #this is SS=1,L=5 + initialDLBWPstartSymbolAndLength_3 = 57; #uplinkConfigCommon #frequencyInfoUL ul_frequencyBand = 78; From e2ee13e9ce4910b621a734c0aa9847e5829244f6 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Mon, 24 Feb 2020 11:25:07 +0100 Subject: [PATCH 057/553] modifications for DCI size of format 1_0 for RAR and filling of FAPI for RAR according to special RAR-related configuration --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 80 ++++++++------ .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 4 +- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 11 +- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 3 +- openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 104 +++++++++--------- 5 files changed, 114 insertions(+), 88 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index c75b4698bb..95ac008b3f 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -245,7 +245,8 @@ void nr_initiate_ra_proc(module_id_t module_idP, // ra_rnti from 5.1.3 in 38.321 uint16_t ra_rnti=1+symbol+(slotP*14)+(freq_index*14*80)+(ul_carrier_id*14*80*8); - int bwp_id=1; + + uint16_t msg2_frame, msg2_slot,monitoring_slot_period,monitoring_offset; gNB_MAC_INST *nr_mac = RC.nrmac[module_idP]; @@ -253,9 +254,12 @@ void nr_initiate_ra_proc(module_id_t module_idP, NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[0]; NR_COMMON_channels_t *cc = &nr_mac->common_channels[CC_id]; NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; - NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; NR_RA_t *ra = &cc->ra[0]; + // This should be handled differently when we use the initialBWP for RA + ra->bwp_id=1; + NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[ra->bwp_id-1]; + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_INITIATE_RA_PROC, 1); LOG_I(MAC, "[gNB %d][RAPROC] CC_id %d Frame %d, Subframe %d Initiating RA procedure for preamble index %d\n", module_idP, CC_id, frameP, slotP, preamble_index); @@ -302,6 +306,7 @@ void nr_initiate_ra_proc(module_id_t module_idP, ra->RA_rnti = ra_rnti; ra->preamble_index = preamble_index; + LOG_I(MAC,"[gNB %d][RAPROC] CC_id %d Frame %d Activating Msg2 generation in frame %d, slot %d using RA rnti %x\n", module_idP, CC_id, @@ -371,7 +376,7 @@ void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t NR_UE_list_t *UE_list = &mac->UE_list; nfapi_nr_ul_tti_request_t *ul_req = &mac->UL_tti_req[0]; - int UE_id = 0, bwp_id = 1; + int UE_id = 0; AssertFatal(ra->state != RA_IDLE, "RA is not active for RA %X\n", ra->rnti); @@ -389,8 +394,8 @@ void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id]; AssertFatal(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count == 1, "downlinkBWP_ToAddModList has %d BWP!\n", secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count); - NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[bwp_id-1]; - NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; + NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[ra->bwp_id-1]; + NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[ra->bwp_id-1]; LOG_D(MAC, "Frame %d, Subframe %d Adding Msg3 UL Config Request for (%d,%d) : (%d,%d,%d) for rnti: %d\n", frameP, slotP, @@ -454,9 +459,9 @@ void nr_generate_Msg2(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ - int UE_id = 0, dci_formats[2], rnti_types[2], CCEIndex, dlBWP_carrier_bandwidth, mcsIndex; + int UE_id = 0, dci_formats[2], rnti_types[2], CCEIndex, mcsIndex; int startSymbolAndLength = 0, StartSymbolIndex = -1, NrOfSymbols = 14, StartSymbolIndex_tmp, NrOfSymbols_tmp, x_Overhead, time_domain_assignment; - int bwp_id = 1, coreset_id, aggregation , search_space_type = 0, N_RB_UL = 106; + int coreset_id, aggregation , search_space_type = 0, N_RB_UL = 106; gNB_MAC_INST *nr_mac = RC.nrmac[module_idP]; NR_COMMON_channels_t *cc = &nr_mac->common_channels[0]; NR_RA_t *ra = &cc->ra[0]; @@ -467,6 +472,20 @@ void nr_generate_Msg2(module_id_t module_idP, long locationAndBandwidth; // uint8_t *vrb_map = cc[CC_id].vrb_map, CC_id; + // check if UE is doing RA on CORESET0 , InitialBWP or configured BWP from SCD + // get the BW of the PDCCH for PDCCH size and RAR PDSCH size + + NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; + int dci10_bw; + + if (ra->coreset0_configured == 1) { + AssertFatal(1==0,"This is a standalone condition\n"); + } + else { // on configured BWP or initial LDBWP, bandwidth parameters in DCI correspond size of initialBWP + locationAndBandwidth = scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth; + dci10_bw = NRRIV2BW(locationAndBandwidth,275); + } + if ((ra->Msg2_frame == frameP) && (ra->Msg2_slot == slotP)) { nfapi_nr_dl_tti_request_body_t *dl_req = &nr_mac->DL_req[CC_id].dl_tti_request_body; @@ -496,31 +515,31 @@ void nr_generate_Msg2(module_id_t module_idP, return; } else { LOG_D(MAC, "[RAPROC] Subframe %d: Checking CCE feasibility format : (%x,%d) \n", slotP, RA_rnti, aggregation); - CCEIndex = allocate_nr_CCEs(nr_mac, bwp_id, coreset_id, aggregation, search_space_type, UE_id, 0); + CCEIndex = allocate_nr_CCEs(nr_mac, ra->bwp_id, coreset_id, aggregation, search_space_type, UE_id, 0); AssertFatal(CCEIndex >= 0,"CCEIndex is negative %d\n",CCEIndex); } LOG_I(MAC,"[gNB %d] [RAPROC] CC_id %d Frame %d, slotP %d: Generating RAR DCI, state %d\n", module_idP, CC_id, frameP, slotP, ra->state); - NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; - locationAndBandwidth = scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth; - dlBWP_carrier_bandwidth = NRRIV2BW(locationAndBandwidth,275); + // This code from this point on will not work on initialBWP or CORESET0 + AssertFatal(ra->bwp_id>0,"cannot work on initialBWP for now\n"); + NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id]; AssertFatal(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count == 1, "downlinkBWP_ToAddModList has %d BWP!\n", secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count); - NR_BWP_Downlink_t *bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id - 1]; + NR_BWP_Downlink_t *bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[ra->bwp_id - 1]; - LOG_D(MAC, "[RAPROC] Scheduling common search space DCI type 1 dlBWP BW.firstRB %d.%d\n", dlBWP_carrier_bandwidth, - NRRIV2PRBOFFSET(locationAndBandwidth, 275)); + LOG_D(MAC, "[RAPROC] Scheduling common search space DCI type 1 dlBWP BW %d\n", dci10_bw); mcsIndex = 0; // Qm>2 not allowed for RAR pdsch_pdu_rel15->pduBitmap = 0; pdsch_pdu_rel15->rnti = RA_rnti; pdsch_pdu_rel15->pduIndex = 0; - pdsch_pdu_rel15->BWPSize = NRRIV2BW(locationAndBandwidth,275); - pdsch_pdu_rel15->BWPStart = NRRIV2PRBOFFSET(locationAndBandwidth,275); - pdsch_pdu_rel15->SubcarrierSpacing = scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.subcarrierSpacing; + + pdsch_pdu_rel15->BWPSize = NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275); + pdsch_pdu_rel15->BWPStart = NRRIV2PRBOFFSET(bwp->bwp_Common->genericParameters.locationAndBandwidth,275); + pdsch_pdu_rel15->SubcarrierSpacing = bwp->bwp_Common->genericParameters.subcarrierSpacing; pdsch_pdu_rel15->CyclicPrefix = 0; pdsch_pdu_rel15->NrOfCodewords = 1; pdsch_pdu_rel15->targetCodeRate[0] = nr_get_code_rate_dl(mcsIndex,0); @@ -542,8 +561,8 @@ void nr_generate_Msg2(module_id_t module_idP, pdsch_pdu_rel15->rbSize = 6; pdsch_pdu_rel15->VRBtoPRBMapping = 0; // non interleaved - for (int i=0; idownlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count; i++) { - startSymbolAndLength = scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->startSymbolAndLength; + for (int i=0; ibwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count; i++) { + startSymbolAndLength = bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->startSymbolAndLength; SLIV2SL(startSymbolAndLength, &StartSymbolIndex_tmp, &NrOfSymbols_tmp); if (NrOfSymbols_tmp < NrOfSymbols) { NrOfSymbols = NrOfSymbols_tmp; @@ -561,22 +580,21 @@ void nr_generate_Msg2(module_id_t module_idP, dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET]; dci_pdu_rel15[0].frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize, - pdsch_pdu_rel15->rbStart, - NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth, 275)); + pdsch_pdu_rel15->rbStart,dci10_bw); dci_pdu_rel15[0].time_domain_assignment = time_domain_assignment; dci_pdu_rel15[0].vrb_to_prb_mapping = 0; dci_pdu_rel15[0].mcs = pdsch_pdu_rel15->mcsIndex[0]; dci_pdu_rel15[0].tb_scaling = 1; LOG_D(MAC, "[RAPROC] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d \n", - dci_pdu_rel15[0].frequency_domain_assignment, - pdsch_pdu_rel15->rbStart, - pdsch_pdu_rel15->rbSize, - NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275), - dci_pdu_rel15[0].time_domain_assignment, - dci_pdu_rel15[0].vrb_to_prb_mapping, - dci_pdu_rel15[0].mcs, - dci_pdu_rel15[0].tb_scaling); + dci_pdu_rel15[0].frequency_domain_assignment, + pdsch_pdu_rel15->rbStart, + pdsch_pdu_rel15->rbSize, + dci10_bw, + dci_pdu_rel15[0].time_domain_assignment, + dci_pdu_rel15[0].vrb_to_prb_mapping, + dci_pdu_rel15[0].mcs, + dci_pdu_rel15[0].tb_scaling); nr_configure_pdcch(pdcch_pdu_rel15, 0, ss, scc, bwp); @@ -602,8 +620,8 @@ void nr_generate_Msg2(module_id_t module_idP, pdcch_pdu_rel15->StartSymbolIndex, pdcch_pdu_rel15->DurationSymbols); - dci_pdu->PayloadSizeBits[0] = nr_dci_size(dci_formats[0], rnti_types[0], pdcch_pdu_rel15->BWPSize); - fill_dci_pdu_rel15(pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); + dci_pdu->PayloadSizeBits[0] = nr_dci_size(dci_formats[0], rnti_types[0], dci10_bw); + fill_dci_pdu_rel15(pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types,dci10_bw); pdcch_pdu_rel15->numDlDci++; dl_req->nPDUs+=2; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index f1916a9f67..5e54bc3a24 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -394,7 +394,7 @@ int configure_fapi_dl_pdu(int Mod_idP, rnti_types[0] = NR_RNTI_C; pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); - fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types); + fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types,pdcch_pdu_rel15->BWPSize); LOG_D(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \ coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n", @@ -846,6 +846,6 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); - fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types); + fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types,pdcch_pdu_rel15->BWPSize); } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 7e92748c83..4adc280972 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -534,10 +534,11 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, - int *rnti_types + int *rnti_types, + int N_RB ) { - uint16_t N_RB = pdcch_pdu_rel15->BWPSize; + uint8_t fsize=0, pos=0; for (int d=0;dnumDlDci;d++) { @@ -546,7 +547,9 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, AssertFatal(pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d]<=64, "DCI sizes above 64 bits not yet supported"); int dci_size = pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d]; - + + *dci_pdu=0; + /// Payload generation switch(dci_formats[d]) { case NR_DL_DCI_FORMAT_1_0: @@ -563,7 +566,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, pos+=4; *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment&0xf) << (dci_size-pos)); #ifdef DEBUG_FILL_DCI - LOG_D(MAC,"time-domain assignment %d (3 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment,dci_size-pos,*dci_pdu); + LOG_D(MAC,"time-domain assignment %d (4 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment,dci_size-pos,*dci_pdu); #endif // VRB to PRB mapping diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index c25ce20331..3785f2575f 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -176,7 +176,8 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, - int *rnti_types); + int *rnti_types, + int N_RB); int get_spf(nfapi_nr_config_request_scf_t *cfg); diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index 977da561f8..b7f86fad68 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -85,56 +85,60 @@ typedef enum { /*! \brief gNB template for the Random access information */ typedef struct { - /// Flag to indicate this process is active - RA_state_t state; - /// Slot where preamble was received - uint8_t preamble_slot; - /// Subframe where Msg2 is to be sent - uint8_t Msg2_slot; - /// Frame where Msg2 is to be sent - frame_t Msg2_frame; - /// Subframe where Msg3 is to be sent - sub_frame_t Msg3_slot; - /// Frame where Msg3 is to be sent - frame_t Msg3_frame; - /// Subframe where Msg4 is to be sent - sub_frame_t Msg4_slot; - /// Frame where Msg4 is to be sent - frame_t Msg4_frame; - /// harq_pid used for Msg4 transmission - uint8_t harq_pid; - /// UE RNTI allocated during RAR - rnti_t rnti; - /// RA RNTI allocated from received PRACH - uint16_t RA_rnti; - /// Received preamble_index - uint8_t preamble_index; - /// Received UE Contention Resolution Identifier - uint8_t cont_res_id[6]; - /// Timing offset indicated by PHY - int16_t timing_offset; - /// Timeout for RRC connection - int16_t RRC_timer; - /// Msg3 first RB - uint8_t msg3_first_rb; - /// Msg3 number of RB - uint8_t msg3_nb_rb; - /// Msg3 MCS - uint8_t msg3_mcs; - /// Msg3 TPC command - uint8_t msg3_TPC; - /// Msg3 ULdelay command - uint8_t msg3_ULdelay; - /// Msg3 cqireq command - uint8_t msg3_cqireq; - /// Round of Msg3 HARQ - uint8_t msg3_round; - /// TBS used for Msg4 - int msg4_TBsize; - /// MCS used for Msg4 - int msg4_mcs; - /// RA search space - NR_SearchSpace_t *ra_ss; + /// Flag to indicate this process is active + RA_state_t state; + /// BWP id of RA process + int bwp_id; + /// CORESET0 configured flag + int coreset0_configured; + /// Slot where preamble was received + uint8_t preamble_slot; + /// Subframe where Msg2 is to be sent + uint8_t Msg2_slot; + /// Frame where Msg2 is to be sent + frame_t Msg2_frame; + /// Subframe where Msg3 is to be sent + sub_frame_t Msg3_slot; + /// Frame where Msg3 is to be sent + frame_t Msg3_frame; + /// Subframe where Msg4 is to be sent + sub_frame_t Msg4_slot; + /// Frame where Msg4 is to be sent + frame_t Msg4_frame; + /// harq_pid used for Msg4 transmission + uint8_t harq_pid; + /// UE RNTI allocated during RAR + rnti_t rnti; + /// RA RNTI allocated from received PRACH + uint16_t RA_rnti; + /// Received preamble_index + uint8_t preamble_index; + /// Received UE Contention Resolution Identifier + uint8_t cont_res_id[6]; + /// Timing offset indicated by PHY + int16_t timing_offset; + /// Timeout for RRC connection + int16_t RRC_timer; + /// Msg3 first RB + uint8_t msg3_first_rb; + /// Msg3 number of RB + uint8_t msg3_nb_rb; + /// Msg3 MCS + uint8_t msg3_mcs; + /// Msg3 TPC command + uint8_t msg3_TPC; + /// Msg3 ULdelay command + uint8_t msg3_ULdelay; + /// Msg3 cqireq command + uint8_t msg3_cqireq; + /// Round of Msg3 HARQ + uint8_t msg3_round; + /// TBS used for Msg4 + int msg4_TBsize; + /// MCS used for Msg4 + int msg4_mcs; + /// RA search space + NR_SearchSpace_t *ra_ss; } NR_RA_t; /*! \brief gNB common channels */ From d113daeb3a6aae53569e4d6bc1f554a90ae89ab5 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Mon, 24 Feb 2020 17:46:19 +0100 Subject: [PATCH 058/553] scrambling rnti fix in nr_dci --- openair1/PHY/NR_TRANSPORT/nr_dci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.c b/openair1/PHY/NR_TRANSPORT/nr_dci.c index 0924740ae5..1bff74f532 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.c @@ -230,6 +230,7 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, uint32_t encoder_output[NR_MAX_DCI_SIZE_DWORD]; uint16_t n_RNTI = pdcch_pdu_rel15->dci_pdu.RNTI[d]; uint16_t Nid = pdcch_pdu_rel15->dci_pdu.ScramblingId[d]; + uint16_t scrambing_RNTI = pdcch_pdu_rel15->dci_pdu.ScramblingRNTI[numDlDci]; t_nrPolar_params *currentPtr = nr_polar_params(NR_POLAR_DCI_MESSAGE_TYPE, pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d], @@ -249,7 +250,7 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, #endif /// Scrambling uint32_t scrambled_output[NR_MAX_DCI_SIZE_DWORD]= {0}; - nr_pdcch_scrambling(encoder_output, encoded_length, Nid, n_RNTI, scrambled_output); + nr_pdcch_scrambling(encoder_output, encoded_length, Nid, scrambling_RNTI, scrambled_output); #ifdef DEBUG_CHANNEL_CODING printf("scrambled output: [0]->0x%08x \t [1]->0x%08x \t [2]->0x%08x \t [3]->0x%08x\t [4]->0x%08x\t [5]->0x%08x\t \ [6]->0x%08x \t [7]->0x%08x \t [8]->0x%08x \t [9]->0x%08x\t [10]->0x%08x\t [11]->0x%08x\n", From 63cf2ffa9a401e6821b057a075da47f4ca2ebfff Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Mon, 24 Feb 2020 17:51:33 +0100 Subject: [PATCH 059/553] fixing the fix --- openair1/PHY/NR_TRANSPORT/nr_dci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.c b/openair1/PHY/NR_TRANSPORT/nr_dci.c index 1bff74f532..218da28b01 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.c @@ -230,7 +230,7 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, uint32_t encoder_output[NR_MAX_DCI_SIZE_DWORD]; uint16_t n_RNTI = pdcch_pdu_rel15->dci_pdu.RNTI[d]; uint16_t Nid = pdcch_pdu_rel15->dci_pdu.ScramblingId[d]; - uint16_t scrambing_RNTI = pdcch_pdu_rel15->dci_pdu.ScramblingRNTI[numDlDci]; + uint16_t scrambling_RNTI = pdcch_pdu_rel15->dci_pdu.ScramblingRNTI[d]; t_nrPolar_params *currentPtr = nr_polar_params(NR_POLAR_DCI_MESSAGE_TYPE, pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d], From 5a9329d1d96aaaf316701569ee4ec9dee74ce706 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Wed, 26 Feb 2020 14:10:57 +0100 Subject: [PATCH 060/553] bugfix in filling dci for rar --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 7 +++---- .../LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c | 12 ++++++------ 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index 95ac008b3f..cace9156e1 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -584,7 +584,7 @@ void nr_generate_Msg2(module_id_t module_idP, dci_pdu_rel15[0].time_domain_assignment = time_domain_assignment; dci_pdu_rel15[0].vrb_to_prb_mapping = 0; dci_pdu_rel15[0].mcs = pdsch_pdu_rel15->mcsIndex[0]; - dci_pdu_rel15[0].tb_scaling = 1; + dci_pdu_rel15[0].tb_scaling = 0; LOG_D(MAC, "[RAPROC] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d \n", dci_pdu_rel15[0].frequency_domain_assignment, @@ -598,7 +598,7 @@ void nr_generate_Msg2(module_id_t module_idP, nr_configure_pdcch(pdcch_pdu_rel15, 0, ss, scc, bwp); - LOG_D(MAC, "Frame %d: Subframe %d : Adding common DL DCI for RA_RNTI %x CCEIndex %d\n", frameP, slotP, RA_rnti, CCEIndex); + LOG_I(MAC, "Frame %d: Subframe %d : Adding common DL DCI for RA_RNTI %x CCEIndex %d\n", frameP, slotP, RA_rnti, CCEIndex); dci_pdu->RNTI[numDlDci] = RA_rnti; dci_pdu->ScramblingId[numDlDci] = *scc->physCellId; @@ -608,7 +608,6 @@ void nr_generate_Msg2(module_id_t module_idP, dci_pdu->CceIndex[numDlDci] = CCEIndex; dci_pdu->beta_PDCCH_1_0[numDlDci] = 0; dci_pdu->powerControlOffsetSS[numDlDci] = 1; - dci_formats[0] = NR_DL_DCI_FORMAT_1_0; rnti_types[0] = NR_RNTI_RA; @@ -620,9 +619,9 @@ void nr_generate_Msg2(module_id_t module_idP, pdcch_pdu_rel15->StartSymbolIndex, pdcch_pdu_rel15->DurationSymbols); + pdcch_pdu_rel15->numDlDci++; dci_pdu->PayloadSizeBits[0] = nr_dci_size(dci_formats[0], rnti_types[0], dci10_bw); fill_dci_pdu_rel15(pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types,dci10_bw); - pdcch_pdu_rel15->numDlDci++; dl_req->nPDUs+=2; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 4adc280972..0d9bf1880a 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -558,34 +558,34 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, // Freq domain assignment fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); pos=fsize; - *dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment&((1<frequency_domain_assignment&((1< %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment,fsize,N_RB,dci_size-pos,*dci_pdu); + LOG_I(MAC,"frequency-domain assignment %d (%d bits) N_RB_BWP %d=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment,fsize,N_RB,dci_size-pos,*dci_pdu); #endif // Time domain assignment pos+=4; *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment&0xf) << (dci_size-pos)); #ifdef DEBUG_FILL_DCI - LOG_D(MAC,"time-domain assignment %d (4 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment,dci_size-pos,*dci_pdu); + LOG_I(MAC,"time-domain assignment %d (4 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment,dci_size-pos,*dci_pdu); #endif // VRB to PRB mapping pos++; *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&0x1)<<(dci_size-pos); #ifdef DEBUG_FILL_DCI - LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,dci_size-pos,*dci_pdu); + LOG_I(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,dci_size-pos,*dci_pdu); #endif // MCS pos+=5; *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos); #ifdef DEBUG_FILL_DCI - LOG_D(MAC,"mcs %d (5 bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,dci_size-pos,*dci_pdu); + LOG_I(MAC,"mcs %d (5 bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,dci_size-pos,*dci_pdu); #endif // TB scaling pos+=2; *dci_pdu |= ((uint64_t)dci_pdu_rel15->tb_scaling&0x3)<<(dci_size-pos); #ifdef DEBUG_FILL_DCI - LOG_D(MAC,"tb_scaling %d (2 bits)=> %d (0x%lx)\n",dci_pdu_rel15->tb_scaling,dci_size-pos,*dci_pdu); + LOG_I(MAC,"tb_scaling %d (2 bits)=> %d (0x%lx)\n",dci_pdu_rel15->tb_scaling,dci_size-pos,*dci_pdu); #endif break; From 80d286b637a067e9917f9020791b6bfb5d081285 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Thu, 27 Feb 2020 10:19:34 +0100 Subject: [PATCH 061/553] removing 6db power boost of pdcch dmrs --- openair1/PHY/NR_TRANSPORT/nr_dci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.c b/openair1/PHY/NR_TRANSPORT/nr_dci.c index 218da28b01..3ee8d7af8b 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.c @@ -295,8 +295,8 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, for (int m=0; mCceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED) { - ((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1] = (2*amp * mod_dmrs[l][dmrs_idx<<1]) >> 15; - ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (2*amp * mod_dmrs[l][(dmrs_idx<<1) + 1]) >> 15; + ((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1] = (amp * mod_dmrs[l][dmrs_idx<<1]) >> 15; + ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (amp * mod_dmrs[l][(dmrs_idx<<1) + 1]) >> 15; #ifdef DEBUG_PDCCH_DMRS printf("PDCCH DMRS: l %d position %d => (%d,%d)\n",l,k,((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1], ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1)+1]); From f1e6a34f76c4caf4c9bd182ba04b3460accda1a4 Mon Sep 17 00:00:00 2001 From: cig Date: Wed, 19 Feb 2020 14:03:27 +0100 Subject: [PATCH 062/553] Add common mac functions declarations to nr_mac_common.h --- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h | 67 ++++++++++--------- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 7 -- 2 files changed, 37 insertions(+), 37 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h index ad62eb6bba..a3114886ba 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h @@ -33,35 +33,7 @@ #define __LAYER2_NR_MAC_COMMON_H__ #include "NR_PDSCH-Config.h" - -uint16_t config_bandwidth(int mu, int nb_rb, int nr_band); - -void get_band(uint64_t downlink_frequency, uint16_t *current_band, int32_t *current_offset, lte_frame_type_t *current_type); - -uint64_t from_nrarfcn(int nr_bandP, uint8_t scs_index, uint32_t dl_nrarfcn); - -uint32_t to_nrarfcn(int nr_bandP, uint64_t dl_CarrierFreq, uint8_t scs_index, uint32_t bw); - -int16_t fill_dmrs_mask(NR_PDSCH_Config_t *pdsch_Config,int dmrs_TypeA_Position,int NrOfSymbols); - -int get_nr_prach_info_from_index(uint8_t index, - int frame, - int slot, - uint32_t pointa, - uint8_t mu, - uint8_t unpaired, - uint16_t *format, - uint8_t *start_symbol, - uint8_t *N_t_slot, - uint8_t *N_dur); - -uint8_t compute_nr_root_seq(NR_RACH_ConfigCommon_t *rach_config, - uint8_t nb_preambles, - uint8_t unpaired); - -int get_format0(uint8_t index, uint8_t unpaired); - -uint16_t get_NCS(uint8_t index, uint16_t format, uint8_t restricted_set_config); +#include "NR_ServingCellConfigCommon.h" typedef enum { NR_DL_DCI_FORMAT_1_0 = 0, @@ -90,4 +62,39 @@ typedef enum { NR_RNTI_TPC_SRS } nr_rnti_type_t; -#endif +uint16_t config_bandwidth(int mu, int nb_rb, int nr_band); + +void get_band(uint64_t downlink_frequency, uint16_t *current_band, int32_t *current_offset, lte_frame_type_t *current_type); + +uint64_t from_nrarfcn(int nr_bandP, uint8_t scs_index, uint32_t dl_nrarfcn); + +uint32_t to_nrarfcn(int nr_bandP, uint64_t dl_CarrierFreq, uint8_t scs_index, uint32_t bw); + +int16_t fill_dmrs_mask(NR_PDSCH_Config_t *pdsch_Config,int dmrs_TypeA_Position,int NrOfSymbols); + +int is_nr_DL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP); + +int is_nr_UL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP); + +uint16_t nr_dci_size(nr_dci_format_t format, nr_rnti_type_t rnti_type, uint16_t N_RB); + +int get_nr_prach_info_from_index(uint8_t index, + int frame, + int slot, + uint32_t pointa, + uint8_t mu, + uint8_t unpaired, + uint16_t *format, + uint8_t *start_symbol, + uint8_t *N_t_slot, + uint8_t *N_dur); + +uint8_t compute_nr_root_seq(NR_RACH_ConfigCommon_t *rach_config, + uint8_t nb_preambles, + uint8_t unpaired); + +int get_format0(uint8_t index, uint8_t unpaired); + +uint16_t get_NCS(uint8_t index, uint16_t format, uint8_t restricted_set_config); + +#endif \ No newline at end of file diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index 3785f2575f..16370d238d 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -206,10 +206,6 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP); int get_num_dmrs(uint16_t dmrs_mask ); -uint16_t nr_dci_size(nr_dci_format_t format, - nr_rnti_type_t rnti_type, - uint16_t N_RB); - int allocate_nr_CCEs(gNB_MAC_INST *nr_mac, int bwp_id, int coreset_id, @@ -219,9 +215,6 @@ int allocate_nr_CCEs(gNB_MAC_INST *nr_mac, int m ); -int is_nr_DL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP); -int is_nr_UL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP); - int get_dlscs(nfapi_nr_config_request_t *cfg); int get_ulscs(nfapi_nr_config_request_t *cfg); From 3c16ad56434259cce313b53584cbe04789f57723 Mon Sep 17 00:00:00 2001 From: cig Date: Thu, 20 Feb 2020 15:35:06 +0100 Subject: [PATCH 063/553] NR UE PRACH scheduler to fill up UL config request with PRACH PDU - takes in input configuration index and TS 38.211 PRACH tables (6.3.3.2.x) - using FAPI NR UL config request struct, derived from SCF standard for gNB --- executables/nr-ue.c | 11 +- .../nfapi/public_inc/fapi_nr_ue_interface.h | 28 ++- openair1/SCHED_NR_UE/fapi_nr_ue_l1.c | 20 +- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 172 ++++++++++++++++-- 4 files changed, 186 insertions(+), 45 deletions(-) diff --git a/executables/nr-ue.c b/executables/nr-ue.c index bbdcd0c29c..239f4aa4bc 100644 --- a/executables/nr-ue.c +++ b/executables/nr-ue.c @@ -359,6 +359,7 @@ void processSlotTX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { uint32_t nb_rb, start_rb; uint8_t nb_symb_sch, start_symbol, mcs, precod_nbr_layers, harq_pid, rvidx; uint16_t n_rnti; + module_id_t mod_id; nr_dcireq_t dcireq; nr_scheduled_response_t scheduled_response; @@ -366,7 +367,9 @@ void processSlotTX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { // program PUSCH. this should actually be done by the MAC upon reception of an UL DCI if (proc->nr_tti_tx == 8 || UE->frame_parms.frame_type == FDD){ - dcireq.module_id = UE->Mod_id; + mod_id = UE->Mod_id; + + dcireq.module_id = mod_id; dcireq.gNB_index = 0; dcireq.cc_id = 0; dcireq.frame = proc->frame_rx; @@ -375,7 +378,7 @@ void processSlotTX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { scheduled_response.dl_config = NULL; scheduled_response.ul_config = &dcireq.ul_config_req; scheduled_response.tx_request = NULL; - scheduled_response.module_id = UE->Mod_id; + scheduled_response.module_id = mod_id; scheduled_response.CC_id = 0; scheduled_response.frame = proc->frame_rx; scheduled_response.slot = proc->nr_tti_rx; @@ -405,8 +408,10 @@ void processSlotTX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.n_layers = precod_nbr_layers; scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.harq_process_nbr = harq_pid; + //nr_ue_prach_scheduler(mod_id, proc->frame_rx, proc->nr_tti_rx); + nr_ue_scheduled_response(&scheduled_response); - + if (UE->mode != loop_through_memory) { uint8_t thread_id = PHY_vars_UE_g[UE->Mod_id][0]->current_thread_id[proc->nr_tti_tx]; phy_procedures_nrUE_TX(UE,proc,0,thread_id); diff --git a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h index 576144e1df..7caeecdc4c 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h @@ -156,22 +156,18 @@ typedef struct { fapi_nr_tx_request_body_t *tx_request_body; } fapi_nr_tx_request_t; - typedef struct { - uint8_t preamble_index; - uint8_t prach_configuration_index; - uint16_t preamble_length; - uint8_t power_ramping_step; - uint16_t preamble_received_target_power; - uint8_t msg1_fdm; - uint8_t msg1_frequency_start; - uint8_t zero_correlation_zone_config; - uint8_t subcarrier_spacing; - uint8_t restrictedset_config; - uint16_t root_sequence_index; - uint16_t rsrp_threshold_ssb; - uint16_t rsrp_threshold_sul; - uint16_t prach_freq_offset; - } fapi_nr_ul_config_prach_pdu; +typedef struct { + uint16_t phys_cell_id; + uint8_t num_prach_ocas; + uint8_t prach_format; + uint8_t num_ra; + uint8_t prach_start_symbol; + uint16_t num_cs; + uint16_t root_seq_id; + uint8_t restricted_set; + uint16_t freq_msg1; + //nfapi_nr_ul_beamforming_t beamforming; +} fapi_nr_ul_config_prach_pdu; typedef struct { diff --git a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c index 7dbb68cf31..612a4b2db9 100644 --- a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c +++ b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c @@ -165,16 +165,16 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response) pucch_config_common->hoppingId = pucch_config_pdu->hoppingId; pucch_config_common->p0_nominal = pucch_config_pdu->p0_nominal;*/ } - if(ul_config->ul_config_list[i].pdu_type == FAPI_NR_UL_CONFIG_TYPE_PRACH){ - // prach config pdu - fapi_nr_ul_config_prach_pdu *prach_config_pdu = &ul_config->ul_config_list[i].prach_config_pdu; - /*frame_parms.prach_config_common.rootSequenceIndex = prach_config_pdu->root_sequence_index; - frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex = prach_config_pdu->prach_configuration_index; - frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig = prach_config_pdu->zero_correlation_zone_config; - frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag = prach_config_pdu->restrictedset_config; - frame_parms.prach_config_common.prach_ConfigInfo.prach_FreqOffset = prach_config_pdu->prach_freq_offset;*/ - prach_resources->ra_PreambleIndex = prach_config_pdu->preamble_index; - } + if (ul_config->ul_config_list[i].pdu_type == FAPI_NR_UL_CONFIG_TYPE_PRACH) { + // prach config pdu + fapi_nr_ul_config_prach_pdu *prach_config_pdu = &ul_config->ul_config_list[i].prach_config_pdu; + /*frame_parms.prach_config_common.rootSequenceIndex = prach_config_pdu->root_sequence_index; + frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex = prach_config_pdu->prach_configuration_index; + frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig = prach_config_pdu->zero_correlation_zone_config; + frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag = prach_config_pdu->restrictedset_config; + frame_parms.prach_config_common.prach_ConfigInfo.prach_FreqOffset = prach_config_pdu->prach_freq_offset;*/ + ////prach_resources->ra_PreambleIndex = prach_config_pdu->preamble_index; + } } }else{ diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 0cd4c27c30..64ce5388b9 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -39,6 +39,9 @@ /* RRC*/ #include "RRC/NR_UE/rrc_proto.h" +#include "NR_RACH-ConfigCommon.h" +#include "NR_RACH-ConfigGeneric.h" +#include "NR_FrequencyInfoDL.h" /* MAC */ #include "mac_defs.h" @@ -738,6 +741,154 @@ NR_UE_L2_STATE_t nr_ue_scheduler(const module_id_t module_id, return UE_CONNECTION_OK; } +// This function schedules the PRACH according to prach_ConfigurationIndex and TS 38.211, tables 6.3.3.2.x +// It fills the PRACH PDU per each FD occasion. +// PRACH formats 9, 10, 11 are corresponding to dual PRACH format configurations A1/B1, A2/B2, A3/B3. +// - todo: +// - Partial configuration is actually already stored in (fapi_nr_prach_config_t) &mac->phy_config.config_req->prach_config +//// however we need rach_ConfigGeneric to retrieve the config_index +void nr_ue_prach_scheduler(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) { + + uint8_t config_index, mu, N_dur, N_t_slot, start_symbol; + uint16_t format, format0, format1, ncs; + int msg1_FDM, is_nr_prach_slot, fdm; + + NR_UE_MAC_INST_t *mac = get_mac_inst(module_idP); + + fapi_nr_ul_config_request_t *ul_config = &mac->ul_config_request; + fapi_nr_ul_config_prach_pdu *prach_config_pdu; + fapi_nr_config_request_t *cfg = &mac->phy_config.config_req; + fapi_nr_prach_config_t *prach_config = &cfg->prach_config; + + NR_ServingCellConfigCommon_t *scc = mac->scc; + NR_RACH_ConfigCommon_t *setup = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup; + NR_FrequencyInfoDL_t *frequencyInfoDL = scc->downlinkConfigCommon->frequencyInfoDL; + NR_RACH_ConfigGeneric_t *rach_ConfigGeneric = &setup->rach_ConfigGeneric; + config_index = rach_ConfigGeneric->prach_ConfigurationIndex; + + ////nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[module_idP]->UL_tti_req[0]; + + if (is_nr_DL_slot(scc, slotP) == 1) { + + if (setup->msg1_SubcarrierSpacing) + mu = *setup->msg1_SubcarrierSpacing; + else + mu = frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing; + + is_nr_prach_slot = get_nr_prach_info_from_index(config_index, + (int)frameP, + (int)slotP, + frequencyInfoDL->absoluteFrequencyPointA, + mu, + cfg->cell_config.frame_duplex_type, + &format, + &start_symbol, + &N_t_slot, + &N_dur); + if (is_nr_prach_slot) { + + fdm = rach_ConfigGeneric->msg1_FDM; + + switch (fdm){ + case 0: + case 1: + case 2: + case 3: + msg1_FDM = 1 << fdm; + break; + default: + AssertFatal(1 == 0, "Unknown msg1_FDM from rach_ConfigGeneric %d\n", fdm); + } + + format0 = format & 0xff; // single PRACH format + format1 = (format >> 8) & 0xff; // dual PRACH format + + ul_config->sfn = frameP; + ul_config->slot = slotP; + + for (int n = 0; n < msg1_FDM; n++) { // one structure per frequency domain occasion + + ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PRACH; + prach_config_pdu = &ul_config->ul_config_list[ul_config->number_pdus].prach_config_pdu; + memset(prach_config_pdu,0,sizeof(fapi_nr_ul_config_prach_pdu)); + ul_config->number_pdus += 1; + + ncs = get_NCS(rach_ConfigGeneric->zeroCorrelationZoneConfig, format0, setup->restrictedSetConfig); + + // filling PRACH PDU for FAPI config request + prach_config_pdu->phys_cell_id = *scc->physCellId; + prach_config_pdu->num_prach_ocas = N_t_slot; + prach_config_pdu->prach_start_symbol = start_symbol; + prach_config_pdu->num_ra = n; + prach_config_pdu->num_cs = ncs; + prach_config_pdu->root_seq_id = prach_config->num_prach_fd_occasions_list[n].prach_root_sequence_index; + prach_config_pdu->restricted_set = prach_config->restricted_set_config; + prach_config_pdu->freq_msg1 = prach_config->num_prach_fd_occasions_list[n].k1; + + if (format1 != 0xff) { + switch(format0) { // dual PRACH format + case 0xa1: + prach_config_pdu->prach_format = 9; + break; + case 0xa2: + prach_config_pdu->prach_format = 10; + break; + case 0xa3: + prach_config_pdu->prach_format = 10; + break; + default: + AssertFatal(1 == 0, "Only formats A1/B1 A2/B2 A3/B3 are valid for dual format"); + } + } else { + switch(format0) { // single PRACH format + case 0xa1: + prach_config_pdu->prach_format = 0; + break; + case 0xa2: + prach_config_pdu->prach_format = 1; + break; + case 0xa3: + prach_config_pdu->prach_format = 2; + break; + case 0xb1: + prach_config_pdu->prach_format = 3; + break; + case 0xb2: + prach_config_pdu->prach_format = 4; + break; + case 0xb3: + prach_config_pdu->prach_format = 5; + break; + case 0xb4: + prach_config_pdu->prach_format = 6; + break; + case 0xc0: + prach_config_pdu->prach_format = 7; + break; + case 0xc2: + prach_config_pdu->prach_format = 8; + break; + case 0: + // long formats are handled @ PHY + break; + case 1: + // long formats are handled @ PHY + break; + case 2: + // long formats are handled @ PHY + break; + case 3: + // long formats are handled @ PHY + break; + default: + AssertFatal(1 == 0, "Invalid PRACH format"); + } + } + } + } + } +} + //////////////////////////////////////////////////////////////////////////// /////////* Random Access Contention Resolution (5.1.35 TS 38.321) *///////// //////////////////////////////////////////////////////////////////////////// @@ -749,29 +900,18 @@ NR_UE_L2_STATE_t nr_ue_scheduler(const module_id_t module_id, void ue_contention_resolution(module_id_t module_id, uint8_t gNB_index, int cc_id, frame_t tx_frame){ NR_UE_MAC_INST_t *mac = get_mac_inst(module_id); - NR_RACH_ConfigCommon_t *rach_ConfigCommon = (NR_RACH_ConfigCommon_t *) NULL; + NR_ServingCellConfigCommon_t *scc = mac->scc; + NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup; if (mac->RA_contention_resolution_timer_active == 1) { - if (mac->nr_rach_ConfigCommon) { - rach_ConfigCommon = mac->nr_rach_ConfigCommon; - } else { - // LOG_E(MAC, "FATAL: radioResourceConfigCommon is NULL!!!\n"); - // VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_SCHEDULER,VCD_FUNCTION_OUT); - // stop_meas(&mac->ue_scheduler); - // AssertFatal(1 == 0, ""); - // #if UE_TIMING_TRACE - // stop_meas(&mac->ue_scheduler); - // #endif - } - - if (rach_ConfigCommon){ + if (nr_rach_ConfigCommon){ LOG_I(MAC, "Frame %d: Contention resolution timer %d/%ld\n", tx_frame, mac->RA_contention_resolution_cnt, - ((1 + rach_ConfigCommon->ra_ContentionResolutionTimer) << 3)); + ((1 + nr_rach_ConfigCommon->ra_ContentionResolutionTimer) << 3)); mac->RA_contention_resolution_cnt++; - if (mac->RA_contention_resolution_cnt == ((1 + rach_ConfigCommon->ra_ContentionResolutionTimer) << 3)) { + if (mac->RA_contention_resolution_cnt == ((1 + nr_rach_ConfigCommon->ra_ContentionResolutionTimer) << 3)) { mac->t_crnti = 0; mac->RA_active = 0; mac->RA_contention_resolution_timer_active = 0; From b5bb01d4a6073db9e75c740a074cfbca8917c8e6 Mon Sep 17 00:00:00 2001 From: cig Date: Fri, 21 Feb 2020 11:56:07 +0100 Subject: [PATCH 064/553] Cleanup and formatting nr_ue_scheduled_response --- openair1/SCHED_NR_UE/fapi_nr_ue_l1.c | 261 ++++++++++++++------------- 1 file changed, 139 insertions(+), 122 deletions(-) diff --git a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c index 612a4b2db9..f365d00c89 100644 --- a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c +++ b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c @@ -34,156 +34,173 @@ #include "fapi_nr_ue_interface.h" #include "fapi_nr_ue_l1.h" -//#include "PHY/phy_vars_nr_ue.h" #include "PHY/defs_nr_UE.h" #include "PHY/impl_defs_nr.h" + extern PHY_VARS_NR_UE ***PHY_vars_UE_g; -int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response) -{ - +int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ if(scheduled_response != NULL){ - /// module id - module_id_t module_id = scheduled_response->module_id; - /// component carrier id - uint8_t cc_id = scheduled_response->CC_id; + + module_id_t module_id = scheduled_response->module_id; + uint8_t cc_id = scheduled_response->CC_id, thread_id; uint32_t i; - int slot = scheduled_response->slot; - + int slot = scheduled_response->slot; + // Note: we have to handle the thread IDs for this. To be revisited completely. - uint8_t thread_id = PHY_vars_UE_g[module_id][cc_id]->current_thread_id[slot]; + thread_id = PHY_vars_UE_g[module_id][cc_id]->current_thread_id[slot]; NR_UE_PDCCH *pdcch_vars = PHY_vars_UE_g[module_id][cc_id]->pdcch_vars[thread_id][0]; NR_UE_DLSCH_t *dlsch0 = PHY_vars_UE_g[module_id][cc_id]->dlsch[thread_id][0][0]; NR_UE_ULSCH_t *ulsch0 = PHY_vars_UE_g[module_id][cc_id]->ulsch[thread_id][0][0]; //NR_DL_FRAME_PARMS frame_parms = PHY_vars_UE_g[module_id][cc_id]->frame_parms; - NR_PRACH_RESOURCES_t *prach_resources = PHY_vars_UE_g[module_id][cc_id]->prach_resources[0]; - - // PUCCH_ConfigCommon_nr_t *pucch_config_common = PHY_vars_UE_g[module_id][cc_id]->pucch_config_common_nr[0]; - // PUCCH_Config_t *pucch_config_dedicated = PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0]; + //NR_PRACH_RESOURCES_t *prach_resources = PHY_vars_UE_g[module_id][cc_id]->prach_resources[0]; if(scheduled_response->dl_config != NULL){ fapi_nr_dl_config_request_t *dl_config = scheduled_response->dl_config; LOG_D(PHY,"Received %d DL pdus\n",dl_config->number_pdus); pdcch_vars->nb_search_space = 0; - for(i=0; inumber_pdus; ++i){ - if(dl_config->dl_config_list[i].pdu_type == FAPI_NR_DL_CONFIG_TYPE_DCI){ - fapi_nr_dl_config_dci_dl_pdu_rel15_t *pdcch_config = &dl_config->dl_config_list[i].dci_config_pdu.dci_config_rel15; - memcpy((void*)&pdcch_vars->pdcch_config[pdcch_vars->nb_search_space],(void*)pdcch_config,sizeof(*pdcch_config)); - pdcch_vars->nb_search_space = pdcch_vars->nb_search_space + 1; - LOG_D(PHY,"Number of DCI SearchSpaces %d\n",pdcch_vars->nb_search_space); - }else{ //FAPI_NR_DL_CONFIG_TYPE_DLSCH - // dlsch config pdu + for (i = 0; i < dl_config->number_pdus; ++i){ - fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu = &dl_config->dl_config_list[i].dlsch_config_pdu.dlsch_config_rel15; - uint8_t current_harq_pid = dlsch_config_pdu->harq_process_nbr; - dlsch0->current_harq_pid = current_harq_pid; - dlsch0->active = 1; - dlsch0->rnti = dl_config->dl_config_list[i].dlsch_config_pdu.rnti; - - //dlsch0->harq_processes[0]->mcs = &dlsch_config_pdu->mcs; - - NR_DL_UE_HARQ_t *dlsch0_harq = dlsch0->harq_processes[current_harq_pid]; + if (dl_config->dl_config_list[i].pdu_type == FAPI_NR_DL_CONFIG_TYPE_DCI) { - dlsch0_harq->BWPStart = dlsch_config_pdu->BWPStart; - dlsch0_harq->BWPSize = dlsch_config_pdu->BWPSize; - dlsch0_harq->nb_rb = dlsch_config_pdu->number_rbs; - dlsch0_harq->start_rb = dlsch_config_pdu->start_rb; - dlsch0_harq->nb_symbols = dlsch_config_pdu->number_symbols; - dlsch0_harq->start_symbol = dlsch_config_pdu->start_symbol; - dlsch0_harq->dlDmrsSymbPos = dlsch_config_pdu->dlDmrsSymbPos; - dlsch0_harq->dmrsConfigType = dlsch_config_pdu->dmrsConfigType; - dlsch0_harq->mcs = dlsch_config_pdu->mcs; - dlsch0_harq->DCINdi = dlsch_config_pdu->ndi; - dlsch0_harq->rvidx = dlsch_config_pdu->rv; - dlsch0->g_pucch = dlsch_config_pdu->accumulated_delta_PUCCH; - dlsch0_harq->harq_ack.pucch_resource_indicator = dlsch_config_pdu->pucch_resource_id; - dlsch0_harq->harq_ack.slot_for_feedback_ack = dlsch_config_pdu->pdsch_to_harq_feedback_time_ind; - dlsch0_harq->Nl=1; - dlsch0_harq->mcs_table=0; - dlsch0_harq->status = ACTIVE; - LOG_D(MAC,">>>> \tdlsch0->g_pucch=%d\tdlsch0_harq.mcs=%d\n",dlsch0->g_pucch,dlsch0_harq->mcs); + fapi_nr_dl_config_dci_dl_pdu_rel15_t *pdcch_config = &dl_config->dl_config_list[i].dci_config_pdu.dci_config_rel15; + memcpy((void*)&pdcch_vars->pdcch_config[pdcch_vars->nb_search_space],(void*)pdcch_config,sizeof(*pdcch_config)); + pdcch_vars->nb_search_space = pdcch_vars->nb_search_space + 1; + LOG_D(PHY,"Number of DCI SearchSpaces %d\n",pdcch_vars->nb_search_space); - } + } else { //FAPI_NR_DL_CONFIG_TYPE_DLSCH + + fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu = &dl_config->dl_config_list[i].dlsch_config_pdu.dlsch_config_rel15; + uint8_t current_harq_pid = dlsch_config_pdu->harq_process_nbr; + NR_DL_UE_HARQ_t *dlsch0_harq; + + dlsch0->current_harq_pid = current_harq_pid; + dlsch0->active = 1; + dlsch0->rnti = dl_config->dl_config_list[i].dlsch_config_pdu.rnti; + //dlsch0->harq_processes[0]->mcs = &dlsch_config_pdu->mcs; + dlsch0_harq = dlsch0->harq_processes[current_harq_pid]; + dlsch0_harq->BWPStart = dlsch_config_pdu->BWPStart; + dlsch0_harq->BWPSize = dlsch_config_pdu->BWPSize; + dlsch0_harq->nb_rb = dlsch_config_pdu->number_rbs; + dlsch0_harq->start_rb = dlsch_config_pdu->start_rb; + dlsch0_harq->nb_symbols = dlsch_config_pdu->number_symbols; + dlsch0_harq->start_symbol = dlsch_config_pdu->start_symbol; + dlsch0_harq->dlDmrsSymbPos = dlsch_config_pdu->dlDmrsSymbPos; + dlsch0_harq->dmrsConfigType = dlsch_config_pdu->dmrsConfigType; + dlsch0_harq->mcs = dlsch_config_pdu->mcs; + dlsch0_harq->DCINdi = dlsch_config_pdu->ndi; + dlsch0_harq->rvidx = dlsch_config_pdu->rv; + dlsch0->g_pucch = dlsch_config_pdu->accumulated_delta_PUCCH; + dlsch0_harq->harq_ack.pucch_resource_indicator = dlsch_config_pdu->pucch_resource_id; + dlsch0_harq->harq_ack.slot_for_feedback_ack = dlsch_config_pdu->pdsch_to_harq_feedback_time_ind; + dlsch0_harq->Nl=1; + dlsch0_harq->mcs_table=0; + dlsch0_harq->status = ACTIVE; + LOG_D(MAC, ">>>> \tdlsch0->g_pucch = %d\tdlsch0_harq.mcs = %d\n", dlsch0->g_pucch, dlsch0_harq->mcs); + } } - }else{ + } else { pdcch_vars->nb_search_space = 0; } - if(scheduled_response->ul_config != NULL){ + if (scheduled_response->ul_config != NULL){ + fapi_nr_ul_config_request_t *ul_config = scheduled_response->ul_config; - for(i=0; inumber_pdus; ++i){ - if(ul_config->ul_config_list[i].pdu_type == FAPI_NR_UL_CONFIG_TYPE_PUSCH){ - // pusch config pdu - fapi_nr_ul_config_pusch_pdu_rel15_t *pusch_config_pdu = &ul_config->ul_config_list[i].ulsch_config_pdu.ulsch_pdu_rel15; - uint8_t current_harq_pid = pusch_config_pdu->harq_process_nbr; - ulsch0->harq_processes[current_harq_pid]->nb_rb = pusch_config_pdu->number_rbs; - ulsch0->harq_processes[current_harq_pid]->first_rb = pusch_config_pdu->start_rb; - ulsch0->harq_processes[current_harq_pid]->number_of_symbols = pusch_config_pdu->number_symbols; - ulsch0->harq_processes[current_harq_pid]->start_symbol = pusch_config_pdu->start_symbol; - ulsch0->harq_processes[current_harq_pid]->mcs = pusch_config_pdu->mcs; - ulsch0->harq_processes[current_harq_pid]->DCINdi = pusch_config_pdu->ndi; - ulsch0->harq_processes[current_harq_pid]->rvidx = pusch_config_pdu->rv; - ulsch0->harq_processes[current_harq_pid]->Nl = pusch_config_pdu->n_layers; - ulsch0->f_pusch = pusch_config_pdu->absolute_delta_PUSCH; - } - if(ul_config->ul_config_list[i].pdu_type == FAPI_NR_UL_CONFIG_TYPE_PUCCH){ - // pucch config pdu - fapi_nr_ul_config_pucch_pdu *pucch_config_pdu = &ul_config->ul_config_list[i].pucch_config_pdu; - uint8_t pucch_resource_id = 0; //FIXME!!! - uint8_t format = 1; // FIXME!!! - PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.initialCyclicShift = pucch_config_pdu->initialCyclicShift; - PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.nrofSymbols = pucch_config_pdu->nrofSymbols; - PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.startingSymbolIndex = pucch_config_pdu->startingSymbolIndex; - PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.nrofPRBs = pucch_config_pdu->nrofPRBs; - PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->startingPRB = pucch_config_pdu->startingPRB; - PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.timeDomainOCC = pucch_config_pdu->timeDomainOCC; - PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.occ_length = pucch_config_pdu->occ_length; - PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.occ_Index = pucch_config_pdu->occ_Index; - PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->intraSlotFrequencyHopping = pucch_config_pdu->intraSlotFrequencyHopping; - PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->secondHopPRB = pucch_config_pdu->secondHopPRB; // Not sure this parameter is used - PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].formatConfig[format-1]->additionalDMRS = pucch_config_pdu->additionalDMRS; // At this point we need to know which format is going to be used - PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].formatConfig[format-1]->pi2PBSK = pucch_config_pdu->pi2PBSK; - PHY_vars_UE_g[module_id][cc_id]->pucch_config_common_nr[0].pucch_GroupHopping = pucch_config_pdu->pucch_GroupHopping; - PHY_vars_UE_g[module_id][cc_id]->pucch_config_common_nr[0].hoppingId = pucch_config_pdu->hoppingId; - PHY_vars_UE_g[module_id][cc_id]->pucch_config_common_nr[0].p0_nominal = pucch_config_pdu->p0_nominal; - /* pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.initialCyclicShift = pucch_config_pdu->initialCyclicShift; - pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.nrofSymbols = pucch_config_pdu->nrofSymbols; - pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.startingSymbolIndex = pucch_config_pdu->startingSymbolIndex; - pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.nrofPRBs = pucch_config_pdu->nrofPRBs; - pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->startingPRB = pucch_config_pdu->startingPRB; - pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.timeDomainOCC = pucch_config_pdu->timeDomainOCC; - pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.occ_length = pucch_config_pdu->occ_length; - pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.occ_Index = pucch_config_pdu->occ_Index; - pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->intraSlotFrequencyHopping = pucch_config_pdu->intraSlotFrequencyHopping; - pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->secondHopPRB = pucch_config_pdu->secondHopPRB; // Not sure this parameter is used - pucch_config_dedicated->formatConfig[format-1]->additionalDMRS = pucch_config_pdu->additionalDMRS; // At this point we need to know which format is going to be used - pucch_config_dedicated->formatConfig[format-1]->pi2PBSK = pucch_config_pdu->pi2PBSK; - pucch_config_common->pucch_GroupHopping = pucch_config_pdu->pucch_GroupHopping; - pucch_config_common->hoppingId = pucch_config_pdu->hoppingId; - pucch_config_common->p0_nominal = pucch_config_pdu->p0_nominal;*/ - } - if (ul_config->ul_config_list[i].pdu_type == FAPI_NR_UL_CONFIG_TYPE_PRACH) { - // prach config pdu - fapi_nr_ul_config_prach_pdu *prach_config_pdu = &ul_config->ul_config_list[i].prach_config_pdu; - /*frame_parms.prach_config_common.rootSequenceIndex = prach_config_pdu->root_sequence_index; - frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex = prach_config_pdu->prach_configuration_index; - frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig = prach_config_pdu->zero_correlation_zone_config; - frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag = prach_config_pdu->restrictedset_config; - frame_parms.prach_config_common.prach_ConfigInfo.prach_FreqOffset = prach_config_pdu->prach_freq_offset;*/ - ////prach_resources->ra_PreambleIndex = prach_config_pdu->preamble_index; - } + + for (i = 0; i < ul_config->number_pdus; ++i){ + + uint8_t pdu_type = ul_config->ul_config_list[i].pdu_type, pucch_resource_id, current_harq_pid, format; + fapi_nr_ul_config_pusch_pdu_rel15_t *pusch_config_pdu; + fapi_nr_ul_config_pucch_pdu *pucch_config_pdu; + fapi_nr_ul_config_prach_pdu *prach_config_pdu; + PUCCH_ConfigCommon_nr_t *pucch_config_common_nr; + PUCCH_Config_t *pucch_config_dedicated_nr; + PUCCH_format_t *format_params; + + switch (pdu_type){ + + case (FAPI_NR_UL_CONFIG_TYPE_PUSCH): + // pusch config pdu + pusch_config_pdu = &ul_config->ul_config_list[i].ulsch_config_pdu.ulsch_pdu_rel15; + current_harq_pid = pusch_config_pdu->harq_process_nbr; + ulsch0->harq_processes[current_harq_pid]->nb_rb = pusch_config_pdu->number_rbs; + ulsch0->harq_processes[current_harq_pid]->first_rb = pusch_config_pdu->start_rb; + ulsch0->harq_processes[current_harq_pid]->number_of_symbols = pusch_config_pdu->number_symbols; + ulsch0->harq_processes[current_harq_pid]->start_symbol = pusch_config_pdu->start_symbol; + ulsch0->harq_processes[current_harq_pid]->mcs = pusch_config_pdu->mcs; + ulsch0->harq_processes[current_harq_pid]->DCINdi = pusch_config_pdu->ndi; + ulsch0->harq_processes[current_harq_pid]->rvidx = pusch_config_pdu->rv; + ulsch0->harq_processes[current_harq_pid]->Nl = pusch_config_pdu->n_layers; + ulsch0->f_pusch = pusch_config_pdu->absolute_delta_PUSCH; + break; + + case (FAPI_NR_UL_CONFIG_TYPE_PUCCH): + // pucch config pdu + pucch_config_pdu = &ul_config->ul_config_list[i].pucch_config_pdu; + pucch_resource_id = 0; //FIXME!!! + format = 1; // FIXME!!! + pucch_config_common_nr = &PHY_vars_UE_g[module_id][cc_id]->pucch_config_common_nr[0]; + pucch_config_dedicated_nr = &PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0]; + format_params = &pucch_config_dedicated_nr->PUCCH_Resource[pucch_resource_id]->format_parameters; + + format_params->initialCyclicShift = pucch_config_pdu->initialCyclicShift; + format_params->nrofSymbols = pucch_config_pdu->nrofSymbols; + format_params->startingSymbolIndex = pucch_config_pdu->startingSymbolIndex; + format_params->nrofPRBs = pucch_config_pdu->nrofPRBs; + format_params->timeDomainOCC = pucch_config_pdu->timeDomainOCC; + format_params->occ_length = pucch_config_pdu->occ_length; + format_params->occ_Index = pucch_config_pdu->occ_Index; + + pucch_config_dedicated_nr->PUCCH_Resource[pucch_resource_id]->startingPRB = pucch_config_pdu->startingPRB; + pucch_config_dedicated_nr->PUCCH_Resource[pucch_resource_id]->intraSlotFrequencyHopping = pucch_config_pdu->intraSlotFrequencyHopping; + pucch_config_dedicated_nr->PUCCH_Resource[pucch_resource_id]->secondHopPRB = pucch_config_pdu->secondHopPRB; // Not sure this parameter is used + pucch_config_dedicated_nr->formatConfig[format - 1]->additionalDMRS = pucch_config_pdu->additionalDMRS; // At this point we need to know which format is going to be used + pucch_config_dedicated_nr->formatConfig[format - 1]->pi2PBSK = pucch_config_pdu->pi2PBSK; + + pucch_config_common_nr->pucch_GroupHopping = pucch_config_pdu->pucch_GroupHopping; + pucch_config_common_nr->hoppingId = pucch_config_pdu->hoppingId; + pucch_config_common_nr->p0_nominal = pucch_config_pdu->p0_nominal; + + /* pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.initialCyclicShift = pucch_config_pdu->initialCyclicShift; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.nrofSymbols = pucch_config_pdu->nrofSymbols; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.startingSymbolIndex = pucch_config_pdu->startingSymbolIndex; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.nrofPRBs = pucch_config_pdu->nrofPRBs; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->startingPRB = pucch_config_pdu->startingPRB; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.timeDomainOCC = pucch_config_pdu->timeDomainOCC; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.occ_length = pucch_config_pdu->occ_length; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.occ_Index = pucch_config_pdu->occ_Index; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->intraSlotFrequencyHopping = pucch_config_pdu->intraSlotFrequencyHopping; + pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->secondHopPRB = pucch_config_pdu->secondHopPRB; // Not sure this parameter is used + pucch_config_dedicated->formatConfig[format-1]->additionalDMRS = pucch_config_pdu->additionalDMRS; // At this point we need to know which format is going to be used + pucch_config_dedicated->formatConfig[format-1]->pi2PBSK = pucch_config_pdu->pi2PBSK; + pucch_config_common->pucch_GroupHopping = pucch_config_pdu->pucch_GroupHopping; + pucch_config_common->hoppingId = pucch_config_pdu->hoppingId; + pucch_config_common->p0_nominal = pucch_config_pdu->p0_nominal;*/ + break; + + case (FAPI_NR_UL_CONFIG_TYPE_PRACH): + // prach config pdu + prach_config_pdu = &ul_config->ul_config_list[i].prach_config_pdu; + /*frame_parms.prach_config_common.rootSequenceIndex = prach_config_pdu->root_sequence_index; + frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex = prach_config_pdu->prach_configuration_index; + frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig = prach_config_pdu->zero_correlation_zone_config; + frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag = prach_config_pdu->restrictedset_config; + frame_parms.prach_config_common.prach_ConfigInfo.prach_FreqOffset = prach_config_pdu->prach_freq_offset;*/ + ////prach_resources->ra_PreambleIndex = prach_config_pdu->preamble_index; + break; + + default: + break; + } } - }else{ - + } else { } - if(scheduled_response->tx_request != NULL){ - - }else{ - + if (scheduled_response->tx_request != NULL){ + } else { } } @@ -194,10 +211,10 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response) int8_t nr_ue_phy_config_request(nr_phy_config_t *phy_config){ fapi_nr_config_request_t *nrUE_config = &PHY_vars_UE_g[phy_config->Mod_id][phy_config->CC_id]->nrUE_config; - + if(phy_config != NULL) memcpy(nrUE_config,&phy_config->config_req,sizeof(fapi_nr_config_request_t)); - + return 0; } From 8ed99c28cf9bc738191b6afd2294023050c471e2 Mon Sep 17 00:00:00 2001 From: cig Date: Tue, 25 Feb 2020 11:07:12 +0100 Subject: [PATCH 065/553] Fixes UE RA procedures: - using NR RACH config common from scc - fixed return type RA preamble target power functions - retrieving PRACH format from PRACH resources --- openair1/PHY/defs_nr_common.h | 6 +- openair2/LAYER2/NR_MAC_UE/mac_defs.h | 2 - openair2/LAYER2/NR_MAC_UE/mac_proto.h | 13 +++- openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c | 34 +++++----- openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 71 ++++++++------------ 5 files changed, 60 insertions(+), 66 deletions(-) diff --git a/openair1/PHY/defs_nr_common.h b/openair1/PHY/defs_nr_common.h index 5241f5736d..172e0b20d6 100644 --- a/openair1/PHY/defs_nr_common.h +++ b/openair1/PHY/defs_nr_common.h @@ -224,12 +224,14 @@ typedef struct { } NR_PRACH_CONFIG_COMMON; typedef struct { + /// PRACH format retrieved from prach_ConfigIndex + uint16_t prach_format; /// Preamble index for PRACH (0-63) uint8_t ra_PreambleIndex; /// RACH MaskIndex uint8_t ra_RACH_MaskIndex; - /// Target received power at eNB (-120 ... -82 dBm) - uint32_t ra_PREAMBLE_RECEIVED_TARGET_POWER; + /// Target received power at gNB. Baseline is range -202..-60 dBm. Depends on delta preamble, power ramping counter and step. + int ra_PREAMBLE_RECEIVED_TARGET_POWER; /// PRACH index for TDD (0 ... 6) depending on TDD configuration and prachConfigIndex uint8_t ra_TDD_map_index; /// RA Preamble Power Ramping Step in dB diff --git a/openair2/LAYER2/NR_MAC_UE/mac_defs.h b/openair2/LAYER2/NR_MAC_UE/mac_defs.h index d0b64c1da6..5f70cd86b8 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_defs.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_defs.h @@ -117,8 +117,6 @@ typedef struct { /* Random Access parameters */ /// state of RA procedure RA_state_t ra_state; - /// RACH ConfigCommon - NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon; /// RA-rnti uint16_t ra_rnti; /// Temporary CRNTI diff --git a/openair2/LAYER2/NR_MAC_UE/mac_proto.h b/openair2/LAYER2/NR_MAC_UE/mac_proto.h index 580e3c438d..afb161b337 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_proto.h @@ -185,17 +185,26 @@ int set_tdd_config_nr_ue(fapi_nr_config_request_t *cfg, int mu, @param Mod_id Module id of UE @returns Po_NOMINAL_PUSCH (PREAMBLE_RECEIVED_TARGET_POWER+DELTA_PREAMBLE */ -int8_t nr_get_Po_NOMINAL_PUSCH(NR_PRACH_RESOURCES_t *prach_resources, module_id_t module_idP, uint8_t CC_id); +int nr_get_Po_NOMINAL_PUSCH(NR_PRACH_RESOURCES_t *prach_resources, module_id_t module_idP, uint8_t CC_id); /** \brief Function to compute DELTA_PREAMBLE from 38.321 subclause 7.3 (for RA power ramping procedure and Msg3 PUSCH power control policy) @param Mod_id Module id of UE @returns DELTA_PREAMBLE */ -int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id); +int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id, uint16_t prach_format); /* Random Access */ +/* \brief This function schedules the PRACH according to prach_ConfigurationIndex and TS 38.211 tables 6.3.3.2.x +and fills the PRACH PDU per each FD occasion. +@param module_idP Index of UE instance +@param frameP Frame index +@param slotP Slot index +@returns void +*/ +void nr_ue_prach_scheduler(module_id_t module_idP, frame_t frameP, sub_frame_t slotP); + /* \brief Function called by PHY to process the received RAR and check that the preamble matches what was sent by the gNB. It provides the timing advance and t-CRNTI. @param Mod_id Index of UE instance @param CC_id Index to a component carrier diff --git a/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c b/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c index e61e58c764..ab15935f16 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c @@ -35,21 +35,16 @@ #include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" #include "LAYER2/NR_MAC_UE/mac_proto.h" -// WIP todo: -//- frame_type and fr are hardcoded. Retireve from fp - /* TS 38.321 subclause 7.3 - return DELTA_PREAMBLE values in dB */ -int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id){ +int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id, uint16_t prach_format){ - NR_UE_MAC_INST_t *nrUE_mac_inst = get_mac_inst(mod_id); - NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = nrUE_mac_inst->nr_rach_ConfigCommon; + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + NR_ServingCellConfigCommon_t *scc = mac->scc; + NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup; AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); - uint8_t preambleFormat, prachConfigIndex; - lte_frame_type_t frame_type = TDD; - nr_frequency_range_e fr = nr_FR1; - int mu; + uint8_t prachConfigIndex, mu; // SCS configuration from msg1_SubcarrierSpacing and table 4.2-1 in TS 38.211 @@ -95,9 +90,8 @@ int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id){ // Preamble formats given by prach_ConfigurationIndex and tables 6.3.3.2-2 and 6.3.3.2-2 in TS 38.211 prachConfigIndex = nr_rach_ConfigCommon->rach_ConfigGeneric.prach_ConfigurationIndex; - preambleFormat = get_nr_prach_fmt(prachConfigIndex,frame_type,fr); - switch (preambleFormat) { + switch (prach_format) { // long preamble formats case 0: case 3: @@ -130,19 +124,25 @@ int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id){ return 5 + 3*mu; default: - AssertFatal(1 == 0, "[UE %d] ue_procedures.c: FATAL, Illegal preambleFormat %d, prachConfigIndex %d\n", mod_id, preambleFormat, prachConfigIndex); + AssertFatal(1 == 0, "[UE %d] ue_procedures.c: FATAL, Illegal preambleFormat %d, prachConfigIndex %d\n", mod_id, prach_format, prachConfigIndex); } } /* TS 38.321 subclause 5.1.3 - RA preamble transmission - ra_PREAMBLE_RECEIVED_TARGET_POWER configuration */ -int8_t nr_get_Po_NOMINAL_PUSCH(NR_PRACH_RESOURCES_t *prach_resources, module_id_t mod_id, uint8_t CC_id){ +int nr_get_Po_NOMINAL_PUSCH(NR_PRACH_RESOURCES_t *prach_resources, module_id_t mod_id, uint8_t CC_id){ - NR_UE_MAC_INST_t *nr_UE_mac_inst = get_mac_inst(mod_id); - NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = nr_UE_mac_inst->nr_rach_ConfigCommon; + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + NR_ServingCellConfigCommon_t *scc = mac->scc; + NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup; + int8_t receivedTargerPower, delta_preamble; + long preambleReceivedTargetPower; AssertFatal(nr_rach_ConfigCommon != NULL, "[UE %d] CCid %d FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id, CC_id); - int8_t receivedTargerPower = nr_rach_ConfigCommon->rach_ConfigGeneric.preambleReceivedTargetPower + nr_get_DELTA_PREAMBLE(mod_id, CC_id) + (nr_UE_mac_inst->RA_PREAMBLE_POWER_RAMPING_COUNTER - 1) * prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP; + preambleReceivedTargetPower = nr_rach_ConfigCommon->rach_ConfigGeneric.preambleReceivedTargetPower; + delta_preamble = nr_get_DELTA_PREAMBLE(mod_id, CC_id, prach_resources->prach_format); + + receivedTargerPower = preambleReceivedTargetPower + delta_preamble + (mac->RA_PREAMBLE_POWER_RAMPING_COUNTER - 1) * prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP; return receivedTargerPower; } \ No newline at end of file diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c index f928aeb572..138d37d394 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -79,11 +79,14 @@ void nr_get_prach_resources(module_id_t mod_id, NR_RACH_ConfigDedicated_t * rach_ConfigDedicated){ NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + NR_ServingCellConfigCommon_t *scc = mac->scc; NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon; + NR_RACH_ConfigGeneric_t *rach_ConfigGeneric; + // NR_BeamFailureRecoveryConfig_t *beam_failure_recovery_config = &mac->RA_BeamFailureRecoveryConfig; // todo int messagePowerOffsetGroupB, messageSizeGroupA, PLThreshold, sizeOfRA_PreamblesGroupA, numberOfRA_Preambles, i, deltaPreamble_Msg3; - uint8_t noGroupB = 0, s_id, f_id, ul_carrier_id, msg1_FDM, prach_ConfigIndex, SFN_nbr, Msg3_size; + uint8_t noGroupB = 0, s_id, f_id, ul_carrier_id, prach_ConfigIndex, SFN_nbr, Msg3_size; // NR_RSRP_Range_t rsrp_ThresholdSSB; // todo @@ -116,9 +119,10 @@ void nr_get_prach_resources(module_id_t mod_id, // rsrp_ThresholdSSB = *nr_rach_ConfigCommon->rsrp_ThresholdSSB; - AssertFatal(mac->nr_rach_ConfigCommon != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); + AssertFatal(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); - nr_rach_ConfigCommon = mac->nr_rach_ConfigCommon; + nr_rach_ConfigCommon = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup; + rach_ConfigGeneric = &nr_rach_ConfigCommon->rach_ConfigGeneric; Msg3_size = mac->RA_Msg3_size; numberOfRA_Preambles = *nr_rach_ConfigCommon->totalNumberOfRA_Preambles; @@ -202,7 +206,7 @@ void nr_get_prach_resources(module_id_t mod_id, deltaPreamble_Msg3 = mac->deltaPreamble_Msg3; } - PLThreshold = prach_resources->RA_PCMAX - nr_rach_ConfigCommon->rach_ConfigGeneric.preambleReceivedTargetPower - deltaPreamble_Msg3 - messagePowerOffsetGroupB; + PLThreshold = prach_resources->RA_PCMAX - rach_ConfigGeneric->preambleReceivedTargetPower - deltaPreamble_Msg3 - messagePowerOffsetGroupB; /* Msg3 has not been transmitted yet */ if (first_Msg3 == 1) { @@ -254,24 +258,7 @@ void nr_get_prach_resources(module_id_t mod_id, // 1) this does not apply to contention-free RA Preamble for beam failure recovery request // 2) getting star_symb, SFN_nbr from table 6.3.3.2-3 (TDD and FR1 scenario) - switch (nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FDM){ // todo this is not used - case 0: - msg1_FDM = 1; - break; - case 1: - msg1_FDM = 2; - break; - case 2: - msg1_FDM = 4; - break; - case 3: - msg1_FDM = 8; - break; - default: - AssertFatal(1 == 0,"Unknown msg1_FDM %lu\n", nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FDM); - } - - prach_ConfigIndex = nr_rach_ConfigCommon->rach_ConfigGeneric.prach_ConfigurationIndex; + prach_ConfigIndex = rach_ConfigGeneric->prach_ConfigurationIndex; // ra_RNTI computation // - todo: this is for TDD FR1 only @@ -281,7 +268,7 @@ void nr_get_prach_resources(module_id_t mod_id, // - t_id is the first slot of the PRACH occasion in a system frame [0...80] ul_carrier_id = 0; // NUL - f_id = nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FrequencyStart; + f_id = rach_ConfigGeneric->msg1_FrequencyStart; SFN_nbr = table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][4]; s_id = table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][5]; @@ -348,7 +335,9 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, uint8_t lcid = UL_SCH_LCID_CCCH_MSG3, *mac_sdus, *payload, ra_ResponseWindow; uint16_t size_sdu = 0; unsigned short post_padding; - NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = (NR_RACH_ConfigCommon_t *) NULL; + NR_ServingCellConfigCommon_t *scc = mac->scc; + NR_RACH_ConfigCommon_t *setup = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup; + NR_RACH_ConfigGeneric_t *rach_ConfigGeneric = &setup->rach_ConfigGeneric; // int32_t frame_diff = 0; uint8_t sdu_lcids[NB_RB_MAX] = {0}; @@ -361,11 +350,7 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, LOG_D(MAC, "nr_ue_get_rach, RA_active value: %d", mac->RA_active); - AssertFatal(mac->nr_rach_ConfigCommon != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); - - if (mac->nr_rach_ConfigCommon != NULL) { - nr_rach_ConfigCommon = mac->nr_rach_ConfigCommon; - } else prach_resources = NULL; + AssertFatal(setup != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); if (mac->RA_active == 0) { /* RA not active - checking if RRC is ready to initiate the RA procedure */ @@ -375,7 +360,7 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, mac->RA_RAPID_found = 0; /* Set RA_PREAMBLE_POWER_RAMPING_STEP */ - switch (nr_rach_ConfigCommon->rach_ConfigGeneric.powerRampingStep){ // in dB + switch (rach_ConfigGeneric->powerRampingStep){ // in dB case 0: prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP = 0; break; @@ -444,7 +429,7 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, mac->RA_active = 1; prach_resources->Msg3 = payload; - ra_ResponseWindow = nr_rach_ConfigCommon->rach_ConfigGeneric.ra_ResponseWindow; + ra_ResponseWindow = rach_ConfigGeneric->ra_ResponseWindow; switch (ra_ResponseWindow) { case 0: mac->RA_window_cnt = 1; @@ -528,38 +513,38 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, mac->RA_PREAMBLE_TRANSMISSION_COUNTER++; preambleTransMax = -1; - switch (nr_rach_ConfigCommon->rach_ConfigGeneric.preambleTransMax) { - case NR_RACH_ConfigGeneric__preambleTransMax_n3: + switch (rach_ConfigGeneric->preambleTransMax) { + case 0: preambleTransMax = 3; break; - case NR_RACH_ConfigGeneric__preambleTransMax_n4: + case 1: preambleTransMax = 4; break; - case NR_RACH_ConfigGeneric__preambleTransMax_n5: + case 2: preambleTransMax = 5; break; - case NR_RACH_ConfigGeneric__preambleTransMax_n6: + case 3: preambleTransMax = 6; break; - case NR_RACH_ConfigGeneric__preambleTransMax_n7: + case 4: preambleTransMax = 7; break; - case NR_RACH_ConfigGeneric__preambleTransMax_n8: + case 5: preambleTransMax = 8; break; - case NR_RACH_ConfigGeneric__preambleTransMax_n10: + case 6: preambleTransMax = 10; break; - case NR_RACH_ConfigGeneric__preambleTransMax_n20: + case 7: preambleTransMax = 20; break; - case NR_RACH_ConfigGeneric__preambleTransMax_n50: + case 8: preambleTransMax = 50; break; - case NR_RACH_ConfigGeneric__preambleTransMax_n100: + case 9: preambleTransMax = 100; break; - case NR_RACH_ConfigGeneric__preambleTransMax_n200: + case 10: preambleTransMax = 200; break; } From 0d6e8ea0fbba4dc3457c4b1305671649f2e77df0 Mon Sep 17 00:00:00 2001 From: cig Date: Tue, 25 Feb 2020 11:14:03 +0100 Subject: [PATCH 066/553] Interface MAC-PHY for RA: passing FAPI PRACH PDU params to PHY --- openair1/PHY/INIT/nr_parms.c | 8 ------ openair1/PHY/NR_UE_TRANSPORT/nr_prach.c | 15 ++++++---- openair1/SCHED_NR_UE/fapi_nr_ue_l1.c | 32 ++++++++++++++------- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 4 --- 4 files changed, 31 insertions(+), 28 deletions(-) diff --git a/openair1/PHY/INIT/nr_parms.c b/openair1/PHY/INIT/nr_parms.c index 70fa9e824f..1ae0a47d59 100644 --- a/openair1/PHY/INIT/nr_parms.c +++ b/openair1/PHY/INIT/nr_parms.c @@ -344,14 +344,6 @@ int nr_init_frame_parms_ue(NR_DL_FRAME_PARMS *fp, fp->ssb_start_subcarrier = (12 * config->ssb_table.ssb_offset_point_a + sco); - // WIP temporary hardcoded - fp->prach_config_common.rootSequenceIndex = 22; // 0 - fp->prach_config_common.prach_Config_enabled = 1; - fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig = 1; // 13 - fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex = 0; // 98 - fp->prach_config_common.prach_ConfigInfo.highSpeedFlag = 0; - fp->prach_config_common.prach_ConfigInfo.msg1_frequencystart = 0; - // definition of Lmax according to ts 38.213 section 4.1 if (fp->dl_CarrierFreq < 6e9) { if(fp->frame_type && (fp->ssb_type==2)) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c index 34331a957d..bfe8179c14 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c @@ -65,9 +65,9 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) //uint8_t tdd_config = ue->frame_parms.tdd_config; NR_DL_FRAME_PARMS *fp=&ue->frame_parms; uint16_t rootSequenceIndex = fp->prach_config_common.rootSequenceIndex; - uint8_t prach_ConfigIndex = fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex; uint8_t Ncs_config = fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig; uint8_t restricted_set = fp->prach_config_common.prach_ConfigInfo.highSpeedFlag; + uint16_t prach_fmt = ue->prach_resources[gNB_id]->prach_format; uint8_t preamble_index = ue->prach_resources[gNB_id]->ra_PreambleIndex; //uint8_t tdd_mapindex = ue->prach_resources[gNB_id]->ra_TDD_map_index; int16_t *prachF = ue->prach_vars[gNB_id]->prachF; @@ -82,7 +82,6 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) uint16_t preamble_index0,n_shift_ra,n_shift_ra_bar; uint16_t d_start,numshift; - uint16_t prach_fmt = get_nr_prach_fmt(prach_ConfigIndex,fp->frame_type,fp->freq_range); //uint8_t Nsp=2; //uint8_t f_ra,t1_ra; uint16_t N_ZC = (prach_fmt<4)?839:139; @@ -224,9 +223,15 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) #ifdef NR_PRACH_DEBUG if (NCS>0) - LOG_I(PHY,"Generate PRACH for RootSeqIndex %d, Preamble Index %d, PRACH Format %x, prach_ConfigIndex %d, NCS %d (NCS_config %d, N_ZC/NCS %d): Preamble_offset %d, Preamble_shift %d\n", - rootSequenceIndex,preamble_index,prach_fmt,prach_ConfigIndex,NCS,Ncs_config,N_ZC/NCS, - preamble_offset,preamble_shift); + LOG_I(PHY,"Generate PRACH for RootSeqIndex %d, Preamble Index %d, PRACH Format %x, NCS %d (NCS_config %d, N_ZC/NCS %d): Preamble_offset %d, Preamble_shift %d\n", + rootSequenceIndex, + preamble_index, + prach_fmt, + NCS, + Ncs_config, + N_ZC/NCS, + preamble_offset, + preamble_shift); #endif diff --git a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c index f365d00c89..cb53fe4920 100644 --- a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c +++ b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c @@ -54,8 +54,6 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ NR_UE_PDCCH *pdcch_vars = PHY_vars_UE_g[module_id][cc_id]->pdcch_vars[thread_id][0]; NR_UE_DLSCH_t *dlsch0 = PHY_vars_UE_g[module_id][cc_id]->dlsch[thread_id][0][0]; NR_UE_ULSCH_t *ulsch0 = PHY_vars_UE_g[module_id][cc_id]->ulsch[thread_id][0][0]; - //NR_DL_FRAME_PARMS frame_parms = PHY_vars_UE_g[module_id][cc_id]->frame_parms; - //NR_PRACH_RESOURCES_t *prach_resources = PHY_vars_UE_g[module_id][cc_id]->prach_resources[0]; if(scheduled_response->dl_config != NULL){ fapi_nr_dl_config_request_t *dl_config = scheduled_response->dl_config; @@ -112,10 +110,16 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ for (i = 0; i < ul_config->number_pdus; ++i){ - uint8_t pdu_type = ul_config->ul_config_list[i].pdu_type, pucch_resource_id, current_harq_pid, format; - fapi_nr_ul_config_pusch_pdu_rel15_t *pusch_config_pdu; - fapi_nr_ul_config_pucch_pdu *pucch_config_pdu; + uint8_t pdu_type = ul_config->ul_config_list[i].pdu_type, pucch_resource_id, current_harq_pid, format, gNB_id = 0; + /* PRACH */ + NR_DL_FRAME_PARMS *fp; + NR_PRACH_RESOURCES_t *prach_resources; + NR_PRACH_CONFIG_COMMON *prach_config_common; fapi_nr_ul_config_prach_pdu *prach_config_pdu; + /* PUSCH */ + fapi_nr_ul_config_pusch_pdu_rel15_t *pusch_config_pdu; + /* PUCCH */ + fapi_nr_ul_config_pucch_pdu *pucch_config_pdu; PUCCH_ConfigCommon_nr_t *pucch_config_common_nr; PUCCH_Config_t *pucch_config_dedicated_nr; PUCCH_format_t *format_params; @@ -183,13 +187,19 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ case (FAPI_NR_UL_CONFIG_TYPE_PRACH): // prach config pdu + fp = &PHY_vars_UE_g[module_id][cc_id]->frame_parms; + prach_resources = &PHY_vars_UE_g[module_id][cc_id]->prach_resources[gNB_id]; + prach_config_common = &fp->prach_config_common; prach_config_pdu = &ul_config->ul_config_list[i].prach_config_pdu; - /*frame_parms.prach_config_common.rootSequenceIndex = prach_config_pdu->root_sequence_index; - frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex = prach_config_pdu->prach_configuration_index; - frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig = prach_config_pdu->zero_correlation_zone_config; - frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag = prach_config_pdu->restrictedset_config; - frame_parms.prach_config_common.prach_ConfigInfo.prach_FreqOffset = prach_config_pdu->prach_freq_offset;*/ - ////prach_resources->ra_PreambleIndex = prach_config_pdu->preamble_index; + + prach_config_common->prach_Config_enabled = 1; + prach_config_common->rootSequenceIndex = prach_config_pdu->root_seq_id; + prach_config_common->prach_ConfigInfo.zeroCorrelationZoneConfig = prach_config_pdu->num_cs; + prach_config_common->prach_ConfigInfo.highSpeedFlag = prach_config_pdu->restricted_set; + prach_config_common->prach_ConfigInfo.msg1_frequencystart = prach_config_pdu->freq_msg1; + + prach_resources->prach_format = prach_config_pdu->prach_format; + break; default: diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 36a2316ebe..ceb523f94c 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -2273,11 +2273,7 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, /* RACH */ if ((ue->UE_mode[gNB_id] == PRACH) && (ue->frame_parms.prach_config_common.prach_Config_enabled == 1)) { - - // check if we have PRACH opportunity - if (is_nr_prach_subframe(&ue->frame_parms, frame_tx, slot_tx)) { nr_ue_prach_procedures(ue, proc, gNB_id, mode); - } } else { ue->generate_nr_prach = 0; From 22d43925e05cc7fc898cdafd9ba3c01894bbc3bc Mon Sep 17 00:00:00 2001 From: cig Date: Wed, 26 Feb 2020 13:59:30 +0100 Subject: [PATCH 067/553] Changes to the logic in nr_ue_dl_indication and nr_ue_prach_scheduler --- executables/nr-ue.c | 40 ++++++++++---------- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 7 ++-- openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c | 4 +- 3 files changed, 25 insertions(+), 26 deletions(-) diff --git a/executables/nr-ue.c b/executables/nr-ue.c index 239f4aa4bc..e8b00051ee 100644 --- a/executables/nr-ue.c +++ b/executables/nr-ue.c @@ -408,8 +408,6 @@ void processSlotTX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.n_layers = precod_nbr_layers; scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.harq_process_nbr = harq_pid; - //nr_ue_prach_scheduler(mod_id, proc->frame_rx, proc->nr_tti_rx); - nr_ue_scheduled_response(&scheduled_response); if (UE->mode != loop_through_memory) { @@ -474,23 +472,6 @@ void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { pdcp_fifo_flush_sdus(&ctxt); } } - - - // no UL for now - /* - if (UE->mac_enabled==1) { - // trigger L2 to run ue_scheduler thru IF module - // [TODO] mapping right after NR initial sync - if(UE->if_inst != NULL && UE->if_inst->ul_indication != NULL) { - UE->ul_indication.module_id = 0; - UE->ul_indication.gNB_index = 0; - UE->ul_indication.cc_id = 0; - UE->ul_indication.frame = proc->frame_rx; - UE->ul_indication.slot = proc->nr_tti_rx; - UE->if_inst->ul_indication(&UE->ul_indication); - } - } - */ } /*! @@ -507,11 +488,15 @@ typedef struct processingData_s { } processingData_t; void UE_processing(void *arg) { - processingData_t *rxtxD=(processingData_t *) arg; + processingData_t *rxtxD = (processingData_t *) arg; UE_nr_rxtx_proc_t *proc = &rxtxD->proc; PHY_VARS_NR_UE *UE = rxtxD->UE; - uint8_t gNB_id = 0; + uint8_t gNB_id = 0, CC_id = 0; + module_id_t mod_id = 0; + + nr_uplink_indication_t ul_indication; + memset((void*)&ul_indication, 0, sizeof(ul_indication)); // params for UL time alignment procedure NR_UL_TIME_ALIGNMENT_t *ul_time_alignment = &UE->ul_time_alignment[gNB_id]; @@ -538,6 +523,19 @@ void UE_processing(void *arg) { processSlotRX(UE, proc); + if (UE->mac_enabled == 1) { + // trigger L2 to run ue_scheduler thru IF module + // [TODO] mapping right after NR initial sync + if(UE->if_inst != NULL && UE->if_inst->ul_indication != NULL) { + ul_indication.module_id = mod_id; + ul_indication.gNB_index = gNB_id; + ul_indication.cc_id = CC_id; + ul_indication.frame = proc->frame_rx; + ul_indication.slot = proc->nr_tti_rx; + UE->if_inst->ul_indication(&ul_indication); + } + } + processSlotTX(UE, proc); } diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 64ce5388b9..5710575719 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -766,9 +766,7 @@ void nr_ue_prach_scheduler(module_id_t module_idP, frame_t frameP, sub_frame_t s NR_RACH_ConfigGeneric_t *rach_ConfigGeneric = &setup->rach_ConfigGeneric; config_index = rach_ConfigGeneric->prach_ConfigurationIndex; - ////nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[module_idP]->UL_tti_req[0]; - - if (is_nr_DL_slot(scc, slotP) == 1) { + if (is_nr_UL_slot(scc, slotP)) { if (setup->msg1_SubcarrierSpacing) mu = *setup->msg1_SubcarrierSpacing; @@ -810,7 +808,7 @@ void nr_ue_prach_scheduler(module_id_t module_idP, frame_t frameP, sub_frame_t s ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PRACH; prach_config_pdu = &ul_config->ul_config_list[ul_config->number_pdus].prach_config_pdu; - memset(prach_config_pdu,0,sizeof(fapi_nr_ul_config_prach_pdu)); + memset(prach_config_pdu, 0, sizeof(fapi_nr_ul_config_prach_pdu)); ul_config->number_pdus += 1; ncs = get_NCS(rach_ConfigGeneric->zeroCorrelationZoneConfig, format0, setup->restrictedSetConfig); @@ -886,6 +884,7 @@ void nr_ue_prach_scheduler(module_id_t module_idP, frame_t frameP, sub_frame_t s } } } + mac->scheduled_response.ul_config = ul_config; } } diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c index f9967dba2e..430f79e703 100644 --- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c @@ -122,6 +122,9 @@ int nr_ue_ul_indication(nr_uplink_indication_t *ul_info){ ul_info->ssb_index, 0, 0); // TODO check tx/rx frame/slot is need for NR version + /*if (is_nr_UL_slot(mac->scc, ul_info->slot)) + nr_ue_prach_scheduler(module_id, ul_info->frame, ul_info->slot);*/ // WIP TbD set tx frame/slot + switch(ret){ case UE_CONNECTION_OK: break; @@ -135,7 +138,6 @@ int nr_ue_ul_indication(nr_uplink_indication_t *ul_info){ break; } - mac->if_module->scheduled_response(&mac->scheduled_response); return 0; From 19a1affc6877dd1b80cb97822660bcae898cd538 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 28 Feb 2020 17:49:00 +0100 Subject: [PATCH 068/553] some change in pdsch configuration for msg2 --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 8 +++++--- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c | 1 - openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 3 +-- openair2/RRC/NR/rrc_gNB_reconfig.c | 6 +++--- .../CONF/gnb.band78.tm1.106PRB.usrpn300.conf | 6 +++--- 5 files changed, 12 insertions(+), 12 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index cace9156e1..462c2c2009 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -468,7 +468,7 @@ void nr_generate_Msg2(module_id_t module_idP, NR_UE_list_t *UE_list = &nr_mac->UE_list; NR_SearchSpace_t *ss = ra->ra_ss; - uint16_t rnti = ra->rnti, RA_rnti = ra->RA_rnti, numDlDci; + uint16_t RA_rnti = ra->RA_rnti, numDlDci; long locationAndBandwidth; // uint8_t *vrb_map = cc[CC_id].vrb_map, CC_id; @@ -537,6 +537,7 @@ void nr_generate_Msg2(module_id_t module_idP, pdsch_pdu_rel15->rnti = RA_rnti; pdsch_pdu_rel15->pduIndex = 0; + pdsch_pdu_rel15->BWPSize = NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275); pdsch_pdu_rel15->BWPStart = NRRIV2PRBOFFSET(bwp->bwp_Common->genericParameters.locationAndBandwidth,275); pdsch_pdu_rel15->SubcarrierSpacing = bwp->bwp_Common->genericParameters.subcarrierSpacing; @@ -558,7 +559,7 @@ void nr_generate_Msg2(module_id_t module_idP, pdsch_pdu_rel15->dmrsPorts = 1; pdsch_pdu_rel15->resourceAlloc = 1; pdsch_pdu_rel15->rbStart = 0; - pdsch_pdu_rel15->rbSize = 6; + pdsch_pdu_rel15->rbSize = 7; pdsch_pdu_rel15->VRBtoPRBMapping = 0; // non interleaved for (int i=0; ibwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count; i++) { @@ -586,7 +587,7 @@ void nr_generate_Msg2(module_id_t module_idP, dci_pdu_rel15[0].mcs = pdsch_pdu_rel15->mcsIndex[0]; dci_pdu_rel15[0].tb_scaling = 0; - LOG_D(MAC, "[RAPROC] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d \n", + LOG_I(MAC, "[RAPROC] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d \n", dci_pdu_rel15[0].frequency_domain_assignment, pdsch_pdu_rel15->rbStart, pdsch_pdu_rel15->rbSize, @@ -711,6 +712,7 @@ void nr_fill_rar(uint8_t Mod_idP, rarh->T = 1; rarh->RAPID = ra->preamble_index; + /// RAR MAC payload /// rar->R = 0; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c index 2342d83ed9..7777e307fb 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c @@ -64,7 +64,6 @@ int nr_generate_dlsch_pdu(module_id_t module_idP, unsigned char * dlsch_buffer_ptr = sdus_payload; uint8_t last_size = 0; int offset = 0, mac_ce_size, i, timing_advance_cmd, tag_id = 0; - // MAC CEs uint8_t mac_header_control_elements[16], *ce_ptr; ce_ptr = &mac_header_control_elements[0]; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 5e54bc3a24..5c82406491 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -488,7 +488,7 @@ void configure_fapi_dl_Tx(module_id_t Mod_idP, tx_req->num_TLV = 1; tx_req->TLVs[0].length = tbs_bytes +2; - memcpy((void*)&tx_req->TLVs[0].value.direct[0], (void*)&nr_mac->UE_list.DLSCH_pdu[0][0].payload[0], tbs_bytes);; + memcpy((void*)&tx_req->TLVs[0].value.direct[0], (void*)&nr_mac->UE_list.DLSCH_pdu[0][0].payload[0], tbs_bytes); nr_mac->TX_req[CC_id].Number_of_PDUs++; nr_mac->TX_req[CC_id].SFN = frameP; @@ -618,7 +618,6 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, //mac_sdus[i] = (unsigned char) rand(); ((uint8_t *)gNB_mac->UE_list.DLSCH_pdu[0][0].payload[0])[i] = (unsigned char) (lrand48()&0xff); } - //Sending SDUs with size 1 //Initialize elements of sdu_lcids and sdu_lengths sdu_lcids[0] = 0x05; // DRB diff --git a/openair2/RRC/NR/rrc_gNB_reconfig.c b/openair2/RRC/NR/rrc_gNB_reconfig.c index 0dc0e83bd6..28aacd53d7 100644 --- a/openair2/RRC/NR/rrc_gNB_reconfig.c +++ b/openair2/RRC/NR/rrc_gNB_reconfig.c @@ -352,7 +352,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType0; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; @@ -720,7 +720,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType0; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1; bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; @@ -746,7 +746,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType0; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1; bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf index 8221cdbda5..de946ccd0b 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf @@ -74,8 +74,8 @@ gNBs = initialDLBWPk0_3 = 0; initialDLBWPmappingType_3 = 0; - #this is SS=1,L=5 - initialDLBWPstartSymbolAndLength_3 = 57; + #this is SS=1,L=4 + initialDLBWPstartSymbolAndLength_3 = 43; #uplinkConfigCommon #frequencyInfoUL @@ -154,7 +154,7 @@ gNBs = # ssb_PositionsInBurs_BitmapPR # 1=short, 2=medium, 3=long ssb_PositionsInBurst_PR = 2; - ssb_PositionsInBurst_Bitmap = 255; + ssb_PositionsInBurst_Bitmap = 1; # ssb_periodicityServingCell # 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1 From e21900bb0afc666f8bcece940d185018d44f40d5 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Mon, 2 Mar 2020 15:31:30 +0100 Subject: [PATCH 069/553] no data in dmrs symbol (hardcoded) --- openair1/PHY/NR_TRANSPORT/nr_dlsch.c | 17 +++++++++-------- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 9 +++++++-- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 14 ++++++++++---- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 2 +- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 1 + .../CONF/gnb.band78.tm1.106PRB.usrpn300.conf | 2 +- 6 files changed, 29 insertions(+), 16 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch.c index 4518280f6b..9eff98d4af 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch.c @@ -133,7 +133,7 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch, int16_t **mod_symbs = (int16_t**)dlsch->mod_symbs; int16_t **tx_layers = (int16_t**)dlsch->txdataF; int8_t Wf[2], Wt[2], l0, l_prime[2], delta; - + uint8_t nodata_dmrs = 1; uint8_t dmrs_Type = rel15->dmrsConfigType; int nb_re_dmrs = (dmrs_Type== NFAPI_NR_DMRS_TYPE1) ? 6:4; uint16_t n_dmrs = ((rel15->rbSize+rel15->rbStart)*nb_re_dmrs)<<1; @@ -297,15 +297,16 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch, } else { - - ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + (2*txdataF_offset)] = (amp * tx_layers[ap][m<<1]) >> 15; - ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + 1 + (2*txdataF_offset)] = (amp * tx_layers[ap][(m<<1) + 1]) >> 15; + if( (l != dmrs_symbol) || !nodata_dmrs) { + ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + (2*txdataF_offset)] = (amp * tx_layers[ap][m<<1]) >> 15; + ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + 1 + (2*txdataF_offset)] = (amp * tx_layers[ap][(m<<1) + 1]) >> 15; #ifdef DEBUG_DLSCH_MAPPING - printf("m %d\t l %d \t k %d \t txdataF: %d %d\n", -m, l, k, ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + (2*txdataF_offset)], - ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + 1 + (2*txdataF_offset)]); + printf("m %d\t l %d \t k %d \t txdataF: %d %d\n", + m, l, k, ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + (2*txdataF_offset)], + ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + 1 + (2*txdataF_offset)]); #endif - m++; + m++; + } } if (++k >= frame_parms->ofdm_symbol_size) k -= frame_parms->ofdm_symbol_size; diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index 73051df613..6a403c8d25 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -1382,13 +1382,18 @@ int32_t get_nr_uldl_offset(int nr_bandP) void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, int x_overhead, + uint8_t nodata_dmrs, uint8_t tb_scaling) { LOG_D(MAC, "TBS calculation\n"); nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_rel15 = &pdsch_pdu->pdsch_pdu_rel15; uint16_t N_PRB_oh = x_overhead; - uint8_t N_PRB_DMRS = (pdsch_rel15->dmrsConfigType == NFAPI_NR_DMRS_TYPE1)?6:4; //This only works for antenna port 1000 + uint8_t N_PRB_DMRS; + if (nodata_dmrs) + N_PRB_DMRS = 12; + else + N_PRB_DMRS = (pdsch_rel15->dmrsConfigType == NFAPI_NR_DMRS_TYPE1)?6:4; //This only works for antenna port 1000 uint8_t N_sh_symb = pdsch_rel15->NrOfSymbols; uint8_t Imcs = pdsch_rel15->mcsIndex[0]; uint16_t N_RE_prime = NR_NB_SC_PER_RB*N_sh_symb - N_PRB_DMRS - N_PRB_oh; @@ -1421,7 +1426,7 @@ void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, // pdsch_rel15->nb_mod_symbols = N_RE_prime*pdsch_rel15->n_prb*pdsch_rel15->nb_codewords; pdsch_rel15->mcsTable[0] = table_idx; - LOG_D(MAC, "TBS %d bytes: N_PRB_DMRS %d N_sh_symb %d N_PRB_oh %d R %d Qm %d table %d nb_symbols %d\n", + LOG_I(MAC, "TBS %d bytes: N_PRB_DMRS %d N_sh_symb %d N_PRB_oh %d R %d Qm %d table %d nb_symbols %d\n", TBS, N_PRB_DMRS, N_sh_symb, N_PRB_oh, R, Qm, table_idx,N_RE_prime*pdsch_rel15->rbSize*pdsch_rel15->NrOfCodewords ); } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index 462c2c2009..f12348eb79 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -546,7 +546,14 @@ void nr_generate_Msg2(module_id_t module_idP, pdsch_pdu_rel15->targetCodeRate[0] = nr_get_code_rate_dl(mcsIndex,0); pdsch_pdu_rel15->qamModOrder[0] = 2; pdsch_pdu_rel15->mcsIndex[0] = mcsIndex; - pdsch_pdu_rel15->mcsTable[0] = 0; + if (bwp->bwp_Dedicated->pdsch_Config->choice.setup->mcs_Table == NULL) + pdsch_pdu_rel15->mcsTable[0] = 0; + else{ + if (*bwp->bwp_Dedicated->pdsch_Config->choice.setup->mcs_Table == 0) + pdsch_pdu_rel15->mcsTable[0] = 1; + else + pdsch_pdu_rel15->mcsTable[0] = 2; + } pdsch_pdu_rel15->rvIndex[0] = 0; pdsch_pdu_rel15->dataScramblingId = *scc->physCellId; pdsch_pdu_rel15->nrOfLayers = 1; @@ -559,7 +566,7 @@ void nr_generate_Msg2(module_id_t module_idP, pdsch_pdu_rel15->dmrsPorts = 1; pdsch_pdu_rel15->resourceAlloc = 1; pdsch_pdu_rel15->rbStart = 0; - pdsch_pdu_rel15->rbSize = 7; + pdsch_pdu_rel15->rbSize = 6; pdsch_pdu_rel15->VRBtoPRBMapping = 0; // non interleaved for (int i=0; ibwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count; i++) { @@ -578,7 +585,6 @@ void nr_generate_Msg2(module_id_t module_idP, pdsch_pdu_rel15->NrOfSymbols = NrOfSymbols; pdsch_pdu_rel15->dlDmrsSymbPos = fill_dmrs_mask(NULL, scc->dmrs_TypeA_Position, NrOfSymbols); - dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET]; dci_pdu_rel15[0].frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize, pdsch_pdu_rel15->rbStart,dci10_bw); @@ -635,7 +641,7 @@ void nr_generate_Msg2(module_id_t module_idP, LOG_D(MAC,"[gNB %d][RAPROC] Frame %d, Subframe %d: RA state %d\n", module_idP, frameP, slotP, ra->state); x_Overhead = 0; - nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead, dci_pdu_rel15[0].tb_scaling); + nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead, 1, dci_pdu_rel15[0].tb_scaling); // DL TX request tx_req->PDU_length = pdsch_pdu_rel15->TBSize[0]; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 5c82406491..9b258b583f 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -406,7 +406,7 @@ int configure_fapi_dl_pdu(int Mod_idP, pdcch_pdu_rel15->DurationSymbols); int x_Overhead = 0; // should be 0 for initialBWP - nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead,0); + nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, 1, x_Overhead,0); // Hardcode it for now TBS = dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15.TBSize[0]; diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index 16370d238d..81969e051f 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -185,6 +185,7 @@ int to_absslot(nfapi_nr_config_request_scf_t *cfg,int frame,int slot); void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, int x_overhead, + uint8_t nodata_dmrs, uint8_t tb_scaling); /** \brief Computes Q based on I_MCS PDSCH and table_idx for downlink. Implements MCS Tables from 38.214. */ uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx); diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf index de946ccd0b..9a296db644 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf @@ -75,7 +75,7 @@ gNBs = initialDLBWPk0_3 = 0; initialDLBWPmappingType_3 = 0; #this is SS=1,L=4 - initialDLBWPstartSymbolAndLength_3 = 43; + initialDLBWPstartSymbolAndLength_3 = 57; #uplinkConfigCommon #frequencyInfoUL From 595e9c6f742bc57ca4e9ab6e9e157e60b97a597d Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Tue, 3 Mar 2020 14:28:45 +0100 Subject: [PATCH 070/553] RE computation for no data in dmrs symbol in phy fixed --- openair1/PHY/NR_TRANSPORT/nr_dlsch.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch.c index 9eff98d4af..74c4f5e328 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch.c @@ -139,7 +139,11 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch, uint16_t n_dmrs = ((rel15->rbSize+rel15->rbStart)*nb_re_dmrs)<<1; int16_t mod_dmrs[n_dmrs<<1]; - uint16_t nb_re = ((12*rel15->NrOfSymbols)-nb_re_dmrs-xOverhead)*rel15->rbSize*rel15->NrOfCodewords; + uint16_t nb_re; + if (nodata_dmrs) // no data in dmrs symbol + nb_re = ((12*rel15->NrOfSymbols)-12-xOverhead)*rel15->rbSize*rel15->NrOfCodewords; + else + nb_re = ((12*rel15->NrOfSymbols)-nb_re_dmrs-xOverhead)*rel15->rbSize*rel15->NrOfCodewords; uint8_t Qm = rel15->qamModOrder[0]; uint32_t encoded_length = nb_re*Qm; From cbbfbca5fb421d13c9100f4c4b824dcf881a1276 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Tue, 3 Mar 2020 15:22:03 +0100 Subject: [PATCH 071/553] another fix in RE computation for no data in dmrs symbol in phy --- openair1/PHY/NR_TRANSPORT/nr_dlsch.c | 2 +- openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch.c index 74c4f5e328..b8d9fdea18 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch.c @@ -141,7 +141,7 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch, uint16_t nb_re; if (nodata_dmrs) // no data in dmrs symbol - nb_re = ((12*rel15->NrOfSymbols)-12-xOverhead)*rel15->rbSize*rel15->NrOfCodewords; + nb_re = ((12*rel15->NrOfSymbols)-12-xOverhead)*rel15->rbSize*rel15->NrOfCodewords; else nb_re = ((12*rel15->NrOfSymbols)-nb_re_dmrs-xOverhead)*rel15->rbSize*rel15->NrOfCodewords; uint8_t Qm = rel15->qamModOrder[0]; diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c index cd38614373..392ccfd1b0 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c @@ -337,7 +337,12 @@ int nr_dlsch_encoding(unsigned char *a, uint32_t E; uint8_t Ilbrm = 1; uint32_t Tbslbrm = 950984; //max tbs - uint8_t nb_re_dmrs = rel15->dmrsConfigType==NFAPI_NR_DMRS_TYPE1 ? 6:4; + uint8_t nodata_dmrs = 1; + uint8_t nb_re_dmrs; + if (nodata_dmrs) + nb_re_dmrs = 12; + else + nb_re_dmrs = rel15->dmrsConfigType==NFAPI_NR_DMRS_TYPE1 ? 6:4; uint16_t length_dmrs = get_num_dmrs(rel15->dlDmrsSymbPos); uint16_t R=rel15->targetCodeRate[0]; float Coderate = 0.0; From 444442d3e31e0d924569797b42fcbc0b149e793d Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Wed, 4 Mar 2020 16:58:49 +0100 Subject: [PATCH 072/553] mac scheduling of msg3 at gnb --- openair1/SCHED_NR/phy_procedures_nr_gNB.c | 4 +- openair2/GNB_APP/RRC_nr_paramsvalues.h | 24 ++-- openair2/GNB_APP/gnb_config.c | 4 + openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 2 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 131 ++++++++++++------ .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 2 +- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 3 +- openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 2 + .../CONF/gnb.band78.tm1.106PRB.usrpn300.conf | 5 + 9 files changed, 119 insertions(+), 58 deletions(-) diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index 61f2a8a1c9..4e5004f8b1 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -160,7 +160,7 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB, if (gNB->pdcch_pdu || gNB->ul_dci_pdu) { - LOG_I(PHY, "[gNB %d] Frame %d slot %d Calling nr_generate_dci_top (number of UL/DL DCI %d/%d)\n", + LOG_D(PHY, "[gNB %d] Frame %d slot %d Calling nr_generate_dci_top (number of UL/DL DCI %d/%d)\n", gNB->Mod_id, frame, slot, gNB->ul_dci_pdu==NULL?0:gNB->ul_dci_pdu->pdcch_pdu.pdcch_pdu_rel15.numDlDci, gNB->pdcch_pdu==NULL?0:gNB->pdcch_pdu->pdcch_pdu_rel15.numDlDci); @@ -178,7 +178,7 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB, for (int i=0; inum_pdsch_rnti; i++) { VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_GENERATE_DLSCH,1); - LOG_I(PHY, "PDSCH generation started (%d)\n", gNB->num_pdsch_rnti); + LOG_D(PHY, "PDSCH generation started (%d)\n", gNB->num_pdsch_rnti); nr_generate_pdsch(gNB->dlsch[i][0], gNB->nr_gold_pdsch_dmrs[slot], gNB->common_vars.txdataF, diff --git a/openair2/GNB_APP/RRC_nr_paramsvalues.h b/openair2/GNB_APP/RRC_nr_paramsvalues.h index fc90b93169..18d6dcdcf5 100644 --- a/openair2/GNB_APP/RRC_nr_paramsvalues.h +++ b/openair2/GNB_APP/RRC_nr_paramsvalues.h @@ -133,7 +133,8 @@ #define GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEXPR "prach_RootSequenceIndex_PR" #define GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEX "prach_RootSequenceIndex" #define GNB_CONFIG_STRING_MSG1SUBCARRIERSPACING "msg1_SubcarrierSpacing" -#define GNB_CONFIG_STRING_RESTRICTEDSETCONFIG "restrictedSetConfig" +#define GNB_CONFIG_STRING_RESTRICTEDSETCONFIG "restrictedSetConfig" +#define GNB_CONFIG_STRING_MSG3TRANSFPREC "msg3_transformPrecoder" #define GNB_CONFIG_STRING_PUSCHTIMEDOMAINALLOCATIONLIST "puschTimeDomainAllocationList" #define GNB_CONFIG_STRING_MSG3DELTAPREABMLE "msg3_DeltaPreamble" #define GNB_CONFIG_STRING_P0NOMINALWITHGRANT "p0_NominalWithGrant" @@ -312,10 +313,11 @@ {GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEXPR,NULL,0,uptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.present,defuintval:NR_RACH_ConfigCommon__prach_RootSequenceIndex_PR_l139,TYPE_UINT,0/*83*/},\ {GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEX,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.choice.l139,defint64val:0,TYPE_INT64,0/*84*/},\ {GNB_CONFIG_STRING_RESTRICTEDSETCONFIG,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig,defintval:NR_RACH_ConfigCommon__restrictedSetConfig_unrestrictedSet,TYPE_INT64,0/*85*/}, \ -{GNB_CONFIG_STRING_INITIALULBWPK2_0,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->k2,defint64val:-1,TYPE_INT64,0/*86*/},\ -{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_0,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,/*87*/},\ -{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_0,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->startSymbolAndLength,defint64val:55,TYPE_INT64,0/*88*/},\ -{GNB_CONFIG_STRING_INITIALULBWPK2_1,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[1]->k2,defint64val:-1,TYPE_INT64,0/*89*/}, \ +{GNB_CONFIG_STRING_MSG3TRANSFPREC,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder,defintval:1,TYPE_INT64,0/*86*/}, \ +{GNB_CONFIG_STRING_INITIALULBWPK2_0,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->k2,defint64val:-1,TYPE_INT64,0/*87*/},\ +{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_0,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,/*88*/},\ +{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_0,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->startSymbolAndLength,defint64val:55,TYPE_INT64,0/*89*/},\ +{GNB_CONFIG_STRING_INITIALULBWPK2_1,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[1]->k2,defint64val:-1,TYPE_INT64,0/*90*/}, \ {GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_1,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[1]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_1,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[1]->startSymbolAndLength,defint64val:53,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPK2_2,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[2]->k2,defint64val:-1,TYPE_INT64,0},\ @@ -325,7 +327,7 @@ {GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_3,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[3]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_3,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[3]->startSymbolAndLength,defint64val:53,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPK2_4,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[4]->k2,defint64val:-1,TYPE_INT64,0},\ -{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_4,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[4]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0 /*99*/}, \ +{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_4,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[4]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0 /*100*/}, \ {GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_4,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[4]->startSymbolAndLength,defint64val:55,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPK2_5,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[5]->k2,defint64val:-1,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_5,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[5]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ @@ -335,7 +337,7 @@ {GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_6,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[6]->startSymbolAndLength,defint64val:55,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPK2_7,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[7]->k2,defint64val:-1,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_7,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[7]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ -{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_7,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[7]->startSymbolAndLength,defint64val:53,TYPE_INT64,0/*109*/}, \ +{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_7,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[7]->startSymbolAndLength,defint64val:53,TYPE_INT64,0/*110*/}, \ {GNB_CONFIG_STRING_INITIALULBWPK2_8,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[8]->k2,defint64val:-1,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_8,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[8]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_8,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[8]->startSymbolAndLength,defint64val:55,TYPE_INT64,0},\ @@ -345,7 +347,7 @@ {GNB_CONFIG_STRING_INITIALULBWPK2_10,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[10]->k2,defint64val:-1,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_10,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[10]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_10,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[10]->startSymbolAndLength,defint64val:55,TYPE_INT64,0},\ -{GNB_CONFIG_STRING_INITIALULBWPK2_11,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[11]->k2,defint64val:-1,TYPE_INT64,0/*119*/}, \ +{GNB_CONFIG_STRING_INITIALULBWPK2_11,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[11]->k2,defint64val:-1,TYPE_INT64,0/*120*/}, \ {GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_11,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[11]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_11,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[11]->startSymbolAndLength,defint64val:53,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPK2_12,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[12]->k2,defint64val:-1,TYPE_INT64,0},\ @@ -355,7 +357,7 @@ {GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_13,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[13]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_13,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[13]->startSymbolAndLength,defint64val:53,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPK2_14,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[14]->k2,defint64val:-1,TYPE_INT64,0},\ -{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_14,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[14]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0 /*129*/}, \ +{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_14,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[14]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0 /*130*/}, \ {GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_14,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[14]->startSymbolAndLength,defint64val:55,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPK2_15,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[15]->k2,defint64val:-1,TYPE_INT64,0},\ {GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_15,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[15]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\ @@ -365,7 +367,7 @@ {GNB_CONFIG_STRING_PUCCHGROUPHOPPING, NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->pucch_GroupHopping,defint64val:NR_PUCCH_ConfigCommon__pucch_GroupHopping_neither,TYPE_INT64,0},\ {GNB_CONFIG_STRING_HOPPINGID, NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->hoppingId,defint64val:40,TYPE_INT64,0},\ {GNB_CONFIG_STRING_P0NOMINAL, NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->p0_nominal,defint64val:1,TYPE_INT64,0},\ -{GNB_CONFIG_STRING_SSBPOSITIONSINBURSTPR,NULL,0,uptr:&scc->ssb_PositionsInBurst->present,defuintval:NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_mediumBitmap,TYPE_UINT,0/*139*/}, \ +{GNB_CONFIG_STRING_SSBPOSITIONSINBURSTPR,NULL,0,uptr:&scc->ssb_PositionsInBurst->present,defuintval:NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_mediumBitmap,TYPE_UINT,0/*140*/}, \ {GNB_CONFIG_STRING_SSBPOSITIONSINBURST,NULL,0,u64ptr:&ssb_bitmap,defintval:0xff,TYPE_UINT64,0}, \ {GNB_CONFIG_STRING_REFERENCESUBCARRIERSPACING,NULL,0,i64ptr:&scc->tdd_UL_DL_ConfigurationCommon->referenceSubcarrierSpacing,defint64val:NR_SubcarrierSpacing_kHz30,TYPE_INT64,0},\ {GNB_CONFIG_STRING_DLULTRANSMISSIONPERIODICITY,NULL,0,i64ptr:&scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity,defint64val:NR_TDD_UL_DL_Pattern__dl_UL_TransmissionPeriodicity_ms0p5,TYPE_INT64,0},\ @@ -379,7 +381,7 @@ {GNB_CONFIG_STRING_NROFUPLINKSLOTS2,NULL,0,i64ptr:&scc->tdd_UL_DL_ConfigurationCommon->pattern2->nrofUplinkSlots,defint64val:-1,TYPE_INT64,0},\ {GNB_CONFIG_STRING_NROFUPLINKSYMBOLS2,NULL,0,i64ptr:&scc->tdd_UL_DL_ConfigurationCommon->pattern2->nrofUplinkSymbols,defint64val:-1,TYPE_INT64,0},\ {GNB_CONFIG_STRING_SSPBCHBLOCKPOWER,NULL,0,i64ptr:&scc->ss_PBCH_BlockPower,defint64val:20,TYPE_INT64,0}, \ -{GNB_CONFIG_STRING_MSG1SUBCARRIERSPACING,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing,defintval:-1,TYPE_INT64,0/*86*/}} +{GNB_CONFIG_STRING_MSG1SUBCARRIERSPACING,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing,defintval:-1,TYPE_INT64,0}} diff --git a/openair2/GNB_APP/gnb_config.c b/openair2/GNB_APP/gnb_config.c index 1c8657aec1..6fc159113e 100644 --- a/openair2/GNB_APP/gnb_config.c +++ b/openair2/GNB_APP/gnb_config.c @@ -255,6 +255,10 @@ void fix_scc(NR_ServingCellConfigCommon_t *scc,uint64_t ssbmap) { scc->uplinkConfigCommon->frequencyInfoUL->absoluteFrequencyPointA = NULL; } + // default value for msg3 precoder is NULL (0 means enabled) + if (*scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder!=0) + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder = NULL; + // fix libconfig (asn1c uses long) scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.preambleReceivedTargetPower-=((long)1<<32); *scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->p0_NominalWithGrant-=((long)1<<32); diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index 6a403c8d25..fd2e73bcc3 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -1426,7 +1426,7 @@ void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, // pdsch_rel15->nb_mod_symbols = N_RE_prime*pdsch_rel15->n_prb*pdsch_rel15->nb_codewords; pdsch_rel15->mcsTable[0] = table_idx; - LOG_I(MAC, "TBS %d bytes: N_PRB_DMRS %d N_sh_symb %d N_PRB_oh %d R %d Qm %d table %d nb_symbols %d\n", + LOG_D(MAC, "TBS %d bytes: N_PRB_DMRS %d N_sh_symb %d N_PRB_oh %d R %d Qm %d table %d nb_symbols %d\n", TBS, N_PRB_DMRS, N_sh_symb, N_PRB_oh, R, Qm, table_idx,N_RE_prime*pdsch_rel15->rbSize*pdsch_rel15->NrOfCodewords ); } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index f12348eb79..0310f7787b 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -43,6 +43,7 @@ extern RAN_CONTEXT_t RC; uint16_t nr_slots_per_frame[5] = {10, 20, 40, 80, 160}; +uint8_t DELTA[4]= {2,3,4,6}; void schedule_nr_prach(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) { @@ -352,17 +353,40 @@ void nr_schedule_RA(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ } void nr_get_Msg3alloc(NR_ServingCellConfigCommon_t *scc, + NR_BWP_Uplink_t *ubwp, sub_frame_t current_slot, frame_t current_frame, NR_RA_t *ra) { - // first simple version to schedule msg3 - // it is schedulend in mixed slot in the following frame - ra->Msg3_frame = current_frame+1; - ra->Msg3_slot = current_slot; - ra->msg3_nb_rb = 6; - ra->msg3_first_rb = 0; + // msg3 is schedulend in mixed slot in the following TDD period + // for now we consider a TBS of 18 bytes + int mu = ubwp->bwp_Common->genericParameters.subcarrierSpacing; + int StartSymbolIndex, NrOfSymbols, startSymbolAndLength, temp_slot; + ra->Msg3_tda_id = 16; // initialization to a value above limit + + for (int i=0; ibwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.count; i++) { + startSymbolAndLength = ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[i]->startSymbolAndLength; + SLIV2SL(startSymbolAndLength, &StartSymbolIndex, &NrOfSymbols); + // we want to transmit in the uplink symbols of mixed slot + if (NrOfSymbols == scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols) { + ra->Msg3_tda_id = i; + break; + } + } + AssertFatal(ra->Msg3_tda_id<16,"Unable to find Msg3 time domain allocation in list\n"); + + uint8_t k2 = *ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[ra->Msg3_tda_id]->k2; + + temp_slot = current_slot + k2 + DELTA[mu]; // msg3 slot according to 8.3 in 38.213 + ra->Msg3_slot = temp_slot%nr_slots_per_frame[mu]; + if (nr_slots_per_frame[mu]>temp_slot) + ra->Msg3_frame = current_frame; + else + ra->Msg3_frame = current_frame + (temp_slot/nr_slots_per_frame[mu]); + + ra->msg3_nb_rb = 18; + ra->msg3_first_rb = 0; } // WIP @@ -395,7 +419,6 @@ void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t AssertFatal(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count == 1, "downlinkBWP_ToAddModList has %d BWP!\n", secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count); NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[ra->bwp_id-1]; - NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[ra->bwp_id-1]; LOG_D(MAC, "Frame %d, Subframe %d Adding Msg3 UL Config Request for (%d,%d) : (%d,%d,%d) for rnti: %d\n", frameP, slotP, @@ -406,48 +429,68 @@ void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t ra->msg3_round, ra->rnti); + int startSymbolAndLength = ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[ra->Msg3_tda_id]->startSymbolAndLength; + int start_symbol_index,nr_of_symbols; + SLIV2SL(startSymbolAndLength, &start_symbol_index, &nr_of_symbols); + pusch_pdu->pdu_bit_map = PUSCH_PDU_BITMAP_PUSCH_DATA; pusch_pdu->rnti = ra->rnti; pusch_pdu->handle = 0; - pusch_pdu->bwp_size = NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275); - pusch_pdu->bwp_start = NRRIV2PRBOFFSET(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275); + int abwp_size = NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275); + int abwp_start = NRRIV2PRBOFFSET(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275); + int ibwp_size = NRRIV2BW(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth,275); + int ibwp_start = NRRIV2PRBOFFSET(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth,275); + if ((ibwp_start < abwp_start) || (ibwp_size > abwp_size)) + pusch_pdu->bwp_start = abwp_start; + else + pusch_pdu->bwp_start = ibwp_start; + pusch_pdu->bwp_size = ibwp_size; pusch_pdu->subcarrier_spacing = ubwp->bwp_Common->genericParameters.subcarrierSpacing; pusch_pdu->cyclic_prefix = 0; - pusch_pdu->mcs_index = 9; + pusch_pdu->mcs_index = 0; pusch_pdu->mcs_table = 0; pusch_pdu->target_code_rate = nr_get_code_rate_ul(pusch_pdu->mcs_index,pusch_pdu->mcs_table); pusch_pdu->qam_mod_order = nr_get_Qm_ul(pusch_pdu->mcs_index,pusch_pdu->mcs_table); - pusch_pdu->transform_precoding = 0; - pusch_pdu->data_scrambling_id = 0; + if (scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder == NULL) + pusch_pdu->transform_precoding = 1; + else + pusch_pdu->transform_precoding = 0; + pusch_pdu->data_scrambling_id = *scc->physCellId; pusch_pdu->nrOfLayers = 1; - pusch_pdu->ul_dmrs_symb_pos = 1; + pusch_pdu->ul_dmrs_symb_pos = 1; // ok for now but use fill dmrs mask later pusch_pdu->dmrs_config_type = 0; - pusch_pdu->ul_dmrs_scrambling_id = 0; //If provided and the PUSCH is not a msg3 PUSCH, otherwise, L2 should set this to physical cell id. + pusch_pdu->ul_dmrs_scrambling_id = *scc->physCellId; //If provided and the PUSCH is not a msg3 PUSCH, otherwise, L2 should set this to physical cell id. pusch_pdu->scid = 0; //DMRS sequence initialization [TS38.211, sec 6.4.1.1.1]. Should match what is sent in DCI 0_1, otherwise set to 0. pusch_pdu->resource_alloc = 1; //type 1 - //pusch_pdu->rb_bitmap;// for ressource alloc type 0 pusch_pdu->rb_start = ra->msg3_first_rb; pusch_pdu->rb_size = ra->msg3_nb_rb; pusch_pdu->vrb_to_prb_mapping = 0; - pusch_pdu->frequency_hopping = 0; + if (ubwp->bwp_Dedicated->pusch_Config->choice.setup->frequencyHopping == NULL) + pusch_pdu->frequency_hopping = 0; + else + pusch_pdu->frequency_hopping = 1; //pusch_pdu->tx_direct_current_location;//The uplink Tx Direct Current location for the carrier. Only values in the value range of this field between 0 and 3299, which indicate the subcarrier index within the carrier corresponding 1o the numerology of the corresponding uplink BWP and value 3300, which indicates "Outside the carrier" and value 3301, which indicates "Undetermined position within the carrier" are used. [TS38.331, UplinkTxDirectCurrentBWP IE] pusch_pdu->uplink_frequency_shift_7p5khz = 0; //Resource Allocation in time domain - pusch_pdu->start_symbol_index = 12; - pusch_pdu->nr_of_symbols = 2; + pusch_pdu->start_symbol_index = start_symbol_index; + pusch_pdu->nr_of_symbols = nr_of_symbols; //Optional Data only included if indicated in pduBitmap - pusch_pdu->pusch_data.rv_index = 0; + pusch_pdu->pusch_data.rv_index = 0; // 8.3 in 38.213 pusch_pdu->pusch_data.harq_process_id = 0; - pusch_pdu->pusch_data.new_data_indicator = 0; - pusch_pdu->pusch_data.tb_size = nr_compute_tbs(pusch_pdu->mcs_index, + pusch_pdu->pusch_data.new_data_indicator = 1; // new data + pusch_pdu->pusch_data.num_cb = 0; + pusch_pdu->pusch_data.tb_size = nr_compute_tbs(pusch_pdu->qam_mod_order, pusch_pdu->target_code_rate, pusch_pdu->rb_size, pusch_pdu->nr_of_symbols, - 6, //nb_re_dmrs - not sure where this is coming from - its not in the FAPI + 12, // nb dmrs set for no data in dmrs symbol 0, //nb_rb_oh 0, // to verify tb scaling - pusch_pdu->nrOfLayers = 1); - pusch_pdu->pusch_data.num_cb = 0; + pusch_pdu->nrOfLayers = 1)>>3; + + // calling function to fill rar message + nr_fill_rar(module_idP, ra, cc->RAR_pdu.payload, pusch_pdu); + } // WIP @@ -461,7 +504,7 @@ void nr_generate_Msg2(module_id_t module_idP, int UE_id = 0, dci_formats[2], rnti_types[2], CCEIndex, mcsIndex; int startSymbolAndLength = 0, StartSymbolIndex = -1, NrOfSymbols = 14, StartSymbolIndex_tmp, NrOfSymbols_tmp, x_Overhead, time_domain_assignment; - int coreset_id, aggregation , search_space_type = 0, N_RB_UL = 106; + int coreset_id, aggregation , search_space_type = 0; gNB_MAC_INST *nr_mac = RC.nrmac[module_idP]; NR_COMMON_channels_t *cc = &nr_mac->common_channels[0]; NR_RA_t *ra = &cc->ra[0]; @@ -528,6 +571,7 @@ void nr_generate_Msg2(module_id_t module_idP, AssertFatal(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count == 1, "downlinkBWP_ToAddModList has %d BWP!\n", secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count); NR_BWP_Downlink_t *bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[ra->bwp_id - 1]; + NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[ra->bwp_id-1]; LOG_D(MAC, "[RAPROC] Scheduling common search space DCI type 1 dlBWP BW %d\n", dci10_bw); @@ -633,10 +677,9 @@ void nr_generate_Msg2(module_id_t module_idP, dl_req->nPDUs+=2; // Program UL processing for Msg3 - nr_get_Msg3alloc(scc, slotP, frameP, ra); + nr_get_Msg3alloc(scc, ubwp, slotP, frameP, ra); LOG_I(MAC, "Frame %d, Subframe %d: Setting Msg3 reception for Frame %d Subframe %d\n", frameP, slotP, ra->Msg3_frame, ra->Msg3_slot); nr_add_msg3(module_idP, CC_id, frameP, slotP); - nr_fill_rar(module_idP, ra, cc[CC_id].RAR_pdu.payload, N_RB_UL); ra->state = WAIT_Msg3; LOG_D(MAC,"[gNB %d][RAPROC] Frame %d, Subframe %d: RA state %d\n", module_idP, frameP, slotP, ra->state); @@ -699,17 +742,14 @@ void nr_clear_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP){ void nr_fill_rar(uint8_t Mod_idP, NR_RA_t * ra, uint8_t * dlsch_buffer, - uint16_t N_RB_UL){ + nfapi_nr_pusch_pdu_t *pusch_pdu){ LOG_D(MAC, "[gNB] Generate RAR MAC PDU frame %d slot %d ", ra->Msg2_frame, ra-> Msg2_slot); - nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[Mod_idP]->UL_tti_req[0]; - nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[UL_tti_req->n_pdus-1].pusch_pdu; NR_RA_HEADER_RAPID *rarh = (NR_RA_HEADER_RAPID *) dlsch_buffer; NR_MAC_RAR *rar = (NR_MAC_RAR *) (dlsch_buffer + 1); - unsigned char frequency_hopping_flag = 0, csi_req = 0, tpc_command = 0, mcs = 9, t_alloc = 0; - uint8_t N_UL_Hop; - uint16_t ul_grant, f_alloc, prb_alloc; - int bwp_size; + unsigned char csi_req = 0, tpc_command = 0; + uint8_t N_UL_Hop, valid_bits; + uint16_t ul_grant, f_alloc, prb_alloc, bwp_size, truncation=0; /// E/T/RAPID subheader /// // E = 0, one only RAR, first and last @@ -718,7 +758,6 @@ void nr_fill_rar(uint8_t Mod_idP, rarh->T = 1; rarh->RAPID = ra->preamble_index; - /// RAR MAC payload /// rar->R = 0; @@ -732,19 +771,27 @@ void nr_fill_rar(uint8_t Mod_idP, // UL grant - ra->msg3_mcs = mcs; + ra->msg3_mcs = pusch_pdu->mcs_index; ra->msg3_TPC = tpc_command; bwp_size = pusch_pdu->bwp_size; prb_alloc = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size, pusch_pdu->rb_start, bwp_size); - if (frequency_hopping_flag){ - // PUSCH with frequency hopping - } else { - N_UL_Hop = 0; + if (bwp_size>180) { + AssertFatal(1==0,"Initial UBWP larger than 180 currently not supported"); + } + else { + valid_bits = (uint8_t)ceil(log2(bwp_size*(bwp_size+1)>>1)); } - f_alloc = (prb_alloc & 0xfff) | (N_UL_Hop << 12); - ul_grant = csi_req | (tpc_command << 1) | (mcs << 4) | (t_alloc << 8) | (f_alloc << 12) | (frequency_hopping_flag << 26); + if (pusch_pdu->frequency_hopping){ + AssertFatal(1==0,"PUSCH with frequency hopping currently not supported"); + } else { + for (int i=0; imsg3_mcs << 4) | (ra->Msg3_tda_id << 8) | (f_alloc << 12) | (pusch_pdu->frequency_hopping << 26); rar->UL_GRANT_1 = (uint8_t) (ul_grant >> 24) & 0x07; rar->UL_GRANT_2 = (uint8_t) (ul_grant >> 16) & 0xff; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 9b258b583f..db85b8d6bd 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -798,7 +798,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, 6, //nb_re_dmrs - not sure where this is coming from - its not in the FAPI 0, //nb_rb_oh 0, - pusch_pdu->nrOfLayers = 1); + pusch_pdu->nrOfLayers = 1)>>3; pusch_pdu->pusch_data.num_cb = 0; //CBG not supported //pusch_pdu->pusch_data.cb_present_and_position; //pusch_pdu->pusch_uci; diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index 81969e051f..c7921de0ad 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -97,6 +97,7 @@ void nr_clear_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP); int nr_allocate_CCEs(int module_idP, int CC_idP, frame_t frameP, sub_frame_t slotP, int test_only); void nr_get_Msg3alloc(NR_ServingCellConfigCommon_t *scc, + NR_BWP_Uplink_t *ubwp, sub_frame_t current_subframe, frame_t current_frame, NR_RA_t *ra); @@ -109,7 +110,7 @@ void nr_get_Msg3alloc(NR_ServingCellConfigCommon_t *scc, void nr_fill_rar(uint8_t Mod_idP, NR_RA_t * ra, uint8_t * dlsch_buffer, - uint16_t N_RB_UL); + nfapi_nr_pusch_pdu_t *pusch_pdu); void schedule_nr_prach(module_id_t module_idP, frame_t frameP, sub_frame_t slotP); diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index b7f86fad68..b874f490ec 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -101,6 +101,8 @@ typedef struct { sub_frame_t Msg3_slot; /// Frame where Msg3 is to be sent frame_t Msg3_frame; + /// Msg3 time domain allocation index + uint8_t Msg3_tda_id; /// Subframe where Msg4 is to be sent sub_frame_t Msg4_slot; /// Frame where Msg4 is to be sent diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf index 9a296db644..611eaa910c 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf @@ -141,6 +141,11 @@ gNBs = # this is SS=0 L=12 initialULBWPstartSymbolAndLength_1 = 69; + initialULBWPk2_2 = 7; + initialULBWPmappingType_2 = 1; + # this is SS=10 L=4 + initialULBWPstartSymbolAndLength_2 = 52; + msg3_DeltaPreamble = 1; p0_NominalWithGrant =-90; From 94b7d132c5b9424ae4cbc4f2585c530d3c19ef5f Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Wed, 4 Mar 2020 17:56:37 +0100 Subject: [PATCH 073/553] fix for tpc command --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index 0310f7787b..4c962cb50f 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -263,11 +263,11 @@ void nr_initiate_ra_proc(module_id_t module_idP, VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_INITIATE_RA_PROC, 1); - LOG_I(MAC, "[gNB %d][RAPROC] CC_id %d Frame %d, Subframe %d Initiating RA procedure for preamble index %d\n", module_idP, CC_id, frameP, slotP, preamble_index); + LOG_I(MAC, "[gNB %d][RAPROC] CC_id %d Frame %d, Slot %d Initiating RA procedure for preamble index %d\n", module_idP, CC_id, frameP, slotP, preamble_index); if (ra->state == RA_IDLE) { int loop = 0; - LOG_D(MAC, "Frame %d, Subframe %d: Activating RA process \n", frameP, slotP); + LOG_D(MAC, "Frame %d, Slot %d: Activating RA process \n", frameP, slotP); ra->state = Msg2; ra->timing_offset = timing_offset; ra->preamble_slot = slotP; @@ -747,10 +747,12 @@ void nr_fill_rar(uint8_t Mod_idP, LOG_D(MAC, "[gNB] Generate RAR MAC PDU frame %d slot %d ", ra->Msg2_frame, ra-> Msg2_slot); NR_RA_HEADER_RAPID *rarh = (NR_RA_HEADER_RAPID *) dlsch_buffer; NR_MAC_RAR *rar = (NR_MAC_RAR *) (dlsch_buffer + 1); - unsigned char csi_req = 0, tpc_command = 0; + unsigned char csi_req = 0, tpc_command; uint8_t N_UL_Hop, valid_bits; uint16_t ul_grant, f_alloc, prb_alloc, bwp_size, truncation=0; + tpc_command = 3; // this is 0 dB + /// E/T/RAPID subheader /// // E = 0, one only RAR, first and last // T = 1, RAPID From f62d94c76f276b57712d07482916e2ffc2f821b0 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Thu, 5 Mar 2020 09:59:59 +0100 Subject: [PATCH 074/553] correct scheduling of msg3 reception --- openair1/SCHED_NR/fapi_nr_l1.c | 10 +++--- openair1/SCHED_NR/phy_procedures_nr_gNB.c | 1 - openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 4 +++ openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 35 ++++++++++++------- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 2 ++ openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 4 +-- 6 files changed, 36 insertions(+), 20 deletions(-) diff --git a/openair1/SCHED_NR/fapi_nr_l1.c b/openair1/SCHED_NR/fapi_nr_l1.c index 33743104d2..5038f9acf8 100644 --- a/openair1/SCHED_NR/fapi_nr_l1.c +++ b/openair1/SCHED_NR/fapi_nr_l1.c @@ -174,6 +174,7 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){ case NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE: AssertFatal(pdcch_received == 0, "pdcch_received is not 0, we can only handle one PDCCH PDU per slot\n"); + LOG_I(PHY,"frame %d, slot %d, Got NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE for %d.%d\n",frame,slot,DL_req->SFN,DL_req->Slot); handle_nfapi_nr_pdcch_pdu(gNB, frame, slot, &dl_tti_pdu->pdcch_pdu); @@ -184,6 +185,7 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){ case NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE: { + LOG_I(PHY,"frame %d, slot %d, Got NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE for %d.%d\n",frame,slot,DL_req->SFN,DL_req->Slot); nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = &dl_tti_pdu->pdsch_pdu.pdsch_pdu_rel15; uint16_t pduIndex = pdsch_pdu_rel15->pduIndex; AssertFatal(TX_req->pdu_list[pduIndex].num_TLV == 1, "TX_req->pdu_list[%d].num_TLV %d != 1\n", @@ -205,21 +207,19 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){ for (int i = 0; i < number_ul_tti_pdu; i++) { switch (UL_tti_req->pdus_list[i].pdu_type) { case NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE: - LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE for %d.%d\n",frame,slot,UL_tti_req->SFN,UL_tti_req->Slot); + LOG_I(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_TTI_PUSCH_PDU_TYPE for %d.%d\n",frame,slot,UL_tti_req->SFN,UL_tti_req->Slot); nr_fill_ulsch(gNB,UL_tti_req->SFN,UL_tti_req->Slot,&UL_tti_req->pdus_list[i].pusch_pdu); break; case NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE: - LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE for %d.%d\n",frame,slot,UL_tti_req->SFN,UL_tti_req->Slot); + LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_TTI_PUCCH_PDU_TYPE for %d.%d\n",frame,slot,UL_tti_req->SFN,UL_tti_req->Slot); // handle_nfapi_nr_pucch_pdu(gNB,frame,slot,UL_tti_req->pdus_list[i].pucch_pdu); break; case NFAPI_NR_UL_CONFIG_PRACH_PDU_TYPE: - LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PRACH_PDU_TYPE for %d.%d\n",frame,slot,UL_tti_req->SFN,UL_tti_req->Slot); + LOG_I(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_TTI_PRACH_PDU_TYPE for %d.%d\n",frame,slot,UL_tti_req->SFN,UL_tti_req->Slot); nfapi_nr_prach_pdu_t *prach_pdu = &UL_tti_req->pdus_list[i].prach_pdu; nr_fill_prach(gNB,UL_tti_req->SFN,UL_tti_req->Slot,prach_pdu); nr_fill_prach_ru(gNB->RU_list[0],UL_tti_req->SFN,UL_tti_req->Slot,prach_pdu); break; } } - - } diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index 4e5004f8b1..798de7da76 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -407,7 +407,6 @@ void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) (ulsch_harq->slot == slot_rx) && (ulsch_harq->handled == 0)){ - uint8_t symbol_start = ulsch_harq->ulsch_pdu.ulsch_pdu_rel15.start_symbol; uint8_t symbol_end = symbol_start + ulsch_harq->ulsch_pdu.ulsch_pdu_rel15.number_symbols; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index 3a7648149f..163c4f2c52 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -387,8 +387,12 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, if (is_nr_UL_slot(cc->ServingCellConfigCommon,slot_rxP)) { + + schedule_nr_prach(module_idP, (frame_rxP+1)&1023, slot_rxP); + nr_schedule_reception_msg3(module_idP, 0, frame_rxP, slot_rxP); + if (phy_test && slot_rxP==8){ //nr_schedule_uss_ulsch_phytest(module_idP, frame_rxP, slot_rxP); } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index 4c962cb50f..e8f01b8f71 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -389,8 +389,25 @@ void nr_get_Msg3alloc(NR_ServingCellConfigCommon_t *scc, ra->msg3_first_rb = 0; } -// WIP -// todo: fix + +void nr_schedule_reception_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP){ + gNB_MAC_INST *mac = RC.nrmac[module_idP]; + nfapi_nr_ul_tti_request_t *ul_req = &mac->UL_tti_req[0]; + NR_COMMON_channels_t *cc = &mac->common_channels[CC_id]; + NR_RA_t *ra = &cc->ra[0]; + + if (ra->state == WAIT_Msg3) { + if ((frameP == ra->Msg3_frame) && (slotP == ra->Msg3_slot) ){ + ul_req->SFN = ra->Msg3_frame; + ul_req->Slot = ra->Msg3_slot; + ul_req->pdus_list[ul_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE; + ul_req->pdus_list[ul_req->n_pdus].pdu_size = sizeof(nfapi_nr_pusch_pdu_t); + ul_req->pdus_list[ul_req->n_pdus].pusch_pdu = ra->pusch_pdu; + ul_req->n_pdus+=1; + } + } +} + void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP){ gNB_MAC_INST *mac = RC.nrmac[module_idP]; @@ -398,20 +415,15 @@ void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; NR_RA_t *ra = &cc->ra[0]; NR_UE_list_t *UE_list = &mac->UE_list; - nfapi_nr_ul_tti_request_t *ul_req = &mac->UL_tti_req[0]; - int UE_id = 0; AssertFatal(ra->state != RA_IDLE, "RA is not active for RA %X\n", ra->rnti); LOG_D(MAC, "[gNB %d][RAPROC] Frame %d, Subframe %d : CC_id %d RA is active, Msg3 in (%d,%d)\n", module_idP, frameP, slotP, CC_id, ra->Msg3_frame, ra->Msg3_slot); - ul_req->SFN = ra->Msg3_frame; - ul_req->Slot = ra->Msg3_slot; - ul_req->pdus_list[ul_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE; - ul_req->pdus_list[ul_req->n_pdus].pdu_size = sizeof(nfapi_nr_pusch_pdu_t); - nfapi_nr_pusch_pdu_t *pusch_pdu = &ul_req->pdus_list[ul_req->n_pdus].pusch_pdu; + + nfapi_nr_pusch_pdu_t *pusch_pdu = &ra->pusch_pdu; memset(pusch_pdu, 0, sizeof(nfapi_nr_pusch_pdu_t)); - ul_req->n_pdus+=1; + AssertFatal(UE_list->active[UE_id] >=0,"Cannot find UE_id %d is not active\n", UE_id); @@ -773,7 +785,6 @@ void nr_fill_rar(uint8_t Mod_idP, // UL grant - ra->msg3_mcs = pusch_pdu->mcs_index; ra->msg3_TPC = tpc_command; bwp_size = pusch_pdu->bwp_size; @@ -793,7 +804,7 @@ void nr_fill_rar(uint8_t Mod_idP, f_alloc = (prb_alloc&truncation); } - ul_grant = csi_req | (tpc_command << 1) | (ra->msg3_mcs << 4) | (ra->Msg3_tda_id << 8) | (f_alloc << 12) | (pusch_pdu->frequency_hopping << 26); + ul_grant = csi_req | (tpc_command << 1) | (pusch_pdu->mcs_index << 4) | (ra->Msg3_tda_id << 8) | (f_alloc << 12) | (pusch_pdu->frequency_hopping << 26); rar->UL_GRANT_1 = (uint8_t) (ul_grant >> 24) & 0x07; rar->UL_GRANT_2 = (uint8_t) (ul_grant >> 16) & 0xff; diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index c7921de0ad..48a120abef 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -240,6 +240,8 @@ void nr_generate_Msg2(module_id_t module_idP, frame_t frameP, sub_frame_t slotP); +void nr_schedule_reception_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP); + int find_aggregation_level (NR_SearchSpace_t *ss); void find_monitoring_periodicity_offset_common(NR_SearchSpace_t *ss, diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index b874f490ec..a2cfe04173 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -125,8 +125,6 @@ typedef struct { uint8_t msg3_first_rb; /// Msg3 number of RB uint8_t msg3_nb_rb; - /// Msg3 MCS - uint8_t msg3_mcs; /// Msg3 TPC command uint8_t msg3_TPC; /// Msg3 ULdelay command @@ -135,6 +133,8 @@ typedef struct { uint8_t msg3_cqireq; /// Round of Msg3 HARQ uint8_t msg3_round; + /// Msg3 pusch pdu + nfapi_nr_pusch_pdu_t pusch_pdu; /// TBS used for Msg4 int msg4_TBsize; /// MCS used for Msg4 From 0ecc3149bad58063b5753fffa0058bc459631d5f Mon Sep 17 00:00:00 2001 From: Cedric Roux Date: Thu, 5 Mar 2020 11:16:46 +0100 Subject: [PATCH 075/553] bugfix: ul grant is 27 bits, does not fit into uint16_t --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index e8f01b8f71..0cbb4043f9 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -761,7 +761,7 @@ void nr_fill_rar(uint8_t Mod_idP, NR_MAC_RAR *rar = (NR_MAC_RAR *) (dlsch_buffer + 1); unsigned char csi_req = 0, tpc_command; uint8_t N_UL_Hop, valid_bits; - uint16_t ul_grant, f_alloc, prb_alloc, bwp_size, truncation=0; + uint32_t ul_grant, f_alloc, prb_alloc, bwp_size, truncation=0; tpc_command = 3; // this is 0 dB From e33dea5f38a6f19caee70cf95d57ca4cdc2e1928 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Thu, 5 Mar 2020 12:19:15 +0100 Subject: [PATCH 076/553] fix prb mapping according to bwps --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index 0cbb4043f9..cbdbafb9fd 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -474,8 +474,11 @@ void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t pusch_pdu->ul_dmrs_scrambling_id = *scc->physCellId; //If provided and the PUSCH is not a msg3 PUSCH, otherwise, L2 should set this to physical cell id. pusch_pdu->scid = 0; //DMRS sequence initialization [TS38.211, sec 6.4.1.1.1]. Should match what is sent in DCI 0_1, otherwise set to 0. pusch_pdu->resource_alloc = 1; //type 1 - pusch_pdu->rb_start = ra->msg3_first_rb; - pusch_pdu->rb_size = ra->msg3_nb_rb; + pusch_pdu->rb_start = ra->msg3_first_rb + ibwp_start - abwp_start; // as for 6.3.1.7 in 38.211 + if (ra->msg3_nb_rb > pusch_pdu->bwp_size) + AssertFatal(1==0,"MSG3 allocated number of RBs exceed the BWP size\n"); + else + pusch_pdu->rb_size = ra->msg3_nb_rb; pusch_pdu->vrb_to_prb_mapping = 0; if (ubwp->bwp_Dedicated->pusch_Config->choice.setup->frequencyHopping == NULL) pusch_pdu->frequency_hopping = 0; @@ -761,7 +764,8 @@ void nr_fill_rar(uint8_t Mod_idP, NR_MAC_RAR *rar = (NR_MAC_RAR *) (dlsch_buffer + 1); unsigned char csi_req = 0, tpc_command; uint8_t N_UL_Hop, valid_bits; - uint32_t ul_grant, f_alloc, prb_alloc, bwp_size, truncation=0; + uint32_t ul_grant; + uint16_t f_alloc, prb_alloc, bwp_size, truncation=0; tpc_command = 3; // this is 0 dB @@ -788,7 +792,7 @@ void nr_fill_rar(uint8_t Mod_idP, ra->msg3_TPC = tpc_command; bwp_size = pusch_pdu->bwp_size; - prb_alloc = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size, pusch_pdu->rb_start, bwp_size); + prb_alloc = PRBalloc_to_locationandbandwidth0(ra->msg3_nb_rb, ra->msg3_first_rb, bwp_size); if (bwp_size>180) { AssertFatal(1==0,"Initial UBWP larger than 180 currently not supported"); } From 98714f3138335a410368707551b0682b3f503e05 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 6 Mar 2020 18:05:12 +0100 Subject: [PATCH 077/553] using SCF fapi structure for PUSCH and initialization of pusch dmrs sequences at nr_init --- .../nfapi/public_inc/nfapi_nr_interface_scf.h | 4 +- openair1/PHY/INIT/nr_init.c | 29 ++- .../NR_ESTIMATION/nr_ul_channel_estimation.c | 146 +++++++------- openair1/PHY/NR_ESTIMATION/nr_ul_estimation.h | 14 +- openair1/PHY/NR_REFSIG/nr_dmrs_rx.c | 12 +- openair1/PHY/NR_REFSIG/nr_gold.c | 58 ++---- openair1/PHY/NR_REFSIG/nr_refsig.h | 2 +- .../PHY/NR_TRANSPORT/nr_transport_proto.h | 9 +- openair1/PHY/NR_TRANSPORT/nr_ulsch.c | 16 +- openair1/PHY/NR_TRANSPORT/nr_ulsch.h | 5 +- openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c | 56 +++--- .../PHY/NR_TRANSPORT/nr_ulsch_demodulation.c | 188 ++++++++---------- openair1/PHY/defs_gNB.h | 14 +- openair1/PHY/impl_defs_nr.h | 4 +- openair1/SCHED_NR/phy_procedures_nr_gNB.c | 60 ++---- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 2 - openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 2 +- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 22 -- .../CONF/gnb.band78.tm1.106PRB.usrpn300.conf | 4 +- 19 files changed, 258 insertions(+), 389 deletions(-) diff --git a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h index e396ea68a7..434bc9b7c4 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h @@ -1116,10 +1116,10 @@ typedef struct uint16_t data_scrambling_id; uint8_t nrOfLayers; //DMRS - uint8_t ul_dmrs_symb_pos; + uint16_t ul_dmrs_symb_pos; uint8_t dmrs_config_type; uint16_t ul_dmrs_scrambling_id; - uint8_t scid;// + uint8_t scid; uint8_t num_dmrs_cdm_grps_no_data; uint16_t dmrs_ports;//DMRS ports. [TS38.212 7.3.1.1.2] provides description between DCI 0-1 content and DMRS ports. Bitmap occupying the 11 LSBs with: bit 0: antenna port 1000 bit 11: antenna port 1011 and for each bit 0: DMRS port not used 1: DMRS port used //Pusch Allocation in frequency domain [TS38.214, sec 6.1.2.2] diff --git a/openair1/PHY/INIT/nr_init.c b/openair1/PHY/INIT/nr_init.c index b2262949c1..7c49a6722b 100644 --- a/openair1/PHY/INIT/nr_init.c +++ b/openair1/PHY/INIT/nr_init.c @@ -150,21 +150,30 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, } } - //------------- config PUSCH DMRS parameters(to be updated from RRC)-------------- - gNB->dmrs_UplinkConfig.pusch_dmrs_type = pusch_dmrs_type1; - gNB->dmrs_UplinkConfig.pusch_dmrs_AdditionalPosition = pusch_dmrs_pos0; - gNB->dmrs_UplinkConfig.pusch_maxLength = pusch_len1; - //-------------------------------------------------------------------------------- - nr_init_pdsch_dmrs(gNB, cfg->cell_config.phy_cell_id.value); - // default values until overwritten by RRCConnectionReconfiguration + //PUSCH DMRS init + gNB->nr_gold_pusch_dmrs = (uint32_t ****)malloc16(2*sizeof(uint32_t ***)); + uint32_t ****pusch_dmrs = gNB->nr_gold_pusch_dmrs; - for (i=0;ipusch_config.pusch_TimeDomainResourceAllocation[i] = (PUSCH_TimeDomainResourceAllocation_t *)malloc16(sizeof(PUSCH_TimeDomainResourceAllocation_t)); - gNB->pusch_config.pusch_TimeDomainResourceAllocation[i]->mappingType = typeB; + for(int nscid=0; nscid<2; nscid++) { + pusch_dmrs[nscid] = (uint32_t ***)malloc16(fp->slots_per_frame*sizeof(uint32_t **)); + AssertFatal(pusch_dmrs[nscid]!=NULL, "NR init: pusch_dmrs for nscid %d - malloc failed\n", nscid); + + for (int slot=0; slotslots_per_frame; slot++) { + pusch_dmrs[nscid][slot] = (uint32_t **)malloc16(fp->symbols_per_slot*sizeof(uint32_t *)); + AssertFatal(pusch_dmrs[nscid][slot]!=NULL, "NR init: pusch_dmrs for slot %d - malloc failed\n", slot); + + for (int symb=0; symbsymbols_per_slot; symb++) { + pusch_dmrs[nscid][slot][symb] = (uint32_t *)malloc16(NR_MAX_PUSCH_DMRS_INIT_LENGTH_DWORD*sizeof(uint32_t)); + AssertFatal(pusch_dmrs[nscid][slot][symb]!=NULL, "NR init: pusch_dmrs for slot %d symbol %d - malloc failed\n", slot, symb); + } + } } + uint32_t Nid_pusch[2] = {cfg->cell_config.phy_cell_id.value,cfg->cell_config.phy_cell_id.value}; + nr_gold_pusch(gNB, &Nid_pusch[0]); + // /// Transport init necessary for NR synchro init_nr_transport(gNB); diff --git a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c index ab6ccd929b..64672f2b7a 100644 --- a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c +++ b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c @@ -31,22 +31,19 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, - uint8_t gNB_offset, unsigned char Ns, unsigned short p, unsigned char symbol, unsigned short bwp_start_subcarrier, - unsigned short nb_rb_pusch, - dmrs_UplinkConfig_t *dmrs_UplinkConfig) -{ + nfapi_nr_pusch_pdu_t *pusch_pdu) { + int pilot[3280] __attribute__((aligned(16))); unsigned char aarx; unsigned short k; unsigned int pilot_cnt,re_cnt; int16_t ch[2],ch_r[2],ch_l[2],*pil,*rxF,*ul_ch; int16_t *fl,*fm,*fr,*fml,*fmr,*fmm,*fdcl,*fdcr,*fdclh,*fdcrh; - int ch_offset,symbol_offset, length_dmrs, UE_id = 0; - unsigned short n_idDMRS[2] = {0,1}; //to update from pusch config + int ch_offset,symbol_offset, UE_id = 0; int32_t **ul_ch_estimates_time = gNB->pusch_vars[UE_id]->ul_ch_estimates_time; __m128i *ul_ch_128; @@ -71,6 +68,8 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, k = bwp_start_subcarrier; int re_offset = k; + uint16_t nb_rb_pusch = pusch_pdu->rb_size; + /* #ifdef DEBUG_CH printf("PUSCH Channel Estimation : gNB_offset %d ch_offset %d, symbol_offset %d OFDM size %d, Ncp=%d, l=%d, Ns=%d, k=%d symbol %d\n", gNB_offset,ch_offset,symbol_offset,gNB->frame_parms.ofdm_symbol_size, @@ -117,21 +116,17 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, //------------------generate DMRS------------------// - length_dmrs = gNB->dmrs_UplinkConfig.pusch_maxLength; - - nr_gold_pusch(gNB, symbol, n_idDMRS, length_dmrs); - - nr_pusch_dmrs_rx(gNB, Ns, gNB->nr_gold_pusch[gNB_offset][Ns][0], &pilot[0], 1000, 0, nb_rb_pusch, dmrs_UplinkConfig->pusch_dmrs_type); + nr_pusch_dmrs_rx(gNB, Ns, gNB->nr_gold_pusch_dmrs[pusch_pdu->scid][Ns][symbol], &pilot[0], 1000, 0, nb_rb_pusch, pusch_pdu->dmrs_config_type); //------------------------------------------------// for (aarx=0; aarxframe_parms.nb_antennas_rx; aarx++) { - pil = (int16_t *)&pilot[0]; - rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+k+nushift)]; - ul_ch = (int16_t *)&ul_ch_estimates[aarx][ch_offset]; + pil = (int16_t *)&pilot[0]; + rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+k+nushift)]; + ul_ch = (int16_t *)&ul_ch_estimates[aarx][ch_offset]; - memset(ul_ch,0,4*(gNB->frame_parms.ofdm_symbol_size)); + memset(ul_ch,0,4*(gNB->frame_parms.ofdm_symbol_size)); #ifdef DEBUG_PUSCH printf("ch est pilot addr %p RB_DL %d\n",&pilot[0], gNB->frame_parms.N_RB_UL); @@ -141,8 +136,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, #endif //if ((gNB->frame_parms.N_RB_UL&1)==0) { - - if (dmrs_UplinkConfig->pusch_dmrs_type == pusch_dmrs_type1){ + if (pusch_pdu->dmrs_config_type == pusch_dmrs_type1){ // Treat first 2 pilots specially (left edge) ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15); @@ -237,10 +231,10 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, } // Treat first 2 pilots specially (right edge) - ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15); + ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15); ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); #ifdef DEBUG_PUSCH - printf("pilot %u : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); + printf("pilot %u : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); #endif multadd_real_vector_complex_scalar(fm, ch, @@ -281,70 +275,69 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, 8); - // check if PRB crosses DC and improve estimates around DC - if ((bwp_start_subcarrier < gNB->frame_parms.ofdm_symbol_size) && (bwp_start_subcarrier+nb_rb_pusch*12 >= gNB->frame_parms.ofdm_symbol_size)) { - ul_ch = (int16_t *)&ul_ch_estimates[aarx][ch_offset]; - uint16_t idxDC = 2*(gNB->frame_parms.ofdm_symbol_size - bwp_start_subcarrier); - uint16_t idxPil = idxDC/2; - re_offset = k; - pil = (int16_t *)&pilot[0]; - pil += (idxPil-2); - ul_ch += (idxDC-4); - ul_ch = memset(ul_ch, 0, sizeof(int16_t)*10); - re_offset = (re_offset+idxDC/2-2) % gNB->frame_parms.ofdm_symbol_size; - rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+nushift+re_offset)]; - ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15); - ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); - - // for proper allignment of SIMD vectors - if((gNB->frame_parms.N_RB_UL&1)==0) { + // check if PRB crosses DC and improve estimates around DC + if ((bwp_start_subcarrier < gNB->frame_parms.ofdm_symbol_size) && (bwp_start_subcarrier+nb_rb_pusch*12 >= gNB->frame_parms.ofdm_symbol_size)) { + ul_ch = (int16_t *)&ul_ch_estimates[aarx][ch_offset]; + uint16_t idxDC = 2*(gNB->frame_parms.ofdm_symbol_size - bwp_start_subcarrier); + uint16_t idxPil = idxDC/2; + re_offset = k; + pil = (int16_t *)&pilot[0]; + pil += (idxPil-2); + ul_ch += (idxDC-4); + ul_ch = memset(ul_ch, 0, sizeof(int16_t)*10); + re_offset = (re_offset+idxDC/2-2) % gNB->frame_parms.ofdm_symbol_size; + rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+nushift+re_offset)]; + ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15); + ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); - multadd_real_vector_complex_scalar(fdcl, - ch, - ul_ch-4, - 8); + // for proper allignment of SIMD vectors + if((gNB->frame_parms.N_RB_UL&1)==0) { + + multadd_real_vector_complex_scalar(fdcl, + ch, + ul_ch-4, + 8); - pil += 4; - re_offset = (re_offset+4) % gNB->frame_parms.ofdm_symbol_size; - rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+nushift+re_offset)]; - ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15); - ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); + pil += 4; + re_offset = (re_offset+4) % gNB->frame_parms.ofdm_symbol_size; + rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+nushift+re_offset)]; + ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15); + ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); - multadd_real_vector_complex_scalar(fdcr, - ch, - ul_ch-4, - 8); - } else { + multadd_real_vector_complex_scalar(fdcr, + ch, + ul_ch-4, + 8); + } + else { + multadd_real_vector_complex_scalar(fdclh, + ch, + ul_ch, + 8); - multadd_real_vector_complex_scalar(fdclh, - ch, - ul_ch, - 8); + pil += 4; + re_offset = (re_offset+4) % gNB->frame_parms.ofdm_symbol_size; + rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+nushift+re_offset)]; + ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15); + ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); - pil += 4; - re_offset = (re_offset+4) % gNB->frame_parms.ofdm_symbol_size; - rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+nushift+re_offset)]; - ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15); - ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); - - multadd_real_vector_complex_scalar(fdcrh, - ch, - ul_ch, - 8); + multadd_real_vector_complex_scalar(fdcrh, + ch, + ul_ch, + 8); + } } - - } #ifdef DEBUG_PDSCH - ul_ch = (int16_t *)&ul_ch_estimates[aarx][ch_offset]; - for(uint16_t idxP=0; idxPframe_parms.ofdm_symbol_size) { + switch (gNB->frame_parms.ofdm_symbol_size) { case 128: idft128((int16_t*) &ul_ch_estimates[aarx][symbol_offset], (int16_t*) ul_ch_estimates_time[aarx], diff --git a/openair1/PHY/NR_ESTIMATION/nr_ul_estimation.h b/openair1/PHY/NR_ESTIMATION/nr_ul_estimation.h index cc84f2292c..a7789c9224 100644 --- a/openair1/PHY/NR_ESTIMATION/nr_ul_estimation.h +++ b/openair1/PHY/NR_ESTIMATION/nr_ul_estimation.h @@ -39,14 +39,12 @@ \param nb_rb_pusch, number of allocated RBs for this UE */ - int32_t nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, - uint8_t gNB_offset, - unsigned char Ns, - unsigned short p, - unsigned char symbol, - unsigned short bwp_start_subcarrier, - unsigned short nb_rb_pusch, - dmrs_UplinkConfig_t *dmrs_UplinkConfig); +int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, + unsigned char Ns, + unsigned short p, + unsigned char symbol, + unsigned short bwp_start_subcarrier, + nfapi_nr_pusch_pdu_t *pusch_pdu); int nr_est_timing_advance_pusch(PHY_VARS_gNB* phy_vars_gNB, int UE_id); diff --git a/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c b/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c index f933a8c7ab..f8ccdf0fdf 100644 --- a/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c +++ b/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c @@ -82,13 +82,13 @@ int nr_pusch_dmrs_rx(PHY_VARS_gNB *gNB, mod_table = (w==1) ? nr_rx_mod_table : nr_rx_nmod_table; idx = ((((nr_gold_pusch[(i<<1)>>5])>>((i<<1)&0x1f))&1)<<1) ^ (((nr_gold_pusch[((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1); - ((int16_t*)output)[i<<1] = mod_table[(NR_MOD_TABLE_QPSK_OFFSET + idx)<<1]; - ((int16_t*)output)[(i<<1)+1] = mod_table[((NR_MOD_TABLE_QPSK_OFFSET + idx)<<1) + 1]; + ((int16_t*)output)[i<<1] = mod_table[(NR_MOD_TABLE_QPSK_OFFSET + idx)<<1]; + ((int16_t*)output)[(i<<1)+1] = mod_table[((NR_MOD_TABLE_QPSK_OFFSET + idx)<<1) + 1]; #ifdef DEBUG_PUSCH - printf("nr_pusch_dmrs_rx dmrs config type %d port %d nb_pusch_rb %d\n", dmrs_type, p, nb_pusch_rb); - printf("wf[%d] = %d wt[%d]= %d\n", i&1, wf[p-1000][i&1], lp, wt[p-1000][lp]); - printf("i %d idx %d pusch gold %u b0-b1 %d-%d mod_dmrs %d %d\n", i, idx, nr_gold_pusch[(i<<1)>>5], (((nr_gold_pusch[(i<<1)>>5])>>((i<<1)&0x1f))&1), - (((nr_gold_pusch[((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1), ((int16_t*)output)[i<<1], ((int16_t*)output)[(i<<1)+1]); + printf("nr_pusch_dmrs_rx dmrs config type %d port %d nb_pusch_rb %d\n", dmrs_type, p, nb_pusch_rb); + printf("wf[%d] = %d wt[%d]= %d\n", i&1, wf[p-1000][i&1], lp, wt[p-1000][lp]); + printf("i %d idx %d pusch gold %u b0-b1 %d-%d mod_dmrs %d %d\n", i, idx, nr_gold_pusch[(i<<1)>>5], (((nr_gold_pusch[(i<<1)>>5])>>((i<<1)&0x1f))&1), + (((nr_gold_pusch[((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1), ((int16_t*)output)[i<<1], ((int16_t*)output)[(i<<1)+1]); #endif } } else { diff --git a/openair1/PHY/NR_REFSIG/nr_gold.c b/openair1/PHY/NR_REFSIG/nr_gold.c index 7057adef21..4b007f1292 100644 --- a/openair1/PHY/NR_REFSIG/nr_gold.c +++ b/openair1/PHY/NR_REFSIG/nr_gold.c @@ -88,6 +88,7 @@ void nr_init_pdsch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid) uint16_t N_n_scid[NR_MAX_NB_CODEWORDS]={Nid, Nid}; // Not correct, appropriate scrambling IDs have to be updated to support DCI 1_1 uint8_t n_scid=0; // again works only for 1_0 for (uint8_t slot=0; slotslots_per_frame; slot++) { + for (uint8_t symb=0; symbsymbols_per_slot; symb++) { reset = 1; x2 = ((1<<17) * (fp->symbols_per_slot*slot+symb+1) * ((N_n_scid[n_scid]<<1)+1) +((N_n_scid[n_scid]<<1)+n_scid)); @@ -104,56 +105,27 @@ void nr_init_pdsch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid) } -void nr_gold_pusch(PHY_VARS_gNB* gNB, unsigned short lbar,unsigned short *n_idDMRS, unsigned short length_dmrs) -{ +void nr_gold_pusch(PHY_VARS_gNB* gNB, uint32_t *Nid) { - unsigned char ns,l; - unsigned int n,x1,x2,x2tmp0; - int nscid; + unsigned char ns; + unsigned int n,x1,x2; + int nscid, reset; unsigned int nid; - - /// to be updated from higher layer - //unsigned short lbar = 0; + NR_DL_FRAME_PARMS *fp = &gNB->frame_parms; + unsigned short l; for (nscid=0; nscid<2; nscid++) { - if (n_idDMRS) - nid = n_idDMRS[nscid]; - else - nid = gNB->frame_parms.Nid_cell; - - //printf("gold pdsch nid %d lbar %d\n",nid,lbar); - - for (ns=0; ns<20; ns++) { - - for (l=0; l>1) ^ (x2>>2) ^ (x2>>3))<<31); - - // skip first 50 double words (1600 bits) - for (n=1; n<50; n++) { - x1 = (x1>>1) ^ (x1>>4); - x1 = x1 ^ (x1<<31) ^ (x1<<28); - x2 = (x2>>1) ^ (x2>>2) ^ (x2>>3) ^ (x2>>4); - x2 = x2 ^ (x2<<31) ^ (x2<<30) ^ (x2<<29) ^ (x2<<28); - //printf("x1 : %x, x2 : %x\n",x1,x2); - } + nid = Nid[nscid]; + for (ns=0; nsslots_per_frame; ns++) { + for (l=0; lsymbols_per_slot; l++) { + reset = 1; + x2 = ((1<<17) * (fp->symbols_per_slot*ns+l+1) * ((nid<<1)+1) +((nid<<1)+nscid)); + LOG_D(PHY,"DMRS slot %d, symb %d x2 %x\n",ns,l,x2); for (n=0; n>1) ^ (x1>>4); - x1 = x1 ^ (x1<<31) ^ (x1<<28); - x2 = (x2>>1) ^ (x2>>2) ^ (x2>>3) ^ (x2>>4); - x2 = x2 ^ (x2<<31) ^ (x2<<30) ^ (x2<<29) ^ (x2<<28); - gNB->nr_gold_pusch[nscid][ns][l][n] = x1^x2; - // if ((ns==2)&&(l==0)) - //printf("n=%d : c %x\n",n,x1^x2); + gNB->nr_gold_pusch_dmrs[nscid][ns][l][n] = lte_gold_generic(&x1, &x2, reset); + reset = 0; } - } } } diff --git a/openair1/PHY/NR_REFSIG/nr_refsig.h b/openair1/PHY/NR_REFSIG/nr_refsig.h index 754edfef64..5af0e88099 100644 --- a/openair1/PHY/NR_REFSIG/nr_refsig.h +++ b/openair1/PHY/NR_REFSIG/nr_refsig.h @@ -39,7 +39,7 @@ void nr_init_pbch_dmrs(PHY_VARS_gNB* gNB); void nr_init_pdcch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid); void nr_init_pdsch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid); -void nr_gold_pusch(PHY_VARS_gNB* gNB, unsigned short lbar,unsigned short *n_idDMRS, unsigned short length_dmrs); +void nr_gold_pusch(PHY_VARS_gNB* gNB, uint32_t *Nid); int nr_pusch_dmrs_rx(PHY_VARS_gNB *gNB, unsigned int Ns, diff --git a/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h b/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h index d613dccede..eb1b726df9 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h +++ b/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h @@ -70,15 +70,10 @@ void nr_ulsch_extract_rbs_single(int **rxdataF, int **rxdataF_ext, int **ul_ch_estimates_ext, uint32_t rxdataF_ext_offset, - // unsigned int *rb_alloc, [hna] Resource Allocation Type 1 is assumed only for the moment unsigned char symbol, - unsigned short start_rb, - unsigned short nb_rb_pusch, + nfapi_nr_pusch_pdu_t *pusch_pdu, NR_DL_FRAME_PARMS *frame_parms, - uint8_t dmrs_symbol, - uint16_t number_symbols, - uint8_t mapping_type, - dmrs_UplinkConfig_t *dmrs_UplinkConfig); + uint8_t dmrs_symbol); void nr_ulsch_scale_channel(int32_t **ul_ch_estimates_ext, NR_DL_FRAME_PARMS *frame_parms, diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch.c index 536e4e9e71..6764e6e125 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch.c @@ -76,23 +76,9 @@ void nr_fill_ulsch(PHY_VARS_gNB *gNB, ulsch->harq_processes[harq_pid]->slot=slot; ulsch->harq_processes[harq_pid]->handled= 0; ulsch->harq_processes[harq_pid]->status= NR_ACTIVE; - nfapi_nr_ul_config_ulsch_pdu *rel15_ul = &ulsch->harq_processes[harq_pid]->ulsch_pdu; + memcpy((void*)&ulsch->harq_processes[harq_pid]->ulsch_pdu, (void*)ulsch_pdu, sizeof(nfapi_nr_pusch_pdu_t)); LOG_D(PHY,"Initializing nFAPI for ULSCH, UE %d, harq_pid %d\n",ulsch_id,harq_pid); - - - //FK this is still a bad hack. We need to replace the L1 FAPI structures with the new scf ones as well. - rel15_ul->rnti = ulsch_pdu->rnti; - rel15_ul->ulsch_pdu_rel15.start_rb = ulsch_pdu->rb_start; - rel15_ul->ulsch_pdu_rel15.number_rbs = ulsch_pdu->rb_size; - rel15_ul->ulsch_pdu_rel15.start_symbol = ulsch_pdu->start_symbol_index; - rel15_ul->ulsch_pdu_rel15.number_symbols = ulsch_pdu->nr_of_symbols; - rel15_ul->ulsch_pdu_rel15.length_dmrs = gNB->dmrs_UplinkConfig.pusch_maxLength; - rel15_ul->ulsch_pdu_rel15.Qm = ulsch_pdu->qam_mod_order; - rel15_ul->ulsch_pdu_rel15.mcs = ulsch_pdu->mcs_index; - rel15_ul->ulsch_pdu_rel15.rv = ulsch_pdu->pusch_data.rv_index; - rel15_ul->ulsch_pdu_rel15.n_layers = ulsch_pdu->nrOfLayers; - rel15_ul->ulsch_pdu_rel15.R = ulsch_pdu->target_code_rate; } diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch.h b/openair1/PHY/NR_TRANSPORT/nr_ulsch.h index f8d8f38dd1..a2672aee38 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch.h +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch.h @@ -53,12 +53,11 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, uint8_t UE_id, short *ulsch_llr, NR_DL_FRAME_PARMS *frame_parms, + nfapi_nr_pusch_pdu_t *pusch_pdu, uint32_t frame, - uint16_t nb_symb_sch, - uint16_t nb_re_dmrs, uint8_t nr_tti_rx, uint8_t harq_pid, - uint8_t is_crnti); + uint32_t G); /*! \brief Perform PUSCH unscrambling. TS 38.211 V15.4.0 subclause 6.3.1.1 diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c index ca39b82edf..d9985d8f7f 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c @@ -296,15 +296,13 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, uint8_t UE_id, short *ulsch_llr, NR_DL_FRAME_PARMS *frame_parms, + nfapi_nr_pusch_pdu_t *pusch_pdu, uint32_t frame, - uint16_t nb_symb_sch, - uint16_t nb_re_dmrs, uint8_t nr_tti_rx, uint8_t harq_pid, - uint8_t is_crnti) + uint32_t G) { uint32_t A,E; - uint32_t G; uint32_t ret, offset; int32_t no_iteration_ldpc, length_dec; uint32_t r,r_offset=0,Kr=8424,Kr_bytes,K_bytes_F,err_flag=0; @@ -318,7 +316,6 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, NR_gNB_ULSCH_t *ulsch = phy_vars_gNB->ulsch[UE_id][0]; NR_UL_gNB_HARQ_t *harq_process = ulsch->harq_processes[harq_pid]; - nfapi_nr_ul_config_ulsch_pdu_rel15_t *nfapi_ulsch_pdu_rel15 = &harq_process->ulsch_pdu.ulsch_pdu_rel15; t_nrLDPC_dec_params decParams; t_nrLDPC_dec_params* p_decParams = &decParams; @@ -338,13 +335,11 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, double Coderate = 0.0; // ------------------------------------------------------------------ - uint16_t nb_rb = nfapi_ulsch_pdu_rel15->number_rbs; - uint16_t number_symbols = nfapi_ulsch_pdu_rel15->number_symbols; - uint8_t Qm = nfapi_ulsch_pdu_rel15->Qm; - uint16_t R = nfapi_ulsch_pdu_rel15->R; - uint8_t mcs = nfapi_ulsch_pdu_rel15->mcs; - uint8_t n_layers = nfapi_ulsch_pdu_rel15->n_layers; - uint8_t length_dmrs = nfapi_ulsch_pdu_rel15->length_dmrs; + uint16_t nb_rb = pusch_pdu->rb_size; + uint8_t Qm = pusch_pdu->qam_mod_order; + uint16_t R = pusch_pdu->target_code_rate; + uint8_t mcs = pusch_pdu->mcs_index; + uint8_t n_layers = pusch_pdu->nrOfLayers; // ------------------------------------------------------------------ uint32_t i,j; @@ -364,14 +359,12 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, } // harq_process->trials[nfapi_ulsch_pdu_rel15->round]++; - harq_process->TBS = nr_compute_tbs(Qm, R, nb_rb, number_symbols, nb_re_dmrs*length_dmrs, 0, 0, n_layers); + harq_process->TBS = pusch_pdu->pusch_data.tb_size; A = harq_process->TBS; ret = ulsch->max_ldpc_iterations + 1; - G = nr_get_G(nb_rb, number_symbols, nb_re_dmrs, length_dmrs, Qm, n_layers); - - LOG_D(PHY,"ULSCH Decoding, harq_pid %d TBS %d G %d mcs %d Nl %d nb_symb_sch %d nb_rb %d, nb_re_dmrs %d, Qm %d, n_layers %d\n",harq_pid,A,G, mcs, n_layers, nb_symb_sch,nb_rb, nb_re_dmrs, Qm, n_layers); + LOG_D(PHY,"ULSCH Decoding, harq_pid %d TBS %d G %d mcs %d Nl %d nb_rb %d, Qm %d, n_layers %d\n",harq_pid,A,G, mcs, n_layers, nb_rb, Qm, n_layers); if (harq_process->round == 0) { @@ -461,7 +454,7 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, K_bytes_F = Kr_bytes-(harq_process->F>>3); for (r=0; rC; r++) { - E = nr_get_E(G, harq_process->C, nfapi_ulsch_pdu_rel15->Qm, nfapi_ulsch_pdu_rel15->n_layers, r); + E = nr_get_E(G, harq_process->C, Qm, n_layers, r); #if gNB_TIMING_TRACE start_meas(ulsch_deinterleaving_stats); @@ -474,7 +467,7 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, //////////////////////////// ulsch_llr =====> harq_process->e ////////////////////////////// nr_deinterleaving_ldpc(E, - nfapi_ulsch_pdu_rel15->Qm, + Qm, harq_process->e[r], ulsch_llr+r_offset); @@ -494,10 +487,10 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, harq_pid,r, G, Kr*3, harq_process->TBS, - nfapi_ulsch_pdu_rel15->Qm, - nfapi_ulsch_pdu_rel15->number_rbs, - nfapi_ulsch_pdu_rel15->n_layers, - nfapi_ulsch_pdu_rel15->rv, + Qm, + nb_rb, + n_layers, + pusch_pdu->pusch_data.rv_index, harq_process->round); #endif ////////////////////////////////////////////////////////////////////////////////////////// @@ -509,7 +502,7 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, ///////////////////////// harq_process->e =====> harq_process->d ///////////////////////// - Tbslbrm = nr_compute_tbslbrm(0,nb_rb,nfapi_ulsch_pdu_rel15->n_layers,harq_process->C); + Tbslbrm = nr_compute_tbslbrm(0,nb_rb,n_layers,harq_process->C); if (nr_rate_matching_ldpc_rx(Ilbrm, Tbslbrm, @@ -518,7 +511,7 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, harq_process->d[r], harq_process->e[r], harq_process->C, - nfapi_ulsch_pdu_rel15->rv, + pusch_pdu->pusch_data.rv_index, (harq_process->round==0)?1:0, E, harq_process->F, @@ -654,7 +647,7 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, int32_t tti_rx_prev = nr_tti_rx - 1; if (tti_rx_prev < 0) { frame_rx_prev--; - tti_rx_prev += 10*frame_parms->ttis_per_subframe; + tti_rx_prev += frame_parms->slots_per_frame; } frame_rx_prev = frame_rx_prev%1024; @@ -678,10 +671,8 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, ulsch->harq_mask &= ~(1 << harq_pid); } - if(is_crnti) { - LOG_D(PHY,"[gNB %d] ULSCH: Setting NACK for nr_tti_rx %d (pid %d, pid status %d, round %d/Max %d, TBS %d)\n", - phy_vars_gNB->Mod_id,nr_tti_rx,harq_pid,harq_process->status,harq_process->round,ulsch->Mlimit,harq_process->TBS); - } + // LOG_D(PHY,"[gNB %d] ULSCH: Setting NACK for nr_tti_rx %d (pid %d, pid status %d, round %d/Max %d, TBS %d)\n", + // phy_vars_gNB->Mod_id,nr_tti_rx,harq_pid,harq_process->status,harq_process->round,ulsch->Mlimit,harq_process->TBS); harq_process->handled = 1; ret = ulsch->max_ldpc_iterations + 1; @@ -701,10 +692,9 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, // harq_process->harq_ack.harq_id = harq_pid; // harq_process->harq_ack.send_harq_status = 1; - if(is_crnti) - { - LOG_D(PHY,"[gNB %d] ULSCH: Setting ACK for nr_tti_rx %d (pid %d, round %d, TBS %d)\n",phy_vars_gNB->Mod_id,nr_tti_rx,harq_pid,harq_process->round,harq_process->TBS); - } + + // LOG_D(PHY,"[gNB %d] ULSCH: Setting ACK for nr_tti_rx %d (pid %d, round %d, TBS %d)\n",phy_vars_gNB->Mod_id,nr_tti_rx,harq_pid,harq_process->round,harq_process->TBS); + // Reassembly of Transport block here offset = 0; diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c index f65261bb39..99083f748f 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c @@ -226,22 +226,17 @@ void nr_ulsch_extract_rbs_single(int **rxdataF, int **rxdataF_ext, int **ul_ch_estimates_ext, uint32_t rxdataF_ext_offset, - // unsigned int *rb_alloc, [hna] Resource Allocation Type 1 is assumed only for the moment unsigned char symbol, - unsigned short start_rb, - unsigned short nb_rb_pusch, + nfapi_nr_pusch_pdu_t *pusch_pdu, NR_DL_FRAME_PARMS *frame_parms, - uint8_t dmrs_symbol, - uint16_t number_symbols, - uint8_t mapping_type, - dmrs_UplinkConfig_t *dmrs_UplinkConfig) + uint8_t dmrs_symbol) { unsigned short start_re, re, nb_re_pusch; unsigned char aarx; uint32_t rxF_ext_index = 0; uint32_t ul_ch0_ext_index = 0; uint32_t ul_ch0_index = 0; - uint8_t is_dmrs_symbol_flag, k_prime; + uint8_t k_prime; uint16_t n=0; int16_t *rxF,*rxF_ext; @@ -250,14 +245,13 @@ void nr_ulsch_extract_rbs_single(int **rxdataF, #ifdef DEBUG_RB_EXT printf("--------------------symbol = %d-----------------------\n", symbol); - printf("--------------------ch_ext_index = %d-----------------------\n", symbol*NR_NB_SC_PER_RB * nb_rb_pusch); + printf("--------------------ch_ext_index = %d-----------------------\n", symbol*NR_NB_SC_PER_RB * pusch_pdu->rb_size); #endif - start_re = (frame_parms->first_carrier_offset + (start_rb * NR_NB_SC_PER_RB))%frame_parms->ofdm_symbol_size; + start_re = (frame_parms->first_carrier_offset + (pusch_pdu->rb_start * NR_NB_SC_PER_RB))%frame_parms->ofdm_symbol_size; - nb_re_pusch = NR_NB_SC_PER_RB * nb_rb_pusch; - is_dmrs_symbol_flag = 0; + nb_re_pusch = NR_NB_SC_PER_RB * pusch_pdu->rb_size; for (aarx = 0; aarx < frame_parms->nb_antennas_rx; aarx++) { @@ -273,21 +267,11 @@ void nr_ulsch_extract_rbs_single(int **rxdataF, for (re = 0; re < nb_re_pusch; re++) { - is_dmrs_symbol_flag = is_dmrs_symbol(symbol, - (start_re + re)%frame_parms->ofdm_symbol_size, - start_re, - k_prime, - n, - 0, - number_symbols, - dmrs_UplinkConfig, - mapping_type, - frame_parms->ofdm_symbol_size); #ifdef DEBUG_RB_EXT printf("re = %d, is_dmrs_symbol_flag = %d, symbol = %d\n", re, is_dmrs_symbol_flag, symbol); #endif - if ( is_dmrs_symbol_flag == 0 ) { + if ( dmrs_symbol != symbol ) { rxF_ext[rxF_ext_index] = (rxF[ ((start_re + re)*2) % (frame_parms->ofdm_symbol_size*2)]); rxF_ext[rxF_ext_index + 1] = (rxF[(((start_re + re)*2) + 1) % (frame_parms->ofdm_symbol_size*2)]); @@ -469,18 +453,17 @@ void nr_ulsch_channel_level(int **ul_ch_estimates_ext, } void nr_ulsch_channel_compensation(int **rxdataF_ext, - int **ul_ch_estimates_ext, - int **ul_ch_mag, - int **ul_ch_magb, - int **rxdataF_comp, - int **rho, - NR_DL_FRAME_PARMS *frame_parms, - unsigned char symbol, - uint8_t is_dmrs_symbol, - unsigned char mod_order, - unsigned short nb_rb, - unsigned char output_shift) -{ + int **ul_ch_estimates_ext, + int **ul_ch_mag, + int **ul_ch_magb, + int **rxdataF_comp, + int **rho, + NR_DL_FRAME_PARMS *frame_parms, + unsigned char symbol, + uint8_t is_dmrs_symbol, + unsigned char mod_order, + unsigned short nb_rb, + unsigned char output_shift) { #ifdef DEBUG_CH_COMP int16_t *rxF, *ul_ch; @@ -1001,105 +984,95 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, unsigned char harq_pid) { - uint8_t first_symbol_flag, aarx, aatx, dmrs_symbol_flag; // dmrs_symbol_flag, a flag to indicate DMRS REs in current symbol + uint8_t aarx, aatx, dmrs_symbol_flag; // dmrs_symbol_flag, a flag to indicate DMRS REs in current symbol NR_DL_FRAME_PARMS *frame_parms = &gNB->frame_parms; - nfapi_nr_ul_config_ulsch_pdu_rel15_t *rel15_ul = &gNB->ulsch[UE_id][0]->harq_processes[harq_pid]->ulsch_pdu.ulsch_pdu_rel15; + nfapi_nr_pusch_pdu_t *rel15_ul = &gNB->ulsch[UE_id][0]->harq_processes[harq_pid]->ulsch_pdu; uint32_t nb_re_pusch, bwp_start_subcarrier; - uint8_t mapping_type; int avgs; int avg[4]; + uint8_t nodata_dmrs = 1; // FIXME to be properly configured from fapi dmrs_symbol_flag = 0; - first_symbol_flag = 0; - mapping_type = gNB->pusch_config.pusch_TimeDomainResourceAllocation[0]->mappingType; - if (mapping_type == typeB) { + if(symbol == rel15_ul->start_symbol_index){ + gNB->pusch_vars[UE_id]->rxdataF_ext_offset = 0; + gNB->pusch_vars[UE_id]->dmrs_symbol = 0; + gNB->pusch_vars[UE_id]->cl_done = 0; + } - if(symbol == rel15_ul->start_symbol){ - gNB->pusch_vars[UE_id]->rxdataF_ext_offset = 0; - gNB->pusch_vars[UE_id]->dmrs_symbol = 0; - first_symbol_flag = 1; - } + bwp_start_subcarrier = (rel15_ul->rb_start*NR_NB_SC_PER_RB + frame_parms->first_carrier_offset) % frame_parms->ofdm_symbol_size; - bwp_start_subcarrier = (rel15_ul->start_rb*NR_NB_SC_PER_RB + frame_parms->first_carrier_offset) % frame_parms->ofdm_symbol_size; + dmrs_symbol_flag = ((rel15_ul->ul_dmrs_symb_pos)>>symbol)&0x01; - dmrs_symbol_flag = is_dmrs_symbol(symbol, - 0, - 0, - 0, - 0, - 0, - rel15_ul->number_symbols, - &gNB->dmrs_UplinkConfig, - mapping_type, - frame_parms->ofdm_symbol_size); + if (dmrs_symbol_flag == 1){ + if (((rel15_ul->ul_dmrs_symb_pos)>>((symbol+1)%frame_parms->symbols_per_slot))&0x01) + AssertFatal(1==0,"Double DMRS configuration is not yet supported\n"); - if (dmrs_symbol_flag == 1){ - nb_re_pusch = rel15_ul->number_rbs * ((gNB->dmrs_UplinkConfig.pusch_dmrs_type==pusch_dmrs_type1)?6:8); - gNB->pusch_vars[UE_id]->dmrs_symbol = symbol; - } else { - nb_re_pusch = rel15_ul->number_rbs * NR_NB_SC_PER_RB; - } + gNB->pusch_vars[UE_id]->dmrs_symbol = symbol; + + if (nodata_dmrs) + nb_re_pusch = 0; + else + nb_re_pusch = rel15_ul->rb_size * ((rel15_ul->dmrs_config_type==pusch_dmrs_type1)?6:8); // 0 means type 1 + } else { + nb_re_pusch = rel15_ul->rb_size * NR_NB_SC_PER_RB; + } - //---------------------------------------------------------- - //--------------------- Channel estimation --------------------- - //---------------------------------------------------------- + //---------------------------------------------------------- + //--------------------- Channel estimation --------------------- + //---------------------------------------------------------- - if (dmrs_symbol_flag == 1) - nr_pusch_channel_estimation(gNB, - 0, - nr_tti_rx, - 0, // p - symbol, - bwp_start_subcarrier, - rel15_ul->number_rbs, - &gNB->dmrs_UplinkConfig); + if (dmrs_symbol_flag == 1) + nr_pusch_channel_estimation(gNB, + nr_tti_rx, + 0, // p + symbol, + bwp_start_subcarrier, + rel15_ul); - //---------------------------------------------------------- - //--------------------- RBs extraction --------------------- - //---------------------------------------------------------- + //---------------------------------------------------------- + //--------------------- RBs extraction --------------------- + //---------------------------------------------------------- + + if (nb_re_pusch > 0) { nr_ulsch_extract_rbs_single(gNB->common_vars.rxdataF, gNB->pusch_vars[UE_id]->ul_ch_estimates, gNB->pusch_vars[UE_id]->rxdataF_ext, gNB->pusch_vars[UE_id]->ul_ch_estimates_ext, gNB->pusch_vars[UE_id]->rxdataF_ext_offset, - // rb_alloc, [hna] Resource Allocation Type 1 is assumed only for the moment symbol, - rel15_ul->start_rb, - rel15_ul->number_rbs, + rel15_ul, frame_parms, - gNB->pusch_vars[UE_id]->dmrs_symbol, - rel15_ul->number_symbols, - mapping_type, - &gNB->dmrs_UplinkConfig); + gNB->pusch_vars[UE_id]->dmrs_symbol); nr_ulsch_scale_channel(gNB->pusch_vars[UE_id]->ul_ch_estimates_ext, frame_parms, gNB->ulsch[UE_id], symbol, dmrs_symbol_flag, - rel15_ul->number_rbs, - gNB->dmrs_UplinkConfig.pusch_dmrs_type); + rel15_ul->rb_size, + rel15_ul->dmrs_config_type); - if (first_symbol_flag==1) { + if (gNB->pusch_vars[UE_id]->cl_done==0) { - nr_ulsch_channel_level(gNB->pusch_vars[UE_id]->ul_ch_estimates_ext, + nr_ulsch_channel_level(gNB->pusch_vars[UE_id]->ul_ch_estimates_ext, frame_parms, avg, symbol, nb_re_pusch, - rel15_ul->number_rbs); - avgs = 0; + rel15_ul->rb_size); - for (aatx=0;aatxnb_antennas_tx;aatx++) - for (aarx=0;aarxnb_antennas_rx;aarx++) - avgs = cmax(avgs,avg[(aatx<<1)+aarx]); + avgs = 0; - gNB->pusch_vars[UE_id]->log2_maxh = (log2_approx(avgs)/2)+1; + for (aatx=0;aatxnb_antennas_tx;aatx++) + for (aarx=0;aarxnb_antennas_rx;aarx++) + avgs = cmax(avgs,avg[(aatx<<1)+aarx]); - } + gNB->pusch_vars[UE_id]->log2_maxh = (log2_approx(avgs)/2)+1; + gNB->pusch_vars[UE_id]->cl_done = 1; + } nr_ulsch_channel_compensation(gNB->pusch_vars[UE_id]->rxdataF_ext, gNB->pusch_vars[UE_id]->ul_ch_estimates_ext, @@ -1110,30 +1083,29 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, frame_parms, symbol, dmrs_symbol_flag, - rel15_ul->Qm, - rel15_ul->number_rbs, + rel15_ul->qam_mod_order, + rel15_ul->rb_size, gNB->pusch_vars[UE_id]->log2_maxh); - #ifdef NR_SC_FDMA - nr_idft(&((uint32_t*)gNB->pusch_vars[UE_id]->rxdataF_ext[0])[symbol * rel15_ul->number_rbs * NR_NB_SC_PER_RB], nb_re_pusch); - #endif +#ifdef NR_SC_FDMA + nr_idft(&((uint32_t*)gNB->pusch_vars[UE_id]->rxdataF_ext[0])[symbol * rel15_ul->rb_size * NR_NB_SC_PER_RB], nb_re_pusch); +#endif //---------------------------------------------------------- //-------------------- LLRs computation -------------------- //---------------------------------------------------------- - nr_ulsch_compute_llr(&gNB->pusch_vars[UE_id]->rxdataF_comp[0][symbol * rel15_ul->number_rbs * NR_NB_SC_PER_RB], + nr_ulsch_compute_llr(&gNB->pusch_vars[UE_id]->rxdataF_comp[0][symbol * rel15_ul->rb_size * NR_NB_SC_PER_RB], gNB->pusch_vars[UE_id]->ul_ch_mag0, gNB->pusch_vars[UE_id]->ul_ch_magb0, - &gNB->pusch_vars[UE_id]->llr[gNB->pusch_vars[UE_id]->rxdataF_ext_offset * rel15_ul->Qm], - rel15_ul->number_rbs, + &gNB->pusch_vars[UE_id]->llr[gNB->pusch_vars[UE_id]->rxdataF_ext_offset * rel15_ul->qam_mod_order], + rel15_ul->rb_size, nb_re_pusch, symbol, - rel15_ul->Qm); + rel15_ul->qam_mod_order); - gNB->pusch_vars[UE_id]->rxdataF_ext_offset = gNB->pusch_vars[UE_id]->rxdataF_ext_offset + nb_re_pusch; - } else { - LOG_E(PHY, "PUSCH mapping type A is not supported \n"); } + + gNB->pusch_vars[UE_id]->rxdataF_ext_offset = gNB->pusch_vars[UE_id]->rxdataF_ext_offset + nb_re_pusch; } diff --git a/openair1/PHY/defs_gNB.h b/openair1/PHY/defs_gNB.h index b930031aff..e07fc4e81e 100644 --- a/openair1/PHY/defs_gNB.h +++ b/openair1/PHY/defs_gNB.h @@ -174,7 +174,7 @@ typedef struct { typedef struct { /// Nfapi ULSCH PDU - nfapi_nr_ul_config_ulsch_pdu ulsch_pdu; + nfapi_nr_pusch_pdu_t ulsch_pdu; /// Frame where current HARQ round was sent uint32_t frame; /// Slot where current HARQ round was sent @@ -414,8 +414,10 @@ typedef struct { /// \brief llr values. /// - first index: ? [0..1179743] (hard coded) int16_t *llr; - // DMRS symbol index, to be updated every DMRS symbol within a slot. + /// DMRS symbol index, to be updated every DMRS symbol within a slot. uint8_t dmrs_symbol; + /// flag to verify if channel level computation is done + uint8_t cl_done; } NR_gNB_PUSCH; @@ -676,7 +678,7 @@ typedef struct PHY_VARS_gNB_s { uint32_t ****nr_gold_pdsch_dmrs; /// PUSCH DMRS - uint32_t nr_gold_pusch[2][20][2][NR_MAX_PUSCH_DMRS_INIT_LENGTH_DWORD]; + uint32_t ****nr_gold_pusch_dmrs; /// Indicator set to 0 after first SR uint8_t first_sr[NUMBER_OF_NR_SR_MAX]; @@ -710,12 +712,6 @@ typedef struct PHY_VARS_gNB_s { /// counter to average prach energh over first 100 prach opportunities int prach_energy_counter; - PUSCH_Config_t pusch_config; - - dmrs_UplinkConfig_t dmrs_UplinkConfig; - - dmrs_DownlinkConfig_t dmrs_DownlinkConfig; - /* time_stats_t phy_proc; */ diff --git a/openair1/PHY/impl_defs_nr.h b/openair1/PHY/impl_defs_nr.h index f4559adf6a..b09206739f 100644 --- a/openair1/PHY/impl_defs_nr.h +++ b/openair1/PHY/impl_defs_nr.h @@ -503,8 +503,8 @@ typedef enum { pdsch_dmrs_type2 = 2 } pdsch_dmrs_type_t; typedef enum { - pusch_dmrs_type1 = 1, - pusch_dmrs_type2 = 2 + pusch_dmrs_type1 = 0, + pusch_dmrs_type2 = 1 } pusch_dmrs_type_t; typedef enum { pdsch_dmrs_pos0 = 0, diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index 798de7da76..5069d363bb 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -212,42 +212,28 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB, void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH_id, uint8_t harq_pid) { - NR_DL_FRAME_PARMS *frame_parms = &gNB->frame_parms; - nfapi_nr_ul_config_ulsch_pdu *rel15_ul = &gNB->ulsch[ULSCH_id][0]->harq_processes[harq_pid]->ulsch_pdu; - nfapi_nr_ul_config_ulsch_pdu_rel15_t *nfapi_ulsch_pdu_rel15 = &rel15_ul->ulsch_pdu_rel15; + NR_DL_FRAME_PARMS *frame_parms = &gNB->frame_parms; + nfapi_nr_pusch_pdu_t *pusch_pdu = &gNB->ulsch[ULSCH_id][0]->harq_processes[harq_pid]->ulsch_pdu; uint8_t ret; uint8_t l, number_dmrs_symbols = 0; - uint8_t mapping_type; uint32_t G; - int Nid_cell = 0; // [hna] shouldn't be a local variable (should be signaled) uint16_t start_symbol, number_symbols, nb_re_dmrs; - mapping_type = gNB->pusch_config.pusch_TimeDomainResourceAllocation[0]->mappingType; - - start_symbol = nfapi_ulsch_pdu_rel15->start_symbol; - number_symbols = nfapi_ulsch_pdu_rel15->number_symbols; + start_symbol = pusch_pdu->start_symbol_index; + number_symbols = pusch_pdu->nr_of_symbols; for (l = start_symbol; l < start_symbol + number_symbols; l++) - number_dmrs_symbols += is_dmrs_symbol(l, - 0, - 0, - 0, - 0, - 0, - number_symbols, - &gNB->dmrs_UplinkConfig, - mapping_type, - frame_parms->ofdm_symbol_size); + number_dmrs_symbols += ((pusch_pdu->ul_dmrs_symb_pos)>>l)&0x01;; - nb_re_dmrs = ((gNB->dmrs_UplinkConfig.pusch_dmrs_type == pusch_dmrs_type1)?6:4)*number_dmrs_symbols; + nb_re_dmrs = ((pusch_pdu->dmrs_config_type == pusch_dmrs_type1)?6:4)*number_dmrs_symbols; - G = nr_get_G(nfapi_ulsch_pdu_rel15->number_rbs, + G = nr_get_G(pusch_pdu->rb_size, number_symbols, nb_re_dmrs, - nfapi_ulsch_pdu_rel15->length_dmrs, - nfapi_ulsch_pdu_rel15->Qm, - nfapi_ulsch_pdu_rel15->n_layers); + 1, // FIXME only single dmrs is implemented + pusch_pdu->qam_mod_order, + pusch_pdu->nrOfLayers); //---------------------------------------------------------- @@ -257,23 +243,22 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH nr_ulsch_unscrambling(gNB->pusch_vars[ULSCH_id]->llr, G, 0, - Nid_cell, - rel15_ul->rnti); + pusch_pdu->data_scrambling_id, + pusch_pdu->rnti); //---------------------------------------------------------- //--------------------- ULSCH decoding --------------------- //---------------------------------------------------------- ret = nr_ulsch_decoding(gNB, - ULSCH_id, - gNB->pusch_vars[ULSCH_id]->llr, - frame_parms, - frame_rx, - number_symbols, - nb_re_dmrs, - slot_rx, - harq_pid, - 0); + ULSCH_id, + gNB->pusch_vars[ULSCH_id]->llr, + frame_parms, + pusch_pdu, + frame_rx, + slot_rx, + harq_pid, + G); if (ret > gNB->ulsch[ULSCH_id][0]->max_ldpc_iterations) LOG_I(PHY, "ULSCH %d in error\n",ULSCH_id); @@ -407,9 +392,8 @@ void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) (ulsch_harq->slot == slot_rx) && (ulsch_harq->handled == 0)){ - uint8_t symbol_start = ulsch_harq->ulsch_pdu.ulsch_pdu_rel15.start_symbol; - uint8_t symbol_end = symbol_start + ulsch_harq->ulsch_pdu.ulsch_pdu_rel15.number_symbols; - + uint8_t symbol_start = ulsch_harq->ulsch_pdu.start_symbol_index; + uint8_t symbol_end = symbol_start + ulsch_harq->ulsch_pdu.nr_of_symbols; for(uint8_t symbol = symbol_start; symbol < symbol_end; symbol++) { nr_rx_pusch(gNB, ULSCH_id, frame_rx, slot_rx, symbol, harq_pid); } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index 163c4f2c52..ed8da54110 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -387,8 +387,6 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, if (is_nr_UL_slot(cc->ServingCellConfigCommon,slot_rxP)) { - - schedule_nr_prach(module_idP, (frame_rxP+1)&1023, slot_rxP); nr_schedule_reception_msg3(module_idP, 0, frame_rxP, slot_rxP); diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index cbdbafb9fd..b06dcd0a23 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -469,7 +469,7 @@ void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t pusch_pdu->transform_precoding = 0; pusch_pdu->data_scrambling_id = *scc->physCellId; pusch_pdu->nrOfLayers = 1; - pusch_pdu->ul_dmrs_symb_pos = 1; // ok for now but use fill dmrs mask later + pusch_pdu->ul_dmrs_symb_pos = 1<dmrs_config_type = 0; pusch_pdu->ul_dmrs_scrambling_id = *scc->physCellId; //If provided and the PUSCH is not a msg3 PUSCH, otherwise, L2 should set this to physical cell id. pusch_pdu->scid = 0; //DMRS sequence initialization [TS38.211, sec 6.4.1.1.1]. Should match what is sent in DCI 0_1, otherwise set to 0. diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 0d9bf1880a..c82e6e28da 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -942,28 +942,6 @@ int extract_length(int startSymbolAndLength) { if (tmp > 0 && tmp < (14-tmp2)) return(tmp); else return(15-tmp2); } - -void fill_initialBWPDLtimeDomainAllocaion(nfapi_nr_config_request_t *cfg,int time_domain_assignment,int *k0,int *mappingType,int *start_symbol,int *length) { - AssertFatal(time_domain_assignment < cfg->pdsch_config.num_PDSCHTimeDomainResourceAllocations.value,"DL time_domain_assignment %d >= %d\n", - time_domain_assignment,cfg->pdsch_config.num_PDSCHTimeDomainResourceAllocations.value); - *k0 = cfg->pdsch_config.PDSCHTimeDomainResourceAllocation_k0[time_domain_assignment].value; - *mappingType = cfg->pdsch_config.PDSCHTimeDomainResourceAllocation_mappingType[time_domain_assignment].value; - *start_symbol = extract_startSymbol(cfg->pdsch_config.PDSCHTimeDomainResourceAllocation_startSymbolAndLength[time_domain_assignment].value); - *length = extract_length(cfg->pdsch_config.PDSCHTimeDomainResourceAllocation_startSymbolAndLength[time_domain_assignment].value); - -} - - - -void fill_initialBWPULtimeDomainAllocaion(nfapi_nr_config_request_t *cfg,int time_domain_assignment,int *k2, int *mappingType, int *start_symbol,int *length) { - AssertFatal(time_domain_assignment < cfg->pusch_config.num_PUSCHTimeDomainResourceAllocations.value,"UL time_domain_assignment %d >= %d\n", - time_domain_assignment,cfg->pusch_config.num_PUSCHTimeDomainResourceAllocations.value); - - *k2 = cfg->pusch_config.PUSCHTimeDomainResourceAllocation_k2[time_domain_assignment].value; - *mappingType = cfg->pusch_config.PUSCHTimeDomainResourceAllocation_mappingType[time_domain_assignment].value; - *start_symbol = extract_startSymbol(cfg->pusch_config.PUSCHTimeDomainResourceAllocation_startSymbolAndLength[time_domain_assignment].value); - *length = extract_length(cfg->pusch_config.PUSCHTimeDomainResourceAllocation_startSymbolAndLength[time_domain_assignment].value); -} /* * Dump the UL or DL UE_list into LOG_T(MAC) diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf index 611eaa910c..9199757c22 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf @@ -46,7 +46,7 @@ gNBs = #initialDownlinkBWP #genericParameters # this is RBstart=0,L=50 (275*(L-1))+RBstart - initialDLBWPlocationAndBandwidth = 13475; + initialDLBWPlocationAndBandwidth = 6366; # subcarrierSpacing # 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 initialDLBWPsubcarrierSpacing = 1; @@ -89,7 +89,7 @@ gNBs = pMax = 20; #initialUplinkBWP #genericParameters - initialULBWPlocationAndBandwidth = 13475; + initialULBWPlocationAndBandwidth = 6366; # subcarrierSpacing # 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 initialULBWPsubcarrierSpacing = 1; From 2b944d175aa54f1a91c5cae49560e31365ae2300 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Sat, 7 Mar 2020 15:24:51 +0100 Subject: [PATCH 078/553] commit before merge --- openair1/SIMULATION/NR_PHY/nr_unitary_defs.h | 15 +++++++++++---- openair1/SIMULATION/NR_PHY/ulsim.c | 2 +- openair2/LAYER2/NR_MAC_UE/mac_defs.h | 2 +- openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 4 ++-- 4 files changed, 15 insertions(+), 8 deletions(-) diff --git a/openair1/SIMULATION/NR_PHY/nr_unitary_defs.h b/openair1/SIMULATION/NR_PHY/nr_unitary_defs.h index 1b2a07514a..3726eea757 100644 --- a/openair1/SIMULATION/NR_PHY/nr_unitary_defs.h +++ b/openair1/SIMULATION/NR_PHY/nr_unitary_defs.h @@ -55,10 +55,17 @@ signed char quantize(double D, double x, unsigned char B) { return ((char) qxd); } -int8_t nr_ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, uint8_t eNB_id, uint16_t rnti, sub_frame_t subframe) { - AssertFatal(1==0,"Shouldn't be here ...\n"); - return 0; -} +int8_t +mac_rrc_data_req_ue( + const module_id_t Mod_idP, + const int CC_id, + const frame_t frameP, + const rb_id_t Srb_id, + const uint8_t Nb_tb, + uint8_t *const buffer_pP, + const mac_enb_index_t eNB_indexP, + const uint8_t mbsfn_sync_area + ) { return(0);} int oai_nfapi_rach_ind(nfapi_rach_indication_t *rach_ind) {return(0);} NR_IF_Module_t *NR_IF_Module_init(int Mod_id){return(NULL);} diff --git a/openair1/SIMULATION/NR_PHY/ulsim.c b/openair1/SIMULATION/NR_PHY/ulsim.c index 79e6f940ea..0cdcafcb2f 100644 --- a/openair1/SIMULATION/NR_PHY/ulsim.c +++ b/openair1/SIMULATION/NR_PHY/ulsim.c @@ -52,7 +52,7 @@ #include "openair1/SIMULATION/TOOLS/sim.h" #include "openair1/SIMULATION/RF/rf.h" #include "openair1/SIMULATION/NR_PHY/nr_unitary_defs.h" -#include "openair1/SIMULATION/NR_PHY/nr_dummy_functions.c" +//#include "openair1/SIMULATION/NR_PHY/nr_dummy_functions.c" #include "LAYER2/NR_MAC_UE/mac_proto.h" #include "LAYER2/NR_MAC_gNB/mac_proto.h" diff --git a/openair2/LAYER2/NR_MAC_UE/mac_defs.h b/openair2/LAYER2/NR_MAC_UE/mac_defs.h index 5f70cd86b8..95ee52f6f9 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_defs.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_defs.h @@ -75,7 +75,7 @@ typedef enum { } SFN_C_TYPE; typedef enum { - RA_IDLE = 0, + RA_UE_IDLE = 0, WAIT_RAR = 1, WAIT_CONTENTION_RESOLUTION = 2, RA_SUCCEEDED = 3 diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index a2cfe04173..7647b08939 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -81,12 +81,12 @@ typedef enum { WAIT_Msg3 = 2, Msg4 = 3, WAIT_Msg4_ACK = 4 -} RA_state_t; +} RA_gNB_state_t; /*! \brief gNB template for the Random access information */ typedef struct { /// Flag to indicate this process is active - RA_state_t state; + RA_gNB_state_t state; /// BWP id of RA process int bwp_id; /// CORESET0 configured flag From 631d345df8a9bf0eb6eeba42e86a5dc3a5f01520 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Mon, 9 Mar 2020 10:03:54 +0100 Subject: [PATCH 079/553] fix indentation and removing an if in scheduler --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 94 +++++++++++----------- 1 file changed, 46 insertions(+), 48 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index ed8da54110..ed5ac13770 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -321,67 +321,65 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, // Check if there are downlink symbols in the slot, if (is_nr_DL_slot(cc->ServingCellConfigCommon,slot_txP)) { - memset(RC.nrmac[module_idP]->cce_list[1][0],0,MAX_NUM_CCE*sizeof(int)); - for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { - //mbsfn_status[CC_id] = 0; + memset(RC.nrmac[module_idP]->cce_list[1][0],0,MAX_NUM_CCE*sizeof(int)); + for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { + //mbsfn_status[CC_id] = 0; - // clear vrb_maps - memset(cc[CC_id].vrb_map, 0, 100); - memset(cc[CC_id].vrb_map_UL, 0, 100); + // clear vrb_maps + memset(cc[CC_id].vrb_map, 0, 100); + memset(cc[CC_id].vrb_map_UL, 0, 100); - clear_nr_nfapi_information(RC.nrmac[module_idP], CC_id, frame_txP, slot_txP); - } + clear_nr_nfapi_information(RC.nrmac[module_idP], CC_id, frame_txP, slot_txP); + } - // refresh UE list based on UEs dropped by PHY in previous subframe - /* - for (i = 0; i < MAX_MOBILES_PER_GNB; i++) { - if (UE_list->active[i]) { + // refresh UE list based on UEs dropped by PHY in previous subframe + /* + for (i = 0; i < MAX_MOBILES_PER_GNB; i++) { + if (UE_list->active[i]) { - nfapi_nr_config_request_t *cfg = &RC.nrmac[module_idP]->config[CC_id]; + nfapi_nr_config_request_t *cfg = &RC.nrmac[module_idP]->config[CC_id]; + rnti = 0;//UE_RNTI(module_idP, i); + CC_id = 0;//UE_PCCID(module_idP, i); - rnti = 0;//UE_RNTI(module_idP, i); - CC_id = 0;//UE_PCCID(module_idP, i); - - } //END if (UE_list->active[i]) - } //END for (i = 0; i < MAX_MOBILES_PER_GNB; i++) - */ - PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, module_idP, ENB_FLAG_YES,NOT_A_RNTI, frame_txP, slot_txP,module_idP); + } //END if (UE_list->active[i]) + } //END for (i = 0; i < MAX_MOBILES_PER_GNB; i++) + */ + PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, module_idP, ENB_FLAG_YES,NOT_A_RNTI, frame_txP, slot_txP,module_idP); - // This schedules MIB - if((slot_txP == 0) && (frame_txP & 7) == 0){ - schedule_nr_mib(module_idP, frame_txP, slot_txP); - } + // This schedules MIB + if((slot_txP == 0) && (frame_txP & 7) == 0){ + schedule_nr_mib(module_idP, frame_txP, slot_txP); + } - // TbD once RACH is available, start ta_timer when UE is connected - if (ue_sched_ctl->ta_timer) ue_sched_ctl->ta_timer--; + // TbD once RACH is available, start ta_timer when UE is connected + if (ue_sched_ctl->ta_timer) ue_sched_ctl->ta_timer--; - if (ue_sched_ctl->ta_timer == 0) { - gNB->ta_command = ue_sched_ctl->ta_update; - /* if time is up, then set the timer to not send it for 5 frames - // regardless of the TA value */ - ue_sched_ctl->ta_timer = 100; - /* reset ta_update */ - ue_sched_ctl->ta_update = 31; - /* MAC CE flag indicating TA length */ - gNB->ta_len = 2; - } + if (ue_sched_ctl->ta_timer == 0) { + gNB->ta_command = ue_sched_ctl->ta_update; + /* if time is up, then set the timer to not send it for 5 frames + // regardless of the TA value */ + ue_sched_ctl->ta_timer = 100; + /* reset ta_update */ + ue_sched_ctl->ta_update = 31; + /* MAC CE flag indicating TA length */ + gNB->ta_len = 2; + } - if (is_nr_DL_slot(cc->ServingCellConfigCommon,slot_rxP)) nr_schedule_RA(module_idP, frame_txP, slot_txP); - // Phytest scheduling - if (phy_test && slot_txP==1){ - //nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP,NULL); - // resetting ta flag - gNB->ta_len = 0; - } + // Phytest scheduling + if (phy_test && slot_txP==1){ + //nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP,NULL); + // resetting ta flag + gNB->ta_len = 0; + } - /* - // Allocate CCEs for good after scheduling is done - for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) - allocate_CCEs(module_idP, CC_id, subframeP, 0); - */ + /* + // Allocate CCEs for good after scheduling is done + for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) + allocate_CCEs(module_idP, CC_id, subframeP, 0); + */ } //is_nr_DL_slot From f9ca54e9a125d033e2ed80afc036511ae2417e2f Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Mon, 9 Mar 2020 12:05:45 +0100 Subject: [PATCH 080/553] crc and tbs fixes in ulsch --- openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c | 8 +++-- .../PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c | 8 ++--- .../PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c | 36 ++++++++++++++----- 3 files changed, 37 insertions(+), 15 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c index d9985d8f7f..decec9d111 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c @@ -361,7 +361,7 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, // harq_process->trials[nfapi_ulsch_pdu_rel15->round]++; harq_process->TBS = pusch_pdu->pusch_data.tb_size; - A = harq_process->TBS; + A = (harq_process->TBS)<<3; ret = ulsch->max_ldpc_iterations + 1; LOG_D(PHY,"ULSCH Decoding, harq_pid %d TBS %d G %d mcs %d Nl %d nb_rb %d, Qm %d, n_layers %d\n",harq_pid,A,G, mcs, n_layers, nb_rb, Qm, n_layers); @@ -548,7 +548,11 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, // printf("done\n"); if (harq_process->C == 1) { - crc_type = CRC24_A; + if (A > 3824) + crc_type = CRC24_A; + else + crc_type = CRC16; + length_dec = harq_process->B; } else { diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c index 2f6f593bd6..a4b1816853 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c @@ -1695,10 +1695,10 @@ void nr_dlsch_decoding_process(void *arg) } no_iteration_ldpc = nrLDPC_decoder(p_decParams, - (int8_t*)&pl[0], - llrProcBuf, - p_nrLDPC_procBuf, - p_procTime); + (int8_t*)&pl[0], + llrProcBuf, + p_nrLDPC_procBuf, + p_procTime); // Fixme: correct type is unsigned, but nrLDPC_decoder and all called behind use signed int if (check_crc((uint8_t*)llrProcBuf,length_dec,harq_process->F,crc_type)) { diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c index cc8beb3c3d..c9c86965e0 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c @@ -292,18 +292,36 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch, printf("%02x.",a[i]); printf("\n"); */ - // Add 24-bit crc (polynomial A) to payload - crc = crc24a(harq_process->a,A)>>8; - harq_process->a[A>>3] = ((uint8_t*)&crc)[2]; - harq_process->a[1+(A>>3)] = ((uint8_t*)&crc)[1]; - harq_process->a[2+(A>>3)] = ((uint8_t*)&crc)[0]; - //printf("CRC %x (A %d)\n",crc,A); - //printf("a0 %d a1 %d a2 %d\n", a[A>>3], a[1+(A>>3)], a[2+(A>>3)]); - harq_process->B = A+24; + if (A > 3824) { + // Add 24-bit crc (polynomial A) to payload + crc = crc24a(harq_process->a,A)>>8; + harq_process->a[A>>3] = ((uint8_t*)&crc)[2]; + harq_process->a[1+(A>>3)] = ((uint8_t*)&crc)[1]; + harq_process->a[2+(A>>3)] = ((uint8_t*)&crc)[0]; + //printf("CRC %x (A %d)\n",crc,A); + //printf("a0 %d a1 %d a2 %d\n", a[A>>3], a[1+(A>>3)], a[2+(A>>3)]); - memcpy(harq_process->b,harq_process->a,(A/8)+4); + harq_process->B = A+24; + AssertFatal((A/8)+4 <= MAX_NR_ULSCH_PAYLOAD_BYTES,"A %d is too big (A/8+4 = %d > %d)\n",A,(A/8)+4,MAX_NR_ULSCH_PAYLOAD_BYTES); + + memcpy(harq_process->b,harq_process->a,(A/8)+4); + } + else { + // Add 16-bit crc (polynomial A) to payload + crc = crc16(harq_process->a,A)>>16; + harq_process->a[A>>3] = ((uint8_t*)&crc)[1]; + harq_process->a[1+(A>>3)] = ((uint8_t*)&crc)[0]; + //printf("CRC %x (A %d)\n",crc,A); + //printf("a0 %d a1 %d \n", a[A>>3], a[1+(A>>3)]); + + harq_process->B = A+16; + + AssertFatal((A/8)+3 <= MAX_NR_ULSCH_PAYLOAD_BYTES,"A %d is too big (A/8+3 = %d > %d)\n",A,(A/8)+3,MAX_NR_ULSCH_PAYLOAD_BYTES); + + memcpy(harq_process->b,harq_process->a,(A/8)+3); // using 3 bytes to mimic the case of 24 bit crc + } /////////// /////////////////////////////////////////////////////////////////////////// From 2ada0eddc57fe335d2713249d59686f6aad74ea4 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Mon, 9 Mar 2020 17:35:30 +0100 Subject: [PATCH 081/553] fix for no data in dmrs in ulsch procedures --- openair1/PHY/NR_TRANSPORT/nr_transport_proto.h | 1 - openair1/SCHED_NR/phy_procedures_nr_gNB.c | 9 ++++++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h b/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h index eb1b726df9..075878de38 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h +++ b/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h @@ -62,7 +62,6 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, @param start_rb The starting RB in the RB allocation (used for Resource Allocation Type 1 in NR) @param nb_rb_pusch The number of RBs allocated (used for Resource Allocation Type 1 in NR) @param frame_parms, Pointer to frame descriptor structure - @param is_dmrs_symbol, flag to indicate wether this OFDM symbol contains DMRS symbols or not. */ void nr_ulsch_extract_rbs_single(int **rxdataF, diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index 5069d363bb..0a8a34e0da 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -215,7 +215,7 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH NR_DL_FRAME_PARMS *frame_parms = &gNB->frame_parms; nfapi_nr_pusch_pdu_t *pusch_pdu = &gNB->ulsch[ULSCH_id][0]->harq_processes[harq_pid]->ulsch_pdu; - uint8_t ret; + uint8_t ret, nodata_dmrs = 1; uint8_t l, number_dmrs_symbols = 0; uint32_t G; uint16_t start_symbol, number_symbols, nb_re_dmrs; @@ -226,7 +226,10 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH for (l = start_symbol; l < start_symbol + number_symbols; l++) number_dmrs_symbols += ((pusch_pdu->ul_dmrs_symb_pos)>>l)&0x01;; - nb_re_dmrs = ((pusch_pdu->dmrs_config_type == pusch_dmrs_type1)?6:4)*number_dmrs_symbols; + if (nodata_dmrs) + nb_re_dmrs = 12*number_dmrs_symbols; + else + nb_re_dmrs = ((pusch_pdu->dmrs_config_type == pusch_dmrs_type1)?6:4)*number_dmrs_symbols; G = nr_get_G(pusch_pdu->rb_size, number_symbols, @@ -259,7 +262,7 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH slot_rx, harq_pid, G); - + if (ret > gNB->ulsch[ULSCH_id][0]->max_ldpc_iterations) LOG_I(PHY, "ULSCH %d in error\n",ULSCH_id); else From 07a2a095d3ee1f4d2815444df7a182d45dbb8169 Mon Sep 17 00:00:00 2001 From: matzakos Date: Wed, 11 Mar 2020 10:37:48 +0100 Subject: [PATCH 082/553] ENDC path switch S1-U: Integrated S1AP E-RAB-Modification indication message at eNB, interfacing with RRC and X2AP to get proper configuration of E-RABs to be modified and GTP-U configuration at gNB --- executables/nr-softmodem.c | 19 ++- openair2/COMMON/s1ap_messages_def.h | 1 + openair2/COMMON/s1ap_messages_types.h | 38 +++++- openair2/COMMON/x2ap_messages_types.h | 2 +- openair2/GNB_APP/gnb_app.c | 17 +-- openair2/RRC/LTE/rrc_defs.h | 6 + openair2/RRC/LTE/rrc_eNB.c | 41 ++++++ openair2/RRC/LTE/rrc_eNB_S1AP.c | 74 +++++++++++ openair2/RRC/LTE/rrc_eNB_S1AP.h | 2 + openair2/RRC/NR/nr_rrc_proto.h | 6 +- openair2/RRC/NR/rrc_gNB.c | 12 +- openair2/RRC/NR/rrc_gNB_internode.c | 4 +- openair2/RRC/NR/rrc_gNB_nsa.c | 51 +++++++- openair2/X2AP/x2ap_eNB.c | 4 +- openair2/X2AP/x2ap_eNB_generate_messages.c | 24 ++-- openair2/X2AP/x2ap_eNB_generate_messages.h | 2 +- openair2/X2AP/x2ap_eNB_handler.c | 10 +- openair3/S1AP/s1ap_eNB.c | 11 +- openair3/S1AP/s1ap_eNB_handlers.c | 18 +++ openair3/S1AP/s1ap_eNB_nas_procedures.c | 143 +++++++++++++++++++++ openair3/S1AP/s1ap_eNB_nas_procedures.h | 4 + targets/COMMON/create_nr_tasks.c | 20 ++- 22 files changed, 449 insertions(+), 60 deletions(-) diff --git a/executables/nr-softmodem.c b/executables/nr-softmodem.c index a91e7918a9..abf10ee0fe 100644 --- a/executables/nr-softmodem.c +++ b/executables/nr-softmodem.c @@ -182,6 +182,7 @@ extern void reset_opp_meas(void); extern void print_opp_meas(void); extern void init_eNB_afterRU(void); +extern void *udp_eNB_task(void *args_p); int transmission_mode=1; int emulate_rf = 0; @@ -389,10 +390,10 @@ int create_gNB_tasks(uint32_t gnb_nb) { if (gnb_nb > 0) { /* Last task to create, others task must be ready before its start */ - if (itti_create_task (TASK_GNB_APP, gNB_app_task, NULL) < 0) { + /*if (itti_create_task (TASK_GNB_APP, gNB_app_task, NULL) < 0) { LOG_E(GNB_APP, "Create task for gNB APP failed\n"); return -1; - } + }*/ if(itti_create_task(TASK_SCTP, sctp_eNB_task, NULL) < 0){ LOG_E(SCTP, "Create task for SCTP failed\n"); return -1; @@ -407,10 +408,10 @@ int create_gNB_tasks(uint32_t gnb_nb) { } } - /* + if (EPC_MODE_ENABLED) { if (gnb_nb > 0) { - if (itti_create_task (TASK_SCTP, sctp_eNB_task, NULL) < 0) { + /*if (itti_create_task (TASK_SCTP, sctp_eNB_task, NULL) < 0) { LOG_E(SCTP, "Create task for SCTP failed\n"); return -1; } @@ -418,7 +419,7 @@ int create_gNB_tasks(uint32_t gnb_nb) { if (itti_create_task (TASK_S1AP, s1ap_eNB_task, NULL) < 0) { LOG_E(S1AP, "Create task for S1AP failed\n"); return -1; - } + }*/ if(!emulate_rf){ if (itti_create_task (TASK_UDP, udp_eNB_task, NULL) < 0) { LOG_E(UDP_, "Create task for UDP failed\n"); @@ -430,12 +431,17 @@ int create_gNB_tasks(uint32_t gnb_nb) { LOG_E(GTPU, "Create task for GTPV1U failed\n"); return -1; } + } } - */ + if (gnb_nb > 0) { + if (itti_create_task (TASK_GNB_APP, gNB_app_task, NULL) < 0) { + LOG_E(GNB_APP, "Create task for gNB APP failed\n"); + return -1; + } LOG_I(NR_RRC,"Creating NR RRC gNB Task\n"); if (itti_create_task (TASK_RRC_GNB, rrc_gnb_task, NULL) < 0) { @@ -830,6 +836,7 @@ int main( int argc, char **argv ) } openair0_cfg[0].threequarter_fs = threequarter_fs; + EPC_MODE_ENABLED = !IS_SOFTMODEM_NOS1; #if T_TRACER T_Config_Init(); diff --git a/openair2/COMMON/s1ap_messages_def.h b/openair2/COMMON/s1ap_messages_def.h index 57201721ce..5e5794fc55 100644 --- a/openair2/COMMON/s1ap_messages_def.h +++ b/openair2/COMMON/s1ap_messages_def.h @@ -66,6 +66,7 @@ MESSAGE_DEF(S1AP_E_RAB_MODIFY_RESP , MESSAGE_PRIORITY_MED, s1ap_e_rab_m MESSAGE_DEF(S1AP_E_RAB_RELEASE_RESPONSE , MESSAGE_PRIORITY_MED, s1ap_e_rab_release_resp_t , s1ap_e_rab_release_resp) MESSAGE_DEF(S1AP_PATH_SWITCH_REQ , MESSAGE_PRIORITY_MED, s1ap_path_switch_req_t , s1ap_path_switch_req) MESSAGE_DEF(S1AP_PATH_SWITCH_REQ_ACK , MESSAGE_PRIORITY_MED, s1ap_path_switch_req_ack_t , s1ap_path_switch_req_ack) +MESSAGE_DEF(S1AP_E_RAB_MODIFICATION_IND , MESSAGE_PRIORITY_MED, s1ap_e_rab_modification_ind_t , s1ap_e_rab_modification_ind) /* S1AP -> RRC messages */ MESSAGE_DEF(S1AP_DOWNLINK_NAS , MESSAGE_PRIORITY_MED, s1ap_downlink_nas_t , s1ap_downlink_nas ) diff --git a/openair2/COMMON/s1ap_messages_types.h b/openair2/COMMON/s1ap_messages_types.h index aa718dbcf8..7225ae31b3 100644 --- a/openair2/COMMON/s1ap_messages_types.h +++ b/openair2/COMMON/s1ap_messages_types.h @@ -45,6 +45,7 @@ #define S1AP_E_RAB_MODIFY_RESP(mSGpTR) (mSGpTR)->ittiMsg.s1ap_e_rab_modify_resp #define S1AP_PATH_SWITCH_REQ(mSGpTR) (mSGpTR)->ittiMsg.s1ap_path_switch_req #define S1AP_PATH_SWITCH_REQ_ACK(mSGpTR) (mSGpTR)->ittiMsg.s1ap_path_switch_req_ack +#define S1AP_E_RAB_MODIFICATION_IND(mSGpTR) (mSGpTR)->ittiMsg.s1ap_e_rab_modification_ind #define S1AP_DOWNLINK_NAS(mSGpTR) (mSGpTR)->ittiMsg.s1ap_downlink_nas #define S1AP_INITIAL_CONTEXT_SETUP_REQ(mSGpTR) (mSGpTR)->ittiMsg.s1ap_initial_context_setup_req @@ -281,12 +282,26 @@ typedef struct e_rab_tobe_added_s { uint8_t drb_ID; /* The transport layer address for the IP packets */ - transport_layer_addr_t eNB_addr; + transport_layer_addr_t sgw_addr; /* S-GW Tunnel endpoint identifier */ uint32_t gtp_teid; } e_rab_tobe_added_t; +typedef struct e_rab_admitted_tobe_added_s { + /* Unique e_rab_id for the UE. */ + uint8_t e_rab_id; + + /* Unique drb_ID for the UE. */ + uint8_t drb_ID; + + /* The transport layer address for the IP packets */ + transport_layer_addr_t gnb_addr; + + /* S-GW Tunnel endpoint identifier */ + uint32_t gtp_teid; +} e_rab_admitted_tobe_added_t; + typedef struct e_rab_tobeswitched_s { @@ -646,6 +661,27 @@ typedef struct s1ap_path_switch_req_ack_s { } s1ap_path_switch_req_ack_t; +typedef struct s1ap_e_rab_modification_ind_s { + + unsigned eNB_ue_s1ap_id:24; + + /* MME UE id */ + uint32_t mme_ue_s1ap_id; + + /* Number of e_rab setup-ed in the list */ + uint8_t nb_of_e_rabs_tobemodified; + + uint8_t nb_of_e_rabs_nottobemodified; + + /* list of e_rab setup-ed by RRC layers */ + e_rab_setup_t e_rabs_tobemodified[S1AP_MAX_E_RAB]; + + e_rab_setup_t e_rabs_nottobemodified[S1AP_MAX_E_RAB]; + + uint16_t ue_initial_id; + +} s1ap_e_rab_modification_ind_t; + // S1AP --> RRC messages typedef struct s1ap_ue_release_command_s { diff --git a/openair2/COMMON/x2ap_messages_types.h b/openair2/COMMON/x2ap_messages_types.h index ed3470a7d6..38b3b7d653 100644 --- a/openair2/COMMON/x2ap_messages_types.h +++ b/openair2/COMMON/x2ap_messages_types.h @@ -363,7 +363,7 @@ typedef struct x2ap_ENDC_sgnb_addition_req_ACK_s { uint8_t nb_e_rabs_admitted_tobeadded; /* list of e_rab to be added by RRC layers */ - e_rab_tobe_added_t e_rabs_admitted_tobeadded[S1AP_MAX_E_RAB]; + e_rab_admitted_tobe_added_t e_rabs_admitted_tobeadded[S1AP_MAX_E_RAB]; /* list of e_rab to be setup by RRC layers */ e_rab_t e_rab_param[S1AP_MAX_E_RAB]; diff --git a/openair2/GNB_APP/gnb_app.c b/openair2/GNB_APP/gnb_app.c index f11e302771..821174deda 100644 --- a/openair2/GNB_APP/gnb_app.c +++ b/openair2/GNB_APP/gnb_app.c @@ -71,7 +71,7 @@ static void configure_nr_rrc(uint32_t gnb_id) /*------------------------------------------------------------------------------*/ -/* + static uint32_t gNB_app_register(uint32_t gnb_id_start, uint32_t gnb_id_end)//, const Enb_properties_array_t *enb_properties) { uint32_t gnb_id; @@ -83,18 +83,18 @@ static uint32_t gNB_app_register(uint32_t gnb_id_start, uint32_t gnb_id_end)//, s1ap_register_enb_req_t *s1ap_register_gNB; //Type Temporarily reuse // note: there is an implicit relationship between the data structure and the message name - msg_p = itti_alloc_new_message (TASK_GNB_APP, S1AP_REGISTER_ENB_REQ); //Message Temporarily reuse + /*msg_p = itti_alloc_new_message (TASK_GNB_APP, S1AP_REGISTER_ENB_REQ); //Message Temporarily reuse - RCconfig_NR_S1(msg_p, gnb_id); + RCconfig_NR_S1(msg_p, gnb_id);*/ if (gnb_id == 0) RCconfig_nr_gtpu(); - s1ap_register_gNB = &S1AP_REGISTER_ENB_REQ(msg_p); //Message Temporarily reuse - LOG_I(GNB_APP,"default drx %d\n",s1ap_register_gNB->default_drx); + /*s1ap_register_gNB = &S1AP_REGISTER_ENB_REQ(msg_p); //Message Temporarily reuse + LOG_I(GNB_APP,"default drx %d\n",s1ap_register_gNB->default_drx);*/ LOG_I(GNB_APP,"[gNB %d] gNB_app_register for instance %d\n", gnb_id, GNB_MODULE_ID_TO_INSTANCE(gnb_id)); - itti_send_msg_to_task (TASK_S1AP, GNB_MODULE_ID_TO_INSTANCE(gnb_id), msg_p); + //itti_send_msg_to_task (TASK_S1AP, GNB_MODULE_ID_TO_INSTANCE(gnb_id), msg_p); register_gnb_pending++; } @@ -102,7 +102,7 @@ static uint32_t gNB_app_register(uint32_t gnb_id_start, uint32_t gnb_id_end)//, return register_gnb_pending; } -*/ + /*------------------------------------------------------------------------------*/ static uint32_t gNB_app_register_x2(uint32_t gnb_id_start, uint32_t gnb_id_end) { @@ -132,6 +132,7 @@ void *gNB_app_task(void *args_p) uint32_t gnb_id_start = 0; uint32_t gnb_id_end = gnb_id_start + gnb_nb; uint32_t x2_register_gnb_pending = 0; + uint32_t register_gnb_pending=0; uint32_t gnb_id; MessageDef *msg_p = NULL; const char *msg_name = NULL; @@ -176,7 +177,7 @@ void *gNB_app_task(void *args_p) if (EPC_MODE_ENABLED) { /* Try to register each gNB */ //registered_gnb = 0; - //register_gnb_pending = gNB_app_register (gnb_id_start, gnb_id_end);//, gnb_properties_p); + register_gnb_pending = gNB_app_register (gnb_id_start, gnb_id_end);//, gnb_properties_p); } else { /* Start L2L1 task */ msg_p = itti_alloc_new_message(TASK_GNB_APP, INITIALIZE_MESSAGE); diff --git a/openair2/RRC/LTE/rrc_defs.h b/openair2/RRC/LTE/rrc_defs.h index f050733a13..52b06b9f11 100644 --- a/openair2/RRC/LTE/rrc_defs.h +++ b/openair2/RRC/LTE/rrc_defs.h @@ -382,6 +382,7 @@ typedef enum e_rab_satus_e { E_RAB_STATUS_DONE, // from the eNB perspective E_RAB_STATUS_ESTABLISHED, // get the reconfigurationcomplete form UE E_RAB_STATUS_REESTABLISHED, // after HO + E_RAB_STATUS_TOMODIFY, // ENDC NSA E_RAB_STATUS_FAILED, E_RAB_STATUS_TORELEASE // to release DRB between eNB and UE } e_rab_status_t; @@ -613,6 +614,7 @@ typedef struct eNB_RRC_UE_s { /* Number of e_rab to be modified in the list */ uint8_t nb_of_modify_e_rabs; uint8_t nb_of_failed_e_rabs; + uint8_t nb_of_modify_endc_e_rabs; e_rab_param_t modify_e_rab[NB_RB_MAX];//[S1AP_MAX_E_RAB]; /* list of e_rab to be setup by RRC layers */ e_rab_param_t e_rab[NB_RB_MAX];//[S1AP_MAX_E_RAB]; @@ -627,6 +629,10 @@ typedef struct eNB_RRC_UE_s { uint32_t enb_gtp_teid[S1AP_MAX_E_RAB]; transport_layer_addr_t enb_gtp_addrs[S1AP_MAX_E_RAB]; rb_id_t enb_gtp_ebi[S1AP_MAX_E_RAB]; + // LG: For GTPV1 TUNNELS ENDC + uint32_t gnb_gtp_endc_teid[S1AP_MAX_E_RAB]; + transport_layer_addr_t gnb_gtp_endc_addrs[S1AP_MAX_E_RAB]; + rb_id_t gnb_gtp_endc_ebi[S1AP_MAX_E_RAB]; /* Total number of e_rab already setup in the list */ uint8_t nb_x2u_e_rabs; // LG: For GTPV1 TUNNELS(X2U) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index aafd1cbf6f..b8bbb55a82 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -4372,6 +4372,16 @@ rrc_eNB_process_MeasurementReport( msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ); X2AP_ENDC_SGNB_ADDITION_REQ(msg).rnti = ctxt_pP->rnti; + //For the moment we have a single E-RAB which will be the one to be added to the gNB + //Not sure how to select bearers to be added if there are multiple. + X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded = 1; + for (int e_rab=0; i< X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded; e_rab++){ + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].e_rab_id = ue_context_pP->ue_context.e_rab[e_rab].param.e_rab_id; + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].gtp_teid = ue_context_pP->ue_context.e_rab[e_rab].param.gtp_teid; + memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr, + &ue_context_pP->ue_context.e_rab[e_rab].param.sgw_addr, + sizeof(transport_layer_addr_t)); + } LOG_I(RRC, "[eNB %d] frame %d subframe %d: UE rnti %x switching to NSA mode\n", ctxt_pP->module_id, ctxt_pP->frame, ctxt_pP->subframe, ctxt_pP->rnti); @@ -7493,6 +7503,16 @@ rrc_eNB_decode_dcch( } ue_context_p->ue_context.reestablishment_xid = -1; + + //Looking for a condition to trigger S1AP E-RAB-Modification-indication, based on the reception of RRCConnectionReconfigurationComplete + //including NR specific elements. Not sure if this is the correct one and the correct placement + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension-> + scg_ConfigResponseNR_r15->buf!=NULL){ + /*Trigger E-RAB Modification Indication */ + rrc_eNB_send_E_RAB_Modification_Indication(ctxt_pP, ue_context_p); + } + } else { dedicated_DRB = 1; ue_context_p->ue_context.Status = RRC_RECONFIGURED; @@ -8527,6 +8547,27 @@ void rrc_eNB_process_AdditionResponseInformation(const module_id_t enb_mod_idP, ue_context = (rrc_eNB_ue_context_t *) get_first_ue_context(RC.rrc[enb_mod_idP]); + ue_context->ue_context.nb_of_modify_endc_e_rabs = m->nb_e_rabs_admitted_tobeadded; + + int j=0; + while(j < m->nb_e_rabs_admitted_tobeadded){ + for (int e_rab_idx=0; e_rab_idxue_context.setup_e_rabs; e_rab_idx++){ + //Update ue_context information with gNB's address and new GTP tunnel ID + if( ue_context->ue_context.e_rab[e_rab_idx].param.e_rab_id == m->e_rabs_admitted_tobeadded[j].e_rab_id){ + memcpy(ue_context->ue_context.gnb_gtp_endc_addrs[e_rab_idx].buffer, + m->e_rabs_admitted_tobeadded[j].gnb_addr.buffer, + m->e_rabs_admitted_tobeadded[j].gnb_addr.length); + ue_context->ue_context.gnb_gtp_endc_addrs[e_rab_idx].length = m->e_rabs_admitted_tobeadded[j].gnb_addr.length; + ue_context->ue_context.gnb_gtp_endc_teid[e_rab_idx] = m->e_rabs_admitted_tobeadded[j].gtp_teid; + ue_context->ue_context.e_rab[e_rab_idx].status = E_RAB_STATUS_TOMODIFY; + break; + } + } + j++; + } + + + PROTOCOL_CTXT_SET_BY_INSTANCE(&ctxt, 0, ENB_FLAG_YES, diff --git a/openair2/RRC/LTE/rrc_eNB_S1AP.c b/openair2/RRC/LTE/rrc_eNB_S1AP.c index 11c6d27f5f..d2e3d4999f 100644 --- a/openair2/RRC/LTE/rrc_eNB_S1AP.c +++ b/openair2/RRC/LTE/rrc_eNB_S1AP.c @@ -2283,3 +2283,77 @@ int s1ap_ue_context_release(instance_t instance, const uint32_t eNB_ue_s1ap_id) }*/ return 0; } + + +int rrc_eNB_send_E_RAB_Modification_Indication(const protocol_ctxt_t *const ctxt_pP, + rrc_eNB_ue_context_t *const ue_context_pP) { + MessageDef *msg_p = NULL; + int e_rab = 0; + int e_rab_modify_index = 0; + int e_rab_notmodify_index = 0; + rrc_ue_s1ap_ids_t *rrc_ue_s1ap_ids_p = NULL; + hashtable_rc_t h_rc; + + uint8_t inde_list[ue_context_pP->ue_context.nb_of_e_rabs]; + memset(inde_list, 0, ue_context_pP->ue_context.nb_of_e_rabs*sizeof(uint8_t)); + + msg_p = itti_alloc_new_message (TASK_RRC_ENB, S1AP_E_RAB_MODIFICATION_IND); + + + S1AP_E_RAB_MODIFICATION_IND (msg_p).eNB_ue_s1ap_id = ue_context_pP->ue_context.eNB_ue_s1ap_id; + S1AP_E_RAB_MODIFICATION_IND (msg_p).mme_ue_s1ap_id = ue_context_pP->ue_context.mme_ue_s1ap_id; + + LOG_I (RRC,"E-RAB modification indication: nb nb_of_e_rabs %u status %u\n", + ue_context_pP->ue_context.nb_of_e_rabs, + ue_context_pP->ue_context.e_rab[e_rab].status); + + if (ue_context_pP->ue_context.nb_of_modify_endc_e_rabs > 0){ + S1AP_E_RAB_MODIFICATION_IND (msg_p).nb_of_e_rabs_tobemodified = ue_context_pP->ue_context.nb_of_modify_endc_e_rabs; + for (e_rab = 0; e_rab < ue_context_pP->ue_context.setup_e_rabs ; e_rab++) { + //Add E-RAB in the list of E-RABs to be modified + if (ue_context_pP->ue_context.e_rab[e_rab].status == E_RAB_STATUS_TOMODIFY) { + S1AP_E_RAB_MODIFICATION_IND (msg_p).e_rabs_tobemodified[e_rab_modify_index].e_rab_id = ue_context_pP->ue_context.e_rab[e_rab].param.e_rab_id; + memcpy(S1AP_E_RAB_MODIFICATION_IND (msg_p).e_rabs_tobemodified[e_rab_modify_index].eNB_addr.buffer, + ue_context_pP->ue_context.gnb_gtp_endc_addrs[e_rab].buffer, + ue_context_pP->ue_context.gnb_gtp_endc_addrs[e_rab].length); + S1AP_E_RAB_MODIFICATION_IND (msg_p).e_rabs_tobemodified[e_rab_modify_index].eNB_addr.length = ue_context_pP->ue_context.gnb_gtp_endc_addrs[e_rab].length; + S1AP_E_RAB_MODIFICATION_IND (msg_p).e_rabs_tobemodified[e_rab_modify_index].gtp_teid = ue_context_pP->ue_context.gnb_gtp_endc_teid[e_rab]; + e_rab_modify_index++; + } + //Add E-RAB in the list of E-RABs NOT to be modified + else{ + S1AP_E_RAB_MODIFICATION_IND (msg_p).e_rabs_nottobemodified[e_rab_notmodify_index].e_rab_id = ue_context_pP->ue_context.e_rab[e_rab].param.e_rab_id; + memcpy(S1AP_E_RAB_MODIFICATION_IND (msg_p).e_rabs_nottobemodified[e_rab_notmodify_index].eNB_addr.buffer, + ue_context_pP->ue_context.gnb_gtp_endc_addrs[e_rab].buffer, + ue_context_pP->ue_context.gnb_gtp_endc_addrs[e_rab].length); + S1AP_E_RAB_MODIFICATION_IND (msg_p).e_rabs_nottobemodified[e_rab_notmodify_index].eNB_addr.length = ue_context_pP->ue_context.gnb_gtp_endc_addrs[e_rab].length; + S1AP_E_RAB_MODIFICATION_IND (msg_p).e_rabs_nottobemodified[e_rab_notmodify_index].gtp_teid = ue_context_pP->ue_context.gnb_gtp_endc_teid[e_rab]; + e_rab_notmodify_index++; + } + } + S1AP_E_RAB_MODIFICATION_IND (msg_p).nb_of_e_rabs_nottobemodified = e_rab_notmodify_index; + } + + if (e_rab_modify_index > 0) { + LOG_I(RRC,"S1AP_E_RAB_MODIFICATION_IND: sending the message: nb_of_erabstobemodified %d, total e_rabs %d, index %d\n", + S1AP_E_RAB_MODIFICATION_IND (msg_p).nb_of_e_rabs_tobemodified, ue_context_pP->ue_context.setup_e_rabs, e_rab); + MSC_LOG_TX_MESSAGE( + MSC_RRC_ENB, + MSC_S1AP_ENB, + (const char *)&S1AP_E_RAB_MODIFICATION_IND (msg_p), + sizeof(s1ap_e_rab_modification_ind_t), + MSC_AS_TIME_FMT" E RAB MODIFICATION IND UE %X eNB_ue_s1ap_id %u e_rabs:%u succ", + MSC_AS_TIME_ARGS(ctxt_pP), + ue_context_pP->ue_id_rnti, + S1AP_E_RAB_MODIFICATION_IND (msg_p).eNB_ue_s1ap_id, + e_rab_modify_index); + itti_send_msg_to_task (TASK_S1AP, ctxt_pP->instance, msg_p); + } else { + itti_free(ITTI_MSG_ORIGIN_ID(msg_p), msg_p); + } + + return 0; +} + + + diff --git a/openair2/RRC/LTE/rrc_eNB_S1AP.h b/openair2/RRC/LTE/rrc_eNB_S1AP.h index e5ff9c27d6..a55d17bfd1 100644 --- a/openair2/RRC/LTE/rrc_eNB_S1AP.h +++ b/openair2/RRC/LTE/rrc_eNB_S1AP.h @@ -285,4 +285,6 @@ int rrc_eNB_send_X2AP_UE_CONTEXT_RELEASE(const protocol_ctxt_t* const ctxt_pP, r int s1ap_ue_context_release(instance_t instance, const uint32_t eNB_ue_s1ap_id); +int rrc_eNB_send_E_RAB_Modification_Indication(const protocol_ctxt_t *const ctxt_pP, rrc_eNB_ue_context_t *const ue_context_pP); + #endif /* RRC_ENB_S1AP_H_ */ diff --git a/openair2/RRC/NR/nr_rrc_proto.h b/openair2/RRC/NR/nr_rrc_proto.h index 1e4b1be054..eb04b0240f 100644 --- a/openair2/RRC/NR/nr_rrc_proto.h +++ b/openair2/RRC/NR/nr_rrc_proto.h @@ -65,9 +65,9 @@ void rrc_gNB_generate_SgNBAdditionRequestAcknowledge( struct rrc_gNB_ue_context_s *rrc_gNB_allocate_new_UE_context(gNB_RRC_INST *rrc_instance_pP); -void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc,LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList); +void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc,LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList, x2ap_ENDC_sgnb_addition_req_t *m); -void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p); +void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p, x2ap_ENDC_sgnb_addition_req_t *m); void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellconfigcommon, NR_CellGroupConfig_t *secondaryCellGroup, @@ -89,7 +89,7 @@ int generate_CG_Config(gNB_RRC_INST *rrc, NR_RRCReconfiguration_t *reconfig, NR_RadioBearerConfig_t *rbconfig); -int parse_CG_ConfigInfo(gNB_RRC_INST *rrc, NR_CG_ConfigInfo_t *CG_ConfigInfo); +int parse_CG_ConfigInfo(gNB_RRC_INST *rrc, NR_CG_ConfigInfo_t *CG_ConfigInfo, x2ap_ENDC_sgnb_addition_req_t *m); diff --git a/openair2/RRC/NR/rrc_gNB.c b/openair2/RRC/NR/rrc_gNB.c index 3abb7e191e..4f1f9287bc 100644 --- a/openair2/RRC/NR/rrc_gNB.c +++ b/openair2/RRC/NR/rrc_gNB.c @@ -245,13 +245,13 @@ static void init_NR_SI(gNB_RRC_INST *rrc) { OCTET_STRING_fromBuf(cg_ConfigInfo->ue_CapabilityInfo, (const char *)buffer, (enc_rval.encoded+7)>>3); - parse_CG_ConfigInfo(rrc,CG_ConfigInfo); + parse_CG_ConfigInfo(rrc,CG_ConfigInfo,NULL); } else { struct rrc_gNB_ue_context_s *ue_context_p = rrc_gNB_allocate_new_UE_context(rrc); LOG_I(NR_RRC,"Adding new user (%p)\n",ue_context_p); - rrc_add_nsa_user(rrc,ue_context_p); + rrc_add_nsa_user(rrc,ue_context_p,NULL); } } } @@ -311,12 +311,6 @@ void rrc_gNB_process_AdditionRequestInformation(const module_id_t gnb_mod_idP, x (uint8_t *)m->rrc_buffer, (int) m->rrc_buffer_size);//m->rrc_buffer_size); -/* asn_dec_rval_t dec_rval = uper_decode( NULL, - &asn_DEF_LTE_UL_DCCH_Message, - (void **)<E_UL_DCCH_Message, - (uint8_t *)m->rrc_buffer, - (int) m->rrc_buffer_size, 0, 0);//m->rrc_buffer_size); -*/ gNB_RRC_INST *rrc=RC.nrrrc[gnb_mod_idP]; if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { @@ -342,7 +336,7 @@ void rrc_gNB_process_AdditionRequestInformation(const module_id_t gnb_mod_idP, x OCTET_STRING_fromBuf(cg_ConfigInfo->ue_CapabilityInfo, (const char *)m->rrc_buffer, (enc_rval.encoded+7)>>3); - parse_CG_ConfigInfo(rrc,CG_ConfigInfo); + parse_CG_ConfigInfo(rrc,CG_ConfigInfo,m); } diff --git a/openair2/RRC/NR/rrc_gNB_internode.c b/openair2/RRC/NR/rrc_gNB_internode.c index 581015db56..916f4d63da 100644 --- a/openair2/RRC/NR/rrc_gNB_internode.c +++ b/openair2/RRC/NR/rrc_gNB_internode.c @@ -38,7 +38,7 @@ #include "LTE_UE-CapabilityRAT-ContainerList.h" #include "NR_CG-Config.h" -int parse_CG_ConfigInfo(gNB_RRC_INST *rrc, NR_CG_ConfigInfo_t *CG_ConfigInfo) { +int parse_CG_ConfigInfo(gNB_RRC_INST *rrc, NR_CG_ConfigInfo_t *CG_ConfigInfo, x2ap_ENDC_sgnb_addition_req_t *m) { if (CG_ConfigInfo->criticalExtensions.present == NR_CG_ConfigInfo__criticalExtensions_PR_c1) { if (CG_ConfigInfo->criticalExtensions.choice.c1) { @@ -56,7 +56,7 @@ int parse_CG_ConfigInfo(gNB_RRC_INST *rrc, NR_CG_ConfigInfo_t *CG_ConfigInfo) { AssertFatal(1==0,"[InterNode] Failed to decode NR_UE_CapabilityRAT_ContainerList (%zu bits), size of OCTET_STRING %lu\n", dec_rval.consumed, cg_ConfigInfo->ue_CapabilityInfo->size); } - rrc_parse_ue_capabilities(rrc,UE_CapabilityRAT_ContainerList); + rrc_parse_ue_capabilities(rrc,UE_CapabilityRAT_ContainerList, m); } if (cg_ConfigInfo->candidateCellInfoListMN) AssertFatal(1==0,"Can't handle candidateCellInfoListMN yet\n"); } diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c index 18fc3d7e7c..d70bbed189 100644 --- a/openair2/RRC/NR/rrc_gNB_nsa.c +++ b/openair2/RRC/NR/rrc_gNB_nsa.c @@ -37,8 +37,9 @@ #include "LTE_UE-CapabilityRAT-ContainerList.h" #include "NR_CG-Config.h" #include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h" +#include "openair2/RRC/LTE/rrc_eNB_GTPV1U.h" -void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc,LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList) { +void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList, x2ap_ENDC_sgnb_addition_req_t *m) { struct rrc_gNB_ue_context_s *ue_context_p = NULL; OCTET_STRING_t *ueCapabilityRAT_Container_nr; @@ -94,10 +95,10 @@ void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc,LTE_UE_CapabilityRAT_ContainerL xer_fprint(stdout, &asn_DEF_NR_UE_MRDC_Capability, ue_context_p->ue_context.UE_Capability_MRDC); } - rrc_add_nsa_user(rrc,ue_context_p); + rrc_add_nsa_user(rrc,ue_context_p, m); } -void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p) { +void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p, x2ap_ENDC_sgnb_addition_req_t *m) { // generate nr-Config-r15 containers for LTE RRC : inside message for X2 EN-DC (CG-Config Message from 38.331) @@ -105,6 +106,11 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_ MessageDef *msg; msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ_ACK); + gtpv1u_enb_create_tunnel_req_t create_tunnel_req; + gtpv1u_enb_create_tunnel_resp_t create_tunnel_resp; + uint8_t inde_list[m->nb_e_rabs_tobeadded]; + memset(inde_list, 0, m->nb_e_rabs_tobeadded*sizeof(uint8_t)); + protocol_ctxt_t *ctxt = NULL; // NR RRCReconfiguration @@ -133,6 +139,45 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_ //int CG_Config_size = generate_CG_Config(rrc,CG_Config,ue_context_p->ue_context.reconfig,ue_context_p->ue_context.rb_config); generate_CG_Config(rrc,CG_Config,ue_context_p->ue_context.reconfig,ue_context_p->ue_context.rb_config); + if(m!=NULL){ + if (m->nb_e_rabs_tobeadded>0){ + for (int i=0; inb_e_rabs_tobeadded; i++){ + // Add the new E-RABs at the corresponding rrc ue context of the gNB + ue_context_p->ue_context.e_rab[i].param.e_rab_id = m->e_rabs_tobeadded[i].e_rab_id; + ue_context_p->ue_context.e_rab[i].param.gtp_teid = m->e_rabs_tobeadded[i].gtp_teid; + memcpy(&ue_context_p->ue_context.e_rab[i].param.sgw_addr, &m->e_rabs_tobeadded[i].sgw_addr, sizeof(transport_layer_addr_t)); + ue_context_p->ue_context.nb_of_e_rabs++; + //Fill the required E-RAB specific information for the creation of the S1-U tunnel between the gNB and the SGW + create_tunnel_req.eps_bearer_id[i] = ue_context_p->ue_context.e_rab[i].param.e_rab_id; + create_tunnel_req.sgw_S1u_teid[i] = ue_context_p->ue_context.e_rab[i].param.gtp_teid; + memcpy(&create_tunnel_req.sgw_addr[i], &ue_context_p->ue_context.e_rab[i].param.sgw_addr, sizeof(transport_layer_addr_t)); + inde_list[i] = i; + } + //PM: Is this where we should extract the rnti from? + create_tunnel_req.rnti = ue_context_p->ue_id_rnti; + create_tunnel_req.num_tunnels = m->nb_e_rabs_tobeadded; + PROTOCOL_CTXT_SET_BY_MODULE_ID(ctxt, rrc->module_id, GNB_FLAG_YES, NOT_A_RNTI, 0, 0,rrc->module_id); + gtpv1u_create_s1u_tunnel( + ctxt->instance, + &create_tunnel_req, + &create_tunnel_resp); + rrc_eNB_process_GTPV1U_CREATE_TUNNEL_RESP( + ctxt, + &create_tunnel_resp, + &inde_list[0]); + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).nb_e_rabs_admitted_tobeadded = m->nb_e_rabs_tobeadded; + + for(int i=0; iue_context.nb_of_e_rabs; i++){ + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].e_rab_id = ue_context_p->ue_context.e_rab[i].param.e_rab_id; + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gtp_teid = create_tunnel_resp.enb_S1u_teid[i]; + memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr, &create_tunnel_resp.enb_addr, sizeof(transport_layer_addr_t)); + } + } + else + LOG_W(RRC, "No E-RAB to be added received from SgNB Addition Request message \n"); + } + + //X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).rrc_buffer_size = CG_Config_size; //Need to verify correct value for the buffer_size // Send to X2 entity to transport to MeNB asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CG_Config, diff --git a/openair2/X2AP/x2ap_eNB.c b/openair2/X2AP/x2ap_eNB.c index b297c96e56..debe5e0712 100644 --- a/openair2/X2AP/x2ap_eNB.c +++ b/openair2/X2AP/x2ap_eNB.c @@ -359,7 +359,7 @@ void x2ap_eNB_handle_sctp_init_msg_multi_cnf( * Failure means multi_sd < 0. */ if (instance->multi_sd < 0) { - X2AP_ERROR("Error: be sure to properly configure X2 in your configuration file.\n"); + X2AP_ERROR("Error: be sure to properly configure X22 in your configuration file.\n"); DevAssert(instance->multi_sd >= 0); } @@ -474,7 +474,7 @@ void x2ap_eNB_handle_sgNB_add_req(instance_t instance, x2ap_set_ids(id_manager, ue_id, x2ap_ENDC_sgnb_addition_req->rnti, ue_id, -1); x2ap_id_set_state(id_manager, ue_id, X2ID_STATE_NSA_PREPARE); - x2ap_eNB_generate_ENDC_x2_SgNB_addition_request(instance_p, x2ap_eNB_data, ue_id); + x2ap_eNB_generate_ENDC_x2_SgNB_addition_request(instance_p, x2ap_ENDC_sgnb_addition_req, x2ap_eNB_data, ue_id); } static diff --git a/openair2/X2AP/x2ap_eNB_generate_messages.c b/openair2/X2AP/x2ap_eNB_generate_messages.c index 47a3475063..c5cc84c21c 100644 --- a/openair2/X2AP/x2ap_eNB_generate_messages.c +++ b/openair2/X2AP/x2ap_eNB_generate_messages.c @@ -1496,7 +1496,7 @@ int x2ap_eNB_generate_ENDC_x2_setup_response( } int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request( - x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p, int ue_id) + x2ap_eNB_instance_t *instance_p, x2ap_ENDC_sgnb_addition_req_t *x2ap_ENDC_sgnb_addition_req, x2ap_eNB_data_t *x2ap_eNB_data_p, int ue_id) { X2AP_X2AP_PDU_t pdu; X2AP_SgNBAdditionRequest_t *out; @@ -1527,9 +1527,9 @@ int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request( priority_level_t priority_level = PRIORITY_LEVEL_NO_PRIORITY; e_rab_tobe_added_t e_MCG_rabs_tobeadded; e_MCG_rabs_tobeadded.gtp_teid = 0; - e_MCG_rabs_tobeadded.eNB_addr.length = 24; + e_MCG_rabs_tobeadded.sgw_addr.length = 24; uint8_t buf[20] = { 0 }; - memcpy(e_MCG_rabs_tobeadded.eNB_addr.buffer, buf, 20*sizeof(uint8_t)); + memcpy(e_MCG_rabs_tobeadded.sgw_addr.buffer, buf, 20*sizeof(uint8_t)); FILE *fd; fd = fopen("../../../executables/uecap.raw","r"); @@ -1614,8 +1614,8 @@ int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request( e_RABS_ToBeAdded_SgNBAddReq_ItemIEs->value.present = X2AP_E_RABs_ToBeAdded_SgNBAddReq_ItemIEs__value_PR_E_RABs_ToBeAdded_SgNBAddReq_Item; e_RABS_ToBeAdded_SgNBAddReq_Item = &e_RABS_ToBeAdded_SgNBAddReq_ItemIEs->value.choice.E_RABs_ToBeAdded_SgNBAddReq_Item; { - e_RABS_ToBeAdded_SgNBAddReq_Item->drb_ID = drb_ID; - e_RABS_ToBeAdded_SgNBAddReq_Item->e_RAB_ID = e_RAB_ID; + e_RABS_ToBeAdded_SgNBAddReq_Item->drb_ID = x2ap_ENDC_sgnb_addition_req->e_rabs_tobeadded[i].drb_ID; + e_RABS_ToBeAdded_SgNBAddReq_Item->e_RAB_ID = x2ap_ENDC_sgnb_addition_req->e_rabs_tobeadded[i].e_rab_id; e_RABS_ToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.pDCPatSgNB = pDCPatSgNB; e_RABS_ToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.mCGresources = mCGresources; e_RABS_ToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.sCGresources = sCGresources; @@ -1628,14 +1628,14 @@ int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request( e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.full_E_RAB_Level_QoS_Parameters.allocationAndRetentionPriority.priorityLevel = priority_level; //Continue from filling the UL_GTPtunnelEndpointInformation inspired from how it is done for the HO case - INT32_TO_OCTET_STRING(e_MCG_rabs_tobeadded.gtp_teid, &e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.gTP_TEID); - e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.size = e_MCG_rabs_tobeadded.eNB_addr.length/8; - e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.bits_unused = e_MCG_rabs_tobeadded.eNB_addr.length%8; + INT32_TO_OCTET_STRING(x2ap_ENDC_sgnb_addition_req->e_rabs_tobeadded[i].gtp_teid, &e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.gTP_TEID); + e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.size = x2ap_ENDC_sgnb_addition_req->e_rabs_tobeadded[i].sgw_addr.length/8; + e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.bits_unused = x2ap_ENDC_sgnb_addition_req->e_rabs_tobeadded[i].sgw_addr.length%8; e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.buf = calloc(1, e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.size); memcpy (e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.buf, - e_MCG_rabs_tobeadded.eNB_addr.buffer, + x2ap_ENDC_sgnb_addition_req->e_rabs_tobeadded[i].sgw_addr.buffer, e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.size); } @@ -1748,21 +1748,21 @@ int x2ap_gNB_generate_ENDC_x2_SgNB_addition_request_ACK( x2ap_eNB_instance_t *in e_RABS_AdmittedToBeAdded_SgNBAddReq_ItemIEs->value.present = X2AP_E_RABs_Admitted_ToBeAdded_SgNBAddReqAck_ItemIEs__value_PR_E_RABs_Admitted_ToBeAdded_SgNBAddReqAck_Item; e_RABS_AdmittedToBeAdded_SgNBAddReq_Item = &e_RABS_AdmittedToBeAdded_SgNBAddReq_ItemIEs->value.choice.E_RABs_Admitted_ToBeAdded_SgNBAddReqAck_Item; { - e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->e_RAB_ID = e_RAB_ID; + e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->e_RAB_ID = x2ap_sgnb_addition_req_ACK->e_rabs_admitted_tobeadded[i].e_rab_id; e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.pDCPatSgNB = pDCPatSgNB; e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.mCGresources = mCGresources; e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.sCGresources = sCGresources; if (pDCPatSgNB == X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present){ e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.present = X2AP_E_RABs_Admitted_ToBeAdded_SgNBAddReqAck_Item__resource_configuration_PR_sgNBPDCPpresent; - INT32_TO_OCTET_STRING(e_SCG_rabs_tobeadded.gtp_teid, &e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.gTP_TEID); + INT32_TO_OCTET_STRING(x2ap_sgnb_addition_req_ACK->e_rabs_admitted_tobeadded[i].gtp_teid, &e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.gTP_TEID); e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.size = e_SCG_rabs_tobeadded.eNB_addr.length/8; e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.bits_unused = e_SCG_rabs_tobeadded.eNB_addr.length%8; e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.buf = calloc(1, e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.size); memcpy (e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.buf, - e_SCG_rabs_tobeadded.eNB_addr.buffer, + x2ap_sgnb_addition_req_ACK->e_rabs_admitted_tobeadded[i].gnb_addr.buffer, e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.size); } diff --git a/openair2/X2AP/x2ap_eNB_generate_messages.h b/openair2/X2AP/x2ap_eNB_generate_messages.h index 114ed84a68..3dfccc0e52 100644 --- a/openair2/X2AP/x2ap_eNB_generate_messages.h +++ b/openair2/X2AP/x2ap_eNB_generate_messages.h @@ -70,7 +70,7 @@ int x2ap_gNB_generate_ENDC_x2_setup_request(x2ap_eNB_instance_t *instance_p, x2a int x2ap_eNB_generate_ENDC_x2_setup_response( x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p); -int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request( x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p, int ue_id); +int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request( x2ap_eNB_instance_t *instance_p, x2ap_ENDC_sgnb_addition_req_t *x2ap_ENDC_sgnb_addition_req, x2ap_eNB_data_t *x2ap_eNB_data_p, int ue_id); int x2ap_gNB_generate_ENDC_x2_SgNB_addition_request_ACK( x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p, x2ap_ENDC_sgnb_addition_req_ACK_t *x2ap_sgnb_addition_req_ACK, int ue_id); diff --git a/openair2/X2AP/x2ap_eNB_handler.c b/openair2/X2AP/x2ap_eNB_handler.c index b7a9b70596..3dfc297ed6 100644 --- a/openair2/X2AP/x2ap_eNB_handler.c +++ b/openair2/X2AP/x2ap_eNB_handler.c @@ -1749,11 +1749,11 @@ int x2ap_gNB_handle_ENDC_sGNB_addition_request (instance_t instance, X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rab_param[i].qos.allocation_retention_priority.pre_emp_capability = e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.full_E_RAB_Level_QoS_Parameters.allocationAndRetentionPriority.pre_emptionCapability; X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rab_param[i].qos.allocation_retention_priority.priority_level = e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.full_E_RAB_Level_QoS_Parameters.allocationAndRetentionPriority.priorityLevel; - memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].eNB_addr.buffer, + memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].sgw_addr.buffer, e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.buf, e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.size); - X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].eNB_addr.length = + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].sgw_addr.length = e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.size * 8 - e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.bits_unused; OCTET_STRING_TO_INT32(&e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.gTP_TEID, @@ -1891,10 +1891,10 @@ int x2ap_eNB_handle_ENDC_sGNB_addition_response (instance_t instance, X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].e_rab_id = e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->e_RAB_ID ; if(e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->en_DC_ResourceConfiguration.pDCPatSgNB == X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present){ - memcpy(X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].eNB_addr.buffer, + memcpy(X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer, e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.buf, e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.size); - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].eNB_addr.length = + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.length = e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.size * 8 - e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.bits_unused; OCTET_STRING_TO_INT32(&e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.gTP_TEID, @@ -1964,7 +1964,7 @@ int x2ap_gNB_handle_ENDC_sGNB_reconfiguration_complete (instance_t instance, instance_p = x2ap_eNB_get_instance(instance); DevAssert(instance_p != NULL); - //Allocate an ITTI X2AP_SGNB_ADDITION_REQ message instead + //Allocate an ITTI X2AP_sGNB_reconfiguration_complete message msg = itti_alloc_new_message(TASK_X2AP, X2AP_ENDC_SGNB_RECONF_COMPLETE); /* X2AP_ProtocolIE_ID_id_MeNB_UE_X2AP_ID */ diff --git a/openair3/S1AP/s1ap_eNB.c b/openair3/S1AP/s1ap_eNB.c index 3592cf80a1..c228034245 100644 --- a/openair3/S1AP/s1ap_eNB.c +++ b/openair3/S1AP/s1ap_eNB.c @@ -69,7 +69,6 @@ s1ap_eNB_config_t s1ap_config; static int s1ap_eNB_generate_s1_setup_request( s1ap_eNB_instance_t *instance_p, s1ap_eNB_mme_data_t *s1ap_mme_data_p); - void s1ap_eNB_handle_register_eNB(instance_t instance, s1ap_register_enb_req_t *s1ap_register_eNB); void s1ap_eNB_handle_sctp_association_resp(instance_t instance, sctp_new_association_resp_t *sctp_new_association_resp); @@ -361,6 +360,12 @@ void *s1ap_eNB_process_itti_msg(void *notUsed) { } break; + case S1AP_E_RAB_MODIFICATION_IND: { + s1ap_eNB_generate_E_RAB_Modification_Indication(ITTI_MESSAGE_GET_INSTANCE(received_msg), + &S1AP_E_RAB_MODIFICATION_IND(received_msg)); + } + break; + case S1AP_UE_CONTEXT_RELEASE_COMPLETE: { s1ap_ue_context_release_complete(ITTI_MESSAGE_GET_INSTANCE(received_msg), &S1AP_UE_CONTEXT_RELEASE_COMPLETE(received_msg)); @@ -508,3 +513,7 @@ static int s1ap_eNB_generate_s1_setup_request( s1ap_eNB_itti_send_sctp_data_req(instance_p->instance, s1ap_mme_data_p->assoc_id, buffer, len, 0); return ret; } + + + + diff --git a/openair3/S1AP/s1ap_eNB_handlers.c b/openair3/S1AP/s1ap_eNB_handlers.c index 87abc1ede9..28ee11187e 100644 --- a/openair3/S1AP/s1ap_eNB_handlers.c +++ b/openair3/S1AP/s1ap_eNB_handlers.c @@ -104,6 +104,11 @@ int s1ap_eNB_handle_s1_path_switch_request_failure(uint32_t assoc_ uint32_t stream, S1AP_S1AP_PDU_t *pdu); +static +int s1ap_eNB_handle_s1_ENDC_e_rab_modification_confirm(uint32_t assoc_id, + uint32_t stream, + S1AP_S1AP_PDU_t *pdu); + /* Handlers matrix. Only eNB related procedure present here */ s1ap_message_decoded_callback messages_callback[][3] = { { 0, 0, 0 }, /* HandoverPreparation */ @@ -154,6 +159,9 @@ s1ap_message_decoded_callback messages_callback[][3] = { { 0, 0, 0 }, /* UplinkUEAssociatedLPPaTransport */ { 0, 0, 0 }, /* DownlinkNonUEAssociatedLPPaTransport */ { 0, 0, 0 }, /* UplinkNonUEAssociatedLPPaTransport */ + { 0, 0, 0 }, /* UERadioCapabilityMatch */ + { 0, 0, 0 }, /* PWSRestartIndication */ + { 0, s1ap_eNB_handle_s1_ENDC_e_rab_modification_confirm, 0 }, /* E_RABModificationIndication */ }; char *s1ap_direction2String(int s1ap_dir) { static char *s1ap_direction_String[] = { @@ -1722,3 +1730,13 @@ int s1ap_eNB_handle_s1_path_switch_request_failure(uint32_t assoc_ // TODO continue return 0; } + +static +int s1ap_eNB_handle_s1_ENDC_e_rab_modification_confirm(uint32_t assoc_id, + uint32_t stream, + S1AP_S1AP_PDU_t *pdu){ + + LOG_W(S1AP, "Implementation of S1AP E-RAB Modification confirm handler is pending...\n"); + return 0; +} + diff --git a/openair3/S1AP/s1ap_eNB_nas_procedures.c b/openair3/S1AP/s1ap_eNB_nas_procedures.c index d271ddf6ba..4877609754 100644 --- a/openair3/S1AP/s1ap_eNB_nas_procedures.c +++ b/openair3/S1AP/s1ap_eNB_nas_procedures.c @@ -1620,3 +1620,146 @@ int s1ap_eNB_path_switch_req(instance_t instance, return ret; } + + +//----------------------------------------------------------------------------- +/* +* eNB generate a S1 E_RAB Modification Indication towards MME +*/ +int s1ap_eNB_generate_E_RAB_Modification_Indication( + instance_t instance, + s1ap_e_rab_modification_ind_t *e_rab_modification_ind) +//----------------------------------------------------------------------------- +{ + struct s1ap_eNB_ue_context_s *ue_context_p = NULL; + S1AP_S1AP_PDU_t pdu; + S1AP_E_RABModificationIndication_t *out = NULL; + S1AP_E_RABModificationIndicationIEs_t *ie = NULL; + S1AP_E_RABToBeModifiedItemBearerModInd_t *E_RAB_ToBeModifiedItem_BearerModInd = NULL; + S1AP_E_RABToBeModifiedItemBearerModIndIEs_t *E_RAB_ToBeModifiedItem_BearerModInd_IEs = NULL; + + S1AP_E_RABNotToBeModifiedItemBearerModInd_t *E_RAB_NotToBeModifiedItem_BearerModInd = NULL; + S1AP_E_RABNotToBeModifiedItemBearerModIndIEs_t *E_RAB_NotToBeModifiedItem_BearerModInd_IEs = NULL; + + + s1ap_eNB_instance_t *s1ap_eNB_instance_p = NULL; + s1ap_eNB_instance_p = s1ap_eNB_get_instance(instance); + uint8_t *buffer = NULL; + uint32_t len = 0; + int ret = 0; + DevAssert(s1ap_eNB_instance_p != NULL); + DevAssert(e_rab_modification_ind != NULL); + + int num_e_rabs_tobemodified = e_rab_modification_ind->nb_of_e_rabs_tobemodified; + int num_e_rabs_nottobemodified = e_rab_modification_ind->nb_of_e_rabs_nottobemodified; + + uint32_t CSG_id = 0; + + /* Prepare the S1AP message to encode */ + memset(&pdu, 0, sizeof(pdu)); + pdu.present = S1AP_S1AP_PDU_PR_initiatingMessage; + pdu.choice.initiatingMessage.procedureCode = S1AP_ProcedureCode_id_E_RABModificationIndication; + pdu.choice.initiatingMessage.criticality = S1AP_Criticality_reject; + pdu.choice.initiatingMessage.value.present = S1AP_InitiatingMessage__value_PR_E_RABModificationIndication; + out = &pdu.choice.initiatingMessage.value.choice.E_RABModificationIndication; + /* mandatory */ + ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t)); + ie->id = S1AP_ProtocolIE_ID_id_MME_UE_S1AP_ID; + ie->criticality = S1AP_Criticality_reject; + ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_MME_UE_S1AP_ID; + ie->value.choice.MME_UE_S1AP_ID = e_rab_modification_ind->mme_ue_s1ap_id; + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t)); + ie->id = S1AP_ProtocolIE_ID_id_eNB_UE_S1AP_ID; + ie->criticality = S1AP_Criticality_reject; + ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_ENB_UE_S1AP_ID; + ie->value.choice.ENB_UE_S1AP_ID = e_rab_modification_ind->eNB_ue_s1ap_id; + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + //E-RABs to be modified list + ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t)); + ie->id = S1AP_ProtocolIE_ID_id_E_RABToBeModifiedListBearerModInd; + ie->criticality = S1AP_Criticality_reject; + ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_E_RABToBeModifiedListBearerModInd; + + //The following two for-loops here will probably need to change. We should do a different type of search + for(int i=0; iid = S1AP_ProtocolIE_ID_id_E_RABToBeModifiedItemBearerModInd; + E_RAB_ToBeModifiedItem_BearerModInd_IEs->criticality = S1AP_Criticality_reject; + E_RAB_ToBeModifiedItem_BearerModInd_IEs->value.present = S1AP_E_RABToBeModifiedItemBearerModIndIEs__value_PR_E_RABToBeModifiedItemBearerModInd; + E_RAB_ToBeModifiedItem_BearerModInd = &E_RAB_ToBeModifiedItem_BearerModInd_IEs->value.choice.E_RABToBeModifiedItemBearerModInd; + + { + E_RAB_ToBeModifiedItem_BearerModInd->e_RAB_ID = e_rab_modification_ind->e_rabs_tobemodified[i].e_rab_id; + + E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.size = e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.length/8; + E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.bits_unused = e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.length%8; + E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.buf = calloc(1, E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.size); + memcpy (E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.buf, e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.buffer, + E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.size); + + INT32_TO_OCTET_STRING(e_rab_modification_ind->e_rabs_tobemodified[i].gtp_teid, &E_RAB_ToBeModifiedItem_BearerModInd->dL_GTP_TEID); + + } + ASN_SEQUENCE_ADD(&ie->value.choice.E_RABToBeModifiedListBearerModInd.list, E_RAB_ToBeModifiedItem_BearerModInd_IEs); + } + + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + //E-RABs NOT to be modified list + ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t)); + ie->id = S1AP_ProtocolIE_ID_id_E_RABNotToBeModifiedListBearerModInd; + ie->criticality = S1AP_Criticality_reject; + if(num_e_rabs_nottobemodified > 0) { + ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_E_RABNotToBeModifiedListBearerModInd; + + for(int i=0; iid = S1AP_ProtocolIE_ID_id_E_RABNotToBeModifiedItemBearerModInd; + E_RAB_NotToBeModifiedItem_BearerModInd_IEs->criticality = S1AP_Criticality_reject; + E_RAB_NotToBeModifiedItem_BearerModInd_IEs->value.present = S1AP_E_RABNotToBeModifiedItemBearerModIndIEs__value_PR_E_RABNotToBeModifiedItemBearerModInd; + E_RAB_NotToBeModifiedItem_BearerModInd = &E_RAB_NotToBeModifiedItem_BearerModInd_IEs->value.choice.E_RABNotToBeModifiedItemBearerModInd; + + { + E_RAB_NotToBeModifiedItem_BearerModInd->e_RAB_ID = e_rab_modification_ind->e_rabs_nottobemodified[i].e_rab_id; + + E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.size = e_rab_modification_ind->e_rabs_nottobemodified[i].eNB_addr.length/8; + E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.bits_unused = e_rab_modification_ind->e_rabs_nottobemodified[i].eNB_addr.length%8; + E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.buf = + calloc(1, E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.size); + memcpy (E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.buf, e_rab_modification_ind->e_rabs_nottobemodified[i].eNB_addr.buffer, + E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.size); + + INT32_TO_OCTET_STRING(e_rab_modification_ind->e_rabs_nottobemodified[i].gtp_teid, &E_RAB_NotToBeModifiedItem_BearerModInd->dL_GTP_TEID); + + } + ASN_SEQUENCE_ADD(&ie->value.choice.E_RABNotToBeModifiedListBearerModInd.list, E_RAB_NotToBeModifiedItem_BearerModInd_IEs); + } + } + else + ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_NOTHING; + + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t)); + ie->id = S1AP_ProtocolIE_ID_id_CSGMembershipInfo; + ie->criticality = S1AP_Criticality_reject; + ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_CSGMembershipInfo; + ie->value.choice.CSGMembershipInfo.cSGMembershipStatus = S1AP_CSGMembershipStatus_member; + INT32_TO_BIT_STRING(CSG_id, &ie->value.choice.CSGMembershipInfo.cSG_Id); + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + + if (s1ap_eNB_encode_pdu(&pdu, &buffer, &len) < 0) { + S1AP_ERROR("Failed to encode S1 setup request\n"); + return -1; + } + + /* Non UE-Associated signalling -> stream = 0 */ + s1ap_eNB_itti_send_sctp_data_req(s1ap_eNB_instance_p->instance, ue_context_p->mme_ref->assoc_id, buffer, len, 0); + return ret; +} + + diff --git a/openair3/S1AP/s1ap_eNB_nas_procedures.h b/openair3/S1AP/s1ap_eNB_nas_procedures.h index c425719872..47f71cc795 100644 --- a/openair3/S1AP/s1ap_eNB_nas_procedures.h +++ b/openair3/S1AP/s1ap_eNB_nas_procedures.h @@ -52,4 +52,8 @@ int s1ap_eNB_e_rab_release_resp(instance_t instance, int s1ap_eNB_path_switch_req(instance_t instance, s1ap_path_switch_req_t *path_switch_req_p); + +int s1ap_eNB_generate_E_RAB_Modification_Indication( + instance_t instance, s1ap_e_rab_modification_ind_t *e_rab_modification_ind); + #endif /* S1AP_ENB_NAS_PROCEDURES_H_ */ diff --git a/targets/COMMON/create_nr_tasks.c b/targets/COMMON/create_nr_tasks.c index 24c4115980..13f72b3876 100644 --- a/targets/COMMON/create_nr_tasks.c +++ b/targets/COMMON/create_nr_tasks.c @@ -51,17 +51,17 @@ int create_gNB_tasks(uint32_t gnb_nb) } if (gnb_nb > 0) { - /* Last task to create, others task must be ready before its start */ + // Last task to create, others task must be ready before its start if (itti_create_task (TASK_GNB_APP, gNB_app_task, NULL) < 0) { LOG_E(GNB_APP, "Create task for gNB APP failed\n"); return -1; } } -/* + if (EPC_MODE_ENABLED) { if (gnb_nb > 0) { - if (itti_create_task (TASK_SCTP, sctp_eNB_task, NULL) < 0) { + /*if (itti_create_task (TASK_SCTP, sctp_eNB_task, NULL) < 0) { LOG_E(SCTP, "Create task for SCTP failed\n"); return -1; } @@ -69,7 +69,7 @@ int create_gNB_tasks(uint32_t gnb_nb) if (itti_create_task (TASK_S1AP, s1ap_eNB_task, NULL) < 0) { LOG_E(S1AP, "Create task for S1AP failed\n"); return -1; - } + }*/ if(!emulate_rf){ if (itti_create_task (TASK_UDP, udp_eNB_task, NULL) < 0) { LOG_E(UDP_, "Create task for UDP failed\n"); @@ -84,7 +84,15 @@ int create_gNB_tasks(uint32_t gnb_nb) } } -*/ + + /*if (gnb_nb > 0) { + // Last task to create, others task must be ready before its start + if (itti_create_task (TASK_GNB_APP, gNB_app_task, NULL) < 0) { + LOG_E(GNB_APP, "Create task for gNB APP failed\n"); + return -1; + } + }*/ + if (gnb_nb > 0) { LOG_I(NR_RRC,"Creating NR RRC gNB Task\n"); @@ -100,4 +108,4 @@ int create_gNB_tasks(uint32_t gnb_nb) return 0; } -#endif +//#endif From de34a2ff28f4648a45df063bf4a3a37c4b324aa1 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Wed, 11 Mar 2020 12:02:55 +0100 Subject: [PATCH 083/553] Update gNB configuration file used for ENDC --- .../CONF/gnb.band78.106PRB.slave.conf | 295 ++++++++++++++++++ 1 file changed, 295 insertions(+) create mode 100644 targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.106PRB.slave.conf diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.106PRB.slave.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.106PRB.slave.conf new file mode 100644 index 0000000000..81796ada2c --- /dev/null +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.106PRB.slave.conf @@ -0,0 +1,295 @@ +Active_gNBs = ( "gNB-Eurecom-5GNRBox"); +# Asn1_verbosity, choice in: none, info, annoying +Asn1_verbosity = "none"; + +gNBs = +( + { + ////////// Identification parameters: + gNB_ID = 0xe00; + + cell_type = "CELL_MACRO_GNB"; + + gNB_name = "gNB-Eurecom-5GNRBox"; + + // Tracking area code, 0x0000 and 0xfffe are reserved values + tracking_area_code = 1; + + plmn_list = ({mcc = 208; mnc = 93; mnc_length = 2;}); + + tr_s_preference = "local_mac" + + ////////// Physical parameters: + + ssb_SubcarrierOffset = 0; + pdsch_AntennaPorts = 1; + + servingCellConfigCommon = ( + { + #spCellConfigCommon + + physCellId = 0; + +# downlinkConfigCommon + #frequencyInfoDL + # this is 3600 MHz + 43 PRBs@30kHz SCS (same as initial BWP) + absoluteFrequencySSB = 641032; + dl_frequencyBand = 78; + # this is 3600 MHz + dl_absoluteFrequencyPointA = 640000; + #scs-SpecificCarrierList + dl_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + dl_subcarrierSpacing = 1; + dl_carrierBandwidth = 106; + #initialDownlinkBWP + #genericParameters + # this is RBstart=0,L=50 (275*(L-1))+RBstart + initialDLBWPlocationAndBandwidth = 6366; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialDLBWPsubcarrierSpacing = 1; + #pdcch-ConfigCommon + initialDLBWPcontrolResourceSetZero = 12; + initialDLBWPsearchSpaceZero = 0; + #pdsch-ConfigCommon + #pdschTimeDomainAllocationList (up to 16 entries) + initialDLBWPk0_0 = 0; + #initialULBWPmappingType + #0=typeA,1=typeB + initialDLBWPmappingType_0 = 0; + #this is SS=1,L=13 + initialDLBWPstartSymbolAndLength_0 = 40; + + initialDLBWPk0_1 = 0; + initialDLBWPmappingType_1 = 0; + #this is SS=2,L=12 + initialDLBWPstartSymbolAndLength_1 = 53; + + initialDLBWPk0_2 = 0; + initialDLBWPmappingType_2 = 0; + #this is SS=1,L=12 + initialDLBWPstartSymbolAndLength_2 = 54; + + initialDLBWPk0_3 = 0; + initialDLBWPmappingType_3 = 0; + #this is SS=1,L=4 + initialDLBWPstartSymbolAndLength_3 = 57; + + #uplinkConfigCommon + #frequencyInfoUL + ul_frequencyBand = 78; + #scs-SpecificCarrierList + ul_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + ul_subcarrierSpacing = 1; + ul_carrierBandwidth = 106; + pMax = 20; + #initialUplinkBWP + #genericParameters + initialULBWPlocationAndBandwidth = 6366; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialULBWPsubcarrierSpacing = 1; + #rach-ConfigCommon + #rach-ConfigGeneric + prach_ConfigurationIndex = 98; +#prach_msg1_FDM +#0 = one, 1=two, 2=four, 3=eight + prach_msg1_FDM = 0; + prach_msg1_FrequencyStart = 0; + zeroCorrelationZoneConfig = 13; + preambleReceivedTargetPower = -118; +#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200) + preambleTransMax = 6; +#powerRampingStep +# 0=dB0,1=dB2,2=dB4,3=dB6 + powerRampingStep = 1; +#ra_ReponseWindow +#1,2,4,8,10,20,40,80 + ra_ResponseWindow = 4; +#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR +#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4; +#oneHalf (0..15) 4,8,12,16,...60,64 + ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; +#ra_ContentionResolutionTimer +#(0..7) 8,16,24,32,40,48,56,64 + ra_ContentionResolutionTimer = 7; + rsrp_ThresholdSSB = 19; +#prach-RootSequenceIndex_PR +#1 = 839, 2 = 139 + prach_RootSequenceIndex_PR = 2; + prach_RootSequenceIndex = 1; + # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex + # + msg1_SubcarrierSpacing = 1, + +# restrictedSetConfig +# 0=unrestricted, 1=restricted type A, 2=restricted type B + restrictedSetConfig = 0, + # pusch-ConfigCommon (up to 16 elements) + initialULBWPk2_0 = 2; + initialULBWPmappingType_0 = 1 + # this is SS=0 L=11 + initialULBWPstartSymbolAndLength_0 = 55; + + initialULBWPk2_1 = 2; + initialULBWPmappingType_1 = 1; + # this is SS=0 L=12 + initialULBWPstartSymbolAndLength_1 = 69; + + initialULBWPk2_2 = 7; + initialULBWPmappingType_2 = 1; + # this is SS=10 L=4 + initialULBWPstartSymbolAndLength_2 = 52; + + + msg3_DeltaPreamble = 1; + p0_NominalWithGrant =-90; + +# pucch-ConfigCommon setup : +# pucchGroupHopping +# 0 = neither, 1= group hopping, 2=sequence hopping + pucchGroupHopping = 0; + hoppingId = 40; + p0_nominal = -90; +# ssb_PositionsInBurs_BitmapPR +# 1=short, 2=medium, 3=long + ssb_PositionsInBurst_PR = 2; + ssb_PositionsInBurst_Bitmap = 1; + +# ssb_periodicityServingCell +# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1 + ssb_periodicityServingCell = 2; + +# dmrs_TypeA_position +# 0 = pos2, 1 = pos3 + dmrs_TypeA_Position = 0; + +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + subcarrierSpacing = 1; + + + #tdd-UL-DL-ConfigurationCommon +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + referenceSubcarrierSpacing = 1; + # pattern1 + # dl_UL_TransmissionPeriodicity + # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10 + dl_UL_TransmissionPeriodicity = 6; + nrofDownlinkSlots = 7; + nrofDownlinkSymbols = 6; + nrofUplinkSlots = 2; + nrofUplinkSymbols = 4; + + ssPBCH_BlockPower = 10; + } + + ); + + + # ------- SCTP definitions + SCTP : + { + # Number of streams to use in input/output + SCTP_INSTREAMS = 2; + SCTP_OUTSTREAMS = 2; + }; + + + ////////// MME parameters: + mme_ip_address = ( { ipv4 = "192.168.12.26"; + ipv6 = "192:168:30::17"; + active = "yes"; + preference = "ipv4"; + } + ); + + ///X2 + enable_x2 = "yes"; + t_reloc_prep = 1000; /* unit: millisecond */ + tx2_reloc_overall = 2000; /* unit: millisecond */ + target_enb_x2_ip_address = ( + { ipv4 = "192.168.12.188"; + ipv6 = "192:168:30::17"; + preference = "ipv4"; + } + ); + + NETWORK_INTERFACES : + { + + GNB_INTERFACE_NAME_FOR_S1_MME = "enp0s31f6"; + GNB_IPV4_ADDRESS_FOR_S1_MME = "192.168.12.75/24"; + GNB_INTERFACE_NAME_FOR_S1U = "eth0"; + GNB_IPV4_ADDRESS_FOR_S1U = "192.168.12.75/24"; + GNB_PORT_FOR_S1U = 2152; # Spec 2152 + + GNB_IPV4_ADDRESS_FOR_X2C = "192.168.12.75/23"; + GNB_PORT_FOR_X2C = 36422; # Spec 36422 + }; + } +); + +MACRLCs = ( + { + num_cc = 1; + tr_s_preference = "local_L1"; + tr_n_preference = "local_RRC"; + } +); + +L1s = ( + { + num_cc = 1; + tr_n_preference = "local_mac"; + } +); + +RUs = ( + { + local_rf = "yes" + nb_tx = 1 + nb_rx = 1 + att_tx = 0 + att_rx = 0; + bands = [7]; + max_pdschReferenceSignalPower = -27; + max_rxgain = 114; + eNB_instances = [0]; + sdr_addrs = "addr=192.168.20.2,mgmt_addr=192.168.20.2"; + clock_src = "internal"; + } +); + +THREAD_STRUCT = ( + { + #three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT" + parallel_config = "PARALLEL_RU_L1_TRX_SPLIT"; + #two option for worker "WORKER_DISABLE" or "WORKER_ENABLE" + worker_config = "WORKER_ENABLE"; + } +); + + log_config : + { + global_log_level ="info"; + global_log_verbosity ="medium"; + hw_log_level ="info"; + hw_log_verbosity ="medium"; + phy_log_level ="info"; + phy_log_verbosity ="medium"; + mac_log_level ="info"; + mac_log_verbosity ="high"; + rlc_log_level ="info"; + rlc_log_verbosity ="medium"; + pdcp_log_level ="info"; + pdcp_log_verbosity ="medium"; + rrc_log_level ="info"; + rrc_log_verbosity ="medium"; + }; From c15fb8c7a419be8ee40f16d8a941c7e6656b6165 Mon Sep 17 00:00:00 2001 From: adk Date: Wed, 11 Mar 2020 14:45:14 +0100 Subject: [PATCH 084/553] PUSCH DMRS mapping type B start symbol fix --- openair1/PHY/NR_REFSIG/dmrs_nr.c | 9 ++++++++- openair1/PHY/NR_REFSIG/dmrs_nr.h | 1 + openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c | 3 +++ 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/openair1/PHY/NR_REFSIG/dmrs_nr.c b/openair1/PHY/NR_REFSIG/dmrs_nr.c index 75de900753..77861aef53 100644 --- a/openair1/PHY/NR_REFSIG/dmrs_nr.c +++ b/openair1/PHY/NR_REFSIG/dmrs_nr.c @@ -111,6 +111,7 @@ int32_t get_l_prime(uint8_t duration_in_symbols, uint8_t mapping_type, pusch_dmr * n index starting 0,1,... * delta see Table 6.4.1.1.3 * duration_in_symbols number of scheduled PUSCH ofdm symbols +* start_symbol first symbol index in PUSCH allocation * dmrs_UplinkConfig DMRS uplink configuration * mapping_type PUSCH mapping type (A or B) * ofdm_symbol_size IFFT size @@ -128,6 +129,7 @@ uint8_t is_dmrs_symbol(uint8_t l, uint16_t n, uint8_t delta, uint8_t duration_in_symbols, + uint8_t start_symbol, dmrs_UplinkConfig_t *dmrs_UplinkConfig, uint8_t mapping_type, uint16_t ofdm_symbol_size) { @@ -141,6 +143,11 @@ uint8_t is_dmrs_symbol(uint8_t l, dmrs_type = dmrs_UplinkConfig->pusch_dmrs_type; additional_pos = dmrs_UplinkConfig->pusch_dmrs_AdditionalPosition; + if (mapping_type==typeB) + l -= start_symbol; + + AssertFatal(l >= 0,"Check DMRS configuration (start_symbol) !\n"); + l0 = get_l0_ul(mapping_type, 2); l_prime_mask = get_l_prime(duration_in_symbols, mapping_type, additional_pos, dmrs_UplinkConfig->pusch_maxLength); @@ -370,7 +377,7 @@ void lte_gold_new(LTE_DL_FRAME_PARMS *frame_parms, uint32_t lte_gold_table[20][2 * * NAME : get_l0_ul * -* PARAMETERS : mapping_type : PUSCH mapping type +* PARAMETERS : mapping_type : PUSCH mapping type * dmrs_typeA_position : higher layer parameter * * RETURN : demodulation reference signal for PUSCH diff --git a/openair1/PHY/NR_REFSIG/dmrs_nr.h b/openair1/PHY/NR_REFSIG/dmrs_nr.h index de77a8a6ce..d03a0ee7ac 100644 --- a/openair1/PHY/NR_REFSIG/dmrs_nr.h +++ b/openair1/PHY/NR_REFSIG/dmrs_nr.h @@ -66,6 +66,7 @@ uint8_t is_dmrs_symbol(uint8_t l, uint16_t n, uint8_t delta, uint8_t duration_in_symbols, + uint8_t start_symbol, dmrs_UplinkConfig_t *dmrs_UplinkConfig, uint8_t mapping_type, uint16_t ofdm_symbol_size); diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c index 09e46421f4..2c5acbf118 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c @@ -136,6 +136,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, 0, 0, harq_process_ul_ue->number_of_symbols, + start_symbol, &UE->dmrs_UplinkConfig, mapping_type, frame_parms->ofdm_symbol_size); @@ -273,6 +274,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, 0, 0, harq_process_ul_ue->number_of_symbols, + start_symbol, &UE->dmrs_UplinkConfig, mapping_type, frame_parms->ofdm_symbol_size); @@ -359,6 +361,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, n, delta, harq_process_ul_ue->number_of_symbols, + start_symbol, &UE->dmrs_UplinkConfig, mapping_type, frame_parms->ofdm_symbol_size); From 0564357e330256e3bc1a6d9b0e55494d1b1a5ca6 Mon Sep 17 00:00:00 2001 From: matzakos Date: Wed, 11 Mar 2020 16:07:02 +0100 Subject: [PATCH 085/553] ENDC path switch S1-U: Minor correction --- openair2/RRC/LTE/rrc_eNB.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index b8bbb55a82..3ab51d6385 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -7506,11 +7506,36 @@ rrc_eNB_decode_dcch( //Looking for a condition to trigger S1AP E-RAB-Modification-indication, based on the reception of RRCConnectionReconfigurationComplete //including NR specific elements. Not sure if this is the correct one and the correct placement - if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + /*if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension-> scg_ConfigResponseNR_r15->buf!=NULL){ - /*Trigger E-RAB Modification Indication */ + //Trigger E-RAB Modification Indication rrc_eNB_send_E_RAB_Modification_Indication(ctxt_pP, ue_context_p); + }*/ + + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension!=NULL){ + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension!=NULL){ + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL){ + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL){ + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL){ + if (ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL){ + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension + ->scg_ConfigResponseNR_r15!=NULL){ + /*Trigger E-RAB Modification Indication */ + rrc_eNB_send_E_RAB_Modification_Indication(ctxt_pP, ue_context_p); + } + } + } + } + } + } } } else { From 18c8a4a4e6577d8d2c3b50b5b26208f9f48def1c Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Thu, 12 Mar 2020 14:09:41 +0100 Subject: [PATCH 086/553] taking into account n_ta_offset in slot fep ul --- openair1/PHY/MODULATION/slot_fep_nr.c | 23 ++++++++++++++++++----- openair1/SCHED_NR/nr_ru_procedures.c | 6 ++++-- 2 files changed, 22 insertions(+), 7 deletions(-) diff --git a/openair1/PHY/MODULATION/slot_fep_nr.c b/openair1/PHY/MODULATION/slot_fep_nr.c index 4bfc3ff30f..a15b12ed4e 100644 --- a/openair1/PHY/MODULATION/slot_fep_nr.c +++ b/openair1/PHY/MODULATION/slot_fep_nr.c @@ -394,12 +394,13 @@ int nr_slot_fep_ul(NR_DL_FRAME_PARMS *frame_parms, int sample_offset, int no_prefix) { - uint32_t slot_offset; - uint32_t rxdata_offset; + int32_t slot_offset, rxdata_offset; unsigned int nb_prefix_samples = (no_prefix ? 0 : frame_parms->nb_prefix_samples); unsigned int nb_prefix_samples0 = (no_prefix ? 0 : frame_parms->nb_prefix_samples0); + int tmp_dft_in[8192] __attribute__ ((aligned (32))); + void (*dft)(int16_t *,int16_t *, int); switch (frame_parms->ofdm_symbol_size) { @@ -442,14 +443,26 @@ int nr_slot_fep_ul(NR_DL_FRAME_PARMS *frame_parms, slot_offset = frame_parms->get_samples_slot_timestamp(Ns,frame_parms,0); - if(symbol == 0) rxdata_offset = slot_offset + nb_prefix_samples0 - SOFFSET; else rxdata_offset = slot_offset + nb_prefix_samples0 + (symbol * (frame_parms->ofdm_symbol_size + nb_prefix_samples)) - SOFFSET; - dft((int16_t *)&rxdata[rxdata_offset], - (int16_t *)&rxdataF[symbol * frame_parms->ofdm_symbol_size], 1); + if(sample_offset>rxdata_offset) { + memcpy((void *)tmp_dft_in, + (void *) &rxdata[frame_parms->samples_per_frame-sample_offset+rxdata_offset], + (sample_offset-rxdata_offset)*sizeof(int)); + + memcpy((void *)&tmp_dft_in[sample_offset-rxdata_offset], + (void *) &rxdata[0], + (frame_parms->ofdm_symbol_size-sample_offset+rxdata_offset)*sizeof(int)); + + dft((int16_t *)&tmp_dft_in, + (int16_t *)&rxdataF[symbol * frame_parms->ofdm_symbol_size], 1); + } + else + dft((int16_t *)&rxdata[rxdata_offset-sample_offset], + (int16_t *)&rxdataF[symbol * frame_parms->ofdm_symbol_size], 1); return(0); } diff --git a/openair1/SCHED_NR/nr_ru_procedures.c b/openair1/SCHED_NR/nr_ru_procedures.c index aefeec43e2..560f47059a 100644 --- a/openair1/SCHED_NR/nr_ru_procedures.c +++ b/openair1/SCHED_NR/nr_ru_procedures.c @@ -520,7 +520,7 @@ void nr_fep0(RU_t *ru, int first_half) { ru->common.rxdataF[aa], l, proc->tti_rx, - 0, + ru->N_TA_offset, 0); } } @@ -642,6 +642,8 @@ void nr_fep_full(RU_t *ru, int slot) { // if ((fp->frame_type == TDD) && // (subframe_select(fp,proc->tti_rx) != NR_UPLINK_SLOT)) return; + LOG_D(PHY,"In fep_full for slot = %d\n", proc->tti_rx); + start_meas(&ru->ofdm_demod_stats); if (ru->idx == 0) VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPRX, 1 ); @@ -655,7 +657,7 @@ void nr_fep_full(RU_t *ru, int slot) { ru->common.rxdataF[aa], l, proc->tti_rx, - 0, + ru->N_TA_offset, 0); } } From 86dc600cd9665926825693484ef0d21e74a8b3f0 Mon Sep 17 00:00:00 2001 From: Cedric Roux Date: Thu, 12 Mar 2020 14:33:47 +0100 Subject: [PATCH 087/553] bugfix --- openair2/RRC/LTE/rrc_eNB.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index 3ab51d6385..ef08b616eb 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -4375,7 +4375,7 @@ rrc_eNB_process_MeasurementReport( //For the moment we have a single E-RAB which will be the one to be added to the gNB //Not sure how to select bearers to be added if there are multiple. X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded = 1; - for (int e_rab=0; i< X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded; e_rab++){ + for (int e_rab=0; e_rab < X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded; e_rab++){ X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].e_rab_id = ue_context_pP->ue_context.e_rab[e_rab].param.e_rab_id; X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].gtp_teid = ue_context_pP->ue_context.e_rab[e_rab].param.gtp_teid; memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr, From 143fd5ea5a223853fdaf402915351cc08abbf990 Mon Sep 17 00:00:00 2001 From: Cedric Roux Date: Thu, 12 Mar 2020 14:50:02 +0100 Subject: [PATCH 088/553] bugfix --- openair2/RRC/NR/rrc_gNB_nsa.c | 69 ++++++++++++++++++----------------- 1 file changed, 36 insertions(+), 33 deletions(-) diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c index d70bbed189..649bacf85f 100644 --- a/openair2/RRC/NR/rrc_gNB_nsa.c +++ b/openair2/RRC/NR/rrc_gNB_nsa.c @@ -42,9 +42,10 @@ void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList, x2ap_ENDC_sgnb_addition_req_t *m) { struct rrc_gNB_ue_context_s *ue_context_p = NULL; - OCTET_STRING_t *ueCapabilityRAT_Container_nr; - OCTET_STRING_t *ueCapabilityRAT_Container_MRDC; + OCTET_STRING_t *ueCapabilityRAT_Container_nr = NULL; + OCTET_STRING_t *ueCapabilityRAT_Container_MRDC = NULL; int list_size; + asn_dec_rval_t dec_rval; AssertFatal(UE_CapabilityRAT_ContainerList!=NULL,"UE_CapabilityRAT_ContainerList is null\n"); AssertFatal((list_size=UE_CapabilityRAT_ContainerList->list.count) >= 2, "UE_CapabilityRAT_ContainerList->list.size %d < 2\n",UE_CapabilityRAT_ContainerList->list.count); for (int i=0;ilist.array[i]->rat_Type == LTE_RAT_Type_eutra_nr) ueCapabilityRAT_Container_MRDC = &UE_CapabilityRAT_ContainerList->list.array[i]->ueCapabilityRAT_Container; } - AssertFatal(ueCapabilityRAT_Container_nr!=NULL,"ueCapabilityRAT_Container_nr is NULL\n"); - AssertFatal(ueCapabilityRAT_Container_MRDC!=NULL,"ueCapabilityRAT_Container_MRDC is NULL\n"); // decode and store capabilities ue_context_p = rrc_gNB_allocate_new_UE_context(rrc); - - asn_dec_rval_t dec_rval = uper_decode(NULL, - &asn_DEF_NR_UE_NR_Capability, - (void **)&ue_context_p->ue_context.UE_Capability_nr, - ueCapabilityRAT_Container_nr->buf, - ueCapabilityRAT_Container_nr->size, 0, 0); - if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { - LOG_E(RRC, "Failed to decode UE NR capabilities (%zu bytes) container size %lu\n", dec_rval.consumed,ueCapabilityRAT_Container_nr->size); - ASN_STRUCT_FREE(asn_DEF_NR_UE_NR_Capability, - ue_context_p->ue_context.UE_Capability_nr); - ue_context_p->ue_context.UE_Capability_nr = 0; - AssertFatal(1==0,"exiting\n"); + if (ueCapabilityRAT_Container_nr != NULL) { + dec_rval = uper_decode(NULL, + &asn_DEF_NR_UE_NR_Capability, + (void **)&ue_context_p->ue_context.UE_Capability_nr, + ueCapabilityRAT_Container_nr->buf, + ueCapabilityRAT_Container_nr->size, 0, 0); + + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + LOG_E(RRC, "Failed to decode UE NR capabilities (%zu bytes) container size %lu\n", dec_rval.consumed,ueCapabilityRAT_Container_nr->size); + ASN_STRUCT_FREE(asn_DEF_NR_UE_NR_Capability, + ue_context_p->ue_context.UE_Capability_nr); + ue_context_p->ue_context.UE_Capability_nr = 0; + AssertFatal(1==0,"exiting\n"); + } } - dec_rval = uper_decode(NULL, - &asn_DEF_NR_UE_MRDC_Capability, - (void **)&ue_context_p->ue_context.UE_Capability_MRDC, - ueCapabilityRAT_Container_MRDC->buf, - ueCapabilityRAT_Container_MRDC->size, 0, 0); + if (ueCapabilityRAT_Container_MRDC != NULL) { + dec_rval = uper_decode(NULL, + &asn_DEF_NR_UE_MRDC_Capability, + (void **)&ue_context_p->ue_context.UE_Capability_MRDC, + ueCapabilityRAT_Container_MRDC->buf, + ueCapabilityRAT_Container_MRDC->size, 0, 0); - if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { - LOG_E(RRC, "Failed to decode UE MRDC capabilities (%zu bytes)\n", dec_rval.consumed); - ASN_STRUCT_FREE(asn_DEF_NR_UE_MRDC_Capability, - ue_context_p->ue_context.UE_Capability_MRDC); - ue_context_p->ue_context.UE_Capability_MRDC = 0; - AssertFatal(1==0,"exiting\n"); + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + LOG_E(RRC, "Failed to decode UE MRDC capabilities (%zu bytes)\n", dec_rval.consumed); + ASN_STRUCT_FREE(asn_DEF_NR_UE_MRDC_Capability, + ue_context_p->ue_context.UE_Capability_MRDC); + ue_context_p->ue_context.UE_Capability_MRDC = 0; + AssertFatal(1==0,"exiting\n"); + } } // dump ue_capabilities - if ( LOG_DEBUGFLAG(DEBUG_ASN1) ) { + if ( LOG_DEBUGFLAG(DEBUG_ASN1 && ueCapabilityRAT_Container_nr != NULL) ) { xer_fprint(stdout, &asn_DEF_NR_UE_NR_Capability, ue_context_p->ue_context.UE_Capability_nr); } - if ( LOG_DEBUGFLAG(DEBUG_ASN1) ) { + if ( LOG_DEBUGFLAG(DEBUG_ASN1 && ueCapabilityRAT_Container_MRDC != NULL) ) { xer_fprint(stdout, &asn_DEF_NR_UE_MRDC_Capability, ue_context_p->ue_context.UE_Capability_MRDC); } @@ -110,7 +113,7 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_ gtpv1u_enb_create_tunnel_resp_t create_tunnel_resp; uint8_t inde_list[m->nb_e_rabs_tobeadded]; memset(inde_list, 0, m->nb_e_rabs_tobeadded*sizeof(uint8_t)); - protocol_ctxt_t *ctxt = NULL; + protocol_ctxt_t ctxt; // NR RRCReconfiguration @@ -156,13 +159,13 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_ //PM: Is this where we should extract the rnti from? create_tunnel_req.rnti = ue_context_p->ue_id_rnti; create_tunnel_req.num_tunnels = m->nb_e_rabs_tobeadded; - PROTOCOL_CTXT_SET_BY_MODULE_ID(ctxt, rrc->module_id, GNB_FLAG_YES, NOT_A_RNTI, 0, 0,rrc->module_id); + PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, rrc->module_id, GNB_FLAG_YES, NOT_A_RNTI, 0, 0,rrc->module_id); gtpv1u_create_s1u_tunnel( - ctxt->instance, + ctxt.instance, &create_tunnel_req, &create_tunnel_resp); rrc_eNB_process_GTPV1U_CREATE_TUNNEL_RESP( - ctxt, + &ctxt, &create_tunnel_resp, &inde_list[0]); X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).nb_e_rabs_admitted_tobeadded = m->nb_e_rabs_tobeadded; From c56075928aeee1cf29a5e24a0e72773ebab76a08 Mon Sep 17 00:00:00 2001 From: matzakos Date: Thu, 12 Mar 2020 19:56:15 +0100 Subject: [PATCH 089/553] ENDC path switch S1-U: Bugfixes --- openair2/RRC/LTE/rrc_eNB.c | 3 ++- openair2/RRC/NR/rrc_gNB_nsa.c | 4 +++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index ef08b616eb..c6a6440c87 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -4378,7 +4378,8 @@ rrc_eNB_process_MeasurementReport( for (int e_rab=0; e_rab < X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded; e_rab++){ X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].e_rab_id = ue_context_pP->ue_context.e_rab[e_rab].param.e_rab_id; X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].gtp_teid = ue_context_pP->ue_context.e_rab[e_rab].param.gtp_teid; - memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr, + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].drb_ID = 1; + memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr, &ue_context_pP->ue_context.e_rab[e_rab].param.sgw_addr, sizeof(transport_layer_addr_t)); } diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c index 649bacf85f..142f068467 100644 --- a/openair2/RRC/NR/rrc_gNB_nsa.c +++ b/openair2/RRC/NR/rrc_gNB_nsa.c @@ -159,7 +159,9 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_ //PM: Is this where we should extract the rnti from? create_tunnel_req.rnti = ue_context_p->ue_id_rnti; create_tunnel_req.num_tunnels = m->nb_e_rabs_tobeadded; - PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, rrc->module_id, GNB_FLAG_YES, NOT_A_RNTI, 0, 0,rrc->module_id); + RB_INSERT(rrc_nr_ue_tree_s, &RC.nrrrc[rrc->module_id]->rrc_ue_head, ue_context_p); + + PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, rrc->module_id, GNB_FLAG_YES, ue_context_p->ue_id_rnti, 0, 0,rrc->module_id); gtpv1u_create_s1u_tunnel( ctxt.instance, &create_tunnel_req, From ab39b74ca165ae3527d1e8feb8443b123b2c0941 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 13 Mar 2020 10:19:24 +0100 Subject: [PATCH 090/553] bugfix in pusch dmrs reception --- openair1/PHY/NR_REFSIG/nr_dmrs_rx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c b/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c index f8ccdf0fdf..443e012ac0 100644 --- a/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c +++ b/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c @@ -59,7 +59,7 @@ int nr_pusch_dmrs_rx(PHY_VARS_gNB *gNB, unsigned short nb_pusch_rb, uint8_t dmrs_type) { - int8_t w; + int8_t w, nb_dmrs; short *mod_table; unsigned char idx=0; @@ -71,12 +71,12 @@ int nr_pusch_dmrs_rx(PHY_VARS_gNB *gNB, wt = (dmrs_type==pusch_dmrs_type1) ? wt1 : wt2; if (dmrs_type > 2) - LOG_E(PHY,"Bad PUSCH DMRS config type %d\n", dmrs_type); + LOG_E(PHY,"PUSCH DMRS config type %d not valid\n", dmrs_type+1); if ((p>=1000) && (p<((dmrs_type==pusch_dmrs_type1) ? 1008 : 1012))) { if (gNB->frame_parms.Ncp == NORMAL) { - - for (int i=0; i Date: Fri, 13 Mar 2020 12:55:49 +0100 Subject: [PATCH 091/553] ENDC path switch S1-U: Adding GTP-U tunnel related functionality at gNB --- openair2/RRC/LTE/rrc_eNB_GTPV1U.c | 50 +++++++++++++++++++++++++++++++ openair2/RRC/LTE/rrc_eNB_GTPV1U.h | 7 +++++ openair2/RRC/NR/nr_rrc_defs.h | 6 ++-- openair2/RRC/NR/rrc_gNB_nsa.c | 3 +- 4 files changed, 61 insertions(+), 5 deletions(-) diff --git a/openair2/RRC/LTE/rrc_eNB_GTPV1U.c b/openair2/RRC/LTE/rrc_eNB_GTPV1U.c index 749dff3ace..48beaaa343 100644 --- a/openair2/RRC/LTE/rrc_eNB_GTPV1U.c +++ b/openair2/RRC/LTE/rrc_eNB_GTPV1U.c @@ -93,6 +93,56 @@ rrc_eNB_process_GTPV1U_CREATE_TUNNEL_RESP( } } + +int +rrc_gNB_process_GTPV1U_CREATE_TUNNEL_RESP( + const protocol_ctxt_t *const ctxt_pP, + const gtpv1u_enb_create_tunnel_resp_t *const create_tunnel_resp_pP, + uint8_t *inde_list +) { + rnti_t rnti; + int i; + struct rrc_gNB_ue_context_s *ue_context_p = NULL; + + if (create_tunnel_resp_pP) { + LOG_D(RRC, PROTOCOL_RRC_CTXT_UE_FMT" RX CREATE_TUNNEL_RESP num tunnels %u \n", + PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP), + create_tunnel_resp_pP->num_tunnels); + rnti = create_tunnel_resp_pP->rnti; + ue_context_p = rrc_gNB_get_ue_context( + RC.nrrrc[ctxt_pP->module_id], + ctxt_pP->rnti); + + for (i = 0; i < create_tunnel_resp_pP->num_tunnels; i++) { + ue_context_p->ue_context.gnb_gtp_teid[inde_list[i]] = create_tunnel_resp_pP->enb_S1u_teid[i]; + ue_context_p->ue_context.gnb_gtp_addrs[inde_list[i]] = create_tunnel_resp_pP->enb_addr; + ue_context_p->ue_context.gnb_gtp_ebi[inde_list[i]] = create_tunnel_resp_pP->eps_bearer_id[i]; + LOG_I(RRC, PROTOCOL_RRC_CTXT_UE_FMT" rrc_eNB_process_GTPV1U_CREATE_TUNNEL_RESP tunnel (%u, %u) bearer UE context index %u, msg index %u, id %u, gtp addr len %d \n", + PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP), + create_tunnel_resp_pP->enb_S1u_teid[i], + ue_context_p->ue_context.gnb_gtp_teid[inde_list[i]], + inde_list[i], + i, + create_tunnel_resp_pP->eps_bearer_id[i], + create_tunnel_resp_pP->enb_addr.length); + } + + MSC_LOG_RX_MESSAGE( + MSC_RRC_ENB, + MSC_GTPU_ENB, + NULL,0, + MSC_AS_TIME_FMT" CREATE_TUNNEL_RESP RNTI %"PRIx16" ntuns %u ebid %u enb-s1u teid %u", + 0,0,rnti, + create_tunnel_resp_pP->num_tunnels, + ue_context_p->ue_context.gnb_gtp_ebi[0], + ue_context_p->ue_context.gnb_gtp_teid[0]); + (void)rnti; /* avoid gcc warning "set but not used" */ + return 0; + } else { + return -1; + } +} + //------------------------------------------------------------------------------ boolean_t gtpv_data_req( diff --git a/openair2/RRC/LTE/rrc_eNB_GTPV1U.h b/openair2/RRC/LTE/rrc_eNB_GTPV1U.h index 00c7490359..6318ed4927 100644 --- a/openair2/RRC/LTE/rrc_eNB_GTPV1U.h +++ b/openair2/RRC/LTE/rrc_eNB_GTPV1U.h @@ -43,6 +43,13 @@ rrc_eNB_process_GTPV1U_CREATE_TUNNEL_RESP( uint8_t *inde_list ); +int +rrc_gNB_process_GTPV1U_CREATE_TUNNEL_RESP( + const protocol_ctxt_t *const ctxt_pP, + const gtpv1u_enb_create_tunnel_resp_t *const create_tunnel_resp_pP, + uint8_t *inde_list +); + /*! \fn rrc_eNB_send_GTPV1U_ENB_DELETE_TUNNEL_REQ(module_id_t enb_mod_idP, const rrc_eNB_ue_context_t* const ue_context_pP) *\brief Send GTPV1U_ENB_DELETE_TUNNEL_REQ message to GTPV1U to destroy all UE-related tunnels. *\param module_id Instance ID of eNB. diff --git a/openair2/RRC/NR/nr_rrc_defs.h b/openair2/RRC/NR/nr_rrc_defs.h index db3d550684..ec50a7ae3e 100644 --- a/openair2/RRC/NR/nr_rrc_defs.h +++ b/openair2/RRC/NR/nr_rrc_defs.h @@ -326,9 +326,9 @@ typedef struct gNB_RRC_UE_s { uint8_t nb_release_of_e_rabs; e_rab_failed_t e_rabs_release_failed[S1AP_MAX_E_RAB]; // LG: For GTPV1 TUNNELS - uint32_t enb_gtp_teid[S1AP_MAX_E_RAB]; - transport_layer_addr_t enb_gtp_addrs[S1AP_MAX_E_RAB]; - rb_id_t enb_gtp_ebi[S1AP_MAX_E_RAB]; + uint32_t gnb_gtp_teid[S1AP_MAX_E_RAB]; + transport_layer_addr_t gnb_gtp_addrs[S1AP_MAX_E_RAB]; + rb_id_t gnb_gtp_ebi[S1AP_MAX_E_RAB]; #endif uint32_t ul_failure_timer; uint32_t ue_release_timer; diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c index 142f068467..caa724ae24 100644 --- a/openair2/RRC/NR/rrc_gNB_nsa.c +++ b/openair2/RRC/NR/rrc_gNB_nsa.c @@ -166,12 +166,11 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_ ctxt.instance, &create_tunnel_req, &create_tunnel_resp); - rrc_eNB_process_GTPV1U_CREATE_TUNNEL_RESP( + rrc_gNB_process_GTPV1U_CREATE_TUNNEL_RESP( &ctxt, &create_tunnel_resp, &inde_list[0]); X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).nb_e_rabs_admitted_tobeadded = m->nb_e_rabs_tobeadded; - for(int i=0; iue_context.nb_of_e_rabs; i++){ X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].e_rab_id = ue_context_p->ue_context.e_rab[i].param.e_rab_id; X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gtp_teid = create_tunnel_resp.enb_S1u_teid[i]; From abddce1dc7c536392f36890815f6a772e38744c2 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 13 Mar 2020 18:23:27 +0100 Subject: [PATCH 092/553] bugfix in computation of B --- openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c | 25 +++++++++++-------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c index a72a92a76d..dcaeebffa0 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c @@ -369,7 +369,10 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, if (harq_process->round == 0) { // This is a new packet, so compute quantities regarding segmentation - harq_process->B = A+24; + if (A > 3824) + harq_process->B = A+24; + else + harq_process->B = A+16; if (R<1024) Coderate = (float) R /(float) 1024; @@ -406,20 +409,20 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, } } - // [hna] Perform nr_segmenation with input and output set to NULL to calculate only (B, C, K, Z, F) - nr_segmentation(NULL, - NULL, - harq_process->B, - &harq_process->C, - &harq_process->K, - &harq_process->Z, // [hna] Z is Zc - &harq_process->F, - p_decParams->BG); + // [hna] Perform nr_segmenation with input and output set to NULL to calculate only (B, C, K, Z, F) + nr_segmentation(NULL, + NULL, + harq_process->B, + &harq_process->C, + &harq_process->K, + &harq_process->Z, // [hna] Z is Zc + &harq_process->F, + p_decParams->BG); #ifdef DEBUG_ULSCH_DECODING printf("ulsch decoding nr segmentation Z %d\n", harq_process->Z); if (!frame%100) - printf("K %d C %d Z %d nl %d \n", harq_process->K, harq_process->C, harq_process->Z, harq_process->Nl); + printf("K %d C %d Z %d \n", harq_process->K, harq_process->C, harq_process->Z); #endif } p_decParams->Z = harq_process->Z; From cb0b7369933bd2a11eeca0a2d33be8da3c05c723 Mon Sep 17 00:00:00 2001 From: matzakos Date: Sun, 15 Mar 2020 16:23:18 +0100 Subject: [PATCH 093/553] ENDC path switch S1-U: Modifications to avoid linking errors for lte-softmodem --- cmake_targets/CMakeLists.txt | 15 +++++++- openair2/RRC/LTE/rrc_eNB_GTPV1U.c | 49 ----------------------- openair2/RRC/NR/rrc_gNB_GTPV1U.c | 64 +++++++++++++++++++++++++++++++ openair2/RRC/NR/rrc_gNB_GTPV1U.h | 39 +++++++++++++++++++ 4 files changed, 117 insertions(+), 50 deletions(-) create mode 100644 openair2/RRC/NR/rrc_gNB_GTPV1U.c create mode 100644 openair2/RRC/NR/rrc_gNB_GTPV1U.h diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index 75b153f660..b1f6fb31d6 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -1880,6 +1880,19 @@ set (GTPV1U_SRC add_library(GTPV1U ${GTPV1U_SRC}) add_dependencies(GTPV1U rrc_flag) +#NR case +set (NR_GTPV1U_SRC + ${NR_RRC_DIR}/rrc_gNB_GTPV1U.c + ${RRC_DIR}/rrc_eNB_GTPV1U.c + ${GTPV1U_DIR}/nw-gtpv1u/src/NwGtpv1uTunnelEndPoint.c + ${GTPV1U_DIR}/nw-gtpv1u/src/NwGtpv1uTrxn.c + ${GTPV1U_DIR}/nw-gtpv1u/src/NwGtpv1uMsg.c + ${GTPV1U_DIR}/nw-gtpv1u/src/NwGtpv1u.c + ${GTPV1U_DIR}/gtpv1u_teid_pool.c +) +add_library(NR_GTPV1U ${NR_GTPV1U_SRC}) +add_dependencies(NR_GTPV1U rrc_flag) + set (MME_APP_SRC ${OPENAIR3_DIR}/MME_APP/mme_app.c ${OPENAIR3_DIR}/MME_APP/mme_config.c @@ -2597,7 +2610,7 @@ add_executable(nr-softmodem target_link_libraries (nr-softmodem -Wl,--start-group - UTIL HASHTABLE SCTP_CLIENT UDP SCHED_LIB SCHED_RU_LIB SCHED_NR_LIB PHY_NR PHY PHY_COMMON PHY_NR_COMMON PHY_RU LFDS GTPV1U SECU_CN SECU_OSA + UTIL HASHTABLE SCTP_CLIENT UDP SCHED_LIB SCHED_RU_LIB SCHED_NR_LIB PHY_NR PHY PHY_COMMON PHY_NR_COMMON PHY_RU LFDS NR_GTPV1U SECU_CN SECU_OSA ${ITTI_LIB} ${FLPT_MSG_LIB} ${ASYNC_IF_LIB} ${FLEXRAN_AGENT_LIB} LFDS7 ${MSC_LIB} ${RAL_LIB} ${NAS_UE_LIB} RRC_LIB NR_RRC_LIB S1AP_LIB S1AP_ENB L2 L2_LTE L2_NR MAC_NR_COMMON NFAPI_COMMON_LIB NFAPI_LIB NFAPI_VNF_LIB NFAPI_PNF_LIB NFAPI_USER_LIB X2AP_LIB X2AP_ENB F1AP_LIB F1AP M2AP_LIB M2AP_ENB M3AP_LIB M3AP_ENB ${PROTO_AGENT_LIB} ${FSPT_MSG_LIB} diff --git a/openair2/RRC/LTE/rrc_eNB_GTPV1U.c b/openair2/RRC/LTE/rrc_eNB_GTPV1U.c index 48beaaa343..add49f8987 100644 --- a/openair2/RRC/LTE/rrc_eNB_GTPV1U.c +++ b/openair2/RRC/LTE/rrc_eNB_GTPV1U.c @@ -94,55 +94,6 @@ rrc_eNB_process_GTPV1U_CREATE_TUNNEL_RESP( } -int -rrc_gNB_process_GTPV1U_CREATE_TUNNEL_RESP( - const protocol_ctxt_t *const ctxt_pP, - const gtpv1u_enb_create_tunnel_resp_t *const create_tunnel_resp_pP, - uint8_t *inde_list -) { - rnti_t rnti; - int i; - struct rrc_gNB_ue_context_s *ue_context_p = NULL; - - if (create_tunnel_resp_pP) { - LOG_D(RRC, PROTOCOL_RRC_CTXT_UE_FMT" RX CREATE_TUNNEL_RESP num tunnels %u \n", - PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP), - create_tunnel_resp_pP->num_tunnels); - rnti = create_tunnel_resp_pP->rnti; - ue_context_p = rrc_gNB_get_ue_context( - RC.nrrrc[ctxt_pP->module_id], - ctxt_pP->rnti); - - for (i = 0; i < create_tunnel_resp_pP->num_tunnels; i++) { - ue_context_p->ue_context.gnb_gtp_teid[inde_list[i]] = create_tunnel_resp_pP->enb_S1u_teid[i]; - ue_context_p->ue_context.gnb_gtp_addrs[inde_list[i]] = create_tunnel_resp_pP->enb_addr; - ue_context_p->ue_context.gnb_gtp_ebi[inde_list[i]] = create_tunnel_resp_pP->eps_bearer_id[i]; - LOG_I(RRC, PROTOCOL_RRC_CTXT_UE_FMT" rrc_eNB_process_GTPV1U_CREATE_TUNNEL_RESP tunnel (%u, %u) bearer UE context index %u, msg index %u, id %u, gtp addr len %d \n", - PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP), - create_tunnel_resp_pP->enb_S1u_teid[i], - ue_context_p->ue_context.gnb_gtp_teid[inde_list[i]], - inde_list[i], - i, - create_tunnel_resp_pP->eps_bearer_id[i], - create_tunnel_resp_pP->enb_addr.length); - } - - MSC_LOG_RX_MESSAGE( - MSC_RRC_ENB, - MSC_GTPU_ENB, - NULL,0, - MSC_AS_TIME_FMT" CREATE_TUNNEL_RESP RNTI %"PRIx16" ntuns %u ebid %u enb-s1u teid %u", - 0,0,rnti, - create_tunnel_resp_pP->num_tunnels, - ue_context_p->ue_context.gnb_gtp_ebi[0], - ue_context_p->ue_context.gnb_gtp_teid[0]); - (void)rnti; /* avoid gcc warning "set but not used" */ - return 0; - } else { - return -1; - } -} - //------------------------------------------------------------------------------ boolean_t gtpv_data_req( diff --git a/openair2/RRC/NR/rrc_gNB_GTPV1U.c b/openair2/RRC/NR/rrc_gNB_GTPV1U.c new file mode 100644 index 0000000000..32394cfcff --- /dev/null +++ b/openair2/RRC/NR/rrc_gNB_GTPV1U.c @@ -0,0 +1,64 @@ +# include "rrc_defs.h" +# include "rrc_extern.h" +# include "RRC/LTE/MESSAGES/asn1_msg.h" +# include "rrc_eNB_GTPV1U.h" +# include "rrc_eNB_UE_context.h" +# include "msc.h" + +//# if defined(ENABLE_ITTI) +# include "asn1_conversions.h" +# include "intertask_interface.h" +//#endif + +# include "common/ran_context.h" + +extern RAN_CONTEXT_t RC; + +int +rrc_gNB_process_GTPV1U_CREATE_TUNNEL_RESP( + const protocol_ctxt_t *const ctxt_pP, + const gtpv1u_enb_create_tunnel_resp_t *const create_tunnel_resp_pP, + uint8_t *inde_list +) { + rnti_t rnti; + int i; + struct rrc_gNB_ue_context_s *ue_context_p = NULL; + + if (create_tunnel_resp_pP) { + LOG_D(RRC, PROTOCOL_RRC_CTXT_UE_FMT" RX CREATE_TUNNEL_RESP num tunnels %u \n", + PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP), + create_tunnel_resp_pP->num_tunnels); + rnti = create_tunnel_resp_pP->rnti; + ue_context_p = rrc_gNB_get_ue_context( + RC.nrrrc[ctxt_pP->module_id], + ctxt_pP->rnti); + + for (i = 0; i < create_tunnel_resp_pP->num_tunnels; i++) { + ue_context_p->ue_context.gnb_gtp_teid[inde_list[i]] = create_tunnel_resp_pP->enb_S1u_teid[i]; + ue_context_p->ue_context.gnb_gtp_addrs[inde_list[i]] = create_tunnel_resp_pP->enb_addr; + ue_context_p->ue_context.gnb_gtp_ebi[inde_list[i]] = create_tunnel_resp_pP->eps_bearer_id[i]; + LOG_I(RRC, PROTOCOL_RRC_CTXT_UE_FMT" rrc_eNB_process_GTPV1U_CREATE_TUNNEL_RESP tunnel (%u, %u) bearer UE context index %u, msg index %u, id %u, gtp addr len %d \n", + PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP), + create_tunnel_resp_pP->enb_S1u_teid[i], + ue_context_p->ue_context.gnb_gtp_teid[inde_list[i]], + inde_list[i], + i, + create_tunnel_resp_pP->eps_bearer_id[i], + create_tunnel_resp_pP->enb_addr.length); + } + + MSC_LOG_RX_MESSAGE( + MSC_RRC_ENB, + MSC_GTPU_ENB, + NULL,0, + MSC_AS_TIME_FMT" CREATE_TUNNEL_RESP RNTI %"PRIx16" ntuns %u ebid %u enb-s1u teid %u", + 0,0,rnti, + create_tunnel_resp_pP->num_tunnels, + ue_context_p->ue_context.gnb_gtp_ebi[0], + ue_context_p->ue_context.gnb_gtp_teid[0]); + (void)rnti; /* avoid gcc warning "set but not used" */ + return 0; + } else { + return -1; + } +} diff --git a/openair2/RRC/NR/rrc_gNB_GTPV1U.h b/openair2/RRC/NR/rrc_gNB_GTPV1U.h new file mode 100644 index 0000000000..49fa0b6ac2 --- /dev/null +++ b/openair2/RRC/NR/rrc_gNB_GTPV1U.h @@ -0,0 +1,39 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file rrc_eNB_GTPV1U.h + * \brief rrc GTPV1U procedures for eNB + * \author Lionel GAUTHIER + * \version 1.0 + * \company Eurecom + * \email: lionel.gauthier@eurecom.fr + */ + +#ifndef RRC_GNB_GTPV1U_H_ +#define RRC_GNB_GTPV1U_H_ + + +int +rrc_gNB_process_GTPV1U_CREATE_TUNNEL_RESP( + const protocol_ctxt_t *const ctxt_pP, + const gtpv1u_enb_create_tunnel_resp_t *const create_tunnel_resp_pP, + uint8_t *inde_list +); From 9bbb12f7ae6dc90cd3adf06d7261e2cb981c8c38 Mon Sep 17 00:00:00 2001 From: Cedric Roux Date: Mon, 16 Mar 2020 09:37:40 +0100 Subject: [PATCH 094/553] nr-gnb: configure contention-free random access for the UE --- openair2/RRC/NR/rrc_gNB_reconfig.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/openair2/RRC/NR/rrc_gNB_reconfig.c b/openair2/RRC/NR/rrc_gNB_reconfig.c index baa771b716..fec40b185c 100644 --- a/openair2/RRC/NR/rrc_gNB_reconfig.c +++ b/openair2/RRC/NR/rrc_gNB_reconfig.c @@ -155,6 +155,26 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated = NULL; secondaryCellGroup->spCellConfig->reconfigurationWithSync->ext1 = NULL; + /* contention free ra */ + secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated = calloc(1,sizeof(struct NR_ReconfigurationWithSync__rach_ConfigDedicated)); + secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->present= NR_ReconfigurationWithSync__rach_ConfigDedicated_PR_uplink; + secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink= calloc(1,sizeof(struct NR_RACH_ConfigDedicated)); + secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra= calloc(1,sizeof(struct NR_CFRA)); + secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->ra_Prioritization= NULL; + secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions= calloc(1,sizeof(struct NR_CFRA__occasions)); + memcpy(&secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions->rach_ConfigGeneric, &servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric, sizeof(NR_RACH_ConfigGeneric_t)); + //secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions->ssb_perRACH_Occasion= calloc(1,sizeof(long)); + //*secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions->ssb_perRACH_Occasion = NR_CFRA__occasions__ssb_perRACH_Occasion_one; + secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions->ssb_perRACH_Occasion= NULL; + secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->resources.present = NR_CFRA__resources_PR_ssb; + secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->resources.choice.ssb = calloc(1,sizeof(struct NR_CFRA__resources__ssb)); + secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->resources.choice.ssb->ra_ssb_OccasionMaskIndex = 0; + struct NR_CFRA_SSB_Resource *ssbElem = calloc(1,sizeof(struct NR_CFRA_SSB_Resource)); + ssbElem->ssb = 0; + ssbElem->ra_PreambleIndex= 63; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->resources.choice.ssb->ssb_ResourceList.list,ssbElem); + secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->ext1 = NULL; + secondaryCellGroup->spCellConfig->rlf_TimersAndConstants = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->rlf_TimersAndConstants)); secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->present = NR_SetupRelease_RLF_TimersAndConstants_PR_setup; secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup)); From cbba3da30b1e0c99ec4b438963cd1d5a36abe760 Mon Sep 17 00:00:00 2001 From: matzakos Date: Mon, 16 Mar 2020 21:20:00 +0100 Subject: [PATCH 095/553] ENDC path switch S1-U: Remove warnings --- openair2/RRC/LTE/rrc_eNB_S1AP.c | 2 -- openair2/RRC/NR/rrc_gNB_GTPV1U.c | 1 + openair2/RRC/NR/rrc_gNB_UE_context.h | 2 +- openair2/X2AP/x2ap_eNB_generate_messages.c | 8 -------- openair2/X2AP/x2ap_eNB_handler.c | 2 -- 5 files changed, 2 insertions(+), 13 deletions(-) diff --git a/openair2/RRC/LTE/rrc_eNB_S1AP.c b/openair2/RRC/LTE/rrc_eNB_S1AP.c index d2e3d4999f..7dd9cd2171 100644 --- a/openair2/RRC/LTE/rrc_eNB_S1AP.c +++ b/openair2/RRC/LTE/rrc_eNB_S1AP.c @@ -2291,8 +2291,6 @@ int rrc_eNB_send_E_RAB_Modification_Indication(const protocol_ctxt_t *const ctxt int e_rab = 0; int e_rab_modify_index = 0; int e_rab_notmodify_index = 0; - rrc_ue_s1ap_ids_t *rrc_ue_s1ap_ids_p = NULL; - hashtable_rc_t h_rc; uint8_t inde_list[ue_context_pP->ue_context.nb_of_e_rabs]; memset(inde_list, 0, ue_context_pP->ue_context.nb_of_e_rabs*sizeof(uint8_t)); diff --git a/openair2/RRC/NR/rrc_gNB_GTPV1U.c b/openair2/RRC/NR/rrc_gNB_GTPV1U.c index 32394cfcff..5fee63c4c2 100644 --- a/openair2/RRC/NR/rrc_gNB_GTPV1U.c +++ b/openair2/RRC/NR/rrc_gNB_GTPV1U.c @@ -4,6 +4,7 @@ # include "rrc_eNB_GTPV1U.h" # include "rrc_eNB_UE_context.h" # include "msc.h" +# include "openair2/RRC/NR/rrc_gNB_UE_context.h" //# if defined(ENABLE_ITTI) # include "asn1_conversions.h" diff --git a/openair2/RRC/NR/rrc_gNB_UE_context.h b/openair2/RRC/NR/rrc_gNB_UE_context.h index 4681cabb8f..5c9c716181 100644 --- a/openair2/RRC/NR/rrc_gNB_UE_context.h +++ b/openair2/RRC/NR/rrc_gNB_UE_context.h @@ -58,7 +58,7 @@ int rrc_gNB_compare_ue_rnti_id( struct rrc_gNB_ue_context_s* c2_pP ); -RB_PROTOTYPE(rrc_ue_tree_s, rrc_gNB_ue_context_s, entries, rrc_gNB_compare_ue_rnti_id); +RB_PROTOTYPE(rrc_nr_ue_tree_s, rrc_gNB_ue_context_s, entries, rrc_gNB_compare_ue_rnti_id); struct rrc_gNB_ue_context_s* rrc_gNB_allocate_new_UE_context( diff --git a/openair2/X2AP/x2ap_eNB_generate_messages.c b/openair2/X2AP/x2ap_eNB_generate_messages.c index c5cc84c21c..c44d608883 100644 --- a/openair2/X2AP/x2ap_eNB_generate_messages.c +++ b/openair2/X2AP/x2ap_eNB_generate_messages.c @@ -1516,8 +1516,6 @@ int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request( int uEaggregateMaximumBitRateDownlink = 100000000; int uEaggregateMaximumBitRateUplink = 100000000; int e_rabs_tobeadded = 1; - int e_RAB_ID = 1; - int drb_ID = 2; long int pDCPatSgNB = X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present; long int mCGresources = X2AP_EN_DC_ResourceConfiguration__mCGresources_not_present; long int sCGresources = X2AP_EN_DC_ResourceConfiguration__sCGresources_not_present; @@ -1691,13 +1689,7 @@ int x2ap_gNB_generate_ENDC_x2_SgNB_addition_request_ACK( x2ap_eNB_instance_t *in // Currently hardcoded (dummy) values filling the fields of SgNB_addition_request message. To be substituted // with values coming from RRC. - uint16_t nRencryptionAlgorithms = 0; - uint16_t nRintegrityProtectionAlgorithms = 0; - uint8_t SgNBSecurityKey[32] = { 0 }; - int uEaggregateMaximumBitRateDownlink = 100000000; - int uEaggregateMaximumBitRateUplink = 100000000; int e_rabs_admitted_tobeadded = 1; - int e_RAB_ID = 1; long int pDCPatSgNB = X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present; long int mCGresources = X2AP_EN_DC_ResourceConfiguration__mCGresources_not_present; long int sCGresources = X2AP_EN_DC_ResourceConfiguration__sCGresources_not_present; diff --git a/openair2/X2AP/x2ap_eNB_handler.c b/openair2/X2AP/x2ap_eNB_handler.c index 3dfc297ed6..e950fa76fd 100644 --- a/openair2/X2AP/x2ap_eNB_handler.c +++ b/openair2/X2AP/x2ap_eNB_handler.c @@ -1771,7 +1771,6 @@ int x2ap_gNB_handle_ENDC_sGNB_addition_request (instance_t instance, X2AP_FIND_PROTOCOLIE_BY_ID(X2AP_SgNBAdditionRequest_IEs_t, ie, x2SgNBAdditionRequest, X2AP_ProtocolIE_ID_id_MeNBtoSgNBContainer, true); - X2AP_MeNBtoSgNBContainer_t *container = &ie->value.choice.MeNBtoSgNBContainer; if (ie->value.choice.MeNBtoSgNBContainer.size > 8192 ) // TODO: this is the size of rrc_buffer in struct x2ap_handover_req_s { printf("%s:%d: fatal: buffer too big\n", __FILE__, __LINE__); abort(); } @@ -1943,7 +1942,6 @@ int x2ap_gNB_handle_ENDC_sGNB_reconfiguration_complete (instance_t instance, x2ap_eNB_instance_t *instance_p; x2ap_eNB_data_t *x2ap_eNB_data; MessageDef *msg; - int ue_id; DevAssert (pdu != NULL); x2SgNBReconfigurationComplete = &pdu->choice.initiatingMessage.value.choice.SgNBReconfigurationComplete; From 5ef2af1cce6bd45b734f551ef25a6f15eb11933c Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Tue, 17 Mar 2020 16:27:08 +0100 Subject: [PATCH 096/553] minor changes --- openair1/PHY/MODULATION/modulation_UE.h | 6 ++++++ openair1/PHY/MODULATION/slot_fep_nr.c | 8 ++++---- openair1/PHY/NR_TRANSPORT/nr_ulsch.c | 9 ++++----- openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c | 11 +++-------- openair1/PHY/NR_UE_TRANSPORT/dci_nr.c | 2 +- openair1/SCHED_NR/phy_procedures_nr_gNB.c | 3 +-- openair1/SIMULATION/NR_PHY/nr_unitary_defs.h | 2 +- openair1/SIMULATION/NR_PHY/ulsim.c | 2 ++ 8 files changed, 22 insertions(+), 21 deletions(-) diff --git a/openair1/PHY/MODULATION/modulation_UE.h b/openair1/PHY/MODULATION/modulation_UE.h index 1199a91baa..228299095f 100644 --- a/openair1/PHY/MODULATION/modulation_UE.h +++ b/openair1/PHY/MODULATION/modulation_UE.h @@ -54,6 +54,12 @@ int nr_slot_fep(PHY_VARS_NR_UE *phy_vars_ue, int sample_offset, int no_prefix); +int nr_slot_fep_init_sync(PHY_VARS_NR_UE *ue, + unsigned char symbol, + unsigned char Ns, + int sample_offset, + int no_prefix); + int slot_fep_mbsfn(PHY_VARS_UE *phy_vars_ue, unsigned char l, int subframe, diff --git a/openair1/PHY/MODULATION/slot_fep_nr.c b/openair1/PHY/MODULATION/slot_fep_nr.c index a15b12ed4e..01ea82d92a 100644 --- a/openair1/PHY/MODULATION/slot_fep_nr.c +++ b/openair1/PHY/MODULATION/slot_fep_nr.c @@ -211,10 +211,10 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue, } int nr_slot_fep_init_sync(PHY_VARS_NR_UE *ue, - unsigned char symbol, - unsigned char Ns, - int sample_offset, - int no_prefix) + unsigned char symbol, + unsigned char Ns, + int sample_offset, + int no_prefix) { NR_DL_FRAME_PARMS *frame_parms = &ue->frame_parms; NR_UE_COMMON *common_vars = &ue->common_vars; diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch.c index 6764e6e125..8b35ca2e0f 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch.c @@ -83,11 +83,10 @@ void nr_fill_ulsch(PHY_VARS_gNB *gNB, } void nr_ulsch_unscrambling(int16_t* llr, - uint32_t size, - uint8_t q, - uint32_t Nid, - uint32_t n_RNTI) -{ + uint32_t size, + uint8_t q, + uint32_t Nid, + uint32_t n_RNTI) { uint8_t reset; uint32_t x1, x2, s=0; diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c index 0478d892d5..add5587ea4 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c @@ -329,7 +329,6 @@ void nr_ulsch_scale_channel(int **ul_ch_estimates_ext, nb_rb = (2*nb_rb)/3; } - for (rb=0;rb=(7-frame_parms->Ncp)) ? symbol-(7-frame_parms->Ncp) : symbol; - for (aatx=0; aatxnb_antenna_ports_gNB; aatx++) + for (aatx=0; aatxnb_antenna_ports_gNB; aatx++) { for (aarx=0; aarxnb_antennas_rx; aarx++) { //clear average level avg128U = vdupq_n_s32(0); @@ -446,8 +445,7 @@ void nr_ulsch_channel_level(int **ul_ch_estimates_ext, ((int32_t*)&avg128U)[2] + ((int32_t*)&avg128U)[3] ) / (nb_rb*nre); } - - + } #endif } @@ -666,7 +664,6 @@ void nr_ulsch_channel_compensation(int **rxdataF_ext, if (rho) { - for (aarx=0; aarxnb_antennas_rx; aarx++) { rho128 = (__m128i *)&rho[aarx][symbol*frame_parms->N_RB_UL*12]; ul_ch128 = (__m128i *)&ul_ch_estimates_ext[aarx][symbol*frame_parms->N_RB_UL*12]; @@ -748,7 +745,6 @@ void nr_ulsch_channel_compensation(int **rxdataF_ext, #elif defined(__arm__) - unsigned short rb; unsigned char aatx,aarx,symbol_mod,is_dmrs_symbol=0; @@ -1017,7 +1013,6 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, nb_re_pusch = rel15_ul->rb_size * NR_NB_SC_PER_RB; } - //---------------------------------------------------------- //--------------------- Channel estimation --------------------- //---------------------------------------------------------- @@ -1071,7 +1066,7 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, gNB->pusch_vars[UE_id]->log2_maxh = (log2_approx(avgs)/2)+1; gNB->pusch_vars[UE_id]->cl_done = 1; - } + } nr_ulsch_channel_compensation(gNB->pusch_vars[UE_id]->rxdataF_ext, gNB->pusch_vars[UE_id]->ul_ch_estimates_ext, diff --git a/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c b/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c index 3a594031bd..6d98031843 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c +++ b/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c @@ -702,7 +702,7 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue, for (aarx = 0; aarx < frame_parms->nb_antennas_rx; aarx++) avgs = cmax(avgs, avgP[aarx]); - log2_maxh = (log2_approx(avgs) / 2) + 5; //+frame_parms->nb_antennas_rx; + log2_maxh = (log2_approx(avgs) / 2) + 5; //+frame_parms->nb_antennas_rx; #ifdef UE_DEBUG_TRACE LOG_D(PHY,"slot %d: pdcch log2_maxh = %d (%d,%d)\n",slot,log2_maxh,avgP[0],avgs); #endif diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index 0a8a34e0da..14b7d2ebae 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -224,7 +224,7 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH number_symbols = pusch_pdu->nr_of_symbols; for (l = start_symbol; l < start_symbol + number_symbols; l++) - number_dmrs_symbols += ((pusch_pdu->ul_dmrs_symb_pos)>>l)&0x01;; + number_dmrs_symbols += ((pusch_pdu->ul_dmrs_symb_pos)>>l)&0x01; if (nodata_dmrs) nb_re_dmrs = 12*number_dmrs_symbols; @@ -238,7 +238,6 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH pusch_pdu->qam_mod_order, pusch_pdu->nrOfLayers); - //---------------------------------------------------------- //------------------- ULSCH unscrambling ------------------- //---------------------------------------------------------- diff --git a/openair1/SIMULATION/NR_PHY/nr_unitary_defs.h b/openair1/SIMULATION/NR_PHY/nr_unitary_defs.h index 6d07576d85..7a465e0ea3 100644 --- a/openair1/SIMULATION/NR_PHY/nr_unitary_defs.h +++ b/openair1/SIMULATION/NR_PHY/nr_unitary_defs.h @@ -161,7 +161,7 @@ void fill_scc(NR_ServingCellConfigCommon_t *scc,uint64_t *ssb_bitmap,int N_RB_DL *scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rsrp_ThresholdSSB=19; scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.present=NR_RACH_ConfigCommon__prach_RootSequenceIndex_PR_l139; scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.choice.l139=0; - scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig=NR_RACH_ConfigCommon__restrictedSetConfig_unrestrictedSet,TYPE_INT64; + scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig=NR_RACH_ConfigCommon__restrictedSetConfig_unrestrictedSet; *scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->k2=2; scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->mappingType=NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB; scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->startSymbolAndLength=55; diff --git a/openair1/SIMULATION/NR_PHY/ulsim.c b/openair1/SIMULATION/NR_PHY/ulsim.c index 1c0ce8acf3..b3a7164378 100644 --- a/openair1/SIMULATION/NR_PHY/ulsim.c +++ b/openair1/SIMULATION/NR_PHY/ulsim.c @@ -46,12 +46,14 @@ #include "PHY/NR_TRANSPORT/nr_ulsch.h" #include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" #include "PHY/TOOLS/tools_defs.h" +#include "SCHED_NR/fapi_nr_l1.h" #include "SCHED_NR/sched_nr.h" #include "SCHED_NR_UE/defs.h" #include "SCHED_NR_UE/fapi_nr_ue_l1.h" #include "openair1/SIMULATION/TOOLS/sim.h" #include "openair1/SIMULATION/RF/rf.h" #include "openair1/SIMULATION/NR_PHY/nr_unitary_defs.h" +#include "openair2/RRC/NR/MESSAGES/asn1_msg.h" //#include "openair1/SIMULATION/NR_PHY/nr_dummy_functions.c" #include "LAYER2/NR_MAC_UE/mac_proto.h" #include "LAYER2/NR_MAC_gNB/mac_proto.h" From f508f310cc37793ecb6a7dcc2770bb97be742ba3 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 20 Mar 2020 14:24:40 +0100 Subject: [PATCH 097/553] fix in rbs extract for dmrs --- openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c index add5587ea4..a287abc60d 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c @@ -238,7 +238,8 @@ void nr_ulsch_extract_rbs_single(int **rxdataF, uint32_t ul_ch0_index = 0; uint8_t k_prime; uint16_t n=0; - + uint8_t delta = 0; + uint8_t is_dmrs_re; int16_t *rxF,*rxF_ext; int *ul_ch0,*ul_ch0_ext; @@ -271,7 +272,13 @@ void nr_ulsch_extract_rbs_single(int **rxdataF, printf("re = %d, symbol = %d\n", re, symbol); #endif - if ( dmrs_symbol != symbol ) { + if (symbol == dmrs_symbol) + is_dmrs_re = (re == get_dmrs_freq_idx_ul(n, k_prime, delta, pusch_pdu->dmrs_config_type)); + else + is_dmrs_re = 0; + + + if ( is_dmrs_re == 0 ) { rxF_ext[rxF_ext_index] = (rxF[ ((start_re + re)*2) % (frame_parms->ofdm_symbol_size*2)]); rxF_ext[rxF_ext_index + 1] = (rxF[(((start_re + re)*2) + 1) % (frame_parms->ofdm_symbol_size*2)]); From f895c4d929a2e323e0e56f59fbbb1377236d5a40 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Fri, 20 Mar 2020 22:48:09 +0100 Subject: [PATCH 098/553] ENDC path switch S1-U: Bugfixes at eNB side. Problem at S1AP E-RAB-Modification-Indication message encoding to be resolved --- openair2/RRC/LTE/rrc_eNB.c | 50 ++++++- openair2/RRC/LTE/rrc_eNB_endc.c | 45 ++++++ openair3/S1AP/s1ap_eNB_encoder.c | 9 +- openair3/S1AP/s1ap_eNB_nas_procedures.c | 186 +++++++++++++++++++++++- 4 files changed, 276 insertions(+), 14 deletions(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index c6a6440c87..51336afbd4 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -3154,6 +3154,7 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t MeasId5->reportConfigId = 6; ASN_SEQUENCE_ADD(&MeasId_list->list, MeasId5); +//ue_context_pP->ue_context.does_nr=0; if (ue_context_pP->ue_context.does_nr) { MeasId6 = calloc(1, sizeof(LTE_MeasIdToAddMod_t)); if (MeasId6 == NULL) exit(1); @@ -3217,7 +3218,7 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t if (MeasObj2 == NULL) exit(1); MeasObj2->measObjectId = 2; MeasObj2->measObject.present = LTE_MeasObjectToAddMod__measObject_PR_measObjectNR_r15; - MeasObj2->measObject.choice.measObjectNR_r15.carrierFreq_r15 = 642256; //634000; //(634000 = 3.51GHz) (640000 = 3.6GHz) (641272 = 3619.08MHz = 3600 + 30/1000*106*12/2) (642256 is for 3.6GHz and absoluteFrequencySSB = 642016) + MeasObj2->measObject.choice.measObjectNR_r15.carrierFreq_r15 = 641272; //642208; //642208 is for SSB at ptA + 82 RBs with ptA at 3600MHz //642256; //634000; //(634000 = 3.51GHz) (640000 = 3.6GHz) (641272 = 3619.08MHz = 3600 + 30/1000*106*12/2) (642256 is for 3.6GHz and absoluteFrequencySSB = 642016) MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.periodicityAndOffset_r15.present = LTE_MTC_SSB_NR_r15__periodicityAndOffset_r15_PR_sf20_r15; MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.periodicityAndOffset_r15.choice.sf20_r15 = 0; MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.ssb_Duration_r15 = LTE_MTC_SSB_NR_r15__ssb_Duration_r15_sf4; @@ -3360,13 +3361,13 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.present = LTE_ReportConfigInterRAT__triggerType_PR_event; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.present = LTE_ReportConfigInterRAT__triggerType__event__eventId_PR_eventB1_NR_r15; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.b1_ThresholdNR_r15.present = LTE_ThresholdNR_r15_PR_nr_RSRP_r15; - ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.b1_ThresholdNR_r15.choice.nr_RSRP_r15 = 46; + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.b1_ThresholdNR_r15.choice.nr_RSRP_r15 = 0; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.reportOnLeave_r15 = FALSE; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.hysteresis = 2; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.timeToTrigger = LTE_TimeToTrigger_ms80; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.maxReportCells = 4; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.reportInterval = LTE_ReportInterval_ms120; - ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.reportAmount = LTE_ReportConfigInterRAT__reportAmount_infinity; + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.reportAmount = LTE_ReportConfigInterRAT__reportAmount_r1; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7 = calloc(1, sizeof(struct LTE_ReportConfigInterRAT__ext7)); if (ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7 == NULL) exit(1); ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15 = calloc(1, sizeof(struct LTE_ReportQuantityNR_r15)); @@ -4292,6 +4293,16 @@ rrc_eNB_generate_RRCConnectionReconfiguration_SCell( return(0); } +static volatile int start_nr; +static void *xx(void *_) +{ + while (1) { + getchar(); + start_nr = 1; + printf("start nr\n"); + } + return 0; +} //----------------------------------------------------------------------------- void @@ -4311,6 +4322,15 @@ rrc_eNB_process_MeasurementReport( T(T_ENB_RRC_MEASUREMENT_REPORT, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame), T_INT(ctxt_pP->subframe), T_INT(ctxt_pP->rnti)); +{ +static int conf = 0; +if (!conf) { + pthread_t t; + pthread_create(&t, NULL, xx, NULL); + conf = 1; +} +} + if (measResults2 == NULL ) return; @@ -4321,6 +4341,7 @@ rrc_eNB_process_MeasurementReport( ue_context_pP->ue_context.measResults->measId=measResults2->measId; +printf("meas %d\n", (int)measResults2->measId); switch (measResults2->measId) { case 1: LOG_D(RRC,"Periodic report at frame %d and subframe %d \n", ctxt_pP->frame, ctxt_pP->subframe); @@ -4366,7 +4387,11 @@ rrc_eNB_process_MeasurementReport( /* TODO: improve NR triggering */ if (measResults2->measId == 7) { - if (ue_context_pP->ue_context.Status != RRC_NR_NSA) { +// if (start_nr) { +printf("nr\n"); +static int gonr = 0; + if (!gonr && ue_context_pP->ue_context.Status != RRC_NR_NSA) { +gonr=1; MessageDef *msg; ue_context_pP->ue_context.Status = RRC_NR_NSA; @@ -4382,6 +4407,14 @@ rrc_eNB_process_MeasurementReport( memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr, &ue_context_pP->ue_context.e_rab[e_rab].param.sgw_addr, sizeof(transport_layer_addr_t)); + LOG_I(RRC,"x2u tunnel: index %d target enb ip %d.%d.%d.%d length %d gtp teid %u\n", + i, + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr.buffer[0], + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr.buffer[1], + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr.buffer[2], + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr.buffer[3], + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr.length, + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].gtp_teid); } LOG_I(RRC, "[eNB %d] frame %d subframe %d: UE rnti %x switching to NSA mode\n", @@ -8509,6 +8542,14 @@ void rrc_eNB_process_AdditionResponseInformation(const module_id_t enb_mod_idP, printf("\n"); } +{ +int i; +int len = m->rrc_buffer_size; +unsigned char *buffer = (unsigned char*)m->rrc_buffer; +printf("xxx: (len %d): ", m->rrc_buffer_size); +for (i = 0; irnti); rrc_data_req(&ctxt, DCCH, diff --git a/openair2/RRC/LTE/rrc_eNB_endc.c b/openair2/RRC/LTE/rrc_eNB_endc.c index d6fb910507..14c46ea79d 100644 --- a/openair2/RRC/LTE/rrc_eNB_endc.c +++ b/openair2/RRC/LTE/rrc_eNB_endc.c @@ -35,6 +35,39 @@ extern RAN_CONTEXT_t RC; extern mui_t rrc_eNB_mui; +static int generate_release_drb1(unsigned char *nr1_buf, int nr1_buf_size) +{ + NR_RadioBearerConfig_t r; + NR_DRB_ToReleaseList_t l; + NR_DRB_Identity_t id; + asn_enc_rval_t enc_rval; + + memset(&r, 0, sizeof(r)); + memset(&l, 0, sizeof(l)); + memset(&id, 0, sizeof(id)); + + id = 1; + + r.drb_ToReleaseList = &l; + + ASN_SEQUENCE_ADD(&l.list, &id); + + enc_rval = uper_encode_to_buffer(&asn_DEF_NR_RadioBearerConfig, + NULL, + &r, + nr1_buf, + nr1_buf_size); +{ +int len = (enc_rval.encoded + 7) / 8; +int i; +printf("generate_release_drb1: len = %d (encoded %d)\n", len, enc_rval.encoded); +for (i = 0; i < len; i++) printf(" %2.2x", nr1_buf[i]); +printf("\n"); +} + + return (enc_rval.encoded + 7) / 8; +} + int rrc_eNB_generate_RRCConnectionReconfiguration_endc(protocol_ctxt_t *ctxt, rrc_eNB_ue_context_t *ue_context, unsigned char *buffer, @@ -130,10 +163,12 @@ int rrc_eNB_generate_RRCConnectionReconfiguration_endc(protocol_ctxt_t *ctxt, mac.choice.explicitValue.timeAlignmentTimerDedicated = LTE_TimeAlignmentTimer_sf10240; mac.choice.explicitValue.ext4 = &mac_ext4; +#if 0 mac_ext4.dualConnectivityPHR = &dc_phr; dc_phr.present = LTE_MAC_MainConfig__ext4__dualConnectivityPHR_PR_setup; dc_phr.choice.setup.phr_ModeOtherCG_r12 = LTE_MAC_MainConfig__ext4__dualConnectivityPHR__setup__phr_ModeOtherCG_r12_virtual; +#endif /* NR config */ struct LTE_RRCConnectionReconfiguration_v890_IEs cr_890; @@ -194,6 +229,7 @@ int rrc_eNB_generate_RRCConnectionReconfiguration_endc(protocol_ctxt_t *ctxt, long sk_counter = 0; cr_1510.sk_Counter_r15 = &sk_counter; +#if 1 OCTET_STRING_t dummy_nr1_conf; unsigned char nr1_buf[4] = { 0, 0, 0, 0 }; @@ -216,6 +252,15 @@ int rrc_eNB_generate_RRCConnectionReconfiguration_endc(protocol_ctxt_t *ctxt, } #endif +#else + OCTET_STRING_t nr1_conf; + unsigned char nr1_buf[1024]; + int nr1_size; + nr1_size = generate_release_drb1(nr1_buf, 1024); + cr_1510.nr_RadioBearerConfig1_r15 = &nr1_conf; + nr1_conf.buf = nr1_buf; + nr1_conf.size = nr1_size; +#endif #if 0 OCTET_STRING_t nr2_conf; diff --git a/openair3/S1AP/s1ap_eNB_encoder.c b/openair3/S1AP/s1ap_eNB_encoder.c index 0cd46214fc..86536ac525 100644 --- a/openair3/S1AP/s1ap_eNB_encoder.c +++ b/openair3/S1AP/s1ap_eNB_encoder.c @@ -118,15 +118,20 @@ int s1ap_eNB_encode_initiating(S1AP_S1AP_PDU_t *pdu, free(res.buffer); break; + case S1AP_ProcedureCode_id_E_RABModificationIndication: + res = asn_encode_to_new_buffer(NULL, ATS_CANONICAL_XER, &asn_DEF_S1AP_S1AP_PDU, pdu); + free(res.buffer); + break; + default: S1AP_DEBUG("Unknown procedure ID (%d) for initiating message\n", (int)pdu->choice.initiatingMessage.procedureCode); return -1; } - if (asn1_xer_print) { + //if (asn1_xer_print) { xer_fprint(stdout, &asn_DEF_S1AP_S1AP_PDU, (void *)pdu); - } + //} memset(&res, 0, sizeof(res)); res = asn_encode_to_new_buffer(NULL, ATS_ALIGNED_CANONICAL_PER, &asn_DEF_S1AP_S1AP_PDU, pdu); diff --git a/openair3/S1AP/s1ap_eNB_nas_procedures.c b/openair3/S1AP/s1ap_eNB_nas_procedures.c index 4877609754..1fb8a47d97 100644 --- a/openair3/S1AP/s1ap_eNB_nas_procedures.c +++ b/openair3/S1AP/s1ap_eNB_nas_procedures.c @@ -1626,7 +1626,7 @@ int s1ap_eNB_path_switch_req(instance_t instance, /* * eNB generate a S1 E_RAB Modification Indication towards MME */ -int s1ap_eNB_generate_E_RAB_Modification_Indication( +/*int s1ap_eNB_generate_E_RAB_Modification_Indication( instance_t instance, s1ap_e_rab_modification_ind_t *e_rab_modification_ind) //----------------------------------------------------------------------------- @@ -1655,14 +1655,22 @@ int s1ap_eNB_generate_E_RAB_Modification_Indication( uint32_t CSG_id = 0; - /* Prepare the S1AP message to encode */ + if ((ue_context_p = s1ap_eNB_get_ue_context(s1ap_eNB_instance_p, + e_rab_modification_ind->eNB_ue_s1ap_id)) == NULL) { + // The context for this eNB ue s1ap id doesn't exist in the map of eNB UEs + S1AP_WARN("Failed to find ue context associated with eNB ue s1ap id: 0x%06x\n", + e_rab_modification_ind->eNB_ue_s1ap_id); + return -1; + } + + // Prepare the S1AP message to encode memset(&pdu, 0, sizeof(pdu)); pdu.present = S1AP_S1AP_PDU_PR_initiatingMessage; pdu.choice.initiatingMessage.procedureCode = S1AP_ProcedureCode_id_E_RABModificationIndication; pdu.choice.initiatingMessage.criticality = S1AP_Criticality_reject; pdu.choice.initiatingMessage.value.present = S1AP_InitiatingMessage__value_PR_E_RABModificationIndication; out = &pdu.choice.initiatingMessage.value.choice.E_RABModificationIndication; - /* mandatory */ + // mandatory ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t)); ie->id = S1AP_ProtocolIE_ID_id_MME_UE_S1AP_ID; ie->criticality = S1AP_Criticality_reject; @@ -1738,8 +1746,12 @@ int s1ap_eNB_generate_E_RAB_Modification_Indication( ASN_SEQUENCE_ADD(&ie->value.choice.E_RABNotToBeModifiedListBearerModInd.list, E_RAB_NotToBeModifiedItem_BearerModInd_IEs); } } - else - ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_NOTHING; + else{ + ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_E_RABNotToBeModifiedListBearerModInd; + ie->value.choice.E_RABNotToBeModifiedListBearerModInd.list.size = 0; + } + + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); @@ -1753,12 +1765,170 @@ int s1ap_eNB_generate_E_RAB_Modification_Indication( if (s1ap_eNB_encode_pdu(&pdu, &buffer, &len) < 0) { - S1AP_ERROR("Failed to encode S1 setup request\n"); + S1AP_ERROR("Failed to encode S1 E-RAB modification indication \n"); return -1; } - /* Non UE-Associated signalling -> stream = 0 */ - s1ap_eNB_itti_send_sctp_data_req(s1ap_eNB_instance_p->instance, ue_context_p->mme_ref->assoc_id, buffer, len, 0); + // Non UE-Associated signalling -> stream = 0 + S1AP_INFO("Size of encoded message: %d \n", len); + s1ap_eNB_itti_send_sctp_data_req(s1ap_eNB_instance_p->instance, + ue_context_p->mme_ref->assoc_id, buffer, + len, ue_context_p->tx_stream); + +//s1ap_eNB_itti_send_sctp_data_req(s1ap_eNB_instance_p->instance, ue_context_p->mme_ref->assoc_id, buffer, len, 0); + return ret; +}*/ + +int s1ap_eNB_generate_E_RAB_Modification_Indication( + instance_t instance, + s1ap_e_rab_modification_ind_t *e_rab_modification_ind) +//----------------------------------------------------------------------------- +{ + struct s1ap_eNB_ue_context_s *ue_context_p = NULL; + S1AP_S1AP_PDU_t pdu; + S1AP_E_RABModificationIndication_t *out = NULL; + S1AP_E_RABModificationIndicationIEs_t *ie = NULL; + S1AP_E_RABToBeModifiedItemBearerModInd_t *E_RAB_ToBeModifiedItem_BearerModInd = NULL; + S1AP_E_RABToBeModifiedItemBearerModIndIEs_t *E_RAB_ToBeModifiedItem_BearerModInd_IEs = NULL; + + S1AP_E_RABNotToBeModifiedItemBearerModInd_t *E_RAB_NotToBeModifiedItem_BearerModInd = NULL; + S1AP_E_RABNotToBeModifiedItemBearerModIndIEs_t *E_RAB_NotToBeModifiedItem_BearerModInd_IEs = NULL; + + + s1ap_eNB_instance_t *s1ap_eNB_instance_p = NULL; + s1ap_eNB_instance_p = s1ap_eNB_get_instance(instance); + uint8_t *buffer = NULL; + uint32_t len = 0; + int ret = 0; + DevAssert(s1ap_eNB_instance_p != NULL); + DevAssert(e_rab_modification_ind != NULL); + + int num_e_rabs_tobemodified = e_rab_modification_ind->nb_of_e_rabs_tobemodified; + int num_e_rabs_nottobemodified = e_rab_modification_ind->nb_of_e_rabs_nottobemodified; + + uint16_t CSG_id = 0; + + if ((ue_context_p = s1ap_eNB_get_ue_context(s1ap_eNB_instance_p, + e_rab_modification_ind->eNB_ue_s1ap_id)) == NULL) { + // The context for this eNB ue s1ap id doesn't exist in the map of eNB UEs + S1AP_WARN("Failed to find ue context associated with eNB ue s1ap id: 0x%06x\n", + e_rab_modification_ind->eNB_ue_s1ap_id); + return -1; + } + + // Prepare the S1AP message to encode + memset(&pdu, 0, sizeof(pdu)); + pdu.present = S1AP_S1AP_PDU_PR_initiatingMessage; + pdu.choice.initiatingMessage.procedureCode = S1AP_ProcedureCode_id_E_RABModificationIndication; + pdu.choice.initiatingMessage.criticality = S1AP_Criticality_reject; + pdu.choice.initiatingMessage.value.present = S1AP_InitiatingMessage__value_PR_E_RABModificationIndication; + out = &pdu.choice.initiatingMessage.value.choice.E_RABModificationIndication; + /* mandatory */ + ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t)); + ie->id = S1AP_ProtocolIE_ID_id_MME_UE_S1AP_ID; + ie->criticality = S1AP_Criticality_reject; + ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_MME_UE_S1AP_ID; + ie->value.choice.MME_UE_S1AP_ID = e_rab_modification_ind->mme_ue_s1ap_id; + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t)); + ie->id = S1AP_ProtocolIE_ID_id_eNB_UE_S1AP_ID; + ie->criticality = S1AP_Criticality_reject; + ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_ENB_UE_S1AP_ID; + ie->value.choice.ENB_UE_S1AP_ID = e_rab_modification_ind->eNB_ue_s1ap_id; + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + //E-RABs to be modified list + ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t)); + ie->id = S1AP_ProtocolIE_ID_id_E_RABToBeModifiedListBearerModInd; + ie->criticality = S1AP_Criticality_reject; + ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_E_RABToBeModifiedListBearerModInd; + + //The following two for-loops here will probably need to change. We should do a different type of search + for(int i=0; iid = S1AP_ProtocolIE_ID_id_E_RABToBeModifiedItemBearerModInd; + E_RAB_ToBeModifiedItem_BearerModInd_IEs->criticality = S1AP_Criticality_reject; + E_RAB_ToBeModifiedItem_BearerModInd_IEs->value.present = S1AP_E_RABToBeModifiedItemBearerModIndIEs__value_PR_E_RABToBeModifiedItemBearerModInd; + E_RAB_ToBeModifiedItem_BearerModInd = &E_RAB_ToBeModifiedItem_BearerModInd_IEs->value.choice.E_RABToBeModifiedItemBearerModInd; + + { + E_RAB_ToBeModifiedItem_BearerModInd->e_RAB_ID = e_rab_modification_ind->e_rabs_tobemodified[i].e_rab_id; + + E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.size = e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.length/8; + E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.bits_unused = e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.length%8; + E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.buf = calloc(1, E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.size); + memcpy (E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.buf, e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.buffer, + E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.size); + + INT32_TO_OCTET_STRING(e_rab_modification_ind->e_rabs_tobemodified[i].gtp_teid, &E_RAB_ToBeModifiedItem_BearerModInd->dL_GTP_TEID); + + } + ASN_SEQUENCE_ADD(&ie->value.choice.E_RABToBeModifiedListBearerModInd.list, E_RAB_ToBeModifiedItem_BearerModInd_IEs); + } + + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + //E-RABs NOT to be modified list + ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t)); + ie->id = S1AP_ProtocolIE_ID_id_E_RABNotToBeModifiedListBearerModInd; + ie->criticality = S1AP_Criticality_reject; + //if(num_e_rabs_nottobemodified > 0) { + ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_E_RABNotToBeModifiedListBearerModInd; + + for(int i=0; iid = S1AP_ProtocolIE_ID_id_E_RABNotToBeModifiedItemBearerModInd; + E_RAB_NotToBeModifiedItem_BearerModInd_IEs->criticality = S1AP_Criticality_reject; + E_RAB_NotToBeModifiedItem_BearerModInd_IEs->value.present = S1AP_E_RABNotToBeModifiedItemBearerModIndIEs__value_PR_E_RABNotToBeModifiedItemBearerModInd; + E_RAB_NotToBeModifiedItem_BearerModInd = &E_RAB_NotToBeModifiedItem_BearerModInd_IEs->value.choice.E_RABNotToBeModifiedItemBearerModInd; + + { + E_RAB_NotToBeModifiedItem_BearerModInd->e_RAB_ID = e_rab_modification_ind->e_rabs_tobemodified[i].e_rab_id; + + E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.size = e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.length/8; + E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.bits_unused = e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.length%8; + E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.buf = + calloc(1, E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.size); + memcpy (E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.buf, e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.buffer, + E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.size); + + INT32_TO_OCTET_STRING(e_rab_modification_ind->e_rabs_tobemodified[i].gtp_teid, &E_RAB_NotToBeModifiedItem_BearerModInd->dL_GTP_TEID); + + } + ASN_SEQUENCE_ADD(&ie->value.choice.E_RABNotToBeModifiedListBearerModInd.list, E_RAB_NotToBeModifiedItem_BearerModInd_IEs); + } + // } + /*else{ + ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_E_RABNotToBeModifiedListBearerModInd; + ie->value.choice.E_RABNotToBeModifiedListBearerModInd.list.size = 0; + } */ + + + + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t)); + ie->id = S1AP_ProtocolIE_ID_id_CSGMembershipInfo; + ie->criticality = S1AP_Criticality_reject; + ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_CSGMembershipInfo; + ie->value.choice.CSGMembershipInfo.cSGMembershipStatus = S1AP_CSGMembershipStatus_member; + INT16_TO_BIT_STRING(CSG_id, &ie->value.choice.CSGMembershipInfo.cSG_Id); + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + + + if (s1ap_eNB_encode_pdu(&pdu, &buffer, &len) < 0) { + S1AP_ERROR("Failed to encode S1 E-RAB modification indication \n"); + return -1; + } + + // Non UE-Associated signalling -> stream = 0 + S1AP_INFO("Size of encoded message: %d \n", len); + s1ap_eNB_itti_send_sctp_data_req(s1ap_eNB_instance_p->instance, + ue_context_p->mme_ref->assoc_id, buffer, + len, ue_context_p->tx_stream); + +//s1ap_eNB_itti_send_sctp_data_req(s1ap_eNB_instance_p->instance, ue_context_p->mme_ref->assoc_id, buffer, len, 0); return ret; } From 1462f0e659122afc68bdb320044a7f96fd0d62d2 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Fri, 20 Mar 2020 22:55:17 +0100 Subject: [PATCH 099/553] ENDC path switch S1-U: Bugfixes at gNB side --- .../NR_ESTIMATION/nr_ul_channel_estimation.c | 14 +++ openair1/PHY/NR_TRANSPORT/nr_dci.c | 2 + openair1/PHY/NR_TRANSPORT/nr_prach.c | 39 ++++++++- openair1/PHY/NR_TRANSPORT/nr_prach_common.c | 2 +- openair1/PHY/NR_TRANSPORT/nr_ulsch.c | 1 + .../PHY/NR_TRANSPORT/nr_ulsch_demodulation.c | 25 ++++++ openair1/SCHED_NR/nr_prach_procedures.c | 4 + openair1/SCHED_NR/nr_ru_procedures.c | 12 +++ openair2/GNB_APP/gnb_config.c | 13 ++- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 2 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 6 +- .../LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c | 2 +- .../LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c | 4 + openair2/RRC/NR/rrc_gNB_nsa.c | 28 ++++++ openair2/RRC/NR/rrc_gNB_reconfig.c | 87 ++++++++++++++----- openair2/X2AP/x2ap_eNB_generate_messages.c | 4 +- openair2/X2AP/x2ap_eNB_handler.c | 9 ++ openair3/GTPV1-U/gtpv1u_eNB.c | 11 +++ 18 files changed, 229 insertions(+), 36 deletions(-) diff --git a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c index 64672f2b7a..59210bb2ea 100644 --- a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c +++ b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c @@ -36,6 +36,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, unsigned char symbol, unsigned short bwp_start_subcarrier, nfapi_nr_pusch_pdu_t *pusch_pdu) { +printf("nr_pusch_channel_estimation Ns %d p %d symbol %d\n", Ns, p, symbol); int pilot[3280] __attribute__((aligned(16))); unsigned char aarx; @@ -488,5 +489,18 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, fclose(debug_ch_est); #endif +{ + char name[128]; + FILE *f; + sprintf(name, "ch_estimate.%d.%d.raw", gNB->proc.frame_rx, symbol); + f = fopen(name, "w"); if (f == NULL) exit(1); + fwrite(&ul_ch_estimates[0][symbol_offset], nb_rb_pusch*12*4, 1, f); + fclose(f); + sprintf(name, "ch_estimate_time.%d.%d.raw", gNB->proc.frame_rx, symbol); + f = fopen(name, "w"); if (f == NULL) exit(1); + fwrite(ul_ch_estimates_time[0], 1536*4, 1, f); + fclose(f); +} + return(0); } diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.c b/openair1/PHY/NR_TRANSPORT/nr_dci.c index 812c49d6f6..75493dfd9c 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.c @@ -238,6 +238,8 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, pdcch_pdu_rel15->dci_pdu.AggregationLevel[d], 0,NULL); polar_encoder_fast((uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[d], encoder_output, n_RNTI,1,currentPtr); + printf("DCI PDU: [0]->0x%lx \t [1]->0x%lx %d bits aggreg %d\n", + ((uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[d])[0], ((uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[d])[1], pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d], pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]); #ifdef DEBUG_CHANNEL_CODING printf("polar rnti %x,length %d, L %d\n",n_RNTI, pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d],pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]); printf("DCI PDU: [0]->0x%lx \t [1]->0x%lx\n", diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index 80760ac032..634d5b2d91 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -81,6 +81,8 @@ void nr_fill_prach(PHY_VARS_gNB *gNB, void init_prach_ru_list(RU_t *ru) { +//g_log->debug_mask |= PRACH; + AssertFatal(ru!=NULL,"ruis null\n"); for (int i=0; iprach_list[i].frame=-1; pthread_mutex_init(&ru->prach_list_mutex,NULL); @@ -382,6 +384,17 @@ void rx_nr_prach_ru(RU_t *ru, for (int i=6;i<12;i++) dft1536(prach2+(3072*i),rxsigF[aa]+(3072*i),1); reps+=6; } +if (0){ + char name[256]; + sprintf(name, "time.%d.%d.raw", frame, slot); + FILE *f = fopen(name, "w"); if (f == NULL) exit(1); + fwrite(prach2-1536*4, 1536*4*4+1536*4, 1, f); + fclose(f); + sprintf(name, "freq.%d.%d.raw", frame, slot); + f = fopen(name, "w"); if (f == NULL) exit(1); + fwrite(rxsigF[aa], 1536*4*4, 1, f); + fclose(f); +} }// mu==1 else if (mu==2) AssertFatal(1==0,"Shouldn't get here\n"); else if (mu==3) AssertFatal(1==0,"Shouldn't get here\n"); @@ -515,6 +528,13 @@ void rx_nr_prach_ru(RU_t *ru, } memcpy((void*)rxsigF2,(void *)rxsigF_tmp,N_ZC<<2); +if (0){ + char name[256]; + sprintf(name, "sum.%d.%d.raw", frame, slot); + FILE *f = fopen(name, "w"); if (f == NULL) exit(1); + fwrite(rxsigF_tmp, N_ZC*4, 1, f); + fclose(f); +} } } @@ -537,7 +557,7 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, uint16_t rootSequenceIndex; int numrootSequenceIndex; uint8_t restricted_set; - uint8_t n_ra_prb; + uint8_t n_ra_prb = 0; int16_t *prachF=NULL; int nb_rx; @@ -620,7 +640,19 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, *max_preamble_delay=0; *max_preamble=0; +if (0){ + char name[256]; + sprintf(name, "sum2.%d.%d.raw", frame, subframe); + FILE *f = fopen(name, "w"); if (f == NULL) exit(1); + fwrite(rxsigF[0], N_ZC*4, 1, f); + fclose(f); +} + for (preamble_index=0 ; preamble_index<64 ; preamble_index++) { +{ +int en = dB_fixed(signal_energy((int32_t*)&rxsigF[0][0],(N_ZC==839) ? 840: 140)); +if (en>40 && preamble_index==0) LOG_I(PHY,"%d.%d: try preamble %d en %d\n",frame,subframe,preamble_index, en); +} if (LOG_DEBUGFLAG(PRACH)){ int en = dB_fixed(signal_energy((int32_t*)&rxsigF[0][0],(N_ZC==839) ? 840: 140)); @@ -701,8 +733,9 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, } // Compute DFT of RX signal (conjugate input, results in conjugate output) for each new rootSequenceIndex + int en = dB_fixed(signal_energy((int32_t*)&rxsigF[0][0],140)); if (LOG_DEBUGFLAG(PRACH)) { - int en = dB_fixed(signal_energy((int32_t*)&rxsigF[0][0],840)); + //int en = dB_fixed(signal_energy((int32_t*)&rxsigF[0][0],840)); if (en>60) LOG_I(PHY,"frame %d, subframe %d : preamble index %d, NCS %d, N_ZC/NCS %d: offset %d, preamble shift %d , en %d)\n", frame,subframe,preamble_index,NCS,N_ZC/NCS,preamble_offset,preamble_shift,en); } @@ -765,6 +798,8 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, for (i=0; i60) LOG_I(PHY, "preamble_index %d NCS2 %d i %d lev %d levdB %d preamble_shift2 %d\n", preamble_index, NCS2, i, lev, levdB, preamble_shift2); if (levdB>*max_preamble_energy) { *max_preamble_energy = levdB; *max_preamble_delay = i; // Note: This has to be normalized to the 30.72 Ms/s sampling rate diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c index e881b91b84..816d7a7bf4 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c @@ -94,7 +94,6 @@ void nr_fill_du(uint16_t N_ZC,uint16_t *prach_root_sequence_map) nr_du[u] = ((p<(N_ZC>>1)) ? p : (N_ZC-p)); } - } @@ -159,6 +158,7 @@ void compute_nr_prach_seq(nfapi_nr_config_request_scf_t *config, for (k=0; k> 16) & 65535), (((k*(1+(inv_u*k)))%N_ZC)*70)%N_ZC); } } diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch.c index 6764e6e125..80322bcda9 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch.c @@ -88,6 +88,7 @@ void nr_ulsch_unscrambling(int16_t* llr, uint32_t Nid, uint32_t n_RNTI) { +printf("nr_ulsch_unscrambling n_RNTI %d\n", n_RNTI); uint8_t reset; uint32_t x1, x2, s=0; diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c index 0478d892d5..d1ea959ab5 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c @@ -991,6 +991,8 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, int avg[4]; uint8_t nodata_dmrs = 1; // FIXME to be properly configured from fapi +printf("nr_rx_pusch frame %d nr_tti_rx %d symbol %d rel15_ul->start_symbol_index %d rel15_ul->nr_of_symbols %d\n", frame, nr_tti_rx, symbol, rel15_ul->start_symbol_index, rel15_ul->nr_of_symbols); + dmrs_symbol_flag = 0; if(symbol == rel15_ul->start_symbol_index){ @@ -1034,6 +1036,15 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, //--------------------- RBs extraction --------------------- //---------------------------------------------------------- +{ + char name[128]; + FILE *f; + sprintf(name, "rxdataF.%d.%d.raw", frame, symbol); + f = fopen(name, "w"); + fwrite(&gNB->common_vars.rxdataF[0][symbol * frame_parms->ofdm_symbol_size], frame_parms->ofdm_symbol_size*4, 1, f); + fclose(f); +} + if (nb_re_pusch > 0) { nr_ulsch_extract_rbs_single(gNB->common_vars.rxdataF, @@ -1086,6 +1097,20 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, rel15_ul->rb_size, gNB->pusch_vars[UE_id]->log2_maxh); +{ + char name[128]; + FILE *f; + sprintf(name, "rxdataF_ext.%d.%d.raw", frame, symbol); + f = fopen(name, "w"); + int nb_re_pusch = NR_NB_SC_PER_RB * rel15_ul->rb_size; + fwrite(&gNB->pusch_vars[UE_id]->rxdataF_ext[0][symbol * nb_re_pusch], nb_re_pusch*4, 1, f); + fclose(f); + sprintf(name, "rxdataF_comp.%d.%d.raw", frame, symbol); + f = fopen(name, "w"); + fwrite(&gNB->pusch_vars[UE_id]->rxdataF_comp[0][symbol * nb_re_pusch], nb_re_pusch*4, 1, f); + fclose(f); +} + #ifdef NR_SC_FDMA nr_idft(&((uint32_t*)gNB->pusch_vars[UE_id]->rxdataF_ext[0])[symbol * rel15_ul->rb_size * NR_NB_SC_PER_RB], nb_re_pusch); #endif diff --git a/openair1/SCHED_NR/nr_prach_procedures.c b/openair1/SCHED_NR/nr_prach_procedures.c index 855da5ac8a..f7b5c6dfda 100644 --- a/openair1/SCHED_NR/nr_prach_procedures.c +++ b/openair1/SCHED_NR/nr_prach_procedures.c @@ -77,6 +77,8 @@ void L1_nr_prach_procedures(PHY_VARS_gNB *gNB,int frame,int slot, } } +//ru = gNB->RU_list[0]; +//rx_nr_prach_ru(ru, prach_pdu, frame, slot); rx_nr_prach(gNB, prach_pdu, @@ -86,6 +88,8 @@ void L1_nr_prach_procedures(PHY_VARS_gNB *gNB,int frame,int slot, &max_preamble_energy[0], &max_preamble_delay[0] ); +if (max_preamble_energy[0] > 200) +printf("ra %d.%d preamble %d energy %d delay %d gNB->measurements.prach_I0+100 %d\n", frame, slot, max_preamble[0], max_preamble_energy[0], max_preamble_delay[0], gNB->measurements.prach_I0+100); LOG_D(PHY,"[RAPROC] Frame %d, slot %d : Most likely preamble %d, energy %d dB delay %d (prach_energy counter %d)\n", frame,slot, diff --git a/openair1/SCHED_NR/nr_ru_procedures.c b/openair1/SCHED_NR/nr_ru_procedures.c index aefeec43e2..ef65a63785 100644 --- a/openair1/SCHED_NR/nr_ru_procedures.c +++ b/openair1/SCHED_NR/nr_ru_procedures.c @@ -512,6 +512,16 @@ void nr_fep0(RU_t *ru, int first_half) { VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPRX+proc->tti_rx, 1); +if(0){ +//printf("nr_fep0 proc->tti_rx %d f %dd\n", proc->tti_rx, proc->frame_rx); + char name[128]; + FILE *f; + sprintf(name, "rxdata.%d.%d.raw", proc->frame_rx, proc->tti_rx); + f = fopen(name, "w"); if (f == NULL) exit(1); + fwrite(&ru->common.rxdata[0][proc->tti_rx * 23040], 23040*4, 1, f); + fclose(f); +} + // remove_7_5_kHz(ru,(slot&1)+(proc->tti_rx<<1)); for (l = start_symbol; l < end_symbol; l++) { for (aa = 0; aa < fp->nb_antennas_rx; aa++) { @@ -648,6 +658,8 @@ void nr_fep_full(RU_t *ru, int slot) { // remove_7_5_kHz(ru,proc->tti_rx<<1); // remove_7_5_kHz(ru,1+(proc->tti_rx<<1)); +printf("nr_fep_full proc->tti_rx %d\n", proc->tti_rx); + for (l = 0; l < fp->symbols_per_slot; l++) { for (aa = 0; aa < fp->nb_antennas_rx; aa++) { nr_slot_fep_ul(fp, diff --git a/openair2/GNB_APP/gnb_config.c b/openair2/GNB_APP/gnb_config.c index afb98309d5..88df3eadad 100644 --- a/openair2/GNB_APP/gnb_config.c +++ b/openair2/GNB_APP/gnb_config.c @@ -237,6 +237,7 @@ void fix_scc(NR_ServingCellConfigCommon_t *scc,uint64_t ssbmap) { scc->ssb_PositionsInBurst->choice.mediumBitmap.buf[0] = 0; for (int i=0; i<8; i++) scc->ssb_PositionsInBurst->choice.mediumBitmap.buf[0] |= (((ssbmap>>(7-i))&0x01)<ssb_PositionsInBurst->choice.mediumBitmap.buf[0] = 0x80; //ssbmap; }else { scc->ssb_PositionsInBurst->choice.longBitmap.size = 8; scc->ssb_PositionsInBurst->choice.longBitmap.bits_unused = 0; @@ -719,10 +720,14 @@ int RCconfig_nr_gtpu(void ) { if (address) { MessageDef *message; AssertFatal((message = itti_alloc_new_message(TASK_GNB_APP, GTPV1U_ENB_S1_REQ))!=NULL,""); - IPV4_STR_ADDR_TO_INT_NWBO ( address, RC.gtpv1u_data_g->enb_ip_address_for_S1u_S12_S4_up, "BAD IP ADDRESS FORMAT FOR eNB S1_U !\n" ); - LOG_I(GTPU,"Configuring GTPu address : %s -> %x\n",address,RC.gtpv1u_data_g->enb_ip_address_for_S1u_S12_S4_up); - GTPV1U_ENB_S1_REQ(message).enb_port_for_S1u_S12_S4_up = gnb_port_for_S1U; - itti_send_msg_to_task (TASK_GTPV1_U, 0, message); // data model is wrong: gtpu doesn't have enb_id (or module_id) + // IPV4_STR_ADDR_TO_INT_NWBO ( address, RC.gtpv1u_data_g->enb_ip_address_for_S1u_S12_S4_up, "BAD IP ADDRESS FORMAT FOR eNB S1_U !\n" ); + // LOG_I(GTPU,"Configuring GTPu address : %s -> %x\n",address,RC.gtpv1u_data_g->enb_ip_address_for_S1u_S12_S4_up); + + + IPV4_STR_ADDR_TO_INT_NWBO ( address, GTPV1U_ENB_S1_REQ(message).enb_ip_address_for_S1u_S12_S4_up, "BAD IP ADDRESS FORMAT FOR eNB S1_U !\n" ); + LOG_I(GTPU,"Configuring GTPu address : %s -> %x\n",address,GTPV1U_ENB_S1_REQ(message).enb_ip_address_for_S1u_S12_S4_up); + GTPV1U_ENB_S1_REQ(message).enb_port_for_S1u_S12_S4_up = gnb_port_for_S1U; + itti_send_msg_to_task (TASK_GTPV1_U, 0, message); // data model is wrong: gtpu doesn't have enb_id (or module_id) } else LOG_E(GTPU,"invalid address for S1U\n"); diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index 92765acf41..ad049bf19d 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -1397,7 +1397,7 @@ void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, uint8_t N_sh_symb = pdsch_rel15->NrOfSymbols; uint8_t Imcs = pdsch_rel15->mcsIndex[0]; uint16_t N_RE_prime = NR_NB_SC_PER_RB*N_sh_symb - N_PRB_DMRS - N_PRB_oh; - LOG_D(MAC, "N_RE_prime %d for %d symbols %d DMRS per PRB and %d overhead\n", N_RE_prime, N_sh_symb, N_PRB_DMRS, N_PRB_oh); + LOG_I(MAC, "N_RE_prime %d for %d symbols %d DMRS per PRB and %d overhead\n", N_RE_prime, N_sh_symb, N_PRB_DMRS, N_PRB_oh); uint16_t R; uint32_t TBS=0; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index b06dcd0a23..7ffb00adbf 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -295,7 +295,7 @@ void nr_initiate_ra_proc(module_id_t module_idP, LOG_D(MAC, "%s() Msg2[%04d%d] SFN/SF:%04d%d\n", __FUNCTION__, ra->Msg2_frame, ra->Msg2_slot, frameP, slotP); do { - ra->rnti = (taus() % 65518) + 1; + ra->rnti = 666; //(taus() % 65518) + 1; loop++; } while (loop != 100 && !(find_nr_UE_id(module_idP, ra->rnti) == -1 && ra->rnti >= 1 && ra->rnti <= 65519)); @@ -677,7 +677,7 @@ void nr_generate_Msg2(module_id_t module_idP, dci_formats[0] = NR_DL_DCI_FORMAT_1_0; rnti_types[0] = NR_RNTI_RA; - LOG_D(MAC, "[RAPROC] DCI params: rnti %d, rnti_type %d, dci_format %d coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n", + LOG_I(MAC, "[RAPROC] DCI params: rnti %d, rnti_type %d, dci_format %d coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n", pdcch_pdu_rel15->dci_pdu.RNTI[0], rnti_types[0], dci_formats[0], @@ -810,6 +810,8 @@ void nr_fill_rar(uint8_t Mod_idP, ul_grant = csi_req | (tpc_command << 1) | (pusch_pdu->mcs_index << 4) | (ra->Msg3_tda_id << 8) | (f_alloc << 12) | (pusch_pdu->frequency_hopping << 26); +printf("ul grant 0x%x mcs %d f_alloc %d tpc %d\n", ul_grant, pusch_pdu->mcs_index, f_alloc, tpc_command); + rar->UL_GRANT_1 = (uint8_t) (ul_grant >> 24) & 0x07; rar->UL_GRANT_2 = (uint8_t) (ul_grant >> 16) & 0xff; rar->UL_GRANT_3 = (uint8_t) (ul_grant >> 8) & 0xff; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c index 024496c3d0..3f36b5630a 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c @@ -84,7 +84,7 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ if (mib_sdu_length > 0) { - LOG_I(MAC, "Frame %d, slot %d: Adding BCH PDU in position %d (length %d)\n", frameP, slotP, dl_req->nPDUs, mib_sdu_length); + LOG_D(MAC, "Frame %d, slot %d: Adding BCH PDU in position %d (length %d)\n", frameP, slotP, dl_req->nPDUs, mib_sdu_length); if ((frameP & 1023) < 80){ LOG_I(MAC,"[gNB %d] Frame %d : MIB->BCH CC_id %d, Received %d bytes\n",module_idP, frameP, CC_id, mib_sdu_length); diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c b/openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c index df23b64e07..4dfb39280a 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c +++ b/openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c @@ -28,6 +28,8 @@ #include "common/utils/nr/nr_common.h" #include +#include "LOG/log.h" + //Table 5.1.2.2-2 uint16_t Tbstable_nr[INDEX_MAX_TBS_TABLE] = {24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,208,224,240,256,272,288,304,320,336,352,368,384,408,432,456,480,504,528,552,576,608,640,672,704,736,768,808,848,888,928,984,1032,1064,1128,1160,1192,1224,1256,1288,1320,1352,1416,1480,1544,1608,1672,1736,1800,1864,1928,2024,2088,2152,2216,2280,2408,2472,2536,2600,2664,2728,2792,2856,2976,3104,3240,3368,3496,3624,3752,3824}; @@ -88,6 +90,8 @@ uint32_t nr_compute_tbs(uint16_t Qm, } //printf("Ninfo %d nbp_re %d nb_re %d Qm %d, R %d, tbs %d\n", Ninfo, nbp_re, nb_re, Qm, R, nr_tbs); + LOG_I(PHY, "Ninfo %d nbp_re %d nb_re %d Qm %d, R %d, tbs %d nb_symb_sch %d nb_dmrs_prb %d nb_rb_oh %d tb_scaling %d Nl %d\n", + Ninfo, nbp_re, nb_re, Qm, R, nr_tbs, nb_symb_sch, nb_dmrs_prb, nb_rb_oh, tb_scaling, Nl); return nr_tbs; } diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c index caa724ae24..e71843944e 100644 --- a/openair2/RRC/NR/rrc_gNB_nsa.c +++ b/openair2/RRC/NR/rrc_gNB_nsa.c @@ -155,6 +155,14 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_ create_tunnel_req.sgw_S1u_teid[i] = ue_context_p->ue_context.e_rab[i].param.gtp_teid; memcpy(&create_tunnel_req.sgw_addr[i], &ue_context_p->ue_context.e_rab[i].param.sgw_addr, sizeof(transport_layer_addr_t)); inde_list[i] = i; + LOG_I(RRC,"S1-U tunnel: index %d target sgw ip %d.%d.%d.%d length %d gtp teid %u\n", + i, + create_tunnel_req.sgw_addr[i].buffer[0], + create_tunnel_req.sgw_addr[i].buffer[1], + create_tunnel_req.sgw_addr[i].buffer[2], + create_tunnel_req.sgw_addr[i].buffer[3], + create_tunnel_req.sgw_addr[i].length, + create_tunnel_req.sgw_S1u_teid[i]); } //PM: Is this where we should extract the rnti from? create_tunnel_req.rnti = ue_context_p->ue_id_rnti; @@ -175,6 +183,26 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_ X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].e_rab_id = ue_context_p->ue_context.e_rab[i].param.e_rab_id; X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gtp_teid = create_tunnel_resp.enb_S1u_teid[i]; memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr, &create_tunnel_resp.enb_addr, sizeof(transport_layer_addr_t)); + + //The length field in the X2AP targetting structure is expected in bits but the create_tunnel_resp returns the address length in bytes + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.length = create_tunnel_resp.enb_addr.length*8; + + LOG_I(RRC,"S1-U create_tunnel_resp tunnel: index %d target gNB ip %d.%d.%d.%d length %d gtp teid %u\n", + i, + create_tunnel_resp.enb_addr.buffer[0], + create_tunnel_resp.enb_addr.buffer[1], + create_tunnel_resp.enb_addr.buffer[2], + create_tunnel_resp.enb_addr.buffer[3], + create_tunnel_resp.enb_addr.length, + create_tunnel_resp.enb_S1u_teid[i]); + LOG_I(RRC,"X2AP sGNB Addition Request: index %d target gNB ip %d.%d.%d.%d length %d gtp teid %u\n", + i, + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[0], + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[1], + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[2], + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[3], + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.length, + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gtp_teid); } } else diff --git a/openair2/RRC/NR/rrc_gNB_reconfig.c b/openair2/RRC/NR/rrc_gNB_reconfig.c index baa771b716..e17e5ad5c4 100644 --- a/openair2/RRC/NR/rrc_gNB_reconfig.c +++ b/openair2/RRC/NR/rrc_gNB_reconfig.c @@ -116,6 +116,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco tag->tag_Id = 0; tag->timeAlignmentTimer = NR_TimeAlignmentTimer_infinity; ASN_SEQUENCE_ADD(&secondaryCellGroup->mac_CellGroupConfig->tag_Config->tag_ToAddModList->list,tag); +#if 1 secondaryCellGroup->mac_CellGroupConfig->phr_Config = calloc(1,sizeof(*secondaryCellGroup->mac_CellGroupConfig->phr_Config)); secondaryCellGroup->mac_CellGroupConfig->phr_Config->present = NR_SetupRelease_PHR_Config_PR_setup; secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup = calloc(1,sizeof(*secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup)); @@ -126,6 +127,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup->dummy=false; secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup->phr_Type2OtherCell = false; secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup->phr_ModeOtherCG = NR_PHR_Config__phr_ModeOtherCG_real; +#endif secondaryCellGroup->mac_CellGroupConfig->skipUplinkTxDynamic=false; secondaryCellGroup->mac_CellGroupConfig->ext1 = NULL; @@ -150,7 +152,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco *secondaryCellGroup->spCellConfig->servCellIndex = servCellIndex; secondaryCellGroup->spCellConfig->reconfigurationWithSync=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->reconfigurationWithSync)); secondaryCellGroup->spCellConfig->reconfigurationWithSync->spCellConfigCommon=servingcellconfigcommon; - secondaryCellGroup->spCellConfig->reconfigurationWithSync->newUE_Identity=(get_softmodem_params()->phy_test==1) ? 0x1234 : (taus()&0xffff); + secondaryCellGroup->spCellConfig->reconfigurationWithSync->newUE_Identity=(get_softmodem_params()->phy_test==1) ? 0x1234 : 0x3456; //(taus()&0xffff); secondaryCellGroup->spCellConfig->reconfigurationWithSync->t304=NR_ReconfigurationWithSync__t304_ms2000; secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated = NULL; secondaryCellGroup->spCellConfig->reconfigurationWithSync->ext1 = NULL; @@ -189,7 +191,11 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition)); *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0; +secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList=NULL; + +#if 0 secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList)); NR_TCI_State_t*tci0=calloc(1,sizeof(*tci0)); @@ -351,6 +357,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco tci15->qcl_Type1.referenceSignal.choice.ssb = 7; tci15->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci15); +#endif secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; @@ -379,6 +386,8 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->sps_Config = NULL; //calloc(1,sizeof(struct NR_SetupRelease_SPS_Config)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig = NULL; +#if 0 secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig)); secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->present = NR_SetupRelease_RadioLinkMonitoringConfig_PR_setup; @@ -389,8 +398,10 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = NR_RadioLinkMonitoringConfig__beamFailureInstanceMaxCount_n3; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer)); *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = NR_RadioLinkMonitoringConfig__beamFailureDetectionTimer_pbfd2; +#endif secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToReleaseList= NULL; +// secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList = NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList)); NR_BWP_Downlink_t *bwp=calloc(1,sizeof(*bwp)); @@ -400,6 +411,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco memcpy((void*)&bwp->bwp_Common->genericParameters, &servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->genericParameters, sizeof(bwp->bwp_Common->genericParameters)); + bwp->bwp_Common->genericParameters.locationAndBandwidth=6407; //PRBalloc_to_locationandbandwidth(servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth,0); bwp->bwp_Common->genericParameters.locationAndBandwidth=PRBalloc_to_locationandbandwidth(servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth,0); @@ -453,7 +465,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ss->monitoringSymbolsWithinSlot->buf = calloc(1,2); // should be '1100 0000 0000 00'B (LSB first!), first two symols in slot, adjust if needed ss->monitoringSymbolsWithinSlot->buf[1] = 0; - ss->monitoringSymbolsWithinSlot->buf[0] = (1<<7) | (1<<6); + ss->monitoringSymbolsWithinSlot->buf[0] = (1<<7); // | (1<<6); ss->monitoringSymbolsWithinSlot->size = 2; ss->monitoringSymbolsWithinSlot->bits_unused = 2; ss->nrofCandidates = calloc(1,sizeof(*ss->nrofCandidates)); @@ -476,6 +488,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace)); *bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace=1; bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ext1=NULL; +//bwp->bwp_Common->pdcch_ConfigCommon=NULL; bwp->bwp_Common->pdsch_ConfigCommon=calloc(1,sizeof(*bwp->bwp_Common->pdsch_ConfigCommon)); bwp->bwp_Common->pdsch_ConfigCommon->present = NR_SetupRelease_PDSCH_ConfigCommon_PR_setup; @@ -521,7 +534,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ss2->monitoringSymbolsWithinSlot->buf = calloc(1,2); ss2->monitoringSymbolsWithinSlot->size = 2; ss2->monitoringSymbolsWithinSlot->bits_unused = 2; - ss2->monitoringSymbolsWithinSlot->buf[0]=0xc0; + ss2->monitoringSymbolsWithinSlot->buf[0]=0x80; //0xc0; ss2->monitoringSymbolsWithinSlot->buf[1]=0x0; ss2->nrofCandidates=calloc(1,sizeof(*ss2->nrofCandidates)); ss2->nrofCandidates->aggregationLevel1 = NR_SearchSpace__nrofCandidates__aggregationLevel1_n0; @@ -557,7 +570,10 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition)); *bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0; +bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList=NULL; +#if 0 bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList=calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList)); NR_TCI_State_t*tcid0=calloc(1,sizeof(*tcid0)); @@ -719,6 +735,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco tcid15->qcl_Type1.referenceSignal.choice.ssb = 7; tcid15->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid15); +#endif bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; @@ -773,6 +790,8 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco bwp->bwp_Dedicated->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL; bwp->bwp_Dedicated->sps_Config = NULL; //calloc(1,sizeof(struct NR_SetupRelease_SPS_Config)); + bwp->bwp_Dedicated->radioLinkMonitoringConfig = NULL; +#if 0 bwp->bwp_Dedicated->radioLinkMonitoringConfig = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig)); bwp->bwp_Dedicated->radioLinkMonitoringConfig->present = NR_SetupRelease_RadioLinkMonitoringConfig_PR_setup; @@ -783,14 +802,17 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco *bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = NR_RadioLinkMonitoringConfig__beamFailureInstanceMaxCount_n3; bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer)); *bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = NR_RadioLinkMonitoringConfig__beamFailureDetectionTimer_pbfd2; +#endif - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list,bwp); + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list,bwp); secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id)); - *secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id=1; + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id=1; //0; //1; secondaryCellGroup->spCellConfig->spCellConfigDedicated->bwp_InactivityTimer = NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->defaultDownlinkBWP_Id = NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->defaultDownlinkBWP_Id = calloc(1, sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->defaultDownlinkBWP_Id)); + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->defaultDownlinkBWP_Id = 1; secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig)); NR_BWP_UplinkDedicated_t *initialUplinkBWP = calloc(1,sizeof(*initialUplinkBWP)); @@ -913,6 +935,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&srs_Config->srs_ResourceToAddModList->list,srs_res0); secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToReleaseList = NULL; +// secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList = NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList)); NR_BWP_Uplink_t *ubwp = calloc(1,sizeof(*ubwp)); ubwp->bwp_Id=1; @@ -921,8 +944,10 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco memcpy((void*)&ubwp->bwp_Common->genericParameters, (void*)&servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->genericParameters, sizeof(servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->genericParameters)); + ubwp->bwp_Common->genericParameters.locationAndBandwidth=6407; //PRBalloc_to_locationandbandwidth(servingcellconfigcommon->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth,0); ubwp->bwp_Common->genericParameters.locationAndBandwidth=PRBalloc_to_locationandbandwidth(servingcellconfigcommon->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth,0); +servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig = 0; ubwp->bwp_Common->rach_ConfigCommon = servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon; ubwp->bwp_Common->pusch_ConfigCommon = servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon; ubwp->bwp_Common->pucch_ConfigCommon = servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon; @@ -1074,10 +1099,10 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ubwp->bwp_Dedicated->beamFailureRecoveryConfig = NULL; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list,ubwp); + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list,ubwp); secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id)); - *secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id = 1; + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id = 1; //0; //1; secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig = NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->carrierSwitching = NULL; @@ -1085,10 +1110,14 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdcch_ServingCellConfig=NULL; +#if 0 secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig)); NR_PDSCH_ServingCellConfig_t *pdsch_servingcellconfig = calloc(1,sizeof(*pdsch_servingcellconfig)); secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->present = NR_SetupRelease_PDSCH_ServingCellConfig_PR_setup; secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup = pdsch_servingcellconfig; +#endif + NR_PDSCH_ServingCellConfig_t *pdsch_servingcellconfig = calloc(1,sizeof(*pdsch_servingcellconfig)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig=NULL; pdsch_servingcellconfig->codeBlockGroupTransmission = NULL; pdsch_servingcellconfig->xOverhead = NULL; pdsch_servingcellconfig->nrofHARQ_ProcessesForPDSCH = NULL; @@ -1098,12 +1127,13 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco *pdsch_servingcellconfig->ext1->maxMIMO_Layers = 2; pdsch_servingcellconfig->ext1->processingType2Enabled = NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->present = NR_SetupRelease_CSI_MeasConfig_PR_setup; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig=NULL; + //secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig)); + //secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->present = NR_SetupRelease_CSI_MeasConfig_PR_setup; NR_CSI_MeasConfig_t *csi_MeasConfig = calloc(1,sizeof(*csi_MeasConfig)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup = csi_MeasConfig; +// secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup = csi_MeasConfig; csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList = calloc(1,sizeof(*csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList)); NR_NZP_CSI_RS_Resource_t *nzpres0 = calloc(1,sizeof(*nzpres0)); @@ -1643,7 +1673,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco imres0->csi_IM_ResourceElementPattern->choice.pattern1->symbolLocation_p1=7; imres0->freqBand=calloc(1,sizeof(*imres0->freqBand)); imres0->freqBand->startingRB=0; - imres0->freqBand->nrofRBs=276; + imres0->freqBand->nrofRBs=106; imres0->periodicityAndOffset=calloc(1,sizeof(*imres0->periodicityAndOffset)); imres0->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots320; imres0->periodicityAndOffset->choice.slots320 = 2; @@ -1717,7 +1747,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires11->csi_RS_ResourceSetList.choice.csi_IM_ResourceSetList->list,csires110); csires11->bwp_Id = 1; csires11->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires11); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires11); NR_CSI_ResourceConfig_t *csires10 = calloc(1,sizeof(*csires10)); csires10->csi_ResourceConfigId=10; @@ -1730,7 +1760,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires100); csires10->bwp_Id = 1; csires10->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires10); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires10); NR_CSI_ResourceConfig_t *csires2 = calloc(1,sizeof(*csires2)); csires2->csi_ResourceConfigId=2; @@ -1743,7 +1773,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires20); csires2->bwp_Id = 1; csires2->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires2); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires2); NR_CSI_ResourceConfig_t *csires3 = calloc(1,sizeof(*csires3)); csires3->csi_ResourceConfigId=3; @@ -1756,7 +1786,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires30); csires3->bwp_Id = 1; csires3->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires3); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires3); NR_CSI_ResourceConfig_t *csires4 = calloc(1,sizeof(*csires4)); csires4->csi_ResourceConfigId=4; @@ -1769,7 +1799,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires40); csires4->bwp_Id = 1; csires4->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires4); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires4); NR_CSI_ResourceConfig_t *csires5 = calloc(1,sizeof(*csires5)); csires5->csi_ResourceConfigId=5; @@ -1782,7 +1812,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires50); csires5->bwp_Id = 1; csires5->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires5); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires5); NR_CSI_ResourceConfig_t *csires6 = calloc(1,sizeof(*csires6)); csires6->csi_ResourceConfigId=6; @@ -1795,7 +1825,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires60); csires6->bwp_Id = 1; csires6->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires6); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires6); NR_CSI_ResourceConfig_t *csires7 = calloc(1,sizeof(*csires7)); csires7->csi_ResourceConfigId=7; @@ -1808,7 +1838,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires70); csires7->bwp_Id = 1; csires7->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires7); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires7); NR_CSI_ResourceConfig_t *csires8 = calloc(1,sizeof(*csires8)); csires8->csi_ResourceConfigId=8; @@ -1821,7 +1851,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires80); csires8->bwp_Id = 1; csires8->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires8); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires8); NR_CSI_ResourceConfig_t *csires9 = calloc(1,sizeof(*csires9)); csires9->csi_ResourceConfigId=9; @@ -1834,7 +1864,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires90); csires9->bwp_Id = 1; csires9->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires9); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires9); csi_MeasConfig->csi_ReportConfigToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_ReportConfigToAddModList)); csi_MeasConfig->csi_ReportConfigToReleaseList = NULL; @@ -1862,8 +1892,9 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco csirep0->reportFreqConfiguration->csi_ReportingBand=calloc(1,sizeof(*csirep0->reportFreqConfiguration->csi_ReportingBand)); - AssertFatal(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id>0,"firstActiveDownlinkBWP_Id %d\n",(int)*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id); + //AssertFatal(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id>0,"firstActiveDownlinkBWP_Id %d\n",(int)*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id); int NPRB = NRRIV2BW(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id-1]->bwp_Common->genericParameters.locationAndBandwidth,275); + //int NPRB = NRRIV2BW(28875,275); int sbsize = get_subband_size(NPRB,0); int numsb = NPRB/sbsize; if (NPRB%sbsize == 0) numsb++; @@ -1992,12 +2023,22 @@ void fill_default_reconfig(NR_ServingCellConfigCommon_t *servingcellconfigcommon // radioBearerConfig reconfig->radioBearerConfig=NULL; // secondaryCellGroup - fill_default_secondaryCellGroup(servingcellconfigcommon,secondaryCellGroup,0,0,n_physical_antenna_ports,initial_csi_index); +#if 0 +NR_ServingCellConfigCommon_t z = *servingcellconfigcommon; +NR_ARFCN_ValueNR_t ssb_freq = 641272; //642208; //642208 is for SSB position = ptA + 82 RBs with ptA at 3600MHz //642256; //642016; //642256; +z.downlinkConfigCommon->frequencyInfoDL->absoluteFrequencySSB = &ssb_freq; +fill_default_secondaryCellGroup(&z,secondaryCellGroup,1,1,n_physical_antenna_ports,initial_csi_index); +#else + fill_default_secondaryCellGroup(servingcellconfigcommon,secondaryCellGroup,1,1,n_physical_antenna_ports,initial_csi_index); +#endif xer_fprint(stdout, &asn_DEF_NR_CellGroupConfig, (const void*)secondaryCellGroup); +//void *x = secondaryCellGroup->spCellConfig->reconfigurationWithSync->spCellConfigCommon->tdd_UL_DL_ConfigurationCommon; +//secondaryCellGroup->spCellConfig->reconfigurationWithSync->spCellConfigCommon->tdd_UL_DL_ConfigurationCommon = NULL; char scg_buffer[1024]; asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CellGroupConfig, NULL, (void *)secondaryCellGroup, scg_buffer, 1024); AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", enc_rval.failed_type->name, enc_rval.encoded); +//secondaryCellGroup->spCellConfig->reconfigurationWithSync->spCellConfigCommon->tdd_UL_DL_ConfigurationCommon = x; reconfig->secondaryCellGroup = calloc(1,sizeof(*reconfig->secondaryCellGroup)); diff --git a/openair2/X2AP/x2ap_eNB_generate_messages.c b/openair2/X2AP/x2ap_eNB_generate_messages.c index c44d608883..78a93e9712 100644 --- a/openair2/X2AP/x2ap_eNB_generate_messages.c +++ b/openair2/X2AP/x2ap_eNB_generate_messages.c @@ -1748,8 +1748,8 @@ int x2ap_gNB_generate_ENDC_x2_SgNB_addition_request_ACK( x2ap_eNB_instance_t *in e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.present = X2AP_E_RABs_Admitted_ToBeAdded_SgNBAddReqAck_Item__resource_configuration_PR_sgNBPDCPpresent; INT32_TO_OCTET_STRING(x2ap_sgnb_addition_req_ACK->e_rabs_admitted_tobeadded[i].gtp_teid, &e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.gTP_TEID); - e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.size = e_SCG_rabs_tobeadded.eNB_addr.length/8; - e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.bits_unused = e_SCG_rabs_tobeadded.eNB_addr.length%8; + e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.size = x2ap_sgnb_addition_req_ACK->e_rabs_admitted_tobeadded[i].gnb_addr.length/8; + e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.bits_unused = x2ap_sgnb_addition_req_ACK->e_rabs_admitted_tobeadded[i].gnb_addr.length%8; e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.buf = calloc(1, e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.size); diff --git a/openair2/X2AP/x2ap_eNB_handler.c b/openair2/X2AP/x2ap_eNB_handler.c index e950fa76fd..f518df1fd9 100644 --- a/openair2/X2AP/x2ap_eNB_handler.c +++ b/openair2/X2AP/x2ap_eNB_handler.c @@ -1756,6 +1756,15 @@ int x2ap_gNB_handle_ENDC_sGNB_addition_request (instance_t instance, X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].sgw_addr.length = e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.size * 8 - e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.bits_unused; +LOG_I(RRC,"x2u tunnel: index %d target sgw ip %d.%d.%d.%d length %d gtp teid %u\n", + i, + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].sgw_addr.buffer[0], + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].sgw_addr.buffer[1], + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].sgw_addr.buffer[2], + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].sgw_addr.buffer[3], + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].sgw_addr.length, + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].gtp_teid); + OCTET_STRING_TO_INT32(&e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.gTP_TEID, X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].gtp_teid); } diff --git a/openair3/GTPV1-U/gtpv1u_eNB.c b/openair3/GTPV1-U/gtpv1u_eNB.c index f15f295548..f095cce67d 100644 --- a/openair3/GTPV1-U/gtpv1u_eNB.c +++ b/openair3/GTPV1-U/gtpv1u_eNB.c @@ -943,6 +943,8 @@ gtpv1u_create_s1u_tunnel( memcpy(&create_tunnel_resp_pP->enb_addr.buffer, &RC.gtpv1u_data_g->enb_ip_address_for_S1u_S12_S4_up, sizeof (in_addr_t)); + + LOG_I(GTPU,"Configured GTPu address : %x\n",RC.gtpv1u_data_g->enb_ip_address_for_S1u_S12_S4_up); create_tunnel_resp_pP->enb_addr.length = sizeof (in_addr_t); addrs_length_in_bytes = create_tunnel_req_pP->sgw_addr[i].length / 8; AssertFatal((addrs_length_in_bytes == 4) || @@ -971,6 +973,15 @@ gtpv1u_create_s1u_tunnel( gtpv1u_ue_data_p->bearers[eps_bearer_id - GTPV1U_BEARER_OFFSET].teid_sgw = create_tunnel_req_pP->sgw_S1u_teid[i]; gtpv1u_ue_data_p->num_bearers++; create_tunnel_resp_pP->enb_S1u_teid[i] = s1u_teid; + + LOG_I(GTPU,"Copied to create_tunnel_resp tunnel: index %d target gNB ip %d.%d.%d.%d length %d gtp teid %u\n", + i, + create_tunnel_resp_pP->enb_addr.buffer[0], + create_tunnel_resp_pP->enb_addr.buffer[1], + create_tunnel_resp_pP->enb_addr.buffer[2], + create_tunnel_resp_pP->enb_addr.buffer[3], + create_tunnel_resp_pP->enb_addr.length, + create_tunnel_resp_pP->enb_S1u_teid[i]); } else { create_tunnel_resp_pP->enb_S1u_teid[i] = 0; create_tunnel_resp_pP->status = 0xFF; From 817afd999b120b776ac5e9920fc9b0187d200fef Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Tue, 24 Mar 2020 16:00:52 +0100 Subject: [PATCH 100/553] fixing reference point for k in pusch dmrs --- openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c | 5 ++++- openair1/PHY/NR_REFSIG/nr_dmrs_rx.c | 7 ++++--- openair1/PHY/NR_REFSIG/nr_refsig.h | 1 + openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 4 +++- 4 files changed, 12 insertions(+), 5 deletions(-) diff --git a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c index 64672f2b7a..ce23b19d27 100644 --- a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c +++ b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c @@ -116,7 +116,10 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, //------------------generate DMRS------------------// - nr_pusch_dmrs_rx(gNB, Ns, gNB->nr_gold_pusch_dmrs[pusch_pdu->scid][Ns][symbol], &pilot[0], 1000, 0, nb_rb_pusch, pusch_pdu->dmrs_config_type); + if (pusch_pdu->transform_precoding) // if transform precoding is disabled + nr_pusch_dmrs_rx(gNB, Ns, gNB->nr_gold_pusch_dmrs[pusch_pdu->scid][Ns][symbol], &pilot[0], 1000, 0, nb_rb_pusch, pusch_pdu->rb_start*NR_NB_SC_PER_RB, pusch_pdu->dmrs_config_type); + else + nr_pusch_dmrs_rx(gNB, Ns, gNB->nr_gold_pusch_dmrs[pusch_pdu->scid][Ns][symbol], &pilot[0], 1000, 0, nb_rb_pusch, 0, pusch_pdu->dmrs_config_type); //------------------------------------------------// diff --git a/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c b/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c index 443e012ac0..b1b038e918 100644 --- a/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c +++ b/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c @@ -45,7 +45,7 @@ int wt1[8][2] = {{1,1},{1,1},{1,1},{1,1},{1,-1},{1,-1},{1,-1},{1,-1}}; int wf2[12][2] = {{1,1},{1,-1},{1,1},{1,-1},{1,1},{1,-1},{1,1},{1,1},{1,1},{1,-1},{1,1},{1,1}}; int wt2[12][2] = {{1,1},{1,1},{1,1},{1,1},{1,1},{1,1},{1,-1},{1,-1},{1,-1},{1,-1},{1,-1},{1,-1}}; - +// complex conjugate of mod table short nr_rx_mod_table[14] = {0,0,23170,-23170,-23170,23170,23170,-23170,23170,23170,-23170,-23170,-23170,23170}; short nr_rx_nmod_table[14] = {0,0,-23170,23170,23170,-23170,-23170,23170,-23170,-23170,23170,23170,23170,-23170}; @@ -57,6 +57,7 @@ int nr_pusch_dmrs_rx(PHY_VARS_gNB *gNB, unsigned short p, unsigned char lp, unsigned short nb_pusch_rb, + uint32_t re_offset, uint8_t dmrs_type) { int8_t w, nb_dmrs; @@ -66,7 +67,6 @@ int nr_pusch_dmrs_rx(PHY_VARS_gNB *gNB, typedef int array_of_w[2]; array_of_w *wf; array_of_w *wt; - wf = (dmrs_type==pusch_dmrs_type1) ? wf1 : wf2; wt = (dmrs_type==pusch_dmrs_type1) ? wt1 : wt2; @@ -76,7 +76,7 @@ int nr_pusch_dmrs_rx(PHY_VARS_gNB *gNB, if ((p>=1000) && (p<((dmrs_type==pusch_dmrs_type1) ? 1008 : 1012))) { if (gNB->frame_parms.Ncp == NORMAL) { nb_dmrs = ((dmrs_type==pusch_dmrs_type1) ? 6:4); - for (int i=0; i>5], (((nr_gold_pusch[(i<<1)>>5])>>((i<<1)&0x1f))&1), (((nr_gold_pusch[((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1), ((int16_t*)output)[i<<1], ((int16_t*)output)[(i<<1)+1]); #endif + } } else { LOG_E(PHY,"extended cp not supported for PUSCH DMRS yet\n"); diff --git a/openair1/PHY/NR_REFSIG/nr_refsig.h b/openair1/PHY/NR_REFSIG/nr_refsig.h index 5af0e88099..9934b2163e 100644 --- a/openair1/PHY/NR_REFSIG/nr_refsig.h +++ b/openair1/PHY/NR_REFSIG/nr_refsig.h @@ -48,5 +48,6 @@ int nr_pusch_dmrs_rx(PHY_VARS_gNB *gNB, unsigned short p, unsigned char lp, unsigned short nb_pusch_rb, + uint32_t re_offset, uint8_t dmrs_type); #endif diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index b06dcd0a23..9da4c9f854 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -473,6 +473,8 @@ void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t pusch_pdu->dmrs_config_type = 0; pusch_pdu->ul_dmrs_scrambling_id = *scc->physCellId; //If provided and the PUSCH is not a msg3 PUSCH, otherwise, L2 should set this to physical cell id. pusch_pdu->scid = 0; //DMRS sequence initialization [TS38.211, sec 6.4.1.1.1]. Should match what is sent in DCI 0_1, otherwise set to 0. + pusch_pdu->dmrs_ports = 1; // 6.2.2 in 38.214 only port 0 to be used + pusch_pdu->num_dmrs_cdm_grps_no_data = 2; // no data in dmrs symbols as in 6.2.2 in 38.214 pusch_pdu->resource_alloc = 1; //type 1 pusch_pdu->rb_start = ra->msg3_first_rb + ibwp_start - abwp_start; // as for 6.3.1.7 in 38.211 if (ra->msg3_nb_rb > pusch_pdu->bwp_size) @@ -621,7 +623,7 @@ void nr_generate_Msg2(module_id_t module_idP, pdsch_pdu_rel15->dmrsConfigType = 0; pdsch_pdu_rel15->dlDmrsScramblingId = *scc->physCellId; pdsch_pdu_rel15->SCID = 0; - pdsch_pdu_rel15->numDmrsCdmGrpsNoData = 1; + pdsch_pdu_rel15->numDmrsCdmGrpsNoData = 2; pdsch_pdu_rel15->dmrsPorts = 1; pdsch_pdu_rel15->resourceAlloc = 1; pdsch_pdu_rel15->rbStart = 0; From 48a61ab5988c4975ad6a2deca38550e93db43366 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Wed, 25 Mar 2020 16:03:43 +0100 Subject: [PATCH 101/553] ENDC path switch procedures: Small modification at generation of E-RAB Modification Indication message --- openair3/S1AP/s1ap_eNB_nas_procedures.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openair3/S1AP/s1ap_eNB_nas_procedures.c b/openair3/S1AP/s1ap_eNB_nas_procedures.c index 1fb8a47d97..15cdb5d8e6 100644 --- a/openair3/S1AP/s1ap_eNB_nas_procedures.c +++ b/openair3/S1AP/s1ap_eNB_nas_procedures.c @@ -1806,7 +1806,7 @@ int s1ap_eNB_generate_E_RAB_Modification_Indication( int num_e_rabs_tobemodified = e_rab_modification_ind->nb_of_e_rabs_tobemodified; int num_e_rabs_nottobemodified = e_rab_modification_ind->nb_of_e_rabs_nottobemodified; - uint16_t CSG_id = 0; + uint32_t CSG_id = 0; if ((ue_context_p = s1ap_eNB_get_ue_context(s1ap_eNB_instance_p, e_rab_modification_ind->eNB_ue_s1ap_id)) == NULL) { @@ -1913,10 +1913,10 @@ int s1ap_eNB_generate_E_RAB_Modification_Indication( ie->criticality = S1AP_Criticality_reject; ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_CSGMembershipInfo; ie->value.choice.CSGMembershipInfo.cSGMembershipStatus = S1AP_CSGMembershipStatus_member; - INT16_TO_BIT_STRING(CSG_id, &ie->value.choice.CSGMembershipInfo.cSG_Id); + INT32_TO_BIT_STRING(CSG_id, &ie->value.choice.CSGMembershipInfo.cSG_Id); + ie->value.choice.CSGMembershipInfo.cSG_Id.bits_unused=5; ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); - - + if (s1ap_eNB_encode_pdu(&pdu, &buffer, &len) < 0) { S1AP_ERROR("Failed to encode S1 E-RAB modification indication \n"); return -1; From e451ff54effe3ccc399fac4cc99ee006f58e6b89 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Thu, 26 Mar 2020 09:34:07 +0100 Subject: [PATCH 102/553] fixing compilation errors and one file left behind --- openair1/PHY/NR_REFSIG/dmrs_nr.c | 3 - .../PHY/NR_TRANSPORT/nr_ulsch_demodulation.c | 10 +- openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h | 2 +- openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c | 111 ++---------------- openair1/SCHED_NR/phy_procedures_nr_gNB.c | 2 - openair2/LAYER2/NR_MAC_UE/mac_proto.h | 3 +- openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 3 +- .../LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c | 28 ++++- 8 files changed, 41 insertions(+), 121 deletions(-) diff --git a/openair1/PHY/NR_REFSIG/dmrs_nr.c b/openair1/PHY/NR_REFSIG/dmrs_nr.c index ea1e0a639a..34c887be30 100644 --- a/openair1/PHY/NR_REFSIG/dmrs_nr.c +++ b/openair1/PHY/NR_REFSIG/dmrs_nr.c @@ -141,9 +141,6 @@ uint8_t is_dmrs_symbol(uint8_t l, is_dmrs_freq = 0; is_dmrs_time = 0; - if (mapping_type==typeB) - l -= start_symbol; - AssertFatal(l >= 0,"Check DMRS configuration (start_symbol) !\n"); diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c index 20d03485b2..d304f26d02 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c @@ -307,12 +307,6 @@ void nr_ulsch_extract_rbs_single(int32_t **rxdataF, printf("re = %d, symbol = %d\n", re, symbol); #endif - if (symbol == dmrs_symbol) - is_dmrs_re = (re == get_dmrs_freq_idx_ul(n, k_prime, delta, pusch_pdu->dmrs_config_type)); - else - is_dmrs_re = 0; - - if ( is_dmrs_re == 0 && is_ptrs_symbol_flag == 0) { rxF_ext[rxF_ext_index] = (rxF[ ((start_re + re)*2) % (frame_parms->ofdm_symbol_size*2)]); @@ -1027,7 +1021,7 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, unsigned char harq_pid) { - uint8_t first_symbol_flag, aarx, aatx, dmrs_symbol_flag, ptrs_symbol_flag; // dmrs_symbol_flag, a flag to indicate DMRS REs in current symbol + uint8_t aarx, aatx, dmrs_symbol_flag, ptrs_symbol_flag; // dmrs_symbol_flag, a flag to indicate DMRS REs in current symbol uint32_t nb_re_pusch, bwp_start_subcarrier; uint8_t L_ptrs = 0; // PTRS parameter int avgs; @@ -1038,7 +1032,6 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, dmrs_symbol_flag = 0; ptrs_symbol_flag = 0; - first_symbol_flag = 0; gNB->pusch_vars[UE_id]->ptrs_sc_per_ofdm_symbol = 0; if(symbol == rel15_ul->start_symbol_index){ @@ -1046,7 +1039,6 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, gNB->pusch_vars[UE_id]->dmrs_symbol = 0; gNB->pusch_vars[UE_id]->cl_done = 0; gNB->pusch_vars[UE_id]->ptrs_symbols = 0; - first_symbol_flag = 1; if ( ((rel15_ul->pdu_bit_map)>>2)& 0x01 ) { // if there is ptrs pdu L_ptrs = 1<<(rel15_ul->pusch_ptrs.ptrs_time_density); diff --git a/openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h b/openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h index fb80f0e124..6326ed9446 100644 --- a/openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h +++ b/openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h @@ -90,7 +90,7 @@ void phy_adjust_gain_nr(PHY_VARS_NR_UE *ue, uint32_t rx_power_fil_dB, uint8_t eNB_id); -int16_t get_nr_PL(PHY_VARS_NR_UE *ue,uint8_t gNB_index); +int16_t get_nr_PL(uint8_t Mod_id, uint8_t CC_id, uint8_t gNB_index); #endif diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c index 19bd3c6f24..f262400f5d 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c @@ -126,14 +126,9 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, n_rnti = 0x1234; Nid_cell = 0; N_PRB_oh = 0; // higher layer (RRC) parameter xOverhead in PUSCH-ServingCellConfig -<<<<<<< HEAD - - mapping_type = UE->pusch_config.pusch_TimeDomainResourceAllocation[0]->mappingType; - int dmrs_symb; -======= number_dmrs_symbols = 0; uint8_t mapping_type = UE->pusch_config.pusch_TimeDomainResourceAllocation[0]->mappingType; ->>>>>>> develop + for (cwd_index = 0;cwd_index < num_of_codewords; cwd_index++) { @@ -142,47 +137,23 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, start_symbol = harq_process_ul_ue->start_symbol; -<<<<<<< HEAD - dmrs_symb=-1; - number_dmrs_symbols = 0; - - for (i = start_symbol; i < start_symbol + harq_process_ul_ue->number_of_symbols; i++) { - number_dmrs_symbols += is_dmrs_symbol(i, -======= for (i = start_symbol; i < start_symbol + harq_process_ul_ue->number_of_symbols; i++) number_dmrs_symbols += is_dmrs_symbol((mapping_type)?i-start_symbol:i, ->>>>>>> develop 0, 0, 0, 0, 0, harq_process_ul_ue->number_of_symbols, -<<<<<<< HEAD - start_symbol, - &UE->dmrs_UplinkConfig, - mapping_type, -======= UE->pusch_config.dmrs_UplinkConfig.pusch_dmrs_type, ->>>>>>> develop frame_parms->ofdm_symbol_size); - if (dmrs_symb == -1 && number_dmrs_symbols == 1) dmrs_symb = i; - } - AssertFatal(number_dmrs_symbols ==1,"number_dmrs_symbols != 1\n"); - AssertFatal(dmrs_symb >=0,"dmrs_symb < 0\n"); - LOG_D(PHY,"pusch: start_symbol %d, dmrs_symbol %d, num_symbols %d\n", - start_symbol,dmrs_symb,harq_process_ul_ue->number_of_symbols); ulsch_ue->length_dmrs = number_dmrs_symbols; // pusch.MaxLenght is redundant here as number_dmrs_symbols // contains all dmrs symbols even for double symbol dmrs ulsch_ue->rnti = n_rnti; ulsch_ue->Nid_cell = Nid_cell; -<<<<<<< HEAD ulsch_ue->nb_re_dmrs = 12;//((UE->dmrs_UplinkConfig.pusch_dmrs_type == pusch_dmrs_type1)?6:4)*number_dmrs_symbols; -======= - ulsch_ue->nb_re_dmrs = ((UE->pusch_config.dmrs_UplinkConfig.pusch_dmrs_type == pusch_dmrs_type1)?6:4); ->>>>>>> develop N_RE_prime = NR_NB_SC_PER_RB*harq_process_ul_ue->number_of_symbols - ulsch_ue->nb_re_dmrs*number_dmrs_symbols - N_PRB_oh; @@ -415,17 +386,13 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, uint8_t l_ref; uint16_t m=0, n=0, dmrs_idx=0, ptrs_idx = 0; - for (l=start_symbol; lnumber_of_symbols; l++) { + for (l=start_symbol; lnumber_of_symbols; l++) { k = start_sc; n = 0; dmrs_idx = 0; l_ref = (mapping_type) ? l-start_symbol : l; -<<<<<<< HEAD - if (l!=dmrs_symb) { - for (i=0; inb_rb*NR_NB_SC_PER_RB; i++) { -======= for (i=0; inb_rb*NR_NB_SC_PER_RB; i++) { sample_offsetF = l*frame_parms->ofdm_symbol_size + k; @@ -491,81 +458,21 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, ptrs_idx++; } else { ->>>>>>> develop - sample_offsetF = l*frame_parms->ofdm_symbol_size + k; ((int16_t*)txdataF[ap])[(sample_offsetF)<<1] = ((int16_t *) ulsch_ue->y)[m<<1]; ((int16_t*)txdataF[ap])[((sample_offsetF)<<1) + 1] = ((int16_t *) ulsch_ue->y)[(m<<1) + 1]; -#ifdef DEBUG_PUSCH_MAPPING - printf("m %d\t l %d \t k %d \t txdataF: %d %d\n", + #ifdef DEBUG_PUSCH_MAPPING + printf("m %d\t l %d \t k %d \t txdataF: %d %d\n", m, l, k, ((int16_t*)txdataF[ap])[(sample_offsetF)<<1], ((int16_t*)txdataF[ap])[((sample_offsetF)<<1) + 1]); -#endif - + #endif + m++; - if (++k >= frame_parms->ofdm_symbol_size) - k -= frame_parms->ofdm_symbol_size; - - } - } - else { + } - for (i=0; inb_rb*NR_NB_SC_PER_RB; i++) { - - sample_offsetF = l*frame_parms->ofdm_symbol_size + k; - is_dmrs = 0; - - is_dmrs = is_dmrs_symbol(l, - k, - start_sc, - k_prime, - n, - delta, - harq_process_ul_ue->number_of_symbols, - start_symbol, - &UE->dmrs_UplinkConfig, - mapping_type, - frame_parms->ofdm_symbol_size); - if (is_dmrs == 1) { - - nr_modulation(pusch_dmrs[l][0], n_dmrs*2, DMRS_MOD_ORDER, mod_dmrs); // currently only codeword 0 is modulated. Qm = 2 as DMRS is QPSK modulated - - ((int16_t*)txdataF[ap])[(sample_offsetF)<<1] = (Wt[l_prime[0]]*Wf[k_prime]*AMP*mod_dmrs[dmrs_idx<<1]) >> 15; - ((int16_t*)txdataF[ap])[((sample_offsetF)<<1) + 1] = (Wt[l_prime[0]]*Wf[k_prime]*AMP*mod_dmrs[(dmrs_idx<<1) + 1]) >> 15; - -#ifdef DEBUG_PUSCH_MAPPING - printf("dmrs_idx %d\t l %d \t k %d \t k_prime %d \t n %d \t dmrs: %d %d\n", - dmrs_idx, l, k, k_prime, n, ((int16_t*)txdataF[ap])[(sample_offsetF)<<1], - ((int16_t*)txdataF[ap])[((sample_offsetF)<<1) + 1]); -#endif - - - dmrs_idx++; - k_prime++; - k_prime&=1; - n+=(k_prime)?0:1; - } - - else { - //remove PDSCH REs from DMRS symbols for now - /* - ((int16_t*)txdataF[ap])[(sample_offsetF)<<1] = ((int16_t *) ulsch_ue->y)[m<<1]; - ((int16_t*)txdataF[ap])[((sample_offsetF)<<1) + 1] = ((int16_t *) ulsch_ue->y)[(m<<1) + 1]; - - #ifdef DEBUG_PUSCH_MAPPING - printf("m %d\t l %d \t k %d \t txdataF: %d %d\n", - m, l, k, ((int16_t*)txdataF[ap])[(sample_offsetF)<<1], - ((int16_t*)txdataF[ap])[((sample_offsetF)<<1) + 1]); - #endif - - m++; - */ - } - - if (++k >= frame_parms->ofdm_symbol_size) - k -= frame_parms->ofdm_symbol_size; - } + if (++k >= frame_parms->ofdm_symbol_size) + k -= frame_parms->ofdm_symbol_size; } } } diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index 027954a5a5..4c1ece8c5f 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -235,8 +235,6 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH G = nr_get_G(pusch_pdu->rb_size, number_symbols, nb_re_dmrs, - pusch_pdu->qam_mod_order, - pusch_pdu->nrOfLayers); number_dmrs_symbols, // number of dmrs symbols irrespective of single or double symbol dmrs pusch_pdu->qam_mod_order, pusch_pdu->nrOfLayers); diff --git a/openair2/LAYER2/NR_MAC_UE/mac_proto.h b/openair2/LAYER2/NR_MAC_UE/mac_proto.h index afb161b337..d6a586b1c9 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_proto.h @@ -163,7 +163,8 @@ unsigned char nr_generate_ulsch_pdu(uint8_t *sdus_payload, uint16_t truncated_bsr, uint16_t short_bsr, uint16_t long_bsr, - unsigned short post_padding); + unsigned short post_padding, + uint16_t buflen); int8_t nr_ue_process_dlsch(module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_indication_t *dci_ind, void *pduP, uint32_t pdu_len); diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c index 138d37d394..decdddbe31 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -470,7 +470,8 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, 0, // truncated bsr 0, // short bsr 0, // long_bsr - post_padding); // post_padding + post_padding, + 0); // Padding: fill remainder with 0 if (post_padding > 0){ diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c index 5adb71d8d8..7a46ce8d85 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c @@ -33,6 +33,7 @@ #include "executables/softmodem-common.h" //#define ENABLE_MAC_PAYLOAD_DEBUG 1 + void nr_process_mac_pdu( module_id_t module_idP, uint8_t CC_id, @@ -88,7 +89,13 @@ void nr_process_mac_pdu( /*#ifdef DEBUG_HEADER_PARSING LOG_D(MAC, "[UE] LCID %d, PDU length %d\n", ((NR_MAC_SUBHEADER_FIXED *)pdu_ptr)->LCID, pdu_len); #endif*/ - + case UL_SCH_LCID_RECOMMENDED_BITRATE_QUERY: + // 38.321 Ch6.1.3.20 + mac_ce_len = 2; + break; + case UL_SCH_LCID_CONFIGURED_GRANT_CONFIRMATION: + // 38.321 Ch6.1.3.7 + break; case UL_SCH_LCID_S_BSR: //38.321 section 6.1.3.1 //fixed length @@ -171,6 +178,24 @@ void nr_process_mac_pdu( // end of MAC PDU, can ignore the rest. break; + // MAC SDUs + case UL_SCH_LCID_SRB1: + // todo + break; + case UL_SCH_LCID_SRB2: + // todo + break; + case UL_SCH_LCID_SRB3: + // todo + break; + case UL_SCH_LCID_CCCH_MSG3: + // todo + break; + case UL_SCH_LCID_CCCH: + // todo + mac_subheader_len = 2; + break; + case UL_SCH_LCID_DTCH: // check if LCID is valid at current time. if(((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->F){ @@ -230,7 +255,6 @@ void nr_process_mac_pdu( } } - /* * When data are received on PHY and transmitted to MAC */ From ce923e59edbe662e5870658f69f84a5d6d8b4101 Mon Sep 17 00:00:00 2001 From: Thomas Schlichter Date: Thu, 26 Mar 2020 09:55:22 +0100 Subject: [PATCH 103/553] fix critical "assignment from incompatible pointer type" warnings --- openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c | 4 ++-- openair1/SCHED_NR_UE/fapi_nr_ue_l1.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c index 60818be9b3..43545bada2 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c @@ -159,14 +159,14 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, switch (type) { case SI_PDSCH: - pdsch_vars = ue->pdsch_vars_SI[ue->current_thread_id[nr_tti_rx]]; + pdsch_vars = ue->pdsch_vars_SI; dlsch = &ue->dlsch_SI[eNB_id]; dlsch0_harq = dlsch[0]->harq_processes[harq_pid]; beamforming_mode = 0; break; case RA_PDSCH: - pdsch_vars = ue->pdsch_vars_ra[ue->current_thread_id[nr_tti_rx]]; + pdsch_vars = ue->pdsch_vars_ra; dlsch = &ue->dlsch_ra[eNB_id]; dlsch0_harq = dlsch[0]->harq_processes[harq_pid]; beamforming_mode = 0; diff --git a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c index cb53fe4920..e324980af7 100644 --- a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c +++ b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c @@ -188,7 +188,7 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ case (FAPI_NR_UL_CONFIG_TYPE_PRACH): // prach config pdu fp = &PHY_vars_UE_g[module_id][cc_id]->frame_parms; - prach_resources = &PHY_vars_UE_g[module_id][cc_id]->prach_resources[gNB_id]; + prach_resources = PHY_vars_UE_g[module_id][cc_id]->prach_resources[gNB_id]; prach_config_common = &fp->prach_config_common; prach_config_pdu = &ul_config->ul_config_list[i].prach_config_pdu; From 4c30e6d3a5284f8a6220508967456b8bf4acf51b Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Thu, 26 Mar 2020 12:29:20 +0100 Subject: [PATCH 104/553] new file for prach dummy functions to avoid compilation failures on physim --- .../SIMULATION/NR_PHY/nr_dummy_functions.c | 341 +---------------- .../NR_PHY/nr_dummy_functions_prach.c | 348 ++++++++++++++++++ 2 files changed, 349 insertions(+), 340 deletions(-) create mode 100644 openair1/SIMULATION/NR_PHY/nr_dummy_functions_prach.c diff --git a/openair1/SIMULATION/NR_PHY/nr_dummy_functions.c b/openair1/SIMULATION/NR_PHY/nr_dummy_functions.c index 8aa5c3e81f..c7ee863c35 100644 --- a/openair1/SIMULATION/NR_PHY/nr_dummy_functions.c +++ b/openair1/SIMULATION/NR_PHY/nr_dummy_functions.c @@ -1,348 +1,9 @@ int oai_nfapi_hi_dci0_req(nfapi_hi_dci0_request_t *hi_dci0_req) { return(0); } int oai_nfapi_tx_req(nfapi_tx_request_t *tx_req) { return(0); } int oai_nfapi_dl_config_req(nfapi_dl_config_request_t *dl_config_req) { return(0); } -int oai_nfapi_ul_config_req(nfapi_ul_config_request_t *ul_config_req) { return(0); } +//int oai_nfapi_ul_config_req(nfapi_ul_config_request_t *ul_config_req) { return(0); } //int oai_nfapi_nr_dl_config_req(nfapi_nr_dl_config_request_t *dl_config_req) { return(0); } int32_t get_uldl_offset(int nr_bandP) { return(0); } NR_IF_Module_t *NR_IF_Module_init(int Mod_id) {return(NULL);} int dummy_nr_ue_dl_indication(nr_downlink_indication_t *dl_info) { return(0); } int dummy_nr_ue_ul_indication(nr_uplink_indication_t *ul_info) { return(0); } -/* - * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. - * The OpenAirInterface Software Alliance licenses this file to You under - * the OAI Public License, Version 1.1 (the "License"); you may not use this file - * except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.openairinterface.org/?page_id=698 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - *------------------------------------------------------------------------------- - * For more information about the OpenAirInterface (OAI) Software Alliance: - * contact@openairinterface.org - */ - -/*! \file ra_procedures.c - * \brief Routines for UE MAC-layer Random Access procedures (TS 38.321, Release 15) - * \author R. Knopp, Navid Nikaein, Guido Casati - * \date 2019 - * \version 0.1 - * \company Eurecom - * \email: knopp@eurecom.fr navid.nikaein@eurecom.fr, guido.casati@iis.fraunhofer.de - * \note - * \warning - */ - -#include "mac.h" - -/* -#include "common/utils/LOG/vcd_signal_dumper.h" -#include "PHY_INTERFACE/phy_interface_extern.h" -#include "SCHED_UE/sched_UE.h" -#include "COMMON/mac_rrc_primitives.h" -#include "RRC/LTE/rrc_extern.h" -#include "RRC/L2_INTERFACE/openair_rrc_L2_interface.h" -#include "common/utils/LOG/log.h" -#include "UTIL/OPT/opt.h" -#include "OCG.h" -#include "OCG_extern.h" -#include "PHY/LTE_ESTIMATION/lte_estimation.h"*/ - -/* Tools */ -#include "SIMULATION/TOOLS/sim.h" // for taus - -/* RRC */ -#include "NR_RACH-ConfigCommon.h" - -/* PHY */ -#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" -#include "PHY/defs_common.h" -#include "PHY/defs_nr_common.h" -#include "PHY/NR_UE_ESTIMATION/nr_estimation.h" - -/* MAC */ -#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" -#include "NR_MAC_COMMON/nr_mac.h" -#include "LAYER2/NR_MAC_UE/mac_proto.h" - -extern int64_t table_6_3_3_2_2_prachConfig_Index [256][9]; -extern int64_t table_6_3_3_2_3_prachConfig_Index [256][9]; - -//extern uint8_t nfapi_mode; - -// WIP -// This routine implements Section 5.1.2 (UE Random Access Resource Selection) -// and Section 5.1.3 (Random Access Preamble Transmission) from 3GPP TS 38.321 -void nr_get_prach_resources(module_id_t mod_id, - int CC_id, - uint8_t gNB_id, - uint8_t t_id, - uint8_t first_Msg3, - NR_PRACH_RESOURCES_t *prach_resources, - NR_RACH_ConfigDedicated_t * rach_ConfigDedicated){ - - NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); - NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon; - // NR_BeamFailureRecoveryConfig_t *beam_failure_recovery_config = &mac->RA_BeamFailureRecoveryConfig; // todo - - int messagePowerOffsetGroupB, messageSizeGroupA, PLThreshold, sizeOfRA_PreamblesGroupA, numberOfRA_Preambles, i, deltaPreamble_Msg3; - uint8_t noGroupB = 0, s_id, f_id, ul_carrier_id, msg1_FDM, prach_ConfigIndex, SFN_nbr, Msg3_size; - - // NR_RSRP_Range_t rsrp_ThresholdSSB; // todo - - /////////////////////////////////////////////////////////// - //////////* UE Random Access Resource Selection *////////// - /////////////////////////////////////////////////////////// - - // todo: - // - switch initialisation cases - // -- RA initiated by beam failure recovery operation (subclause 5.17 TS 38.321) - // --- SSB selection, set prach_resources->ra_PreambleIndex - // -- RA initiated by PDCCH: ra_preamble_index provided by PDCCH && ra_PreambleIndex != 0b000000 - // --- set PREAMBLE_INDEX to ra_preamble_index - // --- select the SSB signalled by PDCCH - // -- RA initiated for SI request: - // --- SSB selection, set prach_resources->ra_PreambleIndex - - // if (rach_ConfigDedicated) { // This is for network controlled Mobility - // // operation for contention-free RA resources when: - // // - available SSB with SS-RSRP above rsrp-ThresholdSSB: SSB selection - // // - availalbe CSI-RS with CSI-RSRP above rsrp-ThresholdCSI-RS: CSI-RS selection - // prach_resources->ra_PreambleIndex = rach_ConfigDedicated->ra_PreambleIndex; - // return; - // } - - //////////* Contention-based RA preamble selection *////////// - // todo: - // - selection of SSB with SS-RSRP above rsrp-ThresholdSSB else select any SSB - // - todo determine next available PRACH occasion - - // rsrp_ThresholdSSB = *nr_rach_ConfigCommon->rsrp_ThresholdSSB; - - AssertFatal(mac->nr_rach_ConfigCommon != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); - - nr_rach_ConfigCommon = mac->nr_rach_ConfigCommon; - - Msg3_size = mac->RA_Msg3_size; - numberOfRA_Preambles = *nr_rach_ConfigCommon->totalNumberOfRA_Preambles; - - if (!nr_rach_ConfigCommon->groupBconfigured) { - noGroupB = 1; - } else { - // RA preambles group B is configured - // - Defining the number of RA preambles in RA Preamble Group A for each SSB */ - sizeOfRA_PreamblesGroupA = nr_rach_ConfigCommon->groupBconfigured->numberOfRA_PreamblesGroupA; - switch (nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA){ - /* - Threshold to determine the groups of RA preambles */ - case 0: - messageSizeGroupA = 56; - break; - case 1: - messageSizeGroupA = 144; - break; - case 2: - messageSizeGroupA = 208; - break; - case 3: - messageSizeGroupA = 256; - break; - case 4: - messageSizeGroupA = 282; - break; - case 5: - messageSizeGroupA = 480; - break; - case 6: - messageSizeGroupA = 640; - break; - case 7: - messageSizeGroupA = 800; - break; - case 8: - messageSizeGroupA = 1000; - break; - case 9: - messageSizeGroupA = 72; - break; - default: - AssertFatal(1 == 0,"Unknown ra_Msg3SizeGroupA %lu\n", nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA); - /* todo cases 10 -15*/ - } - - /* Power offset for preamble selection in dB */ - messagePowerOffsetGroupB = -9999; - switch (nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB){ - case 0: - messagePowerOffsetGroupB = -9999; - break; - case 1: - messagePowerOffsetGroupB = 0; - break; - case 2: - messagePowerOffsetGroupB = 5; - break; - case 3: - messagePowerOffsetGroupB = 8; - break; - case 4: - messagePowerOffsetGroupB = 10; - break; - case 5: - messagePowerOffsetGroupB = 12; - break; - case 6: - messagePowerOffsetGroupB = 15; - break; - case 7: - messagePowerOffsetGroupB = 18; - break; - default: - AssertFatal(1 == 0,"Unknown messagePowerOffsetGroupB %lu\n", nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB); - } - - // todo Msg3-DeltaPreamble should be provided from higher layers, otherwise is 0 - mac->deltaPreamble_Msg3 = 0; - deltaPreamble_Msg3 = mac->deltaPreamble_Msg3; - } - - PLThreshold = prach_resources->RA_PCMAX - nr_rach_ConfigCommon->rach_ConfigGeneric.preambleReceivedTargetPower - deltaPreamble_Msg3 - messagePowerOffsetGroupB; - - /* Msg3 has not been transmitted yet */ - if (first_Msg3 == 1) { - if (noGroupB == 1) { - // use Group A preamble - prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles; - mac->RA_usedGroupA = 1; - } else if ((Msg3_size < messageSizeGroupA) && (get_nr_PL(mod_id, CC_id, gNB_id) > PLThreshold)) { - // Group B is configured and RA preamble Group A is used - // - todo add condition on CCCH_sdu_size for initiation by CCCH - prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; - mac->RA_usedGroupA = 1; - } else { - // Group B preamble is configured and used - // the first sizeOfRA_PreamblesGroupA RA preambles belong to RA Preambles Group A - // the remaining belong to RA Preambles Group B - prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); - mac->RA_usedGroupA = 0; - } - } else { // Msg3 is being retransmitted - if (mac->RA_usedGroupA == 1 && noGroupB == 1) { - prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles; - } else if (mac->RA_usedGroupA == 1 && noGroupB == 0){ - prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; - } else { - prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); - } - } - - // todo determine next available PRACH occasion - // - if RA initiated for SI request and ra_AssociationPeriodIndex and si-RequestPeriod are configured - // - else if SSB is selected above - // - else if CSI-RS is selected above - - ///////////////////////////////////////////////////////////////////////////// - //////////* Random Access Preamble Transmission (5.1.3 TS 38.321) *////////// - ///////////////////////////////////////////////////////////////////////////// - // todo: - // - condition on notification of suspending power ramping counter from lower layer (5.1.3 TS 38.321) - // - check if SSB or CSI-RS have not changed since the selection in the last RA Preamble tranmission - // - Extend RA_rnti computation (e.g. f_id selection, ul_carrier_id are hardcoded) - - if (mac->RA_PREAMBLE_TRANSMISSION_COUNTER > 1) - mac->RA_PREAMBLE_TRANSMISSION_COUNTER++; - - prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = nr_get_Po_NOMINAL_PUSCH(prach_resources, mod_id, CC_id); - - // RA-RNTI computation (associated to PRACH occasion in which the RA Preamble is transmitted) - // 1) this does not apply to contention-free RA Preamble for beam failure recovery request - // 2) getting star_symb, SFN_nbr from table 6.3.3.2-3 (TDD and FR1 scenario) - - switch (nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FDM){ // todo this is not used - case 0: - msg1_FDM = 1; - break; - case 1: - msg1_FDM = 2; - break; - case 2: - msg1_FDM = 4; - break; - case 3: - msg1_FDM = 8; - break; - default: - AssertFatal(1 == 0,"Unknown msg1_FDM %lu\n", nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FDM); - } - - prach_ConfigIndex = nr_rach_ConfigCommon->rach_ConfigGeneric.prach_ConfigurationIndex; - - // ra_RNTI computation - // - todo: this is for TDD FR1 only - // - ul_carrier_id: UL carrier used for RA preamble transmission, hardcoded for NUL carrier - // - f_id: index of the PRACH occasion in the frequency domain - // - s_id is starting symbol of the PRACH occasion [0...14] - // - t_id is the first slot of the PRACH occasion in a system frame [0...80] - - ul_carrier_id = 0; // NUL - f_id = nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FrequencyStart; - SFN_nbr = table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][4]; - s_id = table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][5]; - - // Pick the first slot of the PRACH occasion in a system frame - for (i = 0; i < 10; i++){ - if (((SFN_nbr & (1 << i)) >> i) == 1){ - t_id = 2*i; - break; - } - } - prach_resources->ra_RNTI = 1 + s_id + 14 * t_id + 1120 * f_id + 8960 * ul_carrier_id; - mac->ra_rnti = prach_resources->ra_RNTI; - - LOG_D(MAC, "Computed ra_RNTI is %d", prach_resources->ra_RNTI); -} - -// TbD: RA_attempt_number not used -void nr_Msg1_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id){ - AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); - NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); - mac->ra_state = WAIT_RAR; - // Start contention resolution timer - mac->RA_attempt_number++; -} - -void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id){ - AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); - LOG_D(MAC,"[UE %d][RAPROC] Frame %d : Msg3_tx: Starting contention resolution timer\n", mod_id, frameP); - NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); - // start contention resolution timer - mac->RA_contention_resolution_cnt = 0; - mac->RA_contention_resolution_timer_active = 1; -} - -///////////////////////////////////////////////////////////////////////// -///////* Random Access Preamble Initialization (5.1.1 TS 38.321) */////// -///////////////////////////////////////////////////////////////////////// -/// Handling inizialization by PDCCH order, MAC entity or RRC (TS 38.300) -/// Only one RA procedure is ongoing at any point in time in a MAC entity -/// the RA procedure on a SCell shall only be initiated by PDCCH order - -// WIP -// todo TS 38.321: -// - check if carrier to use is explicitly signalled then do (1) RA CARRIER SELECTION (SUL, NUL) (2) set PCMAX -// - BWP operation (subclause 5.15 TS 38.321) -// - handle initialization by beam failure recovery -// - handle initialization by handover -// - handle transmission on DCCH using PRACH (during handover, or sending SR for example) -// - take into account MAC CEs in size_sdu (currently hardcoded size to 1 MAC subPDU and 1 padding subheader) -// - fix rrc data req logic -// - retrieve TBS -// - add mac_rrc_nr_data_req_ue, etc ... -// - add the backoff condition here if we have it from a previous RA reponse which failed (i.e. backoff indicator) - - diff --git a/openair1/SIMULATION/NR_PHY/nr_dummy_functions_prach.c b/openair1/SIMULATION/NR_PHY/nr_dummy_functions_prach.c new file mode 100644 index 0000000000..e62155e54e --- /dev/null +++ b/openair1/SIMULATION/NR_PHY/nr_dummy_functions_prach.c @@ -0,0 +1,348 @@ +int oai_nfapi_hi_dci0_req(nfapi_hi_dci0_request_t *hi_dci0_req) { return(0); } +int oai_nfapi_tx_req(nfapi_tx_request_t *tx_req) { return(0); } +int oai_nfapi_dl_config_req(nfapi_dl_config_request_t *dl_config_req) { return(0); } +int oai_nfapi_ul_config_req(nfapi_ul_config_request_t *ul_config_req) { return(0); } +//int oai_nfapi_nr_dl_config_req(nfapi_nr_dl_config_request_t *dl_config_req) { return(0); } +int32_t get_uldl_offset(int nr_bandP) { return(0); } +NR_IF_Module_t *NR_IF_Module_init(int Mod_id) {return(NULL);} +int dummy_nr_ue_dl_indication(nr_downlink_indication_t *dl_info) { return(0); } +int dummy_nr_ue_ul_indication(nr_uplink_indication_t *ul_info) { return(0); } +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file ra_procedures.c + * \brief Routines for UE MAC-layer Random Access procedures (TS 38.321, Release 15) + * \author R. Knopp, Navid Nikaein, Guido Casati + * \date 2019 + * \version 0.1 + * \company Eurecom + * \email: knopp@eurecom.fr navid.nikaein@eurecom.fr, guido.casati@iis.fraunhofer.de + * \note + * \warning + */ + + +/* +#include "common/utils/LOG/vcd_signal_dumper.h" +#include "PHY_INTERFACE/phy_interface_extern.h" +#include "SCHED_UE/sched_UE.h" +#include "COMMON/mac_rrc_primitives.h" +#include "RRC/LTE/rrc_extern.h" +#include "RRC/L2_INTERFACE/openair_rrc_L2_interface.h" +#include "common/utils/LOG/log.h" +#include "UTIL/OPT/opt.h" +#include "OCG.h" +#include "OCG_extern.h" +#include "PHY/LTE_ESTIMATION/lte_estimation.h"*/ + +/* Tools */ +#include "SIMULATION/TOOLS/sim.h" // for taus + +/* RRC */ +#include "NR_RACH-ConfigCommon.h" + +/* PHY */ +#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" +#include "PHY/defs_common.h" +#include "PHY/defs_nr_common.h" +#include "PHY/NR_UE_ESTIMATION/nr_estimation.h" + +/* MAC */ +#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h" +#include "NR_MAC_COMMON/nr_mac.h" +#include "LAYER2/NR_MAC_UE/mac_proto.h" +#include "LAYER2/MAC/mac.h" + +extern int64_t table_6_3_3_2_2_prachConfig_Index [256][9]; +extern int64_t table_6_3_3_2_3_prachConfig_Index [256][9]; + +//extern uint8_t nfapi_mode; + +// WIP +// This routine implements Section 5.1.2 (UE Random Access Resource Selection) +// and Section 5.1.3 (Random Access Preamble Transmission) from 3GPP TS 38.321 +void nr_get_prach_resources(module_id_t mod_id, + int CC_id, + uint8_t gNB_id, + uint8_t t_id, + uint8_t first_Msg3, + NR_PRACH_RESOURCES_t *prach_resources, + NR_RACH_ConfigDedicated_t * rach_ConfigDedicated){ + + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon; + // NR_BeamFailureRecoveryConfig_t *beam_failure_recovery_config = &mac->RA_BeamFailureRecoveryConfig; // todo + + int messagePowerOffsetGroupB, messageSizeGroupA, PLThreshold, sizeOfRA_PreamblesGroupA, numberOfRA_Preambles, i, deltaPreamble_Msg3; + uint8_t noGroupB = 0, s_id, f_id, ul_carrier_id, msg1_FDM, prach_ConfigIndex, SFN_nbr, Msg3_size; + + // NR_RSRP_Range_t rsrp_ThresholdSSB; // todo + + /////////////////////////////////////////////////////////// + //////////* UE Random Access Resource Selection *////////// + /////////////////////////////////////////////////////////// + + // todo: + // - switch initialisation cases + // -- RA initiated by beam failure recovery operation (subclause 5.17 TS 38.321) + // --- SSB selection, set prach_resources->ra_PreambleIndex + // -- RA initiated by PDCCH: ra_preamble_index provided by PDCCH && ra_PreambleIndex != 0b000000 + // --- set PREAMBLE_INDEX to ra_preamble_index + // --- select the SSB signalled by PDCCH + // -- RA initiated for SI request: + // --- SSB selection, set prach_resources->ra_PreambleIndex + + // if (rach_ConfigDedicated) { // This is for network controlled Mobility + // // operation for contention-free RA resources when: + // // - available SSB with SS-RSRP above rsrp-ThresholdSSB: SSB selection + // // - availalbe CSI-RS with CSI-RSRP above rsrp-ThresholdCSI-RS: CSI-RS selection + // prach_resources->ra_PreambleIndex = rach_ConfigDedicated->ra_PreambleIndex; + // return; + // } + + //////////* Contention-based RA preamble selection *////////// + // todo: + // - selection of SSB with SS-RSRP above rsrp-ThresholdSSB else select any SSB + // - todo determine next available PRACH occasion + + // rsrp_ThresholdSSB = *nr_rach_ConfigCommon->rsrp_ThresholdSSB; + + AssertFatal(mac->nr_rach_ConfigCommon != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); + + nr_rach_ConfigCommon = mac->nr_rach_ConfigCommon; + + Msg3_size = mac->RA_Msg3_size; + numberOfRA_Preambles = *nr_rach_ConfigCommon->totalNumberOfRA_Preambles; + + if (!nr_rach_ConfigCommon->groupBconfigured) { + noGroupB = 1; + } else { + // RA preambles group B is configured + // - Defining the number of RA preambles in RA Preamble Group A for each SSB */ + sizeOfRA_PreamblesGroupA = nr_rach_ConfigCommon->groupBconfigured->numberOfRA_PreamblesGroupA; + switch (nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA){ + /* - Threshold to determine the groups of RA preambles */ + case 0: + messageSizeGroupA = 56; + break; + case 1: + messageSizeGroupA = 144; + break; + case 2: + messageSizeGroupA = 208; + break; + case 3: + messageSizeGroupA = 256; + break; + case 4: + messageSizeGroupA = 282; + break; + case 5: + messageSizeGroupA = 480; + break; + case 6: + messageSizeGroupA = 640; + break; + case 7: + messageSizeGroupA = 800; + break; + case 8: + messageSizeGroupA = 1000; + break; + case 9: + messageSizeGroupA = 72; + break; + default: + AssertFatal(1 == 0,"Unknown ra_Msg3SizeGroupA %lu\n", nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA); + /* todo cases 10 -15*/ + } + + /* Power offset for preamble selection in dB */ + messagePowerOffsetGroupB = -9999; + switch (nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB){ + case 0: + messagePowerOffsetGroupB = -9999; + break; + case 1: + messagePowerOffsetGroupB = 0; + break; + case 2: + messagePowerOffsetGroupB = 5; + break; + case 3: + messagePowerOffsetGroupB = 8; + break; + case 4: + messagePowerOffsetGroupB = 10; + break; + case 5: + messagePowerOffsetGroupB = 12; + break; + case 6: + messagePowerOffsetGroupB = 15; + break; + case 7: + messagePowerOffsetGroupB = 18; + break; + default: + AssertFatal(1 == 0,"Unknown messagePowerOffsetGroupB %lu\n", nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB); + } + + // todo Msg3-DeltaPreamble should be provided from higher layers, otherwise is 0 + mac->deltaPreamble_Msg3 = 0; + deltaPreamble_Msg3 = mac->deltaPreamble_Msg3; + } + + PLThreshold = prach_resources->RA_PCMAX - nr_rach_ConfigCommon->rach_ConfigGeneric.preambleReceivedTargetPower - deltaPreamble_Msg3 - messagePowerOffsetGroupB; + + /* Msg3 has not been transmitted yet */ + if (first_Msg3 == 1) { + if (noGroupB == 1) { + // use Group A preamble + prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles; + mac->RA_usedGroupA = 1; + } else if ((Msg3_size < messageSizeGroupA) && (get_nr_PL(mod_id, CC_id, gNB_id) > PLThreshold)) { + // Group B is configured and RA preamble Group A is used + // - todo add condition on CCCH_sdu_size for initiation by CCCH + prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; + mac->RA_usedGroupA = 1; + } else { + // Group B preamble is configured and used + // the first sizeOfRA_PreamblesGroupA RA preambles belong to RA Preambles Group A + // the remaining belong to RA Preambles Group B + prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); + mac->RA_usedGroupA = 0; + } + } else { // Msg3 is being retransmitted + if (mac->RA_usedGroupA == 1 && noGroupB == 1) { + prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles; + } else if (mac->RA_usedGroupA == 1 && noGroupB == 0){ + prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; + } else { + prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); + } + } + + // todo determine next available PRACH occasion + // - if RA initiated for SI request and ra_AssociationPeriodIndex and si-RequestPeriod are configured + // - else if SSB is selected above + // - else if CSI-RS is selected above + + ///////////////////////////////////////////////////////////////////////////// + //////////* Random Access Preamble Transmission (5.1.3 TS 38.321) *////////// + ///////////////////////////////////////////////////////////////////////////// + // todo: + // - condition on notification of suspending power ramping counter from lower layer (5.1.3 TS 38.321) + // - check if SSB or CSI-RS have not changed since the selection in the last RA Preamble tranmission + // - Extend RA_rnti computation (e.g. f_id selection, ul_carrier_id are hardcoded) + + if (mac->RA_PREAMBLE_TRANSMISSION_COUNTER > 1) + mac->RA_PREAMBLE_TRANSMISSION_COUNTER++; + + prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = nr_get_Po_NOMINAL_PUSCH(prach_resources, mod_id, CC_id); + + // RA-RNTI computation (associated to PRACH occasion in which the RA Preamble is transmitted) + // 1) this does not apply to contention-free RA Preamble for beam failure recovery request + // 2) getting star_symb, SFN_nbr from table 6.3.3.2-3 (TDD and FR1 scenario) + + switch (nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FDM){ // todo this is not used + case 0: + msg1_FDM = 1; + break; + case 1: + msg1_FDM = 2; + break; + case 2: + msg1_FDM = 4; + break; + case 3: + msg1_FDM = 8; + break; + default: + AssertFatal(1 == 0,"Unknown msg1_FDM %lu\n", nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FDM); + } + + prach_ConfigIndex = nr_rach_ConfigCommon->rach_ConfigGeneric.prach_ConfigurationIndex; + + // ra_RNTI computation + // - todo: this is for TDD FR1 only + // - ul_carrier_id: UL carrier used for RA preamble transmission, hardcoded for NUL carrier + // - f_id: index of the PRACH occasion in the frequency domain + // - s_id is starting symbol of the PRACH occasion [0...14] + // - t_id is the first slot of the PRACH occasion in a system frame [0...80] + + ul_carrier_id = 0; // NUL + f_id = nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FrequencyStart; + SFN_nbr = table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][4]; + s_id = table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][5]; + + // Pick the first slot of the PRACH occasion in a system frame + for (i = 0; i < 10; i++){ + if (((SFN_nbr & (1 << i)) >> i) == 1){ + t_id = 2*i; + break; + } + } + prach_resources->ra_RNTI = 1 + s_id + 14 * t_id + 1120 * f_id + 8960 * ul_carrier_id; + mac->ra_rnti = prach_resources->ra_RNTI; + + LOG_D(MAC, "Computed ra_RNTI is %d", prach_resources->ra_RNTI); +} + +// TbD: RA_attempt_number not used +void nr_Msg1_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id){ + AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + mac->ra_state = WAIT_RAR; + // Start contention resolution timer + mac->RA_attempt_number++; +} + +void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id){ + AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); + LOG_D(MAC,"[UE %d][RAPROC] Frame %d : Msg3_tx: Starting contention resolution timer\n", mod_id, frameP); + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + // start contention resolution timer + mac->RA_contention_resolution_cnt = 0; + mac->RA_contention_resolution_timer_active = 1; +} + +///////////////////////////////////////////////////////////////////////// +///////* Random Access Preamble Initialization (5.1.1 TS 38.321) */////// +///////////////////////////////////////////////////////////////////////// +/// Handling inizialization by PDCCH order, MAC entity or RRC (TS 38.300) +/// Only one RA procedure is ongoing at any point in time in a MAC entity +/// the RA procedure on a SCell shall only be initiated by PDCCH order + +// WIP +// todo TS 38.321: +// - check if carrier to use is explicitly signalled then do (1) RA CARRIER SELECTION (SUL, NUL) (2) set PCMAX +// - BWP operation (subclause 5.15 TS 38.321) +// - handle initialization by beam failure recovery +// - handle initialization by handover +// - handle transmission on DCCH using PRACH (during handover, or sending SR for example) +// - take into account MAC CEs in size_sdu (currently hardcoded size to 1 MAC subPDU and 1 padding subheader) +// - fix rrc data req logic +// - retrieve TBS +// - add mac_rrc_nr_data_req_ue, etc ... +// - add the backoff condition here if we have it from a previous RA reponse which failed (i.e. backoff indicator) + + From 076e7c8e53b57679c9f2f5929a314a6978359c9f Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Thu, 26 Mar 2020 12:50:46 +0100 Subject: [PATCH 105/553] Merge branch 'NR_RRC_PRACH_procedures' of https://gitlab.eurecom.fr/oai/openairinterface5g into NR_RRC_PRACH_procedures From fa3f4617838cfebb6581d9105fe5a61424172598 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Thu, 26 Mar 2020 18:20:05 +0100 Subject: [PATCH 106/553] ENDC path switch procedures: Remove some IEs from E-RAB Modification Indication message which finally appear to be not mandatory --- openair3/S1AP/s1ap_eNB_nas_procedures.c | 27 ++++++++++++++----------- 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/openair3/S1AP/s1ap_eNB_nas_procedures.c b/openair3/S1AP/s1ap_eNB_nas_procedures.c index 15cdb5d8e6..b8a4b98fef 100644 --- a/openair3/S1AP/s1ap_eNB_nas_procedures.c +++ b/openair3/S1AP/s1ap_eNB_nas_procedures.c @@ -1807,6 +1807,7 @@ int s1ap_eNB_generate_E_RAB_Modification_Indication( int num_e_rabs_nottobemodified = e_rab_modification_ind->nb_of_e_rabs_nottobemodified; uint32_t CSG_id = 0; + uint32_t pseudo_gtp_teid = 10; if ((ue_context_p = s1ap_eNB_get_ue_context(s1ap_eNB_instance_p, e_rab_modification_ind->eNB_ue_s1ap_id)) == NULL) { @@ -1870,7 +1871,7 @@ int s1ap_eNB_generate_E_RAB_Modification_Indication( ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); //E-RABs NOT to be modified list - ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t)); + /*ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t)); ie->id = S1AP_ProtocolIE_ID_id_E_RABNotToBeModifiedListBearerModInd; ie->criticality = S1AP_Criticality_reject; //if(num_e_rabs_nottobemodified > 0) { @@ -1884,7 +1885,7 @@ int s1ap_eNB_generate_E_RAB_Modification_Indication( E_RAB_NotToBeModifiedItem_BearerModInd = &E_RAB_NotToBeModifiedItem_BearerModInd_IEs->value.choice.E_RABNotToBeModifiedItemBearerModInd; { - E_RAB_NotToBeModifiedItem_BearerModInd->e_RAB_ID = e_rab_modification_ind->e_rabs_tobemodified[i].e_rab_id; + E_RAB_NotToBeModifiedItem_BearerModInd->e_RAB_ID = 10; //e_rab_modification_ind->e_rabs_tobemodified[i].e_rab_id; E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.size = e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.length/8; E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.bits_unused = e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.length%8; @@ -1893,29 +1894,31 @@ int s1ap_eNB_generate_E_RAB_Modification_Indication( memcpy (E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.buf, e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.buffer, E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.size); - INT32_TO_OCTET_STRING(e_rab_modification_ind->e_rabs_tobemodified[i].gtp_teid, &E_RAB_NotToBeModifiedItem_BearerModInd->dL_GTP_TEID); + //INT32_TO_OCTET_STRING(e_rab_modification_ind->e_rabs_tobemodified[i].gtp_teid, &E_RAB_NotToBeModifiedItem_BearerModInd->dL_GTP_TEID); + INT32_TO_OCTET_STRING(pseudo_gtp_teid, &E_RAB_NotToBeModifiedItem_BearerModInd->dL_GTP_TEID); } ASN_SEQUENCE_ADD(&ie->value.choice.E_RABNotToBeModifiedListBearerModInd.list, E_RAB_NotToBeModifiedItem_BearerModInd_IEs); } // } - /*else{ - ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_E_RABNotToBeModifiedListBearerModInd; - ie->value.choice.E_RABNotToBeModifiedListBearerModInd.list.size = 0; - } */ + //else{ +// ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_E_RABNotToBeModifiedListBearerModInd; +// ie->value.choice.E_RABNotToBeModifiedListBearerModInd.list.size = 0; +// } / - ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie);*/ - ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t)); + /*ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t)); ie->id = S1AP_ProtocolIE_ID_id_CSGMembershipInfo; ie->criticality = S1AP_Criticality_reject; ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_CSGMembershipInfo; ie->value.choice.CSGMembershipInfo.cSGMembershipStatus = S1AP_CSGMembershipStatus_member; - INT32_TO_BIT_STRING(CSG_id, &ie->value.choice.CSGMembershipInfo.cSG_Id); - ie->value.choice.CSGMembershipInfo.cSG_Id.bits_unused=5; - ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); + INT32_TO_BIT_STRING(CSG_id, &ie->value.choice.CSGMembershipInfo.cSG_Id); + ie->value.choice.CSGMembershipInfo.cSG_Id.bits_unused=5; + ie->value.choice.CSGMembershipInfo.cellAccessMode = S1AP_CellAccessMode_hybrid; + ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie);*/ if (s1ap_eNB_encode_pdu(&pdu, &buffer, &len) < 0) { S1AP_ERROR("Failed to encode S1 E-RAB modification indication \n"); From 924d361ded8f34dc986b4f42b17eddd1f89703bc Mon Sep 17 00:00:00 2001 From: cig Date: Fri, 6 Mar 2020 17:00:51 +0100 Subject: [PATCH 107/553] Enabled NR UE PRACH scheduler --- executables/nr-ue.c | 6 ++++-- openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c | 20 ++++++++++---------- openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h | 10 +++++++--- 3 files changed, 21 insertions(+), 15 deletions(-) diff --git a/executables/nr-ue.c b/executables/nr-ue.c index e72e2d49fc..9de58eb8e7 100644 --- a/executables/nr-ue.c +++ b/executables/nr-ue.c @@ -531,8 +531,10 @@ void UE_processing(void *arg) { ul_indication.module_id = mod_id; ul_indication.gNB_index = gNB_id; ul_indication.cc_id = CC_id; - ul_indication.frame = proc->frame_rx; - ul_indication.slot = proc->nr_tti_rx; + ul_indication.frame_rx = proc->frame_rx; + ul_indication.slot_rx = proc->nr_tti_rx; + ul_indication.frame_tx = proc->frame_tx; + ul_indication.slot_tx = proc->nr_tti_tx; UE->if_inst->ul_indication(&ul_indication); } } diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c index cea10ae08c..0d04a0ae93 100644 --- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c @@ -113,17 +113,17 @@ int nr_ue_ul_indication(nr_uplink_indication_t *ul_info){ mac->dl_config_request.number_pdus = 0; // clean previous FAPI messages - ret = nr_ue_scheduler( - ul_info->module_id, - ul_info->gNB_index, - ul_info->cc_id, - ul_info->frame, - ul_info->slot, - ul_info->ssb_index, - 0, 0); // TODO check tx/rx frame/slot is need for NR version + ret = nr_ue_scheduler(ul_info->module_id, + ul_info->gNB_index, + ul_info->cc_id, + ul_info->frame_rx, + ul_info->slot_rx, + ul_info->ssb_index, + ul_info->frame_tx, + ul_info->slot_tx); - /*if (is_nr_UL_slot(mac->scc, ul_info->slot)) - nr_ue_prach_scheduler(module_id, ul_info->frame, ul_info->slot);*/ // WIP TbD set tx frame/slot + if (is_nr_UL_slot(mac->scc, ul_info->slot_tx)) + nr_ue_prach_scheduler(module_id, ul_info->frame_tx, ul_info->slot_tx); switch(ret){ case UE_CONNECTION_OK: diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h index 0784e71584..b7ddfc0c57 100755 --- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h +++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h @@ -87,9 +87,13 @@ typedef struct { /// component carrier id int cc_id; /// frame - frame_t frame; - /// slot - uint32_t slot; + frame_t frame_rx; + /// slot rx + uint32_t slot_rx; + /// frame tx + frame_t frame_tx; + /// slot tx + uint32_t slot_tx; /// ssb_index, if ssb is not present in current TTI, thie value set to -1 int ssb_index; /// dci reception indication structure From ae9303bd52d75ea3f8935b34fe32c5d2268fd1ee Mon Sep 17 00:00:00 2001 From: cig Date: Tue, 24 Mar 2020 17:06:46 +0100 Subject: [PATCH 108/553] Implemented dft/idft 36864 --- openair1/PHY/TOOLS/lte_dfts.c | 107 +++++++++++++++++++++++++++++++++- 1 file changed, 104 insertions(+), 3 deletions(-) diff --git a/openair1/PHY/TOOLS/lte_dfts.c b/openair1/PHY/TOOLS/lte_dfts.c index 2de8653ab3..112035ebaf 100644 --- a/openair1/PHY/TOOLS/lte_dfts.c +++ b/openair1/PHY/TOOLS/lte_dfts.c @@ -6055,25 +6055,126 @@ void idft24576(int16_t *input, int16_t *output,int scale) } int16_t twa36864[24576] __attribute__((aligned(32))); -int16_t twb36884[24576] __attribute__((aligned(32))); +int16_t twb36864[24576] __attribute__((aligned(32))); + // 12288 x 3 void dft36864(int16_t *input, int16_t *output,int scale) { - AssertFatal(1==0,"Need to do this ..\n"); + int i,i2,j; + uint32_t tmp[3][12288] __attribute__((aligned(32))); + uint32_t tmpo[3][12288] __attribute__((aligned(32))); + simd_q15_t *y128p=(simd_q15_t*)output; + simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15); + + for (i=0,j=0; i<12288; i++) { + tmp[0][i] = ((uint32_t *)input)[j++]; + tmp[1][i] = ((uint32_t *)input)[j++]; + tmp[2][i] = ((uint32_t *)input)[j++]; + } + + dft12288((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1); + dft12288((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1); + dft12288((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1); + + if (LOG_DUMPFLAG(DEBUG_DFT)) { + LOG_M("dft36864out0.m","o0",tmpo[0],12288,1,1); + LOG_M("dft36864out1.m","o1",tmpo[1],12288,1,1); + LOG_M("dft36864out2.m","o2",tmpo[2],12288,1,1); + } + + for (i=0,i2=0; i<24576; i+=8,i2+=4) { + bfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),(simd_q15_t*)(&tmpo[2][i2]), + (simd_q15_t*)(output+i),(simd_q15_t*)(output+24576+i),(simd_q15_t*)(output+49152+i), + (simd_q15_t*)(twa36864+i),(simd_q15_t*)(twb36864+i)); + } + + if (scale==1) { + for (i=0; i<576; i++) { + y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128); + y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128); + y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128); + y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128); + y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128); + y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128); + y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128); + y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128); + y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128); + y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128); + y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128); + y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128); + y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128); + y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128); + y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128); + y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128); + y128p+=16; + } + } + _mm_empty(); + _m_empty(); + if (LOG_DUMPFLAG(DEBUG_DFT)) { + LOG_M("out.m","out",output,36864,1,1); + } } + void idft36864(int16_t *input, int16_t *output,int scale) { - AssertFatal(1==0,"Need to do this ..\n"); + int i,i2,j; + uint32_t tmp[3][12288] __attribute__((aligned(32))); + uint32_t tmpo[3][12288] __attribute__((aligned(32))); + simd_q15_t *y128p=(simd_q15_t*)output; + simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15); + + for (i=0,j=0; i<12288; i++) { + tmp[0][i] = ((uint32_t *)input)[j++]; + tmp[1][i] = ((uint32_t *)input)[j++]; + tmp[2][i] = ((uint32_t *)input)[j++]; + } + + idft12288((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1); + idft12288((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1); + idft12288((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1); + + for (i=0,i2=0; i<24576; i+=8,i2+=4) { + ibfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]), + (simd_q15_t*)(output+i),(simd_q15_t*)(output+24576+i),(simd_q15_t*)(output+49152+i), + (simd_q15_t*)(twa36864+i),(simd_q15_t*)(twb36864+i)); + } + if (scale==1) { + for (i=0; i<576; i++) { + y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128); + y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128); + y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128); + y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128); + y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128); + y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128); + y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128); + y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128); + y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128); + y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128); + y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128); + y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128); + y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128); + y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128); + y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128); + y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128); + y128p+=16; + } + } + _mm_empty(); + _m_empty(); } int16_t twa49152[32768] __attribute__((aligned(32))); int16_t twb49152[32768] __attribute__((aligned(32))); + // 16384 x 3 +// TbD todo dft16384 void dft49152(int16_t *input, int16_t *output,int scale) { AssertFatal(1==0,"Need to do this ..\n"); } +// TbD todo dft16384 void idft49152(int16_t *input, int16_t *output,int scale) { AssertFatal(1==0,"Need to do this ..\n"); From 4e38ea23678f43a36ad70b0bf19e7b94e02dca30 Mon Sep 17 00:00:00 2001 From: cig Date: Tue, 24 Mar 2020 19:17:45 +0100 Subject: [PATCH 109/553] Set UE mode to NOT_SYNCHED by default --- executables/nr-ue.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/executables/nr-ue.c b/executables/nr-ue.c index 9de58eb8e7..b064222d04 100644 --- a/executables/nr-ue.c +++ b/executables/nr-ue.c @@ -142,15 +142,23 @@ void init_nr_ue_vars(PHY_VARS_NR_UE *ue, uint8_t abstraction_flag) { + int nb_connected_gNB = 1, gNB_id; + memcpy(&(ue->frame_parms), frame_parms, sizeof(NR_DL_FRAME_PARMS)); ue->Mod_id = UE_id; ue->mac_enabled = 1; + // Setting UE mode to NOT_SYNCHED by default + for (gNB_id = 0; gNB_id < nb_connected_gNB; gNB_id++){ + ue->UE_mode[gNB_id] = NOT_SYNCHED; + ue->prach_resources[gNB_id] = (NR_PRACH_RESOURCES_t *)malloc16_clear(sizeof(NR_PRACH_RESOURCES_t)); + } + // initialize all signal buffers - init_nr_ue_signal(ue,1,abstraction_flag); + init_nr_ue_signal(ue, nb_connected_gNB, abstraction_flag); // intialize transport - init_nr_ue_transport(ue,abstraction_flag); + init_nr_ue_transport(ue, abstraction_flag); } /*! From eb7f3193aa73b94ed7078729a71a6283bee281ed Mon Sep 17 00:00:00 2001 From: cig Date: Tue, 24 Mar 2020 19:30:32 +0100 Subject: [PATCH 110/553] Enabled compute_nr_prach_seq to be used at both gNB and UE side: - now the function gets more input arguments but can be used from both UE and gNB - this change was needed because the prach fapi of UE differs from the gNB one --- openair1/PHY/INIT/nr_init.c | 9 ++++++++- openair1/PHY/NR_TRANSPORT/nr_prach_common.c | 20 +++++-------------- .../NR_TRANSPORT/nr_transport_proto_common.h | 8 ++++---- 3 files changed, 17 insertions(+), 20 deletions(-) diff --git a/openair1/PHY/INIT/nr_init.c b/openair1/PHY/INIT/nr_init.c index dc865aaed9..a74b90749a 100644 --- a/openair1/PHY/INIT/nr_init.c +++ b/openair1/PHY/INIT/nr_init.c @@ -418,6 +418,7 @@ void nr_phy_config_request_sim(PHY_VARS_gNB *gNB, void nr_phy_config_request(NR_PHY_Config_t *phy_config) { uint8_t Mod_id = phy_config->Mod_id; + uint8_t short_sequence, num_sequences, rootSequenceIndex, fd_occasion; NR_DL_FRAME_PARMS *fp = &RC.gNB[Mod_id]->frame_parms; nfapi_nr_config_request_scf_t *gNB_config = &RC.gNB[Mod_id]->gNB_config; @@ -481,7 +482,13 @@ void nr_phy_config_request(NR_PHY_Config_t *phy_config) { return; } - compute_nr_prach_seq(gNB_config,0,RC.gNB[Mod_id]->X_u); + fd_occasion = 0; + nfapi_nr_prach_config_t *prach_config = &gNB_config->prach_config; + short_sequence = prach_config->prach_sequence_length.value; + num_sequences = prach_config->num_prach_fd_occasions_list[fd_occasion].num_root_sequences.value; + rootSequenceIndex = prach_config->num_prach_fd_occasions_list[fd_occasion].prach_root_sequence_index.value; + + compute_nr_prach_seq(short_sequence, num_sequences, rootSequenceIndex, RC.gNB[Mod_id]->X_u); RC.gNB[Mod_id]->configured = 1; LOG_I(PHY,"gNB %d configured\n",Mod_id); diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c index e881b91b84..e824928dbe 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c @@ -97,28 +97,21 @@ void nr_fill_du(uint16_t N_ZC,uint16_t *prach_root_sequence_map) } +void compute_nr_prach_seq(uint8_t short_sequence, + uint8_t num_sequences, + uint8_t rootSequenceIndex, + uint32_t X_u[64][839]){ -void compute_nr_prach_seq(nfapi_nr_config_request_scf_t *config, - uint8_t fd_occasion, - uint32_t X_u[64][839]) -{ // Compute DFT of x_u => X_u[k] = x_u(inv(u)*k)^* X_u[k] = exp(j\pi u*inv(u)*k*(inv(u)*k+1)/N_ZC) - nfapi_nr_prach_config_t prach_config = config->prach_config; unsigned int k,inv_u,i; int N_ZC; uint16_t *prach_root_sequence_map; uint16_t u; - uint8_t short_sequence = prach_config.prach_sequence_length.value; - uint8_t num_sequences = prach_config.num_prach_fd_occasions_list[fd_occasion].num_root_sequences.value; - uint8_t rootSequenceIndex = prach_config.num_prach_fd_occasions_list[fd_occasion].prach_root_sequence_index.value; VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_UE_COMPUTE_PRACH, VCD_FUNCTION_IN); - - LOG_D(PHY,"compute_prach_seq: NCS_config %d, prach short sequence %x, num_Seqeuences %d, rootSequenceIndex %d\n",prach_config.num_prach_fd_occasions_list[fd_occasion].prach_zero_corr_conf.value, short_sequence, num_sequences, rootSequenceIndex); - - + LOG_D(PHY,"compute_prach_seq: prach short sequence %x, num_sequences %d, rootSequenceIndex %d\n", short_sequence, num_sequences, rootSequenceIndex); N_ZC = (short_sequence) ? 139 : 839; //init_prach_tables(N_ZC); //moved to phy_init_lte_ue/eNB, since it takes to long in real-time @@ -132,11 +125,8 @@ void compute_nr_prach_seq(nfapi_nr_config_request_scf_t *config, prach_root_sequence_map = prach_root_sequence_map_0_3; } - - LOG_D( PHY, "compute_prach_seq: done init prach_tables\n" ); - for (i=0; i Date: Tue, 24 Mar 2020 19:41:12 +0100 Subject: [PATCH 111/553] Commented out code for contention resolution at UE side --- openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c index decdddbe31..06c89b9ee7 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -492,6 +492,7 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, // - handle beam failure recovery request // - handle DL assignment on PDCCH for RA-RNTI // - handle backoff and raResponseWindow params + // - disabled contention resolution as OAI NSA is contention-free based LOG_D(MAC, "[MAC][UE %d][RAPROC] frame %d, subframe %d: RA Active, window cnt %d (RA_tx_frame %d, RA_tx_subframe %d)\n", mod_id, frame, nr_tti_tx, mac->RA_window_cnt, mac->RA_tx_frame, mac->RA_tx_subframe); @@ -502,8 +503,8 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, prach_resources->RA_PREAMBLE_BACKOFF = 0; } - if (mac->RA_window_cnt > 0 && mac->RA_RAPID_found == 1) { - mac->ra_state = WAIT_CONTENTION_RESOLUTION; + if (mac->RA_window_cnt > 0 && mac->RA_RAPID_found == 1) { + // mac->ra_state = WAIT_CONTENTION_RESOLUTION; } else { LOG_I(MAC, "[MAC][UE %d][RAPROC] Frame %d: subframe %d: RAR reception not successful, (RA window count %d) \n", mod_id, From 63d6b59f9d1931b818b3f90905839efa4a60e3c9 Mon Sep 17 00:00:00 2001 From: cig Date: Tue, 24 Mar 2020 19:55:54 +0100 Subject: [PATCH 112/553] Enabled check on UE mode to start either ULSCH and PRACH procedures: - ULSCH is temporary disabled --- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 36 ++++++++++----------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 2cc35a02da..b4941d24fc 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -2243,12 +2243,8 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, start_meas(&ue->phy_proc_tx); #endif - nr_ue_ulsch_procedures(ue, - harq_pid, - frame_tx, - slot_tx, - thread_id, - gNB_id); + if (ue->UE_mode[gNB_id] == PUSCH ){ + nr_ue_ulsch_procedures(ue, harq_pid, frame_tx, slot_tx, thread_id, gNB_id); /* if (ue->UE_mode[eNB_id] == PUSCH) { @@ -2266,6 +2262,7 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, thread_id, gNB_id, &ue->frame_parms); + } /* RACH */ @@ -2451,7 +2448,7 @@ void restart_phy(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc, uint8_t eNB_id,uint } #endif //(0) -void nr_ue_pbch_procedures(uint8_t eNB_id, +void nr_ue_pbch_procedures(uint8_t gNB_id, PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t abstraction_flag) @@ -2470,20 +2467,23 @@ void nr_ue_pbch_procedures(uint8_t eNB_id, VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_PBCH_PROCEDURES, VCD_FUNCTION_IN); - //LOG_I(PHY,"[UE %d] Frame %d, Trying PBCH %d (NidCell %d, eNB_id %d)\n",ue->Mod_id,frame_rx,pbch_phase,ue->frame_parms.Nid_cell,eNB_id); + //LOG_I(PHY,"[UE %d] Frame %d, Trying PBCH %d (NidCell %d, gNB_id %d)\n",ue->Mod_id,frame_rx,pbch_phase,ue->frame_parms.Nid_cell,gNB_id); ret = nr_rx_pbch(ue, proc, - ue->pbch_vars[eNB_id], + ue->pbch_vars[gNB_id], &ue->frame_parms, - eNB_id, + gNB_id, (ue->frame_parms.ssb_index)&7, SISO, ue->high_speed_flag); if (ret==0) { - ue->pbch_vars[eNB_id]->pdu_errors_conseq = 0; + ue->pbch_vars[gNB_id]->pdu_errors_conseq = 0; + // Switch to PRACH state if it is first PBCH after initial synch and no timing correction is performed + if (ue->UE_mode[gNB_id] == NOT_SYNCHED && ue->no_timing_correction == 1) + ue->UE_mode[gNB_id] = PRACH; #ifdef DEBUG_PHY_PROC uint16_t frame_tx; @@ -2513,25 +2513,25 @@ void nr_ue_pbch_procedures(uint8_t eNB_id, exit(-1); */ - ue->pbch_vars[eNB_id]->pdu_errors_conseq++; - ue->pbch_vars[eNB_id]->pdu_errors++; + ue->pbch_vars[gNB_id]->pdu_errors_conseq++; + ue->pbch_vars[gNB_id]->pdu_errors++; - if (ue->pbch_vars[eNB_id]->pdu_errors_conseq>=100) { + if (ue->pbch_vars[gNB_id]->pdu_errors_conseq>=100) { LOG_E(PHY,"More that 100 consecutive PBCH errors! Exiting!\n"); exit_fun("More that 100 consecutive PBCH errors! Exiting!\n"); } } if (frame_rx % 100 == 0) { - ue->pbch_vars[eNB_id]->pdu_fer = ue->pbch_vars[eNB_id]->pdu_errors - ue->pbch_vars[eNB_id]->pdu_errors_last; - ue->pbch_vars[eNB_id]->pdu_errors_last = ue->pbch_vars[eNB_id]->pdu_errors; + ue->pbch_vars[gNB_id]->pdu_fer = ue->pbch_vars[gNB_id]->pdu_errors - ue->pbch_vars[gNB_id]->pdu_errors_last; + ue->pbch_vars[gNB_id]->pdu_errors_last = ue->pbch_vars[gNB_id]->pdu_errors; } #ifdef DEBUG_PHY_PROC LOG_D(PHY,"[UE %d] frame %d, slot %d, PBCH errors = %d, consecutive errors = %d!\n", ue->Mod_id,frame_rx, nr_tti_rx, - ue->pbch_vars[eNB_id]->pdu_errors, - ue->pbch_vars[eNB_id]->pdu_errors_conseq); + ue->pbch_vars[gNB_id]->pdu_errors, + ue->pbch_vars[gNB_id]->pdu_errors_conseq); #endif VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_PBCH_PROCEDURES, VCD_FUNCTION_OUT); } From 01b3038d771b43e4beb6f77dfbd8fe88971088fc Mon Sep 17 00:00:00 2001 From: cig Date: Tue, 24 Mar 2020 20:02:42 +0100 Subject: [PATCH 113/553] Check on dlsch0_harq to avoid segmentation fault --- openair1/SCHED_NR_UE/fapi_nr_ue_l1.c | 38 +++++++++++++++------------- 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c index e324980af7..06e6976b14 100644 --- a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c +++ b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c @@ -80,24 +80,26 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ dlsch0->rnti = dl_config->dl_config_list[i].dlsch_config_pdu.rnti; //dlsch0->harq_processes[0]->mcs = &dlsch_config_pdu->mcs; dlsch0_harq = dlsch0->harq_processes[current_harq_pid]; - dlsch0_harq->BWPStart = dlsch_config_pdu->BWPStart; - dlsch0_harq->BWPSize = dlsch_config_pdu->BWPSize; - dlsch0_harq->nb_rb = dlsch_config_pdu->number_rbs; - dlsch0_harq->start_rb = dlsch_config_pdu->start_rb; - dlsch0_harq->nb_symbols = dlsch_config_pdu->number_symbols; - dlsch0_harq->start_symbol = dlsch_config_pdu->start_symbol; - dlsch0_harq->dlDmrsSymbPos = dlsch_config_pdu->dlDmrsSymbPos; - dlsch0_harq->dmrsConfigType = dlsch_config_pdu->dmrsConfigType; - dlsch0_harq->mcs = dlsch_config_pdu->mcs; - dlsch0_harq->DCINdi = dlsch_config_pdu->ndi; - dlsch0_harq->rvidx = dlsch_config_pdu->rv; - dlsch0->g_pucch = dlsch_config_pdu->accumulated_delta_PUCCH; - dlsch0_harq->harq_ack.pucch_resource_indicator = dlsch_config_pdu->pucch_resource_id; - dlsch0_harq->harq_ack.slot_for_feedback_ack = dlsch_config_pdu->pdsch_to_harq_feedback_time_ind; - dlsch0_harq->Nl=1; - dlsch0_harq->mcs_table=0; - dlsch0_harq->status = ACTIVE; - LOG_D(MAC, ">>>> \tdlsch0->g_pucch = %d\tdlsch0_harq.mcs = %d\n", dlsch0->g_pucch, dlsch0_harq->mcs); + if (dlsch0_harq != NULL){ + dlsch0_harq->BWPStart = dlsch_config_pdu->BWPStart; + dlsch0_harq->BWPSize = dlsch_config_pdu->BWPSize; + dlsch0_harq->nb_rb = dlsch_config_pdu->number_rbs; + dlsch0_harq->start_rb = dlsch_config_pdu->start_rb; + dlsch0_harq->nb_symbols = dlsch_config_pdu->number_symbols; + dlsch0_harq->start_symbol = dlsch_config_pdu->start_symbol; + dlsch0_harq->dlDmrsSymbPos = dlsch_config_pdu->dlDmrsSymbPos; + dlsch0_harq->dmrsConfigType = dlsch_config_pdu->dmrsConfigType; + dlsch0_harq->mcs = dlsch_config_pdu->mcs; + dlsch0_harq->DCINdi = dlsch_config_pdu->ndi; + dlsch0_harq->rvidx = dlsch_config_pdu->rv; + dlsch0->g_pucch = dlsch_config_pdu->accumulated_delta_PUCCH; + dlsch0_harq->harq_ack.pucch_resource_indicator = dlsch_config_pdu->pucch_resource_id; + dlsch0_harq->harq_ack.slot_for_feedback_ack = dlsch_config_pdu->pdsch_to_harq_feedback_time_ind; + dlsch0_harq->Nl=1; + dlsch0_harq->mcs_table=0; + dlsch0_harq->status = ACTIVE; + LOG_D(MAC, ">>>> \tdlsch0->g_pucch = %d\tdlsch0_harq.mcs = %d\n", dlsch0->g_pucch, dlsch0_harq->mcs); + } } } } else { From 04a9c72de35e7d2a217f1e64fff3ef228c100531 Mon Sep 17 00:00:00 2001 From: cig Date: Wed, 25 Mar 2020 13:27:41 +0100 Subject: [PATCH 114/553] Bugfix in selection of dual format A3/B3 --- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 2 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 56f985ab31..3ff7a52f9b 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -839,7 +839,7 @@ void nr_ue_prach_scheduler(module_id_t module_idP, frame_t frameP, sub_frame_t s prach_config_pdu->prach_format = 10; break; case 0xa3: - prach_config_pdu->prach_format = 10; + prach_config_pdu->prach_format = 11; break; default: AssertFatal(1 == 0, "Only formats A1/B1 A2/B2 A3/B3 are valid for dual format"); diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index 9da4c9f854..042e53e2dc 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -105,7 +105,7 @@ void schedule_nr_prach(module_id_t module_idP, frame_t frameP, sub_frame_t slotP prach_pdu->prach_format = 10; break; case 0xa3: - prach_pdu->prach_format = 10; + prach_pdu->prach_format = 11; break; default: AssertFatal(1==0,"Only formats A1/B1 A2/B2 A3/B3 are valid for dual format"); From 3bb82a02eef33fa39cc4a558e9e43ac306437022 Mon Sep 17 00:00:00 2001 From: cig Date: Thu, 26 Mar 2020 11:50:29 +0100 Subject: [PATCH 115/553] UE: N_TA_offset configuration depending on SCS and N_RB_DL --- executables/nr-uesoftmodem.c | 48 ++++++++++++++++++++++++++++++------ 1 file changed, 41 insertions(+), 7 deletions(-) diff --git a/executables/nr-uesoftmodem.c b/executables/nr-uesoftmodem.c index af443ed820..b995a85c48 100644 --- a/executables/nr-uesoftmodem.c +++ b/executables/nr-uesoftmodem.c @@ -759,15 +759,49 @@ int main( int argc, char **argv ) { UE[CC_id]->rx_total_gain_dB = (int)rx_gain[CC_id][0] + rx_gain_off; UE[CC_id]->tx_power_max_dBm = tx_max_power[CC_id]; - if (frame_parms[CC_id]->frame_type==FDD) { + if (UE[CC_id]->frame_parms.frame_type == FDD) { UE[CC_id]->N_TA_offset = 0; } else { - if (frame_parms[CC_id]->N_RB_DL == 100) - UE[CC_id]->N_TA_offset = 624; - else if (frame_parms[CC_id]->N_RB_DL == 50) - UE[CC_id]->N_TA_offset = 624/2; - else if (frame_parms[CC_id]->N_RB_DL == 25) - UE[CC_id]->N_TA_offset = 624/4; + int N_RB = UE[CC_id]->frame_parms.N_RB_DL; + int N_TA_offset = UE[CC_id]->frame_parms.ul_CarrierFreq < 6e9 ? 400 : 431; // reference samples for 25600Tc @ 30.72 Ms/s for FR1, same @ 61.44 Ms/s for FR2 + double factor=1; + switch (UE[CC_id]->frame_parms.numerology_index) { + case 0: //15 kHz scs + AssertFatal(N_TA_offset == 400, "scs_common 15kHz only for FR1\n"); + if (N_RB <= 25) factor = .25; // 7.68 Ms/s + else if (N_RB <=50) factor = .5; // 15.36 Ms/s + else if (N_RB <=75) factor = 1.0; // 30.72 Ms/s + else if (N_RB <=100) factor = 1.0; // 30.72 Ms/s + else AssertFatal(1==0,"Too many PRBS for mu=0\n"); + break; + case 1: //30 kHz sc + AssertFatal(N_TA_offset == 400, "scs_common 30kHz only for FR1\n"); + if (N_RB <= 106) factor = 2.0; // 61.44 Ms/s + else if (N_RB <= 275) factor = 4.0; // 122.88 Ms/s + break; + case 2: //60 kHz scs + AssertFatal(1==0,"scs_common should not be 60 kHz\n"); + break; + case 3: //120 kHz scs + AssertFatal(N_TA_offset == 431, "scs_common 120kHz only for FR2\n"); + break; + case 4: //240 kHz scs + AssertFatal(1==0,"scs_common should not be 60 kHz\n"); + if (N_RB <= 32) factor = 1.0; // 61.44 Ms/s + else if (N_RB <= 66) factor = 2.0; // 122.88 Ms/s + else AssertFatal(1==0,"N_RB %d is too big for curretn FR2 implementation\n",N_RB); + break; + + if (N_RB == 100) + UE[CC_id]->N_TA_offset = 624; + else if (N_RB == 50) + UE[CC_id]->N_TA_offset = 624/2; + else if (N_RB == 25) + UE[CC_id]->N_TA_offset = 624/4; + } + if (UE[CC_id]->frame_parms.threequarter_fs == 1) factor = factor*.75; + UE[CC_id]->N_TA_offset = (int)(N_TA_offset * factor); + LOG_I(PHY,"UE %d Setting N_TA_offset to %d samples (factor %f, UL Freq %d, N_RB %d)\n", UE[CC_id]->Mod_id, UE[CC_id]->N_TA_offset, factor, UE[CC_id]->frame_parms.ul_CarrierFreq, N_RB); } } From ae5f30ec8d0f14703d57e4a60c0dcd312036edee Mon Sep 17 00:00:00 2001 From: cig Date: Thu, 26 Mar 2020 15:41:55 +0100 Subject: [PATCH 116/553] Set flag to generate PRACH only on PRACH slot --- openair1/PHY/defs_nr_UE.h | 2 - openair1/PHY/defs_nr_common.h | 2 + openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 17 +++-- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 71 ++++++++++++++----- openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 25 +++++++ 5 files changed, 88 insertions(+), 29 deletions(-) diff --git a/openair1/PHY/defs_nr_UE.h b/openair1/PHY/defs_nr_UE.h index 56b483b02b..b532ddb071 100644 --- a/openair1/PHY/defs_nr_UE.h +++ b/openair1/PHY/defs_nr_UE.h @@ -1009,8 +1009,6 @@ typedef struct { int dlsch_mtch_trials[MAX_MBSFN_AREA][NUMBER_OF_CONNECTED_eNB_MAX]; int current_dlsch_cqi[NUMBER_OF_CONNECTED_eNB_MAX]; unsigned char first_run_timing_advance[NUMBER_OF_CONNECTED_eNB_MAX]; - uint8_t generate_prach; - uint8_t generate_nr_prach; uint8_t prach_cnt; uint8_t prach_PreambleIndex; // uint8_t prach_timer; diff --git a/openair1/PHY/defs_nr_common.h b/openair1/PHY/defs_nr_common.h index 584c70ae64..d8f5563af0 100644 --- a/openair1/PHY/defs_nr_common.h +++ b/openair1/PHY/defs_nr_common.h @@ -246,6 +246,8 @@ typedef struct { uint16_t ra_RNTI; /// Pointer to Msg3 payload for UL-grant uint8_t *Msg3; + /// Flag for the Msg1 generation + uint8_t generate_nr_prach; } NR_PRACH_RESOURCES_t; typedef struct NR_DL_FRAME_PARMS NR_DL_FRAME_PARMS; diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index b4941d24fc..f4d19850c1 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -2270,7 +2270,7 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, nr_ue_prach_procedures(ue, proc, gNB_id, mode); } else { - ue->generate_nr_prach = 0; + ue->prach_resources[gNB_id]->generate_nr_prach = 0; } LOG_I(PHY,"****** end TX-Chain for AbsSubframe %d.%d ******\n", frame_tx, slot_tx); @@ -4503,12 +4503,12 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_IN); - ue->generate_nr_prach = 0; if (ue->mac_enabled == 0){ // prach_resources->ra_PreambleIndex = preamble_tx; prach_resources->ra_TDD_map_index = 0; prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = 10; prach_resources->ra_RNTI = 0x1234; + prach_resources->generate_nr_prach = 1; } else { // ask L2 for RACH transport if ((runmode != rx_calib_ue) && (runmode != rx_calib_ue_med) && (runmode != rx_calib_ue_byp) && (runmode != no_L2_connect) ) { @@ -4523,9 +4523,8 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t } } - if (ue->prach_resources[gNB_id] != NULL) { + if (ue->prach_resources[gNB_id] != NULL && prach_resources->generate_nr_prach == 1) { - ue->generate_nr_prach = 1; ue->prach_cnt = 0; pathloss = get_nr_PL(mod_id, ue->CC_id, gNB_id); LOG_D(PHY,"runmode %d\n",runmode); @@ -4534,7 +4533,7 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t ue->tx_power_dBm[nr_tti_tx] = prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER + pathloss; } - LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d : Generating PRACH, preamble %d, PL %d, P0_PRACH %d, TARGET_RECEIVED_POWER %d dBm, RA-RNTI %d\n", + LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_tx %d : Generating PRACH, preamble %d, PL %d, P0_PRACH %d, TARGET_RECEIVED_POWER %d dBm, RA-RNTI %d\n", ue->Mod_id, frame_tx, nr_tti_tx, @@ -4555,7 +4554,7 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t #endif if ((runmode == calib_prach_tx) && (((proc->frame_tx&0xfffe)%100)==0)) - LOG_D(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d : PRACH TX power %d dBm, amp %d\n", ue->Mod_id, + LOG_D(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_tx %d : PRACH TX power %d dBm, amp %d (%d)\n", ue->Mod_id, proc->frame_rx, proc->nr_tti_tx, ue->tx_power_dBm[nr_tti_tx], @@ -4577,7 +4576,7 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t if (ue->mac_enabled == 1) nr_Msg1_transmitted(ue->Mod_id, ue->CC_id, frame_tx, gNB_id); - LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d: Generating PRACH (gNB %d) preamble index %d for UL, TX power %d dBm (PL %d dB) \n", + LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_tx %d: Generating PRACH (gNB %d) preamble index %d for UL, TX power %d dBm (PL %d dB) \n", ue->Mod_id, frame_tx, nr_tti_tx, @@ -4591,12 +4590,12 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t if (runmode == calib_prach_tx) ue->prach_resources[gNB_id] = NULL; - LOG_D(PHY,"[UE %d] frame %d nr_tti_rx %d : generate_nr_prach %d, prach_cnt %d\n", ue->Mod_id,frame_tx,nr_tti_tx, ue->generate_nr_prach, ue->prach_cnt); + LOG_D(PHY,"[UE %d] frame %d nr_tti_tx %d : generate_nr_prach %d, prach_cnt %d\n", ue->Mod_id, frame_tx, nr_tti_tx, ue->prach_resources[gNB_id]->generate_nr_prach, ue->prach_cnt); ue->prach_cnt++; if (ue->prach_cnt == 3) - ue->generate_nr_prach = 0; + prach_resources->generate_nr_prach = 0; VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_OUT); } diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index 92765acf41..6f691852da 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -906,12 +906,23 @@ int get_nr_prach_info_from_index(uint8_t index, if ( (table_6_3_3_2_4_prachConfig_Index[index][7] == 1) && (slot%2 == 0) ) return 0; // no prach in even slots @ 120kHz for 1 prach per 60khz slot } - *start_symbol = table_6_3_3_2_4_prachConfig_Index[index][6]; - *N_t_slot = table_6_3_3_2_4_prachConfig_Index[index][8]; - *N_dur = table_6_3_3_2_4_prachConfig_Index[index][9]; - if (table_6_3_3_2_4_prachConfig_Index[index][1] != -1) - format2 = (uint8_t) table_6_3_3_2_4_prachConfig_Index[index][1]; - *format = ((uint8_t) table_6_3_3_2_4_prachConfig_Index[index][0]) | (format2<<8); + if (start_symbol != NULL && N_t_slot != NULL && N_dur != NULL && format != NULL){ + *start_symbol = table_6_3_3_2_4_prachConfig_Index[index][6]; + *N_t_slot = table_6_3_3_2_4_prachConfig_Index[index][8]; + *N_dur = table_6_3_3_2_4_prachConfig_Index[index][9]; + if (table_6_3_3_2_4_prachConfig_Index[index][1] != -1) + format2 = (uint8_t) table_6_3_3_2_4_prachConfig_Index[index][1]; + *format = ((uint8_t) table_6_3_3_2_4_prachConfig_Index[index][0]) | (format2<<8); + LOG_D(MAC,"Frame %d slot %d: Getting PRACH info from index %d absoluteFrequencyPointA %u mu %u frame_type %u start_symbol %u N_t_slot %u N_dur %u \n", frame, + slot, + index, + pointa, + mu, + unpaired, + *start_symbol, + *N_t_slot, + *N_dur); + } return 1; } else @@ -933,12 +944,23 @@ int get_nr_prach_info_from_index(uint8_t index, if ( (table_6_3_3_2_3_prachConfig_Index[index][6] == 1) && (slot%2 == 0) ) return 0; // no prach in even slots @ 30kHz for 1 prach per subframe } - *start_symbol = table_6_3_3_2_3_prachConfig_Index[index][5]; - *N_t_slot = table_6_3_3_2_3_prachConfig_Index[index][7]; - *N_dur = table_6_3_3_2_3_prachConfig_Index[index][8]; - if (table_6_3_3_2_3_prachConfig_Index[index][1] != -1) - format2 = (uint8_t) table_6_3_3_2_3_prachConfig_Index[index][1]; - *format = ((uint8_t) table_6_3_3_2_3_prachConfig_Index[index][0]) | (format2<<8); + if (start_symbol != NULL && N_t_slot != NULL && N_dur != NULL && format != NULL){ + *start_symbol = table_6_3_3_2_3_prachConfig_Index[index][5]; + *N_t_slot = table_6_3_3_2_3_prachConfig_Index[index][7]; + *N_dur = table_6_3_3_2_3_prachConfig_Index[index][8]; + if (table_6_3_3_2_3_prachConfig_Index[index][1] != -1) + format2 = (uint8_t) table_6_3_3_2_3_prachConfig_Index[index][1]; + *format = ((uint8_t) table_6_3_3_2_3_prachConfig_Index[index][0]) | (format2<<8); + LOG_D(MAC,"Frame %d slot %d: Getting PRACH info from index %d absoluteFrequencyPointA %u mu %u frame_type %u start_symbol %u N_t_slot %u N_dur %u \n", frame, + slot, + index, + pointa, + mu, + unpaired, + *start_symbol, + *N_t_slot, + *N_dur); + } return 1; } else @@ -958,12 +980,23 @@ int get_nr_prach_info_from_index(uint8_t index, if ( (table_6_3_3_2_2_prachConfig_Index[index][6] == 1) && (slot%2 == 0) ) return 0; // no prach in even slots @ 30kHz for 1 prach per subframe } - *start_symbol = table_6_3_3_2_2_prachConfig_Index[index][5]; - *N_t_slot = table_6_3_3_2_2_prachConfig_Index[index][7]; - *N_dur = table_6_3_3_2_2_prachConfig_Index[index][8]; - if (table_6_3_3_2_2_prachConfig_Index[index][1] != -1) - format2 = (uint8_t) table_6_3_3_2_2_prachConfig_Index[index][1]; - *format = ((uint8_t) table_6_3_3_2_2_prachConfig_Index[index][0]) | (format2<<8); + if (start_symbol != NULL && N_t_slot != NULL && N_dur != NULL && format != NULL){ + *start_symbol = table_6_3_3_2_2_prachConfig_Index[index][5]; + *N_t_slot = table_6_3_3_2_2_prachConfig_Index[index][7]; + *N_dur = table_6_3_3_2_2_prachConfig_Index[index][8]; + if (table_6_3_3_2_2_prachConfig_Index[index][1] != -1) + format2 = (uint8_t) table_6_3_3_2_2_prachConfig_Index[index][1]; + *format = ((uint8_t) table_6_3_3_2_2_prachConfig_Index[index][0]) | (format2<<8); + LOG_D(MAC,"Frame %d slot %d: Getting PRACH info from index %d absoluteFrequencyPointA %u mu %u frame_type %u start_symbol %u N_t_slot %u N_dur %u \n", frame, + slot, + index, + pointa, + mu, + unpaired, + *start_symbol, + *N_t_slot, + *N_dur); + } return 1; } else @@ -1039,6 +1072,7 @@ uint8_t compute_nr_root_seq(NR_RACH_ConfigCommon_t *rach_config, if (NCS == 0) return nb_preambles; else { r = L_ra/NCS; + printf(" found_sequences %u\n", (nb_preambles/r)); return (nb_preambles/r); } } @@ -1076,6 +1110,7 @@ uint8_t compute_nr_root_seq(NR_RACH_ConfigCommon_t *rach_config, AssertFatal(1==0,"Procedure to find nb of sequences for restricted type B not implemented yet"); } } + printf(" found_sequences %u\n", found_sequences); return found_sequences; } } diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c index 06c89b9ee7..8121d14f4f 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -333,11 +333,15 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); uint8_t lcid = UL_SCH_LCID_CCCH_MSG3, *mac_sdus, *payload, ra_ResponseWindow; + uint8_t config_index, mu; + int is_nr_prach_slot; uint16_t size_sdu = 0; unsigned short post_padding; + fapi_nr_config_request_t *cfg = &mac->phy_config.config_req; NR_ServingCellConfigCommon_t *scc = mac->scc; NR_RACH_ConfigCommon_t *setup = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup; NR_RACH_ConfigGeneric_t *rach_ConfigGeneric = &setup->rach_ConfigGeneric; + NR_FrequencyInfoDL_t *frequencyInfoDL = scc->downlinkConfigCommon->frequencyInfoDL; // int32_t frame_diff = 0; uint8_t sdu_lcids[NB_RB_MAX] = {0}; @@ -350,6 +354,27 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, LOG_D(MAC, "nr_ue_get_rach, RA_active value: %d", mac->RA_active); + config_index = rach_ConfigGeneric->prach_ConfigurationIndex; + if (setup->msg1_SubcarrierSpacing) + mu = *setup->msg1_SubcarrierSpacing; + else + mu = frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing; + + is_nr_prach_slot = get_nr_prach_info_from_index(config_index, + (int)frame, + (int)nr_tti_tx, + frequencyInfoDL->absoluteFrequencyPointA, + mu, + cfg->cell_config.frame_duplex_type, + NULL, + NULL, + NULL, + NULL); + if (is_nr_prach_slot) + prach_resources->generate_nr_prach = 1; + else + prach_resources->generate_nr_prach = 0; + AssertFatal(setup != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); if (mac->RA_active == 0) { From 453d5744335502515ea8a8672f404a514dac8658 Mon Sep 17 00:00:00 2001 From: cig Date: Thu, 26 Mar 2020 16:50:42 +0100 Subject: [PATCH 117/553] Temporary set condition on slot 19 to enter PHY PRACH procedures --- executables/nr-ue.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/executables/nr-ue.c b/executables/nr-ue.c index b064222d04..3a6cd01e36 100644 --- a/executables/nr-ue.c +++ b/executables/nr-ue.c @@ -374,7 +374,7 @@ void processSlotTX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { nr_scheduled_response_t scheduled_response; // program PUSCH. this should actually be done by the MAC upon reception of an UL DCI - if (proc->nr_tti_tx == 8 || UE->frame_parms.frame_type == FDD){ + if (proc->nr_tti_tx == 8 || proc->nr_tti_tx == 19 || UE->frame_parms.frame_type == FDD){ mod_id = UE->Mod_id; From 2c6e49c0dadcb3ba7225aa894321480317b6fa98 Mon Sep 17 00:00:00 2001 From: cig Date: Thu, 26 Mar 2020 16:55:44 +0100 Subject: [PATCH 118/553] Enabled timing offset compensation in RFSIM --- executables/nr-ue.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/executables/nr-ue.c b/executables/nr-ue.c index 3a6cd01e36..894c75beea 100644 --- a/executables/nr-ue.c +++ b/executables/nr-ue.c @@ -624,11 +624,6 @@ void syncInFrame(PHY_VARS_NR_UE *UE, openair0_timestamp *timestamp) { } int computeSamplesShift(PHY_VARS_NR_UE *UE) { - if (IS_SOFTMODEM_RFSIM) { - LOG_E(PHY,"SET rx_offset %d \n",UE->rx_offset); - //UE->rx_offset_diff=0; - return 0; - } // compute TO compensation that should be applied for this frame if ( UE->rx_offset < UE->frame_parms.samples_per_frame/2 && From 6982e6f443180744b1d3154d13a2e1c5e776b9d9 Mon Sep 17 00:00:00 2001 From: cig Date: Thu, 26 Mar 2020 17:46:53 +0100 Subject: [PATCH 119/553] Code cleanup and formatting --- executables/nr-ue.c | 2 +- .../PHY/NR_UE_ESTIMATION/nr_adjust_synch_ue.c | 16 ++++++++-------- openair1/SCHED_NR/fapi_nr_l1.c | 18 ++++++++---------- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 2 +- openair2/LAYER2/NR_MAC_UE/config_ue.c | 15 +++++++-------- openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 18 +++++++++--------- 6 files changed, 34 insertions(+), 37 deletions(-) diff --git a/executables/nr-ue.c b/executables/nr-ue.c index 894c75beea..514d5f0239 100644 --- a/executables/nr-ue.c +++ b/executables/nr-ue.c @@ -420,7 +420,7 @@ void processSlotTX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { nr_ue_scheduled_response(&scheduled_response); if (UE->mode != loop_through_memory) { - uint8_t thread_id = PHY_vars_UE_g[UE->Mod_id][0]->current_thread_id[proc->nr_tti_tx]; + uint8_t thread_id = PHY_vars_UE_g[mod_id][0]->current_thread_id[proc->nr_tti_tx]; phy_procedures_nrUE_TX(UE,proc,0,thread_id); } } diff --git a/openair1/PHY/NR_UE_ESTIMATION/nr_adjust_synch_ue.c b/openair1/PHY/NR_UE_ESTIMATION/nr_adjust_synch_ue.c index cc22e5f7d7..24fcbf2e5b 100644 --- a/openair1/PHY/NR_UE_ESTIMATION/nr_adjust_synch_ue.c +++ b/openair1/PHY/NR_UE_ESTIMATION/nr_adjust_synch_ue.c @@ -35,8 +35,8 @@ void nr_adjust_synch_ue(NR_DL_FRAME_PARMS *frame_parms, PHY_VARS_NR_UE *ue, - module_id_t eNB_id, - uint8_t subframe, + module_id_t gNB_id, + uint8_t subframe, unsigned char clear, short coef) { @@ -60,8 +60,8 @@ void nr_adjust_synch_ue(NR_DL_FRAME_PARMS *frame_parms, temp = 0; for (aa=0; aanb_antennas_rx; aa++) { - Re = ((int16_t*)ue->pbch_vars[eNB_id]->dl_ch_estimates_time[aa])[(i<<1)]; - Im = ((int16_t*)ue->pbch_vars[eNB_id]->dl_ch_estimates_time[aa])[1+(i<<1)]; + Re = ((int16_t*)ue->pbch_vars[gNB_id]->dl_ch_estimates_time[aa])[(i<<1)]; + Im = ((int16_t*)ue->pbch_vars[gNB_id]->dl_ch_estimates_time[aa])[1+(i<<1)]; temp += (Re*Re/2) + (Im*Im/2); } @@ -111,11 +111,11 @@ void nr_adjust_synch_ue(NR_DL_FRAME_PARMS *frame_parms, } } - if ( ue->rx_offset < 0 ) - ue->rx_offset += frame_parms->samples_per_frame; + if (ue->rx_offset < 0) + ue->rx_offset += frame_parms->samples_per_frame; - if ( ue->rx_offset >= frame_parms->samples_per_frame ) - ue->rx_offset -= frame_parms->samples_per_frame; + if (ue->rx_offset >= frame_parms->samples_per_frame) + ue->rx_offset -= frame_parms->samples_per_frame; diff --git a/openair1/SCHED_NR/fapi_nr_l1.c b/openair1/SCHED_NR/fapi_nr_l1.c index 8c2b1fe47a..a2d26765f1 100644 --- a/openair1/SCHED_NR/fapi_nr_l1.c +++ b/openair1/SCHED_NR/fapi_nr_l1.c @@ -200,26 +200,24 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){ // if (UL_tti_req!=NULL) memcpy(&gNB->UL_tti_req,UL_tti_req,sizeof(nfapi_nr_ul_tti_request_t)); for (int i=0;iul_dci_pdu_list[i]); + handle_nfapi_nr_ul_dci_pdu(gNB, frame, slot, &UL_dci_req->ul_dci_pdu_list[i]); } for (int i = 0; i < number_ul_tti_pdu; i++) { switch (UL_tti_req->pdus_list[i].pdu_type) { case NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE: - LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_TTI_PUSCH_PDU_TYPE for %d.%d\n",frame,slot,UL_tti_req->SFN,UL_tti_req->Slot); - nr_fill_ulsch(gNB,UL_tti_req->SFN,UL_tti_req->Slot,&UL_tti_req->pdus_list[i].pusch_pdu); + LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_TTI_PUSCH_PDU_TYPE for %d.%d\n", frame, slot, UL_tti_req->SFN, UL_tti_req->Slot); + nr_fill_ulsch(gNB,UL_tti_req->SFN, UL_tti_req->Slot, &UL_tti_req->pdus_list[i].pusch_pdu); break; case NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE: - LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_TTI_PUCCH_PDU_TYPE for %d.%d\n",frame,slot,UL_tti_req->SFN,UL_tti_req->Slot); - // handle_nfapi_nr_pucch_pdu(gNB,frame,slot,UL_tti_req->pdus_list[i].pucch_pdu); + LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_TTI_PUCCH_PDU_TYPE for %d.%d\n", frame, slot, UL_tti_req->SFN, UL_tti_req->Slot); + // handle_nfapi_nr_pucch_pdu(gNB,frame,slot,UL_tti_req->pdus_list[i].pucch_pdu); break; case NFAPI_NR_UL_CONFIG_PRACH_PDU_TYPE: - LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_TTI_PRACH_PDU_TYPE for %d.%d\n",frame,slot,UL_tti_req->SFN,UL_tti_req->Slot); + LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_TTI_PRACH_PDU_TYPE for %d.%d\n", frame, slot, UL_tti_req->SFN, UL_tti_req->Slot); nfapi_nr_prach_pdu_t *prach_pdu = &UL_tti_req->pdus_list[i].prach_pdu; - nr_fill_prach(gNB,UL_tti_req->SFN,UL_tti_req->Slot,prach_pdu); - nr_fill_prach_ru(gNB->RU_list[0],UL_tti_req->SFN,UL_tti_req->Slot,prach_pdu); + nr_fill_prach(gNB, UL_tti_req->SFN, UL_tti_req->Slot, prach_pdu); + nr_fill_prach_ru(gNB->RU_list[0], UL_tti_req->SFN, UL_tti_req->Slot, prach_pdu); break; } } diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index f4d19850c1..07bb58b2d0 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -4576,7 +4576,7 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t if (ue->mac_enabled == 1) nr_Msg1_transmitted(ue->Mod_id, ue->CC_id, frame_tx, gNB_id); - LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_tx %d: Generating PRACH (gNB %d) preamble index %d for UL, TX power %d dBm (PL %d dB) \n", + LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_tx %d: Generated PRACH Msg1 (gNB %d) preamble index %d for UL, TX power %d dBm (PL %d dB) \n", ue->Mod_id, frame_tx, nr_tti_tx, diff --git a/openair2/LAYER2/NR_MAC_UE/config_ue.c b/openair2/LAYER2/NR_MAC_UE/config_ue.c index 1402bce161..758de4f4af 100755 --- a/openair2/LAYER2/NR_MAC_UE/config_ue.c +++ b/openair2/LAYER2/NR_MAC_UE/config_ue.c @@ -149,8 +149,8 @@ void config_common_ue(NR_UE_MAC_INST_t *mac, NR_ServingCellConfigCommon_t *scc = mac->scc; int i; - mac->phy_config.Mod_id = module_id; - mac->phy_config.CC_id = cc_idP; + mac->phy_config.Mod_id = module_id; + mac->phy_config.CC_id = cc_idP; // carrier config @@ -318,8 +318,7 @@ void config_common_ue(NR_UE_MAC_INST_t *mac, cfg->prach_config.num_prach_fd_occasions_list[i].k1 = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FrequencyStart; cfg->prach_config.num_prach_fd_occasions_list[i].prach_zero_corr_conf = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.zeroCorrelationZoneConfig; - cfg->prach_config.num_prach_fd_occasions_list[i].num_root_sequences = compute_nr_root_seq(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup, - nb_preambles, frame_type); + cfg->prach_config.num_prach_fd_occasions_list[i].num_root_sequences = compute_nr_root_seq(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup, nb_preambles, frame_type); //cfg->prach_config.num_prach_fd_occasions_list[i].num_unused_root_sequences = ??? } @@ -351,10 +350,10 @@ int nr_rrc_mac_config_req_ue( if(spCell_ConfigP != NULL ){ mac->servCellIndex = *spCell_ConfigP->servCellIndex; if (spCell_ConfigP->reconfigurationWithSync) { - mac->scc = spCell_ConfigP->reconfigurationWithSync->spCellConfigCommon; - config_common_ue(mac,module_id,cc_idP); - mac->crnti = spCell_ConfigP->reconfigurationWithSync->newUE_Identity; - LOG_I(MAC,"Configuring CRNTI %x\n",mac->crnti); + mac->scc = spCell_ConfigP->reconfigurationWithSync->spCellConfigCommon; + config_common_ue(mac,module_id,cc_idP); + mac->crnti = spCell_ConfigP->reconfigurationWithSync->newUE_Identity; + LOG_I(MAC,"Configuring CRNTI %x\n",mac->crnti); } mac->scd = spCell_ConfigP->spCellConfigDedicated; diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c index 8121d14f4f..fd1248ea6d 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -414,15 +414,15 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, // initialisation by RRC // CCCH PDU mac_sdus = &payload[sizeof(NR_MAC_SUBHEADER_SHORT)]; - size_sdu = (uint16_t) mac_rrc_data_req_ue(mod_id, - CC_id, - frame, - CCCH, - 1, - mac_sdus, - gNB_id, - 0); - LOG_D(MAC,"[UE %d] Frame %d: Requested RRCConnectionRequest, got %d bytes\n", mod_id,frame, size_sdu); + // size_sdu = (uint16_t) mac_rrc_data_req_ue(mod_id, + // CC_id, + // frame, + // CCCH, + // 1, + // mac_sdus, + // gNB_id, + // 0); + LOG_D(MAC,"[UE %d] Frame %d: Requested RRCConnectionRequest, got %d bytes\n", mod_id, frame, size_sdu); } else { // fill ulsch_buffer with random data for (int i = 0; i < TBS_bytes; i++){ From 3bb1407e547188f90b9b5cd3aa1582d4441afdf6 Mon Sep 17 00:00:00 2001 From: cig Date: Thu, 26 Mar 2020 17:59:11 +0100 Subject: [PATCH 120/553] NR PRACH generation fixes for correct reception of msg1 --- openair1/PHY/NR_UE_TRANSPORT/nr_prach.c | 1321 +++++++++++---------- openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c | 108 +- 2 files changed, 727 insertions(+), 702 deletions(-) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c index 4893168eb4..9f98065e90 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c @@ -19,13 +19,13 @@ * contact@openairinterface.org */ -/*! \file PHY/LTE_TRANSPORT/prach_common.c - * \brief Common routines for UE/eNB PRACH physical channel V8.6 2009-03 - * \author R. Knopp - * \date 2011 - * \version 0.1 - * \company Eurecom - * \email: knopp@eurecom.fr +/*! \file PHY/NR_TRANSPORT/nr_prach.c + * \brief Routines for UE PRACH physical channel + * \author R. Knopp, G. Casati + * \date 2019 + * \version 0.2 + * \company Eurecom, Fraunhofer IIS + * \email: knopp@eurecom.fr, guido.casati@iis.fraunhofer.de * \note * \warning */ @@ -35,6 +35,7 @@ #include "PHY/impl_defs_nr.h" #include "PHY/defs_nr_UE.h" #include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto_common.h" #include "common/utils/LOG/log.h" #include "common/utils/LOG/vcd_signal_dumper.h" @@ -57,69 +58,74 @@ extern int64_t table_6_3_3_2_3_prachConfig_Index [256][9]; extern int64_t table_6_3_3_2_4_prachConfig_Index [256][10]; extern uint16_t nr_du[838]; extern int16_t nr_ru[2*839]; +const char *prachfmt[]={"A1","A2","A3","B1","B2","B3","B4","C0","C2"}; -int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) -{ +// Note: +// - prach_fmt_id is an ID used to map to the corresponding PRACH format value in prachfmt +// WIP todo: +// - take prach start symbol into account +// - idft for short sequence assumes we are transmitting starting in symbol 0 of a PRACH slot +// - Assumes that PRACH SCS is same as PUSCH SCS @ 30 kHz, take values for formats 0-2 and adjust for others below +// - Preamble index different from 0 is not detected by gNB +int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t slot){ - //lte_frame_type_t frame_type = ue->frame_parms.frame_type; - //uint8_t tdd_config = ue->frame_parms.tdd_config; NR_DL_FRAME_PARMS *fp=&ue->frame_parms; - uint16_t rootSequenceIndex = fp->prach_config_common.rootSequenceIndex; - uint8_t Ncs_config = fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig; - uint8_t restricted_set = fp->prach_config_common.prach_ConfigInfo.highSpeedFlag; - uint16_t prach_fmt = ue->prach_resources[gNB_id]->prach_format; - uint8_t preamble_index = ue->prach_resources[gNB_id]->ra_PreambleIndex; - //uint8_t tdd_mapindex = ue->prach_resources[gNB_id]->ra_TDD_map_index; - int16_t *prachF = ue->prach_vars[gNB_id]->prachF; + fapi_nr_config_request_t *nrUE_config = &ue->nrUE_config; + NR_PRACH_RESOURCES_t *prach_resources = ue->prach_resources[gNB_id]; + + uint8_t Mod_id, fd_occasion, preamble_index, restricted_set, not_found; + uint16_t rootSequenceIndex, prach_fmt_id, NCS, *prach_root_sequence_map, preamble_offset; + uint16_t preamble_shift, preamble_index0, n_shift_ra, n_shift_ra_bar, d_start, numshift, N_ZC, u, offset, offset2, first_nonzero_root_idx; int16_t prach_tmp[98304*2*4] __attribute__((aligned(32))); - int16_t *prach = prach_tmp; - int16_t *prach2; - int16_t amp = ue->prach_vars[gNB_id]->amp; - int16_t Ncp; - uint16_t NCS=0; - uint16_t *prach_root_sequence_map; - uint16_t preamble_offset,preamble_shift; - uint16_t preamble_index0,n_shift_ra,n_shift_ra_bar; - uint16_t d_start,numshift; + int16_t Ncp, amp, *prach, *prach2, *prachF, *Xu; + int32_t Xu_re, Xu_im, samp_count; + int prach_start, prach_sequence_length, i, prach_len, dftlen, mu, kbar, K, n_ra_prb, k; + //int restricted_Type; - //uint8_t Nsp=2; - //uint8_t f_ra,t1_ra; - uint16_t N_ZC = (prach_fmt<4)?839:139; - uint8_t not_found; - int16_t *Xu; - uint16_t u; - int32_t Xu_re,Xu_im; - uint16_t offset,offset2; - int prach_start; - int i, prach_len=0; - uint16_t first_nonzero_root_idx=0; + prach = prach_tmp; + prachF = ue->prach_vars[gNB_id]->prachF; + amp = ue->prach_vars[gNB_id]->amp; + Mod_id = ue->Mod_id; + prach_sequence_length = nrUE_config->prach_config.prach_sequence_length; + N_ZC = (prach_sequence_length == 0) ? 839:139; + mu = nrUE_config->prach_config.prach_sub_c_spacing; + restricted_set = fp->prach_config_common.prach_ConfigInfo.highSpeedFlag; + rootSequenceIndex = fp->prach_config_common.rootSequenceIndex; + n_ra_prb = fp->prach_config_common.prach_ConfigInfo.msg1_frequencystart; + NCS = fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig; + prach_fmt_id = prach_resources->prach_format; + preamble_index = 0; //prach_resources->ra_PreambleIndex // temporary hardcoded + fd_occasion = 0; + prach_len = 0; + dftlen = 0; + first_nonzero_root_idx = 0; + kbar = 1; + K = 24; + k = 12*n_ra_prb - 6*fp->N_RB_UL; + //prachStartSymbol = prach_config_pdu->prach_start_symbol + //restricted_Type = 0; -#if defined(OAI_USRP) - prach_start = (ue->rx_offset+subframe*fp->samples_per_subframe-ue->hw_timing_advance-ue->N_TA_offset); -#ifdef NR_PRACH_DEBUG - LOG_I(PHY,"[UE %d] prach_start %d, rx_offset %d, hw_timing_advance %d, N_TA_offset %d\n", ue->Mod_id, - prach_start, - ue->rx_offset, - ue->hw_timing_advance, - ue->N_TA_offset); -#endif + compute_nr_prach_seq(nrUE_config->prach_config.prach_sequence_length, + nrUE_config->prach_config.num_prach_fd_occasions_list[fd_occasion].num_root_sequences, + nrUE_config->prach_config.num_prach_fd_occasions_list[fd_occasion].prach_root_sequence_index, + ue->X_u); - if (prach_start<0) - prach_start+=(fp->samples_per_subframe*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME); + if (mu == 0) + samp_count = fp->samples_per_subframe; + else + samp_count = (slot%(fp->slots_per_subframe/2)) ? fp->samples_per_slotN0 : fp->samples_per_slot0; - if (prach_start>=(fp->samples_per_subframe*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME)) - prach_start-=(fp->samples_per_subframe*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME); + #if defined (OAI_USRP) + prach_start = (ue->rx_offset + slot*samp_count - ue->hw_timing_advance - ue->N_TA_offset); -#else //normal case (simulation) - prach_start = subframe*(fp->samples_per_subframe)-ue->N_TA_offset; - LOG_I(PHY,"[UE %d] prach_start %d, rx_offset %d, hw_timing_advance %d, N_TA_offset %d\n", ue->Mod_id, - prach_start, - ue->rx_offset, - ue->hw_timing_advance, - ue->N_TA_offset); - -#endif + if (prach_start<0) + prach_start += (fp->samples_per_subframe*NR_NUMBER_OF_SUBFRAMES_PER_FRAME); + if (prach_start >= (fp->samples_per_subframe*NR_NUMBER_OF_SUBFRAMES_PER_FRAME)) + prach_start -= (fp->samples_per_subframe*NR_NUMBER_OF_SUBFRAMES_PER_FRAME); + #else //normal case (simulation) + prach_start = slot*(fp->samples_per_subframe)-ue->N_TA_offset; + #endif // First compute physical root sequence /************************************************************************ @@ -129,28 +135,29 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) * NOTE: Restricted set type B is not implemented *************************************************************************/ - int restricted_Type = 0; //this is hardcoded ('0' for restricted_TypeA; and '1' for restricted_TypeB). FIXME - if (prach_fmt<3){ - if (restricted_set == 0) { - NCS = NCS_unrestricted_delta_f_RA_125[Ncs_config]; - } else { - if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_125[Ncs_config]; // for TypeA, this is hardcoded. FIXME - if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_125[Ncs_config]; // for TypeB, this is hardcoded. FIXME - } - } - if (prach_fmt==3){ - if (restricted_set == 0) { - NCS = NCS_unrestricted_delta_f_RA_5[Ncs_config]; - } else { - if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_5[Ncs_config]; // for TypeA, this is hardcoded. FIXME - if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_5[Ncs_config]; // for TypeB, this is hardcoded. FIXME - } - } - if (prach_fmt>3){ - NCS = NCS_unrestricted_delta_f_RA_15[Ncs_config]; - } + // restricted type is hardcoded ('0' for restricted_TypeA; and '1' for restricted_TypeB). FIXME + // uint8_t Ncs_config = fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig; + // if (prach_fmt_id<3){ + // if (restricted_set == 0) { + // NCS = NCS_unrestricted_delta_f_RA_125[Ncs_config]; + // } else { + // if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_125[Ncs_config]; // for TypeA, this is hardcoded. FIXME + // if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_125[Ncs_config]; // for TypeB, this is hardcoded. FIXME + // } + // } + // if (prach_fmt_id==3){ + // if (restricted_set == 0) { + // NCS = NCS_unrestricted_delta_f_RA_5[Ncs_config]; + // } else { + // if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_5[Ncs_config]; // for TypeA, this is hardcoded. FIXME + // if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_5[Ncs_config]; // for TypeB, this is hardcoded. FIXME + // } + // } + // if (prach_fmt_id>3){ + // NCS = NCS_unrestricted_delta_f_RA_15[Ncs_config]; + // } - prach_root_sequence_map = (prach_fmt<4) ? prach_root_sequence_map_0_3 : prach_root_sequence_map_abc; + prach_root_sequence_map = (prach_sequence_length == 0) ? prach_root_sequence_map_0_3 : prach_root_sequence_map_abc; // This is the relative offset (for unrestricted case) in the root sequence table (5.7.2-4 from 36.211) for the given preamble index preamble_offset = ((NCS==0)? preamble_index : (preamble_index/(N_ZC/NCS))); @@ -161,9 +168,9 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) preamble_shift *= NCS; } else { // This is the high-speed case -#ifdef NR_PRACH_DEBUG - LOG_I(PHY,"[UE %d] High-speed mode, NCS_config %d\n",ue->Mod_id,Ncs_config); -#endif + #ifdef NR_PRACH_DEBUG + LOG_I(PHY, "PRACH [UE %d] High-speed mode, NCS %d\n", Mod_id, NCS); + #endif not_found = 1; preamble_index0 = preamble_index; @@ -174,8 +181,9 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) while (not_found == 1) { // current root depending on rootSequenceIndex and preamble_offset int index = (rootSequenceIndex + preamble_offset) % N_ZC; + uint16_t n_group_ra = 0; - if (prach_fmt<4) { + if (prach_fmt_id<4) { // prach_root_sequence_map points to prach_root_sequence_map0_3 DevAssert( index < sizeof(prach_root_sequence_map_0_3) / sizeof(prach_root_sequence_map_0_3[0]) ); } else { @@ -185,8 +193,6 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) u = prach_root_sequence_map[index]; - uint16_t n_group_ra = 0; - if ( (nr_du[u]<(N_ZC/3)) && (nr_du[u]>=NCS) ) { n_shift_ra = nr_du[u]/NCS; d_start = (nr_du[u]<<1) + (n_shift_ra * NCS); @@ -219,50 +225,53 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) } } + preamble_offset = 0; + preamble_shift = 0; + // now generate PRACH signal -#ifdef NR_PRACH_DEBUG - - if (NCS>0) - LOG_I(PHY,"Generate PRACH for RootSeqIndex %d, Preamble Index %d, PRACH Format %x, NCS %d (NCS_config %d, N_ZC/NCS %d): Preamble_offset %d, Preamble_shift %d\n", - rootSequenceIndex, - preamble_index, - prach_fmt, - NCS, - Ncs_config, - N_ZC/NCS, - preamble_offset, - preamble_shift); - -#endif + #ifdef NR_PRACH_DEBUG + if (NCS>0) + LOG_I(PHY, "PRACH [UE %d] generate PRACH for RootSeqIndex %d, Preamble Index %d, PRACH Format %s, NCS %d (N_ZC %d): Preamble_offset %d, Preamble_shift %d\n", Mod_id, + rootSequenceIndex, + preamble_index, + prachfmt[prach_fmt_id], + NCS, + N_ZC, + preamble_offset, + preamble_shift); + #endif // nsymb = (frame_parms->Ncp==0) ? 14:12; - // subframe_offset = (unsigned int)frame_parms->ofdm_symbol_size*subframe*nsymb; - int kbar = 1; - int K = 24; - if (prach_fmt == 3) { - K=4; - kbar=10; + // subframe_offset = (unsigned int)frame_parms->ofdm_symbol_size*slot*nsymb; + + if (prach_sequence_length == 0 && prach_fmt_id == 3) { + K = 4; + kbar = 10; + } else if (prach_sequence_length == 1) { + K = 1; + kbar = 2; } - else if (prach_fmt > 3) { - // Note: Assumes that PRACH SCS is same as PUSCH SCS - K=1; - kbar=2; - } - int n_ra_prb = fp->prach_config_common.prach_ConfigInfo.msg1_frequencystart; - int k = (12*n_ra_prb) - 6*fp->N_RB_UL; - k = (12*n_ra_prb) - 6*fp->N_RB_UL; + if (k<0) + k += fp->ofdm_symbol_size; - if (k<0) k+=fp->ofdm_symbol_size; + k *= K; + k += kbar; + k *= 2; - k*=K; - k+=kbar; - - LOG_I(PHY,"placing prach in position %d\n",k); - k*=2; + LOG_I(PHY, "PRACH [UE %d] in slot %d, placing PRACH in position %d, msg1 frequency start %d, preamble_offset %d, first_nonzero_root_idx %d\n", Mod_id, + slot, + k, + n_ra_prb, + preamble_offset, + first_nonzero_root_idx); Xu = (int16_t*)ue->X_u[preamble_offset-first_nonzero_root_idx]; + #if defined (PRACH_WRITE_OUTPUT_DEBUG) + LOG_M("X_u.m", "X_u", (int16_t*)ue->X_u[preamble_offset-first_nonzero_root_idx], N_ZC, 1, 1); + #endif + /******************************************************** * * In function init_prach_tables: @@ -277,10 +286,86 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe) * *********************************************************/ - AssertFatal(prach_fmt>=3,"prach_fmt<=3: Fix this for other formats\n"); - int dftlen=2048; - if (fp->N_RB_UL >= 137) dftlen=4096; - if (fp->threequarter_fs==1) dftlen=(3*dftlen)/4; + if (fp->N_RB_UL <= 100) + AssertFatal(1 == 0, "N_RB_UL %d not support for NR PRACH yet\n", fp->N_RB_UL); + else if (fp->N_RB_UL < 137) { + if (fp->threequarter_fs == 0) { + //40 MHz @ 61.44 Ms/s + //50 MHz @ 61.44 Ms/s + if (prach_sequence_length == 0) { + if (prach_fmt_id == 0 || prach_fmt_id == 1 || prach_fmt_id == 2) + dftlen = 49152; + if (prach_fmt_id == 3) + dftlen = 12288; + } // 839 sequence + else { + switch (mu){ + case 1: + dftlen = 2048; + break; + default: + AssertFatal(1 == 0, "Shouldn't get here\n"); + break; + } + } + } else { // threequarter sampling + // 40 MHz @ 46.08 Ms/s + if (prach_sequence_length == 0) { + AssertFatal(fp->N_RB_UL <= 107, "cannot do 108..136 PRBs with 3/4 sampling\n"); + if (prach_fmt_id == 0 || prach_fmt_id == 1 || prach_fmt_id == 2) + dftlen = 36864; + if (prach_fmt_id == 3) + dftlen = 9216; + } else { + switch (mu){ + case 1: + dftlen = 1536; + break; + default: + AssertFatal(1 == 0, "Shouldn't get here\n"); + break; + } + } // short format + } // 3/4 sampling + } // <=50 MHz BW + else if (fp->N_RB_UL <= 273) { + if (fp->threequarter_fs == 0) { + //80,90,100 MHz @ 122.88 Ms/s + if (prach_sequence_length == 0) { + if (prach_fmt_id == 0 || prach_fmt_id == 1 || prach_fmt_id == 2) + dftlen = 98304; + if (prach_fmt_id == 3) + dftlen = 24576; + } + } else { // threequarter sampling + switch (mu){ + case 1: + dftlen = 4096; + break; + default: + AssertFatal(1 == 0, "Shouldn't get here\n"); + break; + } + } + } else { + AssertFatal(fp->N_RB_UL <= 217, "cannot do more than 217 PRBs with 3/4 sampling\n"); + // 80 MHz @ 92.16 Ms/s + if (prach_sequence_length == 0) { + if (prach_fmt_id == 0 || prach_fmt_id == 1 || prach_fmt_id == 2) + dftlen = 73728; + if (prach_fmt_id == 3) + dftlen = 18432; + } else { + switch (mu){ + case 1: + dftlen = 3072; + break; + default: + AssertFatal(1 == 0, "Shouldn't get here\n"); + break; + } + } + } for (offset=0,offset2=0; offset>15); prachF[k++]= ((Xu_re*nr_ru[offset2<<1]) - (Xu_im*nr_ru[1+(offset2<<1)]))>>15; prachF[k++]= ((Xu_im*nr_ru[offset2<<1]) + (Xu_re*nr_ru[1+(offset2<<1)]))>>15; + if (k==dftlen) k=0; } - switch (fp->N_RB_UL) { - case 6: - memset((void*)prachF,0,4*1536); - break; + #if defined (PRACH_WRITE_OUTPUT_DEBUG) + LOG_M("prachF.m", "prachF", &prachF[1804], 1024, 1, 1); + LOG_M("Xu.m", "Xu", Xu, N_ZC, 1, 1); + #endif - case 15: - memset((void*)prachF,0,4*3072); - break; + if (prach_sequence_length == 0) { - case 25: - memset((void*)prachF,0,4*6144); - break; + AssertFatal(prach_fmt_id < 4, "Illegal PRACH format %d for sequence length 839\n", prach_fmt_id); - case 50: - memset((void*)prachF,0,4*12288); - break; + switch (prach_fmt_id) { + case 0: + Ncp = 3168; + break; + case 1: + Ncp = 21024; + break; + case 2: + Ncp = 4688; + break; + case 3: + Ncp = 3168; + break; + } - case 75: - memset((void*)prachF,0,4*18432); - break; + } else { - case 100: - if (fp->threequarter_fs == 0) - memset((void*)prachF,0,4*24576); - else - memset((void*)prachF,0,4*18432); - break; + //LOG_D(PHY, "PRACH [UE %d] in slot %d, format %d, msg1 frequency start %d startSymbol %d \n", Mod_id, slot, prachfmt[prach_fmt_id], n_ra_prb, prachStartSymbol); - /*case 106: - memset((void*)prachF,0,4*24576); - break;*/ -} - - int mu = 1; // numerology is hardcoded. FIXME!!! - switch (prach_fmt) { - case 0: - Ncp = 3168; - break; - - case 1: - Ncp = 21024; - break; - - case 2: - Ncp = 4688; - break; - - case 3: - Ncp = 3168; - break; - - case 0xa1: - Ncp = 288/(1<N_RB_UL <= 100) AssertFatal(1==0,"N_RB_UL %d not supported for NR PRACH yet\n",fp->N_RB_UL); else if (fp->N_RB_UL < 137) { // 46.08 or 61.44 Ms/s - if (fp->threequarter_fs==0) { //61.44 Ms/s + if (fp->threequarter_fs == 0) { // full sampling @ 61.44 Ms/s Ncp<<=1; // This is after cyclic prefix (Ncp<<1 samples for 30.72 Ms/s, Ncp<<2 samples for 61.44 Ms/s prach2 = prach+(Ncp<<1); - if (prach_fmt == 0) { //24576 samples @ 30.72 Ms/s, 49152 samples @ 61.44 Ms/s - idft49152(prachF,prach2,1); - // here we have |empty | Prach49152| - memmove(prach,prach+(49152<<1),(Ncp<<2)); - // here we have |Prefix | Prach49152| - prach_len = 49152+Ncp; - dftlen=49152; + if (prach_sequence_length == 0){ + if (prach_fmt_id == 0) { //24576 samples @ 30.72 Ms/s, 49152 samples @ 61.44 Ms/s + idft49152(prachF,prach2,1); + // here we have |empty | Prach49152| + memmove(prach,prach+(49152<<1),(Ncp<<2)); + // here we have |Prefix | Prach49152| + prach_len = 49152+Ncp; + } else if (prach_fmt_id == 1) { //24576 samples @ 30.72 Ms/s, 49152 samples @ 61.44 Ms/s + idft49152(prachF,prach2,1); + memmove(prach2+(49152<<1),prach2,(49152<<2)); + // here we have |empty | Prach49152 | Prach49152| + memmove(prach,prach+(49152<<2),(Ncp<<2)); + // here we have |Prefix | Prach49152 | Prach49152| + prach_len = (49152*2)+Ncp; + } else if (prach_fmt_id == 2) { //24576 samples @ 30.72 Ms/s, 49152 samples @ 61.44 Ms/s + idft49152(prachF,prach2,1); + memmove(prach2+(49152<<1),prach2,(49152<<2)); + // here we have |empty | Prach49152 | Prach49152| empty49152 | empty49152 + memmove(prach2+(49152<<2),prach2,(49152<<3)); + // here we have |empty | Prach49152 | Prach49152| Prach49152 | Prach49152 + memmove(prach,prach+(49152<<3),(Ncp<<2)); + // here we have |Prefix | Prach49152 | Prach49152| Prach49152 | Prach49152 + prach_len = (49152*4)+Ncp; + } else if (prach_fmt_id == 3) { // //6144 samples @ 30.72 Ms/s, 12288 samples @ 61.44 Ms/s + idft12288(prachF,prach2,1); + memmove(prach2+(12288<<1),prach2,(12288<<2)); + // here we have |empty | Prach12288 | Prach12288| empty12288 | empty12288 + memmove(prach2+(12288<<2),prach2,(12288<<3)); + // here we have |empty | Prach12288 | Prach12288| Prach12288 | Prach12288 + memmove(prach,prach+(12288<<3),(Ncp<<2)); + // here we have |Prefix | Prach12288 | Prach12288| Prach12288 | Prach12288 + prach_len = (12288*4)+Ncp; + } + } else { // short PRACH sequence + if (prach_fmt_id == 0 || prach_fmt_id == 3 || prach_fmt_id == 7) { + Ncp+=32; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft2048(prachF,prach2,1); + // here we have |empty | Prach2048 | + if (prach_fmt_id != 7) { + memmove(prach2+(2048<<1),prach2,(2048<<2)); + prach_len = (2048*2)+Ncp; + } + else prach_len = (2048*1)+Ncp; + memmove(prach,prach+(2048<<1),(Ncp<<2)); + // here we have |Prefix | Prach2048 | Prach2048 (if ! 0xc0) | + } else if (prach_fmt_id == 1 || prach_fmt_id == 4) { // 6x2048 + Ncp+=32; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft2048(prachF,prach2,1); + // here we have |empty | Prach2048 | + memmove(prach2+(2048<<1),prach2,(2048<<2)); + // here we have |empty | Prach2048 | Prach2048| empty2048 | empty2048 | + memmove(prach2+(2048<<2),prach2,(2048<<3)); + // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | + memmove(prach,prach+(2048<<1),(Ncp<<2)); + // here we have |Prefix | Prach2048 | + prach_len = (2048*4)+Ncp; + } else if (prach_fmt_id == 2 || prach_fmt_id == 5) { // 6x2048 + Ncp+=32; + prach2 = prach+(Ncp<<1); + idft2048(prachF,prach2,1); + // here we have |empty | Prach2048 | + memmove(prach2+(2048<<1),prach2,(2048<<2)); + // here we have |empty | Prach2048 | Prach2048| empty2048 | empty2048 | empty2048 | empty2048 + memmove(prach2+(2048<<2),prach2,(2048<<3)); + // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | empty2048 | empty2048 + memmove(prach2+(2048<<3),prach2,(2048<<3)); + // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048 + memmove(prach,prach+(2048<<1),(Ncp<<2)); + // here we have |Prefix | Prach2048 | + prach_len = (2048*6)+Ncp; + } else if (prach_fmt_id == 6) { // 12x2048 + Ncp+=32; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft2048(prachF,prach2,1); + // here we have |empty | Prach2048 | + memmove(prach2+(2048<<1),prach2,(2048<<2)); + // here we have |empty | Prach2048 | Prach2048| empty2048 | empty2048 | empty2048 | empty2048 + memmove(prach2+(2048<<2),prach2,(2048<<3)); + // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | empty2048 | empty2048 + memmove(prach2+(2048<<3),prach2,(2048<<3)); + // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048 + memmove(prach2+(2048<<1)*6,prach2,(2048<<2)*6); + // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048| + memmove(prach,prach+(2048<<1),(Ncp<<2)); + // here we have |Prefix | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048| + prach_len = (2048*12)+Ncp; + } } - else if (prach_fmt == 1) { //24576 samples @ 30.72 Ms/s, 49152 samples @ 61.44 Ms/s - idft49152(prachF,prach2,1); - memmove(prach2+(49152<<1),prach2,(49152<<2)); - // here we have |empty | Prach49152 | Prach49152| - memmove(prach,prach+(49152<<2),(Ncp<<2)); - // here we have |Prefix | Prach49152 | Prach49152| - prach_len = (49152*2)+Ncp; - dftlen=49152; - } - else if (prach_fmt == 2) { //24576 samples @ 30.72 Ms/s, 49152 samples @ 61.44 Ms/s - idft49152(prachF,prach2,1); - memmove(prach2+(49152<<1),prach2,(49152<<2)); - // here we have |empty | Prach49152 | Prach49152| empty49152 | empty49152 - memmove(prach2+(49152<<2),prach2,(49152<<3)); - // here we have |empty | Prach49152 | Prach49152| Prach49152 | Prach49152 - memmove(prach,prach+(49152<<3),(Ncp<<2)); - // here we have |Prefix | Prach49152 | Prach49152| Prach49152 | Prach49152 - prach_len = (49152*4)+Ncp; - dftlen=49152; - } - else if (prach_fmt == 3) { // //6144 samples @ 30.72 Ms/s, 12288 samples @ 61.44 Ms/s - idft12288(prachF,prach2,1); - memmove(prach2+(12288<<1),prach2,(12288<<2)); - // here we have |empty | Prach12288 | Prach12288| empty12288 | empty12288 - memmove(prach2+(12288<<2),prach2,(12288<<3)); - // here we have |empty | Prach12288 | Prach12288| Prach12288 | Prach12288 - memmove(prach,prach+(12288<<3),(Ncp<<2)); - // here we have |Prefix | Prach12288 | Prach12288| Prach12288 | Prach12288 - prach_len = (12288*4)+Ncp; - dftlen=12288; - } - else if (prach_fmt == 0xa1 || prach_fmt == 0xb1 || prach_fmt == 0xc0) { - Ncp+=32; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling - prach2 = prach+(Ncp<<1); - idft2048(prachF,prach2,1); - dftlen=2048; - // here we have |empty | Prach2048 | - if (prach_fmt != 0xc0) { - memmove(prach2+(2048<<1),prach2,(2048<<2)); - prach_len = (2048*2)+Ncp; - } - else prach_len = (2048*1)+Ncp; - memmove(prach,prach+(2048<<1),(Ncp<<2)); - // here we have |Prefix | Prach2048 | Prach2048 (if ! 0xc0) | - } - else if (prach_fmt == 0xa2 || prach_fmt == 0xb2) { // 6x2048 - Ncp+=32; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling - prach2 = prach+(Ncp<<1); - idft2048(prachF,prach2,1); - dftlen=2048; - // here we have |empty | Prach2048 | - memmove(prach2+(2048<<1),prach2,(2048<<2)); - // here we have |empty | Prach2048 | Prach2048| empty2048 | empty2048 | - memmove(prach2+(2048<<2),prach2,(2048<<3)); - // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | - memmove(prach,prach+(2048<<1),(Ncp<<2)); - // here we have |Prefix | Prach2048 | - prach_len = (2048*4)+Ncp; - } - else if (prach_fmt == 0xa3 || prach_fmt == 0xb3) { // 6x2048 - Ncp+=32; - prach2 = prach+(Ncp<<1); - idft2048(prachF,prach2,1); - dftlen=2048; - // here we have |empty | Prach2048 | - memmove(prach2+(2048<<1),prach2,(2048<<2)); - // here we have |empty | Prach2048 | Prach2048| empty2048 | empty2048 | empty2048 | empty2048 - memmove(prach2+(2048<<2),prach2,(2048<<3)); - // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | empty2048 | empty2048 - memmove(prach2+(2048<<3),prach2,(2048<<3)); - // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048 - memmove(prach,prach+(2048<<1),(Ncp<<2)); - // here we have |Prefix | Prach2048 | - prach_len = (2048*6)+Ncp; - } - else if (prach_fmt == 0xb4) { // 12x2048 - Ncp+=32; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling - prach2 = prach+(Ncp<<1); - idft2048(prachF,prach2,1); - dftlen=2048; - // here we have |empty | Prach2048 | - memmove(prach2+(2048<<1),prach2,(2048<<2)); - // here we have |empty | Prach2048 | Prach2048| empty2048 | empty2048 | empty2048 | empty2048 - memmove(prach2+(2048<<2),prach2,(2048<<3)); - // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | empty2048 | empty2048 - memmove(prach2+(2048<<3),prach2,(2048<<3)); - // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048 - memmove(prach2+(2048<<1)*6,prach2,(2048<<2)*6); - // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048| - memmove(prach,prach+(2048<<1),(Ncp<<2)); - // here we have |Prefix | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048| - prach_len = (2048*12)+Ncp; - } - - } - else { // 46.08 Ms/s + } else { // threequarter sampling @ 46.08 Ms/s Ncp = (Ncp*3)/2; prach2 = prach+(Ncp<<1); - if (prach_fmt == 0) { - idft36864(prachF,prach2,1); - dftlen=36864; - // here we have |empty | Prach73728| - memmove(prach,prach+(36864<<1),(Ncp<<2)); - // here we have |Prefix | Prach73728| - prach_len = (36864*1)+Ncp; + if (prach_sequence_length == 0){ + if (prach_fmt_id == 0) { + idft36864(prachF,prach2,1); + // here we have |empty | Prach73728| + memmove(prach,prach+(36864<<1),(Ncp<<2)); + // here we have |Prefix | Prach73728| + prach_len = (36864*1)+Ncp; + } else if (prach_fmt_id == 1) { + idft36864(prachF,prach2,1); + memmove(prach2+(36864<<1),prach2,(36864<<2)); + // here we have |empty | Prach73728 | Prach73728| + memmove(prach,prach+(36864<<2),(Ncp<<2)); + // here we have |Prefix | Prach73728 | Prach73728| + prach_len = (36864*2)+Ncp; + } else if (prach_fmt_id == 2) { + idft36864(prachF,prach2,1); + memmove(prach2+(36864<<1),prach2,(36864<<2)); + // here we have |empty | Prach73728 | Prach73728| empty73728 | empty73728 + memmove(prach2+(36864<<2),prach2,(36864<<3)); + // here we have |empty | Prach73728 | Prach73728| Prach73728 | Prach73728 + memmove(prach,prach+(36864<<3),(Ncp<<2)); + // here we have |Prefix | Prach73728 | Prach73728| Prach73728 | Prach73728 + prach_len = (36864*4)+Ncp; + } else if (prach_fmt_id == 3) { + idft9216(prachF,prach2,1); + memmove(prach2+(9216<<1),prach2,(9216<<2)); + // here we have |empty | Prach9216 | Prach9216| empty9216 | empty9216 + memmove(prach2+(9216<<2),prach2,(9216<<3)); + // here we have |empty | Prach9216 | Prach9216| Prach9216 | Prach9216 + memmove(prach,prach+(9216<<3),(Ncp<<2)); + // here we have |Prefix | Prach9216 | Prach9216| Prach9216 | Prach9216 + prach_len = (9216*4)+Ncp; + } + } else { // short sequence + if (prach_fmt_id == 0 || prach_fmt_id == 3 || prach_fmt_id == 7) { + Ncp+=24; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft1536(prachF,prach2,1); + + // here we have |empty | Prach1536 | + if (prach_fmt_id != 7) { + memmove(prach2+(1536<<1),prach2,(1536<<2)); + prach_len = (1536*2)+Ncp; + } else prach_len = (1536*1)+Ncp; + + memmove(prach,prach+(1536<<1),(Ncp<<2)); + // here we have |Prefix | Prach1536 | Prach1536 (if ! 0xc0) | + + } else if (prach_fmt_id == 1 || prach_fmt_id == 4) { // 6x1536 + + printf(" CHECK 3/4 sampling prachFormat == 0xa2\n"); + + Ncp+=24; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft1536(prachF,prach2,1); + // here we have |empty | Prach1536 | + memmove(prach2+(1536<<1),prach2,(1536<<2)); + // here we have |empty | Prach1536 | Prach1536| empty1536 | empty1536 | + memmove(prach2+(1536<<2),prach2,(1536<<3)); + // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | + memmove(prach,prach+(1536<<1),(Ncp<<2)); + // here we have |Prefix | Prach1536 | + prach_len = (1536*4)+Ncp; + } else if (prach_fmt_id == 2 || prach_fmt_id == 5) { // 6x1536 + Ncp+=24; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft1536(prachF,prach2,1); + // here we have |empty | Prach1536 | + memmove(prach2+(1536<<1),prach2,(1536<<2)); + // here we have |empty | Prach1536 | Prach1536| empty1536 | empty1536 | empty1536 | empty1536 + memmove(prach2+(1536<<2),prach2,(1536<<3)); + // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | empty1536 | empty1536 + memmove(prach2+(1536<<3),prach2,(1536<<3)); + // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536 + memmove(prach,prach+(1536<<1),(Ncp<<2)); + // here we have |Prefix | Prach1536 | + prach_len = (1536*6)+Ncp; + } else if (prach_fmt_id == 6) { // 12x1536 + Ncp+=24; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft1536(prachF,prach2,1); + // here we have |empty | Prach1536 | + memmove(prach2+(1536<<1),prach2,(1536<<2)); + // here we have |empty | Prach1536 | Prach1536| empty1536 | empty1536 | empty1536 | empty1536 + memmove(prach2+(1536<<2),prach2,(1536<<3)); + // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | empty1536 | empty1536 + memmove(prach2+(1536<<3),prach2,(1536<<3)); + // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536 + memmove(prach2+(1536<<1)*6,prach2,(1536<<2)*6); + // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536| + memmove(prach,prach+(1536<<1),(Ncp<<2)); + // here we have |Prefix | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536| + prach_len = (1536*12)+Ncp; + } } - else if (prach_fmt == 1) { - idft36864(prachF,prach2,1); - dftlen=36864; - memmove(prach2+(36864<<1),prach2,(36864<<2)); - // here we have |empty | Prach73728 | Prach73728| - memmove(prach,prach+(36864<<2),(Ncp<<2)); - // here we have |Prefix | Prach73728 | Prach73728| - prach_len = (36864*2)+Ncp; - } - if (prach_fmt == 2) { - idft36864(prachF,prach2,1); - dftlen=36864; - memmove(prach2+(36864<<1),prach2,(36864<<2)); - // here we have |empty | Prach73728 | Prach73728| empty73728 | empty73728 - memmove(prach2+(36864<<2),prach2,(36864<<3)); - // here we have |empty | Prach73728 | Prach73728| Prach73728 | Prach73728 - memmove(prach,prach+(36864<<3),(Ncp<<2)); - // here we have |Prefix | Prach73728 | Prach73728| Prach73728 | Prach73728 - prach_len = (36864*4)+Ncp; - } - else if (prach_fmt == 3) { - idft9216(prachF,prach2,1); - dftlen=36864; - memmove(prach2+(9216<<1),prach2,(9216<<2)); - // here we have |empty | Prach9216 | Prach9216| empty9216 | empty9216 - memmove(prach2+(9216<<2),prach2,(9216<<3)); - // here we have |empty | Prach9216 | Prach9216| Prach9216 | Prach9216 - memmove(prach,prach+(9216<<3),(Ncp<<2)); - // here we have |Prefix | Prach9216 | Prach9216| Prach9216 | Prach9216 - prach_len = (9216*4)+Ncp; - } - else if (prach_fmt == 0xa1 || prach_fmt == 0xb1 || prach_fmt == 0xc0) { - Ncp+=24; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling - prach2 = prach+(Ncp<<1); - idft1536(prachF,prach2,1); - dftlen=1536; - // here we have |empty | Prach1536 | - if (prach_fmt != 0xc0) { - memmove(prach2+(1536<<1),prach2,(1536<<2)); - prach_len = (1536*2)+Ncp; - } - else prach_len = (1536*1)+Ncp; - memmove(prach,prach+(1536<<1),(Ncp<<2)); - // here we have |Prefix | Prach1536 | Prach1536 (if ! 0xc0) | - - } - else if (prach_fmt == 0xa2 || prach_fmt == 0xb2) { // 6x1536 - Ncp+=24; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling - prach2 = prach+(Ncp<<1); - idft1536(prachF,prach2,1); - dftlen=1536; - // here we have |empty | Prach1536 | - memmove(prach2+(1536<<1),prach2,(1536<<2)); - // here we have |empty | Prach1536 | Prach1536| empty1536 | empty1536 | - memmove(prach2+(1536<<2),prach2,(1536<<3)); - // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | - memmove(prach,prach+(1536<<1),(Ncp<<2)); - // here we have |Prefix | Prach1536 | - prach_len = (1536*4)+Ncp; - } - else if (prach_fmt == 0xa3 || prach_fmt == 0xb3) { // 6x1536 - Ncp+=24; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling - prach2 = prach+(Ncp<<1); - idft1536(prachF,prach2,1); - dftlen=1536; - // here we have |empty | Prach1536 | - memmove(prach2+(1536<<1),prach2,(1536<<2)); - // here we have |empty | Prach1536 | Prach1536| empty1536 | empty1536 | empty1536 | empty1536 - memmove(prach2+(1536<<2),prach2,(1536<<3)); - // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | empty1536 | empty1536 - memmove(prach2+(1536<<3),prach2,(1536<<3)); - // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536 - memmove(prach,prach+(1536<<1),(Ncp<<2)); - // here we have |Prefix | Prach1536 | - prach_len = (1536*6)+Ncp; - } - else if (prach_fmt == 0xb4) { // 12x1536 - Ncp+=24; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling - prach2 = prach+(Ncp<<1); - idft1536(prachF,prach2,1); - dftlen=1536; - // here we have |empty | Prach1536 | - memmove(prach2+(1536<<1),prach2,(1536<<2)); - // here we have |empty | Prach1536 | Prach1536| empty1536 | empty1536 | empty1536 | empty1536 - memmove(prach2+(1536<<2),prach2,(1536<<3)); - // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | empty1536 | empty1536 - memmove(prach2+(1536<<3),prach2,(1536<<3)); - // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536 - memmove(prach2+(1536<<1)*6,prach2,(1536<<2)*6); - // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536| - memmove(prach,prach+(1536<<1),(Ncp<<2)); - // here we have |Prefix | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536| - prach_len = (1536*12)+Ncp; - } } - } - else if (fp->N_RB_UL <= 273) {// 92.16 or 122.88 Ms/s - if (fp->threequarter_fs==0) { //122.88 Ms/s + } else if (fp->N_RB_UL <= 273) {// 92.16 or 122.88 Ms/s + if (fp->threequarter_fs == 0) { // full sampling @ 122.88 Ms/s Ncp<<=2; prach2 = prach+(Ncp<<1); - if (prach_fmt == 0) { //24576 samples @ 30.72 Ms/s, 98304 samples @ 122.88 Ms/s - idft98304(prachF,prach2,1); - dftlen=98304; - // here we have |empty | Prach98304| - memmove(prach,prach+(98304<<1),(Ncp<<2)); - // here we have |Prefix | Prach98304| - prach_len = (98304*1)+Ncp; + if (prach_sequence_length == 0){ + if (prach_fmt_id == 0) { //24576 samples @ 30.72 Ms/s, 98304 samples @ 122.88 Ms/s + idft98304(prachF,prach2,1); + // here we have |empty | Prach98304| + memmove(prach,prach+(98304<<1),(Ncp<<2)); + // here we have |Prefix | Prach98304| + prach_len = (98304*1)+Ncp; + } else if (prach_fmt_id == 1) { + idft98304(prachF,prach2,1); + memmove(prach2+(98304<<1),prach2,(98304<<2)); + // here we have |empty | Prach98304 | Prach98304| + memmove(prach,prach+(98304<<2),(Ncp<<2)); + // here we have |Prefix | Prach98304 | Prach98304| + prach_len = (98304*2)+Ncp; + } else if (prach_fmt_id == 2) { + idft98304(prachF,prach2,1); + memmove(prach2+(98304<<1),prach2,(98304<<2)); + // here we have |empty | Prach98304 | Prach98304| empty98304 | empty98304 + memmove(prach2+(98304<<2),prach2,(98304<<3)); + // here we have |empty | Prach98304 | Prach98304| Prach98304 | Prach98304 + memmove(prach,prach+(98304<<3),(Ncp<<2)); + // here we have |Prefix | Prach98304 | Prach98304| Prach98304 | Prach98304 + prach_len = (98304*4)+Ncp; + } else if (prach_fmt_id == 3) { // 4x6144, Ncp 3168 + idft24576(prachF,prach2,1); + memmove(prach2+(24576<<1),prach2,(24576<<2)); + // here we have |empty | Prach24576 | Prach24576| empty24576 | empty24576 + memmove(prach2+(24576<<2),prach2,(24576<<3)); + // here we have |empty | Prach24576 | Prach24576| Prach24576 | Prach24576 + memmove(prach,prach+(24576<<3),(Ncp<<2)); + // here we have |Prefix | Prach24576 | Prach24576| Prach24576 | Prach24576 + prach_len = (24576*4)+Ncp; + } + } else { // short sequence + if (prach_fmt_id == 0 || prach_fmt_id == 3 || prach_fmt_id == 7) { + Ncp+=64; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft4096(prachF,prach2,1); + // here we have |empty | Prach4096 | + if (prach_fmt_id != 7) { + memmove(prach2+(4096<<1),prach2,(4096<<2)); + prach_len = (4096*2)+Ncp; + } else prach_len = (4096*1)+Ncp; + memmove(prach,prach+(4096<<1),(Ncp<<2)); + // here we have |Prefix | Prach4096 | Prach4096 (if ! 0xc0) | + } else if (prach_fmt_id == 1 || prach_fmt_id == 4) { // 4x4096 + Ncp+=64; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft4096(prachF,prach2,1); + // here we have |empty | Prach4096 | + memmove(prach2+(4096<<1),prach2,(4096<<2)); + // here we have |empty | Prach4096 | Prach4096| empty4096 | empty4096 | + memmove(prach2+(4096<<2),prach2,(4096<<3)); + // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | + memmove(prach,prach+(4096<<1),(Ncp<<2)); + // here we have |Prefix | Prach4096 | + prach_len = (4096*4)+Ncp; + } else if (prach_fmt_id == 2 || prach_fmt_id == 5) { // 6x4096 + Ncp+=64; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft4096(prachF,prach2,1); + // here we have |empty | Prach4096 | + memmove(prach2+(4096<<1),prach2,(4096<<2)); + // here we have |empty | Prach4096 | Prach4096| empty4096 | empty4096 | empty4096 | empty4096 + memmove(prach2+(4096<<2),prach2,(4096<<3)); + // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | empty4096 | empty4096 + memmove(prach2+(4096<<3),prach2,(4096<<3)); + // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096 + memmove(prach,prach+(4096<<1),(Ncp<<2)); + // here we have |Prefix | Prach4096 | + prach_len = (4096*6)+Ncp; + } else if (prach_fmt_id == 6) { // 12x4096 + Ncp+=64; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft4096(prachF,prach2,1); + // here we have |empty | Prach4096 | + memmove(prach2+(4096<<1),prach2,(4096<<2)); + // here we have |empty | Prach4096 | Prach4096| empty4096 | empty4096 | empty4096 | empty4096 + memmove(prach2+(4096<<2),prach2,(4096<<3)); + // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | empty4096 | empty4096 + memmove(prach2+(4096<<3),prach2,(4096<<3)); + // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096 + memmove(prach2+(4096<<1)*6,prach2,(4096<<2)*6); + // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096| + memmove(prach,prach+(4096<<1),(Ncp<<2)); + // here we have |Prefix | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096| + prach_len = (4096*12)+Ncp; + } } - else if (prach_fmt == 1) { - idft98304(prachF,prach2,1); - dftlen=98304; - memmove(prach2+(98304<<1),prach2,(98304<<2)); - // here we have |empty | Prach98304 | Prach98304| - memmove(prach,prach+(98304<<2),(Ncp<<2)); - // here we have |Prefix | Prach98304 | Prach98304| - prach_len = (98304*2)+Ncp; - } - else if (prach_fmt == 2) { - idft98304(prachF,prach2,1); - dftlen=98304; - memmove(prach2+(98304<<1),prach2,(98304<<2)); - // here we have |empty | Prach98304 | Prach98304| empty98304 | empty98304 - memmove(prach2+(98304<<2),prach2,(98304<<3)); - // here we have |empty | Prach98304 | Prach98304| Prach98304 | Prach98304 - memmove(prach,prach+(98304<<3),(Ncp<<2)); - // here we have |Prefix | Prach98304 | Prach98304| Prach98304 | Prach98304 - prach_len = (98304*4)+Ncp; - } - else if (prach_fmt == 3) { // 4x6144, Ncp 3168 - idft24576(prachF,prach2,1); - dftlen=24576; - memmove(prach2+(24576<<1),prach2,(24576<<2)); - // here we have |empty | Prach24576 | Prach24576| empty24576 | empty24576 - memmove(prach2+(24576<<2),prach2,(24576<<3)); - // here we have |empty | Prach24576 | Prach24576| Prach24576 | Prach24576 - memmove(prach,prach+(24576<<3),(Ncp<<2)); - // here we have |Prefix | Prach24576 | Prach24576| Prach24576 | Prach24576 - prach_len = (24576*4)+Ncp; - } - else if (prach_fmt == 0xa1 || prach_fmt == 0xb1 || prach_fmt == 0xc0) { - Ncp+=64; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling - prach2 = prach+(Ncp<<1); - idft4096(prachF,prach2,1); - dftlen=4096; - // here we have |empty | Prach4096 | - if (prach_fmt != 0xc0) { - memmove(prach2+(4096<<1),prach2,(4096<<2)); - prach_len = (4096*2)+Ncp; - } - else prach_len = (4096*1)+Ncp; - memmove(prach,prach+(4096<<1),(Ncp<<2)); - // here we have |Prefix | Prach4096 | Prach4096 (if ! 0xc0) | - - } - else if (prach_fmt == 0xa2 || prach_fmt == 0xb2) { // 4x4096 - Ncp+=64; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling - prach2 = prach+(Ncp<<1); - idft4096(prachF,prach2,1); - dftlen=4096; - // here we have |empty | Prach4096 | - memmove(prach2+(4096<<1),prach2,(4096<<2)); - // here we have |empty | Prach4096 | Prach4096| empty4096 | empty4096 | - memmove(prach2+(4096<<2),prach2,(4096<<3)); - // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | - memmove(prach,prach+(4096<<1),(Ncp<<2)); - // here we have |Prefix | Prach4096 | - prach_len = (4096*4)+Ncp; - } - else if (prach_fmt == 0xa3 || prach_fmt == 0xb3) { // 6x4096 - Ncp+=64; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling - prach2 = prach+(Ncp<<1); - idft4096(prachF,prach2,1); - dftlen=4096; - // here we have |empty | Prach4096 | - memmove(prach2+(4096<<1),prach2,(4096<<2)); - // here we have |empty | Prach4096 | Prach4096| empty4096 | empty4096 | empty4096 | empty4096 - memmove(prach2+(4096<<2),prach2,(4096<<3)); - // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | empty4096 | empty4096 - memmove(prach2+(4096<<3),prach2,(4096<<3)); - // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096 - memmove(prach,prach+(4096<<1),(Ncp<<2)); - // here we have |Prefix | Prach4096 | - prach_len = (4096*6)+Ncp; - } - else if (prach_fmt == 0xb4) { // 12x4096 - Ncp+=64; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling - prach2 = prach+(Ncp<<1); - idft4096(prachF,prach2,1); - dftlen=4096; - // here we have |empty | Prach4096 | - memmove(prach2+(4096<<1),prach2,(4096<<2)); - // here we have |empty | Prach4096 | Prach4096| empty4096 | empty4096 | empty4096 | empty4096 - memmove(prach2+(4096<<2),prach2,(4096<<3)); - // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | empty4096 | empty4096 - memmove(prach2+(4096<<3),prach2,(4096<<3)); - // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096 - memmove(prach2+(4096<<1)*6,prach2,(4096<<2)*6); - // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096| - memmove(prach,prach+(4096<<1),(Ncp<<2)); - // here we have |Prefix | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096| - prach_len = (4096*12)+Ncp; - } - } - else { // 92.16 Ms/s + } else { // three quarter sampling @ 92.16 Ms/s Ncp = (Ncp*3); prach2 = prach+(Ncp<<1); - if (prach_fmt == 0) { - idft73728(prachF,prach2,1); - dftlen=73728; - // here we have |empty | Prach73728| - memmove(prach,prach+(73728<<1),(Ncp<<2)); - // here we have |Prefix | Prach73728| - prach_len = (73728*1)+Ncp; - } - else if (prach_fmt == 1) { - idft73728(prachF,prach2,1); - dftlen=73728; - memmove(prach2+(73728<<1),prach2,(73728<<2)); - // here we have |empty | Prach73728 | Prach73728| - memmove(prach,prach+(73728<<2),(Ncp<<2)); - // here we have |Prefix | Prach73728 | Prach73728| - prach_len = (73728*2)+Ncp; - } - if (prach_fmt == 2) { - idft73728(prachF,prach2,1); - dftlen=73728; - memmove(prach2+(73728<<1),prach2,(73728<<2)); - // here we have |empty | Prach73728 | Prach73728| empty73728 | empty73728 - memmove(prach2+(73728<<2),prach2,(73728<<3)); - // here we have |empty | Prach73728 | Prach73728| Prach73728 | Prach73728 - memmove(prach,prach+(73728<<3),(Ncp<<2)); - // here we have |Prefix | Prach73728 | Prach73728| Prach73728 | Prach73728 - prach_len = (73728*4)+Ncp; - } - else if (prach_fmt == 3) { - idft18432(prachF,prach2,1); - dftlen=18432; - memmove(prach2+(18432<<1),prach2,(18432<<2)); - // here we have |empty | Prach18432 | Prach18432| empty18432 | empty18432 - memmove(prach2+(18432<<2),prach2,(18432<<3)); - // here we have |empty | Prach18432 | Prach18432| Prach18432 | Prach18432 - memmove(prach,prach+(18432<<3),(Ncp<<2)); - // here we have |Prefix | Prach18432 | Prach18432| Prach18432 | Prach18432 - prach_len = (18432*4)+Ncp; - } - else if (prach_fmt == 0xa1 || prach_fmt == 0xb1 || prach_fmt == 0xc0) { - Ncp+=48; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling - prach2 = prach+(Ncp<<1); - idft3072(prachF,prach2,1); - dftlen=3072; - // here we have |empty | Prach3072 | - if (prach_fmt != 0xc0) { - memmove(prach2+(3072<<1),prach2,(3072<<2)); - prach_len = (3072*2)+Ncp; - } - else prach_len = (3072*1)+Ncp; - memmove(prach,prach+(3072<<1),(Ncp<<2)); - // here we have |Prefix | Prach3072 | Prach3072 (if ! 0xc0) | - } - else if (prach_fmt == 0xa3 || prach_fmt == 0xb3) { // 6x3072 - Ncp+=48; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling - prach2 = prach+(Ncp<<1); - idft3072(prachF,prach2,1); - dftlen=3072; - // here we have |empty | Prach3072 | - memmove(prach2+(3072<<1),prach2,(3072<<2)); - // here we have |empty | Prach3072 | Prach3072| empty3072 | empty3072 | empty3072 | empty3072 - memmove(prach2+(3072<<2),prach2,(3072<<3)); - // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | empty3072 | empty3072 - memmove(prach2+(3072<<3),prach2,(3072<<3)); - // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072 - memmove(prach,prach+(3072<<1),(Ncp<<2)); - // here we have |Prefix | Prach3072 | - prach_len = (3072*6)+Ncp; - } - else if (prach_fmt == 0xa2 || prach_fmt == 0xb2) { // 4x3072 - Ncp+=48; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling - prach2 = prach+(Ncp<<1); - idft3072(prachF,prach2,1); - dftlen=3072; - // here we have |empty | Prach3072 | - memmove(prach2+(3072<<1),prach2,(3072<<2)); - // here we have |empty | Prach3072 | Prach3072| empty3072 | empty3072 | - memmove(prach2+(3072<<2),prach2,(3072<<3)); - // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | - memmove(prach,prach+(3072<<1),(Ncp<<2)); - // here we have |Prefix | Prach3072 | - prach_len = (3072*4)+Ncp; - } - else if (prach_fmt == 0xb4) { // 12x3072 - Ncp+=48; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling - prach2 = prach+(Ncp<<1); - idft3072(prachF,prach2,1); - dftlen=3072; - // here we have |empty | Prach3072 | - memmove(prach2+(3072<<1),prach2,(3072<<2)); - // here we have |empty | Prach3072 | Prach3072| empty3072 | empty3072 | empty3072 | empty3072 - memmove(prach2+(3072<<2),prach2,(3072<<3)); - // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | empty3072 | empty3072 - memmove(prach2+(3072<<3),prach2,(3072<<3)); - // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072 - memmove(prach2+(3072<<1)*6,prach2,(3072<<2)*6); - // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072| - memmove(prach,prach+(3072<<1),(Ncp<<2)); - // here we have |Prefix | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072| - prach_len = (3072*12)+Ncp; + if (prach_sequence_length == 0){ + if (prach_fmt_id == 0) { + idft73728(prachF,prach2,1); + // here we have |empty | Prach73728| + memmove(prach,prach+(73728<<1),(Ncp<<2)); + // here we have |Prefix | Prach73728| + prach_len = (73728*1)+Ncp; + } else if (prach_fmt_id == 1) { + idft73728(prachF,prach2,1); + memmove(prach2+(73728<<1),prach2,(73728<<2)); + // here we have |empty | Prach73728 | Prach73728| + memmove(prach,prach+(73728<<2),(Ncp<<2)); + // here we have |Prefix | Prach73728 | Prach73728| + prach_len = (73728*2)+Ncp; + } if (prach_fmt_id == 2) { + idft73728(prachF,prach2,1); + memmove(prach2+(73728<<1),prach2,(73728<<2)); + // here we have |empty | Prach73728 | Prach73728| empty73728 | empty73728 + memmove(prach2+(73728<<2),prach2,(73728<<3)); + // here we have |empty | Prach73728 | Prach73728| Prach73728 | Prach73728 + memmove(prach,prach+(73728<<3),(Ncp<<2)); + // here we have |Prefix | Prach73728 | Prach73728| Prach73728 | Prach73728 + prach_len = (73728*4)+Ncp; + } else if (prach_fmt_id == 3) { + idft18432(prachF,prach2,1); + memmove(prach2+(18432<<1),prach2,(18432<<2)); + // here we have |empty | Prach18432 | Prach18432| empty18432 | empty18432 + memmove(prach2+(18432<<2),prach2,(18432<<3)); + // here we have |empty | Prach18432 | Prach18432| Prach18432 | Prach18432 + memmove(prach,prach+(18432<<3),(Ncp<<2)); + // here we have |Prefix | Prach18432 | Prach18432| Prach18432 | Prach18432 + prach_len = (18432*4)+Ncp; + } + } else { // short sequence + if (prach_fmt_id == 0 || prach_fmt_id == 3 || prach_fmt_id == 7) { + Ncp+=48; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft3072(prachF,prach2,1); + // here we have |empty | Prach3072 | + if (prach_fmt_id != 7) { + memmove(prach2+(3072<<1),prach2,(3072<<2)); + prach_len = (3072*2)+Ncp; + } else prach_len = (3072*1)+Ncp; + memmove(prach,prach+(3072<<1),(Ncp<<2)); + // here we have |Prefix | Prach3072 | Prach3072 (if ! 0xc0) | + } else if (prach_fmt_id == 2 || prach_fmt_id == 5) { // 6x3072 + Ncp+=48; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft3072(prachF,prach2,1); + // here we have |empty | Prach3072 | + memmove(prach2+(3072<<1),prach2,(3072<<2)); + // here we have |empty | Prach3072 | Prach3072| empty3072 | empty3072 | empty3072 | empty3072 + memmove(prach2+(3072<<2),prach2,(3072<<3)); + // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | empty3072 | empty3072 + memmove(prach2+(3072<<3),prach2,(3072<<3)); + // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072 + memmove(prach,prach+(3072<<1),(Ncp<<2)); + // here we have |Prefix | Prach3072 | + prach_len = (3072*6)+Ncp; + } else if (prach_fmt_id == 1 || prach_fmt_id == 4) { // 4x3072 + Ncp+=48; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft3072(prachF,prach2,1); + // here we have |empty | Prach3072 | + memmove(prach2+(3072<<1),prach2,(3072<<2)); + // here we have |empty | Prach3072 | Prach3072| empty3072 | empty3072 | + memmove(prach2+(3072<<2),prach2,(3072<<3)); + // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | + memmove(prach,prach+(3072<<1),(Ncp<<2)); + // here we have |Prefix | Prach3072 | + prach_len = (3072*4)+Ncp; + } else if (prach_fmt_id == 6) { // 12x3072 + Ncp+=48; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft3072(prachF,prach2,1); + // here we have |empty | Prach3072 | + memmove(prach2+(3072<<1),prach2,(3072<<2)); + // here we have |empty | Prach3072 | Prach3072| empty3072 | empty3072 | empty3072 | empty3072 + memmove(prach2+(3072<<2),prach2,(3072<<3)); + // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | empty3072 | empty3072 + memmove(prach2+(3072<<3),prach2,(3072<<3)); + // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072 + memmove(prach2+(3072<<1)*6,prach2,(3072<<2)*6); + // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072| + memmove(prach,prach+(3072<<1),(Ncp<<2)); + // here we have |Prefix | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072| + prach_len = (3072*12)+Ncp; + } } } - } - - - - -#if defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) - int j; - int overflow = prach_start + prach_len - LTE_NUMBER_OF_SUBFRAMES_PER_FRAME*fp->samples_per_subframe; - LOG_D( PHY, "prach_start=%d, overflow=%d\n", prach_start, overflow ); - - for (i=prach_start,j=0; isamples_per_subframe*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME,prach_start+prach_len); i++,j++) { - ((int16_t*)ue->common_vars.txdata[0])[2*i] = prach[2*j]; - ((int16_t*)ue->common_vars.txdata[0])[2*i+1] = prach[2*j+1]; } - for (i=0; icommon_vars.txdata[0])[2*i] = prach[2*j]; - ((int16_t*)ue->common_vars.txdata[0])[2*i+1] = prach[2*j+1]; - } -#else + #ifdef NR_PRACH_DEBUG + LOG_I(PHY, "PRACH [UE %d] N_RB_UL %d prach_start %d, prach_len %d, rx_offset %d, hw_timing_advance %d, N_TA_offset %d\n", Mod_id, + fp->N_RB_UL, + prach_start, + prach_len, + ue->rx_offset, + ue->hw_timing_advance, + ue->N_TA_offset); + #endif - LOG_D( PHY, "prach_start=%d\n", prach_start); + #if defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) + int j, overflow = prach_start + prach_len - NR_NUMBER_OF_SUBFRAMES_PER_FRAME*fp->samples_per_subframe; - for (i=0; icommon_vars.txdata[0][prach_start]))[2*i] = prach[2*i]; - ((int16_t*)(&ue->common_vars.txdata[0][prach_start]))[2*i+1] = prach[2*i+1]; - } -#endif + #ifdef NR_PRACH_DEBUG + LOG_I( PHY, "PRACH [UE %d] overflow = %d\n", Mod_id, overflow); + #endif + // prach_start=414.730, overflow=-39470 prach_len=6600 fp->samples_per_subframe*NR_NUMBER_OF_SUBFRAMES_PER_FRAME 460.800 prach_start+prach_len 421.330 fp->samples_per_subframe 46080 + // from prach_start=414.730 to prach_start+prach_len 421.330 + for (i = prach_start, j = 0; i < min(fp->samples_per_subframe*NR_NUMBER_OF_SUBFRAMES_PER_FRAME, prach_start + prach_len); i++, j++) { + ((int16_t*)ue->common_vars.txdata[0])[2*i] = prach[2*j]; + ((int16_t*)ue->common_vars.txdata[0])[2*i+1] = prach[2*j+1]; + } -#if defined(PRACH_WRITE_OUTPUT_DEBUG) - LOG_M("prach_txF0.m","prachtxF0",prachF,prach_len-Ncp,1,1); - LOG_M("prach_tx0.m","prachtx0",prach+(Ncp<<1),prach_len-Ncp,1,1); - LOG_M("txsig.m","txs",(int16_t*)(&ue->common_vars.txdata[0][prach_start]),fp->samples_per_subframe,1,1); - exit(-1); -#endif + for (i = 0; i < overflow; i++,j++) { + ((int16_t*)ue->common_vars.txdata[0])[2*i] = prach[2*j]; + ((int16_t*)ue->common_vars.txdata[0])[2*i+1] = prach[2*j+1]; + } + #else // simulators + for (i=0; icommon_vars.txdata[0][prach_start]))[2*i] = prach[2*i]; + ((int16_t*)(&ue->common_vars.txdata[0][prach_start]))[2*i+1] = prach[2*i+1]; + } + #endif - return signal_energy( (int*)prach, 256 ); + //printf("----------------------\n"); + //for(int ii = prach_start; ii<2*(prach_start + prach_len); ii++){ + // printf("PRACH rx data[%d] = %d\n", ii, ue->common_vars.txdata[0][ii]); + //} + //printf(" \n"); + + #if defined(PRACH_WRITE_OUTPUT_DEBUG) + LOG_M("prach_tx0.m", "prachtx0", prach+(Ncp<<1), prach_len-Ncp, 1, 1); + LOG_M("Prach_txsig.m","txs",(int16_t*)(&ue->common_vars.txdata[0][prach_start]), 2*(prach_start+prach_len), 1, 1) + #endif + + return signal_energy((int*)prach, 256); } diff --git a/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c b/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c index ab15935f16..5d99acfc3a 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c @@ -20,10 +20,10 @@ */ /*! \file nr_l1_helper.c -* \brief PHY helper function adapted to NR +* \brief PHY helper functions for PRACH adapted to NR * \author Guido Casati * \date 2019 -* \version 1.0 +* \version 2.0 * \email guido.casati@iis.fraunhofer.de * @ingroup _mac @@ -38,60 +38,62 @@ /* TS 38.321 subclause 7.3 - return DELTA_PREAMBLE values in dB */ int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id, uint16_t prach_format){ - NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); - NR_ServingCellConfigCommon_t *scc = mac->scc; - NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup; + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + NR_ServingCellConfigCommon_t *scc = mac->scc; + NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup; + NR_SubcarrierSpacing_t scs = *nr_rach_ConfigCommon->msg1_SubcarrierSpacing; + int prach_sequence_length = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.present - 1; + uint8_t prachConfigIndex, mu; - AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); + AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n"); - uint8_t prachConfigIndex, mu; + // SCS configuration from msg1_SubcarrierSpacing and table 4.2-1 in TS 38.211 - // SCS configuration from msg1_SubcarrierSpacing and table 4.2-1 in TS 38.211 + switch (scs){ + case NR_SubcarrierSpacing_kHz15: + mu = 0; + break; - NR_SubcarrierSpacing_t scs = *nr_rach_ConfigCommon->msg1_SubcarrierSpacing; + case NR_SubcarrierSpacing_kHz30: + mu = 1; + break; - switch (scs){ - case NR_SubcarrierSpacing_kHz15: - mu = 0; - break; + case NR_SubcarrierSpacing_kHz60: + mu = 2; + break; - case NR_SubcarrierSpacing_kHz30: - mu = 1; - break; + case NR_SubcarrierSpacing_kHz120: + mu = 3; + break; - case NR_SubcarrierSpacing_kHz60: - mu = 2; - break; + case NR_SubcarrierSpacing_kHz240: + mu = 4; + break; - case NR_SubcarrierSpacing_kHz120: - mu = 3; - break; + case NR_SubcarrierSpacing_spare3: + mu = 5; + break; - case NR_SubcarrierSpacing_kHz240: - mu = 4; - break; + case NR_SubcarrierSpacing_spare2: + mu = 6; + break; - case NR_SubcarrierSpacing_spare3: - mu = 5; - break; + case NR_SubcarrierSpacing_spare1: + mu = 7; + break; - case NR_SubcarrierSpacing_spare2: - mu = 6; - break; + default: + AssertFatal(1 == 0,"Unknown msg1_SubcarrierSpacing %lu\n", scs); + } - case NR_SubcarrierSpacing_spare1: - mu = 7; - break; + // Preamble formats given by prach_ConfigurationIndex and tables 6.3.3.2-2 and 6.3.3.2-2 in TS 38.211 - default: - AssertFatal(1 == 0,"Unknown msg1_SubcarrierSpacing %lu\n", scs); - } - - // Preamble formats given by prach_ConfigurationIndex and tables 6.3.3.2-2 and 6.3.3.2-2 in TS 38.211 - - prachConfigIndex = nr_rach_ConfigCommon->rach_ConfigGeneric.prach_ConfigurationIndex; + prachConfigIndex = nr_rach_ConfigCommon->rach_ConfigGeneric.prach_ConfigurationIndex; + if (prach_sequence_length == 0) { switch (prach_format) { + AssertFatal(prach_format < 4, "Illegal PRACH format %d for sequence length 839\n", prach_format); + // long preamble formats case 0: case 3: @@ -102,30 +104,32 @@ int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id, uint16_t prach_forma case 2: return -6; - - // short preamble formats - case 0xa1: - case 0xb1: + } + } else { + switch (prach_format) { // short preamble formats + case 0: + case 3: return 8 + 3*mu; - case 0xa2: - case 0xb2: - case 0xc2: + case 1: + case 4: + case 8: return 5 + 3*mu; - case 0xa3: - case 0xb3: + case 2: + case 5: return 3 + 3*mu; - case 0xb4: + case 6: return 3*mu; - case 0xc0: + case 7: return 5 + 3*mu; default: AssertFatal(1 == 0, "[UE %d] ue_procedures.c: FATAL, Illegal preambleFormat %d, prachConfigIndex %d\n", mod_id, prach_format, prachConfigIndex); } + } } /* TS 38.321 subclause 5.1.3 - RA preamble transmission - ra_PREAMBLE_RECEIVED_TARGET_POWER configuration */ From 6d413e2c574079303d3efefd3ba24f7cd06a6b6e Mon Sep 17 00:00:00 2001 From: cig Date: Thu, 26 Mar 2020 18:14:29 +0100 Subject: [PATCH 121/553] Bugfix returning null pointer to prach resources --- openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c index fd1248ea6d..3fe23d8127 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -109,7 +109,6 @@ void nr_get_prach_resources(module_id_t mod_id, // // - available SSB with SS-RSRP above rsrp-ThresholdSSB: SSB selection // // - availalbe CSI-RS with CSI-RSRP above rsrp-ThresholdCSI-RS: CSI-RS selection // prach_resources->ra_PreambleIndex = rach_ConfigDedicated->ra_PreambleIndex; - // return; // } //////////* Contention-based RA preamble selection *////////// @@ -119,7 +118,7 @@ void nr_get_prach_resources(module_id_t mod_id, // rsrp_ThresholdSSB = *nr_rach_ConfigCommon->rsrp_ThresholdSSB; - AssertFatal(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); + AssertFatal(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); nr_rach_ConfigCommon = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup; rach_ConfigGeneric = &nr_rach_ConfigCommon->rach_ConfigGeneric; @@ -503,8 +502,6 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, for (int j = 0; j < (TBS_bytes - offset); j++) payload[offset + j] = 0; // mac_pdu[offset + j] = 0; } - - return; } } else { // RACH is active @@ -603,13 +600,11 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, mac->RA_tx_subframe = nr_tti_tx; // Fill in preamble and PRACH resources nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 0, prach_resources, NULL); - return; } } } else if (UE_mode == PUSCH) { LOG_D(MAC, "[UE %d] FATAL: Should not have checked for RACH in PUSCH yet ...", mod_id); AssertFatal(1 == 0, ""); } - prach_resources = NULL; return; } From cca28a0abdd61e2b36473af7516c697010281ea4 Mon Sep 17 00:00:00 2001 From: cig Date: Fri, 27 Mar 2020 16:58:27 +0100 Subject: [PATCH 122/553] Moved PRACH PDU struct to NR_UE_PRACH in PHY_VARS_NR_UE: - now the FAPI interface copies the struct directly to NR_UE_PRACH - NR_PRACH_CONFIG_COMMON and NR_PRACH_CONFIG_INFO have been removed from FP --- .../nfapi/public_inc/fapi_nr_ue_interface.h | 15 +++++- openair1/PHY/INIT/nr_init_ue.c | 46 +++++++++---------- openair1/PHY/NR_TRANSPORT/nr_prach_common.c | 4 +- openair1/PHY/NR_UE_TRANSPORT/nr_prach.c | 33 +++---------- openair1/PHY/defs_nr_UE.h | 2 + openair1/PHY/defs_nr_common.h | 27 ----------- openair1/SCHED_NR_UE/fapi_nr_ue_l1.c | 15 +----- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 2 +- 8 files changed, 49 insertions(+), 95 deletions(-) diff --git a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h index 7caeecdc4c..610a798292 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h @@ -156,17 +156,28 @@ typedef struct { fapi_nr_tx_request_body_t *tx_request_body; } fapi_nr_tx_request_t; +/// This struct replaces: +/// PRACH-ConfigInfo from 38.331 RRC spec +/// PRACH-ConfigSIB or PRACH-Config typedef struct { + /// PHY cell ID uint16_t phys_cell_id; + /// Num PRACH occasions uint8_t num_prach_ocas; + /// PRACH format uint8_t prach_format; + /// Num RA uint8_t num_ra; uint8_t prach_start_symbol; + /// 38.211 (NCS 38.211 6.3.3.1). uint16_t num_cs; + /// Parameter: prach-rootSequenceIndex, see TS 38.211 (6.3.3.2). uint16_t root_seq_id; - uint8_t restricted_set; + /// Parameter: High-speed-flag, see TS 38.211 (6.3.3.1). 1 corresponds to Restricted set and 0 to Unrestricted set. + uint8_t restricted_set; + /// see TS 38.211 (6.3.3.2). uint16_t freq_msg1; - //nfapi_nr_ul_beamforming_t beamforming; + // nfapi_nr_ul_beamforming_t beamforming; } fapi_nr_ul_config_prach_pdu; typedef struct { diff --git a/openair1/PHY/INIT/nr_init_ue.c b/openair1/PHY/INIT/nr_init_ue.c index 75bc1b4f91..b88f9aa0f2 100644 --- a/openair1/PHY/INIT/nr_init_ue.c +++ b/openair1/PHY/INIT/nr_init_ue.c @@ -77,19 +77,19 @@ void phy_config_sib2_ue(uint8_t Mod_id,int CC_id, LOG_I(PHY,"[UE%d] Applying radioResourceConfigCommon from eNB%d\n",Mod_id,eNB_id); - fp->prach_config_common.rootSequenceIndex =radioResourceConfigCommon->prach_Config.rootSequenceIndex; + ue->prach_vars[eNB_id]->prach_pdu.root_seq_id =radioResourceConfigCommon->prach_Config.rootSequenceIndex; - fp->prach_config_common.prach_Config_enabled=1; - fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex =radioResourceConfigCommon->prach_Config.prach_ConfigInfo.prach_ConfigIndex; - fp->prach_config_common.prach_ConfigInfo.highSpeedFlag =radioResourceConfigCommon->prach_Config.prach_ConfigInfo.highSpeedFlag; - fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig =radioResourceConfigCommon->prach_Config.prach_ConfigInfo.zeroCorrelationZoneConfig; - fp->prach_config_common.prach_ConfigInfo.prach_FreqOffset =radioResourceConfigCommon->prach_Config.prach_ConfigInfo.prach_FreqOffset; + ue->prach_vars[eNB_id]->prach_Config_enabled=1; + //ue->prach_vars[eNB_id]->prach_pdu.prach_ConfigIndex =radioResourceConfigCommon->prach_Config.prach_ConfigInfo.prach_ConfigIndex; + ue->prach_vars[eNB_id]->prach_pdu.restricted_set =radioResourceConfigCommon->prach_Config.prach_ConfigInfo.highSpeedFlag; + ue->prach_vars[eNB_id]->prach_pdu.num_cs =radioResourceConfigCommon->prach_Config.prach_ConfigInfo.zeroCorrelationZoneConfig; + //ue->prach_vars[eNB_id]->prach_pdu.prach_FreqOffset =radioResourceConfigCommon->prach_Config.prach_ConfigInfo.prach_FreqOffset; - compute_prach_seq(fp->prach_config_common.rootSequenceIndex, - fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex, - fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig, - fp->prach_config_common.prach_ConfigInfo.highSpeedFlag, - fp->frame_type,ue->X_u); + //compute_prach_seq(fp->prach_config_common.rootSequenceIndex, + // fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex, + // fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig, + // fp->prach_config_common.prach_ConfigInfo.highSpeedFlag, + // fp->frame_type,ue->X_u); @@ -226,12 +226,12 @@ void phy_config_sib13_ue(uint8_t Mod_id,int CC_id,uint8_t eNB_id,int mbsfn_Area_ LOG_I(PHY,"[UE%d] Handover triggered: Applying radioResourceConfigCommon from eNB %d\n", Mod_id,eNB_id); - fp->prach_config_common.rootSequenceIndex =radioResourceConfigCommon->prach_Config.rootSequenceIndex; - fp->prach_config_common.prach_Config_enabled=1; - fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex =radioResourceConfigCommon->prach_Config.prach_ConfigInfo->prach_ConfigIndex; - fp->prach_config_common.prach_ConfigInfo.highSpeedFlag =radioResourceConfigCommon->prach_Config.prach_ConfigInfo->highSpeedFlag; - fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig =radioResourceConfigCommon->prach_Config.prach_ConfigInfo->zeroCorrelationZoneConfig; - fp->prach_config_common.prach_ConfigInfo.prach_FreqOffset =radioResourceConfigCommon->prach_Config.prach_ConfigInfo->prach_FreqOffset; + ue->prach_vars[eNB_id]->prach_pdu.root_seq_id =radioResourceConfigCommon->prach_Config.rootSequenceIndex; + ue->prach_vars[eNB_id]->prach_Config_enabled=1; + //ue->prach_vars[eNB_id]->prach_pdu.prach_ConfigIndex =radioResourceConfigCommon->prach_Config.prach_ConfigInfo->prach_ConfigIndex; + ue->prach_vars[eNB_id]->prach_pdu.restricted_set =radioResourceConfigCommon->prach_Config.prach_ConfigInfo->highSpeedFlag; + ue->prach_vars[eNB_id]->prach_pdu.num_cs =radioResourceConfigCommon->prach_Config.prach_ConfigInfo->zeroCorrelationZoneConfig; + //ue->prach_vars[eNB_id]->prach_pdu.prach_FreqOffset =radioResourceConfigCommon->prach_Config.prach_ConfigInfo->prach_FreqOffset; // prach_fmt = get_prach_fmt(radioResourceConfigCommon->prach_Config.prach_ConfigInfo->prach_ConfigIndex,fp->frame_type); // N_ZC = (prach_fmt <4)?839:139; @@ -239,12 +239,12 @@ void phy_config_sib13_ue(uint8_t Mod_id,int CC_id,uint8_t eNB_id,int mbsfn_Area_ // prach_root_sequence_map4[fp->prach_config_common.rootSequenceIndex]; //compute_prach_seq(u,N_ZC, PHY_vars_UE_g[Mod_id]->X_u); - compute_prach_seq(PHY_vars_UE_g[Mod_id][CC_id]->frame_parms.prach_config_common.rootSequenceIndex, - PHY_vars_UE_g[Mod_id][CC_id]->frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex, - PHY_vars_UE_g[Mod_id][CC_id]->frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig, - PHY_vars_UE_g[Mod_id][CC_id]->frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag, - fp->frame_type, - PHY_vars_UE_g[Mod_id][CC_id]->X_u); + //compute_prach_seq(PHY_vars_UE_g[Mod_id][CC_id]->frame_parms.prach_config_common.rootSequenceIndex, + // PHY_vars_UE_g[Mod_id][CC_id]->frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex, + // PHY_vars_UE_g[Mod_id][CC_id]->frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig, + // PHY_vars_UE_g[Mod_id][CC_id]->frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag, + // fp->frame_type, + // PHY_vars_UE_g[Mod_id][CC_id]->X_u); fp->pucch_config_common.deltaPUCCH_Shift = 1+radioResourceConfigCommon->pucch_ConfigCommon->deltaPUCCH_Shift; diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c index e824928dbe..8373e775bd 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c @@ -42,7 +42,7 @@ -void dump_nr_prach_config(NR_DL_FRAME_PARMS *frame_parms,uint8_t subframe) { +/*void dump_nr_prach_config(NR_DL_FRAME_PARMS *frame_parms,uint8_t subframe) { FILE *fd; @@ -76,7 +76,7 @@ void dump_nr_prach_config(NR_DL_FRAME_PARMS *frame_parms,uint8_t subframe) { fprintf(fd,"prach_config: n_ra_prboffset = %d\n",frame_parms->prach_config_common.prach_ConfigInfo.msg1_frequencystart); fclose(fd); -} +}*/ // This function computes the du void nr_fill_du(uint16_t N_ZC,uint16_t *prach_root_sequence_map) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c index 9f98065e90..00cddcd451 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c @@ -72,6 +72,7 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t slot){ NR_DL_FRAME_PARMS *fp=&ue->frame_parms; fapi_nr_config_request_t *nrUE_config = &ue->nrUE_config; NR_PRACH_RESOURCES_t *prach_resources = ue->prach_resources[gNB_id]; + fapi_nr_ul_config_prach_pdu *prach_pdu = &ue->prach_vars[gNB_id]->prach_pdu; uint8_t Mod_id, fd_occasion, preamble_index, restricted_set, not_found; uint16_t rootSequenceIndex, prach_fmt_id, NCS, *prach_root_sequence_map, preamble_offset; @@ -89,11 +90,11 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t slot){ prach_sequence_length = nrUE_config->prach_config.prach_sequence_length; N_ZC = (prach_sequence_length == 0) ? 839:139; mu = nrUE_config->prach_config.prach_sub_c_spacing; - restricted_set = fp->prach_config_common.prach_ConfigInfo.highSpeedFlag; - rootSequenceIndex = fp->prach_config_common.rootSequenceIndex; - n_ra_prb = fp->prach_config_common.prach_ConfigInfo.msg1_frequencystart; - NCS = fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig; - prach_fmt_id = prach_resources->prach_format; + restricted_set = prach_pdu->restricted_set; + rootSequenceIndex = prach_pdu->root_seq_id; + n_ra_prb = prach_pdu->freq_msg1; + NCS = prach_pdu->num_cs; + prach_fmt_id = prach_pdu->prach_format; preamble_index = 0; //prach_resources->ra_PreambleIndex // temporary hardcoded fd_occasion = 0; prach_len = 0; @@ -135,28 +136,6 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t slot){ * NOTE: Restricted set type B is not implemented *************************************************************************/ - // restricted type is hardcoded ('0' for restricted_TypeA; and '1' for restricted_TypeB). FIXME - // uint8_t Ncs_config = fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig; - // if (prach_fmt_id<3){ - // if (restricted_set == 0) { - // NCS = NCS_unrestricted_delta_f_RA_125[Ncs_config]; - // } else { - // if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_125[Ncs_config]; // for TypeA, this is hardcoded. FIXME - // if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_125[Ncs_config]; // for TypeB, this is hardcoded. FIXME - // } - // } - // if (prach_fmt_id==3){ - // if (restricted_set == 0) { - // NCS = NCS_unrestricted_delta_f_RA_5[Ncs_config]; - // } else { - // if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_5[Ncs_config]; // for TypeA, this is hardcoded. FIXME - // if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_5[Ncs_config]; // for TypeB, this is hardcoded. FIXME - // } - // } - // if (prach_fmt_id>3){ - // NCS = NCS_unrestricted_delta_f_RA_15[Ncs_config]; - // } - prach_root_sequence_map = (prach_sequence_length == 0) ? prach_root_sequence_map_0_3 : prach_root_sequence_map_abc; // This is the relative offset (for unrestricted case) in the root sequence table (5.7.2-4 from 36.211) for the given preamble index diff --git a/openair1/PHY/defs_nr_UE.h b/openair1/PHY/defs_nr_UE.h index b532ddb071..ac71f708ec 100644 --- a/openair1/PHY/defs_nr_UE.h +++ b/openair1/PHY/defs_nr_UE.h @@ -782,6 +782,8 @@ typedef struct { int16_t amp; int16_t *prachF; int16_t *prach; + fapi_nr_ul_config_prach_pdu prach_pdu; + uint8_t prach_Config_enabled; } NR_UE_PRACH; // structure used for multiple SSB detection diff --git a/openair1/PHY/defs_nr_common.h b/openair1/PHY/defs_nr_common.h index d8f5563af0..9caf3bc682 100644 --- a/openair1/PHY/defs_nr_common.h +++ b/openair1/PHY/defs_nr_common.h @@ -198,31 +198,6 @@ typedef struct { nr_reg_t reg_list[NR_NB_REG_PER_CCE]; } nr_cce_t; - -/// PRACH-ConfigInfo from 38.331 RRC spec -typedef struct { - /// Parameter: prach-ConfigurationIndex, see TS 38.211 (6.3.3.2). - uint8_t prach_ConfigIndex; - /// Parameter: High-speed-flag, see TS 38.211 (6.3.3.1). 1 corresponds to Restricted set and 0 to Unrestricted set. - uint8_t highSpeedFlag; - /// Restricted Set Config (type A=0 , type B=1) TS 38.211 (6.3.3.1) - uint8_t restrictedSetConfig; - /// 38.211 (NCS 38.211 6.3.3.1). - uint8_t zeroCorrelationZoneConfig; - /// see TS 38.211 (6.3.3.2). - uint8_t msg1_frequencystart; -} NR_PRACH_CONFIG_INFO; - -/// PRACH-ConfigSIB or PRACH-Config -typedef struct { - /// Parameter: prach-rootSequenceIndex, see TS 38.211 (6.3.3.2). - uint16_t rootSequenceIndex; - /// prach_Config_enabled=1 means enabled.} - uint8_t prach_Config_enabled; - /// PRACH Configuration Information - NR_PRACH_CONFIG_INFO prach_ConfigInfo; -} NR_PRACH_CONFIG_COMMON; - typedef struct { /// PRACH format retrieved from prach_ConfigIndex uint16_t prach_format; @@ -340,8 +315,6 @@ struct NR_DL_FRAME_PARMS { uint8_t nb_antennas_rx; /// Number of common transmit antenna ports in eNodeB (1 or 2) uint8_t nb_antenna_ports_gNB; - /// PRACH_CONFIG - NR_PRACH_CONFIG_COMMON prach_config_common; /// Cyclic Prefix for DL (0=Normal CP, 1=Extended CP) lte_prefix_type_t Ncp; /// shift of pilot position in one RB diff --git a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c index 06e6976b14..7edbfcbd6c 100644 --- a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c +++ b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c @@ -114,9 +114,7 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ uint8_t pdu_type = ul_config->ul_config_list[i].pdu_type, pucch_resource_id, current_harq_pid, format, gNB_id = 0; /* PRACH */ - NR_DL_FRAME_PARMS *fp; NR_PRACH_RESOURCES_t *prach_resources; - NR_PRACH_CONFIG_COMMON *prach_config_common; fapi_nr_ul_config_prach_pdu *prach_config_pdu; /* PUSCH */ fapi_nr_ul_config_pusch_pdu_rel15_t *pusch_config_pdu; @@ -189,19 +187,10 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ case (FAPI_NR_UL_CONFIG_TYPE_PRACH): // prach config pdu - fp = &PHY_vars_UE_g[module_id][cc_id]->frame_parms; prach_resources = PHY_vars_UE_g[module_id][cc_id]->prach_resources[gNB_id]; - prach_config_common = &fp->prach_config_common; prach_config_pdu = &ul_config->ul_config_list[i].prach_config_pdu; - - prach_config_common->prach_Config_enabled = 1; - prach_config_common->rootSequenceIndex = prach_config_pdu->root_seq_id; - prach_config_common->prach_ConfigInfo.zeroCorrelationZoneConfig = prach_config_pdu->num_cs; - prach_config_common->prach_ConfigInfo.highSpeedFlag = prach_config_pdu->restricted_set; - prach_config_common->prach_ConfigInfo.msg1_frequencystart = prach_config_pdu->freq_msg1; - - prach_resources->prach_format = prach_config_pdu->prach_format; - + memcpy((void*)&(PHY_vars_UE_g[module_id][cc_id]->prach_vars[gNB_id]->prach_pdu), (void*)prach_config_pdu, sizeof(fapi_nr_ul_config_prach_pdu)); + PHY_vars_UE_g[module_id][cc_id]->prach_vars[gNB_id]->prach_Config_enabled = 1; break; default: diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 07bb58b2d0..8668b38785 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -2266,7 +2266,7 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, /* RACH */ - if ((ue->UE_mode[gNB_id] == PRACH) && (ue->frame_parms.prach_config_common.prach_Config_enabled == 1)) { + if ((ue->UE_mode[gNB_id] == PRACH) && (ue->prach_vars[gNB_id]->prach_Config_enabled == 1)) { nr_ue_prach_procedures(ue, proc, gNB_id, mode); } else { From 2b3446ed1577c5c95c99c94e6701190e49f6a394 Mon Sep 17 00:00:00 2001 From: cig Date: Fri, 27 Mar 2020 17:06:37 +0100 Subject: [PATCH 123/553] Hardcoded PRACH tx_amp to AMP --- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 8668b38785..feda6c6d9b 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -4544,17 +4544,18 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t prach_resources->ra_RNTI); //ue->tx_total_RE[nr_tti_tx] = 96; // todo + ue->prach_vars[gNB_id]->amp = AMP; - #if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706) + /* #if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706) tx_amp = get_tx_amp_prach(ue->tx_power_dBm[nr_tti_tx], ue->tx_power_max_dBm, ue->frame_parms.N_RB_UL); if (tx_amp != -1) ue->prach_vars[gNB_id]->amp = tx_amp; #else ue->prach_vars[gNB_id]->amp = AMP; - #endif + #endif */ if ((runmode == calib_prach_tx) && (((proc->frame_tx&0xfffe)%100)==0)) - LOG_D(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_tx %d : PRACH TX power %d dBm, amp %d (%d)\n", ue->Mod_id, + LOG_D(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_tx %d : PRACH TX power %d dBm, amp %d\n", ue->Mod_id, proc->frame_rx, proc->nr_tti_tx, ue->tx_power_dBm[nr_tti_tx], From 7f00dbc53c4717f7180f3f9dae20cc81a9f4bfbf Mon Sep 17 00:00:00 2001 From: cig Date: Mon, 30 Mar 2020 12:03:31 +0200 Subject: [PATCH 124/553] Const prachfmt in nr_mac_common --- openair1/PHY/NR_TRANSPORT/nr_prach.c | 2 +- openair1/PHY/NR_UE_TRANSPORT/nr_prach.c | 2 +- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 2 ++ 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index 80760ac032..2f0ea46ecd 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -38,6 +38,7 @@ extern uint16_t prach_root_sequence_map_0_3[838]; extern uint16_t prach_root_sequence_map_abc[138]; extern uint16_t nr_du[838]; extern int16_t nr_ru[2*839]; +extern const char *prachfmt[9]; void init_prach_list(PHY_VARS_gNB *gNB) { @@ -137,7 +138,6 @@ void free_nr_ru_prach_entry(RU_t *ru, } -const char *prachfmt[]={"A1","A2","A3","B1","B2","B3","B4","C0","C2"}; void rx_nr_prach_ru(RU_t *ru, int prachFormat, diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c index 00cddcd451..6989c0af32 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c @@ -58,7 +58,7 @@ extern int64_t table_6_3_3_2_3_prachConfig_Index [256][9]; extern int64_t table_6_3_3_2_4_prachConfig_Index [256][10]; extern uint16_t nr_du[838]; extern int16_t nr_ru[2*839]; -const char *prachfmt[]={"A1","A2","A3","B1","B2","B3","B4","C0","C2"}; +extern const char *prachfmt[9]; // Note: // - prach_fmt_id is an ID used to map to the corresponding PRACH format value in prachfmt diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index 6f691852da..5a93d2abbf 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -45,6 +45,8 @@ uint16_t NCS_restricted_TypeB_delta_f_RA_5[14] = {36,57,60,63,65,68,71,77,81,8 // Table 6.3.3.1-7 (38.211) NCS for preamble formats with delta_f_RA = 15 * 2mu KHz where mu = {0,1,2,3} uint16_t NCS_unrestricted_delta_f_RA_15[16] = {0,2,4,6,8,10,12,13,15,17,19,23,27,34,46,69}; +const char *prachfmt[]={"A1","A2","A3","B1","B2","B3","B4","C0","C2"}; + uint16_t get_NCS(uint8_t index, uint16_t format0, uint8_t restricted_set_config) { if (format0 < 3) { From 2378b73b1ec07ce39f3c6d364d44aae8afd4cc4b Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Mon, 30 Mar 2020 14:38:42 +0200 Subject: [PATCH 125/553] ENDC path switch procedures: E-RAB Modification Confirm message successfully received at the eNB from the MME now --- openair3/S1AP/s1ap_eNB_decoder.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/openair3/S1AP/s1ap_eNB_decoder.c b/openair3/S1AP/s1ap_eNB_decoder.c index 3eb182b159..4635946a05 100644 --- a/openair3/S1AP/s1ap_eNB_decoder.c +++ b/openair3/S1AP/s1ap_eNB_decoder.c @@ -112,6 +112,12 @@ static int s1ap_eNB_decode_successful_outcome(S1AP_S1AP_PDU_t *pdu) { free(res.buffer); break; + case S1AP_ProcedureCode_id_E_RABModificationIndication: + res = asn_encode_to_new_buffer(NULL, ATS_CANONICAL_XER, &asn_DEF_S1AP_S1AP_PDU, pdu); + free(res.buffer); + break; + + default: S1AP_ERROR("Unknown procedure ID (%d) for successfull outcome message\n", (int)pdu->choice.successfulOutcome.procedureCode); From f404f29e2ff715dbfcf9f7a2a364c8ae7cb4aa97 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Tue, 31 Mar 2020 15:27:41 +0200 Subject: [PATCH 126/553] added some fields in 1_1 DCI bit encoder --- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 4 +- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 110 +++++++++++++++++- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 4 +- 3 files changed, 114 insertions(+), 4 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 1e0fd8d9a2..b89f45be0e 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -387,7 +387,7 @@ int configure_fapi_dl_pdu(int Mod_idP, rnti_types[0] = NR_RNTI_C; pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); - fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types); + fill_dci_pdu_rel15(pdsch_pdu_rel_15,NULL,pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types); LOG_D(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \ coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n", @@ -833,7 +833,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); - fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types); + fill_dci_pdu_rel15(NULL,pusch_pdu,pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types); } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 9376855882..51988c9cb3 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -546,7 +546,9 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, -void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, +void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15, + nfapi_nr_pusch_pdu_t *pusch_pdu, + nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types @@ -554,6 +556,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, uint16_t N_RB = pdcch_pdu_rel15->BWPSize; uint8_t fsize=0, pos=0; + uint8_t nbits=0; for (int d=0;dnumDlDci;d++) { @@ -561,6 +564,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, AssertFatal(pdcch_pdu_rel15->PayloadSizeBits[d]<=64, "DCI sizes above 64 bits not yet supported"); int dci_size = pdcch_pdu_rel15->PayloadSizeBits[d]; + pos = 0; /// Payload generation switch(dci_formats[d]) { @@ -864,6 +868,110 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, } break; + + case NR_DL_DCI_FORMAT_1_1: + // Indicating a DL DCI format 1bit + pos=1; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&1)<<(dci_size-pos); + + // Carrier indicator + if (!dci_pdu_rel15->carrier_indicator) {// TODO: check if UE configured with CrossCarrierSchedulingConfig + pos+=3; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->carrier_indicator&0x7)<<(dci_size-pos); + } + + // BWP indicator + uint8_t n_bwp_rrc = 0; // TODO: get this parameter from RRC + + nbits = (uint8_t)((n_bwp_rrc < 4) ? ceil(log2(n_bwp_rrc+1)) : ceil(log2(n_bwp_rrc))); + pos+=nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->bwp_indicator&((1<resourceAlloc == 0) + nbits = numRBG; + else if (pdsch_pdu_rel15->resourceAlloc == 1) + nbits = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + else + nbits = ((int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )>numRBG) ? (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )+1 : numRBG+1; + + pos+=nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_domain_assignment&((1<time_domain_assignment&((1<resourceAlloc == 1) { + pos++; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos); + } + + // PRB bundling size indicator + if (0) {// TODO: check if prb-BundlingType is dynamic + pos++; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->prb_bundling_size_indicator&1)<<(dci_size-pos); + } + + // Rate matching indicator + // TODO: check for rateMatchPatternGroup + + // ZP CSI-RS trigger + uint8_t nZP = 0; // TODO: replace with number of aperiodic ZP CSI-RS resource sets + nbits = (int)ceil(log2(nZP+1)); + pos+=nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->zp_csi_rs_trigger&((1<mcs&0x1f)<<(dci_size-pos); + + // New data indicator 1bit + pos++; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&1)<<(dci_size-pos); + + // Redundancy version 2bit + pos+=2; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->rv&0x3)<<(dci_size-pos); + + // HARQ process number 4bit + pos+=4; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid&0xf)<<(dci_size-pos); + + // Downlink assignment index + if (0) { // TODO: check if UE has more than 1 serving cell AND pdsch-HARQ-ACK-Codebook is dynamic + pos+=4; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->dai&0xf)<<(dci_size-pos); + } else if (0) { // TODO: check if UE had only 1 serving cell AND " + pos+=2; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->dai&0x3)<<(dci_size-pos); + } + + // TPC command for scheduled PUCCH 2bit + pos+=2; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->tpc&0x3)<<(dci_size-pos); + + // PUCCH resource indicator 3bit + pos+=3; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->pucch_resource_indicator&0x7)<<(dci_size-pos); + + // PDSCH-to-HARQ_feedback timing indicator + uint8_t I = 0; // TODO: replace with number of entries in dl-DataToUL-ACK + nbits = (int)ceil(log2(I)); + pos+=nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator&((1< Date: Wed, 1 Apr 2020 01:26:02 +0200 Subject: [PATCH 127/553] 1_1 DCI encoding - added checks from RRC IEs --- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 4 +- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 72 +++++++++++++------ openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 5 +- 3 files changed, 57 insertions(+), 24 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index b89f45be0e..0c58ba325a 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -387,7 +387,7 @@ int configure_fapi_dl_pdu(int Mod_idP, rnti_types[0] = NR_RNTI_C; pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); - fill_dci_pdu_rel15(pdsch_pdu_rel_15,NULL,pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types); + fill_dci_pdu_rel15(secondaryCellGroup,pdsch_pdu_rel15,pdcch_pdu_rel15,NULL,&dci_pdu_rel15[0],dci_formats,rnti_types); LOG_D(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \ coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n", @@ -833,7 +833,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); - fill_dci_pdu_rel15(NULL,pusch_pdu,pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types); + fill_dci_pdu_rel15(secondaryCellGroup,NULL,pdcch_pdu_rel15,pusch_pdu,&dci_pdu_rel15[0],dci_formats,rnti_types); } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 51988c9cb3..4e8ef2dd44 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -544,16 +544,35 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, } } +// TODO: Move the following 2 functions somewhere that UE can also use +// Table 5.1.2.2.1-1 38.214 +uint8_t getRBGSize(uint16_t bwp_size, long rbg_size_config) { + + AssertFatal(bwp_size<276,"BWP Size > 275\n"); + + if (bwp_size < 37) return (rbg_size_config ? 4 : 2); + if (bwp_size < 73) return (rbg_size_config ? 8 : 4); + if (bwp_size < 145) return (rbg_size_config ? 16 : 8); + if (bwp_size < 276) return 16; +} +uint8_t getNRBG(uint16_t bwp_size, uint16_t bwp_start, long rbg_size_config) { -void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15, - nfapi_nr_pusch_pdu_t *pusch_pdu, + uint8_t rbg_size = getRBGSize(bwp_size,rbg_size_config); + + return (uint8_t)ceil((bwp_size+(bwp_start % rbg_size))/rbg_size); +} + +void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15, nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, + nfapi_nr_pusch_pdu_t *pusch_pdu, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types ) { + NR_PDSCH_Config_t *pdsch_config = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup; uint16_t N_RB = pdcch_pdu_rel15->BWPSize; uint8_t fsize=0, pos=0; uint8_t nbits=0; @@ -875,24 +894,25 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15, *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&1)<<(dci_size-pos); // Carrier indicator - if (!dci_pdu_rel15->carrier_indicator) {// TODO: check if UE configured with CrossCarrierSchedulingConfig + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig != NULL) { pos+=3; *dci_pdu |= ((uint64_t)dci_pdu_rel15->carrier_indicator&0x7)<<(dci_size-pos); } // BWP indicator - uint8_t n_bwp_rrc = 0; // TODO: get this parameter from RRC + uint8_t n_dl_bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count; - nbits = (uint8_t)((n_bwp_rrc < 4) ? ceil(log2(n_bwp_rrc+1)) : ceil(log2(n_bwp_rrc))); + nbits = (uint8_t)((n_dl_bwp < 4) ? ceil(log2(n_dl_bwp+1)) : ceil(log2(n_dl_bwp))); pos+=nbits; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->bwp_indicator&((1<bwp_indicator&((1<spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rbg_Size; + uint16_t numRBG = getNRBG(pdsch_pdu_rel15->BWPSize,pdsch_pdu_rel15->BWPStart,rbg_size_config); - if (pdsch_pdu_rel15->resourceAlloc == 0) + if (pdsch_config->resourceAllocation == 0) nbits = numRBG; - else if (pdsch_pdu_rel15->resourceAlloc == 1) + else if (pdsch_config->resourceAllocation == 1) nbits = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); else nbits = ((int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )>numRBG) ? (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )+1 : numRBG+1; @@ -901,33 +921,43 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15, *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_domain_assignment&((1<spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[0]->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList; + int num_entries; + if (pdsch_timeDomList != NULL) + num_entries = pdsch_timeDomList->list.count; else - num_entries = 16; + num_entries = 16; // num of entries in default table nbits = (int)ceil(log2(num_entries)); pos+=nbits; *dci_pdu |= ((uint64_t)dci_pdu_rel15->time_domain_assignment&((1<resourceAlloc == 1) { + if (pdsch_config->resourceAllocation == 1) { pos++; *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos); } // PRB bundling size indicator - if (0) {// TODO: check if prb-BundlingType is dynamic + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.present == 2) { pos++; *dci_pdu |= ((uint64_t)dci_pdu_rel15->prb_bundling_size_indicator&1)<<(dci_size-pos); } // Rate matching indicator - // TODO: check for rateMatchPatternGroup + NR_RateMatchPatternGroup_t *group1 = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup1; + NR_RateMatchPatternGroup_t *group2 = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup2; + nbits = 0; + if ((group1 != NULL) && (group2 != NULL)) + nbits = 2; + if ((group1 != NULL) != (group2 != NULL)) + nbits = 1; + pos+=nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->rate_matching_indicator&((1<spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList->list.count; nbits = (int)ceil(log2(nZP+1)); pos+=nbits; *dci_pdu |= ((uint64_t)dci_pdu_rel15->zp_csi_rs_trigger&((1<harq_pid&0xf)<<(dci_size-pos); // Downlink assignment index - if (0) { // TODO: check if UE has more than 1 serving cell AND pdsch-HARQ-ACK-Codebook is dynamic + if (secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook == 1) { // at this point the UE has multiple serving cells pos+=4; *dci_pdu |= ((uint64_t)dci_pdu_rel15->dai&0xf)<<(dci_size-pos); - } else if (0) { // TODO: check if UE had only 1 serving cell AND " + } +/* else if (0) { pos+=2; *dci_pdu |= ((uint64_t)dci_pdu_rel15->dai&0x3)<<(dci_size-pos); } +*/ // TPC command for scheduled PUCCH 2bit pos+=2; @@ -966,7 +998,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15, *dci_pdu |= ((uint64_t)dci_pdu_rel15->pucch_resource_indicator&0x7)<<(dci_size-pos); // PDSCH-to-HARQ_feedback timing indicator - uint8_t I = 0; // TODO: replace with number of entries in dl-DataToUL-ACK + uint8_t I = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[0]->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK->list.count; nbits = (int)ceil(log2(I)); pos+=nbits; *dci_pdu |= ((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator&((1< Date: Wed, 1 Apr 2020 21:30:34 +0200 Subject: [PATCH 128/553] added remaining fields in 1_1 DCI pdu fill --- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 52 ++++++++++++++++++- 1 file changed, 50 insertions(+), 2 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 4e8ef2dd44..31266208fd 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -544,7 +544,7 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, } } -// TODO: Move the following 2 functions somewhere that UE can also use +// TODO: Move the following 3 functions somewhere that UE can also use // Table 5.1.2.2.1-1 38.214 uint8_t getRBGSize(uint16_t bwp_size, long rbg_size_config) { @@ -563,6 +563,16 @@ uint8_t getNRBG(uint16_t bwp_size, uint16_t bwp_start, long rbg_size_config) { return (uint8_t)ceil((bwp_size+(bwp_start % rbg_size))/rbg_size); } +uint8_t getAntPortBitWidth(NR_SetupRelease_DMRS_DownlinkConfig_t *typeA, NR_SetupRelease_DMRS_DownlinkConfig_t *typeB) { + + uint8_t nbitsA, nbitsB, nbits = 0; + if (typeA != NULL) nbitsA = (typeA->choise.setup->maxLength[0]==0) ? 4 : 5; + if (typeB != NULL) nbitsB = (typeB->choise.setup->maxLength[0]==0) ? 5 : 6; + if ((typeA != NULL) && (typeB != NULL)) nbits = (nbitsA > nbitsB) ? nbitsA : nbitsB; + + return nbits; +} + void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15, nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, @@ -1003,7 +1013,45 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, pos+=nbits; *dci_pdu |= ((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator&((1<spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA; + NR_SetupRelease_DMRS_DownlinkConfig_t *typeB = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeB; + nbits = getAntPortBitWidth(typeA,typeB); + pos+=nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->antenna_ports&((1<spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[0]->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[0]->tci_PresentInDCI; + if (isTciEnable != NULL) { + pos+=3; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->transmission_configuration_indication&0x7)<<(dci_size-pos); + } + + // SRS request + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig==NULL) + nbits = 2; + else + nbits = 3; + pos+=nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->srs_request&((1<spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_ServingCellConfig->choise.setup->codeBlockGroupTransmission->choise.setup->maxCodeBlockGroupsPerTransportBlock + 1) * 2; + long *maxCWperDCI_rrc = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI; + uint8_t maxCWperDCI = (maxCWperDCI_rrc == NULL) ? 1 : *maxCWperDCI_rrc; + nbits = maxCBGperTB * maxCWperDCI; + pos+=nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->cbgti&((1<spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_ServingCellConfig->choise.setup->codeBlockGroupTransmission->choise.setup->codeBlockGroupFlushIndicator) { + pos+=1; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->cbgfi&0x1)<<(dci_size-pos); + } + + // DMRS sequence init + pos+=1; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->dmrs_sequence_initialization&0x1)<<(dci_size-pos); } } } From bf819df6e3e60bb739eb176d002aa570c2bc9d20 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Thu, 2 Apr 2020 02:54:29 +0200 Subject: [PATCH 129/553] changed dci_pdu_rel15 struct to hold bitwidth for each dci field --- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 149 ++++++- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 84 ++-- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 369 +++++++----------- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 13 +- openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 70 +++- 5 files changed, 398 insertions(+), 287 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index ae23164194..9ab1353b71 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -517,11 +517,44 @@ int get_num_dmrs(uint16_t dmrs_mask ) { return(num_dmrs); } -uint16_t nr_dci_size(nr_dci_format_t format, +// Table 5.1.2.2.1-1 38.214 +uint8_t getRBGSize(uint16_t bwp_size, long rbg_size_config) { + + AssertFatal(bwp_size<276,"BWP Size > 275\n"); + + if (bwp_size < 37) return (rbg_size_config ? 4 : 2); + if (bwp_size < 73) return (rbg_size_config ? 8 : 4); + if (bwp_size < 145) return (rbg_size_config ? 16 : 8); + if (bwp_size < 276) return 16; +} + +uint8_t getNRBG(uint16_t bwp_size, uint16_t bwp_start, long rbg_size_config) { + + uint8_t rbg_size = getRBGSize(bwp_size,rbg_size_config); + + return (uint8_t)ceil((bwp_size+(bwp_start % rbg_size))/rbg_size); +} + +uint8_t getAntPortBitWidth(NR_SetupRelease_DMRS_DownlinkConfig_t *typeA, NR_SetupRelease_DMRS_DownlinkConfig_t *typeB) { + + uint8_t nbitsA, nbitsB, nbits = 0; + if (typeA != NULL) nbitsA = (typeA->choice.setup->maxLength[0]==0) ? 4 : 5; + if (typeB != NULL) nbitsB = (typeB->choice.setup->maxLength[0]==0) ? 5 : 6; + if ((typeA != NULL) && (typeB != NULL)) nbits = (nbitsA > nbitsB) ? nbitsA : nbitsB; + + return nbits; +} + +uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, + dci_pdu_rel15_t *dci_pdu, + nr_dci_format_t format, nr_rnti_type_t rnti_type, uint16_t N_RB) { + NR_PDSCH_Config_t *pdsch_config = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup; uint16_t size = 0; + int bwp_id = 1; + NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; switch(format) { /*Only sizes for 0_0 and 1_0 are correct at the moment*/ @@ -529,7 +562,7 @@ uint16_t nr_dci_size(nr_dci_format_t format, /// fixed: Format identifier 1, Hop flag 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2 Time Domain assgnmt 4 --20 size += 20; size += (uint8_t)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); // Freq domain assignment -- hopping scenario to be updated - size += nr_dci_size(NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB) - size; // Padding to match 1_0 size + size += nr_dci_size(secondaryCellGroup,dci_pdu,NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB) - size; // Padding to match 1_0 size // UL/SUL indicator assumed to be 0 break; @@ -562,29 +595,123 @@ uint16_t nr_dci_size(nr_dci_format_t format, break; case NR_DL_DCI_FORMAT_1_1: + // Format identifier + dci_pdu->format_indicator.nbits=1; + size = dci_pdu->format_indicator.nbits; // Carrier indicator - size += 1; // Format identifier + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig != NULL) { + dci_pdu->carrier_indicator.nbits=3; + size += dci_pdu->carrier_indicator.nbits; + } // BWP Indicator + uint8_t n_dl_bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count; + dci_pdu->bwp_indicator.nbits = (uint8_t)((n_dl_bwp < 4) ? ceil(log2(n_dl_bwp+1)) : ceil(log2(n_dl_bwp))); + size += dci_pdu->bwp_indicator.nbits; // Freq domain assignment + long rbg_size_config = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rbg_Size; + uint16_t numRBG = getNRBG(NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275), + NRRIV2PRBOFFSET(bwp->bwp_Common->genericParameters.locationAndBandwidth,275), + rbg_size_config); + if (pdsch_config->resourceAllocation == 0) + dci_pdu->frequency_domain_assignment.nbits = numRBG; + else if (pdsch_config->resourceAllocation == 1) + dci_pdu->frequency_domain_assignment.nbits = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + else + dci_pdu->frequency_domain_assignment.nbits = ((int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )>numRBG) ? (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )+1 : numRBG+1; + size += dci_pdu->frequency_domain_assignment.nbits; // Time domain assignment + NR_PDSCH_TimeDomainResourceAllocationList_t *pdsch_timeDomList = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[0]->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList; + int num_entries; + if (pdsch_timeDomList != NULL) + num_entries = pdsch_timeDomList->list.count; + else + num_entries = 16; // num of entries in default table + dci_pdu->time_domain_assignment.nbits = (int)ceil(log2(num_entries)); + size += dci_pdu->time_domain_assignment.nbits; // VRB to PRB mapping + if (pdsch_config->resourceAllocation == 1) { + dci_pdu->vrb_to_prb_mapping.nbits = 1; + size += dci_pdu->vrb_to_prb_mapping.nbits; + } // PRB bundling size indicator + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.present == 2) { + dci_pdu->prb_bundling_size_indicator.nbits = 1; + size += dci_pdu->prb_bundling_size_indicator.nbits; + } // Rate matching indicator + NR_RateMatchPatternGroup_t *group1 = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup1; + NR_RateMatchPatternGroup_t *group2 = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup2; + if ((group1 != NULL) && (group2 != NULL)) + dci_pdu->rate_matching_indicator.nbits = 2; + if ((group1 != NULL) != (group2 != NULL)) + dci_pdu->rate_matching_indicator.nbits = 1; + size += dci_pdu->rate_matching_indicator.nbits; // ZP CSI-RS trigger - /// TB1- MCS 5, NDI 1, RV 2 - size += 8; + uint8_t nZP = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList->list.count; + dci_pdu->zp_csi_rs_trigger.nbits = (int)ceil(log2(nZP+1)); + size += dci_pdu->zp_csi_rs_trigger.nbits; + // TB1- MCS 5, NDI 1, RV 2 + dci_pdu->mcs[0].nbits = 5; + dci_pdu->ndi[0].nbits = 1; + dci_pdu->rv[0].nbits = 2; + size += (dci_pdu->mcs[0].nbits + dci_pdu->ndi[0].nbits + dci_pdu->rv[0].nbits); // TB2 - size += 4 ; // HARQ PID + long *maxCWperDCI = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI; + if ((maxCWperDCI != NULL) && (maxCWperDCI == 2)) { + dci_pdu->mcs[1].nbits = 5; + dci_pdu->ndi[1].nbits = 1; + dci_pdu->rv[1].nbits = 2; + size += (dci_pdu->mcs[1].nbits + dci_pdu->ndi[1].nbits + dci_pdu->rv[1].nbits); + } + // HARQ PID + dci_pdu->harq_pid.nbits = 4; + size += dci_pdu->harq_pid.nbits; // DAI - size += 2; // TPC PUCCH - size += 3; // PUCCH resource indicator - size += 3; // PDSCH to HARQ timing indicator + if (secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook == 1) { // at this point the UE has multiple serving cells + dci_pdu->dai.nbits = 4; + size += dci_pdu->dai.nbits; + } + // TPC PUCCH + dci_pdu->tpc.nbits = 2; + size += dci_pdu->tpc.nbits; + // PUCCH resource indicator + dci_pdu->pucch_resource_indicator.nbits = 3; + size += dci_pdu->pucch_resource_indicator.nbits; + // PDSCH to HARQ timing indicator + uint8_t I = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[0]->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK->list.count; + dci_pdu->pdsch_to_harq_feedback_timing_indicator.nbits = (int)ceil(log2(I)); + size += dci_pdu->pdsch_to_harq_feedback_timing_indicator.nbits; // Antenna ports + NR_SetupRelease_DMRS_DownlinkConfig_t *typeA = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA; + NR_SetupRelease_DMRS_DownlinkConfig_t *typeB = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeB; + dci_pdu->antenna_ports.nbits = getAntPortBitWidth(typeA,typeB); + size += dci_pdu->antenna_ports.nbits; // Tx Config Indication - size += 2; // SRS request + long *isTciEnable = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[0]->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[0]->tci_PresentInDCI; + if (isTciEnable != NULL) { + dci_pdu->transmission_configuration_indication.nbits = 3; + size += dci_pdu->transmission_configuration_indication.nbits; + } + // SRS request + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig==NULL) + dci_pdu->srs_request.nbits = 2; + else + dci_pdu->srs_request.nbits = 3; + size += dci_pdu->srs_request.nbits; // CBGTI + uint8_t maxCBGperTB = (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission->choice.setup->maxCodeBlockGroupsPerTransportBlock + 1) * 2; + long *maxCWperDCI_rrc = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI; + uint8_t maxCW = (maxCWperDCI_rrc == NULL) ? 1 : *maxCWperDCI_rrc; + dci_pdu->cbgti.nbits = maxCBGperTB * maxCW; + size += dci_pdu->cbgti.nbits; // CBGFI - size += 1; // DMRS sequence init + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission->choice.setup->codeBlockGroupFlushIndicator) { + dci_pdu->cbgfi.nbits = 1; + size += dci_pdu->cbgfi.nbits; + } + // DMRS sequence init + dci_pdu->dmrs_sequence_initialization.nbits = 1; + size += dci_pdu->dmrs_sequence_initialization.nbits; break; case NR_DL_DCI_FORMAT_2_0: diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 0c58ba325a..2413238a53 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -336,37 +336,37 @@ int configure_fapi_dl_pdu(int Mod_idP, scc->dmrs_TypeA_Position, pdsch_pdu_rel15->NrOfSymbols); - dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET]; + dci_pdu_rel15_t *dci_pdu_rel15 = calloc(MAX_DCI_CORESET,sizeof(dci_pdu_rel15)); - dci_pdu_rel15[0].frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize, + dci_pdu_rel15[0].frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize, pdsch_pdu_rel15->rbStart, NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275)); - dci_pdu_rel15[0].time_domain_assignment = time_domain_assignment; // row index used here instead of SLIV; - dci_pdu_rel15[0].vrb_to_prb_mapping = 1; - dci_pdu_rel15[0].mcs = pdsch_pdu_rel15->mcsIndex[0]; - dci_pdu_rel15[0].tb_scaling = 1; + dci_pdu_rel15[0].time_domain_assignment.val = time_domain_assignment; // row index used here instead of SLIV; + dci_pdu_rel15[0].vrb_to_prb_mapping.val = 1; + dci_pdu_rel15[0].mcs[0].val = pdsch_pdu_rel15->mcsIndex[0]; + dci_pdu_rel15[0].tb_scaling.val = 1; - dci_pdu_rel15[0].ra_preamble_index = 25; - dci_pdu_rel15[0].format_indicator = 1; - dci_pdu_rel15[0].ndi = 1; - dci_pdu_rel15[0].rv = 0; - dci_pdu_rel15[0].harq_pid = 0; - dci_pdu_rel15[0].dai = 2; - dci_pdu_rel15[0].tpc = 2; - dci_pdu_rel15[0].pucch_resource_indicator = 7; - dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator = 7; + dci_pdu_rel15[0].ra_preamble_index.val = 25; + dci_pdu_rel15[0].format_indicator.val = 1; + dci_pdu_rel15[0].ndi[0].val = 1; + dci_pdu_rel15[0].rv[0].val = 0; + dci_pdu_rel15[0].harq_pid.val = 0; + dci_pdu_rel15[0].dai.val = 2; + dci_pdu_rel15[0].tpc.val = 2; + dci_pdu_rel15[0].pucch_resource_indicator.val = 7; + dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator.val = 7; LOG_D(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n", - dci_pdu_rel15[0].frequency_domain_assignment, + dci_pdu_rel15[0].frequency_domain_assignment.val, pdsch_pdu_rel15->rbStart, pdsch_pdu_rel15->rbSize, NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275), - dci_pdu_rel15[0].time_domain_assignment, - dci_pdu_rel15[0].vrb_to_prb_mapping, - dci_pdu_rel15[0].mcs, - dci_pdu_rel15[0].tb_scaling, - dci_pdu_rel15[0].ndi, - dci_pdu_rel15[0].rv); + dci_pdu_rel15[0].time_domain_assignment.val, + dci_pdu_rel15[0].vrb_to_prb_mapping.val, + dci_pdu_rel15[0].mcs[0].val, + dci_pdu_rel15[0].tb_scaling.val, + dci_pdu_rel15[0].ndi[0].val, + dci_pdu_rel15[0].rv[0].val); nr_configure_pdcch(pdcch_pdu_rel15, 1, // ue-specific @@ -386,8 +386,8 @@ int configure_fapi_dl_pdu(int Mod_idP, dci_formats[0] = NR_DL_DCI_FORMAT_1_0; rnti_types[0] = NR_RNTI_C; - pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); - fill_dci_pdu_rel15(secondaryCellGroup,pdsch_pdu_rel15,pdcch_pdu_rel15,NULL,&dci_pdu_rel15[0],dci_formats,rnti_types); + pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(secondaryCellGroup,&dci_pdu_rel15[0],dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); + fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types); LOG_D(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \ coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n", @@ -419,29 +419,29 @@ int configure_fapi_dl_pdu(int Mod_idP, void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types) { - dci_pdu_rel15->frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size, + dci_pdu_rel15->frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size, pusch_pdu->rb_start, NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275)); - dci_pdu_rel15->time_domain_assignment = 2; // row index used here instead of SLIV; - dci_pdu_rel15->frequency_hopping_flag = 0; - dci_pdu_rel15->mcs = 9; + dci_pdu_rel15->time_domain_assignment.val = 2; // row index used here instead of SLIV; + dci_pdu_rel15->frequency_hopping_flag.val = 0; + dci_pdu_rel15->mcs[0].val = 9; - dci_pdu_rel15->format_indicator = 0; - dci_pdu_rel15->ndi = 1; - dci_pdu_rel15->rv = 0; - dci_pdu_rel15->harq_pid = 0; - dci_pdu_rel15->tpc = 2; + dci_pdu_rel15->format_indicator.val = 0; + dci_pdu_rel15->ndi[0].val = 1; + dci_pdu_rel15->rv[0].val = 0; + dci_pdu_rel15->harq_pid.val = 0; + dci_pdu_rel15->tpc.val = 2; LOG_D(MAC, "[gNB scheduler phytest] ULDCI type 0 payload: PDCCH CCEIndex %d, freq_alloc %d, time_alloc %d, freq_hop_flag %d, mcs %d tpc %d ndi %d rv %d\n", pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci], - dci_pdu_rel15->frequency_domain_assignment, - dci_pdu_rel15->time_domain_assignment, - dci_pdu_rel15->frequency_hopping_flag, - dci_pdu_rel15->mcs, - dci_pdu_rel15->tpc, - dci_pdu_rel15->ndi, - dci_pdu_rel15->rv); + dci_pdu_rel15->frequency_domain_assignment.val, + dci_pdu_rel15->time_domain_assignment.val, + dci_pdu_rel15->frequency_hopping_flag.val, + dci_pdu_rel15->mcs[0].val, + dci_pdu_rel15->tpc.val, + dci_pdu_rel15->ndi[0].val, + dci_pdu_rel15->rv[0].val); dci_formats[pdcch_pdu_rel15->numDlDci] = NR_UL_DCI_FORMAT_0_0; rnti_types[pdcch_pdu_rel15->numDlDci] = NR_RNTI_C; @@ -832,8 +832,8 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); - pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); - fill_dci_pdu_rel15(secondaryCellGroup,NULL,pdcch_pdu_rel15,pusch_pdu,&dci_pdu_rel15[0],dci_formats,rnti_types); + pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(secondaryCellGroup,&dci_pdu_rel15[0],dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); + fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types); } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 31266208fd..a3961d1f88 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -544,45 +544,12 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, } } -// TODO: Move the following 3 functions somewhere that UE can also use -// Table 5.1.2.2.1-1 38.214 -uint8_t getRBGSize(uint16_t bwp_size, long rbg_size_config) { - - AssertFatal(bwp_size<276,"BWP Size > 275\n"); - - if (bwp_size < 37) return (rbg_size_config ? 4 : 2); - if (bwp_size < 73) return (rbg_size_config ? 8 : 4); - if (bwp_size < 145) return (rbg_size_config ? 16 : 8); - if (bwp_size < 276) return 16; -} - -uint8_t getNRBG(uint16_t bwp_size, uint16_t bwp_start, long rbg_size_config) { - - uint8_t rbg_size = getRBGSize(bwp_size,rbg_size_config); - - return (uint8_t)ceil((bwp_size+(bwp_start % rbg_size))/rbg_size); -} - -uint8_t getAntPortBitWidth(NR_SetupRelease_DMRS_DownlinkConfig_t *typeA, NR_SetupRelease_DMRS_DownlinkConfig_t *typeB) { - - uint8_t nbitsA, nbitsB, nbits = 0; - if (typeA != NULL) nbitsA = (typeA->choise.setup->maxLength[0]==0) ? 4 : 5; - if (typeB != NULL) nbitsB = (typeB->choise.setup->maxLength[0]==0) ? 5 : 6; - if ((typeA != NULL) && (typeB != NULL)) nbits = (nbitsA > nbitsB) ? nbitsA : nbitsB; - - return nbits; -} - -void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, - nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15, - nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, - nfapi_nr_pusch_pdu_t *pusch_pdu, +void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types ) { - NR_PDSCH_Config_t *pdsch_config = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup; uint16_t N_RB = pdcch_pdu_rel15->BWPSize; uint8_t fsize=0, pos=0; uint8_t nbits=0; @@ -603,44 +570,44 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, // Freq domain assignment fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); pos=fsize; - *dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment&((1< %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment,fsize,N_RB,dci_size-pos,*dci_pdu); + *dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment.val&((1< %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,N_RB,dci_size-pos,*dci_pdu); // Time domain assignment pos+=4; - *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment&0xf) << (dci_size-pos)); - LOG_D(MAC,"time-domain assignment %d (3 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment,dci_size-pos,*dci_pdu); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val&0xf) << (dci_size-pos)); + LOG_D(MAC,"time-domain assignment %d (3 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,dci_size-pos,*dci_pdu); // VRB to PRB mapping pos++; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&0x1)<<(dci_size-pos); - LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,dci_size-pos,*dci_pdu); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&0x1)<<(dci_size-pos); + LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping.val,dci_size-pos,*dci_pdu); // MCS pos+=5; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos); - LOG_D(MAC,"mcs %d (5 bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,dci_size-pos,*dci_pdu); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs[0].val&0x1f)<<(dci_size-pos); + LOG_D(MAC,"mcs[0] %d (5 bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs[0].val,dci_size-pos,*dci_pdu); // TB scaling pos+=2; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->tb_scaling&0x3)<<(dci_size-pos); - LOG_D(MAC,"tb_scaling %d (2 bits)=> %d (0x%lx)\n",dci_pdu_rel15->tb_scaling,dci_size-pos,*dci_pdu); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->tb_scaling.val&0x3)<<(dci_size-pos); + LOG_D(MAC,"tb_scaling %d (2 bits)=> %d (0x%lx)\n",dci_pdu_rel15->tb_scaling.val,dci_size-pos,*dci_pdu); break; case NR_RNTI_C: // indicating a DL DCI format 1bit pos++; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&1)<<(dci_size-pos); - LOG_D(MAC,"Format indicator %d (%d bits) N_RB_BWP %d => %d (0x%lx)\n",dci_pdu_rel15->format_indicator,1,N_RB,dci_size-pos,*dci_pdu); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator.val&1)<<(dci_size-pos); + LOG_D(MAC,"Format indicator %d (%d bits) N_RB_BWP %d => %d (0x%lx)\n",dci_pdu_rel15->format_indicator.val,1,N_RB,dci_size-pos,*dci_pdu); // Freq domain assignment (275rb >> fsize = 16) fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); pos+=fsize; - *dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment&((1<frequency_domain_assignment.val&((1< %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment,fsize,dci_size-pos,*dci_pdu); + LOG_D(MAC,"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,dci_size-pos,*dci_pdu); uint16_t is_ra = 1; for (int i=0; ifrequency_domain_assignment>>i)&1)) { + if (!((dci_pdu_rel15->frequency_domain_assignment.val>>i)&1)) { is_ra = 0; break; } @@ -648,19 +615,19 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, { // ra_preamble_index 6 bits pos+=6; - *dci_pdu |= ((dci_pdu_rel15->ra_preamble_index&0x3f)<<(dci_size-pos)); + *dci_pdu |= ((dci_pdu_rel15->ra_preamble_index.val&0x3f)<<(dci_size-pos)); // UL/SUL indicator 1 bit pos++; - *dci_pdu |= (dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos); + *dci_pdu |= (dci_pdu_rel15->ul_sul_indicator.val&1)<<(dci_size-pos); // SS/PBCH index 6 bits pos+=6; - *dci_pdu |= ((dci_pdu_rel15->ss_pbch_index&0x3f)<<(dci_size-pos)); + *dci_pdu |= ((dci_pdu_rel15->ss_pbch_index.val&0x3f)<<(dci_size-pos)); // prach_mask_index 4 bits pos+=4; - *dci_pdu |= ((dci_pdu_rel15->prach_mask_index&0xf)<<(dci_size-pos)); + *dci_pdu |= ((dci_pdu_rel15->prach_mask_index.val&0xf)<<(dci_size-pos)); } //end if @@ -669,53 +636,53 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, // Time domain assignment 4bit pos+=4; - *dci_pdu |= ((dci_pdu_rel15->time_domain_assignment&0xf) << (dci_size-pos)); - LOG_D(MAC,"Time domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment,4,dci_size-pos,*dci_pdu); + *dci_pdu |= ((dci_pdu_rel15->time_domain_assignment.val&0xf) << (dci_size-pos)); + LOG_D(MAC,"Time domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,4,dci_size-pos,*dci_pdu); // VRB to PRB mapping 1bit pos++; - *dci_pdu |= (dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos); - LOG_D(MAC,"VRB to PRB %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,1,dci_size-pos,*dci_pdu); + *dci_pdu |= (dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos); + LOG_D(MAC,"VRB to PRB %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping.val,1,dci_size-pos,*dci_pdu); // MCS 5bit //bit over 32, so dci_pdu ++ pos+=5; - *dci_pdu |= (dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos); - LOG_D(MAC,"MCS %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,5,dci_size-pos,*dci_pdu); + *dci_pdu |= (dci_pdu_rel15->mcs[0].val&0x1f)<<(dci_size-pos); + LOG_D(MAC,"MCS %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs[0].val,5,dci_size-pos,*dci_pdu); // New data indicator 1bit pos++; - *dci_pdu |= (dci_pdu_rel15->ndi&1)<<(dci_size-pos); - LOG_D(MAC,"NDI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->ndi,1,dci_size-pos,*dci_pdu); + *dci_pdu |= (dci_pdu_rel15->ndi[0].val&1)<<(dci_size-pos); + LOG_D(MAC,"NDI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->ndi[0].val,1,dci_size-pos,*dci_pdu); // Redundancy version 2bit pos+=2; - *dci_pdu |= (dci_pdu_rel15->rv&0x3)<<(dci_size-pos); - LOG_D(MAC,"RV %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->rv,2,dci_size-pos,*dci_pdu); + *dci_pdu |= (dci_pdu_rel15->rv[0].val&0x3)<<(dci_size-pos); + LOG_D(MAC,"RV %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->rv[0].val,2,dci_size-pos,*dci_pdu); // HARQ process number 4bit pos+=4; - *dci_pdu |= ((dci_pdu_rel15->harq_pid&0xf)<<(dci_size-pos)); - LOG_D(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_pid,4,dci_size-pos,*dci_pdu); + *dci_pdu |= ((dci_pdu_rel15->harq_pid.val&0xf)<<(dci_size-pos)); + LOG_D(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_pid.val,4,dci_size-pos,*dci_pdu); // Downlink assignment index 2bit pos+=2; - *dci_pdu |= ((dci_pdu_rel15->dai&3)<<(dci_size-pos)); - LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai,2,dci_size-pos,*dci_pdu); + *dci_pdu |= ((dci_pdu_rel15->dai.val&3)<<(dci_size-pos)); + LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai.val,2,dci_size-pos,*dci_pdu); // TPC command for scheduled PUCCH 2bit pos+=2; - *dci_pdu |= ((dci_pdu_rel15->tpc&3)<<(dci_size-pos)); - LOG_D(MAC,"TPC %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->tpc,2,dci_size-pos,*dci_pdu); + *dci_pdu |= ((dci_pdu_rel15->tpc.val&3)<<(dci_size-pos)); + LOG_D(MAC,"TPC %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->tpc.val,2,dci_size-pos,*dci_pdu); // PUCCH resource indicator 3bit pos+=3; - *dci_pdu |= ((dci_pdu_rel15->pucch_resource_indicator&0x7)<<(dci_size-pos)); - LOG_D(MAC,"PUCCH RI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pucch_resource_indicator,3,dci_size-pos,*dci_pdu); + *dci_pdu |= ((dci_pdu_rel15->pucch_resource_indicator.val&0x7)<<(dci_size-pos)); + LOG_D(MAC,"PUCCH RI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pucch_resource_indicator.val,3,dci_size-pos,*dci_pdu); // PDSCH-to-HARQ_feedback timing indicator 3bit pos+=3; - *dci_pdu |= ((dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator&0x7)<<(dci_size-pos)); - LOG_D(MAC,"PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator,3,dci_size-pos,*dci_pdu); + *dci_pdu |= ((dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val&0x7)<<(dci_size-pos)); + LOG_D(MAC,"PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val,3,dci_size-pos,*dci_pdu); } //end else break; @@ -724,26 +691,26 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, // Short Messages Indicator – 2 bits for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages_indicator>>(1-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages_indicator.val>>(1-i))&1)<<(dci_size-pos++); // Short Messages – 8 bits for (int i=0; i<8; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages>>(7-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages.val>>(7-i))&1)<<(dci_size-pos++); // Freq domain assignment 0-16 bit fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++); // Time domain assignment 4 bit for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++); // VRB to PRB mapping 1 bit - *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++); // MCS 5 bit for (int i=0; i<5; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs[0].val>>(4-i))&1)<<(dci_size-pos++); // TB scaling 2 bit for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->tb_scaling>>(1-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->tb_scaling.val>>(1-i))&1)<<(dci_size-pos++); break; @@ -752,52 +719,52 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, // Freq domain assignment 0-16 bit fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); + *dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++); // Time domain assignment 4 bit for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++); // VRB to PRB mapping 1 bit - *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++); // MCS 5bit //bit over 32, so dci_pdu ++ for (int i=0; i<5; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs[0].val>>(4-i))&1)<<(dci_size-pos++); // Redundancy version 2bit for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv>>(1-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv[0].val>>(1-i))&1)<<(dci_size-pos++); break; case NR_RNTI_TC: // indicating a DL DCI format 1bit - *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator.val&1)<<(dci_size-pos++); // Freq domain assignment 0-16 bit fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++); // Time domain assignment 4 bit for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++); // VRB to PRB mapping 1 bit - *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++); // MCS 5bit //bit over 32, so dci_pdu ++ for (int i=0; i<5; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs[0].val>>(4-i))&1)<<(dci_size-pos++); // New data indicator 1bit - *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi[0].val&1)<<(dci_size-pos++); // Redundancy version 2bit for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv>>(1-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv[0].val>>(1-i))&1)<<(dci_size-pos++); // HARQ process number 4bit for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid>>(3-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid.val>>(3-i))&1)<<(dci_size-pos++); // Downlink assignment index – 2 bits for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->dai>>(1-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->dai.val>>(1-i))&1)<<(dci_size-pos++); // TPC command for scheduled PUCCH – 2 bits for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc>>(1-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc.val>>(1-i))&1)<<(dci_size-pos++); // LOG_D(MAC, "DCI PDU: [0]->0x%08llx \t [1]->0x%08llx \t [2]->0x%08llx \t [3]->0x%08llx\n", @@ -806,7 +773,7 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, // PDSCH-to-HARQ_feedback timing indicator – 3 bits for (int i=0; i<3; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator>>(2-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val>>(2-i))&1)<<(dci_size-pos++); break; } @@ -817,81 +784,81 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, { case NR_RNTI_C: // indicating a DL DCI format 1bit - *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator.val&1)<<(dci_size-pos++); // Freq domain assignment max 16 bit fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); + *dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++); // Time domain assignment 4bit for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++); // Frequency hopping flag – 1 bit - *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag.val&1)<<(dci_size-pos++); // MCS 5 bit for (int i=0; i<5; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs[0].val>>(4-i))&1)<<(dci_size-pos++); // New data indicator 1bit - *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi[0].val&1)<<(dci_size-pos++); // Redundancy version 2bit for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv>>(1-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv[0].val>>(1-i))&1)<<(dci_size-pos++); // HARQ process number 4bit for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid>>(3-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid.val>>(3-i))&1)<<(dci_size-pos++); // TPC command for scheduled PUSCH – 2 bits for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc>>(1-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc.val>>(1-i))&1)<<(dci_size-pos++); // Padding bits for(int a = pos;a<32;a++) - *dci_pdu |= ((uint64_t)dci_pdu_rel15->padding&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->padding.val&1)<<(dci_size-pos++); // UL/SUL indicator – 1 bit /* commented for now (RK): need to get this from BWP descriptor if (cfg->pucch_config.pucch_GroupHopping.value) - *dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator.val&1)<<(dci_size-pos++); */ break; case NFAPI_NR_RNTI_TC: // indicating a DL DCI format 1bit - *dci_pdu |= (dci_pdu_rel15->format_indicator&1)<<(dci_size-pos++); + *dci_pdu |= (dci_pdu_rel15->format_indicator.val&1)<<(dci_size-pos++); // Freq domain assignment max 16 bit fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); + *dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++); // Time domain assignment 4bit for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++); // Frequency hopping flag – 1 bit - *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag.val&1)<<(dci_size-pos++); // MCS 5 bit for (int i=0; i<5; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs[0].val>>(4-i))&1)<<(dci_size-pos++); // New data indicator 1bit - *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi[0].val&1)<<(dci_size-pos++); // Redundancy version 2bit for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv>>(1-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv[0].val>>(1-i))&1)<<(dci_size-pos++); // HARQ process number 4bit for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid>>(3-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid.val>>(3-i))&1)<<(dci_size-pos++); // TPC command for scheduled PUSCH – 2 bits for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc>>(1-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc.val>>(1-i))&1)<<(dci_size-pos++); // Padding bits for(int a = pos;a<32;a++) - *dci_pdu |= ((uint64_t)dci_pdu_rel15->padding&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->padding.val&1)<<(dci_size-pos++); // UL/SUL indicator – 1 bit /* commented for now (RK): need to get this information from BWP descriptor if (cfg->pucch_config.pucch_GroupHopping.value) - *dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator.val&1)<<(dci_size-pos++); */ break; @@ -900,158 +867,110 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, case NR_DL_DCI_FORMAT_1_1: // Indicating a DL DCI format 1bit - pos=1; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&1)<<(dci_size-pos); + pos=dci_pdu_rel15->format_indicator.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator.val&((1<format_indicator.nbits)-1))<<(dci_size-pos); // Carrier indicator - if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig != NULL) { - pos+=3; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->carrier_indicator&0x7)<<(dci_size-pos); - } + pos+=dci_pdu_rel15->carrier_indicator.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->carrier_indicator.val&((1<carrier_indicator.nbits)-1))<<(dci_size-pos); // BWP indicator - uint8_t n_dl_bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count; - - nbits = (uint8_t)((n_dl_bwp < 4) ? ceil(log2(n_dl_bwp+1)) : ceil(log2(n_dl_bwp))); - pos+=nbits; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->bwp_indicator&((1<bwp_indicator.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->bwp_indicator.val&((1<bwp_indicator.nbits)-1))<<(dci_size-pos); // Frequency domain resource assignment - long rbg_size_config = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rbg_Size; - uint16_t numRBG = getNRBG(pdsch_pdu_rel15->BWPSize,pdsch_pdu_rel15->BWPStart,rbg_size_config); - - if (pdsch_config->resourceAllocation == 0) - nbits = numRBG; - else if (pdsch_config->resourceAllocation == 1) - nbits = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); - else - nbits = ((int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )>numRBG) ? (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )+1 : numRBG+1; - - pos+=nbits; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_domain_assignment&((1<frequency_domain_assignment.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val&((1<frequency_domain_assignment.nbits)-1)) << (dci_size-pos); // Time domain resource assignment - NR_PDSCH_TimeDomainResourceAllocationList_t *pdsch_timeDomList = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[0]->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList; - int num_entries; - if (pdsch_timeDomList != NULL) - num_entries = pdsch_timeDomList->list.count; - else - num_entries = 16; // num of entries in default table - - nbits = (int)ceil(log2(num_entries)); pos+=nbits; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->time_domain_assignment&((1<time_domain_assignment.val&((1<time_domain_assignment.nbits)-1)) << (dci_size-pos); // VRB-to-PRB mapping - if (pdsch_config->resourceAllocation == 1) { - pos++; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos); - } + pos+=dci_pdu_rel15->vrb_to_prb_mapping.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&((1<vrb_to_prb_mapping.nbits)-1))<<(dci_size-pos); // PRB bundling size indicator - if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.present == 2) { - pos++; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->prb_bundling_size_indicator&1)<<(dci_size-pos); - } + pos+=dci_pdu_rel15->prb_bundling_size_indicator.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->prb_bundling_size_indicator.val&((1<prb_bundling_size_indicator.nbits)-1))<<(dci_size-pos); // Rate matching indicator - NR_RateMatchPatternGroup_t *group1 = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup1; - NR_RateMatchPatternGroup_t *group2 = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup2; - nbits = 0; - if ((group1 != NULL) && (group2 != NULL)) - nbits = 2; - if ((group1 != NULL) != (group2 != NULL)) - nbits = 1; - pos+=nbits; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->rate_matching_indicator&((1<rate_matching_indicator.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->rate_matching_indicator.val&((1<rate_matching_indicator.nbits)-1))<<(dci_size-pos); // ZP CSI-RS trigger - uint8_t nZP = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList->list.count; - nbits = (int)ceil(log2(nZP+1)); - pos+=nbits; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->zp_csi_rs_trigger&((1<zp_csi_rs_trigger.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->zp_csi_rs_trigger.val&((1<zp_csi_rs_trigger.nbits)-1)) << (dci_size-pos); + //TB1 // MCS 5bit - pos+=5; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos); + pos+=dci_pdu_rel15->mcs[0].nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs[0].val&((1<mcs[0].nbits)-1))<<(dci_size-pos); // New data indicator 1bit - pos++; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&1)<<(dci_size-pos); + pos+=dci_pdu_rel15->ndi[0].nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi[0].val&((1<ndi[0].nbits)-1))<<(dci_size-pos); // Redundancy version 2bit - pos+=2; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->rv&0x3)<<(dci_size-pos); + pos+=dci_pdu_rel15->rv[0].nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->rv[0].val&((1<rv[0].nbits)-1))<<(dci_size-pos); + + //TB2 + // MCS 5bit + pos+=dci_pdu_rel15->mcs[1].nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs[1].val&((1<mcs[1].nbits)-1))<<(dci_size-pos); + + // New data indicator 1bit + pos+=dci_pdu_rel15->ndi[1].nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi[1].val&((1<ndi[1].nbits)-1))<<(dci_size-pos); + + // Redundancy version 2bit + pos+=dci_pdu_rel15->rv[1].nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->rv[1].val&((1<rv[1].nbits)-1))<<(dci_size-pos); // HARQ process number 4bit - pos+=4; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid&0xf)<<(dci_size-pos); + pos+=dci_pdu_rel15->harq_pid.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid.val&((1<harq_pid.nbits)-1))<<(dci_size-pos); // Downlink assignment index - if (secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook == 1) { // at this point the UE has multiple serving cells - pos+=4; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->dai&0xf)<<(dci_size-pos); - } -/* else if (0) { - pos+=2; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->dai&0x3)<<(dci_size-pos); - } -*/ + pos+=dci_pdu_rel15->dai.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->dai.val&((1<dai.nbits)-1))<<(dci_size-pos); // TPC command for scheduled PUCCH 2bit - pos+=2; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->tpc&0x3)<<(dci_size-pos); + pos+=dci_pdu_rel15->tpc.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->tpc.val&((1<tpc.nbits)-1))<<(dci_size-pos); // PUCCH resource indicator 3bit - pos+=3; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->pucch_resource_indicator&0x7)<<(dci_size-pos); + pos+=dci_pdu_rel15->pucch_resource_indicator.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->pucch_resource_indicator.val&((1<pucch_resource_indicator.nbits)-1))<<(dci_size-pos); // PDSCH-to-HARQ_feedback timing indicator - uint8_t I = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[0]->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK->list.count; - nbits = (int)ceil(log2(I)); - pos+=nbits; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator&((1<pdsch_to_harq_feedback_timing_indicator.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val&((1<pdsch_to_harq_feedback_timing_indicator.nbits)-1))<<(dci_size-pos); // Antenna ports - NR_SetupRelease_DMRS_DownlinkConfig_t *typeA = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA; - NR_SetupRelease_DMRS_DownlinkConfig_t *typeB = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeB; - nbits = getAntPortBitWidth(typeA,typeB); - pos+=nbits; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->antenna_ports&((1<antenna_ports.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->antenna_ports.val&((1<antenna_ports.nbits)-1))<<(dci_size-pos); // TCI - long *isTciEnable = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[0]->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[0]->tci_PresentInDCI; - if (isTciEnable != NULL) { - pos+=3; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->transmission_configuration_indication&0x7)<<(dci_size-pos); - } + pos+=dci_pdu_rel15->transmission_configuration_indication.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->transmission_configuration_indication.val&((1<transmission_configuration_indication.nbits)-1))<<(dci_size-pos); // SRS request - if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig==NULL) - nbits = 2; - else - nbits = 3; - pos+=nbits; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->srs_request&((1<srs_request.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->srs_request.val&((1<srs_request.nbits)-1))<<(dci_size-pos); // CBG transmission information - uint8_t maxCBGperTB = (secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_ServingCellConfig->choise.setup->codeBlockGroupTransmission->choise.setup->maxCodeBlockGroupsPerTransportBlock + 1) * 2; - long *maxCWperDCI_rrc = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI; - uint8_t maxCWperDCI = (maxCWperDCI_rrc == NULL) ? 1 : *maxCWperDCI_rrc; - nbits = maxCBGperTB * maxCWperDCI; - pos+=nbits; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->cbgti&((1<cbgti.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->cbgti.val&((1<cbgti.nbits)-1))<<(dci_size-pos); // CBG flushing out information - if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_ServingCellConfig->choise.setup->codeBlockGroupTransmission->choise.setup->codeBlockGroupFlushIndicator) { - pos+=1; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->cbgfi&0x1)<<(dci_size-pos); - } + pos+=dci_pdu_rel15->cbgfi.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->cbgfi.val&((1<cbgfi.nbits)-1))<<(dci_size-pos); // DMRS sequence init - pos+=1; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->dmrs_sequence_initialization&0x1)<<(dci_size-pos); + pos+=dci_pdu_rel15->dmrs_sequence_initialization.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->dmrs_sequence_initialization.val&((1<dmrs_sequence_initialization.nbits)-1))<<(dci_size-pos); } } } diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index fd02368c0d..3046abfb71 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -130,10 +130,7 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, NR_ServingCellConfigCommon_t *scc, NR_BWP_Downlink_t *bwp); -void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, - nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15, - nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, - nfapi_nr_pusch_pdu_t *pusch_pdu, +void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types); @@ -166,9 +163,11 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP); int get_num_dmrs(uint16_t dmrs_mask ); -uint16_t nr_dci_size(nr_dci_format_t format, - nr_rnti_type_t rnti_type, - uint16_t N_RB); +uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, + dci_pdu_rel15_t *dci_pdu, + nr_dci_format_t format, + nr_rnti_type_t rnti_type, + uint16_t N_RB); int allocate_nr_CCEs(gNB_MAC_INST *nr_mac, int bwp_id, diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index 5bc320d5e2..d21f0be2a2 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -190,7 +190,7 @@ typedef struct gNB_MAC_INST_s { int cce_list[MAX_NUM_BWP][MAX_NUM_CORESET][MAX_NUM_CCE]; } gNB_MAC_INST; -typedef struct { +/*typedef struct { uint8_t format_indicator; //1 bit @@ -250,8 +250,74 @@ uint8_t antenna_ports; uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits uint16_t padding; +} dci_pdu_rel15_t;*/ + +typedef struct { + uint16_t val; + uint8_t nbits; +} dci_field_t; + +typedef struct { + + +dci_field_t format_indicator; //1 bit +dci_field_t frequency_domain_assignment; //up to 16 bits +dci_field_t time_domain_assignment; // 4 bits +dci_field_t frequency_hopping_flag; //1 bit + +dci_field_t ra_preamble_index; //6 bits +dci_field_t ss_pbch_index; //6 bits +dci_field_t prach_mask_index; //4 bits + +dci_field_t vrb_to_prb_mapping; //0 or 1 bit +dci_field_t mcs[2]; //5 bits +dci_field_t ndi[2]; //1 bit +dci_field_t rv[2]; //2 bits +dci_field_t harq_pid; //4 bits +dci_field_t dai; //0, 2 or 4 bits +dci_field_t dai1; //1 or 2 bits +dci_field_t dai2; //0 or 2 bits +dci_field_t tpc; //2 bits +dci_field_t pucch_resource_indicator; //3 bits +dci_field_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits + +dci_field_t short_messages_indicator; //2 bits +dci_field_t short_messages; //8 bits +dci_field_t tb_scaling; //2 bits + +dci_field_t carrier_indicator; //0 or 3 bits +dci_field_t bwp_indicator; //0, 1 or 2 bits +dci_field_t prb_bundling_size_indicator; //0 or 1 bits +dci_field_t rate_matching_indicator; //0, 1 or 2 bits +dci_field_t zp_csi_rs_trigger; //0, 1 or 2 bits +dci_field_t transmission_configuration_indication; //0 or 3 bits +dci_field_t srs_request; //2 bits +dci_field_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits +dci_field_t cbgfi; //CBG Flushing Out Information: 0 or 1 bit +dci_field_t dmrs_sequence_initialization; //0 or 1 bit + +dci_field_t srs_resource_indicator; +dci_field_t precoding_information; +dci_field_t csi_request; +dci_field_t ptrs_dmrs_association; +dci_field_t beta_offset_indicator; //0 or 2 bits + +dci_field_t slot_format_indicator_count; +dci_field_t *slot_format_indicators; + +dci_field_t pre_emption_indication_count; +dci_field_t *pre_emption_indications; //14 bit + +dci_field_t block_number_count; +dci_field_t *block_numbers; + +dci_field_t ul_sul_indicator; //0 or 1 bit +dci_field_t antenna_ports; + +dci_field_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits +dci_field_t padding; + } dci_pdu_rel15_t; - #endif /*__LAYER2_NR_MAC_GNB_H__ */ From 8c68f3745066478174aa0fd8aa45f45737fafd8f Mon Sep 17 00:00:00 2001 From: cig Date: Thu, 2 Apr 2020 14:35:41 +0200 Subject: [PATCH 130/553] Prachsim compilation and NR PRACH UE fixes --- cmake_targets/CMakeLists.txt | 2 +- openair1/PHY/NR_UE_TRANSPORT/nr_prach.c | 38 +- openair1/SIMULATION/NR_PHY/prachsim.c | 517 +++++++++++++----------- 3 files changed, 289 insertions(+), 268 deletions(-) diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index a23f985612..015b517a14 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -2822,7 +2822,7 @@ add_executable(nr_prachsim ${T_SOURCE} ${SHLIB_LOADER_SOURCES}) target_link_libraries(nr_prachsim - -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_RU PHY_NR_UE MAC_NR_COMMON SCHED_NR_LIB SCHED_NR_UE_LIB RRC_LIB NR_RRC_LIB L2_NR CONFIG_LIB -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl) + -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_RU PHY_NR_UE MAC_NR_COMMON SCHED_NR_LIB MAC_UE_NR SCHED_NR_UE_LIB RRC_LIB NR_RRC_LIB L2_NR CONFIG_LIB -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl) add_executable(nr_ulschsim ${OPENAIR1_DIR}/SIMULATION/NR_PHY/ulschsim.c diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c index 6989c0af32..72d21600f7 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c @@ -75,8 +75,8 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t slot){ fapi_nr_ul_config_prach_pdu *prach_pdu = &ue->prach_vars[gNB_id]->prach_pdu; uint8_t Mod_id, fd_occasion, preamble_index, restricted_set, not_found; - uint16_t rootSequenceIndex, prach_fmt_id, NCS, *prach_root_sequence_map, preamble_offset; - uint16_t preamble_shift, preamble_index0, n_shift_ra, n_shift_ra_bar, d_start, numshift, N_ZC, u, offset, offset2, first_nonzero_root_idx; + uint16_t rootSequenceIndex, prach_fmt_id, NCS, *prach_root_sequence_map, preamble_offset = 0; + uint16_t preamble_shift = 0, preamble_index0, n_shift_ra, n_shift_ra_bar, d_start, numshift, N_ZC, u, offset, offset2, first_nonzero_root_idx; int16_t prach_tmp[98304*2*4] __attribute__((aligned(32))); int16_t Ncp, amp, *prach, *prach2, *prachF, *Xu; int32_t Xu_re, Xu_im, samp_count; @@ -125,7 +125,7 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t slot){ if (prach_start >= (fp->samples_per_subframe*NR_NUMBER_OF_SUBFRAMES_PER_FRAME)) prach_start -= (fp->samples_per_subframe*NR_NUMBER_OF_SUBFRAMES_PER_FRAME); #else //normal case (simulation) - prach_start = slot*(fp->samples_per_subframe)-ue->N_TA_offset; + prach_start = slot*samp_count - ue->N_TA_offset; #endif // First compute physical root sequence @@ -138,10 +138,9 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t slot){ prach_root_sequence_map = (prach_sequence_length == 0) ? prach_root_sequence_map_0_3 : prach_root_sequence_map_abc; - // This is the relative offset (for unrestricted case) in the root sequence table (5.7.2-4 from 36.211) for the given preamble index - preamble_offset = ((NCS==0)? preamble_index : (preamble_index/(N_ZC/NCS))); - if (restricted_set == 0) { + // This is the relative offset (for unrestricted case) in the root sequence table (5.7.2-4 from 36.211) for the given preamble index + preamble_offset = ((NCS==0)? preamble_index : (preamble_index/(N_ZC/NCS))); // This is the \nu corresponding to the preamble index preamble_shift = (NCS==0)? 0 : (preamble_index % (N_ZC/NCS)); preamble_shift *= NCS; @@ -204,9 +203,6 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t slot){ } } - preamble_offset = 0; - preamble_shift = 0; - // now generate PRACH signal #ifdef NR_PRACH_DEBUG if (NCS>0) @@ -465,17 +461,17 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t slot){ } } else { // short PRACH sequence if (prach_fmt_id == 0 || prach_fmt_id == 3 || prach_fmt_id == 7) { - Ncp+=32; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling - prach2 = prach+(Ncp<<1); - idft2048(prachF,prach2,1); - // here we have |empty | Prach2048 | - if (prach_fmt_id != 7) { - memmove(prach2+(2048<<1),prach2,(2048<<2)); - prach_len = (2048*2)+Ncp; - } - else prach_len = (2048*1)+Ncp; - memmove(prach,prach+(2048<<1),(Ncp<<2)); - // here we have |Prefix | Prach2048 | Prach2048 (if ! 0xc0) | + Ncp+=32; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling + prach2 = prach+(Ncp<<1); + idft2048(prachF,prach2,1); + // here we have |empty | Prach2048 | + if (prach_fmt_id != 7) { + memmove(prach2+(2048<<1),prach2,(2048<<2)); + prach_len = (2048*2)+Ncp; + } + else prach_len = (2048*1)+Ncp; + memmove(prach,prach+(2048<<1),(Ncp<<2)); + // here we have |Prefix | Prach2048 | Prach2048 (if ! 0xc0) | } else if (prach_fmt_id == 1 || prach_fmt_id == 4) { // 6x2048 Ncp+=32; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling prach2 = prach+(Ncp<<1); @@ -573,8 +569,6 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t slot){ } else if (prach_fmt_id == 1 || prach_fmt_id == 4) { // 6x1536 - printf(" CHECK 3/4 sampling prachFormat == 0xa2\n"); - Ncp+=24; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling prach2 = prach+(Ncp<<1); idft1536(prachF,prach2,1); diff --git a/openair1/SIMULATION/NR_PHY/prachsim.c b/openair1/SIMULATION/NR_PHY/prachsim.c index b903b2695e..47f3dd70aa 100644 --- a/openair1/SIMULATION/NR_PHY/prachsim.c +++ b/openair1/SIMULATION/NR_PHY/prachsim.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "common/config/config_userapi.h" #include "common/utils/LOG/log.h" @@ -35,7 +36,6 @@ #include "SCHED_NR/sched_nr.h" #include "SCHED_NR_UE/phy_frame_config_nr.h" #include "PHY/phy_vars_nr_ue.h" - #include "PHY/NR_REFSIG/refsig_defs_ue.h" #include "PHY/NR_REFSIG/nr_mod_table.h" #include "PHY/MODULATION/modulation_eNB.h" @@ -47,107 +47,74 @@ #include "nr_unitary_defs.h" #include "OCG_vars.h" -#include - - +#define NR_PRACH_DEBUG 1 +#define PRACH_WRITE_OUTPUT_DEBUG 1 PHY_VARS_gNB *gNB; PHY_VARS_NR_UE *UE; RAN_CONTEXT_t RC; RU_t *ru; - double cpuf; - extern uint16_t prach_root_sequence_map0_3[838]; - -void dump_nr_prach_config(NR_DL_FRAME_PARMS *frame_parms,uint8_t subframe); - uint16_t NB_UE_INST=1; - - openair0_config_t openair0_cfg[MAX_CARDS]; uint8_t nfapi_mode=0; +int sl_ahead = 0; +//void dump_nr_prach_config(NR_DL_FRAME_PARMS *frame_parms,uint8_t subframe); -void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, - module_id_t mod_id, - int CC_id, - UE_MODE_t UE_mode, - frame_t frame, - uint8_t gNB_id, - int nr_tti_tx) { return;} +/* temporary dummy implem of get_softmodem_optmask, till basic simulators implemented as device */ +uint64_t get_softmodem_optmask(void) {return 0;} +softmodem_params_t *get_softmodem_params(void) {return 0;} -void nr_Msg1_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id) { return;} +void pdcp_run (const protocol_ctxt_t *const ctxt_pP) { return;} -uint16_t nr_ue_process_rar(module_id_t mod_id, - int CC_id, - frame_t frameP, - uint8_t * dlsch_buffer, - rnti_t * t_crnti, - uint8_t preamble_index, - uint8_t * selected_rar_buffer) { return 0;} +boolean_t pdcp_data_ind(const protocol_ctxt_t *const ctxt_pP, + const srb_flag_t srb_flagP, + const MBMS_flag_t MBMS_flagP, + const rb_id_t rb_idP, + const sdu_size_t sdu_buffer_sizeP, + mem_block_t *const sdu_buffer_pP) {return(false);} -int is_nr_prach_subframe(NR_DL_FRAME_PARMS *fp,uint32_t frame,uint8_t slot) { return(1);} +void nr_ip_over_LTE_DRB_preconfiguration(void){} +void pdcp_layer_init(void) {} +int8_t nr_mac_rrc_data_ind_ue(const module_id_t module_id, const int CC_id, const uint8_t gNB_index, const int8_t channel, const uint8_t* pduP, const sdu_size_t pdu_len) {return 0;} -int get_nr_prach_fmt(int prachConfigIndex,int frame_type,int fr) { return(0xa2); } - - -int main(int argc, char **argv) -{ +int main(int argc, char **argv){ char c; - - int i,aa,aarx; - double sigma2, sigma2_dB=0,SNR,snr0=-2.0,snr1=0.0,ue_speed0=0.0,ue_speed1=0.0; - uint8_t snr1set=0; - uint8_t ue_speed1set=0; - int **txdata; - double **s_re,**s_im,**r_re,**r_im; - double iqim=0.0; - int trial; //, ntrials=1; - uint8_t transmission_mode = 1,n_tx=1,n_rx=1; - uint16_t Nid_cell=0; - - uint8_t awgn_flag=0; - uint8_t hs_flag=0; - int n_frames=1; - channel_desc_t *UE2gNB; - uint32_t nsymb,tx_lev=10000; //,tx_lev_dB; + double sigma2, sigma2_dB = 0, SNR, snr0 = -2.0, snr1 = 0.0, ue_speed0 = 0.0, ue_speed1 = 0.0; + double **s_re, **s_im, **r_re, **r_im, iqim = 0.0, delay_avg = 0, ue_speed = 0, fs, bw; + int i, aa, aarx, **txdata, trial, n_frames = 1, prach_start, rx_prach_start; //, ntrials=1; + int N_RB_UL = 106, delay = 0, NCS_config = 13, rootSequenceIndex = 1, threequarter_fs = 0, mu = 1, fd_occasion = 0, loglvl = OAILOG_INFO, numRA = 0, prachStartSymbol = 0; + uint8_t snr1set = 0, ue_speed1set = 0, transmission_mode = 1, n_tx = 1, n_rx = 1, awgn_flag = 0, msg1_frequencystart = 0, num_prach_fd_occasions = 1, prach_format; + uint8_t frame = 1, subframe = 19, config_index = 98, prach_sequence_length = 1, num_root_sequences = 16, restrictedSetConfig = 0, N_dur, N_t_slot, start_symbol; + uint16_t Nid_cell = 0, preamble_tx = 0, preamble_delay, format, format0, format1; + uint32_t tx_lev = 10000, prach_errors = 0, samp_count; //,tx_lev_dB; + uint64_t SSB_positions = 0x01, absoluteFrequencyPointA = 640000; // int8_t interf1=-19,interf2=-19; - NR_DL_FRAME_PARMS *frame_parms; - - SCM_t channel_model=Rayleigh1; - // uint8_t abstraction_flag=0,calibration_flag=0; // double prach_sinr; - int N_RB_UL=273; - uint32_t prach_errors=0; - uint8_t subframe=9; - uint16_t preamble_energy, preamble_tx=50, preamble_delay; - uint16_t preamble_max,preamble_energy_max; + // uint32_t nsymb; + // uint16_t preamble_max, preamble_energy_max; + + NR_DL_FRAME_PARMS *frame_parms; NR_PRACH_RESOURCES_t prach_resources; - //uint8_t prach_fmt; - //int N_ZC; - int delay = 0; - double delay_avg=0; - double ue_speed = 0; - int NCS_config = 13,rootSequenceIndex=0; - int threequarter_fs = 0; - int mu=1; - uint64_t SSB_positions=0x01; - - int loglvl=OAILOG_INFO; + nfapi_nr_prach_config_t *prach_config; + nfapi_nr_prach_pdu_t *prach_pdu; + fapi_nr_prach_config_t *ue_prach_config; + fapi_nr_ul_config_prach_pdu *ue_prach_pdu; + channel_desc_t *UE2gNB; + SCM_t channel_model = Rayleigh1; cpuf = get_cpu_freq_GHz(); - if ( load_configmodule(argc,argv,CONFIG_ENABLECMDLINEONLY) == 0) { exit_fun("[SOFTMODEM] Error, configuration module init failed\n"); } randominit(0); - while ((c = getopt (argc, argv, "hHaA:Cr:p:g:n:s:S:t:x:y:v:V:z:N:F:d:Z:L:R:E")) != -1) { switch (c) { case 'a': @@ -262,7 +229,7 @@ int main(int argc, char **argv) case 'H': printf("High-Speed Flag enabled\n"); - hs_flag = 1; + restrictedSetConfig = 1; break; case 'L': @@ -343,20 +310,13 @@ int main(int argc, char **argv) } } + // Configure log logInit(); - set_glog(loglvl); T_stdout = 1; - SET_LOG_DEBUG(PRACH); - if (snr1set==0) { - if (n_frames==1) - snr1 = snr0+.1; - else - snr1 = snr0+5.0; - } - + // Configure gNB and RU RC.gNB = (PHY_VARS_gNB**) malloc(2*sizeof(PHY_VARS_gNB *)); RC.gNB[0] = malloc(sizeof(PHY_VARS_gNB)); memset(RC.gNB[0],0,sizeof(PHY_VARS_gNB)); @@ -366,104 +326,200 @@ int main(int argc, char **argv) memset(RC.ru[0],0,sizeof(RU_t)); RC.nb_RU = 1; - gNB = RC.gNB[0]; - ru = RC.ru[0]; - - - if (ue_speed1set==0) { - if (n_frames==1) - ue_speed1 = ue_speed0+10; - else - ue_speed1 = ue_speed0+50; - } - - printf("SNR0 %f, SNR1 %f\n",snr0,snr1); - - frame_parms = &gNB->frame_parms; - - + gNB = RC.gNB[0]; + ru = RC.ru[0]; + frame_parms = &gNB->frame_parms; + prach_config = &gNB->gNB_config.prach_config; + prach_pdu = &gNB->prach_vars.list[0].pdu; + frame_parms = &gNB->frame_parms; //to be initialized I suppose (maybe not necessary for PBCH) s_re = malloc(2*sizeof(double*)); s_im = malloc(2*sizeof(double*)); r_re = malloc(2*sizeof(double*)); r_im = malloc(2*sizeof(double*)); - frame_parms = &gNB->frame_parms; //to be initialized I suppose (maybe not necessary for PBCH) - frame_parms->nb_antennas_tx = n_tx; - frame_parms->nb_antennas_rx = n_rx; - frame_parms->N_RB_DL = N_RB_UL; - frame_parms->N_RB_UL = N_RB_UL; - frame_parms->threequarter_fs = threequarter_fs; + frame_parms->nb_antennas_tx = n_tx; + frame_parms->nb_antennas_rx = n_rx; + frame_parms->N_RB_DL = N_RB_UL; + frame_parms->N_RB_UL = N_RB_UL; + frame_parms->threequarter_fs = threequarter_fs; + frame_parms->frame_type = TDD; + frame_parms->freq_range = nr_FR1; + frame_parms->numerology_index = mu; + nr_phy_config_request_sim(gNB, N_RB_UL, N_RB_UL, mu, Nid_cell, SSB_positions); - nr_phy_config_request_sim(gNB,N_RB_UL,N_RB_UL,mu,Nid_cell,SSB_positions); + //nsymb = (frame_parms->Ncp == 0) ? 14 : 12; - frame_parms->frame_type = TDD; - frame_parms->freq_range = nr_FR1; + printf("FFT Size %d, Extended Prefix %d, Samples per subframe %d, Frame type %s, Frequency Range %s\n", + NUMBER_OF_OFDM_CARRIERS, + frame_parms->Ncp, + frame_parms->samples_per_subframe, + frame_parms->frame_type == FDD ? "FDD" : "TDD", + frame_parms->freq_range == nr_FR1 ? "FR1" : "FR2"); - nsymb = (frame_parms->Ncp == 0) ? 14 : 12; + ru->nr_frame_parms = frame_parms; + ru->if_south = LOCAL_RF; + ru->nb_tx = n_tx; + ru->nb_rx = n_rx; - printf("FFT Size %d, Extended Prefix %d, Samples per subframe %d,Frame type %s, Frequency Range %s\n",NUMBER_OF_OFDM_CARRIERS, - frame_parms->Ncp,frame_parms->samples_per_subframe,frame_parms->frame_type == FDD ? "FDD" : "TDD", frame_parms->freq_range == nr_FR1 ? "FR1" : "FR2"); + gNB->gNB_config.carrier_config.num_tx_ant.value = 1; + gNB->gNB_config.carrier_config.num_rx_ant.value = 1; + gNB->gNB_config.tdd_table.tdd_period.value = 6; - ru->nr_frame_parms=frame_parms; - ru->if_south = LOCAL_RF; - ru->nb_tx = n_tx; - ru->nb_rx = n_rx; + gNB->gNB_config.prach_config.num_prach_fd_occasions.value = num_prach_fd_occasions; + gNB->gNB_config.prach_config.num_prach_fd_occasions_list = (nfapi_nr_num_prach_fd_occasions_t *) malloc(num_prach_fd_occasions*sizeof(nfapi_nr_num_prach_fd_occasions_t)); - gNB->gNB_config.carrier_config.num_tx_ant.value=1; - gNB->gNB_config.carrier_config.num_rx_ant.value=1; - gNB->gNB_config.prach_config.num_prach_fd_occasions_list = (nfapi_nr_num_prach_fd_occasions_t *) malloc(gNB->gNB_config.prach_config.num_prach_fd_occasions.value*sizeof(nfapi_nr_num_prach_fd_occasions_t)); - gNB->gNB_config.prach_config.num_prach_fd_occasions_list[0].prach_root_sequence_index.value = 1; - gNB->gNB_config.prach_config.num_prach_fd_occasions_list[0].num_root_sequences.value = 16; - gNB->gNB_config.prach_config.prach_sequence_length.value = 1; - gNB->gNB_config.prach_config.num_prach_fd_occasions_list[0].k1.value = 0; - gNB->gNB_config.prach_config.restricted_set_config.value = 0; - gNB->gNB_config.tdd_table.tdd_period.value = 6; + gNB->proc.slot_rx = subframe; + + get_nr_prach_info_from_index(config_index, + (int)frame, + (int)subframe, + absoluteFrequencyPointA, + mu, + frame_parms->frame_type, + &format, + &start_symbol, + &N_t_slot, + &N_dur); + + format0 = format&0xff; // first column of format from table + format1 = (format>>8)&0xff; // second column of format from table + + if (format1 != 0xff) { + switch(format0) { + case 0xa1: + prach_format = 9; + break; + case 0xa2: + prach_format = 10; + break; + case 0xa3: + prach_format = 11; + break; + default: + AssertFatal(1==0, "Only formats A1/B1 A2/B2 A3/B3 are valid for dual format"); + } + } else { + switch(format0) { + case 0xa1: + prach_format = 0; + break; + case 0xa2: + prach_format = 1; + break; + case 0xa3: + prach_format = 2; + break; + case 0xb1: + prach_format = 3; + break; + case 0xb2: + prach_format = 4; + break; + case 0xb3: + prach_format = 5; + break; + case 0xb4: + prach_format = 6; + break; + case 0xc0: + prach_format = 7; + break; + case 0xc2: + prach_format = 8; + break; + case 0: + // long formats are handled @ PHY + break; + case 1: + // long formats are handled @ PHY + break; + case 2: + // long formats are handled @ PHY + break; + case 3: + // long formats are handled @ PHY + break; + default: + AssertFatal(1==0, "Invalid PRACH format"); + } + } + + prach_config->num_prach_fd_occasions_list[fd_occasion].prach_root_sequence_index.value = rootSequenceIndex; + prach_config->num_prach_fd_occasions_list[fd_occasion].k1.value = msg1_frequencystart; + prach_config->restricted_set_config.value = restrictedSetConfig; + prach_config->prach_sequence_length.value = prach_sequence_length; + prach_config->num_prach_fd_occasions_list[fd_occasion].num_root_sequences.value = num_root_sequences; + prach_pdu->num_cs = get_NCS(NCS_config, format0, restrictedSetConfig); + prach_pdu->prach_format = prach_format; memcpy((void*)&ru->config,(void*)&RC.gNB[0]->gNB_config,sizeof(ru->config)); - RC.nb_nr_L1_inst=1; phy_init_nr_gNB(gNB,0,0); nr_phy_init_RU(ru); + gNB->common_vars.rxdata = ru->common.rxdata; + set_tdd_config_nr(&gNB->gNB_config, mu, 7, 6, 2, 4); - - set_tdd_config_nr(&gNB->gNB_config, 1, - 7, 6, - 2, 4); - - //configure UE + // Configure UE UE = malloc(sizeof(PHY_VARS_NR_UE)); memset((void*)UE,0,sizeof(PHY_VARS_NR_UE)); PHY_vars_UE_g = malloc(2*sizeof(PHY_VARS_NR_UE**)); PHY_vars_UE_g[0] = malloc(2*sizeof(PHY_VARS_NR_UE*)); PHY_vars_UE_g[0][0] = UE; memcpy(&UE->frame_parms,frame_parms,sizeof(NR_DL_FRAME_PARMS)); - if (init_nr_ue_signal(UE, 1, 0) != 0) - { + UE->nrUE_config.prach_config.num_prach_fd_occasions_list = (fapi_nr_num_prach_fd_occasions_t *) malloc(num_prach_fd_occasions*sizeof(fapi_nr_num_prach_fd_occasions_t)); + + if (init_nr_ue_signal(UE, 1, 0) != 0){ printf("Error at UE NR initialisation\n"); exit(-1); } - txdata = UE->common_vars.txdata; - printf("txdata %p\n",&txdata[0][subframe*frame_parms->samples_per_subframe]); + ue_prach_pdu = &UE->prach_vars[0]->prach_pdu; + ue_prach_config = &UE->nrUE_config.prach_config; + UE->prach_resources[0] = &prach_resources; + txdata = UE->common_vars.txdata; - double fs,bw; + UE->prach_vars[0]->amp = AMP; + ue_prach_pdu->root_seq_id = rootSequenceIndex; + ue_prach_pdu->num_cs = get_NCS(NCS_config, format0, restrictedSetConfig); + ue_prach_pdu->restricted_set = restrictedSetConfig; + ue_prach_pdu->freq_msg1 = msg1_frequencystart; + ue_prach_pdu->prach_format = prach_format; + ue_prach_config->prach_sub_c_spacing = mu; + ue_prach_config->prach_sequence_length = prach_sequence_length; + ue_prach_config->restricted_set_config = restrictedSetConfig; + ue_prach_config->num_prach_fd_occasions_list[fd_occasion].num_root_sequences = num_root_sequences; + ue_prach_config->num_prach_fd_occasions_list[fd_occasion].prach_root_sequence_index = rootSequenceIndex; + ue_prach_config->num_prach_fd_occasions_list[fd_occasion].k1 = msg1_frequencystart; + + if (preamble_tx == 99) + preamble_tx = (uint16_t)(taus()&0x3f); + + if (n_frames == 1) + printf("raPreamble %d\n",preamble_tx); + + UE->prach_resources[0]->ra_PreambleIndex = preamble_tx; + + // Configure channel + bw = N_RB_UL*(180e3)*(1 << frame_parms->numerology_index); + AssertFatal(bw<=122.88e6,"Illegal channel bandwidth %f (mu %d,N_RB_UL %d)\n", bw, frame_parms->numerology_index, N_RB_UL); + + if (bw <= 30.72e6) + fs = 30.72e6; + else if (bw <= 61.44e6) + fs = 61.44e6; + else if (bw <= 122.88e6) + fs = 122.88e6; - bw = N_RB_UL*(180e3)*(1<frame_parms.numerology_index); - AssertFatal(bw<=122.88e6,"Illegal channel bandwidth %f (mu %d,N_RB_UL %d)\n",gNB->frame_parms.numerology_index,N_RB_UL); - if (bw <= 30.72e6) fs = 30.72e6; - else if (bw <= 61.44e6) fs = 61.44e6; - else if (bw <= 122.88e6) fs = 122.88e6; LOG_I(PHY,"Running with bandwidth %f Hz, fs %f samp/s, FRAME_LENGTH_COMPLEX_SAMPLES %d\n",bw,fs,FRAME_LENGTH_COMPLEX_SAMPLES); - UE2gNB = new_channel_desc_scm(UE->frame_parms.nb_antennas_tx, gNB->frame_parms.nb_antennas_rx, channel_model, - fs, - bw, + fs, + bw, 0.0, delay, 0); @@ -486,82 +542,80 @@ int main(int argc, char **argv) bzero(r_im[i],FRAME_LENGTH_COMPLEX_SAMPLES*sizeof(double)); } - UE->frame_parms.prach_config_common.rootSequenceIndex=rootSequenceIndex; - UE->frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex=98; - UE->frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig=NCS_config; - UE->frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag=hs_flag; - UE->frame_parms.prach_config_common.prach_ConfigInfo.restrictedSetConfig=0; - UE->frame_parms.prach_config_common.prach_ConfigInfo.msg1_frequencystart=0; + // compute PRACH sequence + compute_nr_prach_seq(prach_config->prach_sequence_length.value, + prach_config->num_prach_fd_occasions_list[fd_occasion].num_root_sequences.value, + prach_config->num_prach_fd_occasions_list[fd_occasion].prach_root_sequence_index.value, + gNB->X_u); - - gNB->frame_parms.prach_config_common.rootSequenceIndex=rootSequenceIndex; - gNB->frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex=98; - gNB->frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig=NCS_config; - gNB->frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag=hs_flag; - gNB->frame_parms.prach_config_common.prach_ConfigInfo.restrictedSetConfig=0; - gNB->frame_parms.prach_config_common.prach_ConfigInfo.msg1_frequencystart=0; - - gNB->proc.slot_rx = subframe<<1; - - gNB->common_vars.rxdata = ru->common.rxdata; - - - compute_nr_prach_seq(&gNB->gNB_config,0,gNB->X_u); - - compute_nr_prach_seq(&gNB->gNB_config,0,UE->X_u); - - - - UE->prach_vars[0]->amp = AMP; - - UE->prach_resources[0] = &prach_resources; - - if (preamble_tx == 99) - preamble_tx = (uint16_t)(taus()&0x3f); - - if (n_frames == 1) - printf("raPreamble %d\n",preamble_tx); - - UE->prach_resources[0]->ra_PreambleIndex = preamble_tx; - UE->prach_resources[0]->ra_TDD_map_index = 0; + compute_nr_prach_seq(ue_prach_config->prach_sequence_length, + ue_prach_config->num_prach_fd_occasions_list[fd_occasion].num_root_sequences, + ue_prach_config->num_prach_fd_occasions_list[fd_occasion].prach_root_sequence_index, + UE->X_u); /*tx_lev = generate_nr_prach(UE, 0, //gNB_id, subframe); */ //commented for testing purpose UE_nr_rxtx_proc_t proc={0}; - proc.frame_tx=0;proc.nr_tti_tx=subframe; + proc.frame_tx = frame; + proc.nr_tti_tx = subframe; nr_ue_prach_procedures(UE,&proc,0,0); /* tx_lev_dB not used later, no need to set */ //tx_lev_dB = (unsigned int) dB_fixed(tx_lev); - LOG_M("txsig0.m","txs0", &txdata[0][subframe*frame_parms->samples_per_subframe],frame_parms->samples_per_subframe,1,1); - //LOG_M("txsig1.m","txs1", txdata[1],FRAME_LENGTH_COMPLEX_SAMPLES,1,1); + if (mu == 0) + samp_count = frame_parms->samples_per_subframe; + else + samp_count = (subframe%(frame_parms->slots_per_subframe/2)) ? frame_parms->samples_per_slotN0 : frame_parms->samples_per_slot0; + + prach_start = subframe*samp_count - UE->N_TA_offset; + + #ifdef NR_PRACH_DEBUG + LOG_M("txsig0.m", "txs0", &txdata[0][prach_start], samp_count, 1, 1); + //LOG_M("txsig1.m","txs1", txdata[1],FRAME_LENGTH_COMPLEX_SAMPLES,1,1); + #endif // multipath channel - // dump_nr_prach_config(&gNB->frame_parms,subframe); + // dump_nr_prach_config(&gNB->frame_parms,subframe); - for (i=0; isamples_per_slot<<1; i++) { + for (i = 0; i < samp_count<<1; i++) { for (aa=0; aa<1; aa++) { if (awgn_flag == 0) { - s_re[aa][i] = ((double)(((short *)&txdata[aa][subframe*frame_parms->samples_per_subframe]))[(i<<1)]); - s_im[aa][i] = ((double)(((short *)&txdata[aa][subframe*frame_parms->samples_per_subframe]))[(i<<1)+1]); + s_re[aa][i] = ((double)(((short *)&txdata[aa][prach_start]))[(i<<1)]); + s_im[aa][i] = ((double)(((short *)&txdata[aa][prach_start]))[(i<<1)+1]); } else { for (aarx=0; aarxframe_parms.nb_antennas_rx; aarx++) { if (aa==0) { - r_re[aarx][i] = ((double)(((short *)&txdata[aa][subframe*frame_parms->samples_per_subframe]))[(i<<1)]); - r_im[aarx][i] = ((double)(((short *)&txdata[aa][subframe*frame_parms->samples_per_subframe]))[(i<<1)+1]); + r_re[aarx][i] = ((double)(((short *)&txdata[aa][prach_start]))[(i<<1)]); + r_im[aarx][i] = ((double)(((short *)&txdata[aa][prach_start]))[(i<<1)+1]); } else { - r_re[aarx][i] += ((double)(((short *)&txdata[aa][subframe*frame_parms->samples_per_subframe]))[(i<<1)]); - r_im[aarx][i] += ((double)(((short *)&txdata[aa][subframe*frame_parms->samples_per_subframe]))[(i<<1)+1]); + r_re[aarx][i] += ((double)(((short *)&txdata[aa][prach_start]))[(i<<1)]); + r_im[aarx][i] += ((double)(((short *)&txdata[aa][prach_start]))[(i<<1)+1]); } } } } } + if (snr1set == 0) { + if (n_frames == 1) + snr1 = snr0 + .1; + else + snr1 = snr0 + 5.0; + } + printf("SNR0 %f, SNR1 %f\n", snr0, snr1); + + if (ue_speed1set == 0) { + if (n_frames == 1) + ue_speed1 = ue_speed0 + 10; + else + ue_speed1 = ue_speed0 + 50; + } + + rx_prach_start = subframe*frame_parms->get_samples_per_slot(subframe,frame_parms); for (SNR=snr0; SNRsamples_per_slot<<1,0); + multipath_tv_channel(UE2gNB, s_re, s_im, r_re, r_im, frame_parms->samples_per_tti<<1, 0); } if (n_frames==1) { @@ -594,63 +648,48 @@ int main(int argc, char **argv) 10*log10(tx_lev)); } - for (i=0; isamples_per_subframe; i++) { - for (aa=0; aaframe_parms.nb_antennas_rx; aa++) { - - ((short*) &gNB->common_vars.rxdata[aa][subframe*(frame_parms->samples_per_subframe)])[2*i] = (short) (.167*(r_re[aa][i] +sqrt(sigma2/2)*gaussdouble(0.0,1.0))); - ((short*) &gNB->common_vars.rxdata[aa][subframe*(frame_parms->samples_per_subframe)])[2*i+1] = (short) (.167*(r_im[aa][i] + (iqim*r_re[aa][i]) + sqrt(sigma2/2)*gaussdouble(0.0,1.0))); + for (i = 0; i< frame_parms->get_samples_per_slot(subframe,frame_parms); i++) { + for (aa = 0; aa < frame_parms->nb_antennas_rx; aa++) { + ((short*) &gNB->common_vars.rxdata[aa][rx_prach_start])[2*i] = (short) (.167*(r_re[aa][i] +sqrt(sigma2/2)*gaussdouble(0.0,1.0))); + ((short*) &gNB->common_vars.rxdata[aa][rx_prach_start])[2*i+1] = (short) (.167*(r_im[aa][i] + (iqim*r_re[aa][i]) + sqrt(sigma2/2)*gaussdouble(0.0,1.0))); } } - uint16_t preamble_rx; - rx_nr_prach_ru(ru, - 1, - 0, - 0, - 0, - subframe<<1); - gNB->prach_vars.rxsigF = ru->prach_rxsigF; + rx_nr_prach_ru(ru, prach_format, numRA, prachStartSymbol, frame, subframe); - nfapi_nr_prach_pdu_t prach_pdu; - prach_pdu.num_cs = 34; - prach_pdu.prach_format = 1; // A2 + gNB->prach_vars.rxsigF = ru->prach_rxsigF; - rx_nr_prach(gNB, - &prach_pdu, - 0, - subframe<<1, - &preamble_rx, - &preamble_energy, - &preamble_delay); - if (preamble_rx!=preamble_tx) + rx_nr_prach(gNB, prach_pdu, frame, subframe, &preamble_rx, &preamble_energy, &preamble_delay); + + printf(" preamble_energy %d preamble_rx %d preamble_tx %d \n", preamble_energy, preamble_rx, preamble_tx); + + if (preamble_rx != preamble_tx) prach_errors++; - else { + else delay_avg += (double)preamble_delay; - } + + N_ZC = (prach_sequence_length) ? 139 : 839; if (n_frames==1) { - printf("preamble %d (tx %d) : energy %d, delay %d\n",preamble_rx,preamble_tx,preamble_energy,preamble_delay); - - - LOG_M("prach0.m","prach0", &txdata[0][subframe*frame_parms->samples_per_slot<<1],frame_parms->samples_per_slot<<1,1,1); - LOG_M("prachF0.m","prachF0", &gNB->prach_vars.prachF[0],1024,1,1); - LOG_M("rxsig0.m","rxs0", - &gNB->common_vars.rxdata[0][subframe*frame_parms->samples_per_subframe], - frame_parms->samples_per_subframe,1,1); - LOG_M("rxsigF0.m","rxsF0", gNB->prach_vars.rxsigF[0],839*4,1,1); - LOG_M("prach_preamble.m","prachp",&gNB->X_u[0],839,1,1); + printf("preamble %d (tx %d) : energy %d, delay %d\n",preamble_rx,preamble_tx,preamble_energy,preamble_delay); + #ifdef NR_PRACH_DEBUG + LOG_M("prach0.m","prach0", &txdata[0][prach_start], samp_count, 1, 1); + LOG_M("prachF0.m","prachF0", &gNB->prach_vars.prachF[0], N_ZC, 1, 1); + LOG_M("rxsig0.m","rxs0", &gNB->common_vars.rxdata[0][rx_prach_start], frame_parms->samples_per_subframe, 1, 1); + //LOG_M("ru_rxsig0.m","rxs0", &ru->common.rxdata[0][rx_prach_start], frame_parms->samples_per_subframe, 1, 1); + LOG_M("rxsigF0.m","rxsF0", gNB->prach_vars.rxsigF[0], N_ZC, 1, 1); + LOG_M("prach_preamble.m","prachp", &gNB->X_u[0], N_ZC, 1, 1); + LOG_M("ue_prach_preamble.m","prachp", &UE->X_u[0], N_ZC, 1, 1); + #endif } } - - printf("SNR %f dB, UE Speed %f km/h: errors %d/%d (delay %f)\n",SNR,ue_speed,prach_errors,n_frames,delay_avg/(double)(n_frames-prach_errors)); + printf("SNR %f dB, UE Speed %f km/h: errors %d/%d (delay %f)\n", SNR, ue_speed, prach_errors, n_frames, delay_avg/(double)(n_frames-prach_errors)); //printf("(%f,%f)\n",ue_speed,(double)prach_errors/(double)n_frames); } // UE Speed loop - //printf("SNR %f dB, UE Speed %f km/h: errors %d/%d (delay %f)\n",SNR,ue_speed,prach_errors,n_frames,delay_avg/(double)(n_frames-prach_errors)); // printf("(%f,%f)\n",SNR,(double)prach_errors/(double)n_frames); } //SNR loop - for (i=0; i<2; i++) { free(s_re[i]); free(s_im[i]); @@ -663,17 +702,5 @@ int main(int argc, char **argv) free(r_re); free(r_im); - return(0); - } - - - -/* - for (i=1;i<4;i++) - memcpy((void *)&PHY_vars->tx_vars[0].TX_DMA_BUFFER[i*12*OFDM_SYMBOL_SIZE_COMPLEX_SAMPLES_NO_PREFIX*2], - (void *)&PHY_vars->tx_vars[0].TX_DMA_BUFFER[0], - 12*OFDM_SYMBOL_SIZE_SAMPLES_NO_PREFIX*2); -*/ - From cf47f059eb0b47aa13fc28e33070e0245817338e Mon Sep 17 00:00:00 2001 From: cig Date: Thu, 2 Apr 2020 14:37:32 +0200 Subject: [PATCH 131/553] Restored preamble index configuration in PRACH UE --- openair1/PHY/NR_UE_TRANSPORT/nr_prach.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c index 72d21600f7..9f3b9c6444 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c @@ -95,7 +95,7 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t slot){ n_ra_prb = prach_pdu->freq_msg1; NCS = prach_pdu->num_cs; prach_fmt_id = prach_pdu->prach_format; - preamble_index = 0; //prach_resources->ra_PreambleIndex // temporary hardcoded + preamble_index = prach_resources->ra_PreambleIndex; fd_occasion = 0; prach_len = 0; dftlen = 0; From 0366be797f936e89c767ff3947252a3824b6b7e5 Mon Sep 17 00:00:00 2001 From: cig Date: Thu, 2 Apr 2020 14:38:33 +0200 Subject: [PATCH 132/553] Prach_start adjustment for both HW and simulation --- openair1/PHY/NR_UE_TRANSPORT/nr_prach.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c index 9f3b9c6444..e7d930b34a 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c @@ -118,16 +118,16 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t slot){ #if defined (OAI_USRP) prach_start = (ue->rx_offset + slot*samp_count - ue->hw_timing_advance - ue->N_TA_offset); - - if (prach_start<0) - prach_start += (fp->samples_per_subframe*NR_NUMBER_OF_SUBFRAMES_PER_FRAME); - - if (prach_start >= (fp->samples_per_subframe*NR_NUMBER_OF_SUBFRAMES_PER_FRAME)) - prach_start -= (fp->samples_per_subframe*NR_NUMBER_OF_SUBFRAMES_PER_FRAME); #else //normal case (simulation) prach_start = slot*samp_count - ue->N_TA_offset; #endif + if (prach_start<0) + prach_start += (fp->samples_per_subframe*NR_NUMBER_OF_SUBFRAMES_PER_FRAME); + + if (prach_start >= (fp->samples_per_subframe*NR_NUMBER_OF_SUBFRAMES_PER_FRAME)) + prach_start -= (fp->samples_per_subframe*NR_NUMBER_OF_SUBFRAMES_PER_FRAME); + // First compute physical root sequence /************************************************************************ * 4G and NR NCS tables are slightly different and depend on prach format From 6e404180f7e3f7e2252a6bbcf6daf1d670040ecf Mon Sep 17 00:00:00 2001 From: cig Date: Thu, 2 Apr 2020 17:24:33 +0200 Subject: [PATCH 133/553] Fixed compilation warnings --- executables/nr-uesoftmodem.c | 2 +- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/executables/nr-uesoftmodem.c b/executables/nr-uesoftmodem.c index b995a85c48..89f2ee8509 100644 --- a/executables/nr-uesoftmodem.c +++ b/executables/nr-uesoftmodem.c @@ -801,7 +801,7 @@ int main( int argc, char **argv ) { } if (UE[CC_id]->frame_parms.threequarter_fs == 1) factor = factor*.75; UE[CC_id]->N_TA_offset = (int)(N_TA_offset * factor); - LOG_I(PHY,"UE %d Setting N_TA_offset to %d samples (factor %f, UL Freq %d, N_RB %d)\n", UE[CC_id]->Mod_id, UE[CC_id]->N_TA_offset, factor, UE[CC_id]->frame_parms.ul_CarrierFreq, N_RB); + LOG_I(PHY,"UE %d Setting N_TA_offset to %d samples (factor %f, UL Freq %lu, N_RB %d)\n", UE[CC_id]->Mod_id, UE[CC_id]->N_TA_offset, factor, UE[CC_id]->frame_parms.ul_CarrierFreq, N_RB); } } diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index feda6c6d9b..16dfb40134 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -4495,7 +4495,7 @@ uint8_t nr_is_ri_TXOp(PHY_VARS_NR_UE *ue, // - power control as per 38.213 ch 7.4 void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t gNB_id, runmode_t runmode) { - int frame_tx = proc->frame_tx, nr_tti_tx = proc->nr_tti_tx, prach_power, tx_amp; + int frame_tx = proc->frame_tx, nr_tti_tx = proc->nr_tti_tx, prach_power; // tx_amp uint16_t /*preamble_tx = 50,*/ pathloss; uint8_t mod_id = ue->Mod_id; UE_MODE_t UE_mode = get_nrUE_mode(mod_id, ue->CC_id, gNB_id); From fbf74bc395f7bc378171326eff8858752f25c0d7 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Thu, 2 Apr 2020 18:48:02 +0200 Subject: [PATCH 134/553] setting type 1 dl freq resource allocation in rrc --- openair2/RRC/NR/rrc_gNB_reconfig.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openair2/RRC/NR/rrc_gNB_reconfig.c b/openair2/RRC/NR/rrc_gNB_reconfig.c index 1df17a19aa..a695018c83 100644 --- a/openair2/RRC/NR/rrc_gNB_reconfig.c +++ b/openair2/RRC/NR/rrc_gNB_reconfig.c @@ -354,7 +354,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType0; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; @@ -747,7 +747,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType0; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1; bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; @@ -773,7 +773,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType0; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1; bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; From 448cae257dd2618490fb75fc11b98f50d1bb4d30 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 3 Apr 2020 13:41:23 +0200 Subject: [PATCH 135/553] Revert "ENDC path switch S1-U: Bugfixes at gNB side" This reverts commit 1462f0e659122afc68bdb320044a7f96fd0d62d2. --- .../NR_ESTIMATION/nr_ul_channel_estimation.c | 14 --- openair1/PHY/NR_TRANSPORT/nr_dci.c | 2 - openair1/PHY/NR_TRANSPORT/nr_prach.c | 39 +-------- openair1/PHY/NR_TRANSPORT/nr_prach_common.c | 2 +- openair1/PHY/NR_TRANSPORT/nr_ulsch.c | 1 + .../PHY/NR_TRANSPORT/nr_ulsch_demodulation.c | 25 ------ openair1/SCHED_NR/nr_prach_procedures.c | 4 - openair1/SCHED_NR/nr_ru_procedures.c | 12 --- openair2/GNB_APP/gnb_config.c | 1 - openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 2 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 6 +- .../LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c | 2 +- .../LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c | 4 - openair2/RRC/NR/rrc_gNB_reconfig.c | 87 +++++-------------- 14 files changed, 31 insertions(+), 170 deletions(-) diff --git a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c index 58b6b15b79..94da06dd8b 100644 --- a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c +++ b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c @@ -36,7 +36,6 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, unsigned char symbol, unsigned short bwp_start_subcarrier, nfapi_nr_pusch_pdu_t *pusch_pdu) { -printf("nr_pusch_channel_estimation Ns %d p %d symbol %d\n", Ns, p, symbol); int pilot[3280] __attribute__((aligned(16))); unsigned char aarx; @@ -492,18 +491,5 @@ printf("nr_pusch_channel_estimation Ns %d p %d symbol %d\n", Ns, p, symbol); fclose(debug_ch_est); #endif -{ - char name[128]; - FILE *f; - sprintf(name, "ch_estimate.%d.%d.raw", gNB->proc.frame_rx, symbol); - f = fopen(name, "w"); if (f == NULL) exit(1); - fwrite(&ul_ch_estimates[0][symbol_offset], nb_rb_pusch*12*4, 1, f); - fclose(f); - sprintf(name, "ch_estimate_time.%d.%d.raw", gNB->proc.frame_rx, symbol); - f = fopen(name, "w"); if (f == NULL) exit(1); - fwrite(ul_ch_estimates_time[0], 1536*4, 1, f); - fclose(f); -} - return(0); } diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.c b/openair1/PHY/NR_TRANSPORT/nr_dci.c index 75493dfd9c..812c49d6f6 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.c @@ -238,8 +238,6 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, pdcch_pdu_rel15->dci_pdu.AggregationLevel[d], 0,NULL); polar_encoder_fast((uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[d], encoder_output, n_RNTI,1,currentPtr); - printf("DCI PDU: [0]->0x%lx \t [1]->0x%lx %d bits aggreg %d\n", - ((uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[d])[0], ((uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[d])[1], pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d], pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]); #ifdef DEBUG_CHANNEL_CODING printf("polar rnti %x,length %d, L %d\n",n_RNTI, pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d],pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]); printf("DCI PDU: [0]->0x%lx \t [1]->0x%lx\n", diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index b7dd94325a..2f0ea46ecd 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -82,8 +82,6 @@ void nr_fill_prach(PHY_VARS_gNB *gNB, void init_prach_ru_list(RU_t *ru) { -//g_log->debug_mask |= PRACH; - AssertFatal(ru!=NULL,"ruis null\n"); for (int i=0; iprach_list[i].frame=-1; pthread_mutex_init(&ru->prach_list_mutex,NULL); @@ -384,17 +382,6 @@ void rx_nr_prach_ru(RU_t *ru, for (int i=6;i<12;i++) dft1536(prach2+(3072*i),rxsigF[aa]+(3072*i),1); reps+=6; } -if (0){ - char name[256]; - sprintf(name, "time.%d.%d.raw", frame, slot); - FILE *f = fopen(name, "w"); if (f == NULL) exit(1); - fwrite(prach2-1536*4, 1536*4*4+1536*4, 1, f); - fclose(f); - sprintf(name, "freq.%d.%d.raw", frame, slot); - f = fopen(name, "w"); if (f == NULL) exit(1); - fwrite(rxsigF[aa], 1536*4*4, 1, f); - fclose(f); -} }// mu==1 else if (mu==2) AssertFatal(1==0,"Shouldn't get here\n"); else if (mu==3) AssertFatal(1==0,"Shouldn't get here\n"); @@ -528,13 +515,6 @@ if (0){ } memcpy((void*)rxsigF2,(void *)rxsigF_tmp,N_ZC<<2); -if (0){ - char name[256]; - sprintf(name, "sum.%d.%d.raw", frame, slot); - FILE *f = fopen(name, "w"); if (f == NULL) exit(1); - fwrite(rxsigF_tmp, N_ZC*4, 1, f); - fclose(f); -} } } @@ -557,7 +537,7 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, uint16_t rootSequenceIndex; int numrootSequenceIndex; uint8_t restricted_set; - uint8_t n_ra_prb = 0; + uint8_t n_ra_prb; int16_t *prachF=NULL; int nb_rx; @@ -640,19 +620,7 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, *max_preamble_delay=0; *max_preamble=0; -if (0){ - char name[256]; - sprintf(name, "sum2.%d.%d.raw", frame, subframe); - FILE *f = fopen(name, "w"); if (f == NULL) exit(1); - fwrite(rxsigF[0], N_ZC*4, 1, f); - fclose(f); -} - for (preamble_index=0 ; preamble_index<64 ; preamble_index++) { -{ -int en = dB_fixed(signal_energy((int32_t*)&rxsigF[0][0],(N_ZC==839) ? 840: 140)); -if (en>40 && preamble_index==0) LOG_I(PHY,"%d.%d: try preamble %d en %d\n",frame,subframe,preamble_index, en); -} if (LOG_DEBUGFLAG(PRACH)){ int en = dB_fixed(signal_energy((int32_t*)&rxsigF[0][0],(N_ZC==839) ? 840: 140)); @@ -733,9 +701,8 @@ if (en>40 && preamble_index==0) LOG_I(PHY,"%d.%d: try preamble %d en %d\n",frame } // Compute DFT of RX signal (conjugate input, results in conjugate output) for each new rootSequenceIndex - int en = dB_fixed(signal_energy((int32_t*)&rxsigF[0][0],140)); if (LOG_DEBUGFLAG(PRACH)) { - //int en = dB_fixed(signal_energy((int32_t*)&rxsigF[0][0],840)); + int en = dB_fixed(signal_energy((int32_t*)&rxsigF[0][0],840)); if (en>60) LOG_I(PHY,"frame %d, subframe %d : preamble index %d, NCS %d, N_ZC/NCS %d: offset %d, preamble shift %d , en %d)\n", frame,subframe,preamble_index,NCS,N_ZC/NCS,preamble_offset,preamble_shift,en); } @@ -798,8 +765,6 @@ if (en>40 && preamble_index==0) LOG_I(PHY,"%d.%d: try preamble %d en %d\n",frame for (i=0; i60) LOG_I(PHY, "preamble_index %d NCS2 %d i %d lev %d levdB %d preamble_shift2 %d\n", preamble_index, NCS2, i, lev, levdB, preamble_shift2); if (levdB>*max_preamble_energy) { *max_preamble_energy = levdB; *max_preamble_delay = i; // Note: This has to be normalized to the 30.72 Ms/s sampling rate diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c index a20f364fa2..8373e775bd 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c @@ -94,6 +94,7 @@ void nr_fill_du(uint16_t N_ZC,uint16_t *prach_root_sequence_map) nr_du[u] = ((p<(N_ZC>>1)) ? p : (N_ZC-p)); } + } void compute_nr_prach_seq(uint8_t short_sequence, @@ -148,7 +149,6 @@ void compute_nr_prach_seq(uint8_t short_sequence, for (k=0; k> 16) & 65535), (((k*(1+(inv_u*k)))%N_ZC)*70)%N_ZC); } } diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch.c index 8b35ca2e0f..3622e61b61 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch.c @@ -87,6 +87,7 @@ void nr_ulsch_unscrambling(int16_t* llr, uint8_t q, uint32_t Nid, uint32_t n_RNTI) { + uint8_t reset; uint32_t x1, x2, s=0; diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c index aefa4d4820..d304f26d02 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c @@ -1030,8 +1030,6 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, nfapi_nr_pusch_pdu_t *rel15_ul = &gNB->ulsch[UE_id][0]->harq_processes[harq_pid]->ulsch_pdu; uint8_t nodata_dmrs = 1; // FIXME to be properly configured from fapi -printf("nr_rx_pusch frame %d nr_tti_rx %d symbol %d rel15_ul->start_symbol_index %d rel15_ul->nr_of_symbols %d\n", frame, nr_tti_rx, symbol, rel15_ul->start_symbol_index, rel15_ul->nr_of_symbols); - dmrs_symbol_flag = 0; ptrs_symbol_flag = 0; gNB->pusch_vars[UE_id]->ptrs_sc_per_ofdm_symbol = 0; @@ -1107,15 +1105,6 @@ printf("nr_rx_pusch frame %d nr_tti_rx %d symbol %d rel15_ul->start_symbol_index //--------------------- RBs extraction --------------------- //---------------------------------------------------------- -{ - char name[128]; - FILE *f; - sprintf(name, "rxdataF.%d.%d.raw", frame, symbol); - f = fopen(name, "w"); - fwrite(&gNB->common_vars.rxdataF[0][symbol * frame_parms->ofdm_symbol_size], frame_parms->ofdm_symbol_size*4, 1, f); - fclose(f); -} - if (nb_re_pusch > 0) { nr_ulsch_extract_rbs_single(gNB->common_vars.rxdataF, @@ -1166,20 +1155,6 @@ printf("nr_rx_pusch frame %d nr_tti_rx %d symbol %d rel15_ul->start_symbol_index rel15_ul->rb_size, gNB->pusch_vars[UE_id]->log2_maxh); -{ - char name[128]; - FILE *f; - sprintf(name, "rxdataF_ext.%d.%d.raw", frame, symbol); - f = fopen(name, "w"); - int nb_re_pusch = NR_NB_SC_PER_RB * rel15_ul->rb_size; - fwrite(&gNB->pusch_vars[UE_id]->rxdataF_ext[0][symbol * nb_re_pusch], nb_re_pusch*4, 1, f); - fclose(f); - sprintf(name, "rxdataF_comp.%d.%d.raw", frame, symbol); - f = fopen(name, "w"); - fwrite(&gNB->pusch_vars[UE_id]->rxdataF_comp[0][symbol * nb_re_pusch], nb_re_pusch*4, 1, f); - fclose(f); -} - #ifdef NR_SC_FDMA nr_idft(&((uint32_t*)gNB->pusch_vars[UE_id]->rxdataF_ext[0])[symbol * rel15_ul->rb_size * NR_NB_SC_PER_RB], nb_re_pusch); #endif diff --git a/openair1/SCHED_NR/nr_prach_procedures.c b/openair1/SCHED_NR/nr_prach_procedures.c index f7b5c6dfda..855da5ac8a 100644 --- a/openair1/SCHED_NR/nr_prach_procedures.c +++ b/openair1/SCHED_NR/nr_prach_procedures.c @@ -77,8 +77,6 @@ void L1_nr_prach_procedures(PHY_VARS_gNB *gNB,int frame,int slot, } } -//ru = gNB->RU_list[0]; -//rx_nr_prach_ru(ru, prach_pdu, frame, slot); rx_nr_prach(gNB, prach_pdu, @@ -88,8 +86,6 @@ void L1_nr_prach_procedures(PHY_VARS_gNB *gNB,int frame,int slot, &max_preamble_energy[0], &max_preamble_delay[0] ); -if (max_preamble_energy[0] > 200) -printf("ra %d.%d preamble %d energy %d delay %d gNB->measurements.prach_I0+100 %d\n", frame, slot, max_preamble[0], max_preamble_energy[0], max_preamble_delay[0], gNB->measurements.prach_I0+100); LOG_D(PHY,"[RAPROC] Frame %d, slot %d : Most likely preamble %d, energy %d dB delay %d (prach_energy counter %d)\n", frame,slot, diff --git a/openair1/SCHED_NR/nr_ru_procedures.c b/openair1/SCHED_NR/nr_ru_procedures.c index afc6b864fd..560f47059a 100644 --- a/openair1/SCHED_NR/nr_ru_procedures.c +++ b/openair1/SCHED_NR/nr_ru_procedures.c @@ -512,16 +512,6 @@ void nr_fep0(RU_t *ru, int first_half) { VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPRX+proc->tti_rx, 1); -if(0){ -//printf("nr_fep0 proc->tti_rx %d f %dd\n", proc->tti_rx, proc->frame_rx); - char name[128]; - FILE *f; - sprintf(name, "rxdata.%d.%d.raw", proc->frame_rx, proc->tti_rx); - f = fopen(name, "w"); if (f == NULL) exit(1); - fwrite(&ru->common.rxdata[0][proc->tti_rx * 23040], 23040*4, 1, f); - fclose(f); -} - // remove_7_5_kHz(ru,(slot&1)+(proc->tti_rx<<1)); for (l = start_symbol; l < end_symbol; l++) { for (aa = 0; aa < fp->nb_antennas_rx; aa++) { @@ -660,8 +650,6 @@ void nr_fep_full(RU_t *ru, int slot) { // remove_7_5_kHz(ru,proc->tti_rx<<1); // remove_7_5_kHz(ru,1+(proc->tti_rx<<1)); -printf("nr_fep_full proc->tti_rx %d\n", proc->tti_rx); - for (l = 0; l < fp->symbols_per_slot; l++) { for (aa = 0; aa < fp->nb_antennas_rx; aa++) { nr_slot_fep_ul(fp, diff --git a/openair2/GNB_APP/gnb_config.c b/openair2/GNB_APP/gnb_config.c index 88df3eadad..5b7ef17d20 100644 --- a/openair2/GNB_APP/gnb_config.c +++ b/openair2/GNB_APP/gnb_config.c @@ -237,7 +237,6 @@ void fix_scc(NR_ServingCellConfigCommon_t *scc,uint64_t ssbmap) { scc->ssb_PositionsInBurst->choice.mediumBitmap.buf[0] = 0; for (int i=0; i<8; i++) scc->ssb_PositionsInBurst->choice.mediumBitmap.buf[0] |= (((ssbmap>>(7-i))&0x01)<ssb_PositionsInBurst->choice.mediumBitmap.buf[0] = 0x80; //ssbmap; }else { scc->ssb_PositionsInBurst->choice.longBitmap.size = 8; scc->ssb_PositionsInBurst->choice.longBitmap.bits_unused = 0; diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index f244c9392c..5a93d2abbf 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -1434,7 +1434,7 @@ void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, uint8_t N_sh_symb = pdsch_rel15->NrOfSymbols; uint8_t Imcs = pdsch_rel15->mcsIndex[0]; uint16_t N_RE_prime = NR_NB_SC_PER_RB*N_sh_symb - N_PRB_DMRS - N_PRB_oh; - LOG_I(MAC, "N_RE_prime %d for %d symbols %d DMRS per PRB and %d overhead\n", N_RE_prime, N_sh_symb, N_PRB_DMRS, N_PRB_oh); + LOG_D(MAC, "N_RE_prime %d for %d symbols %d DMRS per PRB and %d overhead\n", N_RE_prime, N_sh_symb, N_PRB_DMRS, N_PRB_oh); uint16_t R; uint32_t TBS=0; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index 08dcfe0b76..042e53e2dc 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -295,7 +295,7 @@ void nr_initiate_ra_proc(module_id_t module_idP, LOG_D(MAC, "%s() Msg2[%04d%d] SFN/SF:%04d%d\n", __FUNCTION__, ra->Msg2_frame, ra->Msg2_slot, frameP, slotP); do { - ra->rnti = 666; //(taus() % 65518) + 1; + ra->rnti = (taus() % 65518) + 1; loop++; } while (loop != 100 && !(find_nr_UE_id(module_idP, ra->rnti) == -1 && ra->rnti >= 1 && ra->rnti <= 65519)); @@ -679,7 +679,7 @@ void nr_generate_Msg2(module_id_t module_idP, dci_formats[0] = NR_DL_DCI_FORMAT_1_0; rnti_types[0] = NR_RNTI_RA; - LOG_I(MAC, "[RAPROC] DCI params: rnti %d, rnti_type %d, dci_format %d coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n", + LOG_D(MAC, "[RAPROC] DCI params: rnti %d, rnti_type %d, dci_format %d coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n", pdcch_pdu_rel15->dci_pdu.RNTI[0], rnti_types[0], dci_formats[0], @@ -812,8 +812,6 @@ void nr_fill_rar(uint8_t Mod_idP, ul_grant = csi_req | (tpc_command << 1) | (pusch_pdu->mcs_index << 4) | (ra->Msg3_tda_id << 8) | (f_alloc << 12) | (pusch_pdu->frequency_hopping << 26); -printf("ul grant 0x%x mcs %d f_alloc %d tpc %d\n", ul_grant, pusch_pdu->mcs_index, f_alloc, tpc_command); - rar->UL_GRANT_1 = (uint8_t) (ul_grant >> 24) & 0x07; rar->UL_GRANT_2 = (uint8_t) (ul_grant >> 16) & 0xff; rar->UL_GRANT_3 = (uint8_t) (ul_grant >> 8) & 0xff; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c index 0e8fb0aca2..5fa77c6ca7 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c @@ -82,7 +82,7 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ if (mib_sdu_length > 0) { - LOG_D(MAC, "Frame %d, slot %d: Adding BCH PDU in position %d (length %d)\n", frameP, slotP, dl_req->nPDUs, mib_sdu_length); + LOG_I(MAC, "Frame %d, slot %d: Adding BCH PDU in position %d (length %d)\n", frameP, slotP, dl_req->nPDUs, mib_sdu_length); if ((frameP & 1023) < 80){ LOG_I(MAC,"[gNB %d] Frame %d : MIB->BCH CC_id %d, Received %d bytes\n",module_idP, frameP, CC_id, mib_sdu_length); diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c b/openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c index 4dfb39280a..df23b64e07 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c +++ b/openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c @@ -28,8 +28,6 @@ #include "common/utils/nr/nr_common.h" #include -#include "LOG/log.h" - //Table 5.1.2.2-2 uint16_t Tbstable_nr[INDEX_MAX_TBS_TABLE] = {24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,208,224,240,256,272,288,304,320,336,352,368,384,408,432,456,480,504,528,552,576,608,640,672,704,736,768,808,848,888,928,984,1032,1064,1128,1160,1192,1224,1256,1288,1320,1352,1416,1480,1544,1608,1672,1736,1800,1864,1928,2024,2088,2152,2216,2280,2408,2472,2536,2600,2664,2728,2792,2856,2976,3104,3240,3368,3496,3624,3752,3824}; @@ -90,8 +88,6 @@ uint32_t nr_compute_tbs(uint16_t Qm, } //printf("Ninfo %d nbp_re %d nb_re %d Qm %d, R %d, tbs %d\n", Ninfo, nbp_re, nb_re, Qm, R, nr_tbs); - LOG_I(PHY, "Ninfo %d nbp_re %d nb_re %d Qm %d, R %d, tbs %d nb_symb_sch %d nb_dmrs_prb %d nb_rb_oh %d tb_scaling %d Nl %d\n", - Ninfo, nbp_re, nb_re, Qm, R, nr_tbs, nb_symb_sch, nb_dmrs_prb, nb_rb_oh, tb_scaling, Nl); return nr_tbs; } diff --git a/openair2/RRC/NR/rrc_gNB_reconfig.c b/openair2/RRC/NR/rrc_gNB_reconfig.c index c6642bdc6d..03c5e6ec95 100644 --- a/openair2/RRC/NR/rrc_gNB_reconfig.c +++ b/openair2/RRC/NR/rrc_gNB_reconfig.c @@ -116,7 +116,6 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco tag->tag_Id = 0; tag->timeAlignmentTimer = NR_TimeAlignmentTimer_infinity; ASN_SEQUENCE_ADD(&secondaryCellGroup->mac_CellGroupConfig->tag_Config->tag_ToAddModList->list,tag); -#if 1 secondaryCellGroup->mac_CellGroupConfig->phr_Config = calloc(1,sizeof(*secondaryCellGroup->mac_CellGroupConfig->phr_Config)); secondaryCellGroup->mac_CellGroupConfig->phr_Config->present = NR_SetupRelease_PHR_Config_PR_setup; secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup = calloc(1,sizeof(*secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup)); @@ -127,7 +126,6 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup->dummy=false; secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup->phr_Type2OtherCell = false; secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup->phr_ModeOtherCG = NR_PHR_Config__phr_ModeOtherCG_real; -#endif secondaryCellGroup->mac_CellGroupConfig->skipUplinkTxDynamic=false; secondaryCellGroup->mac_CellGroupConfig->ext1 = NULL; @@ -152,7 +150,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco *secondaryCellGroup->spCellConfig->servCellIndex = servCellIndex; secondaryCellGroup->spCellConfig->reconfigurationWithSync=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->reconfigurationWithSync)); secondaryCellGroup->spCellConfig->reconfigurationWithSync->spCellConfigCommon=servingcellconfigcommon; - secondaryCellGroup->spCellConfig->reconfigurationWithSync->newUE_Identity=(get_softmodem_params()->phy_test==1) ? 0x1234 : 0x3456; //(taus()&0xffff); + secondaryCellGroup->spCellConfig->reconfigurationWithSync->newUE_Identity=(get_softmodem_params()->phy_test==1) ? 0x1234 : (taus()&0xffff); secondaryCellGroup->spCellConfig->reconfigurationWithSync->t304=NR_ReconfigurationWithSync__t304_ms2000; secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated = NULL; secondaryCellGroup->spCellConfig->reconfigurationWithSync->ext1 = NULL; @@ -211,11 +209,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition)); *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0; -secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList=NULL; - -#if 0 secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList)); NR_TCI_State_t*tci0=calloc(1,sizeof(*tci0)); @@ -377,7 +371,6 @@ secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pds tci15->qcl_Type1.referenceSignal.choice.ssb = 7; tci15->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci15); -#endif secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; @@ -406,8 +399,6 @@ secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pds secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->sps_Config = NULL; //calloc(1,sizeof(struct NR_SetupRelease_SPS_Config)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig = NULL; -#if 0 secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig)); secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->present = NR_SetupRelease_RadioLinkMonitoringConfig_PR_setup; @@ -418,10 +409,8 @@ secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pds *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = NR_RadioLinkMonitoringConfig__beamFailureInstanceMaxCount_n3; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer)); *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = NR_RadioLinkMonitoringConfig__beamFailureDetectionTimer_pbfd2; -#endif secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToReleaseList= NULL; -// secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList = NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList)); NR_BWP_Downlink_t *bwp=calloc(1,sizeof(*bwp)); @@ -431,7 +420,6 @@ secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pds memcpy((void*)&bwp->bwp_Common->genericParameters, &servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->genericParameters, sizeof(bwp->bwp_Common->genericParameters)); - bwp->bwp_Common->genericParameters.locationAndBandwidth=6407; //PRBalloc_to_locationandbandwidth(servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth,0); bwp->bwp_Common->genericParameters.locationAndBandwidth=PRBalloc_to_locationandbandwidth(servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth,0); @@ -485,7 +473,7 @@ secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pds ss->monitoringSymbolsWithinSlot->buf = calloc(1,2); // should be '1100 0000 0000 00'B (LSB first!), first two symols in slot, adjust if needed ss->monitoringSymbolsWithinSlot->buf[1] = 0; - ss->monitoringSymbolsWithinSlot->buf[0] = (1<<7); // | (1<<6); + ss->monitoringSymbolsWithinSlot->buf[0] = (1<<7) | (1<<6); ss->monitoringSymbolsWithinSlot->size = 2; ss->monitoringSymbolsWithinSlot->bits_unused = 2; ss->nrofCandidates = calloc(1,sizeof(*ss->nrofCandidates)); @@ -508,7 +496,6 @@ secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pds bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace)); *bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace=1; bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ext1=NULL; -//bwp->bwp_Common->pdcch_ConfigCommon=NULL; bwp->bwp_Common->pdsch_ConfigCommon=calloc(1,sizeof(*bwp->bwp_Common->pdsch_ConfigCommon)); bwp->bwp_Common->pdsch_ConfigCommon->present = NR_SetupRelease_PDSCH_ConfigCommon_PR_setup; @@ -554,7 +541,7 @@ secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pds ss2->monitoringSymbolsWithinSlot->buf = calloc(1,2); ss2->monitoringSymbolsWithinSlot->size = 2; ss2->monitoringSymbolsWithinSlot->bits_unused = 2; - ss2->monitoringSymbolsWithinSlot->buf[0]=0x80; //0xc0; + ss2->monitoringSymbolsWithinSlot->buf[0]=0xc0; ss2->monitoringSymbolsWithinSlot->buf[1]=0x0; ss2->nrofCandidates=calloc(1,sizeof(*ss2->nrofCandidates)); ss2->nrofCandidates->aggregationLevel1 = NR_SearchSpace__nrofCandidates__aggregationLevel1_n0; @@ -590,10 +577,7 @@ secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pds bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition)); *bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0; -bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList=NULL; -#if 0 bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList=calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList)); NR_TCI_State_t*tcid0=calloc(1,sizeof(*tcid0)); @@ -755,7 +739,6 @@ bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTyp tcid15->qcl_Type1.referenceSignal.choice.ssb = 7; tcid15->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid15); -#endif bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; @@ -810,8 +793,6 @@ bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTyp bwp->bwp_Dedicated->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL; bwp->bwp_Dedicated->sps_Config = NULL; //calloc(1,sizeof(struct NR_SetupRelease_SPS_Config)); - bwp->bwp_Dedicated->radioLinkMonitoringConfig = NULL; -#if 0 bwp->bwp_Dedicated->radioLinkMonitoringConfig = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig)); bwp->bwp_Dedicated->radioLinkMonitoringConfig->present = NR_SetupRelease_RadioLinkMonitoringConfig_PR_setup; @@ -822,17 +803,14 @@ bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTyp *bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = NR_RadioLinkMonitoringConfig__beamFailureInstanceMaxCount_n3; bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer)); *bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = NR_RadioLinkMonitoringConfig__beamFailureDetectionTimer_pbfd2; -#endif - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list,bwp); + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list,bwp); secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id)); - *secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id=1; //0; //1; + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id=1; secondaryCellGroup->spCellConfig->spCellConfigDedicated->bwp_InactivityTimer = NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->defaultDownlinkBWP_Id = NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->defaultDownlinkBWP_Id = calloc(1, sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->defaultDownlinkBWP_Id)); - *secondaryCellGroup->spCellConfig->spCellConfigDedicated->defaultDownlinkBWP_Id = 1; secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig)); NR_BWP_UplinkDedicated_t *initialUplinkBWP = calloc(1,sizeof(*initialUplinkBWP)); @@ -955,7 +933,6 @@ bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTyp ASN_SEQUENCE_ADD(&srs_Config->srs_ResourceToAddModList->list,srs_res0); secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToReleaseList = NULL; -// secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList = NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList)); NR_BWP_Uplink_t *ubwp = calloc(1,sizeof(*ubwp)); ubwp->bwp_Id=1; @@ -964,10 +941,8 @@ bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTyp memcpy((void*)&ubwp->bwp_Common->genericParameters, (void*)&servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->genericParameters, sizeof(servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->genericParameters)); - ubwp->bwp_Common->genericParameters.locationAndBandwidth=6407; //PRBalloc_to_locationandbandwidth(servingcellconfigcommon->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth,0); ubwp->bwp_Common->genericParameters.locationAndBandwidth=PRBalloc_to_locationandbandwidth(servingcellconfigcommon->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth,0); -servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig = 0; ubwp->bwp_Common->rach_ConfigCommon = servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon; ubwp->bwp_Common->pusch_ConfigCommon = servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon; ubwp->bwp_Common->pucch_ConfigCommon = servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon; @@ -1119,10 +1094,10 @@ servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon ubwp->bwp_Dedicated->beamFailureRecoveryConfig = NULL; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list,ubwp); + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list,ubwp); secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id)); - *secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id = 1; //0; //1; + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id = 1; secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig = NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->carrierSwitching = NULL; @@ -1130,14 +1105,10 @@ servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdcch_ServingCellConfig=NULL; -#if 0 secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig)); NR_PDSCH_ServingCellConfig_t *pdsch_servingcellconfig = calloc(1,sizeof(*pdsch_servingcellconfig)); secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->present = NR_SetupRelease_PDSCH_ServingCellConfig_PR_setup; secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup = pdsch_servingcellconfig; -#endif - NR_PDSCH_ServingCellConfig_t *pdsch_servingcellconfig = calloc(1,sizeof(*pdsch_servingcellconfig)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig=NULL; pdsch_servingcellconfig->codeBlockGroupTransmission = NULL; pdsch_servingcellconfig->xOverhead = NULL; pdsch_servingcellconfig->nrofHARQ_ProcessesForPDSCH = NULL; @@ -1147,13 +1118,12 @@ servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon *pdsch_servingcellconfig->ext1->maxMIMO_Layers = 2; pdsch_servingcellconfig->ext1->processingType2Enabled = NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig=NULL; - //secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig)); - //secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->present = NR_SetupRelease_CSI_MeasConfig_PR_setup; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->present = NR_SetupRelease_CSI_MeasConfig_PR_setup; NR_CSI_MeasConfig_t *csi_MeasConfig = calloc(1,sizeof(*csi_MeasConfig)); -// secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup = csi_MeasConfig; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup = csi_MeasConfig; csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList = calloc(1,sizeof(*csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList)); NR_NZP_CSI_RS_Resource_t *nzpres0 = calloc(1,sizeof(*nzpres0)); @@ -1693,7 +1663,7 @@ servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon imres0->csi_IM_ResourceElementPattern->choice.pattern1->symbolLocation_p1=7; imres0->freqBand=calloc(1,sizeof(*imres0->freqBand)); imres0->freqBand->startingRB=0; - imres0->freqBand->nrofRBs=106; + imres0->freqBand->nrofRBs=276; imres0->periodicityAndOffset=calloc(1,sizeof(*imres0->periodicityAndOffset)); imres0->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots320; imres0->periodicityAndOffset->choice.slots320 = 2; @@ -1767,7 +1737,7 @@ servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon ASN_SEQUENCE_ADD(&csires11->csi_RS_ResourceSetList.choice.csi_IM_ResourceSetList->list,csires110); csires11->bwp_Id = 1; csires11->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires11); + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires11); NR_CSI_ResourceConfig_t *csires10 = calloc(1,sizeof(*csires10)); csires10->csi_ResourceConfigId=10; @@ -1780,7 +1750,7 @@ servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon ASN_SEQUENCE_ADD(&csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires100); csires10->bwp_Id = 1; csires10->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires10); + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires10); NR_CSI_ResourceConfig_t *csires2 = calloc(1,sizeof(*csires2)); csires2->csi_ResourceConfigId=2; @@ -1793,7 +1763,7 @@ servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon ASN_SEQUENCE_ADD(&csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires20); csires2->bwp_Id = 1; csires2->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires2); + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires2); NR_CSI_ResourceConfig_t *csires3 = calloc(1,sizeof(*csires3)); csires3->csi_ResourceConfigId=3; @@ -1806,7 +1776,7 @@ servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon ASN_SEQUENCE_ADD(&csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires30); csires3->bwp_Id = 1; csires3->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires3); + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires3); NR_CSI_ResourceConfig_t *csires4 = calloc(1,sizeof(*csires4)); csires4->csi_ResourceConfigId=4; @@ -1819,7 +1789,7 @@ servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon ASN_SEQUENCE_ADD(&csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires40); csires4->bwp_Id = 1; csires4->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires4); + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires4); NR_CSI_ResourceConfig_t *csires5 = calloc(1,sizeof(*csires5)); csires5->csi_ResourceConfigId=5; @@ -1832,7 +1802,7 @@ servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon ASN_SEQUENCE_ADD(&csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires50); csires5->bwp_Id = 1; csires5->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires5); + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires5); NR_CSI_ResourceConfig_t *csires6 = calloc(1,sizeof(*csires6)); csires6->csi_ResourceConfigId=6; @@ -1845,7 +1815,7 @@ servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon ASN_SEQUENCE_ADD(&csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires60); csires6->bwp_Id = 1; csires6->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires6); + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires6); NR_CSI_ResourceConfig_t *csires7 = calloc(1,sizeof(*csires7)); csires7->csi_ResourceConfigId=7; @@ -1858,7 +1828,7 @@ servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon ASN_SEQUENCE_ADD(&csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires70); csires7->bwp_Id = 1; csires7->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires7); + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires7); NR_CSI_ResourceConfig_t *csires8 = calloc(1,sizeof(*csires8)); csires8->csi_ResourceConfigId=8; @@ -1871,7 +1841,7 @@ servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon ASN_SEQUENCE_ADD(&csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires80); csires8->bwp_Id = 1; csires8->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires8); + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires8); NR_CSI_ResourceConfig_t *csires9 = calloc(1,sizeof(*csires9)); csires9->csi_ResourceConfigId=9; @@ -1884,7 +1854,7 @@ servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon ASN_SEQUENCE_ADD(&csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires90); csires9->bwp_Id = 1; csires9->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires9); + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires9); csi_MeasConfig->csi_ReportConfigToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_ReportConfigToAddModList)); csi_MeasConfig->csi_ReportConfigToReleaseList = NULL; @@ -1912,9 +1882,8 @@ servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon csirep0->reportFreqConfiguration->csi_ReportingBand=calloc(1,sizeof(*csirep0->reportFreqConfiguration->csi_ReportingBand)); - //AssertFatal(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id>0,"firstActiveDownlinkBWP_Id %d\n",(int)*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id); + AssertFatal(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id>0,"firstActiveDownlinkBWP_Id %d\n",(int)*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id); int NPRB = NRRIV2BW(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id-1]->bwp_Common->genericParameters.locationAndBandwidth,275); - //int NPRB = NRRIV2BW(28875,275); int sbsize = get_subband_size(NPRB,0); int numsb = NPRB/sbsize; if (NPRB%sbsize == 0) numsb++; @@ -2043,22 +2012,12 @@ void fill_default_reconfig(NR_ServingCellConfigCommon_t *servingcellconfigcommon // radioBearerConfig reconfig->radioBearerConfig=NULL; // secondaryCellGroup -#if 0 -NR_ServingCellConfigCommon_t z = *servingcellconfigcommon; -NR_ARFCN_ValueNR_t ssb_freq = 641272; //642208; //642208 is for SSB position = ptA + 82 RBs with ptA at 3600MHz //642256; //642016; //642256; -z.downlinkConfigCommon->frequencyInfoDL->absoluteFrequencySSB = &ssb_freq; -fill_default_secondaryCellGroup(&z,secondaryCellGroup,1,1,n_physical_antenna_ports,initial_csi_index); -#else - fill_default_secondaryCellGroup(servingcellconfigcommon,secondaryCellGroup,1,1,n_physical_antenna_ports,initial_csi_index); -#endif + fill_default_secondaryCellGroup(servingcellconfigcommon,secondaryCellGroup,0,0,n_physical_antenna_ports,initial_csi_index); xer_fprint(stdout, &asn_DEF_NR_CellGroupConfig, (const void*)secondaryCellGroup); -//void *x = secondaryCellGroup->spCellConfig->reconfigurationWithSync->spCellConfigCommon->tdd_UL_DL_ConfigurationCommon; -//secondaryCellGroup->spCellConfig->reconfigurationWithSync->spCellConfigCommon->tdd_UL_DL_ConfigurationCommon = NULL; char scg_buffer[1024]; asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CellGroupConfig, NULL, (void *)secondaryCellGroup, scg_buffer, 1024); AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", enc_rval.failed_type->name, enc_rval.encoded); -//secondaryCellGroup->spCellConfig->reconfigurationWithSync->spCellConfigCommon->tdd_UL_DL_ConfigurationCommon = x; reconfig->secondaryCellGroup = calloc(1,sizeof(*reconfig->secondaryCellGroup)); From f73dd0742ef6a4d1017872991ecee1c119b6670a Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 3 Apr 2020 14:19:28 +0200 Subject: [PATCH 136/553] Revert "ENDC path switch S1-U: Bugfixes at eNB side. Problem at S1AP E-RAB-Modification-Indication message encoding to be resolved" This reverts commit f895c4d929a2e323e0e56f59fbbb1377236d5a40. --- openair2/RRC/LTE/rrc_eNB.c | 50 +++----------------------------------- 1 file changed, 4 insertions(+), 46 deletions(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index 9edc5b7758..c8df01722f 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -3146,7 +3146,6 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t MeasId5->reportConfigId = 6; ASN_SEQUENCE_ADD(&MeasId_list->list, MeasId5); -//ue_context_pP->ue_context.does_nr=0; if (ue_context_pP->ue_context.does_nr) { MeasId6 = calloc(1, sizeof(LTE_MeasIdToAddMod_t)); if (MeasId6 == NULL) exit(1); @@ -3210,7 +3209,7 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t if (MeasObj2 == NULL) exit(1); MeasObj2->measObjectId = 2; MeasObj2->measObject.present = LTE_MeasObjectToAddMod__measObject_PR_measObjectNR_r15; - MeasObj2->measObject.choice.measObjectNR_r15.carrierFreq_r15 = 641272; //642208; //642208 is for SSB at ptA + 82 RBs with ptA at 3600MHz //642256; //634000; //(634000 = 3.51GHz) (640000 = 3.6GHz) (641272 = 3619.08MHz = 3600 + 30/1000*106*12/2) (642256 is for 3.6GHz and absoluteFrequencySSB = 642016) + MeasObj2->measObject.choice.measObjectNR_r15.carrierFreq_r15 = 642256; //634000; //(634000 = 3.51GHz) (640000 = 3.6GHz) (641272 = 3619.08MHz = 3600 + 30/1000*106*12/2) (642256 is for 3.6GHz and absoluteFrequencySSB = 642016) MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.periodicityAndOffset_r15.present = LTE_MTC_SSB_NR_r15__periodicityAndOffset_r15_PR_sf20_r15; MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.periodicityAndOffset_r15.choice.sf20_r15 = 0; MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.ssb_Duration_r15 = LTE_MTC_SSB_NR_r15__ssb_Duration_r15_sf4; @@ -3353,13 +3352,13 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.present = LTE_ReportConfigInterRAT__triggerType_PR_event; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.present = LTE_ReportConfigInterRAT__triggerType__event__eventId_PR_eventB1_NR_r15; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.b1_ThresholdNR_r15.present = LTE_ThresholdNR_r15_PR_nr_RSRP_r15; - ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.b1_ThresholdNR_r15.choice.nr_RSRP_r15 = 0; + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.b1_ThresholdNR_r15.choice.nr_RSRP_r15 = 46; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.reportOnLeave_r15 = FALSE; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.hysteresis = 2; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.timeToTrigger = LTE_TimeToTrigger_ms80; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.maxReportCells = 4; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.reportInterval = LTE_ReportInterval_ms120; - ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.reportAmount = LTE_ReportConfigInterRAT__reportAmount_r1; + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.reportAmount = LTE_ReportConfigInterRAT__reportAmount_infinity; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7 = calloc(1, sizeof(struct LTE_ReportConfigInterRAT__ext7)); if (ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7 == NULL) exit(1); ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15 = calloc(1, sizeof(struct LTE_ReportQuantityNR_r15)); @@ -4285,16 +4284,6 @@ rrc_eNB_generate_RRCConnectionReconfiguration_SCell( return(0); } -static volatile int start_nr; -static void *xx(void *_) -{ - while (1) { - getchar(); - start_nr = 1; - printf("start nr\n"); - } - return 0; -} //----------------------------------------------------------------------------- void @@ -4314,15 +4303,6 @@ rrc_eNB_process_MeasurementReport( T(T_ENB_RRC_MEASUREMENT_REPORT, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame), T_INT(ctxt_pP->subframe), T_INT(ctxt_pP->rnti)); -{ -static int conf = 0; -if (!conf) { - pthread_t t; - pthread_create(&t, NULL, xx, NULL); - conf = 1; -} -} - if (measResults2 == NULL ) return; @@ -4333,7 +4313,6 @@ if (!conf) { ue_context_pP->ue_context.measResults->measId=measResults2->measId; -printf("meas %d\n", (int)measResults2->measId); switch (measResults2->measId) { case 1: LOG_D(RRC,"Periodic report at frame %d and subframe %d \n", ctxt_pP->frame, ctxt_pP->subframe); @@ -4379,11 +4358,7 @@ printf("meas %d\n", (int)measResults2->measId); /* TODO: improve NR triggering */ if (measResults2->measId == 7) { -// if (start_nr) { -printf("nr\n"); -static int gonr = 0; - if (!gonr && ue_context_pP->ue_context.Status != RRC_NR_NSA) { -gonr=1; + if (ue_context_pP->ue_context.Status != RRC_NR_NSA) { MessageDef *msg; ue_context_pP->ue_context.Status = RRC_NR_NSA; @@ -4399,14 +4374,6 @@ gonr=1; memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr, &ue_context_pP->ue_context.e_rab[e_rab].param.sgw_addr, sizeof(transport_layer_addr_t)); - LOG_I(RRC,"x2u tunnel: index %d target enb ip %d.%d.%d.%d length %d gtp teid %u\n", - i, - X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr.buffer[0], - X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr.buffer[1], - X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr.buffer[2], - X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr.buffer[3], - X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr.length, - X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].gtp_teid); } LOG_I(RRC, "[eNB %d] frame %d subframe %d: UE rnti %x switching to NSA mode\n", @@ -8527,14 +8494,6 @@ void rrc_eNB_process_AdditionResponseInformation(const module_id_t enb_mod_idP, printf("\n"); } -{ -int i; -int len = m->rrc_buffer_size; -unsigned char *buffer = (unsigned char*)m->rrc_buffer; -printf("xxx: (len %d): ", m->rrc_buffer_size); -for (i = 0; irnti); rrc_data_req(&ctxt, DCCH, From f72259de8ef51974581e87d982ef06278e86a65e Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 3 Apr 2020 16:58:08 +0200 Subject: [PATCH 137/553] reactivating phytest schedulers --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index f993f393a7..c586a03fe0 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -364,7 +364,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, // Phytest scheduling if (get_softmodem_params()->phy_test && slot_txP==1){ - // nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP,NULL); + nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP,NULL); // resetting ta flag gNB->ta_len = 0; } @@ -385,7 +385,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, nr_schedule_reception_msg3(module_idP, 0, frame_rxP, slot_rxP); if (get_softmodem_params()->phy_test && slot_rxP==8){ - //nr_schedule_uss_ulsch_phytest(module_idP, frame_rxP, slot_rxP); + nr_schedule_uss_ulsch_phytest(module_idP, frame_rxP, slot_rxP); } } From 7846132e1c9681cedc34564de4710f097bf9d0c7 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Fri, 3 Apr 2020 19:12:06 +0200 Subject: [PATCH 138/553] updated dci_pdu_rel15_t moved nr_dci_size out of scheduler_phytest --- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 31 +-- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 54 +++-- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 184 ++++++++++-------- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 3 +- openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 103 +++++----- 5 files changed, 191 insertions(+), 184 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index 9ab1353b71..928da7c0fa 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -596,8 +596,7 @@ uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, case NR_DL_DCI_FORMAT_1_1: // Format identifier - dci_pdu->format_indicator.nbits=1; - size = dci_pdu->format_indicator.nbits; + size = 1; // Carrier indicator if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig != NULL) { dci_pdu->carrier_indicator.nbits=3; @@ -651,32 +650,23 @@ uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, dci_pdu->zp_csi_rs_trigger.nbits = (int)ceil(log2(nZP+1)); size += dci_pdu->zp_csi_rs_trigger.nbits; // TB1- MCS 5, NDI 1, RV 2 - dci_pdu->mcs[0].nbits = 5; - dci_pdu->ndi[0].nbits = 1; - dci_pdu->rv[0].nbits = 2; - size += (dci_pdu->mcs[0].nbits + dci_pdu->ndi[0].nbits + dci_pdu->rv[0].nbits); + size += 8; // TB2 long *maxCWperDCI = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI; - if ((maxCWperDCI != NULL) && (maxCWperDCI == 2)) { - dci_pdu->mcs[1].nbits = 5; - dci_pdu->ndi[1].nbits = 1; - dci_pdu->rv[1].nbits = 2; - size += (dci_pdu->mcs[1].nbits + dci_pdu->ndi[1].nbits + dci_pdu->rv[1].nbits); + if ((maxCWperDCI != NULL) && (*maxCWperDCI == 2)) { + size += 8; } // HARQ PID - dci_pdu->harq_pid.nbits = 4; - size += dci_pdu->harq_pid.nbits; + size += 4; // DAI if (secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook == 1) { // at this point the UE has multiple serving cells - dci_pdu->dai.nbits = 4; - size += dci_pdu->dai.nbits; + dci_pdu->dai[0].nbits = 4; + size += dci_pdu->dai[0].nbits; } // TPC PUCCH - dci_pdu->tpc.nbits = 2; - size += dci_pdu->tpc.nbits; + size += 2; // PUCCH resource indicator - dci_pdu->pucch_resource_indicator.nbits = 3; - size += dci_pdu->pucch_resource_indicator.nbits; + size += 3; // PDSCH to HARQ timing indicator uint8_t I = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[0]->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK->list.count; dci_pdu->pdsch_to_harq_feedback_timing_indicator.nbits = (int)ceil(log2(I)); @@ -710,8 +700,7 @@ uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, size += dci_pdu->cbgfi.nbits; } // DMRS sequence init - dci_pdu->dmrs_sequence_initialization.nbits = 1; - size += dci_pdu->dmrs_sequence_initialization.nbits; + size += 1; break; case NR_DL_DCI_FORMAT_2_0: diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 2413238a53..b40eb7d049 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -343,17 +343,17 @@ int configure_fapi_dl_pdu(int Mod_idP, NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275)); dci_pdu_rel15[0].time_domain_assignment.val = time_domain_assignment; // row index used here instead of SLIV; dci_pdu_rel15[0].vrb_to_prb_mapping.val = 1; - dci_pdu_rel15[0].mcs[0].val = pdsch_pdu_rel15->mcsIndex[0]; - dci_pdu_rel15[0].tb_scaling.val = 1; + dci_pdu_rel15[0].mcs = pdsch_pdu_rel15->mcsIndex[0]; + dci_pdu_rel15[0].tb_scaling = 1; - dci_pdu_rel15[0].ra_preamble_index.val = 25; - dci_pdu_rel15[0].format_indicator.val = 1; - dci_pdu_rel15[0].ndi[0].val = 1; - dci_pdu_rel15[0].rv[0].val = 0; - dci_pdu_rel15[0].harq_pid.val = 0; - dci_pdu_rel15[0].dai.val = 2; - dci_pdu_rel15[0].tpc.val = 2; - dci_pdu_rel15[0].pucch_resource_indicator.val = 7; + dci_pdu_rel15[0].ra_preamble_index = 25; + dci_pdu_rel15[0].format_indicator = 1; + dci_pdu_rel15[0].ndi = 1; + dci_pdu_rel15[0].rv = 0; + dci_pdu_rel15[0].harq_pid = 0; + dci_pdu_rel15[0].dai[0].val = 2; + dci_pdu_rel15[0].tpc = 2; + dci_pdu_rel15[0].pucch_resource_indicator = 7; dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator.val = 7; LOG_D(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n", @@ -363,10 +363,10 @@ int configure_fapi_dl_pdu(int Mod_idP, NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275), dci_pdu_rel15[0].time_domain_assignment.val, dci_pdu_rel15[0].vrb_to_prb_mapping.val, - dci_pdu_rel15[0].mcs[0].val, - dci_pdu_rel15[0].tb_scaling.val, - dci_pdu_rel15[0].ndi[0].val, - dci_pdu_rel15[0].rv[0].val); + dci_pdu_rel15[0].mcs, + dci_pdu_rel15[0].tb_scaling, + dci_pdu_rel15[0].ndi, + dci_pdu_rel15[0].rv); nr_configure_pdcch(pdcch_pdu_rel15, 1, // ue-specific @@ -386,8 +386,7 @@ int configure_fapi_dl_pdu(int Mod_idP, dci_formats[0] = NR_DL_DCI_FORMAT_1_0; rnti_types[0] = NR_RNTI_C; - pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(secondaryCellGroup,&dci_pdu_rel15[0],dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); - fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types); + fill_dci_pdu_rel15(secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types); LOG_D(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \ coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n", @@ -425,23 +424,23 @@ void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr dci_pdu_rel15->time_domain_assignment.val = 2; // row index used here instead of SLIV; dci_pdu_rel15->frequency_hopping_flag.val = 0; - dci_pdu_rel15->mcs[0].val = 9; + dci_pdu_rel15->mcs = 9; - dci_pdu_rel15->format_indicator.val = 0; - dci_pdu_rel15->ndi[0].val = 1; - dci_pdu_rel15->rv[0].val = 0; - dci_pdu_rel15->harq_pid.val = 0; - dci_pdu_rel15->tpc.val = 2; + dci_pdu_rel15->format_indicator = 0; + dci_pdu_rel15->ndi = 1; + dci_pdu_rel15->rv = 0; + dci_pdu_rel15->harq_pid = 0; + dci_pdu_rel15->tpc = 2; LOG_D(MAC, "[gNB scheduler phytest] ULDCI type 0 payload: PDCCH CCEIndex %d, freq_alloc %d, time_alloc %d, freq_hop_flag %d, mcs %d tpc %d ndi %d rv %d\n", pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci], dci_pdu_rel15->frequency_domain_assignment.val, dci_pdu_rel15->time_domain_assignment.val, dci_pdu_rel15->frequency_hopping_flag.val, - dci_pdu_rel15->mcs[0].val, - dci_pdu_rel15->tpc.val, - dci_pdu_rel15->ndi[0].val, - dci_pdu_rel15->rv[0].val); + dci_pdu_rel15->mcs, + dci_pdu_rel15->tpc, + dci_pdu_rel15->ndi, + dci_pdu_rel15->rv); dci_formats[pdcch_pdu_rel15->numDlDci] = NR_UL_DCI_FORMAT_0_0; rnti_types[pdcch_pdu_rel15->numDlDci] = NR_RNTI_C; @@ -832,8 +831,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); - pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(secondaryCellGroup,&dci_pdu_rel15[0],dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); - fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types); + fill_dci_pdu_rel15(secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types); } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index a3961d1f88..8f442d6851 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -544,11 +544,31 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, } } -void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, - dci_pdu_rel15_t *dci_pdu_rel15, - int *dci_formats, - int *rnti_types - ) { +void prepare_dci(NR_CellGroupConfig_t *secondaryCellGroup, + dci_pdu_rel15_t *dci_pdu_rel15, + nr_dci_format_t format) { + + switch(format) { + case NR_DL_DCI_FORMAT_1_1: + //carrier indicator + //bwp indicator + //vrb to prb mapping + //bundling size indicator + //rate matching indicator + //ZP CSI-RS trigger + //dai + //antenna ports + //srs resource set + break; + } +} + +void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, + nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, + dci_pdu_rel15_t *dci_pdu_rel15, + int *dci_formats, + int *rnti_types + ) { uint16_t N_RB = pdcch_pdu_rel15->BWPSize; uint8_t fsize=0, pos=0; @@ -557,9 +577,11 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, for (int d=0;dnumDlDci;d++) { uint64_t *dci_pdu = (uint64_t *)pdcch_pdu_rel15->Payload[d]; - AssertFatal(pdcch_pdu_rel15->PayloadSizeBits[d]<=64, "DCI sizes above 64 bits not yet supported"); - int dci_size = pdcch_pdu_rel15->PayloadSizeBits[d]; + int dci_size = nr_dci_size(secondaryCellGroup,&dci_pdu_rel15[d],dci_formats[d],rnti_types[d],pdcch_pdu_rel15->BWPSize); + pdcch_pdu_rel15->PayloadSizeBits[d] = dci_size; + AssertFatal(pdcch_pdu_rel15->PayloadSizeBits[d]<=64, "DCI sizes above 64 bits not yet supported"); + prepare_dci(secondaryCellGroup,&dci_pdu_rel15[d],dci_formats[d]); pos = 0; /// Payload generation @@ -583,20 +605,20 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping.val,dci_size-pos,*dci_pdu); // MCS pos+=5; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs[0].val&0x1f)<<(dci_size-pos); - LOG_D(MAC,"mcs[0] %d (5 bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs[0].val,dci_size-pos,*dci_pdu); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos); + LOG_D(MAC,"mcs %d (5 bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,dci_size-pos,*dci_pdu); // TB scaling pos+=2; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->tb_scaling.val&0x3)<<(dci_size-pos); - LOG_D(MAC,"tb_scaling %d (2 bits)=> %d (0x%lx)\n",dci_pdu_rel15->tb_scaling.val,dci_size-pos,*dci_pdu); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->tb_scaling&0x3)<<(dci_size-pos); + LOG_D(MAC,"tb_scaling %d (2 bits)=> %d (0x%lx)\n",dci_pdu_rel15->tb_scaling,dci_size-pos,*dci_pdu); break; case NR_RNTI_C: // indicating a DL DCI format 1bit pos++; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator.val&1)<<(dci_size-pos); - LOG_D(MAC,"Format indicator %d (%d bits) N_RB_BWP %d => %d (0x%lx)\n",dci_pdu_rel15->format_indicator.val,1,N_RB,dci_size-pos,*dci_pdu); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&1)<<(dci_size-pos); + LOG_D(MAC,"Format indicator %d (%d bits) N_RB_BWP %d => %d (0x%lx)\n",dci_pdu_rel15->format_indicator,1,N_RB,dci_size-pos,*dci_pdu); // Freq domain assignment (275rb >> fsize = 16) fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); @@ -615,7 +637,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, { // ra_preamble_index 6 bits pos+=6; - *dci_pdu |= ((dci_pdu_rel15->ra_preamble_index.val&0x3f)<<(dci_size-pos)); + *dci_pdu |= ((dci_pdu_rel15->ra_preamble_index&0x3f)<<(dci_size-pos)); // UL/SUL indicator 1 bit pos++; @@ -623,11 +645,11 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, // SS/PBCH index 6 bits pos+=6; - *dci_pdu |= ((dci_pdu_rel15->ss_pbch_index.val&0x3f)<<(dci_size-pos)); + *dci_pdu |= ((dci_pdu_rel15->ss_pbch_index&0x3f)<<(dci_size-pos)); // prach_mask_index 4 bits pos+=4; - *dci_pdu |= ((dci_pdu_rel15->prach_mask_index.val&0xf)<<(dci_size-pos)); + *dci_pdu |= ((dci_pdu_rel15->prach_mask_index&0xf)<<(dci_size-pos)); } //end if @@ -646,38 +668,38 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, // MCS 5bit //bit over 32, so dci_pdu ++ pos+=5; - *dci_pdu |= (dci_pdu_rel15->mcs[0].val&0x1f)<<(dci_size-pos); - LOG_D(MAC,"MCS %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs[0].val,5,dci_size-pos,*dci_pdu); + *dci_pdu |= (dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos); + LOG_D(MAC,"MCS %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,5,dci_size-pos,*dci_pdu); // New data indicator 1bit pos++; - *dci_pdu |= (dci_pdu_rel15->ndi[0].val&1)<<(dci_size-pos); - LOG_D(MAC,"NDI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->ndi[0].val,1,dci_size-pos,*dci_pdu); + *dci_pdu |= (dci_pdu_rel15->ndi&1)<<(dci_size-pos); + LOG_D(MAC,"NDI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->ndi,1,dci_size-pos,*dci_pdu); // Redundancy version 2bit pos+=2; - *dci_pdu |= (dci_pdu_rel15->rv[0].val&0x3)<<(dci_size-pos); - LOG_D(MAC,"RV %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->rv[0].val,2,dci_size-pos,*dci_pdu); + *dci_pdu |= (dci_pdu_rel15->rv&0x3)<<(dci_size-pos); + LOG_D(MAC,"RV %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->rv,2,dci_size-pos,*dci_pdu); // HARQ process number 4bit pos+=4; - *dci_pdu |= ((dci_pdu_rel15->harq_pid.val&0xf)<<(dci_size-pos)); - LOG_D(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_pid.val,4,dci_size-pos,*dci_pdu); + *dci_pdu |= ((dci_pdu_rel15->harq_pid&0xf)<<(dci_size-pos)); + LOG_D(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_pid,4,dci_size-pos,*dci_pdu); // Downlink assignment index 2bit pos+=2; - *dci_pdu |= ((dci_pdu_rel15->dai.val&3)<<(dci_size-pos)); - LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai.val,2,dci_size-pos,*dci_pdu); + *dci_pdu |= ((dci_pdu_rel15->dai[0].val&3)<<(dci_size-pos)); + LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai[0].val,2,dci_size-pos,*dci_pdu); // TPC command for scheduled PUCCH 2bit pos+=2; - *dci_pdu |= ((dci_pdu_rel15->tpc.val&3)<<(dci_size-pos)); - LOG_D(MAC,"TPC %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->tpc.val,2,dci_size-pos,*dci_pdu); + *dci_pdu |= ((dci_pdu_rel15->tpc&3)<<(dci_size-pos)); + LOG_D(MAC,"TPC %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->tpc,2,dci_size-pos,*dci_pdu); // PUCCH resource indicator 3bit pos+=3; - *dci_pdu |= ((dci_pdu_rel15->pucch_resource_indicator.val&0x7)<<(dci_size-pos)); - LOG_D(MAC,"PUCCH RI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pucch_resource_indicator.val,3,dci_size-pos,*dci_pdu); + *dci_pdu |= ((dci_pdu_rel15->pucch_resource_indicator&0x7)<<(dci_size-pos)); + LOG_D(MAC,"PUCCH RI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pucch_resource_indicator,3,dci_size-pos,*dci_pdu); // PDSCH-to-HARQ_feedback timing indicator 3bit pos+=3; @@ -691,10 +713,10 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, // Short Messages Indicator – 2 bits for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages_indicator.val>>(1-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages_indicator>>(1-i))&1)<<(dci_size-pos++); // Short Messages – 8 bits for (int i=0; i<8; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages.val>>(7-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages>>(7-i))&1)<<(dci_size-pos++); // Freq domain assignment 0-16 bit fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); for (int i=0; ivrb_to_prb_mapping.val&1)<<(dci_size-pos++); // MCS 5 bit for (int i=0; i<5; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs[0].val>>(4-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); // TB scaling 2 bit for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->tb_scaling.val>>(1-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->tb_scaling>>(1-i))&1)<<(dci_size-pos++); break; @@ -727,16 +749,16 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++); // MCS 5bit //bit over 32, so dci_pdu ++ for (int i=0; i<5; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs[0].val>>(4-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); // Redundancy version 2bit for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv[0].val>>(1-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv>>(1-i))&1)<<(dci_size-pos++); break; case NR_RNTI_TC: // indicating a DL DCI format 1bit - *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator.val&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&1)<<(dci_size-pos++); // Freq domain assignment 0-16 bit fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); for (int i=0; ivrb_to_prb_mapping.val&1)<<(dci_size-pos++); // MCS 5bit //bit over 32, so dci_pdu ++ for (int i=0; i<5; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs[0].val>>(4-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); // New data indicator 1bit - *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi[0].val&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&1)<<(dci_size-pos++); // Redundancy version 2bit for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv[0].val>>(1-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv>>(1-i))&1)<<(dci_size-pos++); // HARQ process number 4bit for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid.val>>(3-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid>>(3-i))&1)<<(dci_size-pos++); // Downlink assignment index – 2 bits for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->dai.val>>(1-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->dai[0].val>>(1-i))&1)<<(dci_size-pos++); // TPC command for scheduled PUCCH – 2 bits for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc.val>>(1-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc>>(1-i))&1)<<(dci_size-pos++); // LOG_D(MAC, "DCI PDU: [0]->0x%08llx \t [1]->0x%08llx \t [2]->0x%08llx \t [3]->0x%08llx\n", @@ -784,7 +806,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, { case NR_RNTI_C: // indicating a DL DCI format 1bit - *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator.val&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&1)<<(dci_size-pos++); // Freq domain assignment max 16 bit fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); for (int i=0; ifrequency_hopping_flag.val&1)<<(dci_size-pos++); // MCS 5 bit for (int i=0; i<5; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs[0].val>>(4-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); // New data indicator 1bit - *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi[0].val&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&1)<<(dci_size-pos++); // Redundancy version 2bit for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv[0].val>>(1-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv>>(1-i))&1)<<(dci_size-pos++); // HARQ process number 4bit for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid.val>>(3-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid>>(3-i))&1)<<(dci_size-pos++); // TPC command for scheduled PUSCH – 2 bits for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc.val>>(1-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc>>(1-i))&1)<<(dci_size-pos++); // Padding bits for(int a = pos;a<32;a++) - *dci_pdu |= ((uint64_t)dci_pdu_rel15->padding.val&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->padding&1)<<(dci_size-pos++); // UL/SUL indicator – 1 bit /* commented for now (RK): need to get this from BWP descriptor @@ -824,7 +846,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, case NFAPI_NR_RNTI_TC: // indicating a DL DCI format 1bit - *dci_pdu |= (dci_pdu_rel15->format_indicator.val&1)<<(dci_size-pos++); + *dci_pdu |= (dci_pdu_rel15->format_indicator&1)<<(dci_size-pos++); // Freq domain assignment max 16 bit fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); for (int i=0; ifrequency_hopping_flag.val&1)<<(dci_size-pos++); // MCS 5 bit for (int i=0; i<5; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs[0].val>>(4-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); // New data indicator 1bit - *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi[0].val&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&1)<<(dci_size-pos++); // Redundancy version 2bit for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv[0].val>>(1-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv>>(1-i))&1)<<(dci_size-pos++); // HARQ process number 4bit for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid.val>>(3-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid>>(3-i))&1)<<(dci_size-pos++); // TPC command for scheduled PUSCH – 2 bits for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc.val>>(1-i))&1)<<(dci_size-pos++); + *dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc>>(1-i))&1)<<(dci_size-pos++); // Padding bits for(int a = pos;a<32;a++) - *dci_pdu |= ((uint64_t)dci_pdu_rel15->padding.val&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->padding&1)<<(dci_size-pos++); // UL/SUL indicator – 1 bit /* @@ -867,8 +889,8 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, case NR_DL_DCI_FORMAT_1_1: // Indicating a DL DCI format 1bit - pos=dci_pdu_rel15->format_indicator.nbits; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator.val&((1<format_indicator.nbits)-1))<<(dci_size-pos); + pos=1; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&0x1)<<(dci_size-pos); // Carrier indicator pos+=dci_pdu_rel15->carrier_indicator.nbits; @@ -904,45 +926,45 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, //TB1 // MCS 5bit - pos+=dci_pdu_rel15->mcs[0].nbits; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs[0].val&((1<mcs[0].nbits)-1))<<(dci_size-pos); + pos+=5; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos); // New data indicator 1bit - pos+=dci_pdu_rel15->ndi[0].nbits; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi[0].val&((1<ndi[0].nbits)-1))<<(dci_size-pos); + pos+=1; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&0x1)<<(dci_size-pos); // Redundancy version 2bit - pos+=dci_pdu_rel15->rv[0].nbits; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->rv[0].val&((1<rv[0].nbits)-1))<<(dci_size-pos); + pos+=2; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->rv&0x3)<<(dci_size-pos); //TB2 // MCS 5bit - pos+=dci_pdu_rel15->mcs[1].nbits; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs[1].val&((1<mcs[1].nbits)-1))<<(dci_size-pos); + pos+=dci_pdu_rel15->mcs2.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs2.val&((1<mcs2.nbits)-1))<<(dci_size-pos); // New data indicator 1bit - pos+=dci_pdu_rel15->ndi[1].nbits; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi[1].val&((1<ndi[1].nbits)-1))<<(dci_size-pos); + pos+=dci_pdu_rel15->ndi2.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi2.val&((1<ndi2.nbits)-1))<<(dci_size-pos); // Redundancy version 2bit - pos+=dci_pdu_rel15->rv[1].nbits; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->rv[1].val&((1<rv[1].nbits)-1))<<(dci_size-pos); + pos+=dci_pdu_rel15->rv2.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->rv2.val&((1<rv2.nbits)-1))<<(dci_size-pos); // HARQ process number 4bit - pos+=dci_pdu_rel15->harq_pid.nbits; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid.val&((1<harq_pid.nbits)-1))<<(dci_size-pos); + pos+=4; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid&0xf)<<(dci_size-pos); // Downlink assignment index - pos+=dci_pdu_rel15->dai.nbits; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->dai.val&((1<dai.nbits)-1))<<(dci_size-pos); + pos+=dci_pdu_rel15->dai[0].nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->dai[0].val&((1<dai[0].nbits)-1))<<(dci_size-pos); // TPC command for scheduled PUCCH 2bit - pos+=dci_pdu_rel15->tpc.nbits; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->tpc.val&((1<tpc.nbits)-1))<<(dci_size-pos); + pos+=2; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->tpc&0x3)<<(dci_size-pos); // PUCCH resource indicator 3bit - pos+=dci_pdu_rel15->pucch_resource_indicator.nbits; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->pucch_resource_indicator.val&((1<pucch_resource_indicator.nbits)-1))<<(dci_size-pos); + pos+=3; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->pucch_resource_indicator&0x7)<<(dci_size-pos); // PDSCH-to-HARQ_feedback timing indicator pos+=dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.nbits; @@ -969,8 +991,8 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, *dci_pdu |= ((uint64_t)dci_pdu_rel15->cbgfi.val&((1<cbgfi.nbits)-1))<<(dci_size-pos); // DMRS sequence init - pos+=dci_pdu_rel15->dmrs_sequence_initialization.nbits; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->dmrs_sequence_initialization.val&((1<dmrs_sequence_initialization.nbits)-1))<<(dci_size-pos); + pos+=1; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->dmrs_sequence_initialization&0x1)<<(dci_size-pos); } } } diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index 3046abfb71..629ad44c09 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -130,7 +130,8 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, NR_ServingCellConfigCommon_t *scc, NR_BWP_Downlink_t *bwp); -void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, +void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, + nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types); diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index d21f0be2a2..0f93299d34 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -260,62 +260,59 @@ typedef struct { typedef struct { -dci_field_t format_indicator; //1 bit -dci_field_t frequency_domain_assignment; //up to 16 bits -dci_field_t time_domain_assignment; // 4 bits -dci_field_t frequency_hopping_flag; //1 bit +uint8_t format_indicator; //1 bit +uint8_t ra_preamble_index; //6 bits +uint8_t ss_pbch_index; //6 bits +uint8_t prach_mask_index; //4 bits +uint8_t mcs; //5 bits +uint8_t ndi; //1 bit +uint8_t rv; //2 bits +uint8_t harq_pid; //4 bits +uint8_t tpc; //2 bits +uint8_t short_messages_indicator; //2 bits +uint8_t short_messages; //8 bits +uint8_t tb_scaling; //2 bits +uint8_t pucch_resource_indicator; //3 bits +uint8_t dmrs_sequence_initialization; //1 bit +uint8_t system_info_indicator; //1 bit + +uint8_t slot_format_indicator_count; +uint8_t *slot_format_indicators; -dci_field_t ra_preamble_index; //6 bits -dci_field_t ss_pbch_index; //6 bits -dci_field_t prach_mask_index; //4 bits - -dci_field_t vrb_to_prb_mapping; //0 or 1 bit -dci_field_t mcs[2]; //5 bits -dci_field_t ndi[2]; //1 bit -dci_field_t rv[2]; //2 bits -dci_field_t harq_pid; //4 bits -dci_field_t dai; //0, 2 or 4 bits -dci_field_t dai1; //1 or 2 bits -dci_field_t dai2; //0 or 2 bits -dci_field_t tpc; //2 bits -dci_field_t pucch_resource_indicator; //3 bits -dci_field_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits - -dci_field_t short_messages_indicator; //2 bits -dci_field_t short_messages; //8 bits -dci_field_t tb_scaling; //2 bits - -dci_field_t carrier_indicator; //0 or 3 bits -dci_field_t bwp_indicator; //0, 1 or 2 bits -dci_field_t prb_bundling_size_indicator; //0 or 1 bits -dci_field_t rate_matching_indicator; //0, 1 or 2 bits -dci_field_t zp_csi_rs_trigger; //0, 1 or 2 bits -dci_field_t transmission_configuration_indication; //0 or 3 bits -dci_field_t srs_request; //2 bits -dci_field_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits -dci_field_t cbgfi; //CBG Flushing Out Information: 0 or 1 bit -dci_field_t dmrs_sequence_initialization; //0 or 1 bit - -dci_field_t srs_resource_indicator; -dci_field_t precoding_information; -dci_field_t csi_request; -dci_field_t ptrs_dmrs_association; -dci_field_t beta_offset_indicator; //0 or 2 bits - -dci_field_t slot_format_indicator_count; -dci_field_t *slot_format_indicators; - -dci_field_t pre_emption_indication_count; -dci_field_t *pre_emption_indications; //14 bit - -dci_field_t block_number_count; -dci_field_t *block_numbers; - -dci_field_t ul_sul_indicator; //0 or 1 bit -dci_field_t antenna_ports; +uint8_t pre_emption_indication_count; +uint16_t *pre_emption_indications; //14 bit each +uint8_t block_number_count; +uint8_t *block_numbers; +uint8_t padding; + +dci_field_t mcs2; //variable +dci_field_t ndi2; //variable +dci_field_t rv2; //variable +dci_field_t frequency_domain_assignment; //variable +dci_field_t time_domain_assignment; //variable +dci_field_t frequency_hopping_flag; //variable +dci_field_t vrb_to_prb_mapping; //variable +dci_field_t dai[2]; //variable +dci_field_t pdsch_to_harq_feedback_timing_indicator; //variable +dci_field_t carrier_indicator; //variable +dci_field_t bwp_indicator; //variable +dci_field_t prb_bundling_size_indicator; //variable +dci_field_t rate_matching_indicator; //variable +dci_field_t zp_csi_rs_trigger; //variable +dci_field_t transmission_configuration_indication; //variable +dci_field_t srs_request; //variable +dci_field_t cbgti; //variable +dci_field_t cbgfi; //variable +dci_field_t srs_resource_indicator; //variable +dci_field_t precoding_information; //variable +dci_field_t csi_request; //variable +dci_field_t ptrs_dmrs_association; //variable +dci_field_t beta_offset_indicator; //variable +dci_field_t cloded_loop_indicator; //variable +dci_field_t ul_sul_indicator; //variable +dci_field_t antenna_ports; //variable dci_field_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits -dci_field_t padding; } dci_pdu_rel15_t; From 8892d00693c186fc0cec47d9e2d5b10985c28a3f Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Sat, 4 Apr 2020 10:32:07 +0200 Subject: [PATCH 139/553] flag do_ra alternative to phy_test to perform RA procedures --- executables/nr-softmodem-common.h | 1 + executables/nr-softmodem.c | 3 +++ executables/nr-uesoftmodem.c | 8 +++---- executables/softmodem-common.h | 4 ++++ openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 26 ++++++++++----------- openair1/SIMULATION/NR_PHY/ulsim.c | 3 ++- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 11 +++++---- openair2/RRC/NR/rrc_gNB.c | 2 +- openair2/RRC/NR_UE/rrc_UE.c | 2 +- 9 files changed, 34 insertions(+), 26 deletions(-) diff --git a/executables/nr-softmodem-common.h b/executables/nr-softmodem-common.h index ccb3f28d98..305e4c4fc8 100644 --- a/executables/nr-softmodem-common.h +++ b/executables/nr-softmodem-common.h @@ -57,6 +57,7 @@ #define CONFIG_HLP_DLSHIFT "dynamic shift for LLR compuation for TM3/4 (default 0)\n" #define CONFIG_HLP_UELOOP "get softmodem (UE) to loop through memory instead of acquiring from HW\n" #define CONFIG_HLP_PHYTST "test UE phy layer, mac disabled\n" +#define CONFIG_HLP_DORA "test gNB and UE with RA procedures\n" #define CONFIG_HLP_DMAMAP "sets flag for improved EXMIMO UE performance\n" #define CONFIG_HLP_EXCCLK "tells hardware to use a clock reference (0:internal(default), 1:external, 2:gpsdo)\n" #define CONFIG_HLP_USIM "use XOR autentication algo in case of test usim mode\n" diff --git a/executables/nr-softmodem.c b/executables/nr-softmodem.c index 659ce056c0..f0efdff39c 100644 --- a/executables/nr-softmodem.c +++ b/executables/nr-softmodem.c @@ -822,6 +822,9 @@ int main( int argc, char **argv ) openair0_cfg[0].threequarter_fs = threequarter_fs; + if (get_softmodem_params()->do_ra) + AssertFatal(get_softmodem_params()->phy_test == 0,"RA and phy_test are mutually exclusive\n"); + #if T_TRACER T_Config_Init(); #endif diff --git a/executables/nr-uesoftmodem.c b/executables/nr-uesoftmodem.c index 89f2ee8509..d5c34fc728 100644 --- a/executables/nr-uesoftmodem.c +++ b/executables/nr-uesoftmodem.c @@ -716,6 +716,9 @@ int main( int argc, char **argv ) { PHY_vars_UE_g = malloc(sizeof(PHY_VARS_NR_UE **)); PHY_vars_UE_g[0] = malloc(sizeof(PHY_VARS_NR_UE *)*MAX_NUM_CCs); + if (get_softmodem_params()->do_ra) + AssertFatal(get_softmodem_params()->phy_test == 0,"RA and phy_test are mutually exclusive\n"); + for (int CC_id=0; CC_idofdm_symbol_size); frame_parms[CC_id]->nb_antennas_tx = nb_antenna_tx; @@ -742,11 +745,6 @@ int main( int argc, char **argv ) { init_nr_ue_vars(UE[CC_id],frame_parms[CC_id],0,abstraction_flag); - if (get_softmodem_params()->phy_test==1) - UE[CC_id]->mac_enabled = 0; - else - UE[CC_id]->mac_enabled = 1; - UE[CC_id]->mac_enabled = 1; UE[CC_id]->if_inst = nr_ue_if_module_init(0); UE[CC_id]->UE_scan = UE_scan; diff --git a/executables/softmodem-common.h b/executables/softmodem-common.h index cfed951469..7684dad948 100644 --- a/executables/softmodem-common.h +++ b/executables/softmodem-common.h @@ -50,6 +50,7 @@ extern "C" #define CONFIG_HLP_DUMPFRAME "dump UE received frame to rxsig_frame0.dat and exit\n" #define CONFIG_HLP_UELOOP "get softmodem (UE) to loop through memory instead of acquiring from HW\n" #define CONFIG_HLP_PHYTST "test UE phy layer, mac disabled\n" +#define CONFIG_HLP_DORA "test gNB and UE with RA procedures\n" #define CONFIG_HLP_EXTS "tells hardware to use an external timing reference\n" #define CONFIG_HLP_DMRSSYNC "tells RU to insert DMRS in subframe 1 slot 0" #define CONFIG_HLP_CLK "tells hardware to use a clock reference (0:internal, 1:external, 2:gpsdo)\n" @@ -89,6 +90,7 @@ extern "C" /*-----------------------------------------------------------------------------------------------------------------------------------------------------*/ #define RF_CONFIG_FILE softmodem_params.rf_config_file #define PHY_TEST softmodem_params.phy_test +#define DO_RA softmodem_params.do_ra #define WAIT_FOR_SYNC softmodem_params.wait_for_sync #define SINGLE_THREAD_FLAG softmodem_params.single_thread_flag #define CHAIN_OFFSET softmodem_params.chain_offset @@ -104,6 +106,7 @@ extern "C" #define CMDLINE_PARAMS_DESC { \ {"rf-config-file", CONFIG_HLP_RFCFGF, 0, strptr:(char **)&RF_CONFIG_FILE, defstrval:NULL, TYPE_STRING, sizeof(RF_CONFIG_FILE)},\ {"phy-test", CONFIG_HLP_PHYTST, PARAMFLAG_BOOL, iptr:&PHY_TEST, defintval:0, TYPE_INT, 0}, \ + {"do-ra", CONFIG_HLP_DORA, PARAMFLAG_BOOL, iptr:&DO_RA, defintval:0, TYPE_INT, 0}, \ {"usim-test", CONFIG_HLP_USIM, PARAMFLAG_BOOL, u8ptr:&USIM_TEST, defintval:0, TYPE_UINT8, 0}, \ {"clock", CONFIG_HLP_CLK, 0, uptr:&CLOCK_SOURCE, defintval:0, TYPE_UINT, 0}, \ {"wait-for-sync", NULL, PARAMFLAG_BOOL, iptr:&WAIT_FOR_SYNC, defintval:0, TYPE_INT, 0}, \ @@ -192,6 +195,7 @@ typedef struct { //THREAD_STRUCT thread_struct; char rf_config_file[1024]; int phy_test; + int do_ra; uint8_t usim_test; int emulate_rf; int wait_for_sync; //eNodeB only diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 16dfb40134..9be9fe8424 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -53,7 +53,7 @@ #ifdef EMOS #include "SCHED/phy_procedures_emos.h" #endif - +#include "executables/softmodem-common.h" //#define DEBUG_PHY_PROC #define NR_PDCCH_SCHED @@ -2255,24 +2255,24 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, } // UE_mode==PUSCH */ - - nr_ue_pusch_common_procedures(ue, - harq_pid, - slot_tx, - thread_id, - gNB_id, - &ue->frame_parms); + nr_ue_pusch_common_procedures(ue, + harq_pid, + slot_tx, + thread_id, + gNB_id, + &ue->frame_parms); } /* RACH */ - if ((ue->UE_mode[gNB_id] == PRACH) && (ue->prach_vars[gNB_id]->prach_Config_enabled == 1)) { + if (get_softmodem_params()->do_ra==1) { + if ((ue->UE_mode[gNB_id] == PRACH) && (ue->prach_vars[gNB_id]->prach_Config_enabled == 1)) { nr_ue_prach_procedures(ue, proc, gNB_id, mode); + } + else { + ue->prach_resources[gNB_id]->generate_nr_prach = 0; + } } - else { - ue->prach_resources[gNB_id]->generate_nr_prach = 0; - } - LOG_I(PHY,"****** end TX-Chain for AbsSubframe %d.%d ******\n", frame_tx, slot_tx); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX, VCD_FUNCTION_OUT); diff --git a/openair1/SIMULATION/NR_PHY/ulsim.c b/openair1/SIMULATION/NR_PHY/ulsim.c index ce26c91ae8..94d3416aec 100644 --- a/openair1/SIMULATION/NR_PHY/ulsim.c +++ b/openair1/SIMULATION/NR_PHY/ulsim.c @@ -353,7 +353,8 @@ int main(int argc, char **argv) T_stdout = 1; get_softmodem_params()->phy_test = 1; - + get_softmodem_params()->do_ra = 0; + if (snr1set == 0) snr1 = snr0 + 10; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index c586a03fe0..d7771fbfa9 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -360,7 +360,8 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, gNB->ta_len = 2; } - nr_schedule_RA(module_idP, frame_txP, slot_txP); + if (get_softmodem_params()->phy_test == 0) + nr_schedule_RA(module_idP, frame_txP, slot_txP); // Phytest scheduling if (get_softmodem_params()->phy_test && slot_txP==1){ @@ -380,10 +381,10 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, if (is_nr_UL_slot(cc->ServingCellConfigCommon,slot_rxP)) { - schedule_nr_prach(module_idP, (frame_rxP+1)&1023, slot_rxP); - - nr_schedule_reception_msg3(module_idP, 0, frame_rxP, slot_rxP); - + if (get_softmodem_params()->phy_test == 0) { + schedule_nr_prach(module_idP, (frame_rxP+1)&1023, slot_rxP); + nr_schedule_reception_msg3(module_idP, 0, frame_rxP, slot_rxP); + } if (get_softmodem_params()->phy_test && slot_rxP==8){ nr_schedule_uss_ulsch_phytest(module_idP, frame_rxP, slot_rxP); } diff --git a/openair2/RRC/NR/rrc_gNB.c b/openair2/RRC/NR/rrc_gNB.c index 22351feb2b..6cf48411cc 100644 --- a/openair2/RRC/NR/rrc_gNB.c +++ b/openair2/RRC/NR/rrc_gNB.c @@ -204,7 +204,7 @@ static void init_NR_SI(gNB_RRC_INST *rrc) { ); - if (get_softmodem_params()->phy_test > 0) { + if (get_softmodem_params()->phy_test > 0 || get_softmodem_params()->do_ra > 0) { // This is for phytest only, emulate first X2 message if uecap.raw file is present FILE *fd; diff --git a/openair2/RRC/NR_UE/rrc_UE.c b/openair2/RRC/NR_UE/rrc_UE.c index 7ddfc6054b..44215df218 100755 --- a/openair2/RRC/NR_UE/rrc_UE.c +++ b/openair2/RRC/NR_UE/rrc_UE.c @@ -319,7 +319,7 @@ NR_UE_RRC_INST_t* openair_rrc_top_init_ue_nr(char* rrc_config_path){ RRC_LIST_INIT(NR_UE_rrc_inst->CSI_ResourceConfig_list, NR_maxNrofCSI_ResourceConfigurations); RRC_LIST_INIT(NR_UE_rrc_inst->CSI_ReportConfig_list, NR_maxNrofCSI_ReportConfigurations); - if (get_softmodem_params()->phy_test==1) { + if (get_softmodem_params()->phy_test==1 || get_softmodem_params()->do_ra==1) { // read in files for RRCReconfiguration and RBconfig FILE *fd; char filename[1024]; From cd843860a80918c714d1ea9eb3e123847aa885be Mon Sep 17 00:00:00 2001 From: matzakos Date: Sat, 4 Apr 2020 11:56:06 +0200 Subject: [PATCH 140/553] Fix RFSIMULATOR issues (gNB side) after merge of NR_test_S1U_RRC_PRACH_procedures into NR_RRC_PRACH_procedures --- executables/nr-softmodem.c | 5 +++-- openair2/RRC/NR/rrc_gNB_nsa.c | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/executables/nr-softmodem.c b/executables/nr-softmodem.c index c659ca5502..04ebe8f562 100644 --- a/executables/nr-softmodem.c +++ b/executables/nr-softmodem.c @@ -402,7 +402,7 @@ int create_gNB_tasks(uint32_t gnb_nb) { } - if (EPC_MODE_ENABLED) { + if (EPC_MODE_ENABLED && get_softmodem_params()->phy_test<0) { if (gnb_nb > 0) { /*if (itti_create_task (TASK_SCTP, sctp_eNB_task, NULL) < 0) { LOG_E(SCTP, "Create task for SCTP failed\n"); @@ -413,6 +413,7 @@ int create_gNB_tasks(uint32_t gnb_nb) { LOG_E(S1AP, "Create task for S1AP failed\n"); return -1; }*/ + if(!emulate_rf){ if (itti_create_task (TASK_UDP, udp_eNB_task, NULL) < 0) { LOG_E(UDP_, "Create task for UDP failed\n"); @@ -827,7 +828,7 @@ int main( int argc, char **argv ) } openair0_cfg[0].threequarter_fs = threequarter_fs; - EPC_MODE_ENABLED = !IS_SOFTMODEM_NOS1; + EPC_MODE_ENABLED = !IS_SOFTMODEM_NOS1; //!get_softmodem_params()->phy_test; #if T_TRACER T_Config_Init(); diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c index e71843944e..afd5404d29 100644 --- a/openair2/RRC/NR/rrc_gNB_nsa.c +++ b/openair2/RRC/NR/rrc_gNB_nsa.c @@ -111,8 +111,6 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_ msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ_ACK); gtpv1u_enb_create_tunnel_req_t create_tunnel_req; gtpv1u_enb_create_tunnel_resp_t create_tunnel_resp; - uint8_t inde_list[m->nb_e_rabs_tobeadded]; - memset(inde_list, 0, m->nb_e_rabs_tobeadded*sizeof(uint8_t)); protocol_ctxt_t ctxt; // NR RRCReconfiguration @@ -143,6 +141,9 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_ generate_CG_Config(rrc,CG_Config,ue_context_p->ue_context.reconfig,ue_context_p->ue_context.rb_config); if(m!=NULL){ + uint8_t inde_list[m->nb_e_rabs_tobeadded]; + memset(inde_list, 0, m->nb_e_rabs_tobeadded*sizeof(uint8_t)); + if (m->nb_e_rabs_tobeadded>0){ for (int i=0; inb_e_rabs_tobeadded; i++){ // Add the new E-RABs at the corresponding rrc ue context of the gNB From 374610dbe256459ba2fdab5e3e4f4fe2adb9fa0c Mon Sep 17 00:00:00 2001 From: matzakos Date: Mon, 6 Apr 2020 09:20:25 +0200 Subject: [PATCH 141/553] ENDC path switch procedures: Small correction --- executables/nr-softmodem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/executables/nr-softmodem.c b/executables/nr-softmodem.c index 04ebe8f562..307c6ff711 100644 --- a/executables/nr-softmodem.c +++ b/executables/nr-softmodem.c @@ -402,7 +402,7 @@ int create_gNB_tasks(uint32_t gnb_nb) { } - if (EPC_MODE_ENABLED && get_softmodem_params()->phy_test<0) { + if (EPC_MODE_ENABLED && get_softmodem_params()->phy_test<1) { if (gnb_nb > 0) { /*if (itti_create_task (TASK_SCTP, sctp_eNB_task, NULL) < 0) { LOG_E(SCTP, "Create task for SCTP failed\n"); From 614c4ab6bdad9a710c758f22f2b9bd9eecabec5d Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Mon, 6 Apr 2020 10:53:48 +0200 Subject: [PATCH 142/553] adding do_ra flag into new statement --- executables/nr-softmodem.c | 49 ++++++++++++++++++-------------------- 1 file changed, 23 insertions(+), 26 deletions(-) diff --git a/executables/nr-softmodem.c b/executables/nr-softmodem.c index 51c8cc1ab0..5efe56115d 100644 --- a/executables/nr-softmodem.c +++ b/executables/nr-softmodem.c @@ -401,34 +401,31 @@ int create_gNB_tasks(uint32_t gnb_nb) { } } - - if (EPC_MODE_ENABLED && get_softmodem_params()->phy_test<0) { - if (gnb_nb > 0) { - /*if (itti_create_task (TASK_SCTP, sctp_eNB_task, NULL) < 0) { - LOG_E(SCTP, "Create task for SCTP failed\n"); - return -1; - } - - if (itti_create_task (TASK_S1AP, s1ap_eNB_task, NULL) < 0) { - LOG_E(S1AP, "Create task for S1AP failed\n"); - return -1; - }*/ - - if(!emulate_rf){ - if (itti_create_task (TASK_UDP, udp_eNB_task, NULL) < 0) { - LOG_E(UDP_, "Create task for UDP failed\n"); - return -1; - } - } - - if (itti_create_task (TASK_GTPV1_U, >pv1u_eNB_task, NULL) < 0) { - LOG_E(GTPU, "Create task for GTPV1U failed\n"); - return -1; - } - + if (EPC_MODE_ENABLED && (get_softmodem_params()->phy_test==0 && get_softmodem_params()->do_ra==0)) { + if (gnb_nb > 0) { + /*if (itti_create_task (TASK_SCTP, sctp_eNB_task, NULL) < 0) { + LOG_E(SCTP, "Create task for SCTP failed\n"); + return -1; } - } + if (itti_create_task (TASK_S1AP, s1ap_eNB_task, NULL) < 0) { + LOG_E(S1AP, "Create task for S1AP failed\n"); + return -1; + }*/ + + if(!emulate_rf){ + if (itti_create_task (TASK_UDP, udp_eNB_task, NULL) < 0) { + LOG_E(UDP_, "Create task for UDP failed\n"); + return -1; + } + } + + if (itti_create_task (TASK_GTPV1_U, >pv1u_eNB_task, NULL) < 0) { + LOG_E(GTPU, "Create task for GTPV1U failed\n"); + return -1; + } + } + } if (gnb_nb > 0) { From 40bd00aa4bd0ef9a68f5239fda869dddb633f6f0 Mon Sep 17 00:00:00 2001 From: Thomas Schlichter Date: Mon, 6 Apr 2020 12:47:37 +0200 Subject: [PATCH 143/553] Add nr_prachsim to CI --- ci-scripts/oai-ci-vm-tool | 2 +- cmake_targets/autotests/README.txt | 12 ++++++++---- cmake_targets/autotests/test_case_list.xml | 20 ++++++++++++++++++++ openair1/SIMULATION/NR_PHY/prachsim.c | 11 +++++++---- 4 files changed, 36 insertions(+), 9 deletions(-) diff --git a/ci-scripts/oai-ci-vm-tool b/ci-scripts/oai-ci-vm-tool index 9d6349077f..3fa91b862c 100755 --- a/ci-scripts/oai-ci-vm-tool +++ b/ci-scripts/oai-ci-vm-tool @@ -186,7 +186,7 @@ function variant__v3__phy_sim { BUILD_OPTIONS="--phy_simulators" VM_MEMORY=8192 VM_DISK=20 - RUN_OPTIONS="./run_exec_autotests.bash -g \"01510* 015111\" -q -np -b" + RUN_OPTIONS="./run_exec_autotests.bash -g \"01510* 015111 015112\" -q -np -b" } function variant__v4__cppcheck { diff --git a/cmake_targets/autotests/README.txt b/cmake_targets/autotests/README.txt index 10c14fd59a..19a333c626 100644 --- a/cmake_targets/autotests/README.txt +++ b/cmake_targets/autotests/README.txt @@ -142,10 +142,14 @@ Obj.# Case# Test# Description (Test 11: 10 MHz, R7.FDD (MCS 25), EVA5, 17.7dB (70%)) (TM2 Test 1 10 MHz, R.11 FDD (MCS 14), EVA5, 6.8 dB (70%)), (TM2 Test 1b 20 MHz, R.11-2 FDD (MCS 13), EVA5, 5.9 dB (70%)), -01 51 11 nr_ulsim Test cases. (Test1: MCS 9), - (Test2: MCS 16), - (Test3: MCS 28) - +01 51 11 nr_ulsim Test cases. (Test1: MCS 9 106 PRBs), + (Test2: MCS 16 50 PRBs), + (Test3: MCS 28 50 PRBs), + (Test4: MCS 9 217 PRBs), + (Test5: MCS 9 273 PRBs) +01 51 12 nr_prachsim Test cases.(Test1: 106 PRBs), + (Test2: 217 PRBs), + (Test3: 273 PRBs) diff --git a/cmake_targets/autotests/test_case_list.xml b/cmake_targets/autotests/test_case_list.xml index b3954db1fd..5b8e5db1ab 100644 --- a/cmake_targets/autotests/test_case_list.xml +++ b/cmake_targets/autotests/test_case_list.xml @@ -1259,6 +1259,26 @@ 3 + + execution + nr_prachsim Test cases. (Test1: 106 PRBs), + (Test2: 217 PRBs), + (Test3: 273 PRBs) + + $OPENAIR_DIR/cmake_targets/build_oai + --phy_simulators -c + $OPENAIR_DIR/cmake_targets/autotests/tools/free_mem.bash + + $OPENAIR_DIR/targets/bin/nr_prachsim.Rel15 + -a -s -30 -n 100 -p 16 -R 106 + -a -s -30 -n 100 -p 16 -R 217 + -a -s -30 -n 100 -p 16 -R 273 + nr_prachsim.test1 nr_prachsim.test2 nr_prachsim.test3 + PRACH test OK + segmentation fault|assertion|exiting|fatal + 3 + + lte-softmodem diff --git a/openair1/SIMULATION/NR_PHY/prachsim.c b/openair1/SIMULATION/NR_PHY/prachsim.c index 47f3dd70aa..aed7eb4505 100644 --- a/openair1/SIMULATION/NR_PHY/prachsim.c +++ b/openair1/SIMULATION/NR_PHY/prachsim.c @@ -617,7 +617,7 @@ int main(int argc, char **argv){ rx_prach_start = subframe*frame_parms->get_samples_per_slot(subframe,frame_parms); - for (SNR=snr0; SNR Date: Mon, 6 Apr 2020 19:06:58 +0200 Subject: [PATCH 144/553] Fix ULSCH traffic generation at UE side. Still not received at gNB --- openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c | 38 ++++++++++----------- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 2 +- openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c | 2 +- 3 files changed, 21 insertions(+), 21 deletions(-) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c index f262400f5d..c55a084b8a 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c @@ -178,23 +178,14 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, if (harq_process_ul_ue != NULL){ data_existing = 0; - - if (IS_SOFTMODEM_NOS1){ - data_existing = nr_ue_get_sdu(UE->Mod_id, UE->CC_id, frame, - slot, 0, ulsch_input_buffer, harq_process_ul_ue->TBS/8, &access_mode); - //IP traffic to be transmitted - if(data_existing){ - //harq_process_ul_ue->a = (unsigned char*)calloc(harq_process_ul_ue->TBS/8, sizeof(unsigned char)); - memcpy(harq_process_ul_ue->a, ulsch_input_buffer, harq_process_ul_ue->TBS/8); - - #ifdef DEBUG_MAC_PDU - LOG_I(PHY, "Printing MAC PDU to be encoded, TBS is: %d \n", harq_process_ul_ue->TBS/8); - for (i = 0; i < harq_process_ul_ue->TBS / 8; i++) { - printf("0x%02x",harq_process_ul_ue->a[i]); - } - printf("\n"); - #endif - } + if (IS_SOFTMODEM_NOS1){ + data_existing = nr_ue_get_sdu(UE->Mod_id, UE->CC_id, frame, + slot, 0, ulsch_input_buffer, harq_process_ul_ue->TBS/8, &access_mode); + //IP traffic to be transmitted + if(data_existing){ + //harq_process_ul_ue->a = (unsigned char*)calloc(harq_process_ul_ue->TBS/8, sizeof(unsigned char)); + memcpy(harq_process_ul_ue->a, ulsch_input_buffer, harq_process_ul_ue->TBS/8); + } } //Random traffic to be transmitted if there is no IP traffic available for this Tx opportunity if (!IS_SOFTMODEM_NOS1 || !data_existing) { @@ -202,15 +193,24 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, //and block this traffic from being forwarded to the upper layers at the gNB uint16_t payload_offset = 5; LOG_D(PHY, "Random data to be tranmsitted: \n"); - //Give the header bytes some dummy value in order to block the random packet at the MAC layer of the receiver + + //Give the header bytes a dummy value (a value not corresponding to any valid LCID based on 38.321, Table 6.2.1-2) + //in order to block the random packet at the MAC layer of the receiver for (i = 0; ia[i] = 0; + harq_process_ul_ue->a[i] = 64; for (i = payload_offset; i < harq_process_ul_ue->TBS / 8; i++) { harq_process_ul_ue->a[i] = (unsigned char) rand(); //printf(" input encoder a[%d]=0x%02x\n",i,harq_process_ul_ue->a[i]); } } + #ifdef DEBUG_MAC_PDU + LOG_I(PHY, "Printing MAC PDU to be encoded, TBS is: %d \n", harq_process_ul_ue->TBS/8); + for (i = 0; i < harq_process_ul_ue->TBS / 8; i++) { + printf("0x%02x",harq_process_ul_ue->a[i]); + } + printf("\n"); + #endif } else { LOG_E(PHY, "[phy_procedures_nrUE_TX] harq_process_ul_ue is NULL !!\n"); return; diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 9be9fe8424..b7922993cf 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -2243,7 +2243,7 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, start_meas(&ue->phy_proc_tx); #endif - if (ue->UE_mode[gNB_id] == PUSCH ){ + if (ue->UE_mode[gNB_id] == PUSCH || get_softmodem_params()->phy_test == 1){ nr_ue_ulsch_procedures(ue, harq_pid, frame_tx, slot_tx, thread_id, gNB_id); /* diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c index 0d04a0ae93..87ddd97366 100644 --- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c @@ -122,7 +122,7 @@ int nr_ue_ul_indication(nr_uplink_indication_t *ul_info){ ul_info->frame_tx, ul_info->slot_tx); - if (is_nr_UL_slot(mac->scc, ul_info->slot_tx)) + if (is_nr_UL_slot(mac->scc, ul_info->slot_tx) && get_softmodem_params()->do_ra) nr_ue_prach_scheduler(module_id, ul_info->frame_tx, ul_info->slot_tx); switch(ret){ From 1e63219bbfacd9cb2872338123d5ca8c74491e2e Mon Sep 17 00:00:00 2001 From: cig Date: Mon, 6 Apr 2020 19:51:56 +0200 Subject: [PATCH 145/553] Fixed bugs in UE RA procedures: - number or RA preambles unitialised - power ramp counter not incrementing - segmentation fault due to wrong pointer initialisation --- openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c index 3fe23d8127..61f1756717 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -124,7 +124,10 @@ void nr_get_prach_resources(module_id_t mod_id, rach_ConfigGeneric = &nr_rach_ConfigCommon->rach_ConfigGeneric; Msg3_size = mac->RA_Msg3_size; - numberOfRA_Preambles = *nr_rach_ConfigCommon->totalNumberOfRA_Preambles; + + numberOfRA_Preambles = 64; + if(nr_rach_ConfigCommon->totalNumberOfRA_Preambles != NULL) + numberOfRA_Preambles = *(nr_rach_ConfigCommon->totalNumberOfRA_Preambles); if (!nr_rach_ConfigCommon->groupBconfigured) { noGroupB = 1; @@ -249,7 +252,7 @@ void nr_get_prach_resources(module_id_t mod_id, // - Extend RA_rnti computation (e.g. f_id selection, ul_carrier_id are hardcoded) if (mac->RA_PREAMBLE_TRANSMISSION_COUNTER > 1) - mac->RA_PREAMBLE_TRANSMISSION_COUNTER++; + mac->RA_PREAMBLE_POWER_RAMPING_COUNTER++; prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = nr_get_Po_NOMINAL_PUSCH(prach_resources, mod_id, CC_id); @@ -409,7 +412,7 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, num_sdus = 1; post_padding = 1; - if (!IS_SOFTMODEM_NOS1){ + if (IS_SOFTMODEM_NOS1){ // initialisation by RRC // CCCH PDU mac_sdus = &payload[sizeof(NR_MAC_SUBHEADER_SHORT)]; @@ -423,10 +426,12 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, // 0); LOG_D(MAC,"[UE %d] Frame %d: Requested RRCConnectionRequest, got %d bytes\n", mod_id, frame, size_sdu); } else { + uint8_t sdus[MAX_NR_ULSCH_PAYLOAD_BYTES]; // fill ulsch_buffer with random data for (int i = 0; i < TBS_bytes; i++){ - mac_sdus[i] = (unsigned char) (lrand48()&0xff); + sdus[i] = (unsigned char) (lrand48()&0xff); } + mac_sdus = sdus; //Sending SDUs with size 1 //Initialize elements of sdu_lcids and sdu_lengths sdu_lcids[0] = lcid; From 690176821de324fa88f749b1d08124977295cdc8 Mon Sep 17 00:00:00 2001 From: Thomas Schlichter Date: Tue, 7 Apr 2020 13:31:14 +0200 Subject: [PATCH 146/553] make mac_sdus an array instead of a pointer --- openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c index 61f1756717..75091d49e2 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -334,7 +334,8 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, int nr_tti_tx){ NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); - uint8_t lcid = UL_SCH_LCID_CCCH_MSG3, *mac_sdus, *payload, ra_ResponseWindow; + uint8_t mac_sdus[MAX_NR_ULSCH_PAYLOAD_BYTES]; + uint8_t lcid = UL_SCH_LCID_CCCH_MSG3, *payload, ra_ResponseWindow; uint8_t config_index, mu; int is_nr_prach_slot; uint16_t size_sdu = 0; @@ -412,10 +413,9 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, num_sdus = 1; post_padding = 1; - if (IS_SOFTMODEM_NOS1){ + if (0){ // initialisation by RRC // CCCH PDU - mac_sdus = &payload[sizeof(NR_MAC_SUBHEADER_SHORT)]; // size_sdu = (uint16_t) mac_rrc_data_req_ue(mod_id, // CC_id, // frame, @@ -426,12 +426,10 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, // 0); LOG_D(MAC,"[UE %d] Frame %d: Requested RRCConnectionRequest, got %d bytes\n", mod_id, frame, size_sdu); } else { - uint8_t sdus[MAX_NR_ULSCH_PAYLOAD_BYTES]; // fill ulsch_buffer with random data for (int i = 0; i < TBS_bytes; i++){ - sdus[i] = (unsigned char) (lrand48()&0xff); + mac_sdus[i] = (unsigned char) (lrand48()&0xff); } - mac_sdus = sdus; //Sending SDUs with size 1 //Initialize elements of sdu_lcids and sdu_lengths sdu_lcids[0] = lcid; From 20f5e27e50e18b47d31579e90e76a1765122a301 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Tue, 7 Apr 2020 17:24:55 +0200 Subject: [PATCH 147/553] filling dci pdu --- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 90 ++++++++++++------- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 37 +++++--- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 87 +++++++++++++----- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 11 ++- 4 files changed, 157 insertions(+), 68 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index 928da7c0fa..fc9322c54b 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -537,24 +537,38 @@ uint8_t getNRBG(uint16_t bwp_size, uint16_t bwp_start, long rbg_size_config) { uint8_t getAntPortBitWidth(NR_SetupRelease_DMRS_DownlinkConfig_t *typeA, NR_SetupRelease_DMRS_DownlinkConfig_t *typeB) { - uint8_t nbitsA, nbitsB, nbits = 0; - if (typeA != NULL) nbitsA = (typeA->choice.setup->maxLength[0]==0) ? 4 : 5; - if (typeB != NULL) nbitsB = (typeB->choice.setup->maxLength[0]==0) ? 5 : 6; - if ((typeA != NULL) && (typeB != NULL)) nbits = (nbitsA > nbitsB) ? nbitsA : nbitsB; + uint8_t nbitsA = 0; + uint8_t nbitsB = 0; + uint8_t type,length,nbits; + if (typeA != NULL) { + type = (typeA->choice.setup->dmrs_Type==NULL) ? 1:2; + length = (typeA->choice.setup->maxLength==NULL) ? 1:2; + nbitsA = type + length + 2; + if (typeB == NULL) return nbitsA; + } + if (typeB != NULL) { + type = (typeB->choice.setup->dmrs_Type==NULL) ? 1:2; + length = (typeB->choice.setup->maxLength==NULL) ? 1:2; + nbitsB = type + length + 2; + if (typeA == NULL) return nbitsB; + } + + nbits = (nbitsA > nbitsB) ? nbitsA : nbitsB; return nbits; } uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, - dci_pdu_rel15_t *dci_pdu, - nr_dci_format_t format, + dci_pdu_rel15_t *dci_pdu, + nr_dci_format_t format, nr_rnti_type_t rnti_type, - uint16_t N_RB) { + uint16_t N_RB, + int bwp_id) { - NR_PDSCH_Config_t *pdsch_config = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup; uint16_t size = 0; - int bwp_id = 1; NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; + NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[bwp_id-1]; + NR_PDSCH_Config_t *pdsch_config = bwp->bwp_Dedicated->pdsch_Config->choice.setup; switch(format) { /*Only sizes for 0_0 and 1_0 are correct at the moment*/ @@ -562,7 +576,7 @@ uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, /// fixed: Format identifier 1, Hop flag 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2 Time Domain assgnmt 4 --20 size += 20; size += (uint8_t)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); // Freq domain assignment -- hopping scenario to be updated - size += nr_dci_size(secondaryCellGroup,dci_pdu,NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB) - size; // Padding to match 1_0 size + size += nr_dci_size(secondaryCellGroup,dci_pdu,NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB, bwp_id) - size; // Padding to match 1_0 size // UL/SUL indicator assumed to be 0 break; @@ -604,7 +618,10 @@ uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, } // BWP Indicator uint8_t n_dl_bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count; - dci_pdu->bwp_indicator.nbits = (uint8_t)((n_dl_bwp < 4) ? ceil(log2(n_dl_bwp+1)) : ceil(log2(n_dl_bwp))); + if (n_dl_bwp < 2) + dci_pdu->bwp_indicator.nbits = n_dl_bwp; + else + dci_pdu->bwp_indicator.nbits = 2; size += dci_pdu->bwp_indicator.nbits; // Freq domain assignment long rbg_size_config = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rbg_Size; @@ -618,49 +635,52 @@ uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, else dci_pdu->frequency_domain_assignment.nbits = ((int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )>numRBG) ? (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )+1 : numRBG+1; size += dci_pdu->frequency_domain_assignment.nbits; - // Time domain assignment - NR_PDSCH_TimeDomainResourceAllocationList_t *pdsch_timeDomList = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[0]->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList; + // Time domain assignment (see table 5.1.2.1.1-1 in 38.214 int num_entries; - if (pdsch_timeDomList != NULL) - num_entries = pdsch_timeDomList->list.count; + if (pdsch_config->pdsch_TimeDomainAllocationList==NULL) { + if (bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList==NULL) + num_entries = 16; // num of entries in default table + else + num_entries = bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count; + } else - num_entries = 16; // num of entries in default table + num_entries = pdsch_config->pdsch_TimeDomainAllocationList->choice.setup->list.count; dci_pdu->time_domain_assignment.nbits = (int)ceil(log2(num_entries)); size += dci_pdu->time_domain_assignment.nbits; - // VRB to PRB mapping + // VRB to PRB mapping FIXME (38.212 also says 0 bits if not configured by higher layers if (pdsch_config->resourceAllocation == 1) { dci_pdu->vrb_to_prb_mapping.nbits = 1; size += dci_pdu->vrb_to_prb_mapping.nbits; } // PRB bundling size indicator - if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.present == 2) { + if (pdsch_config->prb_BundlingType.present == NR_PDSCH_Config__prb_BundlingType_PR_dynamicBundling) { dci_pdu->prb_bundling_size_indicator.nbits = 1; size += dci_pdu->prb_bundling_size_indicator.nbits; } // Rate matching indicator - NR_RateMatchPatternGroup_t *group1 = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup1; - NR_RateMatchPatternGroup_t *group2 = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup2; + NR_RateMatchPatternGroup_t *group1 = pdsch_config->rateMatchPatternGroup1; + NR_RateMatchPatternGroup_t *group2 = pdsch_config->rateMatchPatternGroup2; if ((group1 != NULL) && (group2 != NULL)) dci_pdu->rate_matching_indicator.nbits = 2; if ((group1 != NULL) != (group2 != NULL)) dci_pdu->rate_matching_indicator.nbits = 1; size += dci_pdu->rate_matching_indicator.nbits; // ZP CSI-RS trigger - uint8_t nZP = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList->list.count; + uint8_t nZP = pdsch_config->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList->list.count; dci_pdu->zp_csi_rs_trigger.nbits = (int)ceil(log2(nZP+1)); size += dci_pdu->zp_csi_rs_trigger.nbits; // TB1- MCS 5, NDI 1, RV 2 size += 8; // TB2 - long *maxCWperDCI = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI; + long *maxCWperDCI = pdsch_config->maxNrofCodeWordsScheduledByDCI; if ((maxCWperDCI != NULL) && (*maxCWperDCI == 2)) { size += 8; } // HARQ PID size += 4; // DAI - if (secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook == 1) { // at this point the UE has multiple serving cells - dci_pdu->dai[0].nbits = 4; + if (secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook == NR_PhysicalCellGroupConfig__pdsch_HARQ_ACK_Codebook_dynamic) { // FIXME in case of more than one serving cell + dci_pdu->dai[0].nbits = 2; size += dci_pdu->dai[0].nbits; } // TPC PUCCH @@ -668,32 +688,34 @@ uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, // PUCCH resource indicator size += 3; // PDSCH to HARQ timing indicator - uint8_t I = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[0]->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK->list.count; + uint8_t I = ubwp->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK->list.count; dci_pdu->pdsch_to_harq_feedback_timing_indicator.nbits = (int)ceil(log2(I)); size += dci_pdu->pdsch_to_harq_feedback_timing_indicator.nbits; // Antenna ports - NR_SetupRelease_DMRS_DownlinkConfig_t *typeA = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA; - NR_SetupRelease_DMRS_DownlinkConfig_t *typeB = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeB; + NR_SetupRelease_DMRS_DownlinkConfig_t *typeA = pdsch_config->dmrs_DownlinkForPDSCH_MappingTypeA; + NR_SetupRelease_DMRS_DownlinkConfig_t *typeB = pdsch_config->dmrs_DownlinkForPDSCH_MappingTypeB; dci_pdu->antenna_ports.nbits = getAntPortBitWidth(typeA,typeB); size += dci_pdu->antenna_ports.nbits; // Tx Config Indication - long *isTciEnable = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[0]->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[0]->tci_PresentInDCI; + long *isTciEnable = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[bwp_id-1]->tci_PresentInDCI; if (isTciEnable != NULL) { dci_pdu->transmission_configuration_indication.nbits = 3; size += dci_pdu->transmission_configuration_indication.nbits; } // SRS request - if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig==NULL) + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->supplementaryUplink==NULL) dci_pdu->srs_request.nbits = 2; else dci_pdu->srs_request.nbits = 3; size += dci_pdu->srs_request.nbits; // CBGTI - uint8_t maxCBGperTB = (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission->choice.setup->maxCodeBlockGroupsPerTransportBlock + 1) * 2; - long *maxCWperDCI_rrc = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI; - uint8_t maxCW = (maxCWperDCI_rrc == NULL) ? 1 : *maxCWperDCI_rrc; - dci_pdu->cbgti.nbits = maxCBGperTB * maxCW; - size += dci_pdu->cbgti.nbits; + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission != NULL) { + uint8_t maxCBGperTB = (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission->choice.setup->maxCodeBlockGroupsPerTransportBlock + 1) * 2; + long *maxCWperDCI_rrc = pdsch_config->maxNrofCodeWordsScheduledByDCI; + uint8_t maxCW = (maxCWperDCI_rrc == NULL) ? 1 : *maxCWperDCI_rrc; + dci_pdu->cbgti.nbits = maxCBGperTB * maxCW; + size += dci_pdu->cbgti.nbits; + } // CBGFI if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission->choice.setup->codeBlockGroupFlushIndicator) { dci_pdu->cbgfi.nbits = 1; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 87371760d5..11c083ea3f 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -267,7 +267,7 @@ int configure_fapi_dl_pdu(int Mod_idP, nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu; int TBS; - int bwp_id=1; + bwp_id=1; int UE_id = 0; NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list; @@ -343,24 +343,37 @@ int configure_fapi_dl_pdu(int Mod_idP, dci_pdu_rel15_t *dci_pdu_rel15 = calloc(MAX_DCI_CORESET,sizeof(dci_pdu_rel15)); - dci_pdu_rel15[0].frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize, - pdsch_pdu_rel15->rbStart, - NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275)); + // bwp indicator + int n_dl_bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count; + if (n_dl_bwp < 4) + dci_pdu_rel15[0].bwp_indicator.val = bwp_id; + else + dci_pdu_rel15[0].bwp_indicator.val = bwp_id - 1; // as per table 7.3.1.1.2-1 in 38.212 + // frequency domain assignment + if (bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation==NR_PDSCH_Config__resourceAllocation_resourceAllocationType1) + dci_pdu_rel15[0].frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize, + pdsch_pdu_rel15->rbStart, + NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275)); + else + AssertFatal(1==0,"Only frequency resource allocation type 1 is currently supported\n"); + // time domain assignment dci_pdu_rel15[0].time_domain_assignment.val = time_domain_assignment; // row index used here instead of SLIV; - dci_pdu_rel15[0].vrb_to_prb_mapping.val = 1; + // mcs ndi and rv dci_pdu_rel15[0].mcs = pdsch_pdu_rel15->mcsIndex[0]; - dci_pdu_rel15[0].tb_scaling = 1; - - dci_pdu_rel15[0].ra_preamble_index = 25; - dci_pdu_rel15[0].format_indicator = 1; dci_pdu_rel15[0].ndi = 1; dci_pdu_rel15[0].rv = 0; + // harq pid dci_pdu_rel15[0].harq_pid = 0; + // DAI dci_pdu_rel15[0].dai[0].val = (pucch_sched->dai_c-1)&3; - dci_pdu_rel15[0].tpc = 2; + // TPC for PUCCH + dci_pdu_rel15[0].tpc = 1; // table 7.2.1-1 in 38.213 + // PUCCH resource indicator dci_pdu_rel15[0].pucch_resource_indicator = pucch_sched->resource_indicator; + // PDSCH to HARQ TI dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator.val = pucch_sched->timing_indicator; - + // antenna ports + dci_pdu_rel15[0].antenna_ports.val = 0; // nb of cdm groups w/o data 1 and dmrs port 0 LOG_D(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n", dci_pdu_rel15[0].frequency_domain_assignment.val, @@ -392,7 +405,7 @@ int configure_fapi_dl_pdu(int Mod_idP, dci_formats[0] = NR_DL_DCI_FORMAT_1_0; rnti_types[0] = NR_RNTI_C; - fill_dci_pdu_rel15(secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types); + fill_dci_pdu_rel15(secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types,bwp_id); LOG_D(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \ coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n", diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 0feca3a863..996a75d1fc 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -544,24 +544,7 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, } } -void prepare_dci(NR_CellGroupConfig_t *secondaryCellGroup, - dci_pdu_rel15_t *dci_pdu_rel15, - nr_dci_format_t format) { - switch(format) { - case NR_DL_DCI_FORMAT_1_1: - //carrier indicator - //bwp indicator - //vrb to prb mapping - //bundling size indicator - //rate matching indicator - //ZP CSI-RS trigger - //dai - //antenna ports - //srs resource set - break; - } -} // This function configures pucch pdu fapi structure void nr_configure_pucch(nfapi_nr_pucch_pdu_t* pucch_pdu, @@ -747,11 +730,75 @@ void nr_configure_pucch(nfapi_nr_pucch_pdu_t* pucch_pdu, } + +void prepare_dci(NR_CellGroupConfig_t *secondaryCellGroup, + dci_pdu_rel15_t *dci_pdu_rel15, + nr_dci_format_t format, + int bwp_id) { + + NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; + + switch(format) { + case NR_DL_DCI_FORMAT_1_1: + // format indicator + dci_pdu_rel15->format_indicator = 1; + // carrier indicator + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig != NULL) + AssertFatal(1==0,"Cross Carrier Scheduling Config currently not supported\n"); + //vrb to prb mapping + if (bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver==NULL) + dci_pdu_rel15->vrb_to_prb_mapping.val = 0; + else + dci_pdu_rel15->vrb_to_prb_mapping.val = 1; + //bundling size indicator + if (bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.present == NR_PDSCH_Config__prb_BundlingType_PR_dynamicBundling) + AssertFatal(1==0,"Dynamic PRB bundling type currently not supported\n"); + //rate matching indicator + uint16_t msb = (bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup1==NULL)?0:1; + uint16_t lsb = (bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup2==NULL)?0:1; + dci_pdu_rel15->rate_matching_indicator.val = lsb | (msb<<1); + // aperiodic ZP CSI-RS trigger + if (bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList != NULL) + AssertFatal(1==0,"Aperiodic ZP CSI-RS currently not supported\n"); + // transmission configuration indication + if (bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[bwp_id-1]->tci_PresentInDCI != NULL) + AssertFatal(1==0,"TCI in DCI currently not supported\n"); + //srs resource set + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->carrierSwitching!=NULL) { + NR_SRS_CarrierSwitching_t *cs = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->carrierSwitching->choice.setup; + if (cs->srs_TPC_PDCCH_Group!=NULL){ + switch(cs->srs_TPC_PDCCH_Group->present) { + case NR_SRS_CarrierSwitching__srs_TPC_PDCCH_Group_PR_NOTHING: + dci_pdu_rel15->srs_request.val = 0; + break; + case NR_SRS_CarrierSwitching__srs_TPC_PDCCH_Group_PR_typeA: + AssertFatal(1==0,"SRS TPC PRCCH group type A currently not supported\n"); + break; + case NR_SRS_CarrierSwitching__srs_TPC_PDCCH_Group_PR_typeB: + AssertFatal(1==0,"SRS TPC PRCCH group type B currently not supported\n"); + break; + } + } + else + dci_pdu_rel15->srs_request.val = 0; + } + else + dci_pdu_rel15->srs_request.val = 0; + // CBGTI and CBGFI + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission != NULL) + AssertFatal(1==0,"CBG transmission currently not supported\n"); + // dmrs sequence initialization + dci_pdu_rel15->dmrs_sequence_initialization = 0; // FIXME no information on what this bit should be in 38.212 + break; + } +} + void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, - int *rnti_types) { + int *rnti_types, + int bwp_id) { uint16_t N_RB = pdcch_pdu_rel15->BWPSize; uint8_t fsize=0, pos=0; @@ -760,10 +807,10 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, for (int d=0;dnumDlDci;d++) { uint64_t *dci_pdu = (uint64_t *)pdcch_pdu_rel15->Payload[d]; - int dci_size = nr_dci_size(secondaryCellGroup,&dci_pdu_rel15[d],dci_formats[d],rnti_types[d],pdcch_pdu_rel15->BWPSize); + int dci_size = nr_dci_size(secondaryCellGroup,&dci_pdu_rel15[d],dci_formats[d],rnti_types[d],pdcch_pdu_rel15->BWPSize,bwp_id); pdcch_pdu_rel15->PayloadSizeBits[d] = dci_size; AssertFatal(pdcch_pdu_rel15->PayloadSizeBits[d]<=64, "DCI sizes above 64 bits not yet supported"); - prepare_dci(secondaryCellGroup,&dci_pdu_rel15[d],dci_formats[d]); + prepare_dci(secondaryCellGroup,&dci_pdu_rel15[d],dci_formats[d],bwp_id); pos = 0; /// Payload generation diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index 3fcd8d5482..a6cd3b1869 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -151,7 +151,13 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, - int *rnti_types); + int *rnti_types, + int bwp_id); + +void prepare_dci(NR_CellGroupConfig_t *secondaryCellGroup, + dci_pdu_rel15_t *dci_pdu_rel15, + nr_dci_format_t format, + int bwp_id); void nr_configure_pucch(nfapi_nr_pucch_pdu_t* pucch_pdu, NR_ServingCellConfigCommon_t *scc, @@ -194,7 +200,8 @@ uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, dci_pdu_rel15_t *dci_pdu, nr_dci_format_t format, nr_rnti_type_t rnti_type, - uint16_t N_RB); + uint16_t N_RB, + int bwp_id); int allocate_nr_CCEs(gNB_MAC_INST *nr_mac, int bwp_id, From ac2d1d79d70d2fbe96064c845b639ee863c86bfa Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Tue, 7 Apr 2020 17:38:31 +0200 Subject: [PATCH 148/553] minor fixes --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 4 ++-- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 11c083ea3f..23c43cda9c 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -267,7 +267,7 @@ int configure_fapi_dl_pdu(int Mod_idP, nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu; int TBS; - bwp_id=1; + int bwp_id=1; int UE_id = 0; NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list; @@ -851,7 +851,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); - fill_dci_pdu_rel15(secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types); + fill_dci_pdu_rel15(secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types,bwp_id); } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 996a75d1fc..03480998ba 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -790,6 +790,8 @@ void prepare_dci(NR_CellGroupConfig_t *secondaryCellGroup, // dmrs sequence initialization dci_pdu_rel15->dmrs_sequence_initialization = 0; // FIXME no information on what this bit should be in 38.212 break; + default : + AssertFatal(1==0,"Prepare dci currently only implemented for 1_1 \n"); } } From 3053f37deca29cfb3238d53243e9c742262c4798 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Tue, 7 Apr 2020 18:08:22 +0200 Subject: [PATCH 149/553] added NR_CellGroupConfig to mac in UE --- openair1/SIMULATION/NR_PHY/dlsim.c | 2 +- openair1/SIMULATION/NR_PHY/ulsim.c | 2 +- openair2/LAYER2/NR_MAC_UE/config_ue.c | 14 +++++++------- openair2/LAYER2/NR_MAC_UE/mac_defs.h | 4 ++-- openair2/LAYER2/NR_MAC_UE/mac_proto.h | 2 +- openair2/LAYER2/NR_MAC_UE/main_ue_nr.c | 2 +- .../NR_MAC_UE/nr_ue_dci_configuration.c | 19 ++++++++++--------- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 6 +++--- 8 files changed, 26 insertions(+), 25 deletions(-) diff --git a/openair1/SIMULATION/NR_PHY/dlsim.c b/openair1/SIMULATION/NR_PHY/dlsim.c index ebcedbaeb0..50bfab1389 100644 --- a/openair1/SIMULATION/NR_PHY/dlsim.c +++ b/openair1/SIMULATION/NR_PHY/dlsim.c @@ -656,7 +656,7 @@ int main(int argc, char **argv) rrc.carrier.MIB = (uint8_t*) malloc(4); rrc.carrier.sizeof_MIB = do_MIB_NR(&rrc,0); - nr_rrc_mac_config_req_ue(0,0,0,rrc.carrier.mib.message.choice.mib,secondaryCellGroup->spCellConfig); + nr_rrc_mac_config_req_ue(0,0,0,rrc.carrier.mib.message.choice.mib,secondaryCellGroup); nr_dcireq_t dcireq; diff --git a/openair1/SIMULATION/NR_PHY/ulsim.c b/openair1/SIMULATION/NR_PHY/ulsim.c index 2adc67501a..dea329a36e 100644 --- a/openair1/SIMULATION/NR_PHY/ulsim.c +++ b/openair1/SIMULATION/NR_PHY/ulsim.c @@ -470,7 +470,7 @@ int main(int argc, char **argv) rrc.carrier.MIB = (uint8_t*) malloc(4); rrc.carrier.sizeof_MIB = do_MIB_NR(&rrc,0); - nr_rrc_mac_config_req_ue(0,0,0,rrc.carrier.mib.message.choice.mib,secondaryCellGroup->spCellConfig); + nr_rrc_mac_config_req_ue(0,0,0,rrc.carrier.mib.message.choice.mib,secondaryCellGroup); nr_ue_phy_config_request(&UE_mac->phy_config); diff --git a/openair2/LAYER2/NR_MAC_UE/config_ue.c b/openair2/LAYER2/NR_MAC_UE/config_ue.c index c983023034..6e214a670c 100755 --- a/openair2/LAYER2/NR_MAC_UE/config_ue.c +++ b/openair2/LAYER2/NR_MAC_UE/config_ue.c @@ -281,7 +281,7 @@ int nr_rrc_mac_config_req_ue( // NR_ServingCellConfigCommon_t *sccP, // NR_MAC_CellGroupConfig_t *mac_cell_group_configP, // NR_PhysicalCellGroupConfig_t *phy_cell_group_configP, - NR_SpCellConfig_t *spCell_ConfigP ){ + NR_CellGroupConfig_t *cell_group_config ){ NR_UE_MAC_INST_t *mac = get_mac_inst(module_id); @@ -294,15 +294,15 @@ int nr_rrc_mac_config_req_ue( } - if(spCell_ConfigP != NULL ){ - mac->servCellIndex = *spCell_ConfigP->servCellIndex; - if (spCell_ConfigP->reconfigurationWithSync) { - mac->scc = spCell_ConfigP->reconfigurationWithSync->spCellConfigCommon; + if(cell_group_config != NULL ){ + mac->servCellIndex = *cell_group_config->spCellConfig->servCellIndex; + if (cell_group_config->spCellConfig->reconfigurationWithSync) { + mac->scc = cell_group_config->spCellConfig->reconfigurationWithSync->spCellConfigCommon; config_common_ue(mac,module_id,cc_idP); - mac->crnti = spCell_ConfigP->reconfigurationWithSync->newUE_Identity; + mac->crnti = cell_group_config->spCellConfig->reconfigurationWithSync->newUE_Identity; LOG_I(MAC,"Configuring CRNTI %x\n",mac->crnti); } - mac->scd = spCell_ConfigP->spCellConfigDedicated; + mac->scg = cell_group_config; /* if(mac_cell_group_configP != NULL){ diff --git a/openair2/LAYER2/NR_MAC_UE/mac_defs.h b/openair2/LAYER2/NR_MAC_UE/mac_defs.h index 405ea95eb1..b16464fceb 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_defs.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_defs.h @@ -46,7 +46,7 @@ #include "NR_MIB.h" #include "NR_MAC-CellGroupConfig.h" #include "NR_PhysicalCellGroupConfig.h" -#include "NR_SpCellConfig.h" +#include "NR_CellGroupConfig.h" #include "NR_ServingCellConfig.h" #include "fapi_nr_ue_interface.h" #include "NR_IF_Module.h" @@ -141,7 +141,7 @@ typedef enum { typedef struct { NR_ServingCellConfigCommon_t *scc; - NR_ServingCellConfig_t *scd; + NR_CellGroupConfig_t *scg; int servCellIndex; //// MAC config NR_DRX_Config_t *drx_Config; diff --git a/openair2/LAYER2/NR_MAC_UE/mac_proto.h b/openair2/LAYER2/NR_MAC_UE/mac_proto.h index 36d285e320..0d21ff60a2 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_proto.h @@ -72,7 +72,7 @@ int nr_rrc_mac_config_req_ue( uint8_t gNB_index, NR_MIB_t *mibP, //NR_ServingCellConfigCommon_t *sccP, - NR_SpCellConfig_t *spCell_ConfigP); + NR_CellGroupConfig_t *cell_group_config); /**\brief initialization NR UE MAC instance(s), total number of MAC instance based on NB_NR_UE_MAC_INST*/ NR_UE_MAC_INST_t * nr_l2_init_ue(NR_UE_RRC_INST_t* rrc_inst); diff --git a/openair2/LAYER2/NR_MAC_UE/main_ue_nr.c b/openair2/LAYER2/NR_MAC_UE/main_ue_nr.c index 61f9ab601e..2cb9e5971d 100644 --- a/openair2/LAYER2/NR_MAC_UE/main_ue_nr.c +++ b/openair2/LAYER2/NR_MAC_UE/main_ue_nr.c @@ -52,7 +52,7 @@ NR_UE_MAC_INST_t * nr_l2_init_ue(NR_UE_RRC_INST_t* rrc_inst) //init mac here nr_ue_mac_inst = (NR_UE_MAC_INST_t *)malloc(sizeof(NR_UE_MAC_INST_t)*NB_NR_UE_MAC_INST); if (rrc_inst) { - nr_rrc_mac_config_req_ue(0,0,0,NULL,rrc_inst->cell_group_config->spCellConfig); + nr_rrc_mac_config_req_ue(0,0,0,NULL,rrc_inst->cell_group_config); if (IS_SOFTMODEM_NOS1){ if (rlc_module_init(0) != 0) { diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c index 396e06ff09..8c66ccec5f 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c @@ -62,14 +62,15 @@ void fill_dci_search_candidates(NR_SearchSpace_t *ss,fapi_nr_dl_config_dci_dl_pd void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_config,int frame,int slot) { // check if DL slot + dci_pdu_rel15_t dci_pdu_rel15; if (is_nr_DL_slot(mac->scc,slot)==1) { // get BWP 1, Coreset 0, SearchSpace 0 if (mac->DLbwp[0]==NULL) { - AssertFatal(mac->scd->downlinkBWP_ToAddModList!=NULL,"downlinkBWP_ToAddModList is null\n"); - AssertFatal(mac->scd->downlinkBWP_ToAddModList->list.count==1,"downlinkBWP_ToAddModList->list->count is %d\n", - mac->scd->downlinkBWP_ToAddModList->list.count); - mac->DLbwp[0] = mac->scd->downlinkBWP_ToAddModList->list.array[0]; + AssertFatal(mac->scg->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList!=NULL,"downlinkBWP_ToAddModList is null\n"); + AssertFatal(mac->scg->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count==1,"downlinkBWP_ToAddModList->list->count is %d\n", + mac->scg->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count); + mac->DLbwp[0] = mac->scg->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[0]; AssertFatal(mac->DLbwp[0]->bwp_Dedicated!=NULL,"bwp_Dedicated is null\n"); AssertFatal(mac->DLbwp[0]->bwp_Dedicated->pdcch_Config!=NULL,"pdcch_Config is null\n"); AssertFatal(mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList!=NULL,"controlResourceSetToAddModList is null\n"); @@ -96,10 +97,10 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_ } } if (mac->ULbwp[0]==NULL) { - AssertFatal(mac->scd->uplinkConfig->uplinkBWP_ToAddModList!=NULL,"uplinkBWP_ToAddModList is null\n"); - AssertFatal(mac->scd->uplinkConfig->uplinkBWP_ToAddModList->list.count==1,"uplinkBWP_ToAddModList->list->count is %d\n", - mac->scd->uplinkConfig->uplinkBWP_ToAddModList->list.count); - mac->ULbwp[0] = mac->scd->uplinkConfig->uplinkBWP_ToAddModList->list.array[0]; + AssertFatal(mac->scg->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList!=NULL,"uplinkBWP_ToAddModList is null\n"); + AssertFatal(mac->scg->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.count==1,"uplinkBWP_ToAddModList->list->count is %d\n", + mac->scg->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.count); + mac->ULbwp[0] = mac->scg->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[0]; AssertFatal(mac->ULbwp[0]->bwp_Dedicated!=NULL,"bwp_Dedicated is null\n"); } // check search spaces @@ -171,7 +172,7 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_ rel15->coreset.pdcch_dmrs_scrambling_id = *mac->scc->physCellId; fill_dci_search_candidates(mac->SSpace[0][0][ss_id],rel15); rel15->dci_format = NR_DL_DCI_FORMAT_1_0; - rel15->dci_length = nr_dci_size(rel15->dci_format,NR_RNTI_C,rel15->BWPSize); + rel15->dci_length = nr_dci_size(mac->scg,&dci_pdu_rel15,rel15->dci_format,NR_RNTI_C,rel15->BWPSize); dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI; dl_config->number_pdus = dl_config->number_pdus + 1; } diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 58b312038a..745a5b749b 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -658,7 +658,7 @@ NR_UE_L2_STATE_t nr_ue_scheduler(const module_id_t module_id, fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request; // check type0 from 38.213 13 if we have no CellGroupConfig - if ( mac->scd == NULL) { + if ( mac->scg == NULL) { if( ssb_index != -1){ if(mac->type0_pdcch_ss_mux_pattern == 1){ @@ -2725,10 +2725,10 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, AssertFatal(rnti_type!=-1,"no identified/handled rnti\n"); AssertFatal(mac->DLbwp[0] != NULL, "DLbwp[0] shouldn't be null here!\n"); AssertFatal(mac->ULbwp[0] != NULL, "ULbwp[0] shouldn't be null here!\n"); - int N_RB = (mac->scd != NULL) ? + int N_RB = (mac->scg != NULL) ? NRRIV2BW(mac->DLbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275) : NRRIV2BW(mac->scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth,275); - int N_RB_UL = (mac->scd != NULL) ? + int N_RB_UL = (mac->scg != NULL) ? NRRIV2BW(mac->ULbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275) : NRRIV2BW(mac->scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth,275); From 6f3934acc0e8dba5fd42fc5f0f5ea6f1afc53555 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Tue, 7 Apr 2020 18:09:07 +0200 Subject: [PATCH 150/553] moved dci_pdu_rel15_t to mac_common --- openair2/LAYER2/NR_MAC_COMMON/nr_mac.h | 64 ++++++++++++ openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 127 ------------------------ 2 files changed, 64 insertions(+), 127 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h index 5801fabcfb..fd51602e23 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h @@ -92,6 +92,70 @@ typedef struct { uint8_t TAGID:2; // octet 1 [7:6] } __attribute__ ((__packed__)) NR_MAC_CE_TA; +// DCI pdu structures. Used in UE by nr_dci_size(but not filled in UE) +typedef struct { + uint16_t val; + uint8_t nbits; +} dci_field_t; + +typedef struct { + +uint8_t format_indicator; //1 bit +uint8_t ra_preamble_index; //6 bits +uint8_t ss_pbch_index; //6 bits +uint8_t prach_mask_index; //4 bits +uint8_t mcs; //5 bits +uint8_t ndi; //1 bit +uint8_t rv; //2 bits +uint8_t harq_pid; //4 bits +uint8_t tpc; //2 bits +uint8_t short_messages_indicator; //2 bits +uint8_t short_messages; //8 bits +uint8_t tb_scaling; //2 bits +uint8_t pucch_resource_indicator; //3 bits +uint8_t dmrs_sequence_initialization; //1 bit +uint8_t system_info_indicator; //1 bit + +uint8_t slot_format_indicator_count; +uint8_t *slot_format_indicators; + +uint8_t pre_emption_indication_count; +uint16_t *pre_emption_indications; //14 bit each + +uint8_t block_number_count; +uint8_t *block_numbers; +uint8_t padding; + +dci_field_t mcs2; //variable +dci_field_t ndi2; //variable +dci_field_t rv2; //variable +dci_field_t frequency_domain_assignment; //variable +dci_field_t time_domain_assignment; //variable +dci_field_t frequency_hopping_flag; //variable +dci_field_t vrb_to_prb_mapping; //variable +dci_field_t dai[2]; //variable +dci_field_t pdsch_to_harq_feedback_timing_indicator; //variable +dci_field_t carrier_indicator; //variable +dci_field_t bwp_indicator; //variable +dci_field_t prb_bundling_size_indicator; //variable +dci_field_t rate_matching_indicator; //variable +dci_field_t zp_csi_rs_trigger; //variable +dci_field_t transmission_configuration_indication; //variable +dci_field_t srs_request; //variable +dci_field_t cbgti; //variable +dci_field_t cbgfi; //variable +dci_field_t srs_resource_indicator; //variable +dci_field_t precoding_information; //variable +dci_field_t csi_request; //variable +dci_field_t ptrs_dmrs_association; //variable +dci_field_t beta_offset_indicator; //variable +dci_field_t cloded_loop_indicator; //variable +dci_field_t ul_sul_indicator; //variable +dci_field_t antenna_ports; //variable +dci_field_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits + +} dci_pdu_rel15_t; + // 38.321 ch6.2.1, 38.331 #define DL_SCH_LCID_CCCH 0x00 #define DL_SCH_LCID_DCCH 0x01 diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index 59a8df5114..b70253733a 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -203,131 +203,4 @@ typedef struct gNB_MAC_INST_s { int cce_list[MAX_NUM_BWP][MAX_NUM_CORESET][MAX_NUM_CCE]; } gNB_MAC_INST; -/*typedef struct { - - -uint8_t format_indicator; //1 bit -uint16_t frequency_domain_assignment; //up to 16 bits -uint8_t time_domain_assignment; // 4 bits -uint8_t frequency_hopping_flag; //1 bit - -uint8_t ra_preamble_index; //6 bits -uint8_t ss_pbch_index; //6 bits -uint8_t prach_mask_index; //4 bits - -uint8_t vrb_to_prb_mapping; //0 or 1 bit -uint8_t mcs; //5 bits -uint8_t ndi; //1 bit -uint8_t rv; //2 bits -uint8_t harq_pid; //4 bits -uint8_t dai; //0, 2 or 4 bits -uint8_t dai1; //1 or 2 bits -uint8_t dai2; //0 or 2 bits -uint8_t tpc; //2 bits -uint8_t pucch_resource_indicator; //3 bits -uint8_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits - -uint8_t short_messages_indicator; //2 bits -uint8_t short_messages; //8 bits -uint8_t tb_scaling; //2 bits - -uint8_t carrier_indicator; //0 or 3 bits -uint8_t bwp_indicator; //0, 1 or 2 bits -uint8_t prb_bundling_size_indicator; //0 or 1 bits -uint8_t rate_matching_indicator; //0, 1 or 2 bits -uint8_t zp_csi_rs_trigger; //0, 1 or 2 bits -uint8_t transmission_configuration_indication; //0 or 3 bits -uint8_t srs_request; //2 bits -uint8_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits -uint8_t cbgfi; //CBG Flushing Out Information: 0 or 1 bit -uint8_t dmrs_sequence_initialization; //0 or 1 bit - -uint8_t srs_resource_indicator; -uint8_t precoding_information; -uint8_t csi_request; -uint8_t ptrs_dmrs_association; -uint8_t beta_offset_indicator; //0 or 2 bits - -uint8_t slot_format_indicator_count; -uint8_t *slot_format_indicators; - -uint8_t pre_emption_indication_count; -uint16_t *pre_emption_indications; //14 bit - -uint8_t block_number_count; -uint8_t *block_numbers; - -uint8_t ul_sul_indicator; //0 or 1 bit -uint8_t antenna_ports; - -uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits -uint16_t padding; - -} dci_pdu_rel15_t;*/ - -typedef struct { - uint16_t val; - uint8_t nbits; -} dci_field_t; - -typedef struct { - - -uint8_t format_indicator; //1 bit -uint8_t ra_preamble_index; //6 bits -uint8_t ss_pbch_index; //6 bits -uint8_t prach_mask_index; //4 bits -uint8_t mcs; //5 bits -uint8_t ndi; //1 bit -uint8_t rv; //2 bits -uint8_t harq_pid; //4 bits -uint8_t tpc; //2 bits -uint8_t short_messages_indicator; //2 bits -uint8_t short_messages; //8 bits -uint8_t tb_scaling; //2 bits -uint8_t pucch_resource_indicator; //3 bits -uint8_t dmrs_sequence_initialization; //1 bit -uint8_t system_info_indicator; //1 bit - -uint8_t slot_format_indicator_count; -uint8_t *slot_format_indicators; - -uint8_t pre_emption_indication_count; -uint16_t *pre_emption_indications; //14 bit each - -uint8_t block_number_count; -uint8_t *block_numbers; -uint8_t padding; - -dci_field_t mcs2; //variable -dci_field_t ndi2; //variable -dci_field_t rv2; //variable -dci_field_t frequency_domain_assignment; //variable -dci_field_t time_domain_assignment; //variable -dci_field_t frequency_hopping_flag; //variable -dci_field_t vrb_to_prb_mapping; //variable -dci_field_t dai[2]; //variable -dci_field_t pdsch_to_harq_feedback_timing_indicator; //variable -dci_field_t carrier_indicator; //variable -dci_field_t bwp_indicator; //variable -dci_field_t prb_bundling_size_indicator; //variable -dci_field_t rate_matching_indicator; //variable -dci_field_t zp_csi_rs_trigger; //variable -dci_field_t transmission_configuration_indication; //variable -dci_field_t srs_request; //variable -dci_field_t cbgti; //variable -dci_field_t cbgfi; //variable -dci_field_t srs_resource_indicator; //variable -dci_field_t precoding_information; //variable -dci_field_t csi_request; //variable -dci_field_t ptrs_dmrs_association; //variable -dci_field_t beta_offset_indicator; //variable -dci_field_t cloded_loop_indicator; //variable -dci_field_t ul_sul_indicator; //variable -dci_field_t antenna_ports; //variable -dci_field_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits - -} dci_pdu_rel15_t; - - #endif /*__LAYER2_NR_MAC_GNB_H__ */ From 17e3f2857c30554c3d9b4a67adeff664f4fa59cc Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Thu, 2 Apr 2020 19:38:41 +0200 Subject: [PATCH 151/553] possible fix for ghost dlsim in ci? --- cmake_targets/autotests/test_case_list.xml | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/cmake_targets/autotests/test_case_list.xml b/cmake_targets/autotests/test_case_list.xml index 5b8e5db1ab..734cf871d4 100644 --- a/cmake_targets/autotests/test_case_list.xml +++ b/cmake_targets/autotests/test_case_list.xml @@ -1104,9 +1104,8 @@ -n100 -R217 -a80 -s5 -n100 -R217 -a110 -s5 -b100 -n100 -e27 -s30 - -n100 -e16 -s10 - - nr_dlsim.test1 nr_dlsim.test2 nr_dlsim.test3 nr_dlsim.test4 nr_dlsim.test5 nr_dlsim.test6 nr_dlsim.test7 nr_dlsim.test8 nr_dlsim.test9 nr_dlsim.test10 + -n100 -e16 -s10 + nr_dlsim.test1 nr_dlsim.test2 nr_dlsim.test3 nr_dlsim.test4 nr_dlsim.test5 nr_dlsim.test6 nr_dlsim.test7 nr_dlsim.test8 nr_dlsim.test9 nr_dlsim.test10 PDSCH test OK segmentation fault|assertion|exiting|fatal 3 From 2de42fcf0c68488490be685909cb710e779986e5 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 3 Apr 2020 09:15:10 +0200 Subject: [PATCH 152/553] increasing snr in ulsim mcs9 --- cmake_targets/autotests/test_case_list.xml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/cmake_targets/autotests/test_case_list.xml b/cmake_targets/autotests/test_case_list.xml index 734cf871d4..4ea3184f67 100644 --- a/cmake_targets/autotests/test_case_list.xml +++ b/cmake_targets/autotests/test_case_list.xml @@ -1247,11 +1247,11 @@ $OPENAIR_DIR/cmake_targets/autotests/tools/free_mem.bash $OPENAIR_DIR/targets/bin/nr_ulsim.Rel15 - -n100 -m9 -r106 -s0 + -n100 -m9 -r106 -s5 -n100 -m16 -s10 -n100 -m28 -s20 - -n100 -m9 -R217 -r217 -s0 - -n100 -m9 -R273 -r273 -s0 + -n100 -m9 -R217 -r217 -s5 + -n100 -m9 -R273 -r273 -s5 nr_ulsim.test1 nr_ulsim.test2 nr_ulsim.test3 nr_ulsim.test4 nr_ulsim.test5 PUSCH test OK segmentation fault|assertion|exiting|fatal From 732081dd2223891361dfd565b204295eef887c34 Mon Sep 17 00:00:00 2001 From: matzakos Date: Wed, 8 Apr 2020 11:17:44 +0200 Subject: [PATCH 153/553] ENDC testing: Remove some remaining modifications used only for testing --- openair2/RRC/LTE/rrc_eNB_endc.c | 45 --------------------------------- 1 file changed, 45 deletions(-) diff --git a/openair2/RRC/LTE/rrc_eNB_endc.c b/openair2/RRC/LTE/rrc_eNB_endc.c index 9ddecdb5cb..3d3d9787b5 100644 --- a/openair2/RRC/LTE/rrc_eNB_endc.c +++ b/openair2/RRC/LTE/rrc_eNB_endc.c @@ -35,39 +35,6 @@ extern RAN_CONTEXT_t RC; extern mui_t rrc_eNB_mui; -static int generate_release_drb1(unsigned char *nr1_buf, int nr1_buf_size) -{ - NR_RadioBearerConfig_t r; - NR_DRB_ToReleaseList_t l; - NR_DRB_Identity_t id; - asn_enc_rval_t enc_rval; - - memset(&r, 0, sizeof(r)); - memset(&l, 0, sizeof(l)); - memset(&id, 0, sizeof(id)); - - id = 1; - - r.drb_ToReleaseList = &l; - - ASN_SEQUENCE_ADD(&l.list, &id); - - enc_rval = uper_encode_to_buffer(&asn_DEF_NR_RadioBearerConfig, - NULL, - &r, - nr1_buf, - nr1_buf_size); -{ -int len = (enc_rval.encoded + 7) / 8; -int i; -printf("generate_release_drb1: len = %d (encoded %d)\n", len, enc_rval.encoded); -for (i = 0; i < len; i++) printf(" %2.2x", nr1_buf[i]); -printf("\n"); -} - - return (enc_rval.encoded + 7) / 8; -} - int rrc_eNB_generate_RRCConnectionReconfiguration_endc(protocol_ctxt_t *ctxt, rrc_eNB_ue_context_t *ue_context, unsigned char *buffer, @@ -163,12 +130,10 @@ int rrc_eNB_generate_RRCConnectionReconfiguration_endc(protocol_ctxt_t *ctxt, mac.choice.explicitValue.timeAlignmentTimerDedicated = LTE_TimeAlignmentTimer_sf10240; mac.choice.explicitValue.ext4 = &mac_ext4; -#if 0 mac_ext4.dualConnectivityPHR = &dc_phr; dc_phr.present = LTE_MAC_MainConfig__ext4__dualConnectivityPHR_PR_setup; dc_phr.choice.setup.phr_ModeOtherCG_r12 = LTE_MAC_MainConfig__ext4__dualConnectivityPHR__setup__phr_ModeOtherCG_r12_virtual; -#endif /* NR config */ struct LTE_RRCConnectionReconfiguration_v890_IEs cr_890; @@ -229,7 +194,6 @@ int rrc_eNB_generate_RRCConnectionReconfiguration_endc(protocol_ctxt_t *ctxt, long sk_counter = 0; cr_1510.sk_Counter_r15 = &sk_counter; -#if 1 OCTET_STRING_t dummy_nr1_conf; unsigned char nr1_buf[4] = { 0, 0, 0, 0 }; @@ -252,15 +216,6 @@ int rrc_eNB_generate_RRCConnectionReconfiguration_endc(protocol_ctxt_t *ctxt, } #endif -#else - OCTET_STRING_t nr1_conf; - unsigned char nr1_buf[1024]; - int nr1_size; - nr1_size = generate_release_drb1(nr1_buf, 1024); - cr_1510.nr_RadioBearerConfig1_r15 = &nr1_conf; - nr1_conf.buf = nr1_buf; - nr1_conf.size = nr1_size; -#endif #if 0 OCTET_STRING_t nr2_conf; From b9d80576aaa8a776aac046be9d12c1388bd7d7b9 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Wed, 8 Apr 2020 17:32:19 +0200 Subject: [PATCH 154/553] patch for no data in dmrs symbol for pusch tx --- openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c | 32 ++++++++++++++++------ openair2/GNB_APP/gnb_config.c | 2 +- 2 files changed, 24 insertions(+), 10 deletions(-) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c index c55a084b8a..e34728848d 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c @@ -153,7 +153,8 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, // contains all dmrs symbols even for double symbol dmrs ulsch_ue->rnti = n_rnti; ulsch_ue->Nid_cell = Nid_cell; - ulsch_ue->nb_re_dmrs = 12;//((UE->dmrs_UplinkConfig.pusch_dmrs_type == pusch_dmrs_type1)?6:4)*number_dmrs_symbols; + ulsch_ue->nb_re_dmrs = 12; //FIXME temprary for no data in dmrs symbol +//((UE->dmrs_UplinkConfig.pusch_dmrs_type == pusch_dmrs_type1)?6:4)*number_dmrs_symbols; N_RE_prime = NR_NB_SC_PER_RB*harq_process_ul_ue->number_of_symbols - ulsch_ue->nb_re_dmrs*number_dmrs_symbols - N_PRB_oh; @@ -171,6 +172,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, 0, harq_process_ul_ue->Nl); + uint8_t access_mode = SCHEDULED_ACCESS; //-----------------------------------------------------// @@ -183,8 +185,8 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, slot, 0, ulsch_input_buffer, harq_process_ul_ue->TBS/8, &access_mode); //IP traffic to be transmitted if(data_existing){ - //harq_process_ul_ue->a = (unsigned char*)calloc(harq_process_ul_ue->TBS/8, sizeof(unsigned char)); - memcpy(harq_process_ul_ue->a, ulsch_input_buffer, harq_process_ul_ue->TBS/8); + //harq_process_ul_ue->a = (unsigned char*)calloc(harq_process_ul_ue->TBS/8, sizeof(unsigned char)); + memcpy(harq_process_ul_ue->a, ulsch_input_buffer, harq_process_ul_ue->TBS/8); } } //Random traffic to be transmitted if there is no IP traffic available for this Tx opportunity @@ -271,6 +273,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, /////////////////////////DMRS Modulation///////////////////////// /////////// + ulsch_ue->nb_re_dmrs = ((UE->pusch_config.dmrs_UplinkConfig.pusch_dmrs_type == pusch_dmrs_type1)?6:4)*number_dmrs_symbols; //FIXME temprary here for no data in dmrs symbol pusch_dmrs = UE->nr_gold_pusch_dmrs[slot]; n_dmrs = (harq_process_ul_ue->nb_rb*ulsch_ue->nb_re_dmrs*ulsch_ue->length_dmrs); int16_t mod_dmrs[n_dmrs<<1]; @@ -313,9 +316,9 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, tx_layers = (int16_t **)pusch_ue->txdataF_layers; nr_ue_layer_mapping(UE->ulsch[thread_id][gNB_id], - harq_process_ul_ue->Nl, - available_bits/mod_order, - tx_layers); + harq_process_ul_ue->Nl, + available_bits/mod_order, + tx_layers); /////////// //////////////////////////////////////////////////////////////////////// @@ -459,8 +462,18 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, } else { - ((int16_t*)txdataF[ap])[(sample_offsetF)<<1] = ((int16_t *) ulsch_ue->y)[m<<1]; - ((int16_t*)txdataF[ap])[((sample_offsetF)<<1) + 1] = ((int16_t *) ulsch_ue->y)[(m<<1) + 1]; + if (!is_dmrs_symbol((mapping_type)?l-start_symbol:l, + 0, + 0, + 0, + 0, + 0, + harq_process_ul_ue->number_of_symbols, + UE->pusch_config.dmrs_UplinkConfig.pusch_dmrs_type, + frame_parms->ofdm_symbol_size)) + { + ((int16_t*)txdataF[ap])[(sample_offsetF)<<1] = ((int16_t *) ulsch_ue->y)[m<<1]; + ((int16_t*)txdataF[ap])[((sample_offsetF)<<1) + 1] = ((int16_t *) ulsch_ue->y)[(m<<1) + 1]; #ifdef DEBUG_PUSCH_MAPPING printf("m %d\t l %d \t k %d \t txdataF: %d %d\n", @@ -468,7 +481,8 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, ((int16_t*)txdataF[ap])[((sample_offsetF)<<1) + 1]); #endif - m++; + m++; + } } if (++k >= frame_parms->ofdm_symbol_size) diff --git a/openair2/GNB_APP/gnb_config.c b/openair2/GNB_APP/gnb_config.c index 5b7ef17d20..69c971fb1d 100644 --- a/openair2/GNB_APP/gnb_config.c +++ b/openair2/GNB_APP/gnb_config.c @@ -721,7 +721,7 @@ int RCconfig_nr_gtpu(void ) { AssertFatal((message = itti_alloc_new_message(TASK_GNB_APP, GTPV1U_ENB_S1_REQ))!=NULL,""); // IPV4_STR_ADDR_TO_INT_NWBO ( address, RC.gtpv1u_data_g->enb_ip_address_for_S1u_S12_S4_up, "BAD IP ADDRESS FORMAT FOR eNB S1_U !\n" ); // LOG_I(GTPU,"Configuring GTPu address : %s -> %x\n",address,RC.gtpv1u_data_g->enb_ip_address_for_S1u_S12_S4_up); - + IPV4_STR_ADDR_TO_INT_NWBO ( address, GTPV1U_ENB_S1_REQ(message).enb_ip_address_for_S1u_S12_S4_up, "BAD IP ADDRESS FORMAT FOR eNB S1_U !\n" ); LOG_I(GTPU,"Configuring GTPu address : %s -> %x\n",address,GTPV1U_ENB_S1_REQ(message).enb_ip_address_for_S1u_S12_S4_up); From e0acce65c4907973fc29713d7fd34d599a15ef19 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Wed, 8 Apr 2020 22:22:52 +0200 Subject: [PATCH 155/553] dci 1_1 bit decoding --- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 84 ++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 745a5b749b..81aeea0629 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -3055,6 +3055,90 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, } break; + + case NR_DL_DCI_FORMAT_1_1: + // Format indicator + pos=1; + dci_pdu_rel15->format_indicator = (*dci_pdu>>(dci_size-pos))&1; + // Carrier indicator + pos+=dci_pdu_rel15->carrier_indicator.nbits; + dci_pdu_rel15->carrier_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<carrier_indicator.nbits)-1); + // BWP Indicator + pos+=dci_pdu_rel15->bwp_indicator.nbits; + dci_pdu_rel15->bwp_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<bwp_indicator.nbits)-1); + // Frequency domain resource assignment + pos+=dci_pdu_rel15->frequency_domain_assignment.nbits; + dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<frequency_domain_assignment.nbits)-1); + // Time domain resource assignment + pos+=dci_pdu_rel15->time_domain_assignment.nbits; + dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<time_domain_assignment.nbits)-1); + // VRB-to-PRB mapping + pos+=dci_pdu_rel15->vrb_to_prb_mapping.nbits; + dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu>>(dci_size-pos))&((1<vrb_to_prb_mapping.nbits)-1); + // PRB bundling size indicator + pos+=dci_pdu_rel15->prb_bundling_size_indicator.nbits; + dci_pdu_rel15->prb_bundling_size_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<prb_bundling_size_indicator.nbits)-1); + // Rate matching indicator + pos+=dci_pdu_rel15->rate_matching_indicator.nbits; + dci_pdu_rel15->rate_matching_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<rate_matching_indicator.nbits)-1); + // ZP CSI-RS trigger + pos+=dci_pdu_rel15->zp_csi_rs_trigger.nbits; + dci_pdu_rel15->zp_csi_rs_trigger.val = (*dci_pdu>>(dci_size-pos))&((1<zp_csi_rs_trigger.nbits)-1); + //TB1 + // MCS 5bit + pos+=5; + dci_pdu_rel15->mcs = (*dci_pdu>>(dci_size-pos))&0x1f; + // New data indicator 1bit + pos+=1; + dci_pdu_rel15->ndi = (*dci_pdu>>(dci_size-pos))&0x1; + // Redundancy version 2bit + pos+=2; + dci_pdu_rel15->rv = (*dci_pdu>>(dci_size-pos))&0x3; + //TB2 + // MCS 5bit + pos+=dci_pdu_rel15->mcs2.nbits; + dci_pdu_rel15->mcs2.val = (*dci_pdu>>(dci_size-pos))&((1<mcs2.nbits)-1); + // New data indicator 1bit + pos+=dci_pdu_rel15->ndi2.nbits; + dci_pdu_rel15->ndi2.val = (*dci_pdu>>(dci_size-pos))&((1<ndi2.nbits)-1); + // Redundancy version 2bit + pos+=dci_pdu_rel15->rv2.nbits; + dci_pdu_rel15->rv2.val = (*dci_pdu>>(dci_size-pos))&((1<rv2.nbits)-1); + // HARQ process number 4bit + pos+=4; + dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf; + // Downlink assignment index + pos+=dci_pdu_rel15->dai[0].nbits; + dci_pdu_rel15->dai[0].val = (*dci_pdu>>(dci_size-pos))&((1<dai[0].nbits)-1); + // TPC command for scheduled PUCCH 2bit + pos+=2; + dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&0x3; + // PUCCH resource indicator 3bit + pos+=3; + dci_pdu_rel15->pucch_resource_indicator = (*dci_pdu>>(dci_size-pos))&0x3; + // PDSCH-to-HARQ_feedback timing indicator + pos+=dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.nbits; + dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<pdsch_to_harq_feedback_timing_indicator.nbits)-1); + // Antenna ports + pos+=dci_pdu_rel15->antenna_ports.nbits; + dci_pdu_rel15->antenna_ports.val = (*dci_pdu>>(dci_size-pos))&((1<antenna_ports.nbits)-1); + // TCI + pos+=dci_pdu_rel15->transmission_configuration_indication.nbits; + dci_pdu_rel15->transmission_configuration_indication.val = (*dci_pdu>>(dci_size-pos))&((1<transmission_configuration_indication.nbits)-1); + // SRS request + pos+=dci_pdu_rel15->srs_request.nbits; + dci_pdu_rel15->srs_request.val = (*dci_pdu>>(dci_size-pos))&((1<srs_request.nbits)-1); + // CBG transmission information + pos+=dci_pdu_rel15->cbgti.nbits; + dci_pdu_rel15->cbgti.val = (*dci_pdu>>(dci_size-pos))&((1<cbgti.nbits)-1); + // CBG flushing out information + pos+=dci_pdu_rel15->cbgfi.nbits; + dci_pdu_rel15->cbgfi.val = (*dci_pdu>>(dci_size-pos))&((1<cbgfi.nbits)-1); + // DMRS sequence init + pos+=1; + dci_pdu_rel15->dmrs_sequence_initialization = (*dci_pdu>>(dci_size-pos))&0x1; + break; + } } From 9e8e7de10ab5f12c6e7733d525e20e362381dd34 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Wed, 8 Apr 2020 22:24:08 +0200 Subject: [PATCH 156/553] using same dci_pdu_rel15 for UE also --- openair2/LAYER2/NR_MAC_COMMON/nr_mac.h | 2 +- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 3 +- openair2/LAYER2/NR_MAC_UE/mac_extern.h | 4 +- openair2/LAYER2/NR_MAC_UE/mac_proto.h | 4 +- .../NR_MAC_UE/nr_ue_dci_configuration.c | 7 +- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 485 +++++++++--------- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 2 +- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 7 +- 8 files changed, 262 insertions(+), 252 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h index fd51602e23..53e7c83661 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h @@ -92,7 +92,7 @@ typedef struct { uint8_t TAGID:2; // octet 1 [7:6] } __attribute__ ((__packed__)) NR_MAC_CE_TA; -// DCI pdu structures. Used in UE by nr_dci_size(but not filled in UE) +// DCI pdu structures. Used by both gNB and UE. typedef struct { uint16_t val; uint8_t nbits; diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index fc9322c54b..9dd797b503 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -609,6 +609,7 @@ uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, break; case NR_DL_DCI_FORMAT_1_1: + // General note: 0 bits condition is ignored as default nbits is 0. // Format identifier size = 1; // Carrier indicator @@ -647,7 +648,7 @@ uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, num_entries = pdsch_config->pdsch_TimeDomainAllocationList->choice.setup->list.count; dci_pdu->time_domain_assignment.nbits = (int)ceil(log2(num_entries)); size += dci_pdu->time_domain_assignment.nbits; - // VRB to PRB mapping FIXME (38.212 also says 0 bits if not configured by higher layers + // VRB to PRB mapping if (pdsch_config->resourceAllocation == 1) { dci_pdu->vrb_to_prb_mapping.nbits = 1; size += dci_pdu->vrb_to_prb_mapping.nbits; diff --git a/openair2/LAYER2/NR_MAC_UE/mac_extern.h b/openair2/LAYER2/NR_MAC_UE/mac_extern.h index 26e0ea2667..54cdc4d149 100644 --- a/openair2/LAYER2/NR_MAC_UE/mac_extern.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_extern.h @@ -90,4 +90,6 @@ extern const int32_t table_38213_10_1_1_c2[5]; // for PUSCH from TS 38.214 subclause 6.1.2.1.1 extern uint8_t table_6_1_2_1_1_2_time_dom_res_alloc_A[16][3]; // for PDSCH from TS 38.214 subclause 5.1.2.1.1 -extern uint8_t table_5_1_2_1_1_2_time_dom_res_alloc_A[16][3]; \ No newline at end of file +extern uint8_t table_5_1_2_1_1_2_time_dom_res_alloc_A[16][3]; + +extern dci_pdu_rel15_t *def_dci_pdu_rel15; diff --git a/openair2/LAYER2/NR_MAC_UE/mac_proto.h b/openair2/LAYER2/NR_MAC_UE/mac_proto.h index 0d21ff60a2..2741c7ff84 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_proto.h @@ -115,7 +115,7 @@ uint32_t ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, int8_t nr_ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, uint8_t eNB_id, uint16_t rnti, sub_frame_t subframe); -int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format); +int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format); int nr_ue_process_dci_indication_pdu(module_id_t module_id,int cc_id, int gNB_index,fapi_nr_dci_indication_pdu_t *dci); uint32_t get_ssb_frame(uint32_t test); @@ -163,7 +163,7 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, uint8_t dci_length, uint16_t rnti, uint64_t *dci_pdu, - nr_dci_pdu_rel15_t *nr_pdci_info_extracted); + dci_pdu_rel15_t *nr_pdci_info_extracted); int set_tdd_config_nr_ue(fapi_nr_config_request_t *cfg, int mu, diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c index 8c66ccec5f..e734ce10a5 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c @@ -44,6 +44,7 @@ #endif #define LOG_DCI_PARM(a...) LOG_D(PHY,"\t<-NR_PDCCH_DCI_TOOLS_DEBUG (nr_generate_ue_ul_dlsch_params_from_dci)" a) +dci_pdu_rel15_t *def_dci_pdu_rel15; void fill_dci_search_candidates(NR_SearchSpace_t *ss,fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15) { @@ -61,8 +62,10 @@ void fill_dci_search_candidates(NR_SearchSpace_t *ss,fapi_nr_dl_config_dci_dl_pd void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_config,int frame,int slot) { + def_dci_pdu_rel15 = calloc(1,sizeof(dci_pdu_rel15_t)); + + int bwp_id = 1; // FIXME // check if DL slot - dci_pdu_rel15_t dci_pdu_rel15; if (is_nr_DL_slot(mac->scc,slot)==1) { // get BWP 1, Coreset 0, SearchSpace 0 @@ -172,7 +175,7 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_ rel15->coreset.pdcch_dmrs_scrambling_id = *mac->scc->physCellId; fill_dci_search_candidates(mac->SSpace[0][0][ss_id],rel15); rel15->dci_format = NR_DL_DCI_FORMAT_1_0; - rel15->dci_length = nr_dci_size(mac->scg,&dci_pdu_rel15,rel15->dci_format,NR_RNTI_C,rel15->BWPSize); + rel15->dci_length = nr_dci_size(mac->scg,def_dci_pdu_rel15,rel15->dci_format,NR_RNTI_C,rel15->BWPSize,bwp_id); dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI; dl_config->number_pdus = dl_config->number_pdus + 1; } diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 81aeea0629..5ebd57fd19 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -65,6 +65,8 @@ //#define ENABLE_MAC_PAYLOAD_DEBUG 1 #define DEBUG_EXTRACT_DCI 1 +extern dci_pdu_rel15_t *def_dci_pdu_rel15; + extern void mac_rlc_data_ind ( const module_id_t module_idP, const rnti_t rntiP, @@ -1910,16 +1912,15 @@ int8_t nr_ue_process_dci_time_dom_resource_assignment(NR_UE_MAC_INST_t *mac, int nr_ue_process_dci_indication_pdu(module_id_t module_id,int cc_id, int gNB_index,fapi_nr_dci_indication_pdu_t *dci) { NR_UE_MAC_INST_t *mac = get_mac_inst(module_id); - nr_dci_pdu_rel15_t dci_pdu_rel15; LOG_D(MAC,"Received dci indication (rnti %x,dci format %d,n_CCE %d,payloadSize %d,payload %llx)\n", dci->rnti,dci->dci_format,dci->n_CCE,dci->payloadSize,*(unsigned long long*)dci->payloadBits); - nr_extract_dci_info(mac,dci->dci_format,dci->payloadSize,dci->rnti,(uint64_t *)dci->payloadBits,&dci_pdu_rel15); - nr_ue_process_dci(module_id, cc_id, gNB_index, &dci_pdu_rel15, dci->rnti, dci->dci_format); + nr_extract_dci_info(mac,dci->dci_format,dci->payloadSize,dci->rnti,(uint64_t *)dci->payloadBits,def_dci_pdu_rel15); + nr_ue_process_dci(module_id, cc_id, gNB_index, def_dci_pdu_rel15, dci->rnti, dci->dci_format); } -int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format){ +int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format){ NR_UE_MAC_INST_t *mac = get_mac_inst(module_id); fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request; @@ -1957,16 +1958,16 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu_0_0 = &ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15; /* IDENTIFIER_DCI_FORMATS */ /* FREQ_DOM_RESOURCE_ASSIGNMENT_UL */ - nr_ue_process_dci_freq_dom_resource_assignment(ulsch_config_pdu_0_0,NULL,n_RB_ULBWP,0,dci->freq_dom_resource_assignment_UL); + nr_ue_process_dci_freq_dom_resource_assignment(ulsch_config_pdu_0_0,NULL,n_RB_ULBWP,0,dci->frequency_domain_assignment.val); /* TIME_DOM_RESOURCE_ASSIGNMENT */ nr_ue_process_dci_time_dom_resource_assignment(mac, ulsch_config_pdu_0_0,NULL, - dci->time_dom_resource_assignment); + dci->time_domain_assignment.val); /* FREQ_HOPPING_FLAG */ if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.resource_allocation != 0) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.frequency_hopping !=0)) - ulsch_config_pdu_0_0->pusch_freq_hopping = (dci->freq_hopping_flag == 0)? pusch_freq_hopping_disabled:pusch_freq_hopping_enabled; + ulsch_config_pdu_0_0->pusch_freq_hopping = (dci->frequency_hopping_flag.val == 0)? pusch_freq_hopping_disabled:pusch_freq_hopping_enabled; /* MCS */ ulsch_config_pdu_0_0->mcs = dci->mcs; /* NDI */ @@ -1974,22 +1975,22 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr /* RV */ ulsch_config_pdu_0_0->rv = dci->rv; /* HARQ_PROCESS_NUMBER */ - ulsch_config_pdu_0_0->harq_process_nbr = dci->harq_process_number; + ulsch_config_pdu_0_0->harq_process_nbr = dci->harq_pid; /* TPC_PUSCH */ // according to TS 38.213 Table Table 7.1.1-1 - if (dci->tpc_pusch == 0) { + if (dci->tpc == 0) { ulsch_config_pdu_0_0->accumulated_delta_PUSCH = -1; ulsch_config_pdu_0_0->absolute_delta_PUSCH = -4; } - if (dci->tpc_pusch == 1) { + if (dci->tpc == 1) { ulsch_config_pdu_0_0->accumulated_delta_PUSCH = 0; ulsch_config_pdu_0_0->absolute_delta_PUSCH = -1; } - if (dci->tpc_pusch == 2) { + if (dci->tpc == 2) { ulsch_config_pdu_0_0->accumulated_delta_PUSCH = 1; ulsch_config_pdu_0_0->absolute_delta_PUSCH = 1; } - if (dci->tpc_pusch == 3) { + if (dci->tpc == 3) { ulsch_config_pdu_0_0->accumulated_delta_PUSCH = 3; ulsch_config_pdu_0_0->absolute_delta_PUSCH = 4; } @@ -2034,16 +2035,16 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr /* CARRIER_IND */ /* SUL_IND_0_1 */ /* BANDWIDTH_PART_IND */ - ulsch_config_pdu_0_1->bandwidth_part_ind = dci->bandwidth_part_ind; + ulsch_config_pdu_0_1->bandwidth_part_ind = dci->bwp_indicator.val; /* FREQ_DOM_RESOURCE_ASSIGNMENT_UL */ - nr_ue_process_dci_freq_dom_resource_assignment(ulsch_config_pdu_0_1,NULL,n_RB_ULBWP,0,dci->freq_dom_resource_assignment_UL); + nr_ue_process_dci_freq_dom_resource_assignment(ulsch_config_pdu_0_1,NULL,n_RB_ULBWP,0,dci->frequency_domain_assignment.val); /* TIME_DOM_RESOURCE_ASSIGNMENT */ nr_ue_process_dci_time_dom_resource_assignment(mac,ulsch_config_pdu_0_1,NULL, - dci->time_dom_resource_assignment); + dci->time_domain_assignment.val); /* FREQ_HOPPING_FLAG */ if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.resource_allocation != 0) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.frequency_hopping !=0)) - ulsch_config_pdu_0_1->pusch_freq_hopping = (dci->freq_hopping_flag == 0)? pusch_freq_hopping_disabled:pusch_freq_hopping_enabled; + ulsch_config_pdu_0_1->pusch_freq_hopping = (dci->frequency_hopping_flag.val == 0)? pusch_freq_hopping_disabled:pusch_freq_hopping_enabled; /* MCS */ ulsch_config_pdu_0_1->mcs = dci->mcs; /* NDI */ @@ -2051,24 +2052,24 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr /* RV */ ulsch_config_pdu_0_1->rv = dci->rv; /* HARQ_PROCESS_NUMBER */ - ulsch_config_pdu_0_1->harq_process_nbr = dci->harq_process_number; + ulsch_config_pdu_0_1->harq_process_nbr = dci->harq_pid; /* FIRST_DAI */ //To be implemented, FIXME!!! /* SECOND_DAI */ //To be implemented, FIXME!!! /* TPC_PUSCH */ // according to TS 38.213 Table Table 7.1.1-1 - if (dci->tpc_pusch == 0) { + if (dci->tpc == 0) { ulsch_config_pdu_0_1->accumulated_delta_PUSCH = -1; ulsch_config_pdu_0_1->absolute_delta_PUSCH = -4; } - if (dci->tpc_pusch == 1) { + if (dci->tpc == 1) { ulsch_config_pdu_0_1->accumulated_delta_PUSCH = 0; ulsch_config_pdu_0_1->absolute_delta_PUSCH = -1; } - if (dci->tpc_pusch == 2) { + if (dci->tpc == 2) { ulsch_config_pdu_0_1->accumulated_delta_PUSCH = 1; ulsch_config_pdu_0_1->absolute_delta_PUSCH = 1; } - if (dci->tpc_pusch == 3) { + if (dci->tpc == 3) { ulsch_config_pdu_0_1->accumulated_delta_PUSCH = 3; ulsch_config_pdu_0_1->absolute_delta_PUSCH = 4; } @@ -2087,16 +2088,16 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 3) || (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 4))){ if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) { - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][0]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][1]; + ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][0]; + ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][1]; } if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_partialAndNonCoherent){ - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][2]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][3]; + ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][2]; + ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][3]; } if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){ - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][4]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][5]; + ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][4]; + ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][5]; } } // Table 7.3.1.1.2-3: transformPrecoder= enabled, or transformPrecoder=disabled and maxRank = 1 @@ -2104,16 +2105,16 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr || (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled)) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1)){ if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) { - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][6]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][7]; + ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][6]; + ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][7]; } if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_partialAndNonCoherent){ - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][8]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][9]; + ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][8]; + ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][9]; } if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){ - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][10]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][11]; + ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][10]; + ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][11]; } } } @@ -2122,12 +2123,12 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 2)){ if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) { - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][12]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][13]; + ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][12]; + ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][13]; } if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){ - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][14]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][15]; + ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][14]; + ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][15]; } } // Table 7.3.1.1.2-5: transformPrecoder= enabled, or transformPrecoder= disabled and maxRank = 1 @@ -2135,12 +2136,12 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr || (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled)) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1)){ if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) { - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][16]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][17]; + ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][16]; + ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][17]; } if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){ - ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][18]; - ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][19]; + ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][18]; + ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][19]; } } } @@ -2151,26 +2152,26 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-6 ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2; - ulsch_config_pdu_0_1->dmrs_ports[0] = dci->antenna_ports; + ulsch_config_pdu_0_1->dmrs_ports[0] = dci->antenna_ports.val; } if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-7 ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2; - ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 3)?(dci->antenna_ports-4):(dci->antenna_ports); - ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 3)?2:1; + ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports.val > 3)?(dci->antenna_ports.val-4):(dci->antenna_ports.val); + ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports.val > 3)?2:1; } if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-8/9/10/11 if (rank == 1){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 1)?2:1; - ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports-2):(dci->antenna_ports); + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports.val > 1)?2:1; + ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports.val > 1)?(dci->antenna_ports.val-2):(dci->antenna_ports.val); } if (rank == 2){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?2:1; - ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 2 ?0:2):0; - ulsch_config_pdu_0_1->dmrs_ports[1] = (dci->antenna_ports > 1)?(dci->antenna_ports > 2 ?2:3):1; + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports.val > 0)?2:1; + ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports.val > 1)?(dci->antenna_ports.val > 2 ?0:2):0; + ulsch_config_pdu_0_1->dmrs_ports[1] = (dci->antenna_ports.val > 1)?(dci->antenna_ports.val > 2 ?2:3):1; } if (rank == 3){ ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2; @@ -2190,52 +2191,52 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-12/13/14/15 if (rank == 1){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 1)?2:1; - ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 5 ?(dci->antenna_ports-6):(dci->antenna_ports-2)):dci->antenna_ports; - ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 6)?2:1; + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports.val > 1)?2:1; + ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports.val > 1)?(dci->antenna_ports.val > 5 ?(dci->antenna_ports.val-6):(dci->antenna_ports.val-2)):dci->antenna_ports.val; + ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports.val > 6)?2:1; } if (rank == 2){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?2:1; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_13[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_13[dci->antenna_ports][2]; - ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 3)?2:1; + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports.val > 0)?2:1; + ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_13[dci->antenna_ports.val][1]; + ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_13[dci->antenna_ports.val][2]; + ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports.val > 3)?2:1; } if (rank == 3){ ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_14[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_14[dci->antenna_ports][2]; - ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_14[dci->antenna_ports][3]; - ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 1)?2:1; + ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_14[dci->antenna_ports.val][1]; + ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_14[dci->antenna_ports.val][2]; + ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_14[dci->antenna_ports.val][3]; + ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports.val > 1)?2:1; } if (rank == 4){ ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_15[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_15[dci->antenna_ports][2]; - ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_15[dci->antenna_ports][3]; - ulsch_config_pdu_0_1->dmrs_ports[3] = table_7_3_1_1_2_15[dci->antenna_ports][4]; - ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 1)?2:1; + ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_15[dci->antenna_ports.val][1]; + ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_15[dci->antenna_ports.val][2]; + ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_15[dci->antenna_ports.val][3]; + ulsch_config_pdu_0_1->dmrs_ports[3] = table_7_3_1_1_2_15[dci->antenna_ports.val][4]; + ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports.val > 1)?2:1; } } if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 2) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-16/17/18/19 if (rank == 1){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 1)?((dci->antenna_ports > 5)?3:2):1; - ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 5 ?(dci->antenna_ports-6):(dci->antenna_ports-2)):dci->antenna_ports; + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports.val > 1)?((dci->antenna_ports.val > 5)?3:2):1; + ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports.val > 1)?(dci->antenna_ports.val > 5 ?(dci->antenna_ports.val-6):(dci->antenna_ports.val-2)):dci->antenna_ports.val; } if (rank == 2){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?((dci->antenna_ports > 2)?3:2):1; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_17[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_17[dci->antenna_ports][2]; + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports.val > 0)?((dci->antenna_ports.val > 2)?3:2):1; + ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_17[dci->antenna_ports.val][1]; + ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_17[dci->antenna_ports.val][2]; } if (rank == 3){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?3:2; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_18[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_18[dci->antenna_ports][2]; - ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_18[dci->antenna_ports][3]; + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports.val > 0)?3:2; + ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_18[dci->antenna_ports.val][1]; + ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_18[dci->antenna_ports.val][2]; + ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_18[dci->antenna_ports.val][3]; } if (rank == 4){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = dci->antenna_ports + 2; + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = dci->antenna_ports.val + 2; ulsch_config_pdu_0_1->dmrs_ports[0] = 0; ulsch_config_pdu_0_1->dmrs_ports[1] = 1; ulsch_config_pdu_0_1->dmrs_ports[2] = 2; @@ -2246,50 +2247,50 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 2) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-20/21/22/23 if (rank == 1){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_20[dci->antenna_ports][0]; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_20[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_20[dci->antenna_ports][2]; + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_20[dci->antenna_ports.val][0]; + ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_20[dci->antenna_ports.val][1]; + ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_20[dci->antenna_ports.val][2]; } if (rank == 2){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_21[dci->antenna_ports][0]; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_21[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_21[dci->antenna_ports][2]; - ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_21[dci->antenna_ports][3]; + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_21[dci->antenna_ports.val][0]; + ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_21[dci->antenna_ports.val][1]; + ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_21[dci->antenna_ports.val][2]; + ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_21[dci->antenna_ports.val][3]; } if (rank == 3){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_22[dci->antenna_ports][0]; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_22[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_22[dci->antenna_ports][2]; - ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_22[dci->antenna_ports][3]; - ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_22[dci->antenna_ports][4]; + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_22[dci->antenna_ports.val][0]; + ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_22[dci->antenna_ports.val][1]; + ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_22[dci->antenna_ports.val][2]; + ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_22[dci->antenna_ports.val][3]; + ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_22[dci->antenna_ports.val][4]; } if (rank == 4){ - ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_23[dci->antenna_ports][0]; - ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_23[dci->antenna_ports][1]; - ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_23[dci->antenna_ports][2]; - ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_23[dci->antenna_ports][3]; - ulsch_config_pdu_0_1->dmrs_ports[3] = table_7_3_1_1_2_23[dci->antenna_ports][4]; - ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_23[dci->antenna_ports][5]; + ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_23[dci->antenna_ports.val][0]; + ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_23[dci->antenna_ports.val][1]; + ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_23[dci->antenna_ports.val][2]; + ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_23[dci->antenna_ports.val][3]; + ulsch_config_pdu_0_1->dmrs_ports[3] = table_7_3_1_1_2_23[dci->antenna_ports.val][4]; + ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_23[dci->antenna_ports.val][5]; } } /* SRS_REQUEST */ // if SUL is supported in the cell, there is an additional bit in thsi field and the value of this bit represents table 7.1.1.1-1 TS 38.212 FIXME!!! - ulsch_config_pdu_0_1->srs_config.aperiodicSRS_ResourceTrigger = (dci->srs_request & 0x11); // as per Table 7.3.1.1.2-24 TS 38.212 + ulsch_config_pdu_0_1->srs_config.aperiodicSRS_ResourceTrigger = (dci->srs_request.val & 0x11); // as per Table 7.3.1.1.2-24 TS 38.212 /* CSI_REQUEST */ - ulsch_config_pdu_0_1->csi_reportTriggerSize = dci->csi_request; + ulsch_config_pdu_0_1->csi_reportTriggerSize = dci->csi_request.val; /* CBGTI */ - ulsch_config_pdu_0_1->maxCodeBlockGroupsPerTransportBlock = dci->cbgti; + ulsch_config_pdu_0_1->maxCodeBlockGroupsPerTransportBlock = dci->cbgti.val; /* PTRS_DMRS */ if (((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.ptrs_uplink_config == 0)) || ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1))){ } else { - ulsch_config_pdu_0_1->ptrs_dmrs_association_port = dci->ptrs_dmrs; + ulsch_config_pdu_0_1->ptrs_dmrs_association_port = dci->ptrs_dmrs_association.val; } /* BETA_OFFSET_IND */ // Table 9.3-3 in [5, TS 38.213] - ulsch_config_pdu_0_1->beta_offset_ind = dci->beta_offset_ind; + ulsch_config_pdu_0_1->beta_offset_ind = dci->beta_offset_indicator.val; /* DMRS_SEQ_INI */ // FIXME!! /* UL_SCH_IND */ @@ -2359,10 +2360,10 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr dlsch_config_pdu_1_0->SubcarrierSpacing = mac->DLbwp[0]->bwp_Common->genericParameters.subcarrierSpacing; /* IDENTIFIER_DCI_FORMATS */ /* FREQ_DOM_RESOURCE_ASSIGNMENT_DL */ - nr_ue_process_dci_freq_dom_resource_assignment(NULL,dlsch_config_pdu_1_0,0,n_RB_DLBWP,dci->freq_dom_resource_assignment_DL); + nr_ue_process_dci_freq_dom_resource_assignment(NULL,dlsch_config_pdu_1_0,0,n_RB_DLBWP,dci->frequency_domain_assignment.val); /* TIME_DOM_RESOURCE_ASSIGNMENT */ nr_ue_process_dci_time_dom_resource_assignment(mac,NULL,dlsch_config_pdu_1_0, - dci->time_dom_resource_assignment); + dci->time_domain_assignment.val); /* dmrs symbol positions*/ dlsch_config_pdu_1_0->dlDmrsSymbPos = fill_dmrs_mask(pdsch_config, @@ -2370,7 +2371,7 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr dlsch_config_pdu_1_0->number_symbols); dlsch_config_pdu_1_0->dmrsConfigType = mac->DLbwp[0]->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type == NULL ? 1 : 2; /* VRB_TO_PRB_MAPPING */ - dlsch_config_pdu_1_0->vrb_to_prb_mapping = (dci->vrb_to_prb_mapping == 0) ? vrb_to_prb_mapping_non_interleaved:vrb_to_prb_mapping_interleaved; + dlsch_config_pdu_1_0->vrb_to_prb_mapping = (dci->vrb_to_prb_mapping.val == 0) ? vrb_to_prb_mapping_non_interleaved:vrb_to_prb_mapping_interleaved; /* MCS */ dlsch_config_pdu_1_0->mcs = dci->mcs; /* NDI (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/ @@ -2378,9 +2379,9 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr /* RV (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/ dlsch_config_pdu_1_0->rv = dci->rv; /* HARQ_PROCESS_NUMBER (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/ - dlsch_config_pdu_1_0->harq_process_nbr = dci->harq_process_number; + dlsch_config_pdu_1_0->harq_process_nbr = dci->harq_pid; /* DAI (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/ - dlsch_config_pdu_1_0->dai = dci ->dai; + dlsch_config_pdu_1_0->dai = dci->dai[0].val; /* TB_SCALING (only if CRC scrambled by P-RNTI or RA-RNTI) */ // according to TS 38.214 Table 5.1.3.2-3 if (dci->tb_scaling == 0) dlsch_config_pdu_1_0->scaling_factor_S = 1; @@ -2389,32 +2390,32 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr if (dci->tb_scaling == 3) dlsch_config_pdu_1_0->scaling_factor_S = 0; // value not defined in table /* TPC_PUCCH (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/ // according to TS 38.213 Table 7.2.1-1 - if (dci->tpc_pucch == 0) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = -1; - if (dci->tpc_pucch == 1) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 0; - if (dci->tpc_pucch == 2) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 1; - if (dci->tpc_pucch == 3) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 3; + if (dci->tpc == 0) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = -1; + if (dci->tpc == 1) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 0; + if (dci->tpc == 2) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 1; + if (dci->tpc == 3) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 3; /* PUCCH_RESOURCE_IND (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI)*/ - //if (dci->pucch_resource_ind == 0) dlsch_config_pdu_1_0->pucch_resource_id = 1; //pucch-ResourceId obtained from the 1st value of resourceList FIXME!!! - //if (dci->pucch_resource_ind == 1) dlsch_config_pdu_1_0->pucch_resource_id = 2; //pucch-ResourceId obtained from the 2nd value of resourceList FIXME!! - //if (dci->pucch_resource_ind == 2) dlsch_config_pdu_1_0->pucch_resource_id = 3; //pucch-ResourceId obtained from the 3rd value of resourceList FIXME!! - //if (dci->pucch_resource_ind == 3) dlsch_config_pdu_1_0->pucch_resource_id = 4; //pucch-ResourceId obtained from the 4th value of resourceList FIXME!! - //if (dci->pucch_resource_ind == 4) dlsch_config_pdu_1_0->pucch_resource_id = 5; //pucch-ResourceId obtained from the 5th value of resourceList FIXME!! - //if (dci->pucch_resource_ind == 5) dlsch_config_pdu_1_0->pucch_resource_id = 6; //pucch-ResourceId obtained from the 6th value of resourceList FIXME!! - //if (dci->pucch_resource_ind == 6) dlsch_config_pdu_1_0->pucch_resource_id = 7; //pucch-ResourceId obtained from the 7th value of resourceList FIXME!! - //if (dci->pucch_resource_ind == 7) dlsch_config_pdu_1_0->pucch_resource_id = 8; //pucch-ResourceId obtained from the 8th value of resourceList FIXME!! - dlsch_config_pdu_1_0->pucch_resource_id = dci->pucch_resource_ind; + //if (dci->pucch_resource_indicator == 0) dlsch_config_pdu_1_0->pucch_resource_id = 1; //pucch-ResourceId obtained from the 1st value of resourceList FIXME!!! + //if (dci->pucch_resource_indicator == 1) dlsch_config_pdu_1_0->pucch_resource_id = 2; //pucch-ResourceId obtained from the 2nd value of resourceList FIXME!! + //if (dci->pucch_resource_indicator == 2) dlsch_config_pdu_1_0->pucch_resource_id = 3; //pucch-ResourceId obtained from the 3rd value of resourceList FIXME!! + //if (dci->pucch_resource_indicator == 3) dlsch_config_pdu_1_0->pucch_resource_id = 4; //pucch-ResourceId obtained from the 4th value of resourceList FIXME!! + //if (dci->pucch_resource_indicator == 4) dlsch_config_pdu_1_0->pucch_resource_id = 5; //pucch-ResourceId obtained from the 5th value of resourceList FIXME!! + //if (dci->pucch_resource_indicator == 5) dlsch_config_pdu_1_0->pucch_resource_id = 6; //pucch-ResourceId obtained from the 6th value of resourceList FIXME!! + //if (dci->pucch_resource_indicator == 6) dlsch_config_pdu_1_0->pucch_resource_id = 7; //pucch-ResourceId obtained from the 7th value of resourceList FIXME!! + //if (dci->pucch_resource_indicator == 7) dlsch_config_pdu_1_0->pucch_resource_id = 8; //pucch-ResourceId obtained from the 8th value of resourceList FIXME!! + dlsch_config_pdu_1_0->pucch_resource_id = dci->pucch_resource_indicator; /* PDSCH_TO_HARQ_FEEDBACK_TIME_IND (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI)*/ - dlsch_config_pdu_1_0->pdsch_to_harq_feedback_time_ind = dci->pdsch_to_harq_feedback_time_ind; + dlsch_config_pdu_1_0->pdsch_to_harq_feedback_time_ind = dci->pdsch_to_harq_feedback_timing_indicator.val; LOG_D(MAC,"(nr_ue_procedures.c) rnti=%d dl_config->number_pdus=%d\n", dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.rnti, dl_config->number_pdus); LOG_D(MAC,"(nr_ue_procedures.c) frequency_domain_resource_assignment=%d \t number_rbs=%d \t start_rb=%d\n", - dci->freq_dom_resource_assignment_DL, + dci->frequency_domain_assignment.val, dlsch_config_pdu_1_0->number_rbs, dlsch_config_pdu_1_0->start_rb); LOG_D(MAC,"(nr_ue_procedures.c) time_domain_resource_assignment=%d \t number_symbols=%d \t start_symbol=%d\n", - dci->time_dom_resource_assignment, + dci->time_domain_assignment.val, dlsch_config_pdu_1_0->number_symbols, dlsch_config_pdu_1_0->start_symbol); LOG_D(MAC,"(nr_ue_procedures.c) vrb_to_prb_mapping=%d \n>>> mcs=%d\n>>> ndi=%d\n>>> rv=%d\n>>> harq_process_nbr=%d\n>>> dai=%d\n>>> scaling_factor_S=%f\n>>> tpc_pucch=%d\n>>> pucch_res_ind=%d\n>>> pdsch_to_harq_feedback_time_ind=%d\n", @@ -2475,145 +2476,145 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr /* BANDWIDTH_PART_IND */ // dlsch_config_pdu_1_1->bandwidth_part_ind = dci->bandwidth_part_ind; /* FREQ_DOM_RESOURCE_ASSIGNMENT_DL */ - nr_ue_process_dci_freq_dom_resource_assignment(NULL,dlsch_config_pdu_1_1,0,n_RB_DLBWP,dci->freq_dom_resource_assignment_DL); + nr_ue_process_dci_freq_dom_resource_assignment(NULL,dlsch_config_pdu_1_1,0,n_RB_DLBWP,dci->frequency_domain_assignment.val); /* TIME_DOM_RESOURCE_ASSIGNMENT */ nr_ue_process_dci_time_dom_resource_assignment(mac,NULL,dlsch_config_pdu_1_1, - dci->time_dom_resource_assignment); + dci->time_domain_assignment.val); /* VRB_TO_PRB_MAPPING */ if (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.resource_allocation != 0) - dlsch_config_pdu_1_1->vrb_to_prb_mapping = (dci->vrb_to_prb_mapping == 0) ? vrb_to_prb_mapping_non_interleaved:vrb_to_prb_mapping_interleaved; + dlsch_config_pdu_1_1->vrb_to_prb_mapping = (dci->vrb_to_prb_mapping.val == 0) ? vrb_to_prb_mapping_non_interleaved:vrb_to_prb_mapping_interleaved; /* PRB_BUNDLING_SIZE_IND */ - dlsch_config_pdu_1_1->prb_bundling_size_ind = dci->prb_bundling_size_ind; + dlsch_config_pdu_1_1->prb_bundling_size_ind = dci->prb_bundling_size_indicator.val; /* RATE_MATCHING_IND */ - dlsch_config_pdu_1_1->rate_matching_ind = dci->rate_matching_ind; + dlsch_config_pdu_1_1->rate_matching_ind = dci->rate_matching_indicator.val; /* ZP_CSI_RS_TRIGGER */ - dlsch_config_pdu_1_1->zp_csi_rs_trigger = dci->zp_csi_rs_trigger; + dlsch_config_pdu_1_1->zp_csi_rs_trigger = dci->zp_csi_rs_trigger.val; /* MCS (for transport block 1)*/ - dlsch_config_pdu_1_1->mcs = dci->tb1_mcs; + dlsch_config_pdu_1_1->mcs = dci->mcs; /* NDI (for transport block 1)*/ - dlsch_config_pdu_1_1->ndi = dci->tb1_ndi; + dlsch_config_pdu_1_1->ndi = dci->ndi; /* RV (for transport block 1)*/ - dlsch_config_pdu_1_1->rv = dci->tb1_rv; + dlsch_config_pdu_1_1->rv = dci->rv; /* MCS (for transport block 2)*/ - dlsch_config_pdu_1_1->tb2_mcs = dci->tb2_mcs; + dlsch_config_pdu_1_1->tb2_mcs = dci->mcs2.val; /* NDI (for transport block 2)*/ - dlsch_config_pdu_1_1->tb2_ndi = dci->tb2_ndi; + dlsch_config_pdu_1_1->tb2_ndi = dci->ndi2.val; /* RV (for transport block 2)*/ - dlsch_config_pdu_1_1->tb2_rv = dci->tb2_rv; + dlsch_config_pdu_1_1->tb2_rv = dci->rv2.val; /* HARQ_PROCESS_NUMBER */ - dlsch_config_pdu_1_1->harq_process_nbr = dci->harq_process_number; + dlsch_config_pdu_1_1->harq_process_nbr = dci->harq_pid; /* DAI */ - dlsch_config_pdu_1_1->dai = dci ->dai; + dlsch_config_pdu_1_1->dai = dci->dai[0].val; /* TPC_PUCCH */ // according to TS 38.213 Table 7.2.1-1 - if (dci->tpc_pucch == 0) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = -1; - if (dci->tpc_pucch == 1) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 0; - if (dci->tpc_pucch == 2) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 1; - if (dci->tpc_pucch == 3) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 3; + if (dci->tpc == 0) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = -1; + if (dci->tpc == 1) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 0; + if (dci->tpc == 2) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 1; + if (dci->tpc == 3) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 3; /* PUCCH_RESOURCE_IND */ - if (dci->pucch_resource_ind == 0) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 1st value of resourceList FIXME!!! - if (dci->pucch_resource_ind == 1) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 2nd value of resourceList FIXME!! - if (dci->pucch_resource_ind == 2) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 3rd value of resourceList FIXME!! - if (dci->pucch_resource_ind == 3) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 4th value of resourceList FIXME!! - if (dci->pucch_resource_ind == 4) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 5th value of resourceList FIXME!! - if (dci->pucch_resource_ind == 5) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 6th value of resourceList FIXME!! - if (dci->pucch_resource_ind == 6) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 7th value of resourceList FIXME!! - if (dci->pucch_resource_ind == 7) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 8th value of resourceList FIXME!! + if (dci->pucch_resource_indicator == 0) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 1st value of resourceList FIXME!!! + if (dci->pucch_resource_indicator == 1) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 2nd value of resourceList FIXME!! + if (dci->pucch_resource_indicator == 2) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 3rd value of resourceList FIXME!! + if (dci->pucch_resource_indicator == 3) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 4th value of resourceList FIXME!! + if (dci->pucch_resource_indicator == 4) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 5th value of resourceList FIXME!! + if (dci->pucch_resource_indicator == 5) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 6th value of resourceList FIXME!! + if (dci->pucch_resource_indicator == 6) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 7th value of resourceList FIXME!! + if (dci->pucch_resource_indicator == 7) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 8th value of resourceList FIXME!! /* PDSCH_TO_HARQ_FEEDBACK_TIME_IND */ // according to TS 38.213 Table 9.2.3-1 - dlsch_config_pdu_1_1-> pdsch_to_harq_feedback_time_ind = mac->phy_config.config_req.ul_bwp_dedicated.pucch_config_dedicated.dl_data_to_ul_ack[dci->pdsch_to_harq_feedback_time_ind]; + dlsch_config_pdu_1_1-> pdsch_to_harq_feedback_time_ind = mac->phy_config.config_req.ul_bwp_dedicated.pucch_config_dedicated.dl_data_to_ul_ack[dci->pdsch_to_harq_feedback_timing_indicator.val]; /* ANTENNA_PORTS */ uint8_t n_codewords = 1; // FIXME!!! if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 1) && (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 1)){ // Table 7.3.1.2.2-1: Antenna port(s) (1000 + DMRS port), dmrs-Type=1, maxLength=1 - dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_1[dci->antenna_ports][0]; - dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_1[dci->antenna_ports][1]; - dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_1[dci->antenna_ports][2]; - dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_1[dci->antenna_ports][3]; - dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_1[dci->antenna_ports][4]; + dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_1[dci->antenna_ports.val][0]; + dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_1[dci->antenna_ports.val][1]; + dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_1[dci->antenna_ports.val][2]; + dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_1[dci->antenna_ports.val][3]; + dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_1[dci->antenna_ports.val][4]; } if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 1) && (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 2)){ // Table 7.3.1.2.2-2: Antenna port(s) (1000 + DMRS port), dmrs-Type=1, maxLength=2 if (n_codewords == 1) { - dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][0]; - dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][1]; - dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][2]; - dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][3]; - dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][4]; - dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][5]; + dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports.val][0]; + dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports.val][1]; + dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports.val][2]; + dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports.val][3]; + dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports.val][4]; + dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports.val][5]; } if (n_codewords == 1) { - dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][0]; - dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][1]; - dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][2]; - dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][3]; - dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][4]; - dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][5]; - dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][6]; - dlsch_config_pdu_1_1->dmrs_ports[6] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][7]; - dlsch_config_pdu_1_1->dmrs_ports[7] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][8]; - dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][9]; + dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][0]; + dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][1]; + dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][2]; + dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][3]; + dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][4]; + dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][5]; + dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][6]; + dlsch_config_pdu_1_1->dmrs_ports[6] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][7]; + dlsch_config_pdu_1_1->dmrs_ports[7] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][8]; + dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][9]; } } if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 2) && (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 1)){ // Table 7.3.1.2.2-3: Antenna port(s) (1000 + DMRS port), dmrs-Type=2, maxLength=1 if (n_codewords == 1) { - dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][0]; - dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][1]; - dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][2]; - dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][3]; - dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][4]; + dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports.val][0]; + dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports.val][1]; + dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports.val][2]; + dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports.val][3]; + dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports.val][4]; } if (n_codewords == 1) { - dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][0]; - dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][1]; - dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][2]; - dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][3]; - dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][4]; - dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][5]; - dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][6]; + dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports.val][0]; + dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports.val][1]; + dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports.val][2]; + dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports.val][3]; + dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports.val][4]; + dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports.val][5]; + dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports.val][6]; } } if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 2) && (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 2)){ // Table 7.3.1.2.2-4: Antenna port(s) (1000 + DMRS port), dmrs-Type=2, maxLength=2 if (n_codewords == 1) { - dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][0]; - dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][1]; - dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][2]; - dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][3]; - dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][4]; - dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][5]; + dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports.val][0]; + dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports.val][1]; + dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports.val][2]; + dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports.val][3]; + dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports.val][4]; + dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports.val][5]; } if (n_codewords == 1) { - dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][0]; - dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][1]; - dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][2]; - dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][3]; - dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][4]; - dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][5]; - dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][6]; - dlsch_config_pdu_1_1->dmrs_ports[6] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][7]; - dlsch_config_pdu_1_1->dmrs_ports[7] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][8]; - dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][9]; + dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][0]; + dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][1]; + dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][2]; + dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][3]; + dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][4]; + dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][5]; + dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][6]; + dlsch_config_pdu_1_1->dmrs_ports[6] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][7]; + dlsch_config_pdu_1_1->dmrs_ports[7] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][8]; + dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][9]; } } /* TCI */ if (mac->dl_config_request.dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.tci_present_in_dci == 1){ // 0 bit if higher layer parameter tci-PresentInDCI is not enabled // otherwise 3 bits as defined in Subclause 5.1.5 of [6, TS38.214] - dlsch_config_pdu_1_1->tci_state = dci->tci; + dlsch_config_pdu_1_1->tci_state = dci->transmission_configuration_indication.val; } /* SRS_REQUEST */ // if SUL is supported in the cell, there is an additional bit in this field and the value of this bit represents table 7.1.1.1-1 TS 38.212 FIXME!!! - dlsch_config_pdu_1_1->srs_config.aperiodicSRS_ResourceTrigger = (dci->srs_request & 0x11); // as per Table 7.3.1.1.2-24 TS 38.212 + dlsch_config_pdu_1_1->srs_config.aperiodicSRS_ResourceTrigger = (dci->srs_request.val & 0x11); // as per Table 7.3.1.1.2-24 TS 38.212 /* CBGTI */ - dlsch_config_pdu_1_1->cbgti = dci->cbgti; + dlsch_config_pdu_1_1->cbgti = dci->cbgti.val; /* CBGFI */ - dlsch_config_pdu_1_1->codeBlockGroupFlushIndicator = dci->cbgfi; + dlsch_config_pdu_1_1->codeBlockGroupFlushIndicator = dci->cbgfi.val; /* DMRS_SEQ_INI */ //FIXME!!! @@ -2713,7 +2714,7 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, uint8_t dci_size, uint16_t rnti, uint64_t *dci_pdu, - nr_dci_pdu_rel15_t *dci_pdu_rel15) { + dci_pdu_rel15_t *dci_pdu_rel15) { int rnti_type=-1; if (rnti == mac->ra_rnti) rnti_type = NR_RNTI_RA; @@ -2742,22 +2743,22 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, // Freq domain assignment fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); pos=fsize; - dci_pdu_rel15->freq_dom_resource_assignment_DL = *dci_pdu>>(dci_size-pos)&((1<frequency_domain_assignment.val = *dci_pdu>>(dci_size-pos)&((1< %d (0x%lx)\n",dci_pdu_rel15->freq_dom_resource_assignment_DL,fsize,N_RB,dci_size-pos,*dci_pdu); + LOG_D(MAC,"frequency-domain assignment %d (%d bits) N_RB_BWP %d=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,N_RB,dci_size-pos,*dci_pdu); #endif // Time domain assignment pos+=4; - dci_pdu_rel15->time_dom_resource_assignment = (*dci_pdu >> (dci_size-pos))&0xf; + dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu >> (dci_size-pos))&0xf; #ifdef DEBUG_EXTRACT_DCI - LOG_D(MAC,"time-domain assignment %d (3 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_dom_resource_assignment,dci_size-pos,*dci_pdu); + LOG_D(MAC,"time-domain assignment %d (3 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,dci_size-pos,*dci_pdu); #endif // VRB to PRB mapping pos++; - dci_pdu_rel15->vrb_to_prb_mapping = (*dci_pdu>>(dci_size-pos))&0x1; + dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu>>(dci_size-pos))&0x1; #ifdef DEBUG_EXTRACT_DCI - LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,dci_size-pos,*dci_pdu); + LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping.val,dci_size-pos,*dci_pdu); #endif // MCS pos+=5; @@ -2777,23 +2778,23 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, // indicating a DL DCI format 1bit pos++; - dci_pdu_rel15->identifier_dci_formats = (*dci_pdu>>(dci_size-pos))&1; + dci_pdu_rel15->format_indicator = (*dci_pdu>>(dci_size-pos))&1; #ifdef DEBUG_EXTRACT_DCI - LOG_D(MAC,"Format indicator %d (%d bits) N_RB_BWP %d => %d (0x%lx)\n",dci_pdu_rel15->identifier_dci_formats,1,N_RB,dci_size-pos,*dci_pdu); + LOG_D(MAC,"Format indicator %d (%d bits) N_RB_BWP %d => %d (0x%lx)\n",dci_pdu_rel15->format_indicator,1,N_RB,dci_size-pos,*dci_pdu); #endif // Freq domain assignment (275rb >> fsize = 16) fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); pos+=fsize; - dci_pdu_rel15->freq_dom_resource_assignment_DL = (*dci_pdu>>(dci_size-pos))&((1<frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1< %d (0x%lx)\n",dci_pdu_rel15->freq_dom_resource_assignment_DL,fsize,dci_size-pos,*dci_pdu); + LOG_D(MAC,"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,dci_size-pos,*dci_pdu); #endif uint16_t is_ra = 1; for (int i=0; ifreq_dom_resource_assignment_DL>>i)&1)) { + if (!((dci_pdu_rel15->frequency_domain_assignment.val>>i)&1)) { is_ra = 0; break; } @@ -2805,7 +2806,7 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, // UL/SUL indicator 1 bit pos++; - dci_pdu_rel15->sul_ind_0_1 = (*dci_pdu>>(dci_size-pos))&1; + dci_pdu_rel15->ul_sul_indicator.val = (*dci_pdu>>(dci_size-pos))&1; // SS/PBCH index 6 bits pos+=6; @@ -2821,16 +2822,16 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, // Time domain assignment 4bit pos+=4; - dci_pdu_rel15->time_dom_resource_assignment = (*dci_pdu>>(dci_size-pos))&0xf; + dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&0xf; #ifdef DEBUG_EXTRACT_DCI - LOG_D(MAC,"Time domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_dom_resource_assignment,4,dci_size-pos,*dci_pdu); + LOG_D(MAC,"Time domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,4,dci_size-pos,*dci_pdu); #endif // VRB to PRB mapping 1bit pos++; - dci_pdu_rel15->vrb_to_prb_mapping = (*dci_pdu>>(dci_size-pos))&1; + dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu>>(dci_size-pos))&1; #ifdef DEBUG_EXTRACT_DCI - LOG_D(MAC,"VRB to PRB %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,1,dci_size-pos,*dci_pdu); + LOG_D(MAC,"VRB to PRB %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping.val,1,dci_size-pos,*dci_pdu); #endif // MCS 5bit //bit over 32, so dci_pdu ++ @@ -2856,37 +2857,37 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, // HARQ process number 4bit pos+=4; - dci_pdu_rel15->harq_process_number = (*dci_pdu>>(dci_size-pos))&0xf; + dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf; #ifdef DEBUG_EXTRACT_DCI - LOG_D(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_process_number,4,dci_size-pos,*dci_pdu); + LOG_D(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_pid,4,dci_size-pos,*dci_pdu); #endif // Downlink assignment index 2bit pos+=2; - dci_pdu_rel15->dai = (*dci_pdu>>(dci_size-pos))&3; + dci_pdu_rel15->dai[0].val = (*dci_pdu>>(dci_size-pos))&3; #ifdef DEBUG_EXTRACT_DCI - LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai,2,dci_size-pos,*dci_pdu); + LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai[0].val,2,dci_size-pos,*dci_pdu); #endif // TPC command for scheduled PUCCH 2bit pos+=2; - dci_pdu_rel15->tpc_pucch = (*dci_pdu>>(dci_size-pos))&3; + dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&3; #ifdef DEBUG_EXTRACT_DCI - LOG_D(MAC,"TPC %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->tpc_pucch,2,dci_size-pos,*dci_pdu); + LOG_D(MAC,"TPC %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->tpc,2,dci_size-pos,*dci_pdu); #endif // PUCCH resource indicator 3bit pos+=3; - dci_pdu_rel15->pucch_resource_ind = (*dci_pdu>>(dci_size-pos))&0x7; + dci_pdu_rel15->pucch_resource_indicator = (*dci_pdu>>(dci_size-pos))&0x7; #ifdef DEBUG_EXTRACT_DCI - LOG_D(MAC,"PUCCH RI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pucch_resource_ind,3,dci_size-pos,*dci_pdu); + LOG_D(MAC,"PUCCH RI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pucch_resource_indicator,3,dci_size-pos,*dci_pdu); #endif // PDSCH-to-HARQ_feedback timing indicator 3bit pos+=3; - dci_pdu_rel15->pdsch_to_harq_feedback_time_ind = (*dci_pdu>>(dci_size-pos))&0x7; + dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val = (*dci_pdu>>(dci_size-pos))&0x7; #ifdef DEBUG_EXTRACT_DCI - LOG_D(MAC,"PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pdsch_to_harq_feedback_time_ind,3,dci_size-pos,*dci_pdu); + LOG_D(MAC,"PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val,3,dci_size-pos,*dci_pdu); #endif } //end else @@ -2908,7 +2909,7 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, for (int i=0; i<4; i++) *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); // VRB to PRB mapping 1 bit - *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++); // MCS 5 bit for (int i=0; i<5; i++) *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); @@ -2930,7 +2931,7 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, for (int i=0; i<4; i++) *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); // VRB to PRB mapping 1 bit - *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++); // MCS 5bit //bit over 32, so dci_pdu ++ for (int i=0; i<5; i++) *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); @@ -2943,16 +2944,16 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, case NR_RNTI_TC: // indicating a DL DCI format 1bit pos++; - dci_pdu_rel15->identifier_dci_formats = (*dci_pdu>>(dci_size-pos))&1; + dci_pdu_rel15->format_indicator = (*dci_pdu>>(dci_size-pos))&1; // Freq domain assignment 0-16 bit fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); pos+=fsize; - dci_pdu_rel15->freq_dom_resource_assignment_DL = (*dci_pdu>>(dci_size-pos))&((1<frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<time_dom_resource_assignment = (*dci_pdu>>(dci_size-pos))&0xf; + dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&0xf; // VRB to PRB mapping 1 bit - dci_pdu_rel15->vrb_to_prb_mapping = (*dci_pdu>>(dci_size-pos))&1; + dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu>>(dci_size-pos))&1; // MCS 5bit //bit over 32, so dci_pdu ++ pos+=5; dci_pdu_rel15->mcs = (*dci_pdu>>(dci_size-pos))&0x1f; @@ -2963,16 +2964,16 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, dci_pdu_rel15->rv = (*dci_pdu>>(dci_size-pos))&3; // HARQ process number 4bit pos+=4; - dci_pdu_rel15->harq_process_number = (*dci_pdu>>(dci_size-pos))&0xf; + dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf; // Downlink assignment index – 2 bits pos+=2; - dci_pdu_rel15->dai = (*dci_pdu>>(dci_size-pos))&3; + dci_pdu_rel15->dai[0].val = (*dci_pdu>>(dci_size-pos))&3; // TPC command for scheduled PUCCH – 2 bits pos+=2; - dci_pdu_rel15->tpc_pucch = (*dci_pdu>>(dci_size-pos))&3; + dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&3; // PDSCH-to-HARQ_feedback timing indicator – 3 bits pos+=3; - dci_pdu_rel15->pdsch_to_harq_feedback_time_ind = (*dci_pdu>>(dci_size-pos))&7; + dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val = (*dci_pdu>>(dci_size-pos))&7; break; } @@ -2983,17 +2984,17 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, { case NR_RNTI_C: // indicating a DL DCI format 1bit - dci_pdu_rel15->identifier_dci_formats = (*dci_pdu>>(dci_size-pos))&1; + dci_pdu_rel15->format_indicator = (*dci_pdu>>(dci_size-pos))&1; // Freq domain assignment max 16 bit fsize = (int)ceil( log2( (N_RB_UL*(N_RB_UL+1))>>1 ) ); pos+=fsize; - dci_pdu_rel15->freq_dom_resource_assignment_UL = (*dci_pdu>>(dci_size-pos))&((1<frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<time_dom_resource_assignment = (*dci_pdu>>(dci_size-pos))&0xf; + dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&0xf; // Frequency hopping flag – 1 bit pos++; - dci_pdu_rel15->freq_hopping_flag= (*dci_pdu>>(dci_size-pos))&1; + dci_pdu_rel15->frequency_hopping_flag.val= (*dci_pdu>>(dci_size-pos))&1; // MCS 5 bit pos+=5; dci_pdu_rel15->mcs= (*dci_pdu>>(dci_size-pos))&0x1f; @@ -3005,10 +3006,10 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, dci_pdu_rel15->rv= (*dci_pdu>>(dci_size-pos))&3; // HARQ process number 4bit pos+=4; - dci_pdu_rel15->harq_process_number = (*dci_pdu>>(dci_size-pos))&0xf; + dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf; // TPC command for scheduled PUSCH – 2 bits pos+=2; - dci_pdu_rel15->tpc_pusch = (*dci_pdu>>(dci_size-pos))&3; + dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&3; // UL/SUL indicator – 1 bit /* commented for now (RK): need to get this from BWP descriptor if (cfg->pucch_config.pucch_GroupHopping.value) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 23c43cda9c..a071787fef 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -341,7 +341,7 @@ int configure_fapi_dl_pdu(int Mod_idP, scc->dmrs_TypeA_Position, pdsch_pdu_rel15->NrOfSymbols); - dci_pdu_rel15_t *dci_pdu_rel15 = calloc(MAX_DCI_CORESET,sizeof(dci_pdu_rel15)); + dci_pdu_rel15_t *dci_pdu_rel15 = calloc(MAX_DCI_CORESET,sizeof(dci_pdu_rel15_t)); // bwp indicator int n_dl_bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 03480998ba..94ffcbc653 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -812,7 +812,10 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, int dci_size = nr_dci_size(secondaryCellGroup,&dci_pdu_rel15[d],dci_formats[d],rnti_types[d],pdcch_pdu_rel15->BWPSize,bwp_id); pdcch_pdu_rel15->PayloadSizeBits[d] = dci_size; AssertFatal(pdcch_pdu_rel15->PayloadSizeBits[d]<=64, "DCI sizes above 64 bits not yet supported"); - prepare_dci(secondaryCellGroup,&dci_pdu_rel15[d],dci_formats[d],bwp_id); + + if(dci_formats[d]==NR_DL_DCI_FORMAT_1_1) + prepare_dci(secondaryCellGroup,&dci_pdu_rel15[d],dci_formats[d],bwp_id); + pos = 0; /// Payload generation @@ -1136,7 +1139,7 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val&((1<frequency_domain_assignment.nbits)-1)) << (dci_size-pos); // Time domain resource assignment - pos+=nbits; + pos+=dci_pdu_rel15->time_domain_assignment.nbits; *dci_pdu |= ((uint64_t)dci_pdu_rel15->time_domain_assignment.val&((1<time_domain_assignment.nbits)-1)) << (dci_size-pos); // VRB-to-PRB mapping From 9296949906eb94d74e985ece14c587c1fba4dae2 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Thu, 9 Apr 2020 17:25:24 +0200 Subject: [PATCH 157/553] fix for dlschsim for no data in dmrs symbol --- openair1/SIMULATION/NR_PHY/dlschsim.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair1/SIMULATION/NR_PHY/dlschsim.c b/openair1/SIMULATION/NR_PHY/dlschsim.c index 8bfec90d13..fedf9394da 100644 --- a/openair1/SIMULATION/NR_PHY/dlschsim.c +++ b/openair1/SIMULATION/NR_PHY/dlschsim.c @@ -428,7 +428,7 @@ int main(int argc, char **argv) uint8_t is_crnti = 0, llr8_flag = 0; unsigned int TBS = 8424; unsigned int available_bits; - uint8_t nb_re_dmrs = 6; + uint8_t nb_re_dmrs = 12; // No data in dmrs symbol uint16_t length_dmrs = 1; unsigned char mod_order; uint16_t rate; From 1c3c5c772fb5de7207b5e3f0dce09c3fc52c94e7 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Thu, 9 Apr 2020 19:22:26 +0200 Subject: [PATCH 158/553] allocating memory to UL_INFO pdus --- executables/nr-gnb.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/executables/nr-gnb.c b/executables/nr-gnb.c index 8022ef8276..984aa56cc9 100644 --- a/executables/nr-gnb.c +++ b/executables/nr-gnb.c @@ -963,12 +963,13 @@ void init_gNB(int single_thread_flag,int wait_for_sync) { gNB->if_inst->NR_PHY_config_req = nr_phy_config_request; memset((void *)&gNB->UL_INFO,0,sizeof(gNB->UL_INFO)); LOG_I(PHY,"Setting indication lists\n"); - /*gNB->UL_INFO.rx_ind.rx_indication_body.rx_pdu_list = gNB->rx_pdu_list; - gNB->UL_INFO.crc_ind.crc_indication_body.crc_pdu_list = gNB->crc_pdu_list; - gNB->UL_INFO.sr_ind.sr_indication_body.sr_pdu_list = gNB->sr_pdu_list; - gNB->UL_INFO.harq_ind.harq_indication_body.harq_pdu_list = gNB->harq_pdu_list; - gNB->UL_INFO.cqi_ind.cqi_pdu_list = gNB->cqi_pdu_list; - gNB->UL_INFO.cqi_ind.cqi_raw_pdu_list = gNB->cqi_raw_pdu_list;*/ + gNB->UL_INFO.rx_ind.rx_indication_body.rx_pdu_list = calloc(NFAPI_RX_IND_MAX_PDU,sizeof(nfapi_rx_indication_pdu_t)); + gNB->UL_INFO.crc_ind.crc_indication_body.crc_pdu_list = calloc(NFAPI_CRC_IND_MAX_PDU,sizeof(nfapi_crc_indication_pdu_t)); + gNB->UL_INFO.sr_ind.sr_indication_body.sr_pdu_list = calloc(NFAPI_SR_IND_MAX_PDU,sizeof(nfapi_sr_indication_pdu_t)); + gNB->UL_INFO.harq_ind.harq_indication_body.harq_pdu_list = calloc(NFAPI_HARQ_IND_MAX_PDU,sizeof(nfapi_harq_indication_pdu_t)); + gNB->UL_INFO.cqi_ind.cqi_pdu_list = calloc(NFAPI_CQI_IND_MAX_PDU,sizeof(nfapi_cqi_indication_pdu_t)); + gNB->UL_INFO.cqi_ind.cqi_raw_pdu_list = calloc(NFAPI_CQI_IND_MAX_PDU,sizeof(nfapi_cqi_indication_raw_pdu_t)); + gNB->prach_energy_counter = 0; } From 221e152653a681d818b05ad8ad72e9225841e811 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 10 Apr 2020 10:43:44 +0200 Subject: [PATCH 159/553] one file left behind --- openair1/SCHED_NR/phy_procedures_nr_gNB.c | 29 ++++++++++++----------- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 12 +--------- 2 files changed, 16 insertions(+), 25 deletions(-) diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index eb949f92ed..1173899d1b 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -435,22 +435,23 @@ void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) nfapi_nr_pucch_pdu_t *pucch_pdu = &UL_tti_req->pdus_list[i].pucch_pdu; switch (pucch_pdu->format_type) { - case 0: - uci_indication->uci_list[uci_indication->num_ucis].pdu_type = NFAPI_NR_UCI_FORMAT_0_1_PDU_TYPE; - uci_indication->uci_list[uci_indication->num_ucis].pdu_size = sizeof(nfapi_nr_uci_pucch_pdu_format_0_1_t); - nfapi_nr_uci_pucch_pdu_format_0_1_t *uci_pdu_format0 = &uci_indication->uci_list[uci_indication->num_ucis].pucch_pdu_format_0_1; + case 0: + uci_indication->uci_list[uci_indication->num_ucis].pdu_type = NFAPI_NR_UCI_FORMAT_0_1_PDU_TYPE; + uci_indication->uci_list[uci_indication->num_ucis].pdu_size = sizeof(nfapi_nr_uci_pucch_pdu_format_0_1_t); + nfapi_nr_uci_pucch_pdu_format_0_1_t *uci_pdu_format0 = &uci_indication->uci_list[uci_indication->num_ucis].pucch_pdu_format_0_1; - nr_decode_pucch0(gNB, - slot_rx, - uci_pdu_format0, - pucch_pdu); + nr_decode_pucch0(gNB, + slot_rx, + uci_pdu_format0, + pucch_pdu); - uci_indication->num_ucis += 1; - break; - case 1: - break; - default: - AssertFatal(1==0,"Only PUCCH format 0 and 1 are currently supported\n"); + uci_indication->num_ucis += 1; + break; + case 1: + break; + default: + AssertFatal(1==0,"Only PUCCH format 0 and 1 are currently supported\n"); + } } } } diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index 8b802ebc23..efa4585786 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -140,10 +140,7 @@ int nr_is_dci_opportunity(nfapi_nr_search_space_t search_space, uint16_t slot, nfapi_nr_config_request_scf_t cfg); */ -<<<<<<< HEAD - -======= void nr_configure_pucch(nfapi_nr_pucch_pdu_t* pucch_pdu, NR_ServingCellConfigCommon_t *scc, NR_BWP_Uplink_t *bwp, @@ -151,13 +148,12 @@ void nr_configure_pucch(nfapi_nr_pucch_pdu_t* pucch_pdu, uint16_t O_uci, uint16_t O_ack, uint8_t SR_flag); ->>>>>>> nr_pucch + void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, int ss_type, NR_ServingCellConfigCommon_t *scc, NR_BWP_Downlink_t *bwp); -<<<<<<< HEAD void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, @@ -179,12 +175,6 @@ void nr_configure_pucch(nfapi_nr_pucch_pdu_t* pucch_pdu, uint8_t SR_flag); -======= -void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, - dci_pdu_rel15_t *dci_pdu_rel15, - int *dci_formats, - int *rnti_types); ->>>>>>> nr_pucch int get_spf(nfapi_nr_config_request_scf_t *cfg); int to_absslot(nfapi_nr_config_request_scf_t *cfg,int frame,int slot); From b6ce8ed962a56c51da3a84f15bdb5bec8594e474 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Fri, 10 Apr 2020 12:15:52 +0200 Subject: [PATCH 160/553] ENDC S1-U gNB support: Separate some GTP functions between eNB and gNB. Downlink traffic from SGW arrives properly at gNB now after path switch --- cmake_targets/CMakeLists.txt | 1 + common/utils/ocp_itti/intertask_interface.h | 1 + executables/nr-softmodem.c | 2 +- openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c | 2 +- openair2/RRC/NR/rrc_gNB_GTPV1U.c | 29 ++ openair2/RRC/NR/rrc_gNB_GTPV1U.h | 8 +- openair3/GTPV1-U/gtpv1u_gNB.c | 311 ++++++++++++++++++++ openair3/GTPV1-U/gtpv1u_gNB_task.h | 37 +++ 8 files changed, 385 insertions(+), 6 deletions(-) create mode 100644 openair3/GTPV1-U/gtpv1u_gNB.c create mode 100644 openair3/GTPV1-U/gtpv1u_gNB_task.h diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index 43e8928ae4..ac516ee213 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -2619,6 +2619,7 @@ add_executable(nr-softmodem ${OPENAIR_TARGETS}/ARCH/COMMON/record_player.c ${OPENAIR2_DIR}/RRC/NAS/nas_config.c ${OPENAIR2_DIR}/RRC/NAS/rb_config.c + ${OPENAIR3_DIR}/GTPV1-U/gtpv1u_gNB.c ${OPENAIR1_DIR}/SIMULATION/ETH_TRANSPORT/netlink_init.c ${OPENAIR_DIR}/common/utils/utils.c ${OPENAIR_DIR}/common/utils/system.c diff --git a/common/utils/ocp_itti/intertask_interface.h b/common/utils/ocp_itti/intertask_interface.h index 52c733752d..ae51f7ff42 100644 --- a/common/utils/ocp_itti/intertask_interface.h +++ b/common/utils/ocp_itti/intertask_interface.h @@ -237,6 +237,7 @@ typedef struct IttiMsgText_s { //#include #include +#include void *rrc_enb_process_itti_msg(void *); #include #include diff --git a/executables/nr-softmodem.c b/executables/nr-softmodem.c index 316ff0804b..59aa229b1a 100644 --- a/executables/nr-softmodem.c +++ b/executables/nr-softmodem.c @@ -421,7 +421,7 @@ int create_gNB_tasks(uint32_t gnb_nb) { } } - if (itti_create_task (TASK_GTPV1_U, >pv1u_eNB_task, NULL) < 0) { + if (itti_create_task (TASK_GTPV1_U, >pv1u_gNB_task, NULL) < 0) { LOG_E(GTPU, "Create task for GTPV1U failed\n"); return -1; } diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c index e34728848d..14c70e6582 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c @@ -209,7 +209,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, #ifdef DEBUG_MAC_PDU LOG_I(PHY, "Printing MAC PDU to be encoded, TBS is: %d \n", harq_process_ul_ue->TBS/8); for (i = 0; i < harq_process_ul_ue->TBS / 8; i++) { - printf("0x%02x",harq_process_ul_ue->a[i]); + printf("%02x",harq_process_ul_ue->a[i]); } printf("\n"); #endif diff --git a/openair2/RRC/NR/rrc_gNB_GTPV1U.c b/openair2/RRC/NR/rrc_gNB_GTPV1U.c index 5fee63c4c2..9ab1bbf43a 100644 --- a/openair2/RRC/NR/rrc_gNB_GTPV1U.c +++ b/openair2/RRC/NR/rrc_gNB_GTPV1U.c @@ -1,3 +1,32 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file rrc_gNB_GTPV1U.c + * \brief rrc GTPV1U procedures for gNB + * \author Lionel GAUTHIER, Panos MATZAKOS + * \version 1.0 + * \company Eurecom + * \email: lionel.gauthier@eurecom.fr, panagiotis.matzakos@eurecom.fr + */ + # include "rrc_defs.h" # include "rrc_extern.h" # include "RRC/LTE/MESSAGES/asn1_msg.h" diff --git a/openair2/RRC/NR/rrc_gNB_GTPV1U.h b/openair2/RRC/NR/rrc_gNB_GTPV1U.h index 49fa0b6ac2..caff825a7a 100644 --- a/openair2/RRC/NR/rrc_gNB_GTPV1U.h +++ b/openair2/RRC/NR/rrc_gNB_GTPV1U.h @@ -19,12 +19,12 @@ * contact@openairinterface.org */ -/*! \file rrc_eNB_GTPV1U.h - * \brief rrc GTPV1U procedures for eNB - * \author Lionel GAUTHIER +/*! \file rrc_gNB_GTPV1U.h + * \brief rrc GTPV1U procedures for gNB + * \author Lionel GAUTHIER, Panos MATZAKOS * \version 1.0 * \company Eurecom - * \email: lionel.gauthier@eurecom.fr + * \email: lionel.gauthier@eurecom.fr, panagiotis.matzakos@eurecom.fr */ #ifndef RRC_GNB_GTPV1U_H_ diff --git a/openair3/GTPV1-U/gtpv1u_gNB.c b/openair3/GTPV1-U/gtpv1u_gNB.c new file mode 100644 index 0000000000..1a75214d65 --- /dev/null +++ b/openair3/GTPV1-U/gtpv1u_gNB.c @@ -0,0 +1,311 @@ +/* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file gtpv1u_gNB.c + * \brief + * \author Sebastien ROUX, Lionel GAUTHIER, Navid Nikaein, Panos MATZAKOS + * \version 1.0 + * \company Eurecom + * \email: lionel.gauthier@eurecom.fr + */ +#include +#include + +#include "mme_config.h" +#include "intertask_interface.h" +#include "msc.h" + +#include "gtpv1u.h" +#include "NwGtpv1u.h" +#include "NwGtpv1uMsg.h" +#include "NwGtpv1uPrivate.h" +#include "NwLog.h" +#include "gtpv1u_eNB_defs.h" +#include "gtpv1_u_messages_types.h" +#include "udp_eNB_task.h" +#include "common/utils/LOG/log.h" +#include "COMMON/platform_types.h" +#include "COMMON/platform_constants.h" +#include "common/utils/LOG/vcd_signal_dumper.h" +#include "common/ran_context.h" +#include "gtpv1u_eNB_defs.h" +#include "gtpv1u_eNB_task.h" +#include "gtpv1u_gNB_task.h" +#include "rrc_eNB_GTPV1U.h" + +#undef GTP_DUMP_SOCKET + +extern unsigned char NB_eNB_INST; + +extern RAN_CONTEXT_t RC; + +extern NwGtpv1uRcT gtpv1u_eNB_send_udp_msg( + NwGtpv1uUdpHandleT udpHandle, + uint8_t *buffer, + uint32_t buffer_len, + uint32_t buffer_offset, + uint32_t peerIpAddr, + uint16_t peerPort); + +extern NwGtpv1uRcT gtpv1u_eNB_log_request(NwGtpv1uLogMgrHandleT hLogMgr, + uint32_t logLevel, + NwCharT *file, + uint32_t line, + NwCharT *logStr); + +static NwGtpv1uRcT gtpv1u_start_timer_wrapper( + NwGtpv1uTimerMgrHandleT tmrMgrHandle, + uint32_t timeoutSec, + uint32_t timeoutUsec, + uint32_t tmrType, + void *timeoutArg, + NwGtpv1uTimerHandleT *hTmr) { + NwGtpv1uRcT rc = NW_GTPV1U_OK; + long timer_id; + + if (tmrType == NW_GTPV1U_TMR_TYPE_ONE_SHOT) { + timer_setup(timeoutSec, + timeoutUsec, + TASK_GTPV1_U, + INSTANCE_DEFAULT, + TIMER_ONE_SHOT, + timeoutArg, + &timer_id); + } else { + timer_setup(timeoutSec, + timeoutUsec, + TASK_GTPV1_U, + INSTANCE_DEFAULT, + TIMER_PERIODIC, + timeoutArg, + &timer_id); + } + + return rc; +} + + +static NwGtpv1uRcT +gtpv1u_stop_timer_wrapper( + NwGtpv1uTimerMgrHandleT tmrMgrHandle, + NwGtpv1uTimerHandleT hTmr) { + NwGtpv1uRcT rc = NW_GTPV1U_OK; + return rc; +} + +/* Callback called when a gtpv1u message arrived on UDP interface */ +NwGtpv1uRcT gtpv1u_gNB_process_stack_req( + NwGtpv1uUlpHandleT hUlp, + NwGtpv1uUlpApiT *pUlpApi) { + boolean_t result = FALSE; + teid_t teid = 0; + hashtable_rc_t hash_rc = HASH_TABLE_KEY_NOT_EXISTS; + gtpv1u_teid_data_t *gtpv1u_teid_data_p = NULL; + protocol_ctxt_t ctxt; + NwGtpv1uRcT rc; + + switch(pUlpApi->apiType) { + /* Here there are two type of messages handled: + * - T-PDU + * - END-MARKER + */ + case NW_GTPV1U_ULP_API_RECV_TPDU: { + uint8_t buffer[4096]; + uint32_t buffer_len; + uint16_t msgType = NW_GTP_GPDU; + NwGtpv1uMsgT *pMsg = NULL; + /* Nw-gptv1u stack has processed a PDU. we can schedule it to PDCP + * for transmission. + */ + teid = pUlpApi->apiInfo.recvMsgInfo.teid; + pMsg = (NwGtpv1uMsgT *) pUlpApi->apiInfo.recvMsgInfo.hMsg; + msgType = pMsg->msgType; + + if (NW_GTPV1U_OK != nwGtpv1uMsgGetTpdu(pUlpApi->apiInfo.recvMsgInfo.hMsg, + buffer, &buffer_len)) { + LOG_E(GTPU, "Error while retrieving T-PDU"); + } + + itti_free(TASK_UDP, ((NwGtpv1uMsgT *)pUlpApi->apiInfo.recvMsgInfo.hMsg)->msgBuf); +#if defined(GTP_DUMP_SOCKET) && GTP_DUMP_SOCKET > 0 + gtpv1u_eNB_write_dump_socket(buffer,buffer_len); +#endif + rc = nwGtpv1uMsgDelete(RC.gtpv1u_data_g->gtpv1u_stack, + pUlpApi->apiInfo.recvMsgInfo.hMsg); + + if (rc != NW_GTPV1U_OK) { + LOG_E(GTPU, "nwGtpv1uMsgDelete failed: 0x%x\n", rc); + } + + hash_rc = hashtable_get(RC.gtpv1u_data_g->teid_mapping, teid, (void **)>pv1u_teid_data_p); + + if (hash_rc == HASH_TABLE_OK) { +#if defined(LOG_GTPU) && LOG_GTPU > 0 + LOG_D(GTPU, "Received T-PDU from gtpv1u stack teid %u size %d -> enb module id %u ue module id %u rab id %u\n", + teid, + buffer_len, + gtpv1u_teid_data_p->enb_id, + gtpv1u_teid_data_p->ue_id, + gtpv1u_teid_data_p->eps_bearer_id); +#endif + //warning "LG eps bearer mapping to DRB id to do (offset -4)" + PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, gtpv1u_teid_data_p->enb_id, ENB_FLAG_YES, gtpv1u_teid_data_p->ue_id, 0, 0,gtpv1u_teid_data_p->enb_id); + MSC_LOG_TX_MESSAGE( + MSC_GTPU_ENB, + MSC_PDCP_ENB, + NULL,0, + MSC_AS_TIME_FMT" DATA-REQ rb %u size %u", + 0,0, + (gtpv1u_teid_data_p->eps_bearer_id) ? gtpv1u_teid_data_p->eps_bearer_id - 4: 5-4, + buffer_len); + + result = pdcp_data_req( + &ctxt, + SRB_FLAG_NO, + (gtpv1u_teid_data_p->eps_bearer_id) ? gtpv1u_teid_data_p->eps_bearer_id - 4: 5-4, + 0, // mui + SDU_CONFIRM_NO, // confirm + buffer_len, + buffer, + PDCP_TRANSMISSION_MODE_DATA,NULL, NULL + ); + + if ( result == FALSE ) { + if (ctxt.configured == FALSE ) + LOG_W(GTPU, "gNB node PDCP data request failed, cause: [UE:%x]RB is not configured!\n", ctxt.rnti) ; + else + LOG_W(GTPU, "PDCP data request failed\n"); + + return NW_GTPV1U_FAILURE; + } + } else { + LOG_W(GTPU, "Received T-PDU from gtpv1u stack teid %u unknown size %u", teid, buffer_len); + } + } + break; + + default: { + LOG_E(GTPU, "Received undefined UlpApi (%02x) from gtpv1u stack!\n", + pUlpApi->apiType); + } + } // end of switch + + return NW_GTPV1U_OK; +} + +int gtpv1u_gNB_init(void) { + NwGtpv1uRcT rc = NW_GTPV1U_FAILURE; + NwGtpv1uUlpEntityT ulp; + NwGtpv1uUdpEntityT udp; + NwGtpv1uLogMgrEntityT log; + NwGtpv1uTimerMgrEntityT tmr; + // enb_properties_p = enb_config_get()->properties[0]; + RC.gtpv1u_data_g = (gtpv1u_data_t *)calloc(sizeof(gtpv1u_data_t),1); + LOG_I(GTPU, "Initializing GTPU stack %p\n",&RC.gtpv1u_data_g); + //gtpv1u_data_g.gtpv1u_stack; + /* Initialize UE hashtable */ + RC.gtpv1u_data_g->ue_mapping = hashtable_create (32, NULL, NULL); + AssertFatal(RC.gtpv1u_data_g->ue_mapping != NULL, " ERROR Initializing TASK_GTPV1_U task interface: in hashtable_create returned %p\n", RC.gtpv1u_data_g->ue_mapping); + RC.gtpv1u_data_g->teid_mapping = hashtable_create (256, NULL, NULL); + AssertFatal(RC.gtpv1u_data_g->teid_mapping != NULL, " ERROR Initializing TASK_GTPV1_U task interface: in hashtable_create\n"); + // RC.gtpv1u_data_g.enb_ip_address_for_S1u_S12_S4_up = enb_properties_p->enb_ipv4_address_for_S1U; + //gtpv1u_data_g.udp_data; + RC.gtpv1u_data_g->seq_num = 0; + RC.gtpv1u_data_g->restart_counter = 0; + + /* Initializing GTPv1-U stack */ + if ((rc = nwGtpv1uInitialize(&RC.gtpv1u_data_g->gtpv1u_stack, GTPU_STACK_ENB)) != NW_GTPV1U_OK) { + LOG_E(GTPU, "Failed to setup nwGtpv1u stack %x\n", rc); + return -1; + } + + if ((rc = nwGtpv1uSetLogLevel(RC.gtpv1u_data_g->gtpv1u_stack, + NW_LOG_LEVEL_DEBG)) != NW_GTPV1U_OK) { + LOG_E(GTPU, "Failed to setup loglevel for stack %x\n", rc); + return -1; + } + + /* Set the ULP API callback. Called once message have been processed by the + * nw-gtpv1u stack. + */ + ulp.ulpReqCallback = gtpv1u_gNB_process_stack_req; + memset((void *)&(ulp.hUlp), 0, sizeof(NwGtpv1uUlpHandleT)); + + if ((rc = nwGtpv1uSetUlpEntity(RC.gtpv1u_data_g->gtpv1u_stack, &ulp)) != NW_GTPV1U_OK) { + LOG_E(GTPU, "nwGtpv1uSetUlpEntity: %x", rc); + return -1; + } + + /* nw-gtpv1u stack requires an udp callback to send data over UDP. + * We provide a wrapper to UDP task. + */ + udp.udpDataReqCallback = gtpv1u_eNB_send_udp_msg; + memset((void *)&(udp.hUdp), 0, sizeof(NwGtpv1uUdpHandleT)); + + if ((rc = nwGtpv1uSetUdpEntity(RC.gtpv1u_data_g->gtpv1u_stack, &udp)) != NW_GTPV1U_OK) { + LOG_E(GTPU, "nwGtpv1uSetUdpEntity: %x", rc); + return -1; + } + + log.logReqCallback = gtpv1u_eNB_log_request; + memset((void *)&(log.logMgrHandle), 0, sizeof(NwGtpv1uLogMgrHandleT)); + + if ((rc = nwGtpv1uSetLogMgrEntity(RC.gtpv1u_data_g->gtpv1u_stack, &log)) != NW_GTPV1U_OK) { + LOG_E(GTPU, "nwGtpv1uSetLogMgrEntity: %x", rc); + return -1; + } + + /* Timer interface is more complicated as both wrappers doesn't send a message + * to the timer task but call the timer API functions start/stop timer. + */ + tmr.tmrMgrHandle = 0; + tmr.tmrStartCallback = gtpv1u_start_timer_wrapper; + tmr.tmrStopCallback = gtpv1u_stop_timer_wrapper; + + if ((rc = nwGtpv1uSetTimerMgrEntity(RC.gtpv1u_data_g->gtpv1u_stack, &tmr)) != NW_GTPV1U_OK) { + LOG_E(GTPU, "nwGtpv1uSetTimerMgrEntity: %x", rc); + return -1; + } + +#if defined(GTP_DUMP_SOCKET) && GTP_DUMP_SOCKET > 0 + + if ((ret = gtpv1u_eNB_create_dump_socket()) < 0) { + return -1; + } + +#endif + LOG_D(GTPU, "Initializing GTPV1U interface for eNB: DONE\n"); + return 0; +} + +void *gtpv1u_gNB_task(void *args) { + int rc = 0; + rc = gtpv1u_gNB_init(); + AssertFatal(rc == 0, "gtpv1u_eNB_init Failed"); + itti_mark_task_ready(TASK_GTPV1_U); + MSC_START_USE(); + + while(1) { + (void) gtpv1u_eNB_process_itti_msg (NULL); + } + + return NULL; +} + diff --git a/openair3/GTPV1-U/gtpv1u_gNB_task.h b/openair3/GTPV1-U/gtpv1u_gNB_task.h new file mode 100644 index 0000000000..42fae7a714 --- /dev/null +++ b/openair3/GTPV1-U/gtpv1u_gNB_task.h @@ -0,0 +1,37 @@ +/* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! \file gtpv1u_gNB_task.h +* \brief +* \author Lionel Gauthier Panos Matzakos +* \company Eurecom +* \email: lionel.gauthier@eurecom.fr +*/ + +#ifndef GTPV1U_GNB_TASK_H_ +#define GTPV1U_GNB_TASK_H_ + +int gtpv1u_gNB_init(void); + +void *gtpv1u_gNB_task(void *args); + + +#endif /* GTPV1U_GNB_TASK_H_ */ + From 6ae7548291679b3a0921b8d3af070351872db710 Mon Sep 17 00:00:00 2001 From: Florian Kaltenberger Date: Fri, 10 Apr 2020 14:15:26 +0200 Subject: [PATCH 161/553] updating doc/RUNMODEM.md --- doc/RUNMODEM.md | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/doc/RUNMODEM.md b/doc/RUNMODEM.md index 0c66b58547..70074c65ed 100644 --- a/doc/RUNMODEM.md +++ b/doc/RUNMODEM.md @@ -56,9 +56,48 @@ oai supports [number of deployment](FEATURE_SET.md) model, the following are tes 1. [Monolithic eNodeB](https://gitlab.eurecom.fr/oai/openairinterface5g/wikis/HowToConnectCOTSUEwithOAIeNBNew) where the whole signal processing is performed in a single process 2. if4p5 mode, where frequency domain samples are carried over ethernet, from the RRU which implement part of L1(FFT,IFFT,part of PRACH), to a RAU +# 5G NR + +As of February 2020, all 5G NR development is part of the develop branch (the branch develop-nr is no longer maintained). This also means that all new development will be merged into there once it passes all the CI. + +## NSA setup with COTS UE + +This setup requires an EPC, an OAI eNB and gNB, and a COTS Phone. A dedicated page describe the setup can be found [here](https://gitlab.eurecom.fr/oai/openairinterface5g/wikis/home/gNB-COTS-UE-testing). + +### Launch gNB + +```bash sudo ./nr-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf``` + +### Launch eNB + +```bash sudo ./lte-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.band7.tm1.50PRB.usrpb210.conf +## phy-test setup with OAI UE + +The OAI UE can also be used in front of a OAI gNB without the support of eNB or EPC. In this case both gNB and eNB need to be run with the --phy-test flag. At the gNB this flag does the following + - it reads the RRC configuration from the configuration file + - it encodes the RRCConfiguration and the RBconfig message and stores them in the binary files rbconfig.raw and reconfig.raw + - the MAC uses a pre-configured allocation of PDSCH and PUSCH with randomly generated payload + +At the UE the --phy-test flag will + - read the binary files rbconfig.raw and reconfig.raw from the current directory (a different directory can be specified with the flag --rrc_config_path) and process them. + + +### Launch gNB + +```bash sudo ./nr-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf --phy-test``` + +### Launch UE in another window + +```bash sudo ./nr-uesoftmodem --phy-test [--rrc_config_path ../../../ci-scripts/rrc-files]``` + +## noS1 setup with OAI UE + +Instead of randomly generated payload, in the phy-test mode we can also inject/receive user-plane traffic over a TUN interface. This is the so-called noS1 mode. + +This setup is described in the [rfsimulator page](../targets/ARCH/rfsimulator/README.md#5g-case). In theory this should also work with the real hardware target although this has yet to be tested. From 181e59db963b17279c4aed53bbb3e2b7a594686d Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Fri, 10 Apr 2020 17:54:23 +0200 Subject: [PATCH 162/553] fixing bugs in 1_1 dci --- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 16 +++++++++------- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 2 +- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index 9dd797b503..20ca1cd60b 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -667,8 +667,10 @@ uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, dci_pdu->rate_matching_indicator.nbits = 1; size += dci_pdu->rate_matching_indicator.nbits; // ZP CSI-RS trigger - uint8_t nZP = pdsch_config->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList->list.count; - dci_pdu->zp_csi_rs_trigger.nbits = (int)ceil(log2(nZP+1)); + if (pdsch_config->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList != NULL) { + uint8_t nZP = pdsch_config->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList->list.count; + dci_pdu->zp_csi_rs_trigger.nbits = (int)ceil(log2(nZP+1)); + } size += dci_pdu->zp_csi_rs_trigger.nbits; // TB1- MCS 5, NDI 1, RV 2 size += 8; @@ -716,11 +718,11 @@ uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, uint8_t maxCW = (maxCWperDCI_rrc == NULL) ? 1 : *maxCWperDCI_rrc; dci_pdu->cbgti.nbits = maxCBGperTB * maxCW; size += dci_pdu->cbgti.nbits; - } - // CBGFI - if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission->choice.setup->codeBlockGroupFlushIndicator) { - dci_pdu->cbgfi.nbits = 1; - size += dci_pdu->cbgfi.nbits; + // CBGFI + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission->choice.setup->codeBlockGroupFlushIndicator) { + dci_pdu->cbgfi.nbits = 1; + size += dci_pdu->cbgfi.nbits; + } } // DMRS sequence init size += 1; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index b7413ec1e8..b98b6ae305 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -403,7 +403,7 @@ int configure_fapi_dl_pdu(int Mod_idP, int dci_formats[2]; int rnti_types[2]; - dci_formats[0] = NR_DL_DCI_FORMAT_1_0; + dci_formats[0] = NR_DL_DCI_FORMAT_1_1; rnti_types[0] = NR_RNTI_C; fill_dci_pdu_rel15(secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types,bwp_id); From 042e4e5c77c833abcb9c139517190711fb70081c Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Mon, 13 Apr 2020 09:18:48 +0200 Subject: [PATCH 163/553] reworking of nr_configure_pdcch --- openair1/PHY/NR_TRANSPORT/nr_dci.c | 1 - .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 102 ++++++---- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 179 +++++++++++------- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 15 +- openair2/RRC/NR/rrc_gNB_reconfig.c | 2 +- 5 files changed, 188 insertions(+), 111 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.c b/openair1/PHY/NR_TRANSPORT/nr_dci.c index d62687bd9c..5c4df1b4ed 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.c @@ -230,7 +230,6 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, uint32_t encoder_output[NR_MAX_DCI_SIZE_DWORD]; uint16_t n_RNTI = pdcch_pdu_rel15->RNTI[d]; uint16_t Nid = pdcch_pdu_rel15->ScramblingId[d]; - t_nrPolar_params *currentPtr = nr_polar_params(NR_POLAR_DCI_MESSAGE_TYPE, pdcch_pdu_rel15->PayloadSizeBits[d], pdcch_pdu_rel15->AggregationLevel[d], diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index b7413ec1e8..6b3efae991 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -251,7 +251,6 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP, int configure_fapi_dl_pdu(int Mod_idP, - int *CCEIndex, nfapi_nr_dl_tti_request_body_t *dl_req, NR_sched_pucch *pucch_sched, uint8_t *mcsIndex, @@ -387,23 +386,43 @@ int configure_fapi_dl_pdu(int Mod_idP, dci_pdu_rel15[0].tb_scaling, dci_pdu_rel15[0].ndi, dci_pdu_rel15[0].rv); + + NR_SearchSpace_t *ss; + int target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific; + + AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n"); + AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0, + "searchPsacesToAddModList is empty\n"); + + int found=0; + + for (int i=0;ibwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count;i++) { + ss=bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[i]; + AssertFatal(ss->controlResourceSetId != NULL,"ss->controlResourceSetId is null\n"); + AssertFatal(ss->searchSpaceType != NULL,"ss->searchSpaceType is null\n"); + if (ss->searchSpaceType->present == target_ss) { + found=1; + break; + } + } + AssertFatal(found==1,"Couldn't find an adequate searchspace\n"); - nr_configure_pdcch(pdcch_pdu_rel15, - 1, // ue-specific + nr_configure_pdcch(nr_mac, + pdcch_pdu_rel15, + UE_list->rnti[UE_id], + ss, scc, bwp); - - pdcch_pdu_rel15->numDlDci = 1; - pdcch_pdu_rel15->AggregationLevel[0] = 4; - pdcch_pdu_rel15->RNTI[0]=UE_list->rnti[0]; - pdcch_pdu_rel15->CceIndex[0] = CCEIndex[0]; - pdcch_pdu_rel15->beta_PDCCH_1_0[0]=0; - pdcch_pdu_rel15->powerControlOffsetSS[0]=1; + int dci_formats[2]; int rnti_types[2]; - dci_formats[0] = NR_DL_DCI_FORMAT_1_0; + if (ss->searchSpaceType->choice.ue_Specific->dci_Formats) + dci_formats[0] = NR_DL_DCI_FORMAT_1_0; + else + dci_formats[0] = NR_DL_DCI_FORMAT_1_1; + rnti_types[0] = NR_RNTI_C; fill_dci_pdu_rel15(secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types,bwp_id); @@ -517,7 +536,7 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, int post_padding = 0, ta_len = 0, header_length_total = 0, sdu_length_total = 0, num_sdus = 0; int lcid, offset, i, header_length_last, TBS_bytes; - int UE_id = 0, CCEIndex = -1, CC_id = 0; + int UE_id = 0, CC_id = 0; gNB_MAC_INST *gNB_mac = RC.nrmac[module_idP]; //NR_COMMON_channels_t *cc = nr_mac->common_channels; @@ -541,22 +560,7 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, ta_len = gNB_mac->ta_len; - CCEIndex = allocate_nr_CCEs(gNB_mac, - 1, // bwp_id - 0, // coreset_id - 4, // aggregation, - 1, // search_space, 0 common, 1 ue-specific - UE_id, - 0); // m - - if (CCEIndex == -1) return; - - AssertFatal(CCEIndex>0,"CCEIndex is negative\n"); - int CCEIndices[2]; - CCEIndices[0] = CCEIndex; - TBS_bytes = configure_fapi_dl_pdu(module_idP, - CCEIndices, dl_req, pucch_sched, dlsch_config!=NULL ? dlsch_config->mcsIndex : NULL, @@ -827,29 +831,43 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, int dci_formats[2]; int rnti_types[2]; - int CCEIndex = allocate_nr_CCEs(nr_mac, - 1, // bwp_id - 0, // coreset_id - 4, // aggregation, - 1, // search_space, 0 common, 1 ue-specific - UE_id, - 0); // m + NR_SearchSpace_t *ss; + int target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific; + + AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n"); + AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0, + "searchPsacesToAddModList is empty\n"); + + int found=0; + + for (int i=0;ibwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count;i++) { + ss=bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[i]; + AssertFatal(ss->controlResourceSetId != NULL,"ss->controlResourceSetId is null\n"); + AssertFatal(ss->searchSpaceType != NULL,"ss->searchSpaceType is null\n"); + if (ss->searchSpaceType->present == target_ss) { + found=1; + break; + } + } + AssertFatal(found==1,"Couldn't find an adequate searchspace\n"); + + if (ss->searchSpaceType->choice.ue_Specific->dci_Formats) + dci_formats[0] = NR_UL_DCI_FORMAT_0_1; + else + dci_formats[0] = NR_UL_DCI_FORMAT_0_0; - dci_formats[0] = NR_UL_DCI_FORMAT_0_0; rnti_types[0] = NR_RNTI_C; LOG_D(MAC,"Configuring ULDCI/PDCCH in %d.%d\n", frameP,slotP); - nr_configure_pdcch(pdcch_pdu_rel15, - 1, // ue-specific, + + nr_configure_pdcch(nr_mac, + pdcch_pdu_rel15, + UE_list->rnti[UE_id], + ss, scc, bwp); dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET]; - AssertFatal(CCEIndex>=0,"CCEIndex is negative \n"); - pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci] = CCEIndex; - - LOG_D(PHY,"CCEIndex %d\n",pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci]); - config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); fill_dci_pdu_rel15(secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types,bwp_id); diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index a3e21159ac..eee248e927 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -182,8 +182,8 @@ int allocate_nr_CCEs(gNB_MAC_INST *nr_mac, } int first_cce = aggregation * (( Y + (m*N_cce)/(aggregation*M_s_max) + n_CI ) % CEILIDIV(N_cce,aggregation)); - for (int i=0;iconfig_type = NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG; AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList!=NULL, "controlResourceSetToAddModList is null\n"); - AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.count>0, + int num_list = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.count; + AssertFatal(num_list>0, "controlResourceSetToAddModList is empty\n"); - NR_ControlResourceSet_t *coreset0 = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[0]; - - + NR_ControlResourceSet_t *coreset; + int coresetid=-1; + for (int i=0;ibwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[i]; + if (coreset->controlResourceSetId == *ss->controlResourceSetId) { + coresetid = i; + break; + } + } + AssertFatal(coresetid>-1,"Couldn't find a coreset with ID %ld\n",*ss->controlResourceSetId); + pdcch_pdu->BWPSize = NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275); pdcch_pdu->BWPStart = NRRIV2PRBOFFSET(bwp->bwp_Common->genericParameters.locationAndBandwidth,275); pdcch_pdu->SubcarrierSpacing = bwp->bwp_Common->genericParameters.subcarrierSpacing; pdcch_pdu->CyclicPrefix = (bwp->bwp_Common->genericParameters.cyclicPrefix==NULL) ? 0 : *bwp->bwp_Common->genericParameters.cyclicPrefix; - pdcch_pdu->DurationSymbols = coreset0->duration; + pdcch_pdu->DurationSymbols = coreset->duration; //frequencyDomainResources /* uint8_t count=0, start=0, start_set=0; // find coreset descriptor - uint64_t bitmap = (((uint64_t)coreset0->frequencyDomainResources.buf[0])<<37)| - (((uint64_t)coreset0->frequencyDomainResources.buf[1])<<29)| - (((uint64_t)coreset0->frequencyDomainResources.buf[2])<<21)| - (((uint64_t)coreset0->frequencyDomainResources.buf[3])<<13)| - (((uint64_t)coreset0->frequencyDomainResources.buf[4])<<5)| - (((uint64_t)coreset0->frequencyDomainResources.buf[5])>>3); + uint64_t bitmap = (((uint64_t)coreset->frequencyDomainResources.buf[0])<<37)| + (((uint64_t)coreset->frequencyDomainResources.buf[1])<<29)| + (((uint64_t)coreset->frequencyDomainResources.buf[2])<<21)| + (((uint64_t)coreset->frequencyDomainResources.buf[3])<<13)| + (((uint64_t)coreset->frequencyDomainResources.buf[4])<<5)| + (((uint64_t)coreset->frequencyDomainResources.buf[5])>>3); for (int i=0; i<45; i++) if ((bitmap>>(44-i))&1) { @@ -456,18 +469,18 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, pdcch_pdu->n_rb = 6*count; */ for (int i=0;i<6;i++) - pdcch_pdu->FreqDomainResource[i] = coreset0->frequencyDomainResources.buf[i]; + pdcch_pdu->FreqDomainResource[i] = coreset->frequencyDomainResources.buf[i]; //duration //cce-REG-MappingType - pdcch_pdu->CceRegMappingType = coreset0->cce_REG_MappingType.present == NR_ControlResourceSet__cce_REG_MappingType_PR_interleaved? + pdcch_pdu->CceRegMappingType = coreset->cce_REG_MappingType.present == NR_ControlResourceSet__cce_REG_MappingType_PR_interleaved? NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED : NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED; if (pdcch_pdu->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) { - pdcch_pdu->RegBundleSize = (coreset0->cce_REG_MappingType.choice.interleaved->reg_BundleSize == NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n6) ? 6 : (2+coreset0->cce_REG_MappingType.choice.interleaved->reg_BundleSize); - pdcch_pdu->InterleaverSize = (coreset0->cce_REG_MappingType.choice.interleaved->interleaverSize==NR_ControlResourceSet__cce_REG_MappingType__interleaved__interleaverSize_n6) ? 6 : (2+coreset0->cce_REG_MappingType.choice.interleaved->interleaverSize); + pdcch_pdu->RegBundleSize = (coreset->cce_REG_MappingType.choice.interleaved->reg_BundleSize == NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n6) ? 6 : (2+coreset->cce_REG_MappingType.choice.interleaved->reg_BundleSize); + pdcch_pdu->InterleaverSize = (coreset->cce_REG_MappingType.choice.interleaved->interleaverSize==NR_ControlResourceSet__cce_REG_MappingType__interleaved__interleaverSize_n6) ? 6 : (2+coreset->cce_REG_MappingType.choice.interleaved->interleaverSize); AssertFatal(scc->physCellId != NULL,"scc->physCellId is null\n"); - pdcch_pdu->ShiftIndex = coreset0->cce_REG_MappingType.choice.interleaved->shiftIndex != NULL ? *coreset0->cce_REG_MappingType.choice.interleaved->shiftIndex : *scc->physCellId; + pdcch_pdu->ShiftIndex = coreset->cce_REG_MappingType.choice.interleaved->shiftIndex != NULL ? *coreset->cce_REG_MappingType.choice.interleaved->shiftIndex : *scc->physCellId; } else { pdcch_pdu->RegBundleSize = 0; @@ -478,56 +491,27 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, pdcch_pdu->CoreSetType = 1; //precoderGranularity - pdcch_pdu->precoderGranularity = coreset0->precoderGranularity; + pdcch_pdu->precoderGranularity = coreset->precoderGranularity; //TCI states // /* //TCI present - if (coreset0->tci_PresentInDCI != NULL) { - AssertFatal(coreset0->tci_StatesPDCCH_ToAddList != NULL,"tci_StatesPDCCH_ToAddList is null\n"); - AssertFatal(coreset0->tci_StatesPDCCH_ToAddList->list.count>0,"TCI state list is empty\n"); - for (int i=0;itci_StatesPDCCH_ToAddList->list.count;i++) { + if (coreset->tci_PresentInDCI != NULL) { + AssertFatal(coreset->tci_StatesPDCCH_ToAddList != NULL,"tci_StatesPDCCH_ToAddList is null\n"); + AssertFatal(coreset->tci_StatesPDCCH_ToAddList->list.count>0,"TCI state list is empty\n"); + for (int i=0;itci_StatesPDCCH_ToAddList->list.count;i++) { } */ - for (int i=0;inumDlDci;i++) { - //pdcch-DMRS-ScramblingID - AssertFatal(coreset0->pdcch_DMRS_ScramblingID != NULL,"coreset0->pdcch_DMRS_ScramblingID is null\n"); - pdcch_pdu->ScramblingId[i] = *coreset0->pdcch_DMRS_ScramblingID; - } - - /// SearchSpace + AssertFatal(ss->monitoringSymbolsWithinSlot!=NULL,"ss->monitoringSymbolsWithinSlot is null\n"); + AssertFatal(ss->monitoringSymbolsWithinSlot->buf!=NULL,"ss->monitoringSymbolsWithinSlot->buf is null\n"); // first symbol //AssertFatal(pdcch_scs==kHz15, "PDCCH SCS above 15kHz not allowed if a symbol above 2 is monitored"); int sps = bwp->bwp_Common->genericParameters.cyclicPrefix == NULL ? 14 : 12; - AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n"); - AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0, - "searchPsacesToAddModList is empty\n"); - NR_SearchSpace_t *ss; - int found=0; - int target_ss = NR_SearchSpace__searchSpaceType_PR_common; - if (ss_type == 1) { - target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific; - } - - for (int i=0;ibwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count;i++) { - ss=bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[i]; - AssertFatal(ss->controlResourceSetId != NULL,"ss->controlResourceSetId is null\n"); - AssertFatal(ss->searchSpaceType != NULL,"ss->searchSpaceType is null\n"); - if (*ss->controlResourceSetId == coreset0->controlResourceSetId && - ss->searchSpaceType->present == target_ss) { - found=1; - break; - } - } - AssertFatal(found==1,"Couldn't find a searchspace corresponding to coreset0\n"); - AssertFatal(ss->monitoringSymbolsWithinSlot!=NULL,"ss->monitoringSymbolsWithinSlot is null\n"); - AssertFatal(ss->monitoringSymbolsWithinSlot->buf!=NULL,"ss->monitoringSymbolsWithinSlot->buf is null\n"); - // for SPS=14 8 MSBs in positions 13 downto 6, uint16_t monitoringSymbolsWithinSlot = (ss->monitoringSymbolsWithinSlot->buf[0]<<(sps-8)) | (ss->monitoringSymbolsWithinSlot->buf[1]>>(16-sps)); @@ -537,6 +521,43 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, pdcch_pdu->StartSymbolIndex=i; break; } + + pdcch_pdu->RNTI[pdcch_pdu->numDlDci]=rnti; + + if (coreset->pdcch_DMRS_ScramblingID != NULL && + ss->searchSpaceType->present == NR_SearchSpace__searchSpaceType_PR_ue_Specific) { + pdcch_pdu->ScramblingId[pdcch_pdu->numDlDci] = *coreset->pdcch_DMRS_ScramblingID; + pdcch_pdu->ScramblingRNTI[pdcch_pdu->numDlDci]=rnti; + } + else { + pdcch_pdu->ScramblingId[pdcch_pdu->numDlDci] = *scc->physCellId; + pdcch_pdu->ScramblingRNTI[pdcch_pdu->numDlDci]=0; + } + + uint8_t nr_of_candidates,aggregation_level; + + find_aggregation_candidates(&aggregation_level, + &nr_of_candidates, + ss); + + CCEIndex = allocate_nr_CCEs(nr_mac, + 1, // bwp_id + coresetid, + aggregation_level, + ss->searchSpaceType->present-1, // search_space, 0 common, 1 ue-specific + 0, // UE-id + 0); // m + + AssertFatal(CCEIndex>=0,"CCEIndex is negative \n"); + + pdcch_pdu->AggregationLevel[pdcch_pdu->numDlDci] = aggregation_level; + pdcch_pdu->CceIndex[pdcch_pdu->numDlDci] = CCEIndex; + + if (ss->searchSpaceType->choice.ue_Specific->dci_Formats==NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_0_And_1_0) + pdcch_pdu->beta_PDCCH_1_0[pdcch_pdu->numDlDci]=0; + + pdcch_pdu->powerControlOffsetSS[pdcch_pdu->numDlDci]=1; + pdcch_pdu->numDlDci++; } else { // this is for InitialBWP @@ -545,7 +566,6 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, } - // This function configures pucch pdu fapi structure void nr_configure_pucch(nfapi_nr_pucch_pdu_t* pucch_pdu, NR_ServingCellConfigCommon_t *scc, @@ -1386,28 +1406,33 @@ void get_pdsch_to_harq_feedback(int Mod_idP, pdsch_to_harq_feedback[i] = i+1; } else { + // searching for a ue specific search space int found=0; - + for (int i=0;ibwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count;i++) { ss=bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[i]; AssertFatal(ss->controlResourceSetId != NULL,"ss->controlResourceSetId is null\n"); AssertFatal(ss->searchSpaceType != NULL,"ss->searchSpaceType is null\n"); if (ss->searchSpaceType->present == ss_type) { - found=1; - break; + found=1; + break; } } AssertFatal(found==1,"Couldn't find a ue specific searchspace\n"); + + if (ss->searchSpaceType->choice.ue_Specific->dci_Formats == NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_0_And_1_0) { for (int i=0; i<8; i++) pdsch_to_harq_feedback[i] = i+1; } else { - if(ubwp->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK != NULL) - pdsch_to_harq_feedback = (uint8_t *)ubwp->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK; + if(ubwp->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK != NULL) { + for (int i=0; i<8; i++) + pdsch_to_harq_feedback[i] = *ubwp->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK->list.array[i]; + } else - AssertFatal(found==1,"There is no allocated dl_DataToUL_ACK for pdsch to harq feedback\n"); + AssertFatal(0==1,"There is no allocated dl_DataToUL_ACK for pdsch to harq feedback\n"); } } } @@ -1531,6 +1556,32 @@ void nr_update_pucch_scheduling(int Mod_idP, } +void find_aggregation_candidates(uint8_t *aggregation_level, + uint8_t *nr_of_candidates, + NR_SearchSpace_t *ss) { + + if (ss->nrofCandidates->aggregationLevel1 != NR_SearchSpace__nrofCandidates__aggregationLevel1_n0) { + *aggregation_level = 1; + *nr_of_candidates = ss->nrofCandidates->aggregationLevel1; + } + if (ss->nrofCandidates->aggregationLevel2 != NR_SearchSpace__nrofCandidates__aggregationLevel2_n0) { + *aggregation_level = 2; + *nr_of_candidates = ss->nrofCandidates->aggregationLevel2; + } + if (ss->nrofCandidates->aggregationLevel4 != NR_SearchSpace__nrofCandidates__aggregationLevel4_n0) { + *aggregation_level = 4; + *nr_of_candidates = ss->nrofCandidates->aggregationLevel4; + } + if (ss->nrofCandidates->aggregationLevel8 != NR_SearchSpace__nrofCandidates__aggregationLevel8_n0) { + *aggregation_level = 8; + *nr_of_candidates = ss->nrofCandidates->aggregationLevel8; + } + if (ss->nrofCandidates->aggregationLevel16 != NR_SearchSpace__nrofCandidates__aggregationLevel16_n0) { + *aggregation_level = 16; + *nr_of_candidates = ss->nrofCandidates->aggregationLevel16; + } +} + /*void fill_nfapi_coresets_and_searchspaces(NR_CellGroupConfig_t *cg, nfapi_nr_coreset_t *coreset, nfapi_nr_search_space_t *search_space) { diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index efa4585786..9993e650ca 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -83,7 +83,6 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP, sub_frame_t subframeP); int configure_fapi_dl_pdu(int Mod_id, - int *CCEIndeces, nfapi_nr_dl_tti_request_body_t *dl_req, NR_sched_pucch *pucch_sched, uint8_t *mcsIndex, @@ -149,8 +148,14 @@ void nr_configure_pucch(nfapi_nr_pucch_pdu_t* pucch_pdu, uint16_t O_ack, uint8_t SR_flag); -void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, - int ss_type, +void find_search_space(int ss_type, + NR_BWP_Downlink_t *bwp, + NR_SearchSpace_t *ss); + +void nr_configure_pdcch(gNB_MAC_INST *nr_mac, + nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, + uint16_t rnti, + NR_SearchSpace_t *ss, NR_ServingCellConfigCommon_t *scc, NR_BWP_Downlink_t *bwp); @@ -166,6 +171,10 @@ void prepare_dci(NR_CellGroupConfig_t *secondaryCellGroup, nr_dci_format_t format, int bwp_id); +void find_aggregation_candidates(uint8_t *aggregation_level, + uint8_t *nr_of_candidates, + NR_SearchSpace_t *ss); + void nr_configure_pucch(nfapi_nr_pucch_pdu_t* pucch_pdu, NR_ServingCellConfigCommon_t *scc, NR_BWP_Uplink_t *bwp, diff --git a/openair2/RRC/NR/rrc_gNB_reconfig.c b/openair2/RRC/NR/rrc_gNB_reconfig.c index a695018c83..08cf33c80f 100644 --- a/openair2/RRC/NR/rrc_gNB_reconfig.c +++ b/openair2/RRC/NR/rrc_gNB_reconfig.c @@ -555,7 +555,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ss2->searchSpaceType=calloc(1,sizeof(*ss2->searchSpaceType)); ss2->searchSpaceType->present = NR_SearchSpace__searchSpaceType_PR_ue_Specific; ss2->searchSpaceType->choice.ue_Specific = calloc(1,sizeof(*ss2->searchSpaceType->choice.ue_Specific)); - ss2->searchSpaceType->choice.ue_Specific->dci_Formats=NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_0_And_1_0; + ss2->searchSpaceType->choice.ue_Specific->dci_Formats=NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_1_And_1_1; ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list, ss3); From 478a3f73e2c2db99823357cfc3a8f8254a279284 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Mon, 13 Apr 2020 15:29:40 +0200 Subject: [PATCH 164/553] bugfix for coreset id --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 1cc55b79ff..d8770a51e7 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -418,7 +418,7 @@ void nr_configure_pdcch(gNB_MAC_INST *nr_mac, NR_BWP_Downlink_t *bwp){ int CCEIndex = -1; - + int cid; NR_ControlResourceSet_t *coreset = NULL; if (bwp) { // This is not the InitialBWP @@ -439,6 +439,7 @@ void nr_configure_pdcch(gNB_MAC_INST *nr_mac, temp_coreset = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[i]; if (coresetid==temp_coreset->controlResourceSetId) { coreset = temp_coreset; + cid = i; break; } } @@ -517,7 +518,7 @@ void nr_configure_pdcch(gNB_MAC_INST *nr_mac, CCEIndex = allocate_nr_CCEs(nr_mac, 1, // bwp_id - coresetid, + cid, aggregation_level, ss->searchSpaceType->present-1, // search_space, 0 common, 1 ue-specific 0, // UE-id From 745d8a387688aa68a2352f58bdb6eb6840884b93 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Tue, 14 Apr 2020 01:30:35 +0200 Subject: [PATCH 165/553] setting dmrs type for 1_1 dci --- openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c | 2 +- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c index e734ce10a5..6379166429 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c @@ -174,7 +174,7 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_ else rel15->coreset.pdcch_dmrs_scrambling_id = *mac->scc->physCellId; fill_dci_search_candidates(mac->SSpace[0][0][ss_id],rel15); - rel15->dci_format = NR_DL_DCI_FORMAT_1_0; + rel15->dci_format = NR_DL_DCI_FORMAT_1_1; rel15->dci_length = nr_dci_size(mac->scg,def_dci_pdu_rel15,rel15->dci_format,NR_RNTI_C,rel15->BWPSize,bwp_id); dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI; dl_config->number_pdus = dl_config->number_pdus + 1; diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 5ebd57fd19..3214f7be61 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -2480,6 +2480,11 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, dc /* TIME_DOM_RESOURCE_ASSIGNMENT */ nr_ue_process_dci_time_dom_resource_assignment(mac,NULL,dlsch_config_pdu_1_1, dci->time_domain_assignment.val); + /* dmrs symbol positions*/ + dlsch_config_pdu_1_1->dlDmrsSymbPos = fill_dmrs_mask(pdsch_config, + mac->scc->dmrs_TypeA_Position, + dlsch_config_pdu_1_1->number_symbols); + dlsch_config_pdu_1_1->dmrsConfigType = mac->DLbwp[0]->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type == NULL ? 1 : 2; /* VRB_TO_PRB_MAPPING */ if (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.resource_allocation != 0) dlsch_config_pdu_1_1->vrb_to_prb_mapping = (dci->vrb_to_prb_mapping.val == 0) ? vrb_to_prb_mapping_non_interleaved:vrb_to_prb_mapping_interleaved; From 3e70405b582609c9d595c703eb0e5b0c1bda972d Mon Sep 17 00:00:00 2001 From: cig Date: Thu, 9 Apr 2020 16:39:44 +0200 Subject: [PATCH 166/553] Cleanup transport_proto header --- executables/nr-gnb.c | 2 +- executables/nr-ru.c | 2 +- openair1/PHY/INIT/nr_init.c | 2 +- openair1/PHY/INIT/nr_init_ru.c | 2 +- openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c | 2 +- openair1/PHY/NR_TRANSPORT/nr_pbch.c | 1 + openair1/PHY/NR_TRANSPORT/nr_prach.c | 2 +- openair1/PHY/NR_TRANSPORT/nr_pss.c | 2 +- openair1/PHY/NR_TRANSPORT/nr_sss.c | 2 +- openair1/PHY/NR_TRANSPORT/nr_transport.h | 116 ---------------- .../PHY/NR_TRANSPORT/nr_transport_proto.h | 128 ++++++++++++++++-- openair1/SCHED_NR/nr_prach_procedures.c | 2 +- openair1/SIMULATION/NR_PHY/dlschsim.c | 2 +- openair1/SIMULATION/NR_PHY/dlsim.c | 2 +- openair1/SIMULATION/NR_PHY/pbchsim.c | 2 +- openair1/SIMULATION/NR_PHY/prachsim.c | 2 +- openair1/SIMULATION/NR_PHY/pucchsim.c | 2 +- openair1/SIMULATION/NR_PHY/ulschsim.c | 2 +- 18 files changed, 129 insertions(+), 146 deletions(-) diff --git a/executables/nr-gnb.c b/executables/nr-gnb.c index 8121332ac7..f457db5c02 100644 --- a/executables/nr-gnb.c +++ b/executables/nr-gnb.c @@ -47,7 +47,7 @@ #include "SCHED/sched_eNB.h" #include "SCHED_NR/sched_nr.h" #include "SCHED_NR/fapi_nr_l1.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #undef MALLOC //there are two conflicting definitions, so we better make sure we don't use it at all //#undef FRAME_LENGTH_COMPLEX_SAMPLES //there are two conflicting definitions, so we better make sure we don't use it at all diff --git a/executables/nr-ru.c b/executables/nr-ru.c index 105b6b849a..3dd367d505 100644 --- a/executables/nr-ru.c +++ b/executables/nr-ru.c @@ -68,7 +68,7 @@ #include "PHY/defs_nr_common.h" #include "PHY/phy_extern.h" #include "PHY/LTE_TRANSPORT/transport_proto.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "PHY/INIT/phy_init.h" #include "SCHED/sched_eNB.h" #include "SCHED_NR/sched_nr.h" diff --git a/openair1/PHY/INIT/nr_init.c b/openair1/PHY/INIT/nr_init.c index 62fb89aebb..74f3aa2d04 100644 --- a/openair1/PHY/INIT/nr_init.c +++ b/openair1/PHY/INIT/nr_init.c @@ -25,7 +25,7 @@ #include "PHY/NR_REFSIG/nr_refsig.h" #include "PHY/INIT/phy_init.h" #include "PHY/CODING/nrPolar_tools/nr_polar_pbch_defs.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "PHY/NR_TRANSPORT/nr_transport_proto_common.h" /*#include "RadioResourceConfigCommonSIB.h" #include "RadioResourceConfigDedicated.h" diff --git a/openair1/PHY/INIT/nr_init_ru.c b/openair1/PHY/INIT/nr_init_ru.c index 60921da1cb..ead2538e75 100644 --- a/openair1/PHY/INIT/nr_init_ru.c +++ b/openair1/PHY/INIT/nr_init_ru.c @@ -22,7 +22,7 @@ #include "phy_init.h" #include "SCHED/sched_common.h" #include "PHY/phy_extern.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "SIMULATION/TOOLS/sim.h" /*#include "RadioResourceConfigCommonSIB.h" #include "RadioResourceConfigDedicated.h" diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c index 065e62a2cb..94ac937bba 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c @@ -36,7 +36,7 @@ #include "PHY/CODING/coding_defs.h" #include "PHY/CODING/lte_interleaver_inline.h" #include "PHY/CODING/nrLDPC_extern.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" #include "PHY/NR_TRANSPORT/nr_dlsch.h" #include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h" diff --git a/openair1/PHY/NR_TRANSPORT/nr_pbch.c b/openair1/PHY/NR_TRANSPORT/nr_pbch.c index b6a4787193..923e920321 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_pbch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_pbch.c @@ -32,6 +32,7 @@ */ #include "PHY/defs_gNB.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "PHY/NR_TRANSPORT/nr_transport.h" #include "PHY/LTE_REFSIG/lte_refsig.h" #include "PHY/sse_intrin.h" diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index 2a29d16e0c..c856d29f3c 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -31,7 +31,7 @@ */ #include "PHY/defs_gNB.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "PHY/NR_TRANSPORT/nr_transport_proto_common.h" extern uint16_t prach_root_sequence_map_0_3[838]; diff --git a/openair1/PHY/NR_TRANSPORT/nr_pss.c b/openair1/PHY/NR_TRANSPORT/nr_pss.c index be9e011e60..535ce99143 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_pss.c +++ b/openair1/PHY/NR_TRANSPORT/nr_pss.c @@ -20,7 +20,7 @@ */ -#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" //#define NR_PSS_DEBUG diff --git a/openair1/PHY/NR_TRANSPORT/nr_sss.c b/openair1/PHY/NR_TRANSPORT/nr_sss.c index 7d8b551d7c..de92237f6c 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_sss.c +++ b/openair1/PHY/NR_TRANSPORT/nr_sss.c @@ -19,7 +19,7 @@ * contact@openairinterface.org */ -#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" //#define NR_SSS_DEBUG diff --git a/openair1/PHY/NR_TRANSPORT/nr_transport.h b/openair1/PHY/NR_TRANSPORT/nr_transport.h index 157e309228..9597de10a7 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_transport.h +++ b/openair1/PHY/NR_TRANSPORT/nr_transport.h @@ -22,122 +22,6 @@ #ifndef __NR_TRANSPORT__H__ #define __NR_TRANSPORT__H__ -#include "PHY/defs_gNB.h" -#include "LAYER2/NR_MAC_gNB/mac_proto.h" - #define NR_PBCH_PDU_BITS 24 -/*! -\fn int nr_generate_pss -\brief Generation of the NR PSS -@param -@returns 0 on success - */ -int nr_generate_pss( int16_t *d_pss, - int32_t *txdataF, - int16_t amp, - uint8_t ssb_start_symbol, - nfapi_nr_config_request_scf_t *config, - NR_DL_FRAME_PARMS *frame_parms); - -/*! -\fn int nr_generate_sss -\brief Generation of the NR SSS -@param -@returns 0 on success - */ -int nr_generate_sss( int16_t *d_sss, - int32_t *txdataF, - int16_t amp, - uint8_t ssb_start_symbol, - nfapi_nr_config_request_scf_t *config, - NR_DL_FRAME_PARMS *frame_parms); - -/*! -\fn int nr_generate_pbch_dmrs -\brief Generation of the DMRS for the PBCH -@param -@returns 0 on success - */ -int nr_generate_pbch_dmrs(uint32_t *gold_pbch_dmrs, - int32_t *txdataF, - int16_t amp, - uint8_t ssb_start_symbol, - nfapi_nr_config_request_scf_t *config, - NR_DL_FRAME_PARMS *frame_parms); - -/*! -\fn int nr_pbch_scrambling -\brief PBCH scrambling function -@param - */ -void nr_pbch_scrambling(NR_gNB_PBCH *pbch, - uint32_t Nid, - uint8_t nushift, - uint16_t M, - uint16_t length, - uint8_t encoded, - uint32_t unscrambling_mask); - -/*! -\fn int nr_generate_pbch -\brief Generation of the PBCH -@param -@returns 0 on success - */ -int nr_generate_pbch(NR_gNB_PBCH *pbch, - nfapi_nr_dl_tti_ssb_pdu *ssb_pdu, - uint8_t *interleaver, - int32_t *txdataF, - int16_t amp, - uint8_t ssb_start_symbol, - uint8_t n_hf, - int sfn, - nfapi_nr_config_request_scf_t *config, - NR_DL_FRAME_PARMS *frame_parms); - -/*! -\fn int nr_generate_pbch -\brief PBCH interleaving function -@param bit index i of the input payload -@returns the bit index of the output - */ -void nr_init_pbch_interleaver(uint8_t *interleaver); - -NR_gNB_DLSCH_t *new_gNB_dlsch(NR_DL_FRAME_PARMS *frame_parms, - unsigned char Kmimo, - unsigned char Mdlharq, - uint32_t Nsoft, - uint8_t abstraction_flag, - uint16_t N_RB); - -void rx_nr_prach(PHY_VARS_gNB *gNB, - nfapi_nr_prach_pdu_t *prach_pdu, - int frame, - int subframe, - uint16_t *max_preamble, - uint16_t *max_preamble_energy, - uint16_t *max_preamble_delay - ); - -void rx_nr_prach_ru(RU_t *ru, - int prach_fmt, - int numRA, - int prachStartSymbol, - int frame, - int subframe); - -void nr_fill_prach_ru(RU_t *ru, - int SFN, - int Slot, - nfapi_nr_prach_pdu_t *prach_pdu); - -int16_t find_nr_prach(PHY_VARS_gNB *gNB,int frame,int slot, int numRA, find_type_t type); -int16_t find_nr_prach_ru(RU_t *ru,int frame,int slot, find_type_t type); - -void init_prach_list(PHY_VARS_gNB *gNB); -void init_prach_ru_list(RU_t *ru); -void free_nr_ru_prach_entry(RU_t *ru, - int prach_id); - #endif /*__NR_TRANSPORT__H__*/ diff --git a/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h b/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h index c279a5ba44..26fc190662 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h +++ b/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h @@ -31,6 +31,92 @@ */ #include "PHY/defs_nr_common.h" +#include "PHY/defs_gNB.h" +#include "LAYER2/NR_MAC_gNB/mac_proto.h" + +/*! +\fn int nr_generate_pss +\brief Generation of the NR PSS +@param +@returns 0 on success + */ +int nr_generate_pss(int16_t *d_pss, + int32_t *txdataF, + int16_t amp, + uint8_t ssb_start_symbol, + nfapi_nr_config_request_scf_t *config, + NR_DL_FRAME_PARMS *frame_parms); + +/*! +\fn int nr_generate_sss +\brief Generation of the NR SSS +@param +@returns 0 on success + */ +int nr_generate_sss(int16_t *d_sss, + int32_t *txdataF, + int16_t amp, + uint8_t ssb_start_symbol, + nfapi_nr_config_request_scf_t *config, + NR_DL_FRAME_PARMS *frame_parms); + +/*! +\fn int nr_generate_pbch_dmrs +\brief Generation of the DMRS for the PBCH +@param +@returns 0 on success + */ +int nr_generate_pbch_dmrs(uint32_t *gold_pbch_dmrs, + int32_t *txdataF, + int16_t amp, + uint8_t ssb_start_symbol, + nfapi_nr_config_request_scf_t *config, + NR_DL_FRAME_PARMS *frame_parms); + +/*! +\fn int nr_pbch_scrambling +\brief PBCH scrambling function +@param + */ +void nr_pbch_scrambling(NR_gNB_PBCH *pbch, + uint32_t Nid, + uint8_t nushift, + uint16_t M, + uint16_t length, + uint8_t encoded, + uint32_t unscrambling_mask); + +/*! +\fn int nr_generate_pbch +\brief Generation of the PBCH +@param +@returns 0 on success + */ +int nr_generate_pbch(NR_gNB_PBCH *pbch, + nfapi_nr_dl_tti_ssb_pdu *ssb_pdu, + uint8_t *interleaver, + int32_t *txdataF, + int16_t amp, + uint8_t ssb_start_symbol, + uint8_t n_hf, + int sfn, + nfapi_nr_config_request_scf_t *config, + NR_DL_FRAME_PARMS *frame_parms); + +/*! +\fn int nr_generate_pbch +\brief PBCH interleaving function +@param bit index i of the input payload +@returns the bit index of the output + */ +void nr_init_pbch_interleaver(uint8_t *interleaver); + +NR_gNB_DLSCH_t *new_gNB_dlsch(NR_DL_FRAME_PARMS *frame_parms, + unsigned char Kmimo, + unsigned char Mdlharq, + uint32_t Nsoft, + uint8_t abstraction_flag, + uint16_t N_RB); /** \brief This function is the top-level entry point to PUSCH demodulation, after frequency-domain transformation and channel estimation. It performs - RB extraction (signal and channel estimates) @@ -53,7 +139,6 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, unsigned char symbol, unsigned char harq_pid); - /** \brief This function performs RB extraction (signal and channel estimates) (currently signal only until channel estimation and compensation are implemented) @param rxdataF pointer to the received frequency domain signal @param rxdataF_ext pointer to the extracted frequency domain signal @@ -62,9 +147,7 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, @param start_rb The starting RB in the RB allocation (used for Resource Allocation Type 1 in NR) @param nb_rb_pusch The number of RBs allocated (used for Resource Allocation Type 1 in NR) @param frame_parms, Pointer to frame descriptor structure - */ - void nr_ulsch_extract_rbs_single(int32_t **rxdataF, NR_gNB_PUSCH *pusch_vars, unsigned char symbol, @@ -80,7 +163,6 @@ void nr_ulsch_scale_channel(int32_t **ul_ch_estimates_ext, uint16_t nb_rb, pusch_dmrs_type_t pusch_dmrs_type); - /** \brief This function computes the average channel level over all allocated RBs and antennas (TX/RX) in order to compute output shift for compensated signal @param ul_ch_estimates_ext Channel estimates in allocated RBs @param frame_parms Pointer to frame descriptor @@ -95,7 +177,6 @@ void nr_ulsch_channel_level(int **ul_ch_estimates_ext, uint32_t len, unsigned short nb_rb); - /** \brief This function performs channel compensation (matched filtering) on the received RBs for this allocation. In addition, it computes the squared-magnitude of the channel with weightings for 16QAM/64QAM detection as well as dual-stream detection (cross-correlation) @param rxdataF_ext Frequency-domain received signal in RBs to be demodulated @param ul_ch_estimates_ext Frequency-domain channel estimates in RBs to be demodulated @@ -206,16 +287,33 @@ uint32_t nr_get_code_rate_ul(uint8_t Imcs, uint8_t table_idx); uint32_t nr_get_code_rate_dl(uint8_t Imcs, uint8_t table_idx); void nr_fill_prach(PHY_VARS_gNB *gNB, - int SFN, - int Slot, - nfapi_nr_prach_pdu_t *prach_pdu); + int SFN, + int Slot, + nfapi_nr_prach_pdu_t *prach_pdu); void rx_nr_prach(PHY_VARS_gNB *gNB, - nfapi_nr_prach_pdu_t *prach_pdu, - int frame, - int subframe, - uint16_t *max_preamble, - uint16_t *max_preamble_energy, - uint16_t *max_preamble_delay - ); + nfapi_nr_prach_pdu_t *prach_pdu, + int frame, + int subframe, + uint16_t *max_preamble, + uint16_t *max_preamble_energy, + uint16_t *max_preamble_delay); +void rx_nr_prach_ru(RU_t *ru, + int prach_fmt, + int numRA, + int prachStartSymbol, + int frame, + int subframe); + +void nr_fill_prach_ru(RU_t *ru, + int SFN, + int Slot, + nfapi_nr_prach_pdu_t *prach_pdu); + +int16_t find_nr_prach(PHY_VARS_gNB *gNB,int frame,int slot, int numRA, find_type_t type); +int16_t find_nr_prach_ru(RU_t *ru,int frame,int slot, find_type_t type); + +void init_prach_list(PHY_VARS_gNB *gNB); +void init_prach_ru_list(RU_t *ru); +void free_nr_ru_prach_entry(RU_t *ru, int prach_id); diff --git a/openair1/SCHED_NR/nr_prach_procedures.c b/openair1/SCHED_NR/nr_prach_procedures.c index b86701f4e3..4649598f27 100644 --- a/openair1/SCHED_NR/nr_prach_procedures.c +++ b/openair1/SCHED_NR/nr_prach_procedures.c @@ -32,7 +32,7 @@ #include "PHY/defs_gNB.h" #include "PHY/phy_extern.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "nfapi_nr_interface_scf.h" #include "fapi_nr_l1.h" #include "nfapi_pnf.h" diff --git a/openair1/SIMULATION/NR_PHY/dlschsim.c b/openair1/SIMULATION/NR_PHY/dlschsim.c index fedf9394da..25813191be 100644 --- a/openair1/SIMULATION/NR_PHY/dlschsim.c +++ b/openair1/SIMULATION/NR_PHY/dlschsim.c @@ -40,7 +40,7 @@ #include "PHY/NR_REFSIG/nr_mod_table.h" #include "PHY/NR_REFSIG/refsig_defs_ue.h" #include "PHY/NR_TRANSPORT/nr_dlsch.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" #include "SCHED_NR/sched_nr.h" #include "openair1/SIMULATION/TOOLS/sim.h" diff --git a/openair1/SIMULATION/NR_PHY/dlsim.c b/openair1/SIMULATION/NR_PHY/dlsim.c index 60268a6ad1..195ca19fbd 100644 --- a/openair1/SIMULATION/NR_PHY/dlsim.c +++ b/openair1/SIMULATION/NR_PHY/dlsim.c @@ -41,7 +41,7 @@ #include "PHY/MODULATION/modulation_UE.h" #include "PHY/NR_REFSIG/nr_mod_table.h" #include "PHY/NR_REFSIG/refsig_defs_ue.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" #include "SCHED_NR/fapi_nr_l1.h" #include "SCHED_NR/sched_nr.h" diff --git a/openair1/SIMULATION/NR_PHY/pbchsim.c b/openair1/SIMULATION/NR_PHY/pbchsim.c index 99ca466fee..1eb058d15b 100644 --- a/openair1/SIMULATION/NR_PHY/pbchsim.c +++ b/openair1/SIMULATION/NR_PHY/pbchsim.c @@ -37,7 +37,7 @@ #include "PHY/MODULATION/modulation_eNB.h" #include "PHY/MODULATION/modulation_UE.h" #include "PHY/INIT/phy_init.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" #include "PHY/NR_UE_ESTIMATION/nr_estimation.h" #include "PHY/phy_vars.h" diff --git a/openair1/SIMULATION/NR_PHY/prachsim.c b/openair1/SIMULATION/NR_PHY/prachsim.c index aed7eb4505..a6904ed25b 100644 --- a/openair1/SIMULATION/NR_PHY/prachsim.c +++ b/openair1/SIMULATION/NR_PHY/prachsim.c @@ -41,7 +41,7 @@ #include "PHY/MODULATION/modulation_eNB.h" #include "PHY/MODULATION/modulation_UE.h" #include "PHY/INIT/phy_init.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "PHY/NR_TRANSPORT/nr_transport_proto_common.h" #include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" #include "nr_unitary_defs.h" diff --git a/openair1/SIMULATION/NR_PHY/pucchsim.c b/openair1/SIMULATION/NR_PHY/pucchsim.c index 445c45693e..0f6c432ebc 100644 --- a/openair1/SIMULATION/NR_PHY/pucchsim.c +++ b/openair1/SIMULATION/NR_PHY/pucchsim.c @@ -37,7 +37,7 @@ #include "PHY/MODULATION/modulation_eNB.h" #include "PHY/MODULATION/modulation_UE.h" #include "PHY/INIT/phy_init.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" #include "PHY/NR_UE_TRANSPORT/pucch_nr.h" #include "SCHED_NR/sched_nr.h" diff --git a/openair1/SIMULATION/NR_PHY/ulschsim.c b/openair1/SIMULATION/NR_PHY/ulschsim.c index d0710f6734..fd36d9cda3 100644 --- a/openair1/SIMULATION/NR_PHY/ulschsim.c +++ b/openair1/SIMULATION/NR_PHY/ulschsim.c @@ -37,7 +37,7 @@ #include "PHY/NR_REFSIG/nr_mod_table.h" #include "PHY/MODULATION/modulation_eNB.h" #include "PHY/MODULATION/modulation_UE.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "PHY/NR_TRANSPORT/nr_dlsch.h" #include "PHY/NR_TRANSPORT/nr_ulsch.h" #include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" From c0029473dc9c10aa911847bcf7ebeeed1a54b20e Mon Sep 17 00:00:00 2001 From: cig Date: Thu, 9 Apr 2020 17:15:43 +0200 Subject: [PATCH 167/553] Fixed some warnings --- openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c | 1 + openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c index 6aa9ab9d4b..163b719d9d 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c @@ -42,6 +42,7 @@ #include "SIMULATION/TOOLS/sim.h" #include "executables/nr-uesoftmodem.h" #include "PHY/CODING/nrLDPC_extern.h" +#include "LAYER2/NR_MAC_gNB/mac_proto.h" //#define DEBUG_DLSCH_DECODING //#define ENABLE_PHY_PAYLOAD_DEBUG 1 diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c index 43545bada2..5c4df8ce40 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c @@ -30,6 +30,8 @@ */ #include "PHY/defs_nr_UE.h" #include "PHY/phy_extern_nr_ue.h" +#include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "nr_transport_proto_ue.h" //#include "SCHED/defs.h" //#include "PHY/defs.h" From 8dd88bcb0efe78d5544fab1af375f89a5e51475b Mon Sep 17 00:00:00 2001 From: cig Date: Thu, 9 Apr 2020 18:34:39 +0200 Subject: [PATCH 168/553] Deleted duplicated transport common proto header file --- openair1/PHY/INIT/nr_init.c | 2 +- openair1/PHY/NR_TRANSPORT/nr_prach.c | 2 +- openair1/PHY/NR_TRANSPORT/nr_prach_common.c | 2 +- openair1/PHY/NR_TRANSPORT/nr_tbs_tools.c | 2 +- .../NR_TRANSPORT/nr_transport_common_proto.h | 31 +- .../PHY/NR_TRANSPORT/nr_transport_proto.h | 10 - .../NR_TRANSPORT/nr_transport_proto_common.h | 1763 ----------------- openair1/PHY/NR_UE_TRANSPORT/nr_prach.c | 2 +- .../NR_UE_TRANSPORT/nr_transport_proto_ue.h | 21 +- openair1/SIMULATION/NR_PHY/prachsim.c | 2 +- 10 files changed, 31 insertions(+), 1806 deletions(-) delete mode 100644 openair1/PHY/NR_TRANSPORT/nr_transport_proto_common.h diff --git a/openair1/PHY/INIT/nr_init.c b/openair1/PHY/INIT/nr_init.c index 74f3aa2d04..2d9fdbea81 100644 --- a/openair1/PHY/INIT/nr_init.c +++ b/openair1/PHY/INIT/nr_init.c @@ -26,7 +26,7 @@ #include "PHY/INIT/phy_init.h" #include "PHY/CODING/nrPolar_tools/nr_polar_pbch_defs.h" #include "PHY/NR_TRANSPORT/nr_transport_proto.h" -#include "PHY/NR_TRANSPORT/nr_transport_proto_common.h" +#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" /*#include "RadioResourceConfigCommonSIB.h" #include "RadioResourceConfigDedicated.h" #include "TDD-Config.h" diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index c856d29f3c..0aa1db57ec 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -32,7 +32,7 @@ #include "PHY/defs_gNB.h" #include "PHY/NR_TRANSPORT/nr_transport_proto.h" -#include "PHY/NR_TRANSPORT/nr_transport_proto_common.h" +#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" extern uint16_t prach_root_sequence_map_0_3[838]; extern uint16_t prach_root_sequence_map_abc[138]; diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c index 8373e775bd..251d1cbfd8 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c @@ -34,7 +34,7 @@ #include "PHY/impl_defs_nr.h" #include "PHY/defs_nr_UE.h" #include "PHY/NR_TRANSPORT/nr_prach.h" -#include "PHY/NR_TRANSPORT/nr_transport_proto_common.h" +#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" #include "common/utils/LOG/log.h" #include "common/utils/LOG/vcd_signal_dumper.h" #include "openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h" diff --git a/openair1/PHY/NR_TRANSPORT/nr_tbs_tools.c b/openair1/PHY/NR_TRANSPORT/nr_tbs_tools.c index ea8e39488e..e535286084 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_tbs_tools.c +++ b/openair1/PHY/NR_TRANSPORT/nr_tbs_tools.c @@ -32,7 +32,7 @@ #include "nr_transport_common_proto.h" #include "PHY/CODING/coding_defs.h" - +#include "PHY/defs_nr_common.h" uint32_t nr_get_G(uint16_t nb_rb, uint16_t nb_symb_sch,uint8_t nb_re_dmrs,uint16_t length_dmrs, uint8_t Qm, uint8_t Nl) { uint32_t G; diff --git a/openair1/PHY/NR_TRANSPORT/nr_transport_common_proto.h b/openair1/PHY/NR_TRANSPORT/nr_transport_common_proto.h index 762346048f..82a0cd5d03 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_transport_common_proto.h +++ b/openair1/PHY/NR_TRANSPORT/nr_transport_common_proto.h @@ -31,22 +31,35 @@ * \warning */ +/** @addtogroup _PHY_TRANSPORT_ + * @{ + */ + #ifndef __NR_TRANSPORT_COMMON_PROTO__H__ #define __NR_TRANSPORT_COMMON_PROTO__H__ -#include "PHY/defs_nr_common.h" - - -#define NR_PUSCH_x 2 // UCI placeholder bit TS 38.212 V15.4.0 subclause 5.3.3.1 -#define NR_PUSCH_y 3 // UCI placeholder bit - - - - +#include /** \brief Computes available bits G. */ uint32_t nr_get_G(uint16_t nb_rb, uint16_t nb_symb_sch, uint8_t nb_re_dmrs, uint16_t length_dmrs, uint8_t Qm, uint8_t Nl); uint32_t nr_get_E(uint32_t G, uint8_t C, uint8_t Qm, uint8_t Nl, uint8_t r); +uint8_t nr_get_Qm_ul(uint8_t Imcs, uint8_t table_idx); + +uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx); + +uint32_t nr_get_code_rate_ul(uint8_t Imcs, uint8_t table_idx); + +uint32_t nr_get_code_rate_dl(uint8_t Imcs, uint8_t table_idx); + +void compute_nr_prach_seq(uint8_t short_sequence, + uint8_t num_sequences, + uint8_t rootSequenceIndex, + uint32_t X_u[64][839]); + +void init_nr_prach_tables(int N_ZC); + +/**@}*/ + #endif diff --git a/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h b/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h index 26fc190662..24b6303b9c 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h +++ b/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h @@ -276,16 +276,6 @@ void nr_fill_ulsch(PHY_VARS_gNB *gNB, int slot, nfapi_nr_pusch_pdu_t *ulsch_pdu); -uint32_t nr_get_code_rate_dl(uint8_t Imcs, uint8_t table_idx); - -uint8_t nr_get_Qm_ul(uint8_t Imcs, uint8_t table_idx); - -uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx); - -uint32_t nr_get_code_rate_ul(uint8_t Imcs, uint8_t table_idx); - -uint32_t nr_get_code_rate_dl(uint8_t Imcs, uint8_t table_idx); - void nr_fill_prach(PHY_VARS_gNB *gNB, int SFN, int Slot, diff --git a/openair1/PHY/NR_TRANSPORT/nr_transport_proto_common.h b/openair1/PHY/NR_TRANSPORT/nr_transport_proto_common.h deleted file mode 100644 index 78dd266eea..0000000000 --- a/openair1/PHY/NR_TRANSPORT/nr_transport_proto_common.h +++ /dev/null @@ -1,1763 +0,0 @@ -/* - * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. - * The OpenAirInterface Software Alliance licenses this file to You under - * the OAI Public License, Version 1.1 (the "License"); you may not use this file - * except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.openairinterface.org/?page_id=698 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - *------------------------------------------------------------------------------- - * For more information about the OpenAirInterface (OAI) Software Alliance: - * contact@openairinterface.org - */ - -/*! \file PHY/NR_UE_TRANSPORT/transport_proto_ue.h - * \brief Function prototypes for PHY physical/transport channel processing and generation V8.6 2009-03 - * \author R. Knopp, F. Kaltenberger - * \date 2011 - * \version 0.1 - * \company Eurecom - * \email: knopp@eurecom.fr - * \note - * \warning - */ -#ifndef __NR_TRANSPORT_PROTO_UE__H__ -#define __NR_TRANSPORT_PROTO_UE__H__ -#include "PHY/defs_nr_UE.h" -#include "SCHED_NR_UE/defs.h" -//#include "PHY/LTE_TRANSPORT/transport_common_proto.h" -#include -#include "nfapi_interface.h" - -// Functions below implement 36-211 and 36-212 - -/** @addtogroup _PHY_TRANSPORT_ - * @{ - */ - -/** \fn free_ue_dlsch(NR_UE_DLSCH_t *dlsch) - \brief This function frees memory allocated for a particular DLSCH at UE - @param dlsch Pointer to DLSCH to be removed -*/ -void free_nr_ue_dlsch(NR_UE_DLSCH_t *dlsch); - -/** \fn new_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint8_t abstraction_flag) - \brief This function allocates structures for a particular DLSCH at UE - @returns Pointer to DLSCH to be removed - @param Kmimo Kmimo factor from 36-212/36-213 - @param Mdlharq Maximum number of HARQ rounds (36-212/36-213) - @param Nsoft Soft-LLR buffer size from UE-Category - @params N_RB_DL total number of resource blocks (determine the operating BW) - @param abstraction_flag Flag to indicate abstracted interface -*/ -NR_UE_DLSCH_t *new_nr_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint8_t max_turbo_iterations,uint8_t N_RB_DL, uint8_t abstraction_flag); - - -void free_nr_ue_ulsch(NR_UE_ULSCH_t *ulsch); - - -NR_UE_ULSCH_t *new_nr_ue_ulsch(unsigned char N_RB_UL, int number_of_harq_pids, uint8_t abstraction_flag); - -void fill_UE_dlsch_MCH(PHY_VARS_NR_UE *ue,int mcs,int ndi,int rvidx,int eNB_id); - -int rx_pmch(PHY_VARS_NR_UE *phy_vars_ue, - unsigned char eNB_id, - uint8_t subframe, - unsigned char symbol); - -/** \brief Dump OCTAVE/MATLAB files for PMCH debugging - @param phy_vars_ue Pointer to UE variables - @param eNB_id index of eNB in ue variables - @param coded_bits_per_codeword G from 36.211 - @param subframe Index of subframe - @returns 0 on success -*/ -void dump_mch(PHY_VARS_NR_UE *phy_vars_ue,uint8_t eNB_id,uint16_t coded_bits_per_codeword,int subframe); - - - -/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream QPSK/QPSK reception. - @param stream0_in Input from channel compensated (MR combined) stream 0 - @param stream1_in Input from channel compensated (MR combined) stream 1 - @param stream0_out Output from LLR unit for stream0 - @param rho01 Cross-correlation between channels (MR combined) - @param length in complex channel outputs*/ -void qpsk_qpsk(int16_t *stream0_in, - int16_t *stream1_in, - int16_t *stream0_out, - int16_t *rho01, - int32_t length); - -/** \brief This function perform LLR computation for dual-stream (QPSK/QPSK) transmission. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param rxdataF_comp_i Compensated channel output for interference - @param rho_i Correlation between channel of signal and inteference - @param dlsch_llr llr output - @param symbol OFDM symbol index in sub-frame - @param first_symbol_flag flag to indicate this is the first symbol of the dlsch - @param nb_rb number of RBs for this allocation - @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS - @param llr128p pointer to pointer to symbol in dlsch_llr*/ -int32_t nr_dlsch_qpsk_qpsk_llr(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int32_t **rxdataF_comp_i, - int32_t **rho_i, - int16_t *dlsch_llr, - uint8_t symbol, - uint32_t len, - uint8_t first_symbol_flag, - uint16_t nb_rb, - uint16_t pbch_pss_sss_adj, - int16_t **llr128p); - -/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream QPSK/16QAM reception. - @param stream0_in Input from channel compensated (MR combined) stream 0 - @param stream1_in Input from channel compensated (MR combined) stream 1 - @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 - @param stream0_out Output from LLR unit for stream0 - @param rho01 Cross-correlation between channels (MR combined) - @param length in complex channel outputs*/ -void qpsk_qam16(int16_t *stream0_in, - int16_t *stream1_in, - short *ch_mag_i, - int16_t *stream0_out, - int16_t *rho01, - int32_t length); - -/** \brief This function perform LLR computation for dual-stream (QPSK/16QAM) transmission. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param rxdataF_comp_i Compensated channel output for interference - @param rho_i Correlation between channel of signal and inteference - @param dlsch_llr llr output - @param symbol OFDM symbol index in sub-frame - @param first_symbol_flag flag to indicate this is the first symbol of the dlsch - @param nb_rb number of RBs for this allocation - @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS - @param llr128p pointer to pointer to symbol in dlsch_llr*/ -int32_t nr_dlsch_qpsk_16qam_llr(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int32_t **rxdataF_comp_i, - int **dl_ch_mag_i, //|h_1|^2*(2/sqrt{10}) - int32_t **rho_i, - int16_t *dlsch_llr, - uint8_t symbol, - uint8_t first_symbol_flag, - uint16_t nb_rb, - uint16_t pbch_pss_sss_adj, - int16_t **llr128p); - - -/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream QPSK/64QAM reception. - @param stream0_in Input from channel compensated (MR combined) stream 0 - @param stream1_in Input from channel compensated (MR combined) stream 1 - @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 - @param stream0_out Output from LLR unit for stream0 - @param rho01 Cross-correlation between channels (MR combined) - @param length in complex channel outputs*/ -void qpsk_qam64(int16_t *stream0_in, - int16_t *stream1_in, - short *ch_mag_i, - int16_t *stream0_out, - int16_t *rho01, - int32_t length); - -/** \brief This function perform LLR computation for dual-stream (QPSK/64QAM) transmission. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param rxdataF_comp_i Compensated channel output for interference - @param rho_i Correlation between channel of signal and inteference - @param dlsch_llr llr output - @param symbol OFDM symbol index in sub-frame - @param first_symbol_flag flag to indicate this is the first symbol of the dlsch - @param nb_rb number of RBs for this allocation - @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS - @param llr128p pointer to pointer to symbol in dlsch_llr*/ -int32_t nr_dlsch_qpsk_64qam_llr(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int32_t **rxdataF_comp_i, - int **dl_ch_mag_i, //|h_1|^2*(2/sqrt{10}) - int32_t **rho_i, - int16_t *dlsch_llr, - uint8_t symbol, - uint8_t first_symbol_flag, - uint16_t nb_rb, - uint16_t pbch_pss_sss_adj, - int16_t **llr128p); - - -/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 16QAM/QPSK reception. - @param stream0_in Input from channel compensated (MR combined) stream 0 - @param stream1_in Input from channel compensated (MR combined) stream 1 - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param stream0_out Output from LLR unit for stream0 - @param rho01 Cross-correlation between channels (MR combined) - @param length in complex channel outputs*/ -void qam16_qpsk(short *stream0_in, - short *stream1_in, - short *ch_mag, - short *stream0_out, - short *rho01, - int length); -/** \brief This function perform LLR computation for dual-stream (16QAM/QPSK) transmission. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param rxdataF_comp_i Compensated channel output for interference - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param rho_i Correlation between channel of signal and inteference - @param dlsch_llr llr output - @param symbol OFDM symbol index in sub-frame - @param first_symbol_flag flag to indicate this is the first symbol of the dlsch - @param nb_rb number of RBs for this allocation - @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS - @param llr16p pointer to pointer to symbol in dlsch_llr*/ -int nr_dlsch_16qam_qpsk_llr(NR_DL_FRAME_PARMS *frame_parms, - int **rxdataF_comp, - int **rxdataF_comp_i, - int **dl_ch_mag, //|h_0|^2*(2/sqrt{10}) - int **rho_i, - short *dlsch_llr, - unsigned char symbol, - unsigned char first_symbol_flag, - unsigned short nb_rb, - uint16_t pbch_pss_sss_adjust, - short **llr16p); - -/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 16QAM/16QAM reception. - @param stream0_in Input from channel compensated (MR combined) stream 0 - @param stream1_in Input from channel compensated (MR combined) stream 1 - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 - @param stream0_out Output from LLR unit for stream0 - @param rho01 Cross-correlation between channels (MR combined) - @param length in complex channel outputs*/ -void qam16_qam16(short *stream0_in, - short *stream1_in, - short *ch_mag, - short *ch_mag_i, - short *stream0_out, - short *rho01, - int length); - -/** \brief This function perform LLR computation for dual-stream (16QAM/16QAM) transmission. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param rxdataF_comp_i Compensated channel output for interference - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 - @param rho_i Correlation between channel of signal and inteference - @param dlsch_llr llr output - @param symbol OFDM symbol index in sub-frame - @param first_symbol_flag flag to indicate this is the first symbol of the dlsch - @param nb_rb number of RBs for this allocation - @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS - @param llr16p pointer to pointer to symbol in dlsch_llr*/ -int nr_dlsch_16qam_16qam_llr(NR_DL_FRAME_PARMS *frame_parms, - int **rxdataF_comp, - int **rxdataF_comp_i, - int **dl_ch_mag, //|h_0|^2*(2/sqrt{10}) - int **dl_ch_mag_i, //|h_1|^2*(2/sqrt{10}) - int **rho_i, - short *dlsch_llr, - unsigned char symbol, - uint32_t len, - unsigned char first_symbol_flag, - unsigned short nb_rb, - uint16_t pbch_pss_sss_adjust, - short **llr16p); - -/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 16QAM/64QAM reception. - @param stream0_in Input from channel compensated (MR combined) stream 0 - @param stream1_in Input from channel compensated (MR combined) stream 1 - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 - @param stream0_out Output from LLR unit for stream0 - @param rho01 Cross-correlation between channels (MR combined) - @param length in complex channel outputs*/ -void qam16_qam64(short *stream0_in, - short *stream1_in, - short *ch_mag, - short *ch_mag_i, - short *stream0_out, - short *rho01, - int length); - -/** \brief This function perform LLR computation for dual-stream (16QAM/64QAM) transmission. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param rxdataF_comp_i Compensated channel output for interference - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 - @param rho_i Correlation between channel of signal and inteference - @param dlsch_llr llr output - @param symbol OFDM symbol index in sub-frame - @param first_symbol_flag flag to indicate this is the first symbol of the dlsch - @param nb_rb number of RBs for this allocation - @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS - @param llr16p pointer to pointer to symbol in dlsch_llr*/ -int nr_dlsch_16qam_64qam_llr(NR_DL_FRAME_PARMS *frame_parms, - int **rxdataF_comp, - int **rxdataF_comp_i, - int **dl_ch_mag, //|h_0|^2*(2/sqrt{10}) - int **dl_ch_mag_i, //|h_1|^2*(2/sqrt{10}) - int **rho_i, - short *dlsch_llr, - unsigned char symbol, - unsigned char first_symbol_flag, - unsigned short nb_rb, - uint16_t pbch_pss_sss_adjust, - short **llr16p); - -/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 64QAM/64QAM reception. - @param stream0_in Input from channel compensated (MR combined) stream 0 - @param stream1_in Input from channel compensated (MR combined) stream 1 - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param stream0_out Output from LLR unit for stream0 - @param rho01 Cross-correlation between channels (MR combined) - @param length in complex channel outputs*/ -void qam64_qpsk(short *stream0_in, - short *stream1_in, - short *ch_mag, - short *stream0_out, - short *rho01, - int length); - -/** \brief This function perform LLR computation for dual-stream (64QAM/64QAM) transmission. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param rxdataF_comp_i Compensated channel output for interference - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param rho_i Correlation between channel of signal and inteference - @param dlsch_llr llr output - @param symbol OFDM symbol index in sub-frame - @param first_symbol_flag flag to indicate this is the first symbol of the dlsch - @param nb_rb number of RBs for this allocation - @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS - @param llr16p pointer to pointer to symbol in dlsch_llr*/ -int nr_dlsch_64qam_qpsk_llr(NR_DL_FRAME_PARMS *frame_parms, - int **rxdataF_comp, - int **rxdataF_comp_i, - int **dl_ch_mag, - int **rho_i, - short *dlsch_llr, - unsigned char symbol, - unsigned char first_symbol_flag, - unsigned short nb_rb, - uint16_t pbch_pss_sss_adjust, - short **llr16p); - -/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 64QAM/16QAM reception. - @param stream0_in Input from channel compensated (MR combined) stream 0 - @param stream1_in Input from channel compensated (MR combined) stream 1 - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 - @param stream0_out Output from LLR unit for stream0 - @param rho01 Cross-correlation between channels (MR combined) - @param length in complex channel outputs*/ -void qam64_qam16(short *stream0_in, - short *stream1_in, - short *ch_mag, - short *ch_mag_i, - short *stream0_out, - short *rho01, - int length); - -/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 64QAM/16QAM reception. - @param stream0_in Input from channel compensated (MR combined) stream 0 - @param stream1_in Input from channel compensated (MR combined) stream 1 - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 - @param stream0_out Output from LLR unit for stream0 - @param rho01 Cross-correlation between channels (MR combined) - @param length in complex channel outputs*/ -void qam64_qam16_avx2(short *stream0_in, - short *stream1_in, - short *ch_mag, - short *ch_mag_i, - short *stream0_out, - short *rho01, - int length); - -/** \brief This function perform LLR computation for dual-stream (64QAM/16QAM) transmission. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param rxdataF_comp_i Compensated channel output for interference - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 - @param rho_i Correlation between channel of signal and inteference - @param dlsch_llr llr output - @param symbol OFDM symbol index in sub-frame - @param first_symbol_flag flag to indicate this is the first symbol of the dlsch - @param nb_rb number of RBs for this allocation - @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS - @param llr16p pointer to pointer to symbol in dlsch_llr*/ -int nr_dlsch_64qam_16qam_llr(NR_DL_FRAME_PARMS *frame_parms, - int **rxdataF_comp, - int **rxdataF_comp_i, - int **dl_ch_mag, - int **dl_ch_mag_i, - int **rho_i, - short *dlsch_llr, - unsigned char symbol, - unsigned char first_symbol_flag, - unsigned short nb_rb, - uint16_t pbch_pss_sss_adjust, - short **llr16p); - -/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 64QAM/64QAM reception. - @param stream0_in Input from channel compensated (MR combined) stream 0 - @param stream1_in Input from channel compensated (MR combined) stream 1 - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 - @param stream0_out Output from LLR unit for stream0 - @param rho01 Cross-correlation between channels (MR combined) - @param length in complex channel outputs*/ -void qam64_qam64(short *stream0_in, - short *stream1_in, - short *ch_mag, - short *ch_mag_i, - short *stream0_out, - short *rho01, - int length); - -/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 64QAM/64QAM reception. - @param stream0_in Input from channel compensated (MR combined) stream 0 - @param stream1_in Input from channel compensated (MR combined) stream 1 - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 - @param stream0_out Output from LLR unit for stream0 - @param rho01 Cross-correlation between channels (MR combined) - @param length in complex channel outputs*/ -void qam64_qam64_avx2(int32_t *stream0_in, - int32_t *stream1_in, - int32_t *ch_mag, - int32_t *ch_mag_i, - int16_t *stream0_out, - int32_t *rho01, - int length); - -/** \brief This function perform LLR computation for dual-stream (64QAM/64QAM) transmission. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param rxdataF_comp_i Compensated channel output for interference - @param ch_mag Input from scaled channel magnitude square of h0'*g0 - @param ch_mag_i Input from scaled channel magnitude square of h0'*g1 - @param rho_i Correlation between channel of signal and inteference - @param dlsch_llr llr output - @param symbol OFDM symbol index in sub-frame - @param first_symbol_flag flag to indicate this is the first symbol of the dlsch - @param nb_rb number of RBs for this allocation - @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS - @param llr16p pointer to pointer to symbol in dlsch_llr*/ -int nr_dlsch_64qam_64qam_llr(NR_DL_FRAME_PARMS *frame_parms, - int **rxdataF_comp, - int **rxdataF_comp_i, - int **dl_ch_mag, - int **dl_ch_mag_i, - int **rho_i, - short *dlsch_llr, - unsigned char symbol, - uint32_t len, - unsigned char first_symbol_flag, - unsigned short nb_rb, - uint16_t pbch_pss_sss_adjust, - //short **llr16p, - uint32_t llr_offset); - - -/** \brief This function generates log-likelihood ratios (decoder input) for single-stream QPSK received waveforms. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param dlsch_llr llr output - @param symbol OFDM symbol index in sub-frame - @param first_symbol_flag - @param nb_rb number of RBs for this allocation - @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS - @param llr128p pointer to pointer to symbol in dlsch_llr - @param beamforming_mode beamforming mode -*/ -int32_t nr_dlsch_qpsk_llr(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int16_t *dlsch_llr, - uint8_t symbol, - uint32_t len, - uint8_t first_symbol_flag, - uint16_t nb_rb, - uint8_t beamforming_mode); - -/** - \brief This function generates log-likelihood ratios (decoder input) for single-stream 16QAM received waveforms - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param dlsch_llr llr output - @param dl_ch_mag Squared-magnitude of channel in each resource element position corresponding to allocation and weighted for mid-point in 16QAM constellation - @param symbol OFDM symbol index in sub-frame - @param first_symbol_flag - @param nb_rb number of RBs for this allocation - @param pbch_pss_sss_adjust Adjustment factor in RE for PBCH/PSS/SSS allocations - @param llr128p pointer to pointer to symbol in dlsch_llr - @param beamforming_mode beamforming mode -*/ - -int32_t nr_dlsch_qpsk_llr_SIC(NR_DL_FRAME_PARMS *frame_parms, - int **rxdataF_comp, - int32_t **sic_buffer, - int **rho_i, - short *dlsch_llr, - uint8_t num_pdcch_symbols, - uint16_t nb_rb, - uint8_t subframe, - uint16_t mod_order_0, - uint32_t rb_alloc); - -void nr_dlsch_16qam_llr(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int16_t *dlsch_llr, - int32_t **dl_ch_mag, - uint8_t symbol, - uint32_t len, - uint8_t first_symbol_flag, - uint16_t nb_rb, - int16_t **llr32p, - uint8_t beamforming_mode); -/** - \brief This function generates log-likelihood ratios (decoder input) for single-stream 16QAM received waveforms - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param dlsch_llr llr output - @param dl_ch_mag Squared-magnitude of channel in each resource element position corresponding to allocation, weighted by first mid-point of 64-QAM constellation - @param dl_ch_magb Squared-magnitude of channel in each resource element position corresponding to allocation, weighted by second mid-point of 64-QAM constellation - @param symbol OFDM symbol index in sub-frame - @param first_symbol_flag - @param nb_rb number of RBs for this allocation - @param pbch_pss_sss_adjust PBCH/PSS/SSS RE adjustment (in REs) - @param beamforming_mode beamforming mode -*/ -void nr_dlsch_16qam_llr_SIC (NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int32_t **sic_buffer, //Q15 - int32_t **rho_i, - int16_t *dlsch_llr, - uint8_t num_pdcch_symbols, - int32_t **dl_ch_mag, - uint16_t nb_rb, - uint8_t subframe, - uint16_t mod_order_0, - uint32_t rb_alloc); - -void dlsch_64qam_llr_SIC(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int32_t **sic_buffer, //Q15 - int32_t **rho_i, - int16_t *dlsch_llr, - uint8_t num_pdcch_symbols, - int32_t **dl_ch_mag, - int32_t **dl_ch_magb, - uint16_t nb_rb, - uint8_t subframe, - uint16_t mod_order_0, - uint32_t rb_alloc); - -void nr_dlsch_64qam_llr(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int16_t *dlsch_llr, - int32_t **dl_ch_mag, - int32_t **dl_ch_magb, - uint8_t symbol, - uint32_t len, - uint8_t first_symbol_flag, - uint16_t nb_rb, - uint32_t llr_offset, - uint8_t beamforming_mode); - - -/** \fn dlsch_siso(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int32_t **rxdataF_comp_i, - uint8_t l, - uint16_t nb_rb) - \brief This function does the first stage of llr computation for SISO, by just extracting the pilots, PBCH and primary/secondary synchronization sequences. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param rxdataF_comp_i Compensated channel output for interference - @param l symbol in sub-frame - @param nb_rb Number of RBs in this allocation -*/ - -void dlsch_siso(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int32_t **rxdataF_comp_i, - uint8_t l, - uint16_t nb_rb); - -/** \fn dlsch_alamouti(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int32_t **dl_ch_mag, - int32_t **dl_ch_magb, - uint8_t symbol, - uint16_t nb_rb) - \brief This function does Alamouti combining on RX and prepares LLR inputs by skipping pilots, PBCH and primary/secondary synchronization signals. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param dl_ch_mag First squared-magnitude of channel (16QAM and 64QAM) for LLR computation. Alamouti combining should be performed on this as well. Result is stored in first antenna position - @param dl_ch_magb Second squared-magnitude of channel (64QAM only) for LLR computation. Alamouti combining should be performed on this as well. Result is stored in first antenna position - @param symbol Symbol in sub-frame - @param nb_rb Number of RBs in this allocation -*/ -void dlsch_alamouti(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int32_t **dl_ch_mag, - int32_t **dl_ch_magb, - uint8_t symbol, - uint16_t nb_rb); - -/** \fn dlsch_antcyc(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int32_t **dl_ch_mag, - int32_t **dl_ch_magb, - uint8_t symbol, - uint16_t nb_rb) - \brief This function does antenna selection (based on antenna cycling pattern) on RX and prepares LLR inputs by skipping pilots, PBCH and primary/secondary synchronization signals. Note that this is not LTE, it is just included for comparison purposes. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param dl_ch_mag First squared-magnitude of channel (16QAM and 64QAM) for LLR computation. Alamouti combining should be performed on this as well. Result is stored in first antenna position - @param dl_ch_magb Second squared-magnitude of channel (64QAM only) for LLR computation. Alamouti combining should be performed on this as well. Result is stored in first antenna position - @param symbol Symbol in sub-frame - @param nb_rb Number of RBs in this allocation -*/ -void dlsch_antcyc(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int32_t **dl_ch_mag, - int32_t **dl_ch_magb, - uint8_t symbol, - uint16_t nb_rb); - -/** \fn dlsch_detection_mrc(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int32_t **rxdataF_comp_i, - int32_t **rho, - int32_t **rho_i, - int32_t **dl_ch_mag, - int32_t **dl_ch_magb, - uint8_t symbol, - uint16_t nb_rb, - uint8_t dual_stream_UE) - - \brief This function does maximal-ratio combining for dual-antenna receivers. - @param frame_parms Frame descriptor structure - @param rxdataF_comp Compensated channel output - @param rxdataF_comp_i Compensated channel output for interference - @param rho Cross correlation between spatial channels - @param rho_i Cross correlation between signal and inteference channels - @param dl_ch_mag First squared-magnitude of channel (16QAM and 64QAM) for LLR computation. Alamouti combining should be performed on this as well. Result is stored in first antenna position - @param dl_ch_magb Second squared-magnitude of channel (64QAM only) for LLR computation. Alamouti combining should be performed on this as well. Result is stored in first antenna position - @param symbol Symbol in sub-frame - @param nb_rb Number of RBs in this allocation - @param dual_stream_UE Flag to indicate dual-stream detection -*/ -void dlsch_detection_mrc(NR_DL_FRAME_PARMS *frame_parms, - int32_t **rxdataF_comp, - int32_t **rxdataF_comp_i, - int32_t **rho, - int32_t **rho_i, - int32_t **dl_ch_mag, - int32_t **dl_ch_magb, - int32_t **dl_ch_mag_i, - int32_t **dl_ch_magb_i, - uint8_t symbol, - uint16_t nb_rb, - uint8_t dual_stream_UE); - -void dlsch_detection_mrc_TM34(NR_DL_FRAME_PARMS *frame_parms, - NR_UE_PDSCH *lte_ue_pdsch_vars, - int harq_pid, - int round, - unsigned char symbol, - unsigned short nb_rb, - unsigned char dual_stream_UE); - -/** \fn dlsch_extract_rbs_single(int32_t **rxdataF, - int32_t **dl_ch_estimates, - int32_t **rxdataF_ext, - int32_t **dl_ch_estimates_ext, - uint16_t pmi, - uint8_t *pmi_ext, - uint32_t *rb_alloc, - uint8_t symbol, - uint8_t subframe, - NR_DL_FRAME_PARMS *frame_parms) - \brief This function extracts the received resource blocks, both channel estimates and data symbols, - for the current allocation and for single antenna eNB transmission. - @param rxdataF Raw FFT output of received signal - @param dl_ch_estimates Channel estimates of current slot - @param rxdataF_ext FFT output for RBs in this allocation - @param dl_ch_estimates_ext Channel estimates for RBs in this allocation - @param pmi subband Precoding matrix indicator - @param pmi_ext Extracted PMI for chosen RBs - @param rb_alloc RB allocation vector - @param symbol Symbol to extract - @param subframe Subframe number - @param vrb_type Flag to indicate distributed VRB type - @param high_speed_flag - @param frame_parms Pointer to frame descriptor -*/ -/*uint16_t nr_dlsch_extract_rbs_single(int32_t **rxdataF, - int32_t **dl_ch_estimates, - int32_t **rxdataF_ext, - int32_t **dl_ch_estimates_ext, - uint16_t pmi, - uint8_t *pmi_ext, - uint32_t *rb_alloc, - uint8_t symbol, - uint8_t subframe, - uint32_t high_speed_flag, - NR_DL_FRAME_PARMS *frame_parms);*/ - -unsigned short nr_dlsch_extract_rbs_single(int **rxdataF, - int **dl_ch_estimates, - int **rxdataF_ext, - int **dl_ch_estimates_ext, - unsigned short pmi, - unsigned char *pmi_ext, - unsigned char symbol, - uint8_t pilots, - unsigned short start_rb, - unsigned short nb_pdsch_rb, - unsigned char nr_tti_rx, - uint32_t high_speed_flag, - NR_DL_FRAME_PARMS *frame_parms); - -/** \fn dlsch_extract_rbs_dual(int32_t **rxdataF, - int32_t **dl_ch_estimates, - int32_t **rxdataF_ext, - int32_t **dl_ch_estimates_ext, - uint16_t pmi, - uint8_t *pmi_ext, - uint32_t *rb_alloc, - uint8_t symbol, - NR_DL_FRAME_PARMS *frame_parms) - \brief This function extracts the received resource blocks, both channel estimates and data symbols, - for the current allocation and for dual antenna eNB transmission. - @param rxdataF Raw FFT output of received signal - @param dl_ch_estimates Channel estimates of current slot - @param rxdataF_ext FFT output for RBs in this allocation - @param dl_ch_estimates_ext Channel estimates for RBs in this allocation - @param pmi subband Precoding matrix indicator - @param pmi_ext Extracted PMI for chosen RBs - @param rb_alloc RB allocation vector - @param symbol Symbol to extract - @param subframe Subframe index - @param high_speed_flag - @param frame_parms Pointer to frame descriptor -*/ -unsigned short nr_dlsch_extract_rbs_dual(int **rxdataF, - int **dl_ch_estimates, - int **rxdataF_ext, - int **dl_ch_estimates_ext, - unsigned short pmi, - unsigned char *pmi_ext, - unsigned char symbol, - uint8_t pilots, - unsigned short start_rb, - unsigned short nb_rb_pdsch, - unsigned char nr_tti_rx, - uint32_t high_speed_flag, - NR_DL_FRAME_PARMS *frame_parms, - MIMO_mode_t mimo_mode); - -/** \fn dlsch_extract_rbs_TM7(int32_t **rxdataF, - int32_t **dl_bf_ch_estimates, - int32_t **rxdataF_ext, - int32_t **dl_bf_ch_estimates_ext, - uint32_t *rb_alloc, - uint8_t symbol, - uint8_t subframe, - uint32_t high_speed_flag, - NR_DL_FRAME_PARMS *frame_parms) - \brief This function extracts the received resource blocks, both channel estimates and data symbols, - for the current allocation and for single antenna eNB transmission. - @param rxdataF Raw FFT output of received signal - @param dl_bf_ch_estimates Beamforming channel estimates of current slot - @param rxdataF_ext FFT output for RBs in this allocation - @param dl_bf_ch_estimates_ext Beamforming channel estimates for RBs in this allocation - @param rb_alloc RB allocation vector - @param symbol Symbol to extract - @param subframe Subframe number - @param high_speed_flag - @param frame_parms Pointer to frame descriptor -*/ -uint16_t dlsch_extract_rbs_TM7(int32_t **rxdataF, - int32_t **dl_bf_ch_estimates, - int32_t **rxdataF_ext, - int32_t **dl_bf_ch_estimates_ext, - uint32_t *rb_alloc, - uint8_t symbol, - uint8_t subframe, - uint32_t high_speed_flag, - NR_DL_FRAME_PARMS *frame_parms); - -/** \brief This function performs channel compensation (matched filtering) on the received RBs for this allocation. In addition, it computes the squared-magnitude of the channel with weightings for 16QAM/64QAM detection as well as dual-stream detection (cross-correlation) - @param rxdataF_ext Frequency-domain received signal in RBs to be demodulated - @param dl_ch_estimates_ext Frequency-domain channel estimates in RBs to be demodulated - @param dl_ch_mag First Channel magnitudes (16QAM/64QAM) - @param dl_ch_magb Second weighted Channel magnitudes (64QAM) - @param rxdataF_comp Compensated received waveform - @param rho Cross-correlation between two spatial channels on each RX antenna - @param frame_parms Pointer to frame descriptor - @param symbol Symbol on which to operate - @param first_symbol_flag set to 1 on first DLSCH symbol - @param mod_order Modulation order of allocation - @param nb_rb Number of RBs in allocation - @param output_shift Rescaling for compensated output (should be energy-normalizing) - @param phy_measurements Pointer to UE PHY measurements -*/ -void nr_dlsch_channel_compensation(int32_t **rxdataF_ext, - int32_t **dl_ch_estimates_ext, - int32_t **dl_ch_mag, - int32_t **dl_ch_magb, - int32_t **rxdataF_comp, - int32_t **rho, - NR_DL_FRAME_PARMS *frame_parms, - uint8_t symbol, - uint8_t start_symbol, - uint8_t first_symbol_flag, - uint8_t mod_order, - uint16_t nb_rb, - uint8_t output_shift, - PHY_NR_MEASUREMENTS *phy_measurements); - -void nr_dlsch_channel_compensation_core(int **rxdataF_ext, - int **dl_ch_estimates_ext, - int **dl_ch_mag, - int **dl_ch_magb, - int **rxdataF_comp, - int **rho, - unsigned char n_tx, - unsigned char n_rx, - unsigned char mod_order, - unsigned char output_shift, - int length, - int start_point); - -void nr_dlsch_deinterleaving(uint8_t symbol, - uint8_t start_symbol, - uint16_t L, - uint16_t *llr, - uint16_t *llr_deint, - uint16_t nb_rb_pdsch); - -void dlsch_dual_stream_correlation(NR_DL_FRAME_PARMS *frame_parms, - unsigned char symbol, - unsigned short nb_rb, - int **dl_ch_estimates_ext, - int **dl_ch_estimates_ext_i, - int **dl_ch_rho_ext, - unsigned char output_shift); - -void dlsch_dual_stream_correlationTM34(NR_DL_FRAME_PARMS *frame_parms, - unsigned char symbol, - unsigned short nb_rb, - int **dl_ch_estimates_ext, - int **dl_ch_estimates_ext_i, - int **dl_ch_rho_ext, - unsigned char output_shift0, - unsigned char output_shift1); -//This function is used to compute multiplications in Hhermitian * H matrix -void conjch0_mult_ch1(int *ch0, - int *ch1, - int32_t *ch0conj_ch1, - unsigned short nb_rb, - unsigned char output_shift0); - -void construct_HhH_elements(int *ch0conj_ch0, - int *ch1conj_ch1, - int *ch2conj_ch2, - int *ch3conj_ch3, - int *ch0conj_ch1, - int *ch1conj_ch0, - int *ch2conj_ch3, - int *ch3conj_ch2, - int32_t *after_mf_00, - int32_t *after_mf_01, - int32_t *after_mf_10, - int32_t *after_mf_11, - unsigned short nb_rb); - -void squared_matrix_element(int32_t *Hh_h_00, - int32_t *Hh_h_00_sq, - unsigned short nb_rb); - -void dlsch_channel_level_TM34_meas(int *ch00, - int *ch01, - int *ch10, - int *ch11, - int *avg_0, - int *avg_1, - unsigned short nb_rb); - -void nr_dlsch_channel_level_median(int **dl_ch_estimates_ext, - int32_t *median, - int n_tx, - int n_rx, - int length, - int start_point); - -void nr_dlsch_detection_mrc_core(int **rxdataF_comp, - int **rxdataF_comp_i, - int **rho, - int **rho_i, - int **dl_ch_mag, - int **dl_ch_magb, - int **dl_ch_mag_i, - int **dl_ch_magb_i, - unsigned char n_tx, - unsigned char n_rx, - int length, - int start_point); - -void det_HhH(int32_t *after_mf_00, - int32_t *after_mf_01, - int32_t *after_mf_10, - int32_t *after_mf_11, - int32_t *det_fin_128, - unsigned short nb_rb); - -void numer(int32_t *Hh_h_00_sq, - int32_t *Hh_h_01_sq, - int32_t *Hh_h_10_sq, - int32_t *Hh_h_11_sq, - int32_t *num_fin, - unsigned short nb_rb); - -uint8_t rank_estimation_tm3_tm4(int *dl_ch_estimates_00, - int *dl_ch_estimates_01, - int *dl_ch_estimates_10, - int *dl_ch_estimates_11, - unsigned short nb_rb); - -void dlsch_channel_compensation_TM56(int **rxdataF_ext, - int **dl_ch_estimates_ext, - int **dl_ch_mag, - int **dl_ch_magb, - int **rxdataF_comp, - unsigned char *pmi_ext, - NR_DL_FRAME_PARMS *frame_parms, - PHY_NR_MEASUREMENTS *phy_measurements, - int eNB_id, - unsigned char symbol, - unsigned char mod_order, - unsigned short nb_rb, - unsigned char output_shift, - unsigned char dl_power_off); - - -void dlsch_channel_compensation_TM34(NR_DL_FRAME_PARMS *frame_parms, - NR_UE_PDSCH *lte_ue_pdsch_vars, - PHY_NR_MEASUREMENTS *phy_measurements, - int eNB_id, - unsigned char symbol, - unsigned char mod_order0, - unsigned char mod_order1, - int harq_pid, - int round, - MIMO_mode_t mimo_mode, - unsigned short nb_rb, - unsigned char output_shift0, - unsigned char output_shift1); - - -/** \brief This function computes the average channel level over all allocated RBs and antennas (TX/RX) in order to compute output shift for compensated signal - @param dl_ch_estimates_ext Channel estimates in allocated RBs - @param frame_parms Pointer to frame descriptor - @param avg Pointer to average signal strength - @param pilots_flag Flag to indicate pilots in symbol - @param nb_rb Number of allocated RBs -*/ -void nr_dlsch_channel_level(int **dl_ch_estimates_ext, - NR_DL_FRAME_PARMS *frame_parms, - int32_t *avg, - uint8_t symbol, - uint32_t len, - unsigned short nb_rb); - - -void dlsch_channel_level_TM34(int **dl_ch_estimates_ext, - NR_DL_FRAME_PARMS *frame_parms, - unsigned char *pmi_ext, - int *avg_0, - int *avg_1, - uint8_t symbol, - unsigned short nb_rb, - MIMO_mode_t mimo_mode); - - -void dlsch_channel_level_TM56(int32_t **dl_ch_estimates_ext, - NR_DL_FRAME_PARMS *frame_parms, - unsigned char *pmi_ext, - int32_t *avg, - uint8_t symbol_mod, - uint16_t nb_rb); - -void dlsch_channel_level_TM7(int32_t **dl_bf_ch_estimates_ext, - NR_DL_FRAME_PARMS *frame_parms, - int32_t *avg, - uint8_t pilots_flag, - uint16_t nb_rb); - -void nr_dlsch_scale_channel(int32_t **dl_ch_estimates_ext, - NR_DL_FRAME_PARMS *frame_parms, - NR_UE_DLSCH_t **dlsch_ue, - uint8_t symbol, - uint8_t start_symbol, - uint16_t nb_rb); - -/** \brief This is the top-level entry point for DLSCH decoding in UE. It should be replicated on several - threads (on multi-core machines) corresponding to different HARQ processes. The routine first - computes the segmentation information, followed by rate dematching and sub-block deinterleaving the of the - received LLRs computed by dlsch_demodulation for each transport block segment. It then calls the - turbo-decoding algorithm for each segment and stops after either after unsuccesful decoding of at least - one segment or correct decoding of all segments. Only the segment CRCs are check for the moment, the - overall CRC is ignored. Finally transport block reassembly is performed. - @param phy_vars_ue Pointer to ue variables - @param dlsch_llr Pointer to LLR values computed by dlsch_demodulation - @param lte_frame_parms Pointer to frame descriptor - @param dlsch Pointer to DLSCH descriptor - @param frame Frame number - @param subframe Subframe number - @param num_pdcch_symbols Number of PDCCH symbols - @param is_crnti indicates if PDSCH belongs to a CRNTI (necessary for parallelizing decoding threads) - @param llr8_flag If 1, indicate that the 8-bit turbo decoder should be used - @returns 0 on success, 1 on unsuccessful decoding -*/ - -uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, - short *dlsch_llr, - NR_DL_FRAME_PARMS *frame_parms, - NR_UE_DLSCH_t *dlsch, - NR_DL_UE_HARQ_t *harq_process, - uint32_t frame, - uint16_t nb_symb_sch, - uint8_t nr_tti_rx, - uint8_t harq_pid, - uint8_t is_crnti, - uint8_t llr8_flag); - -int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch, - NR_DL_FRAME_PARMS* frame_parms, - uint8_t harq_pid); - -/*! \brief Perform PUSCH scrambling. TS 38.211 V15.4.0 subclause 6.3.1.1 - @param[in] in Pointer to input bits - @param[in] size of input bits - @param[in] Nid cell id - @param[in] n_RNTI CRNTI - @param[out] out the scrambled bits -*/ - -void nr_pusch_codeword_scrambling(uint8_t *in, - uint16_t size, - uint32_t Nid, - uint32_t n_RNTI, - uint32_t* out); - - -uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue, - UE_nr_rxtx_proc_t *proc, - int eNB_id, - short *dlsch_llr, - NR_DL_FRAME_PARMS *frame_parms, - NR_UE_DLSCH_t *dlsch, - NR_DL_UE_HARQ_t *harq_process, - uint32_t frame, - uint16_t nb_symb_sch, - uint8_t nr_tti_rx, - uint8_t harq_pid, - uint8_t is_crnti, - uint8_t llr8_flag); - -void *nr_dlsch_decoding_2thread0(void *arg); - -void *nr_dlsch_decoding_2thread1(void *arg); - -void nr_dlsch_unscrambling(int16_t* llr, - uint32_t size, - uint8_t q, - uint32_t Nid, - uint32_t n_RNTI); - -uint32_t dlsch_decoding_emul(PHY_VARS_NR_UE *phy_vars_ue, - uint8_t subframe, - PDSCH_t dlsch_id, - uint8_t eNB_id); - -/** \brief This function is the top-level entry point to PDSCH demodulation, after frequency-domain transformation and channel estimation. It performs - - RB extraction (signal and channel estimates) - - channel compensation (matched filtering) - - RE extraction (pilot, PBCH, synch. signals) - - antenna combining (MRC, Alamouti, cycling) - - LLR computation - This function supports TM1, 2, 3, 5, and 6. - @param PHY_VARS_NR_UE Pointer to PHY variables - @param type Type of PDSCH (SI_PDSCH,RA_PDSCH,PDSCH,PMCH) - @param eNB_id eNb index (Nid1) 0,1,2 - @param eNB_id_i Interfering eNB index (Nid1) 0,1,2, or 3 in case of MU-MIMO IC receiver - @param subframe Subframe number - @param symbol Symbol on which to act (within sub-frame) - @param first_symbol_flag set to 1 on first DLSCH symbol - @param rx_type. rx_type=RX_IC_single_stream will enable interference cancellation of a second stream when decoding the first stream. In case of TM1, 2, 5, and this can cancel interference from a neighbouring cell given by eNB_id_i. In case of TM5, eNB_id_i should be set to n_connected_eNB to perform multi-user interference cancellation. In case of TM3, eNB_id_i should be set to eNB_id to perform co-channel interference cancellation; this option should be used together with an interference cancellation step [...]. In case of TM3, if rx_type=RX_IC_dual_stream, both streams will be decoded by applying the IC single stream receiver twice. - @param i_mod Modulation order of the interfering stream -*/ -int32_t nr_rx_pdsch(PHY_VARS_NR_UE *phy_vars_ue, - PDSCH_t type, - uint8_t eNB_id, - uint8_t eNB_id_i, - uint32_t frame, - uint8_t subframe, - uint8_t symbol, - uint8_t first_symbol_flag, - RX_type_t rx_type, - uint8_t i_mod, - uint8_t harq_pid); - -int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue, - uint32_t frame, - uint8_t nr_tti_rx, - uint8_t eNB_id, - MIMO_mode_t mimo_mode, - uint32_t high_speed_flag, - uint8_t is_secondary_ue, - int nb_coreset_active, - uint16_t symbol_mon, - NR_SEARCHSPACE_TYPE_t searchSpaceType); - -/*! \brief Extract PSS and SSS resource elements - @param phy_vars_ue Pointer to UE variables - @param[out] pss_ext contain the PSS signals after the extraction - @param[out] sss_ext contain the SSS signals after the extraction - @returns 0 on success -*/ -int pss_sss_extract(PHY_VARS_NR_UE *phy_vars_ue, - int32_t pss_ext[4][72], - int32_t sss_ext[4][72], - uint8_t subframe); - -/*! \brief Extract only PSS resource elements - @param phy_vars_ue Pointer to UE variables - @param[out] pss_ext contain the PSS signals after the extraction - @returns 0 on success -*/ -int pss_only_extract(PHY_VARS_NR_UE *phy_vars_ue, - int32_t pss_ext[4][72], - uint8_t subframe); - -/*! \brief Extract only SSS resource elements - @param phy_vars_ue Pointer to UE variables - @param[out] sss_ext contain the SSS signals after the extraction - @returns 0 on success -*/ -int sss_only_extract(PHY_VARS_NR_UE *phy_vars_ue, - int32_t sss_ext[4][72], - uint8_t subframe); - -/*! \brief Performs detection of SSS to find cell ID and other framing parameters (FDD/TDD, normal/extended prefix) - @param phy_vars_ue Pointer to UE variables - @param tot_metric Pointer to variable containing maximum metric under framing hypothesis (to be compared to other hypotheses - @param flip_max Pointer to variable indicating if start of frame is in second have of RX buffer (i.e. PSS/SSS is flipped) - @param phase_max Pointer to variable (0 ... 6) containing rought phase offset between PSS and SSS (can be used for carrier - frequency adjustment. 0 means -pi/3, 6 means pi/3. - @returns 0 on success -*/ -int rx_sss(PHY_VARS_NR_UE *phy_vars_ue,int32_t *tot_metric,uint8_t *flip_max,uint8_t *phase_max); - -/*! \brief receiver for the PBCH - \returns number of tx antennas or -1 if error -*/ -int nr_rx_pbch( PHY_VARS_NR_UE *ue, - UE_nr_rxtx_proc_t *proc, - NR_UE_PBCH *nr_ue_pbch_vars, - NR_DL_FRAME_PARMS *frame_parms, - uint8_t eNB_id, - uint8_t i_ssb, - MIMO_mode_t mimo_mode, - uint32_t high_speed_flag); - -int nr_pbch_detection(UE_nr_rxtx_proc_t *proc, - PHY_VARS_NR_UE *ue, - int pbch_initial_symbol, - runmode_t mode); - -uint16_t rx_pbch_emul(PHY_VARS_NR_UE *phy_vars_ue, - uint8_t eNB_id, - uint8_t pbch_phase); - - -/*! \brief PBCH unscrambling - This is similar to pbch_scrabling with the difference that inputs are signed s16s (llr values) and instead of flipping bits we change signs. - \param frame_parms Pointer to frame descriptor - \param llr Output of the demodulator - \param length Length of the sequence - \param frame_mod4 Frame number modulo 4*/ -void pbch_unscrambling(NR_DL_FRAME_PARMS *frame_parms, - int8_t* llr, - uint32_t length, - uint8_t frame_mod4); - - -void generate_64qam_table(void); -void generate_16qam_table(void); -void generate_qpsk_table(void); - -uint16_t extract_crc(uint8_t *dci,uint8_t DCI_LENGTH); - -/*! \brief LLR from two streams. This function takes two streams (qpsk modulated) and calculates the LLR, considering one stream as interference. - \param stream0_in pointer to first stream0 - \param stream1_in pointer to first stream1 - \param stream0_out pointer to output stream - \param rho01 pointer to correlation matrix - \param length*/ -void qpsk_qpsk_TM3456(short *stream0_in, - short *stream1_in, - short *stream0_out, - short *rho01, - int length - ); - -/** \brief Attempt decoding of a particular DCI with given length and format. - @param DCI_LENGTH length of DCI in bits - @param DCI_FMT Format of DCI - @param e e-sequence (soft bits) - @param decoded_output Output of Viterbi decoder -*/ -void dci_decoding(uint8_t DCI_LENGTH, - uint8_t DCI_FMT, - int8_t *e, - uint8_t *decoded_output); - -/** \brief Do 36.213 DCI decoding procedure by searching different RNTI options and aggregation levels. Currently does - not employ the complexity reducing procedure based on RNTI. - @param phy_vars_ue UE variables - @param dci_alloc Pointer to DCI_ALLOC_t array to store results for DLSCH/ULSCH programming - @param do_common If 1 perform search in common search-space else ue-specific search-space - @param eNB_id eNB Index on which to act - @param subframe Index of subframe - @returns bitmap of occupied CCE positions (i.e. those detected) -*/ -uint16_t dci_decoding_procedure(PHY_VARS_NR_UE *phy_vars_ue, - DCI_ALLOC_t *dci_alloc, - int do_common, - int16_t eNB_id, - uint8_t subframe); - -uint16_t dci_CRNTI_decoding_procedure(PHY_VARS_NR_UE *ue, - DCI_ALLOC_t *dci_alloc, - uint8_t DCIFormat, - uint8_t agregationLevel, - int16_t eNB_id, - uint8_t subframe); - -uint16_t dci_decoding_procedure_emul(NR_UE_PDCCH **lte_ue_pdcch_vars, - uint8_t num_ue_spec_dci, - uint8_t num_common_dci, - DCI_ALLOC_t *dci_alloc_tx, - DCI_ALLOC_t *dci_alloc_rx, - int16_t eNB_id); - -/** \brief Compute Q (modulation order) based on I_MCS PDSCH. Implements table 7.1.7.1-1 from 36.213. - @param I_MCS */ -uint8_t get_Qm(uint8_t I_MCS); - -/** \brief Compute Q (modulation order) based on I_MCS for PUSCH. Implements table 8.6.1-1 from 36.213. - @param I_MCS */ -uint8_t get_Qm_ul(uint8_t I_MCS); - -/** \brief Compute I_TBS (transport-block size) based on I_MCS for PDSCH. Implements table 7.1.7.1-1 from 36.213. - @param I_MCS */ -uint8_t get_I_TBS(uint8_t I_MCS); - -/** \brief Compute I_TBS (transport-block size) based on I_MCS for PUSCH. Implements table 8.6.1-1 from 36.213. - @param I_MCS */ -unsigned char get_I_TBS_UL(unsigned char I_MCS); - -/** \brief Compute Q (modulation order) based on downlink I_MCS. Implements table 7.1.7.1-1 from 36.213. - @param I_MCS - @param nb_rb - @return Transport block size */ -uint32_t get_TBS_DL(uint8_t mcs, uint16_t nb_rb); - -/** \brief Compute Q (modulation order) based on uplink I_MCS. Implements table 7.1.7.1-1 from 36.213. - @param I_MCS - @param nb_rb - @return Transport block size */ -uint32_t get_TBS_UL(uint8_t mcs, uint16_t nb_rb); - -/* \brief Return bit-map of resource allocation for a given DCI rballoc (RIV format) and vrb type - @param N_RB_DL number of PRB on DL - @param indicator for even/odd slot - @param vrb vrb index - @param Ngap Gap indicator -*/ -uint32_t get_prb(int N_RB_DL,int odd_slot,int vrb,int Ngap); - -/* \brief Return prb for a given vrb index - @param vrb_type VRB type (0=localized,1=distributed) - @param rb_alloc_dci rballoc field from DCI -*/ -uint32_t get_rballoc(vrb_t vrb_type,uint16_t rb_alloc_dci); - - -/* \brief Return bit-map of resource allocation for a given DCI rballoc (RIV format) and vrb type - @returns Transmission mode (1-7) -*/ -uint8_t get_transmission_mode(module_id_t Mod_id, uint8_t CC_id, rnti_t rnti); - - -/* \brief - @param ra_header Header of resource allocation (0,1) (See sections 7.1.6.1/7.1.6.2 of 36.213 Rel8.6) - @param rb_alloc Bitmap allocation from DCI (format 1,2) - @returns number of physical resource blocks -*/ -uint32_t conv_nprb(uint8_t ra_header,uint32_t rb_alloc,int N_RB_DL); - -int get_G(NR_DL_FRAME_PARMS *frame_parms,uint16_t nb_rb,uint32_t *rb_alloc,uint8_t mod_order,uint8_t Nl,uint8_t num_pdcch_symbols,int frame,uint8_t subframe, uint8_t beamforming_mode); - -int adjust_G(NR_DL_FRAME_PARMS *frame_parms,uint32_t *rb_alloc,uint8_t mod_order,uint8_t subframe); -int adjust_G2(NR_DL_FRAME_PARMS *frame_parms,uint32_t *rb_alloc,uint8_t mod_order,uint8_t subframe,uint8_t symbol); - - -#ifndef modOrder -#define modOrder(I_MCS,I_TBS) ((I_MCS-I_TBS)*2+2) // Find modulation order from I_TBS and I_MCS -#endif - -/** \fn uint8_t I_TBS2I_MCS(uint8_t I_TBS); - \brief This function maps I_tbs to I_mcs according to Table 7.1.7.1-1 in 3GPP TS 36.213 V8.6.0. Where there is two supported modulation orders for the same I_TBS then either high or low modulation is chosen by changing the equality of the two first comparisons in the if-else statement. - \param I_TBS Index of Transport Block Size - \return I_MCS given I_TBS -*/ -uint8_t I_TBS2I_MCS(uint8_t I_TBS); - -/** \fn uint8_t SE2I_TBS(float SE, - uint8_t N_PRB, - uint8_t symbPerRB); - \brief This function maps a requested throughput in number of bits to I_tbs. The throughput is calculated as a function of modulation order, RB allocation and number of symbols per RB. The mapping orginates in the "Transport block size table" (Table 7.1.7.2.1-1 in 3GPP TS 36.213 V8.6.0) - \param SE Spectral Efficiency (before casting to integer, multiply by 1024, remember to divide result by 1024!) - \param N_PRB Number of PhysicalResourceBlocks allocated \sa lte_frame_parms->N_RB_DL - \param symbPerRB Number of symbols per resource block allocated to this channel - \return I_TBS given an SE and an N_PRB -*/ -uint8_t SE2I_TBS(float SE, - uint8_t N_PRB, - uint8_t symbPerRB); -/** \brief This function generates the sounding reference symbol (SRS) for the uplink according to 36.211 v8.6.0. If IFFT_FPGA is defined, the SRS is quantized to a QPSK sequence. - @param frame_parms LTE DL Frame Parameters - @param soundingrs_ul_config_dedicated Dynamic configuration from RRC during Connection Establishment - @param txdataF pointer to the frequency domain TX signal - @returns 0 on success*/ -int generate_srs(NR_DL_FRAME_PARMS *frame_parms, - SOUNDINGRS_UL_CONFIG_DEDICATED *soundingrs_ul_config_dedicated, - int *txdataF, - int16_t amp, - uint32_t subframe); - - -/*! - \brief This function is similar to generate_srs_tx but generates a conjugate sequence for channel estimation. If IFFT_FPGA is defined, the SRS is quantized to a QPSK sequence. - @param phy_vars_ue Pointer to PHY_VARS structure - @param eNB_id Index of destination eNB for this SRS - @param amp Linear amplitude of SRS - @param subframe Index of subframe on which to act - @returns 0 on success, -1 on error with message -*/ - -int32_t generate_srs_tx(PHY_VARS_NR_UE *phy_vars_ue, - uint8_t eNB_id, - int16_t amp, - uint32_t subframe); - -/*! - \brief This function generates the downlink reference signal for the PUSCH according to 36.211 v8.6.0. The DRS occuies the RS defined by rb_alloc and the symbols 2 and 8 for extended CP and 3 and 10 for normal CP. -*/ - -int32_t generate_drs_pusch(PHY_VARS_NR_UE *phy_vars_ue, - UE_nr_rxtx_proc_t *proc, - uint8_t eNB_id, - int16_t amp, - uint32_t subframe, - uint32_t first_rb, - uint32_t nb_rb, - uint8_t ant); - -/*! - \brief This function initializes the Group Hopping, Sequence Hopping and nPRS sequences for PUCCH/PUSCH according to 36.211 v8.6.0. It should be called after configuration of UE (reception of SIB2/3) and initial configuration of eNB (or after reconfiguration of cell-specific parameters). - @param frame_parms Pointer to a NR_DL_FRAME_PARMS structure (eNB or UE)*/ -void init_ul_hopping(NR_DL_FRAME_PARMS *frame_parms); - - -/*! - \brief This function implements the initialization of paging parameters for UE (See Section 7, 36.304).It must be called after setting IMSImod1024 during UE startup and after receiving SIB2 - @param ue Pointer to UE context - @param defaultPagingCycle T from 36.304 (0=32,1=64,2=128,3=256) - @param nB nB from 36.304 (0=4T,1=2T,2=T,3=T/2,4=T/4,5=T/8,6=T/16,7=T/32*/ -int init_ue_paging_info(PHY_VARS_NR_UE *ue, long defaultPagingCycle, long nB); - -int32_t compareints (const void * a, const void * b); - - -void ulsch_modulation(int32_t **txdataF, - int16_t amp, - frame_t frame, - uint32_t subframe, - NR_DL_FRAME_PARMS *frame_parms, - NR_UE_ULSCH_t *ulsch); - - - - - - -int generate_ue_dlsch_params_from_dci(int frame, - uint8_t subframe, - void *dci_pdu, - rnti_t rnti, - DCI_format_t dci_format, - NR_UE_PDCCH *pdcch_vars, - NR_UE_PDSCH *pdsch_vars, - NR_UE_DLSCH_t **dlsch, - NR_DL_FRAME_PARMS *frame_parms, - PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated, - uint16_t si_rnti, - uint16_t ra_rnti, - uint16_t p_rnti, - uint8_t beamforming_mode, - uint16_t tc_rnti); - - -int generate_ue_ulsch_params_from_dci(void *dci_pdu, - rnti_t rnti, - uint8_t subframe, - DCI_format_t dci_format, - PHY_VARS_NR_UE *phy_vars_ue, - UE_nr_rxtx_proc_t *proc, - uint16_t si_rnti, - uint16_t ra_rnti, - uint16_t p_rnti, - uint16_t cba_rnti, - uint8_t eNB_id, - uint8_t use_srs); - -int32_t generate_ue_ulsch_params_from_rar(PHY_VARS_NR_UE *phy_vars_ue, - UE_nr_rxtx_proc_t *proc, - uint8_t eNB_id); -double sinr_eff_cqi_calc(PHY_VARS_NR_UE *phy_vars_ue, - uint8_t eNB_id, - uint8_t subframe); - -uint8_t sinr2cqi(double sinr,uint8_t trans_mode); - - -int dump_dci(NR_DL_FRAME_PARMS *frame_parms, DCI_ALLOC_t *dci); - -int dump_ue_stats(PHY_VARS_NR_UE *phy_vars_ue, UE_nr_rxtx_proc_t *proc, char* buffer, int length, runmode_t mode, int input_level_dBm); - -void init_transport_channels(uint8_t); - -void generate_RIV_tables(void); - -/*! - \brief This function performs the initial cell search procedure - PSS detection, SSS detection and PBCH detection. At the - end, the basic frame parameters are known (Frame configuration - TDD/FDD and cyclic prefix length, - N_RB_DL, PHICH_CONFIG and Nid_cell) and the UE can begin decoding PDCCH and DLSCH SI to retrieve the rest. Once these - parameters are know, the routine calls some basic initialization routines (cell-specific reference signals, etc.) - @param phy_vars_ue Pointer to UE variables - @param mode current running mode -*/ -int nr_initial_sync(UE_nr_rxtx_proc_t *proc, - PHY_VARS_NR_UE *phy_vars_ue, runmode_t mode); - - -/*! - \brief Encoding of PUSCH/ACK/RI/ACK from 36-212. - @param a Pointer to ulsch SDU - @param frame_parms Pointer to Frame parameters - @param ulsch Pointer to ulsch descriptor - @param harq_pid HARQ process ID - @param tmode Transmission mode (1-7) - @param control_only_flag Generate PUSCH with control information only - @param Nbundled Parameter for ACK/NAK bundling (36.213 Section 7.3) -*/ -uint32_t ulsch_encoding(uint8_t *a, - PHY_VARS_NR_UE *phy_vars_ue, - uint8_t harq_pid, - uint8_t eNB_id, - uint8_t subframe_rx, - uint8_t tmode, - uint8_t control_only_flag, - uint8_t Nbundled); - -void print_CQI(void *o,UCI_format_t uci_format,uint8_t eNB_id,int N_RB_DL); - -void fill_CQI(NR_UE_ULSCH_t *ulsch,PHY_NR_MEASUREMENTS *meas,uint8_t eNB_id, uint8_t harq_pid,int N_RB_DL, rnti_t rnti, uint8_t trans_mode,double sinr_eff); - -void reset_cba_uci(void *o); - -/** \brief This routine computes the subband PMI bitmap based on measurements (0,1,2,3 for rank 0 and 0,1 for rank 1) in the format needed for UCI - @param meas pointer to measurements - @param eNB_id eNB_id - @param nb_subbands number of subbands - @returns subband PMI bitmap -*/ -uint16_t quantize_subband_pmi(PHY_NR_MEASUREMENTS *meas,uint8_t eNB_id,int nb_subbands); - -int32_t pmi_convert_rank1_from_rank2(uint16_t pmi_alloc, int tpmi, int nb_rb); - -uint16_t quantize_subband_pmi2(PHY_NR_MEASUREMENTS *meas,uint8_t eNB_id,uint8_t a_id,int nb_subbands); - - - -uint64_t cqi2hex(uint32_t cqi); - -uint16_t computeRIV(uint16_t N_RB_DL,uint16_t RBstart,uint16_t Lcrbs); - - -/** \brief This routine extracts a single subband PMI from a bitmap coming from UCI or the pmi_extend function - @param N_RB_DL number of resource blocks - @param mimo_mode - @param pmi_alloc subband PMI bitmap - @param rb resource block for which to extract PMI - @returns subband PMI -*/ -uint8_t get_pmi(uint8_t N_RB_DL,MIMO_mode_t mode, uint32_t pmi_alloc,uint16_t rb); - -int get_nCCE_offset_l1(int *CCE_table, - const unsigned char L, - const int nCCE, - const int common_dci, - const unsigned short rnti, - const unsigned char subframe); - -uint16_t get_nCCE(uint8_t num_pdcch_symbols,NR_DL_FRAME_PARMS *frame_parms,uint8_t mi); - -uint16_t get_nquad(uint8_t num_pdcch_symbols,NR_DL_FRAME_PARMS *frame_parms,uint8_t mi); - -uint8_t get_mi(NR_DL_FRAME_PARMS *frame,uint8_t subframe); - -uint16_t get_nCCE_mac(uint8_t Mod_id,uint8_t CC_id,int num_pdcch_symbols,int subframe); - -uint8_t get_num_pdcch_symbols(uint8_t num_dci,DCI_ALLOC_t *dci_alloc,NR_DL_FRAME_PARMS *frame_parms,uint8_t subframe); - -void pdcch_interleaving(NR_DL_FRAME_PARMS *frame_parms,int32_t **z, int32_t **wbar,uint8_t n_symbols_pdcch,uint8_t mi); - -void pdcch_unscrambling(NR_DL_FRAME_PARMS *frame_parms, - uint8_t subframe, - int8_t* llr, - uint32_t length); - - - -void dlsch_unscrambling(NR_DL_FRAME_PARMS *frame_parms, - int mbsfn_flag, - NR_UE_DLSCH_t *dlsch, - int G, - int16_t* llr, - uint8_t q, - uint8_t Ns); - -void init_ncs_cell(NR_DL_FRAME_PARMS *frame_parms,uint8_t ncs_cell[20][7]); - -void generate_pucch1x(int32_t **txdataF, - NR_DL_FRAME_PARMS *frame_parms, - uint8_t ncs_cell[20][7], - PUCCH_FMT_t fmt, - PUCCH_CONFIG_DEDICATED *pucch_config_dedicated, - uint16_t n1_pucch, - uint8_t shortened_format, - uint8_t *payload, - int16_t amp, - uint8_t subframe); - -void generate_pucch2x(int32_t **txdataF, - NR_DL_FRAME_PARMS *fp, - uint8_t ncs_cell[20][7], - PUCCH_FMT_t fmt, - PUCCH_CONFIG_DEDICATED *pucch_config_dedicated, - uint16_t n2_pucch, - uint8_t *payload, - int A, - int B2, - int16_t amp, - uint8_t subframe, - uint16_t rnti); - -void generate_pucch3x(int32_t **txdataF, - NR_DL_FRAME_PARMS *frame_parms, - uint8_t ncs_cell[20][7], - PUCCH_FMT_t fmt, - PUCCH_CONFIG_DEDICATED *pucch_config_dedicated, - uint16_t n3_pucch, - uint8_t shortened_format, - uint8_t *payload, - int16_t amp, - uint8_t subframe, - uint16_t rnti); - - -void init_ulsch_power_LUT(void); - -/*! - \brief Check for PRACH TXop in subframe - @param frame_parms Pointer to NR_DL_FRAME_PARMS - @param frame frame index to check - @param subframe subframe index to check - @returns 0 on success -*/ -int is_prach_subframe(NR_DL_FRAME_PARMS *frame_parms,frame_t frame, uint8_t subframe); - -/*! - \brief Generate PRACH waveform - @param phy_vars_ue Pointer to ue top-level descriptor - @param eNB_id Index of destination eNB - @param subframe subframe index to operate on - @param index of preamble (0-63) - @param Nf System frame number - @returns 0 on success - -*/ -int32_t generate_prach(PHY_VARS_NR_UE *phy_vars_ue,uint8_t eNB_id,uint8_t subframe,uint16_t Nf); - - -/*! - \brief Helper for MAC, returns number of available PRACH in TDD for a particular configuration index - @param frame_parms Pointer to NR_DL_FRAME_PARMS structure - @returns 0-5 depending on number of available prach -*/ -uint8_t get_num_prach_tdd(module_id_t Mod_id); - -/*! - \brief Return the PRACH format as a function of the Configuration Index and Frame type. - @param prach_ConfigIndex PRACH Configuration Index - @param frame_type 0-FDD, 1-TDD - @returns 0-1 accordingly -*/ -uint8_t get_prach_fmt(uint8_t prach_ConfigIndex,lte_frame_type_t frame_type); - -/*! - \brief Helper for MAC, returns frequency index of PRACH resource in TDD for a particular configuration index - @param frame_parms Pointer to NR_DL_FRAME_PARMS structure - @returns 0-5 depending on number of available prach -*/ -uint8_t get_fid_prach_tdd(module_id_t Mod_id,uint8_t tdd_map_index); - -/*! - \brief Comp ute DFT of PRACH ZC sequences. Used for generation of prach in UE and reception of PRACH in eNB. - @param rootSequenceIndex PRACH root sequence - #param prach_ConfigIndex PRACH Configuration Index - @param zeroCorrelationZoneConfig PRACH ncs_config - @param highSpeedFlat PRACH High-Speed Flag - @param frame_type TDD/FDD flag - @param Xu DFT output -*/ -void compute_prach_seq(uint16_t rootSequenceIndex, - uint8_t prach_ConfigIndex, - uint8_t zeroCorrelationZoneConfig, - uint8_t highSpeedFlag, - lte_frame_type_t frame_type, - uint32_t X_u[64][839]); - -void compute_nr_prach_seq(uint8_t short_sequence, - uint8_t num_sequences, - uint8_t rootSequenceIndex, - uint32_t X_u[64][839]); - -void init_prach_tables(int N_ZC); -void init_nr_prach_tables(int N_ZC); - -void init_unscrambling_lut(void); -void init_scrambling_lut(void); - -/*! - \brief Return the status of MBSFN in this frame/subframe - @param frame Frame index - @param subframe Subframe index - @param frame_parms Pointer to frame parameters - @returns 1 if subframe is for MBSFN -*/ -int is_pmch_subframe(frame_t frame, int subframe, NR_DL_FRAME_PARMS *frame_parms); - -uint8_t is_not_pilot(uint8_t pilots, uint8_t re, uint8_t nushift, uint8_t use2ndpilots); - -uint8_t is_not_UEspecRS(int8_t lprime, uint8_t re, uint8_t nushift, uint8_t Ncp, uint8_t beamforming_mode); - -uint32_t dlsch_decoding_abstraction(double *dlsch_MIPB, - NR_DL_FRAME_PARMS *lte_frame_parms, - NR_UE_DLSCH_t *dlsch, - uint8_t subframe, - uint8_t num_pdcch_symbols); - -// DL power control functions -double get_pa_dB(uint8_t pa); - - -double computeRhoA_UE(PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated, - NR_UE_DLSCH_t *dlsch_ue, - uint8_t dl_power_off, - uint8_t n_antenna_port); - -double computeRhoB_UE(PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated, - PDSCH_CONFIG_COMMON *pdsch_config_common, - uint8_t n_antenna_port, - NR_UE_DLSCH_t *dlsch_ue, - uint8_t dl_power_off); - -/*void compute_sqrt_RhoAoRhoB(PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated, - PDSCH_CONFIG_COMMON *pdsch_config_common, - uint8_t n_antenna_port, - NR_UE_DLSCH_t *dlsch_ue); -*/ - -uint8_t get_prach_prb_offset(NR_DL_FRAME_PARMS *frame_parms, - uint8_t prach_ConfigIndex, - uint8_t n_ra_prboffset, - uint8_t tdd_mapindex, uint16_t Nf); - -void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8_t nr_tti_rx, - int16_t *z, uint32_t length, uint16_t pdcch_DMRS_scrambling_id, int do_common); - - -uint32_t lte_gold_generic(uint32_t *x1, uint32_t *x2, uint8_t reset); - -int nr_rx_pdsch(PHY_VARS_NR_UE *ue, - PDSCH_t type, - unsigned char eNB_id, - unsigned char eNB_id_i, //if this == ue->n_connected_eNB, we assume MU interference - uint32_t frame, - uint8_t nr_tti_rx, - unsigned char symbol, - unsigned char first_symbol_flag, - RX_type_t rx_type, - unsigned char i_mod, - unsigned char harq_pid); - -uint32_t nr_get_G(uint16_t nb_rb, uint16_t nb_symb_sch,uint8_t nb_re_dmrs,uint16_t length_dmrs, uint8_t Qm, uint8_t Nl) ; - -uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, - short *dlsch_llr, - NR_DL_FRAME_PARMS *frame_parms, - NR_UE_DLSCH_t *dlsch, - NR_DL_UE_HARQ_t *harq_process, - uint32_t frame, - uint16_t nb_symb_sch, - uint8_t nr_tti_rx, - uint8_t harq_pid, - uint8_t is_crnti, - uint8_t llr8_flag); - -/**@}*/ -#endif diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c index cdb7229998..c8dcfdd3f9 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c @@ -35,7 +35,7 @@ #include "PHY/impl_defs_nr.h" #include "PHY/defs_nr_UE.h" #include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" -#include "PHY/NR_TRANSPORT/nr_transport_proto_common.h" +#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" #include "common/utils/LOG/log.h" #include "common/utils/LOG/vcd_signal_dumper.h" diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h index d20457de06..8dbe588cb8 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h @@ -37,6 +37,9 @@ #include #include "nfapi_interface.h" +#define NR_PUSCH_x 2 // UCI placeholder bit TS 38.212 V15.4.0 subclause 5.3.3.1 +#define NR_PUSCH_y 3 // UCI placeholder bit + // Functions below implement 36-211 and 36-212 /** @addtogroup _PHY_TRANSPORT_ @@ -66,24 +69,6 @@ void free_nr_ue_ulsch(NR_UE_ULSCH_t **ulsch,unsigned char N_RB_UL); NR_UE_ULSCH_t *new_nr_ue_ulsch(uint16_t N_RB_UL, int number_of_harq_pids, uint8_t abstraction_flag); -void fill_UE_dlsch_MCH(PHY_VARS_NR_UE *ue,int mcs,int ndi,int rvidx,int eNB_id); - -int rx_pmch(PHY_VARS_NR_UE *phy_vars_ue, - unsigned char eNB_id, - uint8_t subframe, - unsigned char symbol); - -/** \brief Dump OCTAVE/MATLAB files for PMCH debugging - @param phy_vars_ue Pointer to UE variables - @param eNB_id index of eNB in ue variables - @param coded_bits_per_codeword G from 36.211 - @param subframe Index of subframe - @returns 0 on success -*/ -void dump_mch(PHY_VARS_NR_UE *phy_vars_ue,uint8_t eNB_id,uint16_t coded_bits_per_codeword,int subframe); - - - /** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream QPSK/QPSK reception. @param stream0_in Input from channel compensated (MR combined) stream 0 @param stream1_in Input from channel compensated (MR combined) stream 1 diff --git a/openair1/SIMULATION/NR_PHY/prachsim.c b/openair1/SIMULATION/NR_PHY/prachsim.c index a6904ed25b..4c37e49fb2 100644 --- a/openair1/SIMULATION/NR_PHY/prachsim.c +++ b/openair1/SIMULATION/NR_PHY/prachsim.c @@ -42,7 +42,7 @@ #include "PHY/MODULATION/modulation_UE.h" #include "PHY/INIT/phy_init.h" #include "PHY/NR_TRANSPORT/nr_transport_proto.h" -#include "PHY/NR_TRANSPORT/nr_transport_proto_common.h" +#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h" #include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" #include "nr_unitary_defs.h" #include "OCG_vars.h" From 19530c5ab9f03f6f620e67a29adedd4a537f0d23 Mon Sep 17 00:00:00 2001 From: cig Date: Thu, 9 Apr 2020 18:55:57 +0200 Subject: [PATCH 169/553] Cleanup nr transport header file --- openair1/PHY/CODING/TESTBENCH/polartest.c | 1 - openair1/PHY/NR_TRANSPORT/nr_pbch.c | 1 - openair1/PHY/NR_TRANSPORT/nr_transport.h | 27 ------------------- .../PHY/NR_TRANSPORT/nr_transport_proto.h | 7 +++++ .../NR_UE_TRANSPORT/nr_dlsch_demodulation.c | 1 - openair1/SCHED_NR/fapi_nr_l1.c | 1 - openair1/SCHED_NR/phy_procedures_nr_gNB.c | 1 - openair1/SIMULATION/NR_PHY/ulsim.c | 1 - 8 files changed, 7 insertions(+), 33 deletions(-) delete mode 100644 openair1/PHY/NR_TRANSPORT/nr_transport.h diff --git a/openair1/PHY/CODING/TESTBENCH/polartest.c b/openair1/PHY/CODING/TESTBENCH/polartest.c index 806d8de28c..776409121b 100644 --- a/openair1/PHY/CODING/TESTBENCH/polartest.c +++ b/openair1/PHY/CODING/TESTBENCH/polartest.c @@ -12,7 +12,6 @@ #include "PHY/CODING/coding_defs.h" #include "SIMULATION/TOOLS/sim.h" #include "openair1/SIMULATION/NR_PHY/nr_unitary_defs.h" -//#include "PHY/NR_TRANSPORT/nr_transport.h" //#include "common/utils/LOG/log.h" //#define DEBUG_DCI_POLAR_PARAMS diff --git a/openair1/PHY/NR_TRANSPORT/nr_pbch.c b/openair1/PHY/NR_TRANSPORT/nr_pbch.c index 923e920321..f5a26aec80 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_pbch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_pbch.c @@ -33,7 +33,6 @@ #include "PHY/defs_gNB.h" #include "PHY/NR_TRANSPORT/nr_transport_proto.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" #include "PHY/LTE_REFSIG/lte_refsig.h" #include "PHY/sse_intrin.h" diff --git a/openair1/PHY/NR_TRANSPORT/nr_transport.h b/openair1/PHY/NR_TRANSPORT/nr_transport.h deleted file mode 100644 index 9597de10a7..0000000000 --- a/openair1/PHY/NR_TRANSPORT/nr_transport.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. - * The OpenAirInterface Software Alliance licenses this file to You under - * the OAI Public License, Version 1.1 (the "License"); you may not use this file - * except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.openairinterface.org/?page_id=698 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - *------------------------------------------------------------------------------- - * For more information about the OpenAirInterface (OAI) Software Alliance: - * contact@openairinterface.org - */ - -#ifndef __NR_TRANSPORT__H__ -#define __NR_TRANSPORT__H__ - -#define NR_PBCH_PDU_BITS 24 - -#endif /*__NR_TRANSPORT__H__*/ diff --git a/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h b/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h index 24b6303b9c..11d38cc113 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h +++ b/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h @@ -30,10 +30,15 @@ * \warning */ +#ifndef __NR_TRANSPORT__H__ +#define __NR_TRANSPORT__H__ + #include "PHY/defs_nr_common.h" #include "PHY/defs_gNB.h" #include "LAYER2/NR_MAC_gNB/mac_proto.h" +#define NR_PBCH_PDU_BITS 24 + /*! \fn int nr_generate_pss \brief Generation of the NR PSS @@ -307,3 +312,5 @@ int16_t find_nr_prach_ru(RU_t *ru,int frame,int slot, find_type_t type); void init_prach_list(PHY_VARS_gNB *gNB); void init_prach_ru_list(RU_t *ru); void free_nr_ru_prach_entry(RU_t *ru, int prach_id); + +#endif /*__NR_TRANSPORT__H__*/ diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c index 5c4df8ce40..c38deaff2d 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c @@ -30,7 +30,6 @@ */ #include "PHY/defs_nr_UE.h" #include "PHY/phy_extern_nr_ue.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" #include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "nr_transport_proto_ue.h" //#include "SCHED/defs.h" diff --git a/openair1/SCHED_NR/fapi_nr_l1.c b/openair1/SCHED_NR/fapi_nr_l1.c index a2d26765f1..40e4a56667 100644 --- a/openair1/SCHED_NR/fapi_nr_l1.c +++ b/openair1/SCHED_NR/fapi_nr_l1.c @@ -31,7 +31,6 @@ */ #include "fapi_nr_l1.h" #include "PHY/NR_TRANSPORT/nr_transport_proto.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" #include "PHY/NR_TRANSPORT/nr_dlsch.h" #include "PHY/NR_TRANSPORT/nr_dci.h" diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index 37d4e94972..e8b685a885 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -23,7 +23,6 @@ #include "PHY/defs_gNB.h" #include "sched_nr.h" #include "PHY/NR_REFSIG/dmrs_nr.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" #include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "PHY/NR_TRANSPORT/nr_dlsch.h" #include "PHY/NR_TRANSPORT/nr_ulsch.h" diff --git a/openair1/SIMULATION/NR_PHY/ulsim.c b/openair1/SIMULATION/NR_PHY/ulsim.c index 18a1ea6c92..eaff133adb 100644 --- a/openair1/SIMULATION/NR_PHY/ulsim.c +++ b/openair1/SIMULATION/NR_PHY/ulsim.c @@ -41,7 +41,6 @@ #include "PHY/NR_REFSIG/refsig_defs_ue.h" #include "PHY/NR_TRANSPORT/nr_dlsch.h" #include "PHY/NR_TRANSPORT/nr_sch_dmrs.h" -#include "PHY/NR_TRANSPORT/nr_transport.h" #include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "PHY/NR_TRANSPORT/nr_ulsch.h" #include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" From ec422f705056f2a4ca5c9366cd313a84da4eb649 Mon Sep 17 00:00:00 2001 From: cig Date: Mon, 13 Apr 2020 20:26:01 +0200 Subject: [PATCH 170/553] Introduced a delay after a completed sync before starting msg1 generation: - this was necessary because as soon as the gNB starts, it tries detecting the prach preambles and it mesaures the background noise. However, there is a delay of several dozens of frames before it considers the preables as detected. - the solution at the UE consists in avoiding sending preamble as soon as the UE syncs by introducing an offset, this keeps the power measurements low at gNB side as long as the preamble detection counter is under threshold --- openair1/PHY/NR_UE_ESTIMATION/nr_adjust_synch_ue.c | 3 +++ openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h | 1 + openair1/PHY/defs_nr_common.h | 6 +++++- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 11 +++++++++-- openair1/SIMULATION/NR_PHY/prachsim.c | 1 + openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 2 +- 6 files changed, 20 insertions(+), 4 deletions(-) diff --git a/openair1/PHY/NR_UE_ESTIMATION/nr_adjust_synch_ue.c b/openair1/PHY/NR_UE_ESTIMATION/nr_adjust_synch_ue.c index d140442523..b49443c03c 100644 --- a/openair1/PHY/NR_UE_ESTIMATION/nr_adjust_synch_ue.c +++ b/openair1/PHY/NR_UE_ESTIMATION/nr_adjust_synch_ue.c @@ -35,6 +35,7 @@ void nr_adjust_synch_ue(NR_DL_FRAME_PARMS *frame_parms, PHY_VARS_NR_UE *ue, module_id_t gNB_id, + uint8_t frame, uint8_t subframe, unsigned char clear, short coef) @@ -104,6 +105,8 @@ void nr_adjust_synch_ue(NR_DL_FRAME_PARMS *frame_parms, //mac_resynch(); //dl_phy_sync_success(ue->Mod_id,ue->proc.proc_rxtx[0].frame_rx,0,1);//ue->common_vars.eNb_id); ue->UE_mode[0] = PRACH; + ue->prach_resources[gNB_id]->sync_frame = frame; + ue->prach_resources[gNB_id]->init_msg1 = 0; } else { ue->UE_mode[0] = PUSCH; diff --git a/openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h b/openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h index 6326ed9446..1837664391 100644 --- a/openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h +++ b/openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h @@ -75,6 +75,7 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue, void nr_adjust_synch_ue(NR_DL_FRAME_PARMS *frame_parms, PHY_VARS_NR_UE *ue, module_id_t eNB_id, + uint8_t frame, uint8_t subframe, unsigned char clear, short coef); diff --git a/openair1/PHY/defs_nr_common.h b/openair1/PHY/defs_nr_common.h index 9caf3bc682..6531f582ac 100644 --- a/openair1/PHY/defs_nr_common.h +++ b/openair1/PHY/defs_nr_common.h @@ -221,8 +221,12 @@ typedef struct { uint16_t ra_RNTI; /// Pointer to Msg3 payload for UL-grant uint8_t *Msg3; - /// Flag for the Msg1 generation + /// Flag for the Msg1 generation: it is enabled every time it is nr prach slot uint8_t generate_nr_prach; + /// Frame of last completed synch + uint8_t sync_frame; + /// Flag to indicate that prach is ready to start: it is enabled with an initial delay after the sync + uint8_t init_msg1; } NR_PRACH_RESOURCES_t; typedef struct NR_DL_FRAME_PARMS NR_DL_FRAME_PARMS; diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index b7922993cf..ced577b16e 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -2482,8 +2482,11 @@ void nr_ue_pbch_procedures(uint8_t gNB_id, ue->pbch_vars[gNB_id]->pdu_errors_conseq = 0; // Switch to PRACH state if it is first PBCH after initial synch and no timing correction is performed - if (ue->UE_mode[gNB_id] == NOT_SYNCHED && ue->no_timing_correction == 1) + if (ue->UE_mode[gNB_id] == NOT_SYNCHED && ue->no_timing_correction == 1){ ue->UE_mode[gNB_id] = PRACH; + ue->prach_resources[gNB_id]->sync_frame = frame_rx; + ue->prach_resources[gNB_id]->init_msg1 = 0; + } #ifdef DEBUG_PHY_PROC uint16_t frame_tx; @@ -4079,6 +4082,7 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, nr_adjust_synch_ue(fp, ue, eNB_id, + frame_rx, nr_tti_rx, 0, 16384); @@ -4523,7 +4527,10 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t } } - if (ue->prach_resources[gNB_id] != NULL && prach_resources->generate_nr_prach == 1) { + if (!prach_resources->init_msg1 && (frame_tx > ue->prach_resources[gNB_id]->sync_frame + 150)) + prach_resources->init_msg1 = 1; + + if (ue->prach_resources[gNB_id] != NULL && prach_resources->generate_nr_prach == 1 && prach_resources->init_msg1) { ue->prach_cnt = 0; pathloss = get_nr_PL(mod_id, ue->CC_id, gNB_id); diff --git a/openair1/SIMULATION/NR_PHY/prachsim.c b/openair1/SIMULATION/NR_PHY/prachsim.c index 4c37e49fb2..014813aae5 100644 --- a/openair1/SIMULATION/NR_PHY/prachsim.c +++ b/openair1/SIMULATION/NR_PHY/prachsim.c @@ -501,6 +501,7 @@ int main(int argc, char **argv){ printf("raPreamble %d\n",preamble_tx); UE->prach_resources[0]->ra_PreambleIndex = preamble_tx; + UE->prach_resources[0]->init_msg1 = 1; // Configure channel bw = N_RB_UL*(180e3)*(1 << frame_parms->numerology_index); diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c index 75091d49e2..00eaa56855 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -353,7 +353,7 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, AssertFatal(CC_id == 0,"Transmission on secondary CCs is not supported yet\n"); - if (UE_mode == PRACH) { + if (UE_mode == PRACH && prach_resources->init_msg1) { LOG_D(MAC, "nr_ue_get_rach, RA_active value: %d", mac->RA_active); From 6f87d474b7433acd4cf02c5e2d4df3ea0d32ce7c Mon Sep 17 00:00:00 2001 From: cig Date: Tue, 14 Apr 2020 16:08:42 +0200 Subject: [PATCH 171/553] Fixed wrong printing in nr_process_timing_advance --- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index ced577b16e..cc1a2fe838 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -1302,7 +1302,7 @@ void nr_process_timing_advance(module_id_t Mod_id, uint8_t CC_id, uint8_t ta_com PHY_vars_UE_g[Mod_id][CC_id]->timing_advance += (ta_command - 31) * bw_scaling / factor_mu; - LOG_D(PHY, "[UE %d] Got timing advance command %u from MAC, new value is %u\n", Mod_id, ta_command, PHY_vars_UE_g[Mod_id][CC_id]->timing_advance); + LOG_D(PHY, "[UE %d] Got timing advance command %u from MAC, new value is %d\n", Mod_id, ta_command, PHY_vars_UE_g[Mod_id][CC_id]->timing_advance); } // WIP From 7f196b11f6b2a9e717667537534543aa73e3d889 Mon Sep 17 00:00:00 2001 From: Cedric Roux Date: Wed, 15 Apr 2020 17:06:59 +0200 Subject: [PATCH 172/553] 5g nsa: hacks for eurecom testing --- openair2/RRC/LTE/rrc_eNB.c | 4 +-- openair2/RRC/NR/rrc_gNB_reconfig.c | 44 ++++++++++++++++++++---------- 2 files changed, 31 insertions(+), 17 deletions(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index c8df01722f..5efa14f796 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -3209,7 +3209,7 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t if (MeasObj2 == NULL) exit(1); MeasObj2->measObjectId = 2; MeasObj2->measObject.present = LTE_MeasObjectToAddMod__measObject_PR_measObjectNR_r15; - MeasObj2->measObject.choice.measObjectNR_r15.carrierFreq_r15 = 642256; //634000; //(634000 = 3.51GHz) (640000 = 3.6GHz) (641272 = 3619.08MHz = 3600 + 30/1000*106*12/2) (642256 is for 3.6GHz and absoluteFrequencySSB = 642016) + MeasObj2->measObject.choice.measObjectNR_r15.carrierFreq_r15 =641272; //634000; //(634000 = 3.51GHz) (640000 = 3.6GHz) (641272 = 3619.08MHz = 3600 + 30/1000*106*12/2) (642256 is for 3.6GHz and absoluteFrequencySSB = 642016) MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.periodicityAndOffset_r15.present = LTE_MTC_SSB_NR_r15__periodicityAndOffset_r15_PR_sf20_r15; MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.periodicityAndOffset_r15.choice.sf20_r15 = 0; MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.ssb_Duration_r15 = LTE_MTC_SSB_NR_r15__ssb_Duration_r15_sf4; @@ -3352,7 +3352,7 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.present = LTE_ReportConfigInterRAT__triggerType_PR_event; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.present = LTE_ReportConfigInterRAT__triggerType__event__eventId_PR_eventB1_NR_r15; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.b1_ThresholdNR_r15.present = LTE_ThresholdNR_r15_PR_nr_RSRP_r15; - ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.b1_ThresholdNR_r15.choice.nr_RSRP_r15 = 46; + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.b1_ThresholdNR_r15.choice.nr_RSRP_r15 = 0; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.reportOnLeave_r15 = FALSE; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.hysteresis = 2; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.timeToTrigger = LTE_TimeToTrigger_ms80; diff --git a/openair2/RRC/NR/rrc_gNB_reconfig.c b/openair2/RRC/NR/rrc_gNB_reconfig.c index 5418085108..f732529ed7 100644 --- a/openair2/RRC/NR/rrc_gNB_reconfig.c +++ b/openair2/RRC/NR/rrc_gNB_reconfig.c @@ -210,6 +210,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition)); *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0; +#if 0 secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList)); NR_TCI_State_t*tci0=calloc(1,sizeof(*tci0)); @@ -371,6 +372,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco tci15->qcl_Type1.referenceSignal.choice.ssb = 7; tci15->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci15); +#endif secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; @@ -399,6 +401,8 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->sps_Config = NULL; //calloc(1,sizeof(struct NR_SetupRelease_SPS_Config)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig = NULL; +#if 0 secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig)); secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->present = NR_SetupRelease_RadioLinkMonitoringConfig_PR_setup; @@ -409,6 +413,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = NR_RadioLinkMonitoringConfig__beamFailureInstanceMaxCount_n3; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer)); *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = NR_RadioLinkMonitoringConfig__beamFailureDetectionTimer_pbfd2; +#endif secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToReleaseList= NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList)); @@ -578,6 +583,8 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition)); *bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList=NULL; +#if 0 bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList=calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList)); NR_TCI_State_t*tcid0=calloc(1,sizeof(*tcid0)); @@ -739,6 +746,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco tcid15->qcl_Type1.referenceSignal.choice.ssb = 7; tcid15->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid15); +#endif bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; @@ -793,6 +801,8 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco bwp->bwp_Dedicated->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL; bwp->bwp_Dedicated->sps_Config = NULL; //calloc(1,sizeof(struct NR_SetupRelease_SPS_Config)); + bwp->bwp_Dedicated->radioLinkMonitoringConfig = NULL; +#if 0 bwp->bwp_Dedicated->radioLinkMonitoringConfig = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig)); bwp->bwp_Dedicated->radioLinkMonitoringConfig->present = NR_SetupRelease_RadioLinkMonitoringConfig_PR_setup; @@ -803,6 +813,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco *bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = NR_RadioLinkMonitoringConfig__beamFailureInstanceMaxCount_n3; bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer)); *bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = NR_RadioLinkMonitoringConfig__beamFailureDetectionTimer_pbfd2; +#endif ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list,bwp); @@ -811,6 +822,8 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco *secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id=1; secondaryCellGroup->spCellConfig->spCellConfigDedicated->bwp_InactivityTimer = NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->defaultDownlinkBWP_Id = NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->defaultDownlinkBWP_Id = calloc(1, sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->defaultDownlinkBWP_Id)); + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->defaultDownlinkBWP_Id = 1; secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig)); NR_BWP_UplinkDedicated_t *initialUplinkBWP = calloc(1,sizeof(*initialUplinkBWP)); @@ -1118,12 +1131,13 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco *pdsch_servingcellconfig->ext1->maxMIMO_Layers = 2; pdsch_servingcellconfig->ext1->processingType2Enabled = NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->present = NR_SetupRelease_CSI_MeasConfig_PR_setup; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig=NULL; + //secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig)); + //secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->present = NR_SetupRelease_CSI_MeasConfig_PR_setup; NR_CSI_MeasConfig_t *csi_MeasConfig = calloc(1,sizeof(*csi_MeasConfig)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup = csi_MeasConfig; +// secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup = csi_MeasConfig; csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList = calloc(1,sizeof(*csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList)); NR_NZP_CSI_RS_Resource_t *nzpres0 = calloc(1,sizeof(*nzpres0)); @@ -1663,7 +1677,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco imres0->csi_IM_ResourceElementPattern->choice.pattern1->symbolLocation_p1=7; imres0->freqBand=calloc(1,sizeof(*imres0->freqBand)); imres0->freqBand->startingRB=0; - imres0->freqBand->nrofRBs=276; + imres0->freqBand->nrofRBs=106; imres0->periodicityAndOffset=calloc(1,sizeof(*imres0->periodicityAndOffset)); imres0->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots320; imres0->periodicityAndOffset->choice.slots320 = 2; @@ -1737,7 +1751,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires11->csi_RS_ResourceSetList.choice.csi_IM_ResourceSetList->list,csires110); csires11->bwp_Id = 1; csires11->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires11); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires11); NR_CSI_ResourceConfig_t *csires10 = calloc(1,sizeof(*csires10)); csires10->csi_ResourceConfigId=10; @@ -1750,7 +1764,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires100); csires10->bwp_Id = 1; csires10->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires10); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires10); NR_CSI_ResourceConfig_t *csires2 = calloc(1,sizeof(*csires2)); csires2->csi_ResourceConfigId=2; @@ -1763,7 +1777,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires20); csires2->bwp_Id = 1; csires2->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires2); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires2); NR_CSI_ResourceConfig_t *csires3 = calloc(1,sizeof(*csires3)); csires3->csi_ResourceConfigId=3; @@ -1776,7 +1790,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires30); csires3->bwp_Id = 1; csires3->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires3); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires3); NR_CSI_ResourceConfig_t *csires4 = calloc(1,sizeof(*csires4)); csires4->csi_ResourceConfigId=4; @@ -1789,7 +1803,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires40); csires4->bwp_Id = 1; csires4->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires4); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires4); NR_CSI_ResourceConfig_t *csires5 = calloc(1,sizeof(*csires5)); csires5->csi_ResourceConfigId=5; @@ -1802,7 +1816,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires50); csires5->bwp_Id = 1; csires5->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires5); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires5); NR_CSI_ResourceConfig_t *csires6 = calloc(1,sizeof(*csires6)); csires6->csi_ResourceConfigId=6; @@ -1815,7 +1829,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires60); csires6->bwp_Id = 1; csires6->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires6); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires6); NR_CSI_ResourceConfig_t *csires7 = calloc(1,sizeof(*csires7)); csires7->csi_ResourceConfigId=7; @@ -1828,7 +1842,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires70); csires7->bwp_Id = 1; csires7->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires7); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires7); NR_CSI_ResourceConfig_t *csires8 = calloc(1,sizeof(*csires8)); csires8->csi_ResourceConfigId=8; @@ -1841,7 +1855,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires80); csires8->bwp_Id = 1; csires8->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires8); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires8); NR_CSI_ResourceConfig_t *csires9 = calloc(1,sizeof(*csires9)); csires9->csi_ResourceConfigId=9; @@ -1854,7 +1868,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ASN_SEQUENCE_ADD(&csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires90); csires9->bwp_Id = 1; csires9->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires9); + //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires9); csi_MeasConfig->csi_ReportConfigToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_ReportConfigToAddModList)); csi_MeasConfig->csi_ReportConfigToReleaseList = NULL; @@ -2012,7 +2026,7 @@ void fill_default_reconfig(NR_ServingCellConfigCommon_t *servingcellconfigcommon // radioBearerConfig reconfig->radioBearerConfig=NULL; // secondaryCellGroup - fill_default_secondaryCellGroup(servingcellconfigcommon,secondaryCellGroup,0,0,n_physical_antenna_ports,initial_csi_index); + fill_default_secondaryCellGroup(servingcellconfigcommon,secondaryCellGroup,1,1,n_physical_antenna_ports,initial_csi_index); xer_fprint(stdout, &asn_DEF_NR_CellGroupConfig, (const void*)secondaryCellGroup); char scg_buffer[1024]; From fd237596cf0ea8bea1ff8e6b23a71eab90597962 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Thu, 16 Apr 2020 12:07:00 +0200 Subject: [PATCH 173/553] uncommenting in cce function --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index d8770a51e7..2b2c8f6491 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -182,8 +182,8 @@ int allocate_nr_CCEs(gNB_MAC_INST *nr_mac, } int first_cce = aggregation * (( Y + (m*N_cce)/(aggregation*M_s_max) + n_CI ) % CEILIDIV(N_cce,aggregation)); - // for (int i=0;i Date: Thu, 16 Apr 2020 12:54:00 +0200 Subject: [PATCH 174/553] adding conf file to test with phone --- .../GENERIC-LTE-EPC/CONF/testing_enb.conf | 281 +++++++++++++++++ .../GENERIC-LTE-EPC/CONF/testing_gnb.conf | 293 ++++++++++++++++++ 2 files changed, 574 insertions(+) create mode 100644 targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_enb.conf create mode 100644 targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_gnb.conf diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_enb.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_enb.conf new file mode 100644 index 0000000000..58e4e86873 --- /dev/null +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_enb.conf @@ -0,0 +1,281 @@ +Active_eNBs = ( "eNB-Eurecom-LTEBox"); +# Asn1_verbosity, choice in: none, info, annoying +Asn1_verbosity = "none"; + +eNBs = +( + { + # real_time choice in {hard, rt-preempt, no} + real_time = "no"; + ////////// Identification parameters: + eNB_ID = 0xe01; + + cell_type = "CELL_MACRO_ENB"; + + eNB_name = "eNB-Eurecom-LTEBox"; + + // Tracking area code, 0x0000 and 0xfffe are reserved values + tracking_area_code = 1; + plmn_list = ( + { mcc = 222; mnc = 01; mnc_length = 2; } + ); + + tr_s_preference = "local_mac" + + ////////// Physical parameters: + + component_carriers = ( + { + node_function = "eNodeB_3GPP"; + node_timing = "synch_to_ext_device"; + node_synch_ref = 0; + nb_antenna_ports = 1; + ue_TransmissionMode = 1; + frame_type = "FDD"; + tdd_config = 3; + tdd_config_s = 0; + prefix_type = "NORMAL"; + eutra_band = 7; + downlink_frequency = 2680000000L; //2655000000L; + uplink_frequency_offset = -120000000; + + Nid_cell = 0; + N_RB_DL = 25; //100; + Nid_cell_mbsfn = 0; + nb_antennas_tx = 1; + nb_antennas_rx = 1; + prach_root = 0; + tx_gain = 90; + rx_gain = 115; + pbch_repetition = "FALSE"; + prach_config_index = 0; + prach_high_speed = "DISABLE"; + prach_zero_correlation = 1; + prach_freq_offset = 2; + pucch_delta_shift = 1; + pucch_nRB_CQI = 0; + pucch_nCS_AN = 0; + pucch_n1_AN = 0; + pdsch_referenceSignalPower = -29; + pdsch_p_b = 0; + pusch_n_SB = 1; + pusch_enable64QAM = "DISABLE"; + pusch_hoppingMode = "interSubFrame"; + pusch_hoppingOffset = 0; + pusch_groupHoppingEnabled = "ENABLE"; + pusch_groupAssignment = 0; + pusch_sequenceHoppingEnabled = "DISABLE"; + pusch_nDMRS1 = 1; + phich_duration = "NORMAL"; + phich_resource = "ONESIXTH"; + srs_enable = "DISABLE"; + /* srs_BandwidthConfig =; + srs_SubframeConfig =; + srs_ackNackST =; + srs_MaxUpPts =;*/ + + pusch_p0_Nominal = -96; + pusch_alpha = "AL1"; + pucch_p0_Nominal = -96; + msg3_delta_Preamble = 6; + pucch_deltaF_Format1 = "deltaF2"; + pucch_deltaF_Format1b = "deltaF3"; + pucch_deltaF_Format2 = "deltaF0"; + pucch_deltaF_Format2a = "deltaF0"; + pucch_deltaF_Format2b = "deltaF0"; + + rach_numberOfRA_Preambles = 64; + rach_preamblesGroupAConfig = "DISABLE"; +/* + rach_sizeOfRA_PreamblesGroupA = ; + rach_messageSizeGroupA = ; + rach_messagePowerOffsetGroupB = ; +*/ + rach_powerRampingStep = 4; + rach_preambleInitialReceivedTargetPower = -108; + rach_preambleTransMax = 10; + rach_raResponseWindowSize = 10; + rach_macContentionResolutionTimer = 48; + rach_maxHARQ_Msg3Tx = 4; + + pcch_default_PagingCycle = 128; + pcch_nB = "oneT"; + bcch_modificationPeriodCoeff = 2; + ue_TimersAndConstants_t300 = 1000; + ue_TimersAndConstants_t301 = 1000; + ue_TimersAndConstants_t310 = 1000; + ue_TimersAndConstants_t311 = 10000; + ue_TimersAndConstants_n310 = 20; + ue_TimersAndConstants_n311 = 1; + + //Parameters for SIB18 + rxPool_sc_CP_Len = "normal"; + rxPool_sc_Period = "sf40"; + rxPool_data_CP_Len = "normal"; + rxPool_ResourceConfig_prb_Num = 20; + rxPool_ResourceConfig_prb_Start = 5; + rxPool_ResourceConfig_prb_End = 44; + rxPool_ResourceConfig_offsetIndicator_present = "prSmall"; + rxPool_ResourceConfig_offsetIndicator_choice = 0; + rxPool_ResourceConfig_subframeBitmap_present = "prBs40"; + rxPool_ResourceConfig_subframeBitmap_choice_bs_buf = "00000000000000000000"; + rxPool_ResourceConfig_subframeBitmap_choice_bs_size = 5; + rxPool_ResourceConfig_subframeBitmap_choice_bs_bits_unused = 0; +/* rxPool_dataHoppingConfig_hoppingParameter = 0; + rxPool_dataHoppingConfig_numSubbands = "ns1"; + rxPool_dataHoppingConfig_rbOffset = 0; + rxPool_commTxResourceUC-ReqAllowed = "TRUE"; +*/ + // Parameters for SIB19 + discRxPool_cp_Len = "normal" + discRxPool_discPeriod = "rf32" + discRxPool_numRetx = 1; + discRxPool_numRepetition = 2; + discRxPool_ResourceConfig_prb_Num = 5; + discRxPool_ResourceConfig_prb_Start = 3; + discRxPool_ResourceConfig_prb_End = 21; + discRxPool_ResourceConfig_offsetIndicator_present = "prSmall"; + discRxPool_ResourceConfig_offsetIndicator_choice = 0; + discRxPool_ResourceConfig_subframeBitmap_present = "prBs40"; + discRxPool_ResourceConfig_subframeBitmap_choice_bs_buf = "f0ffffffff"; + discRxPool_ResourceConfig_subframeBitmap_choice_bs_size = 5; + discRxPool_ResourceConfig_subframeBitmap_choice_bs_bits_unused = 0; + + } + ); + + srb1_parameters : + { + # timer_poll_retransmit = (ms) [5, 10, 15, 20,... 250, 300, 350, ... 500] + timer_poll_retransmit = 80; + + # timer_reordering = (ms) [0,5, ... 100, 110, 120, ... ,200] + timer_reordering = 35; + + # timer_reordering = (ms) [0,5, ... 250, 300, 350, ... ,500] + timer_status_prohibit = 0; + + # poll_pdu = [4, 8, 16, 32 , 64, 128, 256, infinity(>10000)] + poll_pdu = 4; + + # poll_byte = (kB) [25,50,75,100,125,250,375,500,750,1000,1250,1500,2000,3000,infinity(>10000)] + poll_byte = 99999; + + # max_retx_threshold = [1, 2, 3, 4 , 6, 8, 16, 32] + max_retx_threshold = 4; + } + + # ------- SCTP definitions + SCTP : + { + # Number of streams to use in input/output + SCTP_INSTREAMS = 2; + SCTP_OUTSTREAMS = 2; + }; + + enable_measurement_reports = "yes"; + + ////////// MME parameters: + mme_ip_address = ( { ipv4 = "192.168.18.99"; + ipv6 = "192:168:30::17"; + active = "yes"; + preference = "ipv4"; + } + ); + + ///X2 + enable_x2 = "yes"; + t_reloc_prep = 1000; /* unit: millisecond */ + tx2_reloc_overall = 2000; /* unit: millisecond */ + + NETWORK_INTERFACES : + { + ENB_INTERFACE_NAME_FOR_S1_MME = "eth1"; + ENB_IPV4_ADDRESS_FOR_S1_MME = "192.168.18.199/24"; + + ENB_INTERFACE_NAME_FOR_S1U = "eth1"; + ENB_IPV4_ADDRESS_FOR_S1U = "192.168.18.199/24"; + ENB_PORT_FOR_S1U = 2152; # Spec 2152 + + ENB_IPV4_ADDRESS_FOR_X2C = "192.168.18.199/24"; + ENB_PORT_FOR_X2C = 36422; # Spec 36422 + }; + + log_config : + { + global_log_level ="info"; + global_log_verbosity ="high"; + hw_log_level ="info"; + hw_log_verbosity ="medium"; + phy_log_level ="info"; + phy_log_verbosity ="medium"; + mac_log_level ="info"; + mac_log_verbosity ="high"; + rlc_log_level ="debug"; + rlc_log_verbosity ="high"; + pdcp_log_level ="info"; + pdcp_log_verbosity ="high"; + rrc_log_level ="info"; + rrc_log_verbosity ="medium"; + }; + + } +); + +MACRLCs = ( + { + num_cc = 1; + tr_s_preference = "local_L1"; + tr_n_preference = "local_RRC"; + phy_test_mode = 0; + puSch10xSnr = 160; + puCch10xSnr = 160; + } +); + +THREAD_STRUCT = ( + { + parallel_config = "PARALLEL_RU_L1_TRX_SPLITaaaaaa"; + worker_config = "ENABLE"; + } +); + +L1s = ( + { + num_cc = 1; + tr_n_preference = "local_mac"; + } +); + +RUs = ( + { + local_rf = "yes" + nb_tx = 1 + nb_rx = 1 + att_tx = 0 + att_rx = 0; + bands = [7]; + max_pdschReferenceSignalPower = -27; + max_rxgain = 118; + eNB_instances = [0]; + + } +); + + log_config : + { + global_log_level ="info"; + global_log_verbosity ="high"; + hw_log_level ="info"; + hw_log_verbosity ="medium"; + phy_log_level ="info"; + phy_log_verbosity ="medium"; + mac_log_level ="info"; + mac_log_verbosity ="high"; + rlc_log_level ="info"; + rlc_log_verbosity ="high"; + pdcp_log_level ="info"; + pdcp_log_verbosity ="high"; + rrc_log_level ="info"; + rrc_log_verbosity ="medium"; + }; diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_gnb.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_gnb.conf new file mode 100644 index 0000000000..db8aef33ba --- /dev/null +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_gnb.conf @@ -0,0 +1,293 @@ +Active_gNBs = ( "gNB-Eurecom-5GNRBox"); +# Asn1_verbosity, choice in: none, info, annoying +Asn1_verbosity = "none"; + +gNBs = +( + { + ////////// Identification parameters: + gNB_ID = 0xe00; + + cell_type = "CELL_MACRO_GNB"; + + gNB_name = "gNB-Eurecom-5GNRBox"; + + // Tracking area code, 0x0000 and 0xfffe are reserved values + tracking_area_code = 1; + + plmn_list = ({mcc = 222; mnc = 01; mnc_length = 2;}); + + tr_s_preference = "local_mac" + + ////////// Physical parameters: + + ssb_SubcarrierOffset = 31; //0; + pdsch_AntennaPorts = 1; + + servingCellConfigCommon = ( + { + #spCellConfigCommon + + physCellId = 0; + +# downlinkConfigCommon + #frequencyInfoDL + # this is 3600 MHz + 84 PRBs@30kHz SCS (same as initial BWP) + absoluteFrequencySSB = 641272; //641032; #641968; 641968=start of ssb at 3600MHz + 82 RBs 641032=center of SSB at center of cell + dl_frequencyBand = 78; + # this is 3600 MHz + dl_absoluteFrequencyPointA = 640000; + #scs-SpecificCarrierList + dl_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + dl_subcarrierSpacing = 1; + dl_carrierBandwidth = 106; + #initialDownlinkBWP + #genericParameters + # this is RBstart=84,L=13 (275*(L-1))+RBstart + initialDLBWPlocationAndBandwidth = 6366; //28875; //6366; #6407; #3384; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialDLBWPsubcarrierSpacing = 1; + #pdcch-ConfigCommon + initialDLBWPcontrolResourceSetZero = 0; + initialDLBWPsearchSpaceZero = 0; + #pdsch-ConfigCommon + #pdschTimeDomainAllocationList (up to 16 entries) + initialDLBWPk0_0 = 0; + #initialULBWPmappingType + #0=typeA,1=typeB + initialDLBWPmappingType_0 = 0; + #this is SS=1,L=13 + initialDLBWPstartSymbolAndLength_0 = 40; + + initialDLBWPk0_1 = 0; + initialDLBWPmappingType_1 = 0; + #this is SS=2,L=12 + initialDLBWPstartSymbolAndLength_1 = 53; + + initialDLBWPk0_2 = 0; + initialDLBWPmappingType_2 = 0; + #this is SS=1,L=12 + initialDLBWPstartSymbolAndLength_2 = 54; + + initialDLBWPk0_3 = 0; + initialDLBWPmappingType_3 = 0; + #this is SS=1,L=4 //5 (4 is for 43, 5 is for 57) + initialDLBWPstartSymbolAndLength_3 = 57; //43; //57; + #uplinkConfigCommon + #frequencyInfoUL + ul_frequencyBand = 78; + #scs-SpecificCarrierList + ul_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + ul_subcarrierSpacing = 1; + ul_carrierBandwidth = 106; + pMax = 20; + #initialUplinkBWP + #genericParameters + initialULBWPlocationAndBandwidth = 6366; //28875; //6366; #6407; #3384; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialULBWPsubcarrierSpacing = 1; + #rach-ConfigCommon + #rach-ConfigGeneric + prach_ConfigurationIndex = 98; +#prach_msg1_FDM +#0 = one, 1=two, 2=four, 3=eight + prach_msg1_FDM = 0; + prach_msg1_FrequencyStart = 0; + zeroCorrelationZoneConfig = 13; + preambleReceivedTargetPower = -118; +#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200) + preambleTransMax = 6; +#powerRampingStep +# 0=dB0,1=dB2,2=dB4,3=dB6 + powerRampingStep = 1; +#ra_ReponseWindow +#1,2,4,8,10,20,40,80 + ra_ResponseWindow = 5; +#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR +#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4; +#oneHalf (0..15) 4,8,12,16,...60,64 + ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 14; //15; +#ra_ContentionResolutionTimer +#(0..7) 8,16,24,32,40,48,56,64 + ra_ContentionResolutionTimer = 7; + rsrp_ThresholdSSB = 19; +#prach-RootSequenceIndex_PR +#1 = 839, 2 = 139 + prach_RootSequenceIndex_PR = 2; + prach_RootSequenceIndex = 1; + # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex + # + msg1_SubcarrierSpacing = 1, + +# restrictedSetConfig +# 0=unrestricted, 1=restricted type A, 2=restricted type B + restrictedSetConfig = 0, + # pusch-ConfigCommon (up to 16 elements) + initialULBWPk2_0 = 2; + initialULBWPmappingType_0 = 1 + # this is SS=0 L=11 + initialULBWPstartSymbolAndLength_0 = 55; + + initialULBWPk2_1 = 2; + initialULBWPmappingType_1 = 1; + # this is SS=0 L=12 + initialULBWPstartSymbolAndLength_1 = 69; + + initialULBWPk2_2 = 7; + initialULBWPmappingType_2 = 1; + # this is SS=10 L=4 + initialULBWPstartSymbolAndLength_2 = 52; + + msg3_DeltaPreamble = 1; + p0_NominalWithGrant =-90; + +# pucch-ConfigCommon setup : +# pucchGroupHopping +# 0 = neither, 1= group hopping, 2=sequence hopping + pucchGroupHopping = 0; + hoppingId = 40; + p0_nominal = -90; +# ssb_PositionsInBurs_BitmapPR +# 1=short, 2=medium, 3=long + ssb_PositionsInBurst_PR = 2; + ssb_PositionsInBurst_Bitmap = 1; #0x80; + +# ssb_periodicityServingCell +# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1 + ssb_periodicityServingCell = 2; + +# dmrs_TypeA_position +# 0 = pos2, 1 = pos3 + dmrs_TypeA_Position = 0; + +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + subcarrierSpacing = 1; + + + #tdd-UL-DL-ConfigurationCommon +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + referenceSubcarrierSpacing = 1; + # pattern1 + # dl_UL_TransmissionPeriodicity + # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10 + dl_UL_TransmissionPeriodicity = 6; + nrofDownlinkSlots = 7; //8; //7; + nrofDownlinkSymbols = 6; //0; //6; + nrofUplinkSlots = 2; + nrofUplinkSymbols = 4; //0; //4; + + ssPBCH_BlockPower = 10; + } + + ); + + + # ------- SCTP definitions + SCTP : + { + # Number of streams to use in input/output + SCTP_INSTREAMS = 2; + SCTP_OUTSTREAMS = 2; + }; + + + ////////// MME parameters: + mme_ip_address = ( { ipv4 = "192.168.18.99"; + ipv6 = "192:168:30::17"; + active = "yes"; + preference = "ipv4"; + } + ); + + ///X2 + enable_x2 = "yes"; + t_reloc_prep = 1000; /* unit: millisecond */ + tx2_reloc_overall = 2000; /* unit: millisecond */ + target_enb_x2_ip_address = ( + { ipv4 = "192.168.18.199"; + ipv6 = "192:168:30::17"; + preference = "ipv4"; + } + ); + + NETWORK_INTERFACES : + { + + GNB_INTERFACE_NAME_FOR_S1_MME = "eth0"; + GNB_IPV4_ADDRESS_FOR_S1_MME = "192.168.18.198/24"; + GNB_INTERFACE_NAME_FOR_S1U = "eth0"; + GNB_IPV4_ADDRESS_FOR_S1U = "192.168.18.198/24"; + GNB_PORT_FOR_S1U = 2152; # Spec 2152 + GNB_IPV4_ADDRESS_FOR_X2C = "192.168.18.198/24"; + GNB_PORT_FOR_X2C = 36422; # Spec 36422 + }; + } +); + +MACRLCs = ( + { + num_cc = 1; + tr_s_preference = "local_L1"; + tr_n_preference = "local_RRC"; + } +); + +L1s = ( + { + num_cc = 1; + tr_n_preference = "local_mac"; + } +); + +RUs = ( + { + local_rf = "yes" + nb_tx = 1 + nb_rx = 1 + att_tx = 0 + att_rx = 0; + bands = [7]; + max_pdschReferenceSignalPower = -27; + max_rxgain = 114; + eNB_instances = [0]; + clock_src = "internal"; + } +); + +THREAD_STRUCT = ( + { + #three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT" + //parallel_config = "PARALLEL_RU_L1_TRX_SPLIT"; + parallel_config = "PARALLEL_SINGLE_THREAD"; + #two option for worker "WORKER_DISABLE" or "WORKER_ENABLE" + worker_config = "WORKER_ENABLE"; + } +); + + log_config : + { + global_log_level ="info"; + global_log_verbosity ="medium"; + hw_log_level ="info"; + hw_log_verbosity ="medium"; + phy_log_level ="info"; + phy_log_verbosity ="medium"; + mac_log_level ="info"; + mac_log_verbosity ="high"; + rlc_log_level ="info"; + rlc_log_verbosity ="medium"; + pdcp_log_level ="info"; + pdcp_log_verbosity ="medium"; + rrc_log_level ="info"; + rrc_log_verbosity ="medium"; + }; + From c4e284a3e10819af572908a5d33c30b53f09520c Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Thu, 16 Apr 2020 15:54:27 +0200 Subject: [PATCH 175/553] fix in CCEs function --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 7 +-- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 53 +++++++++++-------- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 26 ++++----- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 14 ++--- 4 files changed, 57 insertions(+), 43 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index 55998e1c1b..5e8282b597 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -366,7 +366,8 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, uint64_t *ulsch_in_slot_bitmap=NULL; NR_sched_pucch *pucch_sched = (NR_sched_pucch*) malloc(sizeof(NR_sched_pucch)); - if (get_softmodem_params()->phy_test) UE_id=0; + UE_id=0; + int bwp_id = 1; gNB_MAC_INST *gNB = RC.nrmac[module_idP]; NR_UE_list_t *UE_list = &gNB->UE_list; @@ -407,8 +408,8 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, // Check if there are downlink symbols in the slot, if (is_nr_DL_slot(cc->ServingCellConfigCommon,slot_txP)) { - - memset(RC.nrmac[module_idP]->cce_list[1][0],0,MAX_NUM_CCE*sizeof(int)); + memset(RC.nrmac[module_idP]->cce_list[bwp_id][0],0,MAX_NUM_CCE*sizeof(int)); // coreset0 + memset(RC.nrmac[module_idP]->cce_list[bwp_id][1],0,MAX_NUM_CCE*sizeof(int)); // coresetid 1 for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { //mbsfn_status[CC_id] = 0; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index a158635848..834feac62c 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -410,14 +410,18 @@ int configure_fapi_dl_pdu(int Mod_idP, } AssertFatal(found==1,"Couldn't find an adequate searchspace\n"); - nr_configure_pdcch(nr_mac, - pdcch_pdu_rel15, - UE_list->rnti[UE_id], - 1, // ue-specific - ss, - scc, - bwp); - + int ret = nr_configure_pdcch(nr_mac, + pdcch_pdu_rel15, + UE_list->rnti[UE_id], + 1, // ue-specific + ss, + scc, + bwp); + if (ret < 0) { + LOG_I(MAC,"CCE list not empty, couldn't schedule PDSCH\n"); + return (0); + } + int dci_formats[2]; int rnti_types[2]; @@ -569,6 +573,9 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, dlsch_config!=NULL ? dlsch_config->mcsIndex : NULL, dlsch_config!=NULL ? &dlsch_config->rbSize : NULL, dlsch_config!=NULL ? &dlsch_config->rbStart : NULL); + + if (TBS_bytes == 0) + return; //The --NOS1 use case currently schedules DLSCH transmissions only when there is IP traffic arriving //through the LTE stack @@ -866,19 +873,23 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, rnti_types[0] = NR_RNTI_C; LOG_D(MAC,"Configuring ULDCI/PDCCH in %d.%d\n", frameP,slotP); - nr_configure_pdcch(nr_mac, - pdcch_pdu_rel15, - UE_list->rnti[UE_id], - 1, // ue-specific, - ss, - scc, - bwp); - - dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET]; + int ret = nr_configure_pdcch(nr_mac, + pdcch_pdu_rel15, + UE_list->rnti[UE_id], + 1, // ue-specific, + ss, + scc, + bwp); - config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); - - fill_dci_pdu_rel15(secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types,pusch_pdu->bwp_size,bwp_id); - + if (ret < 0) { + LOG_I(MAC,"CCE list not empty, couldn't schedule PUSCH\n"); + UL_tti_req->n_pdus-=1; + return; + } + else { + dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET]; + config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); + fill_dci_pdu_rel15(secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types,pusch_pdu->bwp_size,bwp_id); + } } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 2b2c8f6491..146b3278b0 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -131,7 +131,7 @@ static inline uint8_t get_max_cces(uint8_t scs) { int allocate_nr_CCEs(gNB_MAC_INST *nr_mac, int bwp_id, - int coreset_id, + int list_id, int aggregation, int search_space, // 0 common, 1 ue-specific int UE_id, @@ -152,15 +152,15 @@ int allocate_nr_CCEs(gNB_MAC_INST *nr_mac, bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; if (search_space == 1) { - coreset = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[coreset_id]; + coreset = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[list_id]; } else { coreset = bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet; } + int coreset_id = coreset->controlResourceSetId; int *cce_list = nr_mac->cce_list[bwp_id][coreset_id]; - int n_rb=0; for (int i=0;i<6;i++) for (int j=0;j<8;j++) { @@ -409,16 +409,16 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, } -void nr_configure_pdcch(gNB_MAC_INST *nr_mac, - nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, - uint16_t rnti, - int ss_type, - NR_SearchSpace_t *ss, - NR_ServingCellConfigCommon_t *scc, - NR_BWP_Downlink_t *bwp){ +int nr_configure_pdcch(gNB_MAC_INST *nr_mac, + nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, + uint16_t rnti, + int ss_type, + NR_SearchSpace_t *ss, + NR_ServingCellConfigCommon_t *scc, + NR_BWP_Downlink_t *bwp){ int CCEIndex = -1; - int cid; + int cid = 0; NR_ControlResourceSet_t *coreset = NULL; if (bwp) { // This is not the InitialBWP @@ -524,7 +524,8 @@ void nr_configure_pdcch(gNB_MAC_INST *nr_mac, 0, // UE-id 0); // m - AssertFatal(CCEIndex>=0,"CCEIndex is negative \n"); + if (CCEIndex<0) + return (CCEIndex); pdcch_pdu->dci_pdu.AggregationLevel[pdcch_pdu->numDlDci] = aggregation_level; pdcch_pdu->dci_pdu.CceIndex[pdcch_pdu->numDlDci] = CCEIndex; @@ -534,6 +535,7 @@ void nr_configure_pdcch(gNB_MAC_INST *nr_mac, pdcch_pdu->dci_pdu.powerControlOffsetSS[pdcch_pdu->numDlDci]=1; pdcch_pdu->numDlDci++; + return (0); } else { // this is for InitialBWP AssertFatal(1==0,"Fill in InitialBWP PDCCH configuration\n"); diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index d22edb1fd0..cc0254cc3a 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -195,13 +195,13 @@ void find_search_space(int ss_type, NR_BWP_Downlink_t *bwp, NR_SearchSpace_t *ss); -void nr_configure_pdcch(gNB_MAC_INST *nr_mac, - nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, - uint16_t rnti, - int ss_type, - NR_SearchSpace_t *ss, - NR_ServingCellConfigCommon_t *scc, - NR_BWP_Downlink_t *bwp); +int nr_configure_pdcch(gNB_MAC_INST *nr_mac, + nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, + uint16_t rnti, + int ss_type, + NR_SearchSpace_t *ss, + NR_ServingCellConfigCommon_t *scc, + NR_BWP_Downlink_t *bwp); void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, From ddf4ca87d2d37725331107dbbd0ccb4f9c7c0595 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 17 Apr 2020 19:07:47 +0200 Subject: [PATCH 176/553] [gNB] taking into account preamble set at RRC and finalization of RA procedures --- openair2/LAYER2/NR_MAC_gNB/config.c | 6 +++++ openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 26 +++++++++++++++---- .../LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c | 15 +++++++++++ openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 8 ++++++ 4 files changed, 50 insertions(+), 5 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/config.c b/openair2/LAYER2/NR_MAC_gNB/config.c index af75e6afff..1e5a6bed29 100644 --- a/openair2/LAYER2/NR_MAC_gNB/config.c +++ b/openair2/LAYER2/NR_MAC_gNB/config.c @@ -374,6 +374,12 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP, if (add_ue == 1) { UE_id = add_new_nr_ue(Mod_idP,rnti); UE_list->secondaryCellGroup[UE_id] = secondaryCellGroup; + uint8_t num_preamble = secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->resources.choice.ssb->ssb_ResourceList.list.count; + UE_list->preambles[UE_id].num_preambles = num_preamble; + UE_list->preambles[UE_id].preamble_list = (uint8_t *) malloc(num_preamble*sizeof(uint8_t)); + for (int i=0; ipreambles[UE_id].preamble_list[i] = secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->resources.choice.ssb->ssb_ResourceList.list.array[i]->ra_PreambleIndex; + } LOG_I(PHY,"Added new UE_id %d/%x with initial secondaryCellGroup\n",UE_id,rnti); } else { // secondaryCellGroup has been updated diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index 956ca090e8..74bd5ae6a8 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -244,20 +244,35 @@ void nr_initiate_ra_proc(module_id_t module_idP, uint8_t ul_carrier_id = 0; // 0 for NUL 1 for SUL NR_SearchSpace_t *ss; - + int UE_id = 0; // ra_rnti from 5.1.3 in 38.321 uint16_t ra_rnti=1+symbol+(slotP*14)+(freq_index*14*80)+(ul_carrier_id*14*80*8); - - uint16_t msg2_frame, msg2_slot,monitoring_slot_period,monitoring_offset; gNB_MAC_INST *nr_mac = RC.nrmac[module_idP]; NR_UE_list_t *UE_list = &nr_mac->UE_list; - NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[0]; + NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id]; NR_COMMON_channels_t *cc = &nr_mac->common_channels[CC_id]; NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; NR_RA_t *ra = &cc->ra[0]; + // if the preamble received correspond to one of the listed + // the UE sent a RACH either for starting RA procedure or RA procedure failed and UE retries + int pr_found=0; + for (int i=0;ipreambles[UE_id].num_preambles;i++) { + if (preamble_index == UE_list->preambles[UE_id].preamble_list[i]) { + pr_found=1; + break; + } + } + if (pr_found) + UE_list->fiveG_connected[UE_id] = false; + else { + LOG_E(MAC, "[gNB %d][RAPROC] FAILURE: preamble %d does not correspond to any of the ones in rach_ConfigDedicated for UE_id %d\n", + module_idP, preamble_index, UE_id); + return; // if the PRACH preamble does not correspond to any of the ones sent through RRC abort RA proc + } + // This should be handled differently when we use the initialBWP for RA ra->bwp_id=1; NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[ra->bwp_id-1]; @@ -307,7 +322,7 @@ void nr_initiate_ra_proc(module_id_t module_idP, ra->RA_rnti = ra_rnti; ra->preamble_index = preamble_index; - + UE_list->tc_rnti[UE_id] = ra->rnti; LOG_I(MAC,"[gNB %d][RAPROC] CC_id %d Frame %d Activating Msg2 generation in frame %d, slot %d using RA rnti %x\n", module_idP, @@ -405,6 +420,7 @@ void nr_schedule_reception_msg3(module_id_t module_idP, int CC_id, frame_t frame ul_req->pdus_list[ul_req->n_pdus].pdu_size = sizeof(nfapi_nr_pusch_pdu_t); ul_req->pdus_list[ul_req->n_pdus].pusch_pdu = ra->pusch_pdu; ul_req->n_pdus+=1; + ra->state = RA_IDLE; } } } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c index 1a1fda5ec9..03161ea940 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c @@ -307,5 +307,20 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP, nr_process_mac_pdu(gnb_mod_idP, CC_idP, frameP, sduP, sdu_lenP); } } + else { + // random access pusch with TC-RNTI + if (sduP != NULL) { // if the CRC passed + for (int i = 0; i < MAX_MOBILES_PER_GNB; i++) { + if (UE_list->active[i] == TRUE) { + if (UE_list->tc_rnti[i] == current_rnti) { + // for now the only thing we are doing is set the UE as 5G connected + UE_list->fiveG_connected[i] = true; + LOG_I(MAC, "[gNB %d][RAPROC] PUSCH with TC_RNTI %x received correctly and UE_id %d is now 5G connected\n", + gnb_mod_idP, current_rnti, i); + } + } + } + } + } } diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index 2e5912a9a1..a7a81d729e 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -197,6 +197,11 @@ typedef struct { int16_t ta_update; } NR_UE_sched_ctrl_t; +typedef struct NR_preamble_ue { + uint8_t num_preambles; + uint8_t *preamble_list; +} NR_preamble_ue; + /*! \brief UE list used by gNB to order UEs/CC for scheduling*/ typedef struct { DLSCH_PDU DLSCH_pdu[4][MAX_MOBILES_PER_GNB]; @@ -209,7 +214,10 @@ typedef struct { int avail; int num_UEs; boolean_t active[MAX_MOBILES_PER_GNB]; + boolean_t fiveG_connected[MAX_MOBILES_PER_GNB]; rnti_t rnti[MAX_MOBILES_PER_GNB]; + rnti_t tc_rnti[MAX_MOBILES_PER_GNB]; + NR_preamble_ue preambles[MAX_MOBILES_PER_GNB]; NR_CellGroupConfig_t *secondaryCellGroup[MAX_MOBILES_PER_GNB]; } NR_UE_list_t; From 4b0ddb81d53e264a88766f5b56cee1167b768a79 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Sat, 18 Apr 2020 10:52:49 +0200 Subject: [PATCH 177/553] scheduling one pdcch+pdsch after RA procedure --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index 5e8282b597..4751fb1237 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -360,7 +360,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, protocol_ctxt_t ctxt; PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, module_idP, ENB_FLAG_YES, NOT_A_RNTI, frame_txP, slot_txP,module_idP); - int CC_id; + int CC_id; int UE_id; uint64_t *dlsch_in_slot_bitmap=NULL; uint64_t *ulsch_in_slot_bitmap=NULL; @@ -464,6 +464,15 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, gNB->ta_len = 0; } + // Test DL scheduling + if (get_softmodem_params()->phy_test == 0 && slot_txP == 1 && UE_list->fiveG_connected[UE_id]) { + nr_update_pucch_scheduling(module_idP, UE_id, frame_txP, slot_txP, num_slots_per_tdd,pucch_sched); + nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, pucch_sched, NULL); + // resetting ta flag + gNB->ta_len = 0; + UE_list->fiveG_connected[UE_id] = false; + } + /* // Allocate CCEs for good after scheduling is done From 939a28ba07a2634f79fd825b4b9266851df7aec3 Mon Sep 17 00:00:00 2001 From: "s.rampalli" Date: Mon, 20 Apr 2020 11:27:56 +0530 Subject: [PATCH 178/553] Removed temporary values in x2ap and rrc --- openair2/COMMON/x2ap_messages_types.h | 3 +- openair2/RRC/LTE/rrc_eNB.c | 228 +++++++++++++++++++-- openair2/RRC/NR/rrc_gNB_nsa.c | 2 + openair2/X2AP/x2ap_eNB.c | 68 +++++- openair2/X2AP/x2ap_eNB_generate_messages.c | 91 +++----- openair2/X2AP/x2ap_eNB_handler.c | 18 +- 6 files changed, 308 insertions(+), 102 deletions(-) diff --git a/openair2/COMMON/x2ap_messages_types.h b/openair2/COMMON/x2ap_messages_types.h index 38b3b7d653..f0743e60a5 100644 --- a/openair2/COMMON/x2ap_messages_types.h +++ b/openair2/COMMON/x2ap_messages_types.h @@ -315,7 +315,7 @@ typedef struct x2ap_senb_addition_req_ack_s { typedef struct x2ap_ENDC_sgnb_addition_req_s { int ue_x2_id; - + LTE_PhysCellId_t target_physCellId; /* used for RRC->X2AP in source eNB */ int rnti; @@ -386,6 +386,7 @@ typedef struct x2ap_ENDC_reconf_complete_s { int MeNB_ue_x2_id; int SgNB_ue_x2_id; + LTE_PhysCellId_t target_physCellId; x2ap_sgNB_reconf_response_information_t reconf_response; diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index 0ce76e455e..41565e6694 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -96,6 +96,11 @@ #include "SIMULATION/TOOLS/sim.h" // for taus +#define ASN_MAX_ENCODE_SIZE 1000 +static int add_CG_ConfigInfo(char **enc_buf,rrc_eNB_ue_context_t *const ue_context_pP,int * enc_size); +static int is_en_dc_supported(LTE_UE_EUTRA_Capability_t *c); +static void free_rb_config(struct NR_RadioBearerConfig *rb_config); +static void free_cg_configinfo(struct NR_CG_ConfigInfo *cg_configinfo); extern RAN_CONTEXT_t RC; @@ -4300,6 +4305,8 @@ rrc_eNB_process_MeasurementReport( long ncell_max = -150; uint32_t earfcn_dl; uint8_t KeNB_star[32] = { 0 }; + char *enc_buf = NULL; + int enc_size = 0; T(T_ENB_RRC_MEASUREMENT_REPORT, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame), T_INT(ctxt_pP->subframe), T_INT(ctxt_pP->rnti)); @@ -4362,27 +4369,36 @@ rrc_eNB_process_MeasurementReport( MessageDef *msg; ue_context_pP->ue_context.Status = RRC_NR_NSA; - msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ); - X2AP_ENDC_SGNB_ADDITION_REQ(msg).rnti = ctxt_pP->rnti; - //For the moment we have a single E-RAB which will be the one to be added to the gNB - //Not sure how to select bearers to be added if there are multiple. - X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded = 1; - for (int e_rab=0; e_rab < X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded; e_rab++){ - X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].e_rab_id = ue_context_pP->ue_context.e_rab[e_rab].param.e_rab_id; - X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].gtp_teid = ue_context_pP->ue_context.e_rab[e_rab].param.gtp_teid; - X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].drb_ID = 1; - memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr, + if(is_en_dc_supported(ue_context_pP->ue_context.UE_Capability)) { +/** to add gNB as Secondary node CG-ConfigInfo to be added as per 36.423 r15 **/ + if(add_CG_ConfigInfo(&enc_buf,ue_context_pP,&enc_size) == RRC_OK) + LOG_I(RRC,"CG-ConfigInfo encoded successfully\n"); + msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ); + X2AP_ENDC_SGNB_ADDITION_REQ(msg).rnti = ctxt_pP->rnti; + memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer,enc_buf,enc_size); + X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer_size = enc_size; + X2AP_ENDC_SGNB_ADDITION_REQ(msg).target_physCellId + = measResults2->measResultNeighCells->choice.measResultListEUTRA.list.array[0]->physCellId; + + //For the moment we have a single E-RAB which will be the one to be added to the gNB + //Not sure how to select bearers to be added if there are multiple. + X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded = 1; + for (int e_rab=0; e_rab < X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded; e_rab++){ + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].e_rab_id = ue_context_pP->ue_context.e_rab[e_rab].param.e_rab_id; + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].gtp_teid = ue_context_pP->ue_context.e_rab[e_rab].param.gtp_teid; + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].drb_ID = 1; + memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr, &ue_context_pP->ue_context.e_rab[e_rab].param.sgw_addr, sizeof(transport_layer_addr_t)); - } - LOG_I(RRC, + } + LOG_I(RRC, "[eNB %d] frame %d subframe %d: UE rnti %x switching to NSA mode\n", ctxt_pP->module_id, ctxt_pP->frame, ctxt_pP->subframe, ctxt_pP->rnti); - itti_send_msg_to_task(TASK_X2AP, ENB_MODULE_ID_TO_INSTANCE(ctxt_pP->module_id), msg); - return; - } + itti_send_msg_to_task(TASK_X2AP, ENB_MODULE_ID_TO_INSTANCE(ctxt_pP->module_id), msg); + return; + } } - +} if (measResults2->measResultNeighCells == NULL) return; @@ -4497,6 +4513,186 @@ rrc_eNB_process_MeasurementReport( } } + +//----------------------------------------------------------------------------- +/** + * @fn :add_CG_ConfigInfo + * @param :enc_buf to store the encoded bits + * @param :ue_context_pP ue context used to fill CG-ConfigInfo + * @param :enc_size to store thre size of encoded size + * this api is to fill and encode CG-ConfigInfo + */ +int add_CG_ConfigInfo( + char **enc_buf, + rrc_eNB_ue_context_t *const ue_context_pP, + int * enc_size +) { + struct NR_CG_ConfigInfo *cg_configinfo = NULL; + struct NR_RadioBearerConfig *rb_config = NULL; + asn_enc_rval_t enc_rval; + int RRC_OK = 1; + int index = 0; + + rb_config = calloc(1,sizeof( struct NR_RadioBearerConfig)); + AssertFatal(rb_config != NULL,"failed to allocate memory for rb_config"); + + if(ue_context_pP->ue_context.DRB_configList->list.count != 0) { + rb_config->drb_ToAddModList = calloc(1,sizeof(struct NR_DRB_ToAddModList )); + AssertFatal(rb_config->drb_ToAddModList != NULL,"failed to allocated memory for drbtoaddmodlist"); + rb_config->drb_ToAddModList->list.count = ue_context_pP->ue_context.DRB_configList->list.count; + rb_config->drb_ToAddModList->list.array + = calloc(ue_context_pP->ue_context.DRB_configList->list.count, sizeof(struct LTE_DRB_ToAddMod)); + AssertFatal( rb_config->drb_ToAddModList->list.array != NULL, + "falied to allocate memory for list.array"); + for(index = 0;index < ue_context_pP->ue_context.DRB_configList->list.count;index++) { + rb_config->drb_ToAddModList->list.array[index] + = calloc(1,sizeof(struct LTE_DRB_ToAddMod)); + AssertFatal(rb_config->drb_ToAddModList->list.array[index] != NULL, + "failed to allocate memory for drb_toaddmod"); + rb_config->drb_ToAddModList->list.array[index]->drb_Identity + =ue_context_pP->ue_context.DRB_configList->list.array[index]->drb_Identity; + if(ue_context_pP->ue_context.DRB_configList->list.array[index]->eps_BearerIdentity) { + rb_config->drb_ToAddModList->list.array[index]->cnAssociation + =calloc(1,sizeof(struct NR_DRB_ToAddMod__cnAssociation)); + AssertFatal(rb_config->drb_ToAddModList->list.array[index]->cnAssociation != NULL, + "failed to allocate memory cnAssociation"); + rb_config->drb_ToAddModList->list.array[index]->cnAssociation->present + =NR_DRB_ToAddMod__cnAssociation_PR_eps_BearerIdentity; + rb_config->drb_ToAddModList->list.array[index]->cnAssociation->choice.eps_BearerIdentity + =*(ue_context_pP->ue_context.DRB_configList->list.array[index]->eps_BearerIdentity); + } + } + } + + cg_configinfo = calloc(1,sizeof(struct NR_CG_ConfigInfo)); + AssertFatal(cg_configinfo != NULL,"failed to allocate memory for cg_configinfo"); + cg_configinfo->criticalExtensions.present = NR_CG_ConfigInfo__criticalExtensions_PR_c1; + cg_configinfo->criticalExtensions.choice.c1 + = calloc(1, sizeof(struct NR_CG_ConfigInfo__criticalExtensions__c1)); + AssertFatal(cg_configinfo->criticalExtensions.choice.c1 != NULL, + "failed to allocate memory for cg_configinfo->criticalExtensions.choice.c1"); + cg_configinfo->criticalExtensions.choice.c1->present + = NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo; + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo + = calloc(1,sizeof(struct NR_CG_ConfigInfo_IEs)); + AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo != NULL, + "failed to allocate memory for cg_configinfo_IEs"); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo + = calloc(1,sizeof( OCTET_STRING_t)); + AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> + ue_CapabilityInfo != NULL, "failed to allocate memory for ue_capabilityinfo"); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->size + = ue_context_pP->ue_context.UE_Capability_size; + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf + = calloc(1,sizeof(ue_context_pP->ue_context.UE_Capability_size)); + AssertFatal( cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> + ue_CapabilityInfo->buf != NULL, "failed to allocate memory for buf"); + memcpy(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf, + ue_context_pP->ue_context.UE_Capability,ue_context_pP->ue_context.UE_Capability_size); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config + = calloc(1,sizeof(OCTET_STRING_t)); + AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> + mcg_RB_Config != NULL, "failed to allocate memory for mcg_rb_config"); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->size + = sizeof( struct NR_RadioBearerConfig); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf + = calloc(1,sizeof(struct NR_RadioBearerConfig)); + AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> + mcg_RB_Config->buf != NULL,"failed to allocate memory for buf"); + memcpy(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf, + rb_config,sizeof(struct NR_RadioBearerConfig)); + enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CG_ConfigInfo,NULL,(void*)cg_configinfo, + enc_buf,ASN_MAX_ENCODE_SIZE); + AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %lu)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + *enc_size = (enc_rval.encoded+7)/8; + free_rb_config(rb_config); + free_cg_configinfo(cg_configinfo); + return RRC_OK; + } +//----------------------------------------------------------------------------- + + + +/** + * @fn :api to free the all the dynamically allocated memory + * @param :cg_configinfo contains cellgroup configuration + */ +void free_cg_configinfo( + struct NR_CG_ConfigInfo *cg_configinfo +) { + if(cg_configinfo){ + if(cg_configinfo->criticalExtensions.choice.c1){ + if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo){ + if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo){ + if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf){ + if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config){ + if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf){ + free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf =NULL; + free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config =NULL; + free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf = NULL; + free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo =NULL; + free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo =NULL; + free(cg_configinfo->criticalExtensions.choice.c1); + cg_configinfo->criticalExtensions.choice.c1 =NULL; + free(cg_configinfo); + cg_configinfo =NULL; + } + } + } + } + } + } + } + return; +} +//----------------------------------------------------------------------------- + + + +//----------------------------------------------------------------------------- +/** + * @fn :api to free the all the dynamically allocated memory + * @param :rb_config contains radiobearer configuration + */ +void free_rb_config( + struct NR_RadioBearerConfig *rb_config +) { + int index = 0; + + if(rb_config) { + if(rb_config->drb_ToAddModList) { + if(rb_config->drb_ToAddModList->list.array) { + for(index = 0; index < rb_config->drb_ToAddModList->list.count; index++) { + if(rb_config->drb_ToAddModList->list.array[index]->cnAssociation) { + free(rb_config->drb_ToAddModList->list.array[index]->cnAssociation); + rb_config->drb_ToAddModList->list.array[index]->cnAssociation = NULL; + } + if(rb_config->drb_ToAddModList->list.array[index]) { + free(rb_config->drb_ToAddModList->list.array[index]); + rb_config->drb_ToAddModList->list.array[index] = NULL; + } + } + free(rb_config->drb_ToAddModList->list.array); + rb_config->drb_ToAddModList->list.array = NULL; + free(rb_config->drb_ToAddModList); + rb_config->drb_ToAddModList = NULL; + free(rb_config); + rb_config = NULL; + } + } + } + return; +} +//------------------------------------------------------------------------------ + + + //----------------------------------------------------------------------------- void rrc_eNB_generate_HandoverPreparationInformation( diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c index afd5404d29..fe52dff8be 100644 --- a/openair2/RRC/NR/rrc_gNB_nsa.c +++ b/openair2/RRC/NR/rrc_gNB_nsa.c @@ -180,6 +180,8 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_ &create_tunnel_resp, &inde_list[0]); X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).nb_e_rabs_admitted_tobeadded = m->nb_e_rabs_tobeadded; + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).target_assoc_id = m->target_assoc_id; + for(int i=0; iue_context.nb_of_e_rabs; i++){ X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].e_rab_id = ue_context_p->ue_context.e_rab[i].param.e_rab_id; X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gtp_teid = create_tunnel_resp.enb_S1u_teid[i]; diff --git a/openair2/X2AP/x2ap_eNB.c b/openair2/X2AP/x2ap_eNB.c index debe5e0712..6a037b8ee3 100644 --- a/openair2/X2AP/x2ap_eNB.c +++ b/openair2/X2AP/x2ap_eNB.c @@ -359,7 +359,7 @@ void x2ap_eNB_handle_sctp_init_msg_multi_cnf( * Failure means multi_sd < 0. */ if (instance->multi_sd < 0) { - X2AP_ERROR("Error: be sure to properly configure X22 in your configuration file.\n"); + X2AP_ERROR("Error: be sure to properly configure X2 in your configuration file.\n"); DevAssert(instance->multi_sd >= 0); } @@ -454,10 +454,12 @@ void x2ap_eNB_handle_sgNB_add_req(instance_t instance, x2ap_eNB_instance_t *instance_p; x2ap_eNB_data_t *x2ap_eNB_data; int ue_id; - - /* TODO: remove hardcoded value */ - x2ap_eNB_data = x2ap_is_eNB_id_in_list(3584); + LTE_PhysCellId_t target_pci; + target_pci = x2ap_ENDC_sgnb_addition_req->target_physCellId; + x2ap_eNB_data = x2ap_is_eNB_pci_in_list(target_pci); DevAssert(x2ap_eNB_data != NULL); + DevAssert(x2ap_ENDC_sgnb_addition_req != NULL); + instance_p = x2ap_eNB_get_instance(instance); DevAssert(instance_p != NULL); @@ -474,7 +476,8 @@ void x2ap_eNB_handle_sgNB_add_req(instance_t instance, x2ap_set_ids(id_manager, ue_id, x2ap_ENDC_sgnb_addition_req->rnti, ue_id, -1); x2ap_id_set_state(id_manager, ue_id, X2ID_STATE_NSA_PREPARE); - x2ap_eNB_generate_ENDC_x2_SgNB_addition_request(instance_p, x2ap_ENDC_sgnb_addition_req, x2ap_eNB_data, ue_id); + x2ap_eNB_generate_ENDC_x2_SgNB_addition_request(instance_p, x2ap_ENDC_sgnb_addition_req, + x2ap_eNB_data, ue_id); } static @@ -489,16 +492,31 @@ void x2ap_gNB_trigger_sgNB_add_req_ack(instance_t instance, * as far as I understand.. CROUX */ - + x2ap_id_manager *id_manager; x2ap_eNB_instance_t *instance_p; x2ap_eNB_data_t *target; - /*int source_assoc_id = x2ap_ENDC_sgnb_addition_req_ACK->source_assoc_id; int ue_id; + /*int source_assoc_id = x2ap_ENDC_sgnb_addition_req_ACK->source_assoc_id; int id_source; int id_target;*/ instance_p = x2ap_eNB_get_instance(instance); DevAssert(instance_p != NULL); + target = x2ap_get_eNB(NULL,x2ap_ENDC_sgnb_addition_req_ACK->target_assoc_id, 0); + DevAssert(target != NULL); + + /* allocate x2ap ID */ + id_manager = &instance_p->id_manager; + ue_id = x2ap_allocate_new_id(id_manager); + if (ue_id == -1) { + X2AP_ERROR("could not allocate a new X2AP UE ID\n"); + exit(1); + } + /* id_source is ue_id, id_target is unknown yet */ + x2ap_set_ids(id_manager, ue_id, x2ap_ENDC_sgnb_addition_req_ACK->rnti, ue_id, + x2ap_ENDC_sgnb_addition_req_ACK->MeNB_ue_x2_id); + x2ap_id_set_state(id_manager, ue_id, X2ID_STATE_SOURCE_OVERALL); + /*target = x2ap_get_eNB(NULL, source_assoc_id, 0); DevAssert(target != NULL);*/ @@ -511,10 +529,36 @@ void x2ap_gNB_trigger_sgNB_add_req_ack(instance_t instance, x2ap_set_ids(&instance_p->id_manager, ue_id, x2ap_handover_req_ack->rnti, id_source, id_target);*/ - //target = x2ap_get_eNB(NULL, 17, 0); - target = x2ap_is_eNB_id_in_list (3585); //Currently hardcoded. Need to extract it differently + x2ap_gNB_generate_ENDC_x2_SgNB_addition_request_ACK(instance_p, target, + x2ap_ENDC_sgnb_addition_req_ACK, ue_id); +} + +/** + * @fn : Function triggers sgnb reconfiguration complete + * @param : IN instance, IN x2ap_reconf_complete +**/ +static +void x2ap_eNB_trigger_sgnb_reconfiguration_complete(instance_t instance, + x2ap_ENDC_reconf_complete_t *x2ap_reconf_complete) +{ + x2ap_eNB_instance_t *instance_p = NULL; + x2ap_eNB_data_t *target = NULL; + int id_source = -1; + int id_target = -1; + LTE_PhysCellId_t target_pci; + + instance_p = x2ap_eNB_get_instance(instance); + DevAssert(instance_p != NULL); + DevAssert(x2ap_reconf_complete != NULL); + + target_pci = x2ap_reconf_complete->target_physCellId; + target = x2ap_is_eNB_pci_in_list(target_pci); DevAssert(target != NULL); - x2ap_gNB_generate_ENDC_x2_SgNB_addition_request_ACK(instance_p, target, x2ap_ENDC_sgnb_addition_req_ACK, 0); + + id_source = x2ap_reconf_complete->MeNB_ue_x2_id; + id_target = x2ap_reconf_complete->SgNB_ue_x2_id; + x2ap_eNB_generate_ENDC_x2_SgNB_reconfiguration_complete(instance_p, target, id_source, id_target); + } @@ -594,6 +638,10 @@ void *x2ap_task(void *arg) { LOG_I(X2AP, "Received elements for X2AP_ENDC_SGNB_ADDITION_REQ_ACK \n"); break; + case X2AP_ENDC_SGNB_RECONF_COMPLETE: + x2ap_eNB_trigger_sgnb_reconfiguration_complete(ITTI_MESSAGE_GET_INSTANCE(received_msg), + &X2AP_ENDC_SGNB_RECONF_COMPLETE(received_msg)); + break; case SCTP_INIT_MSG_MULTI_CNF: x2ap_eNB_handle_sctp_init_msg_multi_cnf(ITTI_MESSAGE_GET_INSTANCE(received_msg), &received_msg->ittiMsg.sctp_init_msg_multi_cnf); diff --git a/openair2/X2AP/x2ap_eNB_generate_messages.c b/openair2/X2AP/x2ap_eNB_generate_messages.c index 0478448070..a96fa14f48 100644 --- a/openair2/X2AP/x2ap_eNB_generate_messages.c +++ b/openair2/X2AP/x2ap_eNB_generate_messages.c @@ -1496,7 +1496,8 @@ int x2ap_eNB_generate_ENDC_x2_setup_response( } int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request( - x2ap_eNB_instance_t *instance_p, x2ap_ENDC_sgnb_addition_req_t *x2ap_ENDC_sgnb_addition_req, x2ap_eNB_data_t *x2ap_eNB_data_p, int ue_id) + x2ap_eNB_instance_t *instance_p, x2ap_ENDC_sgnb_addition_req_t *x2ap_ENDC_sgnb_addition_req, + x2ap_eNB_data_t *x2ap_eNB_data_p, int ue_id) { X2AP_X2AP_PDU_t pdu; X2AP_SgNBAdditionRequest_t *out; @@ -1507,42 +1508,21 @@ int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request( uint8_t *buffer; uint32_t len; int ret = 0; - - // Currently hardcoded (dummy) values filling the fields of SgNB_addition_request message. To be substituted - // with values coming from RRC. - uint16_t nRencryptionAlgorithms = 0; - uint16_t nRintegrityProtectionAlgorithms = 0; + uint16_t nRencryptionAlgorithms = x2ap_ENDC_sgnb_addition_req->security_capabilities.encryption_algorithms; + uint16_t nRintegrityProtectionAlgorithms = x2ap_ENDC_sgnb_addition_req->security_capabilities + .integrity_algorithms; uint8_t SgNBSecurityKey[32] = { 0 }; - int uEaggregateMaximumBitRateDownlink = 100000000; - int uEaggregateMaximumBitRateUplink = 100000000; - int e_rabs_tobeadded = 1; + int uEaggregateMaximumBitRateDownlink = x2ap_ENDC_sgnb_addition_req->ue_ambr.br_dl; + int uEaggregateMaximumBitRateUplink = x2ap_ENDC_sgnb_addition_req->ue_ambr.br_ul; + int e_rabs_tobeadded = x2ap_ENDC_sgnb_addition_req->nb_e_rabs_tobeadded; long int pDCPatSgNB = X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present; long int mCGresources = X2AP_EN_DC_ResourceConfiguration__mCGresources_not_present; long int sCGresources = X2AP_EN_DC_ResourceConfiguration__sCGresources_not_present; - long qCI = 1; - X2AP_Pre_emptionCapability_t pre_emptionCapability = X2AP_Pre_emptionCapability_shall_not_trigger_pre_emption; - X2AP_Pre_emptionVulnerability_t pre_emptionVulnerability = X2AP_Pre_emptionVulnerability_not_pre_emptable; - priority_level_t priority_level = PRIORITY_LEVEL_NO_PRIORITY; - e_rab_tobe_added_t e_MCG_rabs_tobeadded; - e_MCG_rabs_tobeadded.gtp_teid = 0; - e_MCG_rabs_tobeadded.sgw_addr.length = 24; - uint8_t buf[20] = { 0 }; - memcpy(e_MCG_rabs_tobeadded.sgw_addr.buffer, buf, 20*sizeof(uint8_t)); - - FILE *fd; - fd = fopen("../../../executables/uecap.raw","r"); - if (fd != NULL) { - OCTET_STRING_t CG_Config_Info; - CG_Config_Info.size = 4096; - CG_Config_Info.buf = (uint8_t *)calloc(4096, sizeof(uint8_t)); - int msg_len=fread(CG_Config_Info.buf,1,CG_Config_Info.size,fd); - CG_Config_Info.size = msg_len; - - /*char buffer[4096]; - int msg_len=fread(buffer,1,4096,fd);*/ - LOG_I(RRC,"Read in %d bytes for uecap\n",msg_len); - - + long qCI = 0; + X2AP_Pre_emptionCapability_t pre_emptionCapability; + X2AP_Pre_emptionVulnerability_t pre_emptionVulnerability; + priority_level_t priority_level; + memcpy(SgNBSecurityKey, x2ap_ENDC_sgnb_addition_req->kgnb, sizeof(x2ap_ENDC_sgnb_addition_req->kgnb)); /*OCTET_STRING_t CG_Config_Info; CG_Config_Info.size = 4096; CG_Config_Info.buf = (uint8_t *)calloc(4096, sizeof(uint8_t));*/ @@ -1618,7 +1598,11 @@ int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request( e_RABS_ToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.mCGresources = mCGresources; e_RABS_ToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.sCGresources = sCGresources; if (pDCPatSgNB == X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present){ - e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.present = X2AP_E_RABs_ToBeAdded_SgNBAddReq_Item__resource_configuration_PR_sgNBPDCPpresent; + e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.present = X2AP_E_RABs_ToBeAdded_SgNBAddReq_Item__resource_configuration_PR_sgNBPDCPpresent; + qCI = x2ap_ENDC_sgnb_addition_req->e_rab_param[i].qos.qci; + priority_level = x2ap_ENDC_sgnb_addition_req->e_rab_param[i].qos.allocation_retention_priority.priority_level; + pre_emptionCapability = x2ap_ENDC_sgnb_addition_req->e_rab_param[i].qos.allocation_retention_priority.pre_emp_capability; + pre_emptionVulnerability = x2ap_ENDC_sgnb_addition_req->e_rab_param[i].qos.allocation_retention_priority.pre_emp_vulnerability; e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.full_E_RAB_Level_QoS_Parameters.qCI = qCI; e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.full_E_RAB_Level_QoS_Parameters.allocationAndRetentionPriority.pre_emptionCapability = pre_emptionCapability; @@ -1646,25 +1630,24 @@ int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request( ie->id = X2AP_ProtocolIE_ID_id_MeNBtoSgNBContainer; ie->criticality = X2AP_Criticality_reject; ie->value.present = X2AP_SgNBAdditionRequest_IEs__value_PR_MeNBtoSgNBContainer; - ie->value.choice.MeNBtoSgNBContainer.buf = (uint8_t *)calloc(CG_Config_Info.size, sizeof(uint8_t)); - memcpy(ie->value.choice.MeNBtoSgNBContainer.buf, CG_Config_Info.buf, CG_Config_Info.size); - ie->value.choice.MeNBtoSgNBContainer.size = CG_Config_Info.size; //4096; + if(NULL == (ie->value.choice.MeNBtoSgNBContainer.buf = (uint8_t *) + calloc(x2ap_ENDC_sgnb_addition_req->rrc_buffer_size, sizeof(uint8_t)))) { + X2AP_ERROR("Memory ALLocation failed\n"); + exit(1); + } + memcpy(ie->value.choice.MeNBtoSgNBContainer.buf, x2ap_ENDC_sgnb_addition_req->rrc_buffer, + x2ap_ENDC_sgnb_addition_req->rrc_buffer_size); + ie->value.choice.MeNBtoSgNBContainer.size = x2ap_ENDC_sgnb_addition_req->rrc_buffer_size; ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); if (x2ap_eNB_encode_pdu(&pdu, &buffer, &len) < 0) { X2AP_ERROR("Failed to encode ENDC X2 SgNB_addition request message\n"); return -1; } - + free(ie->value.choice.MeNBtoSgNBContainer.buf); MSC_LOG_TX_MESSAGE (MSC_X2AP_SRC_ENB, MSC_X2AP_TARGET_ENB, NULL, 0, "0 X2Setup/initiatingMessage assoc_id %u", x2ap_eNB_data_p->assoc_id); x2ap_eNB_itti_send_sctp_data_req(instance_p->instance, x2ap_eNB_data_p->assoc_id, buffer, len, 0); - fclose(fd); - } - else { - LOG_I(RRC, "uecap.raw file could not be opened... \n"); - return -1; - } return ret; @@ -1684,26 +1667,14 @@ int x2ap_gNB_generate_ENDC_x2_SgNB_addition_request_ACK( x2ap_eNB_instance_t *in uint8_t *buffer; uint32_t len; int ret = 0; - int MeNB_UE_X2AP_id = ue_id; - int SgNB_UE_X2AP_id = 0; - // Currently hardcoded (dummy) values filling the fields of SgNB_addition_request message. To be substituted - // with values coming from RRC. - //uint16_t nRencryptionAlgorithms = 0; - //uint16_t nRintegrityProtectionAlgorithms = 0; - //uint8_t SgNBSecurityKey[32] = { 0 }; - //int uEaggregateMaximumBitRateDownlink = 100000000; - //int uEaggregateMaximumBitRateUplink = 100000000; - - int e_rabs_admitted_tobeadded = 1; + int MeNB_UE_X2AP_id = x2ap_sgnb_addition_req_ACK->MeNB_ue_x2_id; + int SgNB_UE_X2AP_id = ue_id; + int e_rabs_admitted_tobeadded = x2ap_sgnb_addition_req_ACK->nb_e_rabs_admitted_tobeadded; long int pDCPatSgNB = X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present; long int mCGresources = X2AP_EN_DC_ResourceConfiguration__mCGresources_not_present; long int sCGresources = X2AP_EN_DC_ResourceConfiguration__sCGresources_not_present; - e_rab_setup_t e_SCG_rabs_tobeadded; - e_SCG_rabs_tobeadded.gtp_teid = 0; - e_SCG_rabs_tobeadded.eNB_addr.length = 24; - uint8_t buf[20] = { 0 }; - memcpy(e_SCG_rabs_tobeadded.eNB_addr.buffer, buf, 20*sizeof(uint8_t)); + DevAssert(instance_p != NULL); DevAssert(x2ap_eNB_data_p != NULL); diff --git a/openair2/X2AP/x2ap_eNB_handler.c b/openair2/X2AP/x2ap_eNB_handler.c index e144eda435..87ef5bf69f 100644 --- a/openair2/X2AP/x2ap_eNB_handler.c +++ b/openair2/X2AP/x2ap_eNB_handler.c @@ -1652,7 +1652,6 @@ int x2ap_gNB_handle_ENDC_sGNB_addition_request (instance_t instance, x2ap_eNB_instance_t *instance_p; x2ap_eNB_data_t *x2ap_eNB_data; MessageDef *msg; - int ue_id; DevAssert (pdu != NULL); x2SgNBAdditionRequest = &pdu->choice.initiatingMessage.value.choice.SgNBAdditionRequest; @@ -1683,20 +1682,9 @@ int x2ap_gNB_handle_ENDC_sGNB_addition_request (instance_t instance, X2AP_ERROR("%s %d: ie is a NULL pointer \n",__FILE__,__LINE__); return -1; } - - - // allocate a new X2AP UE ID - ue_id = x2ap_allocate_new_id(&instance_p->id_manager); - if (ue_id == -1) { - X2AP_ERROR("could not allocate a new X2AP UE ID\n"); - // TODO: cancel handover: send HO preparation failure to source eNB - exit(1); - } - // rnti is unknown yet, must not be set to -1, 0 is fine - x2ap_set_ids(&instance_p->id_manager, ue_id, 0, ie->value.choice.UE_X2AP_ID, ue_id); - x2ap_id_set_state(&instance_p->id_manager, ue_id, X2ID_STATE_TARGET); - - X2AP_ENDC_SGNB_ADDITION_REQ(msg).ue_x2_id = ue_id; + /* ue_x2_id = MeNB X2AP Id */ + X2AP_ENDC_SGNB_ADDITION_REQ(msg).ue_x2_id = ie->value.choice.UE_X2AP_ID; + X2AP_ENDC_SGNB_ADDITION_REQ(msg).target_assoc_id = assoc_id; /* X2AP_ProtocolIE_ID_id_NRUESecurityCapabilities */ From 3c5b6368f11a10430ed576af02a907e977344952 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Mon, 20 Apr 2020 13:19:10 +0200 Subject: [PATCH 179/553] bugfix for numdldci for RA --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 1 - 1 file changed, 1 deletion(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index 74bd5ae6a8..5b7bf3ce02 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -686,7 +686,6 @@ void nr_generate_Msg2(module_id_t module_idP, pdcch_pdu_rel15->StartSymbolIndex, pdcch_pdu_rel15->DurationSymbols); - pdcch_pdu_rel15->numDlDci++; fill_dci_pdu_rel15(secondaryCellGroup,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types,dci10_bw,ra->bwp_id); dl_req->nPDUs+=2; From 48325d58e55b161280c8db6047afa41ddf132313 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Tue, 21 Apr 2020 09:58:53 +0200 Subject: [PATCH 180/553] some logs for phytest scheduling DL with phone --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 834feac62c..f483e07ab0 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -378,7 +378,7 @@ int configure_fapi_dl_pdu(int Mod_idP, // antenna ports dci_pdu_rel15[0].antenna_ports.val = 0; // nb of cdm groups w/o data 1 and dmrs port 0 - LOG_D(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n", + LOG_I(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n", dci_pdu_rel15[0].frequency_domain_assignment.val, pdsch_pdu_rel15->rbStart, pdsch_pdu_rel15->rbSize, @@ -448,7 +448,7 @@ int configure_fapi_dl_pdu(int Mod_idP, // Hardcode it for now TBS = dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15.TBSize[0]; - LOG_D(MAC, "DLSCH PDU: start PRB %d n_PRB %d startSymbolAndLength %d start symbol %d nb_symbols %d nb_layers %d nb_codewords %d mcs %d TBS: %d\n", + LOG_I(MAC, "DLSCH PDU: start PRB %d n_PRB %d startSymbolAndLength %d start symbol %d nb_symbols %d nb_layers %d nb_codewords %d mcs %d TBS: %d\n", pdsch_pdu_rel15->rbStart, pdsch_pdu_rel15->rbSize, startSymbolAndLength, @@ -539,7 +539,7 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, NR_sched_pucch *pucch_sched, nfapi_nr_dl_tti_pdsch_pdu_rel15_t *dlsch_config){ - LOG_D(MAC, "In nr_schedule_uss_dlsch_phytest \n"); + LOG_I(MAC, "In nr_schedule_uss_dlsch_phytest frame %d slot %d\n",frameP,slotP); int post_padding = 0, ta_len = 0, header_length_total = 0, sdu_length_total = 0, num_sdus = 0; int lcid, offset, i, header_length_last, TBS_bytes; From 80571bb81e564bdba2fa7a16f3fca83ad25b9248 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Wed, 22 Apr 2020 09:54:56 +0200 Subject: [PATCH 181/553] fapi functions for pucch --- .../nfapi/public_inc/nfapi_nr_interface_scf.h | 2 +- openair1/PHY/INIT/nr_init.c | 7 +++ .../PHY/NR_TRANSPORT/nr_transport_proto.h | 12 +++++ openair1/PHY/NR_TRANSPORT/pucch_rx.c | 48 +++++++++++++++++++ openair1/PHY/defs_gNB.h | 16 +++++-- openair1/SCHED_NR/fapi_nr_l1.c | 4 +- openair1/SCHED_NR/phy_procedures_nr_gNB.c | 31 ++++++++++++ openair2/COMMON/platform_constants.h | 1 + 8 files changed, 114 insertions(+), 7 deletions(-) diff --git a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h index 0e57e2db0e..dd3e2d037f 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h @@ -1560,7 +1560,7 @@ typedef struct uint16_t sfn; uint16_t slot; uint16_t num_ucis; - nfapi_nr_uci_t uci_list[NFAPI_MAX_NUM_UCI_INDICATION]; + nfapi_nr_uci_t *uci_list; } nfapi_nr_uci_indication_t; diff --git a/openair1/PHY/INIT/nr_init.c b/openair1/PHY/INIT/nr_init.c index a74b90749a..85e1079c5b 100644 --- a/openair1/PHY/INIT/nr_init.c +++ b/openair1/PHY/INIT/nr_init.c @@ -26,6 +26,7 @@ #include "PHY/INIT/phy_init.h" #include "PHY/CODING/nrPolar_tools/nr_polar_pbch_defs.h" #include "PHY/NR_TRANSPORT/nr_transport.h" +#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "PHY/NR_TRANSPORT/nr_transport_proto_common.h" /*#include "RadioResourceConfigCommonSIB.h" #include "RadioResourceConfigDedicated.h" @@ -502,6 +503,12 @@ void init_nr_transport(PHY_VARS_gNB *gNB) { LOG_I(PHY, "Initialise nr transport\n"); uint16_t grid_size = cfg->carrier_config.dl_grid_size[fp->numerology_index].value; + for (i=0; ipucch[i] = new_gNB_pucch(); + AssertFatal(gNB->pucch[i]!=NULL,"Can't initialize pucch %d \n", i); + } + for (i=0; iactive = 0; + return (pucch); +} + +int nr_find_pucch(uint16_t rnti, + int frame, + int slot, + PHY_VARS_gNB *gNB) { + + AssertFatal(gNB!=NULL,"gNB is null\n"); + int index = -1; + + for (int i=0; ipucch[i]!=NULL,"gNB->pucch[%d] is null\n",i); + if ((gNB->pucch[i]->active >0) && + (gNB->pucch[i]->pucch_pdu.rnti==rnti) && + (gNB->pucch[i]->frame==frame) && + (gNB->pucch[i]->slot==slot)) return(i); + else if ((gNB->pucch[i]->active == 0) && (index==-1)) index=i; + } + + if (index==-1) + LOG_E(MAC,"PUCCH list is full\n"); + + return(index); +} + +void nr_fill_pucch(PHY_VARS_gNB *gNB, + int frame, + int slot, + nfapi_nr_pucch_pdu_t *pucch_pdu) { + + int id = nr_find_pucch(pucch_pdu->rnti,frame,slot,gNB); + AssertFatal( (id>=0) && (idrnti,id); + + NR_gNB_PUCCH_t *pucch = gNB->pucch[id]; + pucch->frame = frame; + pucch->slot = slot; + pucch->active = 1; + memcpy((void*)&pucch->pucch_pdu, (void*)pucch_pdu, sizeof(nfapi_nr_pucch_pdu_t)); + +} + + int get_pucch0_cs_lut_index(PHY_VARS_gNB *gNB,nfapi_nr_pucch_pdu_t* pucch_pdu) { int i=0; diff --git a/openair1/PHY/defs_gNB.h b/openair1/PHY/defs_gNB.h index 9cd3f5ed23..7a050e2cc3 100644 --- a/openair1/PHY/defs_gNB.h +++ b/openair1/PHY/defs_gNB.h @@ -340,6 +340,15 @@ typedef struct { uint16_t cba_rnti[NUM_MAX_CBA_GROUP]; } NR_gNB_ULSCH_t; +typedef struct { + uint8_t active; + /// Frame where current PUCCH pdu was sent + uint32_t frame; + /// Slot where current PUCCH pdu was sent + uint32_t slot; + /// ULSCH PDU + nfapi_nr_pucch_pdu_t pucch_pdu; +} NR_gNB_PUCCH_t; typedef struct { /// \brief Pointers (dynamic) to the received data in the time domain. @@ -619,9 +628,9 @@ typedef struct { #define MAX_NUM_NR_RX_RACH_PDUS 4 #define MAX_NUM_NR_RX_PRACH_PREAMBLES 4 -#define MAX_UL_PDUS_PER_SLOT 100 -#define MAX_NUM_NR_SRS_PDUS 100 -#define MAX_NUM_NR_UCI_PDUS 100 +#define MAX_UL_PDUS_PER_SLOT 8 +#define MAX_NUM_NR_SRS_PDUS 8 +#define MAX_NUM_NR_UCI_PDUS 8 /// Top-level PHY Data Structure for gNB typedef struct PHY_VARS_gNB_s { @@ -675,6 +684,7 @@ typedef struct PHY_VARS_gNB_s { NR_gNB_COMMON common_vars; NR_gNB_PRACH prach_vars; NR_gNB_PUSCH *pusch_vars[NUMBER_OF_NR_ULSCH_MAX]; + NR_gNB_PUCCH_t *pucch[NUMBER_OF_NR_PUCCH_MAX]; NR_gNB_DLSCH_t *dlsch[NUMBER_OF_NR_DLSCH_MAX][2]; // Nusers times two spatial streams NR_gNB_ULSCH_t *ulsch[NUMBER_OF_NR_ULSCH_MAX][2]; // [Nusers times][2 codewords] NR_gNB_DLSCH_t *dlsch_SI,*dlsch_ra,*dlsch_p; diff --git a/openair1/SCHED_NR/fapi_nr_l1.c b/openair1/SCHED_NR/fapi_nr_l1.c index a2d26765f1..1576ab9e64 100644 --- a/openair1/SCHED_NR/fapi_nr_l1.c +++ b/openair1/SCHED_NR/fapi_nr_l1.c @@ -114,8 +114,6 @@ void handle_nfapi_nr_ul_dci_pdu(PHY_VARS_gNB *gNB, nr_fill_ul_dci(gNB,frame,slot); - - } void handle_nr_nfapi_pdsch_pdu(PHY_VARS_gNB *gNB,int frame,int slot, @@ -211,7 +209,7 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){ break; case NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE: LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_TTI_PUCCH_PDU_TYPE for %d.%d\n", frame, slot, UL_tti_req->SFN, UL_tti_req->Slot); - // handle_nfapi_nr_pucch_pdu(gNB,frame,slot,UL_tti_req->pdus_list[i].pucch_pdu); + nr_fill_pucch(gNB,UL_tti_req->SFN, UL_tti_req->Slot, &UL_tti_req->pdus_list[i].pucch_pdu); break; case NFAPI_NR_UL_CONFIG_PRACH_PDU_TYPE: LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_TTI_PRACH_PDU_TYPE for %d.%d\n", frame, slot, UL_tti_req->SFN, UL_tti_req->Slot); diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index 3d312e0976..8c0fc1f5a3 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -384,6 +384,37 @@ void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) LOG_D(PHY,"phy_procedures_gNB_uespec_RX frame %d, slot %d\n",frame_rx,slot_rx); + for (int i=0;ipucch[i]; + if (pucch) { + nfapi_nr_pucch_pdu_t *pucch_pdu = &pucch[i].pucch_pdu; + uint16_t num_ucis; + + switch (pucch_pdu->format_type) { + case 0: +/* + num_ucis = gNB->UL_INFO.uci_ind.num_ucis; + gNB->UL_INFO.uci_ind.uci_list = &gNB->uci_pdu_list[0]; + gNB->UL_INFO.uci_ind.sfn = frame_rx; + gNB->UL_INFO.uci_ind.slot = slot_rx; + gNB->uci_pdu_list[num_ucis].pdu_type = NFAPI_NR_UCI_FORMAT_0_1_PDU_TYPE; + gNB->uci_pdu_list[num_ucis].pdu_size = sizeof(nfapi_nr_uci_pucch_pdu_format_0_1_t); + nfapi_nr_uci_pucch_pdu_format_0_1_t *uci_pdu_format0 = &gNB->uci_pdu_list[num_ucis].pucch_pdu_format_0_1; + + nr_decode_pucch0(gNB, + slot_rx, + uci_pdu_format0, + pucch_pdu); + + gNB->UL_INFO.uci_ind.num_ucis += 1;*/ + pucch->active = 0; + break; + default: + AssertFatal(1==0,"Only PUCCH format 0 is currently supported\n"); + } + } + } + for (int ULSCH_id=0;ULSCH_idulsch[ULSCH_id][0]; int harq_pid; diff --git a/openair2/COMMON/platform_constants.h b/openair2/COMMON/platform_constants.h index 7a7e984aca..f15751fbee 100644 --- a/openair2/COMMON/platform_constants.h +++ b/openair2/COMMON/platform_constants.h @@ -99,6 +99,7 @@ #define NUMBER_OF_NR_DLSCH_MAX 2//16 #define NUMBER_OF_NR_ULSCH_MAX 2//16 +#define NUMBER_OF_NR_PUCCH_MAX 2 #define NUMBER_OF_NR_SR_MAX 16 From a66f6907dea036fffb282097c8a8cd5310246798 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Wed, 22 Apr 2020 11:11:22 +0200 Subject: [PATCH 182/553] bufix in calling phy pucch function --- openair1/SCHED_NR/phy_procedures_nr_gNB.c | 47 +++++++++++++---------- 1 file changed, 26 insertions(+), 21 deletions(-) diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index 8c0fc1f5a3..147ff778f3 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -387,30 +387,35 @@ void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) for (int i=0;ipucch[i]; if (pucch) { - nfapi_nr_pucch_pdu_t *pucch_pdu = &pucch[i].pucch_pdu; - uint16_t num_ucis; + if ((pucch->active == 1) && + (pucch->frame == frame_rx) && + (pucch->slot == slot_rx) ) { - switch (pucch_pdu->format_type) { - case 0: -/* - num_ucis = gNB->UL_INFO.uci_ind.num_ucis; - gNB->UL_INFO.uci_ind.uci_list = &gNB->uci_pdu_list[0]; - gNB->UL_INFO.uci_ind.sfn = frame_rx; - gNB->UL_INFO.uci_ind.slot = slot_rx; - gNB->uci_pdu_list[num_ucis].pdu_type = NFAPI_NR_UCI_FORMAT_0_1_PDU_TYPE; - gNB->uci_pdu_list[num_ucis].pdu_size = sizeof(nfapi_nr_uci_pucch_pdu_format_0_1_t); - nfapi_nr_uci_pucch_pdu_format_0_1_t *uci_pdu_format0 = &gNB->uci_pdu_list[num_ucis].pucch_pdu_format_0_1; + nfapi_nr_pucch_pdu_t *pucch_pdu = &pucch[i].pucch_pdu; + uint16_t num_ucis; - nr_decode_pucch0(gNB, - slot_rx, - uci_pdu_format0, - pucch_pdu); + switch (pucch_pdu->format_type) { + case 0: - gNB->UL_INFO.uci_ind.num_ucis += 1;*/ - pucch->active = 0; - break; - default: - AssertFatal(1==0,"Only PUCCH format 0 is currently supported\n"); + num_ucis = gNB->UL_INFO.uci_ind.num_ucis; + gNB->UL_INFO.uci_ind.uci_list = &gNB->uci_pdu_list[0]; + gNB->UL_INFO.uci_ind.sfn = frame_rx; + gNB->UL_INFO.uci_ind.slot = slot_rx; + gNB->uci_pdu_list[num_ucis].pdu_type = NFAPI_NR_UCI_FORMAT_0_1_PDU_TYPE; + gNB->uci_pdu_list[num_ucis].pdu_size = sizeof(nfapi_nr_uci_pucch_pdu_format_0_1_t); + nfapi_nr_uci_pucch_pdu_format_0_1_t *uci_pdu_format0 = &gNB->uci_pdu_list[num_ucis].pucch_pdu_format_0_1; + + nr_decode_pucch0(gNB, + slot_rx, + uci_pdu_format0, + pucch_pdu); + + gNB->UL_INFO.uci_ind.num_ucis += 1; + pucch->active = 0; + break; + default: + AssertFatal(1==0,"Only PUCCH format 0 is currently supported\n"); + } } } } From 0546bcea9409d33dac9935715e8202c33b567da4 Mon Sep 17 00:00:00 2001 From: cig Date: Wed, 22 Apr 2020 17:57:24 +0200 Subject: [PATCH 183/553] Doing phy procedures RX in slot 7 for RAR DCI --- executables/nr-ue.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/executables/nr-ue.c b/executables/nr-ue.c index 514d5f0239..759d139169 100644 --- a/executables/nr-ue.c +++ b/executables/nr-ue.c @@ -434,7 +434,8 @@ void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { //program DCI for slot 1 //TODO: all of this has to be moved to the MAC!!! - if (proc->nr_tti_rx == NR_DOWNLINK_SLOT || UE->frame_parms.frame_type == FDD){ + // Note: temp hardcoded slot 7 for RAR + if (proc->nr_tti_rx == NR_DOWNLINK_SLOT || proc->nr_tti_rx == 7 || UE->frame_parms.frame_type == FDD){ dcireq.module_id = UE->Mod_id; dcireq.gNB_index = 0; dcireq.cc_id = 0; @@ -462,7 +463,7 @@ void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { } // Process Rx data for one sub-frame - if ( proc->nr_tti_rx >=0 && proc->nr_tti_rx <= 1 ) { + if ( proc->nr_tti_rx >=0 && proc->nr_tti_rx <= 1 || proc->nr_tti_rx == 7) { #ifdef UE_SLOT_PARALLELISATION phy_procedures_slot_parallelization_nrUE_RX( UE, proc, 0, 0, 1, UE->mode, no_relay, NULL ); #else From b6ba07af141a96de3a16e819580c2dd6b7524862 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Thu, 23 Apr 2020 09:43:25 +0200 Subject: [PATCH 184/553] fix in dlsim --- openair1/SIMULATION/NR_PHY/dlsim.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair1/SIMULATION/NR_PHY/dlsim.c b/openair1/SIMULATION/NR_PHY/dlsim.c index 025c648fc8..8e0ef92c81 100644 --- a/openair1/SIMULATION/NR_PHY/dlsim.c +++ b/openair1/SIMULATION/NR_PHY/dlsim.c @@ -703,8 +703,8 @@ int main(int argc, char **argv) errors_bit = 0; //multipath channel //multipath_channel(gNB2UE,s_re,s_im,r_re,r_im,frame_length_complex_samples,0); - memset(RC.nrmac[0]->cce_list[1][0],0,MAX_NUM_CCE*sizeof(int)); + memset(RC.nrmac[0]->cce_list[1][1],0,MAX_NUM_CCE*sizeof(int)); clear_nr_nfapi_information(RC.nrmac[0], 0, frame, slot); if (css_flag == 0) nr_schedule_uss_dlsch_phytest(0,frame,slot,&pucch_sched,&dlsch_config); else nr_schedule_css_dlsch_phytest(0,frame,slot); From 220685e320ff0f2fbc362cc9659ab10d060e60b4 Mon Sep 17 00:00:00 2001 From: cig Date: Wed, 22 Apr 2020 18:04:39 +0200 Subject: [PATCH 185/553] UE RAR DCI reception - NR UE scheduled response for RA PDSCH case - UE processing of RAR DCI - some cleanup and formatting --- .../nfapi/public_inc/fapi_nr_ue_constants.h | 1 + openair1/SCHED_NR_UE/fapi_nr_ue_l1.c | 15 +- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 219 +++++++++--------- .../NR_MAC_UE/nr_ue_dci_configuration.c | 34 ++- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 6 +- 5 files changed, 146 insertions(+), 129 deletions(-) diff --git a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h index 4b0720078a..e1d06335f5 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h @@ -43,6 +43,7 @@ #define FAPI_NR_DL_CONFIG_TYPE_DCI 0x01 #define FAPI_NR_DL_CONFIG_TYPE_DLSCH 0x02 +#define FAPI_NR_DL_CONFIG_TYPE_RA_DLSCH 0x03 #define FAPI_NR_CCE_REG_MAPPING_TYPE_INTERLEAVED 0x01 diff --git a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c index 7edbfcbd6c..f48635d3f7 100644 --- a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c +++ b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c @@ -51,8 +51,8 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ // Note: we have to handle the thread IDs for this. To be revisited completely. thread_id = PHY_vars_UE_g[module_id][cc_id]->current_thread_id[slot]; + NR_UE_DLSCH_t *dlsch0; NR_UE_PDCCH *pdcch_vars = PHY_vars_UE_g[module_id][cc_id]->pdcch_vars[thread_id][0]; - NR_UE_DLSCH_t *dlsch0 = PHY_vars_UE_g[module_id][cc_id]->dlsch[thread_id][0][0]; NR_UE_ULSCH_t *ulsch0 = PHY_vars_UE_g[module_id][cc_id]->ulsch[thread_id][0][0]; if(scheduled_response->dl_config != NULL){ @@ -69,7 +69,14 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ pdcch_vars->nb_search_space = pdcch_vars->nb_search_space + 1; LOG_D(PHY,"Number of DCI SearchSpaces %d\n",pdcch_vars->nb_search_space); - } else { //FAPI_NR_DL_CONFIG_TYPE_DLSCH + } else { + + if (dl_config->dl_config_list[i].pdu_type == FAPI_NR_DL_CONFIG_TYPE_DLSCH){ + dlsch0 = PHY_vars_UE_g[module_id][cc_id]->dlsch[thread_id][0][0]; + } + else if (dl_config->dl_config_list[i].pdu_type == FAPI_NR_DL_CONFIG_TYPE_RA_DLSCH){ + dlsch0 = PHY_vars_UE_g[module_id][cc_id]->dlsch_ra[0]; + } fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu = &dl_config->dl_config_list[i].dlsch_config_pdu.dlsch_config_rel15; uint8_t current_harq_pid = dlsch_config_pdu->harq_process_nbr; @@ -80,7 +87,9 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ dlsch0->rnti = dl_config->dl_config_list[i].dlsch_config_pdu.rnti; //dlsch0->harq_processes[0]->mcs = &dlsch_config_pdu->mcs; dlsch0_harq = dlsch0->harq_processes[current_harq_pid]; - if (dlsch0_harq != NULL){ + + if (dlsch0_harq){ + dlsch0_harq->BWPStart = dlsch_config_pdu->BWPStart; dlsch0_harq->BWPSize = dlsch_config_pdu->BWPSize; dlsch0_harq->nb_rb = dlsch_config_pdu->number_rbs; diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index cc1a2fe838..adeb186517 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -2774,19 +2774,20 @@ int nr_ue_pdcch_procedures(uint8_t gNB_id, nr_tti_rx, &dci_ind); -#ifdef NR_PDCCH_SCHED_DEBUG +//#ifdef NR_PDCCH_SCHED_DEBUG LOG_I(PHY,"<-NR_PDCCH_PHY_PROCEDURES_LTE_UE (nr_ue_pdcch_procedures)-> Ending function nr_dci_decoding_procedure() -> dci_cnt=%u\n",dci_cnt); -#endif +//#endif VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DCI_DECODING, VCD_FUNCTION_OUT); //LOG_D(PHY,"[UE %d][PUSCH] Frame %d nr_tti_rx %d PHICH RX\n",ue->Mod_id,frame_rx,nr_tti_rx); for (int i=0; i rnti %x : format %d\n", - ue->Mod_id,frame_rx%1024,nr_tti_rx,nr_mode_string[ue->UE_mode[gNB_id]], - i, - dci_ind.dci_list[i].rnti, - dci_ind.dci_list[i].dci_format); + LOG_D(PHY,"[UE %d] AbsSubFrame %d.%d, Mode %s: DCI %i of %d total DCIs found --> rnti %x : format %d\n", + ue->Mod_id,frame_rx%1024,nr_tti_rx,nr_mode_string[ue->UE_mode[gNB_id]], + i + 1, + dci_cnt, + dci_ind.dci_list[i].rnti, + dci_ind.dci_list[i].dci_format); } ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][gNB_id]->dci_received += dci_cnt; @@ -3035,7 +3036,7 @@ void nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB int first_symbol_flag=0; if (!dlsch0) - return; + return; if (dlsch0->active == 0) return; @@ -3044,9 +3045,9 @@ void nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB uint16_t BWPStart = dlsch0->harq_processes[harq_pid]->BWPStart; // uint16_t BWPSize = dlsch0->harq_processes[harq_pid]->BWPSize; uint16_t pdsch_start_rb = dlsch0->harq_processes[harq_pid]->start_rb; - uint16_t pdsch_nb_rb = dlsch0->harq_processes[harq_pid]->nb_rb; - uint16_t s0 = dlsch0->harq_processes[harq_pid]->start_symbol; - uint16_t s1 = dlsch0->harq_processes[harq_pid]->nb_symbols; + uint16_t pdsch_nb_rb = dlsch0->harq_processes[harq_pid]->nb_rb; + uint16_t s0 = dlsch0->harq_processes[harq_pid]->start_symbol; + uint16_t s1 = dlsch0->harq_processes[harq_pid]->nb_symbols; LOG_D(PHY,"[UE %d] PDSCH type %d active in nr_tti_rx %d, harq_pid %d, rb_start %d, nb_rb %d, symbol_start %d, nb_symbols %d, DMRS mask %x\n",ue->Mod_id,pdsch,nr_tti_rx,harq_pid,pdsch_start_rb,pdsch_nb_rb,s0,s1,dlsch0->harq_processes[harq_pid]->dlDmrsSymbPos); @@ -3305,14 +3306,11 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, if (dlsch0==NULL) AssertFatal(0,"dlsch0 should be defined at this level \n"); - harq_pid = dlsch0->current_harq_pid; is_cw0_active = dlsch0->harq_processes[harq_pid]->status; nb_symb_sch = dlsch0->harq_processes[harq_pid]->nb_symbols; start_symbol = dlsch0->harq_processes[harq_pid]->start_symbol; - - if(dlsch1) is_cw1_active = dlsch1->harq_processes[harq_pid]->status; @@ -3379,10 +3377,10 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, start_meas(&ue->dlsch_unscrambling_stats); #endif nr_dlsch_unscrambling(pdsch_vars->llr[0], - dlsch0->harq_processes[harq_pid]->G, - 0, - ue->frame_parms.Nid_cell, - dlsch0->rnti); + dlsch0->harq_processes[harq_pid]->G, + 0, + ue->frame_parms.Nid_cell, + dlsch0->rnti); #if UE_TIMING_TRACE @@ -3463,10 +3461,10 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, start_meas(&ue->dlsch_unscrambling_stats); #endif nr_dlsch_unscrambling(pdsch_vars->llr[1], - dlsch1->harq_processes[harq_pid]->G, - 0, - ue->frame_parms.Nid_cell, - dlsch1->rnti); + dlsch1->harq_processes[harq_pid]->G, + 0, + ue->frame_parms.Nid_cell, + dlsch1->rnti); #if UE_TIMING_TRACE stop_meas(&ue->dlsch_unscrambling_stats); #endif @@ -3487,31 +3485,31 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, #ifdef UE_DLSCH_PARALLELISATION ret1 = nr_dlsch_decoding_mthread(ue, - proc, - eNB_id, - pdsch_vars->llr[1], - &ue->frame_parms, - dlsch1, - dlsch1->harq_processes[harq_pid], - frame_rx, - nb_symb_sch, - nr_tti_rx, - harq_pid, - pdsch==PDSCH?1:0, - dlsch1->harq_processes[harq_pid]->TBS>256?1:0); + proc, + eNB_id, + pdsch_vars->llr[1], + &ue->frame_parms, + dlsch1, + dlsch1->harq_processes[harq_pid], + frame_rx, + nb_symb_sch, + nr_tti_rx, + harq_pid, + pdsch==PDSCH?1:0, + dlsch1->harq_processes[harq_pid]->TBS>256?1:0); LOG_T(PHY,"UE_DLSCH_PARALLELISATION is defined, ret1 = %d\n", ret1); #else ret1 = nr_dlsch_decoding(ue, - pdsch_vars->llr[1], - &ue->frame_parms, - dlsch1, - dlsch1->harq_processes[harq_pid], - frame_rx, - nb_symb_sch, - nr_tti_rx, - harq_pid, - pdsch==PDSCH?1:0,//proc->decoder_switch, - dlsch1->harq_processes[harq_pid]->TBS>256?1:0); + pdsch_vars->llr[1], + &ue->frame_parms, + dlsch1, + dlsch1->harq_processes[harq_pid], + frame_rx, + nb_symb_sch, + nr_tti_rx, + harq_pid, + pdsch==PDSCH?1:0,//proc->decoder_switch, + dlsch1->harq_processes[harq_pid]->TBS>256?1:0); LOG_T(PHY,"UE_DLSCH_PARALLELISATION is NOT defined, ret1 = %d\n", ret1); printf("start cw1 dlsch decoding\n"); #endif @@ -3533,45 +3531,46 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, #endif LOG_I(PHY,"AbsSubframe %d.%d --> ldpc Decoding for CW1 %5.3f\n", frame_rx%1024, nr_tti_rx,(ue->dlsch_decoding_stats[ue->current_thread_id[nr_tti_rx]].p_time)/(cpuf*1000.0)); + + LOG_D(PHY, "harq_pid: %d, TBS expected dlsch1: %d \n", harq_pid, dlsch1->harq_processes[harq_pid]->TBS); } LOG_D(PHY," ------ end ldpc decoder for AbsSubframe %d.%d ------ \n", frame_rx, nr_tti_rx); - - LOG_D(PHY, "harq_pid: %d, TBS expected dlsch0: %d, TBS expected dlsch1: %d \n",harq_pid, dlsch0->harq_processes[harq_pid]->TBS, dlsch1->harq_processes[harq_pid]->TBS); + LOG_D(PHY, "harq_pid: %d, TBS expected dlsch0: %d \n",harq_pid, dlsch0->harq_processes[harq_pid]->TBS); if(retmax_ldpc_iterations+1){ - // fill dl_indication message - dl_indication.module_id = ue->Mod_id; - dl_indication.cc_id = ue->CC_id; - dl_indication.gNB_index = eNB_id; - dl_indication.frame = frame_rx; - dl_indication.slot = nr_tti_rx; - dl_indication.rx_ind = &rx_ind; // hang on rx_ind instance - dl_indication.proc=proc; + // fill dl_indication message + dl_indication.module_id = ue->Mod_id; + dl_indication.cc_id = ue->CC_id; + dl_indication.gNB_index = eNB_id; + dl_indication.frame = frame_rx; + dl_indication.slot = nr_tti_rx; + dl_indication.rx_ind = &rx_ind; // hang on rx_ind instance + dl_indication.proc=proc; - //dl_indication.rx_ind->number_pdus - switch (pdsch) { - case RA_PDSCH: - rx_ind.rx_indication_body[0].pdu_type = FAPI_NR_RX_PDU_TYPE_RAR; - break; - case PDSCH: - rx_ind.rx_indication_body[0].pdu_type = FAPI_NR_RX_PDU_TYPE_DLSCH; - break; - default: - break; - } + //dl_indication.rx_ind->number_pdus + switch (pdsch) { + case RA_PDSCH: + rx_ind.rx_indication_body[0].pdu_type = FAPI_NR_RX_PDU_TYPE_RAR; + break; + case PDSCH: + rx_ind.rx_indication_body[0].pdu_type = FAPI_NR_RX_PDU_TYPE_DLSCH; + break; + default: + break; + } - rx_ind.rx_indication_body[0].pdsch_pdu.pdu = dlsch0->harq_processes[harq_pid]->b; - rx_ind.rx_indication_body[0].pdsch_pdu.pdu_length = dlsch0->harq_processes[harq_pid]->TBS>>3; - LOG_D(PHY, "PDU length in bits: %d, in bytes: %d \n", dlsch0->harq_processes[harq_pid]->TBS, rx_ind.rx_indication_body[0].pdsch_pdu.pdu_length); - rx_ind.number_pdus = 1; + rx_ind.rx_indication_body[0].pdsch_pdu.pdu = dlsch0->harq_processes[harq_pid]->b; + rx_ind.rx_indication_body[0].pdsch_pdu.pdu_length = dlsch0->harq_processes[harq_pid]->TBS>>3; + LOG_D(PHY, "PDU length in bits: %d, in bytes: %d \n", dlsch0->harq_processes[harq_pid]->TBS, rx_ind.rx_indication_body[0].pdsch_pdu.pdu_length); + rx_ind.number_pdus = 1; - //ue->dl_indication.rx_ind = &dlsch1->harq_processes[harq_pid]->b; //no data, only dci for now - dl_indication.dci_ind = NULL; //&ue->dci_ind; - // send to mac - if (ue->if_inst && ue->if_inst->dl_indication) - ue->if_inst->dl_indication(&dl_indication, ul_time_alignment); + //ue->dl_indication.rx_ind = &dlsch1->harq_processes[harq_pid]->b; //no data, only dci for now + dl_indication.dci_ind = NULL; //&ue->dci_ind; + // send to mac + if (ue->if_inst && ue->if_inst->dl_indication) + ue->if_inst->dl_indication(&dl_indication, ul_time_alignment); } // TODO CRC check for CW0 @@ -4026,18 +4025,13 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, int nr_tti_rx = proc->nr_tti_rx; int slot_pbch; NR_UE_PDCCH *pdcch_vars = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][0]; - NR_UE_DLSCH_t **dlsch = ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id]; fapi_nr_config_request_t *cfg = &ue->nrUE_config; - uint8_t harq_pid = ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->current_harq_pid; - NR_DL_UE_HARQ_t *dlsch0_harq = dlsch[0]->harq_processes[harq_pid]; - uint16_t nb_symb_sch = dlsch0_harq->nb_symbols; - uint16_t start_symb_sch = dlsch0_harq->start_symbol; uint8_t nb_symb_pdcch = pdcch_vars->nb_search_space > 0 ? pdcch_vars->pdcch_config[0].coreset.duration : 0; uint8_t dci_cnt = 0; NR_DL_FRAME_PARMS *fp = &ue->frame_parms; - + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_RX, VCD_FUNCTION_IN); - + LOG_D(PHY," ****** start RX-Chain for Frame.Slot %d.%d ****** \n", frame_rx%1024, nr_tti_rx); /* @@ -4045,7 +4039,6 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, uint8_t next2_thread_id = next1_thread_id== (RX_NB_TH-1) ? 0:(next1_thread_id+1); */ - int coreset_nb_rb=0; int coreset_start_rb=0; if (pdcch_vars->nb_search_space > 0) @@ -4080,12 +4073,12 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, if (ue->no_timing_correction==0) { LOG_I(PHY,"start adjust sync slot = %d no timing %d\n", nr_tti_rx, ue->no_timing_correction); nr_adjust_synch_ue(fp, - ue, - eNB_id, + ue, + eNB_id, frame_rx, - nr_tti_rx, - 0, - 16384); + nr_tti_rx, + 0, + 16384); } } @@ -4100,10 +4093,10 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, #endif VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_SLOT_FEP, VCD_FUNCTION_IN); nr_slot_fep(ue, - l, - nr_tti_rx, - 0, - 0); + l, + nr_tti_rx, + 0, + 0); // note: this only works if RBs for PDCCH are contigous! LOG_D(PHY,"pdcch_channel_estimation: first_carrier_offset %d, BWPStart %d, coreset_start_rb %d\n", @@ -4130,40 +4123,40 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, if (dci_cnt > 0) { - LOG_D(PHY,"[UE %d] Frame %d, nr_tti_rx %d: found %d DCIs\n",ue->Mod_id,frame_rx,nr_tti_rx,dci_cnt); + LOG_D(PHY,"[UE %d] Frame %d, nr_tti_rx %d: found %d DCIs\n", ue->Mod_id, frame_rx, nr_tti_rx, dci_cnt); - } else { - LOG_D(PHY,"[UE %d] Frame %d, nr_tti_rx %d: No DCIs found\n",ue->Mod_id,frame_rx,nr_tti_rx); - } -#endif //NR_PDCCH_SCHED + NR_UE_DLSCH_t *dlsch; + if (ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->active == 1){ + dlsch = ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]; + } else if (ue->dlsch_ra[0]->active == 1){ + dlsch = ue->dlsch_ra[0]; + } + uint8_t harq_pid = dlsch->current_harq_pid; + NR_DL_UE_HARQ_t *dlsch0_harq = dlsch->harq_processes[harq_pid]; + uint16_t nb_symb_sch = dlsch0_harq->nb_symbols; + uint16_t start_symb_sch = dlsch0_harq->start_symbol; + int symb_dmrs = -1; - - if (dci_cnt > 0){ LOG_D(PHY," ------ --> PDSCH ChannelComp/LLR Frame.slot %d.%d ------ \n", frame_rx%1024, nr_tti_rx); //to update from pdsch config - start_symb_sch = dlsch0_harq->start_symbol; - int symb_dmrs=-1; + for (int i=0;i<4;i++) if (((1<dlDmrsSymbPos) > 0) {symb_dmrs=i;break;} AssertFatal(symb_dmrs>=0,"no dmrs in 0..3\n"); LOG_D(PHY,"Initializing dmrs for symb %d DMRS mask %x\n",symb_dmrs,dlsch0_harq->dlDmrsSymbPos); nr_gold_pdsch(ue,symb_dmrs,0, 1); - - nb_symb_sch = dlsch0_harq->nb_symbols; for (uint16_t m=start_symb_sch;m<(nb_symb_sch+start_symb_sch) ; m++){ nr_slot_fep(ue, - m, //to be updated from higher layer - nr_tti_rx, - 0, - 0); - - + m, //to be updated from higher layer + nr_tti_rx, + 0, + 0); } - //set active for testing, to be removed - ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->active = 1; + } else { + LOG_D(PHY,"[UE %d] Frame %d, nr_tti_rx %d: No DCIs found\n",ue->Mod_id,frame_rx,nr_tti_rx); } - else - ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->active = 0; + +#endif //NR_PDCCH_SCHED #if UE_TIMING_TRACE start_meas(&ue->generic_stat); @@ -4540,7 +4533,7 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t ue->tx_power_dBm[nr_tti_tx] = prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER + pathloss; } - LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_tx %d : Generating PRACH, preamble %d, PL %d, P0_PRACH %d, TARGET_RECEIVED_POWER %d dBm, RA-RNTI %d\n", + LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_tx %d : Generating PRACH, preamble %d, PL %d, P0_PRACH %d, TARGET_RECEIVED_POWER %d dBm, RA-RNTI %x\n", ue->Mod_id, frame_tx, nr_tti_tx, diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c index 2155374512..61cf7332b2 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c @@ -36,6 +36,7 @@ #include "LAYER2/NR_MAC_UE/mac_extern.h" #include "mac_defs.h" #include "common/utils/nr/nr_common.h" +#include "executables/softmodem-common.h" #include #ifdef NR_PDCCH_DCI_TOOLS_DEBUG @@ -104,7 +105,7 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_ AssertFatal(mac->ULbwp[0]->bwp_Dedicated!=NULL,"bwp_Dedicated is null\n"); } // check search spaces - + int ss_id=0; fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15; int sps =mac->DLbwp[0]->bwp_Common->genericParameters.cyclicPrefix == NULL ? 14 : 12; @@ -120,18 +121,31 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_ if (mac->ra_state == WAIT_RAR) { // check for RAR rel15 = &dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15; - rel15->rnti = 2;//get_RA_RNTI(mac,frame,slot); // WIP - dl_config->number_pdus = dl_config->number_pdus + 1; + // rel15->rnti = 2;//get_RA_RNTI(mac,frame,slot); // WIP } else if (mac->ra_state == WAIT_CONTENTION_RESOLUTION) { rel15 = &dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15; rel15->rnti = mac->t_crnti; - dl_config->number_pdus = dl_config->number_pdus + 1; + //dl_config->number_pdus = dl_config->number_pdus + 1; } if (mac->crnti>0) { rel15 = &dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15; - rel15->rnti = mac->crnti; - rel15->BWPSize = NRRIV2BW(mac->DLbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275); + + if (get_softmodem_params()->do_ra == 1) + rel15->rnti = 0x00; + else // phy_test + rel15->rnti = mac->crnti; + + rel15->dci_format = NR_DL_DCI_FORMAT_1_0; + + if (slot == 0 || slot == 1){ + rel15->BWPSize = NRRIV2BW(mac->DLbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275); + rel15->dci_length = nr_dci_size(rel15->dci_format, NR_RNTI_C, rel15->BWPSize); + } else if (slot == 7){ + rel15->BWPSize = NRRIV2BW(mac->scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, 275); + rel15->dci_length = nr_dci_size(rel15->dci_format, NR_RNTI_RA, rel15->BWPSize); + } + rel15->BWPStart = NRRIV2PRBOFFSET(mac->DLbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275); rel15->SubcarrierSpacing = mac->DLbwp[0]->bwp_Common->genericParameters.subcarrierSpacing; // get UE-specific search space @@ -166,19 +180,15 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_ } rel15->coreset.CoreSetType = 1; rel15->coreset.precoder_granularity = mac->coreset[0][0]->precoderGranularity; + if (mac->coreset[0][0]->pdcch_DMRS_ScramblingID) rel15->coreset.pdcch_dmrs_scrambling_id = *mac->coreset[0][0]->pdcch_DMRS_ScramblingID; else rel15->coreset.pdcch_dmrs_scrambling_id = *mac->scc->physCellId; + fill_dci_search_candidates(mac->SSpace[0][0][ss_id],rel15); - rel15->dci_format = NR_DL_DCI_FORMAT_1_0; - rel15->dci_length = nr_dci_size(rel15->dci_format,NR_RNTI_C,rel15->BWPSize); dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI; dl_config->number_pdus = dl_config->number_pdus + 1; } } } - - - - diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 39b75669b4..6cf0d68a62 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -2622,7 +2622,11 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr dlsch_config_pdu_1_0->pucch_resource_id, dlsch_config_pdu_1_0->pdsch_to_harq_feedback_time_ind); - dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH; + if (mac->ra_rnti == rnti) + dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_RA_DLSCH; + else + dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH; + // dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP = n_RB_DLBWP; LOG_D(MAC,"(nr_ue_procedures.c) pdu_type=%d\n\n",dl_config->dl_config_list[dl_config->number_pdus].pdu_type); From acfad36f1a2698aaba527eeceddb9da673497b00 Mon Sep 17 00:00:00 2001 From: cig Date: Wed, 22 Apr 2020 18:28:35 +0200 Subject: [PATCH 186/553] Code cleanup: - restructured nr_pdcch_unscrambling function - minor cleanups - formatting --- openair1/PHY/NR_TRANSPORT/nr_dci.c | 6 +-- openair1/PHY/NR_UE_TRANSPORT/dci_nr.c | 41 ++++++++++--------- .../NR_UE_TRANSPORT/nr_transport_proto_ue.h | 10 ++--- 3 files changed, 30 insertions(+), 27 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.c b/openair1/PHY/NR_TRANSPORT/nr_dci.c index 812c49d6f6..8508621ae5 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.c @@ -131,13 +131,13 @@ uint16_t nr_get_dci_size(nfapi_nr_dci_format_e format, void nr_pdcch_scrambling(uint32_t *in, uint32_t size, uint32_t Nid, - uint32_t n_RNTI, + uint32_t scrambling_RNTI, uint32_t *out) { uint8_t reset; uint32_t x1, x2, s=0; reset = 1; - x2 = (n_RNTI<<16) + Nid; - LOG_D(PHY,"PDCCH Scrambling x2 %x : n_RNTI %x\n",x2,n_RNTI); + x2 = (scrambling_RNTI<<16) + Nid; + LOG_D(PHY,"PDCCH Scrambling x2 %x : scrambling_RNTI %x \n", x2, scrambling_RNTI); for (int i=0; inumber_of_candidates;j++) { - LOG_D(PHY,"Trying DCI candidate %d, CCE %d (%d), L %d\n",j,rel15->CCE[j],rel15->CCE[j]*9*6*2,rel15->L[j]); int CCEind = rel15->CCE[j]; int L = rel15->L[j]; uint64_t dci_estimation[2]= {0}; - const t_nrPolar_params *currentPtrDCI=nr_polar_params(1, dci_length, L,1,&ue->polarList); + const t_nrPolar_params *currentPtrDCI = nr_polar_params(NR_POLAR_DCI_MESSAGE_TYPE, dci_length, L, 1, &ue->polarList); - nr_pdcch_unscrambling(rel15->rnti, - &ue->frame_parms, - slot, - &pdcch_vars->e_rx[CCEind*108], - tmp_e, - L*108, - // get_nCCE(n_pdcch_symbols, frame_parms, mi) * 72, - rel15->coreset.pdcch_dmrs_scrambling_id); + LOG_D(PHY, "Trying DCI candidate %d, CCE %d (%d), L %d\n", j, CCEind, CCEind*9*6*2, L); + + nr_pdcch_unscrambling(&pdcch_vars->e_rx[CCEind*108], rel15->rnti, L*108, rel15->coreset.pdcch_dmrs_scrambling_id, tmp_e); + + #ifdef DEBUG_DCI_DECODING + uint32_t * z = (uint32_t *) &pdcch_vars->e_rx[CCEind*108]; + for (int index_z = 0; index_z < 96; index_z++){ + for (int i=0; i<9; i++) { + LOG_D(PHY,"z[%d]=(%d,%d) \n", (9*index_z + i), *(int16_t *) &z[index_z + i],*(1 + (int16_t *) &z[index_z + i])); + } + } + #endif uint16_t crc = polar_decoder_int16(tmp_e, dci_estimation, diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h index 8dbe588cb8..38781d7b7e 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h @@ -1524,11 +1524,11 @@ uint8_t get_num_pdcch_symbols(uint8_t num_dci,DCI_ALLOC_t *dci_alloc,NR_DL_FRAME void pdcch_interleaving(NR_DL_FRAME_PARMS *frame_parms,int32_t **z, int32_t **wbar,uint8_t n_symbols_pdcch,uint8_t mi); -void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8_t slot, - int16_t *z, int16_t *z2,uint32_t length, uint16_t pdcch_DMRS_scrambling_id); - - - +void nr_pdcch_unscrambling(int16_t *z, + uint16_t scrambling_RNTI, + uint32_t length, + uint16_t pdcch_DMRS_scrambling_id, + int16_t *z2); void dlsch_unscrambling(NR_DL_FRAME_PARMS *frame_parms, int mbsfn_flag, From c56854afe4f393a9e79f8bd38d96717115ae912f Mon Sep 17 00:00:00 2001 From: cig Date: Wed, 22 Apr 2020 18:31:48 +0200 Subject: [PATCH 187/553] Set proper polar rnti and scrambling rnti for the phy-test and do-ra running modes: - in phy-test both rnti are set to same rnti - in do-ra the scrambling rnti is set to 0 while the polar rnti is the RA_rnti (computed as per TS 38.321) --- openair1/PHY/NR_UE_TRANSPORT/dci_nr.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c b/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c index f3faec2ea2..adc619825a 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c +++ b/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c @@ -29,11 +29,15 @@ * \note * \warning */ + #ifdef USER_MODE #include #include #include #endif + +#include "executables/softmodem-common.h" + #include "nr_transport_proto_ue.h" #include "PHY/CODING/nrPolar_tools/nr_polar_dci_defs.h" #include "PHY/phy_extern_nr_ue.h" @@ -842,7 +846,9 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue, rel15 = &pdcch_vars->pdcch_config[i]; int dci_length = rel15->dci_length; + int gNB_id = 0; int16_t tmp_e[16*108]; + rnti_t n_rnti; for (int j=0;jnumber_of_candidates;j++) { int CCEind = rel15->CCE[j]; @@ -850,7 +856,7 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue, uint64_t dci_estimation[2]= {0}; const t_nrPolar_params *currentPtrDCI = nr_polar_params(NR_POLAR_DCI_MESSAGE_TYPE, dci_length, L, 1, &ue->polarList); - LOG_D(PHY, "Trying DCI candidate %d, CCE %d (%d), L %d\n", j, CCEind, CCEind*9*6*2, L); + LOG_D(PHY, "Trying DCI candidate %d of %d number of candidates, CCE %d (%d), L %d\n", j, rel15->number_of_candidates, CCEind, CCEind*9*6*2, L); nr_pdcch_unscrambling(&pdcch_vars->e_rx[CCEind*108], rel15->rnti, L*108, rel15->coreset.pdcch_dmrs_scrambling_id, tmp_e); @@ -867,16 +873,24 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue, dci_estimation, 1, currentPtrDCI); - LOG_D(PHY,"Decoded crc %x\n",crc); - if (crc == rel15->rnti) { + + if (get_softmodem_params()->do_ra == 1) + n_rnti = ue->prach_resources[gNB_id]->ra_RNTI; + else + n_rnti = rel15->rnti; + + if (crc == n_rnti) { + LOG_D(PHY,"Decoded crc %x matches rnti %x for DCI format %d\n", crc, n_rnti, rel15->dci_format); dci_ind->SFN = frame; dci_ind->slot = slot; - dci_ind->dci_list[dci_ind->number_of_dcis].rnti = rel15->rnti; + dci_ind->dci_list[dci_ind->number_of_dcis].rnti = n_rnti; dci_ind->dci_list[dci_ind->number_of_dcis].n_CCE = CCEind; dci_ind->dci_list[dci_ind->number_of_dcis].dci_format = rel15->dci_format; dci_ind->dci_list[dci_ind->number_of_dcis].payloadSize = dci_length; memcpy((void*)dci_ind->dci_list[dci_ind->number_of_dcis].payloadBits,(void*)dci_estimation,8); dci_ind->number_of_dcis++; + } else { + LOG_D(PHY,"Decoded crc %x does not match rnti %x for DCI format %d\n", crc, n_rnti, rel15->dci_format); } } } From f27649431721d5c673d20f65b458e57a90c4b399 Mon Sep 17 00:00:00 2001 From: cig Date: Wed, 22 Apr 2020 18:49:38 +0200 Subject: [PATCH 188/553] Completed dlsch demodulation for RA PDSCH --- .../NR_UE_TRANSPORT/nr_dlsch_demodulation.c | 108 +++++++++--------- 1 file changed, 56 insertions(+), 52 deletions(-) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c index c38deaff2d..b532dea3c7 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c @@ -132,7 +132,7 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, unsigned short nb_rb = 0, round; int avgs = 0;// rb; - NR_DL_UE_HARQ_t *dlsch0_harq,*dlsch1_harq = 0; + NR_DL_UE_HARQ_t *dlsch0_harq, *dlsch1_harq = NULL; uint8_t beamforming_mode; @@ -157,82 +157,87 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, int32_t median[16]; uint32_t len; - switch (type) { case SI_PDSCH: pdsch_vars = ue->pdsch_vars_SI; dlsch = &ue->dlsch_SI[eNB_id]; dlsch0_harq = dlsch[0]->harq_processes[harq_pid]; - beamforming_mode = 0; + beamforming_mode = 0; break; case RA_PDSCH: pdsch_vars = ue->pdsch_vars_ra; dlsch = &ue->dlsch_ra[eNB_id]; dlsch0_harq = dlsch[0]->harq_processes[harq_pid]; - beamforming_mode = 0; + beamforming_mode = 0; + break; case PDSCH: pdsch_vars = ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]]; dlsch = ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id]; - dlsch[0]->harq_processes[harq_pid]->Qm = nr_get_Qm_dl(dlsch[0]->harq_processes[harq_pid]->mcs, dlsch[0]->harq_processes[harq_pid]->mcs_table); - dlsch[0]->harq_processes[harq_pid]->R = nr_get_code_rate_dl(dlsch[0]->harq_processes[harq_pid]->mcs, dlsch[0]->harq_processes[harq_pid]->mcs_table); - + beamforming_mode = ue->transmission_mode[eNB_id] < 7 ? 0 :ue->transmission_mode[eNB_id]; + + dlsch0_harq = dlsch[0]->harq_processes[harq_pid]; + dlsch1_harq = dlsch[1]->harq_processes[harq_pid]; + //printf("status TB0 = %d, status TB1 = %d \n", dlsch[0]->harq_processes[harq_pid]->status, dlsch[1]->harq_processes[harq_pid]->status); - LOG_D(PHY,"AbsSubframe %d.%d / Sym %d harq_pid %d, harq status %d.%d \n", - frame,nr_tti_rx,symbol,harq_pid, - dlsch[0]->harq_processes[harq_pid]->status, - dlsch[1]->harq_processes[harq_pid]->status); - - if ((dlsch[0]->harq_processes[harq_pid]->status == ACTIVE) && - (dlsch[1]->harq_processes[harq_pid]->status == ACTIVE)){ - codeword_TB0 = dlsch[0]->harq_processes[harq_pid]->codeword; - codeword_TB1 = dlsch[1]->harq_processes[harq_pid]->codeword; + LOG_D(PHY,"AbsSubframe %d.%d / Sym %d harq_pid %d, harq status %d.%d \n", frame, nr_tti_rx, symbol, harq_pid, dlsch0_harq->status, dlsch1_harq->status); + + if ((dlsch0_harq->status == ACTIVE) && (dlsch1_harq->status == ACTIVE)){ + codeword_TB0 = dlsch0_harq->codeword; + codeword_TB1 = dlsch1_harq->codeword; dlsch0_harq = dlsch[codeword_TB0]->harq_processes[harq_pid]; dlsch1_harq = dlsch[codeword_TB1]->harq_processes[harq_pid]; -#ifdef DEBUG_HARQ - printf("[DEMOD] I am assuming both TBs are active\n"); -#endif - } - else if ((dlsch[0]->harq_processes[harq_pid]->status == ACTIVE) && - (dlsch[1]->harq_processes[harq_pid]->status != ACTIVE) ) { - codeword_TB0 = dlsch[0]->harq_processes[harq_pid]->codeword; + + #ifdef DEBUG_HARQ + printf("[DEMOD] I am assuming both TBs are active\n"); + #endif + + } else if ((dlsch0_harq->status == ACTIVE) && (dlsch1_harq->status != ACTIVE) ) { + codeword_TB0 = dlsch0_harq->codeword; + codeword_TB1 = -1; dlsch0_harq = dlsch[0]->harq_processes[harq_pid]; dlsch1_harq = NULL; - codeword_TB1 = -1; -#ifdef DEBUG_HARQ - printf("[DEMOD] I am assuming only TB0 is active\n"); -#endif - } - else if ((dlsch[0]->harq_processes[harq_pid]->status != ACTIVE) && - (dlsch[1]->harq_processes[harq_pid]->status == ACTIVE) ){ - codeword_TB1 = dlsch[1]->harq_processes[harq_pid]->codeword; - dlsch0_harq = dlsch[1]->harq_processes[harq_pid]; - dlsch1_harq = NULL; + + #ifdef DEBUG_HARQ + printf("[DEMOD] I am assuming only TB0 is active\n"); + #endif + + } else if ((dlsch0_harq->status != ACTIVE) && (dlsch1_harq->status == ACTIVE)){ codeword_TB0 = -1; -#ifdef DEBUG_HARQ - printf("[DEMOD] I am assuming only TB1 is active, it is in cw %d\n", dlsch0_harq->codeword); -#endif - } - else { - LOG_E(PHY,"[UE][FATAL] nr_tti_rx %d: no active DLSCH\n",nr_tti_rx); + codeword_TB1 = dlsch1_harq->codeword; + dlsch0_harq = NULL; + dlsch1_harq = dlsch[1]->harq_processes[codeword_TB1]; + + #ifdef DEBUG_HARQ + printf("[DEMOD] I am assuming only TB1 is active, it is in cw %d\n", dlsch0_harq->codeword); + #endif + + AssertFatal(1 == 0, "[UE][FATAL] DLSCH: TB0 not active and TB1 active case is not supported %d\n"); + + } else { + LOG_E(PHY,"[UE][FATAL] nr_tti_rx %d: no active DLSCH\n", nr_tti_rx); return(-1); } - beamforming_mode = ue->transmission_mode[eNB_id]<7?0:ue->transmission_mode[eNB_id]; - break; - - default: - AssertFatal(1==0,"[UE][FATAL] nr_tti_rx %d: Unknown PDSCH format %d\n",nr_tti_rx,type); - return(-1); - break; + + break; + + default: + AssertFatal(1 == 0, "[UE][FATAL] nr_tti_rx %d: Unknown PDSCH format %d\n", nr_tti_rx, type); + return(-1); + break; + } -#ifdef DEBUG_HARQ - printf("[DEMOD] MIMO mode = %d\n", dlsch0_harq->mimo_mode); - printf("[DEMOD] cw for TB0 = %d, cw for TB1 = %d\n", codeword_TB0, codeword_TB1); -#endif - + dlsch0_harq->Qm = nr_get_Qm_dl(dlsch[0]->harq_processes[harq_pid]->mcs, dlsch[0]->harq_processes[harq_pid]->mcs_table); + dlsch0_harq->R = nr_get_code_rate_dl(dlsch[0]->harq_processes[harq_pid]->mcs, dlsch[0]->harq_processes[harq_pid]->mcs_table); + + #ifdef DEBUG_HARQ + printf("[DEMOD] MIMO mode = %d\n", dlsch0_harq->mimo_mode); + printf("[DEMOD] cw for TB0 = %d, cw for TB1 = %d\n", codeword_TB0, codeword_TB1); + #endif + start_rb = dlsch0_harq->start_rb; nb_rb_pdsch = dlsch0_harq->nb_rb; @@ -270,7 +275,6 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, return(-1); } - if (dlsch0_harq->mimo_mode==NR_DUALSTREAM) { DevAssert(dlsch1_harq); } From 32af60bcf5ffc296b288db376a6539ad80b15352 Mon Sep 17 00:00:00 2001 From: cig Date: Wed, 22 Apr 2020 19:49:08 +0200 Subject: [PATCH 189/553] UE RA procedures changes to preamble selection: - get preamble from rach_ConfigDedicated in contention free mode - do preamble selection only in prach slot --- openair2/LAYER2/NR_MAC_UE/config_ue.c | 1 + openair2/LAYER2/NR_MAC_UE/mac_defs.h | 1 + openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 268 ++++++++++--------- 3 files changed, 142 insertions(+), 128 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_UE/config_ue.c b/openair2/LAYER2/NR_MAC_UE/config_ue.c index 758de4f4af..f50c15df50 100755 --- a/openair2/LAYER2/NR_MAC_UE/config_ue.c +++ b/openair2/LAYER2/NR_MAC_UE/config_ue.c @@ -350,6 +350,7 @@ int nr_rrc_mac_config_req_ue( if(spCell_ConfigP != NULL ){ mac->servCellIndex = *spCell_ConfigP->servCellIndex; if (spCell_ConfigP->reconfigurationWithSync) { + mac->rach_ConfigDedicated = spCell_ConfigP->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink; mac->scc = spCell_ConfigP->reconfigurationWithSync->spCellConfigCommon; config_common_ue(mac,module_id,cc_idP); mac->crnti = spCell_ConfigP->reconfigurationWithSync->newUE_Identity; diff --git a/openair2/LAYER2/NR_MAC_UE/mac_defs.h b/openair2/LAYER2/NR_MAC_UE/mac_defs.h index c64c518cee..64dd241499 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_defs.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_defs.h @@ -156,6 +156,7 @@ typedef struct { NR_ServingCellConfigCommon_t *scc; NR_ServingCellConfig_t *scd; + NR_RACH_ConfigDedicated_t *rach_ConfigDedicated; int servCellIndex; //// MAC config NR_DRX_Config_t *drx_Config; diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c index 00eaa56855..a5e1c72c93 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -88,6 +88,10 @@ void nr_get_prach_resources(module_id_t mod_id, int messagePowerOffsetGroupB, messageSizeGroupA, PLThreshold, sizeOfRA_PreamblesGroupA, numberOfRA_Preambles, i, deltaPreamble_Msg3; uint8_t noGroupB = 0, s_id, f_id, ul_carrier_id, prach_ConfigIndex, SFN_nbr, Msg3_size; + AssertFatal(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); + nr_rach_ConfigCommon = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup; + rach_ConfigGeneric = &nr_rach_ConfigCommon->rach_ConfigGeneric; + // NR_RSRP_Range_t rsrp_ThresholdSSB; // todo /////////////////////////////////////////////////////////// @@ -104,138 +108,140 @@ void nr_get_prach_resources(module_id_t mod_id, // -- RA initiated for SI request: // --- SSB selection, set prach_resources->ra_PreambleIndex - // if (rach_ConfigDedicated) { // This is for network controlled Mobility - // // operation for contention-free RA resources when: - // // - available SSB with SS-RSRP above rsrp-ThresholdSSB: SSB selection - // // - availalbe CSI-RS with CSI-RSRP above rsrp-ThresholdCSI-RS: CSI-RS selection - // prach_resources->ra_PreambleIndex = rach_ConfigDedicated->ra_PreambleIndex; - // } - - //////////* Contention-based RA preamble selection *////////// - // todo: - // - selection of SSB with SS-RSRP above rsrp-ThresholdSSB else select any SSB - // - todo determine next available PRACH occasion - - // rsrp_ThresholdSSB = *nr_rach_ConfigCommon->rsrp_ThresholdSSB; - - AssertFatal(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); - - nr_rach_ConfigCommon = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup; - rach_ConfigGeneric = &nr_rach_ConfigCommon->rach_ConfigGeneric; - - Msg3_size = mac->RA_Msg3_size; - - numberOfRA_Preambles = 64; - if(nr_rach_ConfigCommon->totalNumberOfRA_Preambles != NULL) - numberOfRA_Preambles = *(nr_rach_ConfigCommon->totalNumberOfRA_Preambles); - - if (!nr_rach_ConfigCommon->groupBconfigured) { - noGroupB = 1; + if (rach_ConfigDedicated) { + //////////* Contention free RA *////////// + // - the PRACH preamble for the UE to transmit is set through RRC configuration + // - this is the default mode in current implementation! + // Operation for contention-free RA resources when: + // - available SSB with SS-RSRP above rsrp-ThresholdSSB: SSB selection + // - available CSI-RS with CSI-RSRP above rsrp-ThresholdCSI-RS: CSI-RS selection + // - network controlled Mobility + uint8_t cfra_ssb_resource_idx = 0; + prach_resources->ra_PreambleIndex = rach_ConfigDedicated->cfra->resources.choice.ssb->ssb_ResourceList.list.array[cfra_ssb_resource_idx]->ra_PreambleIndex; + LOG_D(MAC, "[RAPROC] - Selected RA preamble index %d for contention-free random access procedure... \n", prach_resources->ra_PreambleIndex); } else { - // RA preambles group B is configured - // - Defining the number of RA preambles in RA Preamble Group A for each SSB */ - sizeOfRA_PreamblesGroupA = nr_rach_ConfigCommon->groupBconfigured->numberOfRA_PreamblesGroupA; - switch (nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA){ - /* - Threshold to determine the groups of RA preambles */ - case 0: - messageSizeGroupA = 56; - break; - case 1: - messageSizeGroupA = 144; - break; - case 2: - messageSizeGroupA = 208; - break; - case 3: - messageSizeGroupA = 256; - break; - case 4: - messageSizeGroupA = 282; - break; - case 5: - messageSizeGroupA = 480; - break; - case 6: - messageSizeGroupA = 640; - break; - case 7: - messageSizeGroupA = 800; - break; - case 8: - messageSizeGroupA = 1000; - break; - case 9: - messageSizeGroupA = 72; - break; - default: - AssertFatal(1 == 0,"Unknown ra_Msg3SizeGroupA %lu\n", nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA); - /* todo cases 10 -15*/ - } + //////////* Contention-based RA preamble selection *////////// + // todo: + // - selection of SSB with SS-RSRP above rsrp-ThresholdSSB else select any SSB + // - todo determine next available PRACH occasion - /* Power offset for preamble selection in dB */ - messagePowerOffsetGroupB = -9999; - switch (nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB){ - case 0: - messagePowerOffsetGroupB = -9999; - break; - case 1: - messagePowerOffsetGroupB = 0; - break; - case 2: - messagePowerOffsetGroupB = 5; - break; - case 3: - messagePowerOffsetGroupB = 8; - break; - case 4: - messagePowerOffsetGroupB = 10; - break; - case 5: - messagePowerOffsetGroupB = 12; - break; - case 6: - messagePowerOffsetGroupB = 15; - break; - case 7: - messagePowerOffsetGroupB = 18; - break; - default: - AssertFatal(1 == 0,"Unknown messagePowerOffsetGroupB %lu\n", nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB); - } + // rsrp_ThresholdSSB = *nr_rach_ConfigCommon->rsrp_ThresholdSSB; - // todo Msg3-DeltaPreamble should be provided from higher layers, otherwise is 0 - mac->deltaPreamble_Msg3 = 0; - deltaPreamble_Msg3 = mac->deltaPreamble_Msg3; - } + Msg3_size = mac->RA_Msg3_size; - PLThreshold = prach_resources->RA_PCMAX - rach_ConfigGeneric->preambleReceivedTargetPower - deltaPreamble_Msg3 - messagePowerOffsetGroupB; + numberOfRA_Preambles = 64; + if(nr_rach_ConfigCommon->totalNumberOfRA_Preambles != NULL) + numberOfRA_Preambles = *(nr_rach_ConfigCommon->totalNumberOfRA_Preambles); - /* Msg3 has not been transmitted yet */ - if (first_Msg3 == 1) { - if (noGroupB == 1) { - // use Group A preamble - prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles; - mac->RA_usedGroupA = 1; - } else if ((Msg3_size < messageSizeGroupA) && (get_nr_PL(mod_id, CC_id, gNB_id) > PLThreshold)) { - // Group B is configured and RA preamble Group A is used - // - todo add condition on CCCH_sdu_size for initiation by CCCH - prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; - mac->RA_usedGroupA = 1; + if (!nr_rach_ConfigCommon->groupBconfigured) { + noGroupB = 1; } else { - // Group B preamble is configured and used - // the first sizeOfRA_PreamblesGroupA RA preambles belong to RA Preambles Group A - // the remaining belong to RA Preambles Group B - prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); - mac->RA_usedGroupA = 0; + // RA preambles group B is configured + // - Defining the number of RA preambles in RA Preamble Group A for each SSB */ + sizeOfRA_PreamblesGroupA = nr_rach_ConfigCommon->groupBconfigured->numberOfRA_PreamblesGroupA; + switch (nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA){ + /* - Threshold to determine the groups of RA preambles */ + case 0: + messageSizeGroupA = 56; + break; + case 1: + messageSizeGroupA = 144; + break; + case 2: + messageSizeGroupA = 208; + break; + case 3: + messageSizeGroupA = 256; + break; + case 4: + messageSizeGroupA = 282; + break; + case 5: + messageSizeGroupA = 480; + break; + case 6: + messageSizeGroupA = 640; + break; + case 7: + messageSizeGroupA = 800; + break; + case 8: + messageSizeGroupA = 1000; + break; + case 9: + messageSizeGroupA = 72; + break; + default: + AssertFatal(1 == 0,"Unknown ra_Msg3SizeGroupA %lu\n", nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA); + /* todo cases 10 -15*/ + } + + /* Power offset for preamble selection in dB */ + messagePowerOffsetGroupB = -9999; + switch (nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB){ + case 0: + messagePowerOffsetGroupB = -9999; + break; + case 1: + messagePowerOffsetGroupB = 0; + break; + case 2: + messagePowerOffsetGroupB = 5; + break; + case 3: + messagePowerOffsetGroupB = 8; + break; + case 4: + messagePowerOffsetGroupB = 10; + break; + case 5: + messagePowerOffsetGroupB = 12; + break; + case 6: + messagePowerOffsetGroupB = 15; + break; + case 7: + messagePowerOffsetGroupB = 18; + break; + default: + AssertFatal(1 == 0,"Unknown messagePowerOffsetGroupB %lu\n", nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB); + } + + // todo Msg3-DeltaPreamble should be provided from higher layers, otherwise is 0 + mac->deltaPreamble_Msg3 = 0; + deltaPreamble_Msg3 = mac->deltaPreamble_Msg3; } - } else { // Msg3 is being retransmitted - if (mac->RA_usedGroupA == 1 && noGroupB == 1) { - prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles; - } else if (mac->RA_usedGroupA == 1 && noGroupB == 0){ - prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; - } else { - prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); + + PLThreshold = prach_resources->RA_PCMAX - rach_ConfigGeneric->preambleReceivedTargetPower - deltaPreamble_Msg3 - messagePowerOffsetGroupB; + + /* Msg3 has not been transmitted yet */ + if (first_Msg3 == 1) { + if (noGroupB == 1) { + // use Group A preamble + prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles; + mac->RA_usedGroupA = 1; + } else if ((Msg3_size < messageSizeGroupA) && (get_nr_PL(mod_id, CC_id, gNB_id) > PLThreshold)) { + // Group B is configured and RA preamble Group A is used + // - todo add condition on CCCH_sdu_size for initiation by CCCH + prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; + mac->RA_usedGroupA = 1; + } else { + // Group B preamble is configured and used + // the first sizeOfRA_PreamblesGroupA RA preambles belong to RA Preambles Group A + // the remaining belong to RA Preambles Group B + prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); + mac->RA_usedGroupA = 0; + } + } else { // Msg3 is being retransmitted + if (mac->RA_usedGroupA == 1 && noGroupB == 1) { + prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles; + } else if (mac->RA_usedGroupA == 1 && noGroupB == 0){ + prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; + } else { + prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); + } } + LOG_D(MAC, "[RAPROC] - Selected RA preamble index %d for contention-based random access procedure... \n", prach_resources->ra_PreambleIndex); } // todo determine next available PRACH occasion @@ -284,7 +290,7 @@ void nr_get_prach_resources(module_id_t mod_id, prach_resources->ra_RNTI = 1 + s_id + 14 * t_id + 1120 * f_id + 8960 * ul_carrier_id; mac->ra_rnti = prach_resources->ra_RNTI; - LOG_D(MAC, "Computed ra_RNTI is %d", prach_resources->ra_RNTI); + LOG_D(MAC, "Computed ra_RNTI is %x \n", prach_resources->ra_RNTI); } // TbD: RA_attempt_number not used @@ -311,6 +317,7 @@ void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint /// Handling inizialization by PDCCH order, MAC entity or RRC (TS 38.300) /// Only one RA procedure is ongoing at any point in time in a MAC entity /// the RA procedure on a SCell shall only be initiated by PDCCH order +/// in the current implementation, RA is contention free only // WIP // todo TS 38.321: @@ -324,7 +331,6 @@ void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint // - retrieve TBS // - add mac_rrc_nr_data_req_ue, etc ... // - add the backoff condition here if we have it from a previous RA reponse which failed (i.e. backoff indicator) - void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, module_id_t mod_id, int CC_id, @@ -345,6 +351,8 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, NR_RACH_ConfigCommon_t *setup = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup; NR_RACH_ConfigGeneric_t *rach_ConfigGeneric = &setup->rach_ConfigGeneric; NR_FrequencyInfoDL_t *frequencyInfoDL = scc->downlinkConfigCommon->frequencyInfoDL; + NR_RACH_ConfigDedicated_t *rach_ConfigDedicated = mac->rach_ConfigDedicated; + // int32_t frame_diff = 0; uint8_t sdu_lcids[NB_RB_MAX] = {0}; @@ -485,7 +493,8 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, } // Fill in preamble and PRACH resources - nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 1, prach_resources, NULL); + if (is_nr_prach_slot) + nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 1, prach_resources, rach_ConfigDedicated); offset = nr_generate_ulsch_pdu((uint8_t *) mac_sdus, // sdus buffer (uint8_t *) payload, // UL MAC pdu pointer @@ -601,8 +610,11 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, mac->RA_tx_frame = frame; mac->RA_tx_subframe = nr_tti_tx; + // Fill in preamble and PRACH resources - nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 0, prach_resources, NULL); + if (is_nr_prach_slot) + nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 0, prach_resources, rach_ConfigDedicated); + } } } else if (UE_mode == PUSCH) { From 5eacaddd0e4f8ca630b54f5f4ae3d8b127f5079b Mon Sep 17 00:00:00 2001 From: cig Date: Wed, 22 Apr 2020 20:32:02 +0200 Subject: [PATCH 190/553] Code cleanup --- .../NR_UE_TRANSPORT/nr_dlsch_demodulation.c | 77 ++++++++++--------- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 2 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 3 - 3 files changed, 40 insertions(+), 42 deletions(-) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c index b532dea3c7..693284a052 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c @@ -182,7 +182,7 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, dlsch1_harq = dlsch[1]->harq_processes[harq_pid]; //printf("status TB0 = %d, status TB1 = %d \n", dlsch[0]->harq_processes[harq_pid]->status, dlsch[1]->harq_processes[harq_pid]->status); - LOG_D(PHY,"AbsSubframe %d.%d / Sym %d harq_pid %d, harq status %d.%d \n", frame, nr_tti_rx, symbol, harq_pid, dlsch0_harq->status, dlsch1_harq->status); + LOG_D(PHY,"AbsSubframe %d.%d / Sym %d harq_pid %d, harq status %d.%d \n", frame, nr_tti_rx, symbol, harq_pid, dlsch0_harq->status, dlsch1_harq->status); if ((dlsch0_harq->status == ACTIVE) && (dlsch1_harq->status == ACTIVE)){ codeword_TB0 = dlsch0_harq->codeword; @@ -969,45 +969,46 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, return(-1); break; } + if (dlsch1_harq) { - switch (nr_get_Qm_dl(dlsch1_harq->mcs,dlsch1_harq->mcs_table)) { - case 2 : - if (rx_type==rx_standard) { - nr_dlsch_qpsk_llr(frame_parms, - pdsch_vars[eNB_id]->rxdataF_comp0, - pllr_symbol_cw0, - symbol,len,first_symbol_flag,nb_rb, - beamforming_mode); + switch (nr_get_Qm_dl(dlsch1_harq->mcs,dlsch1_harq->mcs_table)) { + case 2 : + if (rx_type==rx_standard) { + nr_dlsch_qpsk_llr(frame_parms, + pdsch_vars[eNB_id]->rxdataF_comp0, + pllr_symbol_cw0, + symbol,len,first_symbol_flag,nb_rb, + beamforming_mode); + } + break; + case 4: + if (rx_type==rx_standard) { + nr_dlsch_16qam_llr(frame_parms, + pdsch_vars[eNB_id]->rxdataF_comp0, + pdsch_vars[eNB_id]->llr[0], + pdsch_vars[eNB_id]->dl_ch_mag0, + symbol,len,first_symbol_flag,nb_rb, + pdsch_vars[eNB_id]->llr128, + beamforming_mode); + } + break; + case 6 : + if (rx_type==rx_standard) { + nr_dlsch_64qam_llr(frame_parms, + pdsch_vars[eNB_id]->rxdataF_comp0, + pllr_symbol_cw0, + pdsch_vars[eNB_id]->dl_ch_mag0, + pdsch_vars[eNB_id]->dl_ch_magb0, + symbol,len,first_symbol_flag,nb_rb, + pdsch_vars[eNB_id]->llr_offset[symbol], + beamforming_mode); + } + break; + default: + LOG_W(PHY,"rx_dlsch.c : Unknown mod_order!!!!\n"); + return(-1); + break; } - break; - case 4: - if (rx_type==rx_standard) { - nr_dlsch_16qam_llr(frame_parms, - pdsch_vars[eNB_id]->rxdataF_comp0, - pdsch_vars[eNB_id]->llr[0], - pdsch_vars[eNB_id]->dl_ch_mag0, - symbol,len,first_symbol_flag,nb_rb, - pdsch_vars[eNB_id]->llr128, - beamforming_mode); - } - break; - case 6 : - if (rx_type==rx_standard) { - nr_dlsch_64qam_llr(frame_parms, - pdsch_vars[eNB_id]->rxdataF_comp0, - pllr_symbol_cw0, - pdsch_vars[eNB_id]->dl_ch_mag0, - pdsch_vars[eNB_id]->dl_ch_magb0, - symbol,len,first_symbol_flag,nb_rb, - pdsch_vars[eNB_id]->llr_offset[symbol], - beamforming_mode); - } - break; - default: - LOG_W(PHY,"rx_dlsch.c : Unknown mod_order!!!!\n"); - return(-1); - break; - } } //nr_dlsch_deinterleaving(symbol,bundle_L,(int16_t*)pllr_symbol_cw0,(int16_t*)pllr_symbol_cw0_deint, nb_rb_pdsch); diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 6cf0d68a62..c7fadbdafe 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -2599,7 +2599,7 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr /* PDSCH_TO_HARQ_FEEDBACK_TIME_IND (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI)*/ dlsch_config_pdu_1_0->pdsch_to_harq_feedback_time_ind = dci->pdsch_to_harq_feedback_time_ind; - LOG_D(MAC,"(nr_ue_procedures.c) rnti=%d dl_config->number_pdus=%d\n", + LOG_D(MAC,"(nr_ue_procedures.c) rnti = %x dl_config->number_pdus = %d\n", dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.rnti, dl_config->number_pdus); LOG_D(MAC,"(nr_ue_procedures.c) frequency_domain_resource_assignment=%d \t number_rbs=%d \t start_rb=%d\n", diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index 042e53e2dc..56c3d27210 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -247,8 +247,6 @@ void nr_initiate_ra_proc(module_id_t module_idP, // ra_rnti from 5.1.3 in 38.321 uint16_t ra_rnti=1+symbol+(slotP*14)+(freq_index*14*80)+(ul_carrier_id*14*80*8); - - uint16_t msg2_frame, msg2_slot,monitoring_slot_period,monitoring_offset; gNB_MAC_INST *nr_mac = RC.nrmac[module_idP]; NR_UE_list_t *UE_list = &nr_mac->UE_list; @@ -672,7 +670,6 @@ void nr_generate_Msg2(module_id_t module_idP, dci_pdu->ScramblingId[numDlDci] = *scc->physCellId; dci_pdu->ScramblingRNTI[numDlDci] = 0; dci_pdu->AggregationLevel[numDlDci] = aggregation; - dci_pdu->powerControlOffsetSS[numDlDci] = 0; dci_pdu->CceIndex[numDlDci] = CCEIndex; dci_pdu->beta_PDCCH_1_0[numDlDci] = 0; dci_pdu->powerControlOffsetSS[numDlDci] = 1; From 6b307e8123ebecba54a9bf49d31f91eedb91d30a Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Thu, 23 Apr 2020 19:44:04 +0200 Subject: [PATCH 191/553] bugfix in ratematching for higher rv --- openair1/PHY/CODING/nr_rate_matching.c | 9 +++++---- openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c | 3 +++ 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/openair1/PHY/CODING/nr_rate_matching.c b/openair1/PHY/CODING/nr_rate_matching.c index 0cffc2d852..5294e79b9f 100644 --- a/openair1/PHY/CODING/nr_rate_matching.c +++ b/openair1/PHY/CODING/nr_rate_matching.c @@ -364,8 +364,8 @@ int nr_rate_matching_ldpc(uint8_t Ilbrm, if (ind < Foffset) { // case where we have some bits before the filler and the rest after memcpy((void*)e,(void*)(w+ind),Foffset-ind); - if (E + F <= Ncb) { // E+F doesn't contain all coded bits - memcpy((void*)(e+Foffset-ind),(void*)(w+Foffset+F-ind),E-Foffset+ind); + if (E + F <= Ncb-ind) { // E+F doesn't contain all coded bits + memcpy((void*)(e+Foffset-ind),(void*)(w+Foffset+F),E-Foffset+ind); k=E; } else { @@ -375,11 +375,12 @@ int nr_rate_matching_ldpc(uint8_t Ilbrm, } else { if (E + F <= Ncb-ind) { //E+F doesn't contain all coded bits - memcpy((void*)(e+Foffset-ind),(void*)(w+Foffset+F-ind),E-Foffset+ind); + memcpy((void*)(e),(void*)(w+ind),E); k=E; } else { - + memcpy((void*)(e),(void*)(w+ind),Ncb-ind); + k=Ncb-ind; } } diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c index 856a7863f4..6242008387 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c @@ -460,6 +460,9 @@ int nr_dlsch_encoding(unsigned char *a, } + F = dlsch->harq_processes[harq_pid]->F; + + Kr = dlsch->harq_processes[harq_pid]->K; for (r=0; rharq_processes[harq_pid]->C; r++) { if (F>0) { From 93e745b8ec4153445a65a4589858e3875403b64e Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Thu, 23 Apr 2020 19:45:00 +0200 Subject: [PATCH 192/553] updated dlsim to test harq --- openair1/SIMULATION/NR_PHY/dlsim.c | 240 ++++++++++-------- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 6 +- openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 6 + 3 files changed, 137 insertions(+), 115 deletions(-) diff --git a/openair1/SIMULATION/NR_PHY/dlsim.c b/openair1/SIMULATION/NR_PHY/dlsim.c index 491fd52e5e..e806a6867a 100644 --- a/openair1/SIMULATION/NR_PHY/dlsim.c +++ b/openair1/SIMULATION/NR_PHY/dlsim.c @@ -154,6 +154,8 @@ int main(int argc, char **argv) int trial, n_trials = 1, n_errors = 0, n_false_positive = 0; //int n_errors2, n_alamouti; uint8_t transmission_mode = 1,n_tx=1,n_rx=1; + uint8_t round; + uint8_t num_rounds = 4; channel_desc_t *gNB2UE; //uint32_t nsymb,tx_lev,tx_lev1 = 0,tx_lev2 = 0; @@ -678,6 +680,8 @@ int main(int argc, char **argv) nr_ue_phy_config_request(&UE_mac->phy_config); + NR_UE_list_t *UE_list = &RC.nrmac[0]->UE_list; + NR_COMMON_channels_t *cc = RC.nrmac[0]->common_channels; for (SNR = snr0; SNR < snr1; SNR += .2) { @@ -704,95 +708,6 @@ int main(int argc, char **argv) errors_bit = 0; //multipath channel //multipath_channel(gNB2UE,s_re,s_im,r_re,r_im,frame_length_complex_samples,0); - - memset(RC.nrmac[0]->cce_list[1][0],0,MAX_NUM_CCE*sizeof(int)); - clear_nr_nfapi_information(RC.nrmac[0], 0, frame, slot); - if (css_flag == 0) nr_schedule_uss_dlsch_phytest(0,frame,slot,&pucch_sched,&dlsch_config); - else nr_schedule_css_dlsch_phytest(0,frame,slot); - - - Sched_INFO.module_id = 0; - Sched_INFO.CC_id = 0; - Sched_INFO.frame = frame; - Sched_INFO.slot = slot; - Sched_INFO.DL_req = &gNB_mac->DL_req[0]; - Sched_INFO.UL_tti_req = &gNB_mac->UL_tti_req[0]; - Sched_INFO.UL_dci_req = NULL; - Sched_INFO.TX_req = &gNB_mac->TX_req[0]; - nr_schedule_response(&Sched_INFO); - - if (run_initial_sync) - nr_common_signal_procedures(gNB,frame,slot); - else - phy_procedures_gNB_TX(gNB,frame,slot,0); - - int txdataF_offset = (slot%2) * frame_parms->samples_per_slot_wCP; - - if (n_trials==1) { - LOG_M("txsigF0.m","txsF0", gNB->common_vars.txdataF[0],frame_length_complex_samples_no_prefix,1,1); - if (gNB->frame_parms.nb_antennas_tx>1) - LOG_M("txsigF1.m","txsF1", gNB->common_vars.txdataF[1],frame_length_complex_samples_no_prefix,1,1); - } - int tx_offset = frame_parms->get_samples_slot_timestamp(slot,frame_parms,0); - if (n_trials==1) printf("samples_per_slot_wCP = %d\n", frame_parms->samples_per_slot_wCP); - - //TODO: loop over slots - for (aa=0; aaframe_parms.nb_antennas_tx; aa++) { - - if (cyclic_prefix_type == 1) { - PHY_ofdm_mod(&gNB->common_vars.txdataF[aa][txdataF_offset], - &txdata[aa][tx_offset], - frame_parms->ofdm_symbol_size, - 12, - frame_parms->nb_prefix_samples, - CYCLIC_PREFIX); - } else { - nr_normal_prefix_mod(&gNB->common_vars.txdataF[aa][txdataF_offset], - &txdata[aa][tx_offset], - 14, - frame_parms); - } - } - - if (n_trials==1) { - LOG_M("txsig0.m","txs0", txdata[0],frame_length_complex_samples,1,1); - if (gNB->frame_parms.nb_antennas_tx>1) - LOG_M("txsig1.m","txs1", txdata[1],frame_length_complex_samples,1,1); - } - if (output_fd) - fwrite(txdata[0],sizeof(int32_t),frame_length_complex_samples,output_fd); - - int txlev = signal_energy(&txdata[0][frame_parms->get_samples_slot_timestamp(slot,frame_parms,0)+5*frame_parms->ofdm_symbol_size + 4*frame_parms->nb_prefix_samples + frame_parms->nb_prefix_samples0], - frame_parms->ofdm_symbol_size + frame_parms->nb_prefix_samples); - - // if (n_trials==1) printf("txlev %d (%f)\n",txlev,10*log10((double)txlev)); - - for (i=(frame_parms->get_samples_slot_timestamp(slot,frame_parms,0)); - i<(frame_parms->get_samples_slot_timestamp(slot+1,frame_parms,0)); - i++) { - for (aa=0; aanb_antennas_tx; aa++) { - r_re[aa][i] = ((double)(((short *)txdata[aa]))[(i<<1)]); - r_im[aa][i] = ((double)(((short *)txdata[aa]))[(i<<1)+1]); - } - } - - NR_gNB_DLSCH_t *gNB_dlsch = gNB->dlsch[0][0]; - nfapi_nr_dl_tti_pdsch_pdu_rel15_t rel15 = gNB_dlsch->harq_processes[0]->pdsch_pdu.pdsch_pdu_rel15; - - //AWGN - sigma2_dB = 10 * log10((double)txlev * ((double)UE->frame_parms.ofdm_symbol_size/(12*rel15.rbSize))) - SNR; - sigma2 = pow(10, sigma2_dB/10); - if (n_trials==1) printf("sigma2 %f (%f dB), txlev %f (factor %f)\n",sigma2,sigma2_dB,10*log10((double)txlev),(double)(double)UE->frame_parms.ofdm_symbol_size/(12*rel15.rbSize)); - - for (i=frame_parms->get_samples_slot_timestamp(slot,frame_parms,0); - iget_samples_slot_timestamp(slot+1,frame_parms,0); - i++) { - for (aa=0; aanb_antennas_rx; aa++) { - ((short*) UE->common_vars.rxdata[aa])[2*i] = (short) ((r_re[aa][i] + sqrt(sigma2/2)*gaussdouble(0.0,1.0))); - ((short*) UE->common_vars.rxdata[aa])[2*i+1] = (short) ((r_im[aa][i] + sqrt(sigma2/2)*gaussdouble(0.0,1.0))); - } - } - UE->rx_offset=0; UE_proc.frame_rx = frame; UE_proc.nr_tti_rx= slot; @@ -800,43 +715,144 @@ int main(int argc, char **argv) dcireq.frame = frame; dcireq.slot = slot; + + NR_UE_DLSCH_t *dlsch0 = UE->dlsch[UE->current_thread_id[UE_proc.nr_tti_rx]][0][0]; + + int harq_pid = dlsch0->current_harq_pid; + NR_DL_UE_HARQ_t *UE_harq_process = dlsch0->harq_processes[harq_pid]; + + NR_gNB_DLSCH_t *gNB_dlsch = gNB->dlsch[0][0]; + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &gNB_dlsch->harq_processes[0]->pdsch_pdu.pdsch_pdu_rel15; - nr_ue_dcireq(&dcireq); //to be replaced with function pointer later - nr_ue_scheduled_response(&scheduled_response); + UE_harq_process->harq_ack.ack = 0; + round = 0; + + while ((roundharq_ack.ack==0)) { + memset(RC.nrmac[0]->cce_list[1][0],0,MAX_NUM_CCE*sizeof(int)); + memset(RC.nrmac[0]->cce_list[1][1],0,MAX_NUM_CCE*sizeof(int)); + clear_nr_nfapi_information(RC.nrmac[0], 0, frame, slot); + + UE_list->UE_sched_ctrl[0].harq_processes[0].ndi = (round==0) ? 1 : 0; + + UE_list->UE_sched_ctrl[0].harq_processes[0].round = round; + gNB->dlsch[0][0]->harq_processes[0]->round = round; - phy_procedures_nrUE_RX(UE, - &UE_proc, - 0, - do_pdcch_flag, - normal_txrx); + if (css_flag == 0) nr_schedule_uss_dlsch_phytest(0,frame,slot,&pucch_sched,&dlsch_config); + else nr_schedule_css_dlsch_phytest(0,frame,slot); + Sched_INFO.module_id = 0; + Sched_INFO.CC_id = 0; + Sched_INFO.frame = frame; + Sched_INFO.slot = slot; + Sched_INFO.DL_req = &gNB_mac->DL_req[0]; + Sched_INFO.UL_tti_req = &gNB_mac->UL_tti_req[0]; + Sched_INFO.UL_dci_req = NULL; + Sched_INFO.TX_req = &gNB_mac->TX_req[0]; + nr_schedule_response(&Sched_INFO); + + if (run_initial_sync) + nr_common_signal_procedures(gNB,frame,slot); + else + phy_procedures_gNB_TX(gNB,frame,slot,0); + + int txdataF_offset = (slot%2) * frame_parms->samples_per_slot_wCP; + + if (n_trials==1) { + LOG_M("txsigF0.m","txsF0", gNB->common_vars.txdataF[0],frame_length_complex_samples_no_prefix,1,1); + if (gNB->frame_parms.nb_antennas_tx>1) + LOG_M("txsigF1.m","txsF1", gNB->common_vars.txdataF[1],frame_length_complex_samples_no_prefix,1,1); + } + int tx_offset = frame_parms->get_samples_slot_timestamp(slot,frame_parms,0); + if (n_trials==1) printf("samples_per_slot_wCP = %d\n", frame_parms->samples_per_slot_wCP); + + //TODO: loop over slots + for (aa=0; aaframe_parms.nb_antennas_tx; aa++) { + + if (cyclic_prefix_type == 1) { + PHY_ofdm_mod(&gNB->common_vars.txdataF[aa][txdataF_offset], + &txdata[aa][tx_offset], + frame_parms->ofdm_symbol_size, + 12, + frame_parms->nb_prefix_samples, + CYCLIC_PREFIX); + } else { + nr_normal_prefix_mod(&gNB->common_vars.txdataF[aa][txdataF_offset], + &txdata[aa][tx_offset], + 14, + frame_parms); + } + } + + if (n_trials==1) { + LOG_M("txsig0.m","txs0", txdata[0],frame_length_complex_samples,1,1); + if (gNB->frame_parms.nb_antennas_tx>1) + LOG_M("txsig1.m","txs1", txdata[1],frame_length_complex_samples,1,1); + } + if (output_fd) + fwrite(txdata[0],sizeof(int32_t),frame_length_complex_samples,output_fd); + + int txlev = signal_energy(&txdata[0][frame_parms->get_samples_slot_timestamp(slot,frame_parms,0)+5*frame_parms->ofdm_symbol_size + 4*frame_parms->nb_prefix_samples + frame_parms->nb_prefix_samples0], + frame_parms->ofdm_symbol_size + frame_parms->nb_prefix_samples); + + // if (n_trials==1) printf("txlev %d (%f)\n",txlev,10*log10((double)txlev)); + + for (i=(frame_parms->get_samples_slot_timestamp(slot,frame_parms,0)); + i<(frame_parms->get_samples_slot_timestamp(slot+1,frame_parms,0)); + i++) { + for (aa=0; aanb_antennas_tx; aa++) { + r_re[aa][i] = ((double)(((short *)txdata[aa]))[(i<<1)]); + r_im[aa][i] = ((double)(((short *)txdata[aa]))[(i<<1)+1]); + } + } + + //AWGN + sigma2_dB = 10 * log10((double)txlev * ((double)UE->frame_parms.ofdm_symbol_size/(12*rel15->rbSize))) - SNR; + sigma2 = pow(10, sigma2_dB/10); + if (n_trials==1) printf("sigma2 %f (%f dB), txlev %f (factor %f)\n",sigma2,sigma2_dB,10*log10((double)txlev),(double)(double)UE->frame_parms.ofdm_symbol_size/(12*rel15->rbSize)); + + for (i=frame_parms->get_samples_slot_timestamp(slot,frame_parms,0); + iget_samples_slot_timestamp(slot+1,frame_parms,0); + i++) { + for (aa=0; aanb_antennas_rx; aa++) { + ((short*) UE->common_vars.rxdata[aa])[2*i] = (short) ((r_re[aa][i] + sqrt(sigma2/2)*gaussdouble(0.0,1.0))); + ((short*) UE->common_vars.rxdata[aa])[2*i+1] = (short) ((r_im[aa][i] + sqrt(sigma2/2)*gaussdouble(0.0,1.0))); + } + } + + nr_ue_dcireq(&dcireq); //to be replaced with function pointer later + nr_ue_scheduled_response(&scheduled_response); + + phy_procedures_nrUE_RX(UE, + &UE_proc, + 0, + do_pdcch_flag, + normal_txrx); + + if (UE->dlsch[UE->current_thread_id[slot]][0][0]->last_iteration_cnt >= + UE->dlsch[UE->current_thread_id[slot]][0][0]->max_ldpc_iterations+1) + n_errors++; - if (UE->dlsch[UE->current_thread_id[slot]][0][0]->last_iteration_cnt >= - UE->dlsch[UE->current_thread_id[slot]][0][0]->max_ldpc_iterations+1) - n_errors++; + printf("dlsim round %d ends\n",round); + round++; + } // round //---------------------------------------------------------- //---------------------- count errors ---------------------- //---------------------------------------------------------- - - - NR_UE_DLSCH_t *dlsch0 = UE->dlsch[UE->current_thread_id[UE_proc.nr_tti_rx]][0][0]; - - int harq_pid = dlsch0->current_harq_pid; - NR_DL_UE_HARQ_t *UE_harq_process = dlsch0->harq_processes[harq_pid]; - + + NR_UE_PDSCH **pdsch_vars = UE->pdsch_vars[UE->current_thread_id[UE_proc.nr_tti_rx]]; int16_t *UE_llr = pdsch_vars[0]->llr[0]; - uint32_t TBS = rel15.TBSize[0]; + uint32_t TBS = rel15->TBSize[0]; uint16_t length_dmrs = 1; - uint16_t nb_rb = rel15.rbSize; - uint8_t nb_re_dmrs = rel15.dmrsConfigType == NFAPI_NR_DMRS_TYPE1 ? 6 : 4; - uint8_t mod_order = rel15.qamModOrder[0]; - uint8_t nb_symb_sch = rel15.NrOfSymbols; + uint16_t nb_rb = rel15->rbSize; + uint8_t nb_re_dmrs = rel15->dmrsConfigType == NFAPI_NR_DMRS_TYPE1 ? 6 : 4; + uint8_t mod_order = rel15->qamModOrder[0]; + uint8_t nb_symb_sch = rel15->NrOfSymbols; - available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, rel15.nrOfLayers); + available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, rel15->nrOfLayers); for (i = 0; i < available_bits; i++) { diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index b98b6ae305..d1d2547ad6 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -311,7 +311,7 @@ int configure_fapi_dl_pdu(int Mod_idP, pdsch_pdu_rel15->qamModOrder[0] = 2; pdsch_pdu_rel15->mcsIndex[0] = mcs; pdsch_pdu_rel15->mcsTable[0] = 0; - pdsch_pdu_rel15->rvIndex[0] = 0; + pdsch_pdu_rel15->rvIndex[0] = UE_list->UE_sched_ctrl[UE_id].harq_processes[0].round; pdsch_pdu_rel15->dataScramblingId = *scc->physCellId; pdsch_pdu_rel15->nrOfLayers = 1; pdsch_pdu_rel15->transmissionScheme = 0; @@ -361,10 +361,10 @@ int configure_fapi_dl_pdu(int Mod_idP, dci_pdu_rel15[0].time_domain_assignment.val = time_domain_assignment; // row index used here instead of SLIV; // mcs ndi and rv dci_pdu_rel15[0].mcs = pdsch_pdu_rel15->mcsIndex[0]; - dci_pdu_rel15[0].ndi = 1; - dci_pdu_rel15[0].rv = 0; + dci_pdu_rel15[0].rv = pdsch_pdu_rel15->rvIndex[0]; // harq pid dci_pdu_rel15[0].harq_pid = 0; + dci_pdu_rel15[0].ndi = UE_list->UE_sched_ctrl[UE_id].harq_processes[0].ndi; // DAI dci_pdu_rel15[0].dai[0].val = (pucch_sched->dai_c-1)&3; // TPC for PUCCH diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index e3a30c9b19..af5f6d2992 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -111,6 +111,11 @@ typedef struct NR_sched_pucch { struct NR_sched_pucch *next_sched_pucch; } NR_sched_pucch; +typedef struct NR_UE_harq { + uint8_t ndi; + uint8_t round; +} NR_UE_harq_t; + /*! \brief scheduling control information set through an API */ typedef struct { uint64_t dlsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains dlsch @@ -118,6 +123,7 @@ typedef struct { NR_sched_pucch *sched_pucch; uint16_t ta_timer; int16_t ta_update; + NR_UE_harq_t harq_processes[NR_MAX_NB_HARQ_PROCESSES]; } NR_UE_sched_ctrl_t; /*! \brief UE list used by eNB to order UEs/CC for scheduling*/ From fd50f1b5bd6d0264531f5181984f57dcbb485c90 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Fri, 24 Apr 2020 01:44:47 +0200 Subject: [PATCH 193/553] fixed round update in UE --- openair1/SCHED_NR_UE/fapi_nr_ue_l1.c | 5 +++-- openair1/SIMULATION/NR_PHY/dlsim.c | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c index 69876159d6..a78024f70c 100644 --- a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c +++ b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c @@ -34,6 +34,7 @@ #include "fapi_nr_ue_interface.h" #include "fapi_nr_ue_l1.h" +#include "harq_nr.h" //#include "PHY/phy_vars_nr_ue.h" #include "PHY/defs_nr_UE.h" @@ -95,14 +96,14 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response) dlsch0_harq->dlDmrsSymbPos = dlsch_config_pdu->dlDmrsSymbPos; dlsch0_harq->dmrsConfigType = dlsch_config_pdu->dmrsConfigType; dlsch0_harq->mcs = dlsch_config_pdu->mcs; - dlsch0_harq->DCINdi = dlsch_config_pdu->ndi; dlsch0_harq->rvidx = dlsch_config_pdu->rv; dlsch0->g_pucch = dlsch_config_pdu->accumulated_delta_PUCCH; dlsch0_harq->harq_ack.pucch_resource_indicator = dlsch_config_pdu->pucch_resource_id; dlsch0_harq->harq_ack.slot_for_feedback_ack = dlsch_config_pdu->pdsch_to_harq_feedback_time_ind; dlsch0_harq->Nl=1; dlsch0_harq->mcs_table=0; - dlsch0_harq->status = ACTIVE; + dlsch0_harq->harq_ack.rx_status = downlink_harq_process(dlsch0_harq, dlsch0->current_harq_pid, dlsch_config_pdu->ndi, dlsch0->rnti_type); +ACTIVE; LOG_D(MAC,">>>> \tdlsch0->g_pucch=%d\tdlsch0_harq.mcs=%d\n",dlsch0->g_pucch,dlsch0_harq->mcs); } diff --git a/openair1/SIMULATION/NR_PHY/dlsim.c b/openair1/SIMULATION/NR_PHY/dlsim.c index e806a6867a..50ea3f21de 100644 --- a/openair1/SIMULATION/NR_PHY/dlsim.c +++ b/openair1/SIMULATION/NR_PHY/dlsim.c @@ -732,7 +732,7 @@ int main(int argc, char **argv) memset(RC.nrmac[0]->cce_list[1][1],0,MAX_NUM_CCE*sizeof(int)); clear_nr_nfapi_information(RC.nrmac[0], 0, frame, slot); - UE_list->UE_sched_ctrl[0].harq_processes[0].ndi = (round==0) ? 1 : 0; + UE_list->UE_sched_ctrl[0].harq_processes[0].ndi = !(trial&1); UE_list->UE_sched_ctrl[0].harq_processes[0].round = round; gNB->dlsch[0][0]->harq_processes[0]->round = round; From 111ea68f6358adec6b814c648e336a0dd42c9cff Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 24 Apr 2020 11:42:50 +0200 Subject: [PATCH 194/553] fix for scrambling rnti and dci format --- nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h | 2 +- openair1/PHY/NR_UE_TRANSPORT/dci_nr.c | 2 +- openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c | 8 ++++++-- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 4 ++-- 4 files changed, 10 insertions(+), 6 deletions(-) diff --git a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h index 610a798292..4318db7a68 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h @@ -60,7 +60,7 @@ typedef struct { uint8_t CoreSetType; uint8_t precoder_granularity; uint16_t pdcch_dmrs_scrambling_id; - + uint16_t scrambling_rnti; uint8_t tci_state_pdcch; uint8_t tci_present_in_dci; } fapi_nr_coreset_t; diff --git a/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c b/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c index 6d98031843..8a86192557 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c +++ b/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c @@ -851,7 +851,7 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue, uint64_t dci_estimation[2]= {0}; const t_nrPolar_params *currentPtrDCI=nr_polar_params(1, dci_length, L,1,&ue->polarList); - nr_pdcch_unscrambling(rel15->rnti, + nr_pdcch_unscrambling(rel15->coreset.scrambling_rnti, &ue->frame_parms, slot, &pdcch_vars->e_rx[CCEind*108], diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c index 3da0992fce..a546cea06f 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c @@ -170,10 +170,14 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_ } rel15->coreset.CoreSetType = 1; rel15->coreset.precoder_granularity = mac->coreset[0][0]->precoderGranularity; - if (mac->coreset[0][0]->pdcch_DMRS_ScramblingID) + if (mac->coreset[0][0]->pdcch_DMRS_ScramblingID) { rel15->coreset.pdcch_dmrs_scrambling_id = *mac->coreset[0][0]->pdcch_DMRS_ScramblingID; - else + rel15->coreset.scrambling_rnti = mac->t_crnti; + } + else { rel15->coreset.pdcch_dmrs_scrambling_id = *mac->scc->physCellId; + rel15->coreset.scrambling_rnti = 0; + } fill_dci_search_candidates(mac->SSpace[0][0][ss_id],rel15); rel15->dci_format = NR_DL_DCI_FORMAT_1_1; rel15->dci_length = nr_dci_size(mac->scg,def_dci_pdu_rel15,rel15->dci_format,NR_RNTI_C,rel15->BWPSize,bwp_id); diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index f483e07ab0..7015c0d8ce 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -426,9 +426,9 @@ int configure_fapi_dl_pdu(int Mod_idP, int rnti_types[2]; if (ss->searchSpaceType->choice.ue_Specific->dci_Formats) - dci_formats[0] = NR_DL_DCI_FORMAT_1_0; - else dci_formats[0] = NR_DL_DCI_FORMAT_1_1; + else + dci_formats[0] = NR_DL_DCI_FORMAT_1_0; rnti_types[0] = NR_RNTI_C; From bfe580bd41a14f867612b8d551f7744507a5ffac Mon Sep 17 00:00:00 2001 From: cig Date: Wed, 22 Apr 2020 19:49:08 +0200 Subject: [PATCH 195/553] UE RA procedures changes to preamble selection: - get preamble from rach_ConfigDedicated in contention free mode - do preamble selection only in prach slot --- openair2/LAYER2/NR_MAC_UE/config_ue.c | 2 +- openair2/LAYER2/NR_MAC_UE/mac_defs.h | 1 + openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 268 ++++++++++--------- 3 files changed, 142 insertions(+), 129 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_UE/config_ue.c b/openair2/LAYER2/NR_MAC_UE/config_ue.c index 38829346c7..5a9620ed01 100755 --- a/openair2/LAYER2/NR_MAC_UE/config_ue.c +++ b/openair2/LAYER2/NR_MAC_UE/config_ue.c @@ -349,11 +349,11 @@ int nr_rrc_mac_config_req_ue( if(cell_group_config != NULL ){ mac->servCellIndex = *cell_group_config->spCellConfig->servCellIndex; if (cell_group_config->spCellConfig->reconfigurationWithSync) { + mac->rach_ConfigDedicated = cell_group_config->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink; mac->scc = cell_group_config->spCellConfig->reconfigurationWithSync->spCellConfigCommon; config_common_ue(mac,module_id,cc_idP); mac->crnti = cell_group_config->spCellConfig->reconfigurationWithSync->newUE_Identity; LOG_I(MAC,"Configuring CRNTI %x\n",mac->crnti); - } mac->scg = cell_group_config; diff --git a/openair2/LAYER2/NR_MAC_UE/mac_defs.h b/openair2/LAYER2/NR_MAC_UE/mac_defs.h index 446fe90f77..67782c3ef0 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_defs.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_defs.h @@ -156,6 +156,7 @@ typedef struct { NR_ServingCellConfigCommon_t *scc; NR_CellGroupConfig_t *scg; + NR_RACH_ConfigDedicated_t *rach_ConfigDedicated; int servCellIndex; //// MAC config NR_DRX_Config_t *drx_Config; diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c index 75091d49e2..3e00dba46d 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -88,6 +88,10 @@ void nr_get_prach_resources(module_id_t mod_id, int messagePowerOffsetGroupB, messageSizeGroupA, PLThreshold, sizeOfRA_PreamblesGroupA, numberOfRA_Preambles, i, deltaPreamble_Msg3; uint8_t noGroupB = 0, s_id, f_id, ul_carrier_id, prach_ConfigIndex, SFN_nbr, Msg3_size; + AssertFatal(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); + nr_rach_ConfigCommon = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup; + rach_ConfigGeneric = &nr_rach_ConfigCommon->rach_ConfigGeneric; + // NR_RSRP_Range_t rsrp_ThresholdSSB; // todo /////////////////////////////////////////////////////////// @@ -104,138 +108,140 @@ void nr_get_prach_resources(module_id_t mod_id, // -- RA initiated for SI request: // --- SSB selection, set prach_resources->ra_PreambleIndex - // if (rach_ConfigDedicated) { // This is for network controlled Mobility - // // operation for contention-free RA resources when: - // // - available SSB with SS-RSRP above rsrp-ThresholdSSB: SSB selection - // // - availalbe CSI-RS with CSI-RSRP above rsrp-ThresholdCSI-RS: CSI-RS selection - // prach_resources->ra_PreambleIndex = rach_ConfigDedicated->ra_PreambleIndex; - // } - - //////////* Contention-based RA preamble selection *////////// - // todo: - // - selection of SSB with SS-RSRP above rsrp-ThresholdSSB else select any SSB - // - todo determine next available PRACH occasion - - // rsrp_ThresholdSSB = *nr_rach_ConfigCommon->rsrp_ThresholdSSB; - - AssertFatal(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); - - nr_rach_ConfigCommon = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup; - rach_ConfigGeneric = &nr_rach_ConfigCommon->rach_ConfigGeneric; - - Msg3_size = mac->RA_Msg3_size; - - numberOfRA_Preambles = 64; - if(nr_rach_ConfigCommon->totalNumberOfRA_Preambles != NULL) - numberOfRA_Preambles = *(nr_rach_ConfigCommon->totalNumberOfRA_Preambles); - - if (!nr_rach_ConfigCommon->groupBconfigured) { - noGroupB = 1; + if (rach_ConfigDedicated) { + //////////* Contention free RA *////////// + // - the PRACH preamble for the UE to transmit is set through RRC configuration + // - this is the default mode in current implementation! + // Operation for contention-free RA resources when: + // - available SSB with SS-RSRP above rsrp-ThresholdSSB: SSB selection + // - available CSI-RS with CSI-RSRP above rsrp-ThresholdCSI-RS: CSI-RS selection + // - network controlled Mobility + uint8_t cfra_ssb_resource_idx = 0; + prach_resources->ra_PreambleIndex = rach_ConfigDedicated->cfra->resources.choice.ssb->ssb_ResourceList.list.array[cfra_ssb_resource_idx]->ra_PreambleIndex; + LOG_D(MAC, "[RAPROC] - Selected RA preamble index %d for contention-free random access procedure... \n", prach_resources->ra_PreambleIndex); } else { - // RA preambles group B is configured - // - Defining the number of RA preambles in RA Preamble Group A for each SSB */ - sizeOfRA_PreamblesGroupA = nr_rach_ConfigCommon->groupBconfigured->numberOfRA_PreamblesGroupA; - switch (nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA){ - /* - Threshold to determine the groups of RA preambles */ - case 0: - messageSizeGroupA = 56; - break; - case 1: - messageSizeGroupA = 144; - break; - case 2: - messageSizeGroupA = 208; - break; - case 3: - messageSizeGroupA = 256; - break; - case 4: - messageSizeGroupA = 282; - break; - case 5: - messageSizeGroupA = 480; - break; - case 6: - messageSizeGroupA = 640; - break; - case 7: - messageSizeGroupA = 800; - break; - case 8: - messageSizeGroupA = 1000; - break; - case 9: - messageSizeGroupA = 72; - break; - default: - AssertFatal(1 == 0,"Unknown ra_Msg3SizeGroupA %lu\n", nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA); - /* todo cases 10 -15*/ - } + //////////* Contention-based RA preamble selection *////////// + // todo: + // - selection of SSB with SS-RSRP above rsrp-ThresholdSSB else select any SSB + // - todo determine next available PRACH occasion - /* Power offset for preamble selection in dB */ - messagePowerOffsetGroupB = -9999; - switch (nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB){ - case 0: - messagePowerOffsetGroupB = -9999; - break; - case 1: - messagePowerOffsetGroupB = 0; - break; - case 2: - messagePowerOffsetGroupB = 5; - break; - case 3: - messagePowerOffsetGroupB = 8; - break; - case 4: - messagePowerOffsetGroupB = 10; - break; - case 5: - messagePowerOffsetGroupB = 12; - break; - case 6: - messagePowerOffsetGroupB = 15; - break; - case 7: - messagePowerOffsetGroupB = 18; - break; - default: - AssertFatal(1 == 0,"Unknown messagePowerOffsetGroupB %lu\n", nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB); - } + // rsrp_ThresholdSSB = *nr_rach_ConfigCommon->rsrp_ThresholdSSB; - // todo Msg3-DeltaPreamble should be provided from higher layers, otherwise is 0 - mac->deltaPreamble_Msg3 = 0; - deltaPreamble_Msg3 = mac->deltaPreamble_Msg3; - } + Msg3_size = mac->RA_Msg3_size; - PLThreshold = prach_resources->RA_PCMAX - rach_ConfigGeneric->preambleReceivedTargetPower - deltaPreamble_Msg3 - messagePowerOffsetGroupB; + numberOfRA_Preambles = 64; + if(nr_rach_ConfigCommon->totalNumberOfRA_Preambles != NULL) + numberOfRA_Preambles = *(nr_rach_ConfigCommon->totalNumberOfRA_Preambles); - /* Msg3 has not been transmitted yet */ - if (first_Msg3 == 1) { - if (noGroupB == 1) { - // use Group A preamble - prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles; - mac->RA_usedGroupA = 1; - } else if ((Msg3_size < messageSizeGroupA) && (get_nr_PL(mod_id, CC_id, gNB_id) > PLThreshold)) { - // Group B is configured and RA preamble Group A is used - // - todo add condition on CCCH_sdu_size for initiation by CCCH - prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; - mac->RA_usedGroupA = 1; + if (!nr_rach_ConfigCommon->groupBconfigured) { + noGroupB = 1; } else { - // Group B preamble is configured and used - // the first sizeOfRA_PreamblesGroupA RA preambles belong to RA Preambles Group A - // the remaining belong to RA Preambles Group B - prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); - mac->RA_usedGroupA = 0; + // RA preambles group B is configured + // - Defining the number of RA preambles in RA Preamble Group A for each SSB */ + sizeOfRA_PreamblesGroupA = nr_rach_ConfigCommon->groupBconfigured->numberOfRA_PreamblesGroupA; + switch (nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA){ + /* - Threshold to determine the groups of RA preambles */ + case 0: + messageSizeGroupA = 56; + break; + case 1: + messageSizeGroupA = 144; + break; + case 2: + messageSizeGroupA = 208; + break; + case 3: + messageSizeGroupA = 256; + break; + case 4: + messageSizeGroupA = 282; + break; + case 5: + messageSizeGroupA = 480; + break; + case 6: + messageSizeGroupA = 640; + break; + case 7: + messageSizeGroupA = 800; + break; + case 8: + messageSizeGroupA = 1000; + break; + case 9: + messageSizeGroupA = 72; + break; + default: + AssertFatal(1 == 0,"Unknown ra_Msg3SizeGroupA %lu\n", nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA); + /* todo cases 10 -15*/ + } + + /* Power offset for preamble selection in dB */ + messagePowerOffsetGroupB = -9999; + switch (nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB){ + case 0: + messagePowerOffsetGroupB = -9999; + break; + case 1: + messagePowerOffsetGroupB = 0; + break; + case 2: + messagePowerOffsetGroupB = 5; + break; + case 3: + messagePowerOffsetGroupB = 8; + break; + case 4: + messagePowerOffsetGroupB = 10; + break; + case 5: + messagePowerOffsetGroupB = 12; + break; + case 6: + messagePowerOffsetGroupB = 15; + break; + case 7: + messagePowerOffsetGroupB = 18; + break; + default: + AssertFatal(1 == 0,"Unknown messagePowerOffsetGroupB %lu\n", nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB); + } + + // todo Msg3-DeltaPreamble should be provided from higher layers, otherwise is 0 + mac->deltaPreamble_Msg3 = 0; + deltaPreamble_Msg3 = mac->deltaPreamble_Msg3; } - } else { // Msg3 is being retransmitted - if (mac->RA_usedGroupA == 1 && noGroupB == 1) { - prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles; - } else if (mac->RA_usedGroupA == 1 && noGroupB == 0){ - prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; - } else { - prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); + + PLThreshold = prach_resources->RA_PCMAX - rach_ConfigGeneric->preambleReceivedTargetPower - deltaPreamble_Msg3 - messagePowerOffsetGroupB; + + /* Msg3 has not been transmitted yet */ + if (first_Msg3 == 1) { + if (noGroupB == 1) { + // use Group A preamble + prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles; + mac->RA_usedGroupA = 1; + } else if ((Msg3_size < messageSizeGroupA) && (get_nr_PL(mod_id, CC_id, gNB_id) > PLThreshold)) { + // Group B is configured and RA preamble Group A is used + // - todo add condition on CCCH_sdu_size for initiation by CCCH + prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; + mac->RA_usedGroupA = 1; + } else { + // Group B preamble is configured and used + // the first sizeOfRA_PreamblesGroupA RA preambles belong to RA Preambles Group A + // the remaining belong to RA Preambles Group B + prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); + mac->RA_usedGroupA = 0; + } + } else { // Msg3 is being retransmitted + if (mac->RA_usedGroupA == 1 && noGroupB == 1) { + prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles; + } else if (mac->RA_usedGroupA == 1 && noGroupB == 0){ + prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA; + } else { + prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA); + } } + LOG_D(MAC, "[RAPROC] - Selected RA preamble index %d for contention-based random access procedure... \n", prach_resources->ra_PreambleIndex); } // todo determine next available PRACH occasion @@ -284,7 +290,7 @@ void nr_get_prach_resources(module_id_t mod_id, prach_resources->ra_RNTI = 1 + s_id + 14 * t_id + 1120 * f_id + 8960 * ul_carrier_id; mac->ra_rnti = prach_resources->ra_RNTI; - LOG_D(MAC, "Computed ra_RNTI is %d", prach_resources->ra_RNTI); + LOG_D(MAC, "Computed ra_RNTI is %x \n", prach_resources->ra_RNTI); } // TbD: RA_attempt_number not used @@ -311,6 +317,7 @@ void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint /// Handling inizialization by PDCCH order, MAC entity or RRC (TS 38.300) /// Only one RA procedure is ongoing at any point in time in a MAC entity /// the RA procedure on a SCell shall only be initiated by PDCCH order +/// in the current implementation, RA is contention free only // WIP // todo TS 38.321: @@ -324,7 +331,6 @@ void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint // - retrieve TBS // - add mac_rrc_nr_data_req_ue, etc ... // - add the backoff condition here if we have it from a previous RA reponse which failed (i.e. backoff indicator) - void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, module_id_t mod_id, int CC_id, @@ -345,6 +351,8 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, NR_RACH_ConfigCommon_t *setup = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup; NR_RACH_ConfigGeneric_t *rach_ConfigGeneric = &setup->rach_ConfigGeneric; NR_FrequencyInfoDL_t *frequencyInfoDL = scc->downlinkConfigCommon->frequencyInfoDL; + NR_RACH_ConfigDedicated_t *rach_ConfigDedicated = mac->rach_ConfigDedicated; + // int32_t frame_diff = 0; uint8_t sdu_lcids[NB_RB_MAX] = {0}; @@ -485,7 +493,8 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, } // Fill in preamble and PRACH resources - nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 1, prach_resources, NULL); + if (is_nr_prach_slot) + nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 1, prach_resources, rach_ConfigDedicated); offset = nr_generate_ulsch_pdu((uint8_t *) mac_sdus, // sdus buffer (uint8_t *) payload, // UL MAC pdu pointer @@ -601,8 +610,11 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, mac->RA_tx_frame = frame; mac->RA_tx_subframe = nr_tti_tx; + // Fill in preamble and PRACH resources - nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 0, prach_resources, NULL); + if (is_nr_prach_slot) + nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 0, prach_resources, rach_ConfigDedicated); + } } } else if (UE_mode == PUSCH) { From 46a7b6c742c293de72995f252a3f6be21e6ff749 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 24 Apr 2020 18:59:59 +0200 Subject: [PATCH 196/553] bugfix in dci size for RA --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 146b3278b0..742a74ed9f 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -452,7 +452,6 @@ int nr_configure_pdcch(gNB_MAC_INST *nr_mac, pdcch_pdu->SubcarrierSpacing = bwp->bwp_Common->genericParameters.subcarrierSpacing; pdcch_pdu->CyclicPrefix = (bwp->bwp_Common->genericParameters.cyclicPrefix==NULL) ? 0 : *bwp->bwp_Common->genericParameters.cyclicPrefix; - // first symbol //AssertFatal(pdcch_scs==kHz15, "PDCCH SCS above 15kHz not allowed if a symbol above 2 is monitored"); int sps = bwp->bwp_Common->genericParameters.cyclicPrefix == NULL ? 14 : 12; @@ -807,7 +806,7 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, for (int d=0;dnumDlDci;d++) { uint64_t *dci_pdu = (uint64_t *)pdcch_pdu_rel15->dci_pdu.Payload[d]; - int dci_size = nr_dci_size(secondaryCellGroup,&dci_pdu_rel15[d],dci_formats[d],rnti_types[d],pdcch_pdu_rel15->BWPSize,bwp_id); + int dci_size = nr_dci_size(secondaryCellGroup,&dci_pdu_rel15[d],dci_formats[d],rnti_types[d],N_RB,bwp_id); pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d] = dci_size; AssertFatal(pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d]<=64, "DCI sizes above 64 bits not yet supported"); From 5cbb380efb34678e5d29ce7bf8aa0942b1436122 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Tue, 28 Apr 2020 14:08:19 +0200 Subject: [PATCH 197/553] almost empty function to handle uci indication --- openair2/NR_PHY_INTERFACE/NR_IF_Module.c | 75 ++---------------------- 1 file changed, 4 insertions(+), 71 deletions(-) diff --git a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c index 174e07cc33..f347a33581 100644 --- a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c @@ -76,76 +76,11 @@ void handle_nr_rach(NR_UL_IND_t *UL_info) { } -void handle_nr_sr(NR_UL_IND_t *UL_info) { - - - /* if (nfapi_mode == 1) // PNF - { - if (UL_info->sr_ind.sr_indication_body.number_of_srs>0) - { - // oai_nfapi_sr_indication(&UL_info->sr_ind); - } - } - else - { - - - for (int i=0;isr_ind.sr_indication_body.number_of_srs;i++) - SR_indication(UL_info->module_id, - UL_info->CC_id, - UL_info->frame, - UL_info->slot, - UL_info->sr_ind.sr_indication_body.sr_pdu_list[i].rx_ue_information.rnti, - UL_info->sr_ind.sr_indication_body.sr_pdu_list[i].ul_cqi_information.ul_cqi); - - - - } - - UL_info->sr_ind.sr_indication_body.number_of_srs=0;*/ +void handle_nr_uci(NR_UL_IND_t *UL_info) { + // TODO + UL_info->uci_ind.num_ucis = 0; } -void handle_nr_cqi(NR_UL_IND_t *UL_info) { - - /* - for (int i=0;icqi_ind.number_of_cqis;i++) - cqi_indication(UL_info->module_id, - UL_info->CC_id, - UL_info->frame, - UL_info->slot, - UL_info->cqi_ind.cqi_pdu_list[i].rx_ue_information.rnti, - &UL_info->cqi_ind.cqi_pdu_list[i].cqi_indication_rel9, - UL_info->cqi_ind.cqi_raw_pdu_list[i].pdu, - &UL_info->cqi_ind.cqi_pdu_list[i].ul_cqi_information); - - UL_info->cqi_ind.number_of_cqis=0;*/ - -} - -void handle_nr_harq(NR_UL_IND_t *UL_info) { - /* if (nfapi_mode == 1 && UL_info->harq_ind.harq_indication_body.number_of_harqs>0) { // PNF - //LOG_D(PHY, "UL_info->harq_ind.harq_indication_body.number_of_harqs:%d Send to VNF\n", UL_info->harq_ind.harq_indication_body.number_of_harqs); - int retval = oai_nfapi_harq_indication(&UL_info->harq_ind); - - if (retval!=0) { - LOG_E(PHY, "Failed to encode NFAPI HARQ_IND retval:%d\n", retval); - } - - UL_info->harq_ind.harq_indication_body.number_of_harqs = 0; - } - else - { - - for (int i=0;iharq_ind.harq_indication_body.number_of_harqs;i++) - harq_indication(UL_info->module_id, - UL_info->CC_id, - NFAPI_SFNSF2SFN(UL_info->harq_ind.sfn_sf), - NFAPI_SFNSF2SF(UL_info->harq_ind.sfn_sf), - &UL_info->harq_ind.harq_indication_body.harq_pdu_list[i]); - - UL_info->harq_ind.harq_indication_body.number_of_harqs=0; - }*/ -} void handle_nr_ulsch(NR_UL_IND_t *UL_info) { if(nfapi_mode == 1) { @@ -245,9 +180,7 @@ void NR_UL_indication(NR_UL_IND_t *UL_info) { // clear DL/UL info for new scheduling round clear_nr_nfapi_information(mac,CC_id,UL_info->frame,UL_info->slot); handle_nr_rach(UL_info); - handle_nr_sr(UL_info); - handle_nr_cqi(UL_info); - handle_nr_harq(UL_info); + handle_nr_uci(UL_info); // clear HI prior to handling ULSCH mac->UL_dci_req[CC_id].numPdus = 0; handle_nr_ulsch(UL_info); From eeef6da2aa3bd922603ec31215ae7416670ae2bc Mon Sep 17 00:00:00 2001 From: Ahmed Hussein Date: Tue, 28 Apr 2020 17:47:21 +0200 Subject: [PATCH 198/553] Fixed bug regarding TBS calculation and G calculation - The number of nb_dmrs_re at gNB side was set to 6, but here it is assumed that there will be no data allocation in OFDM symbols that carry DMRS - nb_dmrs_re that is being given as an input to the TBS calculation, should be multiplied by the number of DMRS symbols in order to get the total number of DMRS REs per RB - In the calculation of G, only the number of DMRS per RB in 1 OFDM symbol should be given as an input, because inside the function of the G calculation, this number is being multiplied by the number of OFDM symbols that carry DMRS --- openair1/SCHED_NR/phy_procedures_nr_gNB.c | 3 +-- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 2 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 9 ++++++++- 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index e8b685a885..247f5cb79d 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -226,7 +226,7 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH number_dmrs_symbols += ((pusch_pdu->ul_dmrs_symb_pos)>>l)&0x01; if (nodata_dmrs) - nb_re_dmrs = 12*number_dmrs_symbols; + nb_re_dmrs = 12; else nb_re_dmrs = ((pusch_pdu->dmrs_config_type == pusch_dmrs_type1)?6:4); @@ -241,7 +241,6 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH //---------------------------------------------------------- //------------------- ULSCH unscrambling ------------------- //---------------------------------------------------------- - start_meas(&gNB->ulsch_unscrambling_stats); nr_ulsch_unscrambling(gNB->pusch_vars[ULSCH_id]->llr, G, diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index 5a93d2abbf..baab2f5809 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -1452,7 +1452,7 @@ void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, R, pdsch_rel15->rbSize, N_sh_symb, - N_PRB_DMRS, + N_PRB_DMRS, // FIXME // This should be multiplied by the number of dmrs symbols N_PRB_oh, tb_scaling, pdsch_rel15->nrOfLayers)>>3; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 8f1a043221..3a8db970e8 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -792,11 +792,18 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, pusch_pdu->pusch_data.rv_index = 0; pusch_pdu->pusch_data.harq_process_id = 0; pusch_pdu->pusch_data.new_data_indicator = 0; + + uint8_t no_data_in_dmrs = 1; // temp implementation + uint8_t num_dmrs_symb = 0; + + for(int dmrs_counter = pusch_pdu->start_symbol_index; dmrs_counter < pusch_pdu->start_symbol_index + pusch_pdu->nr_of_symbols; dmrs_counter++) + num_dmrs_symb += ((pusch_pdu->ul_dmrs_symb_pos >> dmrs_counter) & 1); + pusch_pdu->pusch_data.tb_size = nr_compute_tbs(pusch_pdu->qam_mod_order, pusch_pdu->target_code_rate, pusch_pdu->rb_size, pusch_pdu->nr_of_symbols, - 6, //nb_re_dmrs - not sure where this is coming from - its not in the FAPI + ( no_data_in_dmrs ? 12 : ((pusch_pdu->dmrs_config_type == pusch_dmrs_type1) ? 6 : 4) ) * num_dmrs_symb, 0, //nb_rb_oh 0, pusch_pdu->nrOfLayers)>>3; From 4eb78faaa13d5b9d0692f066c7148a5315ae2bf7 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Tue, 28 Apr 2020 21:59:34 +0200 Subject: [PATCH 199/553] added harq stats in dlsim --- openair1/SIMULATION/NR_PHY/dlsim.c | 33 +++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/openair1/SIMULATION/NR_PHY/dlsim.c b/openair1/SIMULATION/NR_PHY/dlsim.c index 50ea3f21de..00552fc953 100644 --- a/openair1/SIMULATION/NR_PHY/dlsim.c +++ b/openair1/SIMULATION/NR_PHY/dlsim.c @@ -139,6 +139,9 @@ int main(int argc, char **argv) int i,aa;//,l; double sigma2, sigma2_dB=10, SNR, snr0=-2.0, snr1=2.0; uint8_t snr1set=0; + float roundStats[50]; + float psnr; + uint8_t snrRun; int **txdata; double **s_re,**s_im,**r_re,**r_im; //double iqim = 0.0; @@ -682,6 +685,7 @@ int main(int argc, char **argv) nr_ue_phy_config_request(&UE_mac->phy_config); NR_UE_list_t *UE_list = &RC.nrmac[0]->UE_list; NR_COMMON_channels_t *cc = RC.nrmac[0]->common_channels; + snrRun = 0; for (SNR = snr0; SNR < snr1; SNR += .2) { @@ -726,6 +730,8 @@ int main(int argc, char **argv) UE_harq_process->harq_ack.ack = 0; round = 0; + UE_harq_process->round = round; + UE_harq_process->first_tx = 1; while ((roundharq_ack.ack==0)) { memset(RC.nrmac[0]->cce_list[1][0],0,MAX_NUM_CCE*sizeof(int)); @@ -827,11 +833,7 @@ int main(int argc, char **argv) do_pdcch_flag, normal_txrx); - if (UE->dlsch[UE->current_thread_id[slot]][0][0]->last_iteration_cnt >= - UE->dlsch[UE->current_thread_id[slot]][0][0]->max_ldpc_iterations+1) - n_errors++; - - printf("dlsim round %d ends\n",round); + //printf("dlsim round %d ends\n",round); round++; } // round @@ -839,12 +841,13 @@ int main(int argc, char **argv) //---------------------- count errors ---------------------- //---------------------------------------------------------- - + if (UE->dlsch[UE->current_thread_id[slot]][0][0]->last_iteration_cnt >= + UE->dlsch[UE->current_thread_id[slot]][0][0]->max_ldpc_iterations+1) + n_errors++; NR_UE_PDSCH **pdsch_vars = UE->pdsch_vars[UE->current_thread_id[UE_proc.nr_tti_rx]]; int16_t *UE_llr = pdsch_vars[0]->llr[0]; - uint32_t TBS = rel15->TBSize[0]; uint16_t length_dmrs = 1; uint16_t nb_rb = rel15->rbSize; @@ -892,15 +895,16 @@ int main(int argc, char **argv) if (n_trials == 1) printf("errors_bit = %u (trial %d)\n", errors_bit, trial); } - + roundStats[snrRun]+=((float)round); } // noise trials + roundStats[snrRun]/=((float)n_trials); printf("*****************************************\n"); printf("SNR %f, (false positive %f)\n", SNR, (float) n_errors / (float) n_trials); printf("*****************************************\n"); printf("\n"); - printf("SNR %f : n_errors (negative CRC) = %d/%d, Channel BER %e\n", SNR, n_errors, n_trials,(double)errors_scrambling/available_bits/n_trials); + printf("SNR %f : n_errors (negative CRC) = %d/%d, Avg round %.2f, Channel BER %e\n", SNR, n_errors, n_trials,roundStats[snrRun],(double)errors_scrambling/available_bits/n_trials); printf("\n"); if (n_trials == 1) { @@ -910,7 +914,6 @@ int main(int argc, char **argv) LOG_M("rxsig1.m","rxs1", UE->common_vars.rxdata[1], frame_length_complex_samples, 1, 1); LOG_M("chestF0.m","chF0",UE->pdsch_vars[0][0]->dl_ch_estimates_ext,N_RB_DL*12*14,1,1); write_output("rxF_comp.m","rxFc",&UE->pdsch_vars[0][0]->rxdataF_comp0[0][0],N_RB_DL*12*14,1,1); - break; } if ((float)n_errors/(float)n_trials <= target_error_rate) { @@ -969,8 +972,18 @@ int main(int argc, char **argv) printStatIndent2(&UE->dlsch_tc_intl2_stats,"intl2+HardDecode+CRC"); */ } + snrRun++; } // NSR + if (n_trials>1) { + printf("HARQ stats:\nSNR\tRounds\n"); + psnr = snr0; + for (uint8_t i=0; i Date: Tue, 28 Apr 2020 17:54:38 +0200 Subject: [PATCH 200/553] Fixed bug related to N_TA_offset not being applied at UE - By default this value is equal to 0 at gNB in case of ulsim, but has a value in case of RF simulator - The N_TA_offset was calculated but not used at UE side --- openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c | 52 +++++++++++++++++----- 1 file changed, 41 insertions(+), 11 deletions(-) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c index 14c70e6582..769cea37a1 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c @@ -537,21 +537,51 @@ uint8_t nr_ue_pusch_common_procedures(PHY_VARS_NR_UE *UE, txdata = UE->common_vars.txdata; txdataF = UE->common_vars.txdataF; - for (ap = 0; ap < Nl; ap++) { + if(UE->N_TA_offset > tx_offset) { + int32_t *tmp_idft_out = (int32_t*)malloc16(frame_parms->get_samples_per_slot(slot, frame_parms) * sizeof(int32_t)); + + for(ap = 0; ap < Nl; ap++) { if (frame_parms->Ncp == 1) { // extended cyclic prefix - PHY_ofdm_mod(txdataF[ap], - &txdata[ap][tx_offset], - frame_parms->ofdm_symbol_size, - 12, - frame_parms->nb_prefix_samples, - CYCLIC_PREFIX); + PHY_ofdm_mod(txdataF[ap], + tmp_idft_out, + frame_parms->ofdm_symbol_size, + 12, + frame_parms->nb_prefix_samples, + CYCLIC_PREFIX); } else { // normal cyclic prefix - nr_normal_prefix_mod(txdataF[ap], - &txdata[ap][tx_offset], - 14, - frame_parms); + nr_normal_prefix_mod(txdataF[ap], + tmp_idft_out, + 14, + frame_parms); + } + + memcpy((void *) &txdata[ap][frame_parms->samples_per_frame - UE->N_TA_offset + tx_offset], + (void *) tmp_idft_out, + (UE->N_TA_offset - tx_offset) * sizeof(int32_t)); + + memcpy((void *) &txdata[ap][0], + (void *) &tmp_idft_out[UE->N_TA_offset - tx_offset], + (frame_parms->get_samples_per_slot(slot, frame_parms) - UE->N_TA_offset + tx_offset) * sizeof(int32_t)); + } + + free(tmp_idft_out); + } else { // UE->N_TA_offset <= tx_offset + for (ap = 0; ap < Nl; ap++) { + if (frame_parms->Ncp == 1) { // extended cyclic prefix + PHY_ofdm_mod(txdataF[ap], + &txdata[ap][tx_offset-UE->N_TA_offset], + frame_parms->ofdm_symbol_size, + 12, + frame_parms->nb_prefix_samples, + CYCLIC_PREFIX); + } else { // normal cyclic prefix + nr_normal_prefix_mod(txdataF[ap], + &txdata[ap][tx_offset-UE->N_TA_offset], + 14, + frame_parms); } } + } /////////// //////////////////////////////////////////////////// From 86bc794518e3e9bbf01a863c9df1cedf1b171a0b Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Wed, 29 Apr 2020 14:00:32 +0200 Subject: [PATCH 201/553] bugfix in dmrs reception for pusch --- openair1/PHY/NR_REFSIG/nr_dmrs_rx.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c b/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c index b1b038e918..a844ac9868 100644 --- a/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c +++ b/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c @@ -63,7 +63,7 @@ int nr_pusch_dmrs_rx(PHY_VARS_gNB *gNB, int8_t w, nb_dmrs; short *mod_table; unsigned char idx=0; - + int k; typedef int array_of_w[2]; array_of_w *wf; array_of_w *wt; @@ -77,18 +77,18 @@ int nr_pusch_dmrs_rx(PHY_VARS_gNB *gNB, if (gNB->frame_parms.Ncp == NORMAL) { nb_dmrs = ((dmrs_type==pusch_dmrs_type1) ? 6:4); for (int i=re_offset; i>5])>>((i<<1)&0x1f))&1)<<1) ^ (((nr_gold_pusch[((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1); - ((int16_t*)output)[i<<1] = mod_table[(NR_MOD_TABLE_QPSK_OFFSET + idx)<<1]; - ((int16_t*)output)[(i<<1)+1] = mod_table[((NR_MOD_TABLE_QPSK_OFFSET + idx)<<1) + 1]; + ((int16_t*)output)[k<<1] = mod_table[(NR_MOD_TABLE_QPSK_OFFSET + idx)<<1]; + ((int16_t*)output)[(k<<1)+1] = mod_table[((NR_MOD_TABLE_QPSK_OFFSET + idx)<<1) + 1]; #ifdef DEBUG_PUSCH printf("nr_pusch_dmrs_rx dmrs config type %d port %d nb_pusch_rb %d\n", dmrs_type, p, nb_pusch_rb); printf("wf[%d] = %d wt[%d]= %d\n", i&1, wf[p-1000][i&1], lp, wt[p-1000][lp]); printf("i %d idx %d pusch gold %u b0-b1 %d-%d mod_dmrs %d %d\n", i, idx, nr_gold_pusch[(i<<1)>>5], (((nr_gold_pusch[(i<<1)>>5])>>((i<<1)&0x1f))&1), - (((nr_gold_pusch[((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1), ((int16_t*)output)[i<<1], ((int16_t*)output)[(i<<1)+1]); + (((nr_gold_pusch[((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1), ((int16_t*)output)[k<<1], ((int16_t*)output)[(k<<1)+1]); #endif } From 2f9bf0d84c0cb7ae57343494a3bb8a0c8d760359 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Mon, 4 May 2020 08:19:48 +0200 Subject: [PATCH 202/553] added file reading for ulsim --- openair1/PHY/INIT/nr_init.c | 1 + openair1/PHY/MODULATION/slot_fep_nr.c | 4 +- .../NR_ESTIMATION/nr_ul_channel_estimation.c | 18 +- openair1/PHY/NR_REFSIG/nr_dmrs_rx.c | 2 +- .../PHY/NR_TRANSPORT/nr_ulsch_demodulation.c | 62 +- openair1/SIMULATION/NR_PHY/ulsim.c | 544 ++++++++++-------- 6 files changed, 366 insertions(+), 265 deletions(-) diff --git a/openair1/PHY/INIT/nr_init.c b/openair1/PHY/INIT/nr_init.c index 85e1079c5b..57e15234ac 100644 --- a/openair1/PHY/INIT/nr_init.c +++ b/openair1/PHY/INIT/nr_init.c @@ -176,6 +176,7 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, } uint32_t Nid_pusch[2] = {cfg->cell_config.phy_cell_id.value,cfg->cell_config.phy_cell_id.value}; + LOG_D(PHY,"Initializing PUSCH DMRS Gold sequence with (%x,%x)\n",Nid_pusch[1],Nid_pusch[2]); nr_gold_pusch(gNB, &Nid_pusch[0]); /// Transport init necessary for NR synchro diff --git a/openair1/PHY/MODULATION/slot_fep_nr.c b/openair1/PHY/MODULATION/slot_fep_nr.c index 8feb5f13b9..5c704f3adf 100644 --- a/openair1/PHY/MODULATION/slot_fep_nr.c +++ b/openair1/PHY/MODULATION/slot_fep_nr.c @@ -456,13 +456,15 @@ int nr_slot_fep_ul(NR_DL_FRAME_PARMS *frame_parms, memcpy((void *)&tmp_dft_in[sample_offset-rxdata_offset], (void *) &rxdata[0], (frame_parms->ofdm_symbol_size-sample_offset+rxdata_offset)*sizeof(int)); - + dft((int16_t *)&tmp_dft_in, (int16_t *)&rxdataF[symbol * frame_parms->ofdm_symbol_size], 1); } else dft((int16_t *)&rxdata[rxdata_offset-sample_offset], (int16_t *)&rxdataF[symbol * frame_parms->ofdm_symbol_size], 1); + // clear DC carrier from OFDM symbols + rxdataF[symbol * frame_parms->ofdm_symbol_size] = 0; return(0); } diff --git a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c index 94da06dd8b..d3ceae74e2 100644 --- a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c +++ b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c @@ -28,7 +28,7 @@ #include "PHY/NR_UE_ESTIMATION/filt16a_32.h" //#define DEBUG_CH - +//#define DEBUG_PUSCH int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, unsigned char Ns, @@ -116,7 +116,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, //------------------generate DMRS------------------// - if (pusch_pdu->transform_precoding) // if transform precoding is disabled + if (pusch_pdu->transform_precoding==0) // if transform precoding is disabled nr_pusch_dmrs_rx(gNB, Ns, gNB->nr_gold_pusch_dmrs[pusch_pdu->scid][Ns][symbol], &pilot[0], 1000, 0, nb_rb_pusch, pusch_pdu->rb_start*NR_NB_SC_PER_RB, pusch_pdu->dmrs_config_type); else nr_pusch_dmrs_rx(gNB, Ns, gNB->nr_gold_pusch_dmrs[pusch_pdu->scid][Ns][symbol], &pilot[0], 1000, 0, nb_rb_pusch, 0, pusch_pdu->dmrs_config_type); @@ -132,8 +132,9 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, memset(ul_ch,0,4*(gNB->frame_parms.ofdm_symbol_size)); #ifdef DEBUG_PUSCH + printf("symbol_offset %d, nushift %d\n",symbol_offset,nushift); printf("ch est pilot addr %p RB_DL %d\n",&pilot[0], gNB->frame_parms.N_RB_UL); - printf("k %d, first_carrier %d\n",k,gNB->frame_parms.first_carrier_offset); + printf("bwp_start_subcarrier %d, k %d, first_carrier %d\n",bwp_start_subcarrier,k,gNB->frame_parms.first_carrier_offset); printf("rxF addr %p p %d\n", rxF,p); printf("ul_ch addr %p nushift %d\n",ul_ch,nushift); #endif @@ -148,7 +149,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, #ifdef DEBUG_PUSCH printf("ch 0 %d\n",((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])); printf("pilot 0 : rxF - > (%d,%d) addr %p ch -> (%d,%d), pil -> (%d,%d) \n",rxF[0],rxF[1],&rxF[0],ch[0],ch[1],pil[0],pil[1]); - printf("data 0 : rxF - > (%d,%d) addr %p ch -> (%d,%d), pil -> (%d,%d) \n",rxF[2],rxF[3],&rxF[2],ch[0],ch[1],pil[0],pil[1]); + printf("data 0 : rxF - > (%d,%d)\n",rxF[2],rxF[3]); #endif multadd_real_vector_complex_scalar(fl, @@ -166,6 +167,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, #ifdef DEBUG_PUSCH printf("pilot 1 : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); + printf("data 1 : rxF - > (%d,%d)\n",rxF[2],rxF[3]); #endif multadd_real_vector_complex_scalar(fml, ch, @@ -181,6 +183,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, #ifdef DEBUG_PUSCH printf("pilot 2 : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); + printf("data 2 : rxF - > (%d,%d)\n",rxF[2],rxF[3]); #endif multadd_real_vector_complex_scalar(fmm, ch, @@ -201,7 +204,8 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); #ifdef DEBUG_PUSCH - printf("pilot 1 : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); + printf("pilot %d : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); + printf("data %d : rxF - > (%d,%d)\n",pilot_cnt,rxF[2],rxF[3]); #endif multadd_real_vector_complex_scalar(fml, ch, @@ -217,6 +221,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, #ifdef DEBUG_PUSCH printf("pilot %u : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt+1,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); + printf("data %d : rxF - > (%d,%d)\n",pilot_cnt+1,rxF[2],rxF[3]); #endif multadd_real_vector_complex_scalar(fmm, ch, @@ -238,6 +243,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); #ifdef DEBUG_PUSCH printf("pilot %u : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); + printf("data %d : rxF - > (%d,%d)\n",pilot_cnt,rxF[2],rxF[3]); #endif multadd_real_vector_complex_scalar(fm, ch, @@ -256,6 +262,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, #ifdef DEBUG_PUSCH printf("ch 0 %d\n",((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])); printf("pilot %u: rxF - > (%d,%d) addr %p ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt+1,rxF[0],rxF[1],&rxF[0],ch[0],ch[1],pil[0],pil[1]); + printf("data %d : rxF - > (%d,%d)\n",pilot_cnt+1,rxF[2],rxF[3]); #endif multadd_real_vector_complex_scalar(fmr, ch, @@ -271,6 +278,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); #ifdef DEBUG_PUSCH printf("pilot %u: rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt+2,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); + printf("data %d : rxF - > (%d,%d)\n",pilot_cnt+2,rxF[2],rxF[3]); #endif multadd_real_vector_complex_scalar(fr, ch, diff --git a/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c b/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c index a844ac9868..1f2687b883 100644 --- a/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c +++ b/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c @@ -32,7 +32,7 @@ //#define NR_PBCH_DMRS_LENGTH_DWORD 5 //#define NR_PBCH_DMRS_LENGTH 144 -//#define DEBUG_PDCCH +//#define DEBUG_PUSCH #include "refsig_defs_ue.h" #include "PHY/defs_nr_UE.h" diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c index b09f911029..3134713d4a 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c @@ -1014,7 +1014,7 @@ void nr_ulsch_channel_compensation(int **rxdataF_ext, } void nr_rx_pusch(PHY_VARS_gNB *gNB, - uint8_t UE_id, + uint8_t ulsch_id, uint32_t frame, uint8_t nr_tti_rx, unsigned char symbol, @@ -1027,23 +1027,23 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, int avgs; int avg[4]; NR_DL_FRAME_PARMS *frame_parms = &gNB->frame_parms; - nfapi_nr_pusch_pdu_t *rel15_ul = &gNB->ulsch[UE_id][0]->harq_processes[harq_pid]->ulsch_pdu; + nfapi_nr_pusch_pdu_t *rel15_ul = &gNB->ulsch[ulsch_id][0]->harq_processes[harq_pid]->ulsch_pdu; uint8_t nodata_dmrs = 1; // FIXME to be properly configured from fapi dmrs_symbol_flag = 0; ptrs_symbol_flag = 0; - gNB->pusch_vars[UE_id]->ptrs_sc_per_ofdm_symbol = 0; + gNB->pusch_vars[ulsch_id]->ptrs_sc_per_ofdm_symbol = 0; if(symbol == rel15_ul->start_symbol_index){ - gNB->pusch_vars[UE_id]->rxdataF_ext_offset = 0; - gNB->pusch_vars[UE_id]->dmrs_symbol = 0; - gNB->pusch_vars[UE_id]->cl_done = 0; - gNB->pusch_vars[UE_id]->ptrs_symbols = 0; + gNB->pusch_vars[ulsch_id]->rxdataF_ext_offset = 0; + gNB->pusch_vars[ulsch_id]->dmrs_symbol = 0; + gNB->pusch_vars[ulsch_id]->cl_done = 0; + gNB->pusch_vars[ulsch_id]->ptrs_symbols = 0; if ( ((rel15_ul->pdu_bit_map)>>2)& 0x01 ) { // if there is ptrs pdu L_ptrs = 1<<(rel15_ul->pusch_ptrs.ptrs_time_density); - set_ptrs_symb_idx(&gNB->pusch_vars[UE_id]->ptrs_symbols, + set_ptrs_symb_idx(&gNB->pusch_vars[ulsch_id]->ptrs_symbols, rel15_ul->nr_of_symbols, rel15_ul->start_symbol_index, rel15_ul->dmrs_config_type, @@ -1064,7 +1064,7 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, nb_re_pusch = 0; else nb_re_pusch = rel15_ul->rb_size * ((rel15_ul->dmrs_config_type==pusch_dmrs_type1)?6:8); - gNB->pusch_vars[UE_id]->dmrs_symbol = symbol; + gNB->pusch_vars[ulsch_id]->dmrs_symbol = symbol; } else { nb_re_pusch = rel15_ul->rb_size * NR_NB_SC_PER_RB; } @@ -1077,7 +1077,7 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, rel15_ul->nr_of_symbols, 0, (rel15_ul->pusch_ptrs.ptrs_freq_density)?4:2, - gNB->pusch_vars[UE_id]->ptrs_symbols, + gNB->pusch_vars[ulsch_id]->ptrs_symbols, 0, frame_parms->ofdm_symbol_size, rel15_ul->dmrs_config_type, @@ -1085,7 +1085,7 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, } if (ptrs_symbol_flag == 1){ - gNB->pusch_vars[UE_id]->ptrs_symbol_index = symbol; + gNB->pusch_vars[ulsch_id]->ptrs_symbol_index = symbol; } @@ -1110,25 +1110,25 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, start_meas(&gNB->ulsch_rbs_extraction_stats); nr_ulsch_extract_rbs_single(gNB->common_vars.rxdataF, - gNB->pusch_vars[UE_id], + gNB->pusch_vars[ulsch_id], symbol, dmrs_symbol_flag, rel15_ul, frame_parms); stop_meas(&gNB->ulsch_rbs_extraction_stats); - nr_ulsch_scale_channel(gNB->pusch_vars[UE_id]->ul_ch_estimates_ext, + nr_ulsch_scale_channel(gNB->pusch_vars[ulsch_id]->ul_ch_estimates_ext, frame_parms, - gNB->ulsch[UE_id], + gNB->ulsch[ulsch_id], symbol, dmrs_symbol_flag, rel15_ul->rb_size, rel15_ul->dmrs_config_type); - if (gNB->pusch_vars[UE_id]->cl_done==0) { + if (gNB->pusch_vars[ulsch_id]->cl_done==0) { - nr_ulsch_channel_level(gNB->pusch_vars[UE_id]->ul_ch_estimates_ext, + nr_ulsch_channel_level(gNB->pusch_vars[ulsch_id]->ul_ch_estimates_ext, frame_parms, avg, symbol, @@ -1141,26 +1141,26 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, for (aarx=0;aarxnb_antennas_rx;aarx++) avgs = cmax(avgs,avg[(aatx<<1)+aarx]); - gNB->pusch_vars[UE_id]->log2_maxh = (log2_approx(avgs)/2)+1; - gNB->pusch_vars[UE_id]->cl_done = 1; + gNB->pusch_vars[ulsch_id]->log2_maxh = (log2_approx(avgs)/2)+1; + gNB->pusch_vars[ulsch_id]->cl_done = 1; } start_meas(&gNB->ulsch_channel_compensation_stats); - nr_ulsch_channel_compensation(gNB->pusch_vars[UE_id]->rxdataF_ext, - gNB->pusch_vars[UE_id]->ul_ch_estimates_ext, - gNB->pusch_vars[UE_id]->ul_ch_mag0, - gNB->pusch_vars[UE_id]->ul_ch_magb0, - gNB->pusch_vars[UE_id]->rxdataF_comp, - (frame_parms->nb_antennas_tx>1) ? gNB->pusch_vars[UE_id]->rho : NULL, + nr_ulsch_channel_compensation(gNB->pusch_vars[ulsch_id]->rxdataF_ext, + gNB->pusch_vars[ulsch_id]->ul_ch_estimates_ext, + gNB->pusch_vars[ulsch_id]->ul_ch_mag0, + gNB->pusch_vars[ulsch_id]->ul_ch_magb0, + gNB->pusch_vars[ulsch_id]->rxdataF_comp, + (frame_parms->nb_antennas_tx>1) ? gNB->pusch_vars[ulsch_id]->rho : NULL, frame_parms, symbol, dmrs_symbol_flag, rel15_ul->qam_mod_order, rel15_ul->rb_size, - gNB->pusch_vars[UE_id]->log2_maxh); + gNB->pusch_vars[ulsch_id]->log2_maxh); stop_meas(&gNB->ulsch_channel_compensation_stats); #ifdef NR_SC_FDMA - nr_idft(&((uint32_t*)gNB->pusch_vars[UE_id]->rxdataF_ext[0])[symbol * rel15_ul->rb_size * NR_NB_SC_PER_RB], nb_re_pusch); + nr_idft(&((uint32_t*)gNB->pusch_vars[ulsch_id]->rxdataF_ext[0])[symbol * rel15_ul->rb_size * NR_NB_SC_PER_RB], nb_re_pusch); #endif //---------------------------------------------------------- @@ -1168,10 +1168,10 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, //---------------------------------------------------------- start_meas(&gNB->ulsch_llr_stats); - nr_ulsch_compute_llr(&gNB->pusch_vars[UE_id]->rxdataF_comp[0][symbol * rel15_ul->rb_size * NR_NB_SC_PER_RB], - gNB->pusch_vars[UE_id]->ul_ch_mag0, - gNB->pusch_vars[UE_id]->ul_ch_magb0, - &gNB->pusch_vars[UE_id]->llr[gNB->pusch_vars[UE_id]->rxdataF_ext_offset * rel15_ul->qam_mod_order], + nr_ulsch_compute_llr(&gNB->pusch_vars[ulsch_id]->rxdataF_comp[0][symbol * rel15_ul->rb_size * NR_NB_SC_PER_RB], + gNB->pusch_vars[ulsch_id]->ul_ch_mag0, + gNB->pusch_vars[ulsch_id]->ul_ch_magb0, + &gNB->pusch_vars[ulsch_id]->llr[gNB->pusch_vars[ulsch_id]->rxdataF_ext_offset * rel15_ul->qam_mod_order], rel15_ul->rb_size, nb_re_pusch, symbol, @@ -1180,6 +1180,6 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, } - gNB->pusch_vars[UE_id]->rxdataF_ext_offset = gNB->pusch_vars[UE_id]->rxdataF_ext_offset + nb_re_pusch; + gNB->pusch_vars[ulsch_id]->rxdataF_ext_offset = gNB->pusch_vars[ulsch_id]->rxdataF_ext_offset + nb_re_pusch; } diff --git a/openair1/SIMULATION/NR_PHY/ulsim.c b/openair1/SIMULATION/NR_PHY/ulsim.c index b3d0d11606..4c43eb87ff 100644 --- a/openair1/SIMULATION/NR_PHY/ulsim.c +++ b/openair1/SIMULATION/NR_PHY/ulsim.c @@ -114,7 +114,7 @@ int main(int argc, char **argv) double sigma, sigma_dB; double snr_step = 1; uint8_t snr1set = 0; - int slot = 0, frame = 0; + int slot = 17, frame = 0; FILE *output_fd = NULL; //uint8_t write_output_file = 0; int trial, n_trials = 1, n_errors = 0, n_false_positive = 0, delay = 0; @@ -147,12 +147,13 @@ int main(int argc, char **argv) float target_error_rate = 0.01; int print_perf = 0; cpuf = get_cpu_freq_GHz(); - + int msg3_flag = 0; UE_nr_rxtx_proc_t UE_proc; FILE *scg_fd=NULL; - + int ibwp_size=24; + int ibwp_rboffset=41; if ( load_configmodule(argc,argv,CONFIG_ENABLECMDLINEONLY) == 0 ) { exit_fun("[NR_ULSIM] Error, configuration module init failed\n"); } @@ -160,202 +161,226 @@ int main(int argc, char **argv) //logInit(); randominit(0); - while ((c = getopt(argc, argv, "d:f:g:h:i:j:l:m:n:p:r:s:y:z:F:M:N:PR:S:L:")) != -1) { + while ((c = getopt(argc, argv, "a:b:c:d:ef:g:h:i:j:kl:m:n:p:r:s:y:z:F:M:N:PR:S:L:")) != -1) { + printf("handling optarg %c\n",c); switch (c) { /*case 'd': frame_type = 1; break;*/ - case 'd': - delay = atoi(optarg); - break; + case 'a': + start_symbol = atoi(optarg); + AssertFatal(start_symbol >= 0 && start_symbol < 13,"start_symbol %d is not in 0..12\n",start_symbol); + break; - case 'f': - scg_fd = fopen(optarg, "r"); + case 'b': + nb_symb_sch = atoi(optarg); + AssertFatal(nb_symb_sch > 0 && nb_symb_sch < 15,"start_symbol %d is not in 1..14\n",nb_symb_sch); + break; + case 'c': + n_rnti = atoi(optarg); + AssertFatal(n_rnti > 0 && n_rnti<=65535,"Illegal n_rnti %x\n",n_rnti); + break; - if (scg_fd == NULL) { - printf("Error opening %s\n", optarg); - exit(-1); - } - - break; - - case 'g': - switch ((char) *optarg) { - case 'A': - channel_model = SCM_A; - break; - - case 'B': - channel_model = SCM_B; - break; - - case 'C': - channel_model = SCM_C; - break; - - case 'D': - channel_model = SCM_D; - break; - - case 'E': - channel_model = EPA; - break; - - case 'F': - channel_model = EVA; - break; - - case 'G': - channel_model = ETU; - break; - - default: - printf("Unsupported channel model!\n"); - exit(-1); - } - - break; + case 'd': + delay = atoi(optarg); + break; + + case 'e': + msg3_flag = 1; + break; + + case 'f': + scg_fd = fopen(optarg, "r"); + + if (scg_fd == NULL) { + printf("Error opening %s\n", optarg); + exit(-1); + } + break; + + case 'g': + switch ((char) *optarg) { + case 'A': + channel_model = SCM_A; + break; + + case 'B': + channel_model = SCM_B; + break; + + case 'C': + channel_model = SCM_C; + break; + + case 'D': + channel_model = SCM_D; + break; + + case 'E': + channel_model = EPA; + break; + + case 'F': + channel_model = EVA; + break; + + case 'G': + channel_model = ETU; + break; + + default: + printf("Unsupported channel model!\n"); + exit(-1); + } + + break; + /*case 'i': interf1 = atoi(optarg); break; - - case 'j': + + case 'j': interf2 = atoi(optarg); break;*/ - case 'l': - nb_symb_sch = atoi(optarg); - break; - - case 'm': - Imcs = atoi(optarg); - break; - - case 'n': - n_trials = atoi(optarg); - break; - - case 'p': - extended_prefix_flag = 1; - break; - - case 'r': - nb_rb = atoi(optarg); - break; - - case 's': - snr0 = atof(optarg); - printf("Setting SNR0 to %f\n", snr0); - break; + case 'k': + printf("Setting threequarter_fs_flag\n"); + openair0_cfg[0].threequarter_fs= 1; + break; + case 'l': + nb_symb_sch = atoi(optarg); + break; + + case 'm': + Imcs = atoi(optarg); + break; + + case 'n': + n_trials = atoi(optarg); + break; + + case 'p': + extended_prefix_flag = 1; + break; + + case 'r': + nb_rb = atoi(optarg); + break; + + case 's': + snr0 = atof(optarg); + printf("Setting SNR0 to %f\n", snr0); + break; + /* - case 'r': - ricean_factor = pow(10,-.1*atof(optarg)); - if (ricean_factor>1) { - printf("Ricean factor must be between 0 and 1\n"); - exit(-1); - } - break; - */ - + case 'r': + ricean_factor = pow(10,-.1*atof(optarg)); + if (ricean_factor>1) { + printf("Ricean factor must be between 0 and 1\n"); + exit(-1); + } + break; + */ + /*case 'x': transmission_mode = atoi(optarg); break;*/ - - case 'y': - n_tx = atoi(optarg); - - if ((n_tx == 0) || (n_tx > 2)) { - printf("Unsupported number of tx antennas %d\n", n_tx); - exit(-1); - } - - break; - - case 'z': - n_rx = atoi(optarg); - - if ((n_rx == 0) || (n_rx > 2)) { - printf("Unsupported number of rx antennas %d\n", n_rx); - exit(-1); - } - - break; - - case 'F': - input_fd = fopen(optarg, "r"); - - if (input_fd == NULL) { - printf("Problem with filename %s\n", optarg); - exit(-1); - } - - break; - - case 'M': - SSB_positions = atoi(optarg); - break; - - case 'N': - Nid_cell = atoi(optarg); - break; - - case 'R': - N_RB_DL = atoi(optarg); - N_RB_UL = N_RB_DL; - break; - - case 'S': - snr1 = atof(optarg); - snr1set = 1; - printf("Setting SNR1 to %f\n", snr1); - break; - - case 'P': - print_perf=1; - opp_enabled=1; - break; - - case 'L': - loglvl = atoi(optarg); - break; - - default: - case 'h': - printf("%s -h(elp) -p(extended_prefix) -N cell_id -f output_filename -F input_filename -g channel_model -n n_frames -t Delayspread -s snr0 -S snr1 -x transmission_mode -y TXant -z RXant -i Intefrence0 -j Interference1 -A interpolation_file -C(alibration offset dB) -N CellId\n", argv[0]); - //printf("-d Use TDD\n"); - printf("-d Introduce delay in terms of number of samples\n"); - printf("-f Number of frames to simulate\n"); - printf("-g [A,B,C,D,E,F,G] Use 3GPP SCM (A,B,C,D) or 36-101 (E-EPA,F-EVA,G-ETU) models (ignores delay spread and Ricean factor)\n"); - printf("-h This message\n"); - //printf("-i Relative strength of first intefering eNB (in dB) - cell_id mod 3 = 1\n"); - //printf("-j Relative strength of second intefering eNB (in dB) - cell_id mod 3 = 2\n"); - printf("-s Starting SNR, runs from SNR0 to SNR0 + 10 dB if ending SNR isn't given\n"); - printf("-m MCS value\n"); - printf("-n Number of trials to simulate\n"); - printf("-p Use extended prefix mode\n"); - printf("-t Delay spread for multipath channel\n"); - //printf("-x Transmission mode (1,2,6 for the moment)\n"); - printf("-y Number of TX antennas used in eNB\n"); - printf("-z Number of RX antennas used in UE\n"); - printf("-A Interpolation_filname Run with Abstraction to generate Scatter plot using interpolation polynomial in file\n"); - //printf("-C Generate Calibration information for Abstraction (effective SNR adjustment to remove Pe bias w.r.t. AWGN)\n"); - printf("-F Input filename (.txt format) for RX conformance testing\n"); - printf("-G raw file containing RRC configuration (generated by gNB)\n"); - printf("-M Multiple SSB positions in burst\n"); - printf("-N Nid_cell\n"); - printf("-O oversampling factor (1,2,4,8,16)\n"); - printf("-R N_RB_DL\n"); - printf("-S Ending SNR, runs from SNR0 to SNR1\n"); - printf("-P Print ULSCH performances\n"); - exit(-1); - break; + + case 'y': + n_tx = atoi(optarg); + + if ((n_tx == 0) || (n_tx > 2)) { + printf("Unsupported number of tx antennas %d\n", n_tx); + exit(-1); + } + + break; + + case 'z': + n_rx = atoi(optarg); + + if ((n_rx == 0) || (n_rx > 2)) { + printf("Unsupported number of rx antennas %d\n", n_rx); + exit(-1); + } + + break; + + case 'F': + input_fd = fopen(optarg, "r"); + + if (input_fd == NULL) { + printf("Problem with filename %s\n", optarg); + exit(-1); + } + + break; + + case 'M': + SSB_positions = atoi(optarg); + break; + + case 'N': + Nid_cell = atoi(optarg); + break; + + case 'R': + N_RB_DL = atoi(optarg); + N_RB_UL = N_RB_DL; + break; + + case 'S': + snr1 = atof(optarg); + snr1set = 1; + printf("Setting SNR1 to %f\n", snr1); + break; + + case 'P': + print_perf=1; + opp_enabled=1; + break; + + case 'L': + loglvl = atoi(optarg); + break; + + default: + case 'h': + printf("%s -h(elp) -p(extended_prefix) -N cell_id -f output_filename -F input_filename -g channel_model -n n_frames -t Delayspread -s snr0 -S snr1 -x transmission_mode -y TXant -z RXant -i Intefrence0 -j Interference1 -A interpolation_file -C(alibration offset dB) -N CellId\n", argv[0]); + //printf("-d Use TDD\n"); + printf("-d Introduce delay in terms of number of samples\n"); + printf("-f Number of frames to simulate\n"); + printf("-g [A,B,C,D,E,F,G] Use 3GPP SCM (A,B,C,D) or 36-101 (E-EPA,F-EVA,G-ETU) models (ignores delay spread and Ricean factor)\n"); + printf("-h This message\n"); + //printf("-i Relative strength of first intefering eNB (in dB) - cell_id mod 3 = 1\n"); + //printf("-j Relative strength of second intefering eNB (in dB) - cell_id mod 3 = 2\n"); + printf("-s Starting SNR, runs from SNR0 to SNR0 + 10 dB if ending SNR isn't given\n"); + printf("-m MCS value\n"); + printf("-n Number of trials to simulate\n"); + printf("-p Use extended prefix mode\n"); + printf("-t Delay spread for multipath channel\n"); + //printf("-x Transmission mode (1,2,6 for the moment)\n"); + printf("-y Number of TX antennas used in eNB\n"); + printf("-z Number of RX antennas used in UE\n"); + printf("-A Interpolation_filname Run with Abstraction to generate Scatter plot using interpolation polynomial in file\n"); + //printf("-C Generate Calibration information for Abstraction (effective SNR adjustment to remove Pe bias w.r.t. AWGN)\n"); + printf("-F Input filename (.txt format) for RX conformance testing\n"); + printf("-G raw file containing RRC configuration (generated by gNB)\n"); + printf("-M Multiple SSB positions in burst\n"); + printf("-N Nid_cell\n"); + printf("-O oversampling factor (1,2,4,8,16)\n"); + printf("-R N_RB_DL\n"); + printf("-S Ending SNR, runs from SNR0 to SNR1\n"); + printf("-P Print ULSCH performances\n"); + exit(-1); + break; } } - + logInit(); set_glog(loglvl); T_stdout = 1; @@ -387,12 +412,15 @@ int main(int argc, char **argv) gNB->UL_INFO.rx_ind.number_of_pdus = 0; gNB->UL_INFO.crc_ind.number_crcs = 0; frame_parms = &gNB->frame_parms; //to be initialized I suppose (maybe not necessary for PBCH) + + frame_parms->nb_antennas_tx = n_tx; frame_parms->nb_antennas_rx = n_rx; frame_parms->N_RB_DL = N_RB_DL; frame_parms->N_RB_UL = N_RB_UL; frame_parms->Ncp = extended_prefix_flag ? EXTENDED : NORMAL; + RC.nb_nr_macrlc_inst = 1; RC.nb_nr_mac_CC = (int*)malloc(RC.nb_nr_macrlc_inst*sizeof(int)); for (i = 0; i < RC.nb_nr_macrlc_inst; i++) @@ -421,6 +449,7 @@ int main(int argc, char **argv) xer_fprint(stdout, &asn_DEF_NR_CellGroupConfig, (const void*)secondaryCellGroup); AssertFatal((gNB->if_inst = NR_IF_Module_init(0))!=NULL,"Cannot register interface"); + gNB->if_inst->NR_PHY_config_req = nr_phy_config_request; // common configuration rrc_mac_config_req_gNB(0,0,1,scc,0,0,NULL); @@ -429,6 +458,10 @@ int main(int argc, char **argv) phy_init_nr_gNB(gNB,0,0); N_RB_DL = gNB->frame_parms.N_RB_DL; + + + NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[0]; + //crcTableInit(); //nr_phy_config_request_sim(gNB, N_RB_DL, N_RB_UL, mu, Nid_cell, SSB_positions); @@ -570,6 +603,25 @@ int main(int argc, char **argv) UL_tti_req->pdus_list[0].pdu_size = sizeof(nfapi_nr_pusch_pdu_t); memset(pusch_pdu,0,sizeof(nfapi_nr_pusch_pdu_t)); + int abwp_size = NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275); + int abwp_start = NRRIV2PRBOFFSET(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275); + int ibwp_size = ibwp_size; + int ibwp_start = ibwp_rboffset; + if (msg3_flag == 1) { + if ((ibwp_start < abwp_start) || (ibwp_size > abwp_size)) + pusch_pdu->bwp_start = abwp_start; + else + pusch_pdu->bwp_start = ibwp_start; + pusch_pdu->bwp_size = ibwp_size; + start_rb += (ibwp_start - abwp_start); + printf("msg3: ibwp_size %d, abwp_size %d, ibwp_start %d, abwp_start %d\n", + ibwp_size,abwp_size,ibwp_start,abwp_start); + } + else { + pusch_pdu->bwp_start = abwp_start; + pusch_pdu->bwp_size = abwp_size; + } + pusch_pdu->pdu_bit_map = PUSCH_PDU_BITMAP_PUSCH_DATA; pusch_pdu->rnti = n_rnti; pusch_pdu->mcs_index = Imcs; @@ -577,12 +629,14 @@ int main(int argc, char **argv) pusch_pdu->target_code_rate = code_rate; pusch_pdu->qam_mod_order = mod_order; pusch_pdu->transform_precoding = 0; - pusch_pdu->data_scrambling_id = 0; + pusch_pdu->data_scrambling_id = *scc->physCellId; pusch_pdu->nrOfLayers = 1; - pusch_pdu->ul_dmrs_symb_pos = 1; + pusch_pdu->ul_dmrs_symb_pos = (1<dmrs_config_type = 0; - pusch_pdu->ul_dmrs_scrambling_id = 0; + pusch_pdu->ul_dmrs_scrambling_id = *scc->physCellId; pusch_pdu->scid = 0; + pusch_pdu->dmrs_ports = 1; + pusch_pdu->num_dmrs_cdm_grps_no_data = 2; pusch_pdu->resource_alloc = 1; pusch_pdu->rb_start = start_rb; pusch_pdu->rb_size = nb_rb; @@ -626,62 +680,98 @@ int main(int argc, char **argv) //there are plenty of other parameters that we don't seem to be using for now. e.g. //ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.absolute_delta_PUSCH = 0; - // set FAPI parameters for UE, put them in the scheduled response and call - nr_ue_scheduled_response(&scheduled_response); - - /////////////////////////phy_procedures_nr_ue_TX/////////////////////// - /////////// - - phy_procedures_nrUE_TX(UE, &UE_proc, gNB_id, 0); - - if (n_trials==1) - LOG_M("txsig0.m","txs0", UE->common_vars.txdata[0],frame_length_complex_samples,1,1); - - /////////// - //////////////////////////////////////////////////// - tx_offset = frame_parms->get_samples_slot_timestamp(slot,frame_parms,0); - - txlev = signal_energy(&UE->common_vars.txdata[0][tx_offset + 5*frame_parms->ofdm_symbol_size + 4*frame_parms->nb_prefix_samples + frame_parms->nb_prefix_samples0], - frame_parms->ofdm_symbol_size + frame_parms->nb_prefix_samples); - - txlev_float = (double)txlev; // output of signal_energy is fixed point representation - - n_errors = 0; - n_false_positive = 0; - - //AWGN - sigma_dB = 10*log10(txlev_float)-SNR; - sigma = pow(10,sigma_dB/10); + if (input_fd != NULL) { + // set FAPI parameters for UE, put them in the scheduled response and call + nr_ue_scheduled_response(&scheduled_response); + + /////////////////////////phy_procedures_nr_ue_TX/////////////////////// + /////////// + + phy_procedures_nrUE_TX(UE, &UE_proc, gNB_id, 0); + + if (n_trials==1) + LOG_M("txsig0.m","txs0", UE->common_vars.txdata[0],frame_length_complex_samples,1,1); + + /////////// + //////////////////////////////////////////////////// + tx_offset = frame_parms->get_samples_slot_timestamp(slot,frame_parms,0); + + txlev = signal_energy(&UE->common_vars.txdata[0][tx_offset + 5*frame_parms->ofdm_symbol_size + 4*frame_parms->nb_prefix_samples + frame_parms->nb_prefix_samples0], + frame_parms->ofdm_symbol_size + frame_parms->nb_prefix_samples); + + txlev_float = (double)txlev; // output of signal_energy is fixed point representation + + n_errors = 0; + n_false_positive = 0; + + //AWGN + sigma_dB = 10*log10(txlev_float)-SNR; + sigma = pow(10,sigma_dB/10); + } + else n_trials = 1; for (trial = 0; trial < n_trials; trial++) { + + errors_scrambling = 0; + errors_decoding = 0; + + //---------------------------------------------------------- + //------------------------ add noise ----------------------- + //---------------------------------------------------------- + if (input_fd == NULL ) { + for (i=0; inb_antennas_rx; ap++) { + ((short*) gNB->common_vars.rxdata[ap])[(2*i) + (delay*2)] = (((int16_t *)UE->common_vars.txdata[ap])[(i<<1)]) + (int16_t)(sqrt(sigma/2)*gaussdouble(0.0,1.0)); // convert to fixed point + ((short*) gNB->common_vars.rxdata[ap])[2*i+1 + (delay*2)] = (((int16_t *)UE->common_vars.txdata[ap])[(i<<1)+1]) + (int16_t)(sqrt(sigma/2)*gaussdouble(0.0,1.0)); + } + } + } + else { + AssertFatal(frame_parms->nb_antennas_rx == 1, "nb_ant != 1\n"); + // 800 samples is N_TA_OFFSET for FR1 @ 30.72 Ms/s, + AssertFatal(frame_parms->subcarrier_spacing==30000,"only 30 kHz for file input for now (%d)\n",frame_parms->subcarrier_spacing); + double factor = 1; + if (openair0_cfg[0].threequarter_fs== 1) factor =.75; + int ta_offset=1600; + if (N_RB_DL <217) ta_offset=800; + else if (N_RB_DL < 106) ta_offset = 400; - errors_scrambling = 0; - errors_decoding = 0; - - //---------------------------------------------------------- - //------------------------ add noise ----------------------- - //---------------------------------------------------------- - for (i=0; inb_antennas_rx; ap++) { - ((short*) gNB->common_vars.rxdata[ap])[(2*i) + (delay*2)] = (((int16_t *)UE->common_vars.txdata[ap])[(i<<1)]) + (int16_t)(sqrt(sigma/2)*gaussdouble(0.0,1.0)); // convert to fixed point - ((short*) gNB->common_vars.rxdata[ap])[2*i+1 + (delay*2)] = (((int16_t *)UE->common_vars.txdata[ap])[(i<<1)+1]) + (int16_t)(sqrt(sigma/2)*gaussdouble(0.0,1.0)); - } - } - //////////////////////////////////////////////////////////// - - //---------------------------------------------------------- - //------------------- gNB phy procedures ------------------- - //---------------------------------------------------------- - gNB->UL_INFO.rx_ind.number_of_pdus = 0; - gNB->UL_INFO.crc_ind.number_crcs = 0; + int slot_offset = frame_parms->get_samples_slot_timestamp(slot,frame_parms,0);// - (int)(800*factor); + int slot_length = slot_offset - frame_parms->get_samples_slot_timestamp(slot-1,frame_parms,0); + fread((void*)&gNB->common_vars.rxdata[0][slot_offset], + sizeof(int16_t), + slot_length<<1, + input_fd); + for (int i=0;i<16;i+=2) printf("slot_offset %d : %d,%d\n", + slot_offset, + ((int16_t*)&gNB->common_vars.rxdata[0][slot_offset])[i], + ((int16_t*)&gNB->common_vars.rxdata[0][slot_offset])[1+i]); + fclose(input_fd); + } + //////////////////////////////////////////////////////////// + + //---------------------------------------------------------- + //------------------- gNB phy procedures ------------------- + //---------------------------------------------------------- + gNB->UL_INFO.rx_ind.number_of_pdus = 0; + gNB->UL_INFO.crc_ind.number_crcs = 0; start_meas(&gNB->phy_proc_rx); phy_procedures_gNB_common_RX(gNB, frame, slot); - if (n_trials==1) - LOG_M("rxsigF0.m","rxsF0",gNB->common_vars.rxdataF[0],frame_length_complex_samples_no_prefix,1,1); + if (n_trials==1) { + LOG_M("rxsigF0.m","rxsF0",gNB->common_vars.rxdataF[0]+start_symbol*frame_parms->ofdm_symbol_size,nb_symb_sch*frame_parms->ofdm_symbol_size,1,1); + } phy_procedures_gNB_uespec_RX(gNB, frame, slot); + if (n_trials == 1) { + LOG_M("rxsigF0_ext.m","rxsF0_ext", + &gNB->pusch_vars[0]->rxdataF_ext[0][(start_symbol+1)*NR_NB_SC_PER_RB * pusch_pdu->rb_size],(nb_symb_sch-1)*NR_NB_SC_PER_RB * pusch_pdu->rb_size,1,1); + LOG_M("chestF0.m","chF0", + &gNB->pusch_vars[0]->ul_ch_estimates[0][start_symbol*frame_parms->ofdm_symbol_size],frame_parms->ofdm_symbol_size,1,1); + LOG_M("chestF0_ext.m","chF0_ext", + &gNB->pusch_vars[0]->ul_ch_estimates_ext[0][(start_symbol+1)*NR_NB_SC_PER_RB * pusch_pdu->rb_size],(nb_symb_sch-1)*NR_NB_SC_PER_RB * pusch_pdu->rb_size,1,1); + } start_meas(&gNB->phy_proc_rx); //////////////////////////////////////////////////////////// From 76551239972ccb44de9aed53ef3f563d5464aee3 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Mon, 4 May 2020 09:29:36 +0200 Subject: [PATCH 203/553] included throughput print --- openair1/SIMULATION/NR_PHY/dlsim.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/openair1/SIMULATION/NR_PHY/dlsim.c b/openair1/SIMULATION/NR_PHY/dlsim.c index 00552fc953..c7ac2ec0cf 100644 --- a/openair1/SIMULATION/NR_PHY/dlsim.c +++ b/openair1/SIMULATION/NR_PHY/dlsim.c @@ -140,8 +140,10 @@ int main(int argc, char **argv) double sigma2, sigma2_dB=10, SNR, snr0=-2.0, snr1=2.0; uint8_t snr1set=0; float roundStats[50]; + float effRate; float psnr; uint8_t snrRun; + uint32_t TBS; int **txdata; double **s_re,**s_im,**r_re,**r_im; //double iqim = 0.0; @@ -703,6 +705,7 @@ int main(int argc, char **argv) reset_meas(&gNB->toutput); n_errors = 0; + effRate = 0; //n_errors2 = 0; //n_alamouti = 0; errors_scrambling=0; @@ -848,7 +851,7 @@ int main(int argc, char **argv) NR_UE_PDSCH **pdsch_vars = UE->pdsch_vars[UE->current_thread_id[UE_proc.nr_tti_rx]]; int16_t *UE_llr = pdsch_vars[0]->llr[0]; - uint32_t TBS = rel15->TBSize[0]; + TBS = rel15->TBSize[0]; uint16_t length_dmrs = 1; uint16_t nb_rb = rel15->rbSize; uint8_t nb_re_dmrs = rel15->dmrsConfigType == NFAPI_NR_DMRS_TYPE1 ? 6 : 4; @@ -896,15 +899,17 @@ int main(int argc, char **argv) printf("errors_bit = %u (trial %d)\n", errors_bit, trial); } roundStats[snrRun]+=((float)round); + if (UE_harq_process->harq_ack.ack==1) effRate += ((float)TBS)/round; } // noise trials roundStats[snrRun]/=((float)n_trials); + effRate /= n_trials; printf("*****************************************\n"); printf("SNR %f, (false positive %f)\n", SNR, (float) n_errors / (float) n_trials); printf("*****************************************\n"); printf("\n"); - printf("SNR %f : n_errors (negative CRC) = %d/%d, Avg round %.2f, Channel BER %e\n", SNR, n_errors, n_trials,roundStats[snrRun],(double)errors_scrambling/available_bits/n_trials); + printf("SNR %f : n_errors (negative CRC) = %d/%d, Avg round %.2f, Channel BER %e, Eff Rate %.4f bits/slot, Eff Throughput %.2f\%, TBS %d bits/slot\n", SNR, n_errors, n_trials,roundStats[snrRun],(double)errors_scrambling/available_bits/n_trials,effRate,effRate/TBS*100,TBS); printf("\n"); if (n_trials == 1) { @@ -916,7 +921,8 @@ int main(int argc, char **argv) write_output("rxF_comp.m","rxFc",&UE->pdsch_vars[0][0]->rxdataF_comp0[0][0],N_RB_DL*12*14,1,1); } - if ((float)n_errors/(float)n_trials <= target_error_rate) { + //if ((float)n_errors/(float)n_trials <= target_error_rate) { + if (effRate >= (0.7*TBS)) { printf("PDSCH test OK\n"); break; } @@ -975,14 +981,14 @@ int main(int argc, char **argv) snrRun++; } // NSR - if (n_trials>1) { + /*if (n_trials>1) { printf("HARQ stats:\nSNR\tRounds\n"); psnr = snr0; for (uint8_t i=0; i Date: Mon, 4 May 2020 09:49:18 +0200 Subject: [PATCH 204/553] reverted handling of transform_precoding variable in NR FAPI. Added correct handling of this in ulsim.c --- openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c | 2 +- openair1/SIMULATION/NR_PHY/ulsim.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c index d3ceae74e2..a141970840 100644 --- a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c +++ b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c @@ -116,7 +116,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, //------------------generate DMRS------------------// - if (pusch_pdu->transform_precoding==0) // if transform precoding is disabled + if (pusch_pdu->transform_precoding==1) // if transform precoding is disabled nr_pusch_dmrs_rx(gNB, Ns, gNB->nr_gold_pusch_dmrs[pusch_pdu->scid][Ns][symbol], &pilot[0], 1000, 0, nb_rb_pusch, pusch_pdu->rb_start*NR_NB_SC_PER_RB, pusch_pdu->dmrs_config_type); else nr_pusch_dmrs_rx(gNB, Ns, gNB->nr_gold_pusch_dmrs[pusch_pdu->scid][Ns][symbol], &pilot[0], 1000, 0, nb_rb_pusch, 0, pusch_pdu->dmrs_config_type); diff --git a/openair1/SIMULATION/NR_PHY/ulsim.c b/openair1/SIMULATION/NR_PHY/ulsim.c index 4c43eb87ff..d184ba130b 100644 --- a/openair1/SIMULATION/NR_PHY/ulsim.c +++ b/openair1/SIMULATION/NR_PHY/ulsim.c @@ -628,7 +628,7 @@ int main(int argc, char **argv) pusch_pdu->mcs_table = 0; pusch_pdu->target_code_rate = code_rate; pusch_pdu->qam_mod_order = mod_order; - pusch_pdu->transform_precoding = 0; + pusch_pdu->transform_precoding = 1; pusch_pdu->data_scrambling_id = *scc->physCellId; pusch_pdu->nrOfLayers = 1; pusch_pdu->ul_dmrs_symb_pos = (1< Date: Mon, 4 May 2020 15:42:15 +0200 Subject: [PATCH 205/553] updated CI test list with harq test --- cmake_targets/autotests/test_case_list.xml | 12 +++++++++--- openair1/SIMULATION/NR_PHY/dlsim.c | 9 ++++++++- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/cmake_targets/autotests/test_case_list.xml b/cmake_targets/autotests/test_case_list.xml index 7908772bb6..245039fe0f 100644 --- a/cmake_targets/autotests/test_case_list.xml +++ b/cmake_targets/autotests/test_case_list.xml @@ -1087,8 +1087,11 @@ (Test6: 217 PRB 100 PDSCH-PRBs), (Test7: 217 PRB 80 PDSCH-Offset), (Test8: 217 PRB 100 PDSCH-PRBs 110 PDSCH-Offset), - (Test9: 106 PRBs 50 PDSCH-PRBs MCS Index 27) - (Test10: 106 PRBs 50 PDSCH-PRBs MCS Index 16) + (Test9: 106 PRBs 50 PDSCH-PRBs MCS Index 27), + (Test10: 106 PRBs 50 PDSCH-PRBs MCS Index 16), + (Test11: HARQ test 25% TP (4 rounds), + (Test12: HARQ test 33% TP (3 rounds), + (Test13: HARQ test 50% TP (2 rounds) $OPENAIR_DIR/cmake_targets/build_oai --phy_simulators -c @@ -1105,8 +1108,11 @@ -n100 -R217 -a110 -s5 -b100 -n100 -e27 -s30 -n100 -e16 -s10 + -n100 -s1 -t25 + -n100 -s1 -t33 + -n100 -s1 -t50 - nr_dlsim.test1 nr_dlsim.test2 nr_dlsim.test3 nr_dlsim.test4 nr_dlsim.test5 nr_dlsim.test6 nr_dlsim.test7 nr_dlsim.test8 nr_dlsim.test9 nr_dlsim.test10 + nr_dlsim.test1 nr_dlsim.test2 nr_dlsim.test3 nr_dlsim.test4 nr_dlsim.test5 nr_dlsim.test6 nr_dlsim.test7 nr_dlsim.test8 nr_dlsim.test9 nr_dlsim.test10 nr_dlsim.test11 nr_dlsim.test12 nr_dlsim.test13 PDSCH test OK segmentation fault|assertion|exiting|fatal 3 diff --git a/openair1/SIMULATION/NR_PHY/dlsim.c b/openair1/SIMULATION/NR_PHY/dlsim.c index c7ac2ec0cf..a102da5744 100644 --- a/openair1/SIMULATION/NR_PHY/dlsim.c +++ b/openair1/SIMULATION/NR_PHY/dlsim.c @@ -142,6 +142,7 @@ int main(int argc, char **argv) float roundStats[50]; float effRate; float psnr; + float eff_tp_check = 0.7; uint8_t snrRun; uint32_t TBS; int **txdata; @@ -391,6 +392,10 @@ int main(int argc, char **argv) mu = atoi(optarg); break; + case 't': + eff_tp_check = (float)atoi(optarg)/100; + break; + default: case 'h': printf("%s -h(elp) -p(extended_prefix) -N cell_id -f output_filename -F input_filename -g channel_model -n n_frames -t Delayspread -s snr0 -S snr1 -x transmission_mode -y TXant -z RXant -i Intefrence0 -j Interference1 -A interpolation_file -C(alibration offset dB) -N CellId\n", @@ -420,6 +425,7 @@ int main(int argc, char **argv) printf("-c Start symbol for PDSCH (fixed for now)\n"); printf("-j Number of symbols for PDSCH (fixed for now)\n"); printf("-e MSC index\n"); + printf("-t Acceptable effective throughput (in percentage)\n"); exit (-1); break; } @@ -919,10 +925,11 @@ int main(int argc, char **argv) LOG_M("rxsig1.m","rxs1", UE->common_vars.rxdata[1], frame_length_complex_samples, 1, 1); LOG_M("chestF0.m","chF0",UE->pdsch_vars[0][0]->dl_ch_estimates_ext,N_RB_DL*12*14,1,1); write_output("rxF_comp.m","rxFc",&UE->pdsch_vars[0][0]->rxdataF_comp0[0][0],N_RB_DL*12*14,1,1); + break; } //if ((float)n_errors/(float)n_trials <= target_error_rate) { - if (effRate >= (0.7*TBS)) { + if (effRate >= (eff_tp_check*TBS)) { printf("PDSCH test OK\n"); break; } From bdc7943b8ff797f18a683fda21d88d5a33bd5e2b Mon Sep 17 00:00:00 2001 From: "s.rampalli" Date: Tue, 5 May 2020 09:09:27 +0530 Subject: [PATCH 206/553] fixed encoding failed issue --- openair2/RRC/LTE/rrc_eNB.c | 7 ++++--- openair2/X2AP/x2ap_eNB_handler.c | 4 ++-- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index 41565e6694..19c3abb726 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -4541,12 +4541,12 @@ int add_CG_ConfigInfo( AssertFatal(rb_config->drb_ToAddModList != NULL,"failed to allocated memory for drbtoaddmodlist"); rb_config->drb_ToAddModList->list.count = ue_context_pP->ue_context.DRB_configList->list.count; rb_config->drb_ToAddModList->list.array - = calloc(ue_context_pP->ue_context.DRB_configList->list.count, sizeof(struct LTE_DRB_ToAddMod)); + = calloc(ue_context_pP->ue_context.DRB_configList->list.count, sizeof(struct NR_DRB_ToAddMod)); AssertFatal( rb_config->drb_ToAddModList->list.array != NULL, "falied to allocate memory for list.array"); for(index = 0;index < ue_context_pP->ue_context.DRB_configList->list.count;index++) { rb_config->drb_ToAddModList->list.array[index] - = calloc(1,sizeof(struct LTE_DRB_ToAddMod)); + = calloc(1,sizeof(struct NR_DRB_ToAddMod)); AssertFatal(rb_config->drb_ToAddModList->list.array[index] != NULL, "failed to allocate memory for drb_toaddmod"); rb_config->drb_ToAddModList->list.array[index]->drb_Identity @@ -4584,7 +4584,7 @@ int add_CG_ConfigInfo( cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->size = ue_context_pP->ue_context.UE_Capability_size; cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf - = calloc(1,sizeof(ue_context_pP->ue_context.UE_Capability_size)); + = calloc(1,ue_context_pP->ue_context.UE_Capability_size); AssertFatal( cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> ue_CapabilityInfo->buf != NULL, "failed to allocate memory for buf"); memcpy(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf, @@ -4601,6 +4601,7 @@ int add_CG_ConfigInfo( mcg_RB_Config->buf != NULL,"failed to allocate memory for buf"); memcpy(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf, rb_config,sizeof(struct NR_RadioBearerConfig)); + xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo,(void*)cg_configinfo); enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CG_ConfigInfo,NULL,(void*)cg_configinfo, enc_buf,ASN_MAX_ENCODE_SIZE); AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %lu)!\n", diff --git a/openair2/X2AP/x2ap_eNB_handler.c b/openair2/X2AP/x2ap_eNB_handler.c index 87ef5bf69f..83bcbc4f15 100644 --- a/openair2/X2AP/x2ap_eNB_handler.c +++ b/openair2/X2AP/x2ap_eNB_handler.c @@ -1772,8 +1772,8 @@ LOG_I(RRC,"x2u tunnel: index %d target sgw ip %d.%d.%d.%d length %d gtp teid %u\ if (ie->value.choice.MeNBtoSgNBContainer.size > 8192 ) { printf("%s:%d: fatal: buffer too big\n", __FILE__, __LINE__); abort(); } - memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer, ie->value.choice.MeNBtoSgNBContainer.buf, ie->value.choice.MeNBtoSgNBContainer.size); - X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer_size = ie->value.choice.MeNBtoSgNBContainer.size; + // memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer, ie->value.choice.MeNBtoSgNBContainer.buf, ie->value.choice.MeNBtoSgNBContainer.size); + // X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer_size = ie->value.choice.MeNBtoSgNBContainer.size; itti_send_msg_to_task(TASK_RRC_GNB, instance_p->instance, msg); From 85cfa10961e0837d0a8d6806b077ff257f582b6a Mon Sep 17 00:00:00 2001 From: "s.rampalli" Date: Tue, 5 May 2020 13:55:49 +0530 Subject: [PATCH 207/553] rrc runtime errors fixed --- openair2/RRC/LTE/rrc_eNB.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index 19c3abb726..62e063ff2f 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -97,7 +97,7 @@ #include "SIMULATION/TOOLS/sim.h" // for taus #define ASN_MAX_ENCODE_SIZE 1000 -static int add_CG_ConfigInfo(char **enc_buf,rrc_eNB_ue_context_t *const ue_context_pP,int * enc_size); +static int add_CG_ConfigInfo(char *enc_buf,rrc_eNB_ue_context_t *const ue_context_pP,int * enc_size); static int is_en_dc_supported(LTE_UE_EUTRA_Capability_t *c); static void free_rb_config(struct NR_RadioBearerConfig *rb_config); static void free_cg_configinfo(struct NR_CG_ConfigInfo *cg_configinfo); @@ -4371,7 +4371,8 @@ rrc_eNB_process_MeasurementReport( if(is_en_dc_supported(ue_context_pP->ue_context.UE_Capability)) { /** to add gNB as Secondary node CG-ConfigInfo to be added as per 36.423 r15 **/ - if(add_CG_ConfigInfo(&enc_buf,ue_context_pP,&enc_size) == RRC_OK) + enc_buf = calloc(1,1000); + if(add_CG_ConfigInfo(enc_buf,ue_context_pP,&enc_size) == RRC_OK) LOG_I(RRC,"CG-ConfigInfo encoded successfully\n"); msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ); X2AP_ENDC_SGNB_ADDITION_REQ(msg).rnti = ctxt_pP->rnti; @@ -4523,9 +4524,9 @@ rrc_eNB_process_MeasurementReport( * this api is to fill and encode CG-ConfigInfo */ int add_CG_ConfigInfo( - char **enc_buf, + char *enc_buf, rrc_eNB_ue_context_t *const ue_context_pP, - int * enc_size + int *enc_size ) { struct NR_CG_ConfigInfo *cg_configinfo = NULL; struct NR_RadioBearerConfig *rb_config = NULL; From c52c9b7ba431c4305942adeba4cd13cdc0ab4589 Mon Sep 17 00:00:00 2001 From: "s.rampalli" Date: Tue, 5 May 2020 14:03:05 +0530 Subject: [PATCH 208/553] fixed rrc issues --- openair2/RRC/LTE/rrc_eNB.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index 62e063ff2f..f8f31c0761 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -4602,7 +4602,8 @@ int add_CG_ConfigInfo( mcg_RB_Config->buf != NULL,"failed to allocate memory for buf"); memcpy(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf, rb_config,sizeof(struct NR_RadioBearerConfig)); - xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo,(void*)cg_configinfo); + // xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo,(void*)cg_configinfo); + // this xer_fprint can be enabled for additional debugging messages enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CG_ConfigInfo,NULL,(void*)cg_configinfo, enc_buf,ASN_MAX_ENCODE_SIZE); AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %lu)!\n", From 509fb16705d6d95acda61b80168ec9e6c049c4e2 Mon Sep 17 00:00:00 2001 From: "s.rampalli" Date: Tue, 5 May 2020 17:22:17 +0530 Subject: [PATCH 209/553] rrc changes --- openair2/RRC/LTE/rrc_eNB.c | 372 +++++++++++++++++++------------------ 1 file changed, 187 insertions(+), 185 deletions(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index f8f31c0761..fb2a503d59 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -97,7 +97,7 @@ #include "SIMULATION/TOOLS/sim.h" // for taus #define ASN_MAX_ENCODE_SIZE 1000 -static int add_CG_ConfigInfo(char *enc_buf,rrc_eNB_ue_context_t *const ue_context_pP,int * enc_size); +static int encode_CG_ConfigInfo(char *buffer,int buffer_size,rrc_eNB_ue_context_t *const ue_context_pP,int *enc_size); static int is_en_dc_supported(LTE_UE_EUTRA_Capability_t *c); static void free_rb_config(struct NR_RadioBearerConfig *rb_config); static void free_cg_configinfo(struct NR_CG_ConfigInfo *cg_configinfo); @@ -4290,6 +4290,190 @@ rrc_eNB_generate_RRCConnectionReconfiguration_SCell( } + +//----------------------------------------------------------------------------- +/** + * @fn :encode_CG_ConfigInfo + * @param :enc_buf to store the encoded bits + * @param :ue_context_pP ue context used to fill CG-ConfigInfo + * @param :enc_size to store thre size of encoded size + * this api is to fill and encode CG-ConfigInfo + */ +static int encode_CG_ConfigInfo( + char *buffer, + int buffer_size, + rrc_eNB_ue_context_t *const ue_context_pP, + int *enc_size +) { + struct NR_CG_ConfigInfo *cg_configinfo = NULL; + struct NR_RadioBearerConfig *rb_config = NULL; + asn_enc_rval_t enc_rval; + int RRC_OK = 1; + int index = 0; + + rb_config = calloc(1,sizeof( struct NR_RadioBearerConfig)); + AssertFatal(rb_config != NULL,"failed to allocate memory for rb_config"); + + if(ue_context_pP->ue_context.DRB_configList->list.count != 0) { + rb_config->drb_ToAddModList = calloc(1,sizeof(struct NR_DRB_ToAddModList )); + AssertFatal(rb_config->drb_ToAddModList != NULL,"failed to allocated memory for drbtoaddmodlist"); + rb_config->drb_ToAddModList->list.count = ue_context_pP->ue_context.DRB_configList->list.count; + rb_config->drb_ToAddModList->list.array + = calloc(ue_context_pP->ue_context.DRB_configList->list.count, sizeof(struct NR_DRB_ToAddMod)); + AssertFatal( rb_config->drb_ToAddModList->list.array != NULL, + "falied to allocate memory for list.array"); + for(index = 0;index < ue_context_pP->ue_context.DRB_configList->list.count;index++) { + rb_config->drb_ToAddModList->list.array[index] + = calloc(1,sizeof(struct NR_DRB_ToAddMod)); + AssertFatal(rb_config->drb_ToAddModList->list.array[index] != NULL, + "failed to allocate memory for drb_toaddmod"); + rb_config->drb_ToAddModList->list.array[index]->drb_Identity + =ue_context_pP->ue_context.DRB_configList->list.array[index]->drb_Identity; + if(ue_context_pP->ue_context.DRB_configList->list.array[index]->eps_BearerIdentity) { + rb_config->drb_ToAddModList->list.array[index]->cnAssociation + =calloc(1,sizeof(struct NR_DRB_ToAddMod__cnAssociation)); + AssertFatal(rb_config->drb_ToAddModList->list.array[index]->cnAssociation != NULL, + "failed to allocate memory cnAssociation"); + rb_config->drb_ToAddModList->list.array[index]->cnAssociation->present + =NR_DRB_ToAddMod__cnAssociation_PR_eps_BearerIdentity; + rb_config->drb_ToAddModList->list.array[index]->cnAssociation->choice.eps_BearerIdentity + =*(ue_context_pP->ue_context.DRB_configList->list.array[index]->eps_BearerIdentity); + } + } + } + + cg_configinfo = calloc(1,sizeof(struct NR_CG_ConfigInfo)); + AssertFatal(cg_configinfo != NULL,"failed to allocate memory for cg_configinfo"); + cg_configinfo->criticalExtensions.present = NR_CG_ConfigInfo__criticalExtensions_PR_c1; + cg_configinfo->criticalExtensions.choice.c1 + = calloc(1, sizeof(struct NR_CG_ConfigInfo__criticalExtensions__c1)); + AssertFatal(cg_configinfo->criticalExtensions.choice.c1 != NULL, + "failed to allocate memory for cg_configinfo->criticalExtensions.choice.c1"); + cg_configinfo->criticalExtensions.choice.c1->present + = NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo; + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo + = calloc(1,sizeof(struct NR_CG_ConfigInfo_IEs)); + AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo != NULL, + "failed to allocate memory for cg_configinfo_IEs"); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo + = calloc(1,sizeof( OCTET_STRING_t)); + AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> + ue_CapabilityInfo != NULL, "failed to allocate memory for ue_capabilityinfo"); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->size + = ue_context_pP->ue_context.UE_Capability_size; + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf + = calloc(1,ue_context_pP->ue_context.UE_Capability_size); + AssertFatal( cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> + ue_CapabilityInfo->buf != NULL, "failed to allocate memory for buf"); + memcpy(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf, + ue_context_pP->ue_context.UE_Capability,ue_context_pP->ue_context.UE_Capability_size); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config + = calloc(1,sizeof(OCTET_STRING_t)); + AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> + mcg_RB_Config != NULL, "failed to allocate memory for mcg_rb_config"); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->size + = sizeof( struct NR_RadioBearerConfig); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf + = calloc(1,sizeof(struct NR_RadioBearerConfig)); + AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> + mcg_RB_Config->buf != NULL,"failed to allocate memory for buf"); + memcpy(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf, + rb_config,sizeof(struct NR_RadioBearerConfig)); + // this xer_fprint can be enabled for additional debugging messages + // xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo,(void*)cg_configinfo); + enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CG_ConfigInfo,NULL,(void*)cg_configinfo, + buffer,buffer_size); + AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %lu)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + *enc_size = (enc_rval.encoded+7)/8; + free_rb_config(rb_config); + free_cg_configinfo(cg_configinfo); + return RRC_OK; + } +//----------------------------------------------------------------------------- + + + +/** + * @fn :api to free the all the dynamically allocated memory + * @param :cg_configinfo contains cellgroup configuration + */ +static void free_cg_configinfo( + struct NR_CG_ConfigInfo *cg_configinfo +) { + if(cg_configinfo){ + if(cg_configinfo->criticalExtensions.choice.c1){ + if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo){ + if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo){ + if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf){ + if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config){ + if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf){ + free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf =NULL; + free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config =NULL; + free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf = NULL; + free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo =NULL; + free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo =NULL; + free(cg_configinfo->criticalExtensions.choice.c1); + cg_configinfo->criticalExtensions.choice.c1 =NULL; + free(cg_configinfo); + cg_configinfo =NULL; + } + } + } + } + } + } + } + return; +} +//----------------------------------------------------------------------------- + + + +//----------------------------------------------------------------------------- +/** + * @fn :api to free the all the dynamically allocated memory + * @param :rb_config contains radiobearer configuration + */ +static void free_rb_config( + struct NR_RadioBearerConfig *rb_config +) { + int index = 0; + + if(rb_config) { + if(rb_config->drb_ToAddModList) { + if(rb_config->drb_ToAddModList->list.array) { + for(index = 0; index < rb_config->drb_ToAddModList->list.count; index++) { + if(rb_config->drb_ToAddModList->list.array[index]->cnAssociation) { + free(rb_config->drb_ToAddModList->list.array[index]->cnAssociation); + rb_config->drb_ToAddModList->list.array[index]->cnAssociation = NULL; + } + if(rb_config->drb_ToAddModList->list.array[index]) { + free(rb_config->drb_ToAddModList->list.array[index]); + rb_config->drb_ToAddModList->list.array[index] = NULL; + } + } + free(rb_config->drb_ToAddModList->list.array); + rb_config->drb_ToAddModList->list.array = NULL; + free(rb_config->drb_ToAddModList); + rb_config->drb_ToAddModList = NULL; + free(rb_config); + rb_config = NULL; + } + } + } + return; +} +//------------------------------------------------------------------------------ + + + + //----------------------------------------------------------------------------- void rrc_eNB_process_MeasurementReport( @@ -4305,7 +4489,7 @@ rrc_eNB_process_MeasurementReport( long ncell_max = -150; uint32_t earfcn_dl; uint8_t KeNB_star[32] = { 0 }; - char *enc_buf = NULL; + char enc_buf[ASN_MAX_ENCODE_SIZE] = {0}; int enc_size = 0; T(T_ENB_RRC_MEASUREMENT_REPORT, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame), T_INT(ctxt_pP->subframe), T_INT(ctxt_pP->rnti)); @@ -4371,8 +4555,7 @@ rrc_eNB_process_MeasurementReport( if(is_en_dc_supported(ue_context_pP->ue_context.UE_Capability)) { /** to add gNB as Secondary node CG-ConfigInfo to be added as per 36.423 r15 **/ - enc_buf = calloc(1,1000); - if(add_CG_ConfigInfo(enc_buf,ue_context_pP,&enc_size) == RRC_OK) + if(encode_CG_ConfigInfo(enc_buf,sizeof(enc_buf),ue_context_pP,&enc_size) == RRC_OK) LOG_I(RRC,"CG-ConfigInfo encoded successfully\n"); msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ); X2AP_ENDC_SGNB_ADDITION_REQ(msg).rnti = ctxt_pP->rnti; @@ -4515,187 +4698,6 @@ rrc_eNB_process_MeasurementReport( } -//----------------------------------------------------------------------------- -/** - * @fn :add_CG_ConfigInfo - * @param :enc_buf to store the encoded bits - * @param :ue_context_pP ue context used to fill CG-ConfigInfo - * @param :enc_size to store thre size of encoded size - * this api is to fill and encode CG-ConfigInfo - */ -int add_CG_ConfigInfo( - char *enc_buf, - rrc_eNB_ue_context_t *const ue_context_pP, - int *enc_size -) { - struct NR_CG_ConfigInfo *cg_configinfo = NULL; - struct NR_RadioBearerConfig *rb_config = NULL; - asn_enc_rval_t enc_rval; - int RRC_OK = 1; - int index = 0; - - rb_config = calloc(1,sizeof( struct NR_RadioBearerConfig)); - AssertFatal(rb_config != NULL,"failed to allocate memory for rb_config"); - - if(ue_context_pP->ue_context.DRB_configList->list.count != 0) { - rb_config->drb_ToAddModList = calloc(1,sizeof(struct NR_DRB_ToAddModList )); - AssertFatal(rb_config->drb_ToAddModList != NULL,"failed to allocated memory for drbtoaddmodlist"); - rb_config->drb_ToAddModList->list.count = ue_context_pP->ue_context.DRB_configList->list.count; - rb_config->drb_ToAddModList->list.array - = calloc(ue_context_pP->ue_context.DRB_configList->list.count, sizeof(struct NR_DRB_ToAddMod)); - AssertFatal( rb_config->drb_ToAddModList->list.array != NULL, - "falied to allocate memory for list.array"); - for(index = 0;index < ue_context_pP->ue_context.DRB_configList->list.count;index++) { - rb_config->drb_ToAddModList->list.array[index] - = calloc(1,sizeof(struct NR_DRB_ToAddMod)); - AssertFatal(rb_config->drb_ToAddModList->list.array[index] != NULL, - "failed to allocate memory for drb_toaddmod"); - rb_config->drb_ToAddModList->list.array[index]->drb_Identity - =ue_context_pP->ue_context.DRB_configList->list.array[index]->drb_Identity; - if(ue_context_pP->ue_context.DRB_configList->list.array[index]->eps_BearerIdentity) { - rb_config->drb_ToAddModList->list.array[index]->cnAssociation - =calloc(1,sizeof(struct NR_DRB_ToAddMod__cnAssociation)); - AssertFatal(rb_config->drb_ToAddModList->list.array[index]->cnAssociation != NULL, - "failed to allocate memory cnAssociation"); - rb_config->drb_ToAddModList->list.array[index]->cnAssociation->present - =NR_DRB_ToAddMod__cnAssociation_PR_eps_BearerIdentity; - rb_config->drb_ToAddModList->list.array[index]->cnAssociation->choice.eps_BearerIdentity - =*(ue_context_pP->ue_context.DRB_configList->list.array[index]->eps_BearerIdentity); - } - } - } - - cg_configinfo = calloc(1,sizeof(struct NR_CG_ConfigInfo)); - AssertFatal(cg_configinfo != NULL,"failed to allocate memory for cg_configinfo"); - cg_configinfo->criticalExtensions.present = NR_CG_ConfigInfo__criticalExtensions_PR_c1; - cg_configinfo->criticalExtensions.choice.c1 - = calloc(1, sizeof(struct NR_CG_ConfigInfo__criticalExtensions__c1)); - AssertFatal(cg_configinfo->criticalExtensions.choice.c1 != NULL, - "failed to allocate memory for cg_configinfo->criticalExtensions.choice.c1"); - cg_configinfo->criticalExtensions.choice.c1->present - = NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo; - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo - = calloc(1,sizeof(struct NR_CG_ConfigInfo_IEs)); - AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo != NULL, - "failed to allocate memory for cg_configinfo_IEs"); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo - = calloc(1,sizeof( OCTET_STRING_t)); - AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> - ue_CapabilityInfo != NULL, "failed to allocate memory for ue_capabilityinfo"); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->size - = ue_context_pP->ue_context.UE_Capability_size; - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf - = calloc(1,ue_context_pP->ue_context.UE_Capability_size); - AssertFatal( cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> - ue_CapabilityInfo->buf != NULL, "failed to allocate memory for buf"); - memcpy(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf, - ue_context_pP->ue_context.UE_Capability,ue_context_pP->ue_context.UE_Capability_size); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config - = calloc(1,sizeof(OCTET_STRING_t)); - AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> - mcg_RB_Config != NULL, "failed to allocate memory for mcg_rb_config"); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->size - = sizeof( struct NR_RadioBearerConfig); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf - = calloc(1,sizeof(struct NR_RadioBearerConfig)); - AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> - mcg_RB_Config->buf != NULL,"failed to allocate memory for buf"); - memcpy(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf, - rb_config,sizeof(struct NR_RadioBearerConfig)); - // xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo,(void*)cg_configinfo); - // this xer_fprint can be enabled for additional debugging messages - enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CG_ConfigInfo,NULL,(void*)cg_configinfo, - enc_buf,ASN_MAX_ENCODE_SIZE); - AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %lu)!\n", - enc_rval.failed_type->name, enc_rval.encoded); - *enc_size = (enc_rval.encoded+7)/8; - free_rb_config(rb_config); - free_cg_configinfo(cg_configinfo); - return RRC_OK; - } -//----------------------------------------------------------------------------- - - - -/** - * @fn :api to free the all the dynamically allocated memory - * @param :cg_configinfo contains cellgroup configuration - */ -void free_cg_configinfo( - struct NR_CG_ConfigInfo *cg_configinfo -) { - if(cg_configinfo){ - if(cg_configinfo->criticalExtensions.choice.c1){ - if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo){ - if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo){ - if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf){ - if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config){ - if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf){ - free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf =NULL; - free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config =NULL; - free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf = NULL; - free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo =NULL; - free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo =NULL; - free(cg_configinfo->criticalExtensions.choice.c1); - cg_configinfo->criticalExtensions.choice.c1 =NULL; - free(cg_configinfo); - cg_configinfo =NULL; - } - } - } - } - } - } - } - return; -} -//----------------------------------------------------------------------------- - - - -//----------------------------------------------------------------------------- -/** - * @fn :api to free the all the dynamically allocated memory - * @param :rb_config contains radiobearer configuration - */ -void free_rb_config( - struct NR_RadioBearerConfig *rb_config -) { - int index = 0; - - if(rb_config) { - if(rb_config->drb_ToAddModList) { - if(rb_config->drb_ToAddModList->list.array) { - for(index = 0; index < rb_config->drb_ToAddModList->list.count; index++) { - if(rb_config->drb_ToAddModList->list.array[index]->cnAssociation) { - free(rb_config->drb_ToAddModList->list.array[index]->cnAssociation); - rb_config->drb_ToAddModList->list.array[index]->cnAssociation = NULL; - } - if(rb_config->drb_ToAddModList->list.array[index]) { - free(rb_config->drb_ToAddModList->list.array[index]); - rb_config->drb_ToAddModList->list.array[index] = NULL; - } - } - free(rb_config->drb_ToAddModList->list.array); - rb_config->drb_ToAddModList->list.array = NULL; - free(rb_config->drb_ToAddModList); - rb_config->drb_ToAddModList = NULL; - free(rb_config); - rb_config = NULL; - } - } - } - return; -} -//------------------------------------------------------------------------------ - - - //----------------------------------------------------------------------------- void rrc_eNB_generate_HandoverPreparationInformation( From cfd402a03ae10a773cc6ee5048ae18addf1c4080 Mon Sep 17 00:00:00 2001 From: "s.rampalli" Date: Tue, 5 May 2020 19:53:13 +0530 Subject: [PATCH 210/553] mistake --- openair2/X2AP/x2ap_eNB_handler.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openair2/X2AP/x2ap_eNB_handler.c b/openair2/X2AP/x2ap_eNB_handler.c index 83bcbc4f15..87ef5bf69f 100644 --- a/openair2/X2AP/x2ap_eNB_handler.c +++ b/openair2/X2AP/x2ap_eNB_handler.c @@ -1772,8 +1772,8 @@ LOG_I(RRC,"x2u tunnel: index %d target sgw ip %d.%d.%d.%d length %d gtp teid %u\ if (ie->value.choice.MeNBtoSgNBContainer.size > 8192 ) { printf("%s:%d: fatal: buffer too big\n", __FILE__, __LINE__); abort(); } - // memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer, ie->value.choice.MeNBtoSgNBContainer.buf, ie->value.choice.MeNBtoSgNBContainer.size); - // X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer_size = ie->value.choice.MeNBtoSgNBContainer.size; + memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer, ie->value.choice.MeNBtoSgNBContainer.buf, ie->value.choice.MeNBtoSgNBContainer.size); + X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer_size = ie->value.choice.MeNBtoSgNBContainer.size; itti_send_msg_to_task(TASK_RRC_GNB, instance_p->instance, msg); From 37dcfb1a9db01b1e7682a88ca8c093abf95d8119 Mon Sep 17 00:00:00 2001 From: "s.rampalli" Date: Tue, 5 May 2020 21:36:07 +0530 Subject: [PATCH 211/553] fixed rrc x2ap runtime issues --- openair2/RRC/LTE/rrc_eNB.c | 1 + 1 file changed, 1 insertion(+) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index fb2a503d59..3d405cc324 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -4558,6 +4558,7 @@ rrc_eNB_process_MeasurementReport( if(encode_CG_ConfigInfo(enc_buf,sizeof(enc_buf),ue_context_pP,&enc_size) == RRC_OK) LOG_I(RRC,"CG-ConfigInfo encoded successfully\n"); msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ); + memset(&(X2AP_ENDC_SGNB_ADDITION_REQ(msg)), 0, sizeof(x2ap_ENDC_sgnb_addition_req_t)); X2AP_ENDC_SGNB_ADDITION_REQ(msg).rnti = ctxt_pP->rnti; memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer,enc_buf,enc_size); X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer_size = enc_size; From 87ecb918859044e207941d5b52d88d98584f73e6 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Wed, 6 May 2020 13:45:14 +0200 Subject: [PATCH 212/553] updated cmakelist --- cmake_targets/CMakeLists.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index 465d2dcada..521eb28407 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -2765,6 +2765,7 @@ target_link_libraries(ldpctest add_executable(nr_dlschsim ${OPENAIR1_DIR}/SIMULATION/NR_PHY/dlschsim.c ${OPENAIR_DIR}/common/utils/system.c + ${OPENAIR_DIR}/common/utils/nr/nr_common.c ${UTIL_SRC} ${T_SOURCE} ${SHLIB_LOADER_SOURCES} @@ -2777,6 +2778,7 @@ target_link_libraries(nr_dlschsim add_executable(nr_pbchsim ${OPENAIR1_DIR}/SIMULATION/NR_PHY/pbchsim.c ${OPENAIR_DIR}/common/utils/system.c + ${OPENAIR_DIR}/common/utils/nr/nr_common.c ${UTIL_SRC} ${T_SOURCE} ${SHLIB_LOADER_SOURCES} @@ -2830,6 +2832,7 @@ target_link_libraries(nr_prachsim add_executable(nr_ulschsim ${OPENAIR1_DIR}/SIMULATION/NR_PHY/ulschsim.c ${OPENAIR_DIR}/common/utils/system.c + ${OPENAIR_DIR}/common/utils/nr/nr_common.c ${UTIL_SRC} ${T_SOURCE} ${SHLIB_LOADER_SOURCES} From cf844cef14060a2cfd3a624ecf5da69cc753950c Mon Sep 17 00:00:00 2001 From: "s.rampalli" Date: Wed, 6 May 2020 22:31:08 +0530 Subject: [PATCH 213/553] changed the encoded buffer size to 4096 --- openair2/RRC/LTE/rrc_eNB.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index 3d405cc324..3be5402e3e 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -96,7 +96,7 @@ #include "SIMULATION/TOOLS/sim.h" // for taus -#define ASN_MAX_ENCODE_SIZE 1000 +#define ASN_MAX_ENCODE_SIZE 4096 static int encode_CG_ConfigInfo(char *buffer,int buffer_size,rrc_eNB_ue_context_t *const ue_context_pP,int *enc_size); static int is_en_dc_supported(LTE_UE_EUTRA_Capability_t *c); static void free_rb_config(struct NR_RadioBearerConfig *rb_config); From 014e045ba6197eee2e096074be2a4fdab961fab4 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Thu, 7 May 2020 09:44:07 +0200 Subject: [PATCH 214/553] bugfix in dmrs offset for pusch --- openair1/PHY/INIT/nr_init.c | 2 +- openair1/PHY/NR_REFSIG/nr_dmrs_rx.c | 6 ++++-- openair1/SCHED_NR/phy_procedures_nr_gNB.c | 13 +++++++++++++ 3 files changed, 18 insertions(+), 3 deletions(-) diff --git a/openair1/PHY/INIT/nr_init.c b/openair1/PHY/INIT/nr_init.c index 57e15234ac..ee64c5a32a 100644 --- a/openair1/PHY/INIT/nr_init.c +++ b/openair1/PHY/INIT/nr_init.c @@ -176,7 +176,7 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, } uint32_t Nid_pusch[2] = {cfg->cell_config.phy_cell_id.value,cfg->cell_config.phy_cell_id.value}; - LOG_D(PHY,"Initializing PUSCH DMRS Gold sequence with (%x,%x)\n",Nid_pusch[1],Nid_pusch[2]); + LOG_D(PHY,"Initializing PUSCH DMRS Gold sequence with (%x,%x)\n",Nid_pusch[0],Nid_pusch[1]); nr_gold_pusch(gNB, &Nid_pusch[0]); /// Transport init necessary for NR synchro diff --git a/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c b/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c index 1f2687b883..2f88242eb7 100644 --- a/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c +++ b/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c @@ -70,14 +70,16 @@ int nr_pusch_dmrs_rx(PHY_VARS_gNB *gNB, wf = (dmrs_type==pusch_dmrs_type1) ? wf1 : wf2; wt = (dmrs_type==pusch_dmrs_type1) ? wt1 : wt2; + int dmrs_offset = re_offset/((dmrs_type==pusch_dmrs_type1)?2:3); + if (dmrs_type > 2) LOG_E(PHY,"PUSCH DMRS config type %d not valid\n", dmrs_type+1); if ((p>=1000) && (p<((dmrs_type==pusch_dmrs_type1) ? 1008 : 1012))) { if (gNB->frame_parms.Ncp == NORMAL) { nb_dmrs = ((dmrs_type==pusch_dmrs_type1) ? 6:4); - for (int i=re_offset; islot == slot_rx) && (ulsch_harq->handled == 0)){ +#ifdef DEBUG_RXDATA + int slot_offset = frame_parms->get_samples_slot_timestamp(slot_rx,frame_parms,0); + slot_offset -= ru->N_TA_offset; + char name[128]; + FILE *f; + sprintf(name, "rxdata.%d.%d.raw", frame_rx,slot_rx); + f = fopen(name, "w"); if (f == NULL) exit(1); + fwrite(&ru->common.rxdata[0][slot_offset],2,frame_parms->get_samples_per_slot(slot_rx,frame_parms)*2, f); + fclose(f); +#endif + uint8_t symbol_start = ulsch_harq->ulsch_pdu.start_symbol_index; uint8_t symbol_end = symbol_start + ulsch_harq->ulsch_pdu.nr_of_symbols; for(uint8_t symbol = symbol_start; symbol < symbol_end; symbol++) { From d4929cc21e917bf13eba929f7d9a1e3b9d2d8fa6 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Thu, 7 May 2020 09:52:48 +0200 Subject: [PATCH 215/553] bugfix in dmrs offset for pusch --- openair1/PHY/NR_REFSIG/nr_dmrs_rx.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c b/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c index b1b038e918..4580ccce8c 100644 --- a/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c +++ b/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c @@ -63,32 +63,34 @@ int nr_pusch_dmrs_rx(PHY_VARS_gNB *gNB, int8_t w, nb_dmrs; short *mod_table; unsigned char idx=0; - + int k; typedef int array_of_w[2]; array_of_w *wf; array_of_w *wt; wf = (dmrs_type==pusch_dmrs_type1) ? wf1 : wf2; wt = (dmrs_type==pusch_dmrs_type1) ? wt1 : wt2; + int dmrs_offset = re_offset/((dmrs_type==pusch_dmrs_type1)?2:3); + if (dmrs_type > 2) LOG_E(PHY,"PUSCH DMRS config type %d not valid\n", dmrs_type+1); if ((p>=1000) && (p<((dmrs_type==pusch_dmrs_type1) ? 1008 : 1012))) { if (gNB->frame_parms.Ncp == NORMAL) { nb_dmrs = ((dmrs_type==pusch_dmrs_type1) ? 6:4); - for (int i=re_offset; i>5])>>((i<<1)&0x1f))&1)<<1) ^ (((nr_gold_pusch[((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1); - ((int16_t*)output)[i<<1] = mod_table[(NR_MOD_TABLE_QPSK_OFFSET + idx)<<1]; - ((int16_t*)output)[(i<<1)+1] = mod_table[((NR_MOD_TABLE_QPSK_OFFSET + idx)<<1) + 1]; + ((int16_t*)output)[k<<1] = mod_table[(NR_MOD_TABLE_QPSK_OFFSET + idx)<<1]; + ((int16_t*)output)[(k<<1)+1] = mod_table[((NR_MOD_TABLE_QPSK_OFFSET + idx)<<1) + 1]; #ifdef DEBUG_PUSCH printf("nr_pusch_dmrs_rx dmrs config type %d port %d nb_pusch_rb %d\n", dmrs_type, p, nb_pusch_rb); printf("wf[%d] = %d wt[%d]= %d\n", i&1, wf[p-1000][i&1], lp, wt[p-1000][lp]); printf("i %d idx %d pusch gold %u b0-b1 %d-%d mod_dmrs %d %d\n", i, idx, nr_gold_pusch[(i<<1)>>5], (((nr_gold_pusch[(i<<1)>>5])>>((i<<1)&0x1f))&1), - (((nr_gold_pusch[((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1), ((int16_t*)output)[i<<1], ((int16_t*)output)[(i<<1)+1]); + (((nr_gold_pusch[((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1), ((int16_t*)output)[k<<1], ((int16_t*)output)[(k<<1)+1]); #endif } @@ -103,7 +105,6 @@ int nr_pusch_dmrs_rx(PHY_VARS_gNB *gNB, } - int nr_pdsch_dmrs_rx(PHY_VARS_NR_UE *ue, unsigned int Ns, unsigned int *nr_gold_pdsch, From fa18a88fdb79892a27c035f15f7ea5e0d1a07690 Mon Sep 17 00:00:00 2001 From: Thomas Schlichter Date: Wed, 29 Apr 2020 14:17:09 +0200 Subject: [PATCH 216/553] fix updating UE->frame_gap and calculation if proc->frame_rx > dcireq.dl_config_req.sfn --- executables/nr-ue.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/executables/nr-ue.c b/executables/nr-ue.c index f5b0c157ef..71d98ce387 100644 --- a/executables/nr-ue.c +++ b/executables/nr-ue.c @@ -443,19 +443,18 @@ void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { dcireq.slot = proc->nr_tti_rx; nr_ue_dcireq(&dcireq); //to be replaced with function pointer later + if ((proc->frame_rx % (1 << (ssb_period-1)) == 0) && (proc->nr_tti_rx == 1)) { + UE->frame_gap = (MAX_FRAME_NUMBER + dcireq.dl_config_req.sfn - proc->frame_rx) % MAX_FRAME_NUMBER; + proc->frame_rx = (proc->frame_rx + UE->frame_gap) % MAX_FRAME_NUMBER; + proc->frame_tx = (proc->frame_tx + UE->frame_gap) % MAX_FRAME_NUMBER; + } + // we should have received a DL DCI here, so configure DL accordingly scheduled_response.dl_config = &dcireq.dl_config_req; scheduled_response.ul_config = NULL; scheduled_response.tx_request = NULL; scheduled_response.module_id = UE->Mod_id; scheduled_response.CC_id = 0; - if (!((proc->frame_rx)%(1<<(ssb_period-1)))) { - if(proc->frame_rx > dcireq.dl_config_req.sfn) - UE->frame_gap = proc->frame_rx - dcireq.dl_config_req.sfn; - if(proc->frame_rx < dcireq.dl_config_req.sfn) - UE->frame_gap = dcireq.dl_config_req.sfn - proc->frame_rx; - proc->frame_rx = dcireq.dl_config_req.sfn; - } scheduled_response.frame = proc->frame_rx; scheduled_response.slot = proc->nr_tti_rx; @@ -737,6 +736,12 @@ void *UE_thread(void *arg) { absolute_slot++; + + if(UE->frame_gap) { + absolute_slot += UE->frame_gap * nb_slot_frame; + UE->frame_gap = 0; + } + // whatever means thread_idx // Fix me: will be wrong when slot 1 is slow, as slot 2 finishes // Slot 3 will overlap if RX_NB_TH is 2 @@ -754,8 +759,8 @@ void *UE_thread(void *arg) { curMsg->proc.subframe_rx=slot_nr/(nb_slot_frame/10); curMsg->proc.nr_tti_tx = (absolute_slot + DURATION_RX_TO_TX) % nb_slot_frame; curMsg->proc.subframe_tx=curMsg->proc.nr_tti_rx; - curMsg->proc.frame_rx = ((absolute_slot/nb_slot_frame)+UE->frame_gap) % MAX_FRAME_NUMBER; - curMsg->proc.frame_tx = (((absolute_slot+DURATION_RX_TO_TX)/nb_slot_frame)+UE->frame_gap) % MAX_FRAME_NUMBER; + curMsg->proc.frame_rx = (absolute_slot/nb_slot_frame) % MAX_FRAME_NUMBER; + curMsg->proc.frame_tx = ((absolute_slot+DURATION_RX_TO_TX)/nb_slot_frame) % MAX_FRAME_NUMBER; curMsg->proc.decoded_frame_rx=-1; //LOG_I(PHY,"Process slot %d thread Idx %d total gain %d\n", slot_nr, thread_idx, UE->rx_total_gain_dB); From aa7e10c4052b8b6bff9685df5f4c7efaa5360cd5 Mon Sep 17 00:00:00 2001 From: Thomas Schlichter Date: Wed, 29 Apr 2020 17:39:33 +0200 Subject: [PATCH 217/553] also use the high 6 bits from MIB when calculating decoded_frame_rx after the initial synchronization --- executables/nr-ue.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/executables/nr-ue.c b/executables/nr-ue.c index 71d98ce387..cf7a77a1d4 100644 --- a/executables/nr-ue.c +++ b/executables/nr-ue.c @@ -690,8 +690,11 @@ void *UE_thread(void *arg) { if (res) { syncRunning=false; syncData_t *tmp=(syncData_t *)NotifiedFifoData(res); - // shift the frame index with all the frames we trashed meanwhile we perform the synch search - decoded_frame_rx=(tmp->proc.decoded_frame_rx + (!UE->init_sync_frame) + trashed_frames) % MAX_FRAME_NUMBER; + if (UE->is_synchronized) { + decoded_frame_rx=(((mac->mib->systemFrameNumber.buf[0] >> mac->mib->systemFrameNumber.bits_unused)<<4) | tmp->proc.decoded_frame_rx); + // shift the frame index with all the frames we trashed meanwhile we perform the synch search + decoded_frame_rx=(decoded_frame_rx + (!UE->init_sync_frame) + trashed_frames) % MAX_FRAME_NUMBER; + } delNotifiedFIFO_elt(res); } else { readFrame(UE, ×tamp, true); From 25c4cea36f66a9730a83439d9446855cf3c0fb20 Mon Sep 17 00:00:00 2001 From: Thomas Schlichter Date: Wed, 29 Apr 2020 18:12:47 +0200 Subject: [PATCH 218/553] remove now unnecessary frame_gap completely --- executables/nr-ue.c | 11 ----------- openair1/PHY/defs_nr_UE.h | 2 -- 2 files changed, 13 deletions(-) diff --git a/executables/nr-ue.c b/executables/nr-ue.c index cf7a77a1d4..8e59bd98b4 100644 --- a/executables/nr-ue.c +++ b/executables/nr-ue.c @@ -443,12 +443,6 @@ void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { dcireq.slot = proc->nr_tti_rx; nr_ue_dcireq(&dcireq); //to be replaced with function pointer later - if ((proc->frame_rx % (1 << (ssb_period-1)) == 0) && (proc->nr_tti_rx == 1)) { - UE->frame_gap = (MAX_FRAME_NUMBER + dcireq.dl_config_req.sfn - proc->frame_rx) % MAX_FRAME_NUMBER; - proc->frame_rx = (proc->frame_rx + UE->frame_gap) % MAX_FRAME_NUMBER; - proc->frame_tx = (proc->frame_tx + UE->frame_gap) % MAX_FRAME_NUMBER; - } - // we should have received a DL DCI here, so configure DL accordingly scheduled_response.dl_config = &dcireq.dl_config_req; scheduled_response.ul_config = NULL; @@ -740,11 +734,6 @@ void *UE_thread(void *arg) { absolute_slot++; - if(UE->frame_gap) { - absolute_slot += UE->frame_gap * nb_slot_frame; - UE->frame_gap = 0; - } - // whatever means thread_idx // Fix me: will be wrong when slot 1 is slow, as slot 2 finishes // Slot 3 will overlap if RX_NB_TH is 2 diff --git a/openair1/PHY/defs_nr_UE.h b/openair1/PHY/defs_nr_UE.h index ac71f708ec..b3bb21881f 100644 --- a/openair1/PHY/defs_nr_UE.h +++ b/openair1/PHY/defs_nr_UE.h @@ -884,8 +884,6 @@ typedef struct { fapi_nr_config_request_t nrUE_config; - uint16_t frame_gap; - // the following structures are not part of PHY_vars_UE anymore as it is not thread safe. They are now on the stack of the functions that actually need them //nr_downlink_indication_t dl_indication; From 589801f620b0e2753de8e5d6bf05f659cc3b4f0f Mon Sep 17 00:00:00 2001 From: Ahmed Hussein Date: Tue, 28 Apr 2020 17:54:38 +0200 Subject: [PATCH 219/553] Fixed bug related to N_TA_offset not being applied at UE - By default this value is equal to 0 at gNB in case of ulsim, but has a value in case of RF simulator - The N_TA_offset was calculated but not used at UE side --- openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c | 52 +++++++++++++++++----- 1 file changed, 41 insertions(+), 11 deletions(-) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c index 14c70e6582..769cea37a1 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c @@ -537,21 +537,51 @@ uint8_t nr_ue_pusch_common_procedures(PHY_VARS_NR_UE *UE, txdata = UE->common_vars.txdata; txdataF = UE->common_vars.txdataF; - for (ap = 0; ap < Nl; ap++) { + if(UE->N_TA_offset > tx_offset) { + int32_t *tmp_idft_out = (int32_t*)malloc16(frame_parms->get_samples_per_slot(slot, frame_parms) * sizeof(int32_t)); + + for(ap = 0; ap < Nl; ap++) { if (frame_parms->Ncp == 1) { // extended cyclic prefix - PHY_ofdm_mod(txdataF[ap], - &txdata[ap][tx_offset], - frame_parms->ofdm_symbol_size, - 12, - frame_parms->nb_prefix_samples, - CYCLIC_PREFIX); + PHY_ofdm_mod(txdataF[ap], + tmp_idft_out, + frame_parms->ofdm_symbol_size, + 12, + frame_parms->nb_prefix_samples, + CYCLIC_PREFIX); } else { // normal cyclic prefix - nr_normal_prefix_mod(txdataF[ap], - &txdata[ap][tx_offset], - 14, - frame_parms); + nr_normal_prefix_mod(txdataF[ap], + tmp_idft_out, + 14, + frame_parms); + } + + memcpy((void *) &txdata[ap][frame_parms->samples_per_frame - UE->N_TA_offset + tx_offset], + (void *) tmp_idft_out, + (UE->N_TA_offset - tx_offset) * sizeof(int32_t)); + + memcpy((void *) &txdata[ap][0], + (void *) &tmp_idft_out[UE->N_TA_offset - tx_offset], + (frame_parms->get_samples_per_slot(slot, frame_parms) - UE->N_TA_offset + tx_offset) * sizeof(int32_t)); + } + + free(tmp_idft_out); + } else { // UE->N_TA_offset <= tx_offset + for (ap = 0; ap < Nl; ap++) { + if (frame_parms->Ncp == 1) { // extended cyclic prefix + PHY_ofdm_mod(txdataF[ap], + &txdata[ap][tx_offset-UE->N_TA_offset], + frame_parms->ofdm_symbol_size, + 12, + frame_parms->nb_prefix_samples, + CYCLIC_PREFIX); + } else { // normal cyclic prefix + nr_normal_prefix_mod(txdataF[ap], + &txdata[ap][tx_offset-UE->N_TA_offset], + 14, + frame_parms); } } + } /////////// //////////////////////////////////////////////////// From 6a32e60a4fc6e140367980b2f1fa784610ba5b13 Mon Sep 17 00:00:00 2001 From: Ahmed Hussein Date: Tue, 28 Apr 2020 17:47:21 +0200 Subject: [PATCH 220/553] Fixed bug regarding TBS calculation and G calculation - The number of nb_dmrs_re at gNB side was set to 6, but here it is assumed that there will be no data allocation in OFDM symbols that carry DMRS - nb_dmrs_re that is being given as an input to the TBS calculation, should be multiplied by the number of DMRS symbols in order to get the total number of DMRS REs per RB - In the calculation of G, only the number of DMRS per RB in 1 OFDM symbol should be given as an input, because inside the function of the G calculation, this number is being multiplied by the number of OFDM symbols that carry DMRS --- openair1/SCHED_NR/phy_procedures_nr_gNB.c | 3 +-- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 2 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 9 ++++++++- 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index cee747203d..4489579c79 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -230,7 +230,7 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH number_dmrs_symbols += ((pusch_pdu->ul_dmrs_symb_pos)>>l)&0x01; if (nodata_dmrs) - nb_re_dmrs = 12*number_dmrs_symbols; + nb_re_dmrs = 12; else nb_re_dmrs = ((pusch_pdu->dmrs_config_type == pusch_dmrs_type1)?6:4); @@ -245,7 +245,6 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH //---------------------------------------------------------- //------------------- ULSCH unscrambling ------------------- //---------------------------------------------------------- - start_meas(&gNB->ulsch_unscrambling_stats); nr_ulsch_unscrambling(gNB->pusch_vars[ULSCH_id]->llr, G, diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index 4358cdd772..3d40807df3 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -1452,7 +1452,7 @@ void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, R, pdsch_rel15->rbSize, N_sh_symb, - N_PRB_DMRS, + N_PRB_DMRS, // FIXME // This should be multiplied by the number of dmrs symbols N_PRB_oh, tb_scaling, pdsch_rel15->nrOfLayers)>>3; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 7015c0d8ce..9255d633f8 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -818,11 +818,18 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, pusch_pdu->pusch_data.rv_index = 0; pusch_pdu->pusch_data.harq_process_id = 0; pusch_pdu->pusch_data.new_data_indicator = 0; + + uint8_t no_data_in_dmrs = 1; // temp implementation + uint8_t num_dmrs_symb = 0; + + for(int dmrs_counter = pusch_pdu->start_symbol_index; dmrs_counter < pusch_pdu->start_symbol_index + pusch_pdu->nr_of_symbols; dmrs_counter++) + num_dmrs_symb += ((pusch_pdu->ul_dmrs_symb_pos >> dmrs_counter) & 1); + pusch_pdu->pusch_data.tb_size = nr_compute_tbs(pusch_pdu->qam_mod_order, pusch_pdu->target_code_rate, pusch_pdu->rb_size, pusch_pdu->nr_of_symbols, - 6, //nb_re_dmrs - not sure where this is coming from - its not in the FAPI + ( no_data_in_dmrs ? 12 : ((pusch_pdu->dmrs_config_type == pusch_dmrs_type1) ? 6 : 4) ) * num_dmrs_symb, 0, //nb_rb_oh 0, pusch_pdu->nrOfLayers)>>3; From 70dff719e24a6a7ca981aae41e894d097b98fb7f Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Fri, 8 May 2020 10:16:30 +0200 Subject: [PATCH 221/553] pusch dmrs rx fix, added comp file dump to ulsim --- openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c | 6 +++--- openair1/PHY/NR_REFSIG/nr_dmrs_rx.c | 2 +- openair1/SIMULATION/NR_PHY/ulsim.c | 2 ++ 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c index a141970840..f39a30fbe3 100644 --- a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c +++ b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c @@ -27,8 +27,8 @@ #include "PHY/NR_REFSIG/nr_refsig.h" #include "PHY/NR_UE_ESTIMATION/filt16a_32.h" -//#define DEBUG_CH -//#define DEBUG_PUSCH +#define DEBUG_CH +#define DEBUG_PUSCH int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, unsigned char Ns, @@ -117,7 +117,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, //------------------generate DMRS------------------// if (pusch_pdu->transform_precoding==1) // if transform precoding is disabled - nr_pusch_dmrs_rx(gNB, Ns, gNB->nr_gold_pusch_dmrs[pusch_pdu->scid][Ns][symbol], &pilot[0], 1000, 0, nb_rb_pusch, pusch_pdu->rb_start*NR_NB_SC_PER_RB, pusch_pdu->dmrs_config_type); + nr_pusch_dmrs_rx(gNB, Ns, gNB->nr_gold_pusch_dmrs[pusch_pdu->scid][Ns][symbol], &pilot[0], 1000, 0, nb_rb_pusch, pusch_pdu->rb_start*NR_NB_SC_PER_RB/((pusch_pdu->dmrs_config_type==pusch_dmrs_type1)?2:3), pusch_pdu->dmrs_config_type); else nr_pusch_dmrs_rx(gNB, Ns, gNB->nr_gold_pusch_dmrs[pusch_pdu->scid][Ns][symbol], &pilot[0], 1000, 0, nb_rb_pusch, 0, pusch_pdu->dmrs_config_type); diff --git a/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c b/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c index 1f2687b883..b72f6e0c61 100644 --- a/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c +++ b/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c @@ -32,7 +32,7 @@ //#define NR_PBCH_DMRS_LENGTH_DWORD 5 //#define NR_PBCH_DMRS_LENGTH 144 -//#define DEBUG_PUSCH +#define DEBUG_PUSCH #include "refsig_defs_ue.h" #include "PHY/defs_nr_UE.h" diff --git a/openair1/SIMULATION/NR_PHY/ulsim.c b/openair1/SIMULATION/NR_PHY/ulsim.c index d184ba130b..3fced2c83d 100644 --- a/openair1/SIMULATION/NR_PHY/ulsim.c +++ b/openair1/SIMULATION/NR_PHY/ulsim.c @@ -771,6 +771,8 @@ int main(int argc, char **argv) &gNB->pusch_vars[0]->ul_ch_estimates[0][start_symbol*frame_parms->ofdm_symbol_size],frame_parms->ofdm_symbol_size,1,1); LOG_M("chestF0_ext.m","chF0_ext", &gNB->pusch_vars[0]->ul_ch_estimates_ext[0][(start_symbol+1)*NR_NB_SC_PER_RB * pusch_pdu->rb_size],(nb_symb_sch-1)*NR_NB_SC_PER_RB * pusch_pdu->rb_size,1,1); + LOG_M("rxsigF0_comp.m","rxsF0_comp", + &gNB->pusch_vars[0]->rxdataF_comp[0][(start_symbol+1)*NR_NB_SC_PER_RB * pusch_pdu->rb_size],(nb_symb_sch-1)*NR_NB_SC_PER_RB * pusch_pdu->rb_size,1,1); } start_meas(&gNB->phy_proc_rx); //////////////////////////////////////////////////////////// From 160fef9a2dd7e29d513dcc82eb3c1463edf302e4 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Fri, 8 May 2020 10:25:06 +0200 Subject: [PATCH 222/553] fix after merge --- openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c index f39a30fbe3..f212e6aadb 100644 --- a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c +++ b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c @@ -117,7 +117,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, //------------------generate DMRS------------------// if (pusch_pdu->transform_precoding==1) // if transform precoding is disabled - nr_pusch_dmrs_rx(gNB, Ns, gNB->nr_gold_pusch_dmrs[pusch_pdu->scid][Ns][symbol], &pilot[0], 1000, 0, nb_rb_pusch, pusch_pdu->rb_start*NR_NB_SC_PER_RB/((pusch_pdu->dmrs_config_type==pusch_dmrs_type1)?2:3), pusch_pdu->dmrs_config_type); + nr_pusch_dmrs_rx(gNB, Ns, gNB->nr_gold_pusch_dmrs[pusch_pdu->scid][Ns][symbol], &pilot[0], 1000, 0, nb_rb_pusch, pusch_pdu->rb_start*NR_NB_SC_PER_RB, pusch_pdu->dmrs_config_type); else nr_pusch_dmrs_rx(gNB, Ns, gNB->nr_gold_pusch_dmrs[pusch_pdu->scid][Ns][symbol], &pilot[0], 1000, 0, nb_rb_pusch, 0, pusch_pdu->dmrs_config_type); From 185477dc9f06dd2df1bca85872f8dc062d6b38d3 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 8 May 2020 15:29:28 +0200 Subject: [PATCH 223/553] fix for ULSCH ok when PRBs are empty --- .../PHY/NR_TRANSPORT/nr_transport_proto.h | 12 +++++------ .../PHY/NR_TRANSPORT/nr_ulsch_demodulation.c | 20 ++++++++++++------- openair1/SCHED_NR/phy_procedures_nr_gNB.c | 6 +++++- 3 files changed, 24 insertions(+), 14 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h b/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h index 9f555e663e..19b50792e4 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h +++ b/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h @@ -46,12 +46,12 @@ @param symbol Symbol on which to act (within-in nr_TTI_rx) @param harq_pid HARQ process ID */ -void nr_rx_pusch(PHY_VARS_gNB *gNB, - uint8_t UE_id, - uint32_t frame, - uint8_t nr_tti_rx, - unsigned char symbol, - unsigned char harq_pid); +int nr_rx_pusch(PHY_VARS_gNB *gNB, + uint8_t UE_id, + uint32_t frame, + uint8_t nr_tti_rx, + unsigned char symbol, + unsigned char harq_pid); /** \brief This function performs RB extraction (signal and channel estimates) (currently signal only until channel estimation and compensation are implemented) diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c index 3134713d4a..2824ac1544 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c @@ -1013,12 +1013,12 @@ void nr_ulsch_channel_compensation(int **rxdataF_ext, } -void nr_rx_pusch(PHY_VARS_gNB *gNB, - uint8_t ulsch_id, - uint32_t frame, - uint8_t nr_tti_rx, - unsigned char symbol, - unsigned char harq_pid) +int nr_rx_pusch(PHY_VARS_gNB *gNB, + uint8_t ulsch_id, + uint32_t frame, + uint8_t nr_tti_rx, + unsigned char symbol, + unsigned char harq_pid) { uint8_t aarx, aatx, dmrs_symbol_flag, ptrs_symbol_flag; // dmrs_symbol_flag, a flag to indicate DMRS REs in current symbol @@ -1159,6 +1159,12 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, gNB->pusch_vars[ulsch_id]->log2_maxh); stop_meas(&gNB->ulsch_channel_compensation_stats); + + int rxsig = signal_energy(&gNB->pusch_vars[ulsch_id]->rxdataF_comp[0][(symbol*rel15_ul->rb_size*12)], + rel15_ul->rb_size*12); + + if (rxsig==1) return (rxsig); + #ifdef NR_SC_FDMA nr_idft(&((uint32_t*)gNB->pusch_vars[ulsch_id]->rxdataF_ext[0])[symbol * rel15_ul->rb_size * NR_NB_SC_PER_RB], nb_re_pusch); #endif @@ -1181,5 +1187,5 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, } gNB->pusch_vars[ulsch_id]->rxdataF_ext_offset = gNB->pusch_vars[ulsch_id]->rxdataF_ext_offset + nb_re_pusch; - + return (0); } diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index 4489579c79..6b49d64338 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -424,6 +424,7 @@ void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) for (int ULSCH_id=0;ULSCH_idulsch[ULSCH_id][0]; int harq_pid; + int no_sig; NR_UL_gNB_HARQ_t *ulsch_harq; if ((ulsch) && @@ -438,6 +439,8 @@ void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) (ulsch_harq->handled == 0)){ #ifdef DEBUG_RXDATA + NR_DL_FRAME_PARMS *frame_parms = &gNB->frame_parms; + RU_t *ru = gNB->RU_list[0]; int slot_offset = frame_parms->get_samples_slot_timestamp(slot_rx,frame_parms,0); slot_offset -= ru->N_TA_offset; char name[128]; @@ -451,7 +454,8 @@ void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) uint8_t symbol_start = ulsch_harq->ulsch_pdu.start_symbol_index; uint8_t symbol_end = symbol_start + ulsch_harq->ulsch_pdu.nr_of_symbols; for(uint8_t symbol = symbol_start; symbol < symbol_end; symbol++) { - nr_rx_pusch(gNB, ULSCH_id, frame_rx, slot_rx, symbol, harq_pid); + no_sig = nr_rx_pusch(gNB, ULSCH_id, frame_rx, slot_rx, symbol, harq_pid); + if (no_sig) return; } //LOG_M("rxdataF_comp.m","rxF_comp",gNB->pusch_vars[0]->rxdataF_comp[0],6900,1,1); //LOG_M("rxdataF_ext.m","rxF_ext",gNB->pusch_vars[0]->rxdataF_ext[0],6900,1,1); From 88e5203dfaf7a822a8b47e7d85ac4dca48a11a31 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 8 May 2020 17:19:31 +0200 Subject: [PATCH 224/553] bugfix in dci1_1 size --- openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c | 4 ++-- openair1/PHY/NR_REFSIG/nr_dmrs_rx.c | 2 +- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c index f212e6aadb..a141970840 100644 --- a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c +++ b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c @@ -27,8 +27,8 @@ #include "PHY/NR_REFSIG/nr_refsig.h" #include "PHY/NR_UE_ESTIMATION/filt16a_32.h" -#define DEBUG_CH -#define DEBUG_PUSCH +//#define DEBUG_CH +//#define DEBUG_PUSCH int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, unsigned char Ns, diff --git a/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c b/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c index 870b8b098c..2f88242eb7 100644 --- a/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c +++ b/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c @@ -32,7 +32,7 @@ //#define NR_PBCH_DMRS_LENGTH_DWORD 5 //#define NR_PBCH_DMRS_LENGTH 144 -#define DEBUG_PUSCH +//#define DEBUG_PUSCH #include "refsig_defs_ue.h" #include "PHY/defs_nr_UE.h" diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index 3d40807df3..60814529a6 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -1742,7 +1742,7 @@ uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, dci_pdu->time_domain_assignment.nbits = (int)ceil(log2(num_entries)); size += dci_pdu->time_domain_assignment.nbits; // VRB to PRB mapping - if (pdsch_config->resourceAllocation == 1) { + if ((pdsch_config->resourceAllocation == 1) && (bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver != NULL)) { dci_pdu->vrb_to_prb_mapping.nbits = 1; size += dci_pdu->vrb_to_prb_mapping.nbits; } @@ -1791,7 +1791,7 @@ uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, NR_SetupRelease_DMRS_DownlinkConfig_t *typeA = pdsch_config->dmrs_DownlinkForPDSCH_MappingTypeA; NR_SetupRelease_DMRS_DownlinkConfig_t *typeB = pdsch_config->dmrs_DownlinkForPDSCH_MappingTypeB; dci_pdu->antenna_ports.nbits = getAntPortBitWidth(typeA,typeB); - size += dci_pdu->antenna_ports.nbits; + size += dci_pdu->antenna_ports.nbits; // Tx Config Indication long *isTciEnable = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[bwp_id-1]->tci_PresentInDCI; if (isTciEnable != NULL) { From cdead06962a6d8ccfa7934842015998f2774bedc Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 24 Apr 2020 11:42:50 +0200 Subject: [PATCH 225/553] fix for scrambling rnti and dci format --- .../open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h | 2 +- openair1/PHY/NR_UE_TRANSPORT/dci_nr.c | 2 +- openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c | 10 ++++++---- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 6 +++++- 4 files changed, 13 insertions(+), 7 deletions(-) diff --git a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h index 610a798292..4318db7a68 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h @@ -60,7 +60,7 @@ typedef struct { uint8_t CoreSetType; uint8_t precoder_granularity; uint16_t pdcch_dmrs_scrambling_id; - + uint16_t scrambling_rnti; uint8_t tci_state_pdcch; uint8_t tci_present_in_dci; } fapi_nr_coreset_t; diff --git a/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c b/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c index adc619825a..1c722665bc 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c +++ b/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c @@ -858,7 +858,7 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue, LOG_D(PHY, "Trying DCI candidate %d of %d number of candidates, CCE %d (%d), L %d\n", j, rel15->number_of_candidates, CCEind, CCEind*9*6*2, L); - nr_pdcch_unscrambling(&pdcch_vars->e_rx[CCEind*108], rel15->rnti, L*108, rel15->coreset.pdcch_dmrs_scrambling_id, tmp_e); + nr_pdcch_unscrambling(&pdcch_vars->e_rx[CCEind*108], rel15->coreset.scrambling_rnti, L*108, rel15->coreset.pdcch_dmrs_scrambling_id, tmp_e); #ifdef DEBUG_DCI_DECODING uint32_t * z = (uint32_t *) &pdcch_vars->e_rx[CCEind*108]; diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c index 61cf7332b2..362b1d3466 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c @@ -180,12 +180,14 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_ } rel15->coreset.CoreSetType = 1; rel15->coreset.precoder_granularity = mac->coreset[0][0]->precoderGranularity; - - if (mac->coreset[0][0]->pdcch_DMRS_ScramblingID) + if (mac->coreset[0][0]->pdcch_DMRS_ScramblingID) { rel15->coreset.pdcch_dmrs_scrambling_id = *mac->coreset[0][0]->pdcch_DMRS_ScramblingID; - else + rel15->coreset.scrambling_rnti = mac->t_crnti; + } + else { rel15->coreset.pdcch_dmrs_scrambling_id = *mac->scc->physCellId; - + rel15->coreset.scrambling_rnti = 0; + } fill_dci_search_candidates(mac->SSpace[0][0][ss_id],rel15); dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI; dl_config->number_pdus = dl_config->number_pdus + 1; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 3a8db970e8..08d55779bd 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -392,7 +392,11 @@ int configure_fapi_dl_pdu(int Mod_idP, int dci_formats[2]; int rnti_types[2]; - dci_formats[0] = NR_DL_DCI_FORMAT_1_0; + if (ss->searchSpaceType->choice.ue_Specific->dci_Formats) + dci_formats[0] = NR_DL_DCI_FORMAT_1_1; + else + dci_formats[0] = NR_DL_DCI_FORMAT_1_0; + rnti_types[0] = NR_RNTI_C; pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); From e3ba90b055aaf122783917241018996e4dc19455 Mon Sep 17 00:00:00 2001 From: cig Date: Tue, 28 Apr 2020 14:00:58 +0200 Subject: [PATCH 226/553] Fixes for polar and scrambling RNTI at UE - including temporary hotfix for the polar rnti --- openair1/PHY/NR_UE_TRANSPORT/dci_nr.c | 5 +---- .../LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c | 16 ++++++++-------- 2 files changed, 9 insertions(+), 12 deletions(-) diff --git a/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c b/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c index 1c722665bc..04dd321db2 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c +++ b/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c @@ -874,10 +874,7 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue, 1, currentPtrDCI); - if (get_softmodem_params()->do_ra == 1) - n_rnti = ue->prach_resources[gNB_id]->ra_RNTI; - else - n_rnti = rel15->rnti; + n_rnti = rel15->rnti; if (crc == n_rnti) { LOG_D(PHY,"Decoded crc %x matches rnti %x for DCI format %d\n", crc, n_rnti, rel15->dci_format); diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c index 362b1d3466..e745bfb693 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c @@ -130,12 +130,6 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_ } if (mac->crnti>0) { rel15 = &dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15; - - if (get_softmodem_params()->do_ra == 1) - rel15->rnti = 0x00; - else // phy_test - rel15->rnti = mac->crnti; - rel15->dci_format = NR_DL_DCI_FORMAT_1_0; if (slot == 0 || slot == 1){ @@ -180,14 +174,20 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_ } rel15->coreset.CoreSetType = 1; rel15->coreset.precoder_granularity = mac->coreset[0][0]->precoderGranularity; + if (mac->coreset[0][0]->pdcch_DMRS_ScramblingID) { rel15->coreset.pdcch_dmrs_scrambling_id = *mac->coreset[0][0]->pdcch_DMRS_ScramblingID; rel15->coreset.scrambling_rnti = mac->t_crnti; - } - else { + } else { rel15->coreset.pdcch_dmrs_scrambling_id = *mac->scc->physCellId; rel15->coreset.scrambling_rnti = 0; } + + if (get_softmodem_params()->do_ra && slot == 7) + rel15->rnti = mac->ra_rnti; + else + rel15->rnti = mac->crnti; + fill_dci_search_candidates(mac->SSpace[0][0][ss_id],rel15); dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI; dl_config->number_pdus = dl_config->number_pdus + 1; From 4dc0e7f2355717c22b5f0d3df9dc7176905d3aaf Mon Sep 17 00:00:00 2001 From: cig Date: Wed, 29 Apr 2020 12:15:49 +0200 Subject: [PATCH 227/553] Enabled UE to process RX and TX in every DL or UL (or mixed) slot respectivey - the commit fixes also the selection of the thread_id in TX procedures - DCI configuration is currently limited to slot 1 and 7 --- executables/nr-ue.c | 18 ++--- openair1/SCHED_NR/phy_frame_config_nr.c | 67 +++++++++++++++++++ .../NR_MAC_UE/nr_ue_dci_configuration.c | 8 ++- 3 files changed, 82 insertions(+), 11 deletions(-) diff --git a/executables/nr-ue.c b/executables/nr-ue.c index 8e59bd98b4..fb9d260541 100644 --- a/executables/nr-ue.c +++ b/executables/nr-ue.c @@ -373,8 +373,11 @@ void processSlotTX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { nr_dcireq_t dcireq; nr_scheduled_response_t scheduled_response; + fapi_nr_config_request_t *cfg = &UE->nrUE_config; + int tx_slot_type = nr_ue_slot_select(cfg, proc->frame_tx, proc->nr_tti_tx); + // program PUSCH. this should actually be done by the MAC upon reception of an UL DCI - if (proc->nr_tti_tx == 8 || proc->nr_tti_tx == 19 || UE->frame_parms.frame_type == FDD){ + if (tx_slot_type == NR_UPLINK_SLOT || tx_slot_type == NR_MIXED_SLOT){ mod_id = UE->Mod_id; @@ -403,7 +406,7 @@ void processSlotTX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { rvidx = 0; //------------------------------------------------------------------------------// - scheduled_response.ul_config->slot = 8; + scheduled_response.ul_config->slot = proc->nr_tti_tx; scheduled_response.ul_config->number_pdus = 1; scheduled_response.ul_config->ul_config_list[0].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH; scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.rnti = n_rnti; @@ -420,7 +423,7 @@ void processSlotTX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { nr_ue_scheduled_response(&scheduled_response); if (UE->mode != loop_through_memory) { - uint8_t thread_id = PHY_vars_UE_g[mod_id][0]->current_thread_id[proc->nr_tti_tx]; + uint8_t thread_id = PHY_vars_UE_g[mod_id][0]->current_thread_id[proc->nr_tti_rx]; phy_procedures_nrUE_TX(UE,proc,0,thread_id); } } @@ -430,12 +433,13 @@ void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { nr_dcireq_t dcireq; nr_scheduled_response_t scheduled_response; - uint8_t ssb_period = UE->nrUE_config.ssb_table.ssb_period; + fapi_nr_config_request_t *cfg = &UE->nrUE_config; + int rx_slot_type = nr_ue_slot_select(cfg, proc->frame_rx, proc->nr_tti_rx); + uint8_t ssb_period = UE->nrUE_config.ssb_table.ssb_period; //program DCI for slot 1 //TODO: all of this has to be moved to the MAC!!! - // Note: temp hardcoded slot 7 for RAR - if (proc->nr_tti_rx == NR_DOWNLINK_SLOT || proc->nr_tti_rx == 7 || UE->frame_parms.frame_type == FDD){ + if (rx_slot_type == NR_DOWNLINK_SLOT || rx_slot_type == NR_MIXED_SLOT){ dcireq.module_id = UE->Mod_id; dcireq.gNB_index = 0; dcireq.cc_id = 0; @@ -453,10 +457,8 @@ void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { scheduled_response.slot = proc->nr_tti_rx; nr_ue_scheduled_response(&scheduled_response); - } // Process Rx data for one sub-frame - if ( proc->nr_tti_rx >=0 && proc->nr_tti_rx <= 1 || proc->nr_tti_rx == 7) { #ifdef UE_SLOT_PARALLELISATION phy_procedures_slot_parallelization_nrUE_RX( UE, proc, 0, 0, 1, UE->mode, no_relay, NULL ); #else diff --git a/openair1/SCHED_NR/phy_frame_config_nr.c b/openair1/SCHED_NR/phy_frame_config_nr.c index a36cebd6ae..0ccb13fc7c 100644 --- a/openair1/SCHED_NR/phy_frame_config_nr.c +++ b/openair1/SCHED_NR/phy_frame_config_nr.c @@ -369,6 +369,73 @@ int nr_slot_select(nfapi_nr_config_request_scf_t *cfg, int nr_frame, int nr_tti) } } +/******************************************************************* +* +* NAME : nr_ue_slot_select +* +* DESCRIPTION : function for the UE equivalent to nr_slot_select +* +*********************************************************************/ + +int nr_ue_slot_select(fapi_nr_config_request_t *cfg, int nr_frame, int nr_tti) { + /* for FFD all slot can be considered as an uplink */ + int mu = cfg->ssb_config.scs_common, check_slot = 0; + + if (cfg->cell_config.frame_duplex_type == FDD) { + return (NR_UPLINK_SLOT | NR_DOWNLINK_SLOT); + } + + if (nr_frame%2 == 0) { + for(int symbol_count=0; symbol_counttdd_table.max_tdd_periodicity_list[nr_tti].max_num_of_symbol_per_slot_list[symbol_count].slot_config == 1) { + check_slot++; + } + } + + if(check_slot == NR_NUMBER_OF_SYMBOLS_PER_SLOT) { + return (NR_UPLINK_SLOT); + } + + check_slot = 0; + + for(int symbol_count=0; symbol_counttdd_table.max_tdd_periodicity_list[nr_tti].max_num_of_symbol_per_slot_list[symbol_count].slot_config == 0) { + check_slot++; + } + } + + if(check_slot == NR_NUMBER_OF_SYMBOLS_PER_SLOT) { + return (NR_DOWNLINK_SLOT); + } else { + return (NR_MIXED_SLOT); + } + } else { + for(int symbol_count=0; symbol_counttdd_table.max_tdd_periodicity_list[((1<tdd_table.max_tdd_periodicity_list[((1<scc,slot)==1) { - - // get BWP 1, Coreset 0, SearchSpace 0 + if (slot == 1 || slot == 7) { + + LOG_D(PHY,"Entering UE DCI configuration frame %d slot %d \n", frame, slot); + + // get BWP 1, Coreset 0, SearchSpace 0 if (mac->DLbwp[0]==NULL) { AssertFatal(mac->scd->downlinkBWP_ToAddModList!=NULL,"downlinkBWP_ToAddModList is null\n"); AssertFatal(mac->scd->downlinkBWP_ToAddModList->list.count==1,"downlinkBWP_ToAddModList->list->count is %d\n", From 785ffa4def2cee1ffc2d934e1c94f1eccbf15832 Mon Sep 17 00:00:00 2001 From: cig Date: Wed, 29 Apr 2020 12:25:30 +0200 Subject: [PATCH 228/553] Minor fixes --- openair1/PHY/CODING/nrPolar_tools/nr_polar_encoder.c | 2 +- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/openair1/PHY/CODING/nrPolar_tools/nr_polar_encoder.c b/openair1/PHY/CODING/nrPolar_tools/nr_polar_encoder.c index 8e4b45f744..b142022e37 100644 --- a/openair1/PHY/CODING/nrPolar_tools/nr_polar_encoder.c +++ b/openair1/PHY/CODING/nrPolar_tools/nr_polar_encoder.c @@ -296,7 +296,7 @@ static inline void polar_rate_matching(t_nrPolar_params *polarParams,void *in,vo void build_polar_tables(t_nrPolar_params *polarParams) { // build table b -> c' AssertFatal(polarParams->K > 32, "K = %d < 33, is not supported yet\n",polarParams->K); - AssertFatal(polarParams->K < 129, "K = %d > 64, is not supported yet\n",polarParams->K); + AssertFatal(polarParams->K < 129, "K = %d > 128, is not supported yet\n", polarParams->K); int bit_i,ip; int numbytes = polarParams->K>>3; int residue = polarParams->K&7; diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index adeb186517..d76718d388 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -4153,7 +4153,7 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, 0); } } else { - LOG_D(PHY,"[UE %d] Frame %d, nr_tti_rx %d: No DCIs found\n",ue->Mod_id,frame_rx,nr_tti_rx); + LOG_D(PHY,"[UE %d] Frame %d, nr_tti_rx %d: No DCIs found\n", ue->Mod_id, frame_rx, nr_tti_rx); } #endif //NR_PDCCH_SCHED From 96b57557533366db1a4aad1d202a606c20091467 Mon Sep 17 00:00:00 2001 From: cig Date: Wed, 29 Apr 2020 18:13:31 +0200 Subject: [PATCH 229/553] Cleanup NR UE DCI configuration --- openair2/LAYER2/NR_MAC_UE/mac_proto.h | 2 +- openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c | 4 +--- openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c | 6 ++++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_UE/mac_proto.h b/openair2/LAYER2/NR_MAC_UE/mac_proto.h index b4827e4d60..1516b2a08c 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_proto.h @@ -168,7 +168,7 @@ unsigned char nr_generate_ulsch_pdu(uint8_t *sdus_payload, int8_t nr_ue_process_dlsch(module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_indication_t *dci_ind, void *pduP, uint32_t pdu_len); -void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_config,int frame,int slot); +void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl_config, int slot); void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, int dci_format, diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c index e5db0c28f8..bb2972c46c 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c @@ -61,13 +61,11 @@ void fill_dci_search_candidates(NR_SearchSpace_t *ss,fapi_nr_dl_config_dci_dl_pd } -void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_config,int frame,int slot) { +void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl_config, int slot) { // check if DL slot if (slot == 1 || slot == 7) { - LOG_D(PHY,"Entering UE DCI configuration frame %d slot %d \n", frame, slot); - // get BWP 1, Coreset 0, SearchSpace 0 if (mac->DLbwp[0]==NULL) { AssertFatal(mac->scd->downlinkBWP_ToAddModList!=NULL,"downlinkBWP_ToAddModList is null\n"); diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c index 87ddd97366..3688d095f1 100644 --- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c @@ -312,7 +312,9 @@ int nr_ue_dcireq(nr_dcireq_t *dcireq) { dl_config->sfn=UE_mac->dl_config_request.sfn; dl_config->slot=UE_mac->dl_config_request.slot; dl_config->number_pdus=0; - - ue_dci_configuration(UE_mac,dl_config,dcireq->frame,dcireq->slot); + + LOG_D(PHY, "Entering UE DCI configuration frame %d slot %d \n", dcireq->frame, dcireq->slot); + ue_dci_configuration(UE_mac, dl_config, dcireq->slot); + return 0; } From ad246f961bf40683e14088e6001a6af5cc6c9aaa Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Tue, 12 May 2020 14:14:41 +0200 Subject: [PATCH 230/553] reset rnti and harq_mask in dlsch structure --- openair1/SCHED_NR/fapi_nr_l1.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/openair1/SCHED_NR/fapi_nr_l1.c b/openair1/SCHED_NR/fapi_nr_l1.c index 1576ab9e64..dccb7fab27 100644 --- a/openair1/SCHED_NR/fapi_nr_l1.c +++ b/openair1/SCHED_NR/fapi_nr_l1.c @@ -156,6 +156,10 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){ int pdcch_received=0; gNB->num_pdsch_rnti=0; + for (int i=0; idlsch[i][0]->rnti=0; + gNB->dlsch[i][0]->harq_mask=0; + } gNB->pdcch_pdu = NULL; gNB->pbch_configured=0; From 58dbf7d4b9b0901d0b5a36499021076a80c9e96f Mon Sep 17 00:00:00 2001 From: cig Date: Sun, 3 May 2020 14:38:30 +0200 Subject: [PATCH 231/553] New design UE scheduler --- executables/nr-ue.c | 32 ++-- openair2/LAYER2/NR_MAC_UE/mac_proto.h | 20 +- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 191 ++++++++++--------- openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c | 11 +- openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h | 5 +- 5 files changed, 126 insertions(+), 133 deletions(-) diff --git a/executables/nr-ue.c b/executables/nr-ue.c index fb9d260541..25fe092401 100644 --- a/executables/nr-ue.c +++ b/executables/nr-ue.c @@ -431,32 +431,24 @@ void processSlotTX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { - nr_dcireq_t dcireq; - nr_scheduled_response_t scheduled_response; fapi_nr_config_request_t *cfg = &UE->nrUE_config; int rx_slot_type = nr_ue_slot_select(cfg, proc->frame_rx, proc->nr_tti_rx); - uint8_t ssb_period = UE->nrUE_config.ssb_table.ssb_period; + uint8_t gNB_id = 0; + + nr_downlink_indication_t dl_indication; + memset((void*)&dl_indication, 0, sizeof(dl_indication)); - //program DCI for slot 1 - //TODO: all of this has to be moved to the MAC!!! if (rx_slot_type == NR_DOWNLINK_SLOT || rx_slot_type == NR_MIXED_SLOT){ - dcireq.module_id = UE->Mod_id; - dcireq.gNB_index = 0; - dcireq.cc_id = 0; - dcireq.frame = proc->frame_rx; - dcireq.slot = proc->nr_tti_rx; - nr_ue_dcireq(&dcireq); //to be replaced with function pointer later - // we should have received a DL DCI here, so configure DL accordingly - scheduled_response.dl_config = &dcireq.dl_config_req; - scheduled_response.ul_config = NULL; - scheduled_response.tx_request = NULL; - scheduled_response.module_id = UE->Mod_id; - scheduled_response.CC_id = 0; - scheduled_response.frame = proc->frame_rx; - scheduled_response.slot = proc->nr_tti_rx; + if(UE->if_inst != NULL && UE->if_inst->dl_indication != NULL) { + dl_indication.module_id = UE->Mod_id; + dl_indication.gNB_index = gNB_id; + dl_indication.cc_id = UE->CC_id; + dl_indication.frame = proc->frame_rx; + dl_indication.slot = proc->nr_tti_rx; + } - nr_ue_scheduled_response(&scheduled_response); + nr_ue_scheduler(&dl_indication, NULL); // Process Rx data for one sub-frame #ifdef UE_SLOT_PARALLELISATION diff --git a/openair2/LAYER2/NR_MAC_UE/mac_proto.h b/openair2/LAYER2/NR_MAC_UE/mac_proto.h index 1516b2a08c..7b71c0c00f 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_proto.h @@ -84,23 +84,9 @@ NR_UE_MAC_INST_t *get_mac_inst( /**\brief called at each slot, slot length based on numerology. now use u=0, scs=15kHz, slot=1ms performs BSR/SR/PHR procedures, random access procedure handler and DLSCH/ULSCH procedures. - \param module_id module id - \param gNB_index corresponding gNB index - \param cc_id component carrier id - \param rx_frame receive frame number - \param rx_slot receive slot number - \param tx_frame transmit frame number - \param tx_slot transmit slot number*/ -NR_UE_L2_STATE_t nr_ue_scheduler( - const module_id_t module_id, - const uint8_t gNB_index, - const int cc_id, - const frame_t rx_frame, - const slot_t rx_slot, - const int32_t ssb_index, - const frame_t tx_frame, - const slot_t tx_slot); - + \param dl_info DL indication + \param ul_info UL indication*/ +NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_indication_t *ul_info); /* \brief Get SR payload (0,1) from UE MAC @param Mod_id Instance id of UE in machine diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index c7fadbdafe..1b87c37b55 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -651,99 +651,120 @@ uint32_t get_ssb_frame(uint32_t test){ // 1. TODO: Call RRC for link status return to PHY // 2. TODO: Perform SR/BSR procedures for scheduling feedback // 3. TODO: Perform PHR procedures -NR_UE_L2_STATE_t nr_ue_scheduler(const module_id_t module_id, - const uint8_t gNB_index, - const int cc_id, - const frame_t rx_frame, - const slot_t rx_slot, - const int32_t ssb_index, - const frame_t tx_frame, - const slot_t tx_slot ){ +NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_indication_t *ul_info){ uint32_t search_space_mask = 0; - NR_UE_MAC_INST_t *mac = get_mac_inst(module_id); - fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request; + if (dl_info){ + + module_id_t mod_id = dl_info->module_id; + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + int cc_id = dl_info->cc_id; + fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request; + nr_scheduled_response_t scheduled_response; + nr_dcireq_t dcireq; + frame_t rx_frame = dl_info->frame; + slot_t rx_slot = dl_info->slot; - // check type0 from 38.213 13 if we have no CellGroupConfig - if ( mac->scd == NULL) { - if( ssb_index != -1){ - - if(mac->type0_pdcch_ss_mux_pattern == 1){ - // 38.213 chapter 13 - if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_0) && !(rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){ - search_space_mask = search_space_mask | type0_pdcch; - mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration; - } - if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_1) && (rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){ - search_space_mask = search_space_mask | type0_pdcch; - mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration; - } + // check type0 from 38.213 13 if we have no CellGroupConfig + // TODO: implementation to be completed + if (mac->scd == NULL) { + if(dl_info->ssb_index != -1){ + + if(mac->type0_pdcch_ss_mux_pattern == 1){ + // 38.213 chapter 13 + if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_0) && !(rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){ + search_space_mask = search_space_mask | type0_pdcch; + mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration; + } + if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_1) && (rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){ + search_space_mask = search_space_mask | type0_pdcch; + mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration; + } + } + if(mac->type0_pdcch_ss_mux_pattern == 2){ + // 38.213 Table 13-13, 13-14 + if((rx_frame == get_ssb_frame(rx_frame)) && (rx_slot == mac->type0_pdcch_ss_n_c)){ + search_space_mask = search_space_mask | type0_pdcch; + mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration; + } + } + if(mac->type0_pdcch_ss_mux_pattern == 3){ + // 38.213 Table 13-15 + if((rx_frame == get_ssb_frame(rx_frame)) && (rx_slot == mac->type0_pdcch_ss_n_c)){ + search_space_mask = search_space_mask | type0_pdcch; + mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration; + } + } + } // ssb_index != -1 + + // Type0 PDCCH search space + if((search_space_mask & type0_pdcch) || ( mac->type0_pdcch_consecutive_slots != 0 )){ + mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_consecutive_slots - 1; + + dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15 = mac->type0_pdcch_dci_config; + dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI; + + /* + dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.rnti = 0xaaaa; // to be set + dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP = 106; // to be set + + LOG_I(MAC,"nr_ue_scheduler Type0 PDCCH with rnti %x, BWP %d\n", + dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.rnti, + dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP); + */ + dl_config->number_pdus = dl_config->number_pdus + 1; + mac->scheduled_response.dl_config = dl_config; } - if(mac->type0_pdcch_ss_mux_pattern == 2){ - // 38.213 Table 13-13, 13-14 - if((rx_frame == get_ssb_frame(rx_frame)) && (rx_slot == mac->type0_pdcch_ss_n_c)){ - search_space_mask = search_space_mask | type0_pdcch; - mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration; - } - } - if(mac->type0_pdcch_ss_mux_pattern == 3){ - // 38.213 Table 13-15 - if((rx_frame == get_ssb_frame(rx_frame)) && (rx_slot == mac->type0_pdcch_ss_n_c)){ - search_space_mask = search_space_mask | type0_pdcch; - mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration; - } - } - } // ssb_index != -1 - - // Type0 PDCCH search space - if((search_space_mask & type0_pdcch) || ( mac->type0_pdcch_consecutive_slots != 0 )){ - mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_consecutive_slots - 1; - - dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15 = mac->type0_pdcch_dci_config; - dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI; - + } else { // get PDCCH configuration(s) from SCGConfig + // get Coreset and SearchSpace Information from spCellConfigDedicated + // DCI configuration done for BWP 1, Coreset 0, SearchSpace 0 + + // TBR first thing to do : schedule msg2 + + // TBR program DCI for slot 1 if PDSCH + // TBR program DCI for slot 7 if RAR DCI PDSCH + + dcireq.module_id = mod_id; + dcireq.gNB_index = 0; + dcireq.cc_id = 0; + dcireq.frame = rx_frame; // TBR not needed + dcireq.slot = rx_slot; + nr_ue_dcireq(&dcireq); //to be replaced with function pointer later + + // we should have received a DL DCI here, so configure DL accordingly + scheduled_response.dl_config = &dcireq.dl_config_req; + scheduled_response.ul_config = NULL; + scheduled_response.tx_request = NULL; + scheduled_response.module_id = mod_id; + scheduled_response.CC_id = cc_id; + scheduled_response.frame = rx_frame; + scheduled_response.slot = rx_slot; + + nr_ue_scheduled_response(&scheduled_response); + /* - dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.rnti = 0xaaaa; // to be set - dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP = 106; // to be set - - LOG_I(MAC,"nr_ue_scheduler Type0 PDCCH with rnti %x, BWP %d\n", - dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.rnti, - dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP); - */ - dl_config->number_pdus = dl_config->number_pdus + 1; + if(search_space_mask & type0a_pdcch){ + } + + if(search_space_mask & type1_pdcch){ + } + + if(search_space_mask & type2_pdcch){ + } + + if(search_space_mask & type3_pdcch){ + } + */ } + } else if (ul_info) { + module_id_t mod_id = ul_info->module_id; + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + // TODO: expand + // Note: Contention resolution is currently not active + if (mac->RA_contention_resolution_timer_active == 1) + ue_contention_resolution(mod_id, ul_info->gNB_index, ul_info->cc_id, ul_info->frame_tx); } - else { // get PDCCH configuration(s) from SCGConfig - - - - - // get Coreset and SearchSpace Information from spCellConfigDedicated - - - - /* - if(search_space_mask & type0a_pdcch){ - } - - if(search_space_mask & type1_pdcch){ - } - - if(search_space_mask & type2_pdcch){ - } - - if(search_space_mask & type3_pdcch){ - } - */ - } - - if (mac->RA_contention_resolution_timer_active == 1) { - ue_contention_resolution(module_id, gNB_index, cc_id, tx_frame); - } - - mac->scheduled_response.dl_config = dl_config; - return UE_CONNECTION_OK; } diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c index 3688d095f1..b250f84c7b 100644 --- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c @@ -113,14 +113,7 @@ int nr_ue_ul_indication(nr_uplink_indication_t *ul_info){ mac->dl_config_request.number_pdus = 0; // clean previous FAPI messages - ret = nr_ue_scheduler(ul_info->module_id, - ul_info->gNB_index, - ul_info->cc_id, - ul_info->frame_rx, - ul_info->slot_rx, - ul_info->ssb_index, - ul_info->frame_tx, - ul_info->slot_tx); + ret = nr_ue_scheduler(NULL, ul_info); if (is_nr_UL_slot(mac->scc, ul_info->slot_tx) && get_softmodem_params()->do_ra) nr_ue_prach_scheduler(module_id, ul_info->frame_tx, ul_info->slot_tx); @@ -313,6 +306,8 @@ int nr_ue_dcireq(nr_dcireq_t *dcireq) { dl_config->slot=UE_mac->dl_config_request.slot; dl_config->number_pdus=0; + printf(" UE_mac->dl_config_request.slot %d VS dcireq->slot %d \n", UE_mac->dl_config_request.slot, dcireq->slot); + LOG_D(PHY, "Entering UE DCI configuration frame %d slot %d \n", dcireq->frame, dcireq->slot); ue_dci_configuration(UE_mac, dl_config, dcireq->slot); diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h index b7ddfc0c57..df2d78f0cb 100755 --- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h +++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h @@ -72,7 +72,8 @@ typedef struct { /// NR UE FAPI-like P7 message, direction: L1 to L2 /// data reception indication structure fapi_nr_rx_indication_t *rx_ind; - + /// ssb_index, if ssb is not present in current TTI, value set to -1 + int ssb_index; /// dci reception indication structure fapi_nr_dci_indication_t *dci_ind; @@ -94,8 +95,6 @@ typedef struct { frame_t frame_tx; /// slot tx uint32_t slot_tx; - /// ssb_index, if ssb is not present in current TTI, thie value set to -1 - int ssb_index; /// dci reception indication structure fapi_nr_dci_indication_t *dci_ind; } nr_uplink_indication_t; From 12b585a190f1b89e04f4fef2d24a2bb1fc308aa3 Mon Sep 17 00:00:00 2001 From: cig Date: Sun, 3 May 2020 17:26:49 +0200 Subject: [PATCH 232/553] Fixes to RA procedure --- openair1/PHY/defs_nr_common.h | 2 - openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 33 +++++----- openair2/LAYER2/NR_MAC_UE/mac_defs.h | 2 + openair2/LAYER2/NR_MAC_UE/mac_proto.h | 16 ++--- openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 64 +++++++------------- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 4 ++ openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c | 2 +- 7 files changed, 53 insertions(+), 70 deletions(-) diff --git a/openair1/PHY/defs_nr_common.h b/openair1/PHY/defs_nr_common.h index 6531f582ac..584962c55c 100644 --- a/openair1/PHY/defs_nr_common.h +++ b/openair1/PHY/defs_nr_common.h @@ -221,8 +221,6 @@ typedef struct { uint16_t ra_RNTI; /// Pointer to Msg3 payload for UL-grant uint8_t *Msg3; - /// Flag for the Msg1 generation: it is enabled every time it is nr prach slot - uint8_t generate_nr_prach; /// Frame of last completed synch uint8_t sync_frame; /// Flag to indicate that prach is ready to start: it is enabled with an initial delay after the sync diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index d76718d388..2d09fc7135 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -2269,9 +2269,6 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, if ((ue->UE_mode[gNB_id] == PRACH) && (ue->prach_vars[gNB_id]->prach_Config_enabled == 1)) { nr_ue_prach_procedures(ue, proc, gNB_id, mode); } - else { - ue->prach_resources[gNB_id]->generate_nr_prach = 0; - } } LOG_I(PHY,"****** end TX-Chain for AbsSubframe %d.%d ******\n", frame_tx, slot_tx); @@ -4497,6 +4494,7 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t uint8_t mod_id = ue->Mod_id; UE_MODE_t UE_mode = get_nrUE_mode(mod_id, ue->CC_id, gNB_id); NR_PRACH_RESOURCES_t * prach_resources = ue->prach_resources[gNB_id]; + uint8_t nr_prach; VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_IN); @@ -4505,7 +4503,7 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t prach_resources->ra_TDD_map_index = 0; prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = 10; prach_resources->ra_RNTI = 0x1234; - prach_resources->generate_nr_prach = 1; + nr_prach = 1; } else { // ask L2 for RACH transport if ((runmode != rx_calib_ue) && (runmode != rx_calib_ue_med) && (runmode != rx_calib_ue_byp) && (runmode != no_L2_connect) ) { @@ -4516,16 +4514,17 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t ue->ulsch_Msg3_active[i] = 0; } } - nr_ue_get_rach(ue->prach_resources[gNB_id], mod_id, ue->CC_id, UE_mode, frame_tx, gNB_id, nr_tti_tx); + nr_prach = nr_ue_get_rach(ue->prach_resources[gNB_id], mod_id, ue->CC_id, UE_mode, frame_tx, gNB_id, nr_tti_tx); } } - if (!prach_resources->init_msg1 && (frame_tx > ue->prach_resources[gNB_id]->sync_frame + 150)) - prach_resources->init_msg1 = 1; - - if (ue->prach_resources[gNB_id] != NULL && prach_resources->generate_nr_prach == 1 && prach_resources->init_msg1) { - + if (!prach_resources->init_msg1 && (frame_tx > ue->prach_resources[gNB_id]->sync_frame + 150)){ ue->prach_cnt = 0; + prach_resources->init_msg1 = 1; + } + + if (ue->prach_resources[gNB_id] != NULL && nr_prach == 1 && prach_resources->init_msg1) { + pathloss = get_nr_PL(mod_id, ue->CC_id, gNB_id); LOG_D(PHY,"runmode %d\n",runmode); @@ -4585,18 +4584,18 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t prach_resources->ra_PreambleIndex, ue->tx_power_dBm[nr_tti_tx], pathloss); + + LOG_D(PHY,"[UE %d] frame %d nr_tti_tx %d : prach_cnt %d\n", ue->Mod_id, frame_tx, nr_tti_tx, ue->prach_cnt); + + ue->prach_cnt++; + + if (ue->prach_cnt == 3) + ue->prach_cnt = 0; } // if we're calibrating the PRACH kill the pointer to its resources so that the RA protocol doesn't continue if (runmode == calib_prach_tx) ue->prach_resources[gNB_id] = NULL; - LOG_D(PHY,"[UE %d] frame %d nr_tti_tx %d : generate_nr_prach %d, prach_cnt %d\n", ue->Mod_id, frame_tx, nr_tti_tx, ue->prach_resources[gNB_id]->generate_nr_prach, ue->prach_cnt); - - ue->prach_cnt++; - - if (ue->prach_cnt == 3) - prach_resources->generate_nr_prach = 0; - VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_OUT); } diff --git a/openair2/LAYER2/NR_MAC_UE/mac_defs.h b/openair2/LAYER2/NR_MAC_UE/mac_defs.h index 64dd241499..8da2d29d75 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_defs.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_defs.h @@ -239,6 +239,8 @@ typedef struct { uint8_t RA_RAPID_found; /// Flag to monitor if BI was received in RAR uint8_t RA_BI_found; + /// Flag for the Msg1 generation: enabled at every occurrence of nr prach slot + uint8_t generate_nr_prach; //// FAPI-like interface message fapi_nr_tx_request_t tx_request; diff --git a/openair2/LAYER2/NR_MAC_UE/mac_proto.h b/openair2/LAYER2/NR_MAC_UE/mac_proto.h index 7b71c0c00f..1ba5600dae 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_proto.h @@ -235,14 +235,14 @@ andom-access to transmit a BSR along with the C-RNTI control element (see 5.1.4 @param frame @param gNB_id gNB index @param nr_tti_tx slot for PRACH transmission -@returns void */ -void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, - module_id_t mod_id, - int CC_id, - UE_MODE_t UE_mode, - frame_t frame, - uint8_t gNB_id, - int nr_tti_tx); +@returns indication to generate PRACH to phy */ +uint8_t nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, + module_id_t mod_id, + int CC_id, + UE_MODE_t UE_mode, + frame_t frame, + uint8_t gNB_id, + int nr_tti_tx); /* \brief Function implementing the routine for the selection of Random Access resources (5.1.2 TS 38.321). @param module_idP Index of UE instance diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c index a5e1c72c93..b41b966a82 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -331,19 +331,17 @@ void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint // - retrieve TBS // - add mac_rrc_nr_data_req_ue, etc ... // - add the backoff condition here if we have it from a previous RA reponse which failed (i.e. backoff indicator) -void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, - module_id_t mod_id, - int CC_id, - UE_MODE_t UE_mode, - frame_t frame, - uint8_t gNB_id, - int nr_tti_tx){ +uint8_t nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, + module_id_t mod_id, + int CC_id, + UE_MODE_t UE_mode, + frame_t frame, + uint8_t gNB_id, + int nr_tti_tx){ NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); uint8_t mac_sdus[MAX_NR_ULSCH_PAYLOAD_BYTES]; uint8_t lcid = UL_SCH_LCID_CCCH_MSG3, *payload, ra_ResponseWindow; - uint8_t config_index, mu; - int is_nr_prach_slot; uint16_t size_sdu = 0; unsigned short post_padding; fapi_nr_config_request_t *cfg = &mac->phy_config.config_req; @@ -365,27 +363,6 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, LOG_D(MAC, "nr_ue_get_rach, RA_active value: %d", mac->RA_active); - config_index = rach_ConfigGeneric->prach_ConfigurationIndex; - if (setup->msg1_SubcarrierSpacing) - mu = *setup->msg1_SubcarrierSpacing; - else - mu = frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing; - - is_nr_prach_slot = get_nr_prach_info_from_index(config_index, - (int)frame, - (int)nr_tti_tx, - frequencyInfoDL->absoluteFrequencyPointA, - mu, - cfg->cell_config.frame_duplex_type, - NULL, - NULL, - NULL, - NULL); - if (is_nr_prach_slot) - prach_resources->generate_nr_prach = 1; - else - prach_resources->generate_nr_prach = 0; - AssertFatal(setup != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); if (mac->RA_active == 0) { @@ -393,6 +370,7 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, LOG_I(MAC, "RA not active. Starting RA preamble initialization.\n"); + mac->ra_state = RA_UE_IDLE; mac->RA_RAPID_found = 0; /* Set RA_PREAMBLE_POWER_RAMPING_STEP */ @@ -446,10 +424,10 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, size_sdu += sdu_lengths[0]; } - mac->RA_tx_frame = frame; - mac->RA_tx_subframe = nr_tti_tx; - mac->RA_backoff_frame = frame; - mac->RA_backoff_subframe = nr_tti_tx; + //mac->RA_tx_frame = frame; + //mac->RA_tx_subframe = nr_tti_tx; + //mac->RA_backoff_frame = frame; + //mac->RA_backoff_subframe = nr_tti_tx; if (size_sdu > 0) { @@ -493,7 +471,7 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, } // Fill in preamble and PRACH resources - if (is_nr_prach_slot) + if (mac->generate_nr_prach) nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 1, prach_resources, rach_ConfigDedicated); offset = nr_generate_ulsch_pdu((uint8_t *) mac_sdus, // sdus buffer @@ -528,18 +506,20 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, // - handle backoff and raResponseWindow params // - disabled contention resolution as OAI NSA is contention-free based - LOG_D(MAC, "[MAC][UE %d][RAPROC] frame %d, subframe %d: RA Active, window cnt %d (RA_tx_frame %d, RA_tx_subframe %d)\n", - mod_id, frame, nr_tti_tx, mac->RA_window_cnt, mac->RA_tx_frame, mac->RA_tx_subframe); + // LOG_D(MAC, "[MAC][UE %d][RAPROC] frame %d, subframe %d: RA Active, window cnt %d (RA_tx_frame %d, RA_tx_subframe %d)\n", + // mod_id, frame, nr_tti_tx, mac->RA_window_cnt, mac->RA_tx_frame, mac->RA_tx_subframe); if (mac->RA_BI_found){ - prach_resources->RA_PREAMBLE_BACKOFF = prach_resources->RA_SCALING_FACTOR_BI * mac->RA_backoff_indicator; + prach_resources->RA_PREAMBLE_BACKOFF = prach_resources->RA_SCALING_FACTOR_BI * mac->RA_backoff_indicator; } else { prach_resources->RA_PREAMBLE_BACKOFF = 0; } if (mac->RA_window_cnt > 0 && mac->RA_RAPID_found == 1) { // mac->ra_state = WAIT_CONTENTION_RESOLUTION; + LOG_I(MAC, "[MAC][UE %d][RAPROC] Frame %d: subframe %d: RAR successfully received \n", mod_id, frame, nr_tti_tx); } else { + mac->ra_state = RA_UE_IDLE; LOG_I(MAC, "[MAC][UE %d][RAPROC] Frame %d: subframe %d: RAR reception not successful, (RA window count %d) \n", mod_id, frame, @@ -608,11 +588,11 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, // LOG_D(MAC, "[MAC][UE %d][RAPROC] Frame %d, subframe %d: RA Active, adjusted window cnt %d\n", mod_id, frame, nr_tti_tx, mac->RA_window_cnt); // } - mac->RA_tx_frame = frame; - mac->RA_tx_subframe = nr_tti_tx; + // mac->RA_tx_frame = frame; + // mac->RA_tx_subframe = nr_tti_tx; // Fill in preamble and PRACH resources - if (is_nr_prach_slot) + if (mac->generate_nr_prach) nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 0, prach_resources, rach_ConfigDedicated); } @@ -621,5 +601,5 @@ void nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, LOG_D(MAC, "[UE %d] FATAL: Should not have checked for RACH in PUSCH yet ...", mod_id); AssertFatal(1 == 0, ""); } - return; + return mac->generate_nr_prach; } diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 1b87c37b55..50ea64c724 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -813,6 +813,8 @@ void nr_ue_prach_scheduler(module_id_t module_idP, frame_t frameP, sub_frame_t s &N_dur); if (is_nr_prach_slot) { + mac->generate_nr_prach = 1; + fdm = rach_ConfigGeneric->msg1_FDM; switch (fdm){ @@ -911,6 +913,8 @@ void nr_ue_prach_scheduler(module_id_t module_idP, frame_t frameP, sub_frame_t s } } } + } else { + mac->generate_nr_prach = 0; } mac->scheduled_response.ul_config = ul_config; } diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c index b250f84c7b..4cda82366c 100644 --- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c @@ -115,7 +115,7 @@ int nr_ue_ul_indication(nr_uplink_indication_t *ul_info){ ret = nr_ue_scheduler(NULL, ul_info); - if (is_nr_UL_slot(mac->scc, ul_info->slot_tx) && get_softmodem_params()->do_ra) + if (is_nr_UL_slot(mac->scc, ul_info->slot_tx) && mac->ra_state <= WAIT_RAR && get_softmodem_params()->do_ra) nr_ue_prach_scheduler(module_id, ul_info->frame_tx, ul_info->slot_tx); switch(ret){ From 08b6211956680d58de451737b096a69a4aac06b6 Mon Sep 17 00:00:00 2001 From: cig Date: Mon, 4 May 2020 17:16:18 +0200 Subject: [PATCH 233/553] Scheduling of Msg2 --- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 74 ++++++++++++- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h | 4 + openair2/LAYER2/NR_MAC_UE/mac_defs.h | 4 + openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 100 +++++++++++++++++- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 2 +- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 75 ------------- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 4 - openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c | 10 +- 8 files changed, 189 insertions(+), 84 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index baab2f5809..95690e19e3 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -47,6 +47,8 @@ uint16_t NCS_unrestricted_delta_f_RA_15[16] = {0,2,4,6,8,10,12,13,15,17,19,23,27 const char *prachfmt[]={"A1","A2","A3","B1","B2","B3","B4","C0","C2"}; +const uint16_t nr_slots_per_frame[5] = {10, 20, 40, 80, 160}; + uint16_t get_NCS(uint8_t index, uint16_t format0, uint8_t restricted_set_config) { if (format0 < 3) { @@ -876,7 +878,77 @@ int get_format0(uint8_t index, return format; } - + +void find_monitoring_periodicity_offset_common(NR_SearchSpace_t *ss, + uint16_t *slot_period, + uint16_t *offset) { + + switch(ss->monitoringSlotPeriodicityAndOffset->present) { + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1: + *slot_period = 1; + *offset = 0; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl2: + *slot_period = 2; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl2; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl4: + *slot_period = 4; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl4; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl5: + *slot_period = 5; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl5; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl8: + *slot_period = 8; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl8; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl10: + *slot_period = 10; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl10; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl16: + *slot_period = 16; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl16; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl20: + *slot_period = 20; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl20; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl40: + *slot_period = 40; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl40; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl80: + *slot_period = 80; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl80; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl160: + *slot_period = 160; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl160; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl320: + *slot_period = 320; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl320; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl640: + *slot_period = 640; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl640; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1280: + *slot_period = 1280; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl1280; + break; + case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl2560: + *slot_period = 2560; + *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl2560; + break; + default: + AssertFatal(1==0,"Invalid monitoring slot periodicity and offset value\n"); + break; + } +} int get_nr_prach_info_from_index(uint8_t index, int frame, diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h index a3114886ba..8f5ee85160 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h @@ -78,6 +78,10 @@ int is_nr_UL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP); uint16_t nr_dci_size(nr_dci_format_t format, nr_rnti_type_t rnti_type, uint16_t N_RB); +void find_monitoring_periodicity_offset_common(NR_SearchSpace_t *ss, + uint16_t *slot_period, + uint16_t *offset); + int get_nr_prach_info_from_index(uint8_t index, int frame, int slot, diff --git a/openair2/LAYER2/NR_MAC_UE/mac_defs.h b/openair2/LAYER2/NR_MAC_UE/mac_defs.h index 8da2d29d75..368eae9682 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_defs.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_defs.h @@ -220,6 +220,10 @@ typedef struct { uint32_t RA_tx_frame; /// Random-access variable for window calculation (subframe of last change in window counter) uint8_t RA_tx_subframe; + /// Scheduled RX frame for RA Msg2 + uint16_t msg2_rx_frame; + /// Scheduled RX slot for RA Msg2 + uint16_t msg2_rx_slot; /// Random-access Group B maximum path-loss /// Random-access variable for backoff (frame of last change in backoff counter) uint32_t RA_backoff_frame; diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 50ea64c724..c33a469a84 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -42,6 +42,7 @@ #include "NR_RACH-ConfigCommon.h" #include "NR_RACH-ConfigGeneric.h" #include "NR_FrequencyInfoDL.h" +#include "NR_PDCCH-ConfigCommon.h" /* MAC */ #include "mac_defs.h" @@ -73,6 +74,8 @@ //#define ENABLE_MAC_PAYLOAD_DEBUG 1 #define DEBUG_EXTRACT_DCI 1 +extern const uint16_t nr_slots_per_frame[5]; + extern void mac_rlc_data_ind ( const module_id_t module_idP, const rnti_t rntiP, @@ -720,8 +723,6 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in // get Coreset and SearchSpace Information from spCellConfigDedicated // DCI configuration done for BWP 1, Coreset 0, SearchSpace 0 - // TBR first thing to do : schedule msg2 - // TBR program DCI for slot 1 if PDSCH // TBR program DCI for slot 7 if RAR DCI PDSCH @@ -769,6 +770,101 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in return UE_CONNECTION_OK; } +// Note: msg2 is scheduled in the mixed slot or in the last dl slot +// if they are allowed by search space configuration +void nr_ue_msg2_scheduler(module_id_t mod_id, + uint16_t rach_frame, + uint16_t rach_slot, + uint16_t *msg2_frame, + uint16_t *msg2_slot){ + + uint8_t bwp_id = 1; + NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + NR_ServingCellConfig_t *scd = mac->scd; + NR_ServingCellConfigCommon_t *scc = mac->scc; + NR_BWP_Downlink_t *bwp = scd->downlinkBWP_ToAddModList->list.array[bwp_id - 1]; + NR_SearchSpace_t *ss; + struct NR_PDCCH_ConfigCommon__commonSearchSpaceList *commonSearchSpaceList = bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList; + uint8_t mu = *scc->ssbSubcarrierSpacing; + uint8_t response_window = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.ra_ResponseWindow; + uint8_t slot_window, slot_limit, frame_limit; + uint16_t start_next_period, monitoring_slot_period, monitoring_offset; + + // number of mixed slot or of last dl slot if there is no mixed slot + uint16_t last_dl_slot_period = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots; + uint16_t nr_dl_symbols = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSymbols; + uint16_t nr_ul_symbols = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols; + + // lenght of tdd period in slots + uint16_t tdd_period_slot = last_dl_slot_period + scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots; + + AssertFatal(commonSearchSpaceList->list.count > 0, "PDCCH common SearchSpace list has 0 elements\n"); + + LOG_D(MAC, "Frame %d, Slot %d: Scheduling Msg2 reception \n", rach_frame, rach_slot); + + // Common searchspace list + for (int i = 0; i < commonSearchSpaceList->list.count; i++) { + ss = commonSearchSpaceList->list.array[i]; + if(ss->searchSpaceId == *bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace) + // retrieving ra pdcch monitoring period and offset + find_monitoring_periodicity_offset_common(ss, &monitoring_slot_period, &monitoring_offset); + } + + if (nr_dl_symbols == 0) + last_dl_slot_period--; + if ((nr_dl_symbols > 0) || (nr_ul_symbols > 0)) + tdd_period_slot++; + + // computing start of next period + start_next_period = (rach_slot - (rach_slot % tdd_period_slot) + tdd_period_slot) % nr_slots_per_frame[mu]; + *msg2_slot = start_next_period + last_dl_slot_period; // initializing scheduling of slot to next mixed (or last dl) slot + *msg2_frame = (*msg2_slot > rach_slot) ? rach_frame : (rach_frame +1); + + switch(response_window){ + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl1: + slot_window = 1; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl2: + slot_window = 2; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl4: + slot_window = 4; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl8: + slot_window = 8; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl10: + slot_window = 10; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl20: + slot_window = 20; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl40: + slot_window = 40; + break; + case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl80: + slot_window = 80; + break; + default: + AssertFatal(1==0,"Invalid response window value %d\n",response_window); + } + AssertFatal(slot_window<=nr_slots_per_frame[mu], "Msg2 response window needs to be lower or equal to 10ms"); + + // slot and frame limit to transmit msg2 according to response window + slot_limit = (rach_slot + slot_window)%nr_slots_per_frame[mu]; + frame_limit = (slot_limit>(rach_slot))? rach_frame : (rach_frame +1); + + // go to previous slot if the current scheduled slot is beyond the response window + // and if the slot is not among the PDCCH monitored ones (38.213 10.1) + while ((*msg2_slot > slot_limit) || ((*msg2_frame*nr_slots_per_frame[mu] + *msg2_slot - monitoring_offset) % monitoring_slot_period != 0)) { + if((*msg2_slot % tdd_period_slot) > 0) + *msg2_slot--; + else + AssertFatal(1 == 0, "No available DL slot to schedule reception of msg2 has been found"); + } + LOG_D(MAC, "Scheduled Msg2 reception in Frame %d, Slot %d: \n", *msg2_frame, *msg2_slot); +} + // This function schedules the PRACH according to prach_ConfigurationIndex and TS 38.211, tables 6.3.3.2.x // It fills the PRACH PDU per each FD occasion. // PRACH formats 9, 10, 11 are corresponding to dual PRACH format configurations A1/B1, A2/B2, A3/B3. diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index 56c3d27210..719571e29c 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -42,7 +42,7 @@ #include "SIMULATION/TOOLS/sim.h" // for taus extern RAN_CONTEXT_t RC; -uint16_t nr_slots_per_frame[5] = {10, 20, 40, 80, 160}; +extern const uint16_t nr_slots_per_frame[5]; uint8_t DELTA[4]= {2,3,4,6}; void schedule_nr_prach(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) { diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 5575f05e1f..fb0a53b4ce 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -998,81 +998,6 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){ return -1; } - -void find_monitoring_periodicity_offset_common(NR_SearchSpace_t *ss, - uint16_t *slot_period, - uint16_t *offset) { - - - switch(ss->monitoringSlotPeriodicityAndOffset->present) { - case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1: - *slot_period = 1; - *offset = 0; - break; - case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl2: - *slot_period = 2; - *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl2; - break; - case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl4: - *slot_period = 4; - *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl4; - break; - case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl5: - *slot_period = 5; - *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl5; - break; - case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl8: - *slot_period = 8; - *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl8; - break; - case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl10: - *slot_period = 10; - *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl10; - break; - case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl16: - *slot_period = 16; - *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl16; - break; - case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl20: - *slot_period = 20; - *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl20; - break; - case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl40: - *slot_period = 40; - *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl40; - break; - case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl80: - *slot_period = 80; - *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl80; - break; - case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl160: - *slot_period = 160; - *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl160; - break; - case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl320: - *slot_period = 320; - *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl320; - break; - case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl640: - *slot_period = 640; - *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl640; - break; - case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1280: - *slot_period = 1280; - *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl1280; - break; - case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl2560: - *slot_period = 2560; - *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl2560; - break; - default: - AssertFatal(1==0,"Invalid monitoring slot periodicity and offset value\n"); - break; - } -} - - - /*void fill_nfapi_coresets_and_searchspaces(NR_CellGroupConfig_t *cg, nfapi_nr_coreset_t *coreset, nfapi_nr_search_space_t *search_space) { diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index e3ce305180..37f06e143a 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -245,10 +245,6 @@ void nr_schedule_reception_msg3(module_id_t module_idP, int CC_id, frame_t frame int find_aggregation_level (NR_SearchSpace_t *ss); -void find_monitoring_periodicity_offset_common(NR_SearchSpace_t *ss, - uint16_t *slot_period, - uint16_t *offset); - void nr_process_mac_pdu( module_id_t module_idP, uint8_t CC_id, diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c index 4cda82366c..3fba88c984 100644 --- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c @@ -115,8 +115,16 @@ int nr_ue_ul_indication(nr_uplink_indication_t *ul_info){ ret = nr_ue_scheduler(NULL, ul_info); - if (is_nr_UL_slot(mac->scc, ul_info->slot_tx) && mac->ra_state <= WAIT_RAR && get_softmodem_params()->do_ra) + if (is_nr_UL_slot(mac->scc, ul_info->slot_tx) && mac->ra_state == RA_UE_IDLE && get_softmodem_params()->do_ra){ nr_ue_prach_scheduler(module_id, ul_info->frame_tx, ul_info->slot_tx); + if (mac->generate_nr_prach){ + uint16_t monitoring_slot_period, monitoring_offset; + uint16_t rach_frame = mac->scheduled_response.ul_config->sfn; + uint16_t rx_rach_frame = (rach_frame + 2) % MAX_FRAME_NUMBER; // compensate 2 frames offset delay at gNB side + uint16_t rach_slot = mac->scheduled_response.ul_config->slot; + nr_ue_msg2_scheduler(module_id, rx_rach_frame, rach_slot, &mac->msg2_rx_frame, &mac->msg2_rx_slot); + } + } switch(ret){ case UE_CONNECTION_OK: From 8394ee82f5fe67c2e56afbeb428ff0e82a6953f4 Mon Sep 17 00:00:00 2001 From: cig Date: Thu, 7 May 2020 11:54:20 +0200 Subject: [PATCH 234/553] More dynamic DCI configuration --- openair2/LAYER2/NR_MAC_UE/mac_proto.h | 2 +- .../NR_MAC_UE/nr_ue_dci_configuration.c | 314 +++++++++++------- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 19 +- openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c | 3 +- 4 files changed, 207 insertions(+), 131 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_UE/mac_proto.h b/openair2/LAYER2/NR_MAC_UE/mac_proto.h index 1ba5600dae..2d49cc0d76 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_proto.h @@ -154,7 +154,7 @@ unsigned char nr_generate_ulsch_pdu(uint8_t *sdus_payload, int8_t nr_ue_process_dlsch(module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_indication_t *dci_ind, void *pduP, uint32_t pdu_len); -void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl_config, int slot); +void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl_config, frame_t frame, int slot); void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, int dci_format, diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c index bb2972c46c..bbae5a5cf4 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c @@ -21,11 +21,11 @@ /* \file nr_ue_dci_configuration.c * \brief functions for generating dci search procedures based on RRC Serving Cell Group Configuration - * \author R. Knopp + * \author R. Knopp, G. Casati * \date 2020 - * \version 0.1 - * \company Eurecom - * \email: knopp@eurecom.fr + * \version 0.2 + * \company Eurecom, Fraunhofer IIS + * \email: knopp@eurecom.fr, guido.casati@iis.fraunhofer.de * \note * \warning */ @@ -61,134 +61,212 @@ void fill_dci_search_candidates(NR_SearchSpace_t *ss,fapi_nr_dl_config_dci_dl_pd } -void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl_config, int slot) { +void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl_config, frame_t frame, int slot) { - // check if DL slot - if (slot == 1 || slot == 7) { + NR_ServingCellConfig_t *scd = mac->scd; + NR_BWP_Downlink_t *bwp; + NR_BWP_DownlinkCommon_t *bwp_Common; + NR_BWP_DownlinkDedicated_t *dl_bwp_Dedicated; + NR_SetupRelease_PDCCH_Config_t *pdcch_Config; + NR_SetupRelease_PDCCH_ConfigCommon_t *pdcch_ConfigCommon; + struct NR_PDCCH_Config__controlResourceSetToAddModList *controlResourceSetToAddModList; + struct NR_PDCCH_Config__searchSpacesToAddModList *searchSpacesToAddModList; + struct NR_UplinkConfig__uplinkBWP_ToAddModList *uplinkBWP_ToAddModList; + NR_SearchSpace_t *NR_SearchSpace; + NR_ControlResourceSet_t *coreset; - // get BWP 1, Coreset 0, SearchSpace 0 - if (mac->DLbwp[0]==NULL) { - AssertFatal(mac->scd->downlinkBWP_ToAddModList!=NULL,"downlinkBWP_ToAddModList is null\n"); - AssertFatal(mac->scd->downlinkBWP_ToAddModList->list.count==1,"downlinkBWP_ToAddModList->list->count is %d\n", - mac->scd->downlinkBWP_ToAddModList->list.count); - mac->DLbwp[0] = mac->scd->downlinkBWP_ToAddModList->list.array[0]; - AssertFatal(mac->DLbwp[0]->bwp_Dedicated!=NULL,"bwp_Dedicated is null\n"); - AssertFatal(mac->DLbwp[0]->bwp_Dedicated->pdcch_Config!=NULL,"pdcch_Config is null\n"); - AssertFatal(mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList!=NULL,"controlResourceSetToAddModList is null\n"); - AssertFatal(mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.count==1,"controlResourceSetToAddModList->list.count=%d\n", - mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.count); - mac->coreset[0][0] = mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[0]; - AssertFatal(mac->coreset[0][0]!=NULL,"coreset[0][0] is null\n"); - - AssertFatal(mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n"); - AssertFatal(mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0, - "searchPsacesToAddModList is empty\n"); - NR_SearchSpace_t *ss; - int ss_id=0; - AssertFatal(mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.countDLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count); - for (int i=0;iDLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count;i++) { - ss=mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[i]; - AssertFatal(ss->controlResourceSetId != NULL,"ss->controlResourceSetId is null\n"); - AssertFatal(ss->searchSpaceType != NULL,"ss->searchSpaceType is null\n"); - AssertFatal(*ss->controlResourceSetId == mac->coreset[0][0]->controlResourceSetId,"ss->controlResourceSetId is unknown\n"); - mac->SSpace[0][0][ss_id] = ss; - ss_id++; - } - } - if (mac->ULbwp[0]==NULL) { - AssertFatal(mac->scd->uplinkConfig->uplinkBWP_ToAddModList!=NULL,"uplinkBWP_ToAddModList is null\n"); - AssertFatal(mac->scd->uplinkConfig->uplinkBWP_ToAddModList->list.count==1,"uplinkBWP_ToAddModList->list->count is %d\n", - mac->scd->uplinkConfig->uplinkBWP_ToAddModList->list.count); - mac->ULbwp[0] = mac->scd->uplinkConfig->uplinkBWP_ToAddModList->list.array[0]; - AssertFatal(mac->ULbwp[0]->bwp_Dedicated!=NULL,"bwp_Dedicated is null\n"); - } - // check search spaces + fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15; - int ss_id=0; - fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15; - int sps =mac->DLbwp[0]->bwp_Common->genericParameters.cyclicPrefix == NULL ? 14 : 12; + uint8_t bwp_id = 1; + int ss_id, sps; + + // get PDCCH configuration(s) (Coreset, SearchSpace, etc...) from BWP Dedicated in serving cell config dedicated (scd) + // get BWP 1, Coreset ID 0, SearchSpace ID 0 (i.e. configured in MIB and in ServingCellConfigCommon) + + // Check dedicated DL BWP + if (mac->DLbwp[0] == NULL) { + NR_SearchSpace_t *ss; + int ss_id = 0; + + AssertFatal(scd->downlinkBWP_ToAddModList != NULL, "downlinkBWP_ToAddModList is null\n"); + AssertFatal(scd->downlinkBWP_ToAddModList->list.count == 1, "downlinkBWP_ToAddModList->list->count is %d\n", scd->downlinkBWP_ToAddModList->list.count); + mac->DLbwp[0] = scd->downlinkBWP_ToAddModList->list.array[bwp_id - 1]; + + dl_bwp_Dedicated = mac->DLbwp[0]->bwp_Dedicated; + AssertFatal(dl_bwp_Dedicated != NULL, "dl_bwp_Dedicated is null\n"); + + bwp_Common = mac->DLbwp[0]->bwp_Common; + AssertFatal(bwp_Common != NULL, "bwp_Common is null\n"); + + pdcch_Config = dl_bwp_Dedicated->pdcch_Config; + AssertFatal(pdcch_Config != NULL, "pdcch_Config is null\n"); + + pdcch_ConfigCommon = bwp_Common->pdcch_ConfigCommon; + AssertFatal(pdcch_ConfigCommon != NULL, "pdcch_ConfigCommon is null\n"); + AssertFatal(pdcch_ConfigCommon->choice.setup->ra_SearchSpace != NULL, "ra_SearchSpace must be available in DL BWP\n"); + + controlResourceSetToAddModList = pdcch_Config->choice.setup->controlResourceSetToAddModList; + AssertFatal(controlResourceSetToAddModList != NULL, "controlResourceSetToAddModList is null\n"); + + AssertFatal(controlResourceSetToAddModList->list.count == 1, "controlResourceSetToAddModList->list.count=%d\n", controlResourceSetToAddModList->list.count); + + mac->coreset[0][0] = controlResourceSetToAddModList->list.array[0]; + coreset = mac->coreset[0][0]; + AssertFatal(coreset != NULL, "coreset[0][0] is null\n"); - while(mac->SSpace[0][0][ss_id]!=NULL && - ss_id < mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count) { - - AssertFatal(mac->SSpace[0][0][ss_id]->monitoringSymbolsWithinSlot!=NULL,"ss->monitoringSymbolsWithinSlot is null\n"); - AssertFatal(mac->SSpace[0][0][ss_id]->monitoringSymbolsWithinSlot->buf!=NULL,"ss->monitoringSymbolsWithinSlot->buf is null\n"); - + searchSpacesToAddModList = pdcch_Config->choice.setup->searchSpacesToAddModList; + AssertFatal(searchSpacesToAddModList != NULL, "searchSpacesToAddModList is null\n"); + AssertFatal(searchSpacesToAddModList->list.count > 0, "searchSpacesToAddModList is empty\n"); + AssertFatal(searchSpacesToAddModList->list.count < FAPI_NR_MAX_SS_PER_CORESET, "too many searchpaces per coreset %d\n", searchSpacesToAddModList->list.count); + + for (int i = 0; i < searchSpacesToAddModList->list.count; i++) { + ss = searchSpacesToAddModList->list.array[i]; + AssertFatal(ss->controlResourceSetId != NULL, "ss->controlResourceSetId is null\n"); + AssertFatal(ss->searchSpaceType != NULL, "ss->searchSpaceType is null\n"); + AssertFatal(*ss->controlResourceSetId == coreset->controlResourceSetId, "ss->controlResourceSetId is unknown\n"); + mac->SSpace[0][0][ss_id] = ss; ss_id++; } - if (mac->ra_state == WAIT_RAR) { - // check for RAR - rel15 = &dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15; - // rel15->rnti = 2;//get_RA_RNTI(mac,frame,slot); // WIP + } + + // Check dedicated UL BWP + if (mac->ULbwp[0] == NULL) { + uplinkBWP_ToAddModList = scd->uplinkConfig->uplinkBWP_ToAddModList; + AssertFatal(uplinkBWP_ToAddModList != NULL, "uplinkBWP_ToAddModList is null\n"); + AssertFatal(uplinkBWP_ToAddModList->list.count == 1, "uplinkBWP_ToAddModList->list->count is %d\n", uplinkBWP_ToAddModList->list.count); + mac->ULbwp[0] = uplinkBWP_ToAddModList->list.array[bwp_id - 1]; + AssertFatal(mac->ULbwp[0]->bwp_Dedicated != NULL, "UL bwp_Dedicated is null\n"); + } + + bwp = mac->DLbwp[0]; + bwp_Common = bwp->bwp_Common; + pdcch_ConfigCommon = bwp_Common->pdcch_ConfigCommon; + dl_bwp_Dedicated = bwp->bwp_Dedicated; + pdcch_Config = dl_bwp_Dedicated->pdcch_Config; + searchSpacesToAddModList = pdcch_Config->choice.setup->searchSpacesToAddModList; + + // check USSs + ss_id = 0; + NR_SearchSpace = mac->SSpace[0][0][ss_id]; + while(NR_SearchSpace != NULL && ss_id < searchSpacesToAddModList->list.count) { + AssertFatal(NR_SearchSpace->monitoringSymbolsWithinSlot != NULL, "NR_SearchSpace->monitoringSymbolsWithinSlot is null\n"); + AssertFatal(NR_SearchSpace->monitoringSymbolsWithinSlot->buf != NULL, "NR_SearchSpace->monitoringSymbolsWithinSlot->buf is null\n"); + ss_id++; + } + + if (mac->crnti > 0) { + + NR_SearchSpace_t *css; + NR_SearchSpace_t *uss; + NR_ServingCellConfigCommon_t *scc; + NR_SearchSpaceId_t ra_SearchSpaceId; + rel15 = &dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15; + uint16_t monitoringSymbolsWithinSlot; + uint8_t add_dci = 1; + + AssertFatal(mac->scc != NULL, "scc is null\n"); + + scc = mac->scc; + rel15->dci_format = NR_DL_DCI_FORMAT_1_0; + + // CoReSet configuration + coreset = mac->coreset[0][0]; + rel15->coreset.duration = coreset->duration; + for (int i = 0; i < 6; i++) + rel15->coreset.frequency_domain_resource[i] = coreset->frequencyDomainResources.buf[i]; + + rel15->coreset.CceRegMappingType = coreset->cce_REG_MappingType.present == NR_ControlResourceSet__cce_REG_MappingType_PR_interleaved ? FAPI_NR_CCE_REG_MAPPING_TYPE_INTERLEAVED : FAPI_NR_CCE_REG_MAPPING_TYPE_NON_INTERLEAVED; + + if (rel15->coreset.CceRegMappingType == FAPI_NR_CCE_REG_MAPPING_TYPE_INTERLEAVED) { + struct NR_ControlResourceSet__cce_REG_MappingType__interleaved *interleaved = coreset->cce_REG_MappingType.choice.interleaved; + rel15->coreset.RegBundleSize = (interleaved->reg_BundleSize == NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n6) ? 6 : (2 + interleaved->reg_BundleSize); + rel15->coreset.InterleaverSize = (interleaved->interleaverSize == NR_ControlResourceSet__cce_REG_MappingType__interleaved__interleaverSize_n6) ? 6 : (2 + interleaved->interleaverSize); + AssertFatal(scc->physCellId != NULL, "mac->scc->physCellId is null\n"); + rel15->coreset.ShiftIndex = interleaved->shiftIndex != NULL ? *interleaved->shiftIndex : *scc->physCellId; + } else { + rel15->coreset.RegBundleSize = 0; + rel15->coreset.InterleaverSize = 0; + rel15->coreset.ShiftIndex = 0; } - else if (mac->ra_state == WAIT_CONTENTION_RESOLUTION) { - rel15 = &dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15; - rel15->rnti = mac->t_crnti; - //dl_config->number_pdus = dl_config->number_pdus + 1; + + rel15->coreset.CoreSetType = 1; + rel15->coreset.precoder_granularity = coreset->precoderGranularity; + + // Scrambling RNTI + if (coreset->pdcch_DMRS_ScramblingID) { + rel15->coreset.pdcch_dmrs_scrambling_id = *coreset->pdcch_DMRS_ScramblingID; + rel15->coreset.scrambling_rnti = mac->t_crnti; + } else { + rel15->coreset.pdcch_dmrs_scrambling_id = *scc->physCellId; + rel15->coreset.scrambling_rnti = 0; } - if (mac->crnti>0) { - rel15 = &dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15; - rel15->dci_format = NR_DL_DCI_FORMAT_1_0; - if (slot == 0 || slot == 1){ - rel15->BWPSize = NRRIV2BW(mac->DLbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275); - rel15->dci_length = nr_dci_size(rel15->dci_format, NR_RNTI_C, rel15->BWPSize); - } else if (slot == 7){ - rel15->BWPSize = NRRIV2BW(mac->scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, 275); - rel15->dci_length = nr_dci_size(rel15->dci_format, NR_RNTI_RA, rel15->BWPSize); - } + if (mac->ra_state == WAIT_RAR){ - rel15->BWPStart = NRRIV2PRBOFFSET(mac->DLbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275); - rel15->SubcarrierSpacing = mac->DLbwp[0]->bwp_Common->genericParameters.subcarrierSpacing; - // get UE-specific search space - for (ss_id=0;ss_idSSpace[0][0][ss_id]!=NULL;ss_id++) - if (mac->SSpace[0][0][ss_id]->searchSpaceType->present == NR_SearchSpace__searchSpaceType_PR_ue_Specific) break; - AssertFatal(ss_idSSpace[0][0][ss_id]->monitoringSymbolsWithinSlot->buf[0]<<(sps-8)) | - (mac->SSpace[0][0][ss_id]->monitoringSymbolsWithinSlot->buf[1]>>(16-sps)); - - for (int i=0; i>(sps-1-i))&1) { - rel15->coreset.StartSymbolIndex=i; - break; - } - rel15->coreset.duration = mac->coreset[0][0]->duration; - for (int i=0;i<6;i++) - rel15->coreset.frequency_domain_resource[i] = mac->coreset[0][0]->frequencyDomainResources.buf[i]; - - rel15->coreset.CceRegMappingType = mac->coreset[0][0]->cce_REG_MappingType.present == NR_ControlResourceSet__cce_REG_MappingType_PR_interleaved? - FAPI_NR_CCE_REG_MAPPING_TYPE_INTERLEAVED : FAPI_NR_CCE_REG_MAPPING_TYPE_NON_INTERLEAVED; - if (rel15->coreset.CceRegMappingType == FAPI_NR_CCE_REG_MAPPING_TYPE_INTERLEAVED) { - rel15->coreset.RegBundleSize = (mac->coreset[0][0]->cce_REG_MappingType.choice.interleaved->reg_BundleSize == NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n6) ? 6 : (2+mac->coreset[0][0]->cce_REG_MappingType.choice.interleaved->reg_BundleSize); - rel15->coreset.InterleaverSize = (mac->coreset[0][0]->cce_REG_MappingType.choice.interleaved->interleaverSize==NR_ControlResourceSet__cce_REG_MappingType__interleaved__interleaverSize_n6) ? 6 : (2+mac->coreset[0][0]->cce_REG_MappingType.choice.interleaved->interleaverSize); - AssertFatal(mac->scc->physCellId != NULL,"mac->scc->physCellId is null\n"); - rel15->coreset.ShiftIndex = mac->coreset[0][0]->cce_REG_MappingType.choice.interleaved->shiftIndex != NULL ? *mac->coreset[0][0]->cce_REG_MappingType.choice.interleaved->shiftIndex : *mac->scc->physCellId; - } - else { - rel15->coreset.RegBundleSize = 0; - rel15->coreset.InterleaverSize = 0; - rel15->coreset.ShiftIndex = 0; - } - rel15->coreset.CoreSetType = 1; - rel15->coreset.precoder_granularity = mac->coreset[0][0]->precoderGranularity; + NR_BWP_DownlinkCommon_t *initialDownlinkBWP = scc->downlinkConfigCommon->initialDownlinkBWP; + struct NR_PDCCH_ConfigCommon__commonSearchSpaceList *commonSearchSpaceList = pdcch_ConfigCommon->choice.setup->commonSearchSpaceList; + AssertFatal(commonSearchSpaceList->list.count > 0, "PDCCH CSS list has 0 elements\n"); - if (mac->coreset[0][0]->pdcch_DMRS_ScramblingID) { - rel15->coreset.pdcch_dmrs_scrambling_id = *mac->coreset[0][0]->pdcch_DMRS_ScramblingID; - rel15->coreset.scrambling_rnti = mac->t_crnti; - } else { - rel15->coreset.pdcch_dmrs_scrambling_id = *mac->scc->physCellId; - rel15->coreset.scrambling_rnti = 0; - } + ra_SearchSpaceId = *pdcch_ConfigCommon->choice.setup->ra_SearchSpace; - if (get_softmodem_params()->do_ra && slot == 7) + // fetch the CSS for RA from the CSS list + for (int i = 0; i < commonSearchSpaceList->list.count; i++) { + css = commonSearchSpaceList->list.array[i]; + if(css->searchSpaceId == ra_SearchSpaceId) + break; + } + + // check CSSs + if(css != NULL) { + AssertFatal(css->monitoringSymbolsWithinSlot != NULL, "css->monitoringSymbolsWithinSlot is null\n"); + AssertFatal(css->monitoringSymbolsWithinSlot->buf != NULL, "css->monitoringSymbolsWithinSlot->buf is null\n"); + } + + if (frame == mac->msg2_rx_frame && slot == mac->msg2_rx_slot){ + sps = initialDownlinkBWP->genericParameters.cyclicPrefix == NULL ? 14 : 12; + monitoringSymbolsWithinSlot = (css->monitoringSymbolsWithinSlot->buf[0]<<(sps-8)) | (css->monitoringSymbolsWithinSlot->buf[1]>>(16-sps)); rel15->rnti = mac->ra_rnti; - else - rel15->rnti = mac->crnti; + rel15->BWPSize = NRRIV2BW(initialDownlinkBWP->genericParameters.locationAndBandwidth, 275); + rel15->BWPStart = NRRIV2PRBOFFSET(bwp_Common->genericParameters.locationAndBandwidth, 275); // NRRIV2PRBOFFSET(initialDownlinkBWP->genericParameters.locationAndBandwidth, 275); + rel15->SubcarrierSpacing = initialDownlinkBWP->genericParameters.subcarrierSpacing; + rel15->dci_length = nr_dci_size(rel15->dci_format, NR_RNTI_RA, rel15->BWPSize); + for (int i = 0; i < sps; i++) + if ((monitoringSymbolsWithinSlot >> (sps - 1 - i)) & 1) { + rel15->coreset.StartSymbolIndex = i; + break; + } + fill_dci_search_candidates(css, rel15); + } else { + add_dci = 0; + } + } else if (mac->ra_state == WAIT_CONTENTION_RESOLUTION){ - fill_dci_search_candidates(mac->SSpace[0][0][ss_id],rel15); + rel15->rnti = mac->t_crnti; + + } else { + + rel15->rnti = mac->crnti; + rel15->BWPSize = NRRIV2BW(bwp_Common->genericParameters.locationAndBandwidth, 275); + rel15->BWPStart = NRRIV2PRBOFFSET(bwp_Common->genericParameters.locationAndBandwidth, 275); + rel15->SubcarrierSpacing = bwp_Common->genericParameters.subcarrierSpacing; + rel15->dci_length = nr_dci_size(rel15->dci_format, NR_RNTI_C, rel15->BWPSize); + // get UE-specific search space + for (ss_id = 0; ss_id < FAPI_NR_MAX_SS_PER_CORESET && mac->SSpace[0][0][ss_id] != NULL; ss_id++){ + uss = mac->SSpace[0][0][ss_id]; + if (uss->searchSpaceType->present == NR_SearchSpace__searchSpaceType_PR_ue_Specific) break; + } + AssertFatal(ss_id < FAPI_NR_MAX_SS_PER_CORESET, "couldn't find a UE-specific SS\n"); + sps = bwp_Common->genericParameters.cyclicPrefix == NULL ? 14 : 12; + // for SPS=14 8 MSBs in positions 13 down to 6 + monitoringSymbolsWithinSlot = (uss->monitoringSymbolsWithinSlot->buf[0]<<(sps-8)) | (uss->monitoringSymbolsWithinSlot->buf[1]>>(16-sps)); + for (int i = 0; i < sps; i++) + if ((monitoringSymbolsWithinSlot >> (sps - 1 - i)) & 1) { + rel15->coreset.StartSymbolIndex = i; + break; + } + fill_dci_search_candidates(uss, rel15); + } + if (add_dci){ dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI; dl_config->number_pdus = dl_config->number_pdus + 1; } diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index c33a469a84..0ec27e401c 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -668,7 +668,7 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in nr_dcireq_t dcireq; frame_t rx_frame = dl_info->frame; slot_t rx_slot = dl_info->slot; - + // check type0 from 38.213 13 if we have no CellGroupConfig // TODO: implementation to be completed if (mac->scd == NULL) { @@ -719,17 +719,12 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in dl_config->number_pdus = dl_config->number_pdus + 1; mac->scheduled_response.dl_config = dl_config; } - } else { // get PDCCH configuration(s) from SCGConfig - // get Coreset and SearchSpace Information from spCellConfigDedicated - // DCI configuration done for BWP 1, Coreset 0, SearchSpace 0 - - // TBR program DCI for slot 1 if PDSCH - // TBR program DCI for slot 7 if RAR DCI PDSCH + } else { // we have an scd dcireq.module_id = mod_id; dcireq.gNB_index = 0; dcireq.cc_id = 0; - dcireq.frame = rx_frame; // TBR not needed + dcireq.frame = rx_frame; dcireq.slot = rx_slot; nr_ue_dcireq(&dcireq); //to be replaced with function pointer later @@ -770,8 +765,11 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in return UE_CONNECTION_OK; } -// Note: msg2 is scheduled in the mixed slot or in the last dl slot -// if they are allowed by search space configuration +// Notes: +// - Type1-PDCCH CSS configuration from ra-SearchSpace. +// - Msg2 is scheduled in the mixed slot or in the last dl slot if they are allowed by the Type 1 Common Search Space configuration +// todo: +// - if Type1-PDCCH CSS is not configured in RRC message (Coreset and SearchSpace), UE searches in Type 0 PDCCH CSS. void nr_ue_msg2_scheduler(module_id_t mod_id, uint16_t rach_frame, uint16_t rach_slot, @@ -870,7 +868,6 @@ void nr_ue_msg2_scheduler(module_id_t mod_id, // PRACH formats 9, 10, 11 are corresponding to dual PRACH format configurations A1/B1, A2/B2, A3/B3. // - todo: // - Partial configuration is actually already stored in (fapi_nr_prach_config_t) &mac->phy_config.config_req->prach_config -//// however we need rach_ConfigGeneric to retrieve the config_index void nr_ue_prach_scheduler(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) { uint8_t config_index, mu, N_dur, N_t_slot, start_symbol; diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c index 3fba88c984..27903d8a3b 100644 --- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c @@ -317,7 +317,8 @@ int nr_ue_dcireq(nr_dcireq_t *dcireq) { printf(" UE_mac->dl_config_request.slot %d VS dcireq->slot %d \n", UE_mac->dl_config_request.slot, dcireq->slot); LOG_D(PHY, "Entering UE DCI configuration frame %d slot %d \n", dcireq->frame, dcireq->slot); - ue_dci_configuration(UE_mac, dl_config, dcireq->slot); + + ue_dci_configuration(UE_mac, dl_config, dcireq->frame, dcireq->slot); return 0; } From 66395ff7b795dc3953d52ea05000e0f2b1e7e70a Mon Sep 17 00:00:00 2001 From: cig Date: Fri, 8 May 2020 11:56:52 +0200 Subject: [PATCH 235/553] Set RA offset at UE to compensate for 2 frames offset introduced by gNB --- openair2/LAYER2/NR_MAC_UE/mac_defs.h | 2 ++ openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 2 ++ openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c | 2 +- 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/openair2/LAYER2/NR_MAC_UE/mac_defs.h b/openair2/LAYER2/NR_MAC_UE/mac_defs.h index 368eae9682..a711561747 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_defs.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_defs.h @@ -188,6 +188,8 @@ typedef struct { /* Random Access parameters */ /// state of RA procedure RA_state_t ra_state; + /// RA rx frame offset: compensate RA rx offset introduced by OAI gNB. + uint8_t RA_offset; /// RA-rnti uint16_t ra_rnti; /// Temporary CRNTI diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 0ec27e401c..57a69e836c 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -887,6 +887,8 @@ void nr_ue_prach_scheduler(module_id_t module_idP, frame_t frameP, sub_frame_t s NR_RACH_ConfigGeneric_t *rach_ConfigGeneric = &setup->rach_ConfigGeneric; config_index = rach_ConfigGeneric->prach_ConfigurationIndex; + mac->RA_offset = 2; // to compensate the rx frame offset at the gNB + if (is_nr_UL_slot(scc, slotP)) { if (setup->msg1_SubcarrierSpacing) diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c index 27903d8a3b..75ae4cd12e 100644 --- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c @@ -120,7 +120,7 @@ int nr_ue_ul_indication(nr_uplink_indication_t *ul_info){ if (mac->generate_nr_prach){ uint16_t monitoring_slot_period, monitoring_offset; uint16_t rach_frame = mac->scheduled_response.ul_config->sfn; - uint16_t rx_rach_frame = (rach_frame + 2) % MAX_FRAME_NUMBER; // compensate 2 frames offset delay at gNB side + uint16_t rx_rach_frame = (rach_frame + mac->RA_offset) % MAX_FRAME_NUMBER; // compensate 2 frames offset delay at gNB side uint16_t rach_slot = mac->scheduled_response.ul_config->slot; nr_ue_msg2_scheduler(module_id, rx_rach_frame, rach_slot, &mac->msg2_rx_frame, &mac->msg2_rx_slot); } From 4522cd4eb9e5e828869836a0d0559ec664c92c98 Mon Sep 17 00:00:00 2001 From: cig Date: Fri, 8 May 2020 12:03:43 +0200 Subject: [PATCH 236/553] Changes to RA procedures: - monitoring RA window - taking RA_offset into account - workaround to generate PRACH only when the RAR has not been received yet (RA is idle) --- openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 109 ++++++++++++------- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 3 +- openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c | 2 +- 3 files changed, 75 insertions(+), 39 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c index b41b966a82..8f01191844 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -64,6 +64,7 @@ extern int64_t table_6_3_3_2_2_prachConfig_Index [256][9]; extern int64_t table_6_3_3_2_3_prachConfig_Index [256][9]; +extern const uint16_t nr_slots_per_frame[5]; //extern uint8_t nfapi_mode; @@ -363,14 +364,13 @@ uint8_t nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, LOG_D(MAC, "nr_ue_get_rach, RA_active value: %d", mac->RA_active); - AssertFatal(setup != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); + AssertFatal(setup != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); if (mac->RA_active == 0) { /* RA not active - checking if RRC is ready to initiate the RA procedure */ LOG_I(MAC, "RA not active. Starting RA preamble initialization.\n"); - mac->ra_state = RA_UE_IDLE; mac->RA_RAPID_found = 0; /* Set RA_PREAMBLE_POWER_RAMPING_STEP */ @@ -442,33 +442,7 @@ uint8_t nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, mac->RA_active = 1; prach_resources->Msg3 = payload; - ra_ResponseWindow = rach_ConfigGeneric->ra_ResponseWindow; - switch (ra_ResponseWindow) { - case 0: - mac->RA_window_cnt = 1; - break; - case 1: - mac->RA_window_cnt = 2; - break; - case 2: - mac->RA_window_cnt = 4; - break; - case 3: - mac->RA_window_cnt = 8; - break; - case 4: - mac->RA_window_cnt = 10; - break; - case 5: - mac->RA_window_cnt = 20; - break; - case 6: - mac->RA_window_cnt = 40; - break; - case 7: - mac->RA_window_cnt = 80; - break; - } + nr_get_RA_window(mac); // Fill in preamble and PRACH resources if (mac->generate_nr_prach) @@ -515,17 +489,16 @@ uint8_t nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, prach_resources->RA_PREAMBLE_BACKOFF = 0; } - if (mac->RA_window_cnt > 0 && mac->RA_RAPID_found == 1) { + if (mac->RA_window_cnt >= 0 && mac->RA_RAPID_found == 1) { + // mac->ra_state = WAIT_CONTENTION_RESOLUTION; LOG_I(MAC, "[MAC][UE %d][RAPROC] Frame %d: subframe %d: RAR successfully received \n", mod_id, frame, nr_tti_tx); - } else { - mac->ra_state = RA_UE_IDLE; - LOG_I(MAC, "[MAC][UE %d][RAPROC] Frame %d: subframe %d: RAR reception not successful, (RA window count %d) \n", - mod_id, - frame, - nr_tti_tx, - mac->RA_window_cnt); + } else if (mac->RA_window_cnt == 0 && !mac->RA_RAPID_found) { + + LOG_I(MAC, "[MAC][UE %d][RAPROC] Frame %d: subframe %d: RAR reception failed \n", mod_id, frame, nr_tti_tx); + + mac->ra_state = RA_UE_IDLE; mac->RA_PREAMBLE_TRANSMISSION_COUNTER++; preambleTransMax = -1; @@ -565,6 +538,9 @@ uint8_t nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, break; } + // Resetting RA window + nr_get_RA_window(mac); + if (mac->RA_PREAMBLE_TRANSMISSION_COUNTER == preambleTransMax + 1){ LOG_D(MAC, "[UE %d] Frame %d: Maximum number of RACH attempts (%d)\n", mod_id, frame, preambleTransMax); mac->RA_backoff_cnt = rand() % (prach_resources->RA_PREAMBLE_BACKOFF + 1); @@ -595,6 +571,20 @@ uint8_t nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, if (mac->generate_nr_prach) nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 0, prach_resources, rach_ConfigDedicated); + } else { + + mac->RA_window_cnt--; + + LOG_I(MAC, "[MAC][UE %d][RAPROC] Frame %d: subframe %d: RAR reception not successful, (RA window count %d) \n", + mod_id, + frame, + nr_tti_tx, + mac->RA_window_cnt); + + // Fill in preamble and PRACH resources + if (mac->generate_nr_prach) + nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 0, prach_resources, rach_ConfigDedicated); + } } } else if (UE_mode == PUSCH) { @@ -603,3 +593,48 @@ uint8_t nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, } return mac->generate_nr_prach; } + +void nr_get_RA_window(NR_UE_MAC_INST_t *mac){ + + uint8_t mu, ra_ResponseWindow; + NR_ServingCellConfigCommon_t *scc = mac->scc; + NR_RACH_ConfigCommon_t *setup = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup; + NR_RACH_ConfigGeneric_t *rach_ConfigGeneric = &setup->rach_ConfigGeneric; + NR_FrequencyInfoDL_t *frequencyInfoDL = scc->downlinkConfigCommon->frequencyInfoDL; + + ra_ResponseWindow = rach_ConfigGeneric->ra_ResponseWindow; + + if (setup->msg1_SubcarrierSpacing) + mu = *setup->msg1_SubcarrierSpacing; + else + mu = frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing; + + mac->RA_window_cnt = mac->RA_offset*nr_slots_per_frame[mu]; // taking into account the 2 frames gap introduced by OAI gNB + + switch (ra_ResponseWindow) { + case 0: + mac->RA_window_cnt += 1; + break; + case 1: + mac->RA_window_cnt += 2; + break; + case 2: + mac->RA_window_cnt += 4; + break; + case 3: + mac->RA_window_cnt += 8; + break; + case 4: + mac->RA_window_cnt += 10; + break; + case 5: + mac->RA_window_cnt += 20; + break; + case 6: + mac->RA_window_cnt += 40; + break; + case 7: + mac->RA_window_cnt += 80; + break; + } +} \ No newline at end of file diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 57a69e836c..cfed0b2d72 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -906,7 +906,8 @@ void nr_ue_prach_scheduler(module_id_t module_idP, frame_t frameP, sub_frame_t s &start_symbol, &N_t_slot, &N_dur); - if (is_nr_prach_slot) { + + if (is_nr_prach_slot && mac->ra_state == RA_UE_IDLE) { mac->generate_nr_prach = 1; diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c index 75ae4cd12e..d123c74e0b 100644 --- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c @@ -115,7 +115,7 @@ int nr_ue_ul_indication(nr_uplink_indication_t *ul_info){ ret = nr_ue_scheduler(NULL, ul_info); - if (is_nr_UL_slot(mac->scc, ul_info->slot_tx) && mac->ra_state == RA_UE_IDLE && get_softmodem_params()->do_ra){ + if (is_nr_UL_slot(mac->scc, ul_info->slot_tx) && get_softmodem_params()->do_ra){ nr_ue_prach_scheduler(module_id, ul_info->frame_tx, ul_info->slot_tx); if (mac->generate_nr_prach){ uint16_t monitoring_slot_period, monitoring_offset; From 268a35419e4137c4050dfaa4543fa6fcaffb0ce6 Mon Sep 17 00:00:00 2001 From: cig Date: Mon, 11 May 2020 16:09:47 +0200 Subject: [PATCH 237/553] Hotfix scrambling rnti - this is needed because in the current implementation of the gNB the scrambling rnti is 0 for the RA and dci rnti otherwise --- .../NR_MAC_UE/nr_ue_dci_configuration.c | 22 +++++++++++-------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c index bbae5a5cf4..8c7be8f725 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c @@ -192,15 +192,6 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl rel15->coreset.CoreSetType = 1; rel15->coreset.precoder_granularity = coreset->precoderGranularity; - // Scrambling RNTI - if (coreset->pdcch_DMRS_ScramblingID) { - rel15->coreset.pdcch_dmrs_scrambling_id = *coreset->pdcch_DMRS_ScramblingID; - rel15->coreset.scrambling_rnti = mac->t_crnti; - } else { - rel15->coreset.pdcch_dmrs_scrambling_id = *scc->physCellId; - rel15->coreset.scrambling_rnti = 0; - } - if (mac->ra_state == WAIT_RAR){ NR_BWP_DownlinkCommon_t *initialDownlinkBWP = scc->downlinkConfigCommon->initialDownlinkBWP; @@ -266,6 +257,19 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl } fill_dci_search_candidates(uss, rel15); } + + // Scrambling RNTI + if (coreset->pdcch_DMRS_ScramblingID) { + rel15->coreset.pdcch_dmrs_scrambling_id = *coreset->pdcch_DMRS_ScramblingID; + rel15->coreset.scrambling_rnti = mac->t_crnti; + } else { + rel15->coreset.pdcch_dmrs_scrambling_id = *scc->physCellId; + if(mac->ra_state == WAIT_RAR) + rel15->coreset.scrambling_rnti = 0; + else + rel15->coreset.scrambling_rnti = rel15->rnti; + } + if (add_dci){ dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI; dl_config->number_pdus = dl_config->number_pdus + 1; From 6f0e4fe149469a90585972cd6524418077af8417 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Wed, 13 May 2020 16:22:05 +0200 Subject: [PATCH 238/553] using numDmrsCdmGrpsNoData for PDSCH in PHY --- openair1/PHY/NR_TRANSPORT/nr_dlsch.c | 23 +++++++++++-------- openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c | 9 ++++---- openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.c | 21 +++++++++++++++++ openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.h | 7 +++++- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 14 +++++++---- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 2 +- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 7 +++--- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 2 +- 8 files changed, 60 insertions(+), 25 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch.c index b8d9fdea18..8324508361 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch.c @@ -133,19 +133,22 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch, int16_t **mod_symbs = (int16_t**)dlsch->mod_symbs; int16_t **tx_layers = (int16_t**)dlsch->txdataF; int8_t Wf[2], Wt[2], l0, l_prime[2], delta; - uint8_t nodata_dmrs = 1; uint8_t dmrs_Type = rel15->dmrsConfigType; - int nb_re_dmrs = (dmrs_Type== NFAPI_NR_DMRS_TYPE1) ? 6:4; - uint16_t n_dmrs = ((rel15->rbSize+rel15->rbStart)*nb_re_dmrs)<<1; - int16_t mod_dmrs[n_dmrs<<1]; - + int nb_re_dmrs; + uint16_t n_dmrs; + if (rel15->dmrsConfigType==NFAPI_NR_DMRS_TYPE1) { + nb_re_dmrs = 6*rel15->numDmrsCdmGrpsNoData; + n_dmrs = ((rel15->rbSize+rel15->rbStart)*6)<<1; + } + else { + nb_re_dmrs = 4*rel15->numDmrsCdmGrpsNoData; + n_dmrs = ((rel15->rbSize+rel15->rbStart)*4)<<1; + } uint16_t nb_re; - if (nodata_dmrs) // no data in dmrs symbol - nb_re = ((12*rel15->NrOfSymbols)-12-xOverhead)*rel15->rbSize*rel15->NrOfCodewords; - else - nb_re = ((12*rel15->NrOfSymbols)-nb_re_dmrs-xOverhead)*rel15->rbSize*rel15->NrOfCodewords; + nb_re = ((12*rel15->NrOfSymbols)-nb_re_dmrs-xOverhead)*rel15->rbSize*rel15->NrOfCodewords; uint8_t Qm = rel15->qamModOrder[0]; uint32_t encoded_length = nb_re*Qm; + int16_t mod_dmrs[n_dmrs<<1]; /// CRC, coding, interleaving and rate matching AssertFatal(harq->pdu!=NULL,"harq->pdu is null\n"); @@ -301,7 +304,7 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch, } else { - if( (l != dmrs_symbol) || !nodata_dmrs) { + if( (l != dmrs_symbol) || allowed_pdsch_re_in_dmrs_symbol(k,start_sc,rel15->numDmrsCdmGrpsNoData,dmrs_Type)) { ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + (2*txdataF_offset)] = (amp * tx_layers[ap][m<<1]) >> 15; ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + 1 + (2*txdataF_offset)] = (amp * tx_layers[ap][(m<<1) + 1]) >> 15; #ifdef DEBUG_DLSCH_MAPPING diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c index 065e62a2cb..5e10e1dd06 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c @@ -336,12 +336,13 @@ int nr_dlsch_encoding(unsigned char *a, uint32_t E; uint8_t Ilbrm = 1; uint32_t Tbslbrm = 950984; //max tbs - uint8_t nodata_dmrs = 1; uint8_t nb_re_dmrs; - if (nodata_dmrs) - nb_re_dmrs = 12; + + if (rel15->dmrsConfigType==NFAPI_NR_DMRS_TYPE1) + nb_re_dmrs = 6*rel15->numDmrsCdmGrpsNoData; else - nb_re_dmrs = rel15->dmrsConfigType==NFAPI_NR_DMRS_TYPE1 ? 6:4; + nb_re_dmrs = 4*rel15->numDmrsCdmGrpsNoData; + uint16_t length_dmrs = get_num_dmrs(rel15->dlDmrsSymbPos); uint16_t R=rel15->targetCodeRate[0]; float Coderate = 0.0; diff --git a/openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.c b/openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.c index 04045380eb..d74819f87f 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.c +++ b/openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.c @@ -84,6 +84,27 @@ uint16_t get_dmrs_freq_idx(uint16_t n, uint8_t k_prime, uint8_t delta, uint8_t d return dmrs_idx; } + +uint8_t allowed_pdsch_re_in_dmrs_symbol(uint16_t k, + uint16_t start_sc, + uint8_t numDmrsCdmGrpsNoData, + uint8_t dmrs_type) { + uint8_t delta; + for (int i = 0; ipdsch_pdu_rel15; uint16_t N_PRB_oh = x_overhead; uint8_t N_PRB_DMRS; - if (nodata_dmrs) - N_PRB_DMRS = 12; - else - N_PRB_DMRS = (pdsch_rel15->dmrsConfigType == NFAPI_NR_DMRS_TYPE1)?6:4; //This only works for antenna port 1000 + if (pdsch_rel15->dmrsConfigType == NFAPI_NR_DMRS_TYPE1) { + // if no data in dmrs cdm group is 1 only even REs have no data + // if no data in dmrs cdm group is 2 both odd and even REs have no data + N_PRB_DMRS = numdmrscdmgroupnodata*6; + } + else { + N_PRB_DMRS = numdmrscdmgroupnodata*4; + } uint8_t N_sh_symb = pdsch_rel15->NrOfSymbols; uint8_t Imcs = pdsch_rel15->mcsIndex[0]; uint16_t N_RE_prime = NR_NB_SC_PER_RB*N_sh_symb - N_PRB_DMRS - N_PRB_oh; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index 5b7bf3ce02..31bdfc6a1b 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -698,7 +698,7 @@ void nr_generate_Msg2(module_id_t module_idP, LOG_D(MAC,"[gNB %d][RAPROC] Frame %d, Subframe %d: RA state %d\n", module_idP, frameP, slotP, ra->state); x_Overhead = 0; - nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead, 1, dci_pdu_rel15[0].tb_scaling); + nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead, pdsch_pdu_rel15->numDmrsCdmGrpsNoData, dci_pdu_rel15[0].tb_scaling); // DL TX request tx_req->PDU_length = pdsch_pdu_rel15->TBSize[0]; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 9255d633f8..46d08cd6d2 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -369,6 +369,7 @@ int configure_fapi_dl_pdu(int Mod_idP, dci_pdu_rel15[0].harq_pid = 0; // DAI dci_pdu_rel15[0].dai[0].val = (pucch_sched->dai_c-1)&3; + // TPC for PUCCH dci_pdu_rel15[0].tpc = 1; // table 7.2.1-1 in 38.213 // PUCCH resource indicator @@ -377,7 +378,7 @@ int configure_fapi_dl_pdu(int Mod_idP, dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator.val = pucch_sched->timing_indicator; // antenna ports dci_pdu_rel15[0].antenna_ports.val = 0; // nb of cdm groups w/o data 1 and dmrs port 0 - + LOG_I(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n", dci_pdu_rel15[0].frequency_domain_assignment.val, pdsch_pdu_rel15->rbStart, @@ -409,7 +410,7 @@ int configure_fapi_dl_pdu(int Mod_idP, } } AssertFatal(found==1,"Couldn't find an adequate searchspace\n"); - + int ret = nr_configure_pdcch(nr_mac, pdcch_pdu_rel15, UE_list->rnti[UE_id], @@ -444,7 +445,7 @@ int configure_fapi_dl_pdu(int Mod_idP, pdcch_pdu_rel15->DurationSymbols); int x_Overhead = 0; // should be 0 for initialBWP - nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead,1,0); + nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu,x_Overhead,pdsch_pdu_rel15->numDmrsCdmGrpsNoData,0); // Hardcode it for now TBS = dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15.TBSize[0]; diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index cc0254cc3a..fc50a4d239 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -226,7 +226,7 @@ int to_absslot(nfapi_nr_config_request_scf_t *cfg,int frame,int slot); void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, int x_overhead, - uint8_t nodata_dmrs, + uint8_t numdmrscdmgroupnodata, uint8_t tb_scaling); /** \brief Computes Q based on I_MCS PDSCH and table_idx for downlink. Implements MCS Tables from 38.214. */ uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx); From 1c7ee3caba8f8606df4fdbd916e8387a11671eea Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Wed, 13 May 2020 18:05:15 +0200 Subject: [PATCH 239/553] using num_dmrs_cdm_grps_no_data for PUSCH in PHY --- openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c | 14 +++++++++----- openair1/SCHED_NR/phy_procedures_nr_gNB.c | 9 ++++----- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 13 ++++++++++--- 3 files changed, 23 insertions(+), 13 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c index 2824ac1544..5c440f7a12 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c @@ -1028,7 +1028,6 @@ int nr_rx_pusch(PHY_VARS_gNB *gNB, int avg[4]; NR_DL_FRAME_PARMS *frame_parms = &gNB->frame_parms; nfapi_nr_pusch_pdu_t *rel15_ul = &gNB->ulsch[ulsch_id][0]->harq_processes[harq_pid]->ulsch_pdu; - uint8_t nodata_dmrs = 1; // FIXME to be properly configured from fapi dmrs_symbol_flag = 0; ptrs_symbol_flag = 0; @@ -1060,10 +1059,15 @@ int nr_rx_pusch(PHY_VARS_gNB *gNB, if (dmrs_symbol_flag == 1){ if (((rel15_ul->ul_dmrs_symb_pos)>>((symbol+1)%frame_parms->symbols_per_slot))&0x01) AssertFatal(1==0,"Double DMRS configuration is not yet supported\n"); - if (nodata_dmrs) - nb_re_pusch = 0; - else - nb_re_pusch = rel15_ul->rb_size * ((rel15_ul->dmrs_config_type==pusch_dmrs_type1)?6:8); + + if (rel15_ul->dmrs_config_type == 0) { + // if no data in dmrs cdm group is 1 only even REs have no data + // if no data in dmrs cdm group is 2 both odd and even REs have no data + nb_re_pusch = rel15_ul->rb_size *(12 - (rel15_ul->num_dmrs_cdm_grps_no_data*6)); + } + else { + nb_re_pusch = rel15_ul->rb_size *(12 - (rel15_ul->num_dmrs_cdm_grps_no_data*4)); + } gNB->pusch_vars[ulsch_id]->dmrs_symbol = symbol; } else { nb_re_pusch = rel15_ul->rb_size * NR_NB_SC_PER_RB; diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index 6b49d64338..11eec5db0a 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -218,7 +218,7 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH NR_DL_FRAME_PARMS *frame_parms = &gNB->frame_parms; nfapi_nr_pusch_pdu_t *pusch_pdu = &gNB->ulsch[ULSCH_id][0]->harq_processes[harq_pid]->ulsch_pdu; - uint8_t ret, nodata_dmrs = 1; + uint8_t ret; uint8_t l, number_dmrs_symbols = 0; uint32_t G; uint16_t start_symbol, number_symbols, nb_re_dmrs; @@ -229,11 +229,10 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH for (l = start_symbol; l < start_symbol + number_symbols; l++) number_dmrs_symbols += ((pusch_pdu->ul_dmrs_symb_pos)>>l)&0x01; - if (nodata_dmrs) - nb_re_dmrs = 12; + if (pusch_pdu->dmrs_config_type==pusch_dmrs_type1) + nb_re_dmrs = 6*pusch_pdu->num_dmrs_cdm_grps_no_data; else - nb_re_dmrs = ((pusch_pdu->dmrs_config_type == pusch_dmrs_type1)?6:4); - + nb_re_dmrs = 4*pusch_pdu->num_dmrs_cdm_grps_no_data; G = nr_get_G(pusch_pdu->rb_size, number_symbols, diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 46d08cd6d2..218c7acbe6 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -801,7 +801,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, pusch_pdu->dmrs_config_type = 0; //dmrs-type 1 (the one with a single DMRS symbol in the beginning) pusch_pdu->ul_dmrs_scrambling_id = 0; //If provided and the PUSCH is not a msg3 PUSCH, otherwise, L2 should set this to physical cell id. pusch_pdu->scid = 0; //DMRS sequence initialization [TS38.211, sec 6.4.1.1.1]. Should match what is sent in DCI 0_1, otherwise set to 0. - //pusch_pdu->num_dmrs_cdm_grps_no_data; + pusch_pdu->num_dmrs_cdm_grps_no_data = 1; //pusch_pdu->dmrs_ports; //DMRS ports. [TS38.212 7.3.1.1.2] provides description between DCI 0-1 content and DMRS ports. Bitmap occupying the 11 LSBs with: bit 0: antenna port 1000 bit 11: antenna port 1011 and for each bit 0: DMRS port not used 1: DMRS port used //Pusch Allocation in frequency domain [TS38.214, sec 6.1.2.2] pusch_pdu->resource_alloc = 1; //type 1 @@ -820,17 +820,24 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, pusch_pdu->pusch_data.harq_process_id = 0; pusch_pdu->pusch_data.new_data_indicator = 0; - uint8_t no_data_in_dmrs = 1; // temp implementation uint8_t num_dmrs_symb = 0; for(int dmrs_counter = pusch_pdu->start_symbol_index; dmrs_counter < pusch_pdu->start_symbol_index + pusch_pdu->nr_of_symbols; dmrs_counter++) num_dmrs_symb += ((pusch_pdu->ul_dmrs_symb_pos >> dmrs_counter) & 1); + uint8_t N_PRB_DMRS; + if (pusch_pdu->dmrs_config_type == 0) { + N_PRB_DMRS = pusch_pdu->num_dmrs_cdm_grps_no_data*6; + } + else { + N_PRB_DMRS = pusch_pdu->num_dmrs_cdm_grps_no_data*4; + } + pusch_pdu->pusch_data.tb_size = nr_compute_tbs(pusch_pdu->qam_mod_order, pusch_pdu->target_code_rate, pusch_pdu->rb_size, pusch_pdu->nr_of_symbols, - ( no_data_in_dmrs ? 12 : ((pusch_pdu->dmrs_config_type == pusch_dmrs_type1) ? 6 : 4) ) * num_dmrs_symb, + N_PRB_DMRS * num_dmrs_symb, 0, //nb_rb_oh 0, pusch_pdu->nrOfLayers)>>3; From 100f75ba45c14b10072ec3c9491c5eae6ee701d5 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Thu, 14 May 2020 00:41:15 +0200 Subject: [PATCH 240/553] polar coding for UCI (PUCCH) integrated into polartest for lengths 12...64 --- openair1/PHY/CODING/TESTBENCH/polartest.c | 12 +++--- openair1/PHY/CODING/coding_defs.h | 12 ++++++ openair1/PHY/CODING/crc_byte.c | 40 +++++++++++++++++++ .../CODING/nrPolar_tools/nr_polar_decoder.c | 10 +++-- .../CODING/nrPolar_tools/nr_polar_encoder.c | 21 ++++++---- .../CODING/nrPolar_tools/nr_polar_uci_defs.h | 4 +- openair1/PHY/CODING/nr_polar_init.c | 34 ++++++++++++++-- 7 files changed, 112 insertions(+), 21 deletions(-) diff --git a/openair1/PHY/CODING/TESTBENCH/polartest.c b/openair1/PHY/CODING/TESTBENCH/polartest.c index 806d8de28c..a07111a986 100644 --- a/openair1/PHY/CODING/TESTBENCH/polartest.c +++ b/openair1/PHY/CODING/TESTBENCH/polartest.c @@ -27,7 +27,7 @@ int main(int argc, char *argv[]) { //Default simulation values (Aim for iterations = 1000000.) int decoder_int16=0; - int itr, iterations = 1000, arguments, polarMessageType = 0; //0=PBCH, 1=DCI, -1=UCI + int itr, iterations = 1000, arguments, polarMessageType = 0; //0=PBCH, 1=DCI, 2=UCI double SNRstart = -20.0, SNRstop = 0.0, SNRinc= 0.5; //dB double SNR, SNR_lin; int16_t nBitError = 0; // -1 = Decoding failed (All list entries have failed the CRC checks). @@ -42,6 +42,7 @@ int main(int argc, char *argv[]) switch (arguments) { case 's': SNRstart = atof(optarg); + SNRstop = SNRstart + 2; break; case 'd': @@ -91,7 +92,7 @@ int main(int argc, char *argv[]) case 'k': testLength=atoi(optarg); - if (testLength < 12 || testLength > 60) { + if (testLength < 12 || testLength > 127) { printf("Illegal packet bitlength %d \n",testLength); exit(-1); } @@ -123,9 +124,10 @@ int main(int argc, char *argv[]) aggregation_level = NR_POLAR_PBCH_AGGREGATION_LEVEL; } else if (polarMessageType == 1) { //DCI coderLength = 108*aggregation_level; - } else if (polarMessageType == -1) { //UCI - printf("UCI testing not supported yet\n"); - exit(-1); + } else if (polarMessageType == 2) { //UCI + //pucch2 parameters, 1 symbol, aggregation_level = NPRB + AssertFatal(aggregation_level>2,"For UCI formats, aggregation (N_RB) should be > 2\n"); + coderLength = 16*aggregation_level; } //Logging diff --git a/openair1/PHY/CODING/coding_defs.h b/openair1/PHY/CODING/coding_defs.h index 9b111309cd..80519ca752 100644 --- a/openair1/PHY/CODING/coding_defs.h +++ b/openair1/PHY/CODING/coding_defs.h @@ -382,12 +382,24 @@ unsigned int crc16 (unsigned char * inptr, int bitlen); @param bitlen length of inputs in bits*/ unsigned int crc12 (unsigned char * inptr, int bitlen); +/*!\fn uint32_t crc12(uint8_t *inPtr, int32_t bitlen) +\brief This computes an 11-bit crc based on 3GPP NR specifications. +@param inPtr Pointer to input byte stream +@param bitlen length of inputs in bits*/ +unsigned int crc11 (unsigned char * inptr, int bitlen); + /*!\fn uint32_t crc8(uint8_t *inPtr, int32_t bitlen) \brief This computes a 8-bit crc based on 3GPP UMTS specifications. @param inPtr Pointer to input byte stream @param bitlen length of inputs in bits*/ unsigned int crc8 (unsigned char * inptr, int bitlen); +/*!\fn uint32_t crc8(uint8_t *inPtr, int32_t bitlen) +\brief This computes a 6-bit crc based on 3GPP NR specifications. +@param inPtr Pointer to input byte stream +@param bitlen length of inputs in bits*/ +unsigned int crc6 (unsigned char * inptr, int bitlen); + int check_crc(uint8_t* decoded_bytes, uint32_t n, uint32_t F, uint8_t crc_type); /*!\fn void phy_viterbi_dot11_sse2(int8_t *y, uint8_t *decoded_bytes, uint16_t n,int offset,int traceback) diff --git a/openair1/PHY/CODING/crc_byte.c b/openair1/PHY/CODING/crc_byte.c index ee5c302adb..0769ab992a 100644 --- a/openair1/PHY/CODING/crc_byte.c +++ b/openair1/PHY/CODING/crc_byte.c @@ -90,7 +90,9 @@ static unsigned int crc24bTable[256]; static unsigned int crc24cTable[256]; static unsigned short crc16Table[256]; static unsigned short crc12Table[256]; +static unsigned short crc11Table[256]; static unsigned char crc8Table[256]; +static unsigned char crc6Table[256]; void crcTableInit (void) { @@ -102,7 +104,9 @@ void crcTableInit (void) crc24cTable[c] = crcbit (&c, 1, poly24c); crc16Table[c] = (unsigned short) (crcbit (&c, 1, poly16) >> 16); crc12Table[c] = (unsigned short) (crcbit (&c, 1, poly12) >> 16); + crc11Table[c] = (unsigned short) (crcbit (&c, 1, poly11) >> 16); crc8Table[c] = (unsigned char) (crcbit (&c, 1, poly8) >> 24); + crc6Table[c] = (unsigned char) (crcbit (&c, 1, poly6) >> 24); } while (++c); } @@ -207,6 +211,24 @@ crc12 (unsigned char * inptr, int bitlen) return crc; } +unsigned int +crc11 (unsigned char * inptr, int bitlen) +{ + int octetlen, resbit; + unsigned int crc = 0; + octetlen = bitlen / 8; /* Change in octets */ + resbit = (bitlen % 8); + + while (octetlen-- > 0) { + crc = (crc << 8) ^ (crc11Table[(*inptr++) ^ (crc >> 24)] << 16); + } + + if (resbit > 0) + crc = (crc << resbit) ^ (crc11Table[((*inptr) >> (8 - resbit)) ^ (crc >> (32 - resbit))] << 16); + + return crc; +} + unsigned int crc8 (unsigned char * inptr, int bitlen) { @@ -225,6 +247,24 @@ crc8 (unsigned char * inptr, int bitlen) return crc; } +unsigned int +crc6 (unsigned char * inptr, int bitlen) +{ + int octetlen, resbit; + unsigned int crc = 0; + octetlen = bitlen / 8; /* Change in octets */ + resbit = (bitlen % 8); + + while (octetlen-- > 0) { + crc = crc6Table[(*inptr++) ^ (crc >> 24)] << 24; + } + + if (resbit > 0) + crc = (crc << resbit) ^ (crc8Table[((*inptr) >> (8 - resbit)) ^ (crc >> (32 - resbit))] << 24); + + return crc; +} + int check_crc(uint8_t* decoded_bytes, uint32_t n, uint32_t F, uint8_t crc_type) { uint32_t crc=0,oldcrc=0; diff --git a/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoder.c b/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoder.c index 53119a1c2b..18db8a01fb 100644 --- a/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoder.c +++ b/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoder.c @@ -569,7 +569,7 @@ int8_t polar_decoder_dci(double *input, } void init_polar_deinterleaver_table(t_nrPolar_params *polarParams) { - AssertFatal(polarParams->K > 32, "K = %d < 33, is not supported yet\n",polarParams->K); + AssertFatal(polarParams->K > 17, "K = %d < 18, is not allowed\n",polarParams->K); AssertFatal(polarParams->K < 129, "K = %d > 128, is not supported yet\n",polarParams->K); int bit_i,ip,ipmod64; int numbytes = polarParams->K>>3; @@ -670,7 +670,9 @@ uint32_t polar_decoder_int16(int16_t *input, A32_flip[1+offset]=((uint8_t *)&Aprime)[2]; A32_flip[2+offset]=((uint8_t *)&Aprime)[1]; A32_flip[3+offset]=((uint8_t *)&Aprime)[0]; - crc = (uint64_t)(crc24c(A32_flip,8*offset+len)>>8); + if (crclen == 24) crc = (uint64_t)((crc24c(A32_flip,8*offset+len)>>8)&0xffffff); + else if (crclen == 11) crc = (uint64_t)((crc11(A32_flip,8*offset+len)>>21)&0x7ff); + else if (crclen == 6) crc = (uint64_t)((crc6(A32_flip,8*offset+len)>>26)&0x3f); } else if (len<=64) { Ar = (B[0]>>crclen) | (B[1]<<(64-crclen));; uint8_t A64_flip[8+offset]; @@ -688,7 +690,9 @@ uint32_t polar_decoder_int16(int16_t *input, A64_flip[5+offset]=((uint8_t *)&Aprime)[2]; A64_flip[6+offset]=((uint8_t *)&Aprime)[1]; A64_flip[7+offset]=((uint8_t *)&Aprime)[0]; - crc = (uint64_t)(crc24c(A64_flip,8*offset+len)>>8); + if (crclen==24) crc = (uint64_t)(crc24c(A64_flip,8*offset+len)>>8)&0xffffff; + else if (crclen==11) crc = (uint64_t)(crc11(A64_flip,8*offset+len)>>21)&0x7ff; + else if (crclen==6) crc = (uint64_t)(crc6(A64_flip,8*offset+len)>>26)&0x3f; } #if 0 diff --git a/openair1/PHY/CODING/nrPolar_tools/nr_polar_encoder.c b/openair1/PHY/CODING/nrPolar_tools/nr_polar_encoder.c index 8e4b45f744..25cc8c80cd 100644 --- a/openair1/PHY/CODING/nrPolar_tools/nr_polar_encoder.c +++ b/openair1/PHY/CODING/nrPolar_tools/nr_polar_encoder.c @@ -295,8 +295,8 @@ static inline void polar_rate_matching(t_nrPolar_params *polarParams,void *in,vo void build_polar_tables(t_nrPolar_params *polarParams) { // build table b -> c' - AssertFatal(polarParams->K > 32, "K = %d < 33, is not supported yet\n",polarParams->K); - AssertFatal(polarParams->K < 129, "K = %d > 64, is not supported yet\n",polarParams->K); + AssertFatal(polarParams->K > 17, "K = %d < 18, is not possible\n",polarParams->K); + AssertFatal(polarParams->K < 129, "K = %d > 128, is not supported yet\n",polarParams->K); int bit_i,ip; int numbytes = polarParams->K>>3; int residue = polarParams->K&7; @@ -327,7 +327,7 @@ void build_polar_tables(t_nrPolar_params *polarParams) { AssertFatal(polarParams->N==512 || polarParams->N==256 || polarParams->N==128,"N = %d, not done yet\n",polarParams->N); // build G bit vectors for information bit positions and convert the bit as bytes tables in nr_polar_kronecker_power_matrices.c to 64 bit packed vectors. // keep only rows of G which correspond to information/crc bits - polarParams->G_N_tab = (uint64_t **)malloc(polarParams->K * sizeof(int64_t *)); + polarParams->G_N_tab = (uint64_t **)malloc((polarParams->K + polarParams->n_pc) * sizeof(int64_t *)); int k=0; for (int i=0; iN; i++) { @@ -412,14 +412,14 @@ void polar_encoder_fast(uint64_t *A, int32_t crcmask, uint8_t ones_flag, t_nrPolar_params *polarParams) { - AssertFatal(polarParams->K > 32, "K = %d < 33, is not supported yet\n",polarParams->K); + // AssertFatal(polarParams->K > 32, "K = %d < 33, is not supported yet\n",polarParams->K); AssertFatal(polarParams->K < 129, "K = %d > 128, is not supported yet\n",polarParams->K); AssertFatal(polarParams->payloadBits < 65, "payload bits = %d > 64, is not supported yet\n",polarParams->payloadBits); uint64_t B[4]= {0,0,0,0},Cprime[4]= {0,0,0,0}; int bitlen = polarParams->payloadBits; // append crc AssertFatal(bitlen<129,"support for payloads <= 128 bits\n"); - AssertFatal(polarParams->crcParityBits == 24,"support for 24-bit crc only for now\n"); + // AssertFatal(polarParams->crcParityBits == 24,"support for 24-bit crc only for now\n"); //int bitlen0=bitlen; uint64_t tcrc=0; uint8_t offset = 0; @@ -444,7 +444,9 @@ void polar_encoder_fast(uint64_t *A, A32_flip[1+offset]=((uint8_t *)&Aprime)[2]; A32_flip[2+offset]=((uint8_t *)&Aprime)[1]; A32_flip[3+offset]=((uint8_t *)&Aprime)[0]; - tcrc = (uint64_t)((crcmask^(crc24c(A32_flip,8*offset+bitlen)>>8))); + if (polarParams->crcParityBits == 24) tcrc = (uint64_t)(((crcmask^(crc24c(A32_flip,8*offset+bitlen)>>8)))&0xffffff); + else if (polarParams->crcParityBits == 11) tcrc = (uint64_t)(((crcmask^(crc11(A32_flip,bitlen)>>21)))&0x7ff); + else if (polarParams->crcParityBits == 6) tcrc = (uint64_t)(((crcmask^(crc6(A32_flip,bitlen)>>26)))&0x3f); } else if (bitlen<=64) { uint8_t A64_flip[8+offset]; if (ones_flag) { @@ -461,7 +463,8 @@ void polar_encoder_fast(uint64_t *A, A64_flip[5+offset]=((uint8_t *)&Aprime)[2]; A64_flip[6+offset]=((uint8_t *)&Aprime)[1]; A64_flip[7+offset]=((uint8_t *)&Aprime)[0]; - tcrc = (uint64_t)((crcmask^(crc24c(A64_flip,8*offset+bitlen)>>8))); + if (polarParams->crcParityBits == 24) tcrc = (uint64_t)((crcmask^(crc24c(A64_flip,8*offset+bitlen)>>8)))&0xffffff; + else if (polarParams->crcParityBits == 11) tcrc = (uint64_t)((crcmask^(crc11(A64_flip,bitlen)>>21)))&0x7ff; } else if (bitlen<=128) { uint8_t A128_flip[16+offset]; @@ -479,7 +482,8 @@ void polar_encoder_fast(uint64_t *A, A128_flip[10+offset]=((uint8_t*)&Aprime)[5]; A128_flip[11+offset]=((uint8_t*)&Aprime)[4]; A128_flip[12+offset]=((uint8_t*)&Aprime)[3]; A128_flip[13+offset]=((uint8_t*)&Aprime)[2]; A128_flip[14+offset]=((uint8_t*)&Aprime)[1]; A128_flip[15+offset]=((uint8_t*)&Aprime)[0]; - tcrc = (uint64_t)((crcmask^(crc24c(A128_flip,8*offset+bitlen)>>8))); + if (polarParams->crcParityBits == 24) tcrc = (uint64_t)((crcmask^(crc24c(A128_flip,8*offset+bitlen)>>8)))&0xffffff; + else if (polarParams->crcParityBits == 11) tcrc = (uint64_t)((crcmask^(crc11(A128_flip,bitlen)>>21)))&0x7ff; } int n; @@ -522,6 +526,7 @@ void polar_encoder_fast(uint64_t *A, #ifdef DEBUG_POLAR_ENCODER + printf("Polar encoder: (N,K) : (%d,%d)\n",polarParams->N,polarParams->K); if (polarParams->K<65) printf("A %llx B %llx Cprime %llx (payload bits %d,crc %x)\n", (unsigned long long)(A[0]&(((uint64_t)1<crcCorrectionBits = NR_POLAR_DCI_CRC_ERROR_CORRECTION_BITS; newPolarInitNode->crc_generator_matrix=crc24c_generator_matrix(newPolarInitNode->payloadBits+newPolarInitNode->crcParityBits);//G_P //printf("Initializing polar parameters for DCI (K %d, E %d, L %d)\n",newPolarInitNode->payloadBits,newPolarInitNode->encoderLength,aggregation_level); - } else if (messageType == -1) { //UCI + } else if (messageType == 2) { //UCI PUCCH2 + AssertFatal(aggregation_level>2,"Aggregation level (%d) for PUCCH 2 encoding is NPRB and should be > 2\n",aggregation_level); + AssertFatal(messageLength>11,"Message length %d is too short for polar encoding of UCI\n",messageLength); + newPolarInitNode->n_max = NR_POLAR_PUCCH_N_MAX; + newPolarInitNode->i_il = NR_POLAR_PUCCH_I_IL; + newPolarInitNode->encoderLength = aggregation_level * 16; + + newPolarInitNode->i_seg = 0; + + if ((messageLength >= 360 && newPolarInitNode->encoderLength >= 1088)|| + (messageLength >= 1013)) newPolarInitNode->i_seg = 1; + + newPolarInitNode->crcParityBits = 11; + newPolarInitNode->n_pc = 0; + newPolarInitNode->n_pc_wm = 0; + + if (messageLength < 20) { + newPolarInitNode->crcParityBits = 6; + newPolarInitNode->n_pc = 3; + if ((newPolarInitNode->encoderLength - messageLength - 6 + 3) < 193) newPolarInitNode->n_pc_wm = 1; + } + + + + newPolarInitNode->i_bil = NR_POLAR_PUCCH_I_BIL; + + newPolarInitNode->payloadBits = messageLength; + newPolarInitNode->crcCorrectionBits = NR_POLAR_PUCCH_CRC_ERROR_CORRECTION_BITS; + //newPolarInitNode->crc_generator_matrix=crc24c_generator_matrix(newPolarInitNode->payloadBits+newPolarInitNode->crcParityBits);//G_P } else { AssertFatal(1 == 0, "[nr_polar_init] Incorrect Message Type(%d)", messageType); } newPolarInitNode->K = newPolarInitNode->payloadBits + newPolarInitNode->crcParityBits; // Number of bits to encode. newPolarInitNode->N = nr_polar_output_length(newPolarInitNode->K, - newPolarInitNode->encoderLength, - newPolarInitNode->n_max); + newPolarInitNode->encoderLength, + newPolarInitNode->n_max); newPolarInitNode->n = log2(newPolarInitNode->N); newPolarInitNode->G_N = nr_polar_kronecker_power_matrices(newPolarInitNode->n); //polar_encoder vectors: From f043c63a34363fd1e593d0aa521a8d2465727ea8 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Thu, 14 May 2020 00:45:58 +0200 Subject: [PATCH 241/553] added 2 UCI tests to CI for polartest --- cmake_targets/autotests/test_case_list.xml | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/cmake_targets/autotests/test_case_list.xml b/cmake_targets/autotests/test_case_list.xml index 882670727b..d424db9903 100644 --- a/cmake_targets/autotests/test_case_list.xml +++ b/cmake_targets/autotests/test_case_list.xml @@ -1036,7 +1036,9 @@ execution polartest Test cases. (Test1: PBCH polar test), - (Test2: DCI polar test) + (Test2: DCI polar test), + (Test3: UCI polar test,6-bit CRC), + (Test4: UCI polar test,11-bit CRC) $OPENAIR_DIR/cmake_targets/build_oai --phy_simulators -c @@ -1044,8 +1046,10 @@ $OPENAIR_DIR/targets/bin/polartest.Rel15 -q -s-10 -f0 - -q -s-10 -f0 -m1 - polartest.test1 polartest.test2 + -q -s-10 -f0 -m1 + -q -s-2 -f2 -m2 -k12 + -q -s-2 -f2 -m2 -k20 + polartest.test1 polartest.test2 polartest.test3 polartest.test4 BLER= 0.000000 segmentation fault|assertion|exiting|fatal 3 From 62bb979b492d02188062fb21aba88bc47df27e1e Mon Sep 17 00:00:00 2001 From: "s.rampalli" Date: Thu, 14 May 2020 12:22:44 +0530 Subject: [PATCH 242/553] coding done need to verify testing part --- openair2/RRC/LTE/rrc_eNB.c | 83 +++++++++++++++++++++++++++-- openair2/RRC/NR/rrc_gNB.c | 23 ++++---- openair2/RRC/NR/rrc_gNB_internode.c | 2 +- openair2/RRC/NR/rrc_gNB_nsa.c | 8 +-- openair2/RRC/NR/rrc_gNB_reconfig.c | 15 +++++- 5 files changed, 112 insertions(+), 19 deletions(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index 3be5402e3e..89f06b7154 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -97,6 +97,7 @@ #include "SIMULATION/TOOLS/sim.h" // for taus #define ASN_MAX_ENCODE_SIZE 4096 +#define NUMBEROF_DRBS_TOBE_ADDED 1 static int encode_CG_ConfigInfo(char *buffer,int buffer_size,rrc_eNB_ue_context_t *const ue_context_pP,int *enc_size); static int is_en_dc_supported(LTE_UE_EUTRA_Capability_t *c); static void free_rb_config(struct NR_RadioBearerConfig *rb_config); @@ -2124,6 +2125,27 @@ rrc_eNB_generate_RRCConnectionReestablishmentReject( PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP), ue_p->Srb0.Tx_buffer.payload_size); } +#ifdef GES_ENDC_SUPPORT +void rrc_generate_SgNBReleaseRequest( + const protocol_ctxt_t *const ctxt_pP, + rrc_eNB_ue_context_t *const ue_context_pP +) +//----------------------------------------------------------------------------- +{ + MessageDef *msg; + msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_RELEASE_REQ); + memset(&(X2AP_ENDC_SGNB_RELEASE_REQ(msg)), 0, sizeof(x2ap_ENDC_sgnb_release_req_t)); + // X2AP_ENDC_SGNB_RELEASE_REQ(msg).MeNB_ue_x2_id = ; + // X2AP_ENDC_SGNB_RELEASE_REQ(msg).SgNB_ue_x2_id = ; + // X2AP_ENDC_SGNB_RELEASE_REQ(msg).cause = ; + // X2AP_ENDC_SGNB_RELEASE_REQ(msg).target_physCellId = ; + LOG_I(RRC, + "[eNB %d] frame %d UE rnti %x transmitting sgnb release request to sgnb \n", + ctxt_pP->module_id,ctxt_pP->frame,ctxt_pP->rnti); + itti_send_msg_to_task(TASK_X2AP, ENB_MODULE_ID_TO_INSTANCE(ctxt_pP->module_id), msg); + return; +} +#endif //----------------------------------------------------------------------------- /* @@ -2142,6 +2164,15 @@ rrc_eNB_generate_RRCConnectionRelease( memset(buffer, 0, RRC_BUF_SIZE); T(T_ENB_RRC_CONNECTION_RELEASE, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame), T_INT(ctxt_pP->subframe), T_INT(ctxt_pP->rnti)); +#ifdef GES_ENDC_SUPPORT + if(ue_context_pP != NULL) + { + if(ue_context_pP->ue_context.Status == RRC_NR_NSA) + { + //rrc_eNB_generate_SgNBReleaseRequest(ctxt_pP,ue_context_pP); + } + } +#endif size = do_RRCConnectionRelease(ctxt_pP->module_id, buffer,rrc_eNB_get_next_transaction_identifier(ctxt_pP->module_id)); ue_context_pP->ue_context.ue_reestablishment_timer = 0; ue_context_pP->ue_context.ue_release_timer = 0; @@ -4310,6 +4341,7 @@ static int encode_CG_ConfigInfo( asn_enc_rval_t enc_rval; int RRC_OK = 1; int index = 0; + char temp_buff[4096]; rb_config = calloc(1,sizeof( struct NR_RadioBearerConfig)); AssertFatal(rb_config != NULL,"failed to allocate memory for rb_config"); @@ -4322,7 +4354,7 @@ static int encode_CG_ConfigInfo( = calloc(ue_context_pP->ue_context.DRB_configList->list.count, sizeof(struct NR_DRB_ToAddMod)); AssertFatal( rb_config->drb_ToAddModList->list.array != NULL, "falied to allocate memory for list.array"); - for(index = 0;index < ue_context_pP->ue_context.DRB_configList->list.count;index++) { + for(index = 0;index < NUMBEROF_DRBS_TOBE_ADDED;index++) { rb_config->drb_ToAddModList->list.array[index] = calloc(1,sizeof(struct NR_DRB_ToAddMod)); AssertFatal(rb_config->drb_ToAddModList->list.array[index] != NULL, @@ -4339,7 +4371,30 @@ static int encode_CG_ConfigInfo( rb_config->drb_ToAddModList->list.array[index]->cnAssociation->choice.eps_BearerIdentity =*(ue_context_pP->ue_context.DRB_configList->list.array[index]->eps_BearerIdentity); } + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config = calloc(1,sizeof(struct NR_PDCP_Config)); + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb = calloc(1,sizeof(struct NR_PDCP_Config__drb)); + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->discardTimer = calloc(1,sizeof(long*)); + *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->discardTimer + = *(ue_context_pP->ue_context.DRB_configList->list.array[index]->pdcp_Config->discardTimer); + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeUL = calloc(1,sizeof(long*)); + *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeUL + = NR_PDCP_Config__drb__pdcp_SN_SizeUL_len18bits; + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeDL = calloc(1,sizeof(long*)); + *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeDL + = NR_PDCP_Config__drb__pdcp_SN_SizeDL_len18bits; + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->headerCompression.present + = NR_PDCP_Config__drb__headerCompression_PR_notUsed; + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->headerCompression.choice.notUsed = 0; + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->t_Reordering = calloc(1,sizeof(long*)); + *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->t_Reordering + = NR_PDCP_Config__t_Reordering_ms0; } + rb_config->securityConfig = calloc(1,sizeof(struct NR_SecurityConfig )); + rb_config->securityConfig->securityAlgorithmConfig = calloc(1,sizeof(struct NR_SecurityAlgorithmConfig)); + rb_config->securityConfig->securityAlgorithmConfig->cipheringAlgorithm = NR_CipheringAlgorithm_nea0; + rb_config->securityConfig->securityAlgorithmConfig->integrityProtAlgorithm = NULL; + rb_config->securityConfig->keyToUse = calloc(1,sizeof(long*)); + *rb_config->securityConfig->keyToUse = NR_SecurityConfig__keyToUse_master; } cg_configinfo = calloc(1,sizeof(struct NR_CG_ConfigInfo)); @@ -4358,7 +4413,17 @@ static int encode_CG_ConfigInfo( cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo = calloc(1,sizeof( OCTET_STRING_t)); AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> - ue_CapabilityInfo != NULL, "failed to allocate memory for ue_capabilityinfo"); + ue_CapabilityInfo != NULL, "failed to allocate memory for ue_capabilityinfo"); +#if 1 + enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,NULL, + (void*)ue_context_pP->ue_context.UE_Capability,temp_buff,4096); + AssertFatal(enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + OCTET_STRING_fromBuf( cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo, + (const char *)temp_buff,(enc_rval.encoded+7)>>3); +#endif + +#if 0 cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->size = ue_context_pP->ue_context.UE_Capability_size; cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf @@ -4367,8 +4432,19 @@ static int encode_CG_ConfigInfo( ue_CapabilityInfo->buf != NULL, "failed to allocate memory for buf"); memcpy(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf, ue_context_pP->ue_context.UE_Capability,ue_context_pP->ue_context.UE_Capability_size); +#endif +#if 1 cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config = calloc(1,sizeof(OCTET_STRING_t)); + AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> + mcg_RB_Config != NULL, "failed to allocate memory for mcg_rb_config"); + enc_rval = uper_encode_to_buffer(&asn_DEF_NR_RadioBearerConfig,NULL,(void *)rb_config,temp_buff,4096); + AssertFatal(enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + OCTET_STRING_fromBuf(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config, + (const char *)temp_buff, (enc_rval.encoded+7)>>3); +#endif +#if 0 AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> mcg_RB_Config != NULL, "failed to allocate memory for mcg_rb_config"); cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->size @@ -4379,8 +4455,9 @@ static int encode_CG_ConfigInfo( mcg_RB_Config->buf != NULL,"failed to allocate memory for buf"); memcpy(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf, rb_config,sizeof(struct NR_RadioBearerConfig)); +#endif // this xer_fprint can be enabled for additional debugging messages - // xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo,(void*)cg_configinfo); + xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo,(void*)cg_configinfo); enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CG_ConfigInfo,NULL,(void*)cg_configinfo, buffer,buffer_size); AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %lu)!\n", diff --git a/openair2/RRC/NR/rrc_gNB.c b/openair2/RRC/NR/rrc_gNB.c index c034663211..8ca8b94b61 100644 --- a/openair2/RRC/NR/rrc_gNB.c +++ b/openair2/RRC/NR/rrc_gNB.c @@ -302,11 +302,12 @@ char openair_rrc_gNB_configuration(const module_id_t gnb_mod_idP, gNB_RrcConfigu void rrc_gNB_process_AdditionRequestInformation(const module_id_t gnb_mod_idP, x2ap_ENDC_sgnb_addition_req_t *m) { - LTE_UL_DCCH_Message_t *LTE_UL_DCCH_Message = NULL; + //LTE_UL_DCCH_Message_t *LTE_UL_DCCH_Message = NULL; + struct NR_CG_ConfigInfo *cg_configinfo = NULL; asn_dec_rval_t dec_rval = uper_decode_complete( NULL, - &asn_DEF_LTE_UL_DCCH_Message, - (void **)<E_UL_DCCH_Message, + &asn_DEF_NR_CG_ConfigInfo, + (void **)&cg_configinfo, (uint8_t *)m->rrc_buffer, (int) m->rrc_buffer_size);//m->rrc_buffer_size); @@ -315,13 +316,14 @@ void rrc_gNB_process_AdditionRequestInformation(const module_id_t gnb_mod_idP, x if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { AssertFatal(1==0,"NR_UL_DCCH_MESSAGE decode error\n"); // free the memory - SEQUENCE_free( &asn_DEF_LTE_UL_DCCH_Message, LTE_UL_DCCH_Message, 1 ); + SEQUENCE_free(&asn_DEF_NR_CG_ConfigInfo, cg_configinfo, 1); return; } - xer_fprint(stdout,&asn_DEF_LTE_UL_DCCH_Message, LTE_UL_DCCH_Message); + xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo, cg_configinfo); // recreate enough of X2 EN-DC Container - AssertFatal(LTE_UL_DCCH_Message->message.choice.c1.present == LTE_UL_DCCH_MessageType__c1_PR_ueCapabilityInformation, + AssertFatal(cg_configinfo->criticalExtensions.choice.c1->present == NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo, "ueCapabilityInformation not present\n"); +#if 0 NR_CG_ConfigInfo_t *CG_ConfigInfo = calloc(1,sizeof(*CG_ConfigInfo)); CG_ConfigInfo->criticalExtensions.present = NR_CG_ConfigInfo__criticalExtensions_PR_c1; CG_ConfigInfo->criticalExtensions.choice.c1 = calloc(1,sizeof(*CG_ConfigInfo->criticalExtensions.choice.c1)); @@ -331,11 +333,12 @@ void rrc_gNB_process_AdditionRequestInformation(const module_id_t gnb_mod_idP, x cg_ConfigInfo->ue_CapabilityInfo = calloc(1,sizeof(*cg_ConfigInfo->ue_CapabilityInfo)); asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,NULL,(void*)<E_UL_DCCH_Message->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList,m->rrc_buffer,m->rrc_buffer_size); AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", - enc_rval.failed_type->name, enc_rval.encoded); + enc_rval.failed_type->name, enc_rval.encoded); OCTET_STRING_fromBuf(cg_ConfigInfo->ue_CapabilityInfo, - (const char *)m->rrc_buffer, - (enc_rval.encoded+7)>>3); - parse_CG_ConfigInfo(rrc,CG_ConfigInfo,m); + (const char *)m->rrc_buffer, + (enc_rval.encoded+7)>>3); +#endif + parse_CG_ConfigInfo(rrc,cg_configinfo,m); } diff --git a/openair2/RRC/NR/rrc_gNB_internode.c b/openair2/RRC/NR/rrc_gNB_internode.c index 916f4d63da..5a89f3a979 100644 --- a/openair2/RRC/NR/rrc_gNB_internode.c +++ b/openair2/RRC/NR/rrc_gNB_internode.c @@ -56,7 +56,7 @@ int parse_CG_ConfigInfo(gNB_RRC_INST *rrc, NR_CG_ConfigInfo_t *CG_ConfigInfo, x2 AssertFatal(1==0,"[InterNode] Failed to decode NR_UE_CapabilityRAT_ContainerList (%zu bits), size of OCTET_STRING %lu\n", dec_rval.consumed, cg_ConfigInfo->ue_CapabilityInfo->size); } - rrc_parse_ue_capabilities(rrc,UE_CapabilityRAT_ContainerList, m); + rrc_parse_ue_capabilities(rrc,UE_CapabilityRAT_ContainerList, m,cg_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo); } if (cg_ConfigInfo->candidateCellInfoListMN) AssertFatal(1==0,"Can't handle candidateCellInfoListMN yet\n"); } diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c index fe52dff8be..d6a3226915 100644 --- a/openair2/RRC/NR/rrc_gNB_nsa.c +++ b/openair2/RRC/NR/rrc_gNB_nsa.c @@ -39,7 +39,7 @@ #include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h" #include "openair2/RRC/LTE/rrc_eNB_GTPV1U.h" -void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList, x2ap_ENDC_sgnb_addition_req_t *m) { +void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList, x2ap_ENDC_sgnb_addition_req_t *m, struct NR_CG_ConfigInfo_IEs * cg_config_info) { struct rrc_gNB_ue_context_s *ue_context_p = NULL; OCTET_STRING_t *ueCapabilityRAT_Container_nr = NULL; @@ -98,10 +98,10 @@ void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_Container xer_fprint(stdout, &asn_DEF_NR_UE_MRDC_Capability, ue_context_p->ue_context.UE_Capability_MRDC); } - rrc_add_nsa_user(rrc,ue_context_p, m); + rrc_add_nsa_user(rrc,ue_context_p, m, cg_config_info); } -void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p, x2ap_ENDC_sgnb_addition_req_t *m) { +void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p, x2ap_ENDC_sgnb_addition_req_t *m, struct NR_CG_ConfigInfo_IEs * cg_config_info) { // generate nr-Config-r15 containers for LTE RRC : inside message for X2 EN-DC (CG-Config Message from 38.331) @@ -133,7 +133,7 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_ ue_context_p->ue_context.rb_config = calloc(1,sizeof(NR_RRCReconfiguration_t)); - fill_default_rbconfig(ue_context_p->ue_context.rb_config); + fill_default_rbconfig(ue_context_p->ue_context.rb_config,m, cg_config_info); ue_context_p->ue_id_rnti = ue_context_p->ue_context.secondaryCellGroup->spCellConfig->reconfigurationWithSync->newUE_Identity; NR_CG_Config_t *CG_Config = calloc(1,sizeof(*CG_Config)); memset((void*)CG_Config,0,sizeof(*CG_Config)); diff --git a/openair2/RRC/NR/rrc_gNB_reconfig.c b/openair2/RRC/NR/rrc_gNB_reconfig.c index 03c5e6ec95..dc25e8ee72 100644 --- a/openair2/RRC/NR/rrc_gNB_reconfig.c +++ b/openair2/RRC/NR/rrc_gNB_reconfig.c @@ -2032,8 +2032,20 @@ void fill_default_reconfig(NR_ServingCellConfigCommon_t *servingcellconfigcommon reconfig->nonCriticalExtension = NULL; } -void fill_default_rbconfig(NR_RadioBearerConfig_t *rbconfig) { +void fill_default_rbconfig(NR_RadioBearerConfig_t *rbconfig, x2ap_ENDC_sgnb_addition_req_t *m, struct NR_CG_ConfigInfo_IEs *cg_config_info) { + if(cg_config_info->mcg_RB_Config) { + asn_dec_rval dec_rval = uper_decode(NULL, + &asn_DEF_NR_RadioBearerConfig, + (void**)&rbconfig, + cg_config_info->mcg_RB_Config->buf, + cg_ConfigInfo->mcg_RB_Config->size, 0, 0); + if((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + AssertFatal(1==0,"[InterNode] Failed to decode mcg_rb_config (%zu bits), size of OCTET_STRING %lu\n", + dec_rval.consumed, cg_ConfigInfo->ue_CapabilityInfo->size); + } + } + #if 0 rbconfig->srb_ToAddModList = NULL; rbconfig->srb3_ToRelease = NULL; rbconfig->drb_ToAddModList = calloc(1,sizeof(*rbconfig->drb_ToAddModList)); @@ -2074,6 +2086,7 @@ void fill_default_rbconfig(NR_RadioBearerConfig_t *rbconfig) { rbconfig->securityConfig->securityAlgorithmConfig->integrityProtAlgorithm=NULL; rbconfig->securityConfig->keyToUse = calloc(1,sizeof(*rbconfig->securityConfig->keyToUse)); *rbconfig->securityConfig->keyToUse = NR_SecurityConfig__keyToUse_master; +#endif xer_fprint(stdout, &asn_DEF_NR_RadioBearerConfig, (const void*)rbconfig); } From 2792f8ce4a924bc728ac368d61b5d1b3d56fd0b4 Mon Sep 17 00:00:00 2001 From: "s.rampalli" Date: Thu, 14 May 2020 15:36:45 +0530 Subject: [PATCH 243/553] compilation done need to verify with GES endc setup --- openair2/RRC/LTE/rrc_eNB.c | 11 +++++++---- openair2/RRC/NR/nr_rrc_proto.h | 2 +- openair2/RRC/NR/rrc_gNB_internode.c | 2 +- openair2/RRC/NR/rrc_gNB_nsa.c | 25 +++++++++++++++++++------ openair2/RRC/NR/rrc_gNB_reconfig.c | 6 +++++- 5 files changed, 33 insertions(+), 13 deletions(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index 89f06b7154..098bb3823f 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -2126,6 +2126,7 @@ rrc_eNB_generate_RRCConnectionReestablishmentReject( ue_p->Srb0.Tx_buffer.payload_size); } #ifdef GES_ENDC_SUPPORT +#if 0 void rrc_generate_SgNBReleaseRequest( const protocol_ctxt_t *const ctxt_pP, rrc_eNB_ue_context_t *const ue_context_pP @@ -2146,7 +2147,7 @@ void rrc_generate_SgNBReleaseRequest( return; } #endif - +#endif //----------------------------------------------------------------------------- /* * Generate the RRC Connection Release to UE. @@ -2165,6 +2166,7 @@ rrc_eNB_generate_RRCConnectionRelease( T(T_ENB_RRC_CONNECTION_RELEASE, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame), T_INT(ctxt_pP->subframe), T_INT(ctxt_pP->rnti)); #ifdef GES_ENDC_SUPPORT +#if 0 if(ue_context_pP != NULL) { if(ue_context_pP->ue_context.Status == RRC_NR_NSA) @@ -2172,6 +2174,7 @@ rrc_eNB_generate_RRCConnectionRelease( //rrc_eNB_generate_SgNBReleaseRequest(ctxt_pP,ue_context_pP); } } +#endif #endif size = do_RRCConnectionRelease(ctxt_pP->module_id, buffer,rrc_eNB_get_next_transaction_identifier(ctxt_pP->module_id)); ue_context_pP->ue_context.ue_reestablishment_timer = 0; @@ -4341,7 +4344,7 @@ static int encode_CG_ConfigInfo( asn_enc_rval_t enc_rval; int RRC_OK = 1; int index = 0; - char temp_buff[4096]; + char temp_buff[ASN_MAX_ENCODE_SIZE]; rb_config = calloc(1,sizeof( struct NR_RadioBearerConfig)); AssertFatal(rb_config != NULL,"failed to allocate memory for rb_config"); @@ -4416,7 +4419,7 @@ static int encode_CG_ConfigInfo( ue_CapabilityInfo != NULL, "failed to allocate memory for ue_capabilityinfo"); #if 1 enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,NULL, - (void*)ue_context_pP->ue_context.UE_Capability,temp_buff,4096); + (void*)ue_context_pP->ue_context.UE_Capability,temp_buff,ASN_MAX_ENCODE_SIZE); AssertFatal(enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", enc_rval.failed_type->name, enc_rval.encoded); OCTET_STRING_fromBuf( cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo, @@ -4438,7 +4441,7 @@ static int encode_CG_ConfigInfo( = calloc(1,sizeof(OCTET_STRING_t)); AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> mcg_RB_Config != NULL, "failed to allocate memory for mcg_rb_config"); - enc_rval = uper_encode_to_buffer(&asn_DEF_NR_RadioBearerConfig,NULL,(void *)rb_config,temp_buff,4096); + enc_rval = uper_encode_to_buffer(&asn_DEF_NR_RadioBearerConfig,NULL,(void *)rb_config,temp_buff,ASN_MAX_ENCODE_SIZE); AssertFatal(enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", enc_rval.failed_type->name, enc_rval.encoded); OCTET_STRING_fromBuf(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config, diff --git a/openair2/RRC/NR/nr_rrc_proto.h b/openair2/RRC/NR/nr_rrc_proto.h index fd766f7e12..317282c814 100644 --- a/openair2/RRC/NR/nr_rrc_proto.h +++ b/openair2/RRC/NR/nr_rrc_proto.h @@ -65,7 +65,7 @@ void rrc_gNB_generate_SgNBAdditionRequestAcknowledge( struct rrc_gNB_ue_context_s *rrc_gNB_allocate_new_UE_context(gNB_RRC_INST *rrc_instance_pP); -void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc,LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList, x2ap_ENDC_sgnb_addition_req_t *m); +void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc,LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList, x2ap_ENDC_sgnb_addition_req_t *m, NR_CG_ConfigInfo_IEs_t * cg_config_info); void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p, x2ap_ENDC_sgnb_addition_req_t *m); diff --git a/openair2/RRC/NR/rrc_gNB_internode.c b/openair2/RRC/NR/rrc_gNB_internode.c index 5a89f3a979..092c63f96e 100644 --- a/openair2/RRC/NR/rrc_gNB_internode.c +++ b/openair2/RRC/NR/rrc_gNB_internode.c @@ -56,7 +56,7 @@ int parse_CG_ConfigInfo(gNB_RRC_INST *rrc, NR_CG_ConfigInfo_t *CG_ConfigInfo, x2 AssertFatal(1==0,"[InterNode] Failed to decode NR_UE_CapabilityRAT_ContainerList (%zu bits), size of OCTET_STRING %lu\n", dec_rval.consumed, cg_ConfigInfo->ue_CapabilityInfo->size); } - rrc_parse_ue_capabilities(rrc,UE_CapabilityRAT_ContainerList, m,cg_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo); + rrc_parse_ue_capabilities(rrc,UE_CapabilityRAT_ContainerList, m,cg_ConfigInfo); } if (cg_ConfigInfo->candidateCellInfoListMN) AssertFatal(1==0,"Can't handle candidateCellInfoListMN yet\n"); } diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c index d6a3226915..7057fcf53a 100644 --- a/openair2/RRC/NR/rrc_gNB_nsa.c +++ b/openair2/RRC/NR/rrc_gNB_nsa.c @@ -39,7 +39,7 @@ #include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h" #include "openair2/RRC/LTE/rrc_eNB_GTPV1U.h" -void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList, x2ap_ENDC_sgnb_addition_req_t *m, struct NR_CG_ConfigInfo_IEs * cg_config_info) { +void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList, x2ap_ENDC_sgnb_addition_req_t *m, NR_CG_ConfigInfo_IEs_t *cg_config_info) { struct rrc_gNB_ue_context_s *ue_context_p = NULL; OCTET_STRING_t *ueCapabilityRAT_Container_nr = NULL; @@ -96,12 +96,25 @@ void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_Container if ( LOG_DEBUGFLAG(DEBUG_ASN1 && ueCapabilityRAT_Container_MRDC != NULL) ) { xer_fprint(stdout, &asn_DEF_NR_UE_MRDC_Capability, ue_context_p->ue_context.UE_Capability_MRDC); - } - - rrc_add_nsa_user(rrc,ue_context_p, m, cg_config_info); + } + + if(cg_config_info->mcg_RB_Config) { + asn_dec_rval_t dec_rval = uper_decode(NULL, + &asn_DEF_NR_RadioBearerConfig, + (void**)&ue_context_p->ue_context.rb_config, + cg_config_info->mcg_RB_Config->buf, + cg_config_info->mcg_RB_Config->size, 0, 0); + + if((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + AssertFatal(1==0,"[InterNode] Failed to decode mcg_rb_config (%zu bits), size of OCTET_STRING %lu\n", + dec_rval.consumed, cg_config_info->mcg_RB_Config->size); + } + } + xer_fprint(stdout, &asn_DEF_NR_RadioBearerConfig, (const void*)ue_context_p->ue_context.rb_config); + rrc_add_nsa_user(rrc,ue_context_p, m); } -void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p, x2ap_ENDC_sgnb_addition_req_t *m, struct NR_CG_ConfigInfo_IEs * cg_config_info) { +void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p, x2ap_ENDC_sgnb_addition_req_t *m) { // generate nr-Config-r15 containers for LTE RRC : inside message for X2 EN-DC (CG-Config Message from 38.331) @@ -133,7 +146,7 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_ ue_context_p->ue_context.rb_config = calloc(1,sizeof(NR_RRCReconfiguration_t)); - fill_default_rbconfig(ue_context_p->ue_context.rb_config,m, cg_config_info); + //fill_default_rbconfig(ue_context_p->ue_context.rb_config,m, cg_config_info); ue_context_p->ue_id_rnti = ue_context_p->ue_context.secondaryCellGroup->spCellConfig->reconfigurationWithSync->newUE_Identity; NR_CG_Config_t *CG_Config = calloc(1,sizeof(*CG_Config)); memset((void*)CG_Config,0,sizeof(*CG_Config)); diff --git a/openair2/RRC/NR/rrc_gNB_reconfig.c b/openair2/RRC/NR/rrc_gNB_reconfig.c index dc25e8ee72..fd8f93462f 100644 --- a/openair2/RRC/NR/rrc_gNB_reconfig.c +++ b/openair2/RRC/NR/rrc_gNB_reconfig.c @@ -2031,8 +2031,9 @@ void fill_default_reconfig(NR_ServingCellConfigCommon_t *servingcellconfigcommon // nonCriticalExtension reconfig->nonCriticalExtension = NULL; } - +#if 0 void fill_default_rbconfig(NR_RadioBearerConfig_t *rbconfig, x2ap_ENDC_sgnb_addition_req_t *m, struct NR_CG_ConfigInfo_IEs *cg_config_info) { +/* if(cg_config_info->mcg_RB_Config) { asn_dec_rval dec_rval = uper_decode(NULL, &asn_DEF_NR_RadioBearerConfig, @@ -2045,6 +2046,8 @@ void fill_default_rbconfig(NR_RadioBearerConfig_t *rbconfig, x2ap_ENDC_sgnb_addi dec_rval.consumed, cg_ConfigInfo->ue_CapabilityInfo->size); } } + */ + #if 0 rbconfig->srb_ToAddModList = NULL; rbconfig->srb3_ToRelease = NULL; @@ -2091,3 +2094,4 @@ void fill_default_rbconfig(NR_RadioBearerConfig_t *rbconfig, x2ap_ENDC_sgnb_addi xer_fprint(stdout, &asn_DEF_NR_RadioBearerConfig, (const void*)rbconfig); } #endif +#endif From 0add4fdb553b79e8c0e30ff0732f02111dae35b7 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 15 May 2020 09:14:30 +0200 Subject: [PATCH 244/553] bugfix in pucch timing indicator selection --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 742a74ed9f..8f5bef1cc7 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -1457,7 +1457,7 @@ void nr_update_pucch_scheduling(int Mod_idP, if (found == 1) { // computing slot in which pucch is scheduled sched_pucch->ul_slot = first_ul_slot_tdd + k + (slotP - (slotP % slots_per_tdd)); - sched_pucch->timing_indicator = pdsch_to_harq_feedback[i]; + sched_pucch->timing_indicator = i; // index in the list of timing indicators } else AssertFatal(1==0,"No Uplink slot available in accordance to allowed timing indicator\n"); From b5b78125c9786da8b6e9aa0671911caebabb2a75 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 15 May 2020 18:47:06 +0200 Subject: [PATCH 245/553] test scheduling of pucch reception --- openair1/PHY/NR_TRANSPORT/pucch_rx.c | 4 ++-- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 5 +++++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/pucch_rx.c b/openair1/PHY/NR_TRANSPORT/pucch_rx.c index 0e9a8b0a89..177217d23f 100644 --- a/openair1/PHY/NR_TRANSPORT/pucch_rx.c +++ b/openair1/PHY/NR_TRANSPORT/pucch_rx.c @@ -367,9 +367,9 @@ void nr_decode_pucch0(PHY_VARS_gNB *gNB, uint8_t xrtmag_dB = dB_fixed(xrtmag); -#ifdef DEBUG_NR_PUCCH_RX +//#ifdef DEBUG_NR_PUCCH_RX printf("PUCCH 0 : maxpos %d\n",maxpos); -#endif +//#endif index=maxpos; #endif diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index 4751fb1237..21bf6b1172 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -321,6 +321,8 @@ void nr_schedule_pucch(int Mod_idP, O_ack = curr_pucch->dai_c; O_uci = O_ack; // for now we are just sending acknacks in pucch + LOG_I(MAC, "Scheduling pucch reception for frame %d slot %d\n", frameP, slotP); + nr_configure_pucch(pucch_pdu, scc, ubwp, @@ -485,6 +487,9 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, if (is_nr_UL_slot(cc->ServingCellConfigCommon,slot_rxP)) { if (get_softmodem_params()->phy_test == 0) { + NR_sched_pucch *curr_pucch = UE_list->UE_sched_ctrl[UE_id].sched_pucch; + if (curr_pucch != NULL) + nr_schedule_pucch(module_idP, UE_id, frame_rxP, slot_rxP); schedule_nr_prach(module_idP, (frame_rxP+1)&1023, slot_rxP); nr_schedule_reception_msg3(module_idP, 0, frame_rxP, slot_rxP); } From 4e50e36ede4793fe1898a2c8cda129d5f035be68 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Sun, 17 May 2020 10:43:15 +0200 Subject: [PATCH 246/553] intermediate commit, pucch2 RX with polar still not complete --- openair1/PHY/CODING/TESTBENCH/polartest.c | 4 +- openair1/PHY/NR_TRANSPORT/pucch_rx.c | 376 ++++++++++++++-------- openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c | 25 +- openair1/SIMULATION/NR_PHY/pucchsim.c | 2 +- 4 files changed, 245 insertions(+), 162 deletions(-) diff --git a/openair1/PHY/CODING/TESTBENCH/polartest.c b/openair1/PHY/CODING/TESTBENCH/polartest.c index a07111a986..3df5b28983 100644 --- a/openair1/PHY/CODING/TESTBENCH/polartest.c +++ b/openair1/PHY/CODING/TESTBENCH/polartest.c @@ -121,9 +121,9 @@ int main(int argc, char *argv[]) crcTableInit(); if (polarMessageType == 0) { //PBCH - aggregation_level = NR_POLAR_PBCH_AGGREGATION_LEVEL; + aggregation_level = NR_POLAR_PBCH_AGGREGATION_LEVEL; } else if (polarMessageType == 1) { //DCI - coderLength = 108*aggregation_level; + coderLength = 108*aggregation_level; } else if (polarMessageType == 2) { //UCI //pucch2 parameters, 1 symbol, aggregation_level = NPRB AssertFatal(aggregation_level>2,"For UCI formats, aggregation (N_RB) should be > 2\n"); diff --git a/openair1/PHY/NR_TRANSPORT/pucch_rx.c b/openair1/PHY/NR_TRANSPORT/pucch_rx.c index 62ced5af9d..a822302c06 100644 --- a/openair1/PHY/NR_TRANSPORT/pucch_rx.c +++ b/openair1/PHY/NR_TRANSPORT/pucch_rx.c @@ -50,7 +50,7 @@ #include "T.h" -//#define DEBUG_NR_PUCCH_RX 1 +#define DEBUG_NR_PUCCH_RX 1 int get_pucch0_cs_lut_index(PHY_VARS_gNB *gNB,nfapi_nr_pucch_pdu_t* pucch_pdu) { @@ -871,6 +871,8 @@ __m256i *pucch2_lut[9]={pucch2_3bit, pucch2_10bit, pucch2_11bit}; +__m64 pucch2_polar_8bit[256*2]; + void init_pucch2_luts() { uint32_t out; @@ -879,7 +881,9 @@ void init_pucch2_luts() { for (int b=3;b<12;b++) { for (uint16_t i=0;i<(1< 0 ? -1 : 1; @@ -948,6 +952,26 @@ void init_pucch2_luts() { *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,15); } } + for (uint16_t i=0;i<256;i++) { + __m64 *lut_i=&pucch2_polar_8bit[i<<1]; + __m64 *lut_ip1=&pucch2_polar_8bit[1+(i<<1)]; + bit = (out&0x1) > 0 ? -1 : 1; + *lut_i = _mm_insert_pi16(*lut_i,bit,0); + bit = (out&0x2) > 0 ? -1 : 1; + *lut_ip1 = _mm_insert_pi16(*lut_ip1,bit,0); + bit = (out&0x4) > 0 ? -1 : 1; + *lut_i = _mm_insert_pi16(*lut_i,bit,1); + bit = (out&0x8) > 0 ? -1 : 1; + *lut_ip1 = _mm_insert_pi16(*lut_ip1,bit,1); + bit = (out&0x10) > 0 ? -1 : 1; + *lut_i = _mm_insert_pi16(*lut_i,bit,2); + bit = (out&0x20) > 0 ? -1 : 1; + *lut_ip1 = _mm_insert_pi16(*lut_ip1,bit,2); + bit = (out&0x40) > 0 ? -1 : 1; + *lut_i = _mm_insert_pi16(*lut_i,bit,3); + bit = (out&0x80) > 0 ? -1 : 1; + *lut_ip1 = _mm_insert_pi16(*lut_ip1,bit,3); + } } @@ -983,6 +1007,7 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB, int16_t r_im_ext2[Prx2][8*pucch_pdu->nr_of_symbols*pucch_pdu->prb_size] __attribute__((aligned(32))); int16_t rd_re_ext[Prx2][4*pucch_pdu->nr_of_symbols*pucch_pdu->prb_size] __attribute__((aligned(32))); int16_t rd_im_ext[Prx2][4*pucch_pdu->nr_of_symbols*pucch_pdu->prb_size] __attribute__((aligned(32))); + int16_t *r_re_ext_p,*r_im_ext_p,*rd_re_ext_p,*rd_im_ext_p; int16_t *rp[Prx2]; __m64 dmrs_re,dmrs_im; @@ -1003,66 +1028,71 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB, // 24 PRBs contains 48x16-bit, so 6x8x16-bit for (int prb=0;prbprb_size;prb+=2) { for (int aa=0;aa (%d,%d)\n",aa,prb+(i>>2),i,rd_re_ext[aa][i],rd_im_ext[aa],i); + for (int i=0;i<8;i++) printf("Ant %d PRB %d dmrs[%d] -> (%d,%d)\n",aa,prb+(i>>2),i,rd_re_ext_p[i],rd_im_ext_p[i],i); #endif + rp[aa]+=48; } // aa } // prb @@ -1076,7 +1106,6 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB, #endif s = lte_gold_generic(&x1, &x2, 1); - for (int group=0;group>=5; corr32_im[group][aa]>>=5; #ifdef DEBUG_NR_PUCCH_RX @@ -1144,7 +1178,7 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB, #endif } //aa - if ((group&3) == 3) s = lte_gold_generic(&x1, &x2, 0); + if ((group&1) == 1) s = lte_gold_generic(&x1, &x2, 0); } // group } else { // 2 symbol case @@ -1262,23 +1296,106 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB, s = lte_gold_generic(&x1, &x2, 0); } AssertFatal(pucch_pdu->bit_len_csi_part1 + pucch_pdu->bit_len_csi_part2 == 0,"no csi for now\n"); - AssertFatal((pucch_pdu->bit_len_harq+pucch_pdu->sr_flag > 2 ) && (pucch_pdu->bit_len_harq+pucch_pdu->sr_flag < 12),"illegal length (%d,%d)\n",pucch_pdu->bit_len_harq,pucch_pdu->sr_flag); + AssertFatal((pucch_pdu->bit_len_harq+pucch_pdu->sr_flag > 2 ) && (pucch_pdu->bit_len_harq+pucch_pdu->sr_flag < 65),"illegal length (%d,%d)\n",pucch_pdu->bit_len_harq,pucch_pdu->sr_flag); int nb_bit = pucch_pdu->bit_len_harq+pucch_pdu->sr_flag; - __m256i *rp_re[Prx2]; - __m256i *rp2_re[Prx2]; - __m256i *rp_im[Prx2]; - __m256i *rp2_im[Prx2]; - for (int aa=0;aa>1], + ((int16_t*)&pucch2_lut[nb_bit-3][cw<<1])[1+(i>>1)]); + } + printf("\n"); +#endif + // do complex correlation + for (int aa=0;aa corr) { + corr = corr_tmp; + cw_ML=cw; + } + } + uint8_t corr_dB = dB_fixed64((uint64_t)corr); + LOG_D(PHY,"cw_ML %d, metric %d dB\n",cw_ML,corr_dB); + uci_pdu->harq.harq_bit_len = pucch_pdu->bit_len_harq; + + + int harq_bytes=pucch_pdu->bit_len_harq>>3; + if ((pucch_pdu->bit_len_harq&7) > 0) harq_bytes++; + uci_pdu->harq.harq_payload = (nfapi_nr_harq_t*)malloc(harq_bytes); + uci_pdu->harq.harq_crc = 2; + for (int i=0;iharq.harq_payload[i] = cw_ML & 255; + cw_ML>>=8; + } + + if (pucch_pdu->sr_flag == 1) { + uci_pdu->sr.sr_bit_len = 1; + uci_pdu->sr.sr_payload = malloc(1); + uci_pdu->sr.sr_payload[0] = cw_ML; + } + } + else { // polar coded case + __m64 *rp_re[Prx2]; + __m64 *rp2_re[Prx2]; + __m64 *rp_im[Prx2]; + __m64 *rp2_im[Prx2]; + for (int aa=0;aa corr) { - corr = corr_tmp; - cw_ML=cw; - } + } - uint8_t corr_dB = dB_fixed64((uint64_t)corr); - LOG_D(PHY,"cw_ML %d, metric %d dB\n",cw_ML,corr_dB); - uci_pdu->harq.harq_bit_len = pucch_pdu->bit_len_harq; + // non-coherent LLR computation on groups of 4 REs (half-PRBs) + for (in half_prb=0;half_prb<(2*pucch_pdu->prb_size);half_prb++) { + for (int cw=0;cw<256;cw++) { + for (int aa=0;aabit_len_harq>>3; - if ((pucch_pdu->bit_len_harq&7) > 0) harq_bytes++; - uci_pdu->harq.harq_payload = (nfapi_nr_harq_t*)malloc(harq_bytes); - uci_pdu->harq.harq_crc = 2; - for (int i=0;iharq.harq_payload[i] = cw_ML & 255; - cw_ML>>=8; + + LOG_D(PHY,"pucch2 half_prb %d cw %d aa %d: (%d,%d)+(%d,%d) = (%d,%d)\n",half_prb,cw,aa, + corr32_re[half_prb>>2][aa],corr32_im[half_prb>>2][aa], + ((int16_t*)(&prod_re[aa]))[0], + ((int16_t*)(&prod_im[aa]))[0], + corr32_re[half_prb>>2][aa]+((int16_t*)(&prod_re[aa]))[0], + corr32_im[half_prb>>2][aa]+((int16_t*)(&prod_im[aa]))[0]); + + corr_re = ( corr32_re[half_prb>>2][aa]+((int16_t*)(&prod_re[aa]))[0]); + corr_im = ( corr32_im[half_prb>>2][aa]+((int16_t*)(&prod_im[aa]))[0]); + corr_tmp += corr_re*corr_re + corr_im*corr_im; + } + int64_t corr_tmp = corr_re*corr_re + corr_im*corr_im; } - - if (pucch_pdu->sr_flag == 1) { - uci_pdu->sr.sr_bit_len = 1; - uci_pdu->sr.sr_payload = malloc(1); - uci_pdu->sr.sr_payload[0] = cw_ML; + AssertFatal(1==0,"stopping here\n"); } } diff --git a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c index 2a08d54c5a..5b7734865b 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c +++ b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c @@ -908,24 +908,13 @@ void nr_uci_encoding(uint64_t payload, // CRC bits are not attached, and coding small block lengths (subclause 5.3.3) b[0] = encodeSmallBlock((uint16_t*)&payload,A); } else if (A>=12) { - AssertFatal(1==0,"Polar encoding not supported yet for UCI\n"); - // procedure in subclause 6.3.1.2.1 (UCI encoded by Polar code -> subclause 6.3.1.3.1) - /*if ((A>=360 && E>=1088)||(A>=1013)) { - I_seg = 1; - } else { - I_seg = 0; - }*/ - - /*if (A>=20) { - // parity bits (subclause 5.2.1) computed by setting L=11 and using generator polynomial gCRC11(D) (subclause 5.1) - L=11; - } else if (A<=19) { - // parity bits (subclause 5.2.1) computed by setting L=6 and using generator polynomial gCRC6(D) (subclause 5.1) - L=6; - }*/ - - // code block segmentation and CRC attachment is performed according to subclause 5.2.1 - // polar coding subclause 5.3.1 + AssertFatal(A<65,"Polar encoding not supported yet for UCI with more than 64 bits\n"); + t_nrPolar_params *currentPtr = nr_polar_params(NR_POLAR_UCI_PUCCH_MESSAGE_TYPE, + A, + nrofPRB, + 1, + NULL); + polar_encoder_fast(&payload, b, 0,0,currentPtr); } } diff --git a/openair1/SIMULATION/NR_PHY/pucchsim.c b/openair1/SIMULATION/NR_PHY/pucchsim.c index d36f42f6c6..aefec7bed3 100644 --- a/openair1/SIMULATION/NR_PHY/pucchsim.c +++ b/openair1/SIMULATION/NR_PHY/pucchsim.c @@ -336,7 +336,7 @@ int main(int argc, char **argv) } AssertFatal(((format < 2)&&(nr_bit<3)&&(actual_payload<4)) || - ((format == 2)&&(nr_bit>2)&&(nr_bit<12)),"illegal combination format %d, nr_bit %d\n", + ((format == 2)&&(nr_bit>2)&&(nr_bit<65)),"illegal combination format %d, nr_bit %d\n", format,nr_bit); actual_payload &= ((1< Date: Sun, 17 May 2020 13:03:24 +0200 Subject: [PATCH 247/553] Change pseudo-subheader byte of random ULSCH PDU (phytest) to an appropriate value - Apply a value which cannot be interpreted as any valid LCID at the MAC layer of the receiver gNB (as per 38.321 Table 6.2.1-2), to avoid forwarding the random PDU to the upper layers in noS1 mode. --- openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c | 4 ++-- openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c | 11 +++++------ 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c index c74bc16754..b098d0c561 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c @@ -715,10 +715,10 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, #ifdef DEBUG_ULSCH_DECODING LOG_I(PHY, "Decoder output (payload): \n"); - for (i = 0; i < harq_process->TBS / 8; i++) { + for (i = 0; i < harq_process->TBS ; i++) { //harq_process_ul_ue->a[i] = (unsigned char) rand(); //printf("a[%d]=0x%02x\n",i,harq_process_ul_ue->a[i]); - printf("0x%02x",harq_process->b[i]); + printf("%02x",harq_process->b[i]); } #endif diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c index b84726c82d..0b57067d25 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c @@ -193,15 +193,14 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, if (!IS_SOFTMODEM_NOS1 || !data_existing) { //Use zeros for the header bytes in noS1 mode, in order to make sure that the LCID is not valid //and block this traffic from being forwarded to the upper layers at the gNB - uint16_t payload_offset = 5; LOG_D(PHY, "Random data to be tranmsitted: \n"); - //Give the header bytes a dummy value (a value not corresponding to any valid LCID based on 38.321, Table 6.2.1-2) - //in order to block the random packet at the MAC layer of the receiver - for (i = 0; ia[i] = 64; + //Give the first byte a dummy value (a value not corresponding to any valid LCID based on 38.321, Table 6.2.1-2) + //in order to distinguish the PHY random packets at the MAC layer of the gNB receiver from the normal packets that should + //have a valid LCID (nr_process_mac_pdu function) + harq_process_ul_ue->a[0] = 0x31; - for (i = payload_offset; i < harq_process_ul_ue->TBS / 8; i++) { + for (i = 1; i < harq_process_ul_ue->TBS / 8; i++) { harq_process_ul_ue->a[i] = (unsigned char) rand(); //printf(" input encoder a[%d]=0x%02x\n",i,harq_process_ul_ue->a[i]); } From 54ca9ea5ab77730fbb8d7f4edfb5690c3a1e62b9 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Mon, 18 May 2020 12:57:24 +0200 Subject: [PATCH 248/553] fixed pucch procedures to use rrc struct in UE --- openair1/PHY/impl_defs_nr.h | 10 +- openair1/SCHED_NR_UE/fapi_nr_ue_l1.c | 4 +- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 6 + openair1/SCHED_NR_UE/pucch_uci_ue_nr.c | 208 +++++++++++++----- openair1/SCHED_NR_UE/pucch_uci_ue_nr.h | 14 +- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 2 +- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 14 +- 7 files changed, 180 insertions(+), 78 deletions(-) diff --git a/openair1/PHY/impl_defs_nr.h b/openair1/PHY/impl_defs_nr.h index 44f2e314ea..3e09f3f593 100644 --- a/openair1/PHY/impl_defs_nr.h +++ b/openair1/PHY/impl_defs_nr.h @@ -757,11 +757,11 @@ typedef struct { #define MAX_NR_OF_SPATIAL_RELATION_INFOS (8) typedef enum { - pucch_format0_nr = 0, - pucch_format1_nr = 1, - pucch_format2_nr = 2, - pucch_format3_nr = 3, - pucch_format4_nr = 4, + pucch_format0_nr = 1, + pucch_format1_nr = 2, + pucch_format2_nr = 3, + pucch_format3_nr = 4, + pucch_format4_nr = 5 } pucch_format_nr_t; typedef enum { diff --git a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c index a78024f70c..19f0f9312f 100644 --- a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c +++ b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c @@ -57,7 +57,7 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response) NR_UE_PDCCH *pdcch_vars = PHY_vars_UE_g[module_id][cc_id]->pdcch_vars[thread_id][0]; NR_UE_DLSCH_t *dlsch0 = PHY_vars_UE_g[module_id][cc_id]->dlsch[thread_id][0][0]; NR_UE_ULSCH_t *ulsch0 = PHY_vars_UE_g[module_id][cc_id]->ulsch[thread_id][0][0]; - //NR_DL_FRAME_PARMS frame_parms = PHY_vars_UE_g[module_id][cc_id]->frame_parms; + NR_DL_FRAME_PARMS frame_parms = PHY_vars_UE_g[module_id][cc_id]->frame_parms; PRACH_RESOURCES_t *prach_resources = PHY_vars_UE_g[module_id][cc_id]->prach_resources[0]; // PUCCH_ConfigCommon_nr_t *pucch_config_common = PHY_vars_UE_g[module_id][cc_id]->pucch_config_common_nr[0]; @@ -99,7 +99,7 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response) dlsch0_harq->rvidx = dlsch_config_pdu->rv; dlsch0->g_pucch = dlsch_config_pdu->accumulated_delta_PUCCH; dlsch0_harq->harq_ack.pucch_resource_indicator = dlsch_config_pdu->pucch_resource_id; - dlsch0_harq->harq_ack.slot_for_feedback_ack = dlsch_config_pdu->pdsch_to_harq_feedback_time_ind; + dlsch0_harq->harq_ack.slot_for_feedback_ack = (slot+dlsch_config_pdu->pdsch_to_harq_feedback_time_ind)%frame_parms.slots_per_frame; dlsch0_harq->Nl=1; dlsch0_harq->mcs_table=0; dlsch0_harq->harq_ack.rx_status = downlink_harq_process(dlsch0_harq, dlsch0->current_harq_pid, dlsch_config_pdu->ndi, dlsch0->rnti_type); diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 509f4b6021..f1406c45a2 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -2356,6 +2356,12 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, } // UE_mode==PUSCH */ + LOG_D(PHY, "Sending PUCCH\n"); + pucch_procedures_ue_nr(ue, + gNB_id, + proc, + TRUE); + LOG_D(PHY, "Sending data \n"); nr_ue_pusch_common_procedures(ue, harq_pid, diff --git a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c index 326c617dfb..61b304bc18 100644 --- a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c +++ b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c @@ -37,7 +37,6 @@ #include "PHY/defs_nr_UE.h" #include #include -#include "openair2/LAYER2/NR_MAC_UE/mac_proto.h" #ifndef NO_RAT_NR @@ -162,6 +161,8 @@ void nr_generate_pucch3_4(int32_t **txdataF, * *********************************************************************/ +static int bwp_id = 1; + bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_t *proc, bool reset_harq) { uint8_t sr_payload = 0; @@ -186,6 +187,9 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ int pucch_resource_id = MAX_NB_OF_PUCCH_RESOURCES; int pucch_resource_indicator = MAX_PUCCH_RESOURCE_INDICATOR; int n_HARQ_ACK; + NR_UE_MAC_INST_t *mac = get_mac_inst(0); + NR_PUCCH_Resource_t *pucch_resource; + //NR_UE_MAC_INST_t *mac = get_mac_inst(0); /* update current context */ @@ -212,11 +216,11 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ /* sr_payload = 1 means that this is a positive SR, sr_payload = 0 means that it is a negative SR */ sr_payload = nr_ue_get_SR(Mod_id, - CC_id, - frame_tx, - gNB_id, - 0,//ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti, - nr_tti_tx); // nr_tti_rx used for meas gap + CC_id, + frame_tx, + gNB_id, + 0,//ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti, + nr_tti_tx); // nr_tti_rx used for meas gap } else { sr_payload = 1; @@ -248,10 +252,10 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ } else { /* a resource set and a resource should be find according to payload size */ - pucch_resource_set = find_pucch_resource_set( ue, gNB_id, N_UCI); + pucch_resource_set = find_pucch_resource_set( mac, gNB_id, N_UCI); if (pucch_resource_set != MAX_NB_OF_PUCCH_RESOURCE_SETS) { pucch_resource_indicator = 0; - pucch_resource_id = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_ResourceSet[pucch_resource_set]->pucch_resource_id[pucch_resource_indicator]; /* get the first resource of the set */ + pucch_resource_id = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[pucch_resource_set]->resourceList.list.array[pucch_resource_indicator][0]; /* get the first resource of the set */ } else { LOG_W(PHY,"PUCCH no resource set found for CSI at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); @@ -297,7 +301,7 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ NR_UE_HARQ_STATUS_t *harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[dl_harq_pid]->harq_ack; - if (select_pucch_resource(ue, gNB_id, N_UCI, pucch_resource_indicator, &initial_pucch_id, &pucch_resource_set, + if (select_pucch_resource(ue, mac, gNB_id, N_UCI, pucch_resource_indicator, &initial_pucch_id, &pucch_resource_set, &pucch_resource_id, harq_status) == TRUE) { /* use of initial pucch configuration provided by system information 1 */ /***********************************************************************/ @@ -338,33 +342,42 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ /**********************************************/ else if ((pucch_resource_set != MAX_NB_OF_PUCCH_RESOURCE_SETS) && (pucch_resource_id != MAX_NB_OF_PUCCH_RESOURCES)) { /* check that current configuration is supported */ - if ((ue->cell_group_config.physicalCellGroupConfig.harq_ACK_SpatialBundlingPUCCH != FALSE) - || (ue->cell_group_config.physicalCellGroupConfig.pdsch_HARQ_ACK_Codebook != dynamic)) { + if ((mac->scg->physicalCellGroupConfig->harq_ACK_SpatialBundlingPUCCH[0] != FALSE) + || (mac->scg->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook != 1)) { LOG_E(PHY,"PUCCH Unsupported cell group configuration : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); return(FALSE); } - else if (ue->PDSCH_ServingCellConfig.codeBlockGroupTransmission != NULL) { + else if (mac->scg->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission != NULL) { LOG_E(PHY,"PUCCH Unsupported code block group for serving cell config : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); return(FALSE); } - format = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.format; - nb_symbols_total = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.nrofSymbols; - starting_symbol_index = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.startingSymbolIndex; - starting_prb = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->startingPRB; + pucch_resource = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceToAddModList->list.array[pucch_resource_id]; + format = pucch_resource->format.present; + nb_symbols_total = get_nb_symbols_pucch(pucch_resource, format); + starting_symbol_index = pucch_resource->startingPRB; + starting_prb = get_starting_symb_idx(pucch_resource, format); second_hop = starting_prb; - time_domain_occ = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.timeDomainOCC; /* format 1 only */ - occ_length = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.occ_length; /* format 4 only */ - occ_Index = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.occ_Index; /* format 4 only */ - - if ((format == pucch_format0_nr) || (format == pucch_format1_nr)) { - m_0 = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.initialCyclicShift; + if (format==pucch_format1_nr) + time_domain_occ = pucch_resource->format.choice.format1->timeDomainOCC; + if (format==pucch_format4_nr) { + occ_length = pucch_resource->format.choice.format4->occ_Length; + occ_Index = pucch_resource->format.choice.format4->occ_Index; } - else if ((format == pucch_format3_nr) || (format == pucch_format4_nr)) { - if (ue->pucch_config_dedicated_nr[gNB_id].formatConfig[format-1]->additionalDMRS == enable_feature) { + + m_0 = get_ics_pucch(pucch_resource, format); + if (format == pucch_format3_nr) { + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format3->choice.setup->additionalDMRS[0] == 1) { index_additional_dmrs = I_PUCCH_ADDITIONAL_DMRS; } + } + else if (format == pucch_format4_nr) { + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format4->choice.setup->additionalDMRS[0] == 1) { + index_additional_dmrs = I_PUCCH_ADDITIONAL_DMRS; + } + } - if (ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->intraSlotFrequencyHopping == feature_enabled) { + if ((format == pucch_format3_nr) || (format == pucch_format4_nr)) { + if (pucch_resource->intraSlotFrequencyHopping[0] == 1) { index_hopping = I_PUCCH_HOPING; } } @@ -383,6 +396,7 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ int O_CRC = 0; nb_symbols = nb_symbols_total; /* by default, it can be reduced due to symbols reserved for dmrs */ + pucch_resource = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceToAddModList->list.array[pucch_resource_id]; switch(format) { case pucch_format0_nr: @@ -399,14 +413,14 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ } case pucch_format2_nr: { - nb_of_prbs = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.nrofPRBs; + nb_of_prbs = pucch_resource->format.choice.format2->nrofPRBs; N_sc_ctrl_RB = N_SC_RB - 4; break; } case pucch_format3_nr: { - nb_of_prbs = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.nrofPRBs; - if (ue->pucch_config_dedicated_nr[gNB_id].formatConfig[format-1]->pi2PBSK == feature_enabled) { + nb_of_prbs = pucch_resource->format.choice.format3->nrofPRBs; + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format3->choice.setup->pi2BPSK[0] == 1) { Q_m = BITS_PER_SYMBOL_BPSK; /* set bpsk modulation type with 1 bit per modulation symbol */ } N_sc_ctrl_RB = N_SC_RB; @@ -415,7 +429,7 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ } case pucch_format4_nr: { - if (ue->pucch_config_dedicated_nr[gNB_id].formatConfig[format-1]->pi2PBSK == feature_enabled) { + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format4->choice.setup->pi2BPSK[0] == 1) { Q_m = BITS_PER_SYMBOL_BPSK; /* set bpsk modulation type with 1 bit per modulation symbol */ } nb_symbols = nb_symbols_excluding_dmrs[nb_symbols_total-4][index_additional_dmrs][index_hopping]; @@ -432,10 +446,10 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ /* drop CSI report if simultaneous HARQ-ACK/SR and periodic/semi-periodic CSI cannot be transmitted at the same time */ if (format != pucch_format0_nr) { - if (ue->pucch_config_dedicated_nr[gNB_id].formatConfig[format-1] != NULL) { - max_code_rate = code_rate_r_time_100[ue->pucch_config_dedicated_nr[gNB_id].formatConfig[format-1]->maxCodeRate]; /* it is code rate * 10 */ + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1 != NULL) { + max_code_rate = code_rate_r_time_100[mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1->choice.setup->maxCodeRate[0]]; /* it is code rate * 10 */ - if ((O_ACK != 0) && (ue->pucch_config_dedicated_nr[gNB_id].formatConfig[format-1]->simultaneousHARQ_ACK_CSI == disable_feature)) { + if ((O_ACK != 0) && (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1->choice.setup->simultaneousHARQ_ACK_CSI[0] == 0)) { N_UCI = N_UCI - O_CSI; O_CSI = cqi_status = ri_status = 0; csi_payload = 0; /* csi should be dropped in this case */ @@ -675,8 +689,9 @@ uint8_t get_downlink_ack(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_t int U_DAI_c = 0; int N_m_c_rx = 0; int V_DAI_m_DL = 0; + NR_UE_MAC_INST_t *mac = get_mac_inst(0); - if (ue->PDSCH_Config.maxNrofCodeWordsScheduledByDCI == nb_code_n2) { + if (mac->DLbwp[0]->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI[0] == 2) { two_transport_blocks = TRUE; number_of_code_word = 2; } @@ -752,8 +767,8 @@ uint8_t get_downlink_ack(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_t U_DAI_c = number_harq_feedback/number_of_code_word; N_m_c_rx = number_harq_feedback; int N_SPS_c = 0; /* FFS TODO_NR multicells and SPS are not supported at the moment */ - if (ue->cell_group_config.physicalCellGroupConfig.harq_ACK_SpatialBundlingPUCCH == FALSE) { - int N_TB_max_DL = ue->PDSCH_Config.maxNrofCodeWordsScheduledByDCI; + if (mac->scg->physicalCellGroupConfig->harq_ACK_SpatialBundlingPUCCH[0] == FALSE) { + int N_TB_max_DL = mac->DLbwp[0]->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI[0]; *n_HARQ_ACK = (((V_DAI_m_DL - U_DAI_c)%4) * N_TB_max_DL) + N_m_c_rx + N_SPS_c; NR_TST_PHY_PRINTF("PUCCH power n(%d) = ( V(%d) - U(%d) )mod4 * N_TB(%d) + N(%d) \n", *n_HARQ_ACK, V_DAI_m_DL, U_DAI_c, N_TB_max_DL, N_m_c_rx); } @@ -849,7 +864,7 @@ uint8_t get_downlink_ack(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_t * *********************************************************************/ -boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size, int pucch_resource_indicator, +boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, NR_UE_MAC_INST_t *mac, uint8_t gNB_id, int uci_size, int pucch_resource_indicator, int *initial_pucch_id, int *resource_set_id, int *resource_id, NR_UE_HARQ_STATUS_t *harq_status) { boolean_t resource_set_found = FALSE; @@ -857,18 +872,19 @@ boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size int current_resource_id = MAX_NB_OF_PUCCH_RESOURCES; pucch_format_nr_t format_pucch; int ready_pucch_resource_id = FALSE; /* in the case that it is already given */ + NR_PUCCH_Resource_t *pucch_resource; /* ini values to unset */ *initial_pucch_id = NB_INITIAL_PUCCH_RESOURCE; //*resource_set_id = MAX_NB_OF_PUCCH_RESOURCE_SETS; //*resource_id = MAX_NB_OF_PUCCH_RESOURCES; - if (ue->pucch_config_dedicated_nr[gNB_id].PUCCH_ResourceSet[0] == NULL) { + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[0] == NULL) { /* No resource set has been already configured so pucch_configCommon from Sib1 should be used in this case */ if (ue->UE_mode[gNB_id] != PUSCH) { - *initial_pucch_id = ue->pucch_config_common_nr[gNB_id].pucch_ResourceCommon; + *initial_pucch_id = mac->ULbwp[bwp_id-1]->bwp_Common->pucch_ConfigCommon->choice.setup->pucch_ResourceCommon; if (*initial_pucch_id >= NB_INITIAL_PUCCH_RESOURCE) { LOG_E(PHY,"PUCCH Invalid initial resource index : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); *initial_pucch_id = NB_INITIAL_PUCCH_RESOURCE; @@ -893,7 +909,7 @@ boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size } nb_symbols_for_tx = initial_pucch_resource[*initial_pucch_id].nrofSymbols; format_pucch = initial_pucch_resource[*initial_pucch_id].format; - if (check_pucch_format(ue, gNB_id, format_pucch, nb_symbols_for_tx, uci_size) == TRUE) { + if (check_pucch_format(mac, gNB_id, format_pucch, nb_symbols_for_tx, uci_size) == TRUE) { return (TRUE); } else { @@ -913,7 +929,7 @@ boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size -- This field can take integer values that are multiples of 4. Corresponds to L1 parameter 'N_2' or 'N_3' (see 38.213, section 9.2) */ /* look for the first resource set which supports uci_size number of bits for payload */ - pucch_resource_set_id = find_pucch_resource_set( ue, gNB_id, uci_size); + pucch_resource_set_id = find_pucch_resource_set(mac, gNB_id, uci_size); if (pucch_resource_set_id != MAX_NB_OF_PUCCH_RESOURCE_SETS) { resource_set_found = TRUE; } @@ -928,13 +944,13 @@ boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size if (resource_set_found == TRUE) { if (pucch_resource_indicator < MAX_PUCCH_RESOURCE_INDICATOR) { /* check if resource indexing by pucch_resource_indicator of this set is compatible */ - if ((ready_pucch_resource_id == TRUE) || (ue->pucch_config_dedicated_nr[gNB_id].PUCCH_ResourceSet[pucch_resource_set_id]->pucch_resource_id[pucch_resource_indicator] != MAX_NB_OF_PUCCH_RESOURCES)) { + if ((ready_pucch_resource_id == TRUE) || (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[pucch_resource_set_id]->resourceList.list.array[pucch_resource_indicator][0] != MAX_NB_OF_PUCCH_RESOURCES)) { if (ready_pucch_resource_id == TRUE) { current_resource_id = *resource_id; } else { - int R_PUCCH = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_ResourceSet[pucch_resource_set_id]->first_resources_set_R_PUCCH; + int R_PUCCH = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[pucch_resource_set_id]->resourceList.list.count; /* is it the first resource and its size exceeds 8 */ if ((pucch_resource_set_id == 0) && (R_PUCCH > MAX_NB_OF_PUCCH_RESOURCES_PER_SET_NOT_0)) { @@ -956,15 +972,22 @@ boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size current_resource_id = r_PUCCH; } else { - current_resource_id = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_ResourceSet[pucch_resource_set_id]->pucch_resource_id[pucch_resource_indicator]; + current_resource_id = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[pucch_resource_set_id]->resourceList.list.array[pucch_resource_indicator][0]; } } - if (ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[current_resource_id] != NULL) { - nb_symbols_for_tx = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[current_resource_id]->format_parameters.nrofSymbols; - format_pucch = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[current_resource_id]->format_parameters.format; + /*uint8_t pucch_resource_count = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceToAddModList.list.count; + for (uint8_t i=0; iULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceToAddModList.list.array[i]->pucch_ResourceId == current_resource_id) + pucch_resource = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceToAddModList.list.array[i]; + }*/ - if (check_pucch_format(ue, gNB_id, format_pucch, nb_symbols_for_tx, uci_size) == TRUE) { + pucch_resource = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceToAddModList->list.array[current_resource_id]; + if (pucch_resource != NULL) { + format_pucch = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceToAddModList->list.array[current_resource_id]->format.present; + nb_symbols_for_tx = get_nb_symbols_pucch(pucch_resource, format_pucch); + + if (check_pucch_format(mac, gNB_id, format_pucch, nb_symbols_for_tx, uci_size) == TRUE) { *resource_set_id = pucch_resource_set_id; *resource_id = current_resource_id; return (TRUE); @@ -1010,7 +1033,7 @@ boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size * *********************************************************************/ -int find_pucch_resource_set(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size) +int find_pucch_resource_set(NR_UE_MAC_INST_t *mac, uint8_t gNB_id, int uci_size) { int pucch_resource_set_id = 0; @@ -1023,8 +1046,8 @@ int find_pucch_resource_set(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size) */ /* look for the first resource set which supports uci_size number of bits for payload */ while (pucch_resource_set_id < MAX_NB_OF_PUCCH_RESOURCE_SETS) { - if (ue->pucch_config_dedicated_nr[gNB_id].PUCCH_ResourceSet[pucch_resource_set_id] != NULL) { - if (uci_size <= ue->pucch_config_dedicated_nr[gNB_id].PUCCH_ResourceSet[pucch_resource_set_id]->maxPayloadMinus1 + 1) { + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[pucch_resource_set_id] != NULL) { + if (uci_size <= mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[pucch_resource_set_id]->maxPayloadMinus1 + 1) { NR_TST_PHY_PRINTF("PUCCH found resource set %d \n", pucch_resource_set_id); return (pucch_resource_set_id); break; @@ -1053,18 +1076,37 @@ int find_pucch_resource_set(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size) * *********************************************************************/ -boolean_t check_pucch_format(PHY_VARS_NR_UE *ue, uint8_t gNB_id, pucch_format_nr_t format_pucch, int nb_symbols_for_tx, int uci_size) +boolean_t check_pucch_format(NR_UE_MAC_INST_t *mac, uint8_t gNB_id, pucch_format_nr_t format_pucch, int nb_symbols_for_tx, int uci_size) { pucch_format_nr_t selected_pucch_format; pucch_format_nr_t selected_pucch_format_second; + NR_SetupRelease_PUCCH_FormatConfig_t *identified_format; - if (format_pucch != pucch_format0_nr) { - if (ue->pucch_config_dedicated_nr[gNB_id].formatConfig[format_pucch-1] != NULL) { - if (ue->pucch_config_dedicated_nr[gNB_id].formatConfig[format_pucch-1]->nrofSlots != 1) { - LOG_E(PHY,"PUCCH not implemented multislots transmission : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); - return (FALSE); - } - } + switch (format_pucch) { + case pucch_format1_nr: + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1 != NULL) + identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1; + break; + + case pucch_format2_nr: + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format2 != NULL) + identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format2; + break; + + case pucch_format3_nr: + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format3 != NULL) + identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format3; + break; + + case pucch_format4_nr: + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format4 != NULL) + identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format4; + break; + } + + if (identified_format->choice.setup->nrofSlots != 1) { + LOG_E(PHY,"PUCCH not implemented multislots transmission : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); + return (FALSE); } if (nb_symbols_for_tx <= 2) { @@ -1215,4 +1257,54 @@ void set_csi_nr(int csi_status, uint32_t csi_payload) } } +uint8_t get_nb_symbols_pucch(NR_PUCCH_Resource_t *pucch_resource, pucch_format_nr_t format_type) +{ + switch (format_type) { + case pucch_format0_nr: + return pucch_resource->format.choice.format0->nrofSymbols; + + case pucch_format1_nr: + return pucch_resource->format.choice.format1->nrofSymbols; + + case pucch_format2_nr: + return pucch_resource->format.choice.format2->nrofSymbols; + + case pucch_format3_nr: + return pucch_resource->format.choice.format3->nrofSymbols; + + case pucch_format4_nr: + return pucch_resource->format.choice.format4->nrofSymbols; + } +} + +uint16_t get_starting_symb_idx(NR_PUCCH_Resource_t *pucch_resource, pucch_format_nr_t format_type) +{ + switch (format_type) { + case pucch_format0_nr: + return pucch_resource->format.choice.format0->startingSymbolIndex; + + case pucch_format1_nr: + return pucch_resource->format.choice.format1->startingSymbolIndex; + + case pucch_format2_nr: + return pucch_resource->format.choice.format2->startingSymbolIndex; + + case pucch_format3_nr: + return pucch_resource->format.choice.format3->startingSymbolIndex; + + case pucch_format4_nr: + return pucch_resource->format.choice.format4->startingSymbolIndex; + } +} + +int get_ics_pucch(NR_PUCCH_Resource_t *pucch_resource, pucch_format_nr_t format_type) +{ + switch (format_type) { + case pucch_format0_nr: + return pucch_resource->format.choice.format0->initialCyclicShift; + + case pucch_format1_nr: + return pucch_resource->format.choice.format1->initialCyclicShift; + } +} diff --git a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.h b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.h index 85cd969e26..8fea1d5ab3 100644 --- a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.h +++ b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.h @@ -41,6 +41,9 @@ /************** INCLUDE *******************************************/ #include "PHY/defs_nr_UE.h" +#include "openair2/LAYER2/NR_MAC_UE/mac_proto.h" +#include "openair2/LAYER2/NR_MAC_UE/mac_defs.h" +#include "RRC/NR_UE/rrc_proto.h" #ifdef DEFINE_VARIABLES_PUCCH_UE_NR_H #define EXTERN @@ -187,7 +190,7 @@ uint8_t get_downlink_ack(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_t @param resource_id pucch resource id if any @returns TRUE a pucch resource has been found FALSE no valid pucch resource */ -boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size, int pucch_resource_indicator, +boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, NR_UE_MAC_INST_t *mac, uint8_t gNB_id, int uci_size, int pucch_resource_indicator, int *initial_pucch_id, int *resource_set_id, int *resource_id, NR_UE_HARQ_STATUS_t *harq_status); /** \brief This function select a pucch resource set @@ -196,7 +199,7 @@ boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size @param uci size number of uci bits @returns number of the pucch resource set */ -int find_pucch_resource_set(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size); +int find_pucch_resource_set(NR_UE_MAC_INST_t *mac, uint8_t gNB_id, int uci_size); /** \brief This function check pucch format @param ue context @@ -206,7 +209,7 @@ int find_pucch_resource_set(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size); @param uci size number of uci bits @returns TRUE pucch format matched uci size and constraints, FALSE invalid pucch format */ -boolean_t check_pucch_format(PHY_VARS_NR_UE *ue, uint8_t gNB_id, pucch_format_nr_t format_pucch, int nb_symbols_for_tx, +boolean_t check_pucch_format(NR_UE_MAC_INST_t *mac, uint8_t gNB_id, pucch_format_nr_t format_pucch, int nb_symbols_for_tx, int uci_size); /** \brief This function selects a pucch resource @@ -232,4 +235,9 @@ int get_csi_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint32_t *csi_payload); void set_csi_nr(int csi_status, uint32_t csi_payload); +uint8_t get_nb_symbols_pucch(NR_PUCCH_Resource_t *pucch_resource, pucch_format_nr_t format_type); + +uint16_t get_starting_symb_idx(NR_PUCCH_Resource_t *pucch_resource, pucch_format_nr_t format_type); + +int get_ics_pucch(NR_PUCCH_Resource_t *pucch_resource, pucch_format_nr_t format_type); #endif /* PUCCH_UCI_UE_NR_H */ diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index 20ca1cd60b..bbf8e670b2 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -649,7 +649,7 @@ uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, dci_pdu->time_domain_assignment.nbits = (int)ceil(log2(num_entries)); size += dci_pdu->time_domain_assignment.nbits; // VRB to PRB mapping - if (pdsch_config->resourceAllocation == 1) { + if ((pdsch_config->resourceAllocation == 1) && (bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver != NULL)) { dci_pdu->vrb_to_prb_mapping.nbits = 1; size += dci_pdu->vrb_to_prb_mapping.nbits; } diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index e292a596a5..7082bb15f7 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -65,6 +65,7 @@ //#define ENABLE_MAC_PAYLOAD_DEBUG 1 #define DEBUG_EXTRACT_DCI 1 +extern int bwp_id; extern dci_pdu_rel15_t *def_dci_pdu_rel15; extern void mac_rlc_data_ind ( @@ -1923,6 +1924,8 @@ int nr_ue_process_dci_indication_pdu(module_id_t module_id,int cc_id, int gNB_in int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format){ + int bwp_id = 1; + NR_UE_MAC_INST_t *mac = get_mac_inst(module_id); fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request; fapi_nr_ul_config_request_t *ul_config = &mac->ul_config_request; @@ -2518,17 +2521,10 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, dc if (dci->tpc == 2) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 1; if (dci->tpc == 3) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 3; /* PUCCH_RESOURCE_IND */ - if (dci->pucch_resource_indicator == 0) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 1st value of resourceList FIXME!!! - if (dci->pucch_resource_indicator == 1) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 2nd value of resourceList FIXME!! - if (dci->pucch_resource_indicator == 2) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 3rd value of resourceList FIXME!! - if (dci->pucch_resource_indicator == 3) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 4th value of resourceList FIXME!! - if (dci->pucch_resource_indicator == 4) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 5th value of resourceList FIXME!! - if (dci->pucch_resource_indicator == 5) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 6th value of resourceList FIXME!! - if (dci->pucch_resource_indicator == 6) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 7th value of resourceList FIXME!! - if (dci->pucch_resource_indicator == 7) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 8th value of resourceList FIXME!! + dlsch_config_pdu_1_1->pucch_resource_id = dci->pucch_resource_indicator; /* PDSCH_TO_HARQ_FEEDBACK_TIME_IND */ // according to TS 38.213 Table 9.2.3-1 - dlsch_config_pdu_1_1-> pdsch_to_harq_feedback_time_ind = mac->phy_config.config_req.ul_bwp_dedicated.pucch_config_dedicated.dl_data_to_ul_ack[dci->pdsch_to_harq_feedback_timing_indicator.val]; + dlsch_config_pdu_1_1->pdsch_to_harq_feedback_time_ind = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK->list.array[dci->pdsch_to_harq_feedback_timing_indicator.val][0]; /* ANTENNA_PORTS */ uint8_t n_codewords = 1; // FIXME!!! if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 1) && From 49991e100b263984d2346a5d6b99cbb39778fedb Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Tue, 19 May 2020 19:09:29 +0200 Subject: [PATCH 249/553] bugfix for 2 acknacks in pucch0 --- .../LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 8f5bef1cc7..4df24d7a16 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -1476,9 +1476,10 @@ void nr_update_pucch_scheduling(int Mod_idP, if (found == 0) i++; } if (found == 1) { // scheduling this harq-ack in current pucch - sched_pucch = curr_pucch; - sched_pucch->dai_c = 1 + sched_pucch->dai_c; - sched_pucch->timing_indicator = pdsch_to_harq_feedback[i]; + curr_pucch->dai_c = 1 + curr_pucch->dai_c; + memcpy(sched_pucch,curr_pucch,sizeof(NR_sched_pucch)); + sched_pucch->timing_indicator = i; + return; } } if (curr_pucch->dai_c==MAX_ACK_BITS || found == 0) { // if current pucch is full or no timing indicator allowed @@ -1498,7 +1499,7 @@ void nr_update_pucch_scheduling(int Mod_idP, sched_pucch->next_sched_pucch = curr_pucch; sched_pucch->dai_c = 1; sched_pucch->resource_indicator = 0; // in phytest with only 1 UE we are using just the 1st resource - sched_pucch->timing_indicator = pdsch_to_harq_feedback[i]; + sched_pucch->timing_indicator = i; UE_list->UE_sched_ctrl[UE_id].sched_pucch = sched_pucch; } else { @@ -1508,7 +1509,7 @@ void nr_update_pucch_scheduling(int Mod_idP, sched_pucch->frame = frameP; sched_pucch->next_sched_pucch = NULL; sched_pucch->dai_c = 1; - sched_pucch->timing_indicator = pdsch_to_harq_feedback[i]; + sched_pucch->timing_indicator = i; sched_pucch->resource_indicator = 0; // in phytest with only 1 UE we are using just the 1st resource sched_pucch->ul_slot = k + (slotP - (slotP % slots_per_tdd)); curr_pucch->next_sched_pucch = (NR_sched_pucch*) malloc(sizeof(NR_sched_pucch)); @@ -1520,7 +1521,7 @@ void nr_update_pucch_scheduling(int Mod_idP, else { // scheduling this harq-ack in current pucch sched_pucch = curr_pucch; sched_pucch->dai_c = 1 + sched_pucch->dai_c; - sched_pucch->timing_indicator = pdsch_to_harq_feedback[i]; + sched_pucch->timing_indicator = i; } } } From dd8cb9844317f1933a6cff47da046df4438580a8 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Tue, 19 May 2020 23:58:28 +0200 Subject: [PATCH 250/553] added support in gNB and UE for long PRACH sequences. Tested format 0 with unitary simulation only. --- openair1/PHY/INIT/nr_init_ru.c | 4 +- openair1/PHY/NR_TRANSPORT/nr_prach.c | 11 +- openair1/PHY/NR_UE_TRANSPORT/nr_prach.c | 7 +- openair1/PHY/TOOLS/Makefile | 20 +- openair1/PHY/TOOLS/oai_dfts.c | 850 +++++++++++++++++- openair1/SIMULATION/NR_PHY/prachsim.c | 45 +- openair1/SIMULATION/TOOLS/taus.c | 3 +- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 1 + 8 files changed, 893 insertions(+), 48 deletions(-) diff --git a/openair1/PHY/INIT/nr_init_ru.c b/openair1/PHY/INIT/nr_init_ru.c index 60921da1cb..30700b4cc6 100644 --- a/openair1/PHY/INIT/nr_init_ru.c +++ b/openair1/PHY/INIT/nr_init_ru.c @@ -113,8 +113,8 @@ int nr_phy_init_RU(RU_t *ru) { ru->prach_rxsigF = (int16_t**)malloc(ru->nb_rx * sizeof(int16_t*)); for (i=0; inb_rx; i++) { - // for preamble format 1 and 2, more memory should be allocated - ru->prach_rxsigF[i] = (int16_t*)malloc16_clear( fp->ofdm_symbol_size*12*(1<prach_rxsigF[i] = (int16_t*)malloc16_clear( 4*98304*2*sizeof(int16_t) ); LOG_D(PHY,"[INIT] prach_vars->rxsigF[%d] = %p\n",i,ru->prach_rxsigF[i]); } diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index e317f71fbc..52ed4a5f19 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -283,6 +283,7 @@ void rx_nr_prach_ru(RU_t *ru, if (prachFormat == 0 || prachFormat == 1 || prachFormat == 2) { dftlen=49152; dft(DFT_49152,prach2,rxsigF[aa],1); + LOG_M("prach_rxsigF.m","prach_rxF0",rxsigF[aa],49152,1,1); } if (prachFormat == 1 || prachFormat == 2) { dft(DFT_49152,prach2+98304,rxsigF[aa]+98304,1); @@ -503,6 +504,7 @@ void rx_nr_prach_ru(RU_t *ru, } //Coherent combining of PRACH repetitions (assumes channel does not change, to be revisted for "long" PRACH) + LOG_D(PHY,"Doing PRACH combining of %d reptitions N_ZC %d\n",reps,N_ZC); int16_t rxsigF_tmp[N_ZC<<1]; // if (k+N_ZC > dftlen) { // PRACH signal is split around DC int16_t *rxsigF2=rxsigF[aa]; @@ -583,8 +585,6 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, restricted_set = cfg->restricted_set_config.value; - AssertFatal(prach_sequence_length == 1, "no support yet for long prachSequenceLength\n"); - uint8_t prach_fmt = prach_pdu->prach_format; uint16_t N_ZC = (prach_sequence_length==0)?839:139; @@ -624,7 +624,7 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, if (LOG_DEBUGFLAG(PRACH)){ int en = dB_fixed(signal_energy((int32_t*)&rxsigF[0][0],(N_ZC==839) ? 840: 140)); - if (en>60) LOG_I(PHY,"frame %d, subframe %d : Trying preamble %d \n",frame,subframe,preamble_index); + if (en>60) LOG_D(PHY,"frame %d, subframe %d : Trying preamble %d \n",frame,subframe,preamble_index); } if (restricted_set == 0) { // This is the relative offset in the root sequence table (5.7.2-4 from 36.211) for the given preamble index @@ -750,10 +750,10 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, prach_ifft[i] += ((int32_t)prach_ifft_tmp[i<<1]*(int32_t)prach_ifft_tmp[(i<<1)] + (int32_t)prach_ifft_tmp[1+(i<<1)]*(int32_t)prach_ifft_tmp[1+(i<<1)])>>10; } - if (LOG_DUMPFLAG(PRACH)) { + // if (LOG_DUMPFLAG(PRACH)) { if (aa==0) LOG_M("prach_rxF_comp0.m","prach_rxF_comp0",prachF,1024,1,1); if (aa==1) LOG_M("prach_rxF_comp1.m","prach_rxF_comp1",prachF,1024,1,1); - } + // } }// antennas_rx } // new dft @@ -766,6 +766,7 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, lev = (int32_t)prach_ifft[(preamble_shift2+i)]; levdB = dB_fixed_times10(lev); if (levdB>*max_preamble_energy) { + LOG_D(PHY,"preamble_index %d, delay %d en %d dB > %d dB\n",preamble_index,i,levdB,*max_preamble_energy); *max_preamble_energy = levdB; *max_preamble_delay = i; // Note: This has to be normalized to the 30.72 Ms/s sampling rate *max_preamble = preamble_index; diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c index 5c049f06c5..82af0b88e5 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c @@ -60,6 +60,7 @@ extern int64_t table_6_3_3_2_4_prachConfig_Index [256][10]; extern uint16_t nr_du[838]; extern int16_t nr_ru[2*839]; extern const char *prachfmt[9]; +extern const char *prachfmt03[4]; // Note: // - prach_fmt_id is an ID used to map to the corresponding PRACH format value in prachfmt @@ -210,9 +211,9 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t slot){ #ifdef NR_PRACH_DEBUG if (NCS>0) LOG_I(PHY, "PRACH [UE %d] generate PRACH for RootSeqIndex %d, Preamble Index %d, PRACH Format %s, NCS %d (N_ZC %d): Preamble_offset %d, Preamble_shift %d\n", Mod_id, - rootSequenceIndex, - preamble_index, - prachfmt[prach_fmt_id], + rootSequenceIndex, + preamble_index, + prach_sequence_length == 0 ? prachfmt03[prach_fmt_id] : prachfmt[prach_fmt_id], NCS, N_ZC, preamble_offset, diff --git a/openair1/PHY/TOOLS/Makefile b/openair1/PHY/TOOLS/Makefile index c71717dc87..a59700bb7c 100644 --- a/openair1/PHY/TOOLS/Makefile +++ b/openair1/PHY/TOOLS/Makefile @@ -1,16 +1,16 @@ -lte_dfts_sse4: lte_dfts.c - gcc-7 -O3 -std=gnu99 -msse4.1 -o lte_dfts_sse4 lte_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS +oai_dfts_sse4: oai_dfts.c + gcc-7 -O3 -std=gnu99 -msse4.1 -o oai_dfts_sse4 oai_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR_TARGETS/COMMON -I$$OPENAIR_TARGETS/ARCH/COMMON -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -I$$OPENAIR_HOME/common/utils/msc -I$$OPENAIR_HOME/nfapi/open-nFAPI/nfapi/public_inc -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS -lte_dfts_avx2: lte_dfts.c - gcc -O2 -std=gnu99 -mavx2 -g -ggdb -o lte_dfts_avx2 lte_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c $$OPENAIR_HOME/common/utils/backtrace.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS +oai_dfts_avx2: oai_dfts.c + gcc -O2 -std=gnu99 -mavx2 -g -ggdb -o oai_dfts_avx2 oai_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c $$OPENAIR_HOME/common/utils/backtrace.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR_TARGETS/COMMON -I$$OPENAIR_TARGETS/ARCH/COMMON -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -I$$OPENAIR_HOME/common/utils/msc -I$$OPENAIR_HOME/nfapi/open-nFAPI/nfapi/public_inc -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS -lte_dfts_avx2.s: lte_dfts.c - gcc -O2 -std=gnu99 -mavx2 -S lte_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c $$OPENAIR_HOME/common/utils/backtrace.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS +oai_dfts_avx2.s: oai_dfts.c + gcc -O2 -std=gnu99 -mavx2 -S oai_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c $$OPENAIR_HOME/common/utils/backtrace.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR_TARGETS/COMMON -I$$OPENAIR_TARGETS/ARCH/COMMON -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -I$$OPENAIR_HOME/common/utils/msc -I$$OPENAIR_HOME/nfapi/open-nFAPI/nfapi/public_inc -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS -lte_dfts_sse4.s: lte_dfts.c - gcc -O2 -std=gnu99 -msse4.1 -S lte_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c $$OPENAIR_HOME/common/utils/backtrace.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS +oai_dfts_sse4.s: oai_dfts.c + gcc -O2 -std=gnu99 -msse4.1 -S oai_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c $$OPENAIR_HOME/common/utils/backtrace.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR_TARGETS/COMMON -I$$OPENAIR_TARGETS/ARCH/COMMON -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -I$$OPENAIR_HOME/common/utils/msc -I$$OPENAIR_HOME/nfapi/open-nFAPI/nfapi/public_inc -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS -dft_cycles_avx2: lte_dfts_avx2 - ./lte_dfts_avx2 | egrep cycles +dft_cycles_avx2: oai_dfts_avx2 + ./oai_dfts_avx2 | egrep cycles diff --git a/openair1/PHY/TOOLS/oai_dfts.c b/openair1/PHY/TOOLS/oai_dfts.c index bb8c46592c..6ae852b127 100644 --- a/openair1/PHY/TOOLS/oai_dfts.c +++ b/openair1/PHY/TOOLS/oai_dfts.c @@ -5353,6 +5353,607 @@ void idft8192(int16_t *x,int16_t *y,unsigned char scale) #endif +int16_t tw16384[3*2*4096]; + +#ifndef __AVX2__ +void dft16384(int16_t *x,int16_t *y,unsigned char scale) +{ + + simd_q15_t xtmp[4096],ytmp[4096],*tw16384_128p=(simd_q15_t *)tw16384,*x128=(simd_q15_t *)x,*y128=(simd_q15_t *)y,*y128p=(simd_q15_t *)y; + simd_q15_t *ytmpp = &ytmp[0]; + int i,j; + + for (i=0,j=0; i<4096; i+=4,j++) { + transpose16_ooff(x128+i,xtmp+j,1024); + } + + + dft4096((int16_t*)(xtmp),(int16_t*)(ytmp),1); + dft4096((int16_t*)(xtmp+1024),(int16_t*)(ytmp+1024),1); + dft4096((int16_t*)(xtmp+2048),(int16_t*)(ytmp+2048),1); + dft4096((int16_t*)(xtmp+3072),(int16_t*)(ytmp+3072),1); + + for (i=0; i<1024; i++) { + bfly4(ytmpp,ytmpp+1024,ytmpp+2048,ytmpp+3072, + y128p,y128p+1024,y128p+2048,y128p+3072, + tw16384_128p,tw16384_128p+1024,tw16384_128p+2048); + tw16384_128p++; + y128p++; + ytmpp++; + } + + if (scale>0) { + + for (i=0; i<256; i++) { + y128[0] = shiftright_int16(y128[0],1); + y128[1] = shiftright_int16(y128[1],1); + y128[2] = shiftright_int16(y128[2],1); + y128[3] = shiftright_int16(y128[3],1); + y128[4] = shiftright_int16(y128[4],1); + y128[5] = shiftright_int16(y128[5],1); + y128[6] = shiftright_int16(y128[6],1); + y128[7] = shiftright_int16(y128[7],1); + y128[8] = shiftright_int16(y128[8],1); + y128[9] = shiftright_int16(y128[9],1); + y128[10] = shiftright_int16(y128[10],1); + y128[11] = shiftright_int16(y128[11],1); + y128[12] = shiftright_int16(y128[12],1); + y128[13] = shiftright_int16(y128[13],1); + y128[14] = shiftright_int16(y128[14],1); + y128[15] = shiftright_int16(y128[15],1); + + y128+=16; + } + + } + + _mm_empty(); + _m_empty(); + +} + + + +void idft16384(int16_t *x,int16_t *y,unsigned char scale) +{ + + simd_q15_t xtmp[4096],ytmp[4096],*tw16384_128p=(simd_q15_t *)tw16384,*x128=(simd_q15_t *)x,*y128=(simd_q15_t *)y,*y128p=(simd_q15_t *)y; + simd_q15_t *ytmpp = &ytmp[0]; + int i,j; + + for (i=0,j=0; i<4096; i+=4,j++) { + transpose16_ooff(x128+i,xtmp+j,1024); + } + + + idft4096((int16_t*)(xtmp),(int16_t*)(ytmp),1); + idft4096((int16_t*)(xtmp+1024),(int16_t*)(ytmp+1024),1); + idft4096((int16_t*)(xtmp+2048),(int16_t*)(ytmp+2048),1); + idft4096((int16_t*)(xtmp+3072),(int16_t*)(ytmp+3072),1); + + for (i=0; i<1024; i++) { + ibfly4(ytmpp,ytmpp+1024,ytmpp+2048,ytmpp+3072, + y128p,y128p+1024,y128p+2048,y128p+3072, + tw16384_128p,tw16384_128p+1024,tw16384_128p+2048); + tw16384_128p++; + y128p++; + ytmpp++; + } + + if (scale>0) { + + for (i=0; i<256; i++) { + y128[0] = shiftright_int16(y128[0],scale); + y128[1] = shiftright_int16(y128[1],scale); + y128[2] = shiftright_int16(y128[2],scale); + y128[3] = shiftright_int16(y128[3],scale); + y128[4] = shiftright_int16(y128[4],scale); + y128[5] = shiftright_int16(y128[5],scale); + y128[6] = shiftright_int16(y128[6],scale); + y128[7] = shiftright_int16(y128[7],scale); + y128[8] = shiftright_int16(y128[8],scale); + y128[9] = shiftright_int16(y128[9],scale); + y128[10] = shiftright_int16(y128[10],scale); + y128[11] = shiftright_int16(y128[11],scale); + y128[12] = shiftright_int16(y128[12],scale); + y128[13] = shiftright_int16(y128[13],scale); + y128[14] = shiftright_int16(y128[14],scale); + y128[15] = shiftright_int16(y128[15],scale); + + y128+=16; + } + + } + + _mm_empty(); + _m_empty(); + +} + +#else //__AVX2__ +void dft16384(int16_t *x,int16_t *y,unsigned char scale) +{ + + simd256_q15_t xtmp[2048],ytmp[2048],*tw16384_256p=(simd256_q15_t *)tw16384,*x256=(simd256_q15_t *)x,*y256=(simd256_q15_t *)y,*y256p=(simd256_q15_t *)y; + simd256_q15_t *ytmpp = &ytmp[0]; + int i,j; + + for (i=0,j=0; i<2048; i+=4,j++) { + transpose16_ooff_simd256(x256+i,xtmp+j,512); + } + + + dft4096((int16_t*)(xtmp),(int16_t*)(ytmp),1); + dft4096((int16_t*)(xtmp+512),(int16_t*)(ytmp+512),1); + dft4096((int16_t*)(xtmp+1024),(int16_t*)(ytmp+1024),1); + dft4096((int16_t*)(xtmp+1536),(int16_t*)(ytmp+1536),1); + + for (i=0; i<512; i++) { + bfly4_256(ytmpp,ytmpp+512,ytmpp+1024,ytmpp+1536, + y256p,y256p+512,y256p+1024,y256p+1536, + tw16384_256p,tw16384_256p+512,tw16384_256p+1024); + tw16384_256p++; + y256p++; + ytmpp++; + } + + if (scale>0) { + + for (i=0; i<128; i++) { + y256[0] = shiftright_int16_simd256(y256[0],1); + y256[1] = shiftright_int16_simd256(y256[1],1); + y256[2] = shiftright_int16_simd256(y256[2],1); + y256[3] = shiftright_int16_simd256(y256[3],1); + y256[4] = shiftright_int16_simd256(y256[4],1); + y256[5] = shiftright_int16_simd256(y256[5],1); + y256[6] = shiftright_int16_simd256(y256[6],1); + y256[7] = shiftright_int16_simd256(y256[7],1); + y256[8] = shiftright_int16_simd256(y256[8],1); + y256[9] = shiftright_int16_simd256(y256[9],1); + y256[10] = shiftright_int16_simd256(y256[10],1); + y256[11] = shiftright_int16_simd256(y256[11],1); + y256[12] = shiftright_int16_simd256(y256[12],1); + y256[13] = shiftright_int16_simd256(y256[13],1); + y256[14] = shiftright_int16_simd256(y256[14],1); + y256[15] = shiftright_int16_simd256(y256[15],1); + + y256+=16; + } + + } + + _mm_empty(); + _m_empty(); + +} + +void idft16384(int16_t *x,int16_t *y,unsigned char scale) +{ + + simd256_q15_t xtmp[2048],ytmp[2048],*tw16384_256p=(simd256_q15_t *)tw16384,*x256=(simd256_q15_t *)x,*y256=(simd256_q15_t *)y,*y256p=(simd256_q15_t *)y; + simd256_q15_t *ytmpp = &ytmp[0]; + int i,j; + + for (i=0,j=0; i<2048; i+=4,j++) { + transpose16_ooff_simd256(x256+i,xtmp+j,512); + } + + + idft4096((int16_t*)(xtmp),(int16_t*)(ytmp),1); + idft4096((int16_t*)(xtmp+512),(int16_t*)(ytmp+512),1); + idft4096((int16_t*)(xtmp+1024),(int16_t*)(ytmp+1024),1); + idft4096((int16_t*)(xtmp+1536),(int16_t*)(ytmp+1536),1); + + for (i=0; i<512; i++) { + ibfly4_256(ytmpp,ytmpp+512,ytmpp+1024,ytmpp+1536, + y256p,y256p+512,y256p+1024,y256p+1536, + tw16384_256p,tw16384_256p+512,tw16384_256p+1024); + tw16384_256p++; + y256p++; + ytmpp++; + } + + if (scale>0) { + + for (i=0; i<128; i++) { + y256[0] = shiftright_int16_simd256(y256[0],1); + y256[1] = shiftright_int16_simd256(y256[1],1); + y256[2] = shiftright_int16_simd256(y256[2],1); + y256[3] = shiftright_int16_simd256(y256[3],1); + y256[4] = shiftright_int16_simd256(y256[4],1); + y256[5] = shiftright_int16_simd256(y256[5],1); + y256[6] = shiftright_int16_simd256(y256[6],1); + y256[7] = shiftright_int16_simd256(y256[7],1); + y256[8] = shiftright_int16_simd256(y256[8],1); + y256[9] = shiftright_int16_simd256(y256[9],1); + y256[10] = shiftright_int16_simd256(y256[10],1); + y256[11] = shiftright_int16_simd256(y256[11],1); + y256[12] = shiftright_int16_simd256(y256[12],1); + y256[13] = shiftright_int16_simd256(y256[13],1); + y256[14] = shiftright_int16_simd256(y256[14],1); + y256[15] = shiftright_int16_simd256(y256[15],1); + + y256+=16; + } + + } + + _mm_empty(); + _m_empty(); + +} + +#endif //__AVX2__ + +int16_t tw32768[2*16384] __attribute__((aligned(32))); + +#ifndef __AVX2__ +void dft32768(int16_t *x,int16_t *y,unsigned char scale) +{ + + simdshort_q15_t xtmp[16384],*xtmpp,*x64 = (simdshort_q15_t *)x; + simd_q15_t ytmp[8192],*tw32768_128p=(simd_q15_t *)tw32768,*y128=(simd_q15_t *)y,*y128p=(simd_q15_t *)y; + simd_q15_t *ytmpp = &ytmp[0]; + int i; + simd_q15_t ONE_OVER_SQRT2_Q15_128 = set1_int16(ONE_OVER_SQRT2_Q15); + + xtmpp = xtmp; + + for (i=0; i<256; i++) { + transpose4_ooff(x64 ,xtmpp,8192); + transpose4_ooff(x64+2,xtmpp+1,8192); + transpose4_ooff(x64+4,xtmpp+2,8192); + transpose4_ooff(x64+6,xtmpp+3,8192); + transpose4_ooff(x64+8,xtmpp+4,8192); + transpose4_ooff(x64+10,xtmpp+5,8192); + transpose4_ooff(x64+12,xtmpp+6,8192); + transpose4_ooff(x64+14,xtmpp+7,8192); + transpose4_ooff(x64+16,xtmpp+8,8192); + transpose4_ooff(x64+18,xtmpp+9,8192); + transpose4_ooff(x64+20,xtmpp+10,8192); + transpose4_ooff(x64+22,xtmpp+11,8192); + transpose4_ooff(x64+24,xtmpp+12,8192); + transpose4_ooff(x64+26,xtmpp+13,8192); + transpose4_ooff(x64+28,xtmpp+14,8192); + transpose4_ooff(x64+30,xtmpp+15,8192); + transpose4_ooff(x64+32,xtmpp+16,8192); + transpose4_ooff(x64+34,xtmpp+17,8192); + transpose4_ooff(x64+36,xtmpp+18,8192); + transpose4_ooff(x64+38,xtmpp+19,8192); + transpose4_ooff(x64+40,xtmpp+20,8192); + transpose4_ooff(x64+42,xtmpp+21,8192); + transpose4_ooff(x64+44,xtmpp+22,8192); + transpose4_ooff(x64+46,xtmpp+23,8192); + transpose4_ooff(x64+48,xtmpp+24,8192); + transpose4_ooff(x64+50,xtmpp+25,8192); + transpose4_ooff(x64+52,xtmpp+26,8192); + transpose4_ooff(x64+54,xtmpp+27,8192); + transpose4_ooff(x64+56,xtmpp+28,8192); + transpose4_ooff(x64+58,xtmpp+29,8192); + transpose4_ooff(x64+60,xtmpp+30,8192); + transpose4_ooff(x64+62,xtmpp+31,8192); + x64+=64; + xtmpp+=32; + } + + dft16384((int16_t*)(xtmp),(int16_t*)ytmp,1); + dft16384((int16_t*)(xtmp+8192),(int16_t*)(ytmp+4096),1); + + + for (i=0; i<4096; i++) { + bfly2(ytmpp,ytmpp+4096, + y128p,y128p+4096, + tw32768_128p); + tw32768_128p++; + y128p++; + ytmpp++; + } + + if (scale>0) { + y128p = y128; + + for (i=0; i<512; i++) { + y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT2_Q15_128); + y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT2_Q15_128); + y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT2_Q15_128); + y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT2_Q15_128); + y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT2_Q15_128); + y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT2_Q15_128); + y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT2_Q15_128); + y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT2_Q15_128); + y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT2_Q15_128); + y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT2_Q15_128); + y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT2_Q15_128); + y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT2_Q15_128); + y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT2_Q15_128); + y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT2_Q15_128); + y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT2_Q15_128); + y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT2_Q15_128); + y128p+=16; + } + } + + _mm_empty(); + _m_empty(); + +} + +void idft32768(int16_t *x,int16_t *y,unsigned char scale) +{ + + simdshort_q15_t xtmp[16384],*xtmpp,*x64 = (simdshort_q15_t *)x; + simd_q15_t ytmp[8192],*tw32768_128p=(simd_q15_t *)tw32768,*y128=(simd_q15_t *)y,*y128p=(simd_q15_t *)y; + simd_q15_t *ytmpp = &ytmp[0]; + int i; + simd_q15_t ONE_OVER_SQRT2_Q15_128 = set1_int16(ONE_OVER_SQRT2_Q15); + + xtmpp = xtmp; + + for (i=0; i<256; i++) { + transpose4_ooff(x64 ,xtmpp,8192); + transpose4_ooff(x64+2,xtmpp+1,8192); + transpose4_ooff(x64+4,xtmpp+2,8192); + transpose4_ooff(x64+6,xtmpp+3,8192); + transpose4_ooff(x64+8,xtmpp+4,8192); + transpose4_ooff(x64+10,xtmpp+5,8192); + transpose4_ooff(x64+12,xtmpp+6,8192); + transpose4_ooff(x64+14,xtmpp+7,8192); + transpose4_ooff(x64+16,xtmpp+8,8192); + transpose4_ooff(x64+18,xtmpp+9,8192); + transpose4_ooff(x64+20,xtmpp+10,8192); + transpose4_ooff(x64+22,xtmpp+11,8192); + transpose4_ooff(x64+24,xtmpp+12,8192); + transpose4_ooff(x64+26,xtmpp+13,8192); + transpose4_ooff(x64+28,xtmpp+14,8192); + transpose4_ooff(x64+30,xtmpp+15,8192); + transpose4_ooff(x64+32,xtmpp+16,8192); + transpose4_ooff(x64+34,xtmpp+17,8192); + transpose4_ooff(x64+36,xtmpp+18,8192); + transpose4_ooff(x64+38,xtmpp+19,8192); + transpose4_ooff(x64+40,xtmpp+20,8192); + transpose4_ooff(x64+42,xtmpp+21,8192); + transpose4_ooff(x64+44,xtmpp+22,8192); + transpose4_ooff(x64+46,xtmpp+23,8192); + transpose4_ooff(x64+48,xtmpp+24,8192); + transpose4_ooff(x64+50,xtmpp+25,8192); + transpose4_ooff(x64+52,xtmpp+26,8192); + transpose4_ooff(x64+54,xtmpp+27,8192); + transpose4_ooff(x64+56,xtmpp+28,8192); + transpose4_ooff(x64+58,xtmpp+29,8192); + transpose4_ooff(x64+60,xtmpp+30,8192); + transpose4_ooff(x64+62,xtmpp+31,8192); + x64+=64; + xtmpp+=32; + } + + idft16384((int16_t*)(xtmp),(int16_t*)ytmp,1); + idft16384((int16_t*)(xtmp+8192),(int16_t*)(ytmp+4096),1); + + + for (i=0; i<4096; i++) { + ibfly2(ytmpp,ytmpp+4096, + y128p,y128p+4096, + tw32768_128p); + tw32768_128p++; + y128p++; + ytmpp++; + } + + if (scale>0) { + y128p = y128; + + for (i=0; i<512; i++) { + y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT2_Q15_128); + y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT2_Q15_128); + y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT2_Q15_128); + y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT2_Q15_128); + y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT2_Q15_128); + y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT2_Q15_128); + y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT2_Q15_128); + y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT2_Q15_128); + y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT2_Q15_128); + y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT2_Q15_128); + y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT2_Q15_128); + y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT2_Q15_128); + y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT2_Q15_128); + y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT2_Q15_128); + y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT2_Q15_128); + y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT2_Q15_128); + y128p+=16; + } + } + + _mm_empty(); + _m_empty(); + +} + +#else // __AVX2__ +void dft32768(int16_t *x,int16_t *y,unsigned char scale) +{ + + simd256_q15_t xtmp[4096],*xtmpp,*x256 = (simd256_q15_t *)x; + simd256_q15_t ytmp[4096],*tw32768_256p=(simd256_q15_t *)tw32768,*y256=(simd256_q15_t *)y,*y256p=(simd256_q15_t *)y; + + simd256_q15_t *ytmpp = &ytmp[0]; + int i; + simd256_q15_t ONE_OVER_SQRT2_Q15_128 = set1_int16_simd256(ONE_OVER_SQRT2_Q15); + + xtmpp = xtmp; + + for (i=0; i<256; i++) { + transpose4_ooff_simd256(x256 ,xtmpp,2048); + transpose4_ooff_simd256(x256+2,xtmpp+1,2048); + transpose4_ooff_simd256(x256+4,xtmpp+2,2048); + transpose4_ooff_simd256(x256+6,xtmpp+3,2048); + transpose4_ooff_simd256(x256+8,xtmpp+4,2048); + transpose4_ooff_simd256(x256+10,xtmpp+5,2048); + transpose4_ooff_simd256(x256+12,xtmpp+6,2048); + transpose4_ooff_simd256(x256+14,xtmpp+7,2048); + transpose4_ooff_simd256(x256+16,xtmpp+8,2048); + transpose4_ooff_simd256(x256+18,xtmpp+9,2048); + transpose4_ooff_simd256(x256+20,xtmpp+10,2048); + transpose4_ooff_simd256(x256+22,xtmpp+11,2048); + transpose4_ooff_simd256(x256+24,xtmpp+12,2048); + transpose4_ooff_simd256(x256+26,xtmpp+13,2048); + transpose4_ooff_simd256(x256+28,xtmpp+14,2048); + transpose4_ooff_simd256(x256+30,xtmpp+15,2048); + transpose4_ooff_simd256(x256+32,xtmpp+16,2048); + transpose4_ooff_simd256(x256+34,xtmpp+17,2048); + transpose4_ooff_simd256(x256+36,xtmpp+18,2048); + transpose4_ooff_simd256(x256+38,xtmpp+19,2048); + transpose4_ooff_simd256(x256+40,xtmpp+20,2048); + transpose4_ooff_simd256(x256+42,xtmpp+21,2048); + transpose4_ooff_simd256(x256+44,xtmpp+22,2048); + transpose4_ooff_simd256(x256+46,xtmpp+23,2048); + transpose4_ooff_simd256(x256+48,xtmpp+24,2048); + transpose4_ooff_simd256(x256+50,xtmpp+25,2048); + transpose4_ooff_simd256(x256+52,xtmpp+26,2048); + transpose4_ooff_simd256(x256+54,xtmpp+27,2048); + transpose4_ooff_simd256(x256+56,xtmpp+28,2048); + transpose4_ooff_simd256(x256+58,xtmpp+29,2048); + transpose4_ooff_simd256(x256+60,xtmpp+30,2048); + transpose4_ooff_simd256(x256+62,xtmpp+31,2048); + x256+=64; + xtmpp+=32; + } + + dft16384((int16_t*)(xtmp),(int16_t*)ytmp,1); + dft16384((int16_t*)(xtmp+2048),(int16_t*)(ytmp+2048),1); + + + for (i=0; i<2048; i++) { + bfly2_256(ytmpp,ytmpp+2048, + y256p,y256p+2048, + tw32768_256p); + tw32768_256p++; + y256p++; + ytmpp++; + } + + if (scale>0) { + y256p = y256; + + for (i=0; i<64; i++) { + y256p[0] = mulhi_int16_simd256(y256p[0],ONE_OVER_SQRT2_Q15_128); + y256p[1] = mulhi_int16_simd256(y256p[1],ONE_OVER_SQRT2_Q15_128); + y256p[2] = mulhi_int16_simd256(y256p[2],ONE_OVER_SQRT2_Q15_128); + y256p[3] = mulhi_int16_simd256(y256p[3],ONE_OVER_SQRT2_Q15_128); + y256p[4] = mulhi_int16_simd256(y256p[4],ONE_OVER_SQRT2_Q15_128); + y256p[5] = mulhi_int16_simd256(y256p[5],ONE_OVER_SQRT2_Q15_128); + y256p[6] = mulhi_int16_simd256(y256p[6],ONE_OVER_SQRT2_Q15_128); + y256p[7] = mulhi_int16_simd256(y256p[7],ONE_OVER_SQRT2_Q15_128); + y256p[8] = mulhi_int16_simd256(y256p[8],ONE_OVER_SQRT2_Q15_128); + y256p[9] = mulhi_int16_simd256(y256p[9],ONE_OVER_SQRT2_Q15_128); + y256p[10] = mulhi_int16_simd256(y256p[10],ONE_OVER_SQRT2_Q15_128); + y256p[11] = mulhi_int16_simd256(y256p[11],ONE_OVER_SQRT2_Q15_128); + y256p[12] = mulhi_int16_simd256(y256p[12],ONE_OVER_SQRT2_Q15_128); + y256p[13] = mulhi_int16_simd256(y256p[13],ONE_OVER_SQRT2_Q15_128); + y256p[14] = mulhi_int16_simd256(y256p[14],ONE_OVER_SQRT2_Q15_128); + y256p[15] = mulhi_int16_simd256(y256p[15],ONE_OVER_SQRT2_Q15_128); + y256p+=16; + } + } + + _mm_empty(); + _m_empty(); + +} + +void idft32768(int16_t *x,int16_t *y,unsigned char scale) +{ + + simd256_q15_t xtmp[4096],*xtmpp,*x256 = (simd256_q15_t *)x; + simd256_q15_t ytmp[4096],*tw32768_256p=(simd256_q15_t *)tw32768,*y256=(simd256_q15_t *)y,*y256p=(simd256_q15_t *)y; + simd256_q15_t *ytmpp = &ytmp[0]; + int i; + simd256_q15_t ONE_OVER_SQRT2_Q15_128 = set1_int16_simd256(ONE_OVER_SQRT2_Q15); + + xtmpp = xtmp; + + for (i=0; i<64; i++) { + transpose4_ooff_simd256(x256 ,xtmpp,2048); + transpose4_ooff_simd256(x256+2,xtmpp+1,2048); + transpose4_ooff_simd256(x256+4,xtmpp+2,2048); + transpose4_ooff_simd256(x256+6,xtmpp+3,2048); + transpose4_ooff_simd256(x256+8,xtmpp+4,2048); + transpose4_ooff_simd256(x256+10,xtmpp+5,2048); + transpose4_ooff_simd256(x256+12,xtmpp+6,2048); + transpose4_ooff_simd256(x256+14,xtmpp+7,2048); + transpose4_ooff_simd256(x256+16,xtmpp+8,2048); + transpose4_ooff_simd256(x256+18,xtmpp+9,2048); + transpose4_ooff_simd256(x256+20,xtmpp+10,2048); + transpose4_ooff_simd256(x256+22,xtmpp+11,2048); + transpose4_ooff_simd256(x256+24,xtmpp+12,2048); + transpose4_ooff_simd256(x256+26,xtmpp+13,2048); + transpose4_ooff_simd256(x256+28,xtmpp+14,2048); + transpose4_ooff_simd256(x256+30,xtmpp+15,2048); + transpose4_ooff_simd256(x256+32,xtmpp+16,2048); + transpose4_ooff_simd256(x256+34,xtmpp+17,2048); + transpose4_ooff_simd256(x256+36,xtmpp+18,2048); + transpose4_ooff_simd256(x256+38,xtmpp+19,2048); + transpose4_ooff_simd256(x256+40,xtmpp+20,2048); + transpose4_ooff_simd256(x256+42,xtmpp+21,2048); + transpose4_ooff_simd256(x256+44,xtmpp+22,2048); + transpose4_ooff_simd256(x256+46,xtmpp+23,2048); + transpose4_ooff_simd256(x256+48,xtmpp+24,2048); + transpose4_ooff_simd256(x256+50,xtmpp+25,2048); + transpose4_ooff_simd256(x256+52,xtmpp+26,2048); + transpose4_ooff_simd256(x256+54,xtmpp+27,2048); + transpose4_ooff_simd256(x256+56,xtmpp+28,2048); + transpose4_ooff_simd256(x256+58,xtmpp+29,2048); + transpose4_ooff_simd256(x256+60,xtmpp+30,2048); + transpose4_ooff_simd256(x256+62,xtmpp+31,2048); + x256+=64; + xtmpp+=32; + } + + idft16384((int16_t*)(xtmp),(int16_t*)ytmp,1); + idft16384((int16_t*)(xtmp+2048),(int16_t*)(ytmp+2048),1); + + + for (i=0; i<2048; i++) { + ibfly2_256(ytmpp,ytmpp+2048, + y256p,y256p+2048, + tw32768_256p); + tw32768_256p++; + y256p++; + ytmpp++; + } + + if (scale>0) { + y256p = y256; + + for (i=0; i<256; i++) { + y256p[0] = mulhi_int16_simd256(y256p[0],ONE_OVER_SQRT2_Q15_128); + y256p[1] = mulhi_int16_simd256(y256p[1],ONE_OVER_SQRT2_Q15_128); + y256p[2] = mulhi_int16_simd256(y256p[2],ONE_OVER_SQRT2_Q15_128); + y256p[3] = mulhi_int16_simd256(y256p[3],ONE_OVER_SQRT2_Q15_128); + y256p[4] = mulhi_int16_simd256(y256p[4],ONE_OVER_SQRT2_Q15_128); + y256p[5] = mulhi_int16_simd256(y256p[5],ONE_OVER_SQRT2_Q15_128); + y256p[6] = mulhi_int16_simd256(y256p[6],ONE_OVER_SQRT2_Q15_128); + y256p[7] = mulhi_int16_simd256(y256p[7],ONE_OVER_SQRT2_Q15_128); + y256p[8] = mulhi_int16_simd256(y256p[8],ONE_OVER_SQRT2_Q15_128); + y256p[9] = mulhi_int16_simd256(y256p[9],ONE_OVER_SQRT2_Q15_128); + y256p[10] = mulhi_int16_simd256(y256p[10],ONE_OVER_SQRT2_Q15_128); + y256p[11] = mulhi_int16_simd256(y256p[11],ONE_OVER_SQRT2_Q15_128); + y256p[12] = mulhi_int16_simd256(y256p[12],ONE_OVER_SQRT2_Q15_128); + y256p[13] = mulhi_int16_simd256(y256p[13],ONE_OVER_SQRT2_Q15_128); + y256p[14] = mulhi_int16_simd256(y256p[14],ONE_OVER_SQRT2_Q15_128); + y256p[15] = mulhi_int16_simd256(y256p[15],ONE_OVER_SQRT2_Q15_128); + y256p+=16; + } + } + + _mm_empty(); + _m_empty(); + +} + + +#endif + + int16_t twa1536[1024],twb1536[1024]; // 512 x 3 @@ -6176,12 +6777,99 @@ int16_t twb49152[32768] __attribute__((aligned(32))); // 16384 x 3 void dft49152(int16_t *input, int16_t *output,uint8_t scale) { - AssertFatal(1==0,"Need to do this ..\n"); + int i,i2,j; + uint32_t tmp[3][16384] __attribute__((aligned(32))); + uint32_t tmpo[3][16384] __attribute__((aligned(32))); + simd_q15_t *y128p=(simd_q15_t*)output; + simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15); + + for (i=0,j=0; i<16384; i++) { + tmp[0][i] = ((uint32_t *)input)[j++]; + tmp[1][i] = ((uint32_t *)input)[j++]; + tmp[2][i] = ((uint32_t *)input)[j++]; + } + + dft16384((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1); + dft16384((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1); + dft16384((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1); + + for (i=0,i2=0; i<32768; i+=8,i2+=4) { + bfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]), + (simd_q15_t*)(output+i),(simd_q15_t*)(output+32768+i),(simd_q15_t*)(output+65536+i), + (simd_q15_t*)(twa49152+i),(simd_q15_t*)(twb49152+i)); + } + if (scale==1) { + for (i=0; i<768; i++) { + y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128); + y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128); + y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128); + y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128); + y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128); + y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128); + y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128); + y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128); + y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128); + y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128); + y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128); + y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128); + y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128); + y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128); + y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128); + y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128); + y128p+=16; + } + } + _mm_empty(); + _m_empty(); + } void idft49152(int16_t *input, int16_t *output,uint8_t scale) { - AssertFatal(1==0,"Need to do this ..\n"); + int i,i2,j; + uint32_t tmp[3][16384] __attribute__((aligned(32))); + uint32_t tmpo[3][16384] __attribute__((aligned(32))); + simd_q15_t *y128p=(simd_q15_t*)output; + simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15); + + for (i=0,j=0; i<16384; i++) { + tmp[0][i] = ((uint32_t *)input)[j++]; + tmp[1][i] = ((uint32_t *)input)[j++]; + tmp[2][i] = ((uint32_t *)input)[j++]; + } + + idft16384((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1); + idft16384((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1); + idft16384((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1); + + for (i=0,i2=0; i<32768; i+=8,i2+=4) { + ibfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]), + (simd_q15_t*)(output+i),(simd_q15_t*)(output+32768+i),(simd_q15_t*)(output+65536+i), + (simd_q15_t*)(twa49152+i),(simd_q15_t*)(twb49152+i)); + } + if (scale==1) { + for (i=0; i<768; i++) { + y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128); + y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128); + y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128); + y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128); + y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128); + y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128); + y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128); + y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128); + y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128); + y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128); + y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128); + y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128); + y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128); + y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128); + y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128); + y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128); + y128p+=16; + } + } + _mm_empty(); + _m_empty(); } int16_t twa73728[49152] __attribute__((aligned(32))); @@ -6198,17 +6886,104 @@ void idft73728(int16_t *input, int16_t *output,uint8_t scale) { } -int16_t twa98304[49152] __attribute__((aligned(32))); -int16_t twb98304[49152] __attribute__((aligned(32))); +int16_t twa98304[65536] __attribute__((aligned(32))); +int16_t twb98304[65536] __attribute__((aligned(32))); // 32768 x 3 void dft98304(int16_t *input, int16_t *output,uint8_t scale) { - AssertFatal(1==0,"Need to do this ..\n"); + int i,i2,j; + uint32_t tmp[3][32768] __attribute__((aligned(32))); + uint32_t tmpo[3][32768] __attribute__((aligned(32))); + simd_q15_t *y128p=(simd_q15_t*)output; + simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15); + + for (i=0,j=0; i<32768; i++) { + tmp[0][i] = ((uint32_t *)input)[j++]; + tmp[1][i] = ((uint32_t *)input)[j++]; + tmp[2][i] = ((uint32_t *)input)[j++]; + } + + dft32768((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1); + dft32768((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1); + dft32768((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1); + + for (i=0,i2=0; i<65536; i+=8,i2+=4) { + bfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]), + (simd_q15_t*)(output+i),(simd_q15_t*)(output+65536+i),(simd_q15_t*)(output+131072+i), + (simd_q15_t*)(twa98304+i),(simd_q15_t*)(twb98304+i)); + } + if (scale==1) { + for (i=0; i<1536; i++) { + y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128); + y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128); + y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128); + y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128); + y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128); + y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128); + y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128); + y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128); + y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128); + y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128); + y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128); + y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128); + y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128); + y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128); + y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128); + y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128); + y128p+=16; + } + } + _mm_empty(); + _m_empty(); + } void idft98304(int16_t *input, int16_t *output,uint8_t scale) { - AssertFatal(1==0,"Need to do this ..\n"); + int i,i2,j; + uint32_t tmp[3][32768] __attribute__((aligned(32))); + uint32_t tmpo[3][32768] __attribute__((aligned(32))); + simd_q15_t *y128p=(simd_q15_t*)output; + simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15); + + for (i=0,j=0; i<32768; i++) { + tmp[0][i] = ((uint32_t *)input)[j++]; + tmp[1][i] = ((uint32_t *)input)[j++]; + tmp[2][i] = ((uint32_t *)input)[j++]; + } + + idft32768((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1); + idft32768((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1); + idft32768((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1); + + for (i=0,i2=0; i<65536; i+=8,i2+=4) { + ibfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]), + (simd_q15_t*)(output+i),(simd_q15_t*)(output+65536+i),(simd_q15_t*)(output+131072+i), + (simd_q15_t*)(twa98304+i),(simd_q15_t*)(twb98304+i)); + } + if (scale==1) { + for (i=0; i<1536; i++) { + y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128); + y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128); + y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128); + y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128); + y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128); + y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128); + y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128); + y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128); + y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128); + y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128); + y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128); + y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128); + y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128); + y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128); + y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128); + y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128); + y128p+=16; + } + } + _mm_empty(); + _m_empty(); } @@ -8823,6 +9598,8 @@ int dfts_autoinit(void) init_rad2(2048,tw2048); init_rad4(4096,tw4096); init_rad2(8192,tw8192); + init_rad4(16384,tw16384); + init_rad2(32768,tw32768); init_rad3(1536,twa1536,twb1536); init_rad3(3072,twa3072,twb3072); @@ -8830,6 +9607,9 @@ int dfts_autoinit(void) init_rad3(12288,twa12288,twb12288); init_rad3(18432,twa18432,twb18432); init_rad3(24576,twa24576,twb24576); + init_rad3(49152,twa49152,twb49152); + init_rad3(98304,twa98304,twb98304); + init_rad2_rep(24,tw24); init_rad3_rep(36,twa36,twb36); @@ -8869,6 +9649,7 @@ int dfts_autoinit(void) +#ifndef MR_MAIN void dft(uint8_t sizeidx, int16_t *sigF,int16_t *sig,unsigned char scale_flag){ AssertFatal((sizeidx>=0 && sizeidx<(int)DFT_SIZE_IDXTABLESIZE),"Invalid dft size index %i\n",sizeidx); @@ -8879,6 +9660,7 @@ void idft(uint8_t sizeidx, int16_t *sigF,int16_t *sig,unsigned char scale_flag){ AssertFatal((sizeidx>=0 && sizeidx<(int)IDFT_SIZE_IDXTABLESIZE),"Invalid idft size index %i\n",sizeidx); idft_ftab[sizeidx](sigF,sig,scale_flag); }; +#endif /*---------------------------------------------------------------------------------------*/ @@ -9049,9 +9831,9 @@ int main(int argc, char**argv) time_stats_t ts; #ifdef __AVX2__ - simd256_q15_t x[4096],x2[4096],y[4096],tw0,tw1,tw2,tw3; + simd256_q15_t x[16384],x2[16384],y[16384],tw0,tw1,tw2,tw3; #else - simd_q15_t x[8192],y[8192],tw0,tw1,tw2,tw3; + simd_q15_t x[32768],y[32768],tw0,tw1,tw2,tw3; #endif int i; simd_q15_t *x128=(simd_q15_t*)x,*y128=(simd_q15_t*)y; @@ -9613,10 +10395,34 @@ int main(int argc, char**argv) stop_meas(&ts); } - printf("\n\n1536-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); + printf("\n\n8192-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); LOG_M("y8192.m","y8192",y,8192,1,1); LOG_M("x8192.m","x8192",x,8192,1,1); + memset((void*)x,0,16384*sizeof(int32_t)); + for (i=2;i<9602;i++) { + if ((taus() & 1)==0) + ((int16_t*)x)[i] = 364; + else + ((int16_t*)x)[i] = -364; + } + for (i=2*(16384-4800);i<32768;i++) { + if ((taus() & 1)==0) + ((int16_t*)x)[i] = 364; + else + ((int16_t*)x)[i] = -364; + } + reset_meas(&ts); + for (i=0; i<10000; i++) { + start_meas(&ts); + dft16384((int16_t *)x,(int16_t *)y,1); + stop_meas(&ts); + } + + printf("\n\n16384-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); + LOG_M("y16384.m","y16384",y,16384,1,1); + LOG_M("x16384.m","x16384",x,16384,1,1); + memset((void*)x,0,1536*sizeof(int32_t)); for (i=2;i<1202;i++) { if ((taus() & 1)==0) @@ -9765,6 +10571,30 @@ int main(int argc, char**argv) LOG_M("y24576.m","y24576",y,24576,1,1); LOG_M("x24576.m","x24576",x,24576,1,1); + memset((void*)x,0,49152*sizeof(int32_t)); + for (i=2;i<28402;i++) { + if ((taus() & 1)==0) + ((int16_t*)x)[i] = 364; + else + ((int16_t*)x)[i] = -364; + } + for (i=2*(49152-14400);i<98304;i++) { + if ((taus() & 1)==0) + ((int16_t*)x)[i] = 364; + else + ((int16_t*)x)[i] = -364; + } + reset_meas(&ts); + for (i=0; i<10000; i++) { + start_meas(&ts); + idft49152((int16_t *)x,(int16_t *)y,1); + stop_meas(&ts); + } + + printf("\n\n49152-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); + LOG_M("y49152.m","y49152",y,49152,1,1); + LOG_M("x49152.m","x49152",x,49152,1,1); + /* int dftsizes[33]={24,36,48,60,72,96,108,120,144,180,192,216,240,288,300,324,360,384,432,480,540,576,600,648,720,768,864,900,960,972,1080,1152,1200}; void (*dft)(int16_t *x,int16_t *y,uint8_t scale)[33] = {dft24,dft36,dft48,dft60,dft72,dft96,dft108,dft120,dft144,dft180,dft192,dft216,dft240,dft288,dft300,dft324,dft360,dft384,dft432,dft480,dft540,dft576,dft600,dft648,dft720,dft768,dft864,dft900,dft960,dft972,dft1080,dft1152,dft1200}; for (int n=0;n<33;n++) { @@ -9797,7 +10627,7 @@ int main(int argc, char**argv) LOG_M(ystr,ystr2,y,dftsizes[n]*4,1,1); LOG_M(xstr,xstr2,x,dftsizes[n]*4,1,1); } - + */ return(0); } diff --git a/openair1/SIMULATION/NR_PHY/prachsim.c b/openair1/SIMULATION/NR_PHY/prachsim.c index 10bdd23ef2..ec3fce08d8 100644 --- a/openair1/SIMULATION/NR_PHY/prachsim.c +++ b/openair1/SIMULATION/NR_PHY/prachsim.c @@ -89,7 +89,7 @@ int main(int argc, char **argv){ int i, aa, aarx, **txdata, trial, n_frames = 1, prach_start, rx_prach_start; //, ntrials=1; int N_RB_UL = 106, delay = 0, NCS_config = 13, rootSequenceIndex = 1, threequarter_fs = 0, mu = 1, fd_occasion = 0, loglvl = OAILOG_INFO, numRA = 0, prachStartSymbol = 0; uint8_t snr1set = 0, ue_speed1set = 0, transmission_mode = 1, n_tx = 1, n_rx = 1, awgn_flag = 0, msg1_frequencystart = 0, num_prach_fd_occasions = 1, prach_format; - uint8_t frame = 1, subframe = 19, config_index = 98, prach_sequence_length = 1, num_root_sequences = 16, restrictedSetConfig = 0, N_dur, N_t_slot, start_symbol; + uint8_t frame = 1, subframe = 9, slot=19, config_index = 98, prach_sequence_length = 1, num_root_sequences = 16, restrictedSetConfig = 0, N_dur, N_t_slot, start_symbol; uint16_t Nid_cell = 0, preamble_tx = 0, preamble_delay, format, format0, format1; uint32_t tx_lev = 10000, prach_errors = 0, samp_count; //,tx_lev_dB; uint64_t SSB_positions = 0x01, absoluteFrequencyPointA = 640000; @@ -118,7 +118,7 @@ int main(int argc, char **argv){ randominit(0); - while ((c = getopt (argc, argv, "hHaA:Cr:p:g:n:s:S:t:x:y:v:V:z:N:F:d:Z:L:R:E")) != -1) { + while ((c = getopt (argc, argv, "hHaA:Cc:r:p:g:n:s:S:t:x:y:v:V:z:N:F:d:Z:L:R:E")) != -1) { switch (c) { case 'a': printf("Running AWGN simulation\n"); @@ -127,6 +127,10 @@ int main(int argc, char **argv){ //ntrials=1; break; + case 'c': + config_index = atoi(optarg); + break; + case 'd': delay = atoi(optarg); break; @@ -313,6 +317,11 @@ int main(int argc, char **argv){ } } + + if (config_index<67) { prach_sequence_length=0; slot = subframe*2; } + + printf("Config_index %d, prach_sequence_length %d\n",config_index,prach_sequence_length); + // Configure log logInit(); set_glog(loglvl); @@ -373,11 +382,11 @@ int main(int argc, char **argv){ gNB->gNB_config.prach_config.num_prach_fd_occasions.value = num_prach_fd_occasions; gNB->gNB_config.prach_config.num_prach_fd_occasions_list = (nfapi_nr_num_prach_fd_occasions_t *) malloc(num_prach_fd_occasions*sizeof(nfapi_nr_num_prach_fd_occasions_t)); - gNB->proc.slot_rx = subframe; + gNB->proc.slot_rx = slot; get_nr_prach_info_from_index(config_index, (int)frame, - (int)subframe, + (int)slot, absoluteFrequencyPointA, mu, frame_parms->frame_type, @@ -562,7 +571,7 @@ int main(int argc, char **argv){ UE_nr_rxtx_proc_t proc={0}; proc.frame_tx = frame; - proc.nr_tti_tx = subframe; + proc.nr_tti_tx = slot; nr_ue_prach_procedures(UE,&proc,0,0); /* tx_lev_dB not used later, no need to set */ @@ -571,19 +580,19 @@ int main(int argc, char **argv){ if (mu == 0) samp_count = frame_parms->samples_per_subframe; else - samp_count = (subframe%(frame_parms->slots_per_subframe/2)) ? frame_parms->samples_per_slotN0 : frame_parms->samples_per_slot0; + samp_count = ((slot)%(frame_parms->slots_per_subframe/2)) ? frame_parms->samples_per_slotN0 : frame_parms->samples_per_slot0; - prach_start = subframe*samp_count - UE->N_TA_offset; + prach_start = slot*samp_count - UE->N_TA_offset; #ifdef NR_PRACH_DEBUG - LOG_M("txsig0.m", "txs0", &txdata[0][prach_start], samp_count, 1, 1); + LOG_M("txsig0.m", "txs0", &txdata[0][prach_start], frame_parms->samples_per_subframe, 1, 1); //LOG_M("txsig1.m","txs1", txdata[1],FRAME_LENGTH_COMPLEX_SAMPLES,1,1); #endif // multipath channel // dump_nr_prach_config(&gNB->frame_parms,subframe); - for (i = 0; i < samp_count<<1; i++) { + for (i = 0; i < frame_parms->samples_per_subframe<<1; i++) { for (aa=0; aa<1; aa++) { if (awgn_flag == 0) { s_re[aa][i] = ((double)(((short *)&txdata[aa][prach_start]))[(i<<1)]); @@ -618,7 +627,10 @@ int main(int argc, char **argv){ ue_speed1 = ue_speed0 + 50; } - rx_prach_start = subframe*frame_parms->get_samples_per_slot(subframe,frame_parms); + rx_prach_start = slot*frame_parms->get_samples_per_slot(slot,frame_parms); + if (n_frames==1) printf("slot %d, rx_prach_start %d\n",slot,rx_prach_start); + uint16_t preamble_rx, preamble_energy, N_ZC; + N_ZC = prach_sequence_length == 0 ? 839 : 139; for (SNR=snr0; SNRget_samples_per_slot(subframe,frame_parms); i++) { + for (i = 0; i< frame_parms->samples_per_subframe; i++) { for (aa = 0; aa < frame_parms->nb_antennas_rx; aa++) { - ((short*) &gNB->common_vars.rxdata[aa][rx_prach_start])[2*i] = (short) (.167*(r_re[aa][i] +sqrt(sigma2/2)*gaussdouble(0.0,1.0))); - ((short*) &gNB->common_vars.rxdata[aa][rx_prach_start])[2*i+1] = (short) (.167*(r_im[aa][i] + (iqim*r_re[aa][i]) + sqrt(sigma2/2)*gaussdouble(0.0,1.0))); + ((short*) &ru->common.rxdata[aa][rx_prach_start])[2*i] = (short) (.167*(r_re[aa][i] +sqrt(sigma2/2)*gaussdouble(0.0,1.0))); + ((short*) &ru->common.rxdata[aa][rx_prach_start])[2*i+1] = (short) (.167*(r_im[aa][i] + (iqim*r_re[aa][i]) + sqrt(sigma2/2)*gaussdouble(0.0,1.0))); } } - rx_nr_prach_ru(ru, prach_format, numRA, prachStartSymbol, frame, subframe); + rx_nr_prach_ru(ru, prach_format, numRA, prachStartSymbol, frame, slot); gNB->prach_vars.rxsigF = ru->prach_rxsigF; rx_nr_prach(gNB, prach_pdu, frame, subframe, &preamble_rx, &preamble_energy, &preamble_delay); - printf(" preamble_energy %d preamble_rx %d preamble_tx %d \n", preamble_energy, preamble_rx, preamble_tx); + // printf(" preamble_energy %d preamble_rx %d preamble_tx %d \n", preamble_energy, preamble_rx, preamble_tx); if (preamble_rx != preamble_tx) prach_errors++; diff --git a/openair1/SIMULATION/TOOLS/taus.c b/openair1/SIMULATION/TOOLS/taus.c index 5fe0ce4d78..cdd4aebec3 100644 --- a/openair1/SIMULATION/TOOLS/taus.c +++ b/openair1/SIMULATION/TOOLS/taus.c @@ -21,7 +21,8 @@ #include #include -#include "SIMULATION/TOOLS/sim.h" +//#include "SIMULATION/TOOLS/sim.h" + unsigned int s0, s1, s2, b; diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index 5ac4de0280..5adcf42560 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -46,6 +46,7 @@ uint16_t NCS_restricted_TypeB_delta_f_RA_5[14] = {36,57,60,63,65,68,71,77,81,8 uint16_t NCS_unrestricted_delta_f_RA_15[16] = {0,2,4,6,8,10,12,13,15,17,19,23,27,34,46,69}; const char *prachfmt[]={"A1","A2","A3","B1","B2","B3","B4","C0","C2"}; +const char *prachfmt03[]={"0","1","2","3"}; uint16_t get_NCS(uint8_t index, uint16_t format0, uint8_t restricted_set_config) { From 729890a133fe5f6f1c29437c289f96c9b6724ad9 Mon Sep 17 00:00:00 2001 From: "s.rampalli" Date: Wed, 20 May 2020 15:26:37 +0530 Subject: [PATCH 251/553] Required changes/modifications are done at both eNB and gNB side --- openair2/RRC/LTE/rrc_defs.h | 10 +- openair2/RRC/LTE/rrc_eNB.c | 857 +++---- openair2/RRC/NR/rrc_gNB.c | 144 +- openair2/RRC/NR/rrc_gNB_internode.c | 80 +- openair2/RRC/NR/rrc_gNB_nsa.c | 235 +- openair2/RRC/NR/rrc_gNB_reconfig.c | 3616 +++++++++++++-------------- 6 files changed, 2363 insertions(+), 2579 deletions(-) diff --git a/openair2/RRC/LTE/rrc_defs.h b/openair2/RRC/LTE/rrc_defs.h index 52b06b9f11..42fa5f6de1 100644 --- a/openair2/RRC/LTE/rrc_defs.h +++ b/openair2/RRC/LTE/rrc_defs.h @@ -40,6 +40,10 @@ #include "rrc_types.h" //#include "PHY/phy_defs.h" #include "LAYER2/RLC/rlc.h" +#include "RRC/NR/nr_rrc_types.h" +#include "NR_UE-MRDC-Capability.h" +#include "NR_UE-NR-Capability.h" + #include "COMMON/platform_constants.h" #include "COMMON/platform_types.h" @@ -569,6 +573,10 @@ typedef struct eNB_RRC_UE_s { LTE_UE_EUTRA_Capability_t *UE_Capability; int UE_Capability_size; + NR_UE_MRDC_Capability_t *UE_Capability_MRDC; + int UE_MRDC_Capability_size; + NR_UE_NR_Capability_t *UE_Capability_nr; + int UE_NR_Capability_size; ImsiMobileIdentity_t imsi; /* KeNB as derived from KASME received from EPC */ @@ -614,7 +622,7 @@ typedef struct eNB_RRC_UE_s { /* Number of e_rab to be modified in the list */ uint8_t nb_of_modify_e_rabs; uint8_t nb_of_failed_e_rabs; - uint8_t nb_of_modify_endc_e_rabs; + uint8_t nb_of_modify_endc_e_rabs; e_rab_param_t modify_e_rab[NB_RB_MAX];//[S1AP_MAX_E_RAB]; /* list of e_rab to be setup by RRC layers */ e_rab_param_t e_rab[NB_RB_MAX];//[S1AP_MAX_E_RAB]; diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index 098bb3823f..37bb33322b 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -100,8 +100,6 @@ #define NUMBEROF_DRBS_TOBE_ADDED 1 static int encode_CG_ConfigInfo(char *buffer,int buffer_size,rrc_eNB_ue_context_t *const ue_context_pP,int *enc_size); static int is_en_dc_supported(LTE_UE_EUTRA_Capability_t *c); -static void free_rb_config(struct NR_RadioBearerConfig *rb_config); -static void free_cg_configinfo(struct NR_CG_ConfigInfo *cg_configinfo); extern RAN_CONTEXT_t RC; @@ -119,8 +117,9 @@ extern uint32_t to_earfcn_DL(int eutra_bandP, uint32_t dl_CarrierFreq, uint32_t extern int rrc_eNB_process_security(const protocol_ctxt_t *const ctxt_pP, rrc_eNB_ue_context_t *const ue_context_pP, security_capabilities_t *security_capabilities_pP); extern void process_eNB_security_key (const protocol_ctxt_t *const ctxt_pP, rrc_eNB_ue_context_t *const ue_context_pP, uint8_t *security_key_pP); extern int derive_keNB_star(const uint8_t *kenb_32, const uint16_t pci, const uint32_t earfcn_dl, const bool is_rel8_only, uint8_t *kenb_star); -extern int rrc_eNB_generate_RRCConnectionReconfiguration_endc(protocol_ctxt_t *ctxt, rrc_eNB_ue_context_t *ue_context, unsigned char *buffer, int buffer_size, OCTET_STRING_t *scg_group_config, OCTET_STRING_t *scg_RB_config); -extern struct rrc_eNB_ue_context_s * get_first_ue_context(eNB_RRC_INST *rrc_instance_pP); +extern int rrc_eNB_generate_RRCConnectionReconfiguration_endc(protocol_ctxt_t *ctxt, rrc_eNB_ue_context_t *ue_context, unsigned char *buffer, int buffer_size, OCTET_STRING_t *scg_group_config, + OCTET_STRING_t *scg_RB_config); +extern struct rrc_eNB_ue_context_s *get_first_ue_context(eNB_RRC_INST *rrc_instance_pP); pthread_mutex_t rrc_release_freelist; RRC_release_list_t rrc_release_info; @@ -168,7 +167,7 @@ init_SI( AssertFatal(RC.rrc[ctxt_pP->module_id]->carrier[CC_id].SIB1_MBMS!=NULL,PROTOCOL_RRC_CTXT_FMT" init_SI: FATAL, no memory for SIB1_MBMS allocated\n", PROTOCOL_RRC_CTXT_ARGS(ctxt_pP)); RC.rrc[ctxt_pP->module_id]->carrier[CC_id].sizeof_SIB1_MBMS = do_SIB1_MBMS(&RC.rrc[ctxt_pP->module_id]->carrier[CC_id],ctxt_pP->module_id,CC_id, - configuration + configuration ); LOG_I(RRC, PROTOCOL_RRC_CTXT_FMT" Contents of SIB1-MBMS\n", PROTOCOL_RRC_CTXT_ARGS(ctxt_pP) @@ -2128,7 +2127,7 @@ rrc_eNB_generate_RRCConnectionReestablishmentReject( #ifdef GES_ENDC_SUPPORT #if 0 void rrc_generate_SgNBReleaseRequest( - const protocol_ctxt_t *const ctxt_pP, + const protocol_ctxt_t *const ctxt_pP, rrc_eNB_ue_context_t *const ue_context_pP ) //----------------------------------------------------------------------------- @@ -2136,13 +2135,13 @@ void rrc_generate_SgNBReleaseRequest( MessageDef *msg; msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_RELEASE_REQ); memset(&(X2AP_ENDC_SGNB_RELEASE_REQ(msg)), 0, sizeof(x2ap_ENDC_sgnb_release_req_t)); - // X2AP_ENDC_SGNB_RELEASE_REQ(msg).MeNB_ue_x2_id = ; - // X2AP_ENDC_SGNB_RELEASE_REQ(msg).SgNB_ue_x2_id = ; - // X2AP_ENDC_SGNB_RELEASE_REQ(msg).cause = ; - // X2AP_ENDC_SGNB_RELEASE_REQ(msg).target_physCellId = ; + // X2AP_ENDC_SGNB_RELEASE_REQ(msg).MeNB_ue_x2_id = ; + // X2AP_ENDC_SGNB_RELEASE_REQ(msg).SgNB_ue_x2_id = ; + // X2AP_ENDC_SGNB_RELEASE_REQ(msg).cause = ; + // X2AP_ENDC_SGNB_RELEASE_REQ(msg).target_physCellId = ; LOG_I(RRC, - "[eNB %d] frame %d UE rnti %x transmitting sgnb release request to sgnb \n", - ctxt_pP->module_id,ctxt_pP->frame,ctxt_pP->rnti); + "[eNB %d] frame %d UE rnti %x transmitting sgnb release request to sgnb \n", + ctxt_pP->module_id,ctxt_pP->frame,ctxt_pP->rnti); itti_send_msg_to_task(TASK_X2AP, ENB_MODULE_ID_TO_INSTANCE(ctxt_pP->module_id), msg); return; } @@ -2167,13 +2166,13 @@ rrc_eNB_generate_RRCConnectionRelease( T_INT(ctxt_pP->subframe), T_INT(ctxt_pP->rnti)); #ifdef GES_ENDC_SUPPORT #if 0 - if(ue_context_pP != NULL) - { - if(ue_context_pP->ue_context.Status == RRC_NR_NSA) - { - //rrc_eNB_generate_SgNBReleaseRequest(ctxt_pP,ue_context_pP); - } + + if(ue_context_pP != NULL) { + if(ue_context_pP->ue_context.Status == RRC_NR_NSA) { + //rrc_eNB_generate_SgNBReleaseRequest(ctxt_pP,ue_context_pP); + } } + #endif #endif size = do_RRCConnectionRelease(ctxt_pP->module_id, buffer,rrc_eNB_get_next_transaction_identifier(ctxt_pP->module_id)); @@ -2871,7 +2870,6 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t uint16_t size; int i; MessageDef *message_p = NULL; - /* Configure SRB1/SRB2, PhysicalConfigDedicated, LTE_MAC_MainConfig for UE */ eNB_RRC_INST *rrc_inst = RC.rrc[ctxt_pP->module_id]; struct LTE_PhysicalConfigDedicated **physicalConfigDedicated = &ue_context_pP->ue_context.physicalConfigDedicated; @@ -3063,7 +3061,7 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t module_id_t module_id = ctxt_pP->module_id; LOG_D(RRC, "Processing the DRX configuration in RRC Connection Reconfiguration\n"); - /* Process the IE drx_Config */ + /* Process the IE drx_Config */ if (NODE_IS_MONOLITHIC(rrc_inst->node_type)) { mac_MainConfig->drx_Config = do_DrxConfig(cc_id, &rrc_inst->configuration, UEcap); // drx_Config IE @@ -3078,8 +3076,8 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t LOG_D(RRC, "DRX configured in MAC Main Configuration for RRC Connection Reconfiguration\n"); } } - /* End of CDRX configuration */ + /* End of CDRX configuration */ sr_ProhibitTimer_r9 = CALLOC(1, sizeof(long)); *sr_ProhibitTimer_r9 = 0; // SR tx on PUCCH, Value in number of SR period(s). Value 0 = no timer for SR, Value 2 = 2*SR mac_MainConfig->ext1 = CALLOC(1, sizeof(struct LTE_MAC_MainConfig__ext1)); @@ -3187,7 +3185,9 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t if (ue_context_pP->ue_context.does_nr) { MeasId6 = calloc(1, sizeof(LTE_MeasIdToAddMod_t)); + if (MeasId6 == NULL) exit(1); + MeasId6->measId = 7; MeasId6->measObjectId = 2; MeasId6->reportConfigId = 7; @@ -3245,22 +3245,28 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t if (ue_context_pP->ue_context.does_nr) { MeasObj2 = calloc(1, sizeof(LTE_MeasObjectToAddMod_t)); + if (MeasObj2 == NULL) exit(1); + MeasObj2->measObjectId = 2; MeasObj2->measObject.present = LTE_MeasObjectToAddMod__measObject_PR_measObjectNR_r15; - MeasObj2->measObject.choice.measObjectNR_r15.carrierFreq_r15 = 642256; //634000; //(634000 = 3.51GHz) (640000 = 3.6GHz) (641272 = 3619.08MHz = 3600 + 30/1000*106*12/2) (642256 is for 3.6GHz and absoluteFrequencySSB = 642016) + MeasObj2->measObject.choice.measObjectNR_r15.carrierFreq_r15 = + 642256; //634000; //(634000 = 3.51GHz) (640000 = 3.6GHz) (641272 = 3619.08MHz = 3600 + 30/1000*106*12/2) (642256 is for 3.6GHz and absoluteFrequencySSB = 642016) MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.periodicityAndOffset_r15.present = LTE_MTC_SSB_NR_r15__periodicityAndOffset_r15_PR_sf20_r15; MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.periodicityAndOffset_r15.choice.sf20_r15 = 0; MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.ssb_Duration_r15 = LTE_MTC_SSB_NR_r15__ssb_Duration_r15_sf4; MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.subcarrierSpacingSSB_r15 = LTE_RS_ConfigSSB_NR_r15__subcarrierSpacingSSB_r15_kHz30; MeasObj2->measObject.choice.measObjectNR_r15.quantityConfigSet_r15 = 1; MeasObj2->measObject.choice.measObjectNR_r15.ext1 = calloc(1, sizeof(struct LTE_MeasObjectNR_r15__ext1)); + if (MeasObj2->measObject.choice.measObjectNR_r15.ext1 == NULL) exit(1); + MeasObj2->measObject.choice.measObjectNR_r15.ext1->bandNR_r15 = calloc(1, sizeof(struct LTE_MeasObjectNR_r15__ext1__bandNR_r15)); + if (MeasObj2->measObject.choice.measObjectNR_r15.ext1->bandNR_r15 == NULL) exit(1); + MeasObj2->measObject.choice.measObjectNR_r15.ext1->bandNR_r15->present = LTE_MeasObjectNR_r15__ext1__bandNR_r15_PR_setup; MeasObj2->measObject.choice.measObjectNR_r15.ext1->bandNR_r15->choice.setup = 78; - ASN_SEQUENCE_ADD(&MeasObj_list->list, MeasObj2); } @@ -3276,9 +3282,11 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t ReportConfig_A3 = CALLOC(1, sizeof(*ReportConfig_A3)); ReportConfig_A4 = CALLOC(1, sizeof(*ReportConfig_A4)); ReportConfig_A5 = CALLOC(1, sizeof(*ReportConfig_A5)); + if (ue_context_pP->ue_context.does_nr) { ReportConfig_NR = CALLOC(1, sizeof(*ReportConfig_NR)); } + ReportConfig_per->reportConfigId = 1; ReportConfig_per->reportConfig.present = LTE_ReportConfigToAddMod__reportConfig_PR_reportConfigEUTRA; ReportConfig_per->reportConfig.choice.reportConfigEUTRA.triggerType.present = @@ -3399,9 +3407,13 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.reportInterval = LTE_ReportInterval_ms120; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.reportAmount = LTE_ReportConfigInterRAT__reportAmount_infinity; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7 = calloc(1, sizeof(struct LTE_ReportConfigInterRAT__ext7)); + if (ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7 == NULL) exit(1); + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15 = calloc(1, sizeof(struct LTE_ReportQuantityNR_r15)); + if (ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15 == NULL) exit(1); + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15->ss_rsrp = TRUE; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15->ss_rsrq = TRUE; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15->ss_sinr = TRUE; @@ -3574,7 +3586,6 @@ flexran_rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt uint16_t size; int i; MessageDef *message_p = NULL; - /* Configure SRB1/SRB2, PhysicalConfigDedicated, LTE_MAC_MainConfig for UE */ eNB_RRC_INST *rrc_inst = RC.rrc[ctxt_pP->module_id]; struct LTE_PhysicalConfigDedicated **physicalConfigDedicated = &ue_context_pP->ue_context.physicalConfigDedicated; @@ -3620,7 +3631,6 @@ flexran_rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt LTE_C_RNTI_t *cba_RNTI = NULL; int measurements_enabled; uint8_t xid = rrc_eNB_get_next_transaction_identifier(ctxt_pP->module_id); //Transaction_id, - #ifdef CBA // Contention Based Access uint8_t *cba_RNTI_buf; cba_RNTI = CALLOC(1, sizeof(LTE_C_RNTI_t)); @@ -3646,8 +3656,8 @@ flexran_rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt frameP, ue_mod_idP); } -#endif +#endif T(T_ENB_RRC_CONNECTION_RECONFIGURATION, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame), @@ -3782,7 +3792,6 @@ flexran_rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt mac_MainConfig->phr_Config->choice.setup.prohibitPHR_Timer = LTE_MAC_MainConfig__phr_Config__setup__prohibitPHR_Timer_sf200; // sf20 = 20 subframes // LTE_MAC_MainConfig__phr_Config__setup__prohibitPHR_Timer_sf1000 mac_MainConfig->phr_Config->choice.setup.dl_PathlossChange = LTE_MAC_MainConfig__phr_Config__setup__dl_PathlossChange_dB3; // Value dB1 =1 dB, dB3 = 3 dB - /* CDRX Configuration */ mac_MainConfig->drx_Config = NULL; rnti_t rnti = ue_context_pP->ue_id_rnti; @@ -3790,11 +3799,11 @@ flexran_rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt uint8_t cc_id = ue_context_pP->ue_context.primaryCC_id; LTE_UE_EUTRA_Capability_t *UEcap = ue_context_pP->ue_context.UE_Capability; LOG_D(RRC, "Processing the DRX configuration in RRC Connection Reconfiguration\n"); - + /* Process the IE drx_Config */ if (NODE_IS_MONOLITHIC(rrc_inst->node_type)) { mac_MainConfig->drx_Config = do_DrxConfig(cc_id, &rrc_inst->configuration, UEcap); // drx_Config IE - + if (mac_MainConfig->drx_Config == NULL) { LOG_W(RRC, "drx_Configuration parameter is NULL, cannot configure local UE parameters or CDRX is deactivated\n"); } else { @@ -3806,8 +3815,8 @@ flexran_rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt LOG_D(RRC, "DRX configured in MAC Main Configuration for RRC Connection Reconfiguration\n"); } } - /* End of CDRX configuration */ + /* End of CDRX configuration */ sr_ProhibitTimer_r9 = CALLOC(1, sizeof(long)); *sr_ProhibitTimer_r9 = 0; // SR tx on PUCCH, Value in number of SR period(s). Value 0 = no timer for SR, Value 2 = 2*SR mac_MainConfig->ext1 = CALLOC(1, sizeof(struct LTE_MAC_MainConfig__ext1)); @@ -4326,12 +4335,12 @@ rrc_eNB_generate_RRCConnectionReconfiguration_SCell( //----------------------------------------------------------------------------- -/** - * @fn :encode_CG_ConfigInfo - * @param :enc_buf to store the encoded bits +/** + * @fn :encode_CG_ConfigInfo + * @param :enc_buf to store the encoded bits * @param :ue_context_pP ue context used to fill CG-ConfigInfo * @param :enc_size to store thre size of encoded size - * this api is to fill and encode CG-ConfigInfo + * this api is to fill and encode CG-ConfigInfo */ static int encode_CG_ConfigInfo( char *buffer, @@ -4345,212 +4354,158 @@ static int encode_CG_ConfigInfo( int RRC_OK = 1; int index = 0; char temp_buff[ASN_MAX_ENCODE_SIZE]; - - rb_config = calloc(1,sizeof( struct NR_RadioBearerConfig)); + LTE_UE_CapabilityRAT_ContainerList_t *ue_cap_rat_container_list = NULL; + LTE_UE_CapabilityRAT_Container_t ue_cap_rat_container_MRDC; + LTE_UE_CapabilityRAT_Container_t ue_cap_rat_container_nr; + int RAT_Container_count = 0; + rb_config = calloc(1,sizeof(struct NR_RadioBearerConfig)); AssertFatal(rb_config != NULL,"failed to allocate memory for rb_config"); if(ue_context_pP->ue_context.DRB_configList->list.count != 0) { rb_config->drb_ToAddModList = calloc(1,sizeof(struct NR_DRB_ToAddModList )); - AssertFatal(rb_config->drb_ToAddModList != NULL,"failed to allocated memory for drbtoaddmodlist"); - rb_config->drb_ToAddModList->list.count = ue_context_pP->ue_context.DRB_configList->list.count; - rb_config->drb_ToAddModList->list.array - = calloc(ue_context_pP->ue_context.DRB_configList->list.count, sizeof(struct NR_DRB_ToAddMod)); - AssertFatal( rb_config->drb_ToAddModList->list.array != NULL, - "falied to allocate memory for list.array"); - for(index = 0;index < NUMBEROF_DRBS_TOBE_ADDED;index++) { - rb_config->drb_ToAddModList->list.array[index] - = calloc(1,sizeof(struct NR_DRB_ToAddMod)); - AssertFatal(rb_config->drb_ToAddModList->list.array[index] != NULL, - "failed to allocate memory for drb_toaddmod"); - rb_config->drb_ToAddModList->list.array[index]->drb_Identity - =ue_context_pP->ue_context.DRB_configList->list.array[index]->drb_Identity; - if(ue_context_pP->ue_context.DRB_configList->list.array[index]->eps_BearerIdentity) { - rb_config->drb_ToAddModList->list.array[index]->cnAssociation - =calloc(1,sizeof(struct NR_DRB_ToAddMod__cnAssociation)); - AssertFatal(rb_config->drb_ToAddModList->list.array[index]->cnAssociation != NULL, - "failed to allocate memory cnAssociation"); - rb_config->drb_ToAddModList->list.array[index]->cnAssociation->present - =NR_DRB_ToAddMod__cnAssociation_PR_eps_BearerIdentity; - rb_config->drb_ToAddModList->list.array[index]->cnAssociation->choice.eps_BearerIdentity - =*(ue_context_pP->ue_context.DRB_configList->list.array[index]->eps_BearerIdentity); - } - rb_config->drb_ToAddModList->list.array[index]->pdcp_Config = calloc(1,sizeof(struct NR_PDCP_Config)); - rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb = calloc(1,sizeof(struct NR_PDCP_Config__drb)); - rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->discardTimer = calloc(1,sizeof(long*)); - *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->discardTimer - = *(ue_context_pP->ue_context.DRB_configList->list.array[index]->pdcp_Config->discardTimer); - rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeUL = calloc(1,sizeof(long*)); - *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeUL - = NR_PDCP_Config__drb__pdcp_SN_SizeUL_len18bits; - rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeDL = calloc(1,sizeof(long*)); - *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeDL - = NR_PDCP_Config__drb__pdcp_SN_SizeDL_len18bits; - rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->headerCompression.present - = NR_PDCP_Config__drb__headerCompression_PR_notUsed; - rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->headerCompression.choice.notUsed = 0; - rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->t_Reordering = calloc(1,sizeof(long*)); - *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->t_Reordering - = NR_PDCP_Config__t_Reordering_ms0; - } - rb_config->securityConfig = calloc(1,sizeof(struct NR_SecurityConfig )); - rb_config->securityConfig->securityAlgorithmConfig = calloc(1,sizeof(struct NR_SecurityAlgorithmConfig)); - rb_config->securityConfig->securityAlgorithmConfig->cipheringAlgorithm = NR_CipheringAlgorithm_nea0; - rb_config->securityConfig->securityAlgorithmConfig->integrityProtAlgorithm = NULL; - rb_config->securityConfig->keyToUse = calloc(1,sizeof(long*)); - *rb_config->securityConfig->keyToUse = NR_SecurityConfig__keyToUse_master; + AssertFatal(rb_config->drb_ToAddModList != NULL,"failed to allocated memory for drbtoaddmodlist"); + rb_config->drb_ToAddModList->list.count = NUMBEROF_DRBS_TOBE_ADDED; + rb_config->drb_ToAddModList->list.array + = calloc(NUMBEROF_DRBS_TOBE_ADDED, sizeof(struct NR_DRB_ToAddMod *)); + AssertFatal( rb_config->drb_ToAddModList->list.array != NULL, + "falied to allocate memory for list.array"); + + for(index = 0; index < NUMBEROF_DRBS_TOBE_ADDED; index++) { + rb_config->drb_ToAddModList->list.array[index] + = calloc(1,sizeof(struct NR_DRB_ToAddMod)); + AssertFatal(rb_config->drb_ToAddModList->list.array[index] != NULL, + "failed to allocate memory for drb_toaddmod"); + rb_config->drb_ToAddModList->list.array[index]->drb_Identity + = ue_context_pP->ue_context.DRB_configList->list.array[index]->drb_Identity; + + if(ue_context_pP->ue_context.DRB_configList->list.array[index]->eps_BearerIdentity) { + rb_config->drb_ToAddModList->list.array[index]->cnAssociation + = calloc(1,sizeof(struct NR_DRB_ToAddMod__cnAssociation)); + AssertFatal(rb_config->drb_ToAddModList->list.array[index]->cnAssociation != NULL, + "failed to allocate memory cnAssociation"); + rb_config->drb_ToAddModList->list.array[index]->cnAssociation->present + = NR_DRB_ToAddMod__cnAssociation_PR_eps_BearerIdentity; + rb_config->drb_ToAddModList->list.array[index]->cnAssociation->choice.eps_BearerIdentity + = *(ue_context_pP->ue_context.DRB_configList->list.array[index]->eps_BearerIdentity); + } + + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config = calloc(1,sizeof(struct NR_PDCP_Config)); + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb = calloc(1,sizeof(struct NR_PDCP_Config__drb)); + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->discardTimer = calloc(1,sizeof(long)); + *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->discardTimer + = *(ue_context_pP->ue_context.DRB_configList->list.array[index]->pdcp_Config->discardTimer); + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeUL = calloc(1,sizeof(long)); + *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeUL + = NR_PDCP_Config__drb__pdcp_SN_SizeUL_len18bits; + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeDL = calloc(1,sizeof(long)); + *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeDL + = NR_PDCP_Config__drb__pdcp_SN_SizeDL_len18bits; + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->headerCompression.present + = NR_PDCP_Config__drb__headerCompression_PR_notUsed; + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->headerCompression.choice.notUsed = 0; + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->t_Reordering = calloc(1,sizeof(long)); + *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->t_Reordering + = NR_PDCP_Config__t_Reordering_ms0; + } + + rb_config->securityConfig = calloc(1,sizeof(struct NR_SecurityConfig )); + rb_config->securityConfig->securityAlgorithmConfig = calloc(1,sizeof(struct NR_SecurityAlgorithmConfig)); + rb_config->securityConfig->securityAlgorithmConfig->cipheringAlgorithm = NR_CipheringAlgorithm_nea0; + rb_config->securityConfig->securityAlgorithmConfig->integrityProtAlgorithm = NULL; + rb_config->securityConfig->keyToUse = calloc(1,sizeof(long)); + *rb_config->securityConfig->keyToUse = NR_SecurityConfig__keyToUse_master; } cg_configinfo = calloc(1,sizeof(struct NR_CG_ConfigInfo)); AssertFatal(cg_configinfo != NULL,"failed to allocate memory for cg_configinfo"); cg_configinfo->criticalExtensions.present = NR_CG_ConfigInfo__criticalExtensions_PR_c1; - cg_configinfo->criticalExtensions.choice.c1 - = calloc(1, sizeof(struct NR_CG_ConfigInfo__criticalExtensions__c1)); + cg_configinfo->criticalExtensions.choice.c1 + = calloc(1, sizeof(struct NR_CG_ConfigInfo__criticalExtensions__c1)); AssertFatal(cg_configinfo->criticalExtensions.choice.c1 != NULL, - "failed to allocate memory for cg_configinfo->criticalExtensions.choice.c1"); - cg_configinfo->criticalExtensions.choice.c1->present - = NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo; - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo - = calloc(1,sizeof(struct NR_CG_ConfigInfo_IEs)); + "failed to allocate memory for cg_configinfo->criticalExtensions.choice.c1"); + cg_configinfo->criticalExtensions.choice.c1->present + = NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo; + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo + = calloc(1,sizeof(struct NR_CG_ConfigInfo_IEs)); AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo != NULL, - "failed to allocate memory for cg_configinfo_IEs"); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo - = calloc(1,sizeof( OCTET_STRING_t)); + "failed to allocate memory for cg_configinfo_IEs"); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo + = calloc(1,sizeof( OCTET_STRING_t)); AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> - ue_CapabilityInfo != NULL, "failed to allocate memory for ue_capabilityinfo"); -#if 1 - enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,NULL, - (void*)ue_context_pP->ue_context.UE_Capability,temp_buff,ASN_MAX_ENCODE_SIZE); - AssertFatal(enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", - enc_rval.failed_type->name, enc_rval.encoded); - OCTET_STRING_fromBuf( cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo, - (const char *)temp_buff,(enc_rval.encoded+7)>>3); -#endif + ue_CapabilityInfo != NULL, "failed to allocate memory for ue_capabilityinfo"); -#if 0 - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->size - = ue_context_pP->ue_context.UE_Capability_size; - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf - = calloc(1,ue_context_pP->ue_context.UE_Capability_size); - AssertFatal( cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> - ue_CapabilityInfo->buf != NULL, "failed to allocate memory for buf"); - memcpy(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf, - ue_context_pP->ue_context.UE_Capability,ue_context_pP->ue_context.UE_Capability_size); -#endif -#if 1 - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config - = calloc(1,sizeof(OCTET_STRING_t)); + if(ue_context_pP->ue_context.UE_Capability_MRDC) { + RAT_Container_count++; + enc_rval = uper_encode_to_buffer(&asn_DEF_NR_UE_MRDC_Capability,NULL, + (void *)ue_context_pP->ue_context.UE_Capability_MRDC,temp_buff,ASN_MAX_ENCODE_SIZE); + AssertFatal(enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + ue_cap_rat_container_MRDC.rat_Type = LTE_RAT_Type_eutra_nr; + OCTET_STRING_fromBuf(&ue_cap_rat_container_MRDC.ueCapabilityRAT_Container, + (const char *)temp_buff,(enc_rval.encoded+7)>>3); + memset((void *)temp_buff,0,sizeof(temp_buff)); + } + + if(ue_context_pP->ue_context.UE_Capability_nr) { + RAT_Container_count++; + enc_rval = uper_encode_to_buffer(&asn_DEF_NR_UE_NR_Capability,NULL, + (void *)ue_context_pP->ue_context.UE_Capability_nr,temp_buff,ASN_MAX_ENCODE_SIZE); + AssertFatal(enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + ue_cap_rat_container_nr.rat_Type = LTE_RAT_Type_nr; + OCTET_STRING_fromBuf(&ue_cap_rat_container_nr.ueCapabilityRAT_Container, + (const char *)temp_buff,(enc_rval.encoded+7)>>3); + memset((void *)temp_buff,0,sizeof(temp_buff)); + } + + ue_cap_rat_container_list = calloc(1,sizeof(LTE_UE_CapabilityRAT_ContainerList_t)); + ue_cap_rat_container_list->list.count = RAT_Container_count; + ue_cap_rat_container_list->list.size = sizeof(RAT_Container_count * sizeof(LTE_UE_CapabilityRAT_Container_t)); + ue_cap_rat_container_list->list.array = calloc(RAT_Container_count,sizeof(LTE_UE_CapabilityRAT_Container_t *)); + + if(ue_context_pP->ue_context.UE_Capability_MRDC) { + ue_cap_rat_container_list->list.array[0] = calloc(1,sizeof(LTE_UE_CapabilityRAT_Container_t)); + memcpy(ue_cap_rat_container_list->list.array[0],&ue_cap_rat_container_MRDC,sizeof(LTE_UE_CapabilityRAT_Container_t)); + } + + if(ue_context_pP->ue_context.UE_Capability_nr) { + ue_cap_rat_container_list->list.array[1] = calloc(1,sizeof(LTE_UE_CapabilityRAT_Container_t)); + memcpy(ue_cap_rat_container_list->list.array[1],&ue_cap_rat_container_nr,sizeof(LTE_UE_CapabilityRAT_Container_t)); + } + + //this xer_fprint logs can be enabled for additional debugging logs + //xer_fprint(stdout,&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,ue_cap_rat_container_list); + enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,NULL, + (void *)ue_cap_rat_container_list,temp_buff,ASN_MAX_ENCODE_SIZE); + AssertFatal(enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + OCTET_STRING_fromBuf(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo, + (const char *)temp_buff, (enc_rval.encoded+7)>>3); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config + = calloc(1,sizeof(OCTET_STRING_t)); AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> - mcg_RB_Config != NULL, "failed to allocate memory for mcg_rb_config"); + mcg_RB_Config != NULL, "failed to allocate memory for mcg_rb_config"); enc_rval = uper_encode_to_buffer(&asn_DEF_NR_RadioBearerConfig,NULL,(void *)rb_config,temp_buff,ASN_MAX_ENCODE_SIZE); AssertFatal(enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", - enc_rval.failed_type->name, enc_rval.encoded); + enc_rval.failed_type->name, enc_rval.encoded); OCTET_STRING_fromBuf(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config, - (const char *)temp_buff, (enc_rval.encoded+7)>>3); -#endif -#if 0 - AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> - mcg_RB_Config != NULL, "failed to allocate memory for mcg_rb_config"); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->size - = sizeof( struct NR_RadioBearerConfig); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf - = calloc(1,sizeof(struct NR_RadioBearerConfig)); - AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> - mcg_RB_Config->buf != NULL,"failed to allocate memory for buf"); - memcpy(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf, - rb_config,sizeof(struct NR_RadioBearerConfig)); -#endif - // this xer_fprint can be enabled for additional debugging messages - xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo,(void*)cg_configinfo); - enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CG_ConfigInfo,NULL,(void*)cg_configinfo, - buffer,buffer_size); + (const char *)temp_buff, (enc_rval.encoded+7)>>3); + // this xer_fprint can be enabled for additional debugging messages + // xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo,(void *)cg_configinfo); + enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CG_ConfigInfo,NULL,(void *)cg_configinfo, + buffer,buffer_size); AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %lu)!\n", - enc_rval.failed_type->name, enc_rval.encoded); + enc_rval.failed_type->name, enc_rval.encoded); *enc_size = (enc_rval.encoded+7)/8; - free_rb_config(rb_config); - free_cg_configinfo(cg_configinfo); + ASN_STRUCT_FREE(asn_DEF_NR_RadioBearerConfig,rb_config); + ASN_STRUCT_FREE(asn_DEF_NR_CG_ConfigInfo,cg_configinfo); + ASN_STRUCT_FREE(asn_DEF_LTE_UE_CapabilityRAT_ContainerList,ue_cap_rat_container_list); return RRC_OK; - } -//----------------------------------------------------------------------------- - - - -/** - * @fn :api to free the all the dynamically allocated memory - * @param :cg_configinfo contains cellgroup configuration - */ -static void free_cg_configinfo( - struct NR_CG_ConfigInfo *cg_configinfo -) { - if(cg_configinfo){ - if(cg_configinfo->criticalExtensions.choice.c1){ - if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo){ - if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo){ - if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf){ - if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config){ - if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf){ - free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf =NULL; - free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config =NULL; - free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf = NULL; - free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo =NULL; - free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo =NULL; - free(cg_configinfo->criticalExtensions.choice.c1); - cg_configinfo->criticalExtensions.choice.c1 =NULL; - free(cg_configinfo); - cg_configinfo =NULL; - } - } - } - } - } - } - } - return; } //----------------------------------------------------------------------------- -//----------------------------------------------------------------------------- -/** - * @fn :api to free the all the dynamically allocated memory - * @param :rb_config contains radiobearer configuration - */ -static void free_rb_config( - struct NR_RadioBearerConfig *rb_config -) { - int index = 0; - - if(rb_config) { - if(rb_config->drb_ToAddModList) { - if(rb_config->drb_ToAddModList->list.array) { - for(index = 0; index < rb_config->drb_ToAddModList->list.count; index++) { - if(rb_config->drb_ToAddModList->list.array[index]->cnAssociation) { - free(rb_config->drb_ToAddModList->list.array[index]->cnAssociation); - rb_config->drb_ToAddModList->list.array[index]->cnAssociation = NULL; - } - if(rb_config->drb_ToAddModList->list.array[index]) { - free(rb_config->drb_ToAddModList->list.array[index]); - rb_config->drb_ToAddModList->list.array[index] = NULL; - } - } - free(rb_config->drb_ToAddModList->list.array); - rb_config->drb_ToAddModList->list.array = NULL; - free(rb_config->drb_ToAddModList); - rb_config->drb_ToAddModList = NULL; - free(rb_config); - rb_config = NULL; - } - } - } - return; -} -//------------------------------------------------------------------------------ - @@ -4634,36 +4589,39 @@ rrc_eNB_process_MeasurementReport( ue_context_pP->ue_context.Status = RRC_NR_NSA; if(is_en_dc_supported(ue_context_pP->ue_context.UE_Capability)) { -/** to add gNB as Secondary node CG-ConfigInfo to be added as per 36.423 r15 **/ - if(encode_CG_ConfigInfo(enc_buf,sizeof(enc_buf),ue_context_pP,&enc_size) == RRC_OK) - LOG_I(RRC,"CG-ConfigInfo encoded successfully\n"); - msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ); - memset(&(X2AP_ENDC_SGNB_ADDITION_REQ(msg)), 0, sizeof(x2ap_ENDC_sgnb_addition_req_t)); - X2AP_ENDC_SGNB_ADDITION_REQ(msg).rnti = ctxt_pP->rnti; - memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer,enc_buf,enc_size); - X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer_size = enc_size; - X2AP_ENDC_SGNB_ADDITION_REQ(msg).target_physCellId - = measResults2->measResultNeighCells->choice.measResultListEUTRA.list.array[0]->physCellId; + /** to add gNB as Secondary node CG-ConfigInfo to be added as per 36.423 r15 **/ + if(encode_CG_ConfigInfo(enc_buf,sizeof(enc_buf),ue_context_pP,&enc_size) == RRC_OK) + LOG_I(RRC,"CG-ConfigInfo encoded successfully\n"); - //For the moment we have a single E-RAB which will be the one to be added to the gNB - //Not sure how to select bearers to be added if there are multiple. - X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded = 1; - for (int e_rab=0; e_rab < X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded; e_rab++){ - X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].e_rab_id = ue_context_pP->ue_context.e_rab[e_rab].param.e_rab_id; - X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].gtp_teid = ue_context_pP->ue_context.e_rab[e_rab].param.gtp_teid; - X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].drb_ID = 1; - memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr, - &ue_context_pP->ue_context.e_rab[e_rab].param.sgw_addr, - sizeof(transport_layer_addr_t)); - } - LOG_I(RRC, - "[eNB %d] frame %d subframe %d: UE rnti %x switching to NSA mode\n", - ctxt_pP->module_id, ctxt_pP->frame, ctxt_pP->subframe, ctxt_pP->rnti); - itti_send_msg_to_task(TASK_X2AP, ENB_MODULE_ID_TO_INSTANCE(ctxt_pP->module_id), msg); - return; + msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ); + memset(&(X2AP_ENDC_SGNB_ADDITION_REQ(msg)), 0, sizeof(x2ap_ENDC_sgnb_addition_req_t)); + X2AP_ENDC_SGNB_ADDITION_REQ(msg).rnti = ctxt_pP->rnti; + memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer,enc_buf,enc_size); + X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer_size = enc_size; + X2AP_ENDC_SGNB_ADDITION_REQ(msg).target_physCellId + = measResults2->measResultNeighCells->choice.measResultListEUTRA.list.array[0]->physCellId; + //For the moment we have a single E-RAB which will be the one to be added to the gNB + //Not sure how to select bearers to be added if there are multiple. + X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded = 1; + + for (int e_rab=0; e_rab < X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded; e_rab++) { + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].e_rab_id = ue_context_pP->ue_context.e_rab[e_rab].param.e_rab_id; + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].gtp_teid = ue_context_pP->ue_context.e_rab[e_rab].param.gtp_teid; + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].drb_ID = 1; + memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr, + &ue_context_pP->ue_context.e_rab[e_rab].param.sgw_addr, + sizeof(transport_layer_addr_t)); + } + + LOG_I(RRC, + "[eNB %d] frame %d subframe %d: UE rnti %x switching to NSA mode\n", + ctxt_pP->module_id, ctxt_pP->frame, ctxt_pP->subframe, ctxt_pP->rnti); + itti_send_msg_to_task(TASK_X2AP, ENB_MODULE_ID_TO_INSTANCE(ctxt_pP->module_id), msg); + return; } + } } -} + if (measResults2->measResultNeighCells == NULL) return; @@ -6306,6 +6264,7 @@ rrc_eNB_generate_HO_RRCConnectionReconfiguration(const protocol_ctxt_t *const ct ue_context_pP->ue_context.e_rab[i].param.nas_pdu.buffer = NULL; } } + LOG_I(RRC, "[eNB %d] Frame %d, Logical Channel DL-DCCH, Generate RRCConnectionReconfiguration handover (bytes %d, UE id %x)\n", ctxt_pP->module_id, ctxt_pP->frame, size, ue_context_pP->ue_context.rnti); @@ -6445,10 +6404,8 @@ rrc_eNB_process_RRCConnectionReconfigurationComplete( LTE_SRB_ToAddModList_t *SRB_configList = ue_context_pP->ue_context.SRB_configList2[xid]; LTE_DRB_ToReleaseList_t *DRB_Release_configList2 = ue_context_pP->ue_context.DRB_Release_configList2[xid]; LTE_DRB_Identity_t *drb_id_p = NULL; - ue_context_pP->ue_context.ue_reestablishment_timer = 0; ue_context_pP->ue_context.ue_rrc_inactivity_timer = 1; // reset rrc inactivity timer - /* CDRX: activated when RRC Connection Reconfiguration Complete is received */ rnti_t rnti = ue_context_pP->ue_id_rnti; module_id_t module_id = ctxt_pP->module_id; @@ -6469,8 +6426,8 @@ rrc_eNB_process_RRCConnectionReconfigurationComplete( LOG_I(RRC, "CDRX configuration activated after RRC Connection Reconfiguration Complete reception\n"); } } - /* End of CDRX processing */ + /* End of CDRX processing */ T(T_ENB_RRC_CONNECTION_RECONFIGURATION_COMPLETE, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame), @@ -6729,7 +6686,6 @@ rrc_eNB_process_RRCConnectionReconfigurationComplete( ue_context_pP->ue_context.nr_capabilities_requested = 1; rrc_eNB_generate_NR_UECapabilityEnquiry(ctxt_pP, ue_context_pP); } - } //----------------------------------------------------------------------------- @@ -7560,33 +7516,34 @@ is_en_dc_supported( */ #define NCE nonCriticalExtension return c != NULL - && c->NCE != NULL - && c->NCE->NCE != NULL - && c->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15 != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15->en_DC_r15 != NULL - && *c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15->en_DC_r15 == LTE_IRAT_ParametersNR_r15__en_DC_r15_supported; + && c->NCE != NULL + && c->NCE->NCE != NULL + && c->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15 != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15->en_DC_r15 != NULL + && *c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15->en_DC_r15 == + LTE_IRAT_ParametersNR_r15__en_DC_r15_supported; #undef NCE } @@ -7775,37 +7732,36 @@ rrc_eNB_decode_dcch( //Looking for a condition to trigger S1AP E-RAB-Modification-indication, based on the reception of RRCConnectionReconfigurationComplete //including NR specific elements. Not sure if this is the correct one and the correct placement /*if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. - nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension-> - scg_ConfigResponseNR_r15->buf!=NULL){ - //Trigger E-RAB Modification Indication - rrc_eNB_send_E_RAB_Modification_Indication(ctxt_pP, ue_context_p); + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension-> + scg_ConfigResponseNR_r15->buf!=NULL){ + //Trigger E-RAB Modification Indication + rrc_eNB_send_E_RAB_Modification_Indication(ctxt_pP, ue_context_p); }*/ if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. - nonCriticalExtension!=NULL){ - if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. - nonCriticalExtension->nonCriticalExtension!=NULL){ - if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. - nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL){ - if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. - nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL){ - if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. - nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL){ - if (ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. - nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL){ - if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. - nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension - ->scg_ConfigResponseNR_r15!=NULL){ - /*Trigger E-RAB Modification Indication */ - rrc_eNB_send_E_RAB_Modification_Indication(ctxt_pP, ue_context_p); - } - } - } - } - } - } + nonCriticalExtension!=NULL) { + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension!=NULL) { + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) { + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) { + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) { + if (ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) { + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension + ->scg_ConfigResponseNR_r15!=NULL) { + /*Trigger E-RAB Modification Indication */ + rrc_eNB_send_E_RAB_Modification_Indication(ctxt_pP, ue_context_p); + } + } + } + } + } + } } - } else { dedicated_DRB = 1; ue_context_p->ue_context.Status = RRC_RECONFIGURED; @@ -8153,15 +8109,74 @@ rrc_eNB_decode_dcch( } LOG_I(RRC, "got UE capabilities for UE %x\n", ctxt_pP->rnti); - int eutra_index = -1; for (i = 0; i < ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.count; i++) { - if (ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->rat_Type == LTE_RAT_Type_eutra) { + if (ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->rat_Type == + LTE_RAT_Type_nr) { + if(ue_context_p->ue_context.UE_Capability_nr) { + ASN_STRUCT_FREE(asn_DEF_NR_UE_NR_Capability,ue_context_p->ue_context.UE_Capability_nr); + ue_context_p->ue_context.UE_Capability_nr = 0; + } + + dec_rval = uper_decode(NULL, + &asn_DEF_NR_UE_NR_Capability, + (void **)&ue_context_p->ue_context.UE_Capability_nr, + ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->ueCapabilityRAT_Container.buf, + ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->ueCapabilityRAT_Container.size, + 0, 0); + + if (LOG_DEBUGFLAG(DEBUG_ASN1)) { + xer_fprint(stdout, &asn_DEF_NR_UE_NR_Capability, ue_context_p->ue_context.UE_Capability_nr); + } + + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + LOG_E(RRC, PROTOCOL_RRC_CTXT_UE_FMT" Failed to decode nr UE capabilities (%zu bytes)\n", + PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP),dec_rval.consumed); + ASN_STRUCT_FREE(asn_DEF_NR_UE_NR_Capability,ue_context_p->ue_context.UE_Capability_nr); + ue_context_p->ue_context.UE_Capability_nr = 0; + } + + ue_context_p->ue_context.UE_NR_Capability_size = + ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->ueCapabilityRAT_Container.size; + } + + if (ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->rat_Type == + LTE_RAT_Type_eutra_nr) { + if(ue_context_p->ue_context.UE_Capability_MRDC) { + ASN_STRUCT_FREE(asn_DEF_NR_UE_MRDC_Capability,ue_context_p->ue_context.UE_Capability_MRDC); + ue_context_p->ue_context.UE_Capability_MRDC = 0; + } + + dec_rval = uper_decode(NULL, + &asn_DEF_NR_UE_MRDC_Capability, + (void **)&ue_context_p->ue_context.UE_Capability_MRDC, + ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->ueCapabilityRAT_Container.buf, + ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->ueCapabilityRAT_Container.size, + 0, 0); + + if (LOG_DEBUGFLAG(DEBUG_ASN1)) { + xer_fprint(stdout, &asn_DEF_NR_UE_MRDC_Capability, ue_context_p->ue_context.UE_Capability_MRDC); + } + + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + LOG_E(RRC, PROTOCOL_RRC_CTXT_UE_FMT" Failed to decode MRDC UE capabilities (%zu bytes)\n", + PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP),dec_rval.consumed); + ASN_STRUCT_FREE(asn_DEF_NR_UE_MRDC_Capability,ue_context_p->ue_context.UE_Capability_MRDC); + ue_context_p->ue_context.UE_Capability_MRDC = 0; + } + + ue_context_p->ue_context.UE_MRDC_Capability_size = + ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->ueCapabilityRAT_Container.size; + } + + if (ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->rat_Type == + LTE_RAT_Type_eutra) { if (eutra_index != -1) { LOG_E(RRC, "fatal: more than 1 eutra capability\n"); exit(1); } + eutra_index = i; } } @@ -8183,7 +8198,8 @@ rrc_eNB_decode_dcch( ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[eutra_index]->ueCapabilityRAT_Container.buf, ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[eutra_index]->ueCapabilityRAT_Container.size, 0, 0); - ue_context_p->ue_context.UE_Capability_size = ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[eutra_index]->ueCapabilityRAT_Container.size; + ue_context_p->ue_context.UE_Capability_size = + ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[eutra_index]->ueCapabilityRAT_Container.size; if ( LOG_DEBUGFLAG(DEBUG_ASN1) ) { xer_fprint(stdout, &asn_DEF_LTE_UE_EUTRA_Capability, ue_context_p->ue_context.UE_Capability); @@ -8765,117 +8781,109 @@ void rrc_subframe_process(protocol_ctxt_t *const ctxt_pP, const int CC_id) { } void rrc_eNB_process_AdditionResponseInformation(const module_id_t enb_mod_idP, x2ap_ENDC_sgnb_addition_req_ACK_t *m) { + NR_CG_Config_t *CG_Config = NULL; + { + int i; + printf("%d: ", m->rrc_buffer_size); + for (i=0; irrc_buffer_size; i++) printf("%2.2x", (unsigned char)m->rrc_buffer[i]); - NR_CG_Config_t *CG_Config = NULL; + printf("\n"); + } + asn_dec_rval_t dec_rval = uper_decode_complete( NULL, + &asn_DEF_NR_CG_Config, + (void **)&CG_Config, + (uint8_t *)m->rrc_buffer, + (int) m->rrc_buffer_size);//m->rrc_buffer_size); - { - int i; - printf("%d: ", m->rrc_buffer_size); - for (i=0; irrc_buffer_size; i++) printf("%2.2x", (unsigned char)m->rrc_buffer[i]); - printf("\n"); + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + AssertFatal(1==0,"NR_UL_DCCH_MESSAGE decode error\n"); + // free the memory + SEQUENCE_free( &asn_DEF_NR_CG_Config, CG_Config, 1 ); + return; + } - } - asn_dec_rval_t dec_rval = uper_decode_complete( NULL, - &asn_DEF_NR_CG_Config, - (void **)&CG_Config, - (uint8_t *)m->rrc_buffer, - (int) m->rrc_buffer_size);//m->rrc_buffer_size); + xer_fprint(stdout,&asn_DEF_NR_CG_Config, CG_Config); + // recreate enough of X2 EN-DC Container + AssertFatal(CG_Config->criticalExtensions.choice.c1->present == NR_CG_Config__criticalExtensions__c1_PR_cg_Config, + "CG_Config not present\n"); + OCTET_STRING_t *scg_CellGroupConfig = NULL; + OCTET_STRING_t *nr1_conf = NULL; - if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { - AssertFatal(1==0,"NR_UL_DCCH_MESSAGE decode error\n"); - // free the memory - SEQUENCE_free( &asn_DEF_NR_CG_Config, CG_Config, 1 ); - return; - } - xer_fprint(stdout,&asn_DEF_NR_CG_Config, CG_Config); - // recreate enough of X2 EN-DC Container - - AssertFatal(CG_Config->criticalExtensions.choice.c1->present == NR_CG_Config__criticalExtensions__c1_PR_cg_Config, - "CG_Config not present\n"); - - OCTET_STRING_t *scg_CellGroupConfig = NULL; - OCTET_STRING_t *nr1_conf = NULL; - - if(CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig){ - scg_CellGroupConfig = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig; + if(CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig) { + scg_CellGroupConfig = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig; #ifdef DEBUG_SCG_CONFIG - { - int size_s = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig->size; - int i; - LOG_I(RRC, "Dumping scg_CellGroupConfig: %d", size_s); - for (i=0; icriticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig->buf[i]); - printf("\n"); + { + int size_s = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig->size; + int i; + LOG_I(RRC, "Dumping scg_CellGroupConfig: %d", size_s); - } + for (i=0; icriticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig->buf[i]); + + printf("\n"); + } #endif + } else { + LOG_W(RRC, "SCG Cell group configuration is not present in the Addition Response message \n"); + return; + } - } - else{ - LOG_W(RRC, "SCG Cell group configuration is not present in the Addition Response message \n"); - return; - } - if(CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config){ - nr1_conf = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config; + if(CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config) { + nr1_conf = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config; #ifdef DEBUG_SCG_CONFIG - { - int size_s = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config->size; - int i; - LOG_I(RRC, "Dumping scg_RB_Config: %d", size_s); - for (i=0; icriticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config->buf[i]); - printf("\n"); + { + int size_s = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config->size; + int i; + LOG_I(RRC, "Dumping scg_RB_Config: %d", size_s); - } + for (i=0; icriticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config->buf[i]); + + printf("\n"); + } #endif - } - else{ - LOG_W(RRC, "SCG RB configuration is not present in the Addition Response message \n"); - return; + } else { + LOG_W(RRC, "SCG RB configuration is not present in the Addition Response message \n"); + return; + } + + protocol_ctxt_t ctxt; + rrc_eNB_ue_context_t *ue_context; + unsigned char buffer[8192]; + int size; + ue_context = rrc_eNB_get_ue_context(RC.rrc[enb_mod_idP], m->rnti); + ue_context->ue_context.nb_of_modify_endc_e_rabs = m->nb_e_rabs_admitted_tobeadded; + int j=0; + + while(j < m->nb_e_rabs_admitted_tobeadded) { + for (int e_rab_idx=0; e_rab_idxue_context.setup_e_rabs; e_rab_idx++) { + //Update ue_context information with gNB's address and new GTP tunnel ID + if( ue_context->ue_context.e_rab[e_rab_idx].param.e_rab_id == m->e_rabs_admitted_tobeadded[j].e_rab_id) { + memcpy(ue_context->ue_context.gnb_gtp_endc_addrs[e_rab_idx].buffer, + m->e_rabs_admitted_tobeadded[j].gnb_addr.buffer, + m->e_rabs_admitted_tobeadded[j].gnb_addr.length); + ue_context->ue_context.gnb_gtp_endc_addrs[e_rab_idx].length = m->e_rabs_admitted_tobeadded[j].gnb_addr.length; + ue_context->ue_context.gnb_gtp_endc_teid[e_rab_idx] = m->e_rabs_admitted_tobeadded[j].gtp_teid; + ue_context->ue_context.e_rab[e_rab_idx].status = E_RAB_STATUS_TOMODIFY; + break; + } } - protocol_ctxt_t ctxt; - rrc_eNB_ue_context_t *ue_context; - unsigned char buffer[8192]; - int size; + j++; + } - ue_context = rrc_eNB_get_ue_context(RC.rrc[enb_mod_idP], m->rnti); - - ue_context->ue_context.nb_of_modify_endc_e_rabs = m->nb_e_rabs_admitted_tobeadded; - - int j=0; - while(j < m->nb_e_rabs_admitted_tobeadded){ - for (int e_rab_idx=0; e_rab_idxue_context.setup_e_rabs; e_rab_idx++){ - //Update ue_context information with gNB's address and new GTP tunnel ID - if( ue_context->ue_context.e_rab[e_rab_idx].param.e_rab_id == m->e_rabs_admitted_tobeadded[j].e_rab_id){ - memcpy(ue_context->ue_context.gnb_gtp_endc_addrs[e_rab_idx].buffer, - m->e_rabs_admitted_tobeadded[j].gnb_addr.buffer, - m->e_rabs_admitted_tobeadded[j].gnb_addr.length); - ue_context->ue_context.gnb_gtp_endc_addrs[e_rab_idx].length = m->e_rabs_admitted_tobeadded[j].gnb_addr.length; - ue_context->ue_context.gnb_gtp_endc_teid[e_rab_idx] = m->e_rabs_admitted_tobeadded[j].gtp_teid; - ue_context->ue_context.e_rab[e_rab_idx].status = E_RAB_STATUS_TOMODIFY; - break; - } - } - j++; - } - - - - PROTOCOL_CTXT_SET_BY_INSTANCE(&ctxt, - 0, - ENB_FLAG_YES, - m->rnti, - 0, 0); - - size = rrc_eNB_generate_RRCConnectionReconfiguration_endc(&ctxt, ue_context, buffer, 8192, scg_CellGroupConfig, nr1_conf); - - rrc_data_req(&ctxt, - DCCH, - rrc_eNB_mui++, - SDU_CONFIRM_NO, - size, - buffer, - PDCP_TRANSMISSION_MODE_CONTROL); + PROTOCOL_CTXT_SET_BY_INSTANCE(&ctxt, + 0, + ENB_FLAG_YES, + m->rnti, + 0, 0); + size = rrc_eNB_generate_RRCConnectionReconfiguration_endc(&ctxt, ue_context, buffer, 8192, scg_CellGroupConfig, nr1_conf); + rrc_data_req(&ctxt, + DCCH, + rrc_eNB_mui++, + SDU_CONFIRM_NO, + size, + buffer, + PDCP_TRANSMISSION_MODE_CONTROL); } @@ -9158,11 +9166,10 @@ void *rrc_enb_process_itti_msg(void *notUsed) { } case X2AP_ENDC_SGNB_ADDITION_REQ_ACK: { - rrc_eNB_process_AdditionResponseInformation(ENB_INSTANCE_TO_MODULE_ID(instance), &X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg_p)); - break; + rrc_eNB_process_AdditionResponseInformation(ENB_INSTANCE_TO_MODULE_ID(instance), &X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg_p)); + break; } - /* Messages from eNB app */ case RRC_CONFIGURATION_REQ: LOG_I(RRC, "[eNB %d] Received %s : %p\n", instance, msg_name_p, &RRC_CONFIGURATION_REQ(msg_p)); @@ -9182,41 +9189,40 @@ void *rrc_enb_process_itti_msg(void *notUsed) { break; case M2AP_SETUP_RESP: - rrc_eNB_process_M2AP_SETUP_RESP(&ctxt,0/*CC_id*/,ENB_INSTANCE_TO_MODULE_ID(instance),&M2AP_SETUP_RESP(msg_p)); + rrc_eNB_process_M2AP_SETUP_RESP(&ctxt,0/*CC_id*/,ENB_INSTANCE_TO_MODULE_ID(instance),&M2AP_SETUP_RESP(msg_p)); break; case M2AP_MBMS_SCHEDULING_INFORMATION: - rrc_eNB_process_M2AP_MBMS_SCHEDULING_INFORMATION(&ctxt,0/*CC_id*/,ENB_INSTANCE_TO_MODULE_ID(instance),&M2AP_MBMS_SCHEDULING_INFORMATION(msg_p)); - break; + rrc_eNB_process_M2AP_MBMS_SCHEDULING_INFORMATION(&ctxt,0/*CC_id*/,ENB_INSTANCE_TO_MODULE_ID(instance),&M2AP_MBMS_SCHEDULING_INFORMATION(msg_p)); + break; case M2AP_MBMS_SESSION_START_REQ: - rrc_eNB_process_M2AP_MBMS_SESSION_START_REQ(&ctxt,0/*CC_id*/,ENB_INSTANCE_TO_MODULE_ID(instance),&M2AP_MBMS_SESSION_START_REQ(msg_p)); - break; + rrc_eNB_process_M2AP_MBMS_SESSION_START_REQ(&ctxt,0/*CC_id*/,ENB_INSTANCE_TO_MODULE_ID(instance),&M2AP_MBMS_SESSION_START_REQ(msg_p)); + break; case M2AP_MBMS_SESSION_STOP_REQ: - rrc_eNB_process_M2AP_MBMS_SESSION_STOP_REQ(&ctxt,&M2AP_MBMS_SESSION_STOP_REQ(msg_p)); - break; + rrc_eNB_process_M2AP_MBMS_SESSION_STOP_REQ(&ctxt,&M2AP_MBMS_SESSION_STOP_REQ(msg_p)); + break; case M2AP_RESET: - rrc_eNB_process_M2AP_RESET(&ctxt,&M2AP_RESET(msg_p)); - break; + rrc_eNB_process_M2AP_RESET(&ctxt,&M2AP_RESET(msg_p)); + break; case M2AP_ENB_CONFIGURATION_UPDATE_ACK: - rrc_eNB_process_M2AP_ENB_CONFIGURATION_UPDATE_ACK(&ctxt,&M2AP_ENB_CONFIGURATION_UPDATE_ACK(msg_p)); - break; + rrc_eNB_process_M2AP_ENB_CONFIGURATION_UPDATE_ACK(&ctxt,&M2AP_ENB_CONFIGURATION_UPDATE_ACK(msg_p)); + break; case M2AP_ERROR_INDICATION: - rrc_eNB_process_M2AP_ERROR_INDICATION(&ctxt,&M2AP_ERROR_INDICATION(msg_p)); - break; + rrc_eNB_process_M2AP_ERROR_INDICATION(&ctxt,&M2AP_ERROR_INDICATION(msg_p)); + break; case M2AP_MBMS_SERVICE_COUNTING_REQ: - rrc_eNB_process_M2AP_MBMS_SERVICE_COUNTING_REQ(&ctxt,&M2AP_MBMS_SERVICE_COUNTING_REQ(msg_p)); - break; + rrc_eNB_process_M2AP_MBMS_SERVICE_COUNTING_REQ(&ctxt,&M2AP_MBMS_SERVICE_COUNTING_REQ(msg_p)); + break; case M2AP_MCE_CONFIGURATION_UPDATE: - rrc_eNB_process_M2AP_MCE_CONFIGURATION_UPDATE(&ctxt,&M2AP_MCE_CONFIGURATION_UPDATE(msg_p)); - break; - + rrc_eNB_process_M2AP_MCE_CONFIGURATION_UPDATE(&ctxt,&M2AP_MCE_CONFIGURATION_UPDATE(msg_p)); + break; default: LOG_E(RRC, "[eNB %d] Received unexpected message %s\n", instance, msg_name_p); @@ -9241,17 +9247,16 @@ rrc_enb_task( //----------------------------------------------------------------------------- { rrc_enb_init(); - itti_mark_task_ready(TASK_RRC_ENB); LOG_I(RRC,"Entering main loop of RRC message task\n"); while (1) { (void) rrc_enb_process_itti_msg(NULL); -{ - //extern volatile int go_nr; - void rrc_go_nr(void); - //if (go_nr) rrc_go_nr(); -} + { + //extern volatile int go_nr; + void rrc_go_nr(void); + //if (go_nr) rrc_go_nr(); + } } } diff --git a/openair2/RRC/NR/rrc_gNB.c b/openair2/RRC/NR/rrc_gNB.c index 8ca8b94b61..cbbea952bb 100644 --- a/openair2/RRC/NR/rrc_gNB.c +++ b/openair2/RRC/NR/rrc_gNB.c @@ -94,12 +94,10 @@ mui_t rrc_gNB_mui = 0; void openair_nr_rrc_on(const protocol_ctxt_t *const ctxt_pP) { LOG_I(NR_RRC, PROTOCOL_NR_RRC_CTXT_FMT" gNB:OPENAIR NR RRC IN....\n",PROTOCOL_NR_RRC_CTXT_ARGS(ctxt_pP)); - rrc_config_nr_buffer (&RC.nrrrc[ctxt_pP->module_id]->carrier.SI, BCCH, 1); RC.nrrrc[ctxt_pP->module_id]->carrier.SI.Active = 1; rrc_config_nr_buffer (&RC.nrrrc[ctxt_pP->module_id]->carrier.Srb0, CCCH, 1); RC.nrrrc[ctxt_pP->module_id]->carrier.Srb0.Active = 1; - } ///---------------------------------------------------------------------------------------------------------------/// @@ -172,7 +170,6 @@ void rrc_gNB_generate_SgNBAdditionRequestAcknowledge( ue_context_pP->ue_context.primaryCC_id, physicalCellGroupConfig, physicalcellgroup_config); - do_SpCellConfig(RC.nrrrc[ctxt_pP->module_id], spCellConfig); } @@ -181,57 +178,47 @@ void rrc_gNB_generate_SgNBAdditionRequestAcknowledge( ///---------------------------------------------------------------------------------------------------------------/// static void init_NR_SI(gNB_RRC_INST *rrc) { - - LOG_D(RRC,"%s()\n\n\n\n",__FUNCTION__); - - - - rrc->carrier.MIB = (uint8_t*) malloc16(4); + rrc->carrier.MIB = (uint8_t *) malloc16(4); rrc->carrier.sizeof_MIB = do_MIB_NR(rrc,0); - - LOG_I(NR_RRC,"Done init_NR_SI\n"); - - rrc_mac_config_req_gNB(rrc->module_id, - rrc->carrier.ssb_SubcarrierOffset, + rrc->carrier.ssb_SubcarrierOffset, rrc->carrier.pdsch_AntennaPorts, (NR_ServingCellConfigCommon_t *)rrc->carrier.servingcellconfigcommon, - 0, - 0, // WIP hardcoded rnti - (NR_CellGroupConfig_t *)NULL - ); - + 0, + 0, // WIP hardcoded rnti + (NR_CellGroupConfig_t *)NULL + ); if (get_softmodem_params()->phy_test > 0 || get_softmodem_params()->do_ra > 0) { // This is for phytest only, emulate first X2 message if uecap.raw file is present FILE *fd; - fd = fopen("uecap.raw","r"); + if (fd != NULL) { char buffer[4096]; int msg_len=fread(buffer,1,4096,fd); LOG_I(RRC,"Read in %d bytes for uecap\n",msg_len); LTE_UL_DCCH_Message_t *LTE_UL_DCCH_Message; - asn_dec_rval_t dec_rval = uper_decode_complete( NULL, - &asn_DEF_LTE_UL_DCCH_Message, - (void **)<E_UL_DCCH_Message, - (uint8_t *)buffer, - msg_len); - + &asn_DEF_LTE_UL_DCCH_Message, + (void **)<E_UL_DCCH_Message, + (uint8_t *)buffer, + msg_len); + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { AssertFatal(1==0,"NR_UL_DCCH_MESSAGE decode error\n"); - // free the memory - SEQUENCE_free( &asn_DEF_LTE_UL_DCCH_Message, LTE_UL_DCCH_Message, 1 ); - return; - } + // free the memory + SEQUENCE_free( &asn_DEF_LTE_UL_DCCH_Message, LTE_UL_DCCH_Message, 1 ); + return; + } + fclose(fd); xer_fprint(stdout,&asn_DEF_LTE_UL_DCCH_Message, LTE_UL_DCCH_Message); // recreate enough of X2 EN-DC Container AssertFatal(LTE_UL_DCCH_Message->message.choice.c1.present == LTE_UL_DCCH_MessageType__c1_PR_ueCapabilityInformation, - "ueCapabilityInformation not present\n"); + "ueCapabilityInformation not present\n"); NR_CG_ConfigInfo_t *CG_ConfigInfo = calloc(1,sizeof(*CG_ConfigInfo)); CG_ConfigInfo->criticalExtensions.present = NR_CG_ConfigInfo__criticalExtensions_PR_c1; CG_ConfigInfo->criticalExtensions.choice.c1 = calloc(1,sizeof(*CG_ConfigInfo->criticalExtensions.choice.c1)); @@ -239,31 +226,27 @@ static void init_NR_SI(gNB_RRC_INST *rrc) { CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo = calloc(1,sizeof(*CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo)); NR_CG_ConfigInfo_IEs_t *cg_ConfigInfo = CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo; cg_ConfigInfo->ue_CapabilityInfo = calloc(1,sizeof(*cg_ConfigInfo->ue_CapabilityInfo)); - asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,NULL,(void*)<E_UL_DCCH_Message->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList,buffer,4096); + asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,NULL, + (void *)<E_UL_DCCH_Message->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList,buffer,4096); AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", - enc_rval.failed_type->name, enc_rval.encoded); + enc_rval.failed_type->name, enc_rval.encoded); OCTET_STRING_fromBuf(cg_ConfigInfo->ue_CapabilityInfo, - (const char *)buffer, - (enc_rval.encoded+7)>>3); + (const char *)buffer, + (enc_rval.encoded+7)>>3); parse_CG_ConfigInfo(rrc,CG_ConfigInfo,NULL); - } - else { + } else { struct rrc_gNB_ue_context_s *ue_context_p = rrc_gNB_allocate_new_UE_context(rrc); - - LOG_I(NR_RRC,"Adding new user (%p)\n",ue_context_p); + LOG_I(NR_RRC,"Adding new user (%p)\n",ue_context_p); rrc_add_nsa_user(rrc,ue_context_p,NULL); - } + } } } char openair_rrc_gNB_configuration(const module_id_t gnb_mod_idP, gNB_RrcConfigurationReq *configuration) { protocol_ctxt_t ctxt; - gNB_RRC_INST *rrc=RC.nrrrc[gnb_mod_idP]; - PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, gnb_mod_idP, GNB_FLAG_YES, NOT_A_RNTI, 0, 0,gnb_mod_idP); - LOG_I(NR_RRC, PROTOCOL_NR_RRC_CTXT_FMT" Init...\n", PROTOCOL_NR_RRC_CTXT_ARGS(&ctxt)); @@ -273,15 +256,14 @@ char openair_rrc_gNB_configuration(const module_id_t gnb_mod_idP, gNB_RrcConfigu LOG_E(NR_RRC, "RC.nrrrc not yet initialized, waiting 1 second\n"); sleep(1); } -#endif + +#endif AssertFatal(rrc != NULL, "RC.nrrrc not initialized!"); AssertFatal(NUMBER_OF_UE_MAX < (module_id_t)0xFFFFFFFFFFFFFFFF, " variable overflow"); AssertFatal(configuration!=NULL,"configuration input is null\n"); rrc->module_id = gnb_mod_idP; rrc->Nb_ue = 0; - rrc->carrier.Srb0.Active = 0; - nr_uid_linear_allocator_init(&rrc->uid_allocator); RB_INIT(&rrc->rrc_ue_head); rrc->initial_id2_s1ap_ids = hashtable_create (NUMBER_OF_UE_MAX * 2, NULL, NULL); @@ -291,7 +273,6 @@ char openair_rrc_gNB_configuration(const module_id_t gnb_mod_idP, gNB_RrcConfigu rrc->carrier.pdsch_AntennaPorts = configuration->pdsch_AntennaPorts; /// System Information INIT LOG_I(NR_RRC, PROTOCOL_NR_RRC_CTXT_FMT" Checking release \n",PROTOCOL_NR_RRC_CTXT_ARGS(&ctxt)); - init_NR_SI(rrc); rrc_init_nr_global_param(); openair_nr_rrc_on(&ctxt); @@ -300,46 +281,26 @@ char openair_rrc_gNB_configuration(const module_id_t gnb_mod_idP, gNB_RrcConfigu void rrc_gNB_process_AdditionRequestInformation(const module_id_t gnb_mod_idP, x2ap_ENDC_sgnb_addition_req_t *m) { + struct NR_CG_ConfigInfo *cg_configinfo = NULL; + asn_dec_rval_t dec_rval = uper_decode_complete(NULL, + &asn_DEF_NR_CG_ConfigInfo, + (void **)&cg_configinfo, + (uint8_t *)m->rrc_buffer, + (int) m->rrc_buffer_size);//m->rrc_buffer_size); + gNB_RRC_INST *rrc=RC.nrrrc[gnb_mod_idP]; + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + AssertFatal(1==0,"NR_UL_DCCH_MESSAGE decode error\n"); + // free the memory + SEQUENCE_free(&asn_DEF_NR_CG_ConfigInfo, cg_configinfo, 1); + return; + } - //LTE_UL_DCCH_Message_t *LTE_UL_DCCH_Message = NULL; - struct NR_CG_ConfigInfo *cg_configinfo = NULL; - - asn_dec_rval_t dec_rval = uper_decode_complete( NULL, - &asn_DEF_NR_CG_ConfigInfo, - (void **)&cg_configinfo, - (uint8_t *)m->rrc_buffer, - (int) m->rrc_buffer_size);//m->rrc_buffer_size); - - gNB_RRC_INST *rrc=RC.nrrrc[gnb_mod_idP]; - - if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { - AssertFatal(1==0,"NR_UL_DCCH_MESSAGE decode error\n"); - // free the memory - SEQUENCE_free(&asn_DEF_NR_CG_ConfigInfo, cg_configinfo, 1); - return; - } - xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo, cg_configinfo); - // recreate enough of X2 EN-DC Container - AssertFatal(cg_configinfo->criticalExtensions.choice.c1->present == NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo, - "ueCapabilityInformation not present\n"); -#if 0 - NR_CG_ConfigInfo_t *CG_ConfigInfo = calloc(1,sizeof(*CG_ConfigInfo)); - CG_ConfigInfo->criticalExtensions.present = NR_CG_ConfigInfo__criticalExtensions_PR_c1; - CG_ConfigInfo->criticalExtensions.choice.c1 = calloc(1,sizeof(*CG_ConfigInfo->criticalExtensions.choice.c1)); - CG_ConfigInfo->criticalExtensions.choice.c1->present = NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo; - CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo = calloc(1,sizeof(*CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo)); - NR_CG_ConfigInfo_IEs_t *cg_ConfigInfo = CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo; - cg_ConfigInfo->ue_CapabilityInfo = calloc(1,sizeof(*cg_ConfigInfo->ue_CapabilityInfo)); - asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,NULL,(void*)<E_UL_DCCH_Message->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList,m->rrc_buffer,m->rrc_buffer_size); - AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", - enc_rval.failed_type->name, enc_rval.encoded); - OCTET_STRING_fromBuf(cg_ConfigInfo->ue_CapabilityInfo, - (const char *)m->rrc_buffer, - (enc_rval.encoded+7)>>3); -#endif - parse_CG_ConfigInfo(rrc,cg_configinfo,m); - + xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo, cg_configinfo); + // recreate enough of X2 EN-DC Container + AssertFatal(cg_configinfo->criticalExtensions.choice.c1->present == NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo, + "ueCapabilityInformation not present\n"); + parse_CG_ConfigInfo(rrc,cg_configinfo,m); } ///---------------------------------------------------------------------------------------------------------------/// @@ -437,16 +398,15 @@ void *rrc_gnb_task(void *args_p) { openair_rrc_gNB_configuration(GNB_INSTANCE_TO_MODULE_ID(instance), &NRRRC_CONFIGURATION_REQ(msg_p)); break; - /* Messages from X2AP */ + /* Messages from X2AP */ case X2AP_ENDC_SGNB_ADDITION_REQ: - LOG_I(NR_RRC, "Received ENDC sgNB addition request from X2AP \n"); - rrc_gNB_process_AdditionRequestInformation(GNB_INSTANCE_TO_MODULE_ID(instance), &X2AP_ENDC_SGNB_ADDITION_REQ(msg_p)); - break; + LOG_I(NR_RRC, "Received ENDC sgNB addition request from X2AP \n"); + rrc_gNB_process_AdditionRequestInformation(GNB_INSTANCE_TO_MODULE_ID(instance), &X2AP_ENDC_SGNB_ADDITION_REQ(msg_p)); + break; case X2AP_ENDC_SGNB_RECONF_COMPLETE: - LOG_I(NR_RRC, "Handling of reconfiguration complete message at RRC gNB is pending \n"); - break; - + LOG_I(NR_RRC, "Handling of reconfiguration complete message at RRC gNB is pending \n"); + break; default: LOG_E(NR_RRC, "[gNB %d] Received unexpected message %s\n", instance, msg_name_p); diff --git a/openair2/RRC/NR/rrc_gNB_internode.c b/openair2/RRC/NR/rrc_gNB_internode.c index 092c63f96e..cacff5cf5c 100644 --- a/openair2/RRC/NR/rrc_gNB_internode.c +++ b/openair2/RRC/NR/rrc_gNB_internode.c @@ -39,47 +39,48 @@ #include "NR_CG-Config.h" int parse_CG_ConfigInfo(gNB_RRC_INST *rrc, NR_CG_ConfigInfo_t *CG_ConfigInfo, x2ap_ENDC_sgnb_addition_req_t *m) { - if (CG_ConfigInfo->criticalExtensions.present == NR_CG_ConfigInfo__criticalExtensions_PR_c1) { if (CG_ConfigInfo->criticalExtensions.choice.c1) { if (CG_ConfigInfo->criticalExtensions.choice.c1->present == NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo) { - NR_CG_ConfigInfo_IEs_t *cg_ConfigInfo = CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo; - if (cg_ConfigInfo->ue_CapabilityInfo) { - // Decode UE-CapabilityRAT-ContainerList + NR_CG_ConfigInfo_IEs_t *cg_ConfigInfo = CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo; + + if (cg_ConfigInfo->ue_CapabilityInfo) { + // Decode UE-CapabilityRAT-ContainerList LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList=NULL; - asn_dec_rval_t dec_rval = uper_decode(NULL, - &asn_DEF_LTE_UE_CapabilityRAT_ContainerList, - (void**)&UE_CapabilityRAT_ContainerList, - cg_ConfigInfo->ue_CapabilityInfo->buf, - cg_ConfigInfo->ue_CapabilityInfo->size, 0, 0); + UE_CapabilityRAT_ContainerList = calloc(1,sizeof(LTE_UE_CapabilityRAT_ContainerList_t)); + asn_dec_rval_t dec_rval = uper_decode(NULL, + &asn_DEF_LTE_UE_CapabilityRAT_ContainerList, + (void **)&UE_CapabilityRAT_ContainerList, + cg_ConfigInfo->ue_CapabilityInfo->buf, + cg_ConfigInfo->ue_CapabilityInfo->size, 0, 0); + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { - AssertFatal(1==0,"[InterNode] Failed to decode NR_UE_CapabilityRAT_ContainerList (%zu bits), size of OCTET_STRING %lu\n", - dec_rval.consumed, cg_ConfigInfo->ue_CapabilityInfo->size); - } - rrc_parse_ue_capabilities(rrc,UE_CapabilityRAT_ContainerList, m,cg_ConfigInfo); - } - if (cg_ConfigInfo->candidateCellInfoListMN) AssertFatal(1==0,"Can't handle candidateCellInfoListMN yet\n"); - } - else AssertFatal(1==0,"c1 extension is not cg_ConfigInfo, returning\n"); - } - else { + AssertFatal(1==0,"[InterNode] Failed to decode NR_UE_CapabilityRAT_ContainerList (%zu bits), size of OCTET_STRING %lu\n", + dec_rval.consumed, cg_ConfigInfo->ue_CapabilityInfo->size); + } + + rrc_parse_ue_capabilities(rrc,UE_CapabilityRAT_ContainerList, m,cg_ConfigInfo); + } + + if (cg_ConfigInfo->candidateCellInfoListMN) AssertFatal(1==0,"Can't handle candidateCellInfoListMN yet\n"); + } else AssertFatal(1==0,"c1 extension is not cg_ConfigInfo, returning\n"); + } else { LOG_E(RRC,"c1 extension not found, returning\n"); - return(-1); + return(-1); } } else { LOG_E(RRC,"Ignoring unknown CG_ConfigInfo extensions\n"); return(-1); } - return(0); + + return(0); } -int generate_CG_Config(gNB_RRC_INST *rrc, - NR_CG_Config_t *cg_Config, - NR_RRCReconfiguration_t *reconfig, - NR_RadioBearerConfig_t *rbconfig) { - - +int generate_CG_Config(gNB_RRC_INST *rrc, + NR_CG_Config_t *cg_Config, + NR_RRCReconfiguration_t *reconfig, + NR_RadioBearerConfig_t *rbconfig) { cg_Config->criticalExtensions.present = NR_CG_Config__criticalExtensions_PR_c1; cg_Config->criticalExtensions.choice.c1 = calloc(1,sizeof(*cg_Config->criticalExtensions.choice.c1)); cg_Config->criticalExtensions.choice.c1->present = NR_CG_Config__criticalExtensions__c1_PR_cg_Config; @@ -91,36 +92,37 @@ int generate_CG_Config(gNB_RRC_INST *rrc, enc_rval.failed_type->name, enc_rval.encoded); cg_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig = calloc(1,sizeof(OCTET_STRING_t)); OCTET_STRING_fromBuf(cg_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig, - (const char *)buffer, - (enc_rval.encoded+7)>>3); + (const char *)buffer, + (enc_rval.encoded+7)>>3); total_size = (enc_rval.encoded+7)>>3; - LOG_I(RRC,"Dumping NR_RRCReconfiguration message (%jd bytes)\n",(enc_rval.encoded+7)>>3); - for (int i=0;i<(enc_rval.encoded+7)>>3;i++) { + + for (int i=0; i<(enc_rval.encoded+7)>>3; i++) { printf("%02x",((uint8_t *)buffer)[i]); } + printf("\n"); FILE *fd = fopen("reconfig.raw","w"); - fwrite((void*)buffer,1,(size_t)((enc_rval.encoded+7)>>3),fd); + fwrite((void *)buffer,1,(size_t)((enc_rval.encoded+7)>>3),fd); fclose(fd); - enc_rval = uper_encode_to_buffer(&asn_DEF_NR_RadioBearerConfig, NULL, (void *)rbconfig, buffer, 1024); AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", enc_rval.failed_type->name, enc_rval.encoded); cg_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config = calloc(1,sizeof(OCTET_STRING_t)); OCTET_STRING_fromBuf(cg_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config, - (const char *)buffer, - (enc_rval.encoded+7)>>3); + (const char *)buffer, + (enc_rval.encoded+7)>>3); LOG_I(RRC,"Dumping scg_RB_Config message (%jd bytes)\n",(enc_rval.encoded+7)>>3); - for (int i=0;i<(enc_rval.encoded+7)>>3;i++) { - printf("%02x",((uint8_t*)buffer)[i]); + + for (int i=0; i<(enc_rval.encoded+7)>>3; i++) { + printf("%02x",((uint8_t *)buffer)[i]); } + printf("\n"); fd = fopen("rbconfig.raw","w"); - fwrite((void*)buffer,1,(size_t)((enc_rval.encoded+7)>>3),fd); + fwrite((void *)buffer,1,(size_t)((enc_rval.encoded+7)>>3),fd); fclose(fd); total_size = total_size + ((enc_rval.encoded+7)>>3); - return(total_size); } diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c index 7057fcf53a..45d56f24fa 100644 --- a/openair2/RRC/NR/rrc_gNB_nsa.c +++ b/openair2/RRC/NR/rrc_gNB_nsa.c @@ -40,7 +40,6 @@ #include "openair2/RRC/LTE/rrc_eNB_GTPV1U.h" void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList, x2ap_ENDC_sgnb_addition_req_t *m, NR_CG_ConfigInfo_IEs_t *cg_config_info) { - struct rrc_gNB_ue_context_s *ue_context_p = NULL; OCTET_STRING_t *ueCapabilityRAT_Container_nr = NULL; OCTET_STRING_t *ueCapabilityRAT_Container_MRDC = NULL; @@ -48,10 +47,11 @@ void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_Container asn_dec_rval_t dec_rval; AssertFatal(UE_CapabilityRAT_ContainerList!=NULL,"UE_CapabilityRAT_ContainerList is null\n"); AssertFatal((list_size=UE_CapabilityRAT_ContainerList->list.count) >= 2, "UE_CapabilityRAT_ContainerList->list.size %d < 2\n",UE_CapabilityRAT_ContainerList->list.count); - for (int i=0;ilist.array[i]->rat_Type == LTE_RAT_Type_nr) ueCapabilityRAT_Container_nr = &UE_CapabilityRAT_ContainerList->list.array[i]->ueCapabilityRAT_Container; else if (UE_CapabilityRAT_ContainerList->list.array[i]->rat_Type == LTE_RAT_Type_eutra_nr) ueCapabilityRAT_Container_MRDC = &UE_CapabilityRAT_ContainerList->list.array[i]->ueCapabilityRAT_Container; - } + } // decode and store capabilities ue_context_p = rrc_gNB_allocate_new_UE_context(rrc); @@ -65,10 +65,10 @@ void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_Container if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { LOG_E(RRC, "Failed to decode UE NR capabilities (%zu bytes) container size %lu\n", dec_rval.consumed,ueCapabilityRAT_Container_nr->size); - ASN_STRUCT_FREE(asn_DEF_NR_UE_NR_Capability, - ue_context_p->ue_context.UE_Capability_nr); - ue_context_p->ue_context.UE_Capability_nr = 0; - AssertFatal(1==0,"exiting\n"); + ASN_STRUCT_FREE(asn_DEF_NR_UE_NR_Capability, + ue_context_p->ue_context.UE_Capability_nr); + ue_context_p->ue_context.UE_Capability_nr = 0; + AssertFatal(1==0,"exiting\n"); } } @@ -80,173 +80,158 @@ void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_Container ueCapabilityRAT_Container_MRDC->size, 0, 0); if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { - LOG_E(RRC, "Failed to decode UE MRDC capabilities (%zu bytes)\n", dec_rval.consumed); - ASN_STRUCT_FREE(asn_DEF_NR_UE_MRDC_Capability, - ue_context_p->ue_context.UE_Capability_MRDC); - ue_context_p->ue_context.UE_Capability_MRDC = 0; - AssertFatal(1==0,"exiting\n"); + LOG_E(RRC, "Failed to decode UE MRDC capabilities (%zu bytes)\n", dec_rval.consumed); + ASN_STRUCT_FREE(asn_DEF_NR_UE_MRDC_Capability, + ue_context_p->ue_context.UE_Capability_MRDC); + ue_context_p->ue_context.UE_Capability_MRDC = 0; + AssertFatal(1==0,"exiting\n"); } } // dump ue_capabilities if ( LOG_DEBUGFLAG(DEBUG_ASN1 && ueCapabilityRAT_Container_nr != NULL) ) { - xer_fprint(stdout, &asn_DEF_NR_UE_NR_Capability, ue_context_p->ue_context.UE_Capability_nr); - } + xer_fprint(stdout, &asn_DEF_NR_UE_NR_Capability, ue_context_p->ue_context.UE_Capability_nr); + } if ( LOG_DEBUGFLAG(DEBUG_ASN1 && ueCapabilityRAT_Container_MRDC != NULL) ) { - xer_fprint(stdout, &asn_DEF_NR_UE_MRDC_Capability, ue_context_p->ue_context.UE_Capability_MRDC); - } - - if(cg_config_info->mcg_RB_Config) { - asn_dec_rval_t dec_rval = uper_decode(NULL, - &asn_DEF_NR_RadioBearerConfig, - (void**)&ue_context_p->ue_context.rb_config, - cg_config_info->mcg_RB_Config->buf, - cg_config_info->mcg_RB_Config->size, 0, 0); - - if((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { - AssertFatal(1==0,"[InterNode] Failed to decode mcg_rb_config (%zu bits), size of OCTET_STRING %lu\n", - dec_rval.consumed, cg_config_info->mcg_RB_Config->size); + xer_fprint(stdout, &asn_DEF_NR_UE_MRDC_Capability, ue_context_p->ue_context.UE_Capability_MRDC); + } + + if(cg_config_info && cg_config_info->mcg_RB_Config) { + asn_dec_rval_t dec_rval = uper_decode(NULL, + &asn_DEF_NR_RadioBearerConfig, + (void **)&ue_context_p->ue_context.rb_config, + cg_config_info->mcg_RB_Config->buf, + cg_config_info->mcg_RB_Config->size, 0, 0); + + if((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + AssertFatal(1==0,"[InterNode] Failed to decode mcg_rb_config (%zu bits), size of OCTET_STRING %lu\n", + dec_rval.consumed, cg_config_info->mcg_RB_Config->size); } } - xer_fprint(stdout, &asn_DEF_NR_RadioBearerConfig, (const void*)ue_context_p->ue_context.rb_config); + + xer_fprint(stdout, &asn_DEF_NR_RadioBearerConfig, (const void *)ue_context_p->ue_context.rb_config); rrc_add_nsa_user(rrc,ue_context_p, m); } void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p, x2ap_ENDC_sgnb_addition_req_t *m) { - -// generate nr-Config-r15 containers for LTE RRC : inside message for X2 EN-DC (CG-Config Message from 38.331) - + // generate nr-Config-r15 containers for LTE RRC : inside message for X2 EN-DC (CG-Config Message from 38.331) rrc_gNB_carrier_data_t *carrier=&rrc->carrier; - MessageDef *msg; msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ_ACK); gtpv1u_enb_create_tunnel_req_t create_tunnel_req; gtpv1u_enb_create_tunnel_resp_t create_tunnel_resp; protocol_ctxt_t ctxt; - -// NR RRCReconfiguration - + // NR RRCReconfiguration AssertFatal(rrc->Nb_ue < MAX_NR_RRC_UE_CONTEXTS,"cannot add another UE\n"); - ue_context_p->ue_context.reconfig = calloc(1,sizeof(NR_RRCReconfiguration_t)); ue_context_p->ue_context.secondaryCellGroup = calloc(1,sizeof(NR_CellGroupConfig_t)); - memset((void*)ue_context_p->ue_context.reconfig,0,sizeof(NR_RRCReconfiguration_t)); + memset((void *)ue_context_p->ue_context.reconfig,0,sizeof(NR_RRCReconfiguration_t)); ue_context_p->ue_context.reconfig->rrc_TransactionIdentifier=0; ue_context_p->ue_context.reconfig->criticalExtensions.present = NR_RRCReconfiguration__criticalExtensions_PR_rrcReconfiguration; NR_RRCReconfiguration_IEs_t *reconfig_ies=calloc(1,sizeof(NR_RRCReconfiguration_IEs_t)); ue_context_p->ue_context.reconfig->criticalExtensions.choice.rrcReconfiguration = reconfig_ies; carrier->initial_csi_index[rrc->Nb_ue] = 0; fill_default_reconfig(carrier->servingcellconfigcommon, - reconfig_ies, - ue_context_p->ue_context.secondaryCellGroup, - carrier->pdsch_AntennaPorts, - carrier->initial_csi_index[rrc->Nb_ue]); - + reconfig_ies, + ue_context_p->ue_context.secondaryCellGroup, + carrier->pdsch_AntennaPorts, + carrier->initial_csi_index[rrc->Nb_ue]); ue_context_p->ue_context.rb_config = calloc(1,sizeof(NR_RRCReconfiguration_t)); - - //fill_default_rbconfig(ue_context_p->ue_context.rb_config,m, cg_config_info); ue_context_p->ue_id_rnti = ue_context_p->ue_context.secondaryCellGroup->spCellConfig->reconfigurationWithSync->newUE_Identity; NR_CG_Config_t *CG_Config = calloc(1,sizeof(*CG_Config)); - memset((void*)CG_Config,0,sizeof(*CG_Config)); + memset((void *)CG_Config,0,sizeof(*CG_Config)); //int CG_Config_size = generate_CG_Config(rrc,CG_Config,ue_context_p->ue_context.reconfig,ue_context_p->ue_context.rb_config); generate_CG_Config(rrc,CG_Config,ue_context_p->ue_context.reconfig,ue_context_p->ue_context.rb_config); - if(m!=NULL){ - uint8_t inde_list[m->nb_e_rabs_tobeadded]; - memset(inde_list, 0, m->nb_e_rabs_tobeadded*sizeof(uint8_t)); + if(m!=NULL) { + uint8_t inde_list[m->nb_e_rabs_tobeadded]; + memset(inde_list, 0, m->nb_e_rabs_tobeadded*sizeof(uint8_t)); - if (m->nb_e_rabs_tobeadded>0){ - for (int i=0; inb_e_rabs_tobeadded; i++){ - // Add the new E-RABs at the corresponding rrc ue context of the gNB - ue_context_p->ue_context.e_rab[i].param.e_rab_id = m->e_rabs_tobeadded[i].e_rab_id; - ue_context_p->ue_context.e_rab[i].param.gtp_teid = m->e_rabs_tobeadded[i].gtp_teid; - memcpy(&ue_context_p->ue_context.e_rab[i].param.sgw_addr, &m->e_rabs_tobeadded[i].sgw_addr, sizeof(transport_layer_addr_t)); - ue_context_p->ue_context.nb_of_e_rabs++; - //Fill the required E-RAB specific information for the creation of the S1-U tunnel between the gNB and the SGW - create_tunnel_req.eps_bearer_id[i] = ue_context_p->ue_context.e_rab[i].param.e_rab_id; - create_tunnel_req.sgw_S1u_teid[i] = ue_context_p->ue_context.e_rab[i].param.gtp_teid; - memcpy(&create_tunnel_req.sgw_addr[i], &ue_context_p->ue_context.e_rab[i].param.sgw_addr, sizeof(transport_layer_addr_t)); - inde_list[i] = i; - LOG_I(RRC,"S1-U tunnel: index %d target sgw ip %d.%d.%d.%d length %d gtp teid %u\n", - i, - create_tunnel_req.sgw_addr[i].buffer[0], - create_tunnel_req.sgw_addr[i].buffer[1], - create_tunnel_req.sgw_addr[i].buffer[2], - create_tunnel_req.sgw_addr[i].buffer[3], - create_tunnel_req.sgw_addr[i].length, - create_tunnel_req.sgw_S1u_teid[i]); - } - //PM: Is this where we should extract the rnti from? - create_tunnel_req.rnti = ue_context_p->ue_id_rnti; - create_tunnel_req.num_tunnels = m->nb_e_rabs_tobeadded; - RB_INSERT(rrc_nr_ue_tree_s, &RC.nrrrc[rrc->module_id]->rrc_ue_head, ue_context_p); + if (m->nb_e_rabs_tobeadded>0) { + for (int i=0; inb_e_rabs_tobeadded; i++) { + // Add the new E-RABs at the corresponding rrc ue context of the gNB + ue_context_p->ue_context.e_rab[i].param.e_rab_id = m->e_rabs_tobeadded[i].e_rab_id; + ue_context_p->ue_context.e_rab[i].param.gtp_teid = m->e_rabs_tobeadded[i].gtp_teid; + memcpy(&ue_context_p->ue_context.e_rab[i].param.sgw_addr, &m->e_rabs_tobeadded[i].sgw_addr, sizeof(transport_layer_addr_t)); + ue_context_p->ue_context.nb_of_e_rabs++; + //Fill the required E-RAB specific information for the creation of the S1-U tunnel between the gNB and the SGW + create_tunnel_req.eps_bearer_id[i] = ue_context_p->ue_context.e_rab[i].param.e_rab_id; + create_tunnel_req.sgw_S1u_teid[i] = ue_context_p->ue_context.e_rab[i].param.gtp_teid; + memcpy(&create_tunnel_req.sgw_addr[i], &ue_context_p->ue_context.e_rab[i].param.sgw_addr, sizeof(transport_layer_addr_t)); + inde_list[i] = i; + LOG_I(RRC,"S1-U tunnel: index %d target sgw ip %d.%d.%d.%d length %d gtp teid %u\n", + i, + create_tunnel_req.sgw_addr[i].buffer[0], + create_tunnel_req.sgw_addr[i].buffer[1], + create_tunnel_req.sgw_addr[i].buffer[2], + create_tunnel_req.sgw_addr[i].buffer[3], + create_tunnel_req.sgw_addr[i].length, + create_tunnel_req.sgw_S1u_teid[i]); + } - PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, rrc->module_id, GNB_FLAG_YES, ue_context_p->ue_id_rnti, 0, 0,rrc->module_id); - gtpv1u_create_s1u_tunnel( - ctxt.instance, - &create_tunnel_req, - &create_tunnel_resp); - rrc_gNB_process_GTPV1U_CREATE_TUNNEL_RESP( - &ctxt, - &create_tunnel_resp, - &inde_list[0]); - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).nb_e_rabs_admitted_tobeadded = m->nb_e_rabs_tobeadded; - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).target_assoc_id = m->target_assoc_id; + //PM: Is this where we should extract the rnti from? + create_tunnel_req.rnti = ue_context_p->ue_id_rnti; + create_tunnel_req.num_tunnels = m->nb_e_rabs_tobeadded; + RB_INSERT(rrc_nr_ue_tree_s, &RC.nrrrc[rrc->module_id]->rrc_ue_head, ue_context_p); + PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, rrc->module_id, GNB_FLAG_YES, ue_context_p->ue_id_rnti, 0, 0,rrc->module_id); + gtpv1u_create_s1u_tunnel( + ctxt.instance, + &create_tunnel_req, + &create_tunnel_resp); + rrc_gNB_process_GTPV1U_CREATE_TUNNEL_RESP( + &ctxt, + &create_tunnel_resp, + &inde_list[0]); + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).nb_e_rabs_admitted_tobeadded = m->nb_e_rabs_tobeadded; + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).target_assoc_id = m->target_assoc_id; - for(int i=0; iue_context.nb_of_e_rabs; i++){ - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].e_rab_id = ue_context_p->ue_context.e_rab[i].param.e_rab_id; - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gtp_teid = create_tunnel_resp.enb_S1u_teid[i]; - memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr, &create_tunnel_resp.enb_addr, sizeof(transport_layer_addr_t)); - - //The length field in the X2AP targetting structure is expected in bits but the create_tunnel_resp returns the address length in bytes - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.length = create_tunnel_resp.enb_addr.length*8; - - LOG_I(RRC,"S1-U create_tunnel_resp tunnel: index %d target gNB ip %d.%d.%d.%d length %d gtp teid %u\n", - i, - create_tunnel_resp.enb_addr.buffer[0], - create_tunnel_resp.enb_addr.buffer[1], - create_tunnel_resp.enb_addr.buffer[2], - create_tunnel_resp.enb_addr.buffer[3], - create_tunnel_resp.enb_addr.length, - create_tunnel_resp.enb_S1u_teid[i]); - LOG_I(RRC,"X2AP sGNB Addition Request: index %d target gNB ip %d.%d.%d.%d length %d gtp teid %u\n", - i, - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[0], - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[1], - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[2], - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[3], - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.length, - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gtp_teid); - } - } - else - LOG_W(RRC, "No E-RAB to be added received from SgNB Addition Request message \n"); + for(int i=0; iue_context.nb_of_e_rabs; i++) { + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].e_rab_id = ue_context_p->ue_context.e_rab[i].param.e_rab_id; + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gtp_teid = create_tunnel_resp.enb_S1u_teid[i]; + memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr, &create_tunnel_resp.enb_addr, sizeof(transport_layer_addr_t)); + //The length field in the X2AP targetting structure is expected in bits but the create_tunnel_resp returns the address length in bytes + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.length = create_tunnel_resp.enb_addr.length*8; + LOG_I(RRC,"S1-U create_tunnel_resp tunnel: index %d target gNB ip %d.%d.%d.%d length %d gtp teid %u\n", + i, + create_tunnel_resp.enb_addr.buffer[0], + create_tunnel_resp.enb_addr.buffer[1], + create_tunnel_resp.enb_addr.buffer[2], + create_tunnel_resp.enb_addr.buffer[3], + create_tunnel_resp.enb_addr.length, + create_tunnel_resp.enb_S1u_teid[i]); + LOG_I(RRC,"X2AP sGNB Addition Request: index %d target gNB ip %d.%d.%d.%d length %d gtp teid %u\n", + i, + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[0], + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[1], + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[2], + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[3], + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.length, + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gtp_teid); + } + } else + LOG_W(RRC, "No E-RAB to be added received from SgNB Addition Request message \n"); } - //X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).rrc_buffer_size = CG_Config_size; //Need to verify correct value for the buffer_size // Send to X2 entity to transport to MeNB asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CG_Config, - NULL, - (void *)CG_Config, - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).rrc_buffer, - 1024); - + NULL, + (void *)CG_Config, + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).rrc_buffer, + 1024); X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).rrc_buffer_size = (enc_rval.encoded+7)>>3; - itti_send_msg_to_task(TASK_X2AP, ENB_MODULE_ID_TO_INSTANCE(0), msg); //Check right id instead of hardcoding - rrc->Nb_ue++; // configure MAC and RLC rrc_mac_config_req_gNB(rrc->module_id, - rrc->carrier.ssb_SubcarrierOffset, + rrc->carrier.ssb_SubcarrierOffset, rrc->carrier.pdsch_AntennaPorts, - NULL, - 1, // add_ue flag - ue_context_p->ue_id_rnti, - ue_context_p->ue_context.secondaryCellGroup); + NULL, + 1, // add_ue flag + ue_context_p->ue_id_rnti, + ue_context_p->ue_context.secondaryCellGroup); } diff --git a/openair2/RRC/NR/rrc_gNB_reconfig.c b/openair2/RRC/NR/rrc_gNB_reconfig.c index fd8f93462f..8f93b42ef4 100644 --- a/openair2/RRC/NR/rrc_gNB_reconfig.c +++ b/openair2/RRC/NR/rrc_gNB_reconfig.c @@ -49,23 +49,19 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellconfigcommon, - NR_CellGroupConfig_t *secondaryCellGroup, - int scg_id, - int servCellIndex, - int n_physical_antenna_ports, - int initial_csi_index) { + NR_CellGroupConfig_t *secondaryCellGroup, + int scg_id, + int servCellIndex, + int n_physical_antenna_ports, + int initial_csi_index) { AssertFatal(servingcellconfigcommon!=NULL,"servingcellconfigcommon is null\n"); AssertFatal(secondaryCellGroup!=NULL,"secondaryCellGroup is null\n"); - memset(secondaryCellGroup,0,sizeof(NR_CellGroupConfig_t)); secondaryCellGroup->cellGroupId = scg_id; - NR_RLC_BearerConfig_t *RLC_BearerConfig = calloc(1,sizeof(*RLC_BearerConfig)); - RLC_BearerConfig->logicalChannelIdentity = 4; RLC_BearerConfig->servedRadioBearer = calloc(1,sizeof(*RLC_BearerConfig->servedRadioBearer)); - RLC_BearerConfig->servedRadioBearer->present = NR_RLC_BearerConfig__servedRadioBearer_PR_drb_Identity; - + RLC_BearerConfig->servedRadioBearer->present = NR_RLC_BearerConfig__servedRadioBearer_PR_drb_Identity; RLC_BearerConfig->servedRadioBearer->choice.drb_Identity=1; RLC_BearerConfig->reestablishRLC=calloc(1,sizeof(*RLC_BearerConfig->reestablishRLC)); *RLC_BearerConfig->reestablishRLC=NR_RLC_BearerConfig__reestablishRLC_true; @@ -73,17 +69,15 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco RLC_BearerConfig->rlc_Config->present = NR_RLC_Config_PR_am; RLC_BearerConfig->rlc_Config->choice.am = calloc(1,sizeof(*RLC_BearerConfig->rlc_Config->choice.am)); RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.sn_FieldLength = calloc(1,sizeof(*RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.sn_FieldLength)); - *RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.sn_FieldLength = NR_SN_FieldLengthAM_size18; + *RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.sn_FieldLength = NR_SN_FieldLengthAM_size18; RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.t_PollRetransmit = NR_T_PollRetransmit_ms45; RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.pollPDU = NR_PollPDU_p64; RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.pollByte = NR_PollByte_kB500; RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.maxRetxThreshold = NR_UL_AM_RLC__maxRetxThreshold_t32; - RLC_BearerConfig->rlc_Config->choice.am->dl_AM_RLC.sn_FieldLength = calloc(1,sizeof(*RLC_BearerConfig->rlc_Config->choice.am->dl_AM_RLC.sn_FieldLength)); *RLC_BearerConfig->rlc_Config->choice.am->dl_AM_RLC.sn_FieldLength = NR_SN_FieldLengthAM_size18; RLC_BearerConfig->rlc_Config->choice.am->dl_AM_RLC.t_Reassembly = NR_T_Reassembly_ms15; RLC_BearerConfig->rlc_Config->choice.am->dl_AM_RLC.t_StatusProhibit = NR_T_StatusProhibit_ms15; - RLC_BearerConfig->mac_LogicalChannelConfig = calloc(1,sizeof(*RLC_BearerConfig->mac_LogicalChannelConfig)); RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters = calloc(1,sizeof(*RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters)); RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->priority = 1; @@ -99,10 +93,8 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->logicalChannelSR_Mask = false; RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->logicalChannelSR_DelayTimerApplied = false; RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->bitRateQueryProhibitTimer = NULL; - secondaryCellGroup->rlc_BearerToAddModList = calloc(1,sizeof(*secondaryCellGroup->rlc_BearerToAddModList)); ASN_SEQUENCE_ADD(&secondaryCellGroup->rlc_BearerToAddModList->list, RLC_BearerConfig); - secondaryCellGroup->mac_CellGroupConfig=calloc(1,sizeof(*secondaryCellGroup->mac_CellGroupConfig)); secondaryCellGroup->mac_CellGroupConfig->drx_Config = NULL; secondaryCellGroup->mac_CellGroupConfig->schedulingRequestConfig = NULL; @@ -126,25 +118,20 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup->dummy=false; secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup->phr_Type2OtherCell = false; secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup->phr_ModeOtherCG = NR_PHR_Config__phr_ModeOtherCG_real; - secondaryCellGroup->mac_CellGroupConfig->skipUplinkTxDynamic=false; secondaryCellGroup->mac_CellGroupConfig->ext1 = NULL; - - secondaryCellGroup->physicalCellGroupConfig = calloc(1,sizeof(*secondaryCellGroup->physicalCellGroupConfig)); - secondaryCellGroup->physicalCellGroupConfig->harq_ACK_SpatialBundlingPUCCH=NULL; secondaryCellGroup->physicalCellGroupConfig->harq_ACK_SpatialBundlingPUSCH=NULL; secondaryCellGroup->physicalCellGroupConfig->p_NR_FR1=calloc(1,sizeof(*secondaryCellGroup->physicalCellGroupConfig->p_NR_FR1)); *secondaryCellGroup->physicalCellGroupConfig->p_NR_FR1=20; - secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook=NR_PhysicalCellGroupConfig__pdsch_HARQ_ACK_Codebook_dynamic; + secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook=NR_PhysicalCellGroupConfig__pdsch_HARQ_ACK_Codebook_dynamic; secondaryCellGroup->physicalCellGroupConfig->tpc_SRS_RNTI=NULL; secondaryCellGroup->physicalCellGroupConfig->tpc_PUCCH_RNTI=NULL; secondaryCellGroup->physicalCellGroupConfig->tpc_PUSCH_RNTI=NULL; secondaryCellGroup->physicalCellGroupConfig->sp_CSI_RNTI=NULL; secondaryCellGroup->physicalCellGroupConfig->cs_RNTI=NULL; secondaryCellGroup->physicalCellGroupConfig->ext1=NULL; - secondaryCellGroup->spCellConfig = calloc(1,sizeof(*secondaryCellGroup->spCellConfig)); secondaryCellGroup->spCellConfig->servCellIndex = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->servCellIndex)); *secondaryCellGroup->spCellConfig->servCellIndex = servCellIndex; @@ -154,7 +141,6 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->spCellConfig->reconfigurationWithSync->t304=NR_ReconfigurationWithSync__t304_ms2000; secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated = NULL; secondaryCellGroup->spCellConfig->reconfigurationWithSync->ext1 = NULL; - /* contention free ra */ secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated = calloc(1,sizeof(struct NR_ReconfigurationWithSync__rach_ConfigDedicated)); secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->present= NR_ReconfigurationWithSync__rach_ConfigDedicated_PR_uplink; @@ -162,7 +148,8 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra= calloc(1,sizeof(struct NR_CFRA)); secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->ra_Prioritization= NULL; secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions= calloc(1,sizeof(struct NR_CFRA__occasions)); - memcpy(&secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions->rach_ConfigGeneric, &servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric, sizeof(NR_RACH_ConfigGeneric_t)); + memcpy(&secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions->rach_ConfigGeneric, + &servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric, sizeof(NR_RACH_ConfigGeneric_t)); //secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions->ssb_perRACH_Occasion= calloc(1,sizeof(long)); //*secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions->ssb_perRACH_Occasion = NR_CFRA__occasions__ssb_perRACH_Occasion_one; secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions->ssb_perRACH_Occasion= NULL; @@ -174,7 +161,6 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ssbElem->ra_PreambleIndex= 63; ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->resources.choice.ssb->ssb_ResourceList.list,ssbElem); secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->ext1 = NULL; - secondaryCellGroup->spCellConfig->rlf_TimersAndConstants = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->rlf_TimersAndConstants)); secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->present = NR_SetupRelease_RLF_TimersAndConstants_PR_setup; secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup)); @@ -183,1847 +169,1748 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup->n311 = NR_RLF_TimersAndConstants__n311_n1; secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup->ext1 = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup->ext1)); secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup->ext1->t311_v1530 = NR_RLF_TimersAndConstants__ext1__t311_v1530_ms30000; - secondaryCellGroup->spCellConfig->rlmInSyncOutOfSyncThreshold = NULL; - - - secondaryCellGroup->spCellConfig->spCellConfigDedicated = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated)); secondaryCellGroup->spCellConfig->spCellConfigDedicated->tdd_UL_DL_ConfigurationDedicated = NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdcch_Config=NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config)); secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->present = NR_SetupRelease_PDSCH_Config_PR_setup; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup = calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup)); secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dataScramblingIdentityPDSCH = NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA = calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA)); secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->present= NR_SetupRelease_DMRS_DownlinkConfig_PR_setup; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup = calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->maxLength=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->scramblingID0=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->scramblingID1=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->phaseTrackingRS=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition)); + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = + NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList=calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList)); + NR_TCI_State_t *tci0=calloc(1,sizeof(*tci0)); + tci0->tci_StateId=0; + tci0->qcl_Type1.cell=NULL; + tci0->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci0->qcl_Type1.bwp_Id)); + *tci0->qcl_Type1.bwp_Id=1; + tci0->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tci0->qcl_Type1.referenceSignal.choice.csi_rs = 2; + tci0->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci0); + NR_TCI_State_t *tci1=calloc(1,sizeof(*tci1)); + tci1->tci_StateId=1; + tci1->qcl_Type1.cell=NULL; + tci1->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci1->qcl_Type1.bwp_Id)); + *tci1->qcl_Type1.bwp_Id=1; + tci1->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tci1->qcl_Type1.referenceSignal.choice.csi_rs = 6; + tci1->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci1); + NR_TCI_State_t *tci2=calloc(1,sizeof(*tci2)); + tci2->tci_StateId=2; + tci2->qcl_Type1.cell=NULL; + tci2->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci2->qcl_Type1.bwp_Id)); + *tci2->qcl_Type1.bwp_Id=1; + tci2->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tci2->qcl_Type1.referenceSignal.choice.csi_rs = 10; + tci2->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci2); + NR_TCI_State_t *tci3=calloc(1,sizeof(*tci3)); + tci3->tci_StateId=3; + tci3->qcl_Type1.cell=NULL; + tci3->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci3->qcl_Type1.bwp_Id)); + *tci3->qcl_Type1.bwp_Id=1; + tci3->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tci3->qcl_Type1.referenceSignal.choice.csi_rs = 14; + tci3->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci3); + NR_TCI_State_t *tci4=calloc(1,sizeof(*tci4)); + tci4->tci_StateId=4; + tci4->qcl_Type1.cell=NULL; + tci4->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci4->qcl_Type1.bwp_Id)); + *tci4->qcl_Type1.bwp_Id=1; + tci4->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tci4->qcl_Type1.referenceSignal.choice.csi_rs = 18; + tci4->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci4); + NR_TCI_State_t *tci5=calloc(1,sizeof(*tci5)); + tci5->tci_StateId=5; + tci5->qcl_Type1.cell=NULL; + tci5->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci5->qcl_Type1.bwp_Id)); + *tci5->qcl_Type1.bwp_Id=1; + tci5->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tci5->qcl_Type1.referenceSignal.choice.csi_rs = 22; + tci5->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci5); + NR_TCI_State_t *tci6=calloc(1,sizeof(*tci6)); + tci6->tci_StateId=6; + tci6->qcl_Type1.cell=NULL; + tci6->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci6->qcl_Type1.bwp_Id)); + *tci6->qcl_Type1.bwp_Id=1; + tci6->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tci6->qcl_Type1.referenceSignal.choice.csi_rs = 26; + tci6->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci6); + NR_TCI_State_t *tci7=calloc(1,sizeof(*tci7)); + tci7->tci_StateId=7; + tci7->qcl_Type1.cell=NULL; + tci7->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci7->qcl_Type1.bwp_Id)); + *tci7->qcl_Type1.bwp_Id=1; + tci7->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tci7->qcl_Type1.referenceSignal.choice.csi_rs = 30; + tci7->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci7); + NR_TCI_State_t *tci8=calloc(1,sizeof(*tci8)); + tci8->tci_StateId=8; + tci8->qcl_Type1.cell=NULL; + tci8->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci8->qcl_Type1.bwp_Id)); + *tci8->qcl_Type1.bwp_Id=1; + tci8->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tci8->qcl_Type1.referenceSignal.choice.ssb = 0; + tci8->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci8); + NR_TCI_State_t *tci9=calloc(1,sizeof(*tci9)); + tci9->tci_StateId=9; + tci9->qcl_Type1.cell=NULL; + tci9->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci9->qcl_Type1.bwp_Id)); + *tci9->qcl_Type1.bwp_Id=1; + tci9->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tci9->qcl_Type1.referenceSignal.choice.ssb = 1; + tci9->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci9); + NR_TCI_State_t *tci10=calloc(1,sizeof(*tci10)); + tci10->tci_StateId=10; + tci10->qcl_Type1.cell=NULL; + tci10->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci10->qcl_Type1.bwp_Id)); + *tci10->qcl_Type1.bwp_Id=1; + tci10->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tci10->qcl_Type1.referenceSignal.choice.ssb = 2; + tci10->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci10); + NR_TCI_State_t *tci11=calloc(1,sizeof(*tci11)); + tci11->tci_StateId=11; + tci11->qcl_Type1.cell=NULL; + tci11->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci11->qcl_Type1.bwp_Id)); + *tci11->qcl_Type1.bwp_Id=1; + tci11->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tci11->qcl_Type1.referenceSignal.choice.ssb = 3; + tci11->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci11); + NR_TCI_State_t *tci12=calloc(1,sizeof(*tci12)); + tci12->tci_StateId=12; + tci12->qcl_Type1.cell=NULL; + tci12->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci12->qcl_Type1.bwp_Id)); + *tci12->qcl_Type1.bwp_Id=1; + tci12->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tci12->qcl_Type1.referenceSignal.choice.ssb = 4; + tci12->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci12); + NR_TCI_State_t *tci13=calloc(1,sizeof(*tci13)); + tci13->tci_StateId=13; + tci13->qcl_Type1.cell=NULL; + tci13->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci13->qcl_Type1.bwp_Id)); + *tci13->qcl_Type1.bwp_Id=1; + tci13->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tci13->qcl_Type1.referenceSignal.choice.ssb = 5; + tci13->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci13); + NR_TCI_State_t *tci14=calloc(1,sizeof(*tci14)); + tci14->tci_StateId=14; + tci14->qcl_Type1.cell=NULL; + tci14->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci14->qcl_Type1.bwp_Id)); + *tci14->qcl_Type1.bwp_Id=1; + tci14->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tci14->qcl_Type1.referenceSignal.choice.ssb = 6; + tci14->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci14); + NR_TCI_State_t *tci15=calloc(1,sizeof(*tci15)); + tci15->tci_StateId=15; + tci15->qcl_Type1.cell=NULL; + tci15->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci15->qcl_Type1.bwp_Id)); + *tci15->qcl_Type1.bwp_Id=1; + tci15->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tci15->qcl_Type1.referenceSignal.choice.ssb = 7; + tci15->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci15); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternToReleaseList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup1=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup2=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rbg_Size=NR_PDSCH_Config__rbg_Size_config1; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->mcs_Table=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI)); + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = NR_PDSCH_Config__maxNrofCodeWordsScheduledByDCI_n1; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.present = NR_PDSCH_Config__prb_BundlingType_PR_staticBundling; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling = calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = + calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize)); + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = + NR_PDSCH_Config__prb_BundlingType__staticBundling__bundleSize_wideband; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToAddModList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToReleaseList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToAddModList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->sps_Config = NULL; //calloc(1,sizeof(struct NR_SetupRelease_SPS_Config)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig = calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->present = NR_SetupRelease_RadioLinkMonitoringConfig_PR_setup; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup = calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->failureDetectionResourcesToAddModList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->failureDetectionResourcesToReleaseList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount)); + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = + NR_RadioLinkMonitoringConfig__beamFailureInstanceMaxCount_n3; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer)); + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = + NR_RadioLinkMonitoringConfig__beamFailureDetectionTimer_pbfd2; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToReleaseList= NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList)); + NR_BWP_Downlink_t *bwp=calloc(1,sizeof(*bwp)); + bwp->bwp_Id=1; + bwp->bwp_Common=calloc(1,sizeof(*bwp->bwp_Common)); + // copy common BWP size from initial BWP except for bandwdith + memcpy((void *)&bwp->bwp_Common->genericParameters, + &servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->genericParameters, + sizeof(bwp->bwp_Common->genericParameters)); + bwp->bwp_Common->genericParameters.locationAndBandwidth=PRBalloc_to_locationandbandwidth( + servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth,0); + bwp->bwp_Common->pdcch_ConfigCommon=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon)); + bwp->bwp_Common->pdcch_ConfigCommon->present = NR_SetupRelease_PDCCH_ConfigCommon_PR_setup; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup = calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup)); + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->controlResourceSetZero=NULL; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet)); + NR_ControlResourceSet_t *coreset = calloc(1,sizeof(*coreset)); + coreset->controlResourceSetId=1; + // frequencyDomainResources '11111111 11111111 00000000 00000000 00000000 00000'B, + coreset->frequencyDomainResources.buf = calloc(1,6); + coreset->frequencyDomainResources.buf[0] = 0xff; + coreset->frequencyDomainResources.buf[1] = 0xff; + coreset->frequencyDomainResources.buf[2] = 0; + coreset->frequencyDomainResources.buf[3] = 0; + coreset->frequencyDomainResources.buf[4] = 0; + coreset->frequencyDomainResources.buf[5] = 0; + coreset->frequencyDomainResources.size = 6; + coreset->frequencyDomainResources.bits_unused = 3; + coreset->duration=1; + coreset->cce_REG_MappingType.present = NR_ControlResourceSet__cce_REG_MappingType_PR_nonInterleaved; + coreset->precoderGranularity = NR_ControlResourceSet__precoderGranularity_sameAsREG_bundle; + coreset->tci_StatesPDCCH_ToAddList=calloc(1,sizeof(*coreset->tci_StatesPDCCH_ToAddList)); + NR_TCI_StateId_t *tci[8]; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->maxLength=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->scramblingID0=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->scramblingID1=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->phaseTrackingRS=NULL; + for (int i=0; i<8; i++) { + tci[i]=calloc(1,sizeof(*tci[i])); + *tci[i] = i; + ASN_SEQUENCE_ADD(&coreset->tci_StatesPDCCH_ToAddList->list,tci[i]); + } - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition)); - *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0; + coreset->tci_StatesPDCCH_ToReleaseList = NULL; + coreset->tci_PresentInDCI = NULL; + coreset->pdcch_DMRS_ScramblingID = NULL; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet = coreset; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->searchSpaceZero=NULL; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList=NULL; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList)); + NR_SearchSpace_t *ss=calloc(1,sizeof(*ss)); + ss->searchSpaceId = 1; + ss->controlResourceSetId=calloc(1,sizeof(*ss->controlResourceSetId)); + *ss->controlResourceSetId=1; + ss->monitoringSlotPeriodicityAndOffset = calloc(1,sizeof(*ss->monitoringSlotPeriodicityAndOffset)); + ss->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1; + ss->duration=NULL; + ss->monitoringSymbolsWithinSlot = calloc(1,sizeof(*ss->monitoringSymbolsWithinSlot)); + ss->monitoringSymbolsWithinSlot->buf = calloc(1,2); + // should be '1100 0000 0000 00'B (LSB first!), first two symols in slot, adjust if needed + ss->monitoringSymbolsWithinSlot->buf[1] = 0; + ss->monitoringSymbolsWithinSlot->buf[0] = (1<<7) | (1<<6); + ss->monitoringSymbolsWithinSlot->size = 2; + ss->monitoringSymbolsWithinSlot->bits_unused = 2; + ss->nrofCandidates = calloc(1,sizeof(*ss->nrofCandidates)); + ss->nrofCandidates->aggregationLevel1 = NR_SearchSpace__nrofCandidates__aggregationLevel1_n0; + ss->nrofCandidates->aggregationLevel2 = NR_SearchSpace__nrofCandidates__aggregationLevel2_n0; + ss->nrofCandidates->aggregationLevel4 = NR_SearchSpace__nrofCandidates__aggregationLevel4_n1; + ss->nrofCandidates->aggregationLevel8 = NR_SearchSpace__nrofCandidates__aggregationLevel8_n0; + ss->nrofCandidates->aggregationLevel16 = NR_SearchSpace__nrofCandidates__aggregationLevel16_n0; + ss->searchSpaceType = calloc(1,sizeof(*ss->searchSpaceType)); + ss->searchSpaceType->present = NR_SearchSpace__searchSpaceType_PR_common; + ss->searchSpaceType->choice.common=calloc(1,sizeof(*ss->searchSpaceType->choice.common)); + ss->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0 = calloc(1,sizeof(*ss->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0)); + ASN_SEQUENCE_ADD(&bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList->list,ss); + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->searchSpaceSIB1=NULL; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->searchSpaceOtherSystemInformation=NULL; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->pagingSearchSpace=NULL; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace)); + *bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace=1; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ext1=NULL; + bwp->bwp_Common->pdsch_ConfigCommon=calloc(1,sizeof(*bwp->bwp_Common->pdsch_ConfigCommon)); + bwp->bwp_Common->pdsch_ConfigCommon->present = NR_SetupRelease_PDSCH_ConfigCommon_PR_setup; + bwp->bwp_Common->pdsch_ConfigCommon->choice.setup = calloc(1,sizeof(*bwp->bwp_Common->pdsch_ConfigCommon->choice.setup)); + bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList = calloc(1,sizeof(*bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList)); + // copy PDSCH TimeDomainResourceAllocation from InitialBWP + NR_PDSCH_TimeDomainResourceAllocation_t *pdschi; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList)); - - NR_TCI_State_t*tci0=calloc(1,sizeof(*tci0)); - tci0->tci_StateId=0; - tci0->qcl_Type1.cell=NULL; - tci0->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci0->qcl_Type1.bwp_Id)); - *tci0->qcl_Type1.bwp_Id=1; - tci0->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tci0->qcl_Type1.referenceSignal.choice.csi_rs = 2; - tci0->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci0); - - NR_TCI_State_t*tci1=calloc(1,sizeof(*tci1)); - tci1->tci_StateId=1; - tci1->qcl_Type1.cell=NULL; - tci1->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci1->qcl_Type1.bwp_Id)); - *tci1->qcl_Type1.bwp_Id=1; - tci1->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tci1->qcl_Type1.referenceSignal.choice.csi_rs = 6; - tci1->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci1); - - NR_TCI_State_t*tci2=calloc(1,sizeof(*tci2)); - tci2->tci_StateId=2; - tci2->qcl_Type1.cell=NULL; - tci2->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci2->qcl_Type1.bwp_Id)); - *tci2->qcl_Type1.bwp_Id=1; - tci2->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tci2->qcl_Type1.referenceSignal.choice.csi_rs = 10; - tci2->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci2); - - NR_TCI_State_t *tci3=calloc(1,sizeof(*tci3)); - tci3->tci_StateId=3; - tci3->qcl_Type1.cell=NULL; - tci3->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci3->qcl_Type1.bwp_Id)); - *tci3->qcl_Type1.bwp_Id=1; - tci3->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tci3->qcl_Type1.referenceSignal.choice.csi_rs = 14; - tci3->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci3); - - NR_TCI_State_t*tci4=calloc(1,sizeof(*tci4)); - tci4->tci_StateId=4; - tci4->qcl_Type1.cell=NULL; - tci4->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci4->qcl_Type1.bwp_Id)); - *tci4->qcl_Type1.bwp_Id=1; - tci4->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tci4->qcl_Type1.referenceSignal.choice.csi_rs = 18; - tci4->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci4); - - NR_TCI_State_t*tci5=calloc(1,sizeof(*tci5)); - tci5->tci_StateId=5; - tci5->qcl_Type1.cell=NULL; - tci5->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci5->qcl_Type1.bwp_Id)); - *tci5->qcl_Type1.bwp_Id=1; - tci5->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tci5->qcl_Type1.referenceSignal.choice.csi_rs = 22; - tci5->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci5); - - NR_TCI_State_t*tci6=calloc(1,sizeof(*tci6)); - tci6->tci_StateId=6; - tci6->qcl_Type1.cell=NULL; - tci6->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci6->qcl_Type1.bwp_Id)); - *tci6->qcl_Type1.bwp_Id=1; - tci6->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tci6->qcl_Type1.referenceSignal.choice.csi_rs = 26; - tci6->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci6); - - NR_TCI_State_t*tci7=calloc(1,sizeof(*tci7)); - tci7->tci_StateId=7; - tci7->qcl_Type1.cell=NULL; - tci7->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci7->qcl_Type1.bwp_Id)); - *tci7->qcl_Type1.bwp_Id=1; - tci7->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tci7->qcl_Type1.referenceSignal.choice.csi_rs = 30; - tci7->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci7); - - NR_TCI_State_t*tci8=calloc(1,sizeof(*tci8)); - tci8->tci_StateId=8; - tci8->qcl_Type1.cell=NULL; - tci8->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci8->qcl_Type1.bwp_Id)); - *tci8->qcl_Type1.bwp_Id=1; - tci8->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tci8->qcl_Type1.referenceSignal.choice.ssb = 0; - tci8->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci8); - - NR_TCI_State_t*tci9=calloc(1,sizeof(*tci9)); - tci9->tci_StateId=9; - tci9->qcl_Type1.cell=NULL; - tci9->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci9->qcl_Type1.bwp_Id)); - *tci9->qcl_Type1.bwp_Id=1; - tci9->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tci9->qcl_Type1.referenceSignal.choice.ssb = 1; - tci9->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci9); - - NR_TCI_State_t*tci10=calloc(1,sizeof(*tci10)); - tci10->tci_StateId=10; - tci10->qcl_Type1.cell=NULL; - tci10->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci10->qcl_Type1.bwp_Id)); - *tci10->qcl_Type1.bwp_Id=1; - tci10->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tci10->qcl_Type1.referenceSignal.choice.ssb = 2; - tci10->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci10); - - NR_TCI_State_t*tci11=calloc(1,sizeof(*tci11)); - tci11->tci_StateId=11; - tci11->qcl_Type1.cell=NULL; - tci11->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci11->qcl_Type1.bwp_Id)); - *tci11->qcl_Type1.bwp_Id=1; - tci11->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tci11->qcl_Type1.referenceSignal.choice.ssb = 3; - tci11->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci11); - - NR_TCI_State_t*tci12=calloc(1,sizeof(*tci12)); - tci12->tci_StateId=12; - tci12->qcl_Type1.cell=NULL; - tci12->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci12->qcl_Type1.bwp_Id)); - *tci12->qcl_Type1.bwp_Id=1; - tci12->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tci12->qcl_Type1.referenceSignal.choice.ssb = 4; - tci12->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci12); - - NR_TCI_State_t*tci13=calloc(1,sizeof(*tci13)); - tci13->tci_StateId=13; - tci13->qcl_Type1.cell=NULL; - tci13->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci13->qcl_Type1.bwp_Id)); - *tci13->qcl_Type1.bwp_Id=1; - tci13->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tci13->qcl_Type1.referenceSignal.choice.ssb = 5; - tci13->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci13); - - NR_TCI_State_t*tci14=calloc(1,sizeof(*tci14)); - tci14->tci_StateId=14; - tci14->qcl_Type1.cell=NULL; - tci14->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci14->qcl_Type1.bwp_Id)); - *tci14->qcl_Type1.bwp_Id=1; - tci14->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tci14->qcl_Type1.referenceSignal.choice.ssb = 6; - tci14->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci14); - - NR_TCI_State_t*tci15=calloc(1,sizeof(*tci15)); - tci15->tci_StateId=15; - tci15->qcl_Type1.cell=NULL; - tci15->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci15->qcl_Type1.bwp_Id)); - *tci15->qcl_Type1.bwp_Id=1; - tci15->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tci15->qcl_Type1.referenceSignal.choice.ssb = 7; - tci15->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci15); - - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternToReleaseList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup1=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup2=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rbg_Size=NR_PDSCH_Config__rbg_Size_config1; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->mcs_Table=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI)); - *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = NR_PDSCH_Config__maxNrofCodeWordsScheduledByDCI_n1; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.present = NR_PDSCH_Config__prb_BundlingType_PR_staticBundling; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = - calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize)); - *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = NR_PDSCH_Config__prb_BundlingType__staticBundling__bundleSize_wideband; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToAddModList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToReleaseList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToAddModList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->sps_Config = NULL; //calloc(1,sizeof(struct NR_SetupRelease_SPS_Config)); - - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->present = NR_SetupRelease_RadioLinkMonitoringConfig_PR_setup; - - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->failureDetectionResourcesToAddModList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->failureDetectionResourcesToReleaseList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount)); - *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = NR_RadioLinkMonitoringConfig__beamFailureInstanceMaxCount_n3; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer)); - *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = NR_RadioLinkMonitoringConfig__beamFailureDetectionTimer_pbfd2; - - secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToReleaseList= NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList)); - - NR_BWP_Downlink_t *bwp=calloc(1,sizeof(*bwp)); - bwp->bwp_Id=1; - bwp->bwp_Common=calloc(1,sizeof(*bwp->bwp_Common)); - // copy common BWP size from initial BWP except for bandwdith - memcpy((void*)&bwp->bwp_Common->genericParameters, - &servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->genericParameters, - sizeof(bwp->bwp_Common->genericParameters)); - bwp->bwp_Common->genericParameters.locationAndBandwidth=PRBalloc_to_locationandbandwidth(servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth,0); - - - bwp->bwp_Common->pdcch_ConfigCommon=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon)); - bwp->bwp_Common->pdcch_ConfigCommon->present = NR_SetupRelease_PDCCH_ConfigCommon_PR_setup; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup = calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup)); - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->controlResourceSetZero=NULL; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet)); - - NR_ControlResourceSet_t *coreset = calloc(1,sizeof(*coreset)); - coreset->controlResourceSetId=1; - // frequencyDomainResources '11111111 11111111 00000000 00000000 00000000 00000'B, - coreset->frequencyDomainResources.buf = calloc(1,6); - coreset->frequencyDomainResources.buf[0] = 0xff; - coreset->frequencyDomainResources.buf[1] = 0xff; - coreset->frequencyDomainResources.buf[2] = 0; - coreset->frequencyDomainResources.buf[3] = 0; - coreset->frequencyDomainResources.buf[4] = 0; - coreset->frequencyDomainResources.buf[5] = 0; - coreset->frequencyDomainResources.size = 6; - coreset->frequencyDomainResources.bits_unused = 3; - coreset->duration=1; - coreset->cce_REG_MappingType.present = NR_ControlResourceSet__cce_REG_MappingType_PR_nonInterleaved; - coreset->precoderGranularity = NR_ControlResourceSet__precoderGranularity_sameAsREG_bundle; - - coreset->tci_StatesPDCCH_ToAddList=calloc(1,sizeof(*coreset->tci_StatesPDCCH_ToAddList)); - NR_TCI_StateId_t *tci[8]; - for (int i=0;i<8;i++) { - tci[i]=calloc(1,sizeof(*tci[i])); - *tci[i] = i; - ASN_SEQUENCE_ADD(&coreset->tci_StatesPDCCH_ToAddList->list,tci[i]); - } - coreset->tci_StatesPDCCH_ToReleaseList = NULL; - coreset->tci_PresentInDCI = NULL; - coreset->pdcch_DMRS_ScramblingID = NULL; - - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet = coreset; - - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->searchSpaceZero=NULL; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList=NULL; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList)); - - NR_SearchSpace_t *ss=calloc(1,sizeof(*ss)); - ss->searchSpaceId = 1; - ss->controlResourceSetId=calloc(1,sizeof(*ss->controlResourceSetId)); - *ss->controlResourceSetId=1; - ss->monitoringSlotPeriodicityAndOffset = calloc(1,sizeof(*ss->monitoringSlotPeriodicityAndOffset)); - ss->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1; - ss->duration=NULL; - ss->monitoringSymbolsWithinSlot = calloc(1,sizeof(*ss->monitoringSymbolsWithinSlot)); - ss->monitoringSymbolsWithinSlot->buf = calloc(1,2); - // should be '1100 0000 0000 00'B (LSB first!), first two symols in slot, adjust if needed - ss->monitoringSymbolsWithinSlot->buf[1] = 0; - ss->monitoringSymbolsWithinSlot->buf[0] = (1<<7) | (1<<6); - ss->monitoringSymbolsWithinSlot->size = 2; - ss->monitoringSymbolsWithinSlot->bits_unused = 2; - ss->nrofCandidates = calloc(1,sizeof(*ss->nrofCandidates)); - ss->nrofCandidates->aggregationLevel1 = NR_SearchSpace__nrofCandidates__aggregationLevel1_n0; - ss->nrofCandidates->aggregationLevel2 = NR_SearchSpace__nrofCandidates__aggregationLevel2_n0; - ss->nrofCandidates->aggregationLevel4 = NR_SearchSpace__nrofCandidates__aggregationLevel4_n1; - ss->nrofCandidates->aggregationLevel8 = NR_SearchSpace__nrofCandidates__aggregationLevel8_n0; - ss->nrofCandidates->aggregationLevel16 = NR_SearchSpace__nrofCandidates__aggregationLevel16_n0; - ss->searchSpaceType = calloc(1,sizeof(*ss->searchSpaceType)); - ss->searchSpaceType->present = NR_SearchSpace__searchSpaceType_PR_common; - ss->searchSpaceType->choice.common=calloc(1,sizeof(*ss->searchSpaceType->choice.common)); - ss->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0 = calloc(1,sizeof(*ss->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0)); - - ASN_SEQUENCE_ADD(&bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList->list,ss); - - - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->searchSpaceSIB1=NULL; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->searchSpaceOtherSystemInformation=NULL; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->pagingSearchSpace=NULL; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace)); - *bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace=1; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ext1=NULL; - - bwp->bwp_Common->pdsch_ConfigCommon=calloc(1,sizeof(*bwp->bwp_Common->pdsch_ConfigCommon)); - bwp->bwp_Common->pdsch_ConfigCommon->present = NR_SetupRelease_PDSCH_ConfigCommon_PR_setup; - bwp->bwp_Common->pdsch_ConfigCommon->choice.setup = calloc(1,sizeof(*bwp->bwp_Common->pdsch_ConfigCommon->choice.setup)); - bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList = calloc(1,sizeof(*bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList)); - - // copy PDSCH TimeDomainResourceAllocation from InitialBWP - - NR_PDSCH_TimeDomainResourceAllocation_t *pdschi; - for (int i=0;idownlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count;i++) { - pdschi= calloc(1,sizeof(*pdschi)); - AssertFatal(servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->k0!=NULL,"element %d is null\n",i); - - pdschi->k0 = calloc(1,sizeof(*pdschi->k0)); - *pdschi->k0 = *servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->k0; - pdschi->mappingType = servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->mappingType; - pdschi->startSymbolAndLength = servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->startSymbolAndLength; - ASN_SEQUENCE_ADD(&bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list,pdschi); - } - - bwp->bwp_Dedicated=calloc(1,sizeof(*bwp->bwp_Dedicated)); - - bwp->bwp_Dedicated->pdcch_Config=calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config)); - bwp->bwp_Dedicated->pdcch_Config->present = NR_SetupRelease_PDCCH_Config_PR_setup; - bwp->bwp_Dedicated->pdcch_Config->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup)); - bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList)); - - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list, - coreset); - - bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList)); - - NR_SearchSpace_t *ss2 = calloc(1,sizeof(*ss2)); - - ss2->searchSpaceId=2; - ss2->controlResourceSetId=calloc(1,sizeof(*ss2->controlResourceSetId)); - *ss2->controlResourceSetId=1; - ss2->monitoringSlotPeriodicityAndOffset=calloc(1,sizeof(*ss2->monitoringSlotPeriodicityAndOffset)); - ss2->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1; - ss2->monitoringSlotPeriodicityAndOffset->choice.sl1=(NULL_t)0; - ss2->duration=NULL; - ss2->monitoringSymbolsWithinSlot = calloc(1,sizeof(*ss2->monitoringSymbolsWithinSlot)); - ss2->monitoringSymbolsWithinSlot->buf = calloc(1,2); - ss2->monitoringSymbolsWithinSlot->size = 2; - ss2->monitoringSymbolsWithinSlot->bits_unused = 2; - ss2->monitoringSymbolsWithinSlot->buf[0]=0xc0; - ss2->monitoringSymbolsWithinSlot->buf[1]=0x0; - ss2->nrofCandidates=calloc(1,sizeof(*ss2->nrofCandidates)); - ss2->nrofCandidates->aggregationLevel1 = NR_SearchSpace__nrofCandidates__aggregationLevel1_n0; - ss2->nrofCandidates->aggregationLevel2 = NR_SearchSpace__nrofCandidates__aggregationLevel2_n0; - ss2->nrofCandidates->aggregationLevel4 = NR_SearchSpace__nrofCandidates__aggregationLevel4_n4; - ss2->nrofCandidates->aggregationLevel8 = NR_SearchSpace__nrofCandidates__aggregationLevel8_n0; - ss2->nrofCandidates->aggregationLevel16 = NR_SearchSpace__nrofCandidates__aggregationLevel16_n0; - ss2->searchSpaceType=calloc(1,sizeof(*ss2->searchSpaceType)); - ss2->searchSpaceType->present = NR_SearchSpace__searchSpaceType_PR_ue_Specific; - ss2->searchSpaceType->choice.ue_Specific = calloc(1,sizeof(*ss2->searchSpaceType->choice.ue_Specific)); - ss2->searchSpaceType->choice.ue_Specific->dci_Formats=NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_0_And_1_0; - - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list, - ss2); - - - bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToReleaseList = NULL; - - bwp->bwp_Dedicated->pdsch_Config = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config)); + for (int i=0; idownlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count; i++) { + pdschi= calloc(1,sizeof(*pdschi)); + AssertFatal(servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->k0!=NULL,"element %d is null\n",i); + pdschi->k0 = calloc(1,sizeof(*pdschi->k0)); + *pdschi->k0 = *servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->k0; + pdschi->mappingType = servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->mappingType; + pdschi->startSymbolAndLength = servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->startSymbolAndLength; + ASN_SEQUENCE_ADD(&bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list,pdschi); + } + bwp->bwp_Dedicated=calloc(1,sizeof(*bwp->bwp_Dedicated)); + bwp->bwp_Dedicated->pdcch_Config=calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config)); + bwp->bwp_Dedicated->pdcch_Config->present = NR_SetupRelease_PDCCH_Config_PR_setup; + bwp->bwp_Dedicated->pdcch_Config->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup)); + bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList)); + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list, + coreset); + bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList)); + NR_SearchSpace_t *ss2 = calloc(1,sizeof(*ss2)); + ss2->searchSpaceId=2; + ss2->controlResourceSetId=calloc(1,sizeof(*ss2->controlResourceSetId)); + *ss2->controlResourceSetId=1; + ss2->monitoringSlotPeriodicityAndOffset=calloc(1,sizeof(*ss2->monitoringSlotPeriodicityAndOffset)); + ss2->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1; + ss2->monitoringSlotPeriodicityAndOffset->choice.sl1=(NULL_t)0; + ss2->duration=NULL; + ss2->monitoringSymbolsWithinSlot = calloc(1,sizeof(*ss2->monitoringSymbolsWithinSlot)); + ss2->monitoringSymbolsWithinSlot->buf = calloc(1,2); + ss2->monitoringSymbolsWithinSlot->size = 2; + ss2->monitoringSymbolsWithinSlot->bits_unused = 2; + ss2->monitoringSymbolsWithinSlot->buf[0]=0xc0; + ss2->monitoringSymbolsWithinSlot->buf[1]=0x0; + ss2->nrofCandidates=calloc(1,sizeof(*ss2->nrofCandidates)); + ss2->nrofCandidates->aggregationLevel1 = NR_SearchSpace__nrofCandidates__aggregationLevel1_n0; + ss2->nrofCandidates->aggregationLevel2 = NR_SearchSpace__nrofCandidates__aggregationLevel2_n0; + ss2->nrofCandidates->aggregationLevel4 = NR_SearchSpace__nrofCandidates__aggregationLevel4_n4; + ss2->nrofCandidates->aggregationLevel8 = NR_SearchSpace__nrofCandidates__aggregationLevel8_n0; + ss2->nrofCandidates->aggregationLevel16 = NR_SearchSpace__nrofCandidates__aggregationLevel16_n0; + ss2->searchSpaceType=calloc(1,sizeof(*ss2->searchSpaceType)); + ss2->searchSpaceType->present = NR_SearchSpace__searchSpaceType_PR_ue_Specific; + ss2->searchSpaceType->choice.ue_Specific = calloc(1,sizeof(*ss2->searchSpaceType->choice.ue_Specific)); + ss2->searchSpaceType->choice.ue_Specific->dci_Formats=NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_0_And_1_0; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list, + ss2); + bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToReleaseList = NULL; + bwp->bwp_Dedicated->pdsch_Config = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config)); bwp->bwp_Dedicated->pdsch_Config->present = NR_SetupRelease_PDSCH_Config_PR_setup; bwp->bwp_Dedicated->pdsch_Config->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup)); bwp->bwp_Dedicated->pdsch_Config->choice.setup->dataScramblingIdentityPDSCH = NULL; bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA)); bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->present= NR_SetupRelease_DMRS_DownlinkConfig_PR_setup; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup)); - - bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->maxLength=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->scramblingID0=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->scramblingID1=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->phaseTrackingRS=NULL; - - bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition)); - *bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0; - - bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList=calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList)); - - NR_TCI_State_t*tcid0=calloc(1,sizeof(*tcid0)); - tcid0->tci_StateId=0; - tcid0->qcl_Type1.cell=NULL; - tcid0->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid0->qcl_Type1.bwp_Id)); - *tcid0->qcl_Type1.bwp_Id=1; - tcid0->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tcid0->qcl_Type1.referenceSignal.choice.csi_rs = 2; - tcid0->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid0); - - NR_TCI_State_t*tcid1=calloc(1,sizeof(*tcid1)); - tcid1->tci_StateId=0; - tcid1->qcl_Type1.cell=NULL; - tcid1->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid1->qcl_Type1.bwp_Id)); - *tcid1->qcl_Type1.bwp_Id=1; - tcid1->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tcid1->qcl_Type1.referenceSignal.choice.csi_rs = 6; - tcid1->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid1); - - NR_TCI_State_t*tcid2=calloc(1,sizeof(*tcid2)); - tcid2->tci_StateId=2; - tcid2->qcl_Type1.cell=NULL; - tcid2->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid2->qcl_Type1.bwp_Id)); - *tcid2->qcl_Type1.bwp_Id=1; - tcid2->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tcid2->qcl_Type1.referenceSignal.choice.csi_rs = 10; - tcid2->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid2); - - NR_TCI_State_t*tcid3=calloc(1,sizeof(*tcid3)); - tcid3->tci_StateId=3; - tcid3->qcl_Type1.cell=NULL; - tcid3->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid3->qcl_Type1.bwp_Id)); - *tcid3->qcl_Type1.bwp_Id=1; - tcid3->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tcid3->qcl_Type1.referenceSignal.choice.csi_rs = 14; - tcid3->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid3); - - NR_TCI_State_t*tcid4=calloc(1,sizeof(*tcid4)); - tcid4->tci_StateId=4; - tcid4->qcl_Type1.cell=NULL; - tcid4->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid4->qcl_Type1.bwp_Id)); - *tcid4->qcl_Type1.bwp_Id=1; - tcid4->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tcid4->qcl_Type1.referenceSignal.choice.csi_rs = 18; - tcid4->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid4); - - NR_TCI_State_t*tcid5=calloc(1,sizeof(*tcid5)); - tcid5->tci_StateId=5; - tcid5->qcl_Type1.cell=NULL; - tcid5->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid5->qcl_Type1.bwp_Id)); - *tcid5->qcl_Type1.bwp_Id=1; - tcid5->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tcid5->qcl_Type1.referenceSignal.choice.csi_rs = 22; - tcid5->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid5); - - NR_TCI_State_t*tcid6=calloc(1,sizeof(*tcid6)); - tcid6->tci_StateId=6; - tcid6->qcl_Type1.cell=NULL; - tcid6->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid6->qcl_Type1.bwp_Id)); - *tcid6->qcl_Type1.bwp_Id=1; - tcid6->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tcid6->qcl_Type1.referenceSignal.choice.csi_rs = 26; - tcid6->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid6); - - NR_TCI_State_t*tcid7=calloc(1,sizeof(*tcid7)); - tcid7->tci_StateId=7; - tcid7->qcl_Type1.cell=NULL; - tcid7->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid7->qcl_Type1.bwp_Id)); - *tcid7->qcl_Type1.bwp_Id=1; - tcid7->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tcid7->qcl_Type1.referenceSignal.choice.csi_rs = 30; - tcid7->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid7); - - NR_TCI_State_t*tcid8=calloc(1,sizeof(*tcid8)); - tcid8->tci_StateId=8; - tcid8->qcl_Type1.cell=NULL; - tcid8->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid8->qcl_Type1.bwp_Id)); - *tcid8->qcl_Type1.bwp_Id=1; - tcid8->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tcid8->qcl_Type1.referenceSignal.choice.ssb = 0; - tcid8->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid8); - - NR_TCI_State_t*tcid9=calloc(1,sizeof(*tcid9)); - tcid9->tci_StateId=9; - tcid9->qcl_Type1.cell=NULL; - tcid9->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid9->qcl_Type1.bwp_Id)); - *tcid9->qcl_Type1.bwp_Id=1; - tcid9->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tcid9->qcl_Type1.referenceSignal.choice.ssb = 1; - tcid9->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid9); - - NR_TCI_State_t*tcid10=calloc(1,sizeof(*tcid10)); - tcid10->tci_StateId=10; - tcid10->qcl_Type1.cell=NULL; - tcid10->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid10->qcl_Type1.bwp_Id)); - *tcid10->qcl_Type1.bwp_Id=1; - tcid10->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tcid10->qcl_Type1.referenceSignal.choice.ssb = 2; - tcid10->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid10); - - NR_TCI_State_t*tcid11=calloc(1,sizeof(*tcid11)); - tcid11->tci_StateId=11; - tcid11->qcl_Type1.cell=NULL; - tcid11->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid11->qcl_Type1.bwp_Id)); - *tcid11->qcl_Type1.bwp_Id=1; - tcid11->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tcid11->qcl_Type1.referenceSignal.choice.ssb = 3; - tcid11->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid11); - - NR_TCI_State_t*tcid12=calloc(1,sizeof(*tcid12)); - tcid12->tci_StateId=12; - tcid12->qcl_Type1.cell=NULL; - tcid12->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid12->qcl_Type1.bwp_Id)); - *tcid12->qcl_Type1.bwp_Id=1; - tcid12->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tcid12->qcl_Type1.referenceSignal.choice.ssb = 4; - tcid12->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid12); - - NR_TCI_State_t*tcid13=calloc(1,sizeof(*tcid13)); - tcid13->tci_StateId=13; - tcid13->qcl_Type1.cell=NULL; - tcid13->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid13->qcl_Type1.bwp_Id)); - *tcid13->qcl_Type1.bwp_Id=1; - tcid13->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tcid13->qcl_Type1.referenceSignal.choice.ssb = 5; - tcid13->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid13); - - NR_TCI_State_t*tcid14=calloc(1,sizeof(*tcid14)); - tcid14->tci_StateId=14; - tcid14->qcl_Type1.cell=NULL; - tcid14->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid14->qcl_Type1.bwp_Id)); - *tcid14->qcl_Type1.bwp_Id=1; - tcid14->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tcid14->qcl_Type1.referenceSignal.choice.ssb = 6; - tcid14->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid14); - - NR_TCI_State_t*tcid15=calloc(1,sizeof(*tcid15)); - tcid15->tci_StateId=15; - tcid15->qcl_Type1.cell=NULL; - tcid15->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid15->qcl_Type1.bwp_Id)); - *tcid15->qcl_Type1.bwp_Id=1; - tcid15->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tcid15->qcl_Type1.referenceSignal.choice.ssb = 7; - tcid15->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid15); - - bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup1=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup2=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rbg_Size=NR_PDSCH_Config__rbg_Size_config1; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->mcs_Table=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI)); - *bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = NR_PDSCH_Config__maxNrofCodeWordsScheduledByDCI_n1; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.present = NR_PDSCH_Config__prb_BundlingType_PR_staticBundling; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling)); - bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = - calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize)); - *bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = NR_PDSCH_Config__prb_BundlingType__staticBundling__bundleSize_wideband; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToAddModList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToAddModList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL; - - bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup1=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup2=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rbg_Size=NR_PDSCH_Config__rbg_Size_config1; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->mcs_Table=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI)); - *bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = NR_PDSCH_Config__maxNrofCodeWordsScheduledByDCI_n1; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.present = NR_PDSCH_Config__prb_BundlingType_PR_staticBundling; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling)); - bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = - calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize)); - *bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = NR_PDSCH_Config__prb_BundlingType__staticBundling__bundleSize_wideband; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToAddModList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToAddModList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL; - bwp->bwp_Dedicated->sps_Config = NULL; //calloc(1,sizeof(struct NR_SetupRelease_SPS_Config)); - - bwp->bwp_Dedicated->radioLinkMonitoringConfig = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig)); - bwp->bwp_Dedicated->radioLinkMonitoringConfig->present = NR_SetupRelease_RadioLinkMonitoringConfig_PR_setup; - - bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup)); - bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->failureDetectionResourcesToAddModList=NULL; - bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->failureDetectionResourcesToReleaseList=NULL; - bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount)); - *bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = NR_RadioLinkMonitoringConfig__beamFailureInstanceMaxCount_n3; - bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer)); - *bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = NR_RadioLinkMonitoringConfig__beamFailureDetectionTimer_pbfd2; - - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list,bwp); - - secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id)); - - *secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id=1; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->bwp_InactivityTimer = NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->defaultDownlinkBWP_Id = NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig)); - - NR_BWP_UplinkDedicated_t *initialUplinkBWP = calloc(1,sizeof(*initialUplinkBWP)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->initialUplinkBWP = initialUplinkBWP; - initialUplinkBWP->pucch_Config = NULL; - initialUplinkBWP->pusch_Config = calloc(1,sizeof(*initialUplinkBWP->pusch_Config)); - initialUplinkBWP->pusch_Config->present = NR_SetupRelease_PUSCH_Config_PR_setup; - NR_PUSCH_Config_t *pusch_Config = calloc(1,sizeof(*pusch_Config)); - initialUplinkBWP->pusch_Config->choice.setup = pusch_Config; - pusch_Config->txConfig=calloc(1,sizeof(*pusch_Config->txConfig)); - *pusch_Config->txConfig= NR_PUSCH_Config__txConfig_codebook; - pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA = NULL; - pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB = calloc(1,sizeof(*pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB)); - pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->present = NR_SetupRelease_DMRS_UplinkConfig_PR_setup; - pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup = calloc(1,sizeof(*pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup)); - NR_DMRS_UplinkConfig_t *NR_DMRS_UplinkConfig = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup; - NR_DMRS_UplinkConfig->dmrs_Type = NULL; - NR_DMRS_UplinkConfig->dmrs_AdditionalPosition =NR_DMRS_UplinkConfig__dmrs_AdditionalPosition_pos0; - NR_DMRS_UplinkConfig->phaseTrackingRS=NULL; - NR_DMRS_UplinkConfig->maxLength=NULL; - NR_DMRS_UplinkConfig->transformPrecodingDisabled = calloc(1,sizeof(*NR_DMRS_UplinkConfig->transformPrecodingDisabled)); - NR_DMRS_UplinkConfig->transformPrecodingDisabled->scramblingID0 = NULL; - NR_DMRS_UplinkConfig->transformPrecodingDisabled->scramblingID1 = NULL; - NR_DMRS_UplinkConfig->transformPrecodingEnabled = NULL; - pusch_Config->pusch_PowerControl = calloc(1,sizeof(*pusch_Config->pusch_PowerControl)); - pusch_Config->pusch_PowerControl->tpc_Accumulation = NULL; - pusch_Config->pusch_PowerControl->msg3_Alpha = calloc(1,sizeof(*pusch_Config->pusch_PowerControl->msg3_Alpha)); - *pusch_Config->pusch_PowerControl->msg3_Alpha = NR_Alpha_alpha1; - pusch_Config->pusch_PowerControl->p0_NominalWithoutGrant = NULL; - pusch_Config->pusch_PowerControl->p0_AlphaSets = calloc(1,sizeof(*pusch_Config->pusch_PowerControl->p0_AlphaSets)); - NR_P0_PUSCH_AlphaSet_t *aset = calloc(1,sizeof(*aset)); - aset->p0_PUSCH_AlphaSetId=0; - aset->p0=calloc(1,sizeof(*aset->p0)); - *aset->p0 = 0; - aset->alpha=calloc(1,sizeof(*aset->alpha)); - *aset->alpha=NR_Alpha_alpha1; - ASN_SEQUENCE_ADD(&pusch_Config->pusch_PowerControl->p0_AlphaSets->list,aset); - pusch_Config->pusch_PowerControl->pathlossReferenceRSToAddModList = calloc(1,sizeof(*pusch_Config->pusch_PowerControl->pathlossReferenceRSToAddModList)); - NR_PUSCH_PathlossReferenceRS_t *pl = calloc(1,sizeof(*pl)); - pl->pusch_PathlossReferenceRS_Id=0; - pl->referenceSignal.present = NR_PUSCH_PathlossReferenceRS__referenceSignal_PR_csi_RS_Index; - pl->referenceSignal.choice.csi_RS_Index=0; - ASN_SEQUENCE_ADD(&pusch_Config->pusch_PowerControl->pathlossReferenceRSToAddModList->list,pl); - pusch_Config->pusch_PowerControl->pathlossReferenceRSToReleaseList = NULL; - pusch_Config->pusch_PowerControl->twoPUSCH_PC_AdjustmentStates = NULL; - pusch_Config->pusch_PowerControl->deltaMCS = NULL; - pusch_Config->pusch_PowerControl->sri_PUSCH_MappingToAddModList = NULL; - pusch_Config->pusch_PowerControl->sri_PUSCH_MappingToReleaseList = NULL; - pusch_Config->frequencyHopping=NULL; - pusch_Config->frequencyHoppingOffsetLists=NULL; - pusch_Config->resourceAllocation = NR_PUSCH_Config__resourceAllocation_resourceAllocationType1; - pusch_Config->pusch_TimeDomainAllocationList = NULL; - pusch_Config->pusch_AggregationFactor=NULL; - pusch_Config->mcs_Table=NULL; - pusch_Config->mcs_TableTransformPrecoder=NULL; - pusch_Config->transformPrecoder=calloc(1,sizeof(*pusch_Config->transformPrecoder)); - *pusch_Config->transformPrecoder = NR_PUSCH_Config__transformPrecoder_disabled; - pusch_Config->codebookSubset=calloc(1,sizeof(*pusch_Config->codebookSubset)); - *pusch_Config->codebookSubset = NR_PUSCH_Config__codebookSubset_nonCoherent; - pusch_Config->maxRank=calloc(1,sizeof(*pusch_Config->maxRank)); - *pusch_Config->maxRank= 1; - pusch_Config->rbg_Size=NULL; - pusch_Config->uci_OnPUSCH=NULL; - pusch_Config->tp_pi2BPSK=NULL; - - initialUplinkBWP->srs_Config = calloc(1,sizeof(*initialUplinkBWP->srs_Config)); - initialUplinkBWP->srs_Config->present = NR_SetupRelease_SRS_Config_PR_setup; - NR_SRS_Config_t *srs_Config = calloc(1,sizeof(*srs_Config)); - initialUplinkBWP->srs_Config->choice.setup=srs_Config; - srs_Config->srs_ResourceSetToReleaseList=NULL; - srs_Config->srs_ResourceSetToAddModList=calloc(1,sizeof(*srs_Config->srs_ResourceSetToAddModList)); - NR_SRS_ResourceSet_t *srs_resset0=calloc(1,sizeof(*srs_resset0)); - srs_resset0->srs_ResourceSetId = 0; - srs_resset0->srs_ResourceIdList=calloc(1,sizeof(*srs_resset0->srs_ResourceIdList)); - NR_SRS_ResourceId_t *srs_resset0_id=calloc(1,sizeof(*srs_resset0_id)); - *srs_resset0_id=0; - ASN_SEQUENCE_ADD(&srs_resset0->srs_ResourceIdList->list,srs_resset0_id); - srs_Config->srs_ResourceToReleaseList=NULL; - srs_resset0->resourceType.present = NR_SRS_ResourceSet__resourceType_PR_aperiodic; - srs_resset0->resourceType.choice.aperiodic = calloc(1,sizeof(*srs_resset0->resourceType.choice.aperiodic)); - srs_resset0->resourceType.choice.aperiodic->aperiodicSRS_ResourceTrigger=1; - srs_resset0->resourceType.choice.aperiodic->csi_RS=NULL; - srs_resset0->resourceType.choice.aperiodic->slotOffset= calloc(1,sizeof(*srs_resset0->resourceType.choice.aperiodic->slotOffset)); - *srs_resset0->resourceType.choice.aperiodic->slotOffset=2; - srs_resset0->resourceType.choice.aperiodic->ext1=NULL; - srs_resset0->usage=NR_SRS_ResourceSet__usage_codebook; - srs_resset0->alpha = calloc(1,sizeof(*srs_resset0->alpha)); - *srs_resset0->alpha = NR_Alpha_alpha1; - srs_resset0->p0=calloc(1,sizeof(*srs_resset0->p0)); - *srs_resset0->p0=-80; - srs_resset0->pathlossReferenceRS=NULL; - srs_resset0->srs_PowerControlAdjustmentStates=NULL; - ASN_SEQUENCE_ADD(&srs_Config->srs_ResourceSetToAddModList->list,srs_resset0); - srs_Config->srs_ResourceToReleaseList=NULL; - srs_Config->srs_ResourceToAddModList=calloc(1,sizeof(*srs_Config->srs_ResourceToAddModList)); - NR_SRS_Resource_t *srs_res0=calloc(1,sizeof(*srs_res0)); - srs_res0->srs_ResourceId=0; - srs_res0->nrofSRS_Ports=NR_SRS_Resource__nrofSRS_Ports_port1; - srs_res0->ptrs_PortIndex=NULL; - srs_res0->transmissionComb.present=NR_SRS_Resource__transmissionComb_PR_n2; - srs_res0->transmissionComb.choice.n2=calloc(1,sizeof(*srs_res0->transmissionComb.choice.n2)); - srs_res0->transmissionComb.choice.n2->combOffset_n2=0; - srs_res0->transmissionComb.choice.n2->cyclicShift_n2=0; - srs_res0->resourceMapping.startPosition=2; - srs_res0->resourceMapping.nrofSymbols=NR_SRS_Resource__resourceMapping__nrofSymbols_n1; - srs_res0->resourceMapping.repetitionFactor=NR_SRS_Resource__resourceMapping__repetitionFactor_n1; - srs_res0->freqDomainPosition=0; - srs_res0->freqDomainShift=0; - srs_res0->freqHopping.c_SRS = 61; - srs_res0->freqHopping.b_SRS=0; - srs_res0->freqHopping.b_hop=0; - srs_res0->groupOrSequenceHopping=NR_SRS_Resource__groupOrSequenceHopping_neither; - srs_res0->resourceType.present= NR_SRS_Resource__resourceType_PR_aperiodic; - srs_res0->resourceType.choice.aperiodic=calloc(1,sizeof(*srs_res0->resourceType.choice.aperiodic)); - srs_res0->sequenceId=40; - srs_res0->spatialRelationInfo=calloc(1,sizeof(*srs_res0->spatialRelationInfo)); - srs_res0->spatialRelationInfo->servingCellId=NULL; - srs_res0->spatialRelationInfo->referenceSignal.present=NR_SRS_SpatialRelationInfo__referenceSignal_PR_csi_RS_Index; - srs_res0->spatialRelationInfo->referenceSignal.choice.csi_RS_Index=0; - ASN_SEQUENCE_ADD(&srs_Config->srs_ResourceToAddModList->list,srs_res0); - - secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToReleaseList = NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList)); - NR_BWP_Uplink_t *ubwp = calloc(1,sizeof(*ubwp)); - ubwp->bwp_Id=1; - ubwp->bwp_Common = calloc(1,sizeof(*ubwp->bwp_Common)); - // copy bwp_Common from Initial UL BWP except for bandwidth - memcpy((void*)&ubwp->bwp_Common->genericParameters, - (void*)&servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->genericParameters, - sizeof(servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->genericParameters)); - ubwp->bwp_Common->genericParameters.locationAndBandwidth=PRBalloc_to_locationandbandwidth(servingcellconfigcommon->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth,0); - - ubwp->bwp_Common->rach_ConfigCommon = servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon; - ubwp->bwp_Common->pusch_ConfigCommon = servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon; - ubwp->bwp_Common->pucch_ConfigCommon = servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon; - - ubwp->bwp_Dedicated = calloc(1,sizeof(*ubwp->bwp_Dedicated)); - ubwp->bwp_Dedicated->pucch_Config = calloc(1,sizeof(*ubwp->bwp_Dedicated->pucch_Config)); - ubwp->bwp_Dedicated->pucch_Config->present = NR_SetupRelease_PUCCH_Config_PR_setup; - NR_PUCCH_Config_t *pucch_Config = calloc(1,sizeof(*pucch_Config)); - ubwp->bwp_Dedicated->pucch_Config->choice.setup=pucch_Config; - pucch_Config->resourceSetToAddModList = calloc(1,sizeof(*pucch_Config->resourceSetToAddModList)); - pucch_Config->resourceSetToReleaseList = NULL; - NR_PUCCH_ResourceSet_t *pucchresset0=calloc(1,sizeof(*pucchresset0)); - NR_PUCCH_ResourceSet_t *pucchresset1=calloc(1,sizeof(*pucchresset1)); - pucchresset0->pucch_ResourceSetId = 0; - NR_PUCCH_ResourceId_t *pucchresset0id0=calloc(1,sizeof(*pucchresset0id0)); - NR_PUCCH_ResourceId_t *pucchresset0id1=calloc(1,sizeof(*pucchresset0id1)); - *pucchresset0id0=1; - ASN_SEQUENCE_ADD(&pucchresset0->resourceList.list,pucchresset0id0); - *pucchresset0id1=2; - ASN_SEQUENCE_ADD(&pucchresset0->resourceList.list,pucchresset0id1); - pucchresset0->maxPayloadMinus1=NULL; - - ASN_SEQUENCE_ADD(&pucch_Config->resourceSetToAddModList->list,pucchresset0); - - pucchresset1->pucch_ResourceSetId = 1; - NR_PUCCH_ResourceId_t *pucchresset1id0=calloc(1,sizeof(*pucchresset1id0)); - NR_PUCCH_ResourceId_t *pucchresset1id1=calloc(1,sizeof(*pucchresset1id1)); - *pucchresset1id0=3; - ASN_SEQUENCE_ADD(&pucchresset1->resourceList.list,pucchresset1id0); - *pucchresset1id1=4; - ASN_SEQUENCE_ADD(&pucchresset1->resourceList.list,pucchresset1id1); - pucchresset1->maxPayloadMinus1=NULL; - ASN_SEQUENCE_ADD(&pucch_Config->resourceSetToAddModList->list,pucchresset1); - - pucch_Config->resourceToAddModList = calloc(1,sizeof(*pucch_Config->resourceToAddModList)); - pucch_Config->resourceToReleaseList = NULL; - NR_PUCCH_Resource_t *pucchres0=calloc(1,sizeof(*pucchres0)); - NR_PUCCH_Resource_t *pucchres1=calloc(1,sizeof(*pucchres1)); - NR_PUCCH_Resource_t *pucchres2=calloc(1,sizeof(*pucchres2)); - NR_PUCCH_Resource_t *pucchres3=calloc(1,sizeof(*pucchres3)); - pucchres0->pucch_ResourceId=1; - pucchres0->startingPRB=48; - pucchres0->intraSlotFrequencyHopping=NULL; - pucchres0->secondHopPRB=NULL; - pucchres0->format.present= NR_PUCCH_Resource__format_PR_format0; - pucchres0->format.choice.format0=calloc(1,sizeof(*pucchres0->format.choice.format0)); - pucchres0->format.choice.format0->initialCyclicShift=0; - pucchres0->format.choice.format0->nrofSymbols=1; - pucchres0->format.choice.format0->startingSymbolIndex=13; - ASN_SEQUENCE_ADD(&pucch_Config->resourceToAddModList->list,pucchres0); - - pucchres1->pucch_ResourceId=2; - pucchres1->startingPRB=48; - pucchres1->intraSlotFrequencyHopping=NULL; - pucchres1->secondHopPRB=NULL; - pucchres1->format.present= NR_PUCCH_Resource__format_PR_format0; - pucchres1->format.choice.format0=calloc(1,sizeof(*pucchres1->format.choice.format0)); - pucchres1->format.choice.format0->initialCyclicShift=0; - pucchres1->format.choice.format0->nrofSymbols=1; - pucchres1->format.choice.format0->startingSymbolIndex=12; - ASN_SEQUENCE_ADD(&pucch_Config->resourceToAddModList->list,pucchres1); - - pucchres2->pucch_ResourceId=3; - pucchres2->startingPRB=40; - pucchres2->intraSlotFrequencyHopping=NULL; - pucchres2->secondHopPRB=NULL; - pucchres2->format.present= NR_PUCCH_Resource__format_PR_format2; - pucchres2->format.choice.format2=calloc(1,sizeof(*pucchres2->format.choice.format2)); - pucchres2->format.choice.format2->nrofPRBs=16; - pucchres2->format.choice.format2->nrofSymbols=1; - pucchres2->format.choice.format2->startingSymbolIndex=13; - ASN_SEQUENCE_ADD(&pucch_Config->resourceToAddModList->list,pucchres2); - - pucchres3->pucch_ResourceId=4; - pucchres3->startingPRB=40; - pucchres3->intraSlotFrequencyHopping=NULL; - pucchres3->secondHopPRB=NULL; - pucchres3->format.present= NR_PUCCH_Resource__format_PR_format2; - pucchres3->format.choice.format2=calloc(1,sizeof(*pucchres3->format.choice.format2)); - pucchres3->format.choice.format2->nrofPRBs=16; - pucchres3->format.choice.format2->nrofSymbols=1; - pucchres3->format.choice.format2->startingSymbolIndex=12; - ASN_SEQUENCE_ADD(&pucch_Config->resourceToAddModList->list,pucchres3); - - pucch_Config->format2=calloc(1,sizeof(*pucch_Config->format2)); - pucch_Config->format2->present=NR_SetupRelease_PUCCH_FormatConfig_PR_setup; - NR_PUCCH_FormatConfig_t *pucchfmt2 = calloc(1,sizeof(*pucchfmt2)); - pucch_Config->format2->choice.setup = pucchfmt2; - pucchfmt2->interslotFrequencyHopping=NULL; - pucchfmt2->additionalDMRS=NULL; - pucchfmt2->maxCodeRate=calloc(1,sizeof(*pucchfmt2->maxCodeRate)); - *pucchfmt2->maxCodeRate=NR_PUCCH_MaxCodeRate_zeroDot15; - pucchfmt2->nrofSlots=NULL; - pucchfmt2->pi2BPSK=NULL; - pucchfmt2->simultaneousHARQ_ACK_CSI=NULL; - pucch_Config->schedulingRequestResourceToAddModList=NULL; - pucch_Config->schedulingRequestResourceToReleaseList=NULL; - pucch_Config->multi_CSI_PUCCH_ResourceList=NULL; - pucch_Config->dl_DataToUL_ACK = calloc(1,sizeof(*pucch_Config->dl_DataToUL_ACK)); - long *delay[8]; - for (int i=0;i<8;i++) { - delay[i] = calloc(1,sizeof(*delay[i])); - *delay[i] = (i<6) ? (i+2) : 0; - ASN_SEQUENCE_ADD(&pucch_Config->dl_DataToUL_ACK->list,delay[i]); - } - pucch_Config->spatialRelationInfoToAddModList = calloc(1,sizeof(*pucch_Config->spatialRelationInfoToAddModList)); - NR_PUCCH_SpatialRelationInfo_t *pucchspatial = calloc(1,sizeof(*pucchspatial)); - pucchspatial->pucch_SpatialRelationInfoId = 1; - pucchspatial->servingCellId = NULL; - pucchspatial->referenceSignal.present = NR_PUCCH_SpatialRelationInfo__referenceSignal_PR_csi_RS_Index; - pucchspatial->referenceSignal.choice.csi_RS_Index = 0; - pucchspatial->pucch_PathlossReferenceRS_Id = 0; - pucchspatial->p0_PUCCH_Id = 1; - pucchspatial->closedLoopIndex = NR_PUCCH_SpatialRelationInfo__closedLoopIndex_i0; - ASN_SEQUENCE_ADD(&pucch_Config->spatialRelationInfoToAddModList->list,pucchspatial); - pucch_Config->spatialRelationInfoToReleaseList=NULL; - pucch_Config->pucch_PowerControl=calloc(1,sizeof(*pucch_Config->pucch_PowerControl)); - pucch_Config->pucch_PowerControl->deltaF_PUCCH_f0 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f0)); - *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f0 = 0; - pucch_Config->pucch_PowerControl->deltaF_PUCCH_f1 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f1)); - *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f1 = 0; - pucch_Config->pucch_PowerControl->deltaF_PUCCH_f2 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f2)); - *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f2 = 0; - pucch_Config->pucch_PowerControl->deltaF_PUCCH_f3 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f3)); - *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f3 = 0; - pucch_Config->pucch_PowerControl->deltaF_PUCCH_f4 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f4)); - *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f4 = 0; - pucch_Config->pucch_PowerControl->p0_Set = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->p0_Set)); - NR_P0_PUCCH_t *p00 = calloc(1,sizeof(*p00)); - p00->p0_PUCCH_Id=1; - p00->p0_PUCCH_Value = 0; - ASN_SEQUENCE_ADD(&pucch_Config->pucch_PowerControl->p0_Set->list,p00); - pucch_Config->pucch_PowerControl->pathlossReferenceRSs = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->pathlossReferenceRSs)); - NR_PUCCH_PathlossReferenceRS_t *pucchPLRef=calloc(1,sizeof(*pucchPLRef)); - pucchPLRef->pucch_PathlossReferenceRS_Id=0; - pucchPLRef->referenceSignal.present = NR_PUCCH_PathlossReferenceRS__referenceSignal_PR_csi_RS_Index; - pucchPLRef->referenceSignal.choice.csi_RS_Index=0; - ASN_SEQUENCE_ADD(&pucch_Config->pucch_PowerControl->pathlossReferenceRSs->list,pucchPLRef); - - // copy pusch_Config from dedicated initialBWP - ubwp->bwp_Dedicated->pusch_Config = calloc(1,sizeof(*ubwp->bwp_Dedicated->pusch_Config)); - ubwp->bwp_Dedicated->pusch_Config->present = NR_SetupRelease_PUSCH_Config_PR_setup; - ubwp->bwp_Dedicated->pusch_Config->choice.setup = pusch_Config; - - ubwp->bwp_Dedicated->configuredGrantConfig = NULL; - ubwp->bwp_Dedicated->srs_Config = calloc(1,sizeof(*ubwp->bwp_Dedicated->srs_Config)); - ubwp->bwp_Dedicated->srs_Config->present = NR_SetupRelease_SRS_Config_PR_setup; - ubwp->bwp_Dedicated->srs_Config->choice.setup = srs_Config; - - ubwp->bwp_Dedicated->beamFailureRecoveryConfig = NULL; - - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list,ubwp); - - secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id)); - *secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id = 1; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig = NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->carrierSwitching = NULL; - - secondaryCellGroup->spCellConfig->spCellConfigDedicated->supplementaryUplink=NULL; - - secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdcch_ServingCellConfig=NULL; - - secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig)); - NR_PDSCH_ServingCellConfig_t *pdsch_servingcellconfig = calloc(1,sizeof(*pdsch_servingcellconfig)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->present = NR_SetupRelease_PDSCH_ServingCellConfig_PR_setup; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup = pdsch_servingcellconfig; - pdsch_servingcellconfig->codeBlockGroupTransmission = NULL; - pdsch_servingcellconfig->xOverhead = NULL; - pdsch_servingcellconfig->nrofHARQ_ProcessesForPDSCH = NULL; - pdsch_servingcellconfig->pucch_Cell= NULL; - pdsch_servingcellconfig->ext1=calloc(1,sizeof(*pdsch_servingcellconfig->ext1)); - pdsch_servingcellconfig->ext1->maxMIMO_Layers = calloc(1,sizeof(*pdsch_servingcellconfig->ext1->maxMIMO_Layers)); - *pdsch_servingcellconfig->ext1->maxMIMO_Layers = 2; - pdsch_servingcellconfig->ext1->processingType2Enabled = NULL; - - secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->present = NR_SetupRelease_CSI_MeasConfig_PR_setup; - - - NR_CSI_MeasConfig_t *csi_MeasConfig = calloc(1,sizeof(*csi_MeasConfig)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup = csi_MeasConfig; - csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList = calloc(1,sizeof(*csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList)); - - NR_NZP_CSI_RS_Resource_t *nzpres0 = calloc(1,sizeof(*nzpres0)); - nzpres0->nzp_CSI_RS_ResourceId=0; - nzpres0->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_other; - nzpres0->resourceMapping.frequencyDomainAllocation.choice.other.buf = calloc(1,1); - nzpres0->resourceMapping.frequencyDomainAllocation.choice.other.size = 1; - nzpres0->resourceMapping.frequencyDomainAllocation.choice.other.bits_unused = 2; - nzpres0->resourceMapping.frequencyDomainAllocation.choice.other.buf[0]=1<<2; - nzpres0->resourceMapping.nrofPorts = (n_physical_antenna_ports==1)? NR_CSI_RS_ResourceMapping__nrofPorts_p1 : NR_CSI_RS_ResourceMapping__nrofPorts_p2; - nzpres0->resourceMapping.firstOFDMSymbolInTimeDomain=7; - nzpres0->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres0->resourceMapping.cdm_Type = (n_physical_antenna_ports==1)? NR_CSI_RS_ResourceMapping__cdm_Type_noCDM : NR_CSI_RS_ResourceMapping__cdm_Type_fd_CDM2; - nzpres0->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_one; - nzpres0->resourceMapping.density.choice.one=(NULL_t)0; - nzpres0->resourceMapping.freqBand.startingRB=0; - nzpres0->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres0->powerControlOffset=13; - nzpres0->powerControlOffsetSS=NULL; - nzpres0->scramblingID=40; - nzpres0->periodicityAndOffset = calloc(1,sizeof(*nzpres0->periodicityAndOffset)); - nzpres0->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots320; - nzpres0->periodicityAndOffset->choice.slots320 = 2; - nzpres0->qcl_InfoPeriodicCSI_RS=NULL; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres0); - - if (n_physical_antenna_ports > 1) { - NR_NZP_CSI_RS_Resource_t *nzpres2 = calloc(1,sizeof(*nzpres2)); - nzpres2->nzp_CSI_RS_ResourceId=2; - nzpres2->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres2->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres2->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres2->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres2->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=1; - nzpres2->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres2->resourceMapping.firstOFDMSymbolInTimeDomain=4; - nzpres2->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres2->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres2->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres2->resourceMapping.density.choice.three=(NULL_t)0; - nzpres2->resourceMapping.freqBand.startingRB=0; - nzpres2->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres2->powerControlOffset=0; - nzpres2->powerControlOffsetSS=calloc(1,sizeof(*nzpres2->powerControlOffsetSS)); - *nzpres2->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres2->scramblingID=40; - nzpres2->periodicityAndOffset = calloc(1,sizeof(*nzpres2->periodicityAndOffset)); - nzpres2->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres2->periodicityAndOffset->choice.slots160 = 25; - nzpres2->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres2->qcl_InfoPeriodicCSI_RS)); - *nzpres2->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres2); - - - NR_NZP_CSI_RS_Resource_t *nzpres3 = calloc(1,sizeof(*nzpres3)); - nzpres3->nzp_CSI_RS_ResourceId=3; - nzpres3->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres3->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres3->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres3->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres3->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=1; - nzpres3->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres3->resourceMapping.firstOFDMSymbolInTimeDomain=8; - nzpres3->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres3->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres3->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres3->resourceMapping.density.choice.three=(NULL_t)0; - nzpres3->resourceMapping.freqBand.startingRB=0; - nzpres3->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres3->powerControlOffset=0; - nzpres3->powerControlOffsetSS=calloc(1,sizeof(*nzpres3->powerControlOffsetSS)); - *nzpres3->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres3->scramblingID=40; - nzpres3->periodicityAndOffset = calloc(1,sizeof(*nzpres3->periodicityAndOffset)); - nzpres3->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres3->periodicityAndOffset->choice.slots160 = 25; - nzpres3->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres3->qcl_InfoPeriodicCSI_RS)); - *nzpres3->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres3); - } - if (n_physical_antenna_ports > 3) { - NR_NZP_CSI_RS_Resource_t *nzpres4 = calloc(1,sizeof(*nzpres4)); - nzpres4->nzp_CSI_RS_ResourceId=4; - nzpres4->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres4->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres4->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres4->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres4->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=1; - nzpres4->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres4->resourceMapping.firstOFDMSymbolInTimeDomain=4; - nzpres4->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres4->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres4->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres4->resourceMapping.density.choice.three=(NULL_t)0; - nzpres4->resourceMapping.freqBand.startingRB=0; - nzpres4->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres4->powerControlOffset=0; - nzpres4->powerControlOffsetSS=calloc(1,sizeof(*nzpres4->powerControlOffsetSS)); - *nzpres4->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres4->scramblingID=40; - nzpres4->periodicityAndOffset = calloc(1,sizeof(*nzpres4->periodicityAndOffset)); - nzpres4->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres4->periodicityAndOffset->choice.slots160 = 26; - nzpres4->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres4->qcl_InfoPeriodicCSI_RS)); - *nzpres4->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres4); - - NR_NZP_CSI_RS_Resource_t *nzpres5 = calloc(1,sizeof(*nzpres5)); - nzpres5->nzp_CSI_RS_ResourceId=5; - nzpres5->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres5->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres5->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres5->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres5->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=1; - nzpres5->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres5->resourceMapping.firstOFDMSymbolInTimeDomain=8; - nzpres5->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres5->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres5->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres5->resourceMapping.density.choice.three=(NULL_t)0; - nzpres5->resourceMapping.freqBand.startingRB=0; - nzpres5->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres5->powerControlOffset=0; - nzpres5->powerControlOffsetSS=calloc(1,sizeof(*nzpres5->powerControlOffsetSS)); - *nzpres5->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres5->scramblingID=40; - nzpres5->periodicityAndOffset = calloc(1,sizeof(*nzpres5->periodicityAndOffset)); - nzpres5->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres5->periodicityAndOffset->choice.slots160 = 26; - nzpres5->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres5->qcl_InfoPeriodicCSI_RS)); - *nzpres5->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres5); - } - if (n_physical_antenna_ports > 7) { - NR_NZP_CSI_RS_Resource_t *nzpres6 = calloc(1,sizeof(*nzpres6)); - nzpres6->nzp_CSI_RS_ResourceId=6; - nzpres6->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres6->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres6->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres6->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres6->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=4; - nzpres6->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres6->resourceMapping.firstOFDMSymbolInTimeDomain=4; - nzpres6->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres6->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres6->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres6->resourceMapping.density.choice.three=(NULL_t)0; - nzpres6->resourceMapping.freqBand.startingRB=0; - nzpres6->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres6->powerControlOffset=0; - nzpres6->powerControlOffsetSS=calloc(1,sizeof(*nzpres6->powerControlOffsetSS)); - *nzpres6->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres6->scramblingID=40; - nzpres6->periodicityAndOffset = calloc(1,sizeof(*nzpres6->periodicityAndOffset)); - nzpres6->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres6->periodicityAndOffset->choice.slots160 = 25; - nzpres6->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres6->qcl_InfoPeriodicCSI_RS)); - *nzpres6->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres6); - - NR_NZP_CSI_RS_Resource_t *nzpres7 = calloc(1,sizeof(*nzpres7)); - nzpres7->nzp_CSI_RS_ResourceId=7; - nzpres7->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres7->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres7->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres7->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres7->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=4; - nzpres7->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres7->resourceMapping.firstOFDMSymbolInTimeDomain=8; - nzpres7->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres7->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres7->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres7->resourceMapping.density.choice.three=(NULL_t)0; - nzpres7->resourceMapping.freqBand.startingRB=0; - nzpres7->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres7->powerControlOffset=0; - nzpres7->powerControlOffsetSS=calloc(1,sizeof(*nzpres7->powerControlOffsetSS)); - *nzpres7->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres7->scramblingID=40; - nzpres7->periodicityAndOffset = calloc(1,sizeof(*nzpres7->periodicityAndOffset)); - nzpres7->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres7->periodicityAndOffset->choice.slots160 = 25; - nzpres7->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres7->qcl_InfoPeriodicCSI_RS)); - *nzpres7->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres7); - NR_NZP_CSI_RS_Resource_t *nzpres8 = calloc(1,sizeof(*nzpres8)); - nzpres8->nzp_CSI_RS_ResourceId=8; - nzpres8->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres8->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres8->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres8->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres8->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=4; - nzpres8->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres8->resourceMapping.firstOFDMSymbolInTimeDomain=4; - nzpres8->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres8->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres8->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres8->resourceMapping.density.choice.three=(NULL_t)0; - nzpres8->resourceMapping.freqBand.startingRB=0; - nzpres8->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres8->powerControlOffset=0; - nzpres8->powerControlOffsetSS=calloc(1,sizeof(*nzpres8->powerControlOffsetSS)); - *nzpres8->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres8->scramblingID=40; - nzpres8->periodicityAndOffset = calloc(1,sizeof(*nzpres8->periodicityAndOffset)); - nzpres8->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres8->periodicityAndOffset->choice.slots160 = 26; - nzpres8->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres8->qcl_InfoPeriodicCSI_RS)); - *nzpres8->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres8); - - NR_NZP_CSI_RS_Resource_t *nzpres9 = calloc(1,sizeof(*nzpres9)); - nzpres9->nzp_CSI_RS_ResourceId=9; - nzpres9->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres9->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres9->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres9->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres9->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=4; - nzpres9->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres9->resourceMapping.firstOFDMSymbolInTimeDomain=8; - nzpres9->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres9->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres9->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres9->resourceMapping.density.choice.three=(NULL_t)0; - nzpres9->resourceMapping.freqBand.startingRB=0; - nzpres9->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres9->powerControlOffset=0; - nzpres9->powerControlOffsetSS=calloc(1,sizeof(*nzpres9->powerControlOffsetSS)); - *nzpres9->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres9->scramblingID=40; - nzpres9->periodicityAndOffset = calloc(1,sizeof(*nzpres9->periodicityAndOffset)); - nzpres9->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres9->periodicityAndOffset->choice.slots160 = 26; - nzpres9->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres9->qcl_InfoPeriodicCSI_RS)); - *nzpres9->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres9); - } - if (n_physical_antenna_ports > 15) { - NR_NZP_CSI_RS_Resource_t *nzpres10 = calloc(1,sizeof(*nzpres10)); - nzpres10->nzp_CSI_RS_ResourceId=10; - nzpres10->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres10->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres10->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres10->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres10->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=2; - nzpres10->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres10->resourceMapping.firstOFDMSymbolInTimeDomain=4; - nzpres10->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres10->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres10->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres10->resourceMapping.density.choice.three=(NULL_t)0; - nzpres10->resourceMapping.freqBand.startingRB=0; - nzpres10->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres10->powerControlOffset=0; - nzpres10->powerControlOffsetSS=calloc(1,sizeof(*nzpres10->powerControlOffsetSS)); - *nzpres10->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres10->scramblingID=40; - nzpres10->periodicityAndOffset = calloc(1,sizeof(*nzpres10->periodicityAndOffset)); - nzpres10->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres10->periodicityAndOffset->choice.slots160 = 25; - nzpres10->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres10->qcl_InfoPeriodicCSI_RS)); - *nzpres10->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres10); - - NR_NZP_CSI_RS_Resource_t *nzpres11 = calloc(1,sizeof(*nzpres11)); - nzpres11->nzp_CSI_RS_ResourceId=11; - nzpres11->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres11->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres11->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres11->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres11->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=2; - nzpres11->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres11->resourceMapping.firstOFDMSymbolInTimeDomain=8; - nzpres11->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres11->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres11->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres11->resourceMapping.density.choice.three=(NULL_t)0; - nzpres11->resourceMapping.freqBand.startingRB=0; - nzpres11->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres11->powerControlOffset=0; - nzpres11->powerControlOffsetSS=calloc(1,sizeof(*nzpres11->powerControlOffsetSS)); - *nzpres11->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres11->scramblingID=40; - nzpres11->periodicityAndOffset = calloc(1,sizeof(*nzpres11->periodicityAndOffset)); - nzpres11->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres11->periodicityAndOffset->choice.slots160 = 25; - nzpres11->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres11->qcl_InfoPeriodicCSI_RS)); - *nzpres11->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres11); - NR_NZP_CSI_RS_Resource_t *nzpres12 = calloc(1,sizeof(*nzpres12)); - nzpres12->nzp_CSI_RS_ResourceId=12; - nzpres12->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres12->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres12->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres12->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres12->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=2; - nzpres12->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres12->resourceMapping.firstOFDMSymbolInTimeDomain=4; - nzpres12->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres12->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres12->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres12->resourceMapping.density.choice.three=(NULL_t)0; - nzpres12->resourceMapping.freqBand.startingRB=0; - nzpres12->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres12->powerControlOffset=0; - nzpres12->powerControlOffsetSS=calloc(1,sizeof(*nzpres12->powerControlOffsetSS)); - *nzpres12->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres12->scramblingID=40; - nzpres12->periodicityAndOffset = calloc(1,sizeof(*nzpres12->periodicityAndOffset)); - nzpres12->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres12->periodicityAndOffset->choice.slots160 = 26; - nzpres12->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres12->qcl_InfoPeriodicCSI_RS)); - *nzpres12->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres12); - - NR_NZP_CSI_RS_Resource_t *nzpres13 = calloc(1,sizeof(*nzpres13)); - nzpres13->nzp_CSI_RS_ResourceId=13; - nzpres13->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres13->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres13->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres13->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres13->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=2; - nzpres13->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres13->resourceMapping.firstOFDMSymbolInTimeDomain=8; - nzpres13->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres13->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres13->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres13->resourceMapping.density.choice.three=(NULL_t)0; - nzpres13->resourceMapping.freqBand.startingRB=0; - nzpres13->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres13->powerControlOffset=0; - nzpres13->powerControlOffsetSS=calloc(1,sizeof(*nzpres13->powerControlOffsetSS)); - *nzpres13->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres13->scramblingID=40; - nzpres13->periodicityAndOffset = calloc(1,sizeof(*nzpres13->periodicityAndOffset)); - nzpres13->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres13->periodicityAndOffset->choice.slots160 = 26; - nzpres13->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres13->qcl_InfoPeriodicCSI_RS)); - *nzpres13->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres13); - NR_NZP_CSI_RS_Resource_t *nzpres14 = calloc(1,sizeof(*nzpres14)); - nzpres14->nzp_CSI_RS_ResourceId=14; - nzpres14->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres14->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres14->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres14->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres14->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=8; - nzpres14->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres14->resourceMapping.firstOFDMSymbolInTimeDomain=4; - nzpres14->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres14->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres14->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres14->resourceMapping.density.choice.three=(NULL_t)0; - nzpres14->resourceMapping.freqBand.startingRB=0; - nzpres14->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres14->powerControlOffset=0; - nzpres14->powerControlOffsetSS=calloc(1,sizeof(*nzpres14->powerControlOffsetSS)); - *nzpres14->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres14->scramblingID=40; - nzpres14->periodicityAndOffset = calloc(1,sizeof(*nzpres14->periodicityAndOffset)); - nzpres14->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres14->periodicityAndOffset->choice.slots160 = 25; - nzpres14->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres14->qcl_InfoPeriodicCSI_RS)); - *nzpres14->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres14); - - NR_NZP_CSI_RS_Resource_t *nzpres15 = calloc(1,sizeof(*nzpres15)); - nzpres15->nzp_CSI_RS_ResourceId=15; - nzpres15->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres15->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres15->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres15->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres15->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=8; - nzpres15->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres15->resourceMapping.firstOFDMSymbolInTimeDomain=8; - nzpres15->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres15->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres15->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres15->resourceMapping.density.choice.three=(NULL_t)0; - nzpres15->resourceMapping.freqBand.startingRB=0; - nzpres15->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres15->powerControlOffset=0; - nzpres15->powerControlOffsetSS=calloc(1,sizeof(*nzpres15->powerControlOffsetSS)); - *nzpres15->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres15->scramblingID=40; - nzpres15->periodicityAndOffset = calloc(1,sizeof(*nzpres15->periodicityAndOffset)); - nzpres15->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres15->periodicityAndOffset->choice.slots160 = 25; - nzpres15->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres15->qcl_InfoPeriodicCSI_RS)); - *nzpres15->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres15); - NR_NZP_CSI_RS_Resource_t *nzpres16 = calloc(1,sizeof(*nzpres16)); - nzpres16->nzp_CSI_RS_ResourceId=16; - nzpres16->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres16->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres16->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres16->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres16->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=8; - nzpres16->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres16->resourceMapping.firstOFDMSymbolInTimeDomain=5; - nzpres16->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres16->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres16->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres16->resourceMapping.density.choice.three=(NULL_t)0; - nzpres16->resourceMapping.freqBand.startingRB=0; - nzpres16->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres16->powerControlOffset=0; - nzpres16->powerControlOffsetSS=calloc(1,sizeof(*nzpres16->powerControlOffsetSS)); - *nzpres16->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres16->scramblingID=40; - nzpres16->periodicityAndOffset = calloc(1,sizeof(*nzpres16->periodicityAndOffset)); - nzpres16->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres16->periodicityAndOffset->choice.slots160 = 26; - nzpres16->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres16->qcl_InfoPeriodicCSI_RS)); - *nzpres16->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres16); - - NR_NZP_CSI_RS_Resource_t *nzpres17 = calloc(1,sizeof(*nzpres17)); - nzpres17->nzp_CSI_RS_ResourceId=9; - nzpres17->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres17->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres17->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres17->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres17->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=8; - nzpres17->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres17->resourceMapping.firstOFDMSymbolInTimeDomain=9; - nzpres17->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres17->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres17->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres17->resourceMapping.density.choice.three=(NULL_t)0; - nzpres17->resourceMapping.freqBand.startingRB=0; - nzpres17->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres17->powerControlOffset=0; - nzpres17->powerControlOffsetSS=calloc(1,sizeof(*nzpres17->powerControlOffsetSS)); - *nzpres17->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres17->scramblingID=40; - nzpres17->periodicityAndOffset = calloc(1,sizeof(*nzpres17->periodicityAndOffset)); - nzpres17->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres17->periodicityAndOffset->choice.slots160 = 26; - nzpres17->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres17->qcl_InfoPeriodicCSI_RS)); - *nzpres17->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres17); - } - - if (n_physical_antenna_ports > 16) AssertFatal(1==0,"Fill in for more than 16 antenna elements\n"); - - csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList = calloc(1,sizeof(*csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList)); - csi_MeasConfig->nzp_CSI_RS_ResourceSetToReleaseList = NULL; - NR_NZP_CSI_RS_ResourceSet_t *nzpresset0=calloc(1,sizeof(*nzpresset0)); - nzpresset0->nzp_CSI_ResourceSetId=0; - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset00=calloc(1,sizeof(*nzpresset00)); - *nzpresset00=0; - ASN_SEQUENCE_ADD(&nzpresset0->nzp_CSI_RS_Resources.list,nzpresset00); - nzpresset0->repetition=NULL; - nzpresset0->aperiodicTriggeringOffset=NULL; - nzpresset0->trs_Info=NULL; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset0); - if (n_physical_antenna_ports > 1) { - NR_NZP_CSI_RS_ResourceSet_t *nzpresset3=calloc(1,sizeof(*nzpresset3)); - nzpresset3->nzp_CSI_ResourceSetId=3; - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset30=calloc(1,sizeof(*nzpresset30)); - *nzpresset30=2; - ASN_SEQUENCE_ADD(&nzpresset3->nzp_CSI_RS_Resources.list,nzpresset30); - if (n_physical_antenna_ports > 3) { - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset31=calloc(1,sizeof(*nzpresset31)); - *nzpresset31=3; - ASN_SEQUENCE_ADD(&nzpresset3->nzp_CSI_RS_Resources.list,nzpresset31); - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset32=calloc(1,sizeof(*nzpresset32)); - *nzpresset32=4; - ASN_SEQUENCE_ADD(&nzpresset3->nzp_CSI_RS_Resources.list,nzpresset32); - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset33=calloc(1,sizeof(*nzpresset33)); - *nzpresset33=5; - ASN_SEQUENCE_ADD(&nzpresset3->nzp_CSI_RS_Resources.list,nzpresset33); - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset3); - } - nzpresset3->repetition=calloc(1,sizeof(*nzpresset3->repetition)); - *nzpresset3->repetition=NR_NZP_CSI_RS_ResourceSet__repetition_off; - nzpresset3->aperiodicTriggeringOffset=NULL; - nzpresset3->trs_Info=calloc(1,sizeof(*nzpresset3->trs_Info)); - *nzpresset3->trs_Info=NR_NZP_CSI_RS_ResourceSet__trs_Info_true; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset3); - } - - if (n_physical_antenna_ports > 7) { - NR_NZP_CSI_RS_ResourceSet_t *nzpresset4=calloc(1,sizeof(*nzpresset4)); - nzpresset4->nzp_CSI_ResourceSetId=4; - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset40=calloc(1,sizeof(*nzpresset40)); - *nzpresset40=6; - ASN_SEQUENCE_ADD(&nzpresset4->nzp_CSI_RS_Resources.list,nzpresset40); - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset41=calloc(1,sizeof(*nzpresset41)); - *nzpresset41=7; - ASN_SEQUENCE_ADD(&nzpresset4->nzp_CSI_RS_Resources.list,nzpresset41); - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset42=calloc(1,sizeof(*nzpresset42)); - *nzpresset42=8; - ASN_SEQUENCE_ADD(&nzpresset4->nzp_CSI_RS_Resources.list,nzpresset42); - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset43=calloc(1,sizeof(*nzpresset43)); - *nzpresset43=9; - ASN_SEQUENCE_ADD(&nzpresset4->nzp_CSI_RS_Resources.list,nzpresset43); - nzpresset4->repetition=calloc(1,sizeof(*nzpresset4->repetition)); - *nzpresset4->repetition=NR_NZP_CSI_RS_ResourceSet__repetition_off; - nzpresset4->aperiodicTriggeringOffset=NULL; - nzpresset4->trs_Info=calloc(1,sizeof(*nzpresset4->trs_Info)); - *nzpresset4->trs_Info=NR_NZP_CSI_RS_ResourceSet__trs_Info_true; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset4); - } - if (n_physical_antenna_ports > 15) { - NR_NZP_CSI_RS_ResourceSet_t *nzpresset5=calloc(1,sizeof(*nzpresset5)); - nzpresset5->nzp_CSI_ResourceSetId=5; - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset50=calloc(1,sizeof(*nzpresset50)); - *nzpresset50=10; - ASN_SEQUENCE_ADD(&nzpresset5->nzp_CSI_RS_Resources.list,nzpresset50); - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset51=calloc(1,sizeof(*nzpresset51)); - *nzpresset51=11; - ASN_SEQUENCE_ADD(&nzpresset5->nzp_CSI_RS_Resources.list,nzpresset51); - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset52=calloc(1,sizeof(*nzpresset52)); - *nzpresset52=12; - ASN_SEQUENCE_ADD(&nzpresset5->nzp_CSI_RS_Resources.list,nzpresset52); - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset53=calloc(1,sizeof(*nzpresset53)); - *nzpresset53=13; - ASN_SEQUENCE_ADD(&nzpresset5->nzp_CSI_RS_Resources.list,nzpresset53); - nzpresset5->repetition=calloc(1,sizeof(*nzpresset5->repetition)); - *nzpresset5->repetition=NR_NZP_CSI_RS_ResourceSet__repetition_off; - nzpresset5->aperiodicTriggeringOffset=NULL; - nzpresset5->trs_Info=calloc(1,sizeof(*nzpresset5->trs_Info)); - *nzpresset5->trs_Info=NR_NZP_CSI_RS_ResourceSet__trs_Info_true; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset5); - } - - csi_MeasConfig->csi_IM_ResourceToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_IM_ResourceToAddModList)); - csi_MeasConfig->csi_IM_ResourceToReleaseList = NULL; - NR_CSI_IM_Resource_t *imres0 = calloc(1,sizeof(*imres0)); - imres0->csi_IM_ResourceId=0; - imres0->csi_IM_ResourceElementPattern=calloc(1,sizeof(*imres0->csi_IM_ResourceElementPattern)); - imres0->csi_IM_ResourceElementPattern->present = NR_CSI_IM_Resource__csi_IM_ResourceElementPattern_PR_pattern1 ; - imres0->csi_IM_ResourceElementPattern->choice.pattern1=calloc(1,sizeof(*imres0->csi_IM_ResourceElementPattern->choice.pattern1)); - imres0->csi_IM_ResourceElementPattern->choice.pattern1->subcarrierLocation_p1 = NR_CSI_IM_Resource__csi_IM_ResourceElementPattern__pattern1__subcarrierLocation_p1_s4; - imres0->csi_IM_ResourceElementPattern->choice.pattern1->symbolLocation_p1=7; - imres0->freqBand=calloc(1,sizeof(*imres0->freqBand)); - imres0->freqBand->startingRB=0; - imres0->freqBand->nrofRBs=276; - imres0->periodicityAndOffset=calloc(1,sizeof(*imres0->periodicityAndOffset)); - imres0->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots320; - imres0->periodicityAndOffset->choice.slots320 = 2; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_IM_ResourceToAddModList->list,imres0); - csi_MeasConfig->csi_IM_ResourceSetToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_IM_ResourceSetToAddModList)); - csi_MeasConfig->csi_IM_ResourceSetToReleaseList = NULL; - NR_CSI_IM_ResourceSet_t *imresset0 = calloc(1,sizeof(*imresset0)); - imresset0->csi_IM_ResourceSetId=0; - NR_CSI_IM_ResourceId_t *imresset00=calloc(1,sizeof(*imresset00)); - *imresset00=0; - ASN_SEQUENCE_ADD(&imresset0->csi_IM_Resources.list,imresset00); - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_IM_ResourceSetToAddModList->list,imresset0); - - csi_MeasConfig->csi_SSB_ResourceSetToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_SSB_ResourceSetToAddModList)); - csi_MeasConfig->csi_SSB_ResourceSetToReleaseList = NULL; - NR_CSI_SSB_ResourceSet_t *ssbresset0 = calloc(1,sizeof(*ssbresset0)); - ssbresset0->csi_SSB_ResourceSetId=0; - NR_SSB_Index_t *ssbresset00=calloc(1,sizeof(*ssbresset00)); - *ssbresset00=0; - ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset00); - if (n_physical_antenna_ports > 1) { - NR_SSB_Index_t *ssbresset01=calloc(1,sizeof(*ssbresset01)); - *ssbresset01=1; - ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset01); - } - if (n_physical_antenna_ports > 3) { - NR_SSB_Index_t *ssbresset02=calloc(1,sizeof(*ssbresset02)); - *ssbresset02=2; - ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset02); - NR_SSB_Index_t *ssbresset03=calloc(1,sizeof(*ssbresset03)); - *ssbresset03=3; - ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset03); - } - if (n_physical_antenna_ports > 7) { - NR_SSB_Index_t *ssbresset04=calloc(1,sizeof(*ssbresset04)); - *ssbresset04=4; - ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset04); - NR_SSB_Index_t *ssbresset05=calloc(1,sizeof(*ssbresset05)); - *ssbresset05=5; - ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset05); - NR_SSB_Index_t *ssbresset06=calloc(1,sizeof(*ssbresset06)); - *ssbresset06=6; - ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset06); - NR_SSB_Index_t *ssbresset07=calloc(1,sizeof(*ssbresset07)); - *ssbresset07=7; - ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset07); - } - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_SSB_ResourceSetToAddModList->list,ssbresset0); - - csi_MeasConfig->csi_ResourceConfigToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_ResourceConfigToAddModList)); - csi_MeasConfig->csi_ResourceConfigToReleaseList = NULL; - NR_CSI_ResourceConfig_t *csires0 = calloc(1,sizeof(*csires0)); - csires0->csi_ResourceConfigId=0; - csires0->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires00 = calloc(1,sizeof(*csires00)); - *csires00 = 0; - ASN_SEQUENCE_ADD(&csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires00); - csires0->bwp_Id = 1; - csires0->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires0); - - NR_CSI_ResourceConfig_t *csires11 = calloc(1,sizeof(*csires11)); - csires11->csi_ResourceConfigId=11; - csires11->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_csi_IM_ResourceSetList; - csires11->csi_RS_ResourceSetList.choice.csi_IM_ResourceSetList = calloc(1,sizeof(*csires11->csi_RS_ResourceSetList.choice.csi_IM_ResourceSetList)); - NR_NZP_CSI_RS_ResourceSetId_t *csires110 = calloc(1,sizeof(*csires110)); - *csires110 = 0; - ASN_SEQUENCE_ADD(&csires11->csi_RS_ResourceSetList.choice.csi_IM_ResourceSetList->list,csires110); - csires11->bwp_Id = 1; - csires11->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires11); - - NR_CSI_ResourceConfig_t *csires10 = calloc(1,sizeof(*csires10)); - csires10->csi_ResourceConfigId=10; - csires10->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires100 = calloc(1,sizeof(*csires100)); - *csires100 = 0; - ASN_SEQUENCE_ADD(&csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires100); - csires10->bwp_Id = 1; - csires10->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires10); - - NR_CSI_ResourceConfig_t *csires2 = calloc(1,sizeof(*csires2)); - csires2->csi_ResourceConfigId=2; - csires2->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires20 = calloc(1,sizeof(*csires20)); - *csires20 = 0; - ASN_SEQUENCE_ADD(&csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires20); - csires2->bwp_Id = 1; - csires2->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires2); - - NR_CSI_ResourceConfig_t *csires3 = calloc(1,sizeof(*csires3)); - csires3->csi_ResourceConfigId=3; - csires3->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires30 = calloc(1,sizeof(*csires30)); - *csires30 = 0; - ASN_SEQUENCE_ADD(&csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires30); - csires3->bwp_Id = 1; - csires3->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires3); - - NR_CSI_ResourceConfig_t *csires4 = calloc(1,sizeof(*csires4)); - csires4->csi_ResourceConfigId=4; - csires4->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires40 = calloc(1,sizeof(*csires40)); - *csires40 = 0; - ASN_SEQUENCE_ADD(&csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires40); - csires4->bwp_Id = 1; - csires4->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires4); - - NR_CSI_ResourceConfig_t *csires5 = calloc(1,sizeof(*csires5)); - csires5->csi_ResourceConfigId=5; - csires5->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires50 = calloc(1,sizeof(*csires50)); - *csires50 = 0; - ASN_SEQUENCE_ADD(&csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires50); - csires5->bwp_Id = 1; - csires5->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires5); - - NR_CSI_ResourceConfig_t *csires6 = calloc(1,sizeof(*csires6)); - csires6->csi_ResourceConfigId=6; - csires6->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires60 = calloc(1,sizeof(*csires60)); - *csires60 = 0; - ASN_SEQUENCE_ADD(&csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires60); - csires6->bwp_Id = 1; - csires6->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires6); - - NR_CSI_ResourceConfig_t *csires7 = calloc(1,sizeof(*csires7)); - csires7->csi_ResourceConfigId=7; - csires7->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires70 = calloc(1,sizeof(*csires70)); - *csires70 = 0; - ASN_SEQUENCE_ADD(&csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires70); - csires7->bwp_Id = 1; - csires7->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires7); - - NR_CSI_ResourceConfig_t *csires8 = calloc(1,sizeof(*csires8)); - csires8->csi_ResourceConfigId=8; - csires8->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires80 = calloc(1,sizeof(*csires80)); - *csires80 = 0; - ASN_SEQUENCE_ADD(&csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires80); - csires8->bwp_Id = 1; - csires8->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires8); - - NR_CSI_ResourceConfig_t *csires9 = calloc(1,sizeof(*csires9)); - csires9->csi_ResourceConfigId=9; - csires9->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires90 = calloc(1,sizeof(*csires90)); - *csires90 = 0; - ASN_SEQUENCE_ADD(&csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires90); - csires9->bwp_Id = 1; - csires9->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires9); - - csi_MeasConfig->csi_ReportConfigToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_ReportConfigToAddModList)); - csi_MeasConfig->csi_ReportConfigToReleaseList = NULL; - NR_CSI_ReportConfig_t *csirep0 = calloc(1,sizeof(*csirep0)); - csirep0->reportConfigId=0; - csirep0->carrier=NULL; - csirep0->resourcesForChannelMeasurement=0; - csirep0->csi_IM_ResourcesForInterference=calloc(1,sizeof(*csirep0->csi_IM_ResourcesForInterference)); - *csirep0->csi_IM_ResourcesForInterference=11; - csirep0->nzp_CSI_RS_ResourcesForInterference=NULL; - csirep0->reportConfigType.present = NR_CSI_ReportConfig__reportConfigType_PR_periodic; - csirep0->reportConfigType.choice.periodic = calloc(1,sizeof(*csirep0->reportConfigType.choice.periodic)); - csirep0->reportConfigType.choice.periodic->reportSlotConfig.present=NR_CSI_ReportPeriodicityAndOffset_PR_slots320; - csirep0->reportConfigType.choice.periodic->reportSlotConfig.choice.slots320 = 9; - - NR_PUCCH_CSI_Resource_t *pucchcsires0 = calloc(1,sizeof(*pucchcsires0)); - pucchcsires0->uplinkBandwidthPartId=1; - pucchcsires0->pucch_Resource=11; - ASN_SEQUENCE_ADD(&csirep0->reportConfigType.choice.periodic->pucch_CSI_ResourceList.list,pucchcsires0); - csirep0->reportQuantity.present = NR_CSI_ReportConfig__reportQuantity_PR_cri_RI_LI_PMI_CQI; - csirep0->reportQuantity.choice.cri_RI_PMI_CQI = (NULL_t)0; - csirep0->reportFreqConfiguration = calloc(1,sizeof(*csirep0->reportFreqConfiguration)); - csirep0->reportFreqConfiguration->cqi_FormatIndicator=NR_CSI_ReportConfig__reportFreqConfiguration__cqi_FormatIndicator_widebandCQI; - csirep0->reportFreqConfiguration->pmi_FormatIndicator=NR_CSI_ReportConfig__reportFreqConfiguration__pmi_FormatIndicator_widebandPMI; - csirep0->reportFreqConfiguration->csi_ReportingBand=calloc(1,sizeof(*csirep0->reportFreqConfiguration->csi_ReportingBand)); - - - AssertFatal(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id>0,"firstActiveDownlinkBWP_Id %d\n",(int)*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id); - int NPRB = NRRIV2BW(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id-1]->bwp_Common->genericParameters.locationAndBandwidth,275); - int sbsize = get_subband_size(NPRB,0); - int numsb = NPRB/sbsize; - if (NPRB%sbsize == 0) numsb++; - csirep0->reportFreqConfiguration->csi_ReportingBand->present= NR_CSI_ReportConfig__reportFreqConfiguration__csi_ReportingBand_PR_NOTHING+(numsb-2); - csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.size=numsb/8; - if ((numsb&7) > 0) csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.size++; - csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.bits_unused = (8-(numsb&7))&7; - csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.buf=malloc(csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.size); - for (int i=0;ireportFreqConfiguration->csi_ReportingBand->choice.subbands18.size;i++) - csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.buf[i]=0xff; - csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.buf[csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.size-1]&=~((1<reportFreqConfiguration->csi_ReportingBand->choice.subbands18.bits_unused)-1); - - csirep0->timeRestrictionForChannelMeasurements= NR_CSI_ReportConfig__timeRestrictionForChannelMeasurements_configured; - csirep0->timeRestrictionForInterferenceMeasurements=NR_CSI_ReportConfig__timeRestrictionForInterferenceMeasurements_configured; - csirep0->codebookConfig=calloc(1,sizeof(*csirep0->codebookConfig)); - csirep0->codebookConfig->codebookType.present = NR_CodebookConfig__codebookType_PR_type1; - csirep0->codebookConfig->codebookType.choice.type1 = calloc(1,sizeof(*csirep0->codebookConfig->codebookType.choice.type1)); - csirep0->codebookConfig->codebookType.choice.type1->subType.present = NR_CodebookConfig__codebookType__type1__subType_PR_typeI_SinglePanel; - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel=calloc(1,sizeof(*csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel)); - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.present=NR_CodebookConfig__codebookType__type1__subType__typeI_SinglePanel__nrOfAntennaPorts_PR_two; - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two= - calloc(1,sizeof(*csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two)); - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.size=1; - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.bits_unused=2; - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.buf=malloc(1); - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.buf[0]=0xfc; - //'111111'B - - - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.size=1; - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.bits_unused=0; - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.buf=malloc(1); - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.buf[0]=0xc0; //'00000011'B - - csirep0->codebookConfig->codebookType.choice.type1->codebookMode=1; - csirep0->dummy = NULL; - csirep0->groupBasedBeamReporting.present = NR_CSI_ReportConfig__groupBasedBeamReporting_PR_disabled; - csirep0->groupBasedBeamReporting.choice.disabled=calloc(1,sizeof(*csirep0->groupBasedBeamReporting.choice.disabled)); - csirep0->groupBasedBeamReporting.choice.disabled->nrofReportedRS = NULL; - csirep0->cqi_Table = calloc(1,sizeof(*csirep0->cqi_Table)); - *csirep0->cqi_Table = NR_CSI_ReportConfig__cqi_Table_table1; - csirep0->subbandSize = NR_CSI_ReportConfig__subbandSize_value1; - csirep0->non_PMI_PortIndication = NULL; - csirep0->ext1 = NULL; - - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ReportConfigToAddModList->list,csirep0); - - NR_CSI_ReportConfig_t *csirep1 = calloc(1,sizeof(*csirep1)); - csirep1->reportConfigId=2; - csirep1->carrier=NULL; - csirep1->resourcesForChannelMeasurement=initial_csi_index; - csirep1->csi_IM_ResourcesForInterference=NULL; - csirep1->nzp_CSI_RS_ResourcesForInterference=NULL; - csirep1->reportConfigType.present = NR_CSI_ReportConfig__reportConfigType_PR_periodic; - csirep1->reportConfigType.choice.periodic = calloc(1,sizeof(*csirep1->reportConfigType.choice.periodic)); - csirep1->reportConfigType.choice.periodic->reportSlotConfig.present=NR_CSI_ReportPeriodicityAndOffset_PR_slots320; - csirep1->reportConfigType.choice.periodic->reportSlotConfig.choice.slots320 = 49; - NR_PUCCH_CSI_Resource_t *pucchcsires1 = calloc(1,sizeof(*pucchcsires1)); - pucchcsires1->uplinkBandwidthPartId=1; - pucchcsires1->pucch_Resource=12; - ASN_SEQUENCE_ADD(&csirep1->reportConfigType.choice.periodic->pucch_CSI_ResourceList.list,pucchcsires1); - csirep1->reportQuantity.present = NR_CSI_ReportConfig__reportQuantity_PR_ssb_Index_RSRP; - csirep1->reportQuantity.choice.ssb_Index_RSRP=(NULL_t)0; - csirep1->reportFreqConfiguration = calloc(1,sizeof(*csirep1->reportFreqConfiguration)); - csirep1->reportFreqConfiguration->cqi_FormatIndicator=NR_CSI_ReportConfig__reportFreqConfiguration__cqi_FormatIndicator_widebandCQI; - csirep1->reportFreqConfiguration->pmi_FormatIndicator=NR_CSI_ReportConfig__reportFreqConfiguration__pmi_FormatIndicator_widebandPMI; - csirep1->reportFreqConfiguration->csi_ReportingBand=NULL; - csirep1->timeRestrictionForChannelMeasurements= NR_CSI_ReportConfig__timeRestrictionForChannelMeasurements_configured; - csirep1->timeRestrictionForInterferenceMeasurements=NR_CSI_ReportConfig__timeRestrictionForInterferenceMeasurements_configured; - csirep1->codebookConfig=calloc(1,sizeof(*csirep1->codebookConfig)); - csirep1->codebookConfig->codebookType.present = NR_CodebookConfig__codebookType_PR_type1; - csirep1->codebookConfig->codebookType.choice.type1 = calloc(1,sizeof(*csirep1->codebookConfig->codebookType.choice.type1)); - csirep1->codebookConfig->codebookType.choice.type1->subType.present=NR_CodebookConfig__codebookType__type1__subType_PR_typeI_SinglePanel; - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel=calloc(1,sizeof(*csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel)); - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.present=NR_CodebookConfig__codebookType__type1__subType__typeI_SinglePanel__nrOfAntennaPorts_PR_two; - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two= - calloc(1,sizeof(*csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two)); - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.size=1; - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.bits_unused=2; - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.buf=malloc(1); - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.buf[0]=0xfc; - //'111111'B - - - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.size=1; - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.bits_unused=0; - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.buf=malloc(1); - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.buf[0]=0xc0; //'00000011'B - - csirep1->codebookConfig->codebookType.choice.type1->codebookMode=1; - csirep1->dummy = NULL; - csirep1->groupBasedBeamReporting.present = NR_CSI_ReportConfig__groupBasedBeamReporting_PR_disabled; - csirep1->groupBasedBeamReporting.choice.disabled=calloc(1,sizeof(*csirep1->groupBasedBeamReporting.choice.disabled)); - csirep1->groupBasedBeamReporting.choice.disabled->nrofReportedRS = calloc(1,sizeof(*csirep1->groupBasedBeamReporting.choice.disabled->nrofReportedRS)); - *csirep1->groupBasedBeamReporting.choice.disabled->nrofReportedRS=NR_CSI_ReportConfig__groupBasedBeamReporting__disabled__nrofReportedRS_n2; - // this corresponds to: - //if the UE is configured with the higher layer parameter groupBasedBeamReporting set to 'disabled', the UE is not required to update measurements for more than 64 CSI-RS and/or SSB resources, and the UE shall report in a single report nrofReportedRS (higher layer configured) different CRI or SSBRI for each report setting. - - csirep1->cqi_Table = calloc(1,sizeof(*csirep1->cqi_Table)); - *csirep1->cqi_Table = NR_CSI_ReportConfig__cqi_Table_table1; - csirep1->subbandSize = NR_CSI_ReportConfig__subbandSize_value1; - csirep1->non_PMI_PortIndication = NULL; - csirep1->ext1 = NULL; - - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ReportConfigToAddModList->list,csirep1); - - - secondaryCellGroup->spCellConfig->spCellConfigDedicated->sCellDeactivationTimer=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->tag_Id=0; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->dummy=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->pathlossReferenceLinking=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->servingCellMO=NULL; - + bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup = calloc(1, + sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup)); + bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->maxLength=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->scramblingID0=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->scramblingID1=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->phaseTrackingRS=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = calloc(1, + sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition)); + *bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList=calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList)); + NR_TCI_State_t *tcid0=calloc(1,sizeof(*tcid0)); + tcid0->tci_StateId=0; + tcid0->qcl_Type1.cell=NULL; + tcid0->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid0->qcl_Type1.bwp_Id)); + *tcid0->qcl_Type1.bwp_Id=1; + tcid0->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tcid0->qcl_Type1.referenceSignal.choice.csi_rs = 2; + tcid0->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid0); + NR_TCI_State_t *tcid1=calloc(1,sizeof(*tcid1)); + tcid1->tci_StateId=0; + tcid1->qcl_Type1.cell=NULL; + tcid1->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid1->qcl_Type1.bwp_Id)); + *tcid1->qcl_Type1.bwp_Id=1; + tcid1->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tcid1->qcl_Type1.referenceSignal.choice.csi_rs = 6; + tcid1->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid1); + NR_TCI_State_t *tcid2=calloc(1,sizeof(*tcid2)); + tcid2->tci_StateId=2; + tcid2->qcl_Type1.cell=NULL; + tcid2->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid2->qcl_Type1.bwp_Id)); + *tcid2->qcl_Type1.bwp_Id=1; + tcid2->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tcid2->qcl_Type1.referenceSignal.choice.csi_rs = 10; + tcid2->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid2); + NR_TCI_State_t *tcid3=calloc(1,sizeof(*tcid3)); + tcid3->tci_StateId=3; + tcid3->qcl_Type1.cell=NULL; + tcid3->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid3->qcl_Type1.bwp_Id)); + *tcid3->qcl_Type1.bwp_Id=1; + tcid3->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tcid3->qcl_Type1.referenceSignal.choice.csi_rs = 14; + tcid3->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid3); + NR_TCI_State_t *tcid4=calloc(1,sizeof(*tcid4)); + tcid4->tci_StateId=4; + tcid4->qcl_Type1.cell=NULL; + tcid4->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid4->qcl_Type1.bwp_Id)); + *tcid4->qcl_Type1.bwp_Id=1; + tcid4->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tcid4->qcl_Type1.referenceSignal.choice.csi_rs = 18; + tcid4->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid4); + NR_TCI_State_t *tcid5=calloc(1,sizeof(*tcid5)); + tcid5->tci_StateId=5; + tcid5->qcl_Type1.cell=NULL; + tcid5->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid5->qcl_Type1.bwp_Id)); + *tcid5->qcl_Type1.bwp_Id=1; + tcid5->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tcid5->qcl_Type1.referenceSignal.choice.csi_rs = 22; + tcid5->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid5); + NR_TCI_State_t *tcid6=calloc(1,sizeof(*tcid6)); + tcid6->tci_StateId=6; + tcid6->qcl_Type1.cell=NULL; + tcid6->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid6->qcl_Type1.bwp_Id)); + *tcid6->qcl_Type1.bwp_Id=1; + tcid6->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tcid6->qcl_Type1.referenceSignal.choice.csi_rs = 26; + tcid6->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid6); + NR_TCI_State_t *tcid7=calloc(1,sizeof(*tcid7)); + tcid7->tci_StateId=7; + tcid7->qcl_Type1.cell=NULL; + tcid7->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid7->qcl_Type1.bwp_Id)); + *tcid7->qcl_Type1.bwp_Id=1; + tcid7->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tcid7->qcl_Type1.referenceSignal.choice.csi_rs = 30; + tcid7->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid7); + NR_TCI_State_t *tcid8=calloc(1,sizeof(*tcid8)); + tcid8->tci_StateId=8; + tcid8->qcl_Type1.cell=NULL; + tcid8->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid8->qcl_Type1.bwp_Id)); + *tcid8->qcl_Type1.bwp_Id=1; + tcid8->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tcid8->qcl_Type1.referenceSignal.choice.ssb = 0; + tcid8->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid8); + NR_TCI_State_t *tcid9=calloc(1,sizeof(*tcid9)); + tcid9->tci_StateId=9; + tcid9->qcl_Type1.cell=NULL; + tcid9->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid9->qcl_Type1.bwp_Id)); + *tcid9->qcl_Type1.bwp_Id=1; + tcid9->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tcid9->qcl_Type1.referenceSignal.choice.ssb = 1; + tcid9->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid9); + NR_TCI_State_t *tcid10=calloc(1,sizeof(*tcid10)); + tcid10->tci_StateId=10; + tcid10->qcl_Type1.cell=NULL; + tcid10->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid10->qcl_Type1.bwp_Id)); + *tcid10->qcl_Type1.bwp_Id=1; + tcid10->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tcid10->qcl_Type1.referenceSignal.choice.ssb = 2; + tcid10->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid10); + NR_TCI_State_t *tcid11=calloc(1,sizeof(*tcid11)); + tcid11->tci_StateId=11; + tcid11->qcl_Type1.cell=NULL; + tcid11->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid11->qcl_Type1.bwp_Id)); + *tcid11->qcl_Type1.bwp_Id=1; + tcid11->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tcid11->qcl_Type1.referenceSignal.choice.ssb = 3; + tcid11->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid11); + NR_TCI_State_t *tcid12=calloc(1,sizeof(*tcid12)); + tcid12->tci_StateId=12; + tcid12->qcl_Type1.cell=NULL; + tcid12->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid12->qcl_Type1.bwp_Id)); + *tcid12->qcl_Type1.bwp_Id=1; + tcid12->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tcid12->qcl_Type1.referenceSignal.choice.ssb = 4; + tcid12->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid12); + NR_TCI_State_t *tcid13=calloc(1,sizeof(*tcid13)); + tcid13->tci_StateId=13; + tcid13->qcl_Type1.cell=NULL; + tcid13->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid13->qcl_Type1.bwp_Id)); + *tcid13->qcl_Type1.bwp_Id=1; + tcid13->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tcid13->qcl_Type1.referenceSignal.choice.ssb = 5; + tcid13->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid13); + NR_TCI_State_t *tcid14=calloc(1,sizeof(*tcid14)); + tcid14->tci_StateId=14; + tcid14->qcl_Type1.cell=NULL; + tcid14->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid14->qcl_Type1.bwp_Id)); + *tcid14->qcl_Type1.bwp_Id=1; + tcid14->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tcid14->qcl_Type1.referenceSignal.choice.ssb = 6; + tcid14->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid14); + NR_TCI_State_t *tcid15=calloc(1,sizeof(*tcid15)); + tcid15->tci_StateId=15; + tcid15->qcl_Type1.cell=NULL; + tcid15->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid15->qcl_Type1.bwp_Id)); + *tcid15->qcl_Type1.bwp_Id=1; + tcid15->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tcid15->qcl_Type1.referenceSignal.choice.ssb = 7; + tcid15->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid15); + bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup1=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup2=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rbg_Size=NR_PDSCH_Config__rbg_Size_config1; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->mcs_Table=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI)); + *bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = NR_PDSCH_Config__maxNrofCodeWordsScheduledByDCI_n1; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.present = NR_PDSCH_Config__prb_BundlingType_PR_staticBundling; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling)); + bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = + calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize)); + *bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = NR_PDSCH_Config__prb_BundlingType__staticBundling__bundleSize_wideband; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToAddModList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToAddModList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup1=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup2=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rbg_Size=NR_PDSCH_Config__rbg_Size_config1; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->mcs_Table=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI)); + *bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = NR_PDSCH_Config__maxNrofCodeWordsScheduledByDCI_n1; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.present = NR_PDSCH_Config__prb_BundlingType_PR_staticBundling; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling)); + bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = + calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize)); + *bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = NR_PDSCH_Config__prb_BundlingType__staticBundling__bundleSize_wideband; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToAddModList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToAddModList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL; + bwp->bwp_Dedicated->sps_Config = NULL; //calloc(1,sizeof(struct NR_SetupRelease_SPS_Config)); + bwp->bwp_Dedicated->radioLinkMonitoringConfig = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig)); + bwp->bwp_Dedicated->radioLinkMonitoringConfig->present = NR_SetupRelease_RadioLinkMonitoringConfig_PR_setup; + bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup)); + bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->failureDetectionResourcesToAddModList=NULL; + bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->failureDetectionResourcesToReleaseList=NULL; + bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount)); + *bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = NR_RadioLinkMonitoringConfig__beamFailureInstanceMaxCount_n3; + bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer)); + *bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = NR_RadioLinkMonitoringConfig__beamFailureDetectionTimer_pbfd2; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list,bwp); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id)); + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id=1; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->bwp_InactivityTimer = NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->defaultDownlinkBWP_Id = NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig)); + NR_BWP_UplinkDedicated_t *initialUplinkBWP = calloc(1,sizeof(*initialUplinkBWP)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->initialUplinkBWP = initialUplinkBWP; + initialUplinkBWP->pucch_Config = NULL; + initialUplinkBWP->pusch_Config = calloc(1,sizeof(*initialUplinkBWP->pusch_Config)); + initialUplinkBWP->pusch_Config->present = NR_SetupRelease_PUSCH_Config_PR_setup; + NR_PUSCH_Config_t *pusch_Config = calloc(1,sizeof(*pusch_Config)); + initialUplinkBWP->pusch_Config->choice.setup = pusch_Config; + pusch_Config->txConfig=calloc(1,sizeof(*pusch_Config->txConfig)); + *pusch_Config->txConfig= NR_PUSCH_Config__txConfig_codebook; + pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA = NULL; + pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB = calloc(1,sizeof(*pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB)); + pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->present = NR_SetupRelease_DMRS_UplinkConfig_PR_setup; + pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup = calloc(1,sizeof(*pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup)); + NR_DMRS_UplinkConfig_t *NR_DMRS_UplinkConfig = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup; + NR_DMRS_UplinkConfig->dmrs_Type = NULL; + NR_DMRS_UplinkConfig->dmrs_AdditionalPosition =NR_DMRS_UplinkConfig__dmrs_AdditionalPosition_pos0; + NR_DMRS_UplinkConfig->phaseTrackingRS=NULL; + NR_DMRS_UplinkConfig->maxLength=NULL; + NR_DMRS_UplinkConfig->transformPrecodingDisabled = calloc(1,sizeof(*NR_DMRS_UplinkConfig->transformPrecodingDisabled)); + NR_DMRS_UplinkConfig->transformPrecodingDisabled->scramblingID0 = NULL; + NR_DMRS_UplinkConfig->transformPrecodingDisabled->scramblingID1 = NULL; + NR_DMRS_UplinkConfig->transformPrecodingEnabled = NULL; + pusch_Config->pusch_PowerControl = calloc(1,sizeof(*pusch_Config->pusch_PowerControl)); + pusch_Config->pusch_PowerControl->tpc_Accumulation = NULL; + pusch_Config->pusch_PowerControl->msg3_Alpha = calloc(1,sizeof(*pusch_Config->pusch_PowerControl->msg3_Alpha)); + *pusch_Config->pusch_PowerControl->msg3_Alpha = NR_Alpha_alpha1; + pusch_Config->pusch_PowerControl->p0_NominalWithoutGrant = NULL; + pusch_Config->pusch_PowerControl->p0_AlphaSets = calloc(1,sizeof(*pusch_Config->pusch_PowerControl->p0_AlphaSets)); + NR_P0_PUSCH_AlphaSet_t *aset = calloc(1,sizeof(*aset)); + aset->p0_PUSCH_AlphaSetId=0; + aset->p0=calloc(1,sizeof(*aset->p0)); + *aset->p0 = 0; + aset->alpha=calloc(1,sizeof(*aset->alpha)); + *aset->alpha=NR_Alpha_alpha1; + ASN_SEQUENCE_ADD(&pusch_Config->pusch_PowerControl->p0_AlphaSets->list,aset); + pusch_Config->pusch_PowerControl->pathlossReferenceRSToAddModList = calloc(1,sizeof(*pusch_Config->pusch_PowerControl->pathlossReferenceRSToAddModList)); + NR_PUSCH_PathlossReferenceRS_t *pl = calloc(1,sizeof(*pl)); + pl->pusch_PathlossReferenceRS_Id=0; + pl->referenceSignal.present = NR_PUSCH_PathlossReferenceRS__referenceSignal_PR_csi_RS_Index; + pl->referenceSignal.choice.csi_RS_Index=0; + ASN_SEQUENCE_ADD(&pusch_Config->pusch_PowerControl->pathlossReferenceRSToAddModList->list,pl); + pusch_Config->pusch_PowerControl->pathlossReferenceRSToReleaseList = NULL; + pusch_Config->pusch_PowerControl->twoPUSCH_PC_AdjustmentStates = NULL; + pusch_Config->pusch_PowerControl->deltaMCS = NULL; + pusch_Config->pusch_PowerControl->sri_PUSCH_MappingToAddModList = NULL; + pusch_Config->pusch_PowerControl->sri_PUSCH_MappingToReleaseList = NULL; + pusch_Config->frequencyHopping=NULL; + pusch_Config->frequencyHoppingOffsetLists=NULL; + pusch_Config->resourceAllocation = NR_PUSCH_Config__resourceAllocation_resourceAllocationType1; + pusch_Config->pusch_TimeDomainAllocationList = NULL; + pusch_Config->pusch_AggregationFactor=NULL; + pusch_Config->mcs_Table=NULL; + pusch_Config->mcs_TableTransformPrecoder=NULL; + pusch_Config->transformPrecoder=calloc(1,sizeof(*pusch_Config->transformPrecoder)); + *pusch_Config->transformPrecoder = NR_PUSCH_Config__transformPrecoder_disabled; + pusch_Config->codebookSubset=calloc(1,sizeof(*pusch_Config->codebookSubset)); + *pusch_Config->codebookSubset = NR_PUSCH_Config__codebookSubset_nonCoherent; + pusch_Config->maxRank=calloc(1,sizeof(*pusch_Config->maxRank)); + *pusch_Config->maxRank= 1; + pusch_Config->rbg_Size=NULL; + pusch_Config->uci_OnPUSCH=NULL; + pusch_Config->tp_pi2BPSK=NULL; + initialUplinkBWP->srs_Config = calloc(1,sizeof(*initialUplinkBWP->srs_Config)); + initialUplinkBWP->srs_Config->present = NR_SetupRelease_SRS_Config_PR_setup; + NR_SRS_Config_t *srs_Config = calloc(1,sizeof(*srs_Config)); + initialUplinkBWP->srs_Config->choice.setup=srs_Config; + srs_Config->srs_ResourceSetToReleaseList=NULL; + srs_Config->srs_ResourceSetToAddModList=calloc(1,sizeof(*srs_Config->srs_ResourceSetToAddModList)); + NR_SRS_ResourceSet_t *srs_resset0=calloc(1,sizeof(*srs_resset0)); + srs_resset0->srs_ResourceSetId = 0; + srs_resset0->srs_ResourceIdList=calloc(1,sizeof(*srs_resset0->srs_ResourceIdList)); + NR_SRS_ResourceId_t *srs_resset0_id=calloc(1,sizeof(*srs_resset0_id)); + *srs_resset0_id=0; + ASN_SEQUENCE_ADD(&srs_resset0->srs_ResourceIdList->list,srs_resset0_id); + srs_Config->srs_ResourceToReleaseList=NULL; + srs_resset0->resourceType.present = NR_SRS_ResourceSet__resourceType_PR_aperiodic; + srs_resset0->resourceType.choice.aperiodic = calloc(1,sizeof(*srs_resset0->resourceType.choice.aperiodic)); + srs_resset0->resourceType.choice.aperiodic->aperiodicSRS_ResourceTrigger=1; + srs_resset0->resourceType.choice.aperiodic->csi_RS=NULL; + srs_resset0->resourceType.choice.aperiodic->slotOffset= calloc(1,sizeof(*srs_resset0->resourceType.choice.aperiodic->slotOffset)); + *srs_resset0->resourceType.choice.aperiodic->slotOffset=2; + srs_resset0->resourceType.choice.aperiodic->ext1=NULL; + srs_resset0->usage=NR_SRS_ResourceSet__usage_codebook; + srs_resset0->alpha = calloc(1,sizeof(*srs_resset0->alpha)); + *srs_resset0->alpha = NR_Alpha_alpha1; + srs_resset0->p0=calloc(1,sizeof(*srs_resset0->p0)); + *srs_resset0->p0=-80; + srs_resset0->pathlossReferenceRS=NULL; + srs_resset0->srs_PowerControlAdjustmentStates=NULL; + ASN_SEQUENCE_ADD(&srs_Config->srs_ResourceSetToAddModList->list,srs_resset0); + srs_Config->srs_ResourceToReleaseList=NULL; + srs_Config->srs_ResourceToAddModList=calloc(1,sizeof(*srs_Config->srs_ResourceToAddModList)); + NR_SRS_Resource_t *srs_res0=calloc(1,sizeof(*srs_res0)); + srs_res0->srs_ResourceId=0; + srs_res0->nrofSRS_Ports=NR_SRS_Resource__nrofSRS_Ports_port1; + srs_res0->ptrs_PortIndex=NULL; + srs_res0->transmissionComb.present=NR_SRS_Resource__transmissionComb_PR_n2; + srs_res0->transmissionComb.choice.n2=calloc(1,sizeof(*srs_res0->transmissionComb.choice.n2)); + srs_res0->transmissionComb.choice.n2->combOffset_n2=0; + srs_res0->transmissionComb.choice.n2->cyclicShift_n2=0; + srs_res0->resourceMapping.startPosition=2; + srs_res0->resourceMapping.nrofSymbols=NR_SRS_Resource__resourceMapping__nrofSymbols_n1; + srs_res0->resourceMapping.repetitionFactor=NR_SRS_Resource__resourceMapping__repetitionFactor_n1; + srs_res0->freqDomainPosition=0; + srs_res0->freqDomainShift=0; + srs_res0->freqHopping.c_SRS = 61; + srs_res0->freqHopping.b_SRS=0; + srs_res0->freqHopping.b_hop=0; + srs_res0->groupOrSequenceHopping=NR_SRS_Resource__groupOrSequenceHopping_neither; + srs_res0->resourceType.present= NR_SRS_Resource__resourceType_PR_aperiodic; + srs_res0->resourceType.choice.aperiodic=calloc(1,sizeof(*srs_res0->resourceType.choice.aperiodic)); + srs_res0->sequenceId=40; + srs_res0->spatialRelationInfo=calloc(1,sizeof(*srs_res0->spatialRelationInfo)); + srs_res0->spatialRelationInfo->servingCellId=NULL; + srs_res0->spatialRelationInfo->referenceSignal.present=NR_SRS_SpatialRelationInfo__referenceSignal_PR_csi_RS_Index; + srs_res0->spatialRelationInfo->referenceSignal.choice.csi_RS_Index=0; + ASN_SEQUENCE_ADD(&srs_Config->srs_ResourceToAddModList->list,srs_res0); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToReleaseList = NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList = calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList)); + NR_BWP_Uplink_t *ubwp = calloc(1,sizeof(*ubwp)); + ubwp->bwp_Id=1; + ubwp->bwp_Common = calloc(1,sizeof(*ubwp->bwp_Common)); + // copy bwp_Common from Initial UL BWP except for bandwidth + memcpy((void *)&ubwp->bwp_Common->genericParameters, + (void *)&servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->genericParameters, + sizeof(servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->genericParameters)); + ubwp->bwp_Common->genericParameters.locationAndBandwidth=PRBalloc_to_locationandbandwidth( + servingcellconfigcommon->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth,0); + ubwp->bwp_Common->rach_ConfigCommon = servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon; + ubwp->bwp_Common->pusch_ConfigCommon = servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon; + ubwp->bwp_Common->pucch_ConfigCommon = servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon; + ubwp->bwp_Dedicated = calloc(1,sizeof(*ubwp->bwp_Dedicated)); + ubwp->bwp_Dedicated->pucch_Config = calloc(1,sizeof(*ubwp->bwp_Dedicated->pucch_Config)); + ubwp->bwp_Dedicated->pucch_Config->present = NR_SetupRelease_PUCCH_Config_PR_setup; + NR_PUCCH_Config_t *pucch_Config = calloc(1,sizeof(*pucch_Config)); + ubwp->bwp_Dedicated->pucch_Config->choice.setup=pucch_Config; + pucch_Config->resourceSetToAddModList = calloc(1,sizeof(*pucch_Config->resourceSetToAddModList)); + pucch_Config->resourceSetToReleaseList = NULL; + NR_PUCCH_ResourceSet_t *pucchresset0=calloc(1,sizeof(*pucchresset0)); + NR_PUCCH_ResourceSet_t *pucchresset1=calloc(1,sizeof(*pucchresset1)); + pucchresset0->pucch_ResourceSetId = 0; + NR_PUCCH_ResourceId_t *pucchresset0id0=calloc(1,sizeof(*pucchresset0id0)); + NR_PUCCH_ResourceId_t *pucchresset0id1=calloc(1,sizeof(*pucchresset0id1)); + *pucchresset0id0=1; + ASN_SEQUENCE_ADD(&pucchresset0->resourceList.list,pucchresset0id0); + *pucchresset0id1=2; + ASN_SEQUENCE_ADD(&pucchresset0->resourceList.list,pucchresset0id1); + pucchresset0->maxPayloadMinus1=NULL; + ASN_SEQUENCE_ADD(&pucch_Config->resourceSetToAddModList->list,pucchresset0); + pucchresset1->pucch_ResourceSetId = 1; + NR_PUCCH_ResourceId_t *pucchresset1id0=calloc(1,sizeof(*pucchresset1id0)); + NR_PUCCH_ResourceId_t *pucchresset1id1=calloc(1,sizeof(*pucchresset1id1)); + *pucchresset1id0=3; + ASN_SEQUENCE_ADD(&pucchresset1->resourceList.list,pucchresset1id0); + *pucchresset1id1=4; + ASN_SEQUENCE_ADD(&pucchresset1->resourceList.list,pucchresset1id1); + pucchresset1->maxPayloadMinus1=NULL; + ASN_SEQUENCE_ADD(&pucch_Config->resourceSetToAddModList->list,pucchresset1); + pucch_Config->resourceToAddModList = calloc(1,sizeof(*pucch_Config->resourceToAddModList)); + pucch_Config->resourceToReleaseList = NULL; + NR_PUCCH_Resource_t *pucchres0=calloc(1,sizeof(*pucchres0)); + NR_PUCCH_Resource_t *pucchres1=calloc(1,sizeof(*pucchres1)); + NR_PUCCH_Resource_t *pucchres2=calloc(1,sizeof(*pucchres2)); + NR_PUCCH_Resource_t *pucchres3=calloc(1,sizeof(*pucchres3)); + pucchres0->pucch_ResourceId=1; + pucchres0->startingPRB=48; + pucchres0->intraSlotFrequencyHopping=NULL; + pucchres0->secondHopPRB=NULL; + pucchres0->format.present= NR_PUCCH_Resource__format_PR_format0; + pucchres0->format.choice.format0=calloc(1,sizeof(*pucchres0->format.choice.format0)); + pucchres0->format.choice.format0->initialCyclicShift=0; + pucchres0->format.choice.format0->nrofSymbols=1; + pucchres0->format.choice.format0->startingSymbolIndex=13; + ASN_SEQUENCE_ADD(&pucch_Config->resourceToAddModList->list,pucchres0); + pucchres1->pucch_ResourceId=2; + pucchres1->startingPRB=48; + pucchres1->intraSlotFrequencyHopping=NULL; + pucchres1->secondHopPRB=NULL; + pucchres1->format.present= NR_PUCCH_Resource__format_PR_format0; + pucchres1->format.choice.format0=calloc(1,sizeof(*pucchres1->format.choice.format0)); + pucchres1->format.choice.format0->initialCyclicShift=0; + pucchres1->format.choice.format0->nrofSymbols=1; + pucchres1->format.choice.format0->startingSymbolIndex=12; + ASN_SEQUENCE_ADD(&pucch_Config->resourceToAddModList->list,pucchres1); + pucchres2->pucch_ResourceId=3; + pucchres2->startingPRB=40; + pucchres2->intraSlotFrequencyHopping=NULL; + pucchres2->secondHopPRB=NULL; + pucchres2->format.present= NR_PUCCH_Resource__format_PR_format2; + pucchres2->format.choice.format2=calloc(1,sizeof(*pucchres2->format.choice.format2)); + pucchres2->format.choice.format2->nrofPRBs=16; + pucchres2->format.choice.format2->nrofSymbols=1; + pucchres2->format.choice.format2->startingSymbolIndex=13; + ASN_SEQUENCE_ADD(&pucch_Config->resourceToAddModList->list,pucchres2); + pucchres3->pucch_ResourceId=4; + pucchres3->startingPRB=40; + pucchres3->intraSlotFrequencyHopping=NULL; + pucchres3->secondHopPRB=NULL; + pucchres3->format.present= NR_PUCCH_Resource__format_PR_format2; + pucchres3->format.choice.format2=calloc(1,sizeof(*pucchres3->format.choice.format2)); + pucchres3->format.choice.format2->nrofPRBs=16; + pucchres3->format.choice.format2->nrofSymbols=1; + pucchres3->format.choice.format2->startingSymbolIndex=12; + ASN_SEQUENCE_ADD(&pucch_Config->resourceToAddModList->list,pucchres3); + pucch_Config->format2=calloc(1,sizeof(*pucch_Config->format2)); + pucch_Config->format2->present=NR_SetupRelease_PUCCH_FormatConfig_PR_setup; + NR_PUCCH_FormatConfig_t *pucchfmt2 = calloc(1,sizeof(*pucchfmt2)); + pucch_Config->format2->choice.setup = pucchfmt2; + pucchfmt2->interslotFrequencyHopping=NULL; + pucchfmt2->additionalDMRS=NULL; + pucchfmt2->maxCodeRate=calloc(1,sizeof(*pucchfmt2->maxCodeRate)); + *pucchfmt2->maxCodeRate=NR_PUCCH_MaxCodeRate_zeroDot15; + pucchfmt2->nrofSlots=NULL; + pucchfmt2->pi2BPSK=NULL; + pucchfmt2->simultaneousHARQ_ACK_CSI=NULL; + pucch_Config->schedulingRequestResourceToAddModList=NULL; + pucch_Config->schedulingRequestResourceToReleaseList=NULL; + pucch_Config->multi_CSI_PUCCH_ResourceList=NULL; + pucch_Config->dl_DataToUL_ACK = calloc(1,sizeof(*pucch_Config->dl_DataToUL_ACK)); + long *delay[8]; + + for (int i=0; i<8; i++) { + delay[i] = calloc(1,sizeof(*delay[i])); + *delay[i] = (i<6) ? (i+2) : 0; + ASN_SEQUENCE_ADD(&pucch_Config->dl_DataToUL_ACK->list,delay[i]); + } + + pucch_Config->spatialRelationInfoToAddModList = calloc(1,sizeof(*pucch_Config->spatialRelationInfoToAddModList)); + NR_PUCCH_SpatialRelationInfo_t *pucchspatial = calloc(1,sizeof(*pucchspatial)); + pucchspatial->pucch_SpatialRelationInfoId = 1; + pucchspatial->servingCellId = NULL; + pucchspatial->referenceSignal.present = NR_PUCCH_SpatialRelationInfo__referenceSignal_PR_csi_RS_Index; + pucchspatial->referenceSignal.choice.csi_RS_Index = 0; + pucchspatial->pucch_PathlossReferenceRS_Id = 0; + pucchspatial->p0_PUCCH_Id = 1; + pucchspatial->closedLoopIndex = NR_PUCCH_SpatialRelationInfo__closedLoopIndex_i0; + ASN_SEQUENCE_ADD(&pucch_Config->spatialRelationInfoToAddModList->list,pucchspatial); + pucch_Config->spatialRelationInfoToReleaseList=NULL; + pucch_Config->pucch_PowerControl=calloc(1,sizeof(*pucch_Config->pucch_PowerControl)); + pucch_Config->pucch_PowerControl->deltaF_PUCCH_f0 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f0)); + *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f0 = 0; + pucch_Config->pucch_PowerControl->deltaF_PUCCH_f1 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f1)); + *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f1 = 0; + pucch_Config->pucch_PowerControl->deltaF_PUCCH_f2 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f2)); + *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f2 = 0; + pucch_Config->pucch_PowerControl->deltaF_PUCCH_f3 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f3)); + *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f3 = 0; + pucch_Config->pucch_PowerControl->deltaF_PUCCH_f4 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f4)); + *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f4 = 0; + pucch_Config->pucch_PowerControl->p0_Set = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->p0_Set)); + NR_P0_PUCCH_t *p00 = calloc(1,sizeof(*p00)); + p00->p0_PUCCH_Id=1; + p00->p0_PUCCH_Value = 0; + ASN_SEQUENCE_ADD(&pucch_Config->pucch_PowerControl->p0_Set->list,p00); + pucch_Config->pucch_PowerControl->pathlossReferenceRSs = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->pathlossReferenceRSs)); + NR_PUCCH_PathlossReferenceRS_t *pucchPLRef=calloc(1,sizeof(*pucchPLRef)); + pucchPLRef->pucch_PathlossReferenceRS_Id=0; + pucchPLRef->referenceSignal.present = NR_PUCCH_PathlossReferenceRS__referenceSignal_PR_csi_RS_Index; + pucchPLRef->referenceSignal.choice.csi_RS_Index=0; + ASN_SEQUENCE_ADD(&pucch_Config->pucch_PowerControl->pathlossReferenceRSs->list,pucchPLRef); + // copy pusch_Config from dedicated initialBWP + ubwp->bwp_Dedicated->pusch_Config = calloc(1,sizeof(*ubwp->bwp_Dedicated->pusch_Config)); + ubwp->bwp_Dedicated->pusch_Config->present = NR_SetupRelease_PUSCH_Config_PR_setup; + ubwp->bwp_Dedicated->pusch_Config->choice.setup = pusch_Config; + ubwp->bwp_Dedicated->configuredGrantConfig = NULL; + ubwp->bwp_Dedicated->srs_Config = calloc(1,sizeof(*ubwp->bwp_Dedicated->srs_Config)); + ubwp->bwp_Dedicated->srs_Config->present = NR_SetupRelease_SRS_Config_PR_setup; + ubwp->bwp_Dedicated->srs_Config->choice.setup = srs_Config; + ubwp->bwp_Dedicated->beamFailureRecoveryConfig = NULL; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list,ubwp); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id = calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id)); + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id = 1; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig = NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->carrierSwitching = NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->supplementaryUplink=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdcch_ServingCellConfig=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig)); + NR_PDSCH_ServingCellConfig_t *pdsch_servingcellconfig = calloc(1,sizeof(*pdsch_servingcellconfig)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->present = NR_SetupRelease_PDSCH_ServingCellConfig_PR_setup; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup = pdsch_servingcellconfig; + pdsch_servingcellconfig->codeBlockGroupTransmission = NULL; + pdsch_servingcellconfig->xOverhead = NULL; + pdsch_servingcellconfig->nrofHARQ_ProcessesForPDSCH = NULL; + pdsch_servingcellconfig->pucch_Cell= NULL; + pdsch_servingcellconfig->ext1=calloc(1,sizeof(*pdsch_servingcellconfig->ext1)); + pdsch_servingcellconfig->ext1->maxMIMO_Layers = calloc(1,sizeof(*pdsch_servingcellconfig->ext1->maxMIMO_Layers)); + *pdsch_servingcellconfig->ext1->maxMIMO_Layers = 2; + pdsch_servingcellconfig->ext1->processingType2Enabled = NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->present = NR_SetupRelease_CSI_MeasConfig_PR_setup; + NR_CSI_MeasConfig_t *csi_MeasConfig = calloc(1,sizeof(*csi_MeasConfig)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup = csi_MeasConfig; + csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList = calloc(1,sizeof(*csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList)); + NR_NZP_CSI_RS_Resource_t *nzpres0 = calloc(1,sizeof(*nzpres0)); + nzpres0->nzp_CSI_RS_ResourceId=0; + nzpres0->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_other; + nzpres0->resourceMapping.frequencyDomainAllocation.choice.other.buf = calloc(1,1); + nzpres0->resourceMapping.frequencyDomainAllocation.choice.other.size = 1; + nzpres0->resourceMapping.frequencyDomainAllocation.choice.other.bits_unused = 2; + nzpres0->resourceMapping.frequencyDomainAllocation.choice.other.buf[0]=1<<2; + nzpres0->resourceMapping.nrofPorts = (n_physical_antenna_ports==1)? NR_CSI_RS_ResourceMapping__nrofPorts_p1 : NR_CSI_RS_ResourceMapping__nrofPorts_p2; + nzpres0->resourceMapping.firstOFDMSymbolInTimeDomain=7; + nzpres0->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres0->resourceMapping.cdm_Type = (n_physical_antenna_ports==1)? NR_CSI_RS_ResourceMapping__cdm_Type_noCDM : NR_CSI_RS_ResourceMapping__cdm_Type_fd_CDM2; + nzpres0->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_one; + nzpres0->resourceMapping.density.choice.one=(NULL_t)0; + nzpres0->resourceMapping.freqBand.startingRB=0; + nzpres0->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres0->powerControlOffset=13; + nzpres0->powerControlOffsetSS=NULL; + nzpres0->scramblingID=40; + nzpres0->periodicityAndOffset = calloc(1,sizeof(*nzpres0->periodicityAndOffset)); + nzpres0->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots320; + nzpres0->periodicityAndOffset->choice.slots320 = 2; + nzpres0->qcl_InfoPeriodicCSI_RS=NULL; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres0); + + if (n_physical_antenna_ports > 1) { + NR_NZP_CSI_RS_Resource_t *nzpres2 = calloc(1,sizeof(*nzpres2)); + nzpres2->nzp_CSI_RS_ResourceId=2; + nzpres2->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres2->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres2->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres2->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres2->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=1; + nzpres2->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres2->resourceMapping.firstOFDMSymbolInTimeDomain=4; + nzpres2->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres2->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres2->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres2->resourceMapping.density.choice.three=(NULL_t)0; + nzpres2->resourceMapping.freqBand.startingRB=0; + nzpres2->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres2->powerControlOffset=0; + nzpres2->powerControlOffsetSS=calloc(1,sizeof(*nzpres2->powerControlOffsetSS)); + *nzpres2->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres2->scramblingID=40; + nzpres2->periodicityAndOffset = calloc(1,sizeof(*nzpres2->periodicityAndOffset)); + nzpres2->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres2->periodicityAndOffset->choice.slots160 = 25; + nzpres2->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres2->qcl_InfoPeriodicCSI_RS)); + *nzpres2->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres2); + NR_NZP_CSI_RS_Resource_t *nzpres3 = calloc(1,sizeof(*nzpres3)); + nzpres3->nzp_CSI_RS_ResourceId=3; + nzpres3->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres3->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres3->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres3->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres3->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=1; + nzpres3->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres3->resourceMapping.firstOFDMSymbolInTimeDomain=8; + nzpres3->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres3->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres3->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres3->resourceMapping.density.choice.three=(NULL_t)0; + nzpres3->resourceMapping.freqBand.startingRB=0; + nzpres3->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres3->powerControlOffset=0; + nzpres3->powerControlOffsetSS=calloc(1,sizeof(*nzpres3->powerControlOffsetSS)); + *nzpres3->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres3->scramblingID=40; + nzpres3->periodicityAndOffset = calloc(1,sizeof(*nzpres3->periodicityAndOffset)); + nzpres3->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres3->periodicityAndOffset->choice.slots160 = 25; + nzpres3->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres3->qcl_InfoPeriodicCSI_RS)); + *nzpres3->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres3); + } + + if (n_physical_antenna_ports > 3) { + NR_NZP_CSI_RS_Resource_t *nzpres4 = calloc(1,sizeof(*nzpres4)); + nzpres4->nzp_CSI_RS_ResourceId=4; + nzpres4->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres4->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres4->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres4->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres4->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=1; + nzpres4->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres4->resourceMapping.firstOFDMSymbolInTimeDomain=4; + nzpres4->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres4->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres4->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres4->resourceMapping.density.choice.three=(NULL_t)0; + nzpres4->resourceMapping.freqBand.startingRB=0; + nzpres4->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres4->powerControlOffset=0; + nzpres4->powerControlOffsetSS=calloc(1,sizeof(*nzpres4->powerControlOffsetSS)); + *nzpres4->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres4->scramblingID=40; + nzpres4->periodicityAndOffset = calloc(1,sizeof(*nzpres4->periodicityAndOffset)); + nzpres4->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres4->periodicityAndOffset->choice.slots160 = 26; + nzpres4->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres4->qcl_InfoPeriodicCSI_RS)); + *nzpres4->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres4); + NR_NZP_CSI_RS_Resource_t *nzpres5 = calloc(1,sizeof(*nzpres5)); + nzpres5->nzp_CSI_RS_ResourceId=5; + nzpres5->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres5->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres5->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres5->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres5->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=1; + nzpres5->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres5->resourceMapping.firstOFDMSymbolInTimeDomain=8; + nzpres5->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres5->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres5->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres5->resourceMapping.density.choice.three=(NULL_t)0; + nzpres5->resourceMapping.freqBand.startingRB=0; + nzpres5->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres5->powerControlOffset=0; + nzpres5->powerControlOffsetSS=calloc(1,sizeof(*nzpres5->powerControlOffsetSS)); + *nzpres5->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres5->scramblingID=40; + nzpres5->periodicityAndOffset = calloc(1,sizeof(*nzpres5->periodicityAndOffset)); + nzpres5->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres5->periodicityAndOffset->choice.slots160 = 26; + nzpres5->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres5->qcl_InfoPeriodicCSI_RS)); + *nzpres5->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres5); + } + + if (n_physical_antenna_ports > 7) { + NR_NZP_CSI_RS_Resource_t *nzpres6 = calloc(1,sizeof(*nzpres6)); + nzpres6->nzp_CSI_RS_ResourceId=6; + nzpres6->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres6->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres6->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres6->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres6->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=4; + nzpres6->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres6->resourceMapping.firstOFDMSymbolInTimeDomain=4; + nzpres6->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres6->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres6->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres6->resourceMapping.density.choice.three=(NULL_t)0; + nzpres6->resourceMapping.freqBand.startingRB=0; + nzpres6->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres6->powerControlOffset=0; + nzpres6->powerControlOffsetSS=calloc(1,sizeof(*nzpres6->powerControlOffsetSS)); + *nzpres6->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres6->scramblingID=40; + nzpres6->periodicityAndOffset = calloc(1,sizeof(*nzpres6->periodicityAndOffset)); + nzpres6->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres6->periodicityAndOffset->choice.slots160 = 25; + nzpres6->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres6->qcl_InfoPeriodicCSI_RS)); + *nzpres6->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres6); + NR_NZP_CSI_RS_Resource_t *nzpres7 = calloc(1,sizeof(*nzpres7)); + nzpres7->nzp_CSI_RS_ResourceId=7; + nzpres7->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres7->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres7->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres7->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres7->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=4; + nzpres7->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres7->resourceMapping.firstOFDMSymbolInTimeDomain=8; + nzpres7->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres7->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres7->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres7->resourceMapping.density.choice.three=(NULL_t)0; + nzpres7->resourceMapping.freqBand.startingRB=0; + nzpres7->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres7->powerControlOffset=0; + nzpres7->powerControlOffsetSS=calloc(1,sizeof(*nzpres7->powerControlOffsetSS)); + *nzpres7->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres7->scramblingID=40; + nzpres7->periodicityAndOffset = calloc(1,sizeof(*nzpres7->periodicityAndOffset)); + nzpres7->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres7->periodicityAndOffset->choice.slots160 = 25; + nzpres7->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres7->qcl_InfoPeriodicCSI_RS)); + *nzpres7->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres7); + NR_NZP_CSI_RS_Resource_t *nzpres8 = calloc(1,sizeof(*nzpres8)); + nzpres8->nzp_CSI_RS_ResourceId=8; + nzpres8->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres8->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres8->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres8->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres8->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=4; + nzpres8->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres8->resourceMapping.firstOFDMSymbolInTimeDomain=4; + nzpres8->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres8->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres8->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres8->resourceMapping.density.choice.three=(NULL_t)0; + nzpres8->resourceMapping.freqBand.startingRB=0; + nzpres8->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres8->powerControlOffset=0; + nzpres8->powerControlOffsetSS=calloc(1,sizeof(*nzpres8->powerControlOffsetSS)); + *nzpres8->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres8->scramblingID=40; + nzpres8->periodicityAndOffset = calloc(1,sizeof(*nzpres8->periodicityAndOffset)); + nzpres8->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres8->periodicityAndOffset->choice.slots160 = 26; + nzpres8->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres8->qcl_InfoPeriodicCSI_RS)); + *nzpres8->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres8); + NR_NZP_CSI_RS_Resource_t *nzpres9 = calloc(1,sizeof(*nzpres9)); + nzpres9->nzp_CSI_RS_ResourceId=9; + nzpres9->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres9->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres9->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres9->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres9->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=4; + nzpres9->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres9->resourceMapping.firstOFDMSymbolInTimeDomain=8; + nzpres9->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres9->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres9->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres9->resourceMapping.density.choice.three=(NULL_t)0; + nzpres9->resourceMapping.freqBand.startingRB=0; + nzpres9->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres9->powerControlOffset=0; + nzpres9->powerControlOffsetSS=calloc(1,sizeof(*nzpres9->powerControlOffsetSS)); + *nzpres9->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres9->scramblingID=40; + nzpres9->periodicityAndOffset = calloc(1,sizeof(*nzpres9->periodicityAndOffset)); + nzpres9->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres9->periodicityAndOffset->choice.slots160 = 26; + nzpres9->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres9->qcl_InfoPeriodicCSI_RS)); + *nzpres9->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres9); + } + + if (n_physical_antenna_ports > 15) { + NR_NZP_CSI_RS_Resource_t *nzpres10 = calloc(1,sizeof(*nzpres10)); + nzpres10->nzp_CSI_RS_ResourceId=10; + nzpres10->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres10->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres10->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres10->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres10->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=2; + nzpres10->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres10->resourceMapping.firstOFDMSymbolInTimeDomain=4; + nzpres10->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres10->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres10->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres10->resourceMapping.density.choice.three=(NULL_t)0; + nzpres10->resourceMapping.freqBand.startingRB=0; + nzpres10->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres10->powerControlOffset=0; + nzpres10->powerControlOffsetSS=calloc(1,sizeof(*nzpres10->powerControlOffsetSS)); + *nzpres10->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres10->scramblingID=40; + nzpres10->periodicityAndOffset = calloc(1,sizeof(*nzpres10->periodicityAndOffset)); + nzpres10->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres10->periodicityAndOffset->choice.slots160 = 25; + nzpres10->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres10->qcl_InfoPeriodicCSI_RS)); + *nzpres10->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres10); + NR_NZP_CSI_RS_Resource_t *nzpres11 = calloc(1,sizeof(*nzpres11)); + nzpres11->nzp_CSI_RS_ResourceId=11; + nzpres11->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres11->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres11->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres11->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres11->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=2; + nzpres11->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres11->resourceMapping.firstOFDMSymbolInTimeDomain=8; + nzpres11->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres11->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres11->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres11->resourceMapping.density.choice.three=(NULL_t)0; + nzpres11->resourceMapping.freqBand.startingRB=0; + nzpres11->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres11->powerControlOffset=0; + nzpres11->powerControlOffsetSS=calloc(1,sizeof(*nzpres11->powerControlOffsetSS)); + *nzpres11->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres11->scramblingID=40; + nzpres11->periodicityAndOffset = calloc(1,sizeof(*nzpres11->periodicityAndOffset)); + nzpres11->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres11->periodicityAndOffset->choice.slots160 = 25; + nzpres11->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres11->qcl_InfoPeriodicCSI_RS)); + *nzpres11->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres11); + NR_NZP_CSI_RS_Resource_t *nzpres12 = calloc(1,sizeof(*nzpres12)); + nzpres12->nzp_CSI_RS_ResourceId=12; + nzpres12->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres12->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres12->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres12->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres12->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=2; + nzpres12->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres12->resourceMapping.firstOFDMSymbolInTimeDomain=4; + nzpres12->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres12->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres12->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres12->resourceMapping.density.choice.three=(NULL_t)0; + nzpres12->resourceMapping.freqBand.startingRB=0; + nzpres12->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres12->powerControlOffset=0; + nzpres12->powerControlOffsetSS=calloc(1,sizeof(*nzpres12->powerControlOffsetSS)); + *nzpres12->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres12->scramblingID=40; + nzpres12->periodicityAndOffset = calloc(1,sizeof(*nzpres12->periodicityAndOffset)); + nzpres12->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres12->periodicityAndOffset->choice.slots160 = 26; + nzpres12->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres12->qcl_InfoPeriodicCSI_RS)); + *nzpres12->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres12); + NR_NZP_CSI_RS_Resource_t *nzpres13 = calloc(1,sizeof(*nzpres13)); + nzpres13->nzp_CSI_RS_ResourceId=13; + nzpres13->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres13->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres13->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres13->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres13->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=2; + nzpres13->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres13->resourceMapping.firstOFDMSymbolInTimeDomain=8; + nzpres13->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres13->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres13->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres13->resourceMapping.density.choice.three=(NULL_t)0; + nzpres13->resourceMapping.freqBand.startingRB=0; + nzpres13->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres13->powerControlOffset=0; + nzpres13->powerControlOffsetSS=calloc(1,sizeof(*nzpres13->powerControlOffsetSS)); + *nzpres13->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres13->scramblingID=40; + nzpres13->periodicityAndOffset = calloc(1,sizeof(*nzpres13->periodicityAndOffset)); + nzpres13->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres13->periodicityAndOffset->choice.slots160 = 26; + nzpres13->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres13->qcl_InfoPeriodicCSI_RS)); + *nzpres13->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres13); + NR_NZP_CSI_RS_Resource_t *nzpres14 = calloc(1,sizeof(*nzpres14)); + nzpres14->nzp_CSI_RS_ResourceId=14; + nzpres14->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres14->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres14->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres14->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres14->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=8; + nzpres14->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres14->resourceMapping.firstOFDMSymbolInTimeDomain=4; + nzpres14->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres14->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres14->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres14->resourceMapping.density.choice.three=(NULL_t)0; + nzpres14->resourceMapping.freqBand.startingRB=0; + nzpres14->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres14->powerControlOffset=0; + nzpres14->powerControlOffsetSS=calloc(1,sizeof(*nzpres14->powerControlOffsetSS)); + *nzpres14->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres14->scramblingID=40; + nzpres14->periodicityAndOffset = calloc(1,sizeof(*nzpres14->periodicityAndOffset)); + nzpres14->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres14->periodicityAndOffset->choice.slots160 = 25; + nzpres14->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres14->qcl_InfoPeriodicCSI_RS)); + *nzpres14->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres14); + NR_NZP_CSI_RS_Resource_t *nzpres15 = calloc(1,sizeof(*nzpres15)); + nzpres15->nzp_CSI_RS_ResourceId=15; + nzpres15->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres15->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres15->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres15->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres15->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=8; + nzpres15->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres15->resourceMapping.firstOFDMSymbolInTimeDomain=8; + nzpres15->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres15->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres15->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres15->resourceMapping.density.choice.three=(NULL_t)0; + nzpres15->resourceMapping.freqBand.startingRB=0; + nzpres15->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres15->powerControlOffset=0; + nzpres15->powerControlOffsetSS=calloc(1,sizeof(*nzpres15->powerControlOffsetSS)); + *nzpres15->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres15->scramblingID=40; + nzpres15->periodicityAndOffset = calloc(1,sizeof(*nzpres15->periodicityAndOffset)); + nzpres15->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres15->periodicityAndOffset->choice.slots160 = 25; + nzpres15->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres15->qcl_InfoPeriodicCSI_RS)); + *nzpres15->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres15); + NR_NZP_CSI_RS_Resource_t *nzpres16 = calloc(1,sizeof(*nzpres16)); + nzpres16->nzp_CSI_RS_ResourceId=16; + nzpres16->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres16->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres16->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres16->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres16->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=8; + nzpres16->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres16->resourceMapping.firstOFDMSymbolInTimeDomain=5; + nzpres16->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres16->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres16->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres16->resourceMapping.density.choice.three=(NULL_t)0; + nzpres16->resourceMapping.freqBand.startingRB=0; + nzpres16->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres16->powerControlOffset=0; + nzpres16->powerControlOffsetSS=calloc(1,sizeof(*nzpres16->powerControlOffsetSS)); + *nzpres16->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres16->scramblingID=40; + nzpres16->periodicityAndOffset = calloc(1,sizeof(*nzpres16->periodicityAndOffset)); + nzpres16->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres16->periodicityAndOffset->choice.slots160 = 26; + nzpres16->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres16->qcl_InfoPeriodicCSI_RS)); + *nzpres16->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres16); + NR_NZP_CSI_RS_Resource_t *nzpres17 = calloc(1,sizeof(*nzpres17)); + nzpres17->nzp_CSI_RS_ResourceId=9; + nzpres17->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres17->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres17->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres17->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres17->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=8; + nzpres17->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres17->resourceMapping.firstOFDMSymbolInTimeDomain=9; + nzpres17->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres17->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres17->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres17->resourceMapping.density.choice.three=(NULL_t)0; + nzpres17->resourceMapping.freqBand.startingRB=0; + nzpres17->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres17->powerControlOffset=0; + nzpres17->powerControlOffsetSS=calloc(1,sizeof(*nzpres17->powerControlOffsetSS)); + *nzpres17->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres17->scramblingID=40; + nzpres17->periodicityAndOffset = calloc(1,sizeof(*nzpres17->periodicityAndOffset)); + nzpres17->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres17->periodicityAndOffset->choice.slots160 = 26; + nzpres17->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres17->qcl_InfoPeriodicCSI_RS)); + *nzpres17->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres17); + } + + if (n_physical_antenna_ports > 16) AssertFatal(1==0,"Fill in for more than 16 antenna elements\n"); + + csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList = calloc(1,sizeof(*csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList)); + csi_MeasConfig->nzp_CSI_RS_ResourceSetToReleaseList = NULL; + NR_NZP_CSI_RS_ResourceSet_t *nzpresset0=calloc(1,sizeof(*nzpresset0)); + nzpresset0->nzp_CSI_ResourceSetId=0; + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset00=calloc(1,sizeof(*nzpresset00)); + *nzpresset00=0; + ASN_SEQUENCE_ADD(&nzpresset0->nzp_CSI_RS_Resources.list,nzpresset00); + nzpresset0->repetition=NULL; + nzpresset0->aperiodicTriggeringOffset=NULL; + nzpresset0->trs_Info=NULL; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset0); + + if (n_physical_antenna_ports > 1) { + NR_NZP_CSI_RS_ResourceSet_t *nzpresset3=calloc(1,sizeof(*nzpresset3)); + nzpresset3->nzp_CSI_ResourceSetId=3; + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset30=calloc(1,sizeof(*nzpresset30)); + *nzpresset30=2; + ASN_SEQUENCE_ADD(&nzpresset3->nzp_CSI_RS_Resources.list,nzpresset30); + + if (n_physical_antenna_ports > 3) { + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset31=calloc(1,sizeof(*nzpresset31)); + *nzpresset31=3; + ASN_SEQUENCE_ADD(&nzpresset3->nzp_CSI_RS_Resources.list,nzpresset31); + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset32=calloc(1,sizeof(*nzpresset32)); + *nzpresset32=4; + ASN_SEQUENCE_ADD(&nzpresset3->nzp_CSI_RS_Resources.list,nzpresset32); + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset33=calloc(1,sizeof(*nzpresset33)); + *nzpresset33=5; + ASN_SEQUENCE_ADD(&nzpresset3->nzp_CSI_RS_Resources.list,nzpresset33); + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset3); + } + + nzpresset3->repetition=calloc(1,sizeof(*nzpresset3->repetition)); + *nzpresset3->repetition=NR_NZP_CSI_RS_ResourceSet__repetition_off; + nzpresset3->aperiodicTriggeringOffset=NULL; + nzpresset3->trs_Info=calloc(1,sizeof(*nzpresset3->trs_Info)); + *nzpresset3->trs_Info=NR_NZP_CSI_RS_ResourceSet__trs_Info_true; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset3); + } + + if (n_physical_antenna_ports > 7) { + NR_NZP_CSI_RS_ResourceSet_t *nzpresset4=calloc(1,sizeof(*nzpresset4)); + nzpresset4->nzp_CSI_ResourceSetId=4; + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset40=calloc(1,sizeof(*nzpresset40)); + *nzpresset40=6; + ASN_SEQUENCE_ADD(&nzpresset4->nzp_CSI_RS_Resources.list,nzpresset40); + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset41=calloc(1,sizeof(*nzpresset41)); + *nzpresset41=7; + ASN_SEQUENCE_ADD(&nzpresset4->nzp_CSI_RS_Resources.list,nzpresset41); + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset42=calloc(1,sizeof(*nzpresset42)); + *nzpresset42=8; + ASN_SEQUENCE_ADD(&nzpresset4->nzp_CSI_RS_Resources.list,nzpresset42); + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset43=calloc(1,sizeof(*nzpresset43)); + *nzpresset43=9; + ASN_SEQUENCE_ADD(&nzpresset4->nzp_CSI_RS_Resources.list,nzpresset43); + nzpresset4->repetition=calloc(1,sizeof(*nzpresset4->repetition)); + *nzpresset4->repetition=NR_NZP_CSI_RS_ResourceSet__repetition_off; + nzpresset4->aperiodicTriggeringOffset=NULL; + nzpresset4->trs_Info=calloc(1,sizeof(*nzpresset4->trs_Info)); + *nzpresset4->trs_Info=NR_NZP_CSI_RS_ResourceSet__trs_Info_true; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset4); + } + + if (n_physical_antenna_ports > 15) { + NR_NZP_CSI_RS_ResourceSet_t *nzpresset5=calloc(1,sizeof(*nzpresset5)); + nzpresset5->nzp_CSI_ResourceSetId=5; + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset50=calloc(1,sizeof(*nzpresset50)); + *nzpresset50=10; + ASN_SEQUENCE_ADD(&nzpresset5->nzp_CSI_RS_Resources.list,nzpresset50); + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset51=calloc(1,sizeof(*nzpresset51)); + *nzpresset51=11; + ASN_SEQUENCE_ADD(&nzpresset5->nzp_CSI_RS_Resources.list,nzpresset51); + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset52=calloc(1,sizeof(*nzpresset52)); + *nzpresset52=12; + ASN_SEQUENCE_ADD(&nzpresset5->nzp_CSI_RS_Resources.list,nzpresset52); + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset53=calloc(1,sizeof(*nzpresset53)); + *nzpresset53=13; + ASN_SEQUENCE_ADD(&nzpresset5->nzp_CSI_RS_Resources.list,nzpresset53); + nzpresset5->repetition=calloc(1,sizeof(*nzpresset5->repetition)); + *nzpresset5->repetition=NR_NZP_CSI_RS_ResourceSet__repetition_off; + nzpresset5->aperiodicTriggeringOffset=NULL; + nzpresset5->trs_Info=calloc(1,sizeof(*nzpresset5->trs_Info)); + *nzpresset5->trs_Info=NR_NZP_CSI_RS_ResourceSet__trs_Info_true; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset5); + } + + csi_MeasConfig->csi_IM_ResourceToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_IM_ResourceToAddModList)); + csi_MeasConfig->csi_IM_ResourceToReleaseList = NULL; + NR_CSI_IM_Resource_t *imres0 = calloc(1,sizeof(*imres0)); + imres0->csi_IM_ResourceId=0; + imres0->csi_IM_ResourceElementPattern=calloc(1,sizeof(*imres0->csi_IM_ResourceElementPattern)); + imres0->csi_IM_ResourceElementPattern->present = NR_CSI_IM_Resource__csi_IM_ResourceElementPattern_PR_pattern1 ; + imres0->csi_IM_ResourceElementPattern->choice.pattern1=calloc(1,sizeof(*imres0->csi_IM_ResourceElementPattern->choice.pattern1)); + imres0->csi_IM_ResourceElementPattern->choice.pattern1->subcarrierLocation_p1 = NR_CSI_IM_Resource__csi_IM_ResourceElementPattern__pattern1__subcarrierLocation_p1_s4; + imres0->csi_IM_ResourceElementPattern->choice.pattern1->symbolLocation_p1=7; + imres0->freqBand=calloc(1,sizeof(*imres0->freqBand)); + imres0->freqBand->startingRB=0; + imres0->freqBand->nrofRBs=276; + imres0->periodicityAndOffset=calloc(1,sizeof(*imres0->periodicityAndOffset)); + imres0->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots320; + imres0->periodicityAndOffset->choice.slots320 = 2; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_IM_ResourceToAddModList->list,imres0); + csi_MeasConfig->csi_IM_ResourceSetToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_IM_ResourceSetToAddModList)); + csi_MeasConfig->csi_IM_ResourceSetToReleaseList = NULL; + NR_CSI_IM_ResourceSet_t *imresset0 = calloc(1,sizeof(*imresset0)); + imresset0->csi_IM_ResourceSetId=0; + NR_CSI_IM_ResourceId_t *imresset00=calloc(1,sizeof(*imresset00)); + *imresset00=0; + ASN_SEQUENCE_ADD(&imresset0->csi_IM_Resources.list,imresset00); + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_IM_ResourceSetToAddModList->list,imresset0); + csi_MeasConfig->csi_SSB_ResourceSetToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_SSB_ResourceSetToAddModList)); + csi_MeasConfig->csi_SSB_ResourceSetToReleaseList = NULL; + NR_CSI_SSB_ResourceSet_t *ssbresset0 = calloc(1,sizeof(*ssbresset0)); + ssbresset0->csi_SSB_ResourceSetId=0; + NR_SSB_Index_t *ssbresset00=calloc(1,sizeof(*ssbresset00)); + *ssbresset00=0; + ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset00); + + if (n_physical_antenna_ports > 1) { + NR_SSB_Index_t *ssbresset01=calloc(1,sizeof(*ssbresset01)); + *ssbresset01=1; + ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset01); + } + + if (n_physical_antenna_ports > 3) { + NR_SSB_Index_t *ssbresset02=calloc(1,sizeof(*ssbresset02)); + *ssbresset02=2; + ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset02); + NR_SSB_Index_t *ssbresset03=calloc(1,sizeof(*ssbresset03)); + *ssbresset03=3; + ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset03); + } + + if (n_physical_antenna_ports > 7) { + NR_SSB_Index_t *ssbresset04=calloc(1,sizeof(*ssbresset04)); + *ssbresset04=4; + ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset04); + NR_SSB_Index_t *ssbresset05=calloc(1,sizeof(*ssbresset05)); + *ssbresset05=5; + ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset05); + NR_SSB_Index_t *ssbresset06=calloc(1,sizeof(*ssbresset06)); + *ssbresset06=6; + ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset06); + NR_SSB_Index_t *ssbresset07=calloc(1,sizeof(*ssbresset07)); + *ssbresset07=7; + ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset07); + } + + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_SSB_ResourceSetToAddModList->list,ssbresset0); + csi_MeasConfig->csi_ResourceConfigToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_ResourceConfigToAddModList)); + csi_MeasConfig->csi_ResourceConfigToReleaseList = NULL; + NR_CSI_ResourceConfig_t *csires0 = calloc(1,sizeof(*csires0)); + csires0->csi_ResourceConfigId=0; + csires0->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires00 = calloc(1,sizeof(*csires00)); + *csires00 = 0; + ASN_SEQUENCE_ADD(&csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires00); + csires0->bwp_Id = 1; + csires0->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires0); + NR_CSI_ResourceConfig_t *csires11 = calloc(1,sizeof(*csires11)); + csires11->csi_ResourceConfigId=11; + csires11->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_csi_IM_ResourceSetList; + csires11->csi_RS_ResourceSetList.choice.csi_IM_ResourceSetList = calloc(1,sizeof(*csires11->csi_RS_ResourceSetList.choice.csi_IM_ResourceSetList)); + NR_NZP_CSI_RS_ResourceSetId_t *csires110 = calloc(1,sizeof(*csires110)); + *csires110 = 0; + ASN_SEQUENCE_ADD(&csires11->csi_RS_ResourceSetList.choice.csi_IM_ResourceSetList->list,csires110); + csires11->bwp_Id = 1; + csires11->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires11); + NR_CSI_ResourceConfig_t *csires10 = calloc(1,sizeof(*csires10)); + csires10->csi_ResourceConfigId=10; + csires10->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires100 = calloc(1,sizeof(*csires100)); + *csires100 = 0; + ASN_SEQUENCE_ADD(&csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires100); + csires10->bwp_Id = 1; + csires10->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires10); + NR_CSI_ResourceConfig_t *csires2 = calloc(1,sizeof(*csires2)); + csires2->csi_ResourceConfigId=2; + csires2->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires20 = calloc(1,sizeof(*csires20)); + *csires20 = 0; + ASN_SEQUENCE_ADD(&csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires20); + csires2->bwp_Id = 1; + csires2->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires2); + NR_CSI_ResourceConfig_t *csires3 = calloc(1,sizeof(*csires3)); + csires3->csi_ResourceConfigId=3; + csires3->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires30 = calloc(1,sizeof(*csires30)); + *csires30 = 0; + ASN_SEQUENCE_ADD(&csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires30); + csires3->bwp_Id = 1; + csires3->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires3); + NR_CSI_ResourceConfig_t *csires4 = calloc(1,sizeof(*csires4)); + csires4->csi_ResourceConfigId=4; + csires4->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires40 = calloc(1,sizeof(*csires40)); + *csires40 = 0; + ASN_SEQUENCE_ADD(&csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires40); + csires4->bwp_Id = 1; + csires4->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires4); + NR_CSI_ResourceConfig_t *csires5 = calloc(1,sizeof(*csires5)); + csires5->csi_ResourceConfigId=5; + csires5->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires50 = calloc(1,sizeof(*csires50)); + *csires50 = 0; + ASN_SEQUENCE_ADD(&csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires50); + csires5->bwp_Id = 1; + csires5->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires5); + NR_CSI_ResourceConfig_t *csires6 = calloc(1,sizeof(*csires6)); + csires6->csi_ResourceConfigId=6; + csires6->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires60 = calloc(1,sizeof(*csires60)); + *csires60 = 0; + ASN_SEQUENCE_ADD(&csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires60); + csires6->bwp_Id = 1; + csires6->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires6); + NR_CSI_ResourceConfig_t *csires7 = calloc(1,sizeof(*csires7)); + csires7->csi_ResourceConfigId=7; + csires7->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires70 = calloc(1,sizeof(*csires70)); + *csires70 = 0; + ASN_SEQUENCE_ADD(&csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires70); + csires7->bwp_Id = 1; + csires7->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires7); + NR_CSI_ResourceConfig_t *csires8 = calloc(1,sizeof(*csires8)); + csires8->csi_ResourceConfigId=8; + csires8->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires80 = calloc(1,sizeof(*csires80)); + *csires80 = 0; + ASN_SEQUENCE_ADD(&csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires80); + csires8->bwp_Id = 1; + csires8->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires8); + NR_CSI_ResourceConfig_t *csires9 = calloc(1,sizeof(*csires9)); + csires9->csi_ResourceConfigId=9; + csires9->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires90 = calloc(1,sizeof(*csires90)); + *csires90 = 0; + ASN_SEQUENCE_ADD(&csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires90); + csires9->bwp_Id = 1; + csires9->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires9); + csi_MeasConfig->csi_ReportConfigToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_ReportConfigToAddModList)); + csi_MeasConfig->csi_ReportConfigToReleaseList = NULL; + NR_CSI_ReportConfig_t *csirep0 = calloc(1,sizeof(*csirep0)); + csirep0->reportConfigId=0; + csirep0->carrier=NULL; + csirep0->resourcesForChannelMeasurement=0; + csirep0->csi_IM_ResourcesForInterference=calloc(1,sizeof(*csirep0->csi_IM_ResourcesForInterference)); + *csirep0->csi_IM_ResourcesForInterference=11; + csirep0->nzp_CSI_RS_ResourcesForInterference=NULL; + csirep0->reportConfigType.present = NR_CSI_ReportConfig__reportConfigType_PR_periodic; + csirep0->reportConfigType.choice.periodic = calloc(1,sizeof(*csirep0->reportConfigType.choice.periodic)); + csirep0->reportConfigType.choice.periodic->reportSlotConfig.present=NR_CSI_ReportPeriodicityAndOffset_PR_slots320; + csirep0->reportConfigType.choice.periodic->reportSlotConfig.choice.slots320 = 9; + NR_PUCCH_CSI_Resource_t *pucchcsires0 = calloc(1,sizeof(*pucchcsires0)); + pucchcsires0->uplinkBandwidthPartId=1; + pucchcsires0->pucch_Resource=11; + ASN_SEQUENCE_ADD(&csirep0->reportConfigType.choice.periodic->pucch_CSI_ResourceList.list,pucchcsires0); + csirep0->reportQuantity.present = NR_CSI_ReportConfig__reportQuantity_PR_cri_RI_LI_PMI_CQI; + csirep0->reportQuantity.choice.cri_RI_PMI_CQI = (NULL_t)0; + csirep0->reportFreqConfiguration = calloc(1,sizeof(*csirep0->reportFreqConfiguration)); + csirep0->reportFreqConfiguration->cqi_FormatIndicator=NR_CSI_ReportConfig__reportFreqConfiguration__cqi_FormatIndicator_widebandCQI; + csirep0->reportFreqConfiguration->pmi_FormatIndicator=NR_CSI_ReportConfig__reportFreqConfiguration__pmi_FormatIndicator_widebandPMI; + csirep0->reportFreqConfiguration->csi_ReportingBand=calloc(1,sizeof(*csirep0->reportFreqConfiguration->csi_ReportingBand)); + AssertFatal(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id>0,"firstActiveDownlinkBWP_Id %d\n", + (int)*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id); + int NPRB = NRRIV2BW(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id + -1]->bwp_Common->genericParameters.locationAndBandwidth,275); + int sbsize = get_subband_size(NPRB,0); + int numsb = NPRB/sbsize; + + if (NPRB%sbsize == 0) numsb++; + + csirep0->reportFreqConfiguration->csi_ReportingBand->present= NR_CSI_ReportConfig__reportFreqConfiguration__csi_ReportingBand_PR_NOTHING+(numsb-2); + csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.size=numsb/8; + + if ((numsb&7) > 0) csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.size++; + + csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.bits_unused = (8-(numsb&7))&7; + csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.buf=malloc(csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.size); + + for (int i=0; ireportFreqConfiguration->csi_ReportingBand->choice.subbands18.size; i++) + csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.buf[i]=0xff; + + csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.buf[csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.size-1]&=~(( + 1<reportFreqConfiguration->csi_ReportingBand->choice.subbands18.bits_unused)-1); + csirep0->timeRestrictionForChannelMeasurements= NR_CSI_ReportConfig__timeRestrictionForChannelMeasurements_configured; + csirep0->timeRestrictionForInterferenceMeasurements=NR_CSI_ReportConfig__timeRestrictionForInterferenceMeasurements_configured; + csirep0->codebookConfig=calloc(1,sizeof(*csirep0->codebookConfig)); + csirep0->codebookConfig->codebookType.present = NR_CodebookConfig__codebookType_PR_type1; + csirep0->codebookConfig->codebookType.choice.type1 = calloc(1,sizeof(*csirep0->codebookConfig->codebookType.choice.type1)); + csirep0->codebookConfig->codebookType.choice.type1->subType.present = NR_CodebookConfig__codebookType__type1__subType_PR_typeI_SinglePanel; + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel=calloc(1,sizeof(*csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel)); + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.present= + NR_CodebookConfig__codebookType__type1__subType__typeI_SinglePanel__nrOfAntennaPorts_PR_two; + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two= + calloc(1,sizeof(*csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two)); + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.size=1; + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.bits_unused=2; + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.buf=malloc(1); + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.buf[0]=0xfc; + //'111111'B + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.size=1; + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.bits_unused=0; + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.buf=malloc(1); + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.buf[0]=0xc0; //'00000011'B + csirep0->codebookConfig->codebookType.choice.type1->codebookMode=1; + csirep0->dummy = NULL; + csirep0->groupBasedBeamReporting.present = NR_CSI_ReportConfig__groupBasedBeamReporting_PR_disabled; + csirep0->groupBasedBeamReporting.choice.disabled=calloc(1,sizeof(*csirep0->groupBasedBeamReporting.choice.disabled)); + csirep0->groupBasedBeamReporting.choice.disabled->nrofReportedRS = NULL; + csirep0->cqi_Table = calloc(1,sizeof(*csirep0->cqi_Table)); + *csirep0->cqi_Table = NR_CSI_ReportConfig__cqi_Table_table1; + csirep0->subbandSize = NR_CSI_ReportConfig__subbandSize_value1; + csirep0->non_PMI_PortIndication = NULL; + csirep0->ext1 = NULL; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ReportConfigToAddModList->list,csirep0); + NR_CSI_ReportConfig_t *csirep1 = calloc(1,sizeof(*csirep1)); + csirep1->reportConfigId=2; + csirep1->carrier=NULL; + csirep1->resourcesForChannelMeasurement=initial_csi_index; + csirep1->csi_IM_ResourcesForInterference=NULL; + csirep1->nzp_CSI_RS_ResourcesForInterference=NULL; + csirep1->reportConfigType.present = NR_CSI_ReportConfig__reportConfigType_PR_periodic; + csirep1->reportConfigType.choice.periodic = calloc(1,sizeof(*csirep1->reportConfigType.choice.periodic)); + csirep1->reportConfigType.choice.periodic->reportSlotConfig.present=NR_CSI_ReportPeriodicityAndOffset_PR_slots320; + csirep1->reportConfigType.choice.periodic->reportSlotConfig.choice.slots320 = 49; + NR_PUCCH_CSI_Resource_t *pucchcsires1 = calloc(1,sizeof(*pucchcsires1)); + pucchcsires1->uplinkBandwidthPartId=1; + pucchcsires1->pucch_Resource=12; + ASN_SEQUENCE_ADD(&csirep1->reportConfigType.choice.periodic->pucch_CSI_ResourceList.list,pucchcsires1); + csirep1->reportQuantity.present = NR_CSI_ReportConfig__reportQuantity_PR_ssb_Index_RSRP; + csirep1->reportQuantity.choice.ssb_Index_RSRP=(NULL_t)0; + csirep1->reportFreqConfiguration = calloc(1,sizeof(*csirep1->reportFreqConfiguration)); + csirep1->reportFreqConfiguration->cqi_FormatIndicator=NR_CSI_ReportConfig__reportFreqConfiguration__cqi_FormatIndicator_widebandCQI; + csirep1->reportFreqConfiguration->pmi_FormatIndicator=NR_CSI_ReportConfig__reportFreqConfiguration__pmi_FormatIndicator_widebandPMI; + csirep1->reportFreqConfiguration->csi_ReportingBand=NULL; + csirep1->timeRestrictionForChannelMeasurements= NR_CSI_ReportConfig__timeRestrictionForChannelMeasurements_configured; + csirep1->timeRestrictionForInterferenceMeasurements=NR_CSI_ReportConfig__timeRestrictionForInterferenceMeasurements_configured; + csirep1->codebookConfig=calloc(1,sizeof(*csirep1->codebookConfig)); + csirep1->codebookConfig->codebookType.present = NR_CodebookConfig__codebookType_PR_type1; + csirep1->codebookConfig->codebookType.choice.type1 = calloc(1,sizeof(*csirep1->codebookConfig->codebookType.choice.type1)); + csirep1->codebookConfig->codebookType.choice.type1->subType.present=NR_CodebookConfig__codebookType__type1__subType_PR_typeI_SinglePanel; + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel=calloc(1,sizeof(*csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel)); + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.present= + NR_CodebookConfig__codebookType__type1__subType__typeI_SinglePanel__nrOfAntennaPorts_PR_two; + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two= + calloc(1,sizeof(*csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two)); + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.size=1; + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.bits_unused=2; + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.buf=malloc(1); + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.buf[0]=0xfc; + //'111111'B + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.size=1; + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.bits_unused=0; + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.buf=malloc(1); + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.buf[0]=0xc0; //'00000011'B + csirep1->codebookConfig->codebookType.choice.type1->codebookMode=1; + csirep1->dummy = NULL; + csirep1->groupBasedBeamReporting.present = NR_CSI_ReportConfig__groupBasedBeamReporting_PR_disabled; + csirep1->groupBasedBeamReporting.choice.disabled=calloc(1,sizeof(*csirep1->groupBasedBeamReporting.choice.disabled)); + csirep1->groupBasedBeamReporting.choice.disabled->nrofReportedRS = calloc(1,sizeof(*csirep1->groupBasedBeamReporting.choice.disabled->nrofReportedRS)); + *csirep1->groupBasedBeamReporting.choice.disabled->nrofReportedRS=NR_CSI_ReportConfig__groupBasedBeamReporting__disabled__nrofReportedRS_n2; + // this corresponds to: + //if the UE is configured with the higher layer parameter groupBasedBeamReporting set to 'disabled', the UE is not required to update measurements for more than 64 CSI-RS and/or SSB resources, and the UE shall report in a single report nrofReportedRS (higher layer configured) different CRI or SSBRI for each report setting. + csirep1->cqi_Table = calloc(1,sizeof(*csirep1->cqi_Table)); + *csirep1->cqi_Table = NR_CSI_ReportConfig__cqi_Table_table1; + csirep1->subbandSize = NR_CSI_ReportConfig__subbandSize_value1; + csirep1->non_PMI_PortIndication = NULL; + csirep1->ext1 = NULL; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ReportConfigToAddModList->list,csirep1); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->sCellDeactivationTimer=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->tag_Id=0; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->dummy=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->pathlossReferenceLinking=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->servingCellMO=NULL; } void fill_default_reconfig(NR_ServingCellConfigCommon_t *servingcellconfigcommon, - NR_RRCReconfiguration_IEs_t *reconfig, - NR_CellGroupConfig_t *secondaryCellGroup, - int n_physical_antenna_ports, - int initial_csi_index) { - + NR_RRCReconfiguration_IEs_t *reconfig, + NR_CellGroupConfig_t *secondaryCellGroup, + int n_physical_antenna_ports, + int initial_csi_index) { AssertFatal(servingcellconfigcommon!=NULL,"servingcellconfigcommon is null\n"); AssertFatal(reconfig!=NULL,"reconfig is null\n"); AssertFatal(secondaryCellGroup!=NULL,"secondaryCellGroup is null\n"); - // radioBearerConfig reconfig->radioBearerConfig=NULL; // secondaryCellGroup fill_default_secondaryCellGroup(servingcellconfigcommon,secondaryCellGroup,0,0,n_physical_antenna_ports,initial_csi_index); - xer_fprint(stdout, &asn_DEF_NR_CellGroupConfig, (const void*)secondaryCellGroup); - + xer_fprint(stdout, &asn_DEF_NR_CellGroupConfig, (const void *)secondaryCellGroup); char scg_buffer[1024]; asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CellGroupConfig, NULL, (void *)secondaryCellGroup, scg_buffer, 1024); AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", enc_rval.failed_type->name, enc_rval.encoded); - - reconfig->secondaryCellGroup = calloc(1,sizeof(*reconfig->secondaryCellGroup)); OCTET_STRING_fromBuf(reconfig->secondaryCellGroup, - (const char*)scg_buffer, - (enc_rval.encoded+7)>>3); + (const char *)scg_buffer, + (enc_rval.encoded+7)>>3); // measConfig reconfig->measConfig=NULL; // lateNonCriticalExtension @@ -2031,67 +1918,4 @@ void fill_default_reconfig(NR_ServingCellConfigCommon_t *servingcellconfigcommon // nonCriticalExtension reconfig->nonCriticalExtension = NULL; } -#if 0 -void fill_default_rbconfig(NR_RadioBearerConfig_t *rbconfig, x2ap_ENDC_sgnb_addition_req_t *m, struct NR_CG_ConfigInfo_IEs *cg_config_info) { -/* - if(cg_config_info->mcg_RB_Config) { - asn_dec_rval dec_rval = uper_decode(NULL, - &asn_DEF_NR_RadioBearerConfig, - (void**)&rbconfig, - cg_config_info->mcg_RB_Config->buf, - cg_ConfigInfo->mcg_RB_Config->size, 0, 0); - - if((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { - AssertFatal(1==0,"[InterNode] Failed to decode mcg_rb_config (%zu bits), size of OCTET_STRING %lu\n", - dec_rval.consumed, cg_ConfigInfo->ue_CapabilityInfo->size); - } - } - */ - - #if 0 - rbconfig->srb_ToAddModList = NULL; - rbconfig->srb3_ToRelease = NULL; - rbconfig->drb_ToAddModList = calloc(1,sizeof(*rbconfig->drb_ToAddModList)); - NR_DRB_ToAddMod_t *drb_ToAddMod = calloc(1,sizeof(*drb_ToAddMod)); - drb_ToAddMod->cnAssociation = calloc(1,sizeof(*drb_ToAddMod->cnAssociation)); - drb_ToAddMod->cnAssociation->present = NR_DRB_ToAddMod__cnAssociation_PR_eps_BearerIdentity; - drb_ToAddMod->cnAssociation->choice.eps_BearerIdentity=5; - drb_ToAddMod->drb_Identity = 1; - drb_ToAddMod->reestablishPDCP = NULL; - drb_ToAddMod->recoverPDCP = NULL; - drb_ToAddMod->pdcp_Config = calloc(1,sizeof(*drb_ToAddMod->pdcp_Config)); - drb_ToAddMod->pdcp_Config->drb = calloc(1,sizeof(*drb_ToAddMod->pdcp_Config->drb)); - drb_ToAddMod->pdcp_Config->drb->discardTimer = calloc(1,sizeof(*drb_ToAddMod->pdcp_Config->drb->discardTimer)); - *drb_ToAddMod->pdcp_Config->drb->discardTimer=NR_PDCP_Config__drb__discardTimer_ms30; - drb_ToAddMod->pdcp_Config->drb->pdcp_SN_SizeUL = calloc(1,sizeof(*drb_ToAddMod->pdcp_Config->drb->pdcp_SN_SizeUL)); - *drb_ToAddMod->pdcp_Config->drb->pdcp_SN_SizeUL = NR_PDCP_Config__drb__pdcp_SN_SizeUL_len18bits; - drb_ToAddMod->pdcp_Config->drb->pdcp_SN_SizeDL = calloc(1,sizeof(*drb_ToAddMod->pdcp_Config->drb->pdcp_SN_SizeDL)); - *drb_ToAddMod->pdcp_Config->drb->pdcp_SN_SizeDL = NR_PDCP_Config__drb__pdcp_SN_SizeDL_len18bits; - drb_ToAddMod->pdcp_Config->drb->headerCompression.present = NR_PDCP_Config__drb__headerCompression_PR_notUsed; - drb_ToAddMod->pdcp_Config->drb->headerCompression.choice.notUsed = 0; - - drb_ToAddMod->pdcp_Config->drb->integrityProtection=NULL; - drb_ToAddMod->pdcp_Config->drb->statusReportRequired=NULL; - drb_ToAddMod->pdcp_Config->drb->outOfOrderDelivery=NULL; - drb_ToAddMod->pdcp_Config->moreThanOneRLC = NULL; - - drb_ToAddMod->pdcp_Config->t_Reordering = calloc(1,sizeof(*drb_ToAddMod->pdcp_Config->t_Reordering)); - *drb_ToAddMod->pdcp_Config->t_Reordering = NR_PDCP_Config__t_Reordering_ms0; - drb_ToAddMod->pdcp_Config->ext1 = NULL; - - ASN_SEQUENCE_ADD(&rbconfig->drb_ToAddModList->list,drb_ToAddMod); - - rbconfig->drb_ToReleaseList = NULL; - - rbconfig->securityConfig = calloc(1,sizeof(*rbconfig->securityConfig)); - rbconfig->securityConfig->securityAlgorithmConfig = calloc(1,sizeof(*rbconfig->securityConfig->securityAlgorithmConfig)); - rbconfig->securityConfig->securityAlgorithmConfig->cipheringAlgorithm = NR_CipheringAlgorithm_nea0; - rbconfig->securityConfig->securityAlgorithmConfig->integrityProtAlgorithm=NULL; - rbconfig->securityConfig->keyToUse = calloc(1,sizeof(*rbconfig->securityConfig->keyToUse)); - *rbconfig->securityConfig->keyToUse = NR_SecurityConfig__keyToUse_master; -#endif - - xer_fprint(stdout, &asn_DEF_NR_RadioBearerConfig, (const void*)rbconfig); -} -#endif #endif From 04e903a39b8bacdc542580e3f75218cf70c3e587 Mon Sep 17 00:00:00 2001 From: "s.rampalli" Date: Wed, 20 May 2020 15:47:03 +0530 Subject: [PATCH 252/553] indentations fixed --- openair2/RRC/LTE/rrc_eNB.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index 37bb33322b..d31e1fb9be 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -2124,7 +2124,6 @@ rrc_eNB_generate_RRCConnectionReestablishmentReject( PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP), ue_p->Srb0.Tx_buffer.payload_size); } -#ifdef GES_ENDC_SUPPORT #if 0 void rrc_generate_SgNBReleaseRequest( const protocol_ctxt_t *const ctxt_pP, @@ -2146,7 +2145,6 @@ void rrc_generate_SgNBReleaseRequest( return; } #endif -#endif //----------------------------------------------------------------------------- /* * Generate the RRC Connection Release to UE. @@ -2164,7 +2162,6 @@ rrc_eNB_generate_RRCConnectionRelease( memset(buffer, 0, RRC_BUF_SIZE); T(T_ENB_RRC_CONNECTION_RELEASE, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame), T_INT(ctxt_pP->subframe), T_INT(ctxt_pP->rnti)); -#ifdef GES_ENDC_SUPPORT #if 0 if(ue_context_pP != NULL) { @@ -2173,7 +2170,6 @@ rrc_eNB_generate_RRCConnectionRelease( } } -#endif #endif size = do_RRCConnectionRelease(ctxt_pP->module_id, buffer,rrc_eNB_get_next_transaction_identifier(ctxt_pP->module_id)); ue_context_pP->ue_context.ue_reestablishment_timer = 0; From 783470905de8d2c6e4d83c968876a6c15aa65e47 Mon Sep 17 00:00:00 2001 From: cig Date: Mon, 18 May 2020 23:15:31 +0200 Subject: [PATCH 253/553] Bugfix: missing deactivation dlsch after processing is done: - the issue popped up with the new rx/tx implementation at the UE - this was causing false processing of DLSCH PDU and reception of false TA commands --- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 2d09fc7135..0158487f3c 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -4278,6 +4278,9 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, #endif + // deactivate dlsch once dlsch proc is done + ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->active = 0; + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC, VCD_FUNCTION_OUT); } From 928dd902e3d5939cefdee72c9ad7221195801c98 Mon Sep 17 00:00:00 2001 From: cig Date: Mon, 18 May 2020 23:21:20 +0200 Subject: [PATCH 254/553] Code cleanup --- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 10 ++++------ openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 2 +- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 0158487f3c..ab9561080f 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -3885,7 +3885,6 @@ void *UE_thread_slot1_dl_processing(void *arg) { } //printf("[slot1 dl processing] AbsSubframe %d.%d LLR Computation Start wait DCI %d\n",frame_rx,nr_tti_rx,wait); - /**** Pdsch Procedure Slot1 ****/ // start slot1 thread for Pdsch Procedure (slot1) // do procedures for C-RNTI @@ -3973,7 +3972,6 @@ void *UE_thread_slot1_dl_processing(void *arg) { #endif #endif - if (pthread_mutex_lock(&proc->mutex_slot1_dl_processing) != 0) { LOG_E( PHY, "[SCHED][UE] error locking mutex for UE RXTX\n" ); exit_fun("noting to add"); @@ -4120,7 +4118,7 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, if (dci_cnt > 0) { - LOG_D(PHY,"[UE %d] Frame %d, nr_tti_rx %d: found %d DCIs\n", ue->Mod_id, frame_rx, nr_tti_rx, dci_cnt); + LOG_D(PHY,"[UE %d] Frame %d, nr_tti_rx %d: found %d DCIs\n", ue->Mod_id, frame_rx, nr_tti_rx, dci_cnt); NR_UE_DLSCH_t *dlsch; if (ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->active == 1){ @@ -4167,7 +4165,7 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, PDSCH, ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0], NULL); - + //printf("phy procedure pdsch start measurement\n"); nr_ue_measurement_procedures(2,ue,proc,eNB_id,nr_tti_rx,mode); @@ -4179,7 +4177,7 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, write_output("rxF_comp.m","rxFc",&ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->rxdataF_comp0[0][0],fp->N_RB_DL*12*14,1,1); write_output("rxF_llr.m","rxFllr",ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->llr[0],(nb_symb_sch-1)*50*12+50*6,1,0); */ - + //VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC, VCD_FUNCTION_OUT); } @@ -4248,7 +4246,7 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, // do procedures for C-RNTI if (ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->active == 1) { - + LOG_D(PHY, "DLSCH data reception at nr_tti_rx: %d \n \n", nr_tti_rx); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC, VCD_FUNCTION_IN); diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 08d55779bd..964c88ff05 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -402,7 +402,7 @@ int configure_fapi_dl_pdu(int Mod_idP, pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types,pdcch_pdu_rel15->BWPSize); - LOG_D(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \ + LOG_D(MAC, "DCI params: rnti %x, rnti_type %d, dci_format %d\n \ coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n", pdcch_pdu_rel15->dci_pdu.RNTI[0], rnti_types[0], From b0ff2cef54abb72188a595b12a8fdd91dd53ded2 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Wed, 20 May 2020 15:05:33 +0200 Subject: [PATCH 255/553] rearranged function to prepare pucch scheduling --- openair2/LAYER2/NR_MAC_gNB/config.c | 3 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 33 +++-- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 113 ++++-------------- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 2 +- openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 1 - 5 files changed, 47 insertions(+), 105 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/config.c b/openair2/LAYER2/NR_MAC_gNB/config.c index 1e5a6bed29..36b81927f8 100644 --- a/openair2/LAYER2/NR_MAC_gNB/config.c +++ b/openair2/LAYER2/NR_MAC_gNB/config.c @@ -290,8 +290,7 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots, scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSymbols, scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots, - scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols - ); + scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols); if (return_tdd !=0){ LOG_E(PHY,"TDD configuration can not be done\n"); diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index 21bf6b1172..b36e4af9eb 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -305,12 +305,14 @@ void nr_schedule_pucch(int Mod_idP, NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[bwp_id-1]; nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[Mod_idP]->UL_tti_req[0]; - NR_sched_pucch *curr_pucch = UE_list->UE_sched_ctrl[UE_id].sched_pucch; - NR_sched_pucch *temp_pucch; - int release_pucch = 0; + NR_sched_pucch *curr_pucch; + int nr_ulmix_slots = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots; + if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols!=0) + nr_ulmix_slots++; - if (curr_pucch != NULL) { - if ((frameP == curr_pucch->frame) && (slotP == curr_pucch->ul_slot)) { + for (int k=0; kUE_sched_ctrl[UE_id].sched_pucch[k]; + if ((curr_pucch->dai_c > 0) && (frameP == curr_pucch->frame) && (slotP == curr_pucch->ul_slot)) { UL_tti_req->SFN = frameP; UL_tti_req->Slot = slotP; UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE; @@ -331,16 +333,9 @@ void nr_schedule_pucch(int Mod_idP, O_ack, SR_flag); - release_pucch = 1; + curr_pucch->dai_c = 0; } } - - if (release_pucch) { - temp_pucch = UE_list->UE_sched_ctrl[UE_id].sched_pucch; - UE_list->UE_sched_ctrl[UE_id].sched_pucch = UE_list->UE_sched_ctrl[UE_id].sched_pucch->next_sched_pucch; - free(temp_pucch); - } - } bool is_xlsch_in_slot(uint64_t bitmap, sub_frame_t slot){ @@ -378,6 +373,18 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; int num_slots_per_tdd = (nr_slots_per_frame[*scc->ssbSubcarrierSpacing])>>(7-scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity); + int nr_ulmix_slots = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots; + if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols!=0) + nr_ulmix_slots++; + + if (slot_txP == 0) { + for (int k=0; kUE_sched_ctrl[UE_id].sched_pucch[k], + 0, + sizeof(NR_sched_pucch)); + } + } + start_meas(&RC.nrmac[module_idP]->eNB_scheduler); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ULSCH_SCHEDULER,VCD_FUNCTION_IN); diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 4df24d7a16..2a90fc26e9 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -1330,6 +1330,11 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){ int UE_id; int i; NR_UE_list_t *UE_list = &RC.nrmac[mod_idP]->UE_list; + NR_COMMON_channels_t *cc = RC.nrmac[mod_idP]->common_channels; + NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; + int num_slots_ul = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots; + if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols>0) + num_slots_ul++; LOG_I(MAC, "[gNB %d] Adding UE with rnti %x (next avail %d, num_UEs %d)\n", mod_idP, rntiP, @@ -1348,6 +1353,7 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){ memset((void *) &UE_list->UE_sched_ctrl[UE_id], 0, sizeof(NR_UE_sched_ctrl_t)); + UE_list->UE_sched_ctrl[UE_id].sched_pucch = (NR_sched_pucch *)malloc(num_slots_ul*sizeof(NR_sched_pucch)); LOG_I(MAC, "gNB %d] Add NR UE_id %d : rnti %x\n", mod_idP, UE_id, @@ -1420,15 +1426,13 @@ void nr_update_pucch_scheduling(int Mod_idP, frame_t frameP, sub_frame_t slotP, int slots_per_tdd, - NR_sched_pucch *sched_pucch) { + NR_sched_pucch *curr_pucch) { NR_ServingCellConfigCommon_t *scc = RC.nrmac[Mod_idP]->common_channels->ServingCellConfigCommon; NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list; - int first_ul_slot_tdd,k; - NR_sched_pucch *curr_pucch; + int first_ul_slot_tdd,k,i; uint8_t pdsch_to_harq_feedback[8]; int found = 0; - int i = 0; int nr_ulmix_slots = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots; if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols!=0) nr_ulmix_slots++; @@ -1437,101 +1441,34 @@ void nr_update_pucch_scheduling(int Mod_idP, NR_SearchSpace__searchSpaceType_PR ss_type = NR_SearchSpace__searchSpaceType_PR_ue_Specific; get_pdsch_to_harq_feedback(Mod_idP,UE_id,ss_type,pdsch_to_harq_feedback); - // if the list of pucch to be scheduled is empty - if (UE_list->UE_sched_ctrl[UE_id].sched_pucch == NULL) { - sched_pucch->frame = frameP; - sched_pucch->next_sched_pucch = NULL; - sched_pucch->dai_c = 1; - sched_pucch->resource_indicator = 0; // in phytest with only 1 UE we are using just the 1st resource - if ( nr_ulmix_slots > 0 ) { + // for each possible ul or mixed slot + for (k=0; kUE_sched_ctrl[UE_id].sched_pucch[k]; + // if there is free room in current pucch structure + if (curr_pucch->dai_cframe = frameP; + curr_pucch->dai_c++; + curr_pucch->resource_indicator = 0; // in phytest with only 1 UE we are using just the 1st resource // first pucch occasion in first UL or MIXED slot first_ul_slot_tdd = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots; - for (k=0; kul_slot = first_ul_slot_tdd + k + (slotP - (slotP % slots_per_tdd)); - sched_pucch->timing_indicator = i; // index in the list of timing indicators - } - else - AssertFatal(1==0,"No Uplink slot available in accordance to allowed timing indicator\n"); - } - else - AssertFatal(1==0,"No Uplink Slots in this Frame\n"); - - UE_list->UE_sched_ctrl[UE_id].sched_pucch = sched_pucch; - } - else { // to be tested - curr_pucch = UE_list->UE_sched_ctrl[UE_id].sched_pucch; - if (curr_pucch->dai_cul_slot % slots_per_tdd)-(slotP % slots_per_tdd)) + i = 0; + while (i<8 && found == 0) { // look if timing indicator is among allowed values + if (pdsch_to_harq_feedback[i]==(first_ul_slot_tdd+k)-(slotP % slots_per_tdd)) found = 1; if (found == 0) i++; } - if (found == 1) { // scheduling this harq-ack in current pucch - curr_pucch->dai_c = 1 + curr_pucch->dai_c; - memcpy(sched_pucch,curr_pucch,sizeof(NR_sched_pucch)); - sched_pucch->timing_indicator = i; + if (found == 1) { + // computing slot in which pucch is scheduled + curr_pucch->ul_slot = first_ul_slot_tdd + k + (slotP - (slotP % slots_per_tdd)); + curr_pucch->timing_indicator = i; // index in the list of timing indicators return; } } - if (curr_pucch->dai_c==MAX_ACK_BITS || found == 0) { // if current pucch is full or no timing indicator allowed - // look for pucch occasions in other UL of mixed slots - for (k=scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots; kul_slot % slots_per_tdd)) { // skip current scheduled slot (already checked) - i = 0; - while (i<8 && found == 0) { // look if timing indicator is among allowed values - if (pdsch_to_harq_feedback[i]==k-(slotP % slots_per_tdd)) - found = 1; - if (found == 0) i++; - } - if (found == 1) { - if (k<(curr_pucch->ul_slot % slots_per_tdd)) { // we need to add a pucch occasion before current pucch - sched_pucch->frame = frameP; - sched_pucch->ul_slot = k + (slotP - (slotP % slots_per_tdd)); - sched_pucch->next_sched_pucch = curr_pucch; - sched_pucch->dai_c = 1; - sched_pucch->resource_indicator = 0; // in phytest with only 1 UE we are using just the 1st resource - sched_pucch->timing_indicator = i; - UE_list->UE_sched_ctrl[UE_id].sched_pucch = sched_pucch; - } - else { - while (curr_pucch->next_sched_pucch != NULL && k!=(curr_pucch->ul_slot % slots_per_tdd)) - curr_pucch = curr_pucch->next_sched_pucch; - if (curr_pucch == NULL) { // creating a new item in the list - sched_pucch->frame = frameP; - sched_pucch->next_sched_pucch = NULL; - sched_pucch->dai_c = 1; - sched_pucch->timing_indicator = i; - sched_pucch->resource_indicator = 0; // in phytest with only 1 UE we are using just the 1st resource - sched_pucch->ul_slot = k + (slotP - (slotP % slots_per_tdd)); - curr_pucch->next_sched_pucch = (NR_sched_pucch*) malloc(sizeof(NR_sched_pucch)); - curr_pucch->next_sched_pucch = sched_pucch; - } - else { - if (curr_pucch->dai_c==MAX_ACK_BITS) - found = 0; // if pucch at index k is already full we have to find a new one in a following occasion - else { // scheduling this harq-ack in current pucch - sched_pucch = curr_pucch; - sched_pucch->dai_c = 1 + sched_pucch->dai_c; - sched_pucch->timing_indicator = i; - } - } - } - } - } - } - } } + AssertFatal(1==0,"No Uplink slot available in accordance to allowed timing indicator\n"); } + void find_monitoring_periodicity_offset_common(NR_SearchSpace_t *ss, uint16_t *slot_period, uint16_t *offset) { diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index fc50a4d239..6190f42976 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -157,7 +157,7 @@ void nr_update_pucch_scheduling(int Mod_idP, frame_t frameP, sub_frame_t slotP, int slots_per_tdd, - NR_sched_pucch *sched_pucch); + NR_sched_pucch *curr_pucch); void get_pdsch_to_harq_feedback(int Mod_idP, int UE_id, diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index 3d6c9fc58e..aba5908aa5 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -185,7 +185,6 @@ typedef struct NR_sched_pucch { uint8_t dai_c; uint8_t timing_indicator; uint8_t resource_indicator; - struct NR_sched_pucch *next_sched_pucch; } NR_sched_pucch; typedef struct NR_UE_harq { From 2f4f90ba24e907eba2f2a4c609e1ac51b0b683ff Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Wed, 20 May 2020 15:49:43 +0200 Subject: [PATCH 256/553] bugfix --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 10 +++++----- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c | 4 +++- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 2 +- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index b36e4af9eb..ee70c9617b 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -361,7 +361,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, int UE_id; uint64_t *dlsch_in_slot_bitmap=NULL; uint64_t *ulsch_in_slot_bitmap=NULL; - NR_sched_pucch *pucch_sched = (NR_sched_pucch*) malloc(sizeof(NR_sched_pucch)); + int pucch_sched; UE_id=0; int bwp_id = 1; @@ -467,16 +467,16 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, // Phytest scheduling if (get_softmodem_params()->phy_test && (is_xlsch_in_slot(*dlsch_in_slot_bitmap,slot_txP%num_slots_per_tdd))) { - nr_update_pucch_scheduling(module_idP, UE_id, frame_txP, slot_txP, num_slots_per_tdd,pucch_sched); - nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, pucch_sched, NULL); + nr_update_pucch_scheduling(module_idP, UE_id, frame_txP, slot_txP, num_slots_per_tdd,&pucch_sched); + nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, &UE_list->UE_sched_ctrl[UE_id].sched_pucch[pucch_sched], NULL); // resetting ta flag gNB->ta_len = 0; } // Test DL scheduling if (get_softmodem_params()->phy_test == 0 && slot_txP == 1 && UE_list->fiveG_connected[UE_id]) { - nr_update_pucch_scheduling(module_idP, UE_id, frame_txP, slot_txP, num_slots_per_tdd,pucch_sched); - nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, pucch_sched, NULL); + nr_update_pucch_scheduling(module_idP, UE_id, frame_txP, slot_txP, num_slots_per_tdd,&pucch_sched); + nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, &UE_list->UE_sched_ctrl[UE_id].sched_pucch[pucch_sched], NULL); // resetting ta flag gNB->ta_len = 0; UE_list->fiveG_connected[UE_id] = false; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 2a90fc26e9..fa1e860c57 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -1426,10 +1426,11 @@ void nr_update_pucch_scheduling(int Mod_idP, frame_t frameP, sub_frame_t slotP, int slots_per_tdd, - NR_sched_pucch *curr_pucch) { + int *pucch_id) { NR_ServingCellConfigCommon_t *scc = RC.nrmac[Mod_idP]->common_channels->ServingCellConfigCommon; NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list; + NR_sched_pucch *curr_pucch; int first_ul_slot_tdd,k,i; uint8_t pdsch_to_harq_feedback[8]; int found = 0; @@ -1461,6 +1462,7 @@ void nr_update_pucch_scheduling(int Mod_idP, // computing slot in which pucch is scheduled curr_pucch->ul_slot = first_ul_slot_tdd + k + (slotP - (slotP % slots_per_tdd)); curr_pucch->timing_indicator = i; // index in the list of timing indicators + *pucch_id = k; return; } } diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index 6190f42976..4e29adf978 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -157,7 +157,7 @@ void nr_update_pucch_scheduling(int Mod_idP, frame_t frameP, sub_frame_t slotP, int slots_per_tdd, - NR_sched_pucch *curr_pucch); + int *pucch_id); void get_pdsch_to_harq_feedback(int Mod_idP, int UE_id, From 8f8894d76466ff6947d33f11b8a46906bf5efa7d Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Thu, 21 May 2020 23:02:08 +0200 Subject: [PATCH 257/553] suppressed some LOG_M that were killing real-time. --- openair1/PHY/NR_TRANSPORT/nr_prach.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index 52ed4a5f19..2200768f47 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -283,7 +283,6 @@ void rx_nr_prach_ru(RU_t *ru, if (prachFormat == 0 || prachFormat == 1 || prachFormat == 2) { dftlen=49152; dft(DFT_49152,prach2,rxsigF[aa],1); - LOG_M("prach_rxsigF.m","prach_rxF0",rxsigF[aa],49152,1,1); } if (prachFormat == 1 || prachFormat == 2) { dft(DFT_49152,prach2+98304,rxsigF[aa]+98304,1); @@ -750,10 +749,10 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, prach_ifft[i] += ((int32_t)prach_ifft_tmp[i<<1]*(int32_t)prach_ifft_tmp[(i<<1)] + (int32_t)prach_ifft_tmp[1+(i<<1)]*(int32_t)prach_ifft_tmp[1+(i<<1)])>>10; } - // if (LOG_DUMPFLAG(PRACH)) { + if (LOG_DUMPFLAG(PRACH)) { if (aa==0) LOG_M("prach_rxF_comp0.m","prach_rxF_comp0",prachF,1024,1,1); if (aa==1) LOG_M("prach_rxF_comp1.m","prach_rxF_comp1",prachF,1024,1,1); - // } + } }// antennas_rx } // new dft From eb5a7a9ab1e9728954bfdf654797adb6b36535cf Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Fri, 22 May 2020 12:41:28 +0200 Subject: [PATCH 258/553] added harq handling in gnb mac --- openair1/PHY/NR_TRANSPORT/nr_dci_tools.c | 3 +- openair1/PHY/NR_TRANSPORT/nr_dlsch.c | 2 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 2 + .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 8 ++-- openair2/LAYER2/NR_MAC_gNB/main.c | 4 ++ openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 2 + openair2/NR_PHY_INTERFACE/NR_IF_Module.c | 39 ++++++++++++++++++- 7 files changed, 53 insertions(+), 7 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c index ec5aee3c8a..96e370eb97 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c @@ -219,7 +219,8 @@ void nr_fill_dci(PHY_VARS_gNB *gNB, } dlsch = gNB->dlsch[dlsch_id][0]; - int harq_pid = 0;//extract_harq_pid(i,pdu_rel15); + int num_slots_tdd = (gNB->frame_params.p_tdd_UL_DL_Configuration->dl_UL_TransmissionPeriodicity/10000) * gNB->frame_params.slots_per_frame; + int harq_pid = slot % num_slots_tdd; dlsch->slot_tx[slot] = 1; dlsch->harq_ids[frame%2][slot] = harq_pid; diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch.c index 8324508361..78d6619d6b 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch.c @@ -126,7 +126,7 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch, time_stats_t *dlsch_interleaving_stats, time_stats_t *dlsch_segmentation_stats) { - int harq_pid = 0; + int harq_pid = dlsch->harq_ids[frame%2][slot]; NR_DL_gNB_HARQ_t *harq = dlsch->harq_processes[harq_pid]; nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &harq->pdsch_pdu.pdsch_pdu_rel15; uint32_t scrambled_output[NR_MAX_NB_CODEWORDS][NR_MAX_PDSCH_ENCODED_LENGTH>>5]; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index 21bf6b1172..79e616b6eb 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -461,6 +461,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, // Phytest scheduling if (get_softmodem_params()->phy_test && (is_xlsch_in_slot(*dlsch_in_slot_bitmap,slot_txP%num_slots_per_tdd))) { nr_update_pucch_scheduling(module_idP, UE_id, frame_txP, slot_txP, num_slots_per_tdd,pucch_sched); + ue_sched_ctl->current_harq_pid = slot_txP % num_slots_per_tdd; nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, pucch_sched, NULL); // resetting ta flag gNB->ta_len = 0; @@ -469,6 +470,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, // Test DL scheduling if (get_softmodem_params()->phy_test == 0 && slot_txP == 1 && UE_list->fiveG_connected[UE_id]) { nr_update_pucch_scheduling(module_idP, UE_id, frame_txP, slot_txP, num_slots_per_tdd,pucch_sched); + ue_sched_ctl->current_harq_pid = slot_txP % num_slots_per_tdd; nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, pucch_sched, NULL); // resetting ta flag gNB->ta_len = 0; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 3b73db4c97..bc435ec047 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -309,11 +309,12 @@ int configure_fapi_dl_pdu(int Mod_idP, pdsch_pdu_rel15->NrOfCodewords = 1; int mcs = (mcsIndex!=NULL) ? *mcsIndex : 9; + int current_harq_pid = UE_list->UE_sched_ctrl[UE_id].current_harq_pid; pdsch_pdu_rel15->targetCodeRate[0] = nr_get_code_rate_dl(mcs,0); pdsch_pdu_rel15->qamModOrder[0] = 2; pdsch_pdu_rel15->mcsIndex[0] = mcs; pdsch_pdu_rel15->mcsTable[0] = 0; - pdsch_pdu_rel15->rvIndex[0] = UE_list->UE_sched_ctrl[UE_id].harq_processes[0].round; + pdsch_pdu_rel15->rvIndex[0] = UE_list->UE_sched_ctrl[UE_id].harq_processes[current_harq_pid].round; pdsch_pdu_rel15->dataScramblingId = *scc->physCellId; pdsch_pdu_rel15->nrOfLayers = 1; pdsch_pdu_rel15->transmissionScheme = 0; @@ -365,8 +366,8 @@ int configure_fapi_dl_pdu(int Mod_idP, dci_pdu_rel15[0].mcs = pdsch_pdu_rel15->mcsIndex[0]; dci_pdu_rel15[0].rv = pdsch_pdu_rel15->rvIndex[0]; // harq pid - dci_pdu_rel15[0].harq_pid = 0; - dci_pdu_rel15[0].ndi = UE_list->UE_sched_ctrl[UE_id].harq_processes[0].ndi; + dci_pdu_rel15[0].harq_pid = current_harq_pid; + dci_pdu_rel15[0].ndi = UE_list->UE_sched_ctrl[UE_id].harq_processes[current_harq_pid].ndi; // DAI dci_pdu_rel15[0].dai[0].val = (pucch_sched->dai_c-1)&3; @@ -376,6 +377,7 @@ int configure_fapi_dl_pdu(int Mod_idP, dci_pdu_rel15[0].pucch_resource_indicator = pucch_sched->resource_indicator; // PDSCH to HARQ TI dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator.val = pucch_sched->timing_indicator; + UE_list->UE_sched_ctrl[UE_id].harq_processes[current_harq_pid].feedback_slot = pucch_sched->ul_slot; // antenna ports dci_pdu_rel15[0].antenna_ports.val = 0; // nb of cdm groups w/o data 1 and dmrs port 0 diff --git a/openair2/LAYER2/NR_MAC_gNB/main.c b/openair2/LAYER2/NR_MAC_gNB/main.c index d38a251a2b..669bc1cd5a 100644 --- a/openair2/LAYER2/NR_MAC_gNB/main.c +++ b/openair2/LAYER2/NR_MAC_gNB/main.c @@ -113,6 +113,10 @@ void mac_top_init_gNB(void) UE_list->next[list_el] = list_el + 1; UE_list->next_ul[list_el] = list_el + 1; UE_list->active[list_el] = FALSE; + for (int list_harq = 0; list_harq < NR_MAX_NB_HARQ_PROCESSES; list_harq++) { + UE_list->UE_sched_ctrl[list_el].harq_processes[list_harq].round = 0; + UE_list->UE_sched_ctrl[list_el].harq_processes[list_harq].ndi = 0; + } } UE_list->next[list_el] = -1; diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index 3d6c9fc58e..82463e61f4 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -191,6 +191,7 @@ typedef struct NR_sched_pucch { typedef struct NR_UE_harq { uint8_t ndi; uint8_t round; + uint16_t feedback_slot; } NR_UE_harq_t; /*! \brief scheduling control information set through an API */ @@ -200,6 +201,7 @@ typedef struct { NR_sched_pucch *sched_pucch; uint16_t ta_timer; int16_t ta_update; + uint8_t current_harq_pid; NR_UE_harq_t harq_processes[NR_MAX_NB_HARQ_PROCESSES]; } NR_UE_sched_ctrl_t; diff --git a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c index f347a33581..797499c990 100644 --- a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c @@ -76,8 +76,43 @@ void handle_nr_rach(NR_UL_IND_t *UL_info) { } -void handle_nr_uci(NR_UL_IND_t *UL_info) { +void handle_nr_uci(NR_UL_IND_t *UL_info, NR_UE_sched_ctrl_t *sched_crtl) { // TODO + int max_harq_rounds = 4; // TODO define macro + int num_ucis = UL_info->uci_ind.num_ucis; + nfapi_nr_uci_t *uci_list = UL_info->uci_ind.uci_list; + + for (int i = 0; i < num_ucis; i++) { + switch (uci_list[i].pdu_type) { + case NFAPI_NR_UCI_PDCCH_PDU_TYPE: break; + + case NFAPI_NR_UCI_FORMAT_0_1_PDU_TYPE: + nfapi_nr_uci_pucch_pdu_format_0_1_t *uci_pdu = &uci_list[i].pucch_pdu_format_0_1; + // handle harq + int harq_idx_s = 0; + // iterate over received harq bits + for (int harq_bit = 0; harq_bit < uci_pdu->harq->num_harq; harq_bit++) { + // search for the right harq process + for (int harq_idx = harq_idx_s; harq_idx < NR_MAX_NB_HARQ_PROCESSES-1; harq_idx++) { + if ((UL_info->slot-1) == sched_ctrl->harq_processes[harq_idx].feedback_slot) { + if (uci_pdu->harq->harq_list[harq_bit].harq_value == 0) + sched_ctrl->harq_processes[harq_idx].round++; + if ((uci_pdu->harq->harq_list[harq_bit].harq_value == 1) || + (sched_ctrl->harq_processes[harq_idx].round == max_harq_rounds)) { + sched_ctrl->harq_processes[harq_idx].ndi ^= 1; + sched_ctrl->harq_processes[harq_idx].round = 0; + } + harq_idx_s = harq_idx + 1; + break; + } + } + } + break; + + case NFAPI_NR_UCI_FORMAT_2_3_4_PDU_TYPE: break; + } + } + UL_info->uci_ind.num_ucis = 0; } @@ -180,7 +215,7 @@ void NR_UL_indication(NR_UL_IND_t *UL_info) { // clear DL/UL info for new scheduling round clear_nr_nfapi_information(mac,CC_id,UL_info->frame,UL_info->slot); handle_nr_rach(UL_info); - handle_nr_uci(UL_info); + handle_nr_uci(UL_info, mac->UE_list->UE_sched_ctrl[0]); // clear HI prior to handling ULSCH mac->UL_dci_req[CC_id].numPdus = 0; handle_nr_ulsch(UL_info); From 94b88cf2cf2ee84d55e254e333c1e5236b618a98 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Fri, 22 May 2020 13:16:30 +0200 Subject: [PATCH 259/553] bug fixes --- openair1/PHY/NR_TRANSPORT/nr_dci_tools.c | 2 +- openair2/NR_PHY_INTERFACE/NR_IF_Module.c | 7 ++++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c index 96e370eb97..f928645212 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c @@ -219,7 +219,7 @@ void nr_fill_dci(PHY_VARS_gNB *gNB, } dlsch = gNB->dlsch[dlsch_id][0]; - int num_slots_tdd = (gNB->frame_params.p_tdd_UL_DL_Configuration->dl_UL_TransmissionPeriodicity/10000) * gNB->frame_params.slots_per_frame; + int num_slots_tdd = (gNB->frame_parms.p_tdd_UL_DL_Configuration->dl_UL_TransmissionPeriodicity/10000) * gNB->frame_parms.slots_per_frame; int harq_pid = slot % num_slots_tdd; dlsch->slot_tx[slot] = 1; diff --git a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c index 797499c990..58a8171e8e 100644 --- a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c @@ -76,7 +76,7 @@ void handle_nr_rach(NR_UL_IND_t *UL_info) { } -void handle_nr_uci(NR_UL_IND_t *UL_info, NR_UE_sched_ctrl_t *sched_crtl) { +void handle_nr_uci(NR_UL_IND_t *UL_info, NR_UE_sched_ctrl_t *sched_ctrl) { // TODO int max_harq_rounds = 4; // TODO define macro int num_ucis = UL_info->uci_ind.num_ucis; @@ -86,7 +86,7 @@ void handle_nr_uci(NR_UL_IND_t *UL_info, NR_UE_sched_ctrl_t *sched_crtl) { switch (uci_list[i].pdu_type) { case NFAPI_NR_UCI_PDCCH_PDU_TYPE: break; - case NFAPI_NR_UCI_FORMAT_0_1_PDU_TYPE: + case NFAPI_NR_UCI_FORMAT_0_1_PDU_TYPE: { nfapi_nr_uci_pucch_pdu_format_0_1_t *uci_pdu = &uci_list[i].pucch_pdu_format_0_1; // handle harq int harq_idx_s = 0; @@ -108,6 +108,7 @@ void handle_nr_uci(NR_UL_IND_t *UL_info, NR_UE_sched_ctrl_t *sched_crtl) { } } break; + } case NFAPI_NR_UCI_FORMAT_2_3_4_PDU_TYPE: break; } @@ -215,7 +216,7 @@ void NR_UL_indication(NR_UL_IND_t *UL_info) { // clear DL/UL info for new scheduling round clear_nr_nfapi_information(mac,CC_id,UL_info->frame,UL_info->slot); handle_nr_rach(UL_info); - handle_nr_uci(UL_info, mac->UE_list->UE_sched_ctrl[0]); + handle_nr_uci(UL_info, &mac->UE_list.UE_sched_ctrl[0]); // clear HI prior to handling ULSCH mac->UL_dci_req[CC_id].numPdus = 0; handle_nr_ulsch(UL_info); From 17e52131d3f9d2744498ddce22089eba5fd67d58 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 22 May 2020 15:00:37 +0200 Subject: [PATCH 260/553] scheduling continuous dl transmission in first half frame --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index ee70c9617b..203978b114 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -377,7 +377,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols!=0) nr_ulmix_slots++; - if (slot_txP == 0) { + if ((slot_txP == 0) && (UE_list->fiveG_connected[UE_id] || get_softmodem_params()->phy_test)) { for (int k=0; kUE_sched_ctrl[UE_id].sched_pucch[k], 0, @@ -474,12 +474,11 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, } // Test DL scheduling - if (get_softmodem_params()->phy_test == 0 && slot_txP == 1 && UE_list->fiveG_connected[UE_id]) { + if (get_softmodem_params()->phy_test == 0 && slot_txP>0 && slot_txP<7 && UE_list->fiveG_connected[UE_id]) { nr_update_pucch_scheduling(module_idP, UE_id, frame_txP, slot_txP, num_slots_per_tdd,&pucch_sched); nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, &UE_list->UE_sched_ctrl[UE_id].sched_pucch[pucch_sched], NULL); // resetting ta flag gNB->ta_len = 0; - UE_list->fiveG_connected[UE_id] = false; } @@ -494,8 +493,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, if (is_nr_UL_slot(cc->ServingCellConfigCommon,slot_rxP)) { if (get_softmodem_params()->phy_test == 0) { - NR_sched_pucch *curr_pucch = UE_list->UE_sched_ctrl[UE_id].sched_pucch; - if (curr_pucch != NULL) + if (UE_list->fiveG_connected[UE_id]) nr_schedule_pucch(module_idP, UE_id, frame_rxP, slot_rxP); schedule_nr_prach(module_idP, (frame_rxP+1)&1023, slot_rxP); nr_schedule_reception_msg3(module_idP, 0, frame_rxP, slot_rxP); From 6fa5a6cf89ffbada59a725d6825f51d2da2dc0e1 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 22 May 2020 15:35:31 +0200 Subject: [PATCH 261/553] bugfix --- openair1/PHY/NR_TRANSPORT/nr_dci_tools.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c index f928645212..02ecfc4404 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c @@ -219,7 +219,7 @@ void nr_fill_dci(PHY_VARS_gNB *gNB, } dlsch = gNB->dlsch[dlsch_id][0]; - int num_slots_tdd = (gNB->frame_parms.p_tdd_UL_DL_Configuration->dl_UL_TransmissionPeriodicity/10000) * gNB->frame_parms.slots_per_frame; + int num_slots_tdd = (gNB->frame_parms.slots_per_frame)>>(7-gNB->gNB_config.tdd_table.tdd_period.value); int harq_pid = slot % num_slots_tdd; dlsch->slot_tx[slot] = 1; From 02be147d17ffe2e3bbfcc8fd3403be6b729cabd4 Mon Sep 17 00:00:00 2001 From: "vr.devendra" Date: Fri, 22 May 2020 20:15:12 +0530 Subject: [PATCH 262/553] GlobalEdge: CSI and TCI related MAC CE intial commit --- cmake_targets/CMakeLists.txt | 1 + openair2/LAYER2/NR_MAC_COMMON/nr_mac.h | 168 ++++-- .../LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c | 385 ++++++++++---- openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 489 ++++++++++-------- 4 files changed, 678 insertions(+), 365 deletions(-) diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index a86c262867..7662d29775 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -249,6 +249,7 @@ add_boolean_option(UE_AUTOTEST_TRACE False "Activate UE autotest specific logs add_boolean_option(UE_DEBUG_TRACE False "Activate UE debug trace") add_boolean_option(UE_TIMING_TRACE False "Activate UE timing trace") add_boolean_option(DEBUG_CONSOLE False "makes debugging easier, disables stdout/stderr buffering") +add_boolean_option(GES_SUPPORT True "To enable the GES Code") set (OCP_ITTI ${OPENAIR_DIR}/common/utils/ocp_itti) add_library(ITTI diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h index 04b213b0d2..d6a26c3be2 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h @@ -24,8 +24,8 @@ * \author R. Knopp, K.H. HSU, G. Casati * \date 2019 * \version 0.1 - * \company Eurecom / NTUST / Fraunhofer IIS - * \email: knopp@eurecom.fr, kai-hsiang.hsu@eurecom.fr, guido.casati@iis.fraunhofer.de + * \company Eurecom / NTUST / Fraunhofer IIS + * \email: knopp@eurecom.fr, kai-hsiang.hsu@eurecom.fr, guido.casati@iis.fraunhofer.de * \note * \warning */ @@ -71,72 +71,132 @@ // R: Reserved bit, set to zero. typedef struct { - uint8_t LCID:6; // octet 1 [5:0] - uint8_t F:1; // octet 1 [6] - uint8_t R:1; // octet 1 [7] - uint8_t L:8; // octet 2 [7:0] + uint8_t LCID: 6; // octet 1 [5:0] + uint8_t F: 1; // octet 1 [6] + uint8_t R: 1; // octet 1 [7] + uint8_t L: 8; // octet 2 [7:0] } __attribute__ ((__packed__)) NR_MAC_SUBHEADER_SHORT; typedef struct { - uint8_t LCID:6; // octet 1 [5:0] - uint8_t F:1; // octet 1 [6] - uint8_t R:1; // octet 1 [7] - uint8_t L1:8; // octet 2 [7:0] - uint8_t L2:8; // octet 3 [7:0] + uint8_t LCID: 6; // octet 1 [5:0] + uint8_t F: 1; // octet 1 [6] + uint8_t R: 1; // octet 1 [7] + uint8_t L1: 8; // octet 2 [7:0] + uint8_t L2: 8; // octet 3 [7:0] } __attribute__ ((__packed__)) NR_MAC_SUBHEADER_LONG; typedef struct { - uint8_t LCID:6; // octet 1 [5:0] - uint8_t R:2; // octet 1 [7:6] + uint8_t LCID: 6; // octet 1 [5:0] + uint8_t R: 2; // octet 1 [7:6] } __attribute__ ((__packed__)) NR_MAC_SUBHEADER_FIXED; // BSR MAC CEs // TS 38.321 ch. 6.1.3.1 // Short BSR for a specific logical channel group ID typedef struct { - uint8_t Buffer_size:5; // octet 1 LSB - uint8_t LcgID:3; // octet 1 MSB + uint8_t Buffer_size: 5; // octet 1 LSB + uint8_t LcgID: 3; // octet 1 MSB } __attribute__ ((__packed__)) NR_BSR_SHORT; typedef NR_BSR_SHORT NR_BSR_SHORT_TRUNCATED; // Long BSR for all logical channel group ID typedef struct { - uint8_t Buffer_size7:8; - uint8_t Buffer_size6:8; - uint8_t Buffer_size5:8; - uint8_t Buffer_size4:8; - uint8_t Buffer_size3:8; - uint8_t Buffer_size2:8; - uint8_t Buffer_size1:8; - uint8_t Buffer_size0:8; - uint8_t LcgID0:1; - uint8_t LcgID1:1; - uint8_t LcgID2:1; - uint8_t LcgID3:1; - uint8_t LcgID4:1; - uint8_t LcgID5:1; - uint8_t LcgID6:1; - uint8_t LcgID7:1; + uint8_t Buffer_size7: 8; + uint8_t Buffer_size6: 8; + uint8_t Buffer_size5: 8; + uint8_t Buffer_size4: 8; + uint8_t Buffer_size3: 8; + uint8_t Buffer_size2: 8; + uint8_t Buffer_size1: 8; + uint8_t Buffer_size0: 8; + uint8_t LcgID0: 1; + uint8_t LcgID1: 1; + uint8_t LcgID2: 1; + uint8_t LcgID3: 1; + uint8_t LcgID4: 1; + uint8_t LcgID5: 1; + uint8_t LcgID6: 1; + uint8_t LcgID7: 1; } __attribute__ ((__packed__)) NR_BSR_LONG; typedef NR_BSR_LONG NR_BSR_LONG_TRUNCATED; // 38.321 ch. 6.1.3.4 typedef struct { - uint8_t TA_COMMAND:6; // octet 1 [5:0] - uint8_t TAGID:2; // octet 1 [7:6] + uint8_t TA_COMMAND: 6; // octet 1 [5:0] + uint8_t TAGID: 2; // octet 1 [7:6] } __attribute__ ((__packed__)) NR_MAC_CE_TA; // single Entry PHR MAC CE // TS 38.321 ch. 6.1.3.8 typedef struct { - uint8_t PH:6; - uint8_t R1:2; - uint8_t PCMAX:6; - uint8_t R2:6; + uint8_t PH: 6; + uint8_t R1: 2; + uint8_t PCMAX: 6; + uint8_t R2: 6; } __attribute__ ((__packed__)) NR_SINGLE_ENTRY_PHR_MAC_CE; +#ifdef GES_SUPPORT + +// SP ZP CSI-RS Resource Set Activation/Deactivation MAC CE +// 38.321 ch. 6.1.3.19 +typedef struct { + uint8_t BWPID: 2; // octet 1 [1:0] + uint8_t CELLID: 5; // octet 1 [6:2] + uint8_t A_D: 1; // octet 1 [7] + uint8_t CSIRS_RSC_ID: 4; // octet 2 [3:0] + uint8_t R: 4 // octet 2 [7:4] +} __attribute__ ((__packed__)) NR_MAC_CE_SP_ZP_CSI_RS_RES_SET; + +//TS 38.321 Sec 6.1.3.15, TCI State indicaton for UE-Specific PDCCH MAC CE +typedef struct { + uint8_t CoresetId1: 3; //Octect 1 [2:0] + uint8_t ServingCellId: 5; //Octect 1 [7:3] + uint8_t TciStateId: 7; //Octect 2 [6:0] + uint8_t CoresetId2: 1; //Octect 2 [7] +} __attribute__ ((__packed__)) NR_TCI_PDCCH; + +//TS 38.321 Sec 6.1.3.14, TCI State activation/deactivation for UE Specific PDSCH MAC CE +typedef struct { + uint8_t BWP_Id: 2; //Octect 1 [1:0] + uint8_t ServingCellId: 5; //Octect 1 [6:2] + uint8_t R: 1; //Octect 1 [7] + uint8_t T[]; //Octects 2 to MAX TCI States/8 +} __attribute__ ((__packed__)) NR_TCI_PDSCH_APERIODIC_CSI; + +//TS 6.1.3.16, SP CSI reporting on PUCCH Activation/Deactivation MAC CE +typedef struct { + uint8_t BWP_Id: 2; //Octect 1 [1:0] + uint8_t ServingCellId: 5; //Octect 1 [6:2] + uint8_t R1: 1; //Octect 1 [7] + uint8_t S0: 1; //Octect 2 [0] + uint8_t S1: 1; //Octect 2 [1] + uint8_t S2: 1; //Octect 2 [2] + uint8_t S3: 1; //Octect 2 [3] + uint8_t R2: 4; //Octect 2 [7:4] +} __attribute__ ((__packed__)) NR_PUCCH_CSI_REPORTING; + + +//TS 38.321 sec 6.1.3.12 +//SP CSI-RS / CSI-IM Resource Set Activation/Deactivation MAC CE +typedef struct { + uint8_t BWP_ID: 2; + uint8_t SCID: 5; + uint8_t A_D: 1; + uint8_t SP_CSI_RSID: 6; + uint8_t IM: 1; + uint8_t R1: 1; + uint8_t SP_CSI_IMID: 6; + uint8_t R2: 2; + struct TCI_S { + uint8_t TCI_STATE_ID: 6; + uint8_t R: 2; + } __attribute__ ((__packed__)) TCI_STATE; +} __attribute__ ((__packed__)) CSI_RS_CSI_IM_ACT_DEACT_MAC_CE; + +#endif + //* RAR MAC subheader // TS 38.321 ch. 6.1.5, 6.2.2 *// // - E: The Extension field is a flag indicating if the MAC subPDU including this MAC subheader is the last MAC subPDU or not in the MAC PDU // - T: The Type field is a flag indicating whether the MAC subheader contains a Random Access Preamble ID or a Backoff Indicator (0, BI) (1, RAPID) @@ -146,30 +206,30 @@ typedef struct { /*!\brief RAR MAC subheader with RAPID */ typedef struct { - uint8_t RAPID:6; - uint8_t T:1; - uint8_t E:1; + uint8_t RAPID: 6; + uint8_t T: 1; + uint8_t E: 1; } __attribute__ ((__packed__)) NR_RA_HEADER_RAPID; /*!\brief RAR MAC subheader with Backoff Indicator */ typedef struct { - uint8_t BI:4; - uint8_t R:2; - uint8_t T:1; - uint8_t E:1; + uint8_t BI: 4; + uint8_t R: 2; + uint8_t T: 1; + uint8_t E: 1; } __attribute__ ((__packed__)) NR_RA_HEADER_BI; // TS 38.321 ch. 6.2.3 typedef struct { - uint8_t TA1:7; // octet 1 [6:0] - uint8_t R:1; // octet 1 [7] - uint8_t UL_GRANT_1:3; // octet 2 [2:0] - uint8_t TA2:5; // octet 2 [7:3] - uint8_t UL_GRANT_2:8; // octet 3 [7:0] - uint8_t UL_GRANT_3:8; // octet 4 [7:0] - uint8_t UL_GRANT_4:8; // octet 5 [7:0] - uint8_t TCRNTI_1:8; // octet 6 [7:0] - uint8_t TCRNTI_2:8; // octet 7 [7:0] + uint8_t TA1: 7; // octet 1 [6:0] + uint8_t R: 1; // octet 1 [7] + uint8_t UL_GRANT_1: 3; // octet 2 [2:0] + uint8_t TA2: 5; // octet 2 [7:3] + uint8_t UL_GRANT_2: 8; // octet 3 [7:0] + uint8_t UL_GRANT_3: 8; // octet 4 [7:0] + uint8_t UL_GRANT_4: 8; // octet 5 [7:0] + uint8_t TCRNTI_1: 8; // octet 6 [7:0] + uint8_t TCRNTI_2: 8; // octet 7 [7:0] } __attribute__ ((__packed__)) NR_MAC_RAR; // 38.321 ch6.2.1, 38.331 @@ -185,7 +245,7 @@ typedef struct { #define DL_SCH_LCID_TCI_STATE_IND_UE_SPEC_PDCCH 0x34 #define DL_SCH_LCID_TCI_STATE_ACT_UE_SPEC_PDSCH 0x35 #define DL_SCH_LCID_APERIODIC_CSI_TRI_STATE_SUBSEL 0x36 -#define DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT 0X37 +#define DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT 0X37 #define DL_SCH_LCID_DUPLICATION_ACT 0X38 #define DL_SCH_LCID_SCell_ACT_4_OCT 0X39 #define DL_SCH_LCID_SCell_ACT_1_OCT 0X3A diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c index 7777e307fb..e086210e4f 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c @@ -47,6 +47,12 @@ //////////////////////////////////////////////////////// /////* DLSCH MAC PDU generation (6.1.2 TS 38.321) *///// //////////////////////////////////////////////////////// +#ifdef GES_SUPPORT +#define OCTET 8 +#define HALFWORD 16 +#define WORD 32 +//#define SIZE_OF_POINTER sizeof (void *) +#endif int nr_generate_dlsch_pdu(module_id_t module_idP, unsigned char *sdus_payload, @@ -56,127 +62,302 @@ int nr_generate_dlsch_pdu(module_id_t module_idP, unsigned char *sdu_lcids, unsigned char drx_cmd, unsigned char *ue_cont_res_id, - unsigned short post_padding){ + unsigned short post_padding) { - gNB_MAC_INST *gNB = RC.nrmac[module_idP]; + gNB_MAC_INST *gNB = RC.nrmac[module_idP]; - NR_MAC_SUBHEADER_FIXED *mac_pdu_ptr = (NR_MAC_SUBHEADER_FIXED *) mac_pdu; - unsigned char * dlsch_buffer_ptr = sdus_payload; - uint8_t last_size = 0; - int offset = 0, mac_ce_size, i, timing_advance_cmd, tag_id = 0; - // MAC CEs - uint8_t mac_header_control_elements[16], *ce_ptr; - ce_ptr = &mac_header_control_elements[0]; + NR_MAC_SUBHEADER_FIXED *mac_pdu_ptr = (NR_MAC_SUBHEADER_FIXED *) mac_pdu; + unsigned char * dlsch_buffer_ptr = sdus_payload; + uint8_t last_size = 0; + int offset = 0, mac_ce_size, i, timing_advance_cmd, tag_id = 0; + // MAC CEs + uint8_t mac_header_control_elements[16], *ce_ptr; + ce_ptr = &mac_header_control_elements[0]; +#ifdef GES_SUPPORT + uint16_t UE_id = 0; //TODO need to get as a function parameter or need to invoke api to UE_id using module Id and RNTI + gNB_MAC_INST *gNB_mac = RC.nrmac[module_idP]; + NR_UE_list_t *UE_list = &gNB_mac->UE_list; + NR_UE_sched_ctrl_t *ue_sched_ctl = NULL; + //NR_CellGroupConfig_t *config = UE_list->secondaryCellGroup[UE_id]; + ue_sched_ctl = &(UE_list->UE_sched_ctrl[UE_id]); +#endif - // 1) Compute MAC CE and related subheaders + // 1) Compute MAC CE and related subheaders - // DRX command subheader (MAC CE size 0) - if (drx_cmd != 255) { - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_DRX; - //last_size = 1; - mac_pdu_ptr++; - } - - // Timing Advance subheader - /* This was done only when timing_advance_cmd != 31 - // now TA is always send when ta_timer resets regardless of its value - // this is done to avoid issues with the timeAlignmentTimer which is - // supposed to monitor if the UE received TA or not */ - if (gNB->ta_len){ - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_TA_COMMAND; - //last_size = 1; - mac_pdu_ptr++; - - // TA MAC CE (1 octet) - timing_advance_cmd = gNB->ta_command; - AssertFatal(timing_advance_cmd < 64,"timing_advance_cmd %d > 63\n", timing_advance_cmd); - ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND = timing_advance_cmd; //(timing_advance_cmd+31)&0x3f; - if (gNB->tag->tag_Id != 0){ - tag_id = gNB->tag->tag_Id; - ((NR_MAC_CE_TA *) ce_ptr)->TAGID = tag_id; + // DRX command subheader (MAC CE size 0) + if (drx_cmd != 255) { + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_DRX; + //last_size = 1; + mac_pdu_ptr++; } - LOG_D(MAC, "NR MAC CE timing advance command = %d (%d) TAG ID = %d\n", timing_advance_cmd, ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND, tag_id); + // Timing Advance subheader + /* This was done only when timing_advance_cmd != 31 + // now TA is always send when ta_timer resets regardless of its value + // this is done to avoid issues with the timeAlignmentTimer which is + // supposed to monitor if the UE received TA or not */ + if (gNB->ta_len) { + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_TA_COMMAND; + //last_size = 1; + mac_pdu_ptr++; - mac_ce_size = sizeof(NR_MAC_CE_TA); + // TA MAC CE (1 octet) + timing_advance_cmd = gNB->ta_command; + AssertFatal(timing_advance_cmd < 64, "timing_advance_cmd %d > 63\n", timing_advance_cmd); + ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND = timing_advance_cmd; //(timing_advance_cmd+31)&0x3f; + if (gNB->tag->tag_Id != 0) { + tag_id = gNB->tag->tag_Id; + ((NR_MAC_CE_TA *) ce_ptr)->TAGID = tag_id; + } - // Copying bytes for MAC CEs to the mac pdu pointer - memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); - ce_ptr += mac_ce_size; - mac_pdu_ptr += (unsigned char) mac_ce_size; - } + LOG_D(MAC, "NR MAC CE timing advance command = %d (%d) TAG ID = %d\n", timing_advance_cmd, ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND, tag_id); - // Contention resolution fixed subheader and MAC CE - if (ue_cont_res_id) { - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_CON_RES_ID; - mac_pdu_ptr++; - //last_size = 1; + mac_ce_size = sizeof(NR_MAC_CE_TA); - // contention resolution identity MAC ce has a fixed 48 bit size - // this contains the UL CCCH SDU. If UL CCCH SDU is longer than 48 bits, - // it contains the first 48 bits of the UL CCCH SDU - LOG_T(MAC, "[gNB ][RAPROC] Generate contention resolution msg: %x.%x.%x.%x.%x.%x\n", - ue_cont_res_id[0], ue_cont_res_id[1], ue_cont_res_id[2], - ue_cont_res_id[3], ue_cont_res_id[4], ue_cont_res_id[5]); + // Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); + ce_ptr += mac_ce_size; + mac_pdu_ptr += (unsigned char) mac_ce_size; + } - // Copying bytes (6 octects) to CEs pointer - mac_ce_size = 6; - memcpy(ce_ptr, ue_cont_res_id, mac_ce_size); - - // Copying bytes for MAC CEs to mac pdu pointer - memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); - ce_ptr += mac_ce_size; - mac_pdu_ptr += (unsigned char) mac_ce_size; - } + // Contention resolution fixed subheader and MAC CE + if (ue_cont_res_id) { + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_CON_RES_ID; + mac_pdu_ptr++; + //last_size = 1; - // 2) Generation of DLSCH MAC subPDUs including subheaders and MAC SDUs - for (i = 0; i < num_sdus; i++) { - LOG_D(MAC, "[gNB] Generate DLSCH header num sdu %d len sdu %d\n", num_sdus, sdu_lengths[i]); + // contention resolution identity MAC ce has a fixed 48 bit size + // this contains the UL CCCH SDU. If UL CCCH SDU is longer than 48 bits, + // it contains the first 48 bits of the UL CCCH SDU + LOG_T(MAC, "[gNB ][RAPROC] Generate contention resolution msg: %x.%x.%x.%x.%x.%x\n", + ue_cont_res_id[0], ue_cont_res_id[1], ue_cont_res_id[2], + ue_cont_res_id[3], ue_cont_res_id[4], ue_cont_res_id[5]); + + // Copying bytes (6 octects) to CEs pointer + mac_ce_size = 6; + memcpy(ce_ptr, ue_cont_res_id, mac_ce_size); + + // Copying bytes for MAC CEs to mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); + ce_ptr += mac_ce_size; + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + +#ifdef GES_SUPPORT + + //TS 38.321 Sec 6.1.3.15 TCI State indication for UE Specific PDCCH MAC CE SubPDU generation + if (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.is_scheduled) { + //filling subheader + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_TCI_STATE_IND_UE_SPEC_PDCCH; + mac_pdu_ptr++; + //Creating the instance of CE structure + NR_TCI_PDCCH nr_UESpec_TCI_StateInd_PDCCH; + //filling the CE structre + nr_UESpec_TCI_StateInd_PDCCH.CoresetId1 = ((ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0xF) >> 1; //extracting MSB 3 bits from LS nibble + nr_UESpec_TCI_StateInd_PDCCH.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.servingCellId) & 0x1F; //extracting LSB 5 Bits + nr_UESpec_TCI_StateInd_PDCCH.TciStateId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.tciStateId) & 0x7F; //extracting LSB 7 bits + nr_UESpec_TCI_StateInd_PDCCH.CoresetId2 = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0x1; //extracting LSB 1 bit + LOG_D(MAC, "NR MAC CE TCI state indication for UE Specific PDCCH = %d \n", nr_UESpec_TCI_StateInd_PDCCH.TciStateId); + mac_ce_size = sizeof(NR_TCI_PDCCH); + // Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)&nr_UESpec_TCI_StateInd_PDCCH, mac_ce_size); + //incrementing the PDU pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + + //TS 38.321 Sec 6.1.3.16, SP CSI reporting on PUCCH Activation/Deactivation MAC CE + if (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.is_scheduled) { + //filling the subheader + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_REP_PUCCH_ACT; + mac_pdu_ptr++; + //creating the instance of CE structure + NR_PUCCH_CSI_REPORTING nr_PUCCH_CSI_reportingActDeact; + //filling the CE structure + nr_PUCCH_CSI_reportingActDeact.BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.bwpId) & 0x3; //extracting LSB 2 bibs + nr_PUCCH_CSI_reportingActDeact.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.servingCellId) & 0x1F; //extracting LSB 5 bits + nr_PUCCH_CSI_reportingActDeact.S0 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[0]; + nr_PUCCH_CSI_reportingActDeact.S1 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[1]; + nr_PUCCH_CSI_reportingActDeact.S2 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[2]; + nr_PUCCH_CSI_reportingActDeact.S3 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[3]; + nr_PUCCH_CSI_reportingActDeact.R2 = 0; + mac_ce_size = sizeof(NR_PUCCH_CSI_REPORTING); + // Copying MAC CE data to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)&nr_PUCCH_CSI_reportingActDeact, mac_ce_size); + //incrementing the PDU pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + + //TS 38.321 Sec 6.1.3.14, TCI State activation/deactivation for UE Specific PDSCH MAC CE + if (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.is_scheduled) { + //Computing the number of octects to be allocated for Flexible array member + //of MAC CE structure + uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.highestTciStateActivated) / 8 + 1; //Calculating the number of octects for allocating the memory + + //filling the subheader + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_TCI_STATE_ACT_UE_SPEC_PDSCH; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + last_size = 2; + //Incrementing the PDU pointer + mac_pdu_ptr += last_size; + //allocating memory for CE Structure + NR_TCI_PDSCH_APERIODIC_CSI *nr_UESpec_TCI_StateInd_PDSCH = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //initializing to zero + memset((void *)nr_UESpec_TCI_StateInd_PDSCH, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //filling the CE Structure + nr_UESpec_TCI_StateInd_PDSCH->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.bwpId) & 0x3; //extracting LSB 2 Bits + nr_UESpec_TCI_StateInd_PDSCH->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.servingCellId) & 0x1F; //extracting LSB 5 bits + for(i = 0; i < (num_octects * 8); i++) { + if(ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.tciStateActDeact[i]) + nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] = nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] | (1 << (i % 8)); + } + mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + //Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)nr_UESpec_TCI_StateInd_PDSCH, mac_ce_size); + //incrementing the mac pdu pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + //freeing the allocated memory + free(nr_UESpec_TCI_StateInd_PDSCH); + } + + //TS38.321 Sec 6.1.3.13 Aperiodic CSI Trigger State Subselection MAC CE + if (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.is_scheduled) { + //Computing the number of octects to be allocated for Flexible array member + //of MAC CE structure + uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.highestTriggerStateSelected) / 8 + 1; //Calculating the number of octects for allocating the memory + + //filling the subheader + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_APERIODIC_CSI_TRI_STATE_SUBSEL; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + last_size = 2; + //Incrementing the PDU pointer + mac_pdu_ptr += last_size; + //allocating memory for CE structure + NR_TCI_PDSCH_APERIODIC_CSI *nr_Aperiodic_CSI_Trigger = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //initializing to zero + memset((void *)nr_Aperiodic_CSI_Trigger, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //filling the CE Structure + nr_Aperiodic_CSI_Trigger->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.bwpId) & 0x3; //extracting LSB 2 bits + nr_Aperiodic_CSI_Trigger->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.servingCellId) & 0x1F; //extracting LSB 5 bits + nr_Aperiodic_CSI_Trigger->R = 0; + for(i = 0; i < (num_octects * 8); i++) { + if(ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.triggerStateSelection[i]) + nr_Aperiodic_CSI_Trigger->T[i / 8] = nr_Aperiodic_CSI_Trigger->T[i / 8] | (1 << (i % 8)); + } + mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + // Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)nr_Aperiodic_CSI_Trigger, mac_ce_size); + //incrementing the mac pdu pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + //freeing the allocated memory + free(nr_Aperiodic_CSI_Trigger); + } + + if (ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.is_scheduled) { + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_SP_ZP_CSI_RS_RES_SET_ACT; + mac_pdu_ptr++; + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->A_D = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.act_deact; + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CELLID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id & 0x1F; //5 bits + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->BWPID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid & 0x3; //2 bits + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CSIRS_RSC_ID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id & 0xF; //4 bits + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->R = 0; + LOG_D(MAC, "NR MAC CE of ZP CSIRS Serv cell ID = %d BWPID= %d Rsc set ID = %d\n", ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id, ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid, ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id); + mac_ce_size = sizeof(NR_MAC_CE_SP_ZP_CSI_RS_RES_SET); + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + + if (ue_sched_ctl->UE_mac_ce_ctrl.csi_im.is_scheduled) { + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT; + mac_pdu_ptr++; + CSI_RS_CSI_IM_ACT_DEACT_MAC_CE csi_rs_im_act_deact_ce; + csi_rs_im_act_deact_ce.A_D = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.act_deact; + csi_rs_im_act_deact_ce.SCID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.serv_cellid & 0x3F;//gNB_PHY -> ssb_pdu.ssb_pdu_rel15.PhysCellId; + csi_rs_im_act_deact_ce.BWP_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.bwp_id; + csi_rs_im_act_deact_ce.R1 = 0; + csi_rs_im_act_deact_ce.IM = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.im;// IF set CSI IM Rsc id will presesent else CSI IM RSC ID is abscent + csi_rs_im_act_deact_ce.SP_CSI_RSID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nzp_csi_rsc_id; + + if ( csi_rs_im_act_deact_ce.IM ) { //is_scheduled if IM is 1 else this field will not present + csi_rs_im_act_deact_ce.R2 = 0; + csi_rs_im_act_deact_ce.SP_CSI_IMID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.csi_im_rsc_id; + mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE ); + } else { + mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE ) - 1; + } + + memcpy ((void *) mac_pdu_ptr, (void *) & ( csi_rs_im_act_deact_ce), mac_ce_size); + mac_pdu_ptr += (unsigned char) mac_ce_size; + + if (csi_rs_im_act_deact_ce.A_D ) { //Following IE is_scheduled only if A/D is 1 + mac_ce_size = sizeof ( struct TCI_S); + + for ( i = 0; i < ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nb_tci_resource_set_id; i++) { + csi_rs_im_act_deact_ce.TCI_STATE.R = 0; + csi_rs_im_act_deact_ce.TCI_STATE.TCI_STATE_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.tci_state_id [i] & 0x7F; + memcpy ((void *) mac_pdu_ptr, (void *) & (csi_rs_im_act_deact_ce.TCI_STATE), mac_ce_size); + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + + } + } + +#endif + + // 2) Generation of DLSCH MAC subPDUs including subheaders and MAC SDUs + for (i = 0; i < num_sdus; i++) { + LOG_D(MAC, "[gNB] Generate DLSCH header num sdu %d len sdu %d\n", num_sdus, sdu_lengths[i]); + + if (sdu_lengths[i] < 128) { + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = sdu_lcids[i]; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = (unsigned char) sdu_lengths[i]; + last_size = 2; + } else { + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->F = 1; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->LCID = sdu_lcids[i]; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L1 = ((unsigned short) sdu_lengths[i] >> 8) & 0x7f; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L2 = (unsigned short) sdu_lengths[i] & 0xff; + last_size = 3; + } + + mac_pdu_ptr += last_size; + + // 3) cycle through SDUs, compute each relevant and place dlsch_buffer in + memcpy((void *) mac_pdu_ptr, (void *) dlsch_buffer_ptr, sdu_lengths[i]); + dlsch_buffer_ptr += sdu_lengths[i]; + mac_pdu_ptr += sdu_lengths[i]; + } + + // 4) Compute final offset for padding + if (post_padding > 0) { + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_PADDING; + mac_pdu_ptr++; - if (sdu_lengths[i] < 128) { - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = sdu_lcids[i]; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = (unsigned char) sdu_lengths[i]; - last_size = 2; } else { - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->F = 1; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->LCID = sdu_lcids[i]; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L1 = ((unsigned short) sdu_lengths[i] >> 8) & 0x7f; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L2 = (unsigned short) sdu_lengths[i] & 0xff; - last_size = 3; + // no MAC subPDU with padding } - mac_pdu_ptr += last_size; + // compute final offset + offset = ((unsigned char *) mac_pdu_ptr - mac_pdu); - // 3) cycle through SDUs, compute each relevant and place dlsch_buffer in - memcpy((void *) mac_pdu_ptr, (void *) dlsch_buffer_ptr, sdu_lengths[i]); - dlsch_buffer_ptr+= sdu_lengths[i]; - mac_pdu_ptr += sdu_lengths[i]; - } + //printf("Offset %d \n", ((unsigned char *) mac_pdu_ptr - mac_pdu)); - // 4) Compute final offset for padding - if (post_padding > 0) { - ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_PADDING; - mac_pdu_ptr++; - - } else { - // no MAC subPDU with padding - } - - // compute final offset - offset = ((unsigned char *) mac_pdu_ptr - mac_pdu); - - //printf("Offset %d \n", ((unsigned char *) mac_pdu_ptr - mac_pdu)); - - return offset; + return offset; } /* functionalities of this function have been moved to nr_schedule_uss_dlsch_phytest */ -void nr_schedule_ue_spec(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ +void nr_schedule_ue_spec(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) { } diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index 7647b08939..7825d72fdb 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -76,254 +76,325 @@ #define NR_NB_RA_PROC_MAX 4 typedef enum { - RA_IDLE = 0, - Msg2 = 1, - WAIT_Msg3 = 2, - Msg4 = 3, - WAIT_Msg4_ACK = 4 + RA_IDLE = 0, + Msg2 = 1, + WAIT_Msg3 = 2, + Msg4 = 3, + WAIT_Msg4_ACK = 4 } RA_gNB_state_t; /*! \brief gNB template for the Random access information */ typedef struct { - /// Flag to indicate this process is active - RA_gNB_state_t state; - /// BWP id of RA process - int bwp_id; - /// CORESET0 configured flag - int coreset0_configured; - /// Slot where preamble was received - uint8_t preamble_slot; - /// Subframe where Msg2 is to be sent - uint8_t Msg2_slot; - /// Frame where Msg2 is to be sent - frame_t Msg2_frame; - /// Subframe where Msg3 is to be sent - sub_frame_t Msg3_slot; - /// Frame where Msg3 is to be sent - frame_t Msg3_frame; - /// Msg3 time domain allocation index - uint8_t Msg3_tda_id; - /// Subframe where Msg4 is to be sent - sub_frame_t Msg4_slot; - /// Frame where Msg4 is to be sent - frame_t Msg4_frame; - /// harq_pid used for Msg4 transmission - uint8_t harq_pid; - /// UE RNTI allocated during RAR - rnti_t rnti; - /// RA RNTI allocated from received PRACH - uint16_t RA_rnti; - /// Received preamble_index - uint8_t preamble_index; - /// Received UE Contention Resolution Identifier - uint8_t cont_res_id[6]; - /// Timing offset indicated by PHY - int16_t timing_offset; - /// Timeout for RRC connection - int16_t RRC_timer; - /// Msg3 first RB - uint8_t msg3_first_rb; - /// Msg3 number of RB - uint8_t msg3_nb_rb; - /// Msg3 TPC command - uint8_t msg3_TPC; - /// Msg3 ULdelay command - uint8_t msg3_ULdelay; - /// Msg3 cqireq command - uint8_t msg3_cqireq; - /// Round of Msg3 HARQ - uint8_t msg3_round; - /// Msg3 pusch pdu - nfapi_nr_pusch_pdu_t pusch_pdu; - /// TBS used for Msg4 - int msg4_TBsize; - /// MCS used for Msg4 - int msg4_mcs; - /// RA search space - NR_SearchSpace_t *ra_ss; + /// Flag to indicate this process is active + RA_gNB_state_t state; + /// BWP id of RA process + int bwp_id; + /// CORESET0 configured flag + int coreset0_configured; + /// Slot where preamble was received + uint8_t preamble_slot; + /// Subframe where Msg2 is to be sent + uint8_t Msg2_slot; + /// Frame where Msg2 is to be sent + frame_t Msg2_frame; + /// Subframe where Msg3 is to be sent + sub_frame_t Msg3_slot; + /// Frame where Msg3 is to be sent + frame_t Msg3_frame; + /// Msg3 time domain allocation index + uint8_t Msg3_tda_id; + /// Subframe where Msg4 is to be sent + sub_frame_t Msg4_slot; + /// Frame where Msg4 is to be sent + frame_t Msg4_frame; + /// harq_pid used for Msg4 transmission + uint8_t harq_pid; + /// UE RNTI allocated during RAR + rnti_t rnti; + /// RA RNTI allocated from received PRACH + uint16_t RA_rnti; + /// Received preamble_index + uint8_t preamble_index; + /// Received UE Contention Resolution Identifier + uint8_t cont_res_id[6]; + /// Timing offset indicated by PHY + int16_t timing_offset; + /// Timeout for RRC connection + int16_t RRC_timer; + /// Msg3 first RB + uint8_t msg3_first_rb; + /// Msg3 number of RB + uint8_t msg3_nb_rb; + /// Msg3 TPC command + uint8_t msg3_TPC; + /// Msg3 ULdelay command + uint8_t msg3_ULdelay; + /// Msg3 cqireq command + uint8_t msg3_cqireq; + /// Round of Msg3 HARQ + uint8_t msg3_round; + /// Msg3 pusch pdu + nfapi_nr_pusch_pdu_t pusch_pdu; + /// TBS used for Msg4 + int msg4_TBsize; + /// MCS used for Msg4 + int msg4_mcs; + /// RA search space + NR_SearchSpace_t *ra_ss; } NR_RA_t; /*! \brief gNB common channels */ typedef struct { - int physCellId; - int p_gNB; - int Ncp; - int nr_band; - lte_frame_type_t frame_type; - uint64_t dl_CarrierFreq; - NR_BCCH_BCH_Message_t *mib; - NR_ServingCellConfigCommon_t *ServingCellConfigCommon; - NR_ARFCN_ValueEUTRA_t ul_CarrierFreq; - long ul_Bandwidth; - /// Outgoing MIB PDU for PHY - MIB_PDU MIB_pdu; - /// Outgoing BCCH pdu for PHY - BCCH_PDU BCCH_pdu; - /// Outgoing BCCH DCI allocation - uint32_t BCCH_alloc_pdu; - /// Outgoing CCCH pdu for PHY - CCCH_PDU CCCH_pdu; - /// Outgoing PCCH DCI allocation - uint32_t PCCH_alloc_pdu; - /// Outgoing PCCH pdu for PHY - PCCH_PDU PCCH_pdu; - /// Outgoing RAR pdu for PHY - RAR_PDU RAR_pdu; - /// Template for RA computations - NR_RA_t ra[NR_NB_RA_PROC_MAX]; - /// VRB map for common channels - uint8_t vrb_map[100]; - /// VRB map for common channels and retransmissions by PHICH - uint8_t vrb_map_UL[100]; - /// number of subframe allocation pattern available for MBSFN sync area - uint8_t num_sf_allocation_pattern; + int physCellId; + int p_gNB; + int Ncp; + int nr_band; + lte_frame_type_t frame_type; + uint64_t dl_CarrierFreq; + NR_BCCH_BCH_Message_t *mib; + NR_ServingCellConfigCommon_t *ServingCellConfigCommon; + NR_ARFCN_ValueEUTRA_t ul_CarrierFreq; + long ul_Bandwidth; + /// Outgoing MIB PDU for PHY + MIB_PDU MIB_pdu; + /// Outgoing BCCH pdu for PHY + BCCH_PDU BCCH_pdu; + /// Outgoing BCCH DCI allocation + uint32_t BCCH_alloc_pdu; + /// Outgoing CCCH pdu for PHY + CCCH_PDU CCCH_pdu; + /// Outgoing PCCH DCI allocation + uint32_t PCCH_alloc_pdu; + /// Outgoing PCCH pdu for PHY + PCCH_PDU PCCH_pdu; + /// Outgoing RAR pdu for PHY + RAR_PDU RAR_pdu; + /// Template for RA computations + NR_RA_t ra[NR_NB_RA_PROC_MAX]; + /// VRB map for common channels + uint8_t vrb_map[100]; + /// VRB map for common channels and retransmissions by PHICH + uint8_t vrb_map_UL[100]; + /// number of subframe allocation pattern available for MBSFN sync area + uint8_t num_sf_allocation_pattern; } NR_COMMON_channels_t; +#ifdef GES_SUPPORT + +// SP ZP CSI-RS Resource Set Activation/Deactivation MAC CE +typedef struct sp_zp_csirs { + bool is_scheduled; //ZP CSI-RS ACT/Deact MAC CE is scheduled + bool act_deact; //Activation/Deactivation indication + uint8_t serv_cell_id; //Identity of Serving cell for which MAC CE applies + uint8_t bwpid; //Downlink BWP id + uint8_t rsc_id; //SP ZP CSI-RS resource set +} sp_zp_csirs_t; + +//SP CSI-RS / CSI-IM Resource Set Activation/Deactivation MAC CE +#define MAX_CSI_RESOURCE_SET 64 +typedef struct csi_rs_im { + bool is_scheduled; + bool act_deact; + uint8_t serv_cellid; + uint8_t bwp_id; + bool im; + uint8_t csi_im_rsc_id; + uint8_t nzp_csi_rsc_id; + uint8_t nb_tci_resource_set_id; + uint8_t tci_state_id [ MAX_CSI_RESOURCE_SET ]; +} csi_rs_im_t; + +typedef struct pdcchStateInd { + bool is_scheduled; + uint8_t servingCellId; + uint8_t coresetId; + uint8_t tciStateId; +} pdcchStateInd_t; + +typedef struct SPCSIReportingpucch { + bool is_scheduled; + uint8_t servingCellId; + uint8_t bwpId; + bool s0tos3_actDeact[4]; +} SPCSIReportingpucch_t; + +#define MAX_APERIODIC_TRIGGER_STATES 128 //38.331 +typedef struct aperiodicCSI_triggerStateSelection { + bool is_scheduled; + uint8_t servingCellId; + uint8_t bwpId; + uint8_t highestTriggerStateSelected; + bool triggerStateSelection[MAX_APERIODIC_TRIGGER_STATES]; +} aperiodicCSI_triggerStateSelection_t; + +#define MAX_TCI_STATES 128 //38.331 +typedef struct pdschTciStatesActDeact { + bool is_scheduled; + uint8_t servingCellId; + uint8_t bwpId; + uint8_t highestTciStateActivated; + bool tciStateActDeact[MAX_TCI_STATES]; +} pdschTciStatesActDeact_t; + +typedef struct UE_info { + sp_zp_csirs_t sp_zp_csi_rs; + csi_rs_im_t csi_im; + pdcchStateInd_t pdcch_state_ind; + SPCSIReportingpucch_t SP_CSI_reporting_pucch; + aperiodicCSI_triggerStateSelection_t aperi_CSI_trigger; + pdschTciStatesActDeact_t pdsch_TCI_States_ActDeact; +} NR_UE_mac_ce_ctrl_t; + +#endif + /*! \brief scheduling control information set through an API (not used)*/ typedef struct { - int dummy; + int dummy; +#ifdef GES_SUPPORT + NR_UE_mac_ce_ctrl_t UE_mac_ce_ctrl;// MAC CE related information +#endif } NR_UE_sched_ctrl_t; /*! \brief UE list used by gNB to order UEs/CC for scheduling*/ typedef struct { - DLSCH_PDU DLSCH_pdu[4][MAX_MOBILES_PER_GNB]; - /// scheduling control info - UE_sched_ctrl_t UE_sched_ctrl[MAX_MOBILES_PER_GNB]; - int next[MAX_MOBILES_PER_GNB]; - int head; - int next_ul[MAX_MOBILES_PER_GNB]; - int head_ul; - int avail; - int num_UEs; - boolean_t active[MAX_MOBILES_PER_GNB]; - rnti_t rnti[MAX_MOBILES_PER_GNB]; - NR_CellGroupConfig_t *secondaryCellGroup[MAX_MOBILES_PER_GNB]; + DLSCH_PDU DLSCH_pdu[4][MAX_MOBILES_PER_GNB]; + /// scheduling control info + UE_sched_ctrl_t UE_sched_ctrl[MAX_MOBILES_PER_GNB]; + int next[MAX_MOBILES_PER_GNB]; + int head; + int next_ul[MAX_MOBILES_PER_GNB]; + int head_ul; + int avail; + int num_UEs; + boolean_t active[MAX_MOBILES_PER_GNB]; + rnti_t rnti[MAX_MOBILES_PER_GNB]; + NR_CellGroupConfig_t *secondaryCellGroup[MAX_MOBILES_PER_GNB]; } NR_UE_list_t; /*! \brief top level eNB MAC structure */ typedef struct gNB_MAC_INST_s { - /// Ethernet parameters for northbound midhaul interface - eth_params_t eth_params_n; - /// Ethernet parameters for fronthaul interface - eth_params_t eth_params_s; - /// Module - module_id_t Mod_id; - /// frame counter - frame_t frame; - /// slot counter - int slot; - /// timing advance group - NR_TAG_t *tag; - /// Pointer to IF module instance for PHY - NR_IF_Module_t *if_inst; - /// TA command - int ta_command; - /// MAC CE flag indicating TA length - int ta_len; - /// Common cell resources - NR_COMMON_channels_t common_channels[NFAPI_CC_MAX]; - /// current PDU index (BCH,DLSCH) - uint16_t pdu_index[NFAPI_CC_MAX]; + /// Ethernet parameters for northbound midhaul interface + eth_params_t eth_params_n; + /// Ethernet parameters for fronthaul interface + eth_params_t eth_params_s; + /// Module + module_id_t Mod_id; + /// frame counter + frame_t frame; + /// slot counter + int slot; + /// timing advance group + NR_TAG_t *tag; + /// Pointer to IF module instance for PHY + NR_IF_Module_t *if_inst; + /// TA command + int ta_command; + /// MAC CE flag indicating TA length + int ta_len; + /// Common cell resources + NR_COMMON_channels_t common_channels[NFAPI_CC_MAX]; + /// current PDU index (BCH,DLSCH) + uint16_t pdu_index[NFAPI_CC_MAX]; - /// NFAPI Config Request Structure - nfapi_nr_config_request_scf_t config[NFAPI_CC_MAX]; - /// NFAPI DL Config Request Structure - nfapi_nr_dl_tti_request_t DL_req[NFAPI_CC_MAX]; - /// NFAPI UL TTI Request Structure (this is from the new SCF specs) - nfapi_nr_ul_tti_request_t UL_tti_req[NFAPI_CC_MAX]; - /// NFAPI HI/DCI0 Config Request Structure - nfapi_nr_ul_dci_request_t UL_dci_req[NFAPI_CC_MAX]; - /// NFAPI DL PDU structure - nfapi_nr_tx_data_request_t TX_req[NFAPI_CC_MAX]; + /// NFAPI Config Request Structure + nfapi_nr_config_request_scf_t config[NFAPI_CC_MAX]; + /// NFAPI DL Config Request Structure + nfapi_nr_dl_tti_request_t DL_req[NFAPI_CC_MAX]; + /// NFAPI UL TTI Request Structure (this is from the new SCF specs) + nfapi_nr_ul_tti_request_t UL_tti_req[NFAPI_CC_MAX]; + /// NFAPI HI/DCI0 Config Request Structure + nfapi_nr_ul_dci_request_t UL_dci_req[NFAPI_CC_MAX]; + /// NFAPI DL PDU structure + nfapi_nr_tx_data_request_t TX_req[NFAPI_CC_MAX]; - NR_UE_list_t UE_list; + NR_UE_list_t UE_list; - /// UL handle - uint32_t ul_handle; + /// UL handle + uint32_t ul_handle; // MAC function execution peformance profiler - /// processing time of eNB scheduler - time_stats_t eNB_scheduler; - /// processing time of eNB scheduler for SI - time_stats_t schedule_si; - /// processing time of eNB scheduler for Random access - time_stats_t schedule_ra; - /// processing time of eNB ULSCH scheduler - time_stats_t schedule_ulsch; - /// processing time of eNB DCI generation - time_stats_t fill_DLSCH_dci; - /// processing time of eNB MAC preprocessor - time_stats_t schedule_dlsch_preprocessor; - /// processing time of eNB DLSCH scheduler - time_stats_t schedule_dlsch; // include rlc_data_req + MAC header + preprocessor - /// processing time of eNB MCH scheduler - time_stats_t schedule_mch; - /// processing time of eNB ULSCH reception - time_stats_t rx_ulsch_sdu; // include rlc_data_ind - /// processing time of eNB PCH scheduler - time_stats_t schedule_pch; - /// CCE lists - int cce_list[MAX_NUM_BWP][MAX_NUM_CORESET][MAX_NUM_CCE]; + /// processing time of eNB scheduler + time_stats_t eNB_scheduler; + /// processing time of eNB scheduler for SI + time_stats_t schedule_si; + /// processing time of eNB scheduler for Random access + time_stats_t schedule_ra; + /// processing time of eNB ULSCH scheduler + time_stats_t schedule_ulsch; + /// processing time of eNB DCI generation + time_stats_t fill_DLSCH_dci; + /// processing time of eNB MAC preprocessor + time_stats_t schedule_dlsch_preprocessor; + /// processing time of eNB DLSCH scheduler + time_stats_t schedule_dlsch; // include rlc_data_req + MAC header + preprocessor + /// processing time of eNB MCH scheduler + time_stats_t schedule_mch; + /// processing time of eNB ULSCH reception + time_stats_t rx_ulsch_sdu; // include rlc_data_ind + /// processing time of eNB PCH scheduler + time_stats_t schedule_pch; + /// CCE lists + int cce_list[MAX_NUM_BWP][MAX_NUM_CORESET][MAX_NUM_CCE]; } gNB_MAC_INST; typedef struct { - uint8_t format_indicator; //1 bit - uint16_t frequency_domain_assignment; //up to 16 bits - uint8_t time_domain_assignment; // 4 bits - uint8_t frequency_hopping_flag; //1 bit + uint8_t format_indicator; //1 bit + uint16_t frequency_domain_assignment; //up to 16 bits + uint8_t time_domain_assignment; // 4 bits + uint8_t frequency_hopping_flag; //1 bit - uint8_t ra_preamble_index; //6 bits - uint8_t ss_pbch_index; //6 bits - uint8_t prach_mask_index; //4 bits + uint8_t ra_preamble_index; //6 bits + uint8_t ss_pbch_index; //6 bits + uint8_t prach_mask_index; //4 bits - uint8_t vrb_to_prb_mapping; //0 or 1 bit - uint8_t mcs; //5 bits - uint8_t ndi; //1 bit - uint8_t rv; //2 bits - uint8_t harq_pid; //4 bits - uint8_t dai; //0, 2 or 4 bits - uint8_t dai1; //1 or 2 bits - uint8_t dai2; //0 or 2 bits - uint8_t tpc; //2 bits - uint8_t pucch_resource_indicator; //3 bits - uint8_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits + uint8_t vrb_to_prb_mapping; //0 or 1 bit + uint8_t mcs; //5 bits + uint8_t ndi; //1 bit + uint8_t rv; //2 bits + uint8_t harq_pid; //4 bits + uint8_t dai; //0, 2 or 4 bits + uint8_t dai1; //1 or 2 bits + uint8_t dai2; //0 or 2 bits + uint8_t tpc; //2 bits + uint8_t pucch_resource_indicator; //3 bits + uint8_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits - uint8_t short_messages_indicator; //2 bits - uint8_t short_messages; //8 bits - uint8_t tb_scaling; //2 bits + uint8_t short_messages_indicator; //2 bits + uint8_t short_messages; //8 bits + uint8_t tb_scaling; //2 bits - uint8_t carrier_indicator; //0 or 3 bits - uint8_t bwp_indicator; //0, 1 or 2 bits - uint8_t prb_bundling_size_indicator; //0 or 1 bits - uint8_t rate_matching_indicator; //0, 1 or 2 bits - uint8_t zp_csi_rs_trigger; //0, 1 or 2 bits - uint8_t transmission_configuration_indication; //0 or 3 bits - uint8_t srs_request; //2 bits - uint8_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits - uint8_t cbgfi; //CBG Flushing Out Information: 0 or 1 bit - uint8_t dmrs_sequence_initialization; //0 or 1 bit + uint8_t carrier_indicator; //0 or 3 bits + uint8_t bwp_indicator; //0, 1 or 2 bits + uint8_t prb_bundling_size_indicator; //0 or 1 bits + uint8_t rate_matching_indicator; //0, 1 or 2 bits + uint8_t zp_csi_rs_trigger; //0, 1 or 2 bits + uint8_t transmission_configuration_indication; //0 or 3 bits + uint8_t srs_request; //2 bits + uint8_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits + uint8_t cbgfi; //CBG Flushing Out Information: 0 or 1 bit + uint8_t dmrs_sequence_initialization; //0 or 1 bit - uint8_t srs_resource_indicator; - uint8_t precoding_information; - uint8_t csi_request; - uint8_t ptrs_dmrs_association; - uint8_t beta_offset_indicator; //0 or 2 bits + uint8_t srs_resource_indicator; + uint8_t precoding_information; + uint8_t csi_request; + uint8_t ptrs_dmrs_association; + uint8_t beta_offset_indicator; //0 or 2 bits - uint8_t slot_format_indicator_count; - uint8_t *slot_format_indicators; + uint8_t slot_format_indicator_count; + uint8_t *slot_format_indicators; - uint8_t pre_emption_indication_count; - uint16_t *pre_emption_indications; //14 bit + uint8_t pre_emption_indication_count; + uint16_t *pre_emption_indications; //14 bit - uint8_t block_number_count; - uint8_t *block_numbers; + uint8_t block_number_count; + uint8_t *block_numbers; - uint8_t ul_sul_indicator; //0 or 1 bit - uint8_t antenna_ports; + uint8_t ul_sul_indicator; //0 or 1 bit + uint8_t antenna_ports; - uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits - uint16_t padding; + uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits + uint16_t padding; } dci_pdu_rel15_t; From fe5cd3d28d376dbc53c63c97dff18faa3991701c Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Tue, 26 May 2020 00:04:49 +0200 Subject: [PATCH 263/553] fixed bug for long PRACH sequence configuration, flipped HARQ bits for 2-bit PUCCH0 UCI report --- openair1/PHY/NR_TRANSPORT/pucch_rx.c | 4 ++-- openair1/SCHED_NR_UE/pucch_uci_ue_nr.c | 8 +++++--- openair1/SIMULATION/NR_PHY/ulsim.c | 1 + openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 2 +- 4 files changed, 9 insertions(+), 6 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/pucch_rx.c b/openair1/PHY/NR_TRANSPORT/pucch_rx.c index 177217d23f..d3943f5265 100644 --- a/openair1/PHY/NR_TRANSPORT/pucch_rx.c +++ b/openair1/PHY/NR_TRANSPORT/pucch_rx.c @@ -409,8 +409,8 @@ void nr_decode_pucch0(PHY_VARS_gNB *gNB, uci_pdu->harq->harq_confidence_level = xrtmag_dB-(gNB->measurements.n0_subband_power_tot_dB[pucch_pdu->prb_start]+gNB->pucch0_thres); uci_pdu->harq->harq_list = (nfapi_nr_harq_t*)malloc(2); - uci_pdu->harq->harq_list[0].harq_value = index&0x01; - uci_pdu->harq->harq_list[1].harq_value = (index>>1)&0x01; + uci_pdu->harq->harq_list[1].harq_value = index&0x01; + uci_pdu->harq->harq_list[0].harq_value = (index>>1)&0x01; if (pucch_pdu->sr_flag == 1) { uci_pdu->sr = calloc(1,sizeof(*uci_pdu->sr)); diff --git a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c index 12992a3a57..a2452248b8 100644 --- a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c +++ b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c @@ -198,7 +198,7 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ /* update current context */ - int subframe_number = (proc->nr_tti_rx)/(ue->frame_parms.ttis_per_subframe); + int subframe_number = (proc->nr_tti_rx)/(ue->frame_parms.slots_per_subframe);//ttis_per_subframe); nb_pucch_format_4_in_subframes[subframe_number] = 0; /* reset pucch format 4 counter at current rx position */ int dl_harq_pid = ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->current_harq_pid; @@ -439,7 +439,7 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ } nb_symbols = nb_symbols_excluding_dmrs[nb_symbols_total-4][index_additional_dmrs][index_hopping]; nb_of_prbs = 1; - subframe_number = nr_tti_tx/(ue->frame_parms.ttis_per_subframe); + subframe_number = nr_tti_tx/(ue->frame_parms.slots_per_subframe);//ttis_per_subframe); nb_pucch_format_4_in_subframes[subframe_number]++; /* increment number of transmit pucch 4 in current subframe */ NR_TST_PHY_PRINTF("PUCCH Number of pucch format 4 in subframe %d is %d \n", subframe_number, nb_pucch_format_4_in_subframes[subframe_number]); N_sc_ctrl_RB = N_SC_RB/(nb_pucch_format_4_in_subframes[subframe_number]); @@ -698,6 +698,8 @@ uint8_t get_downlink_ack(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_t int V_DAI_m_DL = 0; NR_UE_MAC_INST_t *mac = get_mac_inst(0); + if (mac->DLbwp[0] == NULL) return; + if (mac->DLbwp[0]->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI[0] == 2) { two_transport_blocks = TRUE; number_of_code_word = 2; @@ -1205,7 +1207,7 @@ int trigger_periodic_scheduling_request(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_n return (1); /* period is slot */ } - int16_t N_slot_frame = NR_NUMBER_OF_SUBFRAMES_PER_FRAME * ue->frame_parms.ttis_per_subframe; + int16_t N_slot_frame = NR_NUMBER_OF_SUBFRAMES_PER_FRAME * ue->frame_parms.slots_per_subframe;//ttis_per_subframe; if (((proc->frame_tx * N_slot_frame) + proc->nr_tti_tx - SR_offset)%SR_periodicity == 0) { return (1); } diff --git a/openair1/SIMULATION/NR_PHY/ulsim.c b/openair1/SIMULATION/NR_PHY/ulsim.c index 840eaa9ffe..d2c713ab7d 100644 --- a/openair1/SIMULATION/NR_PHY/ulsim.c +++ b/openair1/SIMULATION/NR_PHY/ulsim.c @@ -747,6 +747,7 @@ int main(int argc, char **argv) ((int16_t*)&gNB->common_vars.rxdata[0][slot_offset])[i], ((int16_t*)&gNB->common_vars.rxdata[0][slot_offset])[1+i]); fclose(input_fd); + LOG_M("rxsig0.m","rx0",gNB->common_vars.rxdata[0][slot_offset],slot_length,1,1); } //////////////////////////////////////////////////////////// diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index 5adcf42560..ed7a3b8c78 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -1065,7 +1065,7 @@ uint8_t compute_nr_root_seq(NR_RACH_ConfigCommon_t *rach_config, uint8_t ncs_index = rach_config->rach_ConfigGeneric.zeroCorrelationZoneConfig; uint16_t format0 = get_format0(config_index, unpaired); uint16_t NCS = get_NCS(ncs_index, format0, rach_config->restrictedSetConfig); - uint16_t L_ra = (rach_config->prach_RootSequenceIndex.present) ? 139 : 839; + uint16_t L_ra = (rach_config->prach_RootSequenceIndex.present==NR_RACH_ConfigCommon__prach_RootSequenceIndex_PR_l139) ? 139 : 839; uint16_t r,u,index,q,d_u,n_shift_ra,n_shift_ra_bar,d_start; uint32_t w; uint8_t found_preambles = 0; From d37f077082afc95de7f95b0ef3b96267037d211d Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Tue, 26 May 2020 00:22:48 +0200 Subject: [PATCH 264/553] handling failed ack/nack reception --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 1 + openair2/LAYER2/NR_MAC_gNB/main.c | 1 + openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 1 + openair2/NR_PHY_INTERFACE/NR_IF_Module.c | 11 +++++++++++ 4 files changed, 14 insertions(+) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index bc435ec047..0167a5579b 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -378,6 +378,7 @@ int configure_fapi_dl_pdu(int Mod_idP, // PDSCH to HARQ TI dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator.val = pucch_sched->timing_indicator; UE_list->UE_sched_ctrl[UE_id].harq_processes[current_harq_pid].feedback_slot = pucch_sched->ul_slot; + UE_list->UE_sched_ctrl[UE_id].harq_processes[current_harq_pid].is_waiting = 1; // antenna ports dci_pdu_rel15[0].antenna_ports.val = 0; // nb of cdm groups w/o data 1 and dmrs port 0 diff --git a/openair2/LAYER2/NR_MAC_gNB/main.c b/openair2/LAYER2/NR_MAC_gNB/main.c index 669bc1cd5a..56e020838d 100644 --- a/openair2/LAYER2/NR_MAC_gNB/main.c +++ b/openair2/LAYER2/NR_MAC_gNB/main.c @@ -116,6 +116,7 @@ void mac_top_init_gNB(void) for (int list_harq = 0; list_harq < NR_MAX_NB_HARQ_PROCESSES; list_harq++) { UE_list->UE_sched_ctrl[list_el].harq_processes[list_harq].round = 0; UE_list->UE_sched_ctrl[list_el].harq_processes[list_harq].ndi = 0; + UE_list->UE_sched_ctrl[list_el].harq_processes[list_harq].is_waiting = 0; } } diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index c5ef191506..0125535071 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -188,6 +188,7 @@ typedef struct NR_sched_pucch { } NR_sched_pucch; typedef struct NR_UE_harq { + uint8_t is_waiting; uint8_t ndi; uint8_t round; uint16_t feedback_slot; diff --git a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c index 58a8171e8e..2b8dc0ec02 100644 --- a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c @@ -102,9 +102,20 @@ void handle_nr_uci(NR_UL_IND_t *UL_info, NR_UE_sched_ctrl_t *sched_ctrl) { sched_ctrl->harq_processes[harq_idx].ndi ^= 1; sched_ctrl->harq_processes[harq_idx].round = 0; } + sched_ctrl->harq_processes[harq_idx].is_waiting = 0; harq_idx_s = harq_idx + 1; break; } + // if gNB fails to receive a ACK/NACK + else if (((UL_info->slot-1) > sched_ctrl->harq_processes[harq_idx].feedback_slot) && + (sched_ctrl->harq_processes[harq_idx].is_waiting)) { + sched_ctrl->harq_processes[harq_idx].round++; + if (sched_ctrl->harq_processes[harq_idx].round == max_harq_rounds) { + sched_ctrl->harq_processes[harq_idx].ndi ^= 1; + sched_ctrl->harq_processes[harq_idx].round = 0; + } + sched_ctrl->harq_processes[harq_idx].is_waiting = 0; + } } } break; From c042f7c26af6750d6aa6d356c5517ee2481529ec Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Tue, 26 May 2020 11:40:54 +0200 Subject: [PATCH 265/553] fixed issue related to scheduing of PRACH for long sequence (only gets done in last slot of subframe now, not both) and start point of DFT in RU processing for long-sequence. Removes fatal segfault. --- openair1/PHY/NR_TRANSPORT/nr_prach.c | 10 ++++++---- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 8 ++++---- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index 2200768f47..887cc7cd84 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -150,6 +150,7 @@ void rx_nr_prach_ru(RU_t *ru, int16_t **rxsigF=NULL; NR_DL_FRAME_PARMS *fp=ru->nr_frame_parms; + int slot2=slot; int16_t *prach[ru->nb_rx]; int prach_sequence_length = ru->config.prach_config.prach_sequence_length.value; @@ -159,9 +160,10 @@ void rx_nr_prach_ru(RU_t *ru, rxsigF = ru->prach_rxsigF; AssertFatal(ru->if_south == LOCAL_RF,"we shouldn't call this if if_south != LOCAL_RF\n"); - for (int aa=0; aanb_rx; aa++) - prach[aa] = (int16_t*)&ru->common.rxdata[aa][(slot*fp->get_samples_per_slot(slot,fp))-ru->N_TA_offset]; - + for (int aa=0; aanb_rx; aa++){ + if (prach_sequence_length == 0) slot2=(slot/fp->slots_per_subframe)*fp->slots_per_subframe; + prach[aa] = (int16_t*)&ru->common.rxdata[aa][(slot2*fp->get_samples_per_slot(slot,fp))-ru->N_TA_offset]; + } int mu = fp->numerology_index; @@ -170,7 +172,7 @@ void rx_nr_prach_ru(RU_t *ru, if (prach_sequence_length == 0) { LOG_D(PHY,"PRACH (ru %d) in %d.%d, format %d, msg1_frequencyStart %d\n", - ru->idx,frame,slot,prachFormat,msg1_frequencystart); + ru->idx,frame,slot2,prachFormat,msg1_frequencystart); AssertFatal(prachFormat<4,"Illegal prach format %d for length 839\n",prachFormat); switch (prachFormat) { case 0: diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index ed7a3b8c78..37322b3d48 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -944,7 +944,7 @@ int get_nr_prach_info_from_index(uint8_t index, s_map = table_6_3_3_2_3_prachConfig_Index[index][4]; if ( (s_map>>subframe)&0x01 ) { if (mu == 1) { - if ( (table_6_3_3_2_3_prachConfig_Index[index][6] == 1) && (slot%2 == 0) ) + if ( (table_6_3_3_2_3_prachConfig_Index[index][6] <= 1) && (slot%2 == 0) ) return 0; // no prach in even slots @ 30kHz for 1 prach per subframe } if (start_symbol != NULL && N_t_slot != NULL && N_dur != NULL && format != NULL){ @@ -954,9 +954,9 @@ int get_nr_prach_info_from_index(uint8_t index, if (table_6_3_3_2_3_prachConfig_Index[index][1] != -1) format2 = (uint8_t) table_6_3_3_2_3_prachConfig_Index[index][1]; *format = ((uint8_t) table_6_3_3_2_3_prachConfig_Index[index][0]) | (format2<<8); - LOG_D(MAC,"Frame %d slot %d: Getting PRACH info from index %d absoluteFrequencyPointA %u mu %u frame_type %u start_symbol %u N_t_slot %u N_dur %u \n", frame, + LOG_D(MAC,"Frame %d slot %d: Getting PRACH info from index %d (col 6 %d) absoluteFrequencyPointA %u mu %u frame_type %u start_symbol %u N_t_slot %u N_dur %u \n", frame, slot, - index, + index, table_6_3_3_2_3_prachConfig_Index[index][6], pointa, mu, unpaired, @@ -980,7 +980,7 @@ int get_nr_prach_info_from_index(uint8_t index, s_map = table_6_3_3_2_2_prachConfig_Index[index][4]; if ( (s_map>>subframe)&0x01 ) { if (mu == 1) { - if ( (table_6_3_3_2_2_prachConfig_Index[index][6] == 1) && (slot%2 == 0) ) + if ( (table_6_3_3_2_2_prachConfig_Index[index][6] <= 1) && (slot%2 == 0) ) return 0; // no prach in even slots @ 30kHz for 1 prach per subframe } if (start_symbol != NULL && N_t_slot != NULL && N_dur != NULL && format != NULL){ From 0a45909bd1aa8a8453531d6c2624fa37297b9a1c Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Tue, 26 May 2020 15:37:10 +0200 Subject: [PATCH 266/553] minor changes --- openair1/PHY/TOOLS/oai_dfts.c | 26 +++++++++++++++++++ openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 6 ++--- 2 files changed, 29 insertions(+), 3 deletions(-) diff --git a/openair1/PHY/TOOLS/oai_dfts.c b/openair1/PHY/TOOLS/oai_dfts.c index 6ae852b127..7d3cf0d2c0 100644 --- a/openair1/PHY/TOOLS/oai_dfts.c +++ b/openair1/PHY/TOOLS/oai_dfts.c @@ -10571,6 +10571,32 @@ int main(int argc, char**argv) LOG_M("y24576.m","y24576",y,24576,1,1); LOG_M("x24576.m","x24576",x,24576,1,1); + + memset((void*)x,0,2*18432*sizeof(int32_t)); + for (i=2;i<(2*14402);i++) { + if ((taus() & 1)==0) + ((int16_t*)x)[i] = 364; + else + ((int16_t*)x)[i] = -364; + } + for (i=2*(36864-14400);i<(36864*2);i++) { + if ((taus() & 1)==0) + ((int16_t*)x)[i] = 364; + else + ((int16_t*)x)[i] = -364; + } + reset_meas(&ts); + for (i=0; i<10000; i++) { + start_meas(&ts); + idft36864((int16_t *)x,(int16_t *)y,1); + stop_meas(&ts); + } + + printf("\n\n36864-point(%f cycles)\n",(double)ts.diff/(double)ts.trials); + LOG_M("y36864.m","y36864",y,36864,1,1); + LOG_M("x36864.m","x36864",x,36864,1,1); + + memset((void*)x,0,49152*sizeof(int32_t)); for (i=2;i<28402;i++) { if ((taus() & 1)==0) diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index ed7a3b8c78..f69ec11432 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -904,7 +904,7 @@ int get_nr_prach_info_from_index(uint8_t index, if ( (frame%x)==y || (frame%x)==y2 ) { slot_60khz = slot >> (mu-2); // in table slots are numbered wrt 60kHz s_map = table_6_3_3_2_4_prachConfig_Index[index][5]; - if ( (s_map>>slot_60khz)&0x01 ) { + if ( ((s_map>>slot_60khz)&0x01) ) { if (mu == 3) { if ( (table_6_3_3_2_4_prachConfig_Index[index][7] == 1) && (slot%2 == 0) ) return 0; // no prach in even slots @ 120kHz for 1 prach per 60khz slot @@ -944,7 +944,7 @@ int get_nr_prach_info_from_index(uint8_t index, s_map = table_6_3_3_2_3_prachConfig_Index[index][4]; if ( (s_map>>subframe)&0x01 ) { if (mu == 1) { - if ( (table_6_3_3_2_3_prachConfig_Index[index][6] == 1) && (slot%2 == 0) ) + if ( (table_6_3_3_2_3_prachConfig_Index[index][6] <= 1) && (slot%2 == 0) ) return 0; // no prach in even slots @ 30kHz for 1 prach per subframe } if (start_symbol != NULL && N_t_slot != NULL && N_dur != NULL && format != NULL){ @@ -954,7 +954,7 @@ int get_nr_prach_info_from_index(uint8_t index, if (table_6_3_3_2_3_prachConfig_Index[index][1] != -1) format2 = (uint8_t) table_6_3_3_2_3_prachConfig_Index[index][1]; *format = ((uint8_t) table_6_3_3_2_3_prachConfig_Index[index][0]) | (format2<<8); - LOG_D(MAC,"Frame %d slot %d: Getting PRACH info from index %d absoluteFrequencyPointA %u mu %u frame_type %u start_symbol %u N_t_slot %u N_dur %u \n", frame, + LOG_I(MAC,"Frame %d slot %d: Getting PRACH info from index %d absoluteFrequencyPointA %u mu %u frame_type %u start_symbol %u N_t_slot %u N_dur %u \n", frame, slot, index, pointa, From 4e12c394718c9f5dbe1b15d1dc0dcb3a2a24160c Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Thu, 28 May 2020 17:56:42 +0200 Subject: [PATCH 267/553] static bitmap to schedule dl slots (also to test phone) --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 48 +++++++++------------- 1 file changed, 19 insertions(+), 29 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index 7cd3bd3c91..8652d7fce6 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -377,7 +377,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols!=0) nr_ulmix_slots++; - if ((slot_txP == 0) && (UE_list->fiveG_connected[UE_id] || get_softmodem_params()->phy_test)) { + if (slot_txP== 0 && (UE_list->fiveG_connected[UE_id] || get_softmodem_params()->phy_test)) { for (int k=0; kUE_sched_ctrl[UE_id].sched_pucch[k], 0, @@ -394,25 +394,23 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, RC.nrmac[module_idP]->frame = frame_rxP; RC.nrmac[module_idP]->slot = slot_rxP; - if (get_softmodem_params()->phy_test) { - dlsch_in_slot_bitmap = &RC.nrmac[module_idP]->UE_list.UE_sched_ctrl[UE_id].dlsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains dlsch - ulsch_in_slot_bitmap = &RC.nrmac[module_idP]->UE_list.UE_sched_ctrl[UE_id].ulsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains ulsch + dlsch_in_slot_bitmap = &RC.nrmac[module_idP]->UE_list.UE_sched_ctrl[UE_id].dlsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains dlsch + ulsch_in_slot_bitmap = &RC.nrmac[module_idP]->UE_list.UE_sched_ctrl[UE_id].ulsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains ulsch - // hardcoding dlsch to be in slot 1 - if (!(slot_txP%num_slots_per_tdd)) { - if(slot_txP==0) - *dlsch_in_slot_bitmap = 0x02; - else - *dlsch_in_slot_bitmap = 0x00; - } + // hardcoding dlsch to be in slot 1 + if (!(slot_txP%num_slots_per_tdd)) { + if(slot_txP==0) + *dlsch_in_slot_bitmap = 0x7e; + else + *dlsch_in_slot_bitmap = 0x00; + } - // hardcoding ulsch to be in slot 8 - if (!(slot_rxP%num_slots_per_tdd)) { - if(slot_rxP==0) - *ulsch_in_slot_bitmap = 0x100; - else - *ulsch_in_slot_bitmap = 0x00; - } + // hardcoding ulsch to be in slot 8 + if (!(slot_rxP%num_slots_per_tdd)) { + if(slot_rxP==0) + *ulsch_in_slot_bitmap = 0x100; + else + *ulsch_in_slot_bitmap = 0x00; } // Check if there are downlink symbols in the slot, @@ -464,9 +462,11 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, if (get_softmodem_params()->phy_test == 0) nr_schedule_RA(module_idP, frame_txP, slot_txP); + else + UE_list->fiveG_connected[UE_id] = true; // Phytest scheduling - if (get_softmodem_params()->phy_test && (is_xlsch_in_slot(*dlsch_in_slot_bitmap,slot_txP%num_slots_per_tdd))) { + if (UE_list->fiveG_connected[UE_id] && (is_xlsch_in_slot(*dlsch_in_slot_bitmap,slot_txP%num_slots_per_tdd))) { ue_sched_ctl->current_harq_pid = slot_txP % num_slots_per_tdd; nr_update_pucch_scheduling(module_idP, UE_id, frame_txP, slot_txP, num_slots_per_tdd,&pucch_sched); nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, &UE_list->UE_sched_ctrl[UE_id].sched_pucch[pucch_sched], NULL); @@ -474,16 +474,6 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, gNB->ta_len = 0; } - // Test DL scheduling - if (get_softmodem_params()->phy_test == 0 && slot_txP>0 && slot_txP<7 && UE_list->fiveG_connected[UE_id]) { - ue_sched_ctl->current_harq_pid = slot_txP % num_slots_per_tdd; - nr_update_pucch_scheduling(module_idP, UE_id, frame_txP, slot_txP, num_slots_per_tdd,&pucch_sched); - nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, &UE_list->UE_sched_ctrl[UE_id].sched_pucch[pucch_sched], NULL); - // resetting ta flag - gNB->ta_len = 0; - } - - /* // Allocate CCEs for good after scheduling is done for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) From 19a44bd0927547ffa58ffbcb51c840a8a770b84d Mon Sep 17 00:00:00 2001 From: "s.rampalli" Date: Fri, 29 May 2020 12:57:29 +0530 Subject: [PATCH 268/553] modified the rrc_add_nsa_user api --- openair2/RRC/NR/rrc_gNB_nsa.c | 1 - 1 file changed, 1 deletion(-) diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c index 45d56f24fa..e32d350294 100644 --- a/openair2/RRC/NR/rrc_gNB_nsa.c +++ b/openair2/RRC/NR/rrc_gNB_nsa.c @@ -138,7 +138,6 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_ ue_context_p->ue_context.secondaryCellGroup, carrier->pdsch_AntennaPorts, carrier->initial_csi_index[rrc->Nb_ue]); - ue_context_p->ue_context.rb_config = calloc(1,sizeof(NR_RRCReconfiguration_t)); ue_context_p->ue_id_rnti = ue_context_p->ue_context.secondaryCellGroup->spCellConfig->reconfigurationWithSync->newUE_Identity; NR_CG_Config_t *CG_Config = calloc(1,sizeof(*CG_Config)); memset((void *)CG_Config,0,sizeof(*CG_Config)); From cf5bc231ec2c1ad348c9bb840935b4f7679248a1 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 29 May 2020 16:44:26 +0200 Subject: [PATCH 269/553] scheduling dl in both half frames --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 28 ++++++++----------- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 1 - .../NR_MAC_gNB/gNB_scheduler_primitives.c | 19 +++++++++++-- openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 2 +- 4 files changed, 29 insertions(+), 21 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index 8652d7fce6..08fcf5bbaa 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -291,7 +291,8 @@ void copy_nr_ulreq(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) void nr_schedule_pucch(int Mod_idP, int UE_id, frame_t frameP, - sub_frame_t slotP) { + sub_frame_t slotP, + int num_slots_per_tdd) { uint16_t O_uci; uint16_t O_ack; @@ -306,12 +307,13 @@ void nr_schedule_pucch(int Mod_idP, nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[Mod_idP]->UL_tti_req[0]; NR_sched_pucch *curr_pucch; + int p = slotP/num_slots_per_tdd; int nr_ulmix_slots = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots; if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols!=0) nr_ulmix_slots++; for (int k=0; kUE_sched_ctrl[UE_id].sched_pucch[k]; + curr_pucch = &UE_list->UE_sched_ctrl[UE_id].sched_pucch[p][k]; if ((curr_pucch->dai_c > 0) && (frameP == curr_pucch->frame) && (slotP == curr_pucch->ul_slot)) { UL_tti_req->SFN = frameP; UL_tti_req->Slot = slotP; @@ -333,7 +335,9 @@ void nr_schedule_pucch(int Mod_idP, O_ack, SR_flag); - curr_pucch->dai_c = 0; + memset((void *) &UE_list->UE_sched_ctrl[UE_id].sched_pucch[p][k], + 0, + sizeof(NR_sched_pucch)); } } } @@ -377,14 +381,6 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols!=0) nr_ulmix_slots++; - if (slot_txP== 0 && (UE_list->fiveG_connected[UE_id] || get_softmodem_params()->phy_test)) { - for (int k=0; kUE_sched_ctrl[UE_id].sched_pucch[k], - 0, - sizeof(NR_sched_pucch)); - } - } - start_meas(&RC.nrmac[module_idP]->eNB_scheduler); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ULSCH_SCHEDULER,VCD_FUNCTION_IN); @@ -397,12 +393,11 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, dlsch_in_slot_bitmap = &RC.nrmac[module_idP]->UE_list.UE_sched_ctrl[UE_id].dlsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains dlsch ulsch_in_slot_bitmap = &RC.nrmac[module_idP]->UE_list.UE_sched_ctrl[UE_id].ulsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains ulsch - // hardcoding dlsch to be in slot 1 if (!(slot_txP%num_slots_per_tdd)) { if(slot_txP==0) *dlsch_in_slot_bitmap = 0x7e; else - *dlsch_in_slot_bitmap = 0x00; + *dlsch_in_slot_bitmap = 0x7e; } // hardcoding ulsch to be in slot 8 @@ -469,7 +464,8 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, if (UE_list->fiveG_connected[UE_id] && (is_xlsch_in_slot(*dlsch_in_slot_bitmap,slot_txP%num_slots_per_tdd))) { ue_sched_ctl->current_harq_pid = slot_txP % num_slots_per_tdd; nr_update_pucch_scheduling(module_idP, UE_id, frame_txP, slot_txP, num_slots_per_tdd,&pucch_sched); - nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, &UE_list->UE_sched_ctrl[UE_id].sched_pucch[pucch_sched], NULL); + nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, + &UE_list->UE_sched_ctrl[UE_id].sched_pucch[slot_txP/num_slots_per_tdd][pucch_sched], NULL); // resetting ta flag gNB->ta_len = 0; } @@ -486,12 +482,12 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, if (get_softmodem_params()->phy_test == 0) { if (UE_list->fiveG_connected[UE_id]) - nr_schedule_pucch(module_idP, UE_id, frame_rxP, slot_rxP); + nr_schedule_pucch(module_idP, UE_id, frame_rxP, slot_rxP, num_slots_per_tdd); schedule_nr_prach(module_idP, (frame_rxP+1)&1023, slot_rxP); nr_schedule_reception_msg3(module_idP, 0, frame_rxP, slot_rxP); } if (get_softmodem_params()->phy_test){ - nr_schedule_pucch(module_idP, UE_id, frame_rxP, slot_rxP); + nr_schedule_pucch(module_idP, UE_id, frame_rxP, slot_rxP, num_slots_per_tdd); if (is_xlsch_in_slot(*ulsch_in_slot_bitmap,slot_rxP%num_slots_per_tdd)){ nr_schedule_uss_ulsch_phytest(module_idP, frame_rxP, slot_rxP); } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 0167a5579b..f9e43dfeb3 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -370,7 +370,6 @@ int configure_fapi_dl_pdu(int Mod_idP, dci_pdu_rel15[0].ndi = UE_list->UE_sched_ctrl[UE_id].harq_processes[current_harq_pid].ndi; // DAI dci_pdu_rel15[0].dai[0].val = (pucch_sched->dai_c-1)&3; - // TPC for PUCCH dci_pdu_rel15[0].tpc = 1; // table 7.2.1-1 in 38.213 // PUCCH resource indicator diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index fa1e860c57..5c84d779df 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -1328,11 +1328,13 @@ int find_nr_UE_id(module_id_t mod_idP, rnti_t rntiP) int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){ int UE_id; - int i; + int i,p; NR_UE_list_t *UE_list = &RC.nrmac[mod_idP]->UE_list; NR_COMMON_channels_t *cc = RC.nrmac[mod_idP]->common_channels; NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; int num_slots_ul = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots; + int nb_periods = 1<<(7-scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity); + if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols>0) num_slots_ul++; LOG_I(MAC, "[gNB %d] Adding UE with rnti %x (next avail %d, num_UEs %d)\n", @@ -1353,7 +1355,17 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){ memset((void *) &UE_list->UE_sched_ctrl[UE_id], 0, sizeof(NR_UE_sched_ctrl_t)); - UE_list->UE_sched_ctrl[UE_id].sched_pucch = (NR_sched_pucch *)malloc(num_slots_ul*sizeof(NR_sched_pucch)); + + UE_list->UE_sched_ctrl[UE_id].sched_pucch = (NR_sched_pucch **)malloc(nb_periods*sizeof(NR_sched_pucch *)); + for (p=0; pUE_sched_ctrl[UE_id].sched_pucch[p] = (NR_sched_pucch *)malloc(num_slots_ul*sizeof(NR_sched_pucch)); + for (p=0; pUE_sched_ctrl[UE_id].sched_pucch[p][k], + 0, sizeof(NR_sched_pucch)); + } + } + LOG_I(MAC, "gNB %d] Add NR UE_id %d : rnti %x\n", mod_idP, UE_id, @@ -1431,6 +1443,7 @@ void nr_update_pucch_scheduling(int Mod_idP, NR_ServingCellConfigCommon_t *scc = RC.nrmac[Mod_idP]->common_channels->ServingCellConfigCommon; NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list; NR_sched_pucch *curr_pucch; + int tdd_index = slotP/slots_per_tdd; int first_ul_slot_tdd,k,i; uint8_t pdsch_to_harq_feedback[8]; int found = 0; @@ -1444,7 +1457,7 @@ void nr_update_pucch_scheduling(int Mod_idP, // for each possible ul or mixed slot for (k=0; kUE_sched_ctrl[UE_id].sched_pucch[k]; + curr_pucch = &UE_list->UE_sched_ctrl[UE_id].sched_pucch[tdd_index][k]; // if there is free room in current pucch structure if (curr_pucch->dai_cframe = frameP; diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index 0125535071..666ca64132 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -198,7 +198,7 @@ typedef struct NR_UE_harq { typedef struct { uint64_t dlsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains dlsch uint64_t ulsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains ulsch - NR_sched_pucch *sched_pucch; + NR_sched_pucch **sched_pucch; uint16_t ta_timer; int16_t ta_update; uint8_t current_harq_pid; From 17a1a554b7909c89cb842548339abc55ea198367 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Tue, 2 Jun 2020 16:14:49 +0200 Subject: [PATCH 270/553] separation of dl and ul clear fapi information --- openair1/SIMULATION/NR_PHY/dlsim.c | 2 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 28 +++++++++++++++------- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 13 ++++++---- openair2/NR_PHY_INTERFACE/NR_IF_Module.c | 2 +- 4 files changed, 30 insertions(+), 15 deletions(-) diff --git a/openair1/SIMULATION/NR_PHY/dlsim.c b/openair1/SIMULATION/NR_PHY/dlsim.c index 758d37e6bb..a3ea1ce6b8 100644 --- a/openair1/SIMULATION/NR_PHY/dlsim.c +++ b/openair1/SIMULATION/NR_PHY/dlsim.c @@ -745,7 +745,7 @@ int main(int argc, char **argv) while ((roundharq_ack.ack==0)) { memset(RC.nrmac[0]->cce_list[1][0],0,MAX_NUM_CCE*sizeof(int)); memset(RC.nrmac[0]->cce_list[1][1],0,MAX_NUM_CCE*sizeof(int)); - clear_nr_nfapi_information(RC.nrmac[0], 0, frame, slot); + clear_nr_nfapi_information_dl(RC.nrmac[0], 0, frame, slot); UE_list->UE_sched_ctrl[0].harq_processes[0].ndi = !(trial&1); diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index 08fcf5bbaa..300f8f853a 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -62,13 +62,12 @@ const uint8_t nr_slots_per_frame[5] = {10, 20, 40, 80, 160}; uint16_t nr_pdcch_order_table[6] = { 31, 31, 511, 2047, 2047, 8191 }; -void clear_nr_nfapi_information(gNB_MAC_INST * gNB, - int CC_idP, - frame_t frameP, - sub_frame_t slotP){ +void clear_nr_nfapi_information_dl(gNB_MAC_INST * gNB, + int CC_idP, + frame_t frameP, + sub_frame_t slotP){ nfapi_nr_dl_tti_request_t *DL_req = &gNB->DL_req[0]; - nfapi_nr_ul_tti_request_t *UL_tti_req = &gNB->UL_tti_req[0]; nfapi_nr_ul_dci_request_t *UL_dci_req = &gNB->UL_dci_req[0]; nfapi_nr_tx_data_request_t *TX_req = &gNB->TX_req[0]; @@ -86,17 +85,28 @@ void clear_nr_nfapi_information(gNB_MAC_INST * gNB, UL_dci_req[CC_idP].Slot = slotP; UL_dci_req[CC_idP].numPdus = 0; + TX_req[CC_idP].Number_of_PDUs = 0; + + } +} + +void clear_nr_nfapi_information_ul(gNB_MAC_INST * gNB, + int CC_idP, + frame_t frameP, + sub_frame_t slotP){ + + nfapi_nr_ul_tti_request_t *UL_tti_req = &gNB->UL_tti_req[0]; + + if (nfapi_mode==0 || nfapi_mode == 1) { // monolithic or PNF UL_tti_req[CC_idP].SFN = frameP; UL_tti_req[CC_idP].Slot = slotP; UL_tti_req[CC_idP].n_pdus = 0; UL_tti_req[CC_idP].n_ulsch = 0; UL_tti_req[CC_idP].n_ulcch = 0; UL_tti_req[CC_idP].n_group = 0; - - TX_req[CC_idP].Number_of_PDUs = 0; - } } + /* void check_nr_ul_failure(module_id_t module_idP, int CC_id, @@ -419,7 +429,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, memset(cc[CC_id].vrb_map, 0, 100); memset(cc[CC_id].vrb_map_UL, 0, 100); - clear_nr_nfapi_information(RC.nrmac[module_idP], CC_id, frame_txP, slot_txP); + clear_nr_nfapi_information_dl(RC.nrmac[module_idP], CC_id, frame_txP, slot_txP); } // refresh UE list based on UEs dropped by PHY in previous subframe diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index 4e29adf978..980b26bdbb 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -56,10 +56,15 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP, NR_CellGroupConfig_t *secondaryCellGroup ); -void clear_nr_nfapi_information(gNB_MAC_INST * gNB, - int CC_idP, - frame_t frameP, - sub_frame_t subframeP); +void clear_nr_nfapi_information_dl(gNB_MAC_INST * gNB, + int CC_idP, + frame_t frameP, + sub_frame_t subframeP); + +void clear_nr_nfapi_information_ul(gNB_MAC_INST * gNB, + int CC_idP, + frame_t frameP, + sub_frame_t subframeP); void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, frame_t frame_txP, sub_frame_t slot_txP, diff --git a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c index 2b8dc0ec02..578a47df4f 100644 --- a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c @@ -225,7 +225,7 @@ void NR_UL_indication(NR_UL_IND_t *UL_info) { } // clear DL/UL info for new scheduling round - clear_nr_nfapi_information(mac,CC_id,UL_info->frame,UL_info->slot); + clear_nr_nfapi_information_ul(mac,CC_id,UL_info->frame,UL_info->slot); handle_nr_rach(UL_info); handle_nr_uci(UL_info, &mac->UE_list.UE_sched_ctrl[0]); // clear HI prior to handling ULSCH From c359a05351fbf9eefa41fc87f34292d18c093a8e Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Tue, 2 Jun 2020 18:31:09 +0200 Subject: [PATCH 271/553] Revert "separation of dl and ul clear fapi information" This reverts commit 17a1a554b7909c89cb842548339abc55ea198367. --- openair1/SIMULATION/NR_PHY/dlsim.c | 2 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 28 +++++++--------------- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 13 ++++------ openair2/NR_PHY_INTERFACE/NR_IF_Module.c | 2 +- 4 files changed, 15 insertions(+), 30 deletions(-) diff --git a/openair1/SIMULATION/NR_PHY/dlsim.c b/openair1/SIMULATION/NR_PHY/dlsim.c index a3ea1ce6b8..758d37e6bb 100644 --- a/openair1/SIMULATION/NR_PHY/dlsim.c +++ b/openair1/SIMULATION/NR_PHY/dlsim.c @@ -745,7 +745,7 @@ int main(int argc, char **argv) while ((roundharq_ack.ack==0)) { memset(RC.nrmac[0]->cce_list[1][0],0,MAX_NUM_CCE*sizeof(int)); memset(RC.nrmac[0]->cce_list[1][1],0,MAX_NUM_CCE*sizeof(int)); - clear_nr_nfapi_information_dl(RC.nrmac[0], 0, frame, slot); + clear_nr_nfapi_information(RC.nrmac[0], 0, frame, slot); UE_list->UE_sched_ctrl[0].harq_processes[0].ndi = !(trial&1); diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index 300f8f853a..08fcf5bbaa 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -62,12 +62,13 @@ const uint8_t nr_slots_per_frame[5] = {10, 20, 40, 80, 160}; uint16_t nr_pdcch_order_table[6] = { 31, 31, 511, 2047, 2047, 8191 }; -void clear_nr_nfapi_information_dl(gNB_MAC_INST * gNB, - int CC_idP, - frame_t frameP, - sub_frame_t slotP){ +void clear_nr_nfapi_information(gNB_MAC_INST * gNB, + int CC_idP, + frame_t frameP, + sub_frame_t slotP){ nfapi_nr_dl_tti_request_t *DL_req = &gNB->DL_req[0]; + nfapi_nr_ul_tti_request_t *UL_tti_req = &gNB->UL_tti_req[0]; nfapi_nr_ul_dci_request_t *UL_dci_req = &gNB->UL_dci_req[0]; nfapi_nr_tx_data_request_t *TX_req = &gNB->TX_req[0]; @@ -85,28 +86,17 @@ void clear_nr_nfapi_information_dl(gNB_MAC_INST * gNB, UL_dci_req[CC_idP].Slot = slotP; UL_dci_req[CC_idP].numPdus = 0; - TX_req[CC_idP].Number_of_PDUs = 0; - - } -} - -void clear_nr_nfapi_information_ul(gNB_MAC_INST * gNB, - int CC_idP, - frame_t frameP, - sub_frame_t slotP){ - - nfapi_nr_ul_tti_request_t *UL_tti_req = &gNB->UL_tti_req[0]; - - if (nfapi_mode==0 || nfapi_mode == 1) { // monolithic or PNF UL_tti_req[CC_idP].SFN = frameP; UL_tti_req[CC_idP].Slot = slotP; UL_tti_req[CC_idP].n_pdus = 0; UL_tti_req[CC_idP].n_ulsch = 0; UL_tti_req[CC_idP].n_ulcch = 0; UL_tti_req[CC_idP].n_group = 0; + + TX_req[CC_idP].Number_of_PDUs = 0; + } } - /* void check_nr_ul_failure(module_id_t module_idP, int CC_id, @@ -429,7 +419,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, memset(cc[CC_id].vrb_map, 0, 100); memset(cc[CC_id].vrb_map_UL, 0, 100); - clear_nr_nfapi_information_dl(RC.nrmac[module_idP], CC_id, frame_txP, slot_txP); + clear_nr_nfapi_information(RC.nrmac[module_idP], CC_id, frame_txP, slot_txP); } // refresh UE list based on UEs dropped by PHY in previous subframe diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index 980b26bdbb..4e29adf978 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -56,15 +56,10 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP, NR_CellGroupConfig_t *secondaryCellGroup ); -void clear_nr_nfapi_information_dl(gNB_MAC_INST * gNB, - int CC_idP, - frame_t frameP, - sub_frame_t subframeP); - -void clear_nr_nfapi_information_ul(gNB_MAC_INST * gNB, - int CC_idP, - frame_t frameP, - sub_frame_t subframeP); +void clear_nr_nfapi_information(gNB_MAC_INST * gNB, + int CC_idP, + frame_t frameP, + sub_frame_t subframeP); void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, frame_t frame_txP, sub_frame_t slot_txP, diff --git a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c index 578a47df4f..2b8dc0ec02 100644 --- a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c @@ -225,7 +225,7 @@ void NR_UL_indication(NR_UL_IND_t *UL_info) { } // clear DL/UL info for new scheduling round - clear_nr_nfapi_information_ul(mac,CC_id,UL_info->frame,UL_info->slot); + clear_nr_nfapi_information(mac,CC_id,UL_info->frame,UL_info->slot); handle_nr_rach(UL_info); handle_nr_uci(UL_info, &mac->UE_list.UE_sched_ctrl[0]); // clear HI prior to handling ULSCH From f6b83fd9254102bd5236df15dd8353c9a96ef21a Mon Sep 17 00:00:00 2001 From: Florian Kaltenberger Date: Wed, 3 Jun 2020 11:51:58 +0200 Subject: [PATCH 272/553] adding frequency offset to prachsim --- openair1/SIMULATION/NR_PHY/prachsim.c | 44 +++++++++++++++------------ 1 file changed, 24 insertions(+), 20 deletions(-) diff --git a/openair1/SIMULATION/NR_PHY/prachsim.c b/openair1/SIMULATION/NR_PHY/prachsim.c index 18939b33f2..797118b382 100644 --- a/openair1/SIMULATION/NR_PHY/prachsim.c +++ b/openair1/SIMULATION/NR_PHY/prachsim.c @@ -88,7 +88,7 @@ int main(int argc, char **argv){ double **s_re, **s_im, **r_re, **r_im, iqim = 0.0, delay_avg = 0, ue_speed = 0, fs, bw; int i, aa, aarx, **txdata, trial, n_frames = 1, prach_start, rx_prach_start; //, ntrials=1; int N_RB_UL = 106, delay = 0, NCS_config = 13, rootSequenceIndex = 1, threequarter_fs = 0, mu = 1, fd_occasion = 0, loglvl = OAILOG_INFO, numRA = 0, prachStartSymbol = 0; - uint8_t snr1set = 0, ue_speed1set = 0, transmission_mode = 1, n_tx = 1, n_rx = 1, awgn_flag = 0, msg1_frequencystart = 0, num_prach_fd_occasions = 1, prach_format; + uint8_t snr1set = 0, ue_speed1set = 0, transmission_mode = 1, n_tx = 1, n_rx = 1, awgn_flag = 0, msg1_frequencystart = 0, num_prach_fd_occasions = 1, prach_format=0; uint8_t frame = 1, subframe = 9, slot=19, slot_gNB=19, config_index = 98, prach_sequence_length = 1, num_root_sequences = 16, restrictedSetConfig = 0, N_dur, N_t_slot, start_symbol; uint16_t Nid_cell = 0, preamble_tx = 0, preamble_delay, format, format0, format1; uint32_t tx_lev = 10000, prach_errors = 0, samp_count; //,tx_lev_dB; @@ -131,6 +131,10 @@ int main(int argc, char **argv){ config_index = atoi(optarg); break; + case 'r': + msg1_frequencystart = atoi(optarg); + break; + case 'd': delay = atoi(optarg); break; @@ -401,15 +405,15 @@ int main(int argc, char **argv){ if (format1 != 0xff) { switch(format0) { - case 0xa1: - prach_format = 9; - break; - case 0xa2: - prach_format = 10; - break; - case 0xa3: - prach_format = 11; - break; + case 0xa1: + prach_format = 9; + break; + case 0xa2: + prach_format = 10; + break; + case 0xa3: + prach_format = 11; + break; default: AssertFatal(1==0, "Only formats A1/B1 A2/B2 A3/B3 are valid for dual format"); } @@ -459,6 +463,8 @@ int main(int argc, char **argv){ } } + printf("PRACH format %d\n",prach_format); + prach_config->num_prach_fd_occasions_list[fd_occasion].prach_root_sequence_index.value = rootSequenceIndex; prach_config->num_prach_fd_occasions_list[fd_occasion].k1.value = msg1_frequencystart; prach_config->restricted_set_config.value = restrictedSetConfig; @@ -578,16 +584,14 @@ int main(int argc, char **argv){ /* tx_lev_dB not used later, no need to set */ //tx_lev_dB = (unsigned int) dB_fixed(tx_lev); - if (mu == 0) - samp_count = frame_parms->samples_per_subframe; - else - samp_count = ((slot)%(frame_parms->slots_per_subframe/2)) ? frame_parms->samples_per_slotN0 : frame_parms->samples_per_slot0; - - prach_start = slot*samp_count - UE->N_TA_offset; + samp_count=0; + for (int s=0; sget_samples_per_slot(s,frame_parms); + + prach_start = samp_count - UE->N_TA_offset; #ifdef NR_PRACH_DEBUG - LOG_M("txsig0.m", "txs0", &txdata[0][prach_start], frame_parms->samples_per_subframe, 1, 1); - //LOG_M("txsig1.m","txs1", txdata[1],FRAME_LENGTH_COMPLEX_SAMPLES,1,1); + LOG_M("txsig0.m", "txs0", &txdata[0][prach_start], frame_parms->samples_per_subframe, 1, 1); + LOG_M("txsig0_frame.m","txs0", txdata[0],frame_parms->samples_per_frame,1,1); #endif // multipath channel @@ -628,7 +632,7 @@ int main(int argc, char **argv){ ue_speed1 = ue_speed0 + 50; } - rx_prach_start = slot*frame_parms->get_samples_per_slot(slot,frame_parms); + rx_prach_start = subframe*frame_parms->samples_per_subframe; if (n_frames==1) printf("slot %d, rx_prach_start %d\n",slot,rx_prach_start); uint16_t preamble_rx, preamble_energy, N_ZC; N_ZC = prach_sequence_length == 0 ? 839 : 139; @@ -688,7 +692,7 @@ int main(int argc, char **argv){ if (n_frames==1) { printf("preamble %d (tx %d) : energy %d, delay %d\n",preamble_rx,preamble_tx,preamble_energy,preamble_delay); #ifdef NR_PRACH_DEBUG - LOG_M("prach0.m","prach0", &txdata[0][prach_start], samp_count, 1, 1); + LOG_M("prach0.m","prach0", &txdata[0][prach_start], frame_parms->samples_per_subframe, 1, 1); LOG_M("prachF0.m","prachF0", &gNB->prach_vars.prachF[0], N_ZC, 1, 1); LOG_M("rxsig0.m","rxs0", &gNB->common_vars.rxdata[0][rx_prach_start], frame_parms->samples_per_subframe, 1, 1); //LOG_M("ru_rxsig0.m","rxs0", &ru->common.rxdata[0][rx_prach_start], frame_parms->samples_per_subframe, 1, 1); From 7948d26f8ca3d6ec2495f6412e5d2bdb403bbd42 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Wed, 3 Jun 2020 15:45:00 +0200 Subject: [PATCH 273/553] Revert "scheduling dl in both half frames" This reverts commit cf5bc231ec2c1ad348c9bb840935b4f7679248a1. --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 28 +++++++++++-------- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 1 + .../NR_MAC_gNB/gNB_scheduler_primitives.c | 19 ++----------- openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 2 +- 4 files changed, 21 insertions(+), 29 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index 08fcf5bbaa..8652d7fce6 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -291,8 +291,7 @@ void copy_nr_ulreq(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) void nr_schedule_pucch(int Mod_idP, int UE_id, frame_t frameP, - sub_frame_t slotP, - int num_slots_per_tdd) { + sub_frame_t slotP) { uint16_t O_uci; uint16_t O_ack; @@ -307,13 +306,12 @@ void nr_schedule_pucch(int Mod_idP, nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[Mod_idP]->UL_tti_req[0]; NR_sched_pucch *curr_pucch; - int p = slotP/num_slots_per_tdd; int nr_ulmix_slots = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots; if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols!=0) nr_ulmix_slots++; for (int k=0; kUE_sched_ctrl[UE_id].sched_pucch[p][k]; + curr_pucch = &UE_list->UE_sched_ctrl[UE_id].sched_pucch[k]; if ((curr_pucch->dai_c > 0) && (frameP == curr_pucch->frame) && (slotP == curr_pucch->ul_slot)) { UL_tti_req->SFN = frameP; UL_tti_req->Slot = slotP; @@ -335,9 +333,7 @@ void nr_schedule_pucch(int Mod_idP, O_ack, SR_flag); - memset((void *) &UE_list->UE_sched_ctrl[UE_id].sched_pucch[p][k], - 0, - sizeof(NR_sched_pucch)); + curr_pucch->dai_c = 0; } } } @@ -381,6 +377,14 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols!=0) nr_ulmix_slots++; + if (slot_txP== 0 && (UE_list->fiveG_connected[UE_id] || get_softmodem_params()->phy_test)) { + for (int k=0; kUE_sched_ctrl[UE_id].sched_pucch[k], + 0, + sizeof(NR_sched_pucch)); + } + } + start_meas(&RC.nrmac[module_idP]->eNB_scheduler); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ULSCH_SCHEDULER,VCD_FUNCTION_IN); @@ -393,11 +397,12 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, dlsch_in_slot_bitmap = &RC.nrmac[module_idP]->UE_list.UE_sched_ctrl[UE_id].dlsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains dlsch ulsch_in_slot_bitmap = &RC.nrmac[module_idP]->UE_list.UE_sched_ctrl[UE_id].ulsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains ulsch + // hardcoding dlsch to be in slot 1 if (!(slot_txP%num_slots_per_tdd)) { if(slot_txP==0) *dlsch_in_slot_bitmap = 0x7e; else - *dlsch_in_slot_bitmap = 0x7e; + *dlsch_in_slot_bitmap = 0x00; } // hardcoding ulsch to be in slot 8 @@ -464,8 +469,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, if (UE_list->fiveG_connected[UE_id] && (is_xlsch_in_slot(*dlsch_in_slot_bitmap,slot_txP%num_slots_per_tdd))) { ue_sched_ctl->current_harq_pid = slot_txP % num_slots_per_tdd; nr_update_pucch_scheduling(module_idP, UE_id, frame_txP, slot_txP, num_slots_per_tdd,&pucch_sched); - nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, - &UE_list->UE_sched_ctrl[UE_id].sched_pucch[slot_txP/num_slots_per_tdd][pucch_sched], NULL); + nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, &UE_list->UE_sched_ctrl[UE_id].sched_pucch[pucch_sched], NULL); // resetting ta flag gNB->ta_len = 0; } @@ -482,12 +486,12 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, if (get_softmodem_params()->phy_test == 0) { if (UE_list->fiveG_connected[UE_id]) - nr_schedule_pucch(module_idP, UE_id, frame_rxP, slot_rxP, num_slots_per_tdd); + nr_schedule_pucch(module_idP, UE_id, frame_rxP, slot_rxP); schedule_nr_prach(module_idP, (frame_rxP+1)&1023, slot_rxP); nr_schedule_reception_msg3(module_idP, 0, frame_rxP, slot_rxP); } if (get_softmodem_params()->phy_test){ - nr_schedule_pucch(module_idP, UE_id, frame_rxP, slot_rxP, num_slots_per_tdd); + nr_schedule_pucch(module_idP, UE_id, frame_rxP, slot_rxP); if (is_xlsch_in_slot(*ulsch_in_slot_bitmap,slot_rxP%num_slots_per_tdd)){ nr_schedule_uss_ulsch_phytest(module_idP, frame_rxP, slot_rxP); } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index f9e43dfeb3..0167a5579b 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -370,6 +370,7 @@ int configure_fapi_dl_pdu(int Mod_idP, dci_pdu_rel15[0].ndi = UE_list->UE_sched_ctrl[UE_id].harq_processes[current_harq_pid].ndi; // DAI dci_pdu_rel15[0].dai[0].val = (pucch_sched->dai_c-1)&3; + // TPC for PUCCH dci_pdu_rel15[0].tpc = 1; // table 7.2.1-1 in 38.213 // PUCCH resource indicator diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 5c84d779df..fa1e860c57 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -1328,13 +1328,11 @@ int find_nr_UE_id(module_id_t mod_idP, rnti_t rntiP) int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){ int UE_id; - int i,p; + int i; NR_UE_list_t *UE_list = &RC.nrmac[mod_idP]->UE_list; NR_COMMON_channels_t *cc = RC.nrmac[mod_idP]->common_channels; NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; int num_slots_ul = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots; - int nb_periods = 1<<(7-scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity); - if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols>0) num_slots_ul++; LOG_I(MAC, "[gNB %d] Adding UE with rnti %x (next avail %d, num_UEs %d)\n", @@ -1355,17 +1353,7 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){ memset((void *) &UE_list->UE_sched_ctrl[UE_id], 0, sizeof(NR_UE_sched_ctrl_t)); - - UE_list->UE_sched_ctrl[UE_id].sched_pucch = (NR_sched_pucch **)malloc(nb_periods*sizeof(NR_sched_pucch *)); - for (p=0; pUE_sched_ctrl[UE_id].sched_pucch[p] = (NR_sched_pucch *)malloc(num_slots_ul*sizeof(NR_sched_pucch)); - for (p=0; pUE_sched_ctrl[UE_id].sched_pucch[p][k], - 0, sizeof(NR_sched_pucch)); - } - } - + UE_list->UE_sched_ctrl[UE_id].sched_pucch = (NR_sched_pucch *)malloc(num_slots_ul*sizeof(NR_sched_pucch)); LOG_I(MAC, "gNB %d] Add NR UE_id %d : rnti %x\n", mod_idP, UE_id, @@ -1443,7 +1431,6 @@ void nr_update_pucch_scheduling(int Mod_idP, NR_ServingCellConfigCommon_t *scc = RC.nrmac[Mod_idP]->common_channels->ServingCellConfigCommon; NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list; NR_sched_pucch *curr_pucch; - int tdd_index = slotP/slots_per_tdd; int first_ul_slot_tdd,k,i; uint8_t pdsch_to_harq_feedback[8]; int found = 0; @@ -1457,7 +1444,7 @@ void nr_update_pucch_scheduling(int Mod_idP, // for each possible ul or mixed slot for (k=0; kUE_sched_ctrl[UE_id].sched_pucch[tdd_index][k]; + curr_pucch = &UE_list->UE_sched_ctrl[UE_id].sched_pucch[k]; // if there is free room in current pucch structure if (curr_pucch->dai_cframe = frameP; diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index 666ca64132..0125535071 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -198,7 +198,7 @@ typedef struct NR_UE_harq { typedef struct { uint64_t dlsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains dlsch uint64_t ulsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains ulsch - NR_sched_pucch **sched_pucch; + NR_sched_pucch *sched_pucch; uint16_t ta_timer; int16_t ta_update; uint8_t current_harq_pid; From 884cbc7c8c4a966c80d41e161a79cd56899915ed Mon Sep 17 00:00:00 2001 From: Rangaswami Date: Thu, 4 Jun 2020 11:04:43 +0530 Subject: [PATCH 274/553] Corrected indentation and removed GES macro --- cmake_targets/CMakeLists.txt | 1 - openair2/LAYER2/NR_MAC_COMMON/nr_mac.h | 176 +++--- .../LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c | 525 +++++++++--------- openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 502 +++++++++-------- 4 files changed, 590 insertions(+), 614 deletions(-) diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index 7662d29775..a86c262867 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -249,7 +249,6 @@ add_boolean_option(UE_AUTOTEST_TRACE False "Activate UE autotest specific logs add_boolean_option(UE_DEBUG_TRACE False "Activate UE debug trace") add_boolean_option(UE_TIMING_TRACE False "Activate UE timing trace") add_boolean_option(DEBUG_CONSOLE False "makes debugging easier, disables stdout/stderr buffering") -add_boolean_option(GES_SUPPORT True "To enable the GES Code") set (OCP_ITTI ${OPENAIR_DIR}/common/utils/ocp_itti) add_library(ITTI diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h index d6a26c3be2..c085078064 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h @@ -71,131 +71,129 @@ // R: Reserved bit, set to zero. typedef struct { - uint8_t LCID: 6; // octet 1 [5:0] - uint8_t F: 1; // octet 1 [6] - uint8_t R: 1; // octet 1 [7] - uint8_t L: 8; // octet 2 [7:0] + uint8_t LCID: 6; // octet 1 [5:0] + uint8_t F: 1; // octet 1 [6] + uint8_t R: 1; // octet 1 [7] + uint8_t L: 8; // octet 2 [7:0] } __attribute__ ((__packed__)) NR_MAC_SUBHEADER_SHORT; typedef struct { - uint8_t LCID: 6; // octet 1 [5:0] - uint8_t F: 1; // octet 1 [6] - uint8_t R: 1; // octet 1 [7] - uint8_t L1: 8; // octet 2 [7:0] - uint8_t L2: 8; // octet 3 [7:0] + uint8_t LCID: 6; // octet 1 [5:0] + uint8_t F: 1; // octet 1 [6] + uint8_t R: 1; // octet 1 [7] + uint8_t L1: 8; // octet 2 [7:0] + uint8_t L2: 8; // octet 3 [7:0] } __attribute__ ((__packed__)) NR_MAC_SUBHEADER_LONG; typedef struct { - uint8_t LCID: 6; // octet 1 [5:0] - uint8_t R: 2; // octet 1 [7:6] + uint8_t LCID: 6; // octet 1 [5:0] + uint8_t R: 2; // octet 1 [7:6] } __attribute__ ((__packed__)) NR_MAC_SUBHEADER_FIXED; // BSR MAC CEs // TS 38.321 ch. 6.1.3.1 // Short BSR for a specific logical channel group ID typedef struct { - uint8_t Buffer_size: 5; // octet 1 LSB - uint8_t LcgID: 3; // octet 1 MSB + uint8_t Buffer_size: 5; // octet 1 LSB + uint8_t LcgID: 3; // octet 1 MSB } __attribute__ ((__packed__)) NR_BSR_SHORT; typedef NR_BSR_SHORT NR_BSR_SHORT_TRUNCATED; // Long BSR for all logical channel group ID typedef struct { - uint8_t Buffer_size7: 8; - uint8_t Buffer_size6: 8; - uint8_t Buffer_size5: 8; - uint8_t Buffer_size4: 8; - uint8_t Buffer_size3: 8; - uint8_t Buffer_size2: 8; - uint8_t Buffer_size1: 8; - uint8_t Buffer_size0: 8; - uint8_t LcgID0: 1; - uint8_t LcgID1: 1; - uint8_t LcgID2: 1; - uint8_t LcgID3: 1; - uint8_t LcgID4: 1; - uint8_t LcgID5: 1; - uint8_t LcgID6: 1; - uint8_t LcgID7: 1; + uint8_t Buffer_size7: 8; + uint8_t Buffer_size6: 8; + uint8_t Buffer_size5: 8; + uint8_t Buffer_size4: 8; + uint8_t Buffer_size3: 8; + uint8_t Buffer_size2: 8; + uint8_t Buffer_size1: 8; + uint8_t Buffer_size0: 8; + uint8_t LcgID0: 1; + uint8_t LcgID1: 1; + uint8_t LcgID2: 1; + uint8_t LcgID3: 1; + uint8_t LcgID4: 1; + uint8_t LcgID5: 1; + uint8_t LcgID6: 1; + uint8_t LcgID7: 1; } __attribute__ ((__packed__)) NR_BSR_LONG; typedef NR_BSR_LONG NR_BSR_LONG_TRUNCATED; // 38.321 ch. 6.1.3.4 typedef struct { - uint8_t TA_COMMAND: 6; // octet 1 [5:0] - uint8_t TAGID: 2; // octet 1 [7:6] + uint8_t TA_COMMAND: 6; // octet 1 [5:0] + uint8_t TAGID: 2; // octet 1 [7:6] } __attribute__ ((__packed__)) NR_MAC_CE_TA; // single Entry PHR MAC CE // TS 38.321 ch. 6.1.3.8 typedef struct { - uint8_t PH: 6; - uint8_t R1: 2; - uint8_t PCMAX: 6; - uint8_t R2: 6; + uint8_t PH: 6; + uint8_t R1: 2; + uint8_t PCMAX: 6; + uint8_t R2: 6; } __attribute__ ((__packed__)) NR_SINGLE_ENTRY_PHR_MAC_CE; -#ifdef GES_SUPPORT // SP ZP CSI-RS Resource Set Activation/Deactivation MAC CE // 38.321 ch. 6.1.3.19 typedef struct { - uint8_t BWPID: 2; // octet 1 [1:0] - uint8_t CELLID: 5; // octet 1 [6:2] - uint8_t A_D: 1; // octet 1 [7] - uint8_t CSIRS_RSC_ID: 4; // octet 2 [3:0] - uint8_t R: 4 // octet 2 [7:4] + uint8_t BWPID: 2; // octet 1 [1:0] + uint8_t CELLID: 5; // octet 1 [6:2] + uint8_t A_D: 1; // octet 1 [7] + uint8_t CSIRS_RSC_ID: 4; // octet 2 [3:0] + uint8_t R: 4; // octet 2 [7:4] } __attribute__ ((__packed__)) NR_MAC_CE_SP_ZP_CSI_RS_RES_SET; //TS 38.321 Sec 6.1.3.15, TCI State indicaton for UE-Specific PDCCH MAC CE typedef struct { - uint8_t CoresetId1: 3; //Octect 1 [2:0] - uint8_t ServingCellId: 5; //Octect 1 [7:3] - uint8_t TciStateId: 7; //Octect 2 [6:0] - uint8_t CoresetId2: 1; //Octect 2 [7] + uint8_t CoresetId1: 3; //Octect 1 [2:0] + uint8_t ServingCellId: 5; //Octect 1 [7:3] + uint8_t TciStateId: 7; //Octect 2 [6:0] + uint8_t CoresetId2: 1; //Octect 2 [7] } __attribute__ ((__packed__)) NR_TCI_PDCCH; //TS 38.321 Sec 6.1.3.14, TCI State activation/deactivation for UE Specific PDSCH MAC CE typedef struct { - uint8_t BWP_Id: 2; //Octect 1 [1:0] - uint8_t ServingCellId: 5; //Octect 1 [6:2] - uint8_t R: 1; //Octect 1 [7] - uint8_t T[]; //Octects 2 to MAX TCI States/8 + uint8_t BWP_Id: 2; //Octect 1 [1:0] + uint8_t ServingCellId: 5; //Octect 1 [6:2] + uint8_t R: 1; //Octect 1 [7] + uint8_t T[]; //Octects 2 to MAX TCI States/8 } __attribute__ ((__packed__)) NR_TCI_PDSCH_APERIODIC_CSI; //TS 6.1.3.16, SP CSI reporting on PUCCH Activation/Deactivation MAC CE typedef struct { - uint8_t BWP_Id: 2; //Octect 1 [1:0] - uint8_t ServingCellId: 5; //Octect 1 [6:2] - uint8_t R1: 1; //Octect 1 [7] - uint8_t S0: 1; //Octect 2 [0] - uint8_t S1: 1; //Octect 2 [1] - uint8_t S2: 1; //Octect 2 [2] - uint8_t S3: 1; //Octect 2 [3] - uint8_t R2: 4; //Octect 2 [7:4] + uint8_t BWP_Id: 2; //Octect 1 [1:0] + uint8_t ServingCellId: 5; //Octect 1 [6:2] + uint8_t R1: 1; //Octect 1 [7] + uint8_t S0: 1; //Octect 2 [0] + uint8_t S1: 1; //Octect 2 [1] + uint8_t S2: 1; //Octect 2 [2] + uint8_t S3: 1; //Octect 2 [3] + uint8_t R2: 4; //Octect 2 [7:4] } __attribute__ ((__packed__)) NR_PUCCH_CSI_REPORTING; //TS 38.321 sec 6.1.3.12 //SP CSI-RS / CSI-IM Resource Set Activation/Deactivation MAC CE typedef struct { - uint8_t BWP_ID: 2; - uint8_t SCID: 5; - uint8_t A_D: 1; - uint8_t SP_CSI_RSID: 6; - uint8_t IM: 1; - uint8_t R1: 1; - uint8_t SP_CSI_IMID: 6; - uint8_t R2: 2; - struct TCI_S { - uint8_t TCI_STATE_ID: 6; - uint8_t R: 2; - } __attribute__ ((__packed__)) TCI_STATE; + uint8_t BWP_ID: 2; + uint8_t SCID: 5; + uint8_t A_D: 1; + uint8_t SP_CSI_RSID: 6; + uint8_t IM: 1; + uint8_t R1: 1; + uint8_t SP_CSI_IMID: 6; + uint8_t R2: 2; + struct TCI_S { + uint8_t TCI_STATE_ID: 6; + uint8_t R: 2; + } __attribute__ ((__packed__)) TCI_STATE; } __attribute__ ((__packed__)) CSI_RS_CSI_IM_ACT_DEACT_MAC_CE; -#endif //* RAR MAC subheader // TS 38.321 ch. 6.1.5, 6.2.2 *// // - E: The Extension field is a flag indicating if the MAC subPDU including this MAC subheader is the last MAC subPDU or not in the MAC PDU @@ -206,30 +204,30 @@ typedef struct { /*!\brief RAR MAC subheader with RAPID */ typedef struct { - uint8_t RAPID: 6; - uint8_t T: 1; - uint8_t E: 1; + uint8_t RAPID: 6; + uint8_t T: 1; + uint8_t E: 1; } __attribute__ ((__packed__)) NR_RA_HEADER_RAPID; /*!\brief RAR MAC subheader with Backoff Indicator */ typedef struct { - uint8_t BI: 4; - uint8_t R: 2; - uint8_t T: 1; - uint8_t E: 1; + uint8_t BI: 4; + uint8_t R: 2; + uint8_t T: 1; + uint8_t E: 1; } __attribute__ ((__packed__)) NR_RA_HEADER_BI; // TS 38.321 ch. 6.2.3 typedef struct { - uint8_t TA1: 7; // octet 1 [6:0] - uint8_t R: 1; // octet 1 [7] - uint8_t UL_GRANT_1: 3; // octet 2 [2:0] - uint8_t TA2: 5; // octet 2 [7:3] - uint8_t UL_GRANT_2: 8; // octet 3 [7:0] - uint8_t UL_GRANT_3: 8; // octet 4 [7:0] - uint8_t UL_GRANT_4: 8; // octet 5 [7:0] - uint8_t TCRNTI_1: 8; // octet 6 [7:0] - uint8_t TCRNTI_2: 8; // octet 7 [7:0] + uint8_t TA1: 7; // octet 1 [6:0] + uint8_t R: 1; // octet 1 [7] + uint8_t UL_GRANT_1: 3; // octet 2 [2:0] + uint8_t TA2: 5; // octet 2 [7:3] + uint8_t UL_GRANT_2: 8; // octet 3 [7:0] + uint8_t UL_GRANT_3: 8; // octet 4 [7:0] + uint8_t UL_GRANT_4: 8; // octet 5 [7:0] + uint8_t TCRNTI_1: 8; // octet 6 [7:0] + uint8_t TCRNTI_2: 8; // octet 7 [7:0] } __attribute__ ((__packed__)) NR_MAC_RAR; // 38.321 ch6.2.1, 38.331 @@ -273,9 +271,9 @@ typedef struct { #define UL_SCH_LCID_L_BSR 0x3E #define UL_SCH_LCID_PADDING 0x3F -#define NR_MAX_NUM_LCID 32 -#define NR_MAX_NUM_LCGID 8 -#define MAX_RLC_SDU_SUBHEADER_SIZE 3 +#define NR_MAX_NUM_LCID 32 +#define NR_MAX_NUM_LCGID 8 +#define MAX_RLC_SDU_SUBHEADER_SIZE 3 #endif /*__LAYER2_MAC_H__ */ diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c index e086210e4f..cf2323f571 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c @@ -47,12 +47,10 @@ //////////////////////////////////////////////////////// /////* DLSCH MAC PDU generation (6.1.2 TS 38.321) *///// //////////////////////////////////////////////////////// -#ifdef GES_SUPPORT #define OCTET 8 #define HALFWORD 16 #define WORD 32 //#define SIZE_OF_POINTER sizeof (void *) -#endif int nr_generate_dlsch_pdu(module_id_t module_idP, unsigned char *sdus_payload, @@ -63,299 +61,284 @@ int nr_generate_dlsch_pdu(module_id_t module_idP, unsigned char drx_cmd, unsigned char *ue_cont_res_id, unsigned short post_padding) { + gNB_MAC_INST *gNB = RC.nrmac[module_idP]; + NR_MAC_SUBHEADER_FIXED *mac_pdu_ptr = (NR_MAC_SUBHEADER_FIXED *) mac_pdu; + unsigned char *dlsch_buffer_ptr = sdus_payload; + uint8_t last_size = 0; + int offset = 0, mac_ce_size, i, timing_advance_cmd, tag_id = 0; + // MAC CEs + uint8_t mac_header_control_elements[16], *ce_ptr; + ce_ptr = &mac_header_control_elements[0]; + uint16_t UE_id = 0; //TODO need to get as a function parameter or need to invoke api to UE_id using module Id and RNTI + gNB_MAC_INST *gNB_mac = RC.nrmac[module_idP]; + NR_UE_list_t *UE_list = &gNB_mac->UE_list; + NR_UE_sched_ctrl_t *ue_sched_ctl = NULL; + //NR_CellGroupConfig_t *config = UE_list->secondaryCellGroup[UE_id]; + ue_sched_ctl = &(UE_list->UE_sched_ctrl[UE_id]); - gNB_MAC_INST *gNB = RC.nrmac[module_idP]; + // 1) Compute MAC CE and related subheaders - NR_MAC_SUBHEADER_FIXED *mac_pdu_ptr = (NR_MAC_SUBHEADER_FIXED *) mac_pdu; - unsigned char * dlsch_buffer_ptr = sdus_payload; - uint8_t last_size = 0; - int offset = 0, mac_ce_size, i, timing_advance_cmd, tag_id = 0; - // MAC CEs - uint8_t mac_header_control_elements[16], *ce_ptr; - ce_ptr = &mac_header_control_elements[0]; -#ifdef GES_SUPPORT - uint16_t UE_id = 0; //TODO need to get as a function parameter or need to invoke api to UE_id using module Id and RNTI - gNB_MAC_INST *gNB_mac = RC.nrmac[module_idP]; - NR_UE_list_t *UE_list = &gNB_mac->UE_list; - NR_UE_sched_ctrl_t *ue_sched_ctl = NULL; - //NR_CellGroupConfig_t *config = UE_list->secondaryCellGroup[UE_id]; - ue_sched_ctl = &(UE_list->UE_sched_ctrl[UE_id]); -#endif + // DRX command subheader (MAC CE size 0) + if (drx_cmd != 255) { + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_DRX; + //last_size = 1; + mac_pdu_ptr++; + } - // 1) Compute MAC CE and related subheaders + // Timing Advance subheader + /* This was done only when timing_advance_cmd != 31 + // now TA is always send when ta_timer resets regardless of its value + // this is done to avoid issues with the timeAlignmentTimer which is + // supposed to monitor if the UE received TA or not */ + if (gNB->ta_len) { + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_TA_COMMAND; + //last_size = 1; + mac_pdu_ptr++; + // TA MAC CE (1 octet) + timing_advance_cmd = gNB->ta_command; + AssertFatal(timing_advance_cmd < 64, "timing_advance_cmd %d > 63\n", timing_advance_cmd); + ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND = timing_advance_cmd; //(timing_advance_cmd+31)&0x3f; - // DRX command subheader (MAC CE size 0) - if (drx_cmd != 255) { - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_DRX; - //last_size = 1; - mac_pdu_ptr++; + if (gNB->tag->tag_Id != 0) { + tag_id = gNB->tag->tag_Id; + ((NR_MAC_CE_TA *) ce_ptr)->TAGID = tag_id; } - // Timing Advance subheader - /* This was done only when timing_advance_cmd != 31 - // now TA is always send when ta_timer resets regardless of its value - // this is done to avoid issues with the timeAlignmentTimer which is - // supposed to monitor if the UE received TA or not */ - if (gNB->ta_len) { - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_TA_COMMAND; - //last_size = 1; - mac_pdu_ptr++; + LOG_D(MAC, "NR MAC CE timing advance command = %d (%d) TAG ID = %d\n", timing_advance_cmd, ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND, tag_id); + mac_ce_size = sizeof(NR_MAC_CE_TA); + // Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); + ce_ptr += mac_ce_size; + mac_pdu_ptr += (unsigned char) mac_ce_size; + } - // TA MAC CE (1 octet) - timing_advance_cmd = gNB->ta_command; - AssertFatal(timing_advance_cmd < 64, "timing_advance_cmd %d > 63\n", timing_advance_cmd); - ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND = timing_advance_cmd; //(timing_advance_cmd+31)&0x3f; - if (gNB->tag->tag_Id != 0) { - tag_id = gNB->tag->tag_Id; - ((NR_MAC_CE_TA *) ce_ptr)->TAGID = tag_id; - } + // Contention resolution fixed subheader and MAC CE + if (ue_cont_res_id) { + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_CON_RES_ID; + mac_pdu_ptr++; + //last_size = 1; + // contention resolution identity MAC ce has a fixed 48 bit size + // this contains the UL CCCH SDU. If UL CCCH SDU is longer than 48 bits, + // it contains the first 48 bits of the UL CCCH SDU + LOG_T(MAC, "[gNB ][RAPROC] Generate contention resolution msg: %x.%x.%x.%x.%x.%x\n", + ue_cont_res_id[0], ue_cont_res_id[1], ue_cont_res_id[2], + ue_cont_res_id[3], ue_cont_res_id[4], ue_cont_res_id[5]); + // Copying bytes (6 octects) to CEs pointer + mac_ce_size = 6; + memcpy(ce_ptr, ue_cont_res_id, mac_ce_size); + // Copying bytes for MAC CEs to mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); + ce_ptr += mac_ce_size; + mac_pdu_ptr += (unsigned char) mac_ce_size; + } - LOG_D(MAC, "NR MAC CE timing advance command = %d (%d) TAG ID = %d\n", timing_advance_cmd, ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND, tag_id); + //TS 38.321 Sec 6.1.3.15 TCI State indication for UE Specific PDCCH MAC CE SubPDU generation + if (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.is_scheduled) { + //filling subheader + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_TCI_STATE_IND_UE_SPEC_PDCCH; + mac_pdu_ptr++; + //Creating the instance of CE structure + NR_TCI_PDCCH nr_UESpec_TCI_StateInd_PDCCH; + //filling the CE structre + nr_UESpec_TCI_StateInd_PDCCH.CoresetId1 = ((ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0xF) >> 1; //extracting MSB 3 bits from LS nibble + nr_UESpec_TCI_StateInd_PDCCH.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.servingCellId) & 0x1F; //extracting LSB 5 Bits + nr_UESpec_TCI_StateInd_PDCCH.TciStateId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.tciStateId) & 0x7F; //extracting LSB 7 bits + nr_UESpec_TCI_StateInd_PDCCH.CoresetId2 = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0x1; //extracting LSB 1 bit + LOG_D(MAC, "NR MAC CE TCI state indication for UE Specific PDCCH = %d \n", nr_UESpec_TCI_StateInd_PDCCH.TciStateId); + mac_ce_size = sizeof(NR_TCI_PDCCH); + // Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)&nr_UESpec_TCI_StateInd_PDCCH, mac_ce_size); + //incrementing the PDU pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + } - mac_ce_size = sizeof(NR_MAC_CE_TA); + //TS 38.321 Sec 6.1.3.16, SP CSI reporting on PUCCH Activation/Deactivation MAC CE + if (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.is_scheduled) { + //filling the subheader + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_REP_PUCCH_ACT; + mac_pdu_ptr++; + //creating the instance of CE structure + NR_PUCCH_CSI_REPORTING nr_PUCCH_CSI_reportingActDeact; + //filling the CE structure + nr_PUCCH_CSI_reportingActDeact.BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.bwpId) & 0x3; //extracting LSB 2 bibs + nr_PUCCH_CSI_reportingActDeact.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.servingCellId) & 0x1F; //extracting LSB 5 bits + nr_PUCCH_CSI_reportingActDeact.S0 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[0]; + nr_PUCCH_CSI_reportingActDeact.S1 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[1]; + nr_PUCCH_CSI_reportingActDeact.S2 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[2]; + nr_PUCCH_CSI_reportingActDeact.S3 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[3]; + nr_PUCCH_CSI_reportingActDeact.R2 = 0; + mac_ce_size = sizeof(NR_PUCCH_CSI_REPORTING); + // Copying MAC CE data to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)&nr_PUCCH_CSI_reportingActDeact, mac_ce_size); + //incrementing the PDU pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + } - // Copying bytes for MAC CEs to the mac pdu pointer - memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); - ce_ptr += mac_ce_size; - mac_pdu_ptr += (unsigned char) mac_ce_size; + //TS 38.321 Sec 6.1.3.14, TCI State activation/deactivation for UE Specific PDSCH MAC CE + if (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.is_scheduled) { + //Computing the number of octects to be allocated for Flexible array member + //of MAC CE structure + uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.highestTciStateActivated) / 8 + 1; //Calculating the number of octects for allocating the memory + //filling the subheader + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_TCI_STATE_ACT_UE_SPEC_PDSCH; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + last_size = 2; + //Incrementing the PDU pointer + mac_pdu_ptr += last_size; + //allocating memory for CE Structure + NR_TCI_PDSCH_APERIODIC_CSI *nr_UESpec_TCI_StateInd_PDSCH = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //initializing to zero + memset((void *)nr_UESpec_TCI_StateInd_PDSCH, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //filling the CE Structure + nr_UESpec_TCI_StateInd_PDSCH->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.bwpId) & 0x3; //extracting LSB 2 Bits + nr_UESpec_TCI_StateInd_PDSCH->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.servingCellId) & 0x1F; //extracting LSB 5 bits + + for(i = 0; i < (num_octects * 8); i++) { + if(ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.tciStateActDeact[i]) + nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] = nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] | (1 << (i % 8)); } - // Contention resolution fixed subheader and MAC CE - if (ue_cont_res_id) { - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_CON_RES_ID; - mac_pdu_ptr++; - //last_size = 1; + mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + //Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)nr_UESpec_TCI_StateInd_PDSCH, mac_ce_size); + //incrementing the mac pdu pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + //freeing the allocated memory + free(nr_UESpec_TCI_StateInd_PDSCH); + } - // contention resolution identity MAC ce has a fixed 48 bit size - // this contains the UL CCCH SDU. If UL CCCH SDU is longer than 48 bits, - // it contains the first 48 bits of the UL CCCH SDU - LOG_T(MAC, "[gNB ][RAPROC] Generate contention resolution msg: %x.%x.%x.%x.%x.%x\n", - ue_cont_res_id[0], ue_cont_res_id[1], ue_cont_res_id[2], - ue_cont_res_id[3], ue_cont_res_id[4], ue_cont_res_id[5]); + //TS38.321 Sec 6.1.3.13 Aperiodic CSI Trigger State Subselection MAC CE + if (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.is_scheduled) { + //Computing the number of octects to be allocated for Flexible array member + //of MAC CE structure + uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.highestTriggerStateSelected) / 8 + 1; //Calculating the number of octects for allocating the memory + //filling the subheader + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_APERIODIC_CSI_TRI_STATE_SUBSEL; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + last_size = 2; + //Incrementing the PDU pointer + mac_pdu_ptr += last_size; + //allocating memory for CE structure + NR_TCI_PDSCH_APERIODIC_CSI *nr_Aperiodic_CSI_Trigger = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //initializing to zero + memset((void *)nr_Aperiodic_CSI_Trigger, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //filling the CE Structure + nr_Aperiodic_CSI_Trigger->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.bwpId) & 0x3; //extracting LSB 2 bits + nr_Aperiodic_CSI_Trigger->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.servingCellId) & 0x1F; //extracting LSB 5 bits + nr_Aperiodic_CSI_Trigger->R = 0; - // Copying bytes (6 octects) to CEs pointer - mac_ce_size = 6; - memcpy(ce_ptr, ue_cont_res_id, mac_ce_size); - - // Copying bytes for MAC CEs to mac pdu pointer - memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); - ce_ptr += mac_ce_size; - mac_pdu_ptr += (unsigned char) mac_ce_size; + for(i = 0; i < (num_octects * 8); i++) { + if(ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.triggerStateSelection[i]) + nr_Aperiodic_CSI_Trigger->T[i / 8] = nr_Aperiodic_CSI_Trigger->T[i / 8] | (1 << (i % 8)); } -#ifdef GES_SUPPORT + mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + // Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)nr_Aperiodic_CSI_Trigger, mac_ce_size); + //incrementing the mac pdu pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + //freeing the allocated memory + free(nr_Aperiodic_CSI_Trigger); + } - //TS 38.321 Sec 6.1.3.15 TCI State indication for UE Specific PDCCH MAC CE SubPDU generation - if (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.is_scheduled) { - //filling subheader - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_TCI_STATE_IND_UE_SPEC_PDCCH; - mac_pdu_ptr++; - //Creating the instance of CE structure - NR_TCI_PDCCH nr_UESpec_TCI_StateInd_PDCCH; - //filling the CE structre - nr_UESpec_TCI_StateInd_PDCCH.CoresetId1 = ((ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0xF) >> 1; //extracting MSB 3 bits from LS nibble - nr_UESpec_TCI_StateInd_PDCCH.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.servingCellId) & 0x1F; //extracting LSB 5 Bits - nr_UESpec_TCI_StateInd_PDCCH.TciStateId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.tciStateId) & 0x7F; //extracting LSB 7 bits - nr_UESpec_TCI_StateInd_PDCCH.CoresetId2 = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0x1; //extracting LSB 1 bit - LOG_D(MAC, "NR MAC CE TCI state indication for UE Specific PDCCH = %d \n", nr_UESpec_TCI_StateInd_PDCCH.TciStateId); - mac_ce_size = sizeof(NR_TCI_PDCCH); - // Copying bytes for MAC CEs to the mac pdu pointer - memcpy((void *) mac_pdu_ptr, (void *)&nr_UESpec_TCI_StateInd_PDCCH, mac_ce_size); - //incrementing the PDU pointer - mac_pdu_ptr += (unsigned char) mac_ce_size; - } + if (ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.is_scheduled) { + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_SP_ZP_CSI_RS_RES_SET_ACT; + mac_pdu_ptr++; + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->A_D = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.act_deact; + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CELLID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id & 0x1F; //5 bits + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->BWPID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid & 0x3; //2 bits + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CSIRS_RSC_ID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id & 0xF; //4 bits + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->R = 0; + LOG_D(MAC, "NR MAC CE of ZP CSIRS Serv cell ID = %d BWPID= %d Rsc set ID = %d\n", ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id, ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid, + ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id); + mac_ce_size = sizeof(NR_MAC_CE_SP_ZP_CSI_RS_RES_SET); + mac_pdu_ptr += (unsigned char) mac_ce_size; + } - //TS 38.321 Sec 6.1.3.16, SP CSI reporting on PUCCH Activation/Deactivation MAC CE - if (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.is_scheduled) { - //filling the subheader - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_REP_PUCCH_ACT; - mac_pdu_ptr++; - //creating the instance of CE structure - NR_PUCCH_CSI_REPORTING nr_PUCCH_CSI_reportingActDeact; - //filling the CE structure - nr_PUCCH_CSI_reportingActDeact.BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.bwpId) & 0x3; //extracting LSB 2 bibs - nr_PUCCH_CSI_reportingActDeact.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.servingCellId) & 0x1F; //extracting LSB 5 bits - nr_PUCCH_CSI_reportingActDeact.S0 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[0]; - nr_PUCCH_CSI_reportingActDeact.S1 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[1]; - nr_PUCCH_CSI_reportingActDeact.S2 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[2]; - nr_PUCCH_CSI_reportingActDeact.S3 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[3]; - nr_PUCCH_CSI_reportingActDeact.R2 = 0; - mac_ce_size = sizeof(NR_PUCCH_CSI_REPORTING); - // Copying MAC CE data to the mac pdu pointer - memcpy((void *) mac_pdu_ptr, (void *)&nr_PUCCH_CSI_reportingActDeact, mac_ce_size); - //incrementing the PDU pointer - mac_pdu_ptr += (unsigned char) mac_ce_size; - } - - //TS 38.321 Sec 6.1.3.14, TCI State activation/deactivation for UE Specific PDSCH MAC CE - if (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.is_scheduled) { - //Computing the number of octects to be allocated for Flexible array member - //of MAC CE structure - uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.highestTciStateActivated) / 8 + 1; //Calculating the number of octects for allocating the memory - - //filling the subheader - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_TCI_STATE_ACT_UE_SPEC_PDSCH; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); - last_size = 2; - //Incrementing the PDU pointer - mac_pdu_ptr += last_size; - //allocating memory for CE Structure - NR_TCI_PDSCH_APERIODIC_CSI *nr_UESpec_TCI_StateInd_PDSCH = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); - //initializing to zero - memset((void *)nr_UESpec_TCI_StateInd_PDSCH, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); - //filling the CE Structure - nr_UESpec_TCI_StateInd_PDSCH->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.bwpId) & 0x3; //extracting LSB 2 Bits - nr_UESpec_TCI_StateInd_PDSCH->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.servingCellId) & 0x1F; //extracting LSB 5 bits - for(i = 0; i < (num_octects * 8); i++) { - if(ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.tciStateActDeact[i]) - nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] = nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] | (1 << (i % 8)); - } - mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); - //Copying bytes for MAC CEs to the mac pdu pointer - memcpy((void *) mac_pdu_ptr, (void *)nr_UESpec_TCI_StateInd_PDSCH, mac_ce_size); - //incrementing the mac pdu pointer - mac_pdu_ptr += (unsigned char) mac_ce_size; - //freeing the allocated memory - free(nr_UESpec_TCI_StateInd_PDSCH); - } - - //TS38.321 Sec 6.1.3.13 Aperiodic CSI Trigger State Subselection MAC CE - if (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.is_scheduled) { - //Computing the number of octects to be allocated for Flexible array member - //of MAC CE structure - uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.highestTriggerStateSelected) / 8 + 1; //Calculating the number of octects for allocating the memory - - //filling the subheader - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_APERIODIC_CSI_TRI_STATE_SUBSEL; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); - last_size = 2; - //Incrementing the PDU pointer - mac_pdu_ptr += last_size; - //allocating memory for CE structure - NR_TCI_PDSCH_APERIODIC_CSI *nr_Aperiodic_CSI_Trigger = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); - //initializing to zero - memset((void *)nr_Aperiodic_CSI_Trigger, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); - //filling the CE Structure - nr_Aperiodic_CSI_Trigger->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.bwpId) & 0x3; //extracting LSB 2 bits - nr_Aperiodic_CSI_Trigger->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.servingCellId) & 0x1F; //extracting LSB 5 bits - nr_Aperiodic_CSI_Trigger->R = 0; - for(i = 0; i < (num_octects * 8); i++) { - if(ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.triggerStateSelection[i]) - nr_Aperiodic_CSI_Trigger->T[i / 8] = nr_Aperiodic_CSI_Trigger->T[i / 8] | (1 << (i % 8)); - } - mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); - // Copying bytes for MAC CEs to the mac pdu pointer - memcpy((void *) mac_pdu_ptr, (void *)nr_Aperiodic_CSI_Trigger, mac_ce_size); - //incrementing the mac pdu pointer - mac_pdu_ptr += (unsigned char) mac_ce_size; - //freeing the allocated memory - free(nr_Aperiodic_CSI_Trigger); - } - - if (ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.is_scheduled) { - ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_SP_ZP_CSI_RS_RES_SET_ACT; - mac_pdu_ptr++; - ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->A_D = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.act_deact; - ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CELLID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id & 0x1F; //5 bits - ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->BWPID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid & 0x3; //2 bits - ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CSIRS_RSC_ID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id & 0xF; //4 bits - ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->R = 0; - LOG_D(MAC, "NR MAC CE of ZP CSIRS Serv cell ID = %d BWPID= %d Rsc set ID = %d\n", ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id, ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid, ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id); - mac_ce_size = sizeof(NR_MAC_CE_SP_ZP_CSI_RS_RES_SET); - mac_pdu_ptr += (unsigned char) mac_ce_size; - } - - if (ue_sched_ctl->UE_mac_ce_ctrl.csi_im.is_scheduled) { - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT; - mac_pdu_ptr++; - CSI_RS_CSI_IM_ACT_DEACT_MAC_CE csi_rs_im_act_deact_ce; - csi_rs_im_act_deact_ce.A_D = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.act_deact; - csi_rs_im_act_deact_ce.SCID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.serv_cellid & 0x3F;//gNB_PHY -> ssb_pdu.ssb_pdu_rel15.PhysCellId; - csi_rs_im_act_deact_ce.BWP_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.bwp_id; - csi_rs_im_act_deact_ce.R1 = 0; - csi_rs_im_act_deact_ce.IM = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.im;// IF set CSI IM Rsc id will presesent else CSI IM RSC ID is abscent - csi_rs_im_act_deact_ce.SP_CSI_RSID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nzp_csi_rsc_id; - - if ( csi_rs_im_act_deact_ce.IM ) { //is_scheduled if IM is 1 else this field will not present - csi_rs_im_act_deact_ce.R2 = 0; - csi_rs_im_act_deact_ce.SP_CSI_IMID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.csi_im_rsc_id; - mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE ); - } else { - mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE ) - 1; - } - - memcpy ((void *) mac_pdu_ptr, (void *) & ( csi_rs_im_act_deact_ce), mac_ce_size); - mac_pdu_ptr += (unsigned char) mac_ce_size; - - if (csi_rs_im_act_deact_ce.A_D ) { //Following IE is_scheduled only if A/D is 1 - mac_ce_size = sizeof ( struct TCI_S); - - for ( i = 0; i < ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nb_tci_resource_set_id; i++) { - csi_rs_im_act_deact_ce.TCI_STATE.R = 0; - csi_rs_im_act_deact_ce.TCI_STATE.TCI_STATE_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.tci_state_id [i] & 0x7F; - memcpy ((void *) mac_pdu_ptr, (void *) & (csi_rs_im_act_deact_ce.TCI_STATE), mac_ce_size); - mac_pdu_ptr += (unsigned char) mac_ce_size; - } - - } - } - -#endif - - // 2) Generation of DLSCH MAC subPDUs including subheaders and MAC SDUs - for (i = 0; i < num_sdus; i++) { - LOG_D(MAC, "[gNB] Generate DLSCH header num sdu %d len sdu %d\n", num_sdus, sdu_lengths[i]); - - if (sdu_lengths[i] < 128) { - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = sdu_lcids[i]; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = (unsigned char) sdu_lengths[i]; - last_size = 2; - } else { - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->F = 1; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->LCID = sdu_lcids[i]; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L1 = ((unsigned short) sdu_lengths[i] >> 8) & 0x7f; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L2 = (unsigned short) sdu_lengths[i] & 0xff; - last_size = 3; - } - - mac_pdu_ptr += last_size; - - // 3) cycle through SDUs, compute each relevant and place dlsch_buffer in - memcpy((void *) mac_pdu_ptr, (void *) dlsch_buffer_ptr, sdu_lengths[i]); - dlsch_buffer_ptr += sdu_lengths[i]; - mac_pdu_ptr += sdu_lengths[i]; - } - - // 4) Compute final offset for padding - if (post_padding > 0) { - ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_PADDING; - mac_pdu_ptr++; + if (ue_sched_ctl->UE_mac_ce_ctrl.csi_im.is_scheduled) { + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT; + mac_pdu_ptr++; + CSI_RS_CSI_IM_ACT_DEACT_MAC_CE csi_rs_im_act_deact_ce; + csi_rs_im_act_deact_ce.A_D = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.act_deact; + csi_rs_im_act_deact_ce.SCID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.serv_cellid & 0x3F;//gNB_PHY -> ssb_pdu.ssb_pdu_rel15.PhysCellId; + csi_rs_im_act_deact_ce.BWP_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.bwp_id; + csi_rs_im_act_deact_ce.R1 = 0; + csi_rs_im_act_deact_ce.IM = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.im;// IF set CSI IM Rsc id will presesent else CSI IM RSC ID is abscent + csi_rs_im_act_deact_ce.SP_CSI_RSID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nzp_csi_rsc_id; + if ( csi_rs_im_act_deact_ce.IM ) { //is_scheduled if IM is 1 else this field will not present + csi_rs_im_act_deact_ce.R2 = 0; + csi_rs_im_act_deact_ce.SP_CSI_IMID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.csi_im_rsc_id; + mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE ); } else { - // no MAC subPDU with padding + mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE ) - 1; } - // compute final offset - offset = ((unsigned char *) mac_pdu_ptr - mac_pdu); + memcpy ((void *) mac_pdu_ptr, (void *) & ( csi_rs_im_act_deact_ce), mac_ce_size); + mac_pdu_ptr += (unsigned char) mac_ce_size; - //printf("Offset %d \n", ((unsigned char *) mac_pdu_ptr - mac_pdu)); + if (csi_rs_im_act_deact_ce.A_D ) { //Following IE is_scheduled only if A/D is 1 + mac_ce_size = sizeof ( struct TCI_S); - return offset; + for ( i = 0; i < ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nb_tci_resource_set_id; i++) { + csi_rs_im_act_deact_ce.TCI_STATE.R = 0; + csi_rs_im_act_deact_ce.TCI_STATE.TCI_STATE_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.tci_state_id [i] & 0x7F; + memcpy ((void *) mac_pdu_ptr, (void *) & (csi_rs_im_act_deact_ce.TCI_STATE), mac_ce_size); + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + } + } + + // 2) Generation of DLSCH MAC subPDUs including subheaders and MAC SDUs + for (i = 0; i < num_sdus; i++) { + LOG_D(MAC, "[gNB] Generate DLSCH header num sdu %d len sdu %d\n", num_sdus, sdu_lengths[i]); + + if (sdu_lengths[i] < 128) { + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = sdu_lcids[i]; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = (unsigned char) sdu_lengths[i]; + last_size = 2; + } else { + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->F = 1; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->LCID = sdu_lcids[i]; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L1 = ((unsigned short) sdu_lengths[i] >> 8) & 0x7f; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L2 = (unsigned short) sdu_lengths[i] & 0xff; + last_size = 3; + } + + mac_pdu_ptr += last_size; + // 3) cycle through SDUs, compute each relevant and place dlsch_buffer in + memcpy((void *) mac_pdu_ptr, (void *) dlsch_buffer_ptr, sdu_lengths[i]); + dlsch_buffer_ptr += sdu_lengths[i]; + mac_pdu_ptr += sdu_lengths[i]; + } + + // 4) Compute final offset for padding + if (post_padding > 0) { + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_PADDING; + mac_pdu_ptr++; + } else { + // no MAC subPDU with padding + } + + // compute final offset + offset = ((unsigned char *) mac_pdu_ptr - mac_pdu); + //printf("Offset %d \n", ((unsigned char *) mac_pdu_ptr - mac_pdu)); + return offset; } /* functionalities of this function have been moved to nr_schedule_uss_dlsch_phytest */ diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index 7825d72fdb..c00c1b3927 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -76,325 +76,321 @@ #define NR_NB_RA_PROC_MAX 4 typedef enum { - RA_IDLE = 0, - Msg2 = 1, - WAIT_Msg3 = 2, - Msg4 = 3, - WAIT_Msg4_ACK = 4 + RA_IDLE = 0, + Msg2 = 1, + WAIT_Msg3 = 2, + Msg4 = 3, + WAIT_Msg4_ACK = 4 } RA_gNB_state_t; /*! \brief gNB template for the Random access information */ typedef struct { - /// Flag to indicate this process is active - RA_gNB_state_t state; - /// BWP id of RA process - int bwp_id; - /// CORESET0 configured flag - int coreset0_configured; - /// Slot where preamble was received - uint8_t preamble_slot; - /// Subframe where Msg2 is to be sent - uint8_t Msg2_slot; - /// Frame where Msg2 is to be sent - frame_t Msg2_frame; - /// Subframe where Msg3 is to be sent - sub_frame_t Msg3_slot; - /// Frame where Msg3 is to be sent - frame_t Msg3_frame; - /// Msg3 time domain allocation index - uint8_t Msg3_tda_id; - /// Subframe where Msg4 is to be sent - sub_frame_t Msg4_slot; - /// Frame where Msg4 is to be sent - frame_t Msg4_frame; - /// harq_pid used for Msg4 transmission - uint8_t harq_pid; - /// UE RNTI allocated during RAR - rnti_t rnti; - /// RA RNTI allocated from received PRACH - uint16_t RA_rnti; - /// Received preamble_index - uint8_t preamble_index; - /// Received UE Contention Resolution Identifier - uint8_t cont_res_id[6]; - /// Timing offset indicated by PHY - int16_t timing_offset; - /// Timeout for RRC connection - int16_t RRC_timer; - /// Msg3 first RB - uint8_t msg3_first_rb; - /// Msg3 number of RB - uint8_t msg3_nb_rb; - /// Msg3 TPC command - uint8_t msg3_TPC; - /// Msg3 ULdelay command - uint8_t msg3_ULdelay; - /// Msg3 cqireq command - uint8_t msg3_cqireq; - /// Round of Msg3 HARQ - uint8_t msg3_round; - /// Msg3 pusch pdu - nfapi_nr_pusch_pdu_t pusch_pdu; - /// TBS used for Msg4 - int msg4_TBsize; - /// MCS used for Msg4 - int msg4_mcs; - /// RA search space - NR_SearchSpace_t *ra_ss; + /// Flag to indicate this process is active + RA_gNB_state_t state; + /// BWP id of RA process + int bwp_id; + /// CORESET0 configured flag + int coreset0_configured; + /// Slot where preamble was received + uint8_t preamble_slot; + /// Subframe where Msg2 is to be sent + uint8_t Msg2_slot; + /// Frame where Msg2 is to be sent + frame_t Msg2_frame; + /// Subframe where Msg3 is to be sent + sub_frame_t Msg3_slot; + /// Frame where Msg3 is to be sent + frame_t Msg3_frame; + /// Msg3 time domain allocation index + uint8_t Msg3_tda_id; + /// Subframe where Msg4 is to be sent + sub_frame_t Msg4_slot; + /// Frame where Msg4 is to be sent + frame_t Msg4_frame; + /// harq_pid used for Msg4 transmission + uint8_t harq_pid; + /// UE RNTI allocated during RAR + rnti_t rnti; + /// RA RNTI allocated from received PRACH + uint16_t RA_rnti; + /// Received preamble_index + uint8_t preamble_index; + /// Received UE Contention Resolution Identifier + uint8_t cont_res_id[6]; + /// Timing offset indicated by PHY + int16_t timing_offset; + /// Timeout for RRC connection + int16_t RRC_timer; + /// Msg3 first RB + uint8_t msg3_first_rb; + /// Msg3 number of RB + uint8_t msg3_nb_rb; + /// Msg3 TPC command + uint8_t msg3_TPC; + /// Msg3 ULdelay command + uint8_t msg3_ULdelay; + /// Msg3 cqireq command + uint8_t msg3_cqireq; + /// Round of Msg3 HARQ + uint8_t msg3_round; + /// Msg3 pusch pdu + nfapi_nr_pusch_pdu_t pusch_pdu; + /// TBS used for Msg4 + int msg4_TBsize; + /// MCS used for Msg4 + int msg4_mcs; + /// RA search space + NR_SearchSpace_t *ra_ss; } NR_RA_t; /*! \brief gNB common channels */ typedef struct { - int physCellId; - int p_gNB; - int Ncp; - int nr_band; - lte_frame_type_t frame_type; - uint64_t dl_CarrierFreq; - NR_BCCH_BCH_Message_t *mib; - NR_ServingCellConfigCommon_t *ServingCellConfigCommon; - NR_ARFCN_ValueEUTRA_t ul_CarrierFreq; - long ul_Bandwidth; - /// Outgoing MIB PDU for PHY - MIB_PDU MIB_pdu; - /// Outgoing BCCH pdu for PHY - BCCH_PDU BCCH_pdu; - /// Outgoing BCCH DCI allocation - uint32_t BCCH_alloc_pdu; - /// Outgoing CCCH pdu for PHY - CCCH_PDU CCCH_pdu; - /// Outgoing PCCH DCI allocation - uint32_t PCCH_alloc_pdu; - /// Outgoing PCCH pdu for PHY - PCCH_PDU PCCH_pdu; - /// Outgoing RAR pdu for PHY - RAR_PDU RAR_pdu; - /// Template for RA computations - NR_RA_t ra[NR_NB_RA_PROC_MAX]; - /// VRB map for common channels - uint8_t vrb_map[100]; - /// VRB map for common channels and retransmissions by PHICH - uint8_t vrb_map_UL[100]; - /// number of subframe allocation pattern available for MBSFN sync area - uint8_t num_sf_allocation_pattern; + int physCellId; + int p_gNB; + int Ncp; + int nr_band; + lte_frame_type_t frame_type; + uint64_t dl_CarrierFreq; + NR_BCCH_BCH_Message_t *mib; + NR_ServingCellConfigCommon_t *ServingCellConfigCommon; + NR_ARFCN_ValueEUTRA_t ul_CarrierFreq; + long ul_Bandwidth; + /// Outgoing MIB PDU for PHY + MIB_PDU MIB_pdu; + /// Outgoing BCCH pdu for PHY + BCCH_PDU BCCH_pdu; + /// Outgoing BCCH DCI allocation + uint32_t BCCH_alloc_pdu; + /// Outgoing CCCH pdu for PHY + CCCH_PDU CCCH_pdu; + /// Outgoing PCCH DCI allocation + uint32_t PCCH_alloc_pdu; + /// Outgoing PCCH pdu for PHY + PCCH_PDU PCCH_pdu; + /// Outgoing RAR pdu for PHY + RAR_PDU RAR_pdu; + /// Template for RA computations + NR_RA_t ra[NR_NB_RA_PROC_MAX]; + /// VRB map for common channels + uint8_t vrb_map[100]; + /// VRB map for common channels and retransmissions by PHICH + uint8_t vrb_map_UL[100]; + /// number of subframe allocation pattern available for MBSFN sync area + uint8_t num_sf_allocation_pattern; } NR_COMMON_channels_t; -#ifdef GES_SUPPORT // SP ZP CSI-RS Resource Set Activation/Deactivation MAC CE typedef struct sp_zp_csirs { - bool is_scheduled; //ZP CSI-RS ACT/Deact MAC CE is scheduled - bool act_deact; //Activation/Deactivation indication - uint8_t serv_cell_id; //Identity of Serving cell for which MAC CE applies - uint8_t bwpid; //Downlink BWP id - uint8_t rsc_id; //SP ZP CSI-RS resource set + bool is_scheduled; //ZP CSI-RS ACT/Deact MAC CE is scheduled + bool act_deact; //Activation/Deactivation indication + uint8_t serv_cell_id; //Identity of Serving cell for which MAC CE applies + uint8_t bwpid; //Downlink BWP id + uint8_t rsc_id; //SP ZP CSI-RS resource set } sp_zp_csirs_t; //SP CSI-RS / CSI-IM Resource Set Activation/Deactivation MAC CE #define MAX_CSI_RESOURCE_SET 64 typedef struct csi_rs_im { - bool is_scheduled; - bool act_deact; - uint8_t serv_cellid; - uint8_t bwp_id; - bool im; - uint8_t csi_im_rsc_id; - uint8_t nzp_csi_rsc_id; - uint8_t nb_tci_resource_set_id; - uint8_t tci_state_id [ MAX_CSI_RESOURCE_SET ]; + bool is_scheduled; + bool act_deact; + uint8_t serv_cellid; + uint8_t bwp_id; + bool im; + uint8_t csi_im_rsc_id; + uint8_t nzp_csi_rsc_id; + uint8_t nb_tci_resource_set_id; + uint8_t tci_state_id [ MAX_CSI_RESOURCE_SET ]; } csi_rs_im_t; typedef struct pdcchStateInd { - bool is_scheduled; - uint8_t servingCellId; - uint8_t coresetId; - uint8_t tciStateId; + bool is_scheduled; + uint8_t servingCellId; + uint8_t coresetId; + uint8_t tciStateId; } pdcchStateInd_t; typedef struct SPCSIReportingpucch { - bool is_scheduled; - uint8_t servingCellId; - uint8_t bwpId; - bool s0tos3_actDeact[4]; + bool is_scheduled; + uint8_t servingCellId; + uint8_t bwpId; + bool s0tos3_actDeact[4]; } SPCSIReportingpucch_t; #define MAX_APERIODIC_TRIGGER_STATES 128 //38.331 typedef struct aperiodicCSI_triggerStateSelection { - bool is_scheduled; - uint8_t servingCellId; - uint8_t bwpId; - uint8_t highestTriggerStateSelected; - bool triggerStateSelection[MAX_APERIODIC_TRIGGER_STATES]; + bool is_scheduled; + uint8_t servingCellId; + uint8_t bwpId; + uint8_t highestTriggerStateSelected; + bool triggerStateSelection[MAX_APERIODIC_TRIGGER_STATES]; } aperiodicCSI_triggerStateSelection_t; #define MAX_TCI_STATES 128 //38.331 typedef struct pdschTciStatesActDeact { - bool is_scheduled; - uint8_t servingCellId; - uint8_t bwpId; - uint8_t highestTciStateActivated; - bool tciStateActDeact[MAX_TCI_STATES]; + bool is_scheduled; + uint8_t servingCellId; + uint8_t bwpId; + uint8_t highestTciStateActivated; + bool tciStateActDeact[MAX_TCI_STATES]; } pdschTciStatesActDeact_t; typedef struct UE_info { - sp_zp_csirs_t sp_zp_csi_rs; - csi_rs_im_t csi_im; - pdcchStateInd_t pdcch_state_ind; - SPCSIReportingpucch_t SP_CSI_reporting_pucch; - aperiodicCSI_triggerStateSelection_t aperi_CSI_trigger; - pdschTciStatesActDeact_t pdsch_TCI_States_ActDeact; + sp_zp_csirs_t sp_zp_csi_rs; + csi_rs_im_t csi_im; + pdcchStateInd_t pdcch_state_ind; + SPCSIReportingpucch_t SP_CSI_reporting_pucch; + aperiodicCSI_triggerStateSelection_t aperi_CSI_trigger; + pdschTciStatesActDeact_t pdsch_TCI_States_ActDeact; } NR_UE_mac_ce_ctrl_t; -#endif /*! \brief scheduling control information set through an API (not used)*/ typedef struct { - int dummy; -#ifdef GES_SUPPORT - NR_UE_mac_ce_ctrl_t UE_mac_ce_ctrl;// MAC CE related information -#endif + int dummy; + NR_UE_mac_ce_ctrl_t UE_mac_ce_ctrl;// MAC CE related information } NR_UE_sched_ctrl_t; /*! \brief UE list used by gNB to order UEs/CC for scheduling*/ typedef struct { - DLSCH_PDU DLSCH_pdu[4][MAX_MOBILES_PER_GNB]; - /// scheduling control info - UE_sched_ctrl_t UE_sched_ctrl[MAX_MOBILES_PER_GNB]; - int next[MAX_MOBILES_PER_GNB]; - int head; - int next_ul[MAX_MOBILES_PER_GNB]; - int head_ul; - int avail; - int num_UEs; - boolean_t active[MAX_MOBILES_PER_GNB]; - rnti_t rnti[MAX_MOBILES_PER_GNB]; - NR_CellGroupConfig_t *secondaryCellGroup[MAX_MOBILES_PER_GNB]; + DLSCH_PDU DLSCH_pdu[4][MAX_MOBILES_PER_GNB]; + /// scheduling control info + UE_sched_ctrl_t UE_sched_ctrl[MAX_MOBILES_PER_GNB]; + int next[MAX_MOBILES_PER_GNB]; + int head; + int next_ul[MAX_MOBILES_PER_GNB]; + int head_ul; + int avail; + int num_UEs; + boolean_t active[MAX_MOBILES_PER_GNB]; + rnti_t rnti[MAX_MOBILES_PER_GNB]; + NR_CellGroupConfig_t *secondaryCellGroup[MAX_MOBILES_PER_GNB]; } NR_UE_list_t; /*! \brief top level eNB MAC structure */ typedef struct gNB_MAC_INST_s { - /// Ethernet parameters for northbound midhaul interface - eth_params_t eth_params_n; - /// Ethernet parameters for fronthaul interface - eth_params_t eth_params_s; - /// Module - module_id_t Mod_id; - /// frame counter - frame_t frame; - /// slot counter - int slot; - /// timing advance group - NR_TAG_t *tag; - /// Pointer to IF module instance for PHY - NR_IF_Module_t *if_inst; - /// TA command - int ta_command; - /// MAC CE flag indicating TA length - int ta_len; - /// Common cell resources - NR_COMMON_channels_t common_channels[NFAPI_CC_MAX]; - /// current PDU index (BCH,DLSCH) - uint16_t pdu_index[NFAPI_CC_MAX]; + /// Ethernet parameters for northbound midhaul interface + eth_params_t eth_params_n; + /// Ethernet parameters for fronthaul interface + eth_params_t eth_params_s; + /// Module + module_id_t Mod_id; + /// frame counter + frame_t frame; + /// slot counter + int slot; + /// timing advance group + NR_TAG_t *tag; + /// Pointer to IF module instance for PHY + NR_IF_Module_t *if_inst; + /// TA command + int ta_command; + /// MAC CE flag indicating TA length + int ta_len; + /// Common cell resources + NR_COMMON_channels_t common_channels[NFAPI_CC_MAX]; + /// current PDU index (BCH,DLSCH) + uint16_t pdu_index[NFAPI_CC_MAX]; - /// NFAPI Config Request Structure - nfapi_nr_config_request_scf_t config[NFAPI_CC_MAX]; - /// NFAPI DL Config Request Structure - nfapi_nr_dl_tti_request_t DL_req[NFAPI_CC_MAX]; - /// NFAPI UL TTI Request Structure (this is from the new SCF specs) - nfapi_nr_ul_tti_request_t UL_tti_req[NFAPI_CC_MAX]; - /// NFAPI HI/DCI0 Config Request Structure - nfapi_nr_ul_dci_request_t UL_dci_req[NFAPI_CC_MAX]; - /// NFAPI DL PDU structure - nfapi_nr_tx_data_request_t TX_req[NFAPI_CC_MAX]; + /// NFAPI Config Request Structure + nfapi_nr_config_request_scf_t config[NFAPI_CC_MAX]; + /// NFAPI DL Config Request Structure + nfapi_nr_dl_tti_request_t DL_req[NFAPI_CC_MAX]; + /// NFAPI UL TTI Request Structure (this is from the new SCF specs) + nfapi_nr_ul_tti_request_t UL_tti_req[NFAPI_CC_MAX]; + /// NFAPI HI/DCI0 Config Request Structure + nfapi_nr_ul_dci_request_t UL_dci_req[NFAPI_CC_MAX]; + /// NFAPI DL PDU structure + nfapi_nr_tx_data_request_t TX_req[NFAPI_CC_MAX]; - NR_UE_list_t UE_list; + NR_UE_list_t UE_list; - /// UL handle - uint32_t ul_handle; + /// UL handle + uint32_t ul_handle; - // MAC function execution peformance profiler - /// processing time of eNB scheduler - time_stats_t eNB_scheduler; - /// processing time of eNB scheduler for SI - time_stats_t schedule_si; - /// processing time of eNB scheduler for Random access - time_stats_t schedule_ra; - /// processing time of eNB ULSCH scheduler - time_stats_t schedule_ulsch; - /// processing time of eNB DCI generation - time_stats_t fill_DLSCH_dci; - /// processing time of eNB MAC preprocessor - time_stats_t schedule_dlsch_preprocessor; - /// processing time of eNB DLSCH scheduler - time_stats_t schedule_dlsch; // include rlc_data_req + MAC header + preprocessor - /// processing time of eNB MCH scheduler - time_stats_t schedule_mch; - /// processing time of eNB ULSCH reception - time_stats_t rx_ulsch_sdu; // include rlc_data_ind - /// processing time of eNB PCH scheduler - time_stats_t schedule_pch; - /// CCE lists - int cce_list[MAX_NUM_BWP][MAX_NUM_CORESET][MAX_NUM_CCE]; + // MAC function execution peformance profiler + /// processing time of eNB scheduler + time_stats_t eNB_scheduler; + /// processing time of eNB scheduler for SI + time_stats_t schedule_si; + /// processing time of eNB scheduler for Random access + time_stats_t schedule_ra; + /// processing time of eNB ULSCH scheduler + time_stats_t schedule_ulsch; + /// processing time of eNB DCI generation + time_stats_t fill_DLSCH_dci; + /// processing time of eNB MAC preprocessor + time_stats_t schedule_dlsch_preprocessor; + /// processing time of eNB DLSCH scheduler + time_stats_t schedule_dlsch; // include rlc_data_req + MAC header + preprocessor + /// processing time of eNB MCH scheduler + time_stats_t schedule_mch; + /// processing time of eNB ULSCH reception + time_stats_t rx_ulsch_sdu; // include rlc_data_ind + /// processing time of eNB PCH scheduler + time_stats_t schedule_pch; + /// CCE lists + int cce_list[MAX_NUM_BWP][MAX_NUM_CORESET][MAX_NUM_CCE]; } gNB_MAC_INST; typedef struct { - uint8_t format_indicator; //1 bit - uint16_t frequency_domain_assignment; //up to 16 bits - uint8_t time_domain_assignment; // 4 bits - uint8_t frequency_hopping_flag; //1 bit + uint8_t format_indicator; //1 bit + uint16_t frequency_domain_assignment; //up to 16 bits + uint8_t time_domain_assignment; // 4 bits + uint8_t frequency_hopping_flag; //1 bit - uint8_t ra_preamble_index; //6 bits - uint8_t ss_pbch_index; //6 bits - uint8_t prach_mask_index; //4 bits + uint8_t ra_preamble_index; //6 bits + uint8_t ss_pbch_index; //6 bits + uint8_t prach_mask_index; //4 bits - uint8_t vrb_to_prb_mapping; //0 or 1 bit - uint8_t mcs; //5 bits - uint8_t ndi; //1 bit - uint8_t rv; //2 bits - uint8_t harq_pid; //4 bits - uint8_t dai; //0, 2 or 4 bits - uint8_t dai1; //1 or 2 bits - uint8_t dai2; //0 or 2 bits - uint8_t tpc; //2 bits - uint8_t pucch_resource_indicator; //3 bits - uint8_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits + uint8_t vrb_to_prb_mapping; //0 or 1 bit + uint8_t mcs; //5 bits + uint8_t ndi; //1 bit + uint8_t rv; //2 bits + uint8_t harq_pid; //4 bits + uint8_t dai; //0, 2 or 4 bits + uint8_t dai1; //1 or 2 bits + uint8_t dai2; //0 or 2 bits + uint8_t tpc; //2 bits + uint8_t pucch_resource_indicator; //3 bits + uint8_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits - uint8_t short_messages_indicator; //2 bits - uint8_t short_messages; //8 bits - uint8_t tb_scaling; //2 bits + uint8_t short_messages_indicator; //2 bits + uint8_t short_messages; //8 bits + uint8_t tb_scaling; //2 bits - uint8_t carrier_indicator; //0 or 3 bits - uint8_t bwp_indicator; //0, 1 or 2 bits - uint8_t prb_bundling_size_indicator; //0 or 1 bits - uint8_t rate_matching_indicator; //0, 1 or 2 bits - uint8_t zp_csi_rs_trigger; //0, 1 or 2 bits - uint8_t transmission_configuration_indication; //0 or 3 bits - uint8_t srs_request; //2 bits - uint8_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits - uint8_t cbgfi; //CBG Flushing Out Information: 0 or 1 bit - uint8_t dmrs_sequence_initialization; //0 or 1 bit + uint8_t carrier_indicator; //0 or 3 bits + uint8_t bwp_indicator; //0, 1 or 2 bits + uint8_t prb_bundling_size_indicator; //0 or 1 bits + uint8_t rate_matching_indicator; //0, 1 or 2 bits + uint8_t zp_csi_rs_trigger; //0, 1 or 2 bits + uint8_t transmission_configuration_indication; //0 or 3 bits + uint8_t srs_request; //2 bits + uint8_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits + uint8_t cbgfi; //CBG Flushing Out Information: 0 or 1 bit + uint8_t dmrs_sequence_initialization; //0 or 1 bit - uint8_t srs_resource_indicator; - uint8_t precoding_information; - uint8_t csi_request; - uint8_t ptrs_dmrs_association; - uint8_t beta_offset_indicator; //0 or 2 bits + uint8_t srs_resource_indicator; + uint8_t precoding_information; + uint8_t csi_request; + uint8_t ptrs_dmrs_association; + uint8_t beta_offset_indicator; //0 or 2 bits - uint8_t slot_format_indicator_count; - uint8_t *slot_format_indicators; + uint8_t slot_format_indicator_count; + uint8_t *slot_format_indicators; - uint8_t pre_emption_indication_count; - uint16_t *pre_emption_indications; //14 bit + uint8_t pre_emption_indication_count; + uint16_t *pre_emption_indications; //14 bit - uint8_t block_number_count; - uint8_t *block_numbers; + uint8_t block_number_count; + uint8_t *block_numbers; - uint8_t ul_sul_indicator; //0 or 1 bit - uint8_t antenna_ports; + uint8_t ul_sul_indicator; //0 or 1 bit + uint8_t antenna_ports; - uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits - uint16_t padding; + uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits + uint16_t padding; } dci_pdu_rel15_t; From 89acc094202781a8a51c68cf2556bcac1de8fe76 Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Thu, 4 Jun 2020 14:32:41 +0200 Subject: [PATCH 275/553] CI: fix the RAW files usage by NR-UE Signed-off-by: Raphael Defosseux --- ci-scripts/main.py | 18 +++++++++------ ci-scripts/ran.py | 3 +++ ci-scripts/rrc-files/rbconfig.raw | Bin 8 -> 0 bytes ci-scripts/rrc-files/reconfig.raw | Bin 479 -> 0 bytes ci-scripts/runTestOnVM.sh | 23 ++++++++++++++++++-- ci-scripts/xml_files/gnb_nr_ue_usrp_run.xml | 2 +- 6 files changed, 36 insertions(+), 10 deletions(-) delete mode 100644 ci-scripts/rrc-files/rbconfig.raw delete mode 100644 ci-scripts/rrc-files/reconfig.raw diff --git a/ci-scripts/main.py b/ci-scripts/main.py index e9313051fc..b7538097f8 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -332,12 +332,6 @@ class OaiCiTest(): logging.debug('Found a N3xx device --> resetting it') SSH.command('cd ' + self.UESourceCodePath, '\$', 5) # Initialize_OAI_UE_args usually start with -C and followed by the location in repository - # in case of NR-UE, we may have rrc_config_path (Temporary?) - modifiedUeOptions = str(self.Initialize_OAI_UE_args) - if RAN.Getair_interface() == 'nr': - result = re.search('--rrc_config_path ', modifiedUeOptions) - if result is not None: - modifiedUeOptions = modifiedUeOptions.replace('rrc_config_path ', 'rrc_config_path ' + self.UESourceCodePath + '/') SSH.command('source oaienv', '\$', 5) SSH.command('cd cmake_targets/ran_build/build', '\$', 5) if RAN.Getair_interface() == 'lte': @@ -352,7 +346,17 @@ class OaiCiTest(): SSH.command('sed -e "s#93#92#" -e "s#8baf473f2f8fd09487cccbd7097c6862#fec86ba6eb707ed08905757b1bb44b8f#" -e "s#e734f8734007d6c5ce7a0508809e7e9c#C42449363BBAD02B66D16BC975D77CC1#" ../../../openair3/NAS/TOOLS/ue_eurecom_test_sfr.conf > ../../../openair3/NAS/TOOLS/ci-ue_eurecom_test_sfr.conf', '\$', 5) SSH.command('echo ' + self.UEPassword + ' | sudo -S rm -Rf .u*', '\$', 5) SSH.command('echo ' + self.UEPassword + ' | sudo -S ../../../targets/bin/conf2uedata -c ../../../openair3/NAS/TOOLS/ci-ue_eurecom_test_sfr.conf -o .', '\$', 5) - SSH.command('echo "ulimit -c unlimited && ./'+ RAN.Getair_interface() +'-uesoftmodem ' + modifiedUeOptions + '" > ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5) + else: + SSH.command('if [ -e rbconfig.raw ]; then echo ' + self.UEPassword + ' | sudo -S rm rbconfig.raw; fi', '\$', 5) + SSH.command('if [ -e rbconfig.raw ]; then echo ' + self.UEPassword + ' | sudo -S rm reconfig.raw; fi', '\$', 5) + # Copy the RAW files from gNB running directory (maybe on another machine) + copyin_res = SSH.copyin(RAN.GeteNBIPAddress(), RAN.GeteNBUserName(), RAN.GeteNBPassword(), RAN.GeteNBSourceCodePath() + '/cmake_targets/rbconfig.raw', '.') + if (copyin_res == 0): + SSH.copyout(self.UEIPAddress, self.UEUserName, self.UEPassword, './rbconfig.raw', self.UESourceCodePath + '/cmake_targets/ran_build/build') + copyin_res = SSH.copyin(RAN.GeteNBIPAddress(), RAN.GeteNBUserName(), RAN.GeteNBPassword(), RAN.GeteNBSourceCodePath() + '/cmake_targets/reconfig.raw', '.') + if (copyin_res == 0): + SSH.copyout(self.UEIPAddress, self.UEUserName, self.UEPassword, './reconfig.raw', self.UESourceCodePath + '/cmake_targets/ran_build/build') + SSH.command('echo "ulimit -c unlimited && ./'+ RAN.Getair_interface() +'-uesoftmodem ' + self.Initialize_OAI_UE_args + '" > ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5) SSH.command('chmod 775 ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5) SSH.command('echo ' + self.UEPassword + ' | sudo -S rm -Rf ' + self.UESourceCodePath + '/cmake_targets/ue_' + self.testCase_id + '.log', '\$', 5) self.UELogFile = 'ue_' + self.testCase_id + '.log' diff --git a/ci-scripts/ran.py b/ci-scripts/ran.py index 5b5add0adb..598f3acfb9 100644 --- a/ci-scripts/ran.py +++ b/ci-scripts/ran.py @@ -546,6 +546,9 @@ class RANManagement(): # Launch eNB with the modified config file mySSH.command('source oaienv', '\$', 5) mySSH.command('cd cmake_targets', '\$', 5) + if self.air_interface == 'nr': + mySSH.command('if [ -e rbconfig.raw ]; then echo ' + lPassWord + ' | sudo -S rm rbconfig.raw; fi', '\$', 5) + mySSH.command('if [ -e rbconfig.raw ]; then echo ' + lPassWord + ' | sudo -S rm reconfig.raw; fi', '\$', 5) mySSH.command('echo "ulimit -c unlimited && ./ran_build/build/' + self.air_interface + '-softmodem -O ' + lSourcePath + '/' + ci_full_config_file + extra_options + '" > ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh', '\$', 5) mySSH.command('chmod 775 ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh', '\$', 5) mySSH.command('echo ' + lPassWord + ' | sudo -S rm -Rf enb_' + self.testCase_id + '.log', '\$', 5) diff --git a/ci-scripts/rrc-files/rbconfig.raw b/ci-scripts/rrc-files/rbconfig.raw deleted file mode 100644 index b03f18d1219201d789d1c70e1dced3e84a932990..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8 PcmWgP)DUkvz{3Cl2C4z8 diff --git a/ci-scripts/rrc-files/reconfig.raw b/ci-scripts/rrc-files/reconfig.raw deleted file mode 100644 index 97b41d9b6b0f0662487ca39848f85e9c1f7f8594..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 479 zcmZvXK}Zx)0EYiJZ+7;%j_XKUh%ENXDK?21#KRUHp2H>+lyvMMF*~+WLFgem)aA{% zl66`(S%faD6@&yyL3n&?+qPmv2;D@MEa;eCx>&Z|yM5p7`&hU&j$JjxrW$?heDiE# zrp~RxosN$_z1U>h&8!6U&Bpv>RXxWN$Vq{N}IvEipfZ!CNn4gOq0Wp{R}^Kfa2pe-7*}_6@%Q6AZjd^V@W_3Ne!j2yN1Yorg8CJ&MSq*vtF|z9Rf}kw9 zOx9^wP&>JogICi$s@0-2 zPoAI>dgr#}5FkI0;q=V(#{Xt(%cWbI-oqTJ2GB)JI7a5$XTEsf?jL>hsog_Mw{JWI@5GhC+Q#8h* qJUD$YnWS13stM;DOiNO|EftB=CGW!CtAm++osPf`dKT!uA^!qOo0Vh$ diff --git a/ci-scripts/runTestOnVM.sh b/ci-scripts/runTestOnVM.sh index 64af11c8ba..aa3f171770 100755 --- a/ci-scripts/runTestOnVM.sh +++ b/ci-scripts/runTestOnVM.sh @@ -1158,6 +1158,10 @@ function start_rf_sim_gnb { local LOC_CONF_FILE=$5 # 1 is with S1 and 0 without S1 aka noS1 local LOC_S1_CONFIGURATION=$6 + + if [ -e rbconfig.raw ]; then rm -f rbconfig.raw; fi + if [ -e reconfig.raw ]; then rm -f reconfig.raw; fi + echo "cd /home/ubuntu/tmp" > $1 echo "echo \"sudo apt-get --yes --quiet install daemon \"" >> $1 echo "sudo apt-get --yes install daemon >> /home/ubuntu/tmp/cmake_targets/log/daemon-install.txt 2>&1" >> $1 @@ -1171,6 +1175,7 @@ function start_rf_sim_gnb { echo "echo \"cd /home/ubuntu/tmp/cmake_targets/ran_build/build/\"" >> $1 echo "sudo chmod 777 /home/ubuntu/tmp/cmake_targets/ran_build/build/" >> $1 echo "cd /home/ubuntu/tmp/cmake_targets/ran_build/build/" >> $1 + echo "sudo rm -f r*config.raw" >> $1 if [ $LOC_S1_CONFIGURATION -eq 0 ] then echo "echo \"RFSIMULATOR=server ./nr-softmodem -O /home/ubuntu/tmp/ci-scripts/conf_files/ci-$LOC_CONF_FILE --log_config.global_log_options level,nocolor --parallel-config PARALLEL_SINGLE_THREAD --noS1 --nokrnmod 1 --rfsim --phy-test\" > ./my-nr-softmodem-run.sh " >> $1 @@ -1231,6 +1236,9 @@ function start_rf_sim_gnb { fi fi sleep 10 + # Copy the RAW files from the gNB run for the NR-UE + scp -o StrictHostKeyChecking=no ubuntu@$LOC_GNB_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/ran_build/build/rbconfig.raw . + scp -o StrictHostKeyChecking=no ubuntu@$LOC_GNB_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/ran_build/build/reconfig.raw . } function start_rf_sim_nr_ue { @@ -1241,14 +1249,21 @@ function start_rf_sim_nr_ue { local LOC_FREQUENCY=$6 # 1 is with S1 and 0 without S1 aka noS1 local LOC_S1_CONFIGURATION=$7 + + # Copy the RAW files from the gNB run + scp -o StrictHostKeyChecking=no rbconfig.raw ubuntu@$LOC_NR_UE_VM_IP_ADDR:/home/ubuntu/tmp + scp -o StrictHostKeyChecking=no reconfig.raw ubuntu@$LOC_NR_UE_VM_IP_ADDR:/home/ubuntu/tmp + echo "echo \"sudo apt-get --yes --quiet install daemon \"" > $1 echo "sudo apt-get --yes install daemon >> /home/ubuntu/tmp/cmake_targets/log/daemon-install.txt 2>&1" >> $1 echo "echo \"cd /home/ubuntu/tmp/cmake_targets/ran_build/build/\"" >> $1 echo "sudo chmod 777 /home/ubuntu/tmp/cmake_targets/ran_build/build/" >> $1 + echo "sudo cp /home/ubuntu/tmp/r*config.raw /home/ubuntu/tmp/cmake_targets/ran_build/build/" >> $1 + echo "sudo chmod 666 /home/ubuntu/tmp/cmake_targets/ran_build/build/r*config.raw" >> $1 echo "cd /home/ubuntu/tmp/cmake_targets/ran_build/build/" >> $1 if [ $LOC_S1_CONFIGURATION -eq 0 ] then - echo "echo \"RFSIMULATOR=${LOC_GNB_VM_IP_ADDR} ./nr-uesoftmodem --nokrnmod 1 --rfsim --phy-test --rrc_config_path /home/ubuntu/tmp/ci-scripts/rrc-files --log_config.global_log_options level,nocolor --noS1\" > ./my-nr-softmodem-run.sh " >> $1 + echo "echo \"RFSIMULATOR=${LOC_GNB_VM_IP_ADDR} ./nr-uesoftmodem --nokrnmod 1 --rfsim --phy-test --rrc_config_path /home/ubuntu/tmp/cmake_targets/ran_build/build/ --log_config.global_log_options level,nocolor --noS1\" > ./my-nr-softmodem-run.sh " >> $1 fi echo "chmod 775 ./my-nr-softmodem-run.sh" >> $1 echo "cat ./my-nr-softmodem-run.sh" >> $1 @@ -2028,7 +2043,7 @@ function run_test_on_vm { NR_STATUS=0 ######### start of loop - while [ $try_cnt -lt 5 ] + while [ $try_cnt -lt 1 ] do SYNC_STATUS=0 PING_STATUS=0 @@ -2050,6 +2065,8 @@ function run_test_on_vm { echo "Problem w/ gNB and NR-UE not syncing" terminate_enb_ue_basic_sim $NR_UE_VM_CMDS $NR_UE_VM_IP_ADDR 2 terminate_enb_ue_basic_sim $GNB_VM_CMDS $GNB_VM_IP_ADDR 1 + scp -o StrictHostKeyChecking=no ubuntu@$GNB_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/log/$CURRENT_GNB_LOG_FILE $ARCHIVES_LOC + scp -o StrictHostKeyChecking=no ubuntu@$NR_UE_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/log/$CURRENT_NR_UE_LOG_FILE $ARCHIVES_LOC SYNC_STATUS=-1 try_cnt=$[$try_cnt+1] continue @@ -2089,6 +2106,8 @@ function run_test_on_vm { echo "DL test not OK" terminate_enb_ue_basic_sim $NR_UE_VM_CMDS $NR_UE_VM_IP_ADDR 2 terminate_enb_ue_basic_sim $GNB_VM_CMDS $GNB_VM_IP_ADDR 1 + scp -o StrictHostKeyChecking=no ubuntu@$GNB_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/log/$CURRENT_GNB_LOG_FILE $ARCHIVES_LOC + scp -o StrictHostKeyChecking=no ubuntu@$NR_UE_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/log/$CURRENT_NR_UE_LOG_FILE $ARCHIVES_LOC try_cnt=$[$try_cnt+1] continue fi diff --git a/ci-scripts/xml_files/gnb_nr_ue_usrp_run.xml b/ci-scripts/xml_files/gnb_nr_ue_usrp_run.xml index f3e80c576a..c51093c178 100644 --- a/ci-scripts/xml_files/gnb_nr_ue_usrp_run.xml +++ b/ci-scripts/xml_files/gnb_nr_ue_usrp_run.xml @@ -52,7 +52,7 @@ Initialize_OAI_UE Initialize NR UE USRP - --phy-test --usrp-args "addr=192.168.30.2,second_addr=192.168.50.2,clock_source=external,time_source=external" --threadoffset 16 --rrc_config_path ci-scripts/rrc-files + --phy-test --usrp-args "addr=192.168.30.2,second_addr=192.168.50.2,clock_source=external,time_source=external" --threadoffset 16 --rrc_config_path . NR From 84dfeff40aa561aab3b0de3816910cbcd533c437 Mon Sep 17 00:00:00 2001 From: Thomas Schlichter Date: Fri, 5 Jun 2020 10:09:57 +0200 Subject: [PATCH 276/553] fix broken merge from develop in phy_procedures_gNB_common_RX() --- openair1/SCHED_NR/phy_procedures_nr_gNB.c | 83 +++++++---------------- 1 file changed, 25 insertions(+), 58 deletions(-) diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index 2685d0c37d..702571fef5 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -380,67 +380,34 @@ void phy_procedures_gNB_common_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) { - nfapi_nr_ul_tti_request_t *UL_tti_req = &gNB->UL_tti_req; - int num_pdus = UL_tti_req->n_pdus; + LOG_D(PHY,"phy_procedures_gNB_uespec_RX frame %d, slot %d\n",frame_rx,slot_rx); - nfapi_nr_uci_indication_t *uci_indication = &gNB->uci_indication; - uci_indication->sfn = frame_rx; - uci_indication->slot = slot_rx; - uci_indication->num_ucis = 0; + for (int ULSCH_id=0;ULSCH_idulsch[ULSCH_id][0]; + int harq_pid; + NR_UL_gNB_HARQ_t *ulsch_harq; + if ((ulsch) && + (ulsch->rnti > 0)) { + // for for an active HARQ process + for (harq_pid=0;harq_pidharq_processes[harq_pid]; + AssertFatal(ulsch_harq!=NULL,"harq_pid %d is not allocated\n",harq_pid); + if ((ulsch_harq->status == NR_ACTIVE) && + (ulsch_harq->frame == frame_rx) && + (ulsch_harq->slot == slot_rx) && + (ulsch_harq->handled == 0)){ - LOG_D(PHY,"phy_procedures_gNB_uespec_RX frame %d, slot %d, num_pdus %d\n",frame_rx,slot_rx,num_pdus); - - gNB->UL_INFO.rx_ind.number_of_pdus = 0; - gNB->UL_INFO.crc_ind.number_crcs = 0; - - for (int i = 0; i < num_pdus; i++) { - switch (UL_tti_req->pdus_list[i].pdu_type) { - case NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE: - { - LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE\n",frame_rx,slot_rx); - - nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[0].pusch_pdu; - nr_fill_ulsch(gNB,frame_rx,slot_rx,pusch_pdu); - - uint8_t ULSCH_id = find_nr_ulsch(pusch_pdu->rnti,gNB,SEARCH_EXIST); - uint8_t harq_pid = pusch_pdu->pusch_data.harq_process_id; - uint8_t symbol_start = pusch_pdu->start_symbol_index; - uint8_t symbol_end = symbol_start + pusch_pdu->nr_of_symbols; - - for(uint8_t symbol = symbol_start; symbol < symbol_end; symbol++) { - nr_rx_pusch(gNB, ULSCH_id, frame_rx, slot_rx, symbol, harq_pid); - } - //LOG_M("rxdataF_comp.m","rxF_comp",gNB->pusch_vars[0]->rxdataF_comp[0],6900,1,1); - //LOG_M("rxdataF_ext.m","rxF_ext",gNB->pusch_vars[0]->rxdataF_ext[0],6900,1,1); - nr_ulsch_procedures(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); - } - break; - case NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE: - { - LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE\n",frame_rx,slot_rx); - - nfapi_nr_pucch_pdu_t *pucch_pdu = &UL_tti_req->pdus_list[i].pucch_pdu; - switch (pucch_pdu->format_type) { - case 0: - uci_indication->uci_list[uci_indication->num_ucis].pdu_type = NFAPI_NR_UCI_FORMAT_0_1_PDU_TYPE; - uci_indication->uci_list[uci_indication->num_ucis].pdu_size = sizeof(nfapi_nr_uci_pucch_pdu_format_0_1_t); - nfapi_nr_uci_pucch_pdu_format_0_1_t *uci_pdu_format0 = &uci_indication->uci_list[uci_indication->num_ucis].pucch_pdu_format_0_1; - - nr_decode_pucch0(gNB, - slot_rx, - uci_pdu_format0, - pucch_pdu); - - uci_indication->num_ucis += 1; - break; - case 1: - break; - case 2: - break; - default: - AssertFatal(1==0,"Only PUCCH format 0,1 and 2 are currently supported\n"); - } + uint8_t symbol_start = ulsch_harq->ulsch_pdu.start_symbol_index; + uint8_t symbol_end = symbol_start + ulsch_harq->ulsch_pdu.nr_of_symbols; + for(uint8_t symbol = symbol_start; symbol < symbol_end; symbol++) { + nr_rx_pusch(gNB, ULSCH_id, frame_rx, slot_rx, symbol, harq_pid); + } + //LOG_M("rxdataF_comp.m","rxF_comp",gNB->pusch_vars[0]->rxdataF_comp[0],6900,1,1); + //LOG_M("rxdataF_ext.m","rxF_ext",gNB->pusch_vars[0]->rxdataF_ext[0],6900,1,1); + nr_ulsch_procedures(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); + break; + } } } } From 91fd14bf995e194054f7b8e3f0ebbab7a9a264e5 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Fri, 5 Jun 2020 17:35:25 +0200 Subject: [PATCH 277/553] UE harq bugfixes --- executables/nr-ue.c | 9 +-- .../PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c | 3 + openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 6 +- openair1/SCHED_NR_UE/pucch_uci_ue_nr.c | 63 ++++++++++--------- 4 files changed, 45 insertions(+), 36 deletions(-) diff --git a/executables/nr-ue.c b/executables/nr-ue.c index 30ce657edb..db0af31a65 100644 --- a/executables/nr-ue.c +++ b/executables/nr-ue.c @@ -374,7 +374,7 @@ void processSlotTX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { nr_scheduled_response_t scheduled_response; // program PUSCH. this should actually be done by the MAC upon reception of an UL DCI - if (proc->nr_tti_tx == 8 || proc->nr_tti_tx == 19 || UE->frame_parms.frame_type == FDD){ + if (proc->nr_tti_tx == 8 || proc->nr_tti_tx == 7 || UE->frame_parms.frame_type == FDD){ mod_id = UE->Mod_id; @@ -420,7 +420,7 @@ void processSlotTX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { nr_ue_scheduled_response(&scheduled_response); if (UE->mode != loop_through_memory) { - uint8_t thread_id = PHY_vars_UE_g[mod_id][0]->current_thread_id[proc->nr_tti_tx]; + uint8_t thread_id = PHY_vars_UE_g[mod_id][0]->current_thread_id[proc->nr_tti_rx]; phy_procedures_nrUE_TX(UE,proc,0,thread_id); } } @@ -860,8 +860,9 @@ void *UE_thread(void *arg) { usleep(200); } - if ( decoded_frame_rx != curMsg->proc.frame_rx && - ((decoded_frame_rx+1) % MAX_FRAME_NUMBER) != curMsg->proc.frame_rx ) + if ( (decoded_frame_rx != curMsg->proc.frame_rx) && + (((decoded_frame_rx+1) % MAX_FRAME_NUMBER) != curMsg->proc.frame_rx) && + (((decoded_frame_rx+2) % MAX_FRAME_NUMBER) != curMsg->proc.frame_rx)) LOG_D(PHY,"Decoded frame index (%d) is not compatible with current context (%d), UE should go back to synch mode\n", decoded_frame_rx, curMsg->proc.frame_rx ); diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c index 0dffb66c15..5c2221805f 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c @@ -32,6 +32,7 @@ #include "common/utils/LOG/vcd_signal_dumper.h" #include "PHY/defs_nr_UE.h" +#include "SCHED_NR_UE/harq_nr.h" #include "PHY/phy_extern_nr_ue.h" #include "PHY/CODING/coding_extern.h" #include "PHY/CODING/coding_defs.h" @@ -132,6 +133,7 @@ NR_UE_DLSCH_t *new_nr_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint memset(dlsch,0,sizeof(NR_UE_DLSCH_t)); dlsch->Kmimo = Kmimo; dlsch->Mdlharq = Mdlharq; + dlsch->number_harq_processes_for_pdsch = Mdlharq; dlsch->Nsoft = Nsoft; dlsch->Mlimit = 4; dlsch->max_ldpc_iterations = max_ldpc_iterations; @@ -142,6 +144,7 @@ NR_UE_DLSCH_t *new_nr_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint if (dlsch->harq_processes[i]) { memset(dlsch->harq_processes[i],0,sizeof(NR_DL_UE_HARQ_t)); + init_downlink_harq_status(dlsch->harq_processes[i]); dlsch->harq_processes[i]->first_tx=1; dlsch->harq_processes[i]->b = (uint8_t*)malloc16(dlsch_bytes); diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 1a562c04c8..d05dde4667 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -44,6 +44,7 @@ #include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h" //#include "PHY/extern.h" #include "SCHED_NR_UE/defs.h" +#include "SCHED_NR_UE/pucch_uci_ue_nr.h" #include "SCHED_NR/extern.h" #include "SCHED_NR_UE/phy_sch_processing_time.h" //#include @@ -4032,8 +4033,8 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, NR_UE_PDCCH *pdcch_vars = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][0]; NR_UE_DLSCH_t **dlsch = ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id]; fapi_nr_config_request_t *cfg = &ue->nrUE_config; - uint8_t harq_pid = ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->current_harq_pid; - NR_DL_UE_HARQ_t *dlsch0_harq = dlsch[0]->harq_processes[harq_pid]; + uint8_t *harq_pid = &ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->current_harq_pid; + NR_DL_UE_HARQ_t *dlsch0_harq = dlsch[0]->harq_processes[*harq_pid]; uint16_t nb_symb_sch = dlsch0_harq->nb_symbols; uint16_t start_symb_sch = dlsch0_harq->start_symbol; uint8_t nb_symb_pdcch = pdcch_vars->nb_search_space > 0 ? pdcch_vars->pdcch_config[0].coreset.duration : 0; @@ -4144,6 +4145,7 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, if (dci_cnt > 0){ LOG_D(PHY," ------ --> PDSCH ChannelComp/LLR Frame.slot %d.%d ------ \n", frame_rx%1024, nr_tti_rx); //to update from pdsch config + dlsch0_harq = dlsch[0]->harq_processes[*harq_pid]; start_symb_sch = dlsch0_harq->start_symbol; int symb_dmrs=-1; for (int i=0;i<4;i++) if (((1<dlDmrsSymbPos) > 0) {symb_dmrs=i;break;} diff --git a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c index a2452248b8..de6605b08d 100644 --- a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c +++ b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c @@ -718,41 +718,44 @@ uint8_t get_downlink_ack(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_t for (int dl_harq_pid = 0; dl_harq_pid < number_pid_dl; dl_harq_pid++) { - harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][code_word]->harq_processes[dl_harq_pid]->harq_ack; + for (int thread_idx = 0; thread_idx < RX_NB_TH; thread_idx++) { - /* check if current tx slot should transmit downlink acknowlegment */ - if (harq_status->slot_for_feedback_ack == proc->nr_tti_tx) { + harq_status = &ue->dlsch[thread_idx][gNB_id][code_word]->harq_processes[dl_harq_pid]->harq_ack; - if (harq_status->ack == DL_ACKNACK_NO_SET) { - LOG_E(PHY,"PUCCH Downlink acknowledgment has not been set : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); - return (0); - } - else if (harq_status->vDAI_DL == DL_DAI_NO_SET) { - LOG_E(PHY,"PUCCH Downlink DAI has not been set : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); - return (0); - } - else if (harq_status->vDAI_DL > NR_DL_MAX_DAI) { - LOG_E(PHY,"PUCCH Downlink DAI has an invalid value : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); - return (0); - } - else if (harq_status->send_harq_status == 0) { - LOG_E(PHY,"PUCCH Downlink ack can not be transmitted : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); - return(0); - } - else { + /* check if current tx slot should transmit downlink acknowlegment */ + if (harq_status->slot_for_feedback_ack == proc->nr_tti_tx) { - dai_current = harq_status->vDAI_DL; - - if (dai_current == 0) { - LOG_E(PHY,"PUCCH Downlink dai is invalid : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); - return(0); - } else if (dai_current > dai_max) { - dai_max = dai_current; + if (harq_status->ack == DL_ACKNACK_NO_SET) { + LOG_E(PHY,"PUCCH Downlink acknowledgment has not been set : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); + return (0); } + else if (harq_status->vDAI_DL == DL_DAI_NO_SET) { + LOG_E(PHY,"PUCCH Downlink DAI has not been set : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); + return (0); + } + else if (harq_status->vDAI_DL > NR_DL_MAX_DAI) { + LOG_E(PHY,"PUCCH Downlink DAI has an invalid value : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); + return (0); + } + else if (harq_status->send_harq_status == 0) { + LOG_E(PHY,"PUCCH Downlink ack can not be transmitted : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); + return(0); + } + else { - number_harq_feedback++; - ack_data[code_word][dai_current - 1] = harq_status->ack; - dai[code_word][dai_current - 1] = dai_current; + dai_current = harq_status->vDAI_DL; + + if (dai_current == 0) { + LOG_E(PHY,"PUCCH Downlink dai is invalid : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); + return(0); + } else if (dai_current > dai_max) { + dai_max = dai_current; + } + + number_harq_feedback++; + ack_data[code_word][dai_current - 1] = harq_status->ack; + dai[code_word][dai_current - 1] = dai_current; + } } } if (do_reset == TRUE) { From 06ee95f40e546c6e3587f0b4d7cfa3be5ef8f418 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Fri, 5 Jun 2020 17:35:46 +0200 Subject: [PATCH 278/553] UE sync fix --- openair1/PHY/MODULATION/slot_fep_nr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openair1/PHY/MODULATION/slot_fep_nr.c b/openair1/PHY/MODULATION/slot_fep_nr.c index 7ff735cb71..0a3047a56d 100644 --- a/openair1/PHY/MODULATION/slot_fep_nr.c +++ b/openair1/PHY/MODULATION/slot_fep_nr.c @@ -338,7 +338,7 @@ int nr_slot_fep_init_sync(PHY_VARS_NR_UE *ue, #endif - dft(dftsize,(int16_t *) &common_vars->rxdata[aa][(rx_offset) % frame_length_samples], + dft(dftsize,(int16_t *) &common_vars->rxdata[aa][rx_offset], (int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1); #if UE_TIMING_TRACE stop_meas(&ue->rx_dft_stats); @@ -362,7 +362,7 @@ int nr_slot_fep_init_sync(PHY_VARS_NR_UE *ue, dft(dftsize,(int16_t *)tmp_dft_in, (int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1); } else { // use dft input from RX buffer directly - dft(dftsize,(int16_t *) &common_vars->rxdata[aa][(rx_offset) % frame_length_samples], + dft(dftsize,(int16_t *) &common_vars->rxdata[aa][rx_offset], (int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1); } #if UE_TIMING_TRACE From 0124e5378c910ea5fe0f745d59b7d43214c330e7 Mon Sep 17 00:00:00 2001 From: Florian Kaltenberger Date: Sat, 6 Jun 2020 22:55:13 +0200 Subject: [PATCH 279/553] adding possibility to read rx signal from file --- openair1/SIMULATION/NR_PHY/prachsim.c | 31 ++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/openair1/SIMULATION/NR_PHY/prachsim.c b/openair1/SIMULATION/NR_PHY/prachsim.c index 797118b382..c420ca41fa 100644 --- a/openair1/SIMULATION/NR_PHY/prachsim.c +++ b/openair1/SIMULATION/NR_PHY/prachsim.c @@ -99,7 +99,9 @@ int main(int argc, char **argv){ // double prach_sinr; // uint32_t nsymb; // uint16_t preamble_max, preamble_energy_max; - + FILE *input_fd=NULL; + char* input_file=NULL; + int n_bytes=0; NR_DL_FRAME_PARMS *frame_parms; NR_PRACH_RESOURCES_t prach_resources; @@ -292,6 +294,14 @@ int main(int argc, char **argv){ break; case 'F': + input_fd = fopen(optarg,"r"); + input_file = optarg; + + if (input_fd==NULL) { + printf("Problem with filename %s\n",optarg); + exit(-1); + } + break; default: @@ -647,7 +657,7 @@ int main(int argc, char **argv){ for (trial=0; trialcommon.rxdata[aa][rx_prach_start])[2*i+1] = (short) (.167*(r_im[aa][i] + (iqim*r_re[aa][i]) + sqrt(sigma2/2)*gaussdouble(0.0,1.0))); } } + } else { + n_bytes = fread(&ru->common.rxdata[0][rx_prach_start+frame_parms->samples_per_subframe/2],sizeof(int32_t),frame_parms->samples_per_subframe/2,input_fd); + printf("fread %d bytes from file %s\n",n_bytes,input_file); + if (n_bytes!=frame_parms->samples_per_subframe/2) { + printf("expected %d bytes\n",frame_parms->samples_per_subframe/2); + exit(-1); + } + } + rx_nr_prach_ru(ru, prach_format, numRA, prachStartSymbol, frame, slot); @@ -695,7 +714,7 @@ int main(int argc, char **argv){ LOG_M("prach0.m","prach0", &txdata[0][prach_start], frame_parms->samples_per_subframe, 1, 1); LOG_M("prachF0.m","prachF0", &gNB->prach_vars.prachF[0], N_ZC, 1, 1); LOG_M("rxsig0.m","rxs0", &gNB->common_vars.rxdata[0][rx_prach_start], frame_parms->samples_per_subframe, 1, 1); - //LOG_M("ru_rxsig0.m","rxs0", &ru->common.rxdata[0][rx_prach_start], frame_parms->samples_per_subframe, 1, 1); + LOG_M("ru_rxsig0.m","rxs0", &ru->common.rxdata[0][rx_prach_start], frame_parms->samples_per_subframe, 1, 1); LOG_M("rxsigF0.m","rxsF0", gNB->prach_vars.rxsigF[0], N_ZC, 1, 1); LOG_M("prach_preamble.m","prachp", &gNB->X_u[0], N_ZC, 1, 1); LOG_M("ue_prach_preamble.m","prachp", &UE->X_u[0], N_ZC, 1, 1); @@ -703,6 +722,8 @@ int main(int argc, char **argv){ } } printf("SNR %f dB, UE Speed %f km/h: errors %d/%d (delay %f)\n", SNR, ue_speed, prach_errors, n_frames, delay_avg/(double)(n_frames-prach_errors)); + if (input_fd) + break; if (prach_errors) break; } // UE Speed loop @@ -710,6 +731,8 @@ int main(int argc, char **argv){ printf("PRACH test OK\n"); break; } + if (input_fd) + break; } //SNR loop for (i=0; i<2; i++) { @@ -724,5 +747,7 @@ int main(int argc, char **argv){ free(r_re); free(r_im); + if (input_fd) fclose(input_fd); + return(0); } From 96dc4a888db2cdebc3ef421aaf863e2516230476 Mon Sep 17 00:00:00 2001 From: Thomas Schlichter Date: Tue, 9 Jun 2020 12:38:54 +0200 Subject: [PATCH 280/553] fix broken merge from develop in ulsim --- openair1/SIMULATION/NR_PHY/ulsim.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/openair1/SIMULATION/NR_PHY/ulsim.c b/openair1/SIMULATION/NR_PHY/ulsim.c index 959f73be38..9b9001d491 100644 --- a/openair1/SIMULATION/NR_PHY/ulsim.c +++ b/openair1/SIMULATION/NR_PHY/ulsim.c @@ -611,6 +611,9 @@ int main(int argc, char **argv) pusch_pdu->pusch_ptrs.ptrs_ports_list = (nfapi_nr_ptrs_ports_t *) malloc(2*sizeof(nfapi_nr_ptrs_ports_t)); pusch_pdu->pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset = 0; + // prepare ULSCH/PUSCH reception + nr_schedule_response(Sched_INFO); + // --------- setting parameters for UE -------- scheduled_response.module_id = 0; From 36f5e80ea38e9669a6249d33921e2f1e6e9317af Mon Sep 17 00:00:00 2001 From: Thomas Schlichter Date: Wed, 13 May 2020 14:27:30 +0200 Subject: [PATCH 281/553] cleaning up the UE MAC/PHY interface --- executables/nr-ue.c | 122 ++++--------------- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 98 +++++++++++++-- openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c | 2 + 3 files changed, 113 insertions(+), 109 deletions(-) diff --git a/executables/nr-ue.c b/executables/nr-ue.c index ced533b029..63c3172917 100644 --- a/executables/nr-ue.c +++ b/executables/nr-ue.c @@ -366,88 +366,31 @@ static void UE_synch(void *arg) { void processSlotTX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { - uint32_t rb_size, rb_start; - uint16_t rnti, l_prime_mask, n_rb0, n_rb1, pdu_bit_map; - uint8_t nr_of_symbols, start_symbol_index, mcs_index, mcs_table, nrOfLayers, harq_process_id, rv_index, dmrs_config_type; - uint8_t ptrs_mcs1, ptrs_mcs2, ptrs_mcs3, ptrs_time_density, ptrs_freq_density; - module_id_t mod_id; - nr_dcireq_t dcireq; - nr_scheduled_response_t scheduled_response; - fapi_nr_config_request_t *cfg = &UE->nrUE_config; int tx_slot_type = nr_ue_slot_select(cfg, proc->frame_tx, proc->nr_tti_tx); + uint8_t gNB_id = 0; - // program PUSCH. this should actually be done by the MAC upon reception of an UL DCI if (tx_slot_type == NR_UPLINK_SLOT || tx_slot_type == NR_MIXED_SLOT){ - mod_id = UE->Mod_id; + // trigger L2 to run ue_scheduler thru IF module + // [TODO] mapping right after NR initial sync + if(UE->if_inst != NULL && UE->if_inst->ul_indication != NULL) { + nr_uplink_indication_t ul_indication; + memset((void*)&ul_indication, 0, sizeof(ul_indication)); - dcireq.module_id = mod_id; - dcireq.gNB_index = 0; - dcireq.cc_id = 0; - dcireq.frame = proc->frame_rx; - dcireq.slot = proc->nr_tti_rx; + ul_indication.module_id = UE->Mod_id; + ul_indication.gNB_index = gNB_id; + ul_indication.cc_id = UE->CC_id; + ul_indication.frame_rx = proc->frame_rx; + ul_indication.slot_rx = proc->nr_tti_rx; + ul_indication.frame_tx = proc->frame_tx; + ul_indication.slot_tx = proc->nr_tti_tx; - scheduled_response.dl_config = NULL; - scheduled_response.ul_config = &dcireq.ul_config_req; - scheduled_response.tx_request = NULL; - scheduled_response.module_id = mod_id; - scheduled_response.CC_id = 0; - scheduled_response.frame = proc->frame_rx; - scheduled_response.slot = proc->nr_tti_rx; - //--------------------------Temporary configuration-----------------------------// - rnti = 0x1234; - rb_size = 50; - rb_start = 0; - nr_of_symbols = 12; - start_symbol_index = 2; - nrOfLayers = 1; - mcs_index = 9; - mcs_table = 0; - harq_process_id = 0; - rv_index = 0; - l_prime_mask = get_l_prime(nr_of_symbols, typeB, pusch_dmrs_pos0, pusch_len1); - dmrs_config_type = 0; - ptrs_mcs1 = 2; - ptrs_mcs2 = 4; - ptrs_mcs3 = 10; - n_rb0 = 25; - n_rb1 = 75; - pdu_bit_map = PUSCH_PDU_BITMAP_PUSCH_DATA; - ptrs_time_density = get_L_ptrs(ptrs_mcs1, ptrs_mcs2, ptrs_mcs3, mcs_index, mcs_table); - ptrs_freq_density = get_K_ptrs(n_rb0, n_rb1, rb_size); - //------------------------------------------------------------------------------// - - scheduled_response.ul_config->slot = proc->nr_tti_tx; - scheduled_response.ul_config->number_pdus = 1; - scheduled_response.ul_config->ul_config_list[0].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.rnti = rnti; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.rb_size = rb_size; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.rb_start = rb_start; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.nr_of_symbols = nr_of_symbols; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.start_symbol_index = start_symbol_index; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.ul_dmrs_symb_pos = l_prime_mask << start_symbol_index; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.dmrs_config_type = dmrs_config_type; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.mcs_index = mcs_index; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.mcs_table = mcs_table; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_data.new_data_indicator = 0; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_data.rv_index = rv_index; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.nrOfLayers = nrOfLayers; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_data.harq_process_id = harq_process_id; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pdu_bit_map = pdu_bit_map; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_time_density = ptrs_time_density; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_freq_density = ptrs_freq_density; - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_ports_list = (nfapi_nr_ue_ptrs_ports_t *) malloc(2*sizeof(nfapi_nr_ue_ptrs_ports_t)); - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset = 0; - - if (1 << ptrs_time_density >= nr_of_symbols) { - scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pdu_bit_map &= ~PUSCH_PDU_BITMAP_PUSCH_PTRS; // disable PUSCH PTRS + UE->if_inst->ul_indication(&ul_indication); } - nr_ue_scheduled_response(&scheduled_response); - if (UE->mode != loop_through_memory) { - uint8_t thread_id = PHY_vars_UE_g[mod_id][0]->current_thread_id[proc->nr_tti_rx]; + uint8_t thread_id = PHY_vars_UE_g[UE->Mod_id][0]->current_thread_id[proc->nr_tti_rx]; phy_procedures_nrUE_TX(UE,proc,0,thread_id); } } @@ -459,20 +402,20 @@ void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { int rx_slot_type = nr_ue_slot_select(cfg, proc->frame_rx, proc->nr_tti_rx); uint8_t gNB_id = 0; - nr_downlink_indication_t dl_indication; - memset((void*)&dl_indication, 0, sizeof(dl_indication)); - if (rx_slot_type == NR_DOWNLINK_SLOT || rx_slot_type == NR_MIXED_SLOT){ if(UE->if_inst != NULL && UE->if_inst->dl_indication != NULL) { + nr_downlink_indication_t dl_indication; + memset((void*)&dl_indication, 0, sizeof(dl_indication)); + dl_indication.module_id = UE->Mod_id; dl_indication.gNB_index = gNB_id; dl_indication.cc_id = UE->CC_id; dl_indication.frame = proc->frame_rx; dl_indication.slot = proc->nr_tti_rx; - } - nr_ue_scheduler(&dl_indication, NULL); + UE->if_inst->dl_indication(&dl_indication, NULL); + } // Process Rx data for one sub-frame #ifdef UE_SLOT_PARALLELISATION @@ -513,11 +456,7 @@ void UE_processing(void *arg) { UE_nr_rxtx_proc_t *proc = &rxtxD->proc; PHY_VARS_NR_UE *UE = rxtxD->UE; - uint8_t gNB_id = 0, CC_id = 0; - module_id_t mod_id = 0; - - nr_uplink_indication_t ul_indication; - memset((void*)&ul_indication, 0, sizeof(ul_indication)); + uint8_t gNB_id = 0; // params for UL time alignment procedure NR_UL_TIME_ALIGNMENT_t *ul_time_alignment = &UE->ul_time_alignment[gNB_id]; @@ -543,24 +482,7 @@ void UE_processing(void *arg) { } processSlotRX(UE, proc); - - if (UE->mac_enabled == 1) { - // trigger L2 to run ue_scheduler thru IF module - // [TODO] mapping right after NR initial sync - if(UE->if_inst != NULL && UE->if_inst->ul_indication != NULL) { - ul_indication.module_id = mod_id; - ul_indication.gNB_index = gNB_id; - ul_indication.cc_id = CC_id; - ul_indication.frame_rx = proc->frame_rx; - ul_indication.slot_rx = proc->nr_tti_rx; - ul_indication.frame_tx = proc->frame_tx; - ul_indication.slot_tx = proc->nr_tti_tx; - UE->if_inst->ul_indication(&ul_indication); - } - } - processSlotTX(UE, proc); - } void dummyWrite(PHY_VARS_NR_UE *UE,openair0_timestamp timestamp, int writeBlockSize) { @@ -763,7 +685,7 @@ void *UE_thread(void *arg) { curMsg->UE=UE; // update thread index for received subframe curMsg->UE->current_thread_id[slot_nr] = thread_idx; - curMsg->proc.CC_id = 0; + curMsg->proc.CC_id = UE->CC_id; curMsg->proc.nr_tti_rx= slot_nr; curMsg->proc.subframe_rx=slot_nr/(nb_slot_frame/10); curMsg->proc.nr_tti_tx = (absolute_slot + DURATION_RX_TO_TX) % nb_slot_frame; diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index ac10a62396..2ccd1f369b 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -658,14 +658,16 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in if (dl_info){ - module_id_t mod_id = dl_info->module_id; + module_id_t mod_id = dl_info->module_id; + uint32_t gNB_index = dl_info->gNB_index; + int cc_id = dl_info->cc_id; + frame_t rx_frame = dl_info->frame; + slot_t rx_slot = dl_info->slot; NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); - int cc_id = dl_info->cc_id; + fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request; nr_scheduled_response_t scheduled_response; nr_dcireq_t dcireq; - frame_t rx_frame = dl_info->frame; - slot_t rx_slot = dl_info->slot; // check type0 from 38.213 13 if we have no CellGroupConfig // TODO: implementation to be completed @@ -720,8 +722,8 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in } else { // we have an scd dcireq.module_id = mod_id; - dcireq.gNB_index = 0; - dcireq.cc_id = 0; + dcireq.gNB_index = gNB_index; + dcireq.cc_id = cc_id; dcireq.frame = rx_frame; dcireq.slot = rx_slot; nr_ue_dcireq(&dcireq); //to be replaced with function pointer later @@ -735,7 +737,9 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in scheduled_response.frame = rx_frame; scheduled_response.slot = rx_slot; - nr_ue_scheduled_response(&scheduled_response); + if(mac->if_module != NULL && mac->if_module->scheduled_response != NULL){ + mac->if_module->scheduled_response(&scheduled_response); + } /* if(search_space_mask & type0a_pdcch){ @@ -752,12 +756,88 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in */ } } else if (ul_info) { - module_id_t mod_id = ul_info->module_id; + module_id_t mod_id = ul_info->module_id; + uint32_t gNB_index = ul_info->gNB_index; + int cc_id = ul_info->cc_id; + frame_t rx_frame = ul_info->frame_rx; + slot_t rx_slot = ul_info->slot_rx; NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); + + // program PUSCH. this should actually be done upon reception of an UL DCI + nr_dcireq_t dcireq; + nr_scheduled_response_t scheduled_response; + + //--------------------------Temporary configuration-----------------------------// + uint16_t rnti = 0x1234; + uint32_t rb_size = 50; + uint32_t rb_start = 0; + uint8_t nr_of_symbols = 12; + uint8_t start_symbol_index = 2; + uint8_t nrOfLayers = 1; + uint8_t mcs_index = 9; + uint8_t mcs_table = 0; + uint8_t harq_process_id = 0; + uint8_t rv_index = 0; + uint16_t l_prime_mask = get_l_prime(nr_of_symbols, typeB, pusch_dmrs_pos0, pusch_len1); + uint8_t dmrs_config_type = 0; + uint8_t ptrs_mcs1 = 2; + uint8_t ptrs_mcs2 = 4; + uint8_t ptrs_mcs3 = 10; + uint16_t n_rb0 = 25; + uint16_t n_rb1 = 75; + uint16_t pdu_bit_map = PUSCH_PDU_BITMAP_PUSCH_DATA; + uint8_t ptrs_time_density = get_L_ptrs(ptrs_mcs1, ptrs_mcs2, ptrs_mcs3, mcs_index, mcs_table); + uint8_t ptrs_freq_density = get_K_ptrs(n_rb0, n_rb1, rb_size); + //------------------------------------------------------------------------------// + + dcireq.module_id = mod_id; + dcireq.gNB_index = gNB_index; + dcireq.cc_id = cc_id; + dcireq.frame = rx_frame; + dcireq.slot = rx_slot; + + scheduled_response.dl_config = NULL; + scheduled_response.ul_config = &dcireq.ul_config_req; + scheduled_response.tx_request = NULL; + scheduled_response.module_id = mod_id; + scheduled_response.CC_id = cc_id; + scheduled_response.frame = rx_frame; + scheduled_response.slot = rx_slot; + + scheduled_response.ul_config->slot = ul_info->slot_tx; + scheduled_response.ul_config->number_pdus = 1; + scheduled_response.ul_config->ul_config_list[0].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.rnti = rnti; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.rb_size = rb_size; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.rb_start = rb_start; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.nr_of_symbols = nr_of_symbols; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.start_symbol_index = start_symbol_index; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.ul_dmrs_symb_pos = l_prime_mask << start_symbol_index; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.dmrs_config_type = dmrs_config_type; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.mcs_index = mcs_index; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.mcs_table = mcs_table; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_data.new_data_indicator = 0; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_data.rv_index = rv_index; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.nrOfLayers = nrOfLayers; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_data.harq_process_id = harq_process_id; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pdu_bit_map = pdu_bit_map; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_time_density = ptrs_time_density; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_freq_density = ptrs_freq_density; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_ports_list = (nfapi_nr_ue_ptrs_ports_t *) malloc(2*sizeof(nfapi_nr_ue_ptrs_ports_t)); + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset = 0; + + if (1 << ptrs_time_density >= nr_of_symbols) { + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pdu_bit_map &= ~PUSCH_PDU_BITMAP_PUSCH_PTRS; // disable PUSCH PTRS + } + + if(mac->if_module != NULL && mac->if_module->scheduled_response != NULL){ + mac->if_module->scheduled_response(&scheduled_response); + } + // TODO: expand // Note: Contention resolution is currently not active if (mac->RA_contention_resolution_timer_active == 1) - ue_contention_resolution(mod_id, ul_info->gNB_index, ul_info->cc_id, ul_info->frame_tx); + ue_contention_resolution(mod_id, gNB_index, cc_id, ul_info->frame_tx); } return UE_CONNECTION_OK; diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c index d123c74e0b..ad4f0d8d30 100644 --- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c @@ -153,6 +153,8 @@ int nr_ue_dl_indication(nr_downlink_indication_t *dl_info, NR_UL_TIME_ALIGNMENT_ fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request; fapi_nr_ul_config_request_t *ul_config = &mac->ul_config_request; + nr_ue_scheduler(dl_info, NULL); + dl_config->number_pdus = 0; ul_config->number_pdus = 0; //hook up pointers From f4d47b1ea7356f82c1a5bfae2a8e82db7f09432c Mon Sep 17 00:00:00 2001 From: cig Date: Wed, 20 May 2020 14:50:53 +0200 Subject: [PATCH 282/553] Checking in dl_indication if scheduling is needed or any DL PDU was received: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - scheduling is needed only when whe it doesn´t fall in dci_ind or rx_ind cases - cleaned up some old commented out code --- openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c | 209 +++++++++----------- 1 file changed, 88 insertions(+), 121 deletions(-) diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c index ad4f0d8d30..6773c3ee1c 100644 --- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c @@ -145,7 +145,7 @@ int nr_ue_ul_indication(nr_uplink_indication_t *ul_info){ } int nr_ue_dl_indication(nr_downlink_indication_t *dl_info, NR_UL_TIME_ALIGNMENT_t *ul_time_alignment){ - + int32_t i; uint32_t ret_mask = 0x0; module_id_t module_id = dl_info->module_id; @@ -153,132 +153,99 @@ int nr_ue_dl_indication(nr_downlink_indication_t *dl_info, NR_UL_TIME_ALIGNMENT_ fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request; fapi_nr_ul_config_request_t *ul_config = &mac->ul_config_request; - nr_ue_scheduler(dl_info, NULL); + if (!dl_info->dci_ind && !dl_info->rx_ind) { + // UL indication to schedule reception DCI reception + nr_ue_scheduler(dl_info, NULL); + } else { + // UL indication after reception of DCI or DL PDU + dl_config->number_pdus = 0; + ul_config->number_pdus = 0; + //hook up pointers + mac->scheduled_response.dl_config = dl_config; + mac->scheduled_response.ul_config = ul_config; + mac->scheduled_response.tx_request = &mac->tx_request; + mac->scheduled_response.module_id = dl_info->module_id; + mac->scheduled_response.CC_id = dl_info->cc_id; + mac->scheduled_response.frame = dl_info->frame; + mac->scheduled_response.slot = dl_info->slot; - dl_config->number_pdus = 0; - ul_config->number_pdus = 0; - //hook up pointers - mac->scheduled_response.dl_config = dl_config; - mac->scheduled_response.ul_config = ul_config; - mac->scheduled_response.tx_request = &mac->tx_request; - mac->scheduled_response.module_id = dl_info->module_id; - mac->scheduled_response.CC_id = dl_info->cc_id; - mac->scheduled_response.frame = dl_info->frame; - mac->scheduled_response.slot = dl_info->slot; + if(dl_info->dci_ind != NULL){ + LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][DCI_IND]\n"); + for(i=0; idci_ind->number_of_dcis; ++i){ + LOG_D(MAC,">>>NR_IF_Module i=%d, dl_info->dci_ind->number_of_dcis=%d\n",i,dl_info->dci_ind->number_of_dcis); - if(dl_info->dci_ind != NULL){ - LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][DCI_IND]\n"); - for(i=0; idci_ind->number_of_dcis; ++i){ - LOG_D(MAC,">>>NR_IF_Module i=%d, dl_info->dci_ind->number_of_dcis=%d\n",i,dl_info->dci_ind->number_of_dcis); - // fapi_nr_dci_pdu_rel15_t *dci = &dl_info->dci_ind->dci_list[i].dci; + ret_mask |= (handle_dci(dl_info->module_id, + dl_info->cc_id, + dl_info->gNB_index, + dl_info->dci_ind->dci_list+i)<< FAPI_NR_DCI_IND); - ret_mask |= (handle_dci(dl_info->module_id, - dl_info->cc_id, - dl_info->gNB_index, - dl_info->dci_ind->dci_list+i)<< FAPI_NR_DCI_IND); - - AssertFatal( nr_ue_if_module_inst[module_id] != NULL, "IF module is void!\n" ); - nr_ue_if_module_inst[module_id]->scheduled_response(&mac->scheduled_response); - - - /*switch((dl_info->dci_ind->dci_list+i)->dci_type){ - case FAPI_NR_DCI_TYPE_0_0: - case FAPI_NR_DCI_TYPE_0_1: - case FAPI_NR_DCI_TYPE_1_1: - case FAPI_NR_DCI_TYPE_2_0: - case FAPI_NR_DCI_TYPE_2_1: - case FAPI_NR_DCI_TYPE_2_2: - case FAPI_NR_DCI_TYPE_2_3: - AssertFatal(1==0, "Not yet support at this moment!\n"); - break; - - case FAPI_NR_DCI_TYPE_1_0: - - dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH; - - // mapping into DL_CONFIG_REQ for DL-SCH - fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu = &dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.dlsch_config_rel15; - - dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.rnti = 0x0000; // TX RNTI: UE-spec - memcpy(dlsch_config_pdu, dci, sizeof(fapi_nr_dci_pdu_rel15_t)); - - dl_config->number_pdus = dl_config->number_pdus + 1; - - ret_mask |= (handle_dci( - dl_info->module_id, - dl_info->cc_id, - dl_info->gNB_index, - dci, - (dl_info->dci_ind->dci_list+i)->rnti, - (dl_info->dci_ind->dci_list+i)->dci_type)) << FAPI_NR_DCI_IND; - - - - break; - - default: - break; - }*/ - - //(dl_info->dci_list+i)->rnti - } - } - - if(dl_info->rx_ind != NULL){ - LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], Number of PDUs: %d \n", dl_info->rx_ind->number_pdus); - for(i=0; irx_ind->number_pdus; ++i){ - switch(dl_info->rx_ind->rx_indication_body[i].pdu_type){ - case FAPI_NR_RX_PDU_TYPE_MIB: - ret_mask |= (handle_bcch_bch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, - (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.pdu, - (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.additional_bits, - (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.ssb_index, - (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.ssb_length, - (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.cell_id )) << FAPI_NR_RX_PDU_TYPE_MIB; - LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], MIB case Number of PDUs: %d \n", dl_info->rx_ind->number_pdus); - /*ret_mask |= (handle_bcch_bch( dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, - dl_info->rx_ind->rx_indication_body[i].mib_pdu.pdu, - dl_info->rx_ind->rx_indication_body[i].mib_pdu.additional_bits, - dl_info->rx_ind->rx_indication_body[i].mib_pdu.ssb_index, - dl_info->rx_ind->rx_indication_body[i].mib_pdu.ssb_length, - dl_info->rx_ind->rx_indication_body[i].mib_pdu.cell_id )) << FAPI_NR_RX_PDU_TYPE_MIB;*/ - break; - case FAPI_NR_RX_PDU_TYPE_SIB: - ret_mask |= (handle_bcch_dlsch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, - (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.sibs_mask, - (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.pdu, - (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.pdu_length )) << FAPI_NR_RX_PDU_TYPE_SIB; - break; - case FAPI_NR_RX_PDU_TYPE_DLSCH: - // ret_mask |= (0) << FAPI_NR_RX_PDU_TYPE_DLSCH; - ret_mask |= (handle_dlsch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, dl_info->dci_ind, - (dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu, - (dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu_length, dl_info->frame, dl_info->slot, ul_time_alignment)) << FAPI_NR_RX_PDU_TYPE_DLSCH; - - LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], DLSCH case Number of PDUs: %d \n", dl_info->rx_ind->number_pdus); - - /* - // dl_config structure just stores what was received - not really needed - dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH; - dl_config->number_pdus = dl_config->number_pdus + 1; - */ - break; - - case FAPI_NR_RX_PDU_TYPE_RAR: - ret_mask |= (handle_rar(dl_info)) << FAPI_NR_RX_PDU_TYPE_RAR; - break; - - default: - break; + AssertFatal( nr_ue_if_module_inst[module_id] != NULL, "IF module is void!\n" ); + nr_ue_if_module_inst[module_id]->scheduled_response(&mac->scheduled_response); } } + + if(dl_info->rx_ind != NULL){ + + LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], Number of PDUs: %d \n", dl_info->rx_ind->number_pdus); + + for(i=0; irx_ind->number_pdus; ++i){ + + switch(dl_info->rx_ind->rx_indication_body[i].pdu_type){ + + case FAPI_NR_RX_PDU_TYPE_MIB: + ret_mask |= (handle_bcch_bch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, + (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.pdu, + (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.additional_bits, + (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.ssb_index, + (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.ssb_length, + (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.cell_id)) << FAPI_NR_RX_PDU_TYPE_MIB; + + LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], MIB case Number of PDUs: %d \n", dl_info->rx_ind->number_pdus); + + break; + + case FAPI_NR_RX_PDU_TYPE_SIB: + + ret_mask |= (handle_bcch_dlsch(dl_info->module_id, + dl_info->cc_id, dl_info->gNB_index, + (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.sibs_mask, + (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.pdu, + (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.pdu_length)) << FAPI_NR_RX_PDU_TYPE_SIB; + + break; + + case FAPI_NR_RX_PDU_TYPE_DLSCH: + + ret_mask |= (handle_dlsch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, + dl_info->dci_ind, + (dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu, + (dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu_length, + dl_info->frame, + dl_info->slot, + ul_time_alignment)) << FAPI_NR_RX_PDU_TYPE_DLSCH; + + LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], DLSCH case Number of PDUs: %d \n", dl_info->rx_ind->number_pdus); + + break; + + case FAPI_NR_RX_PDU_TYPE_RAR: + + ret_mask |= (handle_rar(dl_info)) << FAPI_NR_RX_PDU_TYPE_RAR; + + break; + + default: + break; + } + } + } + + //clean up nr_downlink_indication_t *dl_info + dl_info->rx_ind = NULL; + dl_info->dci_ind = NULL; + + return 0; } - - //clean up nr_downlink_indication_t *dl_info - dl_info->rx_ind = NULL; - dl_info->dci_ind = NULL; - - return 0; } nr_ue_if_module_t *nr_ue_if_module_init(uint32_t module_id){ From d988eb82fc1ca3fcc83e5324a876f1468699c30b Mon Sep 17 00:00:00 2001 From: "s.rampalli" Date: Mon, 20 Apr 2020 11:27:56 +0530 Subject: [PATCH 283/553] Removed temporary values in x2ap and rrc --- openair2/COMMON/x2ap_messages_types.h | 3 +- openair2/RRC/LTE/rrc_eNB.c | 228 +++++++++++++++++++-- openair2/RRC/NR/rrc_gNB_nsa.c | 2 + openair2/X2AP/x2ap_eNB.c | 68 +++++- openair2/X2AP/x2ap_eNB_generate_messages.c | 91 +++----- openair2/X2AP/x2ap_eNB_handler.c | 18 +- 6 files changed, 308 insertions(+), 102 deletions(-) diff --git a/openair2/COMMON/x2ap_messages_types.h b/openair2/COMMON/x2ap_messages_types.h index 38b3b7d653..f0743e60a5 100644 --- a/openair2/COMMON/x2ap_messages_types.h +++ b/openair2/COMMON/x2ap_messages_types.h @@ -315,7 +315,7 @@ typedef struct x2ap_senb_addition_req_ack_s { typedef struct x2ap_ENDC_sgnb_addition_req_s { int ue_x2_id; - + LTE_PhysCellId_t target_physCellId; /* used for RRC->X2AP in source eNB */ int rnti; @@ -386,6 +386,7 @@ typedef struct x2ap_ENDC_reconf_complete_s { int MeNB_ue_x2_id; int SgNB_ue_x2_id; + LTE_PhysCellId_t target_physCellId; x2ap_sgNB_reconf_response_information_t reconf_response; diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index ba6b2c41c1..cf69d9620e 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -96,6 +96,11 @@ #include "SIMULATION/TOOLS/sim.h" // for taus +#define ASN_MAX_ENCODE_SIZE 1000 +static int add_CG_ConfigInfo(char **enc_buf,rrc_eNB_ue_context_t *const ue_context_pP,int * enc_size); +static int is_en_dc_supported(LTE_UE_EUTRA_Capability_t *c); +static void free_rb_config(struct NR_RadioBearerConfig *rb_config); +static void free_cg_configinfo(struct NR_CG_ConfigInfo *cg_configinfo); extern RAN_CONTEXT_t RC; @@ -4334,6 +4339,8 @@ rrc_eNB_process_MeasurementReport( long ncell_max = -150; uint32_t earfcn_dl; uint8_t KeNB_star[32] = { 0 }; + char *enc_buf = NULL; + int enc_size = 0; T(T_ENB_RRC_MEASUREMENT_REPORT, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame), T_INT(ctxt_pP->subframe), T_INT(ctxt_pP->rnti)); @@ -4396,27 +4403,36 @@ rrc_eNB_process_MeasurementReport( MessageDef *msg; ue_context_pP->ue_context.Status = RRC_NR_NSA; - msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ); - X2AP_ENDC_SGNB_ADDITION_REQ(msg).rnti = ctxt_pP->rnti; - //For the moment we have a single E-RAB which will be the one to be added to the gNB - //Not sure how to select bearers to be added if there are multiple. - X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded = 1; - for (int e_rab=0; e_rab < X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded; e_rab++){ - X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].e_rab_id = ue_context_pP->ue_context.e_rab[e_rab].param.e_rab_id; - X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].gtp_teid = ue_context_pP->ue_context.e_rab[e_rab].param.gtp_teid; - X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].drb_ID = 1; - memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr, + if(is_en_dc_supported(ue_context_pP->ue_context.UE_Capability)) { +/** to add gNB as Secondary node CG-ConfigInfo to be added as per 36.423 r15 **/ + if(add_CG_ConfigInfo(&enc_buf,ue_context_pP,&enc_size) == RRC_OK) + LOG_I(RRC,"CG-ConfigInfo encoded successfully\n"); + msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ); + X2AP_ENDC_SGNB_ADDITION_REQ(msg).rnti = ctxt_pP->rnti; + memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer,enc_buf,enc_size); + X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer_size = enc_size; + X2AP_ENDC_SGNB_ADDITION_REQ(msg).target_physCellId + = measResults2->measResultNeighCells->choice.measResultListEUTRA.list.array[0]->physCellId; + + //For the moment we have a single E-RAB which will be the one to be added to the gNB + //Not sure how to select bearers to be added if there are multiple. + X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded = 1; + for (int e_rab=0; e_rab < X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded; e_rab++){ + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].e_rab_id = ue_context_pP->ue_context.e_rab[e_rab].param.e_rab_id; + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].gtp_teid = ue_context_pP->ue_context.e_rab[e_rab].param.gtp_teid; + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].drb_ID = 1; + memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr, &ue_context_pP->ue_context.e_rab[e_rab].param.sgw_addr, sizeof(transport_layer_addr_t)); - } - LOG_I(RRC, + } + LOG_I(RRC, "[eNB %d] frame %d subframe %d: UE rnti %x switching to NSA mode\n", ctxt_pP->module_id, ctxt_pP->frame, ctxt_pP->subframe, ctxt_pP->rnti); - itti_send_msg_to_task(TASK_X2AP, ENB_MODULE_ID_TO_INSTANCE(ctxt_pP->module_id), msg); - return; - } + itti_send_msg_to_task(TASK_X2AP, ENB_MODULE_ID_TO_INSTANCE(ctxt_pP->module_id), msg); + return; + } } - +} if (measResults2->measResultNeighCells == NULL) return; @@ -4531,6 +4547,186 @@ rrc_eNB_process_MeasurementReport( } } + +//----------------------------------------------------------------------------- +/** + * @fn :add_CG_ConfigInfo + * @param :enc_buf to store the encoded bits + * @param :ue_context_pP ue context used to fill CG-ConfigInfo + * @param :enc_size to store thre size of encoded size + * this api is to fill and encode CG-ConfigInfo + */ +int add_CG_ConfigInfo( + char **enc_buf, + rrc_eNB_ue_context_t *const ue_context_pP, + int * enc_size +) { + struct NR_CG_ConfigInfo *cg_configinfo = NULL; + struct NR_RadioBearerConfig *rb_config = NULL; + asn_enc_rval_t enc_rval; + int RRC_OK = 1; + int index = 0; + + rb_config = calloc(1,sizeof( struct NR_RadioBearerConfig)); + AssertFatal(rb_config != NULL,"failed to allocate memory for rb_config"); + + if(ue_context_pP->ue_context.DRB_configList->list.count != 0) { + rb_config->drb_ToAddModList = calloc(1,sizeof(struct NR_DRB_ToAddModList )); + AssertFatal(rb_config->drb_ToAddModList != NULL,"failed to allocated memory for drbtoaddmodlist"); + rb_config->drb_ToAddModList->list.count = ue_context_pP->ue_context.DRB_configList->list.count; + rb_config->drb_ToAddModList->list.array + = calloc(ue_context_pP->ue_context.DRB_configList->list.count, sizeof(struct LTE_DRB_ToAddMod)); + AssertFatal( rb_config->drb_ToAddModList->list.array != NULL, + "falied to allocate memory for list.array"); + for(index = 0;index < ue_context_pP->ue_context.DRB_configList->list.count;index++) { + rb_config->drb_ToAddModList->list.array[index] + = calloc(1,sizeof(struct LTE_DRB_ToAddMod)); + AssertFatal(rb_config->drb_ToAddModList->list.array[index] != NULL, + "failed to allocate memory for drb_toaddmod"); + rb_config->drb_ToAddModList->list.array[index]->drb_Identity + =ue_context_pP->ue_context.DRB_configList->list.array[index]->drb_Identity; + if(ue_context_pP->ue_context.DRB_configList->list.array[index]->eps_BearerIdentity) { + rb_config->drb_ToAddModList->list.array[index]->cnAssociation + =calloc(1,sizeof(struct NR_DRB_ToAddMod__cnAssociation)); + AssertFatal(rb_config->drb_ToAddModList->list.array[index]->cnAssociation != NULL, + "failed to allocate memory cnAssociation"); + rb_config->drb_ToAddModList->list.array[index]->cnAssociation->present + =NR_DRB_ToAddMod__cnAssociation_PR_eps_BearerIdentity; + rb_config->drb_ToAddModList->list.array[index]->cnAssociation->choice.eps_BearerIdentity + =*(ue_context_pP->ue_context.DRB_configList->list.array[index]->eps_BearerIdentity); + } + } + } + + cg_configinfo = calloc(1,sizeof(struct NR_CG_ConfigInfo)); + AssertFatal(cg_configinfo != NULL,"failed to allocate memory for cg_configinfo"); + cg_configinfo->criticalExtensions.present = NR_CG_ConfigInfo__criticalExtensions_PR_c1; + cg_configinfo->criticalExtensions.choice.c1 + = calloc(1, sizeof(struct NR_CG_ConfigInfo__criticalExtensions__c1)); + AssertFatal(cg_configinfo->criticalExtensions.choice.c1 != NULL, + "failed to allocate memory for cg_configinfo->criticalExtensions.choice.c1"); + cg_configinfo->criticalExtensions.choice.c1->present + = NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo; + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo + = calloc(1,sizeof(struct NR_CG_ConfigInfo_IEs)); + AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo != NULL, + "failed to allocate memory for cg_configinfo_IEs"); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo + = calloc(1,sizeof( OCTET_STRING_t)); + AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> + ue_CapabilityInfo != NULL, "failed to allocate memory for ue_capabilityinfo"); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->size + = ue_context_pP->ue_context.UE_Capability_size; + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf + = calloc(1,sizeof(ue_context_pP->ue_context.UE_Capability_size)); + AssertFatal( cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> + ue_CapabilityInfo->buf != NULL, "failed to allocate memory for buf"); + memcpy(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf, + ue_context_pP->ue_context.UE_Capability,ue_context_pP->ue_context.UE_Capability_size); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config + = calloc(1,sizeof(OCTET_STRING_t)); + AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> + mcg_RB_Config != NULL, "failed to allocate memory for mcg_rb_config"); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->size + = sizeof( struct NR_RadioBearerConfig); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf + = calloc(1,sizeof(struct NR_RadioBearerConfig)); + AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> + mcg_RB_Config->buf != NULL,"failed to allocate memory for buf"); + memcpy(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf, + rb_config,sizeof(struct NR_RadioBearerConfig)); + enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CG_ConfigInfo,NULL,(void*)cg_configinfo, + enc_buf,ASN_MAX_ENCODE_SIZE); + AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %lu)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + *enc_size = (enc_rval.encoded+7)/8; + free_rb_config(rb_config); + free_cg_configinfo(cg_configinfo); + return RRC_OK; + } +//----------------------------------------------------------------------------- + + + +/** + * @fn :api to free the all the dynamically allocated memory + * @param :cg_configinfo contains cellgroup configuration + */ +void free_cg_configinfo( + struct NR_CG_ConfigInfo *cg_configinfo +) { + if(cg_configinfo){ + if(cg_configinfo->criticalExtensions.choice.c1){ + if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo){ + if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo){ + if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf){ + if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config){ + if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf){ + free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf =NULL; + free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config =NULL; + free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf = NULL; + free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo =NULL; + free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo =NULL; + free(cg_configinfo->criticalExtensions.choice.c1); + cg_configinfo->criticalExtensions.choice.c1 =NULL; + free(cg_configinfo); + cg_configinfo =NULL; + } + } + } + } + } + } + } + return; +} +//----------------------------------------------------------------------------- + + + +//----------------------------------------------------------------------------- +/** + * @fn :api to free the all the dynamically allocated memory + * @param :rb_config contains radiobearer configuration + */ +void free_rb_config( + struct NR_RadioBearerConfig *rb_config +) { + int index = 0; + + if(rb_config) { + if(rb_config->drb_ToAddModList) { + if(rb_config->drb_ToAddModList->list.array) { + for(index = 0; index < rb_config->drb_ToAddModList->list.count; index++) { + if(rb_config->drb_ToAddModList->list.array[index]->cnAssociation) { + free(rb_config->drb_ToAddModList->list.array[index]->cnAssociation); + rb_config->drb_ToAddModList->list.array[index]->cnAssociation = NULL; + } + if(rb_config->drb_ToAddModList->list.array[index]) { + free(rb_config->drb_ToAddModList->list.array[index]); + rb_config->drb_ToAddModList->list.array[index] = NULL; + } + } + free(rb_config->drb_ToAddModList->list.array); + rb_config->drb_ToAddModList->list.array = NULL; + free(rb_config->drb_ToAddModList); + rb_config->drb_ToAddModList = NULL; + free(rb_config); + rb_config = NULL; + } + } + } + return; +} +//------------------------------------------------------------------------------ + + + //----------------------------------------------------------------------------- void rrc_eNB_generate_HandoverPreparationInformation( diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c index 70bd150bd4..18ebfebf8d 100644 --- a/openair2/RRC/NR/rrc_gNB_nsa.c +++ b/openair2/RRC/NR/rrc_gNB_nsa.c @@ -179,6 +179,8 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_ &create_tunnel_resp, &inde_list[0]); X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).nb_e_rabs_admitted_tobeadded = m->nb_e_rabs_tobeadded; + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).target_assoc_id = m->target_assoc_id; + for(int i=0; iue_context.nb_of_e_rabs; i++){ X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].e_rab_id = ue_context_p->ue_context.e_rab[i].param.e_rab_id; X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gtp_teid = create_tunnel_resp.enb_S1u_teid[i]; diff --git a/openair2/X2AP/x2ap_eNB.c b/openair2/X2AP/x2ap_eNB.c index debe5e0712..6a037b8ee3 100644 --- a/openair2/X2AP/x2ap_eNB.c +++ b/openair2/X2AP/x2ap_eNB.c @@ -359,7 +359,7 @@ void x2ap_eNB_handle_sctp_init_msg_multi_cnf( * Failure means multi_sd < 0. */ if (instance->multi_sd < 0) { - X2AP_ERROR("Error: be sure to properly configure X22 in your configuration file.\n"); + X2AP_ERROR("Error: be sure to properly configure X2 in your configuration file.\n"); DevAssert(instance->multi_sd >= 0); } @@ -454,10 +454,12 @@ void x2ap_eNB_handle_sgNB_add_req(instance_t instance, x2ap_eNB_instance_t *instance_p; x2ap_eNB_data_t *x2ap_eNB_data; int ue_id; - - /* TODO: remove hardcoded value */ - x2ap_eNB_data = x2ap_is_eNB_id_in_list(3584); + LTE_PhysCellId_t target_pci; + target_pci = x2ap_ENDC_sgnb_addition_req->target_physCellId; + x2ap_eNB_data = x2ap_is_eNB_pci_in_list(target_pci); DevAssert(x2ap_eNB_data != NULL); + DevAssert(x2ap_ENDC_sgnb_addition_req != NULL); + instance_p = x2ap_eNB_get_instance(instance); DevAssert(instance_p != NULL); @@ -474,7 +476,8 @@ void x2ap_eNB_handle_sgNB_add_req(instance_t instance, x2ap_set_ids(id_manager, ue_id, x2ap_ENDC_sgnb_addition_req->rnti, ue_id, -1); x2ap_id_set_state(id_manager, ue_id, X2ID_STATE_NSA_PREPARE); - x2ap_eNB_generate_ENDC_x2_SgNB_addition_request(instance_p, x2ap_ENDC_sgnb_addition_req, x2ap_eNB_data, ue_id); + x2ap_eNB_generate_ENDC_x2_SgNB_addition_request(instance_p, x2ap_ENDC_sgnb_addition_req, + x2ap_eNB_data, ue_id); } static @@ -489,16 +492,31 @@ void x2ap_gNB_trigger_sgNB_add_req_ack(instance_t instance, * as far as I understand.. CROUX */ - + x2ap_id_manager *id_manager; x2ap_eNB_instance_t *instance_p; x2ap_eNB_data_t *target; - /*int source_assoc_id = x2ap_ENDC_sgnb_addition_req_ACK->source_assoc_id; int ue_id; + /*int source_assoc_id = x2ap_ENDC_sgnb_addition_req_ACK->source_assoc_id; int id_source; int id_target;*/ instance_p = x2ap_eNB_get_instance(instance); DevAssert(instance_p != NULL); + target = x2ap_get_eNB(NULL,x2ap_ENDC_sgnb_addition_req_ACK->target_assoc_id, 0); + DevAssert(target != NULL); + + /* allocate x2ap ID */ + id_manager = &instance_p->id_manager; + ue_id = x2ap_allocate_new_id(id_manager); + if (ue_id == -1) { + X2AP_ERROR("could not allocate a new X2AP UE ID\n"); + exit(1); + } + /* id_source is ue_id, id_target is unknown yet */ + x2ap_set_ids(id_manager, ue_id, x2ap_ENDC_sgnb_addition_req_ACK->rnti, ue_id, + x2ap_ENDC_sgnb_addition_req_ACK->MeNB_ue_x2_id); + x2ap_id_set_state(id_manager, ue_id, X2ID_STATE_SOURCE_OVERALL); + /*target = x2ap_get_eNB(NULL, source_assoc_id, 0); DevAssert(target != NULL);*/ @@ -511,10 +529,36 @@ void x2ap_gNB_trigger_sgNB_add_req_ack(instance_t instance, x2ap_set_ids(&instance_p->id_manager, ue_id, x2ap_handover_req_ack->rnti, id_source, id_target);*/ - //target = x2ap_get_eNB(NULL, 17, 0); - target = x2ap_is_eNB_id_in_list (3585); //Currently hardcoded. Need to extract it differently + x2ap_gNB_generate_ENDC_x2_SgNB_addition_request_ACK(instance_p, target, + x2ap_ENDC_sgnb_addition_req_ACK, ue_id); +} + +/** + * @fn : Function triggers sgnb reconfiguration complete + * @param : IN instance, IN x2ap_reconf_complete +**/ +static +void x2ap_eNB_trigger_sgnb_reconfiguration_complete(instance_t instance, + x2ap_ENDC_reconf_complete_t *x2ap_reconf_complete) +{ + x2ap_eNB_instance_t *instance_p = NULL; + x2ap_eNB_data_t *target = NULL; + int id_source = -1; + int id_target = -1; + LTE_PhysCellId_t target_pci; + + instance_p = x2ap_eNB_get_instance(instance); + DevAssert(instance_p != NULL); + DevAssert(x2ap_reconf_complete != NULL); + + target_pci = x2ap_reconf_complete->target_physCellId; + target = x2ap_is_eNB_pci_in_list(target_pci); DevAssert(target != NULL); - x2ap_gNB_generate_ENDC_x2_SgNB_addition_request_ACK(instance_p, target, x2ap_ENDC_sgnb_addition_req_ACK, 0); + + id_source = x2ap_reconf_complete->MeNB_ue_x2_id; + id_target = x2ap_reconf_complete->SgNB_ue_x2_id; + x2ap_eNB_generate_ENDC_x2_SgNB_reconfiguration_complete(instance_p, target, id_source, id_target); + } @@ -594,6 +638,10 @@ void *x2ap_task(void *arg) { LOG_I(X2AP, "Received elements for X2AP_ENDC_SGNB_ADDITION_REQ_ACK \n"); break; + case X2AP_ENDC_SGNB_RECONF_COMPLETE: + x2ap_eNB_trigger_sgnb_reconfiguration_complete(ITTI_MESSAGE_GET_INSTANCE(received_msg), + &X2AP_ENDC_SGNB_RECONF_COMPLETE(received_msg)); + break; case SCTP_INIT_MSG_MULTI_CNF: x2ap_eNB_handle_sctp_init_msg_multi_cnf(ITTI_MESSAGE_GET_INSTANCE(received_msg), &received_msg->ittiMsg.sctp_init_msg_multi_cnf); diff --git a/openair2/X2AP/x2ap_eNB_generate_messages.c b/openair2/X2AP/x2ap_eNB_generate_messages.c index 0478448070..a96fa14f48 100644 --- a/openair2/X2AP/x2ap_eNB_generate_messages.c +++ b/openair2/X2AP/x2ap_eNB_generate_messages.c @@ -1496,7 +1496,8 @@ int x2ap_eNB_generate_ENDC_x2_setup_response( } int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request( - x2ap_eNB_instance_t *instance_p, x2ap_ENDC_sgnb_addition_req_t *x2ap_ENDC_sgnb_addition_req, x2ap_eNB_data_t *x2ap_eNB_data_p, int ue_id) + x2ap_eNB_instance_t *instance_p, x2ap_ENDC_sgnb_addition_req_t *x2ap_ENDC_sgnb_addition_req, + x2ap_eNB_data_t *x2ap_eNB_data_p, int ue_id) { X2AP_X2AP_PDU_t pdu; X2AP_SgNBAdditionRequest_t *out; @@ -1507,42 +1508,21 @@ int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request( uint8_t *buffer; uint32_t len; int ret = 0; - - // Currently hardcoded (dummy) values filling the fields of SgNB_addition_request message. To be substituted - // with values coming from RRC. - uint16_t nRencryptionAlgorithms = 0; - uint16_t nRintegrityProtectionAlgorithms = 0; + uint16_t nRencryptionAlgorithms = x2ap_ENDC_sgnb_addition_req->security_capabilities.encryption_algorithms; + uint16_t nRintegrityProtectionAlgorithms = x2ap_ENDC_sgnb_addition_req->security_capabilities + .integrity_algorithms; uint8_t SgNBSecurityKey[32] = { 0 }; - int uEaggregateMaximumBitRateDownlink = 100000000; - int uEaggregateMaximumBitRateUplink = 100000000; - int e_rabs_tobeadded = 1; + int uEaggregateMaximumBitRateDownlink = x2ap_ENDC_sgnb_addition_req->ue_ambr.br_dl; + int uEaggregateMaximumBitRateUplink = x2ap_ENDC_sgnb_addition_req->ue_ambr.br_ul; + int e_rabs_tobeadded = x2ap_ENDC_sgnb_addition_req->nb_e_rabs_tobeadded; long int pDCPatSgNB = X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present; long int mCGresources = X2AP_EN_DC_ResourceConfiguration__mCGresources_not_present; long int sCGresources = X2AP_EN_DC_ResourceConfiguration__sCGresources_not_present; - long qCI = 1; - X2AP_Pre_emptionCapability_t pre_emptionCapability = X2AP_Pre_emptionCapability_shall_not_trigger_pre_emption; - X2AP_Pre_emptionVulnerability_t pre_emptionVulnerability = X2AP_Pre_emptionVulnerability_not_pre_emptable; - priority_level_t priority_level = PRIORITY_LEVEL_NO_PRIORITY; - e_rab_tobe_added_t e_MCG_rabs_tobeadded; - e_MCG_rabs_tobeadded.gtp_teid = 0; - e_MCG_rabs_tobeadded.sgw_addr.length = 24; - uint8_t buf[20] = { 0 }; - memcpy(e_MCG_rabs_tobeadded.sgw_addr.buffer, buf, 20*sizeof(uint8_t)); - - FILE *fd; - fd = fopen("../../../executables/uecap.raw","r"); - if (fd != NULL) { - OCTET_STRING_t CG_Config_Info; - CG_Config_Info.size = 4096; - CG_Config_Info.buf = (uint8_t *)calloc(4096, sizeof(uint8_t)); - int msg_len=fread(CG_Config_Info.buf,1,CG_Config_Info.size,fd); - CG_Config_Info.size = msg_len; - - /*char buffer[4096]; - int msg_len=fread(buffer,1,4096,fd);*/ - LOG_I(RRC,"Read in %d bytes for uecap\n",msg_len); - - + long qCI = 0; + X2AP_Pre_emptionCapability_t pre_emptionCapability; + X2AP_Pre_emptionVulnerability_t pre_emptionVulnerability; + priority_level_t priority_level; + memcpy(SgNBSecurityKey, x2ap_ENDC_sgnb_addition_req->kgnb, sizeof(x2ap_ENDC_sgnb_addition_req->kgnb)); /*OCTET_STRING_t CG_Config_Info; CG_Config_Info.size = 4096; CG_Config_Info.buf = (uint8_t *)calloc(4096, sizeof(uint8_t));*/ @@ -1618,7 +1598,11 @@ int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request( e_RABS_ToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.mCGresources = mCGresources; e_RABS_ToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.sCGresources = sCGresources; if (pDCPatSgNB == X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present){ - e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.present = X2AP_E_RABs_ToBeAdded_SgNBAddReq_Item__resource_configuration_PR_sgNBPDCPpresent; + e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.present = X2AP_E_RABs_ToBeAdded_SgNBAddReq_Item__resource_configuration_PR_sgNBPDCPpresent; + qCI = x2ap_ENDC_sgnb_addition_req->e_rab_param[i].qos.qci; + priority_level = x2ap_ENDC_sgnb_addition_req->e_rab_param[i].qos.allocation_retention_priority.priority_level; + pre_emptionCapability = x2ap_ENDC_sgnb_addition_req->e_rab_param[i].qos.allocation_retention_priority.pre_emp_capability; + pre_emptionVulnerability = x2ap_ENDC_sgnb_addition_req->e_rab_param[i].qos.allocation_retention_priority.pre_emp_vulnerability; e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.full_E_RAB_Level_QoS_Parameters.qCI = qCI; e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.full_E_RAB_Level_QoS_Parameters.allocationAndRetentionPriority.pre_emptionCapability = pre_emptionCapability; @@ -1646,25 +1630,24 @@ int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request( ie->id = X2AP_ProtocolIE_ID_id_MeNBtoSgNBContainer; ie->criticality = X2AP_Criticality_reject; ie->value.present = X2AP_SgNBAdditionRequest_IEs__value_PR_MeNBtoSgNBContainer; - ie->value.choice.MeNBtoSgNBContainer.buf = (uint8_t *)calloc(CG_Config_Info.size, sizeof(uint8_t)); - memcpy(ie->value.choice.MeNBtoSgNBContainer.buf, CG_Config_Info.buf, CG_Config_Info.size); - ie->value.choice.MeNBtoSgNBContainer.size = CG_Config_Info.size; //4096; + if(NULL == (ie->value.choice.MeNBtoSgNBContainer.buf = (uint8_t *) + calloc(x2ap_ENDC_sgnb_addition_req->rrc_buffer_size, sizeof(uint8_t)))) { + X2AP_ERROR("Memory ALLocation failed\n"); + exit(1); + } + memcpy(ie->value.choice.MeNBtoSgNBContainer.buf, x2ap_ENDC_sgnb_addition_req->rrc_buffer, + x2ap_ENDC_sgnb_addition_req->rrc_buffer_size); + ie->value.choice.MeNBtoSgNBContainer.size = x2ap_ENDC_sgnb_addition_req->rrc_buffer_size; ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie); if (x2ap_eNB_encode_pdu(&pdu, &buffer, &len) < 0) { X2AP_ERROR("Failed to encode ENDC X2 SgNB_addition request message\n"); return -1; } - + free(ie->value.choice.MeNBtoSgNBContainer.buf); MSC_LOG_TX_MESSAGE (MSC_X2AP_SRC_ENB, MSC_X2AP_TARGET_ENB, NULL, 0, "0 X2Setup/initiatingMessage assoc_id %u", x2ap_eNB_data_p->assoc_id); x2ap_eNB_itti_send_sctp_data_req(instance_p->instance, x2ap_eNB_data_p->assoc_id, buffer, len, 0); - fclose(fd); - } - else { - LOG_I(RRC, "uecap.raw file could not be opened... \n"); - return -1; - } return ret; @@ -1684,26 +1667,14 @@ int x2ap_gNB_generate_ENDC_x2_SgNB_addition_request_ACK( x2ap_eNB_instance_t *in uint8_t *buffer; uint32_t len; int ret = 0; - int MeNB_UE_X2AP_id = ue_id; - int SgNB_UE_X2AP_id = 0; - // Currently hardcoded (dummy) values filling the fields of SgNB_addition_request message. To be substituted - // with values coming from RRC. - //uint16_t nRencryptionAlgorithms = 0; - //uint16_t nRintegrityProtectionAlgorithms = 0; - //uint8_t SgNBSecurityKey[32] = { 0 }; - //int uEaggregateMaximumBitRateDownlink = 100000000; - //int uEaggregateMaximumBitRateUplink = 100000000; - - int e_rabs_admitted_tobeadded = 1; + int MeNB_UE_X2AP_id = x2ap_sgnb_addition_req_ACK->MeNB_ue_x2_id; + int SgNB_UE_X2AP_id = ue_id; + int e_rabs_admitted_tobeadded = x2ap_sgnb_addition_req_ACK->nb_e_rabs_admitted_tobeadded; long int pDCPatSgNB = X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present; long int mCGresources = X2AP_EN_DC_ResourceConfiguration__mCGresources_not_present; long int sCGresources = X2AP_EN_DC_ResourceConfiguration__sCGresources_not_present; - e_rab_setup_t e_SCG_rabs_tobeadded; - e_SCG_rabs_tobeadded.gtp_teid = 0; - e_SCG_rabs_tobeadded.eNB_addr.length = 24; - uint8_t buf[20] = { 0 }; - memcpy(e_SCG_rabs_tobeadded.eNB_addr.buffer, buf, 20*sizeof(uint8_t)); + DevAssert(instance_p != NULL); DevAssert(x2ap_eNB_data_p != NULL); diff --git a/openair2/X2AP/x2ap_eNB_handler.c b/openair2/X2AP/x2ap_eNB_handler.c index e144eda435..87ef5bf69f 100644 --- a/openair2/X2AP/x2ap_eNB_handler.c +++ b/openair2/X2AP/x2ap_eNB_handler.c @@ -1652,7 +1652,6 @@ int x2ap_gNB_handle_ENDC_sGNB_addition_request (instance_t instance, x2ap_eNB_instance_t *instance_p; x2ap_eNB_data_t *x2ap_eNB_data; MessageDef *msg; - int ue_id; DevAssert (pdu != NULL); x2SgNBAdditionRequest = &pdu->choice.initiatingMessage.value.choice.SgNBAdditionRequest; @@ -1683,20 +1682,9 @@ int x2ap_gNB_handle_ENDC_sGNB_addition_request (instance_t instance, X2AP_ERROR("%s %d: ie is a NULL pointer \n",__FILE__,__LINE__); return -1; } - - - // allocate a new X2AP UE ID - ue_id = x2ap_allocate_new_id(&instance_p->id_manager); - if (ue_id == -1) { - X2AP_ERROR("could not allocate a new X2AP UE ID\n"); - // TODO: cancel handover: send HO preparation failure to source eNB - exit(1); - } - // rnti is unknown yet, must not be set to -1, 0 is fine - x2ap_set_ids(&instance_p->id_manager, ue_id, 0, ie->value.choice.UE_X2AP_ID, ue_id); - x2ap_id_set_state(&instance_p->id_manager, ue_id, X2ID_STATE_TARGET); - - X2AP_ENDC_SGNB_ADDITION_REQ(msg).ue_x2_id = ue_id; + /* ue_x2_id = MeNB X2AP Id */ + X2AP_ENDC_SGNB_ADDITION_REQ(msg).ue_x2_id = ie->value.choice.UE_X2AP_ID; + X2AP_ENDC_SGNB_ADDITION_REQ(msg).target_assoc_id = assoc_id; /* X2AP_ProtocolIE_ID_id_NRUESecurityCapabilities */ From b8e43ff2daea87b10a63e5b2c0c28b7a400ac312 Mon Sep 17 00:00:00 2001 From: "s.rampalli" Date: Tue, 5 May 2020 09:09:27 +0530 Subject: [PATCH 284/553] fixed encoding failed issue --- openair2/RRC/LTE/rrc_eNB.c | 7 ++++--- openair2/X2AP/x2ap_eNB_handler.c | 4 ++-- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index cf69d9620e..f1bda35a26 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -4575,12 +4575,12 @@ int add_CG_ConfigInfo( AssertFatal(rb_config->drb_ToAddModList != NULL,"failed to allocated memory for drbtoaddmodlist"); rb_config->drb_ToAddModList->list.count = ue_context_pP->ue_context.DRB_configList->list.count; rb_config->drb_ToAddModList->list.array - = calloc(ue_context_pP->ue_context.DRB_configList->list.count, sizeof(struct LTE_DRB_ToAddMod)); + = calloc(ue_context_pP->ue_context.DRB_configList->list.count, sizeof(struct NR_DRB_ToAddMod)); AssertFatal( rb_config->drb_ToAddModList->list.array != NULL, "falied to allocate memory for list.array"); for(index = 0;index < ue_context_pP->ue_context.DRB_configList->list.count;index++) { rb_config->drb_ToAddModList->list.array[index] - = calloc(1,sizeof(struct LTE_DRB_ToAddMod)); + = calloc(1,sizeof(struct NR_DRB_ToAddMod)); AssertFatal(rb_config->drb_ToAddModList->list.array[index] != NULL, "failed to allocate memory for drb_toaddmod"); rb_config->drb_ToAddModList->list.array[index]->drb_Identity @@ -4618,7 +4618,7 @@ int add_CG_ConfigInfo( cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->size = ue_context_pP->ue_context.UE_Capability_size; cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf - = calloc(1,sizeof(ue_context_pP->ue_context.UE_Capability_size)); + = calloc(1,ue_context_pP->ue_context.UE_Capability_size); AssertFatal( cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> ue_CapabilityInfo->buf != NULL, "failed to allocate memory for buf"); memcpy(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf, @@ -4635,6 +4635,7 @@ int add_CG_ConfigInfo( mcg_RB_Config->buf != NULL,"failed to allocate memory for buf"); memcpy(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf, rb_config,sizeof(struct NR_RadioBearerConfig)); + xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo,(void*)cg_configinfo); enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CG_ConfigInfo,NULL,(void*)cg_configinfo, enc_buf,ASN_MAX_ENCODE_SIZE); AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %lu)!\n", diff --git a/openair2/X2AP/x2ap_eNB_handler.c b/openair2/X2AP/x2ap_eNB_handler.c index 87ef5bf69f..83bcbc4f15 100644 --- a/openair2/X2AP/x2ap_eNB_handler.c +++ b/openair2/X2AP/x2ap_eNB_handler.c @@ -1772,8 +1772,8 @@ LOG_I(RRC,"x2u tunnel: index %d target sgw ip %d.%d.%d.%d length %d gtp teid %u\ if (ie->value.choice.MeNBtoSgNBContainer.size > 8192 ) { printf("%s:%d: fatal: buffer too big\n", __FILE__, __LINE__); abort(); } - memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer, ie->value.choice.MeNBtoSgNBContainer.buf, ie->value.choice.MeNBtoSgNBContainer.size); - X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer_size = ie->value.choice.MeNBtoSgNBContainer.size; + // memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer, ie->value.choice.MeNBtoSgNBContainer.buf, ie->value.choice.MeNBtoSgNBContainer.size); + // X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer_size = ie->value.choice.MeNBtoSgNBContainer.size; itti_send_msg_to_task(TASK_RRC_GNB, instance_p->instance, msg); From eac285d40527a03e96673aacf1437ef46911f273 Mon Sep 17 00:00:00 2001 From: "s.rampalli" Date: Tue, 5 May 2020 13:55:49 +0530 Subject: [PATCH 285/553] rrc runtime errors fixed --- openair2/RRC/LTE/rrc_eNB.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index f1bda35a26..43f8b83a69 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -97,7 +97,7 @@ #include "SIMULATION/TOOLS/sim.h" // for taus #define ASN_MAX_ENCODE_SIZE 1000 -static int add_CG_ConfigInfo(char **enc_buf,rrc_eNB_ue_context_t *const ue_context_pP,int * enc_size); +static int add_CG_ConfigInfo(char *enc_buf,rrc_eNB_ue_context_t *const ue_context_pP,int * enc_size); static int is_en_dc_supported(LTE_UE_EUTRA_Capability_t *c); static void free_rb_config(struct NR_RadioBearerConfig *rb_config); static void free_cg_configinfo(struct NR_CG_ConfigInfo *cg_configinfo); @@ -4405,7 +4405,8 @@ rrc_eNB_process_MeasurementReport( if(is_en_dc_supported(ue_context_pP->ue_context.UE_Capability)) { /** to add gNB as Secondary node CG-ConfigInfo to be added as per 36.423 r15 **/ - if(add_CG_ConfigInfo(&enc_buf,ue_context_pP,&enc_size) == RRC_OK) + enc_buf = calloc(1,1000); + if(add_CG_ConfigInfo(enc_buf,ue_context_pP,&enc_size) == RRC_OK) LOG_I(RRC,"CG-ConfigInfo encoded successfully\n"); msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ); X2AP_ENDC_SGNB_ADDITION_REQ(msg).rnti = ctxt_pP->rnti; @@ -4557,9 +4558,9 @@ rrc_eNB_process_MeasurementReport( * this api is to fill and encode CG-ConfigInfo */ int add_CG_ConfigInfo( - char **enc_buf, + char *enc_buf, rrc_eNB_ue_context_t *const ue_context_pP, - int * enc_size + int *enc_size ) { struct NR_CG_ConfigInfo *cg_configinfo = NULL; struct NR_RadioBearerConfig *rb_config = NULL; From 69455512c8b6add2f9c7fb086d5b274e8f6347d7 Mon Sep 17 00:00:00 2001 From: "s.rampalli" Date: Tue, 5 May 2020 14:03:05 +0530 Subject: [PATCH 286/553] fixed rrc issues --- openair2/RRC/LTE/rrc_eNB.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index 43f8b83a69..f93eafd040 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -4636,7 +4636,8 @@ int add_CG_ConfigInfo( mcg_RB_Config->buf != NULL,"failed to allocate memory for buf"); memcpy(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf, rb_config,sizeof(struct NR_RadioBearerConfig)); - xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo,(void*)cg_configinfo); + // xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo,(void*)cg_configinfo); + // this xer_fprint can be enabled for additional debugging messages enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CG_ConfigInfo,NULL,(void*)cg_configinfo, enc_buf,ASN_MAX_ENCODE_SIZE); AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %lu)!\n", From a07cfa3dd33832fbb0d2d1f64b38ae014d47c494 Mon Sep 17 00:00:00 2001 From: "s.rampalli" Date: Tue, 5 May 2020 17:22:17 +0530 Subject: [PATCH 287/553] rrc changes --- openair2/RRC/LTE/rrc_eNB.c | 372 +++++++++++++++++++------------------ 1 file changed, 187 insertions(+), 185 deletions(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index f93eafd040..72e0304e62 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -97,7 +97,7 @@ #include "SIMULATION/TOOLS/sim.h" // for taus #define ASN_MAX_ENCODE_SIZE 1000 -static int add_CG_ConfigInfo(char *enc_buf,rrc_eNB_ue_context_t *const ue_context_pP,int * enc_size); +static int encode_CG_ConfigInfo(char *buffer,int buffer_size,rrc_eNB_ue_context_t *const ue_context_pP,int *enc_size); static int is_en_dc_supported(LTE_UE_EUTRA_Capability_t *c); static void free_rb_config(struct NR_RadioBearerConfig *rb_config); static void free_cg_configinfo(struct NR_CG_ConfigInfo *cg_configinfo); @@ -4324,6 +4324,190 @@ rrc_eNB_generate_RRCConnectionReconfiguration_SCell( } + +//----------------------------------------------------------------------------- +/** + * @fn :encode_CG_ConfigInfo + * @param :enc_buf to store the encoded bits + * @param :ue_context_pP ue context used to fill CG-ConfigInfo + * @param :enc_size to store thre size of encoded size + * this api is to fill and encode CG-ConfigInfo + */ +static int encode_CG_ConfigInfo( + char *buffer, + int buffer_size, + rrc_eNB_ue_context_t *const ue_context_pP, + int *enc_size +) { + struct NR_CG_ConfigInfo *cg_configinfo = NULL; + struct NR_RadioBearerConfig *rb_config = NULL; + asn_enc_rval_t enc_rval; + int RRC_OK = 1; + int index = 0; + + rb_config = calloc(1,sizeof( struct NR_RadioBearerConfig)); + AssertFatal(rb_config != NULL,"failed to allocate memory for rb_config"); + + if(ue_context_pP->ue_context.DRB_configList->list.count != 0) { + rb_config->drb_ToAddModList = calloc(1,sizeof(struct NR_DRB_ToAddModList )); + AssertFatal(rb_config->drb_ToAddModList != NULL,"failed to allocated memory for drbtoaddmodlist"); + rb_config->drb_ToAddModList->list.count = ue_context_pP->ue_context.DRB_configList->list.count; + rb_config->drb_ToAddModList->list.array + = calloc(ue_context_pP->ue_context.DRB_configList->list.count, sizeof(struct NR_DRB_ToAddMod)); + AssertFatal( rb_config->drb_ToAddModList->list.array != NULL, + "falied to allocate memory for list.array"); + for(index = 0;index < ue_context_pP->ue_context.DRB_configList->list.count;index++) { + rb_config->drb_ToAddModList->list.array[index] + = calloc(1,sizeof(struct NR_DRB_ToAddMod)); + AssertFatal(rb_config->drb_ToAddModList->list.array[index] != NULL, + "failed to allocate memory for drb_toaddmod"); + rb_config->drb_ToAddModList->list.array[index]->drb_Identity + =ue_context_pP->ue_context.DRB_configList->list.array[index]->drb_Identity; + if(ue_context_pP->ue_context.DRB_configList->list.array[index]->eps_BearerIdentity) { + rb_config->drb_ToAddModList->list.array[index]->cnAssociation + =calloc(1,sizeof(struct NR_DRB_ToAddMod__cnAssociation)); + AssertFatal(rb_config->drb_ToAddModList->list.array[index]->cnAssociation != NULL, + "failed to allocate memory cnAssociation"); + rb_config->drb_ToAddModList->list.array[index]->cnAssociation->present + =NR_DRB_ToAddMod__cnAssociation_PR_eps_BearerIdentity; + rb_config->drb_ToAddModList->list.array[index]->cnAssociation->choice.eps_BearerIdentity + =*(ue_context_pP->ue_context.DRB_configList->list.array[index]->eps_BearerIdentity); + } + } + } + + cg_configinfo = calloc(1,sizeof(struct NR_CG_ConfigInfo)); + AssertFatal(cg_configinfo != NULL,"failed to allocate memory for cg_configinfo"); + cg_configinfo->criticalExtensions.present = NR_CG_ConfigInfo__criticalExtensions_PR_c1; + cg_configinfo->criticalExtensions.choice.c1 + = calloc(1, sizeof(struct NR_CG_ConfigInfo__criticalExtensions__c1)); + AssertFatal(cg_configinfo->criticalExtensions.choice.c1 != NULL, + "failed to allocate memory for cg_configinfo->criticalExtensions.choice.c1"); + cg_configinfo->criticalExtensions.choice.c1->present + = NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo; + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo + = calloc(1,sizeof(struct NR_CG_ConfigInfo_IEs)); + AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo != NULL, + "failed to allocate memory for cg_configinfo_IEs"); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo + = calloc(1,sizeof( OCTET_STRING_t)); + AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> + ue_CapabilityInfo != NULL, "failed to allocate memory for ue_capabilityinfo"); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->size + = ue_context_pP->ue_context.UE_Capability_size; + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf + = calloc(1,ue_context_pP->ue_context.UE_Capability_size); + AssertFatal( cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> + ue_CapabilityInfo->buf != NULL, "failed to allocate memory for buf"); + memcpy(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf, + ue_context_pP->ue_context.UE_Capability,ue_context_pP->ue_context.UE_Capability_size); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config + = calloc(1,sizeof(OCTET_STRING_t)); + AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> + mcg_RB_Config != NULL, "failed to allocate memory for mcg_rb_config"); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->size + = sizeof( struct NR_RadioBearerConfig); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf + = calloc(1,sizeof(struct NR_RadioBearerConfig)); + AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> + mcg_RB_Config->buf != NULL,"failed to allocate memory for buf"); + memcpy(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf, + rb_config,sizeof(struct NR_RadioBearerConfig)); + // this xer_fprint can be enabled for additional debugging messages + // xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo,(void*)cg_configinfo); + enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CG_ConfigInfo,NULL,(void*)cg_configinfo, + buffer,buffer_size); + AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %lu)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + *enc_size = (enc_rval.encoded+7)/8; + free_rb_config(rb_config); + free_cg_configinfo(cg_configinfo); + return RRC_OK; + } +//----------------------------------------------------------------------------- + + + +/** + * @fn :api to free the all the dynamically allocated memory + * @param :cg_configinfo contains cellgroup configuration + */ +static void free_cg_configinfo( + struct NR_CG_ConfigInfo *cg_configinfo +) { + if(cg_configinfo){ + if(cg_configinfo->criticalExtensions.choice.c1){ + if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo){ + if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo){ + if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf){ + if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config){ + if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf){ + free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf =NULL; + free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config =NULL; + free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf = NULL; + free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo =NULL; + free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo =NULL; + free(cg_configinfo->criticalExtensions.choice.c1); + cg_configinfo->criticalExtensions.choice.c1 =NULL; + free(cg_configinfo); + cg_configinfo =NULL; + } + } + } + } + } + } + } + return; +} +//----------------------------------------------------------------------------- + + + +//----------------------------------------------------------------------------- +/** + * @fn :api to free the all the dynamically allocated memory + * @param :rb_config contains radiobearer configuration + */ +static void free_rb_config( + struct NR_RadioBearerConfig *rb_config +) { + int index = 0; + + if(rb_config) { + if(rb_config->drb_ToAddModList) { + if(rb_config->drb_ToAddModList->list.array) { + for(index = 0; index < rb_config->drb_ToAddModList->list.count; index++) { + if(rb_config->drb_ToAddModList->list.array[index]->cnAssociation) { + free(rb_config->drb_ToAddModList->list.array[index]->cnAssociation); + rb_config->drb_ToAddModList->list.array[index]->cnAssociation = NULL; + } + if(rb_config->drb_ToAddModList->list.array[index]) { + free(rb_config->drb_ToAddModList->list.array[index]); + rb_config->drb_ToAddModList->list.array[index] = NULL; + } + } + free(rb_config->drb_ToAddModList->list.array); + rb_config->drb_ToAddModList->list.array = NULL; + free(rb_config->drb_ToAddModList); + rb_config->drb_ToAddModList = NULL; + free(rb_config); + rb_config = NULL; + } + } + } + return; +} +//------------------------------------------------------------------------------ + + + + //----------------------------------------------------------------------------- void rrc_eNB_process_MeasurementReport( @@ -4339,7 +4523,7 @@ rrc_eNB_process_MeasurementReport( long ncell_max = -150; uint32_t earfcn_dl; uint8_t KeNB_star[32] = { 0 }; - char *enc_buf = NULL; + char enc_buf[ASN_MAX_ENCODE_SIZE] = {0}; int enc_size = 0; T(T_ENB_RRC_MEASUREMENT_REPORT, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame), T_INT(ctxt_pP->subframe), T_INT(ctxt_pP->rnti)); @@ -4405,8 +4589,7 @@ rrc_eNB_process_MeasurementReport( if(is_en_dc_supported(ue_context_pP->ue_context.UE_Capability)) { /** to add gNB as Secondary node CG-ConfigInfo to be added as per 36.423 r15 **/ - enc_buf = calloc(1,1000); - if(add_CG_ConfigInfo(enc_buf,ue_context_pP,&enc_size) == RRC_OK) + if(encode_CG_ConfigInfo(enc_buf,sizeof(enc_buf),ue_context_pP,&enc_size) == RRC_OK) LOG_I(RRC,"CG-ConfigInfo encoded successfully\n"); msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ); X2AP_ENDC_SGNB_ADDITION_REQ(msg).rnti = ctxt_pP->rnti; @@ -4549,187 +4732,6 @@ rrc_eNB_process_MeasurementReport( } -//----------------------------------------------------------------------------- -/** - * @fn :add_CG_ConfigInfo - * @param :enc_buf to store the encoded bits - * @param :ue_context_pP ue context used to fill CG-ConfigInfo - * @param :enc_size to store thre size of encoded size - * this api is to fill and encode CG-ConfigInfo - */ -int add_CG_ConfigInfo( - char *enc_buf, - rrc_eNB_ue_context_t *const ue_context_pP, - int *enc_size -) { - struct NR_CG_ConfigInfo *cg_configinfo = NULL; - struct NR_RadioBearerConfig *rb_config = NULL; - asn_enc_rval_t enc_rval; - int RRC_OK = 1; - int index = 0; - - rb_config = calloc(1,sizeof( struct NR_RadioBearerConfig)); - AssertFatal(rb_config != NULL,"failed to allocate memory for rb_config"); - - if(ue_context_pP->ue_context.DRB_configList->list.count != 0) { - rb_config->drb_ToAddModList = calloc(1,sizeof(struct NR_DRB_ToAddModList )); - AssertFatal(rb_config->drb_ToAddModList != NULL,"failed to allocated memory for drbtoaddmodlist"); - rb_config->drb_ToAddModList->list.count = ue_context_pP->ue_context.DRB_configList->list.count; - rb_config->drb_ToAddModList->list.array - = calloc(ue_context_pP->ue_context.DRB_configList->list.count, sizeof(struct NR_DRB_ToAddMod)); - AssertFatal( rb_config->drb_ToAddModList->list.array != NULL, - "falied to allocate memory for list.array"); - for(index = 0;index < ue_context_pP->ue_context.DRB_configList->list.count;index++) { - rb_config->drb_ToAddModList->list.array[index] - = calloc(1,sizeof(struct NR_DRB_ToAddMod)); - AssertFatal(rb_config->drb_ToAddModList->list.array[index] != NULL, - "failed to allocate memory for drb_toaddmod"); - rb_config->drb_ToAddModList->list.array[index]->drb_Identity - =ue_context_pP->ue_context.DRB_configList->list.array[index]->drb_Identity; - if(ue_context_pP->ue_context.DRB_configList->list.array[index]->eps_BearerIdentity) { - rb_config->drb_ToAddModList->list.array[index]->cnAssociation - =calloc(1,sizeof(struct NR_DRB_ToAddMod__cnAssociation)); - AssertFatal(rb_config->drb_ToAddModList->list.array[index]->cnAssociation != NULL, - "failed to allocate memory cnAssociation"); - rb_config->drb_ToAddModList->list.array[index]->cnAssociation->present - =NR_DRB_ToAddMod__cnAssociation_PR_eps_BearerIdentity; - rb_config->drb_ToAddModList->list.array[index]->cnAssociation->choice.eps_BearerIdentity - =*(ue_context_pP->ue_context.DRB_configList->list.array[index]->eps_BearerIdentity); - } - } - } - - cg_configinfo = calloc(1,sizeof(struct NR_CG_ConfigInfo)); - AssertFatal(cg_configinfo != NULL,"failed to allocate memory for cg_configinfo"); - cg_configinfo->criticalExtensions.present = NR_CG_ConfigInfo__criticalExtensions_PR_c1; - cg_configinfo->criticalExtensions.choice.c1 - = calloc(1, sizeof(struct NR_CG_ConfigInfo__criticalExtensions__c1)); - AssertFatal(cg_configinfo->criticalExtensions.choice.c1 != NULL, - "failed to allocate memory for cg_configinfo->criticalExtensions.choice.c1"); - cg_configinfo->criticalExtensions.choice.c1->present - = NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo; - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo - = calloc(1,sizeof(struct NR_CG_ConfigInfo_IEs)); - AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo != NULL, - "failed to allocate memory for cg_configinfo_IEs"); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo - = calloc(1,sizeof( OCTET_STRING_t)); - AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> - ue_CapabilityInfo != NULL, "failed to allocate memory for ue_capabilityinfo"); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->size - = ue_context_pP->ue_context.UE_Capability_size; - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf - = calloc(1,ue_context_pP->ue_context.UE_Capability_size); - AssertFatal( cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> - ue_CapabilityInfo->buf != NULL, "failed to allocate memory for buf"); - memcpy(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf, - ue_context_pP->ue_context.UE_Capability,ue_context_pP->ue_context.UE_Capability_size); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config - = calloc(1,sizeof(OCTET_STRING_t)); - AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> - mcg_RB_Config != NULL, "failed to allocate memory for mcg_rb_config"); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->size - = sizeof( struct NR_RadioBearerConfig); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf - = calloc(1,sizeof(struct NR_RadioBearerConfig)); - AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> - mcg_RB_Config->buf != NULL,"failed to allocate memory for buf"); - memcpy(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf, - rb_config,sizeof(struct NR_RadioBearerConfig)); - // xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo,(void*)cg_configinfo); - // this xer_fprint can be enabled for additional debugging messages - enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CG_ConfigInfo,NULL,(void*)cg_configinfo, - enc_buf,ASN_MAX_ENCODE_SIZE); - AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %lu)!\n", - enc_rval.failed_type->name, enc_rval.encoded); - *enc_size = (enc_rval.encoded+7)/8; - free_rb_config(rb_config); - free_cg_configinfo(cg_configinfo); - return RRC_OK; - } -//----------------------------------------------------------------------------- - - - -/** - * @fn :api to free the all the dynamically allocated memory - * @param :cg_configinfo contains cellgroup configuration - */ -void free_cg_configinfo( - struct NR_CG_ConfigInfo *cg_configinfo -) { - if(cg_configinfo){ - if(cg_configinfo->criticalExtensions.choice.c1){ - if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo){ - if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo){ - if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf){ - if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config){ - if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf){ - free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf =NULL; - free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config =NULL; - free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf = NULL; - free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo =NULL; - free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo =NULL; - free(cg_configinfo->criticalExtensions.choice.c1); - cg_configinfo->criticalExtensions.choice.c1 =NULL; - free(cg_configinfo); - cg_configinfo =NULL; - } - } - } - } - } - } - } - return; -} -//----------------------------------------------------------------------------- - - - -//----------------------------------------------------------------------------- -/** - * @fn :api to free the all the dynamically allocated memory - * @param :rb_config contains radiobearer configuration - */ -void free_rb_config( - struct NR_RadioBearerConfig *rb_config -) { - int index = 0; - - if(rb_config) { - if(rb_config->drb_ToAddModList) { - if(rb_config->drb_ToAddModList->list.array) { - for(index = 0; index < rb_config->drb_ToAddModList->list.count; index++) { - if(rb_config->drb_ToAddModList->list.array[index]->cnAssociation) { - free(rb_config->drb_ToAddModList->list.array[index]->cnAssociation); - rb_config->drb_ToAddModList->list.array[index]->cnAssociation = NULL; - } - if(rb_config->drb_ToAddModList->list.array[index]) { - free(rb_config->drb_ToAddModList->list.array[index]); - rb_config->drb_ToAddModList->list.array[index] = NULL; - } - } - free(rb_config->drb_ToAddModList->list.array); - rb_config->drb_ToAddModList->list.array = NULL; - free(rb_config->drb_ToAddModList); - rb_config->drb_ToAddModList = NULL; - free(rb_config); - rb_config = NULL; - } - } - } - return; -} -//------------------------------------------------------------------------------ - - - //----------------------------------------------------------------------------- void rrc_eNB_generate_HandoverPreparationInformation( From e7c20bc081ad7a29b77b06ed5d5845602a414e25 Mon Sep 17 00:00:00 2001 From: "s.rampalli" Date: Tue, 5 May 2020 19:53:13 +0530 Subject: [PATCH 288/553] mistake --- openair2/X2AP/x2ap_eNB_handler.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openair2/X2AP/x2ap_eNB_handler.c b/openair2/X2AP/x2ap_eNB_handler.c index 83bcbc4f15..87ef5bf69f 100644 --- a/openair2/X2AP/x2ap_eNB_handler.c +++ b/openair2/X2AP/x2ap_eNB_handler.c @@ -1772,8 +1772,8 @@ LOG_I(RRC,"x2u tunnel: index %d target sgw ip %d.%d.%d.%d length %d gtp teid %u\ if (ie->value.choice.MeNBtoSgNBContainer.size > 8192 ) { printf("%s:%d: fatal: buffer too big\n", __FILE__, __LINE__); abort(); } - // memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer, ie->value.choice.MeNBtoSgNBContainer.buf, ie->value.choice.MeNBtoSgNBContainer.size); - // X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer_size = ie->value.choice.MeNBtoSgNBContainer.size; + memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer, ie->value.choice.MeNBtoSgNBContainer.buf, ie->value.choice.MeNBtoSgNBContainer.size); + X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer_size = ie->value.choice.MeNBtoSgNBContainer.size; itti_send_msg_to_task(TASK_RRC_GNB, instance_p->instance, msg); From 38a39ec0be0e02cf0660f3379c02e84b46a1d13e Mon Sep 17 00:00:00 2001 From: "s.rampalli" Date: Tue, 5 May 2020 21:36:07 +0530 Subject: [PATCH 289/553] fixed rrc x2ap runtime issues --- openair2/RRC/LTE/rrc_eNB.c | 1 + 1 file changed, 1 insertion(+) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index 72e0304e62..f3205eeedd 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -4592,6 +4592,7 @@ rrc_eNB_process_MeasurementReport( if(encode_CG_ConfigInfo(enc_buf,sizeof(enc_buf),ue_context_pP,&enc_size) == RRC_OK) LOG_I(RRC,"CG-ConfigInfo encoded successfully\n"); msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ); + memset(&(X2AP_ENDC_SGNB_ADDITION_REQ(msg)), 0, sizeof(x2ap_ENDC_sgnb_addition_req_t)); X2AP_ENDC_SGNB_ADDITION_REQ(msg).rnti = ctxt_pP->rnti; memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer,enc_buf,enc_size); X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer_size = enc_size; From 9747773f16fe56be49bcac5eda251a04d2593731 Mon Sep 17 00:00:00 2001 From: "s.rampalli" Date: Wed, 6 May 2020 22:31:08 +0530 Subject: [PATCH 290/553] changed the encoded buffer size to 4096 --- openair2/RRC/LTE/rrc_eNB.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index f3205eeedd..3257a84f21 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -96,7 +96,7 @@ #include "SIMULATION/TOOLS/sim.h" // for taus -#define ASN_MAX_ENCODE_SIZE 1000 +#define ASN_MAX_ENCODE_SIZE 4096 static int encode_CG_ConfigInfo(char *buffer,int buffer_size,rrc_eNB_ue_context_t *const ue_context_pP,int *enc_size); static int is_en_dc_supported(LTE_UE_EUTRA_Capability_t *c); static void free_rb_config(struct NR_RadioBearerConfig *rb_config); From 63bc9a9ba3dea7bf4c14584ca4930beb50dd35b0 Mon Sep 17 00:00:00 2001 From: "s.rampalli" Date: Thu, 14 May 2020 12:22:44 +0530 Subject: [PATCH 291/553] coding done need to verify testing part --- openair2/RRC/LTE/rrc_eNB.c | 83 +++++++++++++++++++++++++++-- openair2/RRC/NR/rrc_gNB.c | 23 ++++---- openair2/RRC/NR/rrc_gNB_internode.c | 2 +- openair2/RRC/NR/rrc_gNB_nsa.c | 8 +-- openair2/RRC/NR/rrc_gNB_reconfig.c | 15 +++++- 5 files changed, 112 insertions(+), 19 deletions(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index 3257a84f21..a2e998535e 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -97,6 +97,7 @@ #include "SIMULATION/TOOLS/sim.h" // for taus #define ASN_MAX_ENCODE_SIZE 4096 +#define NUMBEROF_DRBS_TOBE_ADDED 1 static int encode_CG_ConfigInfo(char *buffer,int buffer_size,rrc_eNB_ue_context_t *const ue_context_pP,int *enc_size); static int is_en_dc_supported(LTE_UE_EUTRA_Capability_t *c); static void free_rb_config(struct NR_RadioBearerConfig *rb_config); @@ -2124,6 +2125,27 @@ rrc_eNB_generate_RRCConnectionReestablishmentReject( PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP), ue_p->Srb0.Tx_buffer.payload_size); } +#ifdef GES_ENDC_SUPPORT +void rrc_generate_SgNBReleaseRequest( + const protocol_ctxt_t *const ctxt_pP, + rrc_eNB_ue_context_t *const ue_context_pP +) +//----------------------------------------------------------------------------- +{ + MessageDef *msg; + msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_RELEASE_REQ); + memset(&(X2AP_ENDC_SGNB_RELEASE_REQ(msg)), 0, sizeof(x2ap_ENDC_sgnb_release_req_t)); + // X2AP_ENDC_SGNB_RELEASE_REQ(msg).MeNB_ue_x2_id = ; + // X2AP_ENDC_SGNB_RELEASE_REQ(msg).SgNB_ue_x2_id = ; + // X2AP_ENDC_SGNB_RELEASE_REQ(msg).cause = ; + // X2AP_ENDC_SGNB_RELEASE_REQ(msg).target_physCellId = ; + LOG_I(RRC, + "[eNB %d] frame %d UE rnti %x transmitting sgnb release request to sgnb \n", + ctxt_pP->module_id,ctxt_pP->frame,ctxt_pP->rnti); + itti_send_msg_to_task(TASK_X2AP, ENB_MODULE_ID_TO_INSTANCE(ctxt_pP->module_id), msg); + return; +} +#endif //----------------------------------------------------------------------------- /* @@ -2144,6 +2166,15 @@ rrc_eNB_generate_RRCConnectionRelease( memset(buffer, 0, RRC_BUF_SIZE); T(T_ENB_RRC_CONNECTION_RELEASE, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame), T_INT(ctxt_pP->subframe), T_INT(ctxt_pP->rnti)); +#ifdef GES_ENDC_SUPPORT + if(ue_context_pP != NULL) + { + if(ue_context_pP->ue_context.Status == RRC_NR_NSA) + { + //rrc_eNB_generate_SgNBReleaseRequest(ctxt_pP,ue_context_pP); + } + } +#endif size = do_RRCConnectionRelease(ctxt_pP->module_id, buffer,rrc_eNB_get_next_transaction_identifier(ctxt_pP->module_id)); ue_context_pP->ue_context.ue_reestablishment_timer = 0; ue_context_pP->ue_context.ue_release_timer = 0; @@ -4344,6 +4375,7 @@ static int encode_CG_ConfigInfo( asn_enc_rval_t enc_rval; int RRC_OK = 1; int index = 0; + char temp_buff[4096]; rb_config = calloc(1,sizeof( struct NR_RadioBearerConfig)); AssertFatal(rb_config != NULL,"failed to allocate memory for rb_config"); @@ -4356,7 +4388,7 @@ static int encode_CG_ConfigInfo( = calloc(ue_context_pP->ue_context.DRB_configList->list.count, sizeof(struct NR_DRB_ToAddMod)); AssertFatal( rb_config->drb_ToAddModList->list.array != NULL, "falied to allocate memory for list.array"); - for(index = 0;index < ue_context_pP->ue_context.DRB_configList->list.count;index++) { + for(index = 0;index < NUMBEROF_DRBS_TOBE_ADDED;index++) { rb_config->drb_ToAddModList->list.array[index] = calloc(1,sizeof(struct NR_DRB_ToAddMod)); AssertFatal(rb_config->drb_ToAddModList->list.array[index] != NULL, @@ -4373,7 +4405,30 @@ static int encode_CG_ConfigInfo( rb_config->drb_ToAddModList->list.array[index]->cnAssociation->choice.eps_BearerIdentity =*(ue_context_pP->ue_context.DRB_configList->list.array[index]->eps_BearerIdentity); } + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config = calloc(1,sizeof(struct NR_PDCP_Config)); + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb = calloc(1,sizeof(struct NR_PDCP_Config__drb)); + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->discardTimer = calloc(1,sizeof(long*)); + *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->discardTimer + = *(ue_context_pP->ue_context.DRB_configList->list.array[index]->pdcp_Config->discardTimer); + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeUL = calloc(1,sizeof(long*)); + *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeUL + = NR_PDCP_Config__drb__pdcp_SN_SizeUL_len18bits; + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeDL = calloc(1,sizeof(long*)); + *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeDL + = NR_PDCP_Config__drb__pdcp_SN_SizeDL_len18bits; + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->headerCompression.present + = NR_PDCP_Config__drb__headerCompression_PR_notUsed; + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->headerCompression.choice.notUsed = 0; + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->t_Reordering = calloc(1,sizeof(long*)); + *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->t_Reordering + = NR_PDCP_Config__t_Reordering_ms0; } + rb_config->securityConfig = calloc(1,sizeof(struct NR_SecurityConfig )); + rb_config->securityConfig->securityAlgorithmConfig = calloc(1,sizeof(struct NR_SecurityAlgorithmConfig)); + rb_config->securityConfig->securityAlgorithmConfig->cipheringAlgorithm = NR_CipheringAlgorithm_nea0; + rb_config->securityConfig->securityAlgorithmConfig->integrityProtAlgorithm = NULL; + rb_config->securityConfig->keyToUse = calloc(1,sizeof(long*)); + *rb_config->securityConfig->keyToUse = NR_SecurityConfig__keyToUse_master; } cg_configinfo = calloc(1,sizeof(struct NR_CG_ConfigInfo)); @@ -4392,7 +4447,17 @@ static int encode_CG_ConfigInfo( cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo = calloc(1,sizeof( OCTET_STRING_t)); AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> - ue_CapabilityInfo != NULL, "failed to allocate memory for ue_capabilityinfo"); + ue_CapabilityInfo != NULL, "failed to allocate memory for ue_capabilityinfo"); +#if 1 + enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,NULL, + (void*)ue_context_pP->ue_context.UE_Capability,temp_buff,4096); + AssertFatal(enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + OCTET_STRING_fromBuf( cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo, + (const char *)temp_buff,(enc_rval.encoded+7)>>3); +#endif + +#if 0 cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->size = ue_context_pP->ue_context.UE_Capability_size; cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf @@ -4401,8 +4466,19 @@ static int encode_CG_ConfigInfo( ue_CapabilityInfo->buf != NULL, "failed to allocate memory for buf"); memcpy(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf, ue_context_pP->ue_context.UE_Capability,ue_context_pP->ue_context.UE_Capability_size); +#endif +#if 1 cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config = calloc(1,sizeof(OCTET_STRING_t)); + AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> + mcg_RB_Config != NULL, "failed to allocate memory for mcg_rb_config"); + enc_rval = uper_encode_to_buffer(&asn_DEF_NR_RadioBearerConfig,NULL,(void *)rb_config,temp_buff,4096); + AssertFatal(enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + OCTET_STRING_fromBuf(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config, + (const char *)temp_buff, (enc_rval.encoded+7)>>3); +#endif +#if 0 AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> mcg_RB_Config != NULL, "failed to allocate memory for mcg_rb_config"); cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->size @@ -4413,8 +4489,9 @@ static int encode_CG_ConfigInfo( mcg_RB_Config->buf != NULL,"failed to allocate memory for buf"); memcpy(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf, rb_config,sizeof(struct NR_RadioBearerConfig)); +#endif // this xer_fprint can be enabled for additional debugging messages - // xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo,(void*)cg_configinfo); + xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo,(void*)cg_configinfo); enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CG_ConfigInfo,NULL,(void*)cg_configinfo, buffer,buffer_size); AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %lu)!\n", diff --git a/openair2/RRC/NR/rrc_gNB.c b/openair2/RRC/NR/rrc_gNB.c index a2e66fa93e..c74846b75a 100644 --- a/openair2/RRC/NR/rrc_gNB.c +++ b/openair2/RRC/NR/rrc_gNB.c @@ -296,11 +296,12 @@ char openair_rrc_gNB_configuration(const module_id_t gnb_mod_idP, gNB_RrcConfigu void rrc_gNB_process_AdditionRequestInformation(const module_id_t gnb_mod_idP, x2ap_ENDC_sgnb_addition_req_t *m) { - LTE_UL_DCCH_Message_t *LTE_UL_DCCH_Message = NULL; + //LTE_UL_DCCH_Message_t *LTE_UL_DCCH_Message = NULL; + struct NR_CG_ConfigInfo *cg_configinfo = NULL; asn_dec_rval_t dec_rval = uper_decode_complete( NULL, - &asn_DEF_LTE_UL_DCCH_Message, - (void **)<E_UL_DCCH_Message, + &asn_DEF_NR_CG_ConfigInfo, + (void **)&cg_configinfo, (uint8_t *)m->rrc_buffer, (int) m->rrc_buffer_size);//m->rrc_buffer_size); @@ -309,13 +310,14 @@ void rrc_gNB_process_AdditionRequestInformation(const module_id_t gnb_mod_idP, x if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { AssertFatal(1==0,"NR_UL_DCCH_MESSAGE decode error\n"); // free the memory - SEQUENCE_free( &asn_DEF_LTE_UL_DCCH_Message, LTE_UL_DCCH_Message, 1 ); + SEQUENCE_free(&asn_DEF_NR_CG_ConfigInfo, cg_configinfo, 1); return; } - xer_fprint(stdout,&asn_DEF_LTE_UL_DCCH_Message, LTE_UL_DCCH_Message); + xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo, cg_configinfo); // recreate enough of X2 EN-DC Container - AssertFatal(LTE_UL_DCCH_Message->message.choice.c1.present == LTE_UL_DCCH_MessageType__c1_PR_ueCapabilityInformation, + AssertFatal(cg_configinfo->criticalExtensions.choice.c1->present == NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo, "ueCapabilityInformation not present\n"); +#if 0 NR_CG_ConfigInfo_t *CG_ConfigInfo = calloc(1,sizeof(*CG_ConfigInfo)); CG_ConfigInfo->criticalExtensions.present = NR_CG_ConfigInfo__criticalExtensions_PR_c1; CG_ConfigInfo->criticalExtensions.choice.c1 = calloc(1,sizeof(*CG_ConfigInfo->criticalExtensions.choice.c1)); @@ -325,11 +327,12 @@ void rrc_gNB_process_AdditionRequestInformation(const module_id_t gnb_mod_idP, x cg_ConfigInfo->ue_CapabilityInfo = calloc(1,sizeof(*cg_ConfigInfo->ue_CapabilityInfo)); asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,NULL,(void*)<E_UL_DCCH_Message->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList,m->rrc_buffer,m->rrc_buffer_size); AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", - enc_rval.failed_type->name, enc_rval.encoded); + enc_rval.failed_type->name, enc_rval.encoded); OCTET_STRING_fromBuf(cg_ConfigInfo->ue_CapabilityInfo, - (const char *)m->rrc_buffer, - (enc_rval.encoded+7)>>3); - parse_CG_ConfigInfo(rrc,CG_ConfigInfo,m); + (const char *)m->rrc_buffer, + (enc_rval.encoded+7)>>3); +#endif + parse_CG_ConfigInfo(rrc,cg_configinfo,m); } diff --git a/openair2/RRC/NR/rrc_gNB_internode.c b/openair2/RRC/NR/rrc_gNB_internode.c index 916f4d63da..5a89f3a979 100644 --- a/openair2/RRC/NR/rrc_gNB_internode.c +++ b/openair2/RRC/NR/rrc_gNB_internode.c @@ -56,7 +56,7 @@ int parse_CG_ConfigInfo(gNB_RRC_INST *rrc, NR_CG_ConfigInfo_t *CG_ConfigInfo, x2 AssertFatal(1==0,"[InterNode] Failed to decode NR_UE_CapabilityRAT_ContainerList (%zu bits), size of OCTET_STRING %lu\n", dec_rval.consumed, cg_ConfigInfo->ue_CapabilityInfo->size); } - rrc_parse_ue_capabilities(rrc,UE_CapabilityRAT_ContainerList, m); + rrc_parse_ue_capabilities(rrc,UE_CapabilityRAT_ContainerList, m,cg_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo); } if (cg_ConfigInfo->candidateCellInfoListMN) AssertFatal(1==0,"Can't handle candidateCellInfoListMN yet\n"); } diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c index 18ebfebf8d..969588d0c4 100644 --- a/openair2/RRC/NR/rrc_gNB_nsa.c +++ b/openair2/RRC/NR/rrc_gNB_nsa.c @@ -39,7 +39,7 @@ #include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h" #include "openair2/RRC/LTE/rrc_eNB_GTPV1U.h" -void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList, x2ap_ENDC_sgnb_addition_req_t *m) { +void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList, x2ap_ENDC_sgnb_addition_req_t *m, struct NR_CG_ConfigInfo_IEs * cg_config_info) { struct rrc_gNB_ue_context_s *ue_context_p = NULL; OCTET_STRING_t *ueCapabilityRAT_Container_nr = NULL; @@ -98,10 +98,10 @@ void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_Container xer_fprint(stdout, &asn_DEF_NR_UE_MRDC_Capability, ue_context_p->ue_context.UE_Capability_MRDC); } - rrc_add_nsa_user(rrc,ue_context_p, m); + rrc_add_nsa_user(rrc,ue_context_p, m, cg_config_info); } -void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p, x2ap_ENDC_sgnb_addition_req_t *m) { +void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p, x2ap_ENDC_sgnb_addition_req_t *m, struct NR_CG_ConfigInfo_IEs * cg_config_info) { // generate nr-Config-r15 containers for LTE RRC : inside message for X2 EN-DC (CG-Config Message from 38.331) @@ -133,7 +133,7 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_ ue_context_p->ue_context.rb_config = calloc(1,sizeof(NR_RRCReconfiguration_t)); - fill_default_rbconfig(ue_context_p->ue_context.rb_config); + fill_default_rbconfig(ue_context_p->ue_context.rb_config,m, cg_config_info); ue_context_p->ue_id_rnti = ue_context_p->ue_context.secondaryCellGroup->spCellConfig->reconfigurationWithSync->newUE_Identity; NR_CG_Config_t *CG_Config = calloc(1,sizeof(*CG_Config)); memset((void*)CG_Config,0,sizeof(*CG_Config)); diff --git a/openair2/RRC/NR/rrc_gNB_reconfig.c b/openair2/RRC/NR/rrc_gNB_reconfig.c index 03c5e6ec95..dc25e8ee72 100644 --- a/openair2/RRC/NR/rrc_gNB_reconfig.c +++ b/openair2/RRC/NR/rrc_gNB_reconfig.c @@ -2032,8 +2032,20 @@ void fill_default_reconfig(NR_ServingCellConfigCommon_t *servingcellconfigcommon reconfig->nonCriticalExtension = NULL; } -void fill_default_rbconfig(NR_RadioBearerConfig_t *rbconfig) { +void fill_default_rbconfig(NR_RadioBearerConfig_t *rbconfig, x2ap_ENDC_sgnb_addition_req_t *m, struct NR_CG_ConfigInfo_IEs *cg_config_info) { + if(cg_config_info->mcg_RB_Config) { + asn_dec_rval dec_rval = uper_decode(NULL, + &asn_DEF_NR_RadioBearerConfig, + (void**)&rbconfig, + cg_config_info->mcg_RB_Config->buf, + cg_ConfigInfo->mcg_RB_Config->size, 0, 0); + if((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + AssertFatal(1==0,"[InterNode] Failed to decode mcg_rb_config (%zu bits), size of OCTET_STRING %lu\n", + dec_rval.consumed, cg_ConfigInfo->ue_CapabilityInfo->size); + } + } + #if 0 rbconfig->srb_ToAddModList = NULL; rbconfig->srb3_ToRelease = NULL; rbconfig->drb_ToAddModList = calloc(1,sizeof(*rbconfig->drb_ToAddModList)); @@ -2074,6 +2086,7 @@ void fill_default_rbconfig(NR_RadioBearerConfig_t *rbconfig) { rbconfig->securityConfig->securityAlgorithmConfig->integrityProtAlgorithm=NULL; rbconfig->securityConfig->keyToUse = calloc(1,sizeof(*rbconfig->securityConfig->keyToUse)); *rbconfig->securityConfig->keyToUse = NR_SecurityConfig__keyToUse_master; +#endif xer_fprint(stdout, &asn_DEF_NR_RadioBearerConfig, (const void*)rbconfig); } From 2f48b925012286c93c9f3423d36ef862a003d950 Mon Sep 17 00:00:00 2001 From: "s.rampalli" Date: Thu, 14 May 2020 15:36:45 +0530 Subject: [PATCH 292/553] compilation done need to verify with GES endc setup --- openair2/RRC/LTE/rrc_eNB.c | 11 +++++++---- openair2/RRC/NR/nr_rrc_proto.h | 2 +- openair2/RRC/NR/rrc_gNB_internode.c | 2 +- openair2/RRC/NR/rrc_gNB_nsa.c | 25 +++++++++++++++++++------ openair2/RRC/NR/rrc_gNB_reconfig.c | 6 +++++- 5 files changed, 33 insertions(+), 13 deletions(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index a2e998535e..1e6610c22a 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -2126,6 +2126,7 @@ rrc_eNB_generate_RRCConnectionReestablishmentReject( ue_p->Srb0.Tx_buffer.payload_size); } #ifdef GES_ENDC_SUPPORT +#if 0 void rrc_generate_SgNBReleaseRequest( const protocol_ctxt_t *const ctxt_pP, rrc_eNB_ue_context_t *const ue_context_pP @@ -2146,7 +2147,7 @@ void rrc_generate_SgNBReleaseRequest( return; } #endif - +#endif //----------------------------------------------------------------------------- /* * Generate the RRC Connection Release to UE. @@ -2167,6 +2168,7 @@ rrc_eNB_generate_RRCConnectionRelease( T(T_ENB_RRC_CONNECTION_RELEASE, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame), T_INT(ctxt_pP->subframe), T_INT(ctxt_pP->rnti)); #ifdef GES_ENDC_SUPPORT +#if 0 if(ue_context_pP != NULL) { if(ue_context_pP->ue_context.Status == RRC_NR_NSA) @@ -2174,6 +2176,7 @@ rrc_eNB_generate_RRCConnectionRelease( //rrc_eNB_generate_SgNBReleaseRequest(ctxt_pP,ue_context_pP); } } +#endif #endif size = do_RRCConnectionRelease(ctxt_pP->module_id, buffer,rrc_eNB_get_next_transaction_identifier(ctxt_pP->module_id)); ue_context_pP->ue_context.ue_reestablishment_timer = 0; @@ -4375,7 +4378,7 @@ static int encode_CG_ConfigInfo( asn_enc_rval_t enc_rval; int RRC_OK = 1; int index = 0; - char temp_buff[4096]; + char temp_buff[ASN_MAX_ENCODE_SIZE]; rb_config = calloc(1,sizeof( struct NR_RadioBearerConfig)); AssertFatal(rb_config != NULL,"failed to allocate memory for rb_config"); @@ -4450,7 +4453,7 @@ static int encode_CG_ConfigInfo( ue_CapabilityInfo != NULL, "failed to allocate memory for ue_capabilityinfo"); #if 1 enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,NULL, - (void*)ue_context_pP->ue_context.UE_Capability,temp_buff,4096); + (void*)ue_context_pP->ue_context.UE_Capability,temp_buff,ASN_MAX_ENCODE_SIZE); AssertFatal(enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", enc_rval.failed_type->name, enc_rval.encoded); OCTET_STRING_fromBuf( cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo, @@ -4472,7 +4475,7 @@ static int encode_CG_ConfigInfo( = calloc(1,sizeof(OCTET_STRING_t)); AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> mcg_RB_Config != NULL, "failed to allocate memory for mcg_rb_config"); - enc_rval = uper_encode_to_buffer(&asn_DEF_NR_RadioBearerConfig,NULL,(void *)rb_config,temp_buff,4096); + enc_rval = uper_encode_to_buffer(&asn_DEF_NR_RadioBearerConfig,NULL,(void *)rb_config,temp_buff,ASN_MAX_ENCODE_SIZE); AssertFatal(enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", enc_rval.failed_type->name, enc_rval.encoded); OCTET_STRING_fromBuf(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config, diff --git a/openair2/RRC/NR/nr_rrc_proto.h b/openair2/RRC/NR/nr_rrc_proto.h index fd766f7e12..317282c814 100644 --- a/openair2/RRC/NR/nr_rrc_proto.h +++ b/openair2/RRC/NR/nr_rrc_proto.h @@ -65,7 +65,7 @@ void rrc_gNB_generate_SgNBAdditionRequestAcknowledge( struct rrc_gNB_ue_context_s *rrc_gNB_allocate_new_UE_context(gNB_RRC_INST *rrc_instance_pP); -void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc,LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList, x2ap_ENDC_sgnb_addition_req_t *m); +void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc,LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList, x2ap_ENDC_sgnb_addition_req_t *m, NR_CG_ConfigInfo_IEs_t * cg_config_info); void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p, x2ap_ENDC_sgnb_addition_req_t *m); diff --git a/openair2/RRC/NR/rrc_gNB_internode.c b/openair2/RRC/NR/rrc_gNB_internode.c index 5a89f3a979..092c63f96e 100644 --- a/openair2/RRC/NR/rrc_gNB_internode.c +++ b/openair2/RRC/NR/rrc_gNB_internode.c @@ -56,7 +56,7 @@ int parse_CG_ConfigInfo(gNB_RRC_INST *rrc, NR_CG_ConfigInfo_t *CG_ConfigInfo, x2 AssertFatal(1==0,"[InterNode] Failed to decode NR_UE_CapabilityRAT_ContainerList (%zu bits), size of OCTET_STRING %lu\n", dec_rval.consumed, cg_ConfigInfo->ue_CapabilityInfo->size); } - rrc_parse_ue_capabilities(rrc,UE_CapabilityRAT_ContainerList, m,cg_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo); + rrc_parse_ue_capabilities(rrc,UE_CapabilityRAT_ContainerList, m,cg_ConfigInfo); } if (cg_ConfigInfo->candidateCellInfoListMN) AssertFatal(1==0,"Can't handle candidateCellInfoListMN yet\n"); } diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c index 969588d0c4..9232b4d4be 100644 --- a/openair2/RRC/NR/rrc_gNB_nsa.c +++ b/openair2/RRC/NR/rrc_gNB_nsa.c @@ -39,7 +39,7 @@ #include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h" #include "openair2/RRC/LTE/rrc_eNB_GTPV1U.h" -void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList, x2ap_ENDC_sgnb_addition_req_t *m, struct NR_CG_ConfigInfo_IEs * cg_config_info) { +void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList, x2ap_ENDC_sgnb_addition_req_t *m, NR_CG_ConfigInfo_IEs_t *cg_config_info) { struct rrc_gNB_ue_context_s *ue_context_p = NULL; OCTET_STRING_t *ueCapabilityRAT_Container_nr = NULL; @@ -96,12 +96,25 @@ void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_Container if ( LOG_DEBUGFLAG(DEBUG_ASN1 && ueCapabilityRAT_Container_MRDC != NULL) ) { xer_fprint(stdout, &asn_DEF_NR_UE_MRDC_Capability, ue_context_p->ue_context.UE_Capability_MRDC); - } - - rrc_add_nsa_user(rrc,ue_context_p, m, cg_config_info); + } + + if(cg_config_info->mcg_RB_Config) { + asn_dec_rval_t dec_rval = uper_decode(NULL, + &asn_DEF_NR_RadioBearerConfig, + (void**)&ue_context_p->ue_context.rb_config, + cg_config_info->mcg_RB_Config->buf, + cg_config_info->mcg_RB_Config->size, 0, 0); + + if((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + AssertFatal(1==0,"[InterNode] Failed to decode mcg_rb_config (%zu bits), size of OCTET_STRING %lu\n", + dec_rval.consumed, cg_config_info->mcg_RB_Config->size); + } + } + xer_fprint(stdout, &asn_DEF_NR_RadioBearerConfig, (const void*)ue_context_p->ue_context.rb_config); + rrc_add_nsa_user(rrc,ue_context_p, m); } -void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p, x2ap_ENDC_sgnb_addition_req_t *m, struct NR_CG_ConfigInfo_IEs * cg_config_info) { +void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p, x2ap_ENDC_sgnb_addition_req_t *m) { // generate nr-Config-r15 containers for LTE RRC : inside message for X2 EN-DC (CG-Config Message from 38.331) @@ -133,7 +146,7 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_ ue_context_p->ue_context.rb_config = calloc(1,sizeof(NR_RRCReconfiguration_t)); - fill_default_rbconfig(ue_context_p->ue_context.rb_config,m, cg_config_info); + //fill_default_rbconfig(ue_context_p->ue_context.rb_config,m, cg_config_info); ue_context_p->ue_id_rnti = ue_context_p->ue_context.secondaryCellGroup->spCellConfig->reconfigurationWithSync->newUE_Identity; NR_CG_Config_t *CG_Config = calloc(1,sizeof(*CG_Config)); memset((void*)CG_Config,0,sizeof(*CG_Config)); diff --git a/openair2/RRC/NR/rrc_gNB_reconfig.c b/openair2/RRC/NR/rrc_gNB_reconfig.c index dc25e8ee72..fd8f93462f 100644 --- a/openair2/RRC/NR/rrc_gNB_reconfig.c +++ b/openair2/RRC/NR/rrc_gNB_reconfig.c @@ -2031,8 +2031,9 @@ void fill_default_reconfig(NR_ServingCellConfigCommon_t *servingcellconfigcommon // nonCriticalExtension reconfig->nonCriticalExtension = NULL; } - +#if 0 void fill_default_rbconfig(NR_RadioBearerConfig_t *rbconfig, x2ap_ENDC_sgnb_addition_req_t *m, struct NR_CG_ConfigInfo_IEs *cg_config_info) { +/* if(cg_config_info->mcg_RB_Config) { asn_dec_rval dec_rval = uper_decode(NULL, &asn_DEF_NR_RadioBearerConfig, @@ -2045,6 +2046,8 @@ void fill_default_rbconfig(NR_RadioBearerConfig_t *rbconfig, x2ap_ENDC_sgnb_addi dec_rval.consumed, cg_ConfigInfo->ue_CapabilityInfo->size); } } + */ + #if 0 rbconfig->srb_ToAddModList = NULL; rbconfig->srb3_ToRelease = NULL; @@ -2091,3 +2094,4 @@ void fill_default_rbconfig(NR_RadioBearerConfig_t *rbconfig, x2ap_ENDC_sgnb_addi xer_fprint(stdout, &asn_DEF_NR_RadioBearerConfig, (const void*)rbconfig); } #endif +#endif From defea03ab98c89db67c23dfcd226589b19db3373 Mon Sep 17 00:00:00 2001 From: "s.rampalli" Date: Wed, 20 May 2020 15:26:37 +0530 Subject: [PATCH 293/553] Required changes/modifications are done at both eNB and gNB side --- openair2/RRC/LTE/rrc_defs.h | 10 +- openair2/RRC/LTE/rrc_eNB.c | 852 +++---- openair2/RRC/NR/rrc_gNB.c | 142 +- openair2/RRC/NR/rrc_gNB_internode.c | 80 +- openair2/RRC/NR/rrc_gNB_nsa.c | 238 +- openair2/RRC/NR/rrc_gNB_reconfig.c | 3616 +++++++++++++-------------- 6 files changed, 2362 insertions(+), 2576 deletions(-) diff --git a/openair2/RRC/LTE/rrc_defs.h b/openair2/RRC/LTE/rrc_defs.h index 52b06b9f11..42fa5f6de1 100644 --- a/openair2/RRC/LTE/rrc_defs.h +++ b/openair2/RRC/LTE/rrc_defs.h @@ -40,6 +40,10 @@ #include "rrc_types.h" //#include "PHY/phy_defs.h" #include "LAYER2/RLC/rlc.h" +#include "RRC/NR/nr_rrc_types.h" +#include "NR_UE-MRDC-Capability.h" +#include "NR_UE-NR-Capability.h" + #include "COMMON/platform_constants.h" #include "COMMON/platform_types.h" @@ -569,6 +573,10 @@ typedef struct eNB_RRC_UE_s { LTE_UE_EUTRA_Capability_t *UE_Capability; int UE_Capability_size; + NR_UE_MRDC_Capability_t *UE_Capability_MRDC; + int UE_MRDC_Capability_size; + NR_UE_NR_Capability_t *UE_Capability_nr; + int UE_NR_Capability_size; ImsiMobileIdentity_t imsi; /* KeNB as derived from KASME received from EPC */ @@ -614,7 +622,7 @@ typedef struct eNB_RRC_UE_s { /* Number of e_rab to be modified in the list */ uint8_t nb_of_modify_e_rabs; uint8_t nb_of_failed_e_rabs; - uint8_t nb_of_modify_endc_e_rabs; + uint8_t nb_of_modify_endc_e_rabs; e_rab_param_t modify_e_rab[NB_RB_MAX];//[S1AP_MAX_E_RAB]; /* list of e_rab to be setup by RRC layers */ e_rab_param_t e_rab[NB_RB_MAX];//[S1AP_MAX_E_RAB]; diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index 1e6610c22a..75ed1873f5 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -100,8 +100,6 @@ #define NUMBEROF_DRBS_TOBE_ADDED 1 static int encode_CG_ConfigInfo(char *buffer,int buffer_size,rrc_eNB_ue_context_t *const ue_context_pP,int *enc_size); static int is_en_dc_supported(LTE_UE_EUTRA_Capability_t *c); -static void free_rb_config(struct NR_RadioBearerConfig *rb_config); -static void free_cg_configinfo(struct NR_CG_ConfigInfo *cg_configinfo); extern RAN_CONTEXT_t RC; @@ -119,8 +117,9 @@ extern uint32_t to_earfcn_DL(int eutra_bandP, uint32_t dl_CarrierFreq, uint32_t extern int rrc_eNB_process_security(const protocol_ctxt_t *const ctxt_pP, rrc_eNB_ue_context_t *const ue_context_pP, security_capabilities_t *security_capabilities_pP); extern void process_eNB_security_key (const protocol_ctxt_t *const ctxt_pP, rrc_eNB_ue_context_t *const ue_context_pP, uint8_t *security_key_pP); extern int derive_keNB_star(const uint8_t *kenb_32, const uint16_t pci, const uint32_t earfcn_dl, const bool is_rel8_only, uint8_t *kenb_star); -extern int rrc_eNB_generate_RRCConnectionReconfiguration_endc(protocol_ctxt_t *ctxt, rrc_eNB_ue_context_t *ue_context, unsigned char *buffer, int buffer_size, OCTET_STRING_t *scg_group_config, OCTET_STRING_t *scg_RB_config); -extern struct rrc_eNB_ue_context_s * get_first_ue_context(eNB_RRC_INST *rrc_instance_pP); +extern int rrc_eNB_generate_RRCConnectionReconfiguration_endc(protocol_ctxt_t *ctxt, rrc_eNB_ue_context_t *ue_context, unsigned char *buffer, int buffer_size, OCTET_STRING_t *scg_group_config, + OCTET_STRING_t *scg_RB_config); +extern struct rrc_eNB_ue_context_s *get_first_ue_context(eNB_RRC_INST *rrc_instance_pP); pthread_mutex_t rrc_release_freelist; RRC_release_list_t rrc_release_info; @@ -168,7 +167,7 @@ init_SI( AssertFatal(RC.rrc[ctxt_pP->module_id]->carrier[CC_id].SIB1_MBMS!=NULL,PROTOCOL_RRC_CTXT_FMT" init_SI: FATAL, no memory for SIB1_MBMS allocated\n", PROTOCOL_RRC_CTXT_ARGS(ctxt_pP)); RC.rrc[ctxt_pP->module_id]->carrier[CC_id].sizeof_SIB1_MBMS = do_SIB1_MBMS(&RC.rrc[ctxt_pP->module_id]->carrier[CC_id],ctxt_pP->module_id,CC_id, - configuration + configuration ); LOG_I(RRC, PROTOCOL_RRC_CTXT_FMT" Contents of SIB1-MBMS\n", PROTOCOL_RRC_CTXT_ARGS(ctxt_pP) @@ -2128,7 +2127,7 @@ rrc_eNB_generate_RRCConnectionReestablishmentReject( #ifdef GES_ENDC_SUPPORT #if 0 void rrc_generate_SgNBReleaseRequest( - const protocol_ctxt_t *const ctxt_pP, + const protocol_ctxt_t *const ctxt_pP, rrc_eNB_ue_context_t *const ue_context_pP ) //----------------------------------------------------------------------------- @@ -2136,13 +2135,13 @@ void rrc_generate_SgNBReleaseRequest( MessageDef *msg; msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_RELEASE_REQ); memset(&(X2AP_ENDC_SGNB_RELEASE_REQ(msg)), 0, sizeof(x2ap_ENDC_sgnb_release_req_t)); - // X2AP_ENDC_SGNB_RELEASE_REQ(msg).MeNB_ue_x2_id = ; - // X2AP_ENDC_SGNB_RELEASE_REQ(msg).SgNB_ue_x2_id = ; - // X2AP_ENDC_SGNB_RELEASE_REQ(msg).cause = ; - // X2AP_ENDC_SGNB_RELEASE_REQ(msg).target_physCellId = ; + // X2AP_ENDC_SGNB_RELEASE_REQ(msg).MeNB_ue_x2_id = ; + // X2AP_ENDC_SGNB_RELEASE_REQ(msg).SgNB_ue_x2_id = ; + // X2AP_ENDC_SGNB_RELEASE_REQ(msg).cause = ; + // X2AP_ENDC_SGNB_RELEASE_REQ(msg).target_physCellId = ; LOG_I(RRC, - "[eNB %d] frame %d UE rnti %x transmitting sgnb release request to sgnb \n", - ctxt_pP->module_id,ctxt_pP->frame,ctxt_pP->rnti); + "[eNB %d] frame %d UE rnti %x transmitting sgnb release request to sgnb \n", + ctxt_pP->module_id,ctxt_pP->frame,ctxt_pP->rnti); itti_send_msg_to_task(TASK_X2AP, ENB_MODULE_ID_TO_INSTANCE(ctxt_pP->module_id), msg); return; } @@ -2169,13 +2168,13 @@ rrc_eNB_generate_RRCConnectionRelease( T_INT(ctxt_pP->subframe), T_INT(ctxt_pP->rnti)); #ifdef GES_ENDC_SUPPORT #if 0 - if(ue_context_pP != NULL) - { - if(ue_context_pP->ue_context.Status == RRC_NR_NSA) - { - //rrc_eNB_generate_SgNBReleaseRequest(ctxt_pP,ue_context_pP); - } + + if(ue_context_pP != NULL) { + if(ue_context_pP->ue_context.Status == RRC_NR_NSA) { + //rrc_eNB_generate_SgNBReleaseRequest(ctxt_pP,ue_context_pP); + } } + #endif #endif size = do_RRCConnectionRelease(ctxt_pP->module_id, buffer,rrc_eNB_get_next_transaction_identifier(ctxt_pP->module_id)); @@ -2876,7 +2875,6 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t uint16_t size; int i; MessageDef *message_p = NULL; - /* Configure SRB1/SRB2, PhysicalConfigDedicated, LTE_MAC_MainConfig for UE */ eNB_RRC_INST *rrc_inst = RC.rrc[ctxt_pP->module_id]; struct LTE_PhysicalConfigDedicated **physicalConfigDedicated = &ue_context_pP->ue_context.physicalConfigDedicated; @@ -3068,7 +3066,7 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t module_id_t module_id = ctxt_pP->module_id; LOG_D(RRC, "Processing the DRX configuration in RRC Connection Reconfiguration\n"); - /* Process the IE drx_Config */ + /* Process the IE drx_Config */ if (NODE_IS_MONOLITHIC(rrc_inst->node_type)) { mac_MainConfig->drx_Config = do_DrxConfig(cc_id, &rrc_inst->configuration, UEcap); // drx_Config IE @@ -3083,8 +3081,8 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t LOG_D(RRC, "DRX configured in MAC Main Configuration for RRC Connection Reconfiguration\n"); } } - /* End of CDRX configuration */ + /* End of CDRX configuration */ sr_ProhibitTimer_r9 = CALLOC(1, sizeof(long)); *sr_ProhibitTimer_r9 = 0; // SR tx on PUCCH, Value in number of SR period(s). Value 0 = no timer for SR, Value 2 = 2*SR mac_MainConfig->ext1 = CALLOC(1, sizeof(struct LTE_MAC_MainConfig__ext1)); @@ -3192,7 +3190,9 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t if (ue_context_pP->ue_context.does_nr) { MeasId6 = calloc(1, sizeof(LTE_MeasIdToAddMod_t)); + if (MeasId6 == NULL) exit(1); + MeasId6->measId = 7; MeasId6->measObjectId = 2; MeasId6->reportConfigId = 7; @@ -3250,22 +3250,28 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t if (ue_context_pP->ue_context.does_nr) { MeasObj2 = calloc(1, sizeof(LTE_MeasObjectToAddMod_t)); + if (MeasObj2 == NULL) exit(1); + MeasObj2->measObjectId = 2; MeasObj2->measObject.present = LTE_MeasObjectToAddMod__measObject_PR_measObjectNR_r15; - MeasObj2->measObject.choice.measObjectNR_r15.carrierFreq_r15 = 642256; //634000; //(634000 = 3.51GHz) (640000 = 3.6GHz) (641272 = 3619.08MHz = 3600 + 30/1000*106*12/2) (642256 is for 3.6GHz and absoluteFrequencySSB = 642016) + MeasObj2->measObject.choice.measObjectNR_r15.carrierFreq_r15 = + 642256; //634000; //(634000 = 3.51GHz) (640000 = 3.6GHz) (641272 = 3619.08MHz = 3600 + 30/1000*106*12/2) (642256 is for 3.6GHz and absoluteFrequencySSB = 642016) MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.periodicityAndOffset_r15.present = LTE_MTC_SSB_NR_r15__periodicityAndOffset_r15_PR_sf20_r15; MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.periodicityAndOffset_r15.choice.sf20_r15 = 0; MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.ssb_Duration_r15 = LTE_MTC_SSB_NR_r15__ssb_Duration_r15_sf4; MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.subcarrierSpacingSSB_r15 = LTE_RS_ConfigSSB_NR_r15__subcarrierSpacingSSB_r15_kHz30; MeasObj2->measObject.choice.measObjectNR_r15.quantityConfigSet_r15 = 1; MeasObj2->measObject.choice.measObjectNR_r15.ext1 = calloc(1, sizeof(struct LTE_MeasObjectNR_r15__ext1)); + if (MeasObj2->measObject.choice.measObjectNR_r15.ext1 == NULL) exit(1); + MeasObj2->measObject.choice.measObjectNR_r15.ext1->bandNR_r15 = calloc(1, sizeof(struct LTE_MeasObjectNR_r15__ext1__bandNR_r15)); + if (MeasObj2->measObject.choice.measObjectNR_r15.ext1->bandNR_r15 == NULL) exit(1); + MeasObj2->measObject.choice.measObjectNR_r15.ext1->bandNR_r15->present = LTE_MeasObjectNR_r15__ext1__bandNR_r15_PR_setup; MeasObj2->measObject.choice.measObjectNR_r15.ext1->bandNR_r15->choice.setup = 78; - ASN_SEQUENCE_ADD(&MeasObj_list->list, MeasObj2); } @@ -3281,9 +3287,11 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t ReportConfig_A3 = CALLOC(1, sizeof(*ReportConfig_A3)); ReportConfig_A4 = CALLOC(1, sizeof(*ReportConfig_A4)); ReportConfig_A5 = CALLOC(1, sizeof(*ReportConfig_A5)); + if (ue_context_pP->ue_context.does_nr) { ReportConfig_NR = CALLOC(1, sizeof(*ReportConfig_NR)); } + ReportConfig_per->reportConfigId = 1; ReportConfig_per->reportConfig.present = LTE_ReportConfigToAddMod__reportConfig_PR_reportConfigEUTRA; ReportConfig_per->reportConfig.choice.reportConfigEUTRA.triggerType.present = @@ -3404,9 +3412,13 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.reportInterval = LTE_ReportInterval_ms120; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.reportAmount = LTE_ReportConfigInterRAT__reportAmount_infinity; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7 = calloc(1, sizeof(struct LTE_ReportConfigInterRAT__ext7)); + if (ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7 == NULL) exit(1); + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15 = calloc(1, sizeof(struct LTE_ReportQuantityNR_r15)); + if (ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15 == NULL) exit(1); + ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15->ss_rsrp = TRUE; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15->ss_rsrq = TRUE; ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15->ss_sinr = TRUE; @@ -3608,7 +3620,6 @@ flexran_rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt uint16_t size; int i; MessageDef *message_p = NULL; - /* Configure SRB1/SRB2, PhysicalConfigDedicated, LTE_MAC_MainConfig for UE */ eNB_RRC_INST *rrc_inst = RC.rrc[ctxt_pP->module_id]; struct LTE_PhysicalConfigDedicated **physicalConfigDedicated = &ue_context_pP->ue_context.physicalConfigDedicated; @@ -3654,7 +3665,6 @@ flexran_rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt LTE_C_RNTI_t *cba_RNTI = NULL; int measurements_enabled; uint8_t xid = rrc_eNB_get_next_transaction_identifier(ctxt_pP->module_id); //Transaction_id, - #ifdef CBA // Contention Based Access uint8_t *cba_RNTI_buf; cba_RNTI = CALLOC(1, sizeof(LTE_C_RNTI_t)); @@ -3680,8 +3690,8 @@ flexran_rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt frameP, ue_mod_idP); } -#endif +#endif T(T_ENB_RRC_CONNECTION_RECONFIGURATION, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame), @@ -3816,7 +3826,6 @@ flexran_rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt mac_MainConfig->phr_Config->choice.setup.prohibitPHR_Timer = LTE_MAC_MainConfig__phr_Config__setup__prohibitPHR_Timer_sf200; // sf20 = 20 subframes // LTE_MAC_MainConfig__phr_Config__setup__prohibitPHR_Timer_sf1000 mac_MainConfig->phr_Config->choice.setup.dl_PathlossChange = LTE_MAC_MainConfig__phr_Config__setup__dl_PathlossChange_dB3; // Value dB1 =1 dB, dB3 = 3 dB - /* CDRX Configuration */ mac_MainConfig->drx_Config = NULL; rnti_t rnti = ue_context_pP->ue_id_rnti; @@ -3824,11 +3833,11 @@ flexran_rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt uint8_t cc_id = ue_context_pP->ue_context.primaryCC_id; LTE_UE_EUTRA_Capability_t *UEcap = ue_context_pP->ue_context.UE_Capability; LOG_D(RRC, "Processing the DRX configuration in RRC Connection Reconfiguration\n"); - + /* Process the IE drx_Config */ if (NODE_IS_MONOLITHIC(rrc_inst->node_type)) { mac_MainConfig->drx_Config = do_DrxConfig(cc_id, &rrc_inst->configuration, UEcap); // drx_Config IE - + if (mac_MainConfig->drx_Config == NULL) { LOG_W(RRC, "drx_Configuration parameter is NULL, cannot configure local UE parameters or CDRX is deactivated\n"); } else { @@ -3840,8 +3849,8 @@ flexran_rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt LOG_D(RRC, "DRX configured in MAC Main Configuration for RRC Connection Reconfiguration\n"); } } - /* End of CDRX configuration */ + /* End of CDRX configuration */ sr_ProhibitTimer_r9 = CALLOC(1, sizeof(long)); *sr_ProhibitTimer_r9 = 0; // SR tx on PUCCH, Value in number of SR period(s). Value 0 = no timer for SR, Value 2 = 2*SR mac_MainConfig->ext1 = CALLOC(1, sizeof(struct LTE_MAC_MainConfig__ext1)); @@ -4360,12 +4369,12 @@ rrc_eNB_generate_RRCConnectionReconfiguration_SCell( //----------------------------------------------------------------------------- -/** - * @fn :encode_CG_ConfigInfo - * @param :enc_buf to store the encoded bits +/** + * @fn :encode_CG_ConfigInfo + * @param :enc_buf to store the encoded bits * @param :ue_context_pP ue context used to fill CG-ConfigInfo * @param :enc_size to store thre size of encoded size - * this api is to fill and encode CG-ConfigInfo + * this api is to fill and encode CG-ConfigInfo */ static int encode_CG_ConfigInfo( char *buffer, @@ -4379,212 +4388,158 @@ static int encode_CG_ConfigInfo( int RRC_OK = 1; int index = 0; char temp_buff[ASN_MAX_ENCODE_SIZE]; - - rb_config = calloc(1,sizeof( struct NR_RadioBearerConfig)); + LTE_UE_CapabilityRAT_ContainerList_t *ue_cap_rat_container_list = NULL; + LTE_UE_CapabilityRAT_Container_t ue_cap_rat_container_MRDC; + LTE_UE_CapabilityRAT_Container_t ue_cap_rat_container_nr; + int RAT_Container_count = 0; + rb_config = calloc(1,sizeof(struct NR_RadioBearerConfig)); AssertFatal(rb_config != NULL,"failed to allocate memory for rb_config"); if(ue_context_pP->ue_context.DRB_configList->list.count != 0) { rb_config->drb_ToAddModList = calloc(1,sizeof(struct NR_DRB_ToAddModList )); - AssertFatal(rb_config->drb_ToAddModList != NULL,"failed to allocated memory for drbtoaddmodlist"); - rb_config->drb_ToAddModList->list.count = ue_context_pP->ue_context.DRB_configList->list.count; - rb_config->drb_ToAddModList->list.array - = calloc(ue_context_pP->ue_context.DRB_configList->list.count, sizeof(struct NR_DRB_ToAddMod)); - AssertFatal( rb_config->drb_ToAddModList->list.array != NULL, - "falied to allocate memory for list.array"); - for(index = 0;index < NUMBEROF_DRBS_TOBE_ADDED;index++) { - rb_config->drb_ToAddModList->list.array[index] - = calloc(1,sizeof(struct NR_DRB_ToAddMod)); - AssertFatal(rb_config->drb_ToAddModList->list.array[index] != NULL, - "failed to allocate memory for drb_toaddmod"); - rb_config->drb_ToAddModList->list.array[index]->drb_Identity - =ue_context_pP->ue_context.DRB_configList->list.array[index]->drb_Identity; - if(ue_context_pP->ue_context.DRB_configList->list.array[index]->eps_BearerIdentity) { - rb_config->drb_ToAddModList->list.array[index]->cnAssociation - =calloc(1,sizeof(struct NR_DRB_ToAddMod__cnAssociation)); - AssertFatal(rb_config->drb_ToAddModList->list.array[index]->cnAssociation != NULL, - "failed to allocate memory cnAssociation"); - rb_config->drb_ToAddModList->list.array[index]->cnAssociation->present - =NR_DRB_ToAddMod__cnAssociation_PR_eps_BearerIdentity; - rb_config->drb_ToAddModList->list.array[index]->cnAssociation->choice.eps_BearerIdentity - =*(ue_context_pP->ue_context.DRB_configList->list.array[index]->eps_BearerIdentity); - } - rb_config->drb_ToAddModList->list.array[index]->pdcp_Config = calloc(1,sizeof(struct NR_PDCP_Config)); - rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb = calloc(1,sizeof(struct NR_PDCP_Config__drb)); - rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->discardTimer = calloc(1,sizeof(long*)); - *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->discardTimer - = *(ue_context_pP->ue_context.DRB_configList->list.array[index]->pdcp_Config->discardTimer); - rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeUL = calloc(1,sizeof(long*)); - *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeUL - = NR_PDCP_Config__drb__pdcp_SN_SizeUL_len18bits; - rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeDL = calloc(1,sizeof(long*)); - *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeDL - = NR_PDCP_Config__drb__pdcp_SN_SizeDL_len18bits; - rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->headerCompression.present - = NR_PDCP_Config__drb__headerCompression_PR_notUsed; - rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->headerCompression.choice.notUsed = 0; - rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->t_Reordering = calloc(1,sizeof(long*)); - *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->t_Reordering - = NR_PDCP_Config__t_Reordering_ms0; - } - rb_config->securityConfig = calloc(1,sizeof(struct NR_SecurityConfig )); - rb_config->securityConfig->securityAlgorithmConfig = calloc(1,sizeof(struct NR_SecurityAlgorithmConfig)); - rb_config->securityConfig->securityAlgorithmConfig->cipheringAlgorithm = NR_CipheringAlgorithm_nea0; - rb_config->securityConfig->securityAlgorithmConfig->integrityProtAlgorithm = NULL; - rb_config->securityConfig->keyToUse = calloc(1,sizeof(long*)); - *rb_config->securityConfig->keyToUse = NR_SecurityConfig__keyToUse_master; + AssertFatal(rb_config->drb_ToAddModList != NULL,"failed to allocated memory for drbtoaddmodlist"); + rb_config->drb_ToAddModList->list.count = NUMBEROF_DRBS_TOBE_ADDED; + rb_config->drb_ToAddModList->list.array + = calloc(NUMBEROF_DRBS_TOBE_ADDED, sizeof(struct NR_DRB_ToAddMod *)); + AssertFatal( rb_config->drb_ToAddModList->list.array != NULL, + "falied to allocate memory for list.array"); + + for(index = 0; index < NUMBEROF_DRBS_TOBE_ADDED; index++) { + rb_config->drb_ToAddModList->list.array[index] + = calloc(1,sizeof(struct NR_DRB_ToAddMod)); + AssertFatal(rb_config->drb_ToAddModList->list.array[index] != NULL, + "failed to allocate memory for drb_toaddmod"); + rb_config->drb_ToAddModList->list.array[index]->drb_Identity + = ue_context_pP->ue_context.DRB_configList->list.array[index]->drb_Identity; + + if(ue_context_pP->ue_context.DRB_configList->list.array[index]->eps_BearerIdentity) { + rb_config->drb_ToAddModList->list.array[index]->cnAssociation + = calloc(1,sizeof(struct NR_DRB_ToAddMod__cnAssociation)); + AssertFatal(rb_config->drb_ToAddModList->list.array[index]->cnAssociation != NULL, + "failed to allocate memory cnAssociation"); + rb_config->drb_ToAddModList->list.array[index]->cnAssociation->present + = NR_DRB_ToAddMod__cnAssociation_PR_eps_BearerIdentity; + rb_config->drb_ToAddModList->list.array[index]->cnAssociation->choice.eps_BearerIdentity + = *(ue_context_pP->ue_context.DRB_configList->list.array[index]->eps_BearerIdentity); + } + + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config = calloc(1,sizeof(struct NR_PDCP_Config)); + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb = calloc(1,sizeof(struct NR_PDCP_Config__drb)); + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->discardTimer = calloc(1,sizeof(long)); + *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->discardTimer + = *(ue_context_pP->ue_context.DRB_configList->list.array[index]->pdcp_Config->discardTimer); + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeUL = calloc(1,sizeof(long)); + *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeUL + = NR_PDCP_Config__drb__pdcp_SN_SizeUL_len18bits; + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeDL = calloc(1,sizeof(long)); + *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeDL + = NR_PDCP_Config__drb__pdcp_SN_SizeDL_len18bits; + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->headerCompression.present + = NR_PDCP_Config__drb__headerCompression_PR_notUsed; + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->headerCompression.choice.notUsed = 0; + rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->t_Reordering = calloc(1,sizeof(long)); + *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->t_Reordering + = NR_PDCP_Config__t_Reordering_ms0; + } + + rb_config->securityConfig = calloc(1,sizeof(struct NR_SecurityConfig )); + rb_config->securityConfig->securityAlgorithmConfig = calloc(1,sizeof(struct NR_SecurityAlgorithmConfig)); + rb_config->securityConfig->securityAlgorithmConfig->cipheringAlgorithm = NR_CipheringAlgorithm_nea0; + rb_config->securityConfig->securityAlgorithmConfig->integrityProtAlgorithm = NULL; + rb_config->securityConfig->keyToUse = calloc(1,sizeof(long)); + *rb_config->securityConfig->keyToUse = NR_SecurityConfig__keyToUse_master; } cg_configinfo = calloc(1,sizeof(struct NR_CG_ConfigInfo)); AssertFatal(cg_configinfo != NULL,"failed to allocate memory for cg_configinfo"); cg_configinfo->criticalExtensions.present = NR_CG_ConfigInfo__criticalExtensions_PR_c1; - cg_configinfo->criticalExtensions.choice.c1 - = calloc(1, sizeof(struct NR_CG_ConfigInfo__criticalExtensions__c1)); + cg_configinfo->criticalExtensions.choice.c1 + = calloc(1, sizeof(struct NR_CG_ConfigInfo__criticalExtensions__c1)); AssertFatal(cg_configinfo->criticalExtensions.choice.c1 != NULL, - "failed to allocate memory for cg_configinfo->criticalExtensions.choice.c1"); - cg_configinfo->criticalExtensions.choice.c1->present - = NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo; - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo - = calloc(1,sizeof(struct NR_CG_ConfigInfo_IEs)); + "failed to allocate memory for cg_configinfo->criticalExtensions.choice.c1"); + cg_configinfo->criticalExtensions.choice.c1->present + = NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo; + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo + = calloc(1,sizeof(struct NR_CG_ConfigInfo_IEs)); AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo != NULL, - "failed to allocate memory for cg_configinfo_IEs"); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo - = calloc(1,sizeof( OCTET_STRING_t)); + "failed to allocate memory for cg_configinfo_IEs"); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo + = calloc(1,sizeof( OCTET_STRING_t)); AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> - ue_CapabilityInfo != NULL, "failed to allocate memory for ue_capabilityinfo"); -#if 1 - enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,NULL, - (void*)ue_context_pP->ue_context.UE_Capability,temp_buff,ASN_MAX_ENCODE_SIZE); - AssertFatal(enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", - enc_rval.failed_type->name, enc_rval.encoded); - OCTET_STRING_fromBuf( cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo, - (const char *)temp_buff,(enc_rval.encoded+7)>>3); -#endif + ue_CapabilityInfo != NULL, "failed to allocate memory for ue_capabilityinfo"); -#if 0 - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->size - = ue_context_pP->ue_context.UE_Capability_size; - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf - = calloc(1,ue_context_pP->ue_context.UE_Capability_size); - AssertFatal( cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> - ue_CapabilityInfo->buf != NULL, "failed to allocate memory for buf"); - memcpy(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf, - ue_context_pP->ue_context.UE_Capability,ue_context_pP->ue_context.UE_Capability_size); -#endif -#if 1 - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config - = calloc(1,sizeof(OCTET_STRING_t)); + if(ue_context_pP->ue_context.UE_Capability_MRDC) { + RAT_Container_count++; + enc_rval = uper_encode_to_buffer(&asn_DEF_NR_UE_MRDC_Capability,NULL, + (void *)ue_context_pP->ue_context.UE_Capability_MRDC,temp_buff,ASN_MAX_ENCODE_SIZE); + AssertFatal(enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + ue_cap_rat_container_MRDC.rat_Type = LTE_RAT_Type_eutra_nr; + OCTET_STRING_fromBuf(&ue_cap_rat_container_MRDC.ueCapabilityRAT_Container, + (const char *)temp_buff,(enc_rval.encoded+7)>>3); + memset((void *)temp_buff,0,sizeof(temp_buff)); + } + + if(ue_context_pP->ue_context.UE_Capability_nr) { + RAT_Container_count++; + enc_rval = uper_encode_to_buffer(&asn_DEF_NR_UE_NR_Capability,NULL, + (void *)ue_context_pP->ue_context.UE_Capability_nr,temp_buff,ASN_MAX_ENCODE_SIZE); + AssertFatal(enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + ue_cap_rat_container_nr.rat_Type = LTE_RAT_Type_nr; + OCTET_STRING_fromBuf(&ue_cap_rat_container_nr.ueCapabilityRAT_Container, + (const char *)temp_buff,(enc_rval.encoded+7)>>3); + memset((void *)temp_buff,0,sizeof(temp_buff)); + } + + ue_cap_rat_container_list = calloc(1,sizeof(LTE_UE_CapabilityRAT_ContainerList_t)); + ue_cap_rat_container_list->list.count = RAT_Container_count; + ue_cap_rat_container_list->list.size = sizeof(RAT_Container_count * sizeof(LTE_UE_CapabilityRAT_Container_t)); + ue_cap_rat_container_list->list.array = calloc(RAT_Container_count,sizeof(LTE_UE_CapabilityRAT_Container_t *)); + + if(ue_context_pP->ue_context.UE_Capability_MRDC) { + ue_cap_rat_container_list->list.array[0] = calloc(1,sizeof(LTE_UE_CapabilityRAT_Container_t)); + memcpy(ue_cap_rat_container_list->list.array[0],&ue_cap_rat_container_MRDC,sizeof(LTE_UE_CapabilityRAT_Container_t)); + } + + if(ue_context_pP->ue_context.UE_Capability_nr) { + ue_cap_rat_container_list->list.array[1] = calloc(1,sizeof(LTE_UE_CapabilityRAT_Container_t)); + memcpy(ue_cap_rat_container_list->list.array[1],&ue_cap_rat_container_nr,sizeof(LTE_UE_CapabilityRAT_Container_t)); + } + + //this xer_fprint logs can be enabled for additional debugging logs + //xer_fprint(stdout,&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,ue_cap_rat_container_list); + enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,NULL, + (void *)ue_cap_rat_container_list,temp_buff,ASN_MAX_ENCODE_SIZE); + AssertFatal(enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", + enc_rval.failed_type->name, enc_rval.encoded); + OCTET_STRING_fromBuf(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo, + (const char *)temp_buff, (enc_rval.encoded+7)>>3); + cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config + = calloc(1,sizeof(OCTET_STRING_t)); AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> - mcg_RB_Config != NULL, "failed to allocate memory for mcg_rb_config"); + mcg_RB_Config != NULL, "failed to allocate memory for mcg_rb_config"); enc_rval = uper_encode_to_buffer(&asn_DEF_NR_RadioBearerConfig,NULL,(void *)rb_config,temp_buff,ASN_MAX_ENCODE_SIZE); AssertFatal(enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", - enc_rval.failed_type->name, enc_rval.encoded); + enc_rval.failed_type->name, enc_rval.encoded); OCTET_STRING_fromBuf(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config, - (const char *)temp_buff, (enc_rval.encoded+7)>>3); -#endif -#if 0 - AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> - mcg_RB_Config != NULL, "failed to allocate memory for mcg_rb_config"); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->size - = sizeof( struct NR_RadioBearerConfig); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf - = calloc(1,sizeof(struct NR_RadioBearerConfig)); - AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo-> - mcg_RB_Config->buf != NULL,"failed to allocate memory for buf"); - memcpy(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf, - rb_config,sizeof(struct NR_RadioBearerConfig)); -#endif - // this xer_fprint can be enabled for additional debugging messages - xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo,(void*)cg_configinfo); - enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CG_ConfigInfo,NULL,(void*)cg_configinfo, - buffer,buffer_size); + (const char *)temp_buff, (enc_rval.encoded+7)>>3); + // this xer_fprint can be enabled for additional debugging messages + // xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo,(void *)cg_configinfo); + enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CG_ConfigInfo,NULL,(void *)cg_configinfo, + buffer,buffer_size); AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %lu)!\n", - enc_rval.failed_type->name, enc_rval.encoded); + enc_rval.failed_type->name, enc_rval.encoded); *enc_size = (enc_rval.encoded+7)/8; - free_rb_config(rb_config); - free_cg_configinfo(cg_configinfo); + ASN_STRUCT_FREE(asn_DEF_NR_RadioBearerConfig,rb_config); + ASN_STRUCT_FREE(asn_DEF_NR_CG_ConfigInfo,cg_configinfo); + ASN_STRUCT_FREE(asn_DEF_LTE_UE_CapabilityRAT_ContainerList,ue_cap_rat_container_list); return RRC_OK; - } -//----------------------------------------------------------------------------- - - - -/** - * @fn :api to free the all the dynamically allocated memory - * @param :cg_configinfo contains cellgroup configuration - */ -static void free_cg_configinfo( - struct NR_CG_ConfigInfo *cg_configinfo -) { - if(cg_configinfo){ - if(cg_configinfo->criticalExtensions.choice.c1){ - if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo){ - if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo){ - if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf){ - if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config){ - if(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf){ - free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config->buf =NULL; - free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config =NULL; - free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo->buf = NULL; - free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo =NULL; - free(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo); - cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo =NULL; - free(cg_configinfo->criticalExtensions.choice.c1); - cg_configinfo->criticalExtensions.choice.c1 =NULL; - free(cg_configinfo); - cg_configinfo =NULL; - } - } - } - } - } - } - } - return; } //----------------------------------------------------------------------------- -//----------------------------------------------------------------------------- -/** - * @fn :api to free the all the dynamically allocated memory - * @param :rb_config contains radiobearer configuration - */ -static void free_rb_config( - struct NR_RadioBearerConfig *rb_config -) { - int index = 0; - - if(rb_config) { - if(rb_config->drb_ToAddModList) { - if(rb_config->drb_ToAddModList->list.array) { - for(index = 0; index < rb_config->drb_ToAddModList->list.count; index++) { - if(rb_config->drb_ToAddModList->list.array[index]->cnAssociation) { - free(rb_config->drb_ToAddModList->list.array[index]->cnAssociation); - rb_config->drb_ToAddModList->list.array[index]->cnAssociation = NULL; - } - if(rb_config->drb_ToAddModList->list.array[index]) { - free(rb_config->drb_ToAddModList->list.array[index]); - rb_config->drb_ToAddModList->list.array[index] = NULL; - } - } - free(rb_config->drb_ToAddModList->list.array); - rb_config->drb_ToAddModList->list.array = NULL; - free(rb_config->drb_ToAddModList); - rb_config->drb_ToAddModList = NULL; - free(rb_config); - rb_config = NULL; - } - } - } - return; -} -//------------------------------------------------------------------------------ - @@ -4668,36 +4623,39 @@ rrc_eNB_process_MeasurementReport( ue_context_pP->ue_context.Status = RRC_NR_NSA; if(is_en_dc_supported(ue_context_pP->ue_context.UE_Capability)) { -/** to add gNB as Secondary node CG-ConfigInfo to be added as per 36.423 r15 **/ - if(encode_CG_ConfigInfo(enc_buf,sizeof(enc_buf),ue_context_pP,&enc_size) == RRC_OK) - LOG_I(RRC,"CG-ConfigInfo encoded successfully\n"); - msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ); - memset(&(X2AP_ENDC_SGNB_ADDITION_REQ(msg)), 0, sizeof(x2ap_ENDC_sgnb_addition_req_t)); - X2AP_ENDC_SGNB_ADDITION_REQ(msg).rnti = ctxt_pP->rnti; - memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer,enc_buf,enc_size); - X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer_size = enc_size; - X2AP_ENDC_SGNB_ADDITION_REQ(msg).target_physCellId - = measResults2->measResultNeighCells->choice.measResultListEUTRA.list.array[0]->physCellId; + /** to add gNB as Secondary node CG-ConfigInfo to be added as per 36.423 r15 **/ + if(encode_CG_ConfigInfo(enc_buf,sizeof(enc_buf),ue_context_pP,&enc_size) == RRC_OK) + LOG_I(RRC,"CG-ConfigInfo encoded successfully\n"); - //For the moment we have a single E-RAB which will be the one to be added to the gNB - //Not sure how to select bearers to be added if there are multiple. - X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded = 1; - for (int e_rab=0; e_rab < X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded; e_rab++){ - X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].e_rab_id = ue_context_pP->ue_context.e_rab[e_rab].param.e_rab_id; - X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].gtp_teid = ue_context_pP->ue_context.e_rab[e_rab].param.gtp_teid; - X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].drb_ID = 1; - memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr, - &ue_context_pP->ue_context.e_rab[e_rab].param.sgw_addr, - sizeof(transport_layer_addr_t)); - } - LOG_I(RRC, - "[eNB %d] frame %d subframe %d: UE rnti %x switching to NSA mode\n", - ctxt_pP->module_id, ctxt_pP->frame, ctxt_pP->subframe, ctxt_pP->rnti); - itti_send_msg_to_task(TASK_X2AP, ENB_MODULE_ID_TO_INSTANCE(ctxt_pP->module_id), msg); - return; + msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ); + memset(&(X2AP_ENDC_SGNB_ADDITION_REQ(msg)), 0, sizeof(x2ap_ENDC_sgnb_addition_req_t)); + X2AP_ENDC_SGNB_ADDITION_REQ(msg).rnti = ctxt_pP->rnti; + memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer,enc_buf,enc_size); + X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer_size = enc_size; + X2AP_ENDC_SGNB_ADDITION_REQ(msg).target_physCellId + = measResults2->measResultNeighCells->choice.measResultListEUTRA.list.array[0]->physCellId; + //For the moment we have a single E-RAB which will be the one to be added to the gNB + //Not sure how to select bearers to be added if there are multiple. + X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded = 1; + + for (int e_rab=0; e_rab < X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded; e_rab++) { + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].e_rab_id = ue_context_pP->ue_context.e_rab[e_rab].param.e_rab_id; + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].gtp_teid = ue_context_pP->ue_context.e_rab[e_rab].param.gtp_teid; + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].drb_ID = 1; + memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr, + &ue_context_pP->ue_context.e_rab[e_rab].param.sgw_addr, + sizeof(transport_layer_addr_t)); + } + + LOG_I(RRC, + "[eNB %d] frame %d subframe %d: UE rnti %x switching to NSA mode\n", + ctxt_pP->module_id, ctxt_pP->frame, ctxt_pP->subframe, ctxt_pP->rnti); + itti_send_msg_to_task(TASK_X2AP, ENB_MODULE_ID_TO_INSTANCE(ctxt_pP->module_id), msg); + return; } + } } -} + if (measResults2->measResultNeighCells == NULL) return; @@ -6340,6 +6298,7 @@ rrc_eNB_generate_HO_RRCConnectionReconfiguration(const protocol_ctxt_t *const ct ue_context_pP->ue_context.e_rab[i].param.nas_pdu.buffer = NULL; } } + LOG_I(RRC, "[eNB %d] Frame %d, Logical Channel DL-DCCH, Generate RRCConnectionReconfiguration handover (bytes %d, UE id %x)\n", ctxt_pP->module_id, ctxt_pP->frame, size, ue_context_pP->ue_context.rnti); @@ -6510,10 +6469,8 @@ rrc_eNB_process_RRCConnectionReconfigurationComplete( LTE_SRB_ToAddModList_t *SRB_configList = ue_context_pP->ue_context.SRB_configList2[xid]; LTE_DRB_ToReleaseList_t *DRB_Release_configList2 = ue_context_pP->ue_context.DRB_Release_configList2[xid]; LTE_DRB_Identity_t *drb_id_p = NULL; - ue_context_pP->ue_context.ue_reestablishment_timer = 0; ue_context_pP->ue_context.ue_rrc_inactivity_timer = 1; // reset rrc inactivity timer - /* CDRX: activated when RRC Connection Reconfiguration Complete is received */ rnti_t rnti = ue_context_pP->ue_id_rnti; module_id_t module_id = ctxt_pP->module_id; @@ -6534,8 +6491,8 @@ rrc_eNB_process_RRCConnectionReconfigurationComplete( LOG_I(RRC, "CDRX configuration activated after RRC Connection Reconfiguration Complete reception\n"); } } - /* End of CDRX processing */ + /* End of CDRX processing */ T(T_ENB_RRC_CONNECTION_RECONFIGURATION_COMPLETE, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame), @@ -6796,7 +6753,6 @@ rrc_eNB_process_RRCConnectionReconfigurationComplete( ue_context_pP->ue_context.nr_capabilities_requested = 1; rrc_eNB_generate_NR_UECapabilityEnquiry(ctxt_pP, ue_context_pP); } - } //----------------------------------------------------------------------------- @@ -7619,33 +7575,34 @@ is_en_dc_supported( */ #define NCE nonCriticalExtension return c != NULL - && c->NCE != NULL - && c->NCE->NCE != NULL - && c->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15 != NULL - && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15->en_DC_r15 != NULL - && *c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15->en_DC_r15 == LTE_IRAT_ParametersNR_r15__en_DC_r15_supported; + && c->NCE != NULL + && c->NCE->NCE != NULL + && c->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15 != NULL + && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15->en_DC_r15 != NULL + && *c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15->en_DC_r15 == + LTE_IRAT_ParametersNR_r15__en_DC_r15_supported; #undef NCE } @@ -7834,37 +7791,36 @@ rrc_eNB_decode_dcch( //Looking for a condition to trigger S1AP E-RAB-Modification-indication, based on the reception of RRCConnectionReconfigurationComplete //including NR specific elements. Not sure if this is the correct one and the correct placement /*if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. - nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension-> - scg_ConfigResponseNR_r15->buf!=NULL){ - //Trigger E-RAB Modification Indication - rrc_eNB_send_E_RAB_Modification_Indication(ctxt_pP, ue_context_p); + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension-> + scg_ConfigResponseNR_r15->buf!=NULL){ + //Trigger E-RAB Modification Indication + rrc_eNB_send_E_RAB_Modification_Indication(ctxt_pP, ue_context_p); }*/ if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. - nonCriticalExtension!=NULL){ - if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. - nonCriticalExtension->nonCriticalExtension!=NULL){ - if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. - nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL){ - if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. - nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL){ - if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. - nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL){ - if (ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. - nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL){ - if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. - nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension - ->scg_ConfigResponseNR_r15!=NULL){ - /*Trigger E-RAB Modification Indication */ - rrc_eNB_send_E_RAB_Modification_Indication(ctxt_pP, ue_context_p); - } - } - } - } - } - } + nonCriticalExtension!=NULL) { + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension!=NULL) { + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) { + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) { + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) { + if (ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) { + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension + ->scg_ConfigResponseNR_r15!=NULL) { + /*Trigger E-RAB Modification Indication */ + rrc_eNB_send_E_RAB_Modification_Indication(ctxt_pP, ue_context_p); + } + } + } + } + } + } } - } else { dedicated_DRB = 1; ue_context_p->ue_context.Status = RRC_RECONFIGURED; @@ -8212,15 +8168,74 @@ rrc_eNB_decode_dcch( } LOG_I(RRC, "got UE capabilities for UE %x\n", ctxt_pP->rnti); - int eutra_index = -1; for (i = 0; i < ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.count; i++) { - if (ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->rat_Type == LTE_RAT_Type_eutra) { + if (ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->rat_Type == + LTE_RAT_Type_nr) { + if(ue_context_p->ue_context.UE_Capability_nr) { + ASN_STRUCT_FREE(asn_DEF_NR_UE_NR_Capability,ue_context_p->ue_context.UE_Capability_nr); + ue_context_p->ue_context.UE_Capability_nr = 0; + } + + dec_rval = uper_decode(NULL, + &asn_DEF_NR_UE_NR_Capability, + (void **)&ue_context_p->ue_context.UE_Capability_nr, + ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->ueCapabilityRAT_Container.buf, + ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->ueCapabilityRAT_Container.size, + 0, 0); + + if (LOG_DEBUGFLAG(DEBUG_ASN1)) { + xer_fprint(stdout, &asn_DEF_NR_UE_NR_Capability, ue_context_p->ue_context.UE_Capability_nr); + } + + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + LOG_E(RRC, PROTOCOL_RRC_CTXT_UE_FMT" Failed to decode nr UE capabilities (%zu bytes)\n", + PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP),dec_rval.consumed); + ASN_STRUCT_FREE(asn_DEF_NR_UE_NR_Capability,ue_context_p->ue_context.UE_Capability_nr); + ue_context_p->ue_context.UE_Capability_nr = 0; + } + + ue_context_p->ue_context.UE_NR_Capability_size = + ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->ueCapabilityRAT_Container.size; + } + + if (ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->rat_Type == + LTE_RAT_Type_eutra_nr) { + if(ue_context_p->ue_context.UE_Capability_MRDC) { + ASN_STRUCT_FREE(asn_DEF_NR_UE_MRDC_Capability,ue_context_p->ue_context.UE_Capability_MRDC); + ue_context_p->ue_context.UE_Capability_MRDC = 0; + } + + dec_rval = uper_decode(NULL, + &asn_DEF_NR_UE_MRDC_Capability, + (void **)&ue_context_p->ue_context.UE_Capability_MRDC, + ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->ueCapabilityRAT_Container.buf, + ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->ueCapabilityRAT_Container.size, + 0, 0); + + if (LOG_DEBUGFLAG(DEBUG_ASN1)) { + xer_fprint(stdout, &asn_DEF_NR_UE_MRDC_Capability, ue_context_p->ue_context.UE_Capability_MRDC); + } + + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + LOG_E(RRC, PROTOCOL_RRC_CTXT_UE_FMT" Failed to decode MRDC UE capabilities (%zu bytes)\n", + PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP),dec_rval.consumed); + ASN_STRUCT_FREE(asn_DEF_NR_UE_MRDC_Capability,ue_context_p->ue_context.UE_Capability_MRDC); + ue_context_p->ue_context.UE_Capability_MRDC = 0; + } + + ue_context_p->ue_context.UE_MRDC_Capability_size = + ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->ueCapabilityRAT_Container.size; + } + + if (ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->rat_Type == + LTE_RAT_Type_eutra) { if (eutra_index != -1) { LOG_E(RRC, "fatal: more than 1 eutra capability\n"); exit(1); } + eutra_index = i; } } @@ -8242,7 +8257,8 @@ rrc_eNB_decode_dcch( ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[eutra_index]->ueCapabilityRAT_Container.buf, ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[eutra_index]->ueCapabilityRAT_Container.size, 0, 0); - ue_context_p->ue_context.UE_Capability_size = ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[eutra_index]->ueCapabilityRAT_Container.size; + ue_context_p->ue_context.UE_Capability_size = + ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[eutra_index]->ueCapabilityRAT_Container.size; if ( LOG_DEBUGFLAG(DEBUG_ASN1) ) { xer_fprint(stdout, &asn_DEF_LTE_UE_EUTRA_Capability, ue_context_p->ue_context.UE_Capability); @@ -8961,117 +8977,109 @@ void rrc_subframe_process(protocol_ctxt_t *const ctxt_pP, const int CC_id) { } void rrc_eNB_process_AdditionResponseInformation(const module_id_t enb_mod_idP, x2ap_ENDC_sgnb_addition_req_ACK_t *m) { + NR_CG_Config_t *CG_Config = NULL; + { + int i; + printf("%d: ", m->rrc_buffer_size); + for (i=0; irrc_buffer_size; i++) printf("%2.2x", (unsigned char)m->rrc_buffer[i]); - NR_CG_Config_t *CG_Config = NULL; + printf("\n"); + } + asn_dec_rval_t dec_rval = uper_decode_complete( NULL, + &asn_DEF_NR_CG_Config, + (void **)&CG_Config, + (uint8_t *)m->rrc_buffer, + (int) m->rrc_buffer_size);//m->rrc_buffer_size); - { - int i; - printf("%d: ", m->rrc_buffer_size); - for (i=0; irrc_buffer_size; i++) printf("%2.2x", (unsigned char)m->rrc_buffer[i]); - printf("\n"); + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + AssertFatal(1==0,"NR_UL_DCCH_MESSAGE decode error\n"); + // free the memory + SEQUENCE_free( &asn_DEF_NR_CG_Config, CG_Config, 1 ); + return; + } - } - asn_dec_rval_t dec_rval = uper_decode_complete( NULL, - &asn_DEF_NR_CG_Config, - (void **)&CG_Config, - (uint8_t *)m->rrc_buffer, - (int) m->rrc_buffer_size);//m->rrc_buffer_size); + xer_fprint(stdout,&asn_DEF_NR_CG_Config, CG_Config); + // recreate enough of X2 EN-DC Container + AssertFatal(CG_Config->criticalExtensions.choice.c1->present == NR_CG_Config__criticalExtensions__c1_PR_cg_Config, + "CG_Config not present\n"); + OCTET_STRING_t *scg_CellGroupConfig = NULL; + OCTET_STRING_t *nr1_conf = NULL; - if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { - AssertFatal(1==0,"NR_UL_DCCH_MESSAGE decode error\n"); - // free the memory - SEQUENCE_free( &asn_DEF_NR_CG_Config, CG_Config, 1 ); - return; - } - xer_fprint(stdout,&asn_DEF_NR_CG_Config, CG_Config); - // recreate enough of X2 EN-DC Container - - AssertFatal(CG_Config->criticalExtensions.choice.c1->present == NR_CG_Config__criticalExtensions__c1_PR_cg_Config, - "CG_Config not present\n"); - - OCTET_STRING_t *scg_CellGroupConfig = NULL; - OCTET_STRING_t *nr1_conf = NULL; - - if(CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig){ - scg_CellGroupConfig = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig; + if(CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig) { + scg_CellGroupConfig = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig; #ifdef DEBUG_SCG_CONFIG - { - int size_s = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig->size; - int i; - LOG_I(RRC, "Dumping scg_CellGroupConfig: %d", size_s); - for (i=0; icriticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig->buf[i]); - printf("\n"); + { + int size_s = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig->size; + int i; + LOG_I(RRC, "Dumping scg_CellGroupConfig: %d", size_s); - } + for (i=0; icriticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig->buf[i]); + + printf("\n"); + } #endif + } else { + LOG_W(RRC, "SCG Cell group configuration is not present in the Addition Response message \n"); + return; + } - } - else{ - LOG_W(RRC, "SCG Cell group configuration is not present in the Addition Response message \n"); - return; - } - if(CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config){ - nr1_conf = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config; + if(CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config) { + nr1_conf = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config; #ifdef DEBUG_SCG_CONFIG - { - int size_s = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config->size; - int i; - LOG_I(RRC, "Dumping scg_RB_Config: %d", size_s); - for (i=0; icriticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config->buf[i]); - printf("\n"); + { + int size_s = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config->size; + int i; + LOG_I(RRC, "Dumping scg_RB_Config: %d", size_s); - } + for (i=0; icriticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config->buf[i]); + + printf("\n"); + } #endif - } - else{ - LOG_W(RRC, "SCG RB configuration is not present in the Addition Response message \n"); - return; + } else { + LOG_W(RRC, "SCG RB configuration is not present in the Addition Response message \n"); + return; + } + + protocol_ctxt_t ctxt; + rrc_eNB_ue_context_t *ue_context; + unsigned char buffer[8192]; + int size; + ue_context = rrc_eNB_get_ue_context(RC.rrc[enb_mod_idP], m->rnti); + ue_context->ue_context.nb_of_modify_endc_e_rabs = m->nb_e_rabs_admitted_tobeadded; + int j=0; + + while(j < m->nb_e_rabs_admitted_tobeadded) { + for (int e_rab_idx=0; e_rab_idxue_context.setup_e_rabs; e_rab_idx++) { + //Update ue_context information with gNB's address and new GTP tunnel ID + if( ue_context->ue_context.e_rab[e_rab_idx].param.e_rab_id == m->e_rabs_admitted_tobeadded[j].e_rab_id) { + memcpy(ue_context->ue_context.gnb_gtp_endc_addrs[e_rab_idx].buffer, + m->e_rabs_admitted_tobeadded[j].gnb_addr.buffer, + m->e_rabs_admitted_tobeadded[j].gnb_addr.length); + ue_context->ue_context.gnb_gtp_endc_addrs[e_rab_idx].length = m->e_rabs_admitted_tobeadded[j].gnb_addr.length; + ue_context->ue_context.gnb_gtp_endc_teid[e_rab_idx] = m->e_rabs_admitted_tobeadded[j].gtp_teid; + ue_context->ue_context.e_rab[e_rab_idx].status = E_RAB_STATUS_TOMODIFY; + break; + } } - protocol_ctxt_t ctxt; - rrc_eNB_ue_context_t *ue_context; - unsigned char buffer[8192]; - int size; + j++; + } - ue_context = rrc_eNB_get_ue_context(RC.rrc[enb_mod_idP], m->rnti); - - ue_context->ue_context.nb_of_modify_endc_e_rabs = m->nb_e_rabs_admitted_tobeadded; - - int j=0; - while(j < m->nb_e_rabs_admitted_tobeadded){ - for (int e_rab_idx=0; e_rab_idxue_context.setup_e_rabs; e_rab_idx++){ - //Update ue_context information with gNB's address and new GTP tunnel ID - if( ue_context->ue_context.e_rab[e_rab_idx].param.e_rab_id == m->e_rabs_admitted_tobeadded[j].e_rab_id){ - memcpy(ue_context->ue_context.gnb_gtp_endc_addrs[e_rab_idx].buffer, - m->e_rabs_admitted_tobeadded[j].gnb_addr.buffer, - m->e_rabs_admitted_tobeadded[j].gnb_addr.length); - ue_context->ue_context.gnb_gtp_endc_addrs[e_rab_idx].length = m->e_rabs_admitted_tobeadded[j].gnb_addr.length; - ue_context->ue_context.gnb_gtp_endc_teid[e_rab_idx] = m->e_rabs_admitted_tobeadded[j].gtp_teid; - ue_context->ue_context.e_rab[e_rab_idx].status = E_RAB_STATUS_TOMODIFY; - break; - } - } - j++; - } - - - - PROTOCOL_CTXT_SET_BY_INSTANCE(&ctxt, - 0, - ENB_FLAG_YES, - m->rnti, - 0, 0); - - size = rrc_eNB_generate_RRCConnectionReconfiguration_endc(&ctxt, ue_context, buffer, 8192, scg_CellGroupConfig, nr1_conf); - - rrc_data_req(&ctxt, - DCCH, - rrc_eNB_mui++, - SDU_CONFIRM_NO, - size, - buffer, - PDCP_TRANSMISSION_MODE_CONTROL); + PROTOCOL_CTXT_SET_BY_INSTANCE(&ctxt, + 0, + ENB_FLAG_YES, + m->rnti, + 0, 0); + size = rrc_eNB_generate_RRCConnectionReconfiguration_endc(&ctxt, ue_context, buffer, 8192, scg_CellGroupConfig, nr1_conf); + rrc_data_req(&ctxt, + DCCH, + rrc_eNB_mui++, + SDU_CONFIRM_NO, + size, + buffer, + PDCP_TRANSMISSION_MODE_CONTROL); } @@ -9354,11 +9362,10 @@ void *rrc_enb_process_itti_msg(void *notUsed) { } case X2AP_ENDC_SGNB_ADDITION_REQ_ACK: { - rrc_eNB_process_AdditionResponseInformation(ENB_INSTANCE_TO_MODULE_ID(instance), &X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg_p)); - break; + rrc_eNB_process_AdditionResponseInformation(ENB_INSTANCE_TO_MODULE_ID(instance), &X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg_p)); + break; } - /* Messages from eNB app */ case RRC_CONFIGURATION_REQ: LOG_I(RRC, "[eNB %d] Received %s : %p\n", instance, msg_name_p, &RRC_CONFIGURATION_REQ(msg_p)); @@ -9378,36 +9385,36 @@ void *rrc_enb_process_itti_msg(void *notUsed) { break; case M2AP_SETUP_RESP: - rrc_eNB_process_M2AP_SETUP_RESP(&ctxt,0/*CC_id*/,ENB_INSTANCE_TO_MODULE_ID(instance),&M2AP_SETUP_RESP(msg_p)); + rrc_eNB_process_M2AP_SETUP_RESP(&ctxt,0/*CC_id*/,ENB_INSTANCE_TO_MODULE_ID(instance),&M2AP_SETUP_RESP(msg_p)); break; case M2AP_MBMS_SCHEDULING_INFORMATION: - rrc_eNB_process_M2AP_MBMS_SCHEDULING_INFORMATION(&ctxt,0/*CC_id*/,ENB_INSTANCE_TO_MODULE_ID(instance),&M2AP_MBMS_SCHEDULING_INFORMATION(msg_p)); - break; + rrc_eNB_process_M2AP_MBMS_SCHEDULING_INFORMATION(&ctxt,0/*CC_id*/,ENB_INSTANCE_TO_MODULE_ID(instance),&M2AP_MBMS_SCHEDULING_INFORMATION(msg_p)); + break; case M2AP_MBMS_SESSION_START_REQ: - rrc_eNB_process_M2AP_MBMS_SESSION_START_REQ(&ctxt,0/*CC_id*/,ENB_INSTANCE_TO_MODULE_ID(instance),&M2AP_MBMS_SESSION_START_REQ(msg_p)); - break; + rrc_eNB_process_M2AP_MBMS_SESSION_START_REQ(&ctxt,0/*CC_id*/,ENB_INSTANCE_TO_MODULE_ID(instance),&M2AP_MBMS_SESSION_START_REQ(msg_p)); + break; case M2AP_MBMS_SESSION_STOP_REQ: - rrc_eNB_process_M2AP_MBMS_SESSION_STOP_REQ(&ctxt,&M2AP_MBMS_SESSION_STOP_REQ(msg_p)); - break; + rrc_eNB_process_M2AP_MBMS_SESSION_STOP_REQ(&ctxt,&M2AP_MBMS_SESSION_STOP_REQ(msg_p)); + break; case M2AP_RESET: - rrc_eNB_process_M2AP_RESET(&ctxt,&M2AP_RESET(msg_p)); - break; + rrc_eNB_process_M2AP_RESET(&ctxt,&M2AP_RESET(msg_p)); + break; case M2AP_ENB_CONFIGURATION_UPDATE_ACK: - rrc_eNB_process_M2AP_ENB_CONFIGURATION_UPDATE_ACK(&ctxt,&M2AP_ENB_CONFIGURATION_UPDATE_ACK(msg_p)); - break; + rrc_eNB_process_M2AP_ENB_CONFIGURATION_UPDATE_ACK(&ctxt,&M2AP_ENB_CONFIGURATION_UPDATE_ACK(msg_p)); + break; case M2AP_ERROR_INDICATION: - rrc_eNB_process_M2AP_ERROR_INDICATION(&ctxt,&M2AP_ERROR_INDICATION(msg_p)); - break; + rrc_eNB_process_M2AP_ERROR_INDICATION(&ctxt,&M2AP_ERROR_INDICATION(msg_p)); + break; case M2AP_MBMS_SERVICE_COUNTING_REQ: - rrc_eNB_process_M2AP_MBMS_SERVICE_COUNTING_REQ(&ctxt,&M2AP_MBMS_SERVICE_COUNTING_REQ(msg_p)); - break; + rrc_eNB_process_M2AP_MBMS_SERVICE_COUNTING_REQ(&ctxt,&M2AP_MBMS_SERVICE_COUNTING_REQ(msg_p)); + break; case M2AP_MCE_CONFIGURATION_UPDATE: rrc_eNB_process_M2AP_MCE_CONFIGURATION_UPDATE(&ctxt,&M2AP_MCE_CONFIGURATION_UPDATE(msg_p)); @@ -9444,17 +9451,16 @@ rrc_enb_task( //----------------------------------------------------------------------------- { rrc_enb_init(); - itti_mark_task_ready(TASK_RRC_ENB); LOG_I(RRC,"Entering main loop of RRC message task\n"); while (1) { (void) rrc_enb_process_itti_msg(NULL); -{ - //extern volatile int go_nr; - void rrc_go_nr(void); - //if (go_nr) rrc_go_nr(); -} + { + //extern volatile int go_nr; + void rrc_go_nr(void); + //if (go_nr) rrc_go_nr(); + } } } diff --git a/openair2/RRC/NR/rrc_gNB.c b/openair2/RRC/NR/rrc_gNB.c index c74846b75a..1f341cfdf9 100644 --- a/openair2/RRC/NR/rrc_gNB.c +++ b/openair2/RRC/NR/rrc_gNB.c @@ -95,12 +95,10 @@ mui_t rrc_gNB_mui = 0; void openair_nr_rrc_on(const protocol_ctxt_t *const ctxt_pP) { LOG_I(NR_RRC, PROTOCOL_NR_RRC_CTXT_FMT" gNB:OPENAIR NR RRC IN....\n",PROTOCOL_NR_RRC_CTXT_ARGS(ctxt_pP)); - rrc_config_nr_buffer (&RC.nrrrc[ctxt_pP->module_id]->carrier.SI, BCCH, 1); RC.nrrrc[ctxt_pP->module_id]->carrier.SI.Active = 1; rrc_config_nr_buffer (&RC.nrrrc[ctxt_pP->module_id]->carrier.Srb0, CCCH, 1); RC.nrrrc[ctxt_pP->module_id]->carrier.Srb0.Active = 1; - } ///---------------------------------------------------------------------------------------------------------------/// @@ -173,7 +171,6 @@ void rrc_gNB_generate_SgNBAdditionRequestAcknowledge( ue_context_pP->ue_context.primaryCC_id, physicalCellGroupConfig, physicalcellgroup_config); - do_SpCellConfig(RC.nrrrc[ctxt_pP->module_id], spCellConfig); } @@ -182,57 +179,47 @@ void rrc_gNB_generate_SgNBAdditionRequestAcknowledge( ///---------------------------------------------------------------------------------------------------------------/// static void init_NR_SI(gNB_RRC_INST *rrc) { - - LOG_D(RRC,"%s()\n\n\n\n",__FUNCTION__); - - - - rrc->carrier.MIB = (uint8_t*) malloc16(4); + rrc->carrier.MIB = (uint8_t *) malloc16(4); rrc->carrier.sizeof_MIB = do_MIB_NR(rrc,0); - - LOG_I(NR_RRC,"Done init_NR_SI\n"); - - rrc_mac_config_req_gNB(rrc->module_id, - rrc->carrier.ssb_SubcarrierOffset, + rrc->carrier.ssb_SubcarrierOffset, rrc->carrier.pdsch_AntennaPorts, (NR_ServingCellConfigCommon_t *)rrc->carrier.servingcellconfigcommon, - 0, - 0, // WIP hardcoded rnti - (NR_CellGroupConfig_t *)NULL - ); - + 0, + 0, // WIP hardcoded rnti + (NR_CellGroupConfig_t *)NULL + ); if (get_softmodem_params()->phy_test > 0 || get_softmodem_params()->do_ra > 0) { // This is for phytest only, emulate first X2 message if uecap.raw file is present FILE *fd; - fd = fopen("uecap.raw","r"); + if (fd != NULL) { char buffer[4096]; int msg_len=fread(buffer,1,4096,fd); LOG_I(RRC,"Read in %d bytes for uecap\n",msg_len); LTE_UL_DCCH_Message_t *LTE_UL_DCCH_Message; - asn_dec_rval_t dec_rval = uper_decode_complete( NULL, - &asn_DEF_LTE_UL_DCCH_Message, - (void **)<E_UL_DCCH_Message, - (uint8_t *)buffer, - msg_len); - + &asn_DEF_LTE_UL_DCCH_Message, + (void **)<E_UL_DCCH_Message, + (uint8_t *)buffer, + msg_len); + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { AssertFatal(1==0,"NR_UL_DCCH_MESSAGE decode error\n"); - // free the memory - SEQUENCE_free( &asn_DEF_LTE_UL_DCCH_Message, LTE_UL_DCCH_Message, 1 ); - return; - } + // free the memory + SEQUENCE_free( &asn_DEF_LTE_UL_DCCH_Message, LTE_UL_DCCH_Message, 1 ); + return; + } + fclose(fd); xer_fprint(stdout,&asn_DEF_LTE_UL_DCCH_Message, LTE_UL_DCCH_Message); // recreate enough of X2 EN-DC Container AssertFatal(LTE_UL_DCCH_Message->message.choice.c1.present == LTE_UL_DCCH_MessageType__c1_PR_ueCapabilityInformation, - "ueCapabilityInformation not present\n"); + "ueCapabilityInformation not present\n"); NR_CG_ConfigInfo_t *CG_ConfigInfo = calloc(1,sizeof(*CG_ConfigInfo)); CG_ConfigInfo->criticalExtensions.present = NR_CG_ConfigInfo__criticalExtensions_PR_c1; CG_ConfigInfo->criticalExtensions.choice.c1 = calloc(1,sizeof(*CG_ConfigInfo->criticalExtensions.choice.c1)); @@ -240,42 +227,37 @@ static void init_NR_SI(gNB_RRC_INST *rrc) { CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo = calloc(1,sizeof(*CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo)); NR_CG_ConfigInfo_IEs_t *cg_ConfigInfo = CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo; cg_ConfigInfo->ue_CapabilityInfo = calloc(1,sizeof(*cg_ConfigInfo->ue_CapabilityInfo)); - asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,NULL,(void*)<E_UL_DCCH_Message->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList,buffer,4096); + asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,NULL, + (void *)<E_UL_DCCH_Message->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList,buffer,4096); AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", - enc_rval.failed_type->name, enc_rval.encoded); + enc_rval.failed_type->name, enc_rval.encoded); OCTET_STRING_fromBuf(cg_ConfigInfo->ue_CapabilityInfo, - (const char *)buffer, - (enc_rval.encoded+7)>>3); + (const char *)buffer, + (enc_rval.encoded+7)>>3); parse_CG_ConfigInfo(rrc,CG_ConfigInfo,NULL); - } - else { + } else { struct rrc_gNB_ue_context_s *ue_context_p = rrc_gNB_allocate_new_UE_context(rrc); - - LOG_I(NR_RRC,"Adding new user (%p)\n",ue_context_p); + LOG_I(NR_RRC,"Adding new user (%p)\n",ue_context_p); rrc_add_nsa_user(rrc,ue_context_p,NULL); - } + } } } char openair_rrc_gNB_configuration(const module_id_t gnb_mod_idP, gNB_RrcConfigurationReq *configuration) { protocol_ctxt_t ctxt; - gNB_RRC_INST *rrc=RC.nrrrc[gnb_mod_idP]; - PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, gnb_mod_idP, GNB_FLAG_YES, NOT_A_RNTI, 0, 0,gnb_mod_idP); - LOG_I(NR_RRC, PROTOCOL_NR_RRC_CTXT_FMT" Init...\n", PROTOCOL_NR_RRC_CTXT_ARGS(&ctxt)); + AssertFatal(rrc != NULL, "RC.nrrrc not initialized!"); AssertFatal(NUMBER_OF_UE_MAX < (module_id_t)0xFFFFFFFFFFFFFFFF, " variable overflow"); AssertFatal(configuration!=NULL,"configuration input is null\n"); rrc->module_id = gnb_mod_idP; rrc->Nb_ue = 0; - rrc->carrier.Srb0.Active = 0; - nr_uid_linear_allocator_init(&rrc->uid_allocator); RB_INIT(&rrc->rrc_ue_head); rrc->initial_id2_s1ap_ids = hashtable_create (NUMBER_OF_UE_MAX * 2, NULL, NULL); @@ -285,7 +267,6 @@ char openair_rrc_gNB_configuration(const module_id_t gnb_mod_idP, gNB_RrcConfigu rrc->carrier.pdsch_AntennaPorts = configuration->pdsch_AntennaPorts; /// System Information INIT LOG_I(NR_RRC, PROTOCOL_NR_RRC_CTXT_FMT" Checking release \n",PROTOCOL_NR_RRC_CTXT_ARGS(&ctxt)); - init_NR_SI(rrc); rrc_init_nr_global_param(); openair_nr_rrc_on(&ctxt); @@ -294,46 +275,26 @@ char openair_rrc_gNB_configuration(const module_id_t gnb_mod_idP, gNB_RrcConfigu void rrc_gNB_process_AdditionRequestInformation(const module_id_t gnb_mod_idP, x2ap_ENDC_sgnb_addition_req_t *m) { + struct NR_CG_ConfigInfo *cg_configinfo = NULL; + asn_dec_rval_t dec_rval = uper_decode_complete(NULL, + &asn_DEF_NR_CG_ConfigInfo, + (void **)&cg_configinfo, + (uint8_t *)m->rrc_buffer, + (int) m->rrc_buffer_size);//m->rrc_buffer_size); + gNB_RRC_INST *rrc=RC.nrrrc[gnb_mod_idP]; + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + AssertFatal(1==0,"NR_UL_DCCH_MESSAGE decode error\n"); + // free the memory + SEQUENCE_free(&asn_DEF_NR_CG_ConfigInfo, cg_configinfo, 1); + return; + } - //LTE_UL_DCCH_Message_t *LTE_UL_DCCH_Message = NULL; - struct NR_CG_ConfigInfo *cg_configinfo = NULL; - - asn_dec_rval_t dec_rval = uper_decode_complete( NULL, - &asn_DEF_NR_CG_ConfigInfo, - (void **)&cg_configinfo, - (uint8_t *)m->rrc_buffer, - (int) m->rrc_buffer_size);//m->rrc_buffer_size); - - gNB_RRC_INST *rrc=RC.nrrrc[gnb_mod_idP]; - - if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { - AssertFatal(1==0,"NR_UL_DCCH_MESSAGE decode error\n"); - // free the memory - SEQUENCE_free(&asn_DEF_NR_CG_ConfigInfo, cg_configinfo, 1); - return; - } - xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo, cg_configinfo); - // recreate enough of X2 EN-DC Container - AssertFatal(cg_configinfo->criticalExtensions.choice.c1->present == NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo, - "ueCapabilityInformation not present\n"); -#if 0 - NR_CG_ConfigInfo_t *CG_ConfigInfo = calloc(1,sizeof(*CG_ConfigInfo)); - CG_ConfigInfo->criticalExtensions.present = NR_CG_ConfigInfo__criticalExtensions_PR_c1; - CG_ConfigInfo->criticalExtensions.choice.c1 = calloc(1,sizeof(*CG_ConfigInfo->criticalExtensions.choice.c1)); - CG_ConfigInfo->criticalExtensions.choice.c1->present = NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo; - CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo = calloc(1,sizeof(*CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo)); - NR_CG_ConfigInfo_IEs_t *cg_ConfigInfo = CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo; - cg_ConfigInfo->ue_CapabilityInfo = calloc(1,sizeof(*cg_ConfigInfo->ue_CapabilityInfo)); - asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,NULL,(void*)<E_UL_DCCH_Message->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList,m->rrc_buffer,m->rrc_buffer_size); - AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", - enc_rval.failed_type->name, enc_rval.encoded); - OCTET_STRING_fromBuf(cg_ConfigInfo->ue_CapabilityInfo, - (const char *)m->rrc_buffer, - (enc_rval.encoded+7)>>3); -#endif - parse_CG_ConfigInfo(rrc,cg_configinfo,m); - + xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo, cg_configinfo); + // recreate enough of X2 EN-DC Container + AssertFatal(cg_configinfo->criticalExtensions.choice.c1->present == NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo, + "ueCapabilityInformation not present\n"); + parse_CG_ConfigInfo(rrc,cg_configinfo,m); } ///---------------------------------------------------------------------------------------------------------------/// @@ -431,16 +392,15 @@ void *rrc_gnb_task(void *args_p) { openair_rrc_gNB_configuration(GNB_INSTANCE_TO_MODULE_ID(instance), &NRRRC_CONFIGURATION_REQ(msg_p)); break; - /* Messages from X2AP */ + /* Messages from X2AP */ case X2AP_ENDC_SGNB_ADDITION_REQ: - LOG_I(NR_RRC, "Received ENDC sgNB addition request from X2AP \n"); - rrc_gNB_process_AdditionRequestInformation(GNB_INSTANCE_TO_MODULE_ID(instance), &X2AP_ENDC_SGNB_ADDITION_REQ(msg_p)); - break; + LOG_I(NR_RRC, "Received ENDC sgNB addition request from X2AP \n"); + rrc_gNB_process_AdditionRequestInformation(GNB_INSTANCE_TO_MODULE_ID(instance), &X2AP_ENDC_SGNB_ADDITION_REQ(msg_p)); + break; case X2AP_ENDC_SGNB_RECONF_COMPLETE: - LOG_I(NR_RRC, "Handling of reconfiguration complete message at RRC gNB is pending \n"); - break; - + LOG_I(NR_RRC, "Handling of reconfiguration complete message at RRC gNB is pending \n"); + break; default: LOG_E(NR_RRC, "[gNB %d] Received unexpected message %s\n", instance, msg_name_p); diff --git a/openair2/RRC/NR/rrc_gNB_internode.c b/openair2/RRC/NR/rrc_gNB_internode.c index 092c63f96e..cacff5cf5c 100644 --- a/openair2/RRC/NR/rrc_gNB_internode.c +++ b/openair2/RRC/NR/rrc_gNB_internode.c @@ -39,47 +39,48 @@ #include "NR_CG-Config.h" int parse_CG_ConfigInfo(gNB_RRC_INST *rrc, NR_CG_ConfigInfo_t *CG_ConfigInfo, x2ap_ENDC_sgnb_addition_req_t *m) { - if (CG_ConfigInfo->criticalExtensions.present == NR_CG_ConfigInfo__criticalExtensions_PR_c1) { if (CG_ConfigInfo->criticalExtensions.choice.c1) { if (CG_ConfigInfo->criticalExtensions.choice.c1->present == NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo) { - NR_CG_ConfigInfo_IEs_t *cg_ConfigInfo = CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo; - if (cg_ConfigInfo->ue_CapabilityInfo) { - // Decode UE-CapabilityRAT-ContainerList + NR_CG_ConfigInfo_IEs_t *cg_ConfigInfo = CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo; + + if (cg_ConfigInfo->ue_CapabilityInfo) { + // Decode UE-CapabilityRAT-ContainerList LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList=NULL; - asn_dec_rval_t dec_rval = uper_decode(NULL, - &asn_DEF_LTE_UE_CapabilityRAT_ContainerList, - (void**)&UE_CapabilityRAT_ContainerList, - cg_ConfigInfo->ue_CapabilityInfo->buf, - cg_ConfigInfo->ue_CapabilityInfo->size, 0, 0); + UE_CapabilityRAT_ContainerList = calloc(1,sizeof(LTE_UE_CapabilityRAT_ContainerList_t)); + asn_dec_rval_t dec_rval = uper_decode(NULL, + &asn_DEF_LTE_UE_CapabilityRAT_ContainerList, + (void **)&UE_CapabilityRAT_ContainerList, + cg_ConfigInfo->ue_CapabilityInfo->buf, + cg_ConfigInfo->ue_CapabilityInfo->size, 0, 0); + if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { - AssertFatal(1==0,"[InterNode] Failed to decode NR_UE_CapabilityRAT_ContainerList (%zu bits), size of OCTET_STRING %lu\n", - dec_rval.consumed, cg_ConfigInfo->ue_CapabilityInfo->size); - } - rrc_parse_ue_capabilities(rrc,UE_CapabilityRAT_ContainerList, m,cg_ConfigInfo); - } - if (cg_ConfigInfo->candidateCellInfoListMN) AssertFatal(1==0,"Can't handle candidateCellInfoListMN yet\n"); - } - else AssertFatal(1==0,"c1 extension is not cg_ConfigInfo, returning\n"); - } - else { + AssertFatal(1==0,"[InterNode] Failed to decode NR_UE_CapabilityRAT_ContainerList (%zu bits), size of OCTET_STRING %lu\n", + dec_rval.consumed, cg_ConfigInfo->ue_CapabilityInfo->size); + } + + rrc_parse_ue_capabilities(rrc,UE_CapabilityRAT_ContainerList, m,cg_ConfigInfo); + } + + if (cg_ConfigInfo->candidateCellInfoListMN) AssertFatal(1==0,"Can't handle candidateCellInfoListMN yet\n"); + } else AssertFatal(1==0,"c1 extension is not cg_ConfigInfo, returning\n"); + } else { LOG_E(RRC,"c1 extension not found, returning\n"); - return(-1); + return(-1); } } else { LOG_E(RRC,"Ignoring unknown CG_ConfigInfo extensions\n"); return(-1); } - return(0); + + return(0); } -int generate_CG_Config(gNB_RRC_INST *rrc, - NR_CG_Config_t *cg_Config, - NR_RRCReconfiguration_t *reconfig, - NR_RadioBearerConfig_t *rbconfig) { - - +int generate_CG_Config(gNB_RRC_INST *rrc, + NR_CG_Config_t *cg_Config, + NR_RRCReconfiguration_t *reconfig, + NR_RadioBearerConfig_t *rbconfig) { cg_Config->criticalExtensions.present = NR_CG_Config__criticalExtensions_PR_c1; cg_Config->criticalExtensions.choice.c1 = calloc(1,sizeof(*cg_Config->criticalExtensions.choice.c1)); cg_Config->criticalExtensions.choice.c1->present = NR_CG_Config__criticalExtensions__c1_PR_cg_Config; @@ -91,36 +92,37 @@ int generate_CG_Config(gNB_RRC_INST *rrc, enc_rval.failed_type->name, enc_rval.encoded); cg_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig = calloc(1,sizeof(OCTET_STRING_t)); OCTET_STRING_fromBuf(cg_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig, - (const char *)buffer, - (enc_rval.encoded+7)>>3); + (const char *)buffer, + (enc_rval.encoded+7)>>3); total_size = (enc_rval.encoded+7)>>3; - LOG_I(RRC,"Dumping NR_RRCReconfiguration message (%jd bytes)\n",(enc_rval.encoded+7)>>3); - for (int i=0;i<(enc_rval.encoded+7)>>3;i++) { + + for (int i=0; i<(enc_rval.encoded+7)>>3; i++) { printf("%02x",((uint8_t *)buffer)[i]); } + printf("\n"); FILE *fd = fopen("reconfig.raw","w"); - fwrite((void*)buffer,1,(size_t)((enc_rval.encoded+7)>>3),fd); + fwrite((void *)buffer,1,(size_t)((enc_rval.encoded+7)>>3),fd); fclose(fd); - enc_rval = uper_encode_to_buffer(&asn_DEF_NR_RadioBearerConfig, NULL, (void *)rbconfig, buffer, 1024); AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", enc_rval.failed_type->name, enc_rval.encoded); cg_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config = calloc(1,sizeof(OCTET_STRING_t)); OCTET_STRING_fromBuf(cg_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config, - (const char *)buffer, - (enc_rval.encoded+7)>>3); + (const char *)buffer, + (enc_rval.encoded+7)>>3); LOG_I(RRC,"Dumping scg_RB_Config message (%jd bytes)\n",(enc_rval.encoded+7)>>3); - for (int i=0;i<(enc_rval.encoded+7)>>3;i++) { - printf("%02x",((uint8_t*)buffer)[i]); + + for (int i=0; i<(enc_rval.encoded+7)>>3; i++) { + printf("%02x",((uint8_t *)buffer)[i]); } + printf("\n"); fd = fopen("rbconfig.raw","w"); - fwrite((void*)buffer,1,(size_t)((enc_rval.encoded+7)>>3),fd); + fwrite((void *)buffer,1,(size_t)((enc_rval.encoded+7)>>3),fd); fclose(fd); total_size = total_size + ((enc_rval.encoded+7)>>3); - return(total_size); } diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c index 9232b4d4be..45d56f24fa 100644 --- a/openair2/RRC/NR/rrc_gNB_nsa.c +++ b/openair2/RRC/NR/rrc_gNB_nsa.c @@ -40,7 +40,6 @@ #include "openair2/RRC/LTE/rrc_eNB_GTPV1U.h" void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList, x2ap_ENDC_sgnb_addition_req_t *m, NR_CG_ConfigInfo_IEs_t *cg_config_info) { - struct rrc_gNB_ue_context_s *ue_context_p = NULL; OCTET_STRING_t *ueCapabilityRAT_Container_nr = NULL; OCTET_STRING_t *ueCapabilityRAT_Container_MRDC = NULL; @@ -48,10 +47,11 @@ void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_Container asn_dec_rval_t dec_rval; AssertFatal(UE_CapabilityRAT_ContainerList!=NULL,"UE_CapabilityRAT_ContainerList is null\n"); AssertFatal((list_size=UE_CapabilityRAT_ContainerList->list.count) >= 2, "UE_CapabilityRAT_ContainerList->list.size %d < 2\n",UE_CapabilityRAT_ContainerList->list.count); - for (int i=0;ilist.array[i]->rat_Type == LTE_RAT_Type_nr) ueCapabilityRAT_Container_nr = &UE_CapabilityRAT_ContainerList->list.array[i]->ueCapabilityRAT_Container; else if (UE_CapabilityRAT_ContainerList->list.array[i]->rat_Type == LTE_RAT_Type_eutra_nr) ueCapabilityRAT_Container_MRDC = &UE_CapabilityRAT_ContainerList->list.array[i]->ueCapabilityRAT_Container; - } + } // decode and store capabilities ue_context_p = rrc_gNB_allocate_new_UE_context(rrc); @@ -65,10 +65,10 @@ void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_Container if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { LOG_E(RRC, "Failed to decode UE NR capabilities (%zu bytes) container size %lu\n", dec_rval.consumed,ueCapabilityRAT_Container_nr->size); - ASN_STRUCT_FREE(asn_DEF_NR_UE_NR_Capability, - ue_context_p->ue_context.UE_Capability_nr); - ue_context_p->ue_context.UE_Capability_nr = 0; - AssertFatal(1==0,"exiting\n"); + ASN_STRUCT_FREE(asn_DEF_NR_UE_NR_Capability, + ue_context_p->ue_context.UE_Capability_nr); + ue_context_p->ue_context.UE_Capability_nr = 0; + AssertFatal(1==0,"exiting\n"); } } @@ -80,172 +80,158 @@ void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_Container ueCapabilityRAT_Container_MRDC->size, 0, 0); if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { - LOG_E(RRC, "Failed to decode UE MRDC capabilities (%zu bytes)\n", dec_rval.consumed); - ASN_STRUCT_FREE(asn_DEF_NR_UE_MRDC_Capability, - ue_context_p->ue_context.UE_Capability_MRDC); - ue_context_p->ue_context.UE_Capability_MRDC = 0; - AssertFatal(1==0,"exiting\n"); + LOG_E(RRC, "Failed to decode UE MRDC capabilities (%zu bytes)\n", dec_rval.consumed); + ASN_STRUCT_FREE(asn_DEF_NR_UE_MRDC_Capability, + ue_context_p->ue_context.UE_Capability_MRDC); + ue_context_p->ue_context.UE_Capability_MRDC = 0; + AssertFatal(1==0,"exiting\n"); } } // dump ue_capabilities if ( LOG_DEBUGFLAG(DEBUG_ASN1 && ueCapabilityRAT_Container_nr != NULL) ) { - xer_fprint(stdout, &asn_DEF_NR_UE_NR_Capability, ue_context_p->ue_context.UE_Capability_nr); - } + xer_fprint(stdout, &asn_DEF_NR_UE_NR_Capability, ue_context_p->ue_context.UE_Capability_nr); + } if ( LOG_DEBUGFLAG(DEBUG_ASN1 && ueCapabilityRAT_Container_MRDC != NULL) ) { - xer_fprint(stdout, &asn_DEF_NR_UE_MRDC_Capability, ue_context_p->ue_context.UE_Capability_MRDC); - } - - if(cg_config_info->mcg_RB_Config) { - asn_dec_rval_t dec_rval = uper_decode(NULL, - &asn_DEF_NR_RadioBearerConfig, - (void**)&ue_context_p->ue_context.rb_config, - cg_config_info->mcg_RB_Config->buf, - cg_config_info->mcg_RB_Config->size, 0, 0); - - if((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { - AssertFatal(1==0,"[InterNode] Failed to decode mcg_rb_config (%zu bits), size of OCTET_STRING %lu\n", - dec_rval.consumed, cg_config_info->mcg_RB_Config->size); + xer_fprint(stdout, &asn_DEF_NR_UE_MRDC_Capability, ue_context_p->ue_context.UE_Capability_MRDC); + } + + if(cg_config_info && cg_config_info->mcg_RB_Config) { + asn_dec_rval_t dec_rval = uper_decode(NULL, + &asn_DEF_NR_RadioBearerConfig, + (void **)&ue_context_p->ue_context.rb_config, + cg_config_info->mcg_RB_Config->buf, + cg_config_info->mcg_RB_Config->size, 0, 0); + + if((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { + AssertFatal(1==0,"[InterNode] Failed to decode mcg_rb_config (%zu bits), size of OCTET_STRING %lu\n", + dec_rval.consumed, cg_config_info->mcg_RB_Config->size); } } - xer_fprint(stdout, &asn_DEF_NR_RadioBearerConfig, (const void*)ue_context_p->ue_context.rb_config); + + xer_fprint(stdout, &asn_DEF_NR_RadioBearerConfig, (const void *)ue_context_p->ue_context.rb_config); rrc_add_nsa_user(rrc,ue_context_p, m); } void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p, x2ap_ENDC_sgnb_addition_req_t *m) { - -// generate nr-Config-r15 containers for LTE RRC : inside message for X2 EN-DC (CG-Config Message from 38.331) - + // generate nr-Config-r15 containers for LTE RRC : inside message for X2 EN-DC (CG-Config Message from 38.331) rrc_gNB_carrier_data_t *carrier=&rrc->carrier; - MessageDef *msg; msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ_ACK); gtpv1u_enb_create_tunnel_req_t create_tunnel_req; gtpv1u_enb_create_tunnel_resp_t create_tunnel_resp; protocol_ctxt_t ctxt; - -// NR RRCReconfiguration - + // NR RRCReconfiguration AssertFatal(rrc->Nb_ue < MAX_NR_RRC_UE_CONTEXTS,"cannot add another UE\n"); - ue_context_p->ue_context.reconfig = calloc(1,sizeof(NR_RRCReconfiguration_t)); ue_context_p->ue_context.secondaryCellGroup = calloc(1,sizeof(NR_CellGroupConfig_t)); - memset((void*)ue_context_p->ue_context.reconfig,0,sizeof(NR_RRCReconfiguration_t)); + memset((void *)ue_context_p->ue_context.reconfig,0,sizeof(NR_RRCReconfiguration_t)); ue_context_p->ue_context.reconfig->rrc_TransactionIdentifier=0; ue_context_p->ue_context.reconfig->criticalExtensions.present = NR_RRCReconfiguration__criticalExtensions_PR_rrcReconfiguration; NR_RRCReconfiguration_IEs_t *reconfig_ies=calloc(1,sizeof(NR_RRCReconfiguration_IEs_t)); ue_context_p->ue_context.reconfig->criticalExtensions.choice.rrcReconfiguration = reconfig_ies; carrier->initial_csi_index[rrc->Nb_ue] = 0; fill_default_reconfig(carrier->servingcellconfigcommon, - reconfig_ies, - ue_context_p->ue_context.secondaryCellGroup, - carrier->pdsch_AntennaPorts, - carrier->initial_csi_index[rrc->Nb_ue]); - + reconfig_ies, + ue_context_p->ue_context.secondaryCellGroup, + carrier->pdsch_AntennaPorts, + carrier->initial_csi_index[rrc->Nb_ue]); ue_context_p->ue_context.rb_config = calloc(1,sizeof(NR_RRCReconfiguration_t)); - - //fill_default_rbconfig(ue_context_p->ue_context.rb_config,m, cg_config_info); ue_context_p->ue_id_rnti = ue_context_p->ue_context.secondaryCellGroup->spCellConfig->reconfigurationWithSync->newUE_Identity; NR_CG_Config_t *CG_Config = calloc(1,sizeof(*CG_Config)); - memset((void*)CG_Config,0,sizeof(*CG_Config)); - __attribute__((unused))int CG_Config_size = generate_CG_Config(rrc,CG_Config,ue_context_p->ue_context.reconfig,ue_context_p->ue_context.rb_config); + memset((void *)CG_Config,0,sizeof(*CG_Config)); + //int CG_Config_size = generate_CG_Config(rrc,CG_Config,ue_context_p->ue_context.reconfig,ue_context_p->ue_context.rb_config); + generate_CG_Config(rrc,CG_Config,ue_context_p->ue_context.reconfig,ue_context_p->ue_context.rb_config); - if(m!=NULL){ - uint8_t inde_list[m->nb_e_rabs_tobeadded]; - memset(inde_list, 0, m->nb_e_rabs_tobeadded*sizeof(uint8_t)); + if(m!=NULL) { + uint8_t inde_list[m->nb_e_rabs_tobeadded]; + memset(inde_list, 0, m->nb_e_rabs_tobeadded*sizeof(uint8_t)); - if (m->nb_e_rabs_tobeadded>0){ - for (int i=0; inb_e_rabs_tobeadded; i++){ - // Add the new E-RABs at the corresponding rrc ue context of the gNB - ue_context_p->ue_context.e_rab[i].param.e_rab_id = m->e_rabs_tobeadded[i].e_rab_id; - ue_context_p->ue_context.e_rab[i].param.gtp_teid = m->e_rabs_tobeadded[i].gtp_teid; - memcpy(&ue_context_p->ue_context.e_rab[i].param.sgw_addr, &m->e_rabs_tobeadded[i].sgw_addr, sizeof(transport_layer_addr_t)); - ue_context_p->ue_context.nb_of_e_rabs++; - //Fill the required E-RAB specific information for the creation of the S1-U tunnel between the gNB and the SGW - create_tunnel_req.eps_bearer_id[i] = ue_context_p->ue_context.e_rab[i].param.e_rab_id; - create_tunnel_req.sgw_S1u_teid[i] = ue_context_p->ue_context.e_rab[i].param.gtp_teid; - memcpy(&create_tunnel_req.sgw_addr[i], &ue_context_p->ue_context.e_rab[i].param.sgw_addr, sizeof(transport_layer_addr_t)); - inde_list[i] = i; - LOG_I(RRC,"S1-U tunnel: index %d target sgw ip %d.%d.%d.%d length %d gtp teid %u\n", - i, - create_tunnel_req.sgw_addr[i].buffer[0], - create_tunnel_req.sgw_addr[i].buffer[1], - create_tunnel_req.sgw_addr[i].buffer[2], - create_tunnel_req.sgw_addr[i].buffer[3], - create_tunnel_req.sgw_addr[i].length, - create_tunnel_req.sgw_S1u_teid[i]); - } - //PM: Is this where we should extract the rnti from? - create_tunnel_req.rnti = ue_context_p->ue_id_rnti; - create_tunnel_req.num_tunnels = m->nb_e_rabs_tobeadded; - RB_INSERT(rrc_nr_ue_tree_s, &RC.nrrrc[rrc->module_id]->rrc_ue_head, ue_context_p); + if (m->nb_e_rabs_tobeadded>0) { + for (int i=0; inb_e_rabs_tobeadded; i++) { + // Add the new E-RABs at the corresponding rrc ue context of the gNB + ue_context_p->ue_context.e_rab[i].param.e_rab_id = m->e_rabs_tobeadded[i].e_rab_id; + ue_context_p->ue_context.e_rab[i].param.gtp_teid = m->e_rabs_tobeadded[i].gtp_teid; + memcpy(&ue_context_p->ue_context.e_rab[i].param.sgw_addr, &m->e_rabs_tobeadded[i].sgw_addr, sizeof(transport_layer_addr_t)); + ue_context_p->ue_context.nb_of_e_rabs++; + //Fill the required E-RAB specific information for the creation of the S1-U tunnel between the gNB and the SGW + create_tunnel_req.eps_bearer_id[i] = ue_context_p->ue_context.e_rab[i].param.e_rab_id; + create_tunnel_req.sgw_S1u_teid[i] = ue_context_p->ue_context.e_rab[i].param.gtp_teid; + memcpy(&create_tunnel_req.sgw_addr[i], &ue_context_p->ue_context.e_rab[i].param.sgw_addr, sizeof(transport_layer_addr_t)); + inde_list[i] = i; + LOG_I(RRC,"S1-U tunnel: index %d target sgw ip %d.%d.%d.%d length %d gtp teid %u\n", + i, + create_tunnel_req.sgw_addr[i].buffer[0], + create_tunnel_req.sgw_addr[i].buffer[1], + create_tunnel_req.sgw_addr[i].buffer[2], + create_tunnel_req.sgw_addr[i].buffer[3], + create_tunnel_req.sgw_addr[i].length, + create_tunnel_req.sgw_S1u_teid[i]); + } - PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, rrc->module_id, GNB_FLAG_YES, ue_context_p->ue_id_rnti, 0, 0,rrc->module_id); - gtpv1u_create_s1u_tunnel( - ctxt.instance, - &create_tunnel_req, - &create_tunnel_resp); - rrc_gNB_process_GTPV1U_CREATE_TUNNEL_RESP( - &ctxt, - &create_tunnel_resp, - &inde_list[0]); - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).nb_e_rabs_admitted_tobeadded = m->nb_e_rabs_tobeadded; - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).target_assoc_id = m->target_assoc_id; + //PM: Is this where we should extract the rnti from? + create_tunnel_req.rnti = ue_context_p->ue_id_rnti; + create_tunnel_req.num_tunnels = m->nb_e_rabs_tobeadded; + RB_INSERT(rrc_nr_ue_tree_s, &RC.nrrrc[rrc->module_id]->rrc_ue_head, ue_context_p); + PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, rrc->module_id, GNB_FLAG_YES, ue_context_p->ue_id_rnti, 0, 0,rrc->module_id); + gtpv1u_create_s1u_tunnel( + ctxt.instance, + &create_tunnel_req, + &create_tunnel_resp); + rrc_gNB_process_GTPV1U_CREATE_TUNNEL_RESP( + &ctxt, + &create_tunnel_resp, + &inde_list[0]); + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).nb_e_rabs_admitted_tobeadded = m->nb_e_rabs_tobeadded; + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).target_assoc_id = m->target_assoc_id; - for(int i=0; iue_context.nb_of_e_rabs; i++){ - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].e_rab_id = ue_context_p->ue_context.e_rab[i].param.e_rab_id; - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gtp_teid = create_tunnel_resp.enb_S1u_teid[i]; - memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr, &create_tunnel_resp.enb_addr, sizeof(transport_layer_addr_t)); - - //The length field in the X2AP targetting structure is expected in bits but the create_tunnel_resp returns the address length in bytes - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.length = create_tunnel_resp.enb_addr.length*8; - - LOG_I(RRC,"S1-U create_tunnel_resp tunnel: index %d target gNB ip %d.%d.%d.%d length %d gtp teid %u\n", - i, - create_tunnel_resp.enb_addr.buffer[0], - create_tunnel_resp.enb_addr.buffer[1], - create_tunnel_resp.enb_addr.buffer[2], - create_tunnel_resp.enb_addr.buffer[3], - create_tunnel_resp.enb_addr.length, - create_tunnel_resp.enb_S1u_teid[i]); - LOG_I(RRC,"X2AP sGNB Addition Request: index %d target gNB ip %d.%d.%d.%d length %d gtp teid %u\n", - i, - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[0], - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[1], - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[2], - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[3], - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.length, - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gtp_teid); - } - } - else - LOG_W(RRC, "No E-RAB to be added received from SgNB Addition Request message \n"); + for(int i=0; iue_context.nb_of_e_rabs; i++) { + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].e_rab_id = ue_context_p->ue_context.e_rab[i].param.e_rab_id; + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gtp_teid = create_tunnel_resp.enb_S1u_teid[i]; + memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr, &create_tunnel_resp.enb_addr, sizeof(transport_layer_addr_t)); + //The length field in the X2AP targetting structure is expected in bits but the create_tunnel_resp returns the address length in bytes + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.length = create_tunnel_resp.enb_addr.length*8; + LOG_I(RRC,"S1-U create_tunnel_resp tunnel: index %d target gNB ip %d.%d.%d.%d length %d gtp teid %u\n", + i, + create_tunnel_resp.enb_addr.buffer[0], + create_tunnel_resp.enb_addr.buffer[1], + create_tunnel_resp.enb_addr.buffer[2], + create_tunnel_resp.enb_addr.buffer[3], + create_tunnel_resp.enb_addr.length, + create_tunnel_resp.enb_S1u_teid[i]); + LOG_I(RRC,"X2AP sGNB Addition Request: index %d target gNB ip %d.%d.%d.%d length %d gtp teid %u\n", + i, + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[0], + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[1], + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[2], + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[3], + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.length, + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gtp_teid); + } + } else + LOG_W(RRC, "No E-RAB to be added received from SgNB Addition Request message \n"); } - //X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).rrc_buffer_size = CG_Config_size; //Need to verify correct value for the buffer_size // Send to X2 entity to transport to MeNB asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CG_Config, - NULL, - (void *)CG_Config, - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).rrc_buffer, - 1024); - + NULL, + (void *)CG_Config, + X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).rrc_buffer, + 1024); X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).rrc_buffer_size = (enc_rval.encoded+7)>>3; - itti_send_msg_to_task(TASK_X2AP, ENB_MODULE_ID_TO_INSTANCE(0), msg); //Check right id instead of hardcoding - rrc->Nb_ue++; // configure MAC and RLC rrc_mac_config_req_gNB(rrc->module_id, - rrc->carrier.ssb_SubcarrierOffset, + rrc->carrier.ssb_SubcarrierOffset, rrc->carrier.pdsch_AntennaPorts, - NULL, - 1, // add_ue flag - ue_context_p->ue_id_rnti, - ue_context_p->ue_context.secondaryCellGroup); + NULL, + 1, // add_ue flag + ue_context_p->ue_id_rnti, + ue_context_p->ue_context.secondaryCellGroup); } diff --git a/openair2/RRC/NR/rrc_gNB_reconfig.c b/openair2/RRC/NR/rrc_gNB_reconfig.c index fd8f93462f..8f93b42ef4 100644 --- a/openair2/RRC/NR/rrc_gNB_reconfig.c +++ b/openair2/RRC/NR/rrc_gNB_reconfig.c @@ -49,23 +49,19 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellconfigcommon, - NR_CellGroupConfig_t *secondaryCellGroup, - int scg_id, - int servCellIndex, - int n_physical_antenna_ports, - int initial_csi_index) { + NR_CellGroupConfig_t *secondaryCellGroup, + int scg_id, + int servCellIndex, + int n_physical_antenna_ports, + int initial_csi_index) { AssertFatal(servingcellconfigcommon!=NULL,"servingcellconfigcommon is null\n"); AssertFatal(secondaryCellGroup!=NULL,"secondaryCellGroup is null\n"); - memset(secondaryCellGroup,0,sizeof(NR_CellGroupConfig_t)); secondaryCellGroup->cellGroupId = scg_id; - NR_RLC_BearerConfig_t *RLC_BearerConfig = calloc(1,sizeof(*RLC_BearerConfig)); - RLC_BearerConfig->logicalChannelIdentity = 4; RLC_BearerConfig->servedRadioBearer = calloc(1,sizeof(*RLC_BearerConfig->servedRadioBearer)); - RLC_BearerConfig->servedRadioBearer->present = NR_RLC_BearerConfig__servedRadioBearer_PR_drb_Identity; - + RLC_BearerConfig->servedRadioBearer->present = NR_RLC_BearerConfig__servedRadioBearer_PR_drb_Identity; RLC_BearerConfig->servedRadioBearer->choice.drb_Identity=1; RLC_BearerConfig->reestablishRLC=calloc(1,sizeof(*RLC_BearerConfig->reestablishRLC)); *RLC_BearerConfig->reestablishRLC=NR_RLC_BearerConfig__reestablishRLC_true; @@ -73,17 +69,15 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco RLC_BearerConfig->rlc_Config->present = NR_RLC_Config_PR_am; RLC_BearerConfig->rlc_Config->choice.am = calloc(1,sizeof(*RLC_BearerConfig->rlc_Config->choice.am)); RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.sn_FieldLength = calloc(1,sizeof(*RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.sn_FieldLength)); - *RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.sn_FieldLength = NR_SN_FieldLengthAM_size18; + *RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.sn_FieldLength = NR_SN_FieldLengthAM_size18; RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.t_PollRetransmit = NR_T_PollRetransmit_ms45; RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.pollPDU = NR_PollPDU_p64; RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.pollByte = NR_PollByte_kB500; RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.maxRetxThreshold = NR_UL_AM_RLC__maxRetxThreshold_t32; - RLC_BearerConfig->rlc_Config->choice.am->dl_AM_RLC.sn_FieldLength = calloc(1,sizeof(*RLC_BearerConfig->rlc_Config->choice.am->dl_AM_RLC.sn_FieldLength)); *RLC_BearerConfig->rlc_Config->choice.am->dl_AM_RLC.sn_FieldLength = NR_SN_FieldLengthAM_size18; RLC_BearerConfig->rlc_Config->choice.am->dl_AM_RLC.t_Reassembly = NR_T_Reassembly_ms15; RLC_BearerConfig->rlc_Config->choice.am->dl_AM_RLC.t_StatusProhibit = NR_T_StatusProhibit_ms15; - RLC_BearerConfig->mac_LogicalChannelConfig = calloc(1,sizeof(*RLC_BearerConfig->mac_LogicalChannelConfig)); RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters = calloc(1,sizeof(*RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters)); RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->priority = 1; @@ -99,10 +93,8 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->logicalChannelSR_Mask = false; RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->logicalChannelSR_DelayTimerApplied = false; RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->bitRateQueryProhibitTimer = NULL; - secondaryCellGroup->rlc_BearerToAddModList = calloc(1,sizeof(*secondaryCellGroup->rlc_BearerToAddModList)); ASN_SEQUENCE_ADD(&secondaryCellGroup->rlc_BearerToAddModList->list, RLC_BearerConfig); - secondaryCellGroup->mac_CellGroupConfig=calloc(1,sizeof(*secondaryCellGroup->mac_CellGroupConfig)); secondaryCellGroup->mac_CellGroupConfig->drx_Config = NULL; secondaryCellGroup->mac_CellGroupConfig->schedulingRequestConfig = NULL; @@ -126,25 +118,20 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup->dummy=false; secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup->phr_Type2OtherCell = false; secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup->phr_ModeOtherCG = NR_PHR_Config__phr_ModeOtherCG_real; - secondaryCellGroup->mac_CellGroupConfig->skipUplinkTxDynamic=false; secondaryCellGroup->mac_CellGroupConfig->ext1 = NULL; - - secondaryCellGroup->physicalCellGroupConfig = calloc(1,sizeof(*secondaryCellGroup->physicalCellGroupConfig)); - secondaryCellGroup->physicalCellGroupConfig->harq_ACK_SpatialBundlingPUCCH=NULL; secondaryCellGroup->physicalCellGroupConfig->harq_ACK_SpatialBundlingPUSCH=NULL; secondaryCellGroup->physicalCellGroupConfig->p_NR_FR1=calloc(1,sizeof(*secondaryCellGroup->physicalCellGroupConfig->p_NR_FR1)); *secondaryCellGroup->physicalCellGroupConfig->p_NR_FR1=20; - secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook=NR_PhysicalCellGroupConfig__pdsch_HARQ_ACK_Codebook_dynamic; + secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook=NR_PhysicalCellGroupConfig__pdsch_HARQ_ACK_Codebook_dynamic; secondaryCellGroup->physicalCellGroupConfig->tpc_SRS_RNTI=NULL; secondaryCellGroup->physicalCellGroupConfig->tpc_PUCCH_RNTI=NULL; secondaryCellGroup->physicalCellGroupConfig->tpc_PUSCH_RNTI=NULL; secondaryCellGroup->physicalCellGroupConfig->sp_CSI_RNTI=NULL; secondaryCellGroup->physicalCellGroupConfig->cs_RNTI=NULL; secondaryCellGroup->physicalCellGroupConfig->ext1=NULL; - secondaryCellGroup->spCellConfig = calloc(1,sizeof(*secondaryCellGroup->spCellConfig)); secondaryCellGroup->spCellConfig->servCellIndex = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->servCellIndex)); *secondaryCellGroup->spCellConfig->servCellIndex = servCellIndex; @@ -154,7 +141,6 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->spCellConfig->reconfigurationWithSync->t304=NR_ReconfigurationWithSync__t304_ms2000; secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated = NULL; secondaryCellGroup->spCellConfig->reconfigurationWithSync->ext1 = NULL; - /* contention free ra */ secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated = calloc(1,sizeof(struct NR_ReconfigurationWithSync__rach_ConfigDedicated)); secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->present= NR_ReconfigurationWithSync__rach_ConfigDedicated_PR_uplink; @@ -162,7 +148,8 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra= calloc(1,sizeof(struct NR_CFRA)); secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->ra_Prioritization= NULL; secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions= calloc(1,sizeof(struct NR_CFRA__occasions)); - memcpy(&secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions->rach_ConfigGeneric, &servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric, sizeof(NR_RACH_ConfigGeneric_t)); + memcpy(&secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions->rach_ConfigGeneric, + &servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric, sizeof(NR_RACH_ConfigGeneric_t)); //secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions->ssb_perRACH_Occasion= calloc(1,sizeof(long)); //*secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions->ssb_perRACH_Occasion = NR_CFRA__occasions__ssb_perRACH_Occasion_one; secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions->ssb_perRACH_Occasion= NULL; @@ -174,7 +161,6 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco ssbElem->ra_PreambleIndex= 63; ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->resources.choice.ssb->ssb_ResourceList.list,ssbElem); secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->ext1 = NULL; - secondaryCellGroup->spCellConfig->rlf_TimersAndConstants = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->rlf_TimersAndConstants)); secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->present = NR_SetupRelease_RLF_TimersAndConstants_PR_setup; secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup)); @@ -183,1847 +169,1748 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup->n311 = NR_RLF_TimersAndConstants__n311_n1; secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup->ext1 = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup->ext1)); secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup->ext1->t311_v1530 = NR_RLF_TimersAndConstants__ext1__t311_v1530_ms30000; - secondaryCellGroup->spCellConfig->rlmInSyncOutOfSyncThreshold = NULL; - - - secondaryCellGroup->spCellConfig->spCellConfigDedicated = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated)); secondaryCellGroup->spCellConfig->spCellConfigDedicated->tdd_UL_DL_ConfigurationDedicated = NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdcch_Config=NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config)); secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->present = NR_SetupRelease_PDSCH_Config_PR_setup; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup = calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup)); secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dataScramblingIdentityPDSCH = NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA = calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA)); secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->present= NR_SetupRelease_DMRS_DownlinkConfig_PR_setup; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup = calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->maxLength=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->scramblingID0=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->scramblingID1=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->phaseTrackingRS=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition)); + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = + NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList=calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList)); + NR_TCI_State_t *tci0=calloc(1,sizeof(*tci0)); + tci0->tci_StateId=0; + tci0->qcl_Type1.cell=NULL; + tci0->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci0->qcl_Type1.bwp_Id)); + *tci0->qcl_Type1.bwp_Id=1; + tci0->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tci0->qcl_Type1.referenceSignal.choice.csi_rs = 2; + tci0->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci0); + NR_TCI_State_t *tci1=calloc(1,sizeof(*tci1)); + tci1->tci_StateId=1; + tci1->qcl_Type1.cell=NULL; + tci1->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci1->qcl_Type1.bwp_Id)); + *tci1->qcl_Type1.bwp_Id=1; + tci1->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tci1->qcl_Type1.referenceSignal.choice.csi_rs = 6; + tci1->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci1); + NR_TCI_State_t *tci2=calloc(1,sizeof(*tci2)); + tci2->tci_StateId=2; + tci2->qcl_Type1.cell=NULL; + tci2->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci2->qcl_Type1.bwp_Id)); + *tci2->qcl_Type1.bwp_Id=1; + tci2->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tci2->qcl_Type1.referenceSignal.choice.csi_rs = 10; + tci2->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci2); + NR_TCI_State_t *tci3=calloc(1,sizeof(*tci3)); + tci3->tci_StateId=3; + tci3->qcl_Type1.cell=NULL; + tci3->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci3->qcl_Type1.bwp_Id)); + *tci3->qcl_Type1.bwp_Id=1; + tci3->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tci3->qcl_Type1.referenceSignal.choice.csi_rs = 14; + tci3->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci3); + NR_TCI_State_t *tci4=calloc(1,sizeof(*tci4)); + tci4->tci_StateId=4; + tci4->qcl_Type1.cell=NULL; + tci4->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci4->qcl_Type1.bwp_Id)); + *tci4->qcl_Type1.bwp_Id=1; + tci4->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tci4->qcl_Type1.referenceSignal.choice.csi_rs = 18; + tci4->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci4); + NR_TCI_State_t *tci5=calloc(1,sizeof(*tci5)); + tci5->tci_StateId=5; + tci5->qcl_Type1.cell=NULL; + tci5->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci5->qcl_Type1.bwp_Id)); + *tci5->qcl_Type1.bwp_Id=1; + tci5->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tci5->qcl_Type1.referenceSignal.choice.csi_rs = 22; + tci5->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci5); + NR_TCI_State_t *tci6=calloc(1,sizeof(*tci6)); + tci6->tci_StateId=6; + tci6->qcl_Type1.cell=NULL; + tci6->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci6->qcl_Type1.bwp_Id)); + *tci6->qcl_Type1.bwp_Id=1; + tci6->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tci6->qcl_Type1.referenceSignal.choice.csi_rs = 26; + tci6->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci6); + NR_TCI_State_t *tci7=calloc(1,sizeof(*tci7)); + tci7->tci_StateId=7; + tci7->qcl_Type1.cell=NULL; + tci7->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci7->qcl_Type1.bwp_Id)); + *tci7->qcl_Type1.bwp_Id=1; + tci7->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tci7->qcl_Type1.referenceSignal.choice.csi_rs = 30; + tci7->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci7); + NR_TCI_State_t *tci8=calloc(1,sizeof(*tci8)); + tci8->tci_StateId=8; + tci8->qcl_Type1.cell=NULL; + tci8->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci8->qcl_Type1.bwp_Id)); + *tci8->qcl_Type1.bwp_Id=1; + tci8->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tci8->qcl_Type1.referenceSignal.choice.ssb = 0; + tci8->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci8); + NR_TCI_State_t *tci9=calloc(1,sizeof(*tci9)); + tci9->tci_StateId=9; + tci9->qcl_Type1.cell=NULL; + tci9->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci9->qcl_Type1.bwp_Id)); + *tci9->qcl_Type1.bwp_Id=1; + tci9->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tci9->qcl_Type1.referenceSignal.choice.ssb = 1; + tci9->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci9); + NR_TCI_State_t *tci10=calloc(1,sizeof(*tci10)); + tci10->tci_StateId=10; + tci10->qcl_Type1.cell=NULL; + tci10->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci10->qcl_Type1.bwp_Id)); + *tci10->qcl_Type1.bwp_Id=1; + tci10->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tci10->qcl_Type1.referenceSignal.choice.ssb = 2; + tci10->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci10); + NR_TCI_State_t *tci11=calloc(1,sizeof(*tci11)); + tci11->tci_StateId=11; + tci11->qcl_Type1.cell=NULL; + tci11->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci11->qcl_Type1.bwp_Id)); + *tci11->qcl_Type1.bwp_Id=1; + tci11->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tci11->qcl_Type1.referenceSignal.choice.ssb = 3; + tci11->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci11); + NR_TCI_State_t *tci12=calloc(1,sizeof(*tci12)); + tci12->tci_StateId=12; + tci12->qcl_Type1.cell=NULL; + tci12->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci12->qcl_Type1.bwp_Id)); + *tci12->qcl_Type1.bwp_Id=1; + tci12->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tci12->qcl_Type1.referenceSignal.choice.ssb = 4; + tci12->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci12); + NR_TCI_State_t *tci13=calloc(1,sizeof(*tci13)); + tci13->tci_StateId=13; + tci13->qcl_Type1.cell=NULL; + tci13->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci13->qcl_Type1.bwp_Id)); + *tci13->qcl_Type1.bwp_Id=1; + tci13->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tci13->qcl_Type1.referenceSignal.choice.ssb = 5; + tci13->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci13); + NR_TCI_State_t *tci14=calloc(1,sizeof(*tci14)); + tci14->tci_StateId=14; + tci14->qcl_Type1.cell=NULL; + tci14->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci14->qcl_Type1.bwp_Id)); + *tci14->qcl_Type1.bwp_Id=1; + tci14->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tci14->qcl_Type1.referenceSignal.choice.ssb = 6; + tci14->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci14); + NR_TCI_State_t *tci15=calloc(1,sizeof(*tci15)); + tci15->tci_StateId=15; + tci15->qcl_Type1.cell=NULL; + tci15->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci15->qcl_Type1.bwp_Id)); + *tci15->qcl_Type1.bwp_Id=1; + tci15->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tci15->qcl_Type1.referenceSignal.choice.ssb = 7; + tci15->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci15); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternToReleaseList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup1=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup2=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rbg_Size=NR_PDSCH_Config__rbg_Size_config1; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->mcs_Table=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI)); + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = NR_PDSCH_Config__maxNrofCodeWordsScheduledByDCI_n1; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.present = NR_PDSCH_Config__prb_BundlingType_PR_staticBundling; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling = calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = + calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize)); + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = + NR_PDSCH_Config__prb_BundlingType__staticBundling__bundleSize_wideband; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToAddModList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToReleaseList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToAddModList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->sps_Config = NULL; //calloc(1,sizeof(struct NR_SetupRelease_SPS_Config)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig = calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->present = NR_SetupRelease_RadioLinkMonitoringConfig_PR_setup; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup = calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->failureDetectionResourcesToAddModList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->failureDetectionResourcesToReleaseList=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount)); + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = + NR_RadioLinkMonitoringConfig__beamFailureInstanceMaxCount_n3; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer)); + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = + NR_RadioLinkMonitoringConfig__beamFailureDetectionTimer_pbfd2; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToReleaseList= NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList)); + NR_BWP_Downlink_t *bwp=calloc(1,sizeof(*bwp)); + bwp->bwp_Id=1; + bwp->bwp_Common=calloc(1,sizeof(*bwp->bwp_Common)); + // copy common BWP size from initial BWP except for bandwdith + memcpy((void *)&bwp->bwp_Common->genericParameters, + &servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->genericParameters, + sizeof(bwp->bwp_Common->genericParameters)); + bwp->bwp_Common->genericParameters.locationAndBandwidth=PRBalloc_to_locationandbandwidth( + servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth,0); + bwp->bwp_Common->pdcch_ConfigCommon=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon)); + bwp->bwp_Common->pdcch_ConfigCommon->present = NR_SetupRelease_PDCCH_ConfigCommon_PR_setup; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup = calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup)); + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->controlResourceSetZero=NULL; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet)); + NR_ControlResourceSet_t *coreset = calloc(1,sizeof(*coreset)); + coreset->controlResourceSetId=1; + // frequencyDomainResources '11111111 11111111 00000000 00000000 00000000 00000'B, + coreset->frequencyDomainResources.buf = calloc(1,6); + coreset->frequencyDomainResources.buf[0] = 0xff; + coreset->frequencyDomainResources.buf[1] = 0xff; + coreset->frequencyDomainResources.buf[2] = 0; + coreset->frequencyDomainResources.buf[3] = 0; + coreset->frequencyDomainResources.buf[4] = 0; + coreset->frequencyDomainResources.buf[5] = 0; + coreset->frequencyDomainResources.size = 6; + coreset->frequencyDomainResources.bits_unused = 3; + coreset->duration=1; + coreset->cce_REG_MappingType.present = NR_ControlResourceSet__cce_REG_MappingType_PR_nonInterleaved; + coreset->precoderGranularity = NR_ControlResourceSet__precoderGranularity_sameAsREG_bundle; + coreset->tci_StatesPDCCH_ToAddList=calloc(1,sizeof(*coreset->tci_StatesPDCCH_ToAddList)); + NR_TCI_StateId_t *tci[8]; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->maxLength=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->scramblingID0=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->scramblingID1=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->phaseTrackingRS=NULL; + for (int i=0; i<8; i++) { + tci[i]=calloc(1,sizeof(*tci[i])); + *tci[i] = i; + ASN_SEQUENCE_ADD(&coreset->tci_StatesPDCCH_ToAddList->list,tci[i]); + } - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition)); - *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0; + coreset->tci_StatesPDCCH_ToReleaseList = NULL; + coreset->tci_PresentInDCI = NULL; + coreset->pdcch_DMRS_ScramblingID = NULL; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet = coreset; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->searchSpaceZero=NULL; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList=NULL; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList)); + NR_SearchSpace_t *ss=calloc(1,sizeof(*ss)); + ss->searchSpaceId = 1; + ss->controlResourceSetId=calloc(1,sizeof(*ss->controlResourceSetId)); + *ss->controlResourceSetId=1; + ss->monitoringSlotPeriodicityAndOffset = calloc(1,sizeof(*ss->monitoringSlotPeriodicityAndOffset)); + ss->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1; + ss->duration=NULL; + ss->monitoringSymbolsWithinSlot = calloc(1,sizeof(*ss->monitoringSymbolsWithinSlot)); + ss->monitoringSymbolsWithinSlot->buf = calloc(1,2); + // should be '1100 0000 0000 00'B (LSB first!), first two symols in slot, adjust if needed + ss->monitoringSymbolsWithinSlot->buf[1] = 0; + ss->monitoringSymbolsWithinSlot->buf[0] = (1<<7) | (1<<6); + ss->monitoringSymbolsWithinSlot->size = 2; + ss->monitoringSymbolsWithinSlot->bits_unused = 2; + ss->nrofCandidates = calloc(1,sizeof(*ss->nrofCandidates)); + ss->nrofCandidates->aggregationLevel1 = NR_SearchSpace__nrofCandidates__aggregationLevel1_n0; + ss->nrofCandidates->aggregationLevel2 = NR_SearchSpace__nrofCandidates__aggregationLevel2_n0; + ss->nrofCandidates->aggregationLevel4 = NR_SearchSpace__nrofCandidates__aggregationLevel4_n1; + ss->nrofCandidates->aggregationLevel8 = NR_SearchSpace__nrofCandidates__aggregationLevel8_n0; + ss->nrofCandidates->aggregationLevel16 = NR_SearchSpace__nrofCandidates__aggregationLevel16_n0; + ss->searchSpaceType = calloc(1,sizeof(*ss->searchSpaceType)); + ss->searchSpaceType->present = NR_SearchSpace__searchSpaceType_PR_common; + ss->searchSpaceType->choice.common=calloc(1,sizeof(*ss->searchSpaceType->choice.common)); + ss->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0 = calloc(1,sizeof(*ss->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0)); + ASN_SEQUENCE_ADD(&bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList->list,ss); + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->searchSpaceSIB1=NULL; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->searchSpaceOtherSystemInformation=NULL; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->pagingSearchSpace=NULL; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace)); + *bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace=1; + bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ext1=NULL; + bwp->bwp_Common->pdsch_ConfigCommon=calloc(1,sizeof(*bwp->bwp_Common->pdsch_ConfigCommon)); + bwp->bwp_Common->pdsch_ConfigCommon->present = NR_SetupRelease_PDSCH_ConfigCommon_PR_setup; + bwp->bwp_Common->pdsch_ConfigCommon->choice.setup = calloc(1,sizeof(*bwp->bwp_Common->pdsch_ConfigCommon->choice.setup)); + bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList = calloc(1,sizeof(*bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList)); + // copy PDSCH TimeDomainResourceAllocation from InitialBWP + NR_PDSCH_TimeDomainResourceAllocation_t *pdschi; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList)); - - NR_TCI_State_t*tci0=calloc(1,sizeof(*tci0)); - tci0->tci_StateId=0; - tci0->qcl_Type1.cell=NULL; - tci0->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci0->qcl_Type1.bwp_Id)); - *tci0->qcl_Type1.bwp_Id=1; - tci0->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tci0->qcl_Type1.referenceSignal.choice.csi_rs = 2; - tci0->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci0); - - NR_TCI_State_t*tci1=calloc(1,sizeof(*tci1)); - tci1->tci_StateId=1; - tci1->qcl_Type1.cell=NULL; - tci1->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci1->qcl_Type1.bwp_Id)); - *tci1->qcl_Type1.bwp_Id=1; - tci1->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tci1->qcl_Type1.referenceSignal.choice.csi_rs = 6; - tci1->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci1); - - NR_TCI_State_t*tci2=calloc(1,sizeof(*tci2)); - tci2->tci_StateId=2; - tci2->qcl_Type1.cell=NULL; - tci2->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci2->qcl_Type1.bwp_Id)); - *tci2->qcl_Type1.bwp_Id=1; - tci2->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tci2->qcl_Type1.referenceSignal.choice.csi_rs = 10; - tci2->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci2); - - NR_TCI_State_t *tci3=calloc(1,sizeof(*tci3)); - tci3->tci_StateId=3; - tci3->qcl_Type1.cell=NULL; - tci3->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci3->qcl_Type1.bwp_Id)); - *tci3->qcl_Type1.bwp_Id=1; - tci3->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tci3->qcl_Type1.referenceSignal.choice.csi_rs = 14; - tci3->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci3); - - NR_TCI_State_t*tci4=calloc(1,sizeof(*tci4)); - tci4->tci_StateId=4; - tci4->qcl_Type1.cell=NULL; - tci4->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci4->qcl_Type1.bwp_Id)); - *tci4->qcl_Type1.bwp_Id=1; - tci4->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tci4->qcl_Type1.referenceSignal.choice.csi_rs = 18; - tci4->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci4); - - NR_TCI_State_t*tci5=calloc(1,sizeof(*tci5)); - tci5->tci_StateId=5; - tci5->qcl_Type1.cell=NULL; - tci5->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci5->qcl_Type1.bwp_Id)); - *tci5->qcl_Type1.bwp_Id=1; - tci5->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tci5->qcl_Type1.referenceSignal.choice.csi_rs = 22; - tci5->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci5); - - NR_TCI_State_t*tci6=calloc(1,sizeof(*tci6)); - tci6->tci_StateId=6; - tci6->qcl_Type1.cell=NULL; - tci6->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci6->qcl_Type1.bwp_Id)); - *tci6->qcl_Type1.bwp_Id=1; - tci6->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tci6->qcl_Type1.referenceSignal.choice.csi_rs = 26; - tci6->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci6); - - NR_TCI_State_t*tci7=calloc(1,sizeof(*tci7)); - tci7->tci_StateId=7; - tci7->qcl_Type1.cell=NULL; - tci7->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci7->qcl_Type1.bwp_Id)); - *tci7->qcl_Type1.bwp_Id=1; - tci7->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tci7->qcl_Type1.referenceSignal.choice.csi_rs = 30; - tci7->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci7); - - NR_TCI_State_t*tci8=calloc(1,sizeof(*tci8)); - tci8->tci_StateId=8; - tci8->qcl_Type1.cell=NULL; - tci8->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci8->qcl_Type1.bwp_Id)); - *tci8->qcl_Type1.bwp_Id=1; - tci8->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tci8->qcl_Type1.referenceSignal.choice.ssb = 0; - tci8->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci8); - - NR_TCI_State_t*tci9=calloc(1,sizeof(*tci9)); - tci9->tci_StateId=9; - tci9->qcl_Type1.cell=NULL; - tci9->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci9->qcl_Type1.bwp_Id)); - *tci9->qcl_Type1.bwp_Id=1; - tci9->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tci9->qcl_Type1.referenceSignal.choice.ssb = 1; - tci9->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci9); - - NR_TCI_State_t*tci10=calloc(1,sizeof(*tci10)); - tci10->tci_StateId=10; - tci10->qcl_Type1.cell=NULL; - tci10->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci10->qcl_Type1.bwp_Id)); - *tci10->qcl_Type1.bwp_Id=1; - tci10->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tci10->qcl_Type1.referenceSignal.choice.ssb = 2; - tci10->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci10); - - NR_TCI_State_t*tci11=calloc(1,sizeof(*tci11)); - tci11->tci_StateId=11; - tci11->qcl_Type1.cell=NULL; - tci11->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci11->qcl_Type1.bwp_Id)); - *tci11->qcl_Type1.bwp_Id=1; - tci11->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tci11->qcl_Type1.referenceSignal.choice.ssb = 3; - tci11->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci11); - - NR_TCI_State_t*tci12=calloc(1,sizeof(*tci12)); - tci12->tci_StateId=12; - tci12->qcl_Type1.cell=NULL; - tci12->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci12->qcl_Type1.bwp_Id)); - *tci12->qcl_Type1.bwp_Id=1; - tci12->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tci12->qcl_Type1.referenceSignal.choice.ssb = 4; - tci12->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci12); - - NR_TCI_State_t*tci13=calloc(1,sizeof(*tci13)); - tci13->tci_StateId=13; - tci13->qcl_Type1.cell=NULL; - tci13->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci13->qcl_Type1.bwp_Id)); - *tci13->qcl_Type1.bwp_Id=1; - tci13->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tci13->qcl_Type1.referenceSignal.choice.ssb = 5; - tci13->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci13); - - NR_TCI_State_t*tci14=calloc(1,sizeof(*tci14)); - tci14->tci_StateId=14; - tci14->qcl_Type1.cell=NULL; - tci14->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci14->qcl_Type1.bwp_Id)); - *tci14->qcl_Type1.bwp_Id=1; - tci14->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tci14->qcl_Type1.referenceSignal.choice.ssb = 6; - tci14->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci14); - - NR_TCI_State_t*tci15=calloc(1,sizeof(*tci15)); - tci15->tci_StateId=15; - tci15->qcl_Type1.cell=NULL; - tci15->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci15->qcl_Type1.bwp_Id)); - *tci15->qcl_Type1.bwp_Id=1; - tci15->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tci15->qcl_Type1.referenceSignal.choice.ssb = 7; - tci15->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci15); - - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternToReleaseList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup1=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup2=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rbg_Size=NR_PDSCH_Config__rbg_Size_config1; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->mcs_Table=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI)); - *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = NR_PDSCH_Config__maxNrofCodeWordsScheduledByDCI_n1; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.present = NR_PDSCH_Config__prb_BundlingType_PR_staticBundling; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = - calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize)); - *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = NR_PDSCH_Config__prb_BundlingType__staticBundling__bundleSize_wideband; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToAddModList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToReleaseList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToAddModList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->sps_Config = NULL; //calloc(1,sizeof(struct NR_SetupRelease_SPS_Config)); - - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->present = NR_SetupRelease_RadioLinkMonitoringConfig_PR_setup; - - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->failureDetectionResourcesToAddModList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->failureDetectionResourcesToReleaseList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount)); - *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = NR_RadioLinkMonitoringConfig__beamFailureInstanceMaxCount_n3; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer)); - *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = NR_RadioLinkMonitoringConfig__beamFailureDetectionTimer_pbfd2; - - secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToReleaseList= NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList)); - - NR_BWP_Downlink_t *bwp=calloc(1,sizeof(*bwp)); - bwp->bwp_Id=1; - bwp->bwp_Common=calloc(1,sizeof(*bwp->bwp_Common)); - // copy common BWP size from initial BWP except for bandwdith - memcpy((void*)&bwp->bwp_Common->genericParameters, - &servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->genericParameters, - sizeof(bwp->bwp_Common->genericParameters)); - bwp->bwp_Common->genericParameters.locationAndBandwidth=PRBalloc_to_locationandbandwidth(servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth,0); - - - bwp->bwp_Common->pdcch_ConfigCommon=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon)); - bwp->bwp_Common->pdcch_ConfigCommon->present = NR_SetupRelease_PDCCH_ConfigCommon_PR_setup; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup = calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup)); - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->controlResourceSetZero=NULL; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet)); - - NR_ControlResourceSet_t *coreset = calloc(1,sizeof(*coreset)); - coreset->controlResourceSetId=1; - // frequencyDomainResources '11111111 11111111 00000000 00000000 00000000 00000'B, - coreset->frequencyDomainResources.buf = calloc(1,6); - coreset->frequencyDomainResources.buf[0] = 0xff; - coreset->frequencyDomainResources.buf[1] = 0xff; - coreset->frequencyDomainResources.buf[2] = 0; - coreset->frequencyDomainResources.buf[3] = 0; - coreset->frequencyDomainResources.buf[4] = 0; - coreset->frequencyDomainResources.buf[5] = 0; - coreset->frequencyDomainResources.size = 6; - coreset->frequencyDomainResources.bits_unused = 3; - coreset->duration=1; - coreset->cce_REG_MappingType.present = NR_ControlResourceSet__cce_REG_MappingType_PR_nonInterleaved; - coreset->precoderGranularity = NR_ControlResourceSet__precoderGranularity_sameAsREG_bundle; - - coreset->tci_StatesPDCCH_ToAddList=calloc(1,sizeof(*coreset->tci_StatesPDCCH_ToAddList)); - NR_TCI_StateId_t *tci[8]; - for (int i=0;i<8;i++) { - tci[i]=calloc(1,sizeof(*tci[i])); - *tci[i] = i; - ASN_SEQUENCE_ADD(&coreset->tci_StatesPDCCH_ToAddList->list,tci[i]); - } - coreset->tci_StatesPDCCH_ToReleaseList = NULL; - coreset->tci_PresentInDCI = NULL; - coreset->pdcch_DMRS_ScramblingID = NULL; - - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet = coreset; - - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->searchSpaceZero=NULL; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList=NULL; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList)); - - NR_SearchSpace_t *ss=calloc(1,sizeof(*ss)); - ss->searchSpaceId = 1; - ss->controlResourceSetId=calloc(1,sizeof(*ss->controlResourceSetId)); - *ss->controlResourceSetId=1; - ss->monitoringSlotPeriodicityAndOffset = calloc(1,sizeof(*ss->monitoringSlotPeriodicityAndOffset)); - ss->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1; - ss->duration=NULL; - ss->monitoringSymbolsWithinSlot = calloc(1,sizeof(*ss->monitoringSymbolsWithinSlot)); - ss->monitoringSymbolsWithinSlot->buf = calloc(1,2); - // should be '1100 0000 0000 00'B (LSB first!), first two symols in slot, adjust if needed - ss->monitoringSymbolsWithinSlot->buf[1] = 0; - ss->monitoringSymbolsWithinSlot->buf[0] = (1<<7) | (1<<6); - ss->monitoringSymbolsWithinSlot->size = 2; - ss->monitoringSymbolsWithinSlot->bits_unused = 2; - ss->nrofCandidates = calloc(1,sizeof(*ss->nrofCandidates)); - ss->nrofCandidates->aggregationLevel1 = NR_SearchSpace__nrofCandidates__aggregationLevel1_n0; - ss->nrofCandidates->aggregationLevel2 = NR_SearchSpace__nrofCandidates__aggregationLevel2_n0; - ss->nrofCandidates->aggregationLevel4 = NR_SearchSpace__nrofCandidates__aggregationLevel4_n1; - ss->nrofCandidates->aggregationLevel8 = NR_SearchSpace__nrofCandidates__aggregationLevel8_n0; - ss->nrofCandidates->aggregationLevel16 = NR_SearchSpace__nrofCandidates__aggregationLevel16_n0; - ss->searchSpaceType = calloc(1,sizeof(*ss->searchSpaceType)); - ss->searchSpaceType->present = NR_SearchSpace__searchSpaceType_PR_common; - ss->searchSpaceType->choice.common=calloc(1,sizeof(*ss->searchSpaceType->choice.common)); - ss->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0 = calloc(1,sizeof(*ss->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0)); - - ASN_SEQUENCE_ADD(&bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList->list,ss); - - - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->searchSpaceSIB1=NULL; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->searchSpaceOtherSystemInformation=NULL; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->pagingSearchSpace=NULL; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace)); - *bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace=1; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ext1=NULL; - - bwp->bwp_Common->pdsch_ConfigCommon=calloc(1,sizeof(*bwp->bwp_Common->pdsch_ConfigCommon)); - bwp->bwp_Common->pdsch_ConfigCommon->present = NR_SetupRelease_PDSCH_ConfigCommon_PR_setup; - bwp->bwp_Common->pdsch_ConfigCommon->choice.setup = calloc(1,sizeof(*bwp->bwp_Common->pdsch_ConfigCommon->choice.setup)); - bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList = calloc(1,sizeof(*bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList)); - - // copy PDSCH TimeDomainResourceAllocation from InitialBWP - - NR_PDSCH_TimeDomainResourceAllocation_t *pdschi; - for (int i=0;idownlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count;i++) { - pdschi= calloc(1,sizeof(*pdschi)); - AssertFatal(servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->k0!=NULL,"element %d is null\n",i); - - pdschi->k0 = calloc(1,sizeof(*pdschi->k0)); - *pdschi->k0 = *servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->k0; - pdschi->mappingType = servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->mappingType; - pdschi->startSymbolAndLength = servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->startSymbolAndLength; - ASN_SEQUENCE_ADD(&bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list,pdschi); - } - - bwp->bwp_Dedicated=calloc(1,sizeof(*bwp->bwp_Dedicated)); - - bwp->bwp_Dedicated->pdcch_Config=calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config)); - bwp->bwp_Dedicated->pdcch_Config->present = NR_SetupRelease_PDCCH_Config_PR_setup; - bwp->bwp_Dedicated->pdcch_Config->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup)); - bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList)); - - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list, - coreset); - - bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList)); - - NR_SearchSpace_t *ss2 = calloc(1,sizeof(*ss2)); - - ss2->searchSpaceId=2; - ss2->controlResourceSetId=calloc(1,sizeof(*ss2->controlResourceSetId)); - *ss2->controlResourceSetId=1; - ss2->monitoringSlotPeriodicityAndOffset=calloc(1,sizeof(*ss2->monitoringSlotPeriodicityAndOffset)); - ss2->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1; - ss2->monitoringSlotPeriodicityAndOffset->choice.sl1=(NULL_t)0; - ss2->duration=NULL; - ss2->monitoringSymbolsWithinSlot = calloc(1,sizeof(*ss2->monitoringSymbolsWithinSlot)); - ss2->monitoringSymbolsWithinSlot->buf = calloc(1,2); - ss2->monitoringSymbolsWithinSlot->size = 2; - ss2->monitoringSymbolsWithinSlot->bits_unused = 2; - ss2->monitoringSymbolsWithinSlot->buf[0]=0xc0; - ss2->monitoringSymbolsWithinSlot->buf[1]=0x0; - ss2->nrofCandidates=calloc(1,sizeof(*ss2->nrofCandidates)); - ss2->nrofCandidates->aggregationLevel1 = NR_SearchSpace__nrofCandidates__aggregationLevel1_n0; - ss2->nrofCandidates->aggregationLevel2 = NR_SearchSpace__nrofCandidates__aggregationLevel2_n0; - ss2->nrofCandidates->aggregationLevel4 = NR_SearchSpace__nrofCandidates__aggregationLevel4_n4; - ss2->nrofCandidates->aggregationLevel8 = NR_SearchSpace__nrofCandidates__aggregationLevel8_n0; - ss2->nrofCandidates->aggregationLevel16 = NR_SearchSpace__nrofCandidates__aggregationLevel16_n0; - ss2->searchSpaceType=calloc(1,sizeof(*ss2->searchSpaceType)); - ss2->searchSpaceType->present = NR_SearchSpace__searchSpaceType_PR_ue_Specific; - ss2->searchSpaceType->choice.ue_Specific = calloc(1,sizeof(*ss2->searchSpaceType->choice.ue_Specific)); - ss2->searchSpaceType->choice.ue_Specific->dci_Formats=NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_0_And_1_0; - - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list, - ss2); - - - bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToReleaseList = NULL; - - bwp->bwp_Dedicated->pdsch_Config = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config)); + for (int i=0; idownlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count; i++) { + pdschi= calloc(1,sizeof(*pdschi)); + AssertFatal(servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->k0!=NULL,"element %d is null\n",i); + pdschi->k0 = calloc(1,sizeof(*pdschi->k0)); + *pdschi->k0 = *servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->k0; + pdschi->mappingType = servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->mappingType; + pdschi->startSymbolAndLength = servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->startSymbolAndLength; + ASN_SEQUENCE_ADD(&bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list,pdschi); + } + bwp->bwp_Dedicated=calloc(1,sizeof(*bwp->bwp_Dedicated)); + bwp->bwp_Dedicated->pdcch_Config=calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config)); + bwp->bwp_Dedicated->pdcch_Config->present = NR_SetupRelease_PDCCH_Config_PR_setup; + bwp->bwp_Dedicated->pdcch_Config->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup)); + bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList)); + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list, + coreset); + bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList)); + NR_SearchSpace_t *ss2 = calloc(1,sizeof(*ss2)); + ss2->searchSpaceId=2; + ss2->controlResourceSetId=calloc(1,sizeof(*ss2->controlResourceSetId)); + *ss2->controlResourceSetId=1; + ss2->monitoringSlotPeriodicityAndOffset=calloc(1,sizeof(*ss2->monitoringSlotPeriodicityAndOffset)); + ss2->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1; + ss2->monitoringSlotPeriodicityAndOffset->choice.sl1=(NULL_t)0; + ss2->duration=NULL; + ss2->monitoringSymbolsWithinSlot = calloc(1,sizeof(*ss2->monitoringSymbolsWithinSlot)); + ss2->monitoringSymbolsWithinSlot->buf = calloc(1,2); + ss2->monitoringSymbolsWithinSlot->size = 2; + ss2->monitoringSymbolsWithinSlot->bits_unused = 2; + ss2->monitoringSymbolsWithinSlot->buf[0]=0xc0; + ss2->monitoringSymbolsWithinSlot->buf[1]=0x0; + ss2->nrofCandidates=calloc(1,sizeof(*ss2->nrofCandidates)); + ss2->nrofCandidates->aggregationLevel1 = NR_SearchSpace__nrofCandidates__aggregationLevel1_n0; + ss2->nrofCandidates->aggregationLevel2 = NR_SearchSpace__nrofCandidates__aggregationLevel2_n0; + ss2->nrofCandidates->aggregationLevel4 = NR_SearchSpace__nrofCandidates__aggregationLevel4_n4; + ss2->nrofCandidates->aggregationLevel8 = NR_SearchSpace__nrofCandidates__aggregationLevel8_n0; + ss2->nrofCandidates->aggregationLevel16 = NR_SearchSpace__nrofCandidates__aggregationLevel16_n0; + ss2->searchSpaceType=calloc(1,sizeof(*ss2->searchSpaceType)); + ss2->searchSpaceType->present = NR_SearchSpace__searchSpaceType_PR_ue_Specific; + ss2->searchSpaceType->choice.ue_Specific = calloc(1,sizeof(*ss2->searchSpaceType->choice.ue_Specific)); + ss2->searchSpaceType->choice.ue_Specific->dci_Formats=NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_0_And_1_0; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list, + ss2); + bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToReleaseList = NULL; + bwp->bwp_Dedicated->pdsch_Config = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config)); bwp->bwp_Dedicated->pdsch_Config->present = NR_SetupRelease_PDSCH_Config_PR_setup; bwp->bwp_Dedicated->pdsch_Config->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup)); bwp->bwp_Dedicated->pdsch_Config->choice.setup->dataScramblingIdentityPDSCH = NULL; bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA)); bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->present= NR_SetupRelease_DMRS_DownlinkConfig_PR_setup; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup)); - - bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->maxLength=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->scramblingID0=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->scramblingID1=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->phaseTrackingRS=NULL; - - bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition)); - *bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0; - - bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList=calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList)); - - NR_TCI_State_t*tcid0=calloc(1,sizeof(*tcid0)); - tcid0->tci_StateId=0; - tcid0->qcl_Type1.cell=NULL; - tcid0->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid0->qcl_Type1.bwp_Id)); - *tcid0->qcl_Type1.bwp_Id=1; - tcid0->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tcid0->qcl_Type1.referenceSignal.choice.csi_rs = 2; - tcid0->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid0); - - NR_TCI_State_t*tcid1=calloc(1,sizeof(*tcid1)); - tcid1->tci_StateId=0; - tcid1->qcl_Type1.cell=NULL; - tcid1->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid1->qcl_Type1.bwp_Id)); - *tcid1->qcl_Type1.bwp_Id=1; - tcid1->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tcid1->qcl_Type1.referenceSignal.choice.csi_rs = 6; - tcid1->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid1); - - NR_TCI_State_t*tcid2=calloc(1,sizeof(*tcid2)); - tcid2->tci_StateId=2; - tcid2->qcl_Type1.cell=NULL; - tcid2->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid2->qcl_Type1.bwp_Id)); - *tcid2->qcl_Type1.bwp_Id=1; - tcid2->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tcid2->qcl_Type1.referenceSignal.choice.csi_rs = 10; - tcid2->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid2); - - NR_TCI_State_t*tcid3=calloc(1,sizeof(*tcid3)); - tcid3->tci_StateId=3; - tcid3->qcl_Type1.cell=NULL; - tcid3->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid3->qcl_Type1.bwp_Id)); - *tcid3->qcl_Type1.bwp_Id=1; - tcid3->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tcid3->qcl_Type1.referenceSignal.choice.csi_rs = 14; - tcid3->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid3); - - NR_TCI_State_t*tcid4=calloc(1,sizeof(*tcid4)); - tcid4->tci_StateId=4; - tcid4->qcl_Type1.cell=NULL; - tcid4->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid4->qcl_Type1.bwp_Id)); - *tcid4->qcl_Type1.bwp_Id=1; - tcid4->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tcid4->qcl_Type1.referenceSignal.choice.csi_rs = 18; - tcid4->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid4); - - NR_TCI_State_t*tcid5=calloc(1,sizeof(*tcid5)); - tcid5->tci_StateId=5; - tcid5->qcl_Type1.cell=NULL; - tcid5->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid5->qcl_Type1.bwp_Id)); - *tcid5->qcl_Type1.bwp_Id=1; - tcid5->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tcid5->qcl_Type1.referenceSignal.choice.csi_rs = 22; - tcid5->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid5); - - NR_TCI_State_t*tcid6=calloc(1,sizeof(*tcid6)); - tcid6->tci_StateId=6; - tcid6->qcl_Type1.cell=NULL; - tcid6->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid6->qcl_Type1.bwp_Id)); - *tcid6->qcl_Type1.bwp_Id=1; - tcid6->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tcid6->qcl_Type1.referenceSignal.choice.csi_rs = 26; - tcid6->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid6); - - NR_TCI_State_t*tcid7=calloc(1,sizeof(*tcid7)); - tcid7->tci_StateId=7; - tcid7->qcl_Type1.cell=NULL; - tcid7->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid7->qcl_Type1.bwp_Id)); - *tcid7->qcl_Type1.bwp_Id=1; - tcid7->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tcid7->qcl_Type1.referenceSignal.choice.csi_rs = 30; - tcid7->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid7); - - NR_TCI_State_t*tcid8=calloc(1,sizeof(*tcid8)); - tcid8->tci_StateId=8; - tcid8->qcl_Type1.cell=NULL; - tcid8->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid8->qcl_Type1.bwp_Id)); - *tcid8->qcl_Type1.bwp_Id=1; - tcid8->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tcid8->qcl_Type1.referenceSignal.choice.ssb = 0; - tcid8->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid8); - - NR_TCI_State_t*tcid9=calloc(1,sizeof(*tcid9)); - tcid9->tci_StateId=9; - tcid9->qcl_Type1.cell=NULL; - tcid9->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid9->qcl_Type1.bwp_Id)); - *tcid9->qcl_Type1.bwp_Id=1; - tcid9->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tcid9->qcl_Type1.referenceSignal.choice.ssb = 1; - tcid9->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid9); - - NR_TCI_State_t*tcid10=calloc(1,sizeof(*tcid10)); - tcid10->tci_StateId=10; - tcid10->qcl_Type1.cell=NULL; - tcid10->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid10->qcl_Type1.bwp_Id)); - *tcid10->qcl_Type1.bwp_Id=1; - tcid10->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tcid10->qcl_Type1.referenceSignal.choice.ssb = 2; - tcid10->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid10); - - NR_TCI_State_t*tcid11=calloc(1,sizeof(*tcid11)); - tcid11->tci_StateId=11; - tcid11->qcl_Type1.cell=NULL; - tcid11->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid11->qcl_Type1.bwp_Id)); - *tcid11->qcl_Type1.bwp_Id=1; - tcid11->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tcid11->qcl_Type1.referenceSignal.choice.ssb = 3; - tcid11->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid11); - - NR_TCI_State_t*tcid12=calloc(1,sizeof(*tcid12)); - tcid12->tci_StateId=12; - tcid12->qcl_Type1.cell=NULL; - tcid12->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid12->qcl_Type1.bwp_Id)); - *tcid12->qcl_Type1.bwp_Id=1; - tcid12->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tcid12->qcl_Type1.referenceSignal.choice.ssb = 4; - tcid12->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid12); - - NR_TCI_State_t*tcid13=calloc(1,sizeof(*tcid13)); - tcid13->tci_StateId=13; - tcid13->qcl_Type1.cell=NULL; - tcid13->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid13->qcl_Type1.bwp_Id)); - *tcid13->qcl_Type1.bwp_Id=1; - tcid13->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tcid13->qcl_Type1.referenceSignal.choice.ssb = 5; - tcid13->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid13); - - NR_TCI_State_t*tcid14=calloc(1,sizeof(*tcid14)); - tcid14->tci_StateId=14; - tcid14->qcl_Type1.cell=NULL; - tcid14->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid14->qcl_Type1.bwp_Id)); - *tcid14->qcl_Type1.bwp_Id=1; - tcid14->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tcid14->qcl_Type1.referenceSignal.choice.ssb = 6; - tcid14->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid14); - - NR_TCI_State_t*tcid15=calloc(1,sizeof(*tcid15)); - tcid15->tci_StateId=15; - tcid15->qcl_Type1.cell=NULL; - tcid15->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid15->qcl_Type1.bwp_Id)); - *tcid15->qcl_Type1.bwp_Id=1; - tcid15->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tcid15->qcl_Type1.referenceSignal.choice.ssb = 7; - tcid15->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid15); - - bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup1=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup2=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rbg_Size=NR_PDSCH_Config__rbg_Size_config1; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->mcs_Table=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI)); - *bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = NR_PDSCH_Config__maxNrofCodeWordsScheduledByDCI_n1; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.present = NR_PDSCH_Config__prb_BundlingType_PR_staticBundling; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling)); - bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = - calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize)); - *bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = NR_PDSCH_Config__prb_BundlingType__staticBundling__bundleSize_wideband; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToAddModList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToAddModList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL; - - bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup1=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup2=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rbg_Size=NR_PDSCH_Config__rbg_Size_config1; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->mcs_Table=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI)); - *bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = NR_PDSCH_Config__maxNrofCodeWordsScheduledByDCI_n1; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.present = NR_PDSCH_Config__prb_BundlingType_PR_staticBundling; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling)); - bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = - calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize)); - *bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = NR_PDSCH_Config__prb_BundlingType__staticBundling__bundleSize_wideband; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToAddModList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToAddModList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL; - bwp->bwp_Dedicated->sps_Config = NULL; //calloc(1,sizeof(struct NR_SetupRelease_SPS_Config)); - - bwp->bwp_Dedicated->radioLinkMonitoringConfig = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig)); - bwp->bwp_Dedicated->radioLinkMonitoringConfig->present = NR_SetupRelease_RadioLinkMonitoringConfig_PR_setup; - - bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup)); - bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->failureDetectionResourcesToAddModList=NULL; - bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->failureDetectionResourcesToReleaseList=NULL; - bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount)); - *bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = NR_RadioLinkMonitoringConfig__beamFailureInstanceMaxCount_n3; - bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer)); - *bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = NR_RadioLinkMonitoringConfig__beamFailureDetectionTimer_pbfd2; - - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list,bwp); - - secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id)); - - *secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id=1; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->bwp_InactivityTimer = NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->defaultDownlinkBWP_Id = NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig)); - - NR_BWP_UplinkDedicated_t *initialUplinkBWP = calloc(1,sizeof(*initialUplinkBWP)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->initialUplinkBWP = initialUplinkBWP; - initialUplinkBWP->pucch_Config = NULL; - initialUplinkBWP->pusch_Config = calloc(1,sizeof(*initialUplinkBWP->pusch_Config)); - initialUplinkBWP->pusch_Config->present = NR_SetupRelease_PUSCH_Config_PR_setup; - NR_PUSCH_Config_t *pusch_Config = calloc(1,sizeof(*pusch_Config)); - initialUplinkBWP->pusch_Config->choice.setup = pusch_Config; - pusch_Config->txConfig=calloc(1,sizeof(*pusch_Config->txConfig)); - *pusch_Config->txConfig= NR_PUSCH_Config__txConfig_codebook; - pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA = NULL; - pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB = calloc(1,sizeof(*pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB)); - pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->present = NR_SetupRelease_DMRS_UplinkConfig_PR_setup; - pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup = calloc(1,sizeof(*pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup)); - NR_DMRS_UplinkConfig_t *NR_DMRS_UplinkConfig = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup; - NR_DMRS_UplinkConfig->dmrs_Type = NULL; - NR_DMRS_UplinkConfig->dmrs_AdditionalPosition =NR_DMRS_UplinkConfig__dmrs_AdditionalPosition_pos0; - NR_DMRS_UplinkConfig->phaseTrackingRS=NULL; - NR_DMRS_UplinkConfig->maxLength=NULL; - NR_DMRS_UplinkConfig->transformPrecodingDisabled = calloc(1,sizeof(*NR_DMRS_UplinkConfig->transformPrecodingDisabled)); - NR_DMRS_UplinkConfig->transformPrecodingDisabled->scramblingID0 = NULL; - NR_DMRS_UplinkConfig->transformPrecodingDisabled->scramblingID1 = NULL; - NR_DMRS_UplinkConfig->transformPrecodingEnabled = NULL; - pusch_Config->pusch_PowerControl = calloc(1,sizeof(*pusch_Config->pusch_PowerControl)); - pusch_Config->pusch_PowerControl->tpc_Accumulation = NULL; - pusch_Config->pusch_PowerControl->msg3_Alpha = calloc(1,sizeof(*pusch_Config->pusch_PowerControl->msg3_Alpha)); - *pusch_Config->pusch_PowerControl->msg3_Alpha = NR_Alpha_alpha1; - pusch_Config->pusch_PowerControl->p0_NominalWithoutGrant = NULL; - pusch_Config->pusch_PowerControl->p0_AlphaSets = calloc(1,sizeof(*pusch_Config->pusch_PowerControl->p0_AlphaSets)); - NR_P0_PUSCH_AlphaSet_t *aset = calloc(1,sizeof(*aset)); - aset->p0_PUSCH_AlphaSetId=0; - aset->p0=calloc(1,sizeof(*aset->p0)); - *aset->p0 = 0; - aset->alpha=calloc(1,sizeof(*aset->alpha)); - *aset->alpha=NR_Alpha_alpha1; - ASN_SEQUENCE_ADD(&pusch_Config->pusch_PowerControl->p0_AlphaSets->list,aset); - pusch_Config->pusch_PowerControl->pathlossReferenceRSToAddModList = calloc(1,sizeof(*pusch_Config->pusch_PowerControl->pathlossReferenceRSToAddModList)); - NR_PUSCH_PathlossReferenceRS_t *pl = calloc(1,sizeof(*pl)); - pl->pusch_PathlossReferenceRS_Id=0; - pl->referenceSignal.present = NR_PUSCH_PathlossReferenceRS__referenceSignal_PR_csi_RS_Index; - pl->referenceSignal.choice.csi_RS_Index=0; - ASN_SEQUENCE_ADD(&pusch_Config->pusch_PowerControl->pathlossReferenceRSToAddModList->list,pl); - pusch_Config->pusch_PowerControl->pathlossReferenceRSToReleaseList = NULL; - pusch_Config->pusch_PowerControl->twoPUSCH_PC_AdjustmentStates = NULL; - pusch_Config->pusch_PowerControl->deltaMCS = NULL; - pusch_Config->pusch_PowerControl->sri_PUSCH_MappingToAddModList = NULL; - pusch_Config->pusch_PowerControl->sri_PUSCH_MappingToReleaseList = NULL; - pusch_Config->frequencyHopping=NULL; - pusch_Config->frequencyHoppingOffsetLists=NULL; - pusch_Config->resourceAllocation = NR_PUSCH_Config__resourceAllocation_resourceAllocationType1; - pusch_Config->pusch_TimeDomainAllocationList = NULL; - pusch_Config->pusch_AggregationFactor=NULL; - pusch_Config->mcs_Table=NULL; - pusch_Config->mcs_TableTransformPrecoder=NULL; - pusch_Config->transformPrecoder=calloc(1,sizeof(*pusch_Config->transformPrecoder)); - *pusch_Config->transformPrecoder = NR_PUSCH_Config__transformPrecoder_disabled; - pusch_Config->codebookSubset=calloc(1,sizeof(*pusch_Config->codebookSubset)); - *pusch_Config->codebookSubset = NR_PUSCH_Config__codebookSubset_nonCoherent; - pusch_Config->maxRank=calloc(1,sizeof(*pusch_Config->maxRank)); - *pusch_Config->maxRank= 1; - pusch_Config->rbg_Size=NULL; - pusch_Config->uci_OnPUSCH=NULL; - pusch_Config->tp_pi2BPSK=NULL; - - initialUplinkBWP->srs_Config = calloc(1,sizeof(*initialUplinkBWP->srs_Config)); - initialUplinkBWP->srs_Config->present = NR_SetupRelease_SRS_Config_PR_setup; - NR_SRS_Config_t *srs_Config = calloc(1,sizeof(*srs_Config)); - initialUplinkBWP->srs_Config->choice.setup=srs_Config; - srs_Config->srs_ResourceSetToReleaseList=NULL; - srs_Config->srs_ResourceSetToAddModList=calloc(1,sizeof(*srs_Config->srs_ResourceSetToAddModList)); - NR_SRS_ResourceSet_t *srs_resset0=calloc(1,sizeof(*srs_resset0)); - srs_resset0->srs_ResourceSetId = 0; - srs_resset0->srs_ResourceIdList=calloc(1,sizeof(*srs_resset0->srs_ResourceIdList)); - NR_SRS_ResourceId_t *srs_resset0_id=calloc(1,sizeof(*srs_resset0_id)); - *srs_resset0_id=0; - ASN_SEQUENCE_ADD(&srs_resset0->srs_ResourceIdList->list,srs_resset0_id); - srs_Config->srs_ResourceToReleaseList=NULL; - srs_resset0->resourceType.present = NR_SRS_ResourceSet__resourceType_PR_aperiodic; - srs_resset0->resourceType.choice.aperiodic = calloc(1,sizeof(*srs_resset0->resourceType.choice.aperiodic)); - srs_resset0->resourceType.choice.aperiodic->aperiodicSRS_ResourceTrigger=1; - srs_resset0->resourceType.choice.aperiodic->csi_RS=NULL; - srs_resset0->resourceType.choice.aperiodic->slotOffset= calloc(1,sizeof(*srs_resset0->resourceType.choice.aperiodic->slotOffset)); - *srs_resset0->resourceType.choice.aperiodic->slotOffset=2; - srs_resset0->resourceType.choice.aperiodic->ext1=NULL; - srs_resset0->usage=NR_SRS_ResourceSet__usage_codebook; - srs_resset0->alpha = calloc(1,sizeof(*srs_resset0->alpha)); - *srs_resset0->alpha = NR_Alpha_alpha1; - srs_resset0->p0=calloc(1,sizeof(*srs_resset0->p0)); - *srs_resset0->p0=-80; - srs_resset0->pathlossReferenceRS=NULL; - srs_resset0->srs_PowerControlAdjustmentStates=NULL; - ASN_SEQUENCE_ADD(&srs_Config->srs_ResourceSetToAddModList->list,srs_resset0); - srs_Config->srs_ResourceToReleaseList=NULL; - srs_Config->srs_ResourceToAddModList=calloc(1,sizeof(*srs_Config->srs_ResourceToAddModList)); - NR_SRS_Resource_t *srs_res0=calloc(1,sizeof(*srs_res0)); - srs_res0->srs_ResourceId=0; - srs_res0->nrofSRS_Ports=NR_SRS_Resource__nrofSRS_Ports_port1; - srs_res0->ptrs_PortIndex=NULL; - srs_res0->transmissionComb.present=NR_SRS_Resource__transmissionComb_PR_n2; - srs_res0->transmissionComb.choice.n2=calloc(1,sizeof(*srs_res0->transmissionComb.choice.n2)); - srs_res0->transmissionComb.choice.n2->combOffset_n2=0; - srs_res0->transmissionComb.choice.n2->cyclicShift_n2=0; - srs_res0->resourceMapping.startPosition=2; - srs_res0->resourceMapping.nrofSymbols=NR_SRS_Resource__resourceMapping__nrofSymbols_n1; - srs_res0->resourceMapping.repetitionFactor=NR_SRS_Resource__resourceMapping__repetitionFactor_n1; - srs_res0->freqDomainPosition=0; - srs_res0->freqDomainShift=0; - srs_res0->freqHopping.c_SRS = 61; - srs_res0->freqHopping.b_SRS=0; - srs_res0->freqHopping.b_hop=0; - srs_res0->groupOrSequenceHopping=NR_SRS_Resource__groupOrSequenceHopping_neither; - srs_res0->resourceType.present= NR_SRS_Resource__resourceType_PR_aperiodic; - srs_res0->resourceType.choice.aperiodic=calloc(1,sizeof(*srs_res0->resourceType.choice.aperiodic)); - srs_res0->sequenceId=40; - srs_res0->spatialRelationInfo=calloc(1,sizeof(*srs_res0->spatialRelationInfo)); - srs_res0->spatialRelationInfo->servingCellId=NULL; - srs_res0->spatialRelationInfo->referenceSignal.present=NR_SRS_SpatialRelationInfo__referenceSignal_PR_csi_RS_Index; - srs_res0->spatialRelationInfo->referenceSignal.choice.csi_RS_Index=0; - ASN_SEQUENCE_ADD(&srs_Config->srs_ResourceToAddModList->list,srs_res0); - - secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToReleaseList = NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList)); - NR_BWP_Uplink_t *ubwp = calloc(1,sizeof(*ubwp)); - ubwp->bwp_Id=1; - ubwp->bwp_Common = calloc(1,sizeof(*ubwp->bwp_Common)); - // copy bwp_Common from Initial UL BWP except for bandwidth - memcpy((void*)&ubwp->bwp_Common->genericParameters, - (void*)&servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->genericParameters, - sizeof(servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->genericParameters)); - ubwp->bwp_Common->genericParameters.locationAndBandwidth=PRBalloc_to_locationandbandwidth(servingcellconfigcommon->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth,0); - - ubwp->bwp_Common->rach_ConfigCommon = servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon; - ubwp->bwp_Common->pusch_ConfigCommon = servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon; - ubwp->bwp_Common->pucch_ConfigCommon = servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon; - - ubwp->bwp_Dedicated = calloc(1,sizeof(*ubwp->bwp_Dedicated)); - ubwp->bwp_Dedicated->pucch_Config = calloc(1,sizeof(*ubwp->bwp_Dedicated->pucch_Config)); - ubwp->bwp_Dedicated->pucch_Config->present = NR_SetupRelease_PUCCH_Config_PR_setup; - NR_PUCCH_Config_t *pucch_Config = calloc(1,sizeof(*pucch_Config)); - ubwp->bwp_Dedicated->pucch_Config->choice.setup=pucch_Config; - pucch_Config->resourceSetToAddModList = calloc(1,sizeof(*pucch_Config->resourceSetToAddModList)); - pucch_Config->resourceSetToReleaseList = NULL; - NR_PUCCH_ResourceSet_t *pucchresset0=calloc(1,sizeof(*pucchresset0)); - NR_PUCCH_ResourceSet_t *pucchresset1=calloc(1,sizeof(*pucchresset1)); - pucchresset0->pucch_ResourceSetId = 0; - NR_PUCCH_ResourceId_t *pucchresset0id0=calloc(1,sizeof(*pucchresset0id0)); - NR_PUCCH_ResourceId_t *pucchresset0id1=calloc(1,sizeof(*pucchresset0id1)); - *pucchresset0id0=1; - ASN_SEQUENCE_ADD(&pucchresset0->resourceList.list,pucchresset0id0); - *pucchresset0id1=2; - ASN_SEQUENCE_ADD(&pucchresset0->resourceList.list,pucchresset0id1); - pucchresset0->maxPayloadMinus1=NULL; - - ASN_SEQUENCE_ADD(&pucch_Config->resourceSetToAddModList->list,pucchresset0); - - pucchresset1->pucch_ResourceSetId = 1; - NR_PUCCH_ResourceId_t *pucchresset1id0=calloc(1,sizeof(*pucchresset1id0)); - NR_PUCCH_ResourceId_t *pucchresset1id1=calloc(1,sizeof(*pucchresset1id1)); - *pucchresset1id0=3; - ASN_SEQUENCE_ADD(&pucchresset1->resourceList.list,pucchresset1id0); - *pucchresset1id1=4; - ASN_SEQUENCE_ADD(&pucchresset1->resourceList.list,pucchresset1id1); - pucchresset1->maxPayloadMinus1=NULL; - ASN_SEQUENCE_ADD(&pucch_Config->resourceSetToAddModList->list,pucchresset1); - - pucch_Config->resourceToAddModList = calloc(1,sizeof(*pucch_Config->resourceToAddModList)); - pucch_Config->resourceToReleaseList = NULL; - NR_PUCCH_Resource_t *pucchres0=calloc(1,sizeof(*pucchres0)); - NR_PUCCH_Resource_t *pucchres1=calloc(1,sizeof(*pucchres1)); - NR_PUCCH_Resource_t *pucchres2=calloc(1,sizeof(*pucchres2)); - NR_PUCCH_Resource_t *pucchres3=calloc(1,sizeof(*pucchres3)); - pucchres0->pucch_ResourceId=1; - pucchres0->startingPRB=48; - pucchres0->intraSlotFrequencyHopping=NULL; - pucchres0->secondHopPRB=NULL; - pucchres0->format.present= NR_PUCCH_Resource__format_PR_format0; - pucchres0->format.choice.format0=calloc(1,sizeof(*pucchres0->format.choice.format0)); - pucchres0->format.choice.format0->initialCyclicShift=0; - pucchres0->format.choice.format0->nrofSymbols=1; - pucchres0->format.choice.format0->startingSymbolIndex=13; - ASN_SEQUENCE_ADD(&pucch_Config->resourceToAddModList->list,pucchres0); - - pucchres1->pucch_ResourceId=2; - pucchres1->startingPRB=48; - pucchres1->intraSlotFrequencyHopping=NULL; - pucchres1->secondHopPRB=NULL; - pucchres1->format.present= NR_PUCCH_Resource__format_PR_format0; - pucchres1->format.choice.format0=calloc(1,sizeof(*pucchres1->format.choice.format0)); - pucchres1->format.choice.format0->initialCyclicShift=0; - pucchres1->format.choice.format0->nrofSymbols=1; - pucchres1->format.choice.format0->startingSymbolIndex=12; - ASN_SEQUENCE_ADD(&pucch_Config->resourceToAddModList->list,pucchres1); - - pucchres2->pucch_ResourceId=3; - pucchres2->startingPRB=40; - pucchres2->intraSlotFrequencyHopping=NULL; - pucchres2->secondHopPRB=NULL; - pucchres2->format.present= NR_PUCCH_Resource__format_PR_format2; - pucchres2->format.choice.format2=calloc(1,sizeof(*pucchres2->format.choice.format2)); - pucchres2->format.choice.format2->nrofPRBs=16; - pucchres2->format.choice.format2->nrofSymbols=1; - pucchres2->format.choice.format2->startingSymbolIndex=13; - ASN_SEQUENCE_ADD(&pucch_Config->resourceToAddModList->list,pucchres2); - - pucchres3->pucch_ResourceId=4; - pucchres3->startingPRB=40; - pucchres3->intraSlotFrequencyHopping=NULL; - pucchres3->secondHopPRB=NULL; - pucchres3->format.present= NR_PUCCH_Resource__format_PR_format2; - pucchres3->format.choice.format2=calloc(1,sizeof(*pucchres3->format.choice.format2)); - pucchres3->format.choice.format2->nrofPRBs=16; - pucchres3->format.choice.format2->nrofSymbols=1; - pucchres3->format.choice.format2->startingSymbolIndex=12; - ASN_SEQUENCE_ADD(&pucch_Config->resourceToAddModList->list,pucchres3); - - pucch_Config->format2=calloc(1,sizeof(*pucch_Config->format2)); - pucch_Config->format2->present=NR_SetupRelease_PUCCH_FormatConfig_PR_setup; - NR_PUCCH_FormatConfig_t *pucchfmt2 = calloc(1,sizeof(*pucchfmt2)); - pucch_Config->format2->choice.setup = pucchfmt2; - pucchfmt2->interslotFrequencyHopping=NULL; - pucchfmt2->additionalDMRS=NULL; - pucchfmt2->maxCodeRate=calloc(1,sizeof(*pucchfmt2->maxCodeRate)); - *pucchfmt2->maxCodeRate=NR_PUCCH_MaxCodeRate_zeroDot15; - pucchfmt2->nrofSlots=NULL; - pucchfmt2->pi2BPSK=NULL; - pucchfmt2->simultaneousHARQ_ACK_CSI=NULL; - pucch_Config->schedulingRequestResourceToAddModList=NULL; - pucch_Config->schedulingRequestResourceToReleaseList=NULL; - pucch_Config->multi_CSI_PUCCH_ResourceList=NULL; - pucch_Config->dl_DataToUL_ACK = calloc(1,sizeof(*pucch_Config->dl_DataToUL_ACK)); - long *delay[8]; - for (int i=0;i<8;i++) { - delay[i] = calloc(1,sizeof(*delay[i])); - *delay[i] = (i<6) ? (i+2) : 0; - ASN_SEQUENCE_ADD(&pucch_Config->dl_DataToUL_ACK->list,delay[i]); - } - pucch_Config->spatialRelationInfoToAddModList = calloc(1,sizeof(*pucch_Config->spatialRelationInfoToAddModList)); - NR_PUCCH_SpatialRelationInfo_t *pucchspatial = calloc(1,sizeof(*pucchspatial)); - pucchspatial->pucch_SpatialRelationInfoId = 1; - pucchspatial->servingCellId = NULL; - pucchspatial->referenceSignal.present = NR_PUCCH_SpatialRelationInfo__referenceSignal_PR_csi_RS_Index; - pucchspatial->referenceSignal.choice.csi_RS_Index = 0; - pucchspatial->pucch_PathlossReferenceRS_Id = 0; - pucchspatial->p0_PUCCH_Id = 1; - pucchspatial->closedLoopIndex = NR_PUCCH_SpatialRelationInfo__closedLoopIndex_i0; - ASN_SEQUENCE_ADD(&pucch_Config->spatialRelationInfoToAddModList->list,pucchspatial); - pucch_Config->spatialRelationInfoToReleaseList=NULL; - pucch_Config->pucch_PowerControl=calloc(1,sizeof(*pucch_Config->pucch_PowerControl)); - pucch_Config->pucch_PowerControl->deltaF_PUCCH_f0 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f0)); - *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f0 = 0; - pucch_Config->pucch_PowerControl->deltaF_PUCCH_f1 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f1)); - *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f1 = 0; - pucch_Config->pucch_PowerControl->deltaF_PUCCH_f2 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f2)); - *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f2 = 0; - pucch_Config->pucch_PowerControl->deltaF_PUCCH_f3 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f3)); - *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f3 = 0; - pucch_Config->pucch_PowerControl->deltaF_PUCCH_f4 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f4)); - *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f4 = 0; - pucch_Config->pucch_PowerControl->p0_Set = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->p0_Set)); - NR_P0_PUCCH_t *p00 = calloc(1,sizeof(*p00)); - p00->p0_PUCCH_Id=1; - p00->p0_PUCCH_Value = 0; - ASN_SEQUENCE_ADD(&pucch_Config->pucch_PowerControl->p0_Set->list,p00); - pucch_Config->pucch_PowerControl->pathlossReferenceRSs = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->pathlossReferenceRSs)); - NR_PUCCH_PathlossReferenceRS_t *pucchPLRef=calloc(1,sizeof(*pucchPLRef)); - pucchPLRef->pucch_PathlossReferenceRS_Id=0; - pucchPLRef->referenceSignal.present = NR_PUCCH_PathlossReferenceRS__referenceSignal_PR_csi_RS_Index; - pucchPLRef->referenceSignal.choice.csi_RS_Index=0; - ASN_SEQUENCE_ADD(&pucch_Config->pucch_PowerControl->pathlossReferenceRSs->list,pucchPLRef); - - // copy pusch_Config from dedicated initialBWP - ubwp->bwp_Dedicated->pusch_Config = calloc(1,sizeof(*ubwp->bwp_Dedicated->pusch_Config)); - ubwp->bwp_Dedicated->pusch_Config->present = NR_SetupRelease_PUSCH_Config_PR_setup; - ubwp->bwp_Dedicated->pusch_Config->choice.setup = pusch_Config; - - ubwp->bwp_Dedicated->configuredGrantConfig = NULL; - ubwp->bwp_Dedicated->srs_Config = calloc(1,sizeof(*ubwp->bwp_Dedicated->srs_Config)); - ubwp->bwp_Dedicated->srs_Config->present = NR_SetupRelease_SRS_Config_PR_setup; - ubwp->bwp_Dedicated->srs_Config->choice.setup = srs_Config; - - ubwp->bwp_Dedicated->beamFailureRecoveryConfig = NULL; - - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list,ubwp); - - secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id)); - *secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id = 1; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig = NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->carrierSwitching = NULL; - - secondaryCellGroup->spCellConfig->spCellConfigDedicated->supplementaryUplink=NULL; - - secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdcch_ServingCellConfig=NULL; - - secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig)); - NR_PDSCH_ServingCellConfig_t *pdsch_servingcellconfig = calloc(1,sizeof(*pdsch_servingcellconfig)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->present = NR_SetupRelease_PDSCH_ServingCellConfig_PR_setup; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup = pdsch_servingcellconfig; - pdsch_servingcellconfig->codeBlockGroupTransmission = NULL; - pdsch_servingcellconfig->xOverhead = NULL; - pdsch_servingcellconfig->nrofHARQ_ProcessesForPDSCH = NULL; - pdsch_servingcellconfig->pucch_Cell= NULL; - pdsch_servingcellconfig->ext1=calloc(1,sizeof(*pdsch_servingcellconfig->ext1)); - pdsch_servingcellconfig->ext1->maxMIMO_Layers = calloc(1,sizeof(*pdsch_servingcellconfig->ext1->maxMIMO_Layers)); - *pdsch_servingcellconfig->ext1->maxMIMO_Layers = 2; - pdsch_servingcellconfig->ext1->processingType2Enabled = NULL; - - secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->present = NR_SetupRelease_CSI_MeasConfig_PR_setup; - - - NR_CSI_MeasConfig_t *csi_MeasConfig = calloc(1,sizeof(*csi_MeasConfig)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup = csi_MeasConfig; - csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList = calloc(1,sizeof(*csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList)); - - NR_NZP_CSI_RS_Resource_t *nzpres0 = calloc(1,sizeof(*nzpres0)); - nzpres0->nzp_CSI_RS_ResourceId=0; - nzpres0->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_other; - nzpres0->resourceMapping.frequencyDomainAllocation.choice.other.buf = calloc(1,1); - nzpres0->resourceMapping.frequencyDomainAllocation.choice.other.size = 1; - nzpres0->resourceMapping.frequencyDomainAllocation.choice.other.bits_unused = 2; - nzpres0->resourceMapping.frequencyDomainAllocation.choice.other.buf[0]=1<<2; - nzpres0->resourceMapping.nrofPorts = (n_physical_antenna_ports==1)? NR_CSI_RS_ResourceMapping__nrofPorts_p1 : NR_CSI_RS_ResourceMapping__nrofPorts_p2; - nzpres0->resourceMapping.firstOFDMSymbolInTimeDomain=7; - nzpres0->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres0->resourceMapping.cdm_Type = (n_physical_antenna_ports==1)? NR_CSI_RS_ResourceMapping__cdm_Type_noCDM : NR_CSI_RS_ResourceMapping__cdm_Type_fd_CDM2; - nzpres0->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_one; - nzpres0->resourceMapping.density.choice.one=(NULL_t)0; - nzpres0->resourceMapping.freqBand.startingRB=0; - nzpres0->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres0->powerControlOffset=13; - nzpres0->powerControlOffsetSS=NULL; - nzpres0->scramblingID=40; - nzpres0->periodicityAndOffset = calloc(1,sizeof(*nzpres0->periodicityAndOffset)); - nzpres0->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots320; - nzpres0->periodicityAndOffset->choice.slots320 = 2; - nzpres0->qcl_InfoPeriodicCSI_RS=NULL; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres0); - - if (n_physical_antenna_ports > 1) { - NR_NZP_CSI_RS_Resource_t *nzpres2 = calloc(1,sizeof(*nzpres2)); - nzpres2->nzp_CSI_RS_ResourceId=2; - nzpres2->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres2->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres2->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres2->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres2->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=1; - nzpres2->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres2->resourceMapping.firstOFDMSymbolInTimeDomain=4; - nzpres2->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres2->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres2->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres2->resourceMapping.density.choice.three=(NULL_t)0; - nzpres2->resourceMapping.freqBand.startingRB=0; - nzpres2->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres2->powerControlOffset=0; - nzpres2->powerControlOffsetSS=calloc(1,sizeof(*nzpres2->powerControlOffsetSS)); - *nzpres2->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres2->scramblingID=40; - nzpres2->periodicityAndOffset = calloc(1,sizeof(*nzpres2->periodicityAndOffset)); - nzpres2->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres2->periodicityAndOffset->choice.slots160 = 25; - nzpres2->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres2->qcl_InfoPeriodicCSI_RS)); - *nzpres2->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres2); - - - NR_NZP_CSI_RS_Resource_t *nzpres3 = calloc(1,sizeof(*nzpres3)); - nzpres3->nzp_CSI_RS_ResourceId=3; - nzpres3->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres3->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres3->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres3->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres3->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=1; - nzpres3->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres3->resourceMapping.firstOFDMSymbolInTimeDomain=8; - nzpres3->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres3->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres3->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres3->resourceMapping.density.choice.three=(NULL_t)0; - nzpres3->resourceMapping.freqBand.startingRB=0; - nzpres3->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres3->powerControlOffset=0; - nzpres3->powerControlOffsetSS=calloc(1,sizeof(*nzpres3->powerControlOffsetSS)); - *nzpres3->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres3->scramblingID=40; - nzpres3->periodicityAndOffset = calloc(1,sizeof(*nzpres3->periodicityAndOffset)); - nzpres3->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres3->periodicityAndOffset->choice.slots160 = 25; - nzpres3->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres3->qcl_InfoPeriodicCSI_RS)); - *nzpres3->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres3); - } - if (n_physical_antenna_ports > 3) { - NR_NZP_CSI_RS_Resource_t *nzpres4 = calloc(1,sizeof(*nzpres4)); - nzpres4->nzp_CSI_RS_ResourceId=4; - nzpres4->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres4->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres4->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres4->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres4->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=1; - nzpres4->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres4->resourceMapping.firstOFDMSymbolInTimeDomain=4; - nzpres4->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres4->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres4->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres4->resourceMapping.density.choice.three=(NULL_t)0; - nzpres4->resourceMapping.freqBand.startingRB=0; - nzpres4->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres4->powerControlOffset=0; - nzpres4->powerControlOffsetSS=calloc(1,sizeof(*nzpres4->powerControlOffsetSS)); - *nzpres4->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres4->scramblingID=40; - nzpres4->periodicityAndOffset = calloc(1,sizeof(*nzpres4->periodicityAndOffset)); - nzpres4->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres4->periodicityAndOffset->choice.slots160 = 26; - nzpres4->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres4->qcl_InfoPeriodicCSI_RS)); - *nzpres4->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres4); - - NR_NZP_CSI_RS_Resource_t *nzpres5 = calloc(1,sizeof(*nzpres5)); - nzpres5->nzp_CSI_RS_ResourceId=5; - nzpres5->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres5->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres5->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres5->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres5->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=1; - nzpres5->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres5->resourceMapping.firstOFDMSymbolInTimeDomain=8; - nzpres5->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres5->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres5->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres5->resourceMapping.density.choice.three=(NULL_t)0; - nzpres5->resourceMapping.freqBand.startingRB=0; - nzpres5->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres5->powerControlOffset=0; - nzpres5->powerControlOffsetSS=calloc(1,sizeof(*nzpres5->powerControlOffsetSS)); - *nzpres5->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres5->scramblingID=40; - nzpres5->periodicityAndOffset = calloc(1,sizeof(*nzpres5->periodicityAndOffset)); - nzpres5->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres5->periodicityAndOffset->choice.slots160 = 26; - nzpres5->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres5->qcl_InfoPeriodicCSI_RS)); - *nzpres5->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres5); - } - if (n_physical_antenna_ports > 7) { - NR_NZP_CSI_RS_Resource_t *nzpres6 = calloc(1,sizeof(*nzpres6)); - nzpres6->nzp_CSI_RS_ResourceId=6; - nzpres6->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres6->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres6->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres6->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres6->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=4; - nzpres6->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres6->resourceMapping.firstOFDMSymbolInTimeDomain=4; - nzpres6->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres6->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres6->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres6->resourceMapping.density.choice.three=(NULL_t)0; - nzpres6->resourceMapping.freqBand.startingRB=0; - nzpres6->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres6->powerControlOffset=0; - nzpres6->powerControlOffsetSS=calloc(1,sizeof(*nzpres6->powerControlOffsetSS)); - *nzpres6->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres6->scramblingID=40; - nzpres6->periodicityAndOffset = calloc(1,sizeof(*nzpres6->periodicityAndOffset)); - nzpres6->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres6->periodicityAndOffset->choice.slots160 = 25; - nzpres6->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres6->qcl_InfoPeriodicCSI_RS)); - *nzpres6->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres6); - - NR_NZP_CSI_RS_Resource_t *nzpres7 = calloc(1,sizeof(*nzpres7)); - nzpres7->nzp_CSI_RS_ResourceId=7; - nzpres7->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres7->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres7->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres7->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres7->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=4; - nzpres7->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres7->resourceMapping.firstOFDMSymbolInTimeDomain=8; - nzpres7->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres7->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres7->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres7->resourceMapping.density.choice.three=(NULL_t)0; - nzpres7->resourceMapping.freqBand.startingRB=0; - nzpres7->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres7->powerControlOffset=0; - nzpres7->powerControlOffsetSS=calloc(1,sizeof(*nzpres7->powerControlOffsetSS)); - *nzpres7->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres7->scramblingID=40; - nzpres7->periodicityAndOffset = calloc(1,sizeof(*nzpres7->periodicityAndOffset)); - nzpres7->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres7->periodicityAndOffset->choice.slots160 = 25; - nzpres7->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres7->qcl_InfoPeriodicCSI_RS)); - *nzpres7->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres7); - NR_NZP_CSI_RS_Resource_t *nzpres8 = calloc(1,sizeof(*nzpres8)); - nzpres8->nzp_CSI_RS_ResourceId=8; - nzpres8->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres8->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres8->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres8->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres8->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=4; - nzpres8->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres8->resourceMapping.firstOFDMSymbolInTimeDomain=4; - nzpres8->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres8->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres8->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres8->resourceMapping.density.choice.three=(NULL_t)0; - nzpres8->resourceMapping.freqBand.startingRB=0; - nzpres8->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres8->powerControlOffset=0; - nzpres8->powerControlOffsetSS=calloc(1,sizeof(*nzpres8->powerControlOffsetSS)); - *nzpres8->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres8->scramblingID=40; - nzpres8->periodicityAndOffset = calloc(1,sizeof(*nzpres8->periodicityAndOffset)); - nzpres8->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres8->periodicityAndOffset->choice.slots160 = 26; - nzpres8->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres8->qcl_InfoPeriodicCSI_RS)); - *nzpres8->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres8); - - NR_NZP_CSI_RS_Resource_t *nzpres9 = calloc(1,sizeof(*nzpres9)); - nzpres9->nzp_CSI_RS_ResourceId=9; - nzpres9->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres9->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres9->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres9->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres9->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=4; - nzpres9->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres9->resourceMapping.firstOFDMSymbolInTimeDomain=8; - nzpres9->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres9->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres9->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres9->resourceMapping.density.choice.three=(NULL_t)0; - nzpres9->resourceMapping.freqBand.startingRB=0; - nzpres9->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres9->powerControlOffset=0; - nzpres9->powerControlOffsetSS=calloc(1,sizeof(*nzpres9->powerControlOffsetSS)); - *nzpres9->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres9->scramblingID=40; - nzpres9->periodicityAndOffset = calloc(1,sizeof(*nzpres9->periodicityAndOffset)); - nzpres9->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres9->periodicityAndOffset->choice.slots160 = 26; - nzpres9->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres9->qcl_InfoPeriodicCSI_RS)); - *nzpres9->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres9); - } - if (n_physical_antenna_ports > 15) { - NR_NZP_CSI_RS_Resource_t *nzpres10 = calloc(1,sizeof(*nzpres10)); - nzpres10->nzp_CSI_RS_ResourceId=10; - nzpres10->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres10->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres10->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres10->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres10->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=2; - nzpres10->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres10->resourceMapping.firstOFDMSymbolInTimeDomain=4; - nzpres10->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres10->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres10->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres10->resourceMapping.density.choice.three=(NULL_t)0; - nzpres10->resourceMapping.freqBand.startingRB=0; - nzpres10->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres10->powerControlOffset=0; - nzpres10->powerControlOffsetSS=calloc(1,sizeof(*nzpres10->powerControlOffsetSS)); - *nzpres10->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres10->scramblingID=40; - nzpres10->periodicityAndOffset = calloc(1,sizeof(*nzpres10->periodicityAndOffset)); - nzpres10->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres10->periodicityAndOffset->choice.slots160 = 25; - nzpres10->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres10->qcl_InfoPeriodicCSI_RS)); - *nzpres10->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres10); - - NR_NZP_CSI_RS_Resource_t *nzpres11 = calloc(1,sizeof(*nzpres11)); - nzpres11->nzp_CSI_RS_ResourceId=11; - nzpres11->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres11->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres11->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres11->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres11->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=2; - nzpres11->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres11->resourceMapping.firstOFDMSymbolInTimeDomain=8; - nzpres11->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres11->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres11->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres11->resourceMapping.density.choice.three=(NULL_t)0; - nzpres11->resourceMapping.freqBand.startingRB=0; - nzpres11->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres11->powerControlOffset=0; - nzpres11->powerControlOffsetSS=calloc(1,sizeof(*nzpres11->powerControlOffsetSS)); - *nzpres11->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres11->scramblingID=40; - nzpres11->periodicityAndOffset = calloc(1,sizeof(*nzpres11->periodicityAndOffset)); - nzpres11->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres11->periodicityAndOffset->choice.slots160 = 25; - nzpres11->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres11->qcl_InfoPeriodicCSI_RS)); - *nzpres11->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres11); - NR_NZP_CSI_RS_Resource_t *nzpres12 = calloc(1,sizeof(*nzpres12)); - nzpres12->nzp_CSI_RS_ResourceId=12; - nzpres12->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres12->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres12->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres12->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres12->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=2; - nzpres12->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres12->resourceMapping.firstOFDMSymbolInTimeDomain=4; - nzpres12->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres12->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres12->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres12->resourceMapping.density.choice.three=(NULL_t)0; - nzpres12->resourceMapping.freqBand.startingRB=0; - nzpres12->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres12->powerControlOffset=0; - nzpres12->powerControlOffsetSS=calloc(1,sizeof(*nzpres12->powerControlOffsetSS)); - *nzpres12->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres12->scramblingID=40; - nzpres12->periodicityAndOffset = calloc(1,sizeof(*nzpres12->periodicityAndOffset)); - nzpres12->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres12->periodicityAndOffset->choice.slots160 = 26; - nzpres12->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres12->qcl_InfoPeriodicCSI_RS)); - *nzpres12->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres12); - - NR_NZP_CSI_RS_Resource_t *nzpres13 = calloc(1,sizeof(*nzpres13)); - nzpres13->nzp_CSI_RS_ResourceId=13; - nzpres13->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres13->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres13->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres13->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres13->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=2; - nzpres13->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres13->resourceMapping.firstOFDMSymbolInTimeDomain=8; - nzpres13->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres13->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres13->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres13->resourceMapping.density.choice.three=(NULL_t)0; - nzpres13->resourceMapping.freqBand.startingRB=0; - nzpres13->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres13->powerControlOffset=0; - nzpres13->powerControlOffsetSS=calloc(1,sizeof(*nzpres13->powerControlOffsetSS)); - *nzpres13->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres13->scramblingID=40; - nzpres13->periodicityAndOffset = calloc(1,sizeof(*nzpres13->periodicityAndOffset)); - nzpres13->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres13->periodicityAndOffset->choice.slots160 = 26; - nzpres13->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres13->qcl_InfoPeriodicCSI_RS)); - *nzpres13->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres13); - NR_NZP_CSI_RS_Resource_t *nzpres14 = calloc(1,sizeof(*nzpres14)); - nzpres14->nzp_CSI_RS_ResourceId=14; - nzpres14->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres14->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres14->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres14->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres14->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=8; - nzpres14->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres14->resourceMapping.firstOFDMSymbolInTimeDomain=4; - nzpres14->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres14->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres14->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres14->resourceMapping.density.choice.three=(NULL_t)0; - nzpres14->resourceMapping.freqBand.startingRB=0; - nzpres14->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres14->powerControlOffset=0; - nzpres14->powerControlOffsetSS=calloc(1,sizeof(*nzpres14->powerControlOffsetSS)); - *nzpres14->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres14->scramblingID=40; - nzpres14->periodicityAndOffset = calloc(1,sizeof(*nzpres14->periodicityAndOffset)); - nzpres14->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres14->periodicityAndOffset->choice.slots160 = 25; - nzpres14->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres14->qcl_InfoPeriodicCSI_RS)); - *nzpres14->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres14); - - NR_NZP_CSI_RS_Resource_t *nzpres15 = calloc(1,sizeof(*nzpres15)); - nzpres15->nzp_CSI_RS_ResourceId=15; - nzpres15->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres15->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres15->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres15->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres15->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=8; - nzpres15->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres15->resourceMapping.firstOFDMSymbolInTimeDomain=8; - nzpres15->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres15->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres15->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres15->resourceMapping.density.choice.three=(NULL_t)0; - nzpres15->resourceMapping.freqBand.startingRB=0; - nzpres15->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres15->powerControlOffset=0; - nzpres15->powerControlOffsetSS=calloc(1,sizeof(*nzpres15->powerControlOffsetSS)); - *nzpres15->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres15->scramblingID=40; - nzpres15->periodicityAndOffset = calloc(1,sizeof(*nzpres15->periodicityAndOffset)); - nzpres15->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres15->periodicityAndOffset->choice.slots160 = 25; - nzpres15->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres15->qcl_InfoPeriodicCSI_RS)); - *nzpres15->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres15); - NR_NZP_CSI_RS_Resource_t *nzpres16 = calloc(1,sizeof(*nzpres16)); - nzpres16->nzp_CSI_RS_ResourceId=16; - nzpres16->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres16->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres16->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres16->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres16->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=8; - nzpres16->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres16->resourceMapping.firstOFDMSymbolInTimeDomain=5; - nzpres16->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres16->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres16->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres16->resourceMapping.density.choice.three=(NULL_t)0; - nzpres16->resourceMapping.freqBand.startingRB=0; - nzpres16->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres16->powerControlOffset=0; - nzpres16->powerControlOffsetSS=calloc(1,sizeof(*nzpres16->powerControlOffsetSS)); - *nzpres16->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres16->scramblingID=40; - nzpres16->periodicityAndOffset = calloc(1,sizeof(*nzpres16->periodicityAndOffset)); - nzpres16->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres16->periodicityAndOffset->choice.slots160 = 26; - nzpres16->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres16->qcl_InfoPeriodicCSI_RS)); - *nzpres16->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres16); - - NR_NZP_CSI_RS_Resource_t *nzpres17 = calloc(1,sizeof(*nzpres17)); - nzpres17->nzp_CSI_RS_ResourceId=9; - nzpres17->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres17->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres17->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres17->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres17->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=8; - nzpres17->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres17->resourceMapping.firstOFDMSymbolInTimeDomain=9; - nzpres17->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres17->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres17->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres17->resourceMapping.density.choice.three=(NULL_t)0; - nzpres17->resourceMapping.freqBand.startingRB=0; - nzpres17->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres17->powerControlOffset=0; - nzpres17->powerControlOffsetSS=calloc(1,sizeof(*nzpres17->powerControlOffsetSS)); - *nzpres17->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres17->scramblingID=40; - nzpres17->periodicityAndOffset = calloc(1,sizeof(*nzpres17->periodicityAndOffset)); - nzpres17->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres17->periodicityAndOffset->choice.slots160 = 26; - nzpres17->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres17->qcl_InfoPeriodicCSI_RS)); - *nzpres17->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres17); - } - - if (n_physical_antenna_ports > 16) AssertFatal(1==0,"Fill in for more than 16 antenna elements\n"); - - csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList = calloc(1,sizeof(*csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList)); - csi_MeasConfig->nzp_CSI_RS_ResourceSetToReleaseList = NULL; - NR_NZP_CSI_RS_ResourceSet_t *nzpresset0=calloc(1,sizeof(*nzpresset0)); - nzpresset0->nzp_CSI_ResourceSetId=0; - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset00=calloc(1,sizeof(*nzpresset00)); - *nzpresset00=0; - ASN_SEQUENCE_ADD(&nzpresset0->nzp_CSI_RS_Resources.list,nzpresset00); - nzpresset0->repetition=NULL; - nzpresset0->aperiodicTriggeringOffset=NULL; - nzpresset0->trs_Info=NULL; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset0); - if (n_physical_antenna_ports > 1) { - NR_NZP_CSI_RS_ResourceSet_t *nzpresset3=calloc(1,sizeof(*nzpresset3)); - nzpresset3->nzp_CSI_ResourceSetId=3; - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset30=calloc(1,sizeof(*nzpresset30)); - *nzpresset30=2; - ASN_SEQUENCE_ADD(&nzpresset3->nzp_CSI_RS_Resources.list,nzpresset30); - if (n_physical_antenna_ports > 3) { - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset31=calloc(1,sizeof(*nzpresset31)); - *nzpresset31=3; - ASN_SEQUENCE_ADD(&nzpresset3->nzp_CSI_RS_Resources.list,nzpresset31); - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset32=calloc(1,sizeof(*nzpresset32)); - *nzpresset32=4; - ASN_SEQUENCE_ADD(&nzpresset3->nzp_CSI_RS_Resources.list,nzpresset32); - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset33=calloc(1,sizeof(*nzpresset33)); - *nzpresset33=5; - ASN_SEQUENCE_ADD(&nzpresset3->nzp_CSI_RS_Resources.list,nzpresset33); - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset3); - } - nzpresset3->repetition=calloc(1,sizeof(*nzpresset3->repetition)); - *nzpresset3->repetition=NR_NZP_CSI_RS_ResourceSet__repetition_off; - nzpresset3->aperiodicTriggeringOffset=NULL; - nzpresset3->trs_Info=calloc(1,sizeof(*nzpresset3->trs_Info)); - *nzpresset3->trs_Info=NR_NZP_CSI_RS_ResourceSet__trs_Info_true; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset3); - } - - if (n_physical_antenna_ports > 7) { - NR_NZP_CSI_RS_ResourceSet_t *nzpresset4=calloc(1,sizeof(*nzpresset4)); - nzpresset4->nzp_CSI_ResourceSetId=4; - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset40=calloc(1,sizeof(*nzpresset40)); - *nzpresset40=6; - ASN_SEQUENCE_ADD(&nzpresset4->nzp_CSI_RS_Resources.list,nzpresset40); - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset41=calloc(1,sizeof(*nzpresset41)); - *nzpresset41=7; - ASN_SEQUENCE_ADD(&nzpresset4->nzp_CSI_RS_Resources.list,nzpresset41); - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset42=calloc(1,sizeof(*nzpresset42)); - *nzpresset42=8; - ASN_SEQUENCE_ADD(&nzpresset4->nzp_CSI_RS_Resources.list,nzpresset42); - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset43=calloc(1,sizeof(*nzpresset43)); - *nzpresset43=9; - ASN_SEQUENCE_ADD(&nzpresset4->nzp_CSI_RS_Resources.list,nzpresset43); - nzpresset4->repetition=calloc(1,sizeof(*nzpresset4->repetition)); - *nzpresset4->repetition=NR_NZP_CSI_RS_ResourceSet__repetition_off; - nzpresset4->aperiodicTriggeringOffset=NULL; - nzpresset4->trs_Info=calloc(1,sizeof(*nzpresset4->trs_Info)); - *nzpresset4->trs_Info=NR_NZP_CSI_RS_ResourceSet__trs_Info_true; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset4); - } - if (n_physical_antenna_ports > 15) { - NR_NZP_CSI_RS_ResourceSet_t *nzpresset5=calloc(1,sizeof(*nzpresset5)); - nzpresset5->nzp_CSI_ResourceSetId=5; - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset50=calloc(1,sizeof(*nzpresset50)); - *nzpresset50=10; - ASN_SEQUENCE_ADD(&nzpresset5->nzp_CSI_RS_Resources.list,nzpresset50); - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset51=calloc(1,sizeof(*nzpresset51)); - *nzpresset51=11; - ASN_SEQUENCE_ADD(&nzpresset5->nzp_CSI_RS_Resources.list,nzpresset51); - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset52=calloc(1,sizeof(*nzpresset52)); - *nzpresset52=12; - ASN_SEQUENCE_ADD(&nzpresset5->nzp_CSI_RS_Resources.list,nzpresset52); - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset53=calloc(1,sizeof(*nzpresset53)); - *nzpresset53=13; - ASN_SEQUENCE_ADD(&nzpresset5->nzp_CSI_RS_Resources.list,nzpresset53); - nzpresset5->repetition=calloc(1,sizeof(*nzpresset5->repetition)); - *nzpresset5->repetition=NR_NZP_CSI_RS_ResourceSet__repetition_off; - nzpresset5->aperiodicTriggeringOffset=NULL; - nzpresset5->trs_Info=calloc(1,sizeof(*nzpresset5->trs_Info)); - *nzpresset5->trs_Info=NR_NZP_CSI_RS_ResourceSet__trs_Info_true; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset5); - } - - csi_MeasConfig->csi_IM_ResourceToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_IM_ResourceToAddModList)); - csi_MeasConfig->csi_IM_ResourceToReleaseList = NULL; - NR_CSI_IM_Resource_t *imres0 = calloc(1,sizeof(*imres0)); - imres0->csi_IM_ResourceId=0; - imres0->csi_IM_ResourceElementPattern=calloc(1,sizeof(*imres0->csi_IM_ResourceElementPattern)); - imres0->csi_IM_ResourceElementPattern->present = NR_CSI_IM_Resource__csi_IM_ResourceElementPattern_PR_pattern1 ; - imres0->csi_IM_ResourceElementPattern->choice.pattern1=calloc(1,sizeof(*imres0->csi_IM_ResourceElementPattern->choice.pattern1)); - imres0->csi_IM_ResourceElementPattern->choice.pattern1->subcarrierLocation_p1 = NR_CSI_IM_Resource__csi_IM_ResourceElementPattern__pattern1__subcarrierLocation_p1_s4; - imres0->csi_IM_ResourceElementPattern->choice.pattern1->symbolLocation_p1=7; - imres0->freqBand=calloc(1,sizeof(*imres0->freqBand)); - imres0->freqBand->startingRB=0; - imres0->freqBand->nrofRBs=276; - imres0->periodicityAndOffset=calloc(1,sizeof(*imres0->periodicityAndOffset)); - imres0->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots320; - imres0->periodicityAndOffset->choice.slots320 = 2; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_IM_ResourceToAddModList->list,imres0); - csi_MeasConfig->csi_IM_ResourceSetToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_IM_ResourceSetToAddModList)); - csi_MeasConfig->csi_IM_ResourceSetToReleaseList = NULL; - NR_CSI_IM_ResourceSet_t *imresset0 = calloc(1,sizeof(*imresset0)); - imresset0->csi_IM_ResourceSetId=0; - NR_CSI_IM_ResourceId_t *imresset00=calloc(1,sizeof(*imresset00)); - *imresset00=0; - ASN_SEQUENCE_ADD(&imresset0->csi_IM_Resources.list,imresset00); - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_IM_ResourceSetToAddModList->list,imresset0); - - csi_MeasConfig->csi_SSB_ResourceSetToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_SSB_ResourceSetToAddModList)); - csi_MeasConfig->csi_SSB_ResourceSetToReleaseList = NULL; - NR_CSI_SSB_ResourceSet_t *ssbresset0 = calloc(1,sizeof(*ssbresset0)); - ssbresset0->csi_SSB_ResourceSetId=0; - NR_SSB_Index_t *ssbresset00=calloc(1,sizeof(*ssbresset00)); - *ssbresset00=0; - ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset00); - if (n_physical_antenna_ports > 1) { - NR_SSB_Index_t *ssbresset01=calloc(1,sizeof(*ssbresset01)); - *ssbresset01=1; - ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset01); - } - if (n_physical_antenna_ports > 3) { - NR_SSB_Index_t *ssbresset02=calloc(1,sizeof(*ssbresset02)); - *ssbresset02=2; - ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset02); - NR_SSB_Index_t *ssbresset03=calloc(1,sizeof(*ssbresset03)); - *ssbresset03=3; - ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset03); - } - if (n_physical_antenna_ports > 7) { - NR_SSB_Index_t *ssbresset04=calloc(1,sizeof(*ssbresset04)); - *ssbresset04=4; - ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset04); - NR_SSB_Index_t *ssbresset05=calloc(1,sizeof(*ssbresset05)); - *ssbresset05=5; - ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset05); - NR_SSB_Index_t *ssbresset06=calloc(1,sizeof(*ssbresset06)); - *ssbresset06=6; - ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset06); - NR_SSB_Index_t *ssbresset07=calloc(1,sizeof(*ssbresset07)); - *ssbresset07=7; - ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset07); - } - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_SSB_ResourceSetToAddModList->list,ssbresset0); - - csi_MeasConfig->csi_ResourceConfigToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_ResourceConfigToAddModList)); - csi_MeasConfig->csi_ResourceConfigToReleaseList = NULL; - NR_CSI_ResourceConfig_t *csires0 = calloc(1,sizeof(*csires0)); - csires0->csi_ResourceConfigId=0; - csires0->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires00 = calloc(1,sizeof(*csires00)); - *csires00 = 0; - ASN_SEQUENCE_ADD(&csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires00); - csires0->bwp_Id = 1; - csires0->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires0); - - NR_CSI_ResourceConfig_t *csires11 = calloc(1,sizeof(*csires11)); - csires11->csi_ResourceConfigId=11; - csires11->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_csi_IM_ResourceSetList; - csires11->csi_RS_ResourceSetList.choice.csi_IM_ResourceSetList = calloc(1,sizeof(*csires11->csi_RS_ResourceSetList.choice.csi_IM_ResourceSetList)); - NR_NZP_CSI_RS_ResourceSetId_t *csires110 = calloc(1,sizeof(*csires110)); - *csires110 = 0; - ASN_SEQUENCE_ADD(&csires11->csi_RS_ResourceSetList.choice.csi_IM_ResourceSetList->list,csires110); - csires11->bwp_Id = 1; - csires11->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires11); - - NR_CSI_ResourceConfig_t *csires10 = calloc(1,sizeof(*csires10)); - csires10->csi_ResourceConfigId=10; - csires10->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires100 = calloc(1,sizeof(*csires100)); - *csires100 = 0; - ASN_SEQUENCE_ADD(&csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires100); - csires10->bwp_Id = 1; - csires10->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires10); - - NR_CSI_ResourceConfig_t *csires2 = calloc(1,sizeof(*csires2)); - csires2->csi_ResourceConfigId=2; - csires2->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires20 = calloc(1,sizeof(*csires20)); - *csires20 = 0; - ASN_SEQUENCE_ADD(&csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires20); - csires2->bwp_Id = 1; - csires2->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires2); - - NR_CSI_ResourceConfig_t *csires3 = calloc(1,sizeof(*csires3)); - csires3->csi_ResourceConfigId=3; - csires3->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires30 = calloc(1,sizeof(*csires30)); - *csires30 = 0; - ASN_SEQUENCE_ADD(&csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires30); - csires3->bwp_Id = 1; - csires3->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires3); - - NR_CSI_ResourceConfig_t *csires4 = calloc(1,sizeof(*csires4)); - csires4->csi_ResourceConfigId=4; - csires4->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires40 = calloc(1,sizeof(*csires40)); - *csires40 = 0; - ASN_SEQUENCE_ADD(&csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires40); - csires4->bwp_Id = 1; - csires4->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires4); - - NR_CSI_ResourceConfig_t *csires5 = calloc(1,sizeof(*csires5)); - csires5->csi_ResourceConfigId=5; - csires5->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires50 = calloc(1,sizeof(*csires50)); - *csires50 = 0; - ASN_SEQUENCE_ADD(&csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires50); - csires5->bwp_Id = 1; - csires5->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires5); - - NR_CSI_ResourceConfig_t *csires6 = calloc(1,sizeof(*csires6)); - csires6->csi_ResourceConfigId=6; - csires6->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires60 = calloc(1,sizeof(*csires60)); - *csires60 = 0; - ASN_SEQUENCE_ADD(&csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires60); - csires6->bwp_Id = 1; - csires6->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires6); - - NR_CSI_ResourceConfig_t *csires7 = calloc(1,sizeof(*csires7)); - csires7->csi_ResourceConfigId=7; - csires7->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires70 = calloc(1,sizeof(*csires70)); - *csires70 = 0; - ASN_SEQUENCE_ADD(&csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires70); - csires7->bwp_Id = 1; - csires7->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires7); - - NR_CSI_ResourceConfig_t *csires8 = calloc(1,sizeof(*csires8)); - csires8->csi_ResourceConfigId=8; - csires8->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires80 = calloc(1,sizeof(*csires80)); - *csires80 = 0; - ASN_SEQUENCE_ADD(&csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires80); - csires8->bwp_Id = 1; - csires8->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires8); - - NR_CSI_ResourceConfig_t *csires9 = calloc(1,sizeof(*csires9)); - csires9->csi_ResourceConfigId=9; - csires9->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires90 = calloc(1,sizeof(*csires90)); - *csires90 = 0; - ASN_SEQUENCE_ADD(&csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires90); - csires9->bwp_Id = 1; - csires9->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires9); - - csi_MeasConfig->csi_ReportConfigToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_ReportConfigToAddModList)); - csi_MeasConfig->csi_ReportConfigToReleaseList = NULL; - NR_CSI_ReportConfig_t *csirep0 = calloc(1,sizeof(*csirep0)); - csirep0->reportConfigId=0; - csirep0->carrier=NULL; - csirep0->resourcesForChannelMeasurement=0; - csirep0->csi_IM_ResourcesForInterference=calloc(1,sizeof(*csirep0->csi_IM_ResourcesForInterference)); - *csirep0->csi_IM_ResourcesForInterference=11; - csirep0->nzp_CSI_RS_ResourcesForInterference=NULL; - csirep0->reportConfigType.present = NR_CSI_ReportConfig__reportConfigType_PR_periodic; - csirep0->reportConfigType.choice.periodic = calloc(1,sizeof(*csirep0->reportConfigType.choice.periodic)); - csirep0->reportConfigType.choice.periodic->reportSlotConfig.present=NR_CSI_ReportPeriodicityAndOffset_PR_slots320; - csirep0->reportConfigType.choice.periodic->reportSlotConfig.choice.slots320 = 9; - - NR_PUCCH_CSI_Resource_t *pucchcsires0 = calloc(1,sizeof(*pucchcsires0)); - pucchcsires0->uplinkBandwidthPartId=1; - pucchcsires0->pucch_Resource=11; - ASN_SEQUENCE_ADD(&csirep0->reportConfigType.choice.periodic->pucch_CSI_ResourceList.list,pucchcsires0); - csirep0->reportQuantity.present = NR_CSI_ReportConfig__reportQuantity_PR_cri_RI_LI_PMI_CQI; - csirep0->reportQuantity.choice.cri_RI_PMI_CQI = (NULL_t)0; - csirep0->reportFreqConfiguration = calloc(1,sizeof(*csirep0->reportFreqConfiguration)); - csirep0->reportFreqConfiguration->cqi_FormatIndicator=NR_CSI_ReportConfig__reportFreqConfiguration__cqi_FormatIndicator_widebandCQI; - csirep0->reportFreqConfiguration->pmi_FormatIndicator=NR_CSI_ReportConfig__reportFreqConfiguration__pmi_FormatIndicator_widebandPMI; - csirep0->reportFreqConfiguration->csi_ReportingBand=calloc(1,sizeof(*csirep0->reportFreqConfiguration->csi_ReportingBand)); - - - AssertFatal(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id>0,"firstActiveDownlinkBWP_Id %d\n",(int)*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id); - int NPRB = NRRIV2BW(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id-1]->bwp_Common->genericParameters.locationAndBandwidth,275); - int sbsize = get_subband_size(NPRB,0); - int numsb = NPRB/sbsize; - if (NPRB%sbsize == 0) numsb++; - csirep0->reportFreqConfiguration->csi_ReportingBand->present= NR_CSI_ReportConfig__reportFreqConfiguration__csi_ReportingBand_PR_NOTHING+(numsb-2); - csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.size=numsb/8; - if ((numsb&7) > 0) csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.size++; - csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.bits_unused = (8-(numsb&7))&7; - csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.buf=malloc(csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.size); - for (int i=0;ireportFreqConfiguration->csi_ReportingBand->choice.subbands18.size;i++) - csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.buf[i]=0xff; - csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.buf[csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.size-1]&=~((1<reportFreqConfiguration->csi_ReportingBand->choice.subbands18.bits_unused)-1); - - csirep0->timeRestrictionForChannelMeasurements= NR_CSI_ReportConfig__timeRestrictionForChannelMeasurements_configured; - csirep0->timeRestrictionForInterferenceMeasurements=NR_CSI_ReportConfig__timeRestrictionForInterferenceMeasurements_configured; - csirep0->codebookConfig=calloc(1,sizeof(*csirep0->codebookConfig)); - csirep0->codebookConfig->codebookType.present = NR_CodebookConfig__codebookType_PR_type1; - csirep0->codebookConfig->codebookType.choice.type1 = calloc(1,sizeof(*csirep0->codebookConfig->codebookType.choice.type1)); - csirep0->codebookConfig->codebookType.choice.type1->subType.present = NR_CodebookConfig__codebookType__type1__subType_PR_typeI_SinglePanel; - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel=calloc(1,sizeof(*csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel)); - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.present=NR_CodebookConfig__codebookType__type1__subType__typeI_SinglePanel__nrOfAntennaPorts_PR_two; - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two= - calloc(1,sizeof(*csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two)); - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.size=1; - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.bits_unused=2; - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.buf=malloc(1); - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.buf[0]=0xfc; - //'111111'B - - - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.size=1; - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.bits_unused=0; - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.buf=malloc(1); - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.buf[0]=0xc0; //'00000011'B - - csirep0->codebookConfig->codebookType.choice.type1->codebookMode=1; - csirep0->dummy = NULL; - csirep0->groupBasedBeamReporting.present = NR_CSI_ReportConfig__groupBasedBeamReporting_PR_disabled; - csirep0->groupBasedBeamReporting.choice.disabled=calloc(1,sizeof(*csirep0->groupBasedBeamReporting.choice.disabled)); - csirep0->groupBasedBeamReporting.choice.disabled->nrofReportedRS = NULL; - csirep0->cqi_Table = calloc(1,sizeof(*csirep0->cqi_Table)); - *csirep0->cqi_Table = NR_CSI_ReportConfig__cqi_Table_table1; - csirep0->subbandSize = NR_CSI_ReportConfig__subbandSize_value1; - csirep0->non_PMI_PortIndication = NULL; - csirep0->ext1 = NULL; - - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ReportConfigToAddModList->list,csirep0); - - NR_CSI_ReportConfig_t *csirep1 = calloc(1,sizeof(*csirep1)); - csirep1->reportConfigId=2; - csirep1->carrier=NULL; - csirep1->resourcesForChannelMeasurement=initial_csi_index; - csirep1->csi_IM_ResourcesForInterference=NULL; - csirep1->nzp_CSI_RS_ResourcesForInterference=NULL; - csirep1->reportConfigType.present = NR_CSI_ReportConfig__reportConfigType_PR_periodic; - csirep1->reportConfigType.choice.periodic = calloc(1,sizeof(*csirep1->reportConfigType.choice.periodic)); - csirep1->reportConfigType.choice.periodic->reportSlotConfig.present=NR_CSI_ReportPeriodicityAndOffset_PR_slots320; - csirep1->reportConfigType.choice.periodic->reportSlotConfig.choice.slots320 = 49; - NR_PUCCH_CSI_Resource_t *pucchcsires1 = calloc(1,sizeof(*pucchcsires1)); - pucchcsires1->uplinkBandwidthPartId=1; - pucchcsires1->pucch_Resource=12; - ASN_SEQUENCE_ADD(&csirep1->reportConfigType.choice.periodic->pucch_CSI_ResourceList.list,pucchcsires1); - csirep1->reportQuantity.present = NR_CSI_ReportConfig__reportQuantity_PR_ssb_Index_RSRP; - csirep1->reportQuantity.choice.ssb_Index_RSRP=(NULL_t)0; - csirep1->reportFreqConfiguration = calloc(1,sizeof(*csirep1->reportFreqConfiguration)); - csirep1->reportFreqConfiguration->cqi_FormatIndicator=NR_CSI_ReportConfig__reportFreqConfiguration__cqi_FormatIndicator_widebandCQI; - csirep1->reportFreqConfiguration->pmi_FormatIndicator=NR_CSI_ReportConfig__reportFreqConfiguration__pmi_FormatIndicator_widebandPMI; - csirep1->reportFreqConfiguration->csi_ReportingBand=NULL; - csirep1->timeRestrictionForChannelMeasurements= NR_CSI_ReportConfig__timeRestrictionForChannelMeasurements_configured; - csirep1->timeRestrictionForInterferenceMeasurements=NR_CSI_ReportConfig__timeRestrictionForInterferenceMeasurements_configured; - csirep1->codebookConfig=calloc(1,sizeof(*csirep1->codebookConfig)); - csirep1->codebookConfig->codebookType.present = NR_CodebookConfig__codebookType_PR_type1; - csirep1->codebookConfig->codebookType.choice.type1 = calloc(1,sizeof(*csirep1->codebookConfig->codebookType.choice.type1)); - csirep1->codebookConfig->codebookType.choice.type1->subType.present=NR_CodebookConfig__codebookType__type1__subType_PR_typeI_SinglePanel; - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel=calloc(1,sizeof(*csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel)); - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.present=NR_CodebookConfig__codebookType__type1__subType__typeI_SinglePanel__nrOfAntennaPorts_PR_two; - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two= - calloc(1,sizeof(*csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two)); - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.size=1; - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.bits_unused=2; - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.buf=malloc(1); - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.buf[0]=0xfc; - //'111111'B - - - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.size=1; - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.bits_unused=0; - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.buf=malloc(1); - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.buf[0]=0xc0; //'00000011'B - - csirep1->codebookConfig->codebookType.choice.type1->codebookMode=1; - csirep1->dummy = NULL; - csirep1->groupBasedBeamReporting.present = NR_CSI_ReportConfig__groupBasedBeamReporting_PR_disabled; - csirep1->groupBasedBeamReporting.choice.disabled=calloc(1,sizeof(*csirep1->groupBasedBeamReporting.choice.disabled)); - csirep1->groupBasedBeamReporting.choice.disabled->nrofReportedRS = calloc(1,sizeof(*csirep1->groupBasedBeamReporting.choice.disabled->nrofReportedRS)); - *csirep1->groupBasedBeamReporting.choice.disabled->nrofReportedRS=NR_CSI_ReportConfig__groupBasedBeamReporting__disabled__nrofReportedRS_n2; - // this corresponds to: - //if the UE is configured with the higher layer parameter groupBasedBeamReporting set to 'disabled', the UE is not required to update measurements for more than 64 CSI-RS and/or SSB resources, and the UE shall report in a single report nrofReportedRS (higher layer configured) different CRI or SSBRI for each report setting. - - csirep1->cqi_Table = calloc(1,sizeof(*csirep1->cqi_Table)); - *csirep1->cqi_Table = NR_CSI_ReportConfig__cqi_Table_table1; - csirep1->subbandSize = NR_CSI_ReportConfig__subbandSize_value1; - csirep1->non_PMI_PortIndication = NULL; - csirep1->ext1 = NULL; - - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ReportConfigToAddModList->list,csirep1); - - - secondaryCellGroup->spCellConfig->spCellConfigDedicated->sCellDeactivationTimer=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->tag_Id=0; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->dummy=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->pathlossReferenceLinking=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->servingCellMO=NULL; - + bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup = calloc(1, + sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup)); + bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->maxLength=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->scramblingID0=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->scramblingID1=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->phaseTrackingRS=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = calloc(1, + sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition)); + *bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList=calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList)); + NR_TCI_State_t *tcid0=calloc(1,sizeof(*tcid0)); + tcid0->tci_StateId=0; + tcid0->qcl_Type1.cell=NULL; + tcid0->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid0->qcl_Type1.bwp_Id)); + *tcid0->qcl_Type1.bwp_Id=1; + tcid0->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tcid0->qcl_Type1.referenceSignal.choice.csi_rs = 2; + tcid0->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid0); + NR_TCI_State_t *tcid1=calloc(1,sizeof(*tcid1)); + tcid1->tci_StateId=0; + tcid1->qcl_Type1.cell=NULL; + tcid1->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid1->qcl_Type1.bwp_Id)); + *tcid1->qcl_Type1.bwp_Id=1; + tcid1->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tcid1->qcl_Type1.referenceSignal.choice.csi_rs = 6; + tcid1->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid1); + NR_TCI_State_t *tcid2=calloc(1,sizeof(*tcid2)); + tcid2->tci_StateId=2; + tcid2->qcl_Type1.cell=NULL; + tcid2->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid2->qcl_Type1.bwp_Id)); + *tcid2->qcl_Type1.bwp_Id=1; + tcid2->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tcid2->qcl_Type1.referenceSignal.choice.csi_rs = 10; + tcid2->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid2); + NR_TCI_State_t *tcid3=calloc(1,sizeof(*tcid3)); + tcid3->tci_StateId=3; + tcid3->qcl_Type1.cell=NULL; + tcid3->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid3->qcl_Type1.bwp_Id)); + *tcid3->qcl_Type1.bwp_Id=1; + tcid3->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tcid3->qcl_Type1.referenceSignal.choice.csi_rs = 14; + tcid3->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid3); + NR_TCI_State_t *tcid4=calloc(1,sizeof(*tcid4)); + tcid4->tci_StateId=4; + tcid4->qcl_Type1.cell=NULL; + tcid4->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid4->qcl_Type1.bwp_Id)); + *tcid4->qcl_Type1.bwp_Id=1; + tcid4->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tcid4->qcl_Type1.referenceSignal.choice.csi_rs = 18; + tcid4->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid4); + NR_TCI_State_t *tcid5=calloc(1,sizeof(*tcid5)); + tcid5->tci_StateId=5; + tcid5->qcl_Type1.cell=NULL; + tcid5->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid5->qcl_Type1.bwp_Id)); + *tcid5->qcl_Type1.bwp_Id=1; + tcid5->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tcid5->qcl_Type1.referenceSignal.choice.csi_rs = 22; + tcid5->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid5); + NR_TCI_State_t *tcid6=calloc(1,sizeof(*tcid6)); + tcid6->tci_StateId=6; + tcid6->qcl_Type1.cell=NULL; + tcid6->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid6->qcl_Type1.bwp_Id)); + *tcid6->qcl_Type1.bwp_Id=1; + tcid6->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tcid6->qcl_Type1.referenceSignal.choice.csi_rs = 26; + tcid6->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid6); + NR_TCI_State_t *tcid7=calloc(1,sizeof(*tcid7)); + tcid7->tci_StateId=7; + tcid7->qcl_Type1.cell=NULL; + tcid7->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid7->qcl_Type1.bwp_Id)); + *tcid7->qcl_Type1.bwp_Id=1; + tcid7->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; + tcid7->qcl_Type1.referenceSignal.choice.csi_rs = 30; + tcid7->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid7); + NR_TCI_State_t *tcid8=calloc(1,sizeof(*tcid8)); + tcid8->tci_StateId=8; + tcid8->qcl_Type1.cell=NULL; + tcid8->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid8->qcl_Type1.bwp_Id)); + *tcid8->qcl_Type1.bwp_Id=1; + tcid8->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tcid8->qcl_Type1.referenceSignal.choice.ssb = 0; + tcid8->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid8); + NR_TCI_State_t *tcid9=calloc(1,sizeof(*tcid9)); + tcid9->tci_StateId=9; + tcid9->qcl_Type1.cell=NULL; + tcid9->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid9->qcl_Type1.bwp_Id)); + *tcid9->qcl_Type1.bwp_Id=1; + tcid9->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tcid9->qcl_Type1.referenceSignal.choice.ssb = 1; + tcid9->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid9); + NR_TCI_State_t *tcid10=calloc(1,sizeof(*tcid10)); + tcid10->tci_StateId=10; + tcid10->qcl_Type1.cell=NULL; + tcid10->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid10->qcl_Type1.bwp_Id)); + *tcid10->qcl_Type1.bwp_Id=1; + tcid10->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tcid10->qcl_Type1.referenceSignal.choice.ssb = 2; + tcid10->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid10); + NR_TCI_State_t *tcid11=calloc(1,sizeof(*tcid11)); + tcid11->tci_StateId=11; + tcid11->qcl_Type1.cell=NULL; + tcid11->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid11->qcl_Type1.bwp_Id)); + *tcid11->qcl_Type1.bwp_Id=1; + tcid11->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tcid11->qcl_Type1.referenceSignal.choice.ssb = 3; + tcid11->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid11); + NR_TCI_State_t *tcid12=calloc(1,sizeof(*tcid12)); + tcid12->tci_StateId=12; + tcid12->qcl_Type1.cell=NULL; + tcid12->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid12->qcl_Type1.bwp_Id)); + *tcid12->qcl_Type1.bwp_Id=1; + tcid12->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tcid12->qcl_Type1.referenceSignal.choice.ssb = 4; + tcid12->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid12); + NR_TCI_State_t *tcid13=calloc(1,sizeof(*tcid13)); + tcid13->tci_StateId=13; + tcid13->qcl_Type1.cell=NULL; + tcid13->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid13->qcl_Type1.bwp_Id)); + *tcid13->qcl_Type1.bwp_Id=1; + tcid13->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tcid13->qcl_Type1.referenceSignal.choice.ssb = 5; + tcid13->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid13); + NR_TCI_State_t *tcid14=calloc(1,sizeof(*tcid14)); + tcid14->tci_StateId=14; + tcid14->qcl_Type1.cell=NULL; + tcid14->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid14->qcl_Type1.bwp_Id)); + *tcid14->qcl_Type1.bwp_Id=1; + tcid14->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tcid14->qcl_Type1.referenceSignal.choice.ssb = 6; + tcid14->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid14); + NR_TCI_State_t *tcid15=calloc(1,sizeof(*tcid15)); + tcid15->tci_StateId=15; + tcid15->qcl_Type1.cell=NULL; + tcid15->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid15->qcl_Type1.bwp_Id)); + *tcid15->qcl_Type1.bwp_Id=1; + tcid15->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; + tcid15->qcl_Type1.referenceSignal.choice.ssb = 7; + tcid15->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; + ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid15); + bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup1=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup2=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rbg_Size=NR_PDSCH_Config__rbg_Size_config1; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->mcs_Table=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI)); + *bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = NR_PDSCH_Config__maxNrofCodeWordsScheduledByDCI_n1; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.present = NR_PDSCH_Config__prb_BundlingType_PR_staticBundling; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling)); + bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = + calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize)); + *bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = NR_PDSCH_Config__prb_BundlingType__staticBundling__bundleSize_wideband; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToAddModList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToAddModList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup1=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup2=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->rbg_Size=NR_PDSCH_Config__rbg_Size_config1; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->mcs_Table=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI)); + *bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = NR_PDSCH_Config__maxNrofCodeWordsScheduledByDCI_n1; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.present = NR_PDSCH_Config__prb_BundlingType_PR_staticBundling; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling)); + bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = + calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize)); + *bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = NR_PDSCH_Config__prb_BundlingType__staticBundling__bundleSize_wideband; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToAddModList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToAddModList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; + bwp->bwp_Dedicated->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL; + bwp->bwp_Dedicated->sps_Config = NULL; //calloc(1,sizeof(struct NR_SetupRelease_SPS_Config)); + bwp->bwp_Dedicated->radioLinkMonitoringConfig = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig)); + bwp->bwp_Dedicated->radioLinkMonitoringConfig->present = NR_SetupRelease_RadioLinkMonitoringConfig_PR_setup; + bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup)); + bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->failureDetectionResourcesToAddModList=NULL; + bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->failureDetectionResourcesToReleaseList=NULL; + bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount)); + *bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = NR_RadioLinkMonitoringConfig__beamFailureInstanceMaxCount_n3; + bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer)); + *bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = NR_RadioLinkMonitoringConfig__beamFailureDetectionTimer_pbfd2; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list,bwp); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id)); + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id=1; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->bwp_InactivityTimer = NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->defaultDownlinkBWP_Id = NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig)); + NR_BWP_UplinkDedicated_t *initialUplinkBWP = calloc(1,sizeof(*initialUplinkBWP)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->initialUplinkBWP = initialUplinkBWP; + initialUplinkBWP->pucch_Config = NULL; + initialUplinkBWP->pusch_Config = calloc(1,sizeof(*initialUplinkBWP->pusch_Config)); + initialUplinkBWP->pusch_Config->present = NR_SetupRelease_PUSCH_Config_PR_setup; + NR_PUSCH_Config_t *pusch_Config = calloc(1,sizeof(*pusch_Config)); + initialUplinkBWP->pusch_Config->choice.setup = pusch_Config; + pusch_Config->txConfig=calloc(1,sizeof(*pusch_Config->txConfig)); + *pusch_Config->txConfig= NR_PUSCH_Config__txConfig_codebook; + pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA = NULL; + pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB = calloc(1,sizeof(*pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB)); + pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->present = NR_SetupRelease_DMRS_UplinkConfig_PR_setup; + pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup = calloc(1,sizeof(*pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup)); + NR_DMRS_UplinkConfig_t *NR_DMRS_UplinkConfig = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup; + NR_DMRS_UplinkConfig->dmrs_Type = NULL; + NR_DMRS_UplinkConfig->dmrs_AdditionalPosition =NR_DMRS_UplinkConfig__dmrs_AdditionalPosition_pos0; + NR_DMRS_UplinkConfig->phaseTrackingRS=NULL; + NR_DMRS_UplinkConfig->maxLength=NULL; + NR_DMRS_UplinkConfig->transformPrecodingDisabled = calloc(1,sizeof(*NR_DMRS_UplinkConfig->transformPrecodingDisabled)); + NR_DMRS_UplinkConfig->transformPrecodingDisabled->scramblingID0 = NULL; + NR_DMRS_UplinkConfig->transformPrecodingDisabled->scramblingID1 = NULL; + NR_DMRS_UplinkConfig->transformPrecodingEnabled = NULL; + pusch_Config->pusch_PowerControl = calloc(1,sizeof(*pusch_Config->pusch_PowerControl)); + pusch_Config->pusch_PowerControl->tpc_Accumulation = NULL; + pusch_Config->pusch_PowerControl->msg3_Alpha = calloc(1,sizeof(*pusch_Config->pusch_PowerControl->msg3_Alpha)); + *pusch_Config->pusch_PowerControl->msg3_Alpha = NR_Alpha_alpha1; + pusch_Config->pusch_PowerControl->p0_NominalWithoutGrant = NULL; + pusch_Config->pusch_PowerControl->p0_AlphaSets = calloc(1,sizeof(*pusch_Config->pusch_PowerControl->p0_AlphaSets)); + NR_P0_PUSCH_AlphaSet_t *aset = calloc(1,sizeof(*aset)); + aset->p0_PUSCH_AlphaSetId=0; + aset->p0=calloc(1,sizeof(*aset->p0)); + *aset->p0 = 0; + aset->alpha=calloc(1,sizeof(*aset->alpha)); + *aset->alpha=NR_Alpha_alpha1; + ASN_SEQUENCE_ADD(&pusch_Config->pusch_PowerControl->p0_AlphaSets->list,aset); + pusch_Config->pusch_PowerControl->pathlossReferenceRSToAddModList = calloc(1,sizeof(*pusch_Config->pusch_PowerControl->pathlossReferenceRSToAddModList)); + NR_PUSCH_PathlossReferenceRS_t *pl = calloc(1,sizeof(*pl)); + pl->pusch_PathlossReferenceRS_Id=0; + pl->referenceSignal.present = NR_PUSCH_PathlossReferenceRS__referenceSignal_PR_csi_RS_Index; + pl->referenceSignal.choice.csi_RS_Index=0; + ASN_SEQUENCE_ADD(&pusch_Config->pusch_PowerControl->pathlossReferenceRSToAddModList->list,pl); + pusch_Config->pusch_PowerControl->pathlossReferenceRSToReleaseList = NULL; + pusch_Config->pusch_PowerControl->twoPUSCH_PC_AdjustmentStates = NULL; + pusch_Config->pusch_PowerControl->deltaMCS = NULL; + pusch_Config->pusch_PowerControl->sri_PUSCH_MappingToAddModList = NULL; + pusch_Config->pusch_PowerControl->sri_PUSCH_MappingToReleaseList = NULL; + pusch_Config->frequencyHopping=NULL; + pusch_Config->frequencyHoppingOffsetLists=NULL; + pusch_Config->resourceAllocation = NR_PUSCH_Config__resourceAllocation_resourceAllocationType1; + pusch_Config->pusch_TimeDomainAllocationList = NULL; + pusch_Config->pusch_AggregationFactor=NULL; + pusch_Config->mcs_Table=NULL; + pusch_Config->mcs_TableTransformPrecoder=NULL; + pusch_Config->transformPrecoder=calloc(1,sizeof(*pusch_Config->transformPrecoder)); + *pusch_Config->transformPrecoder = NR_PUSCH_Config__transformPrecoder_disabled; + pusch_Config->codebookSubset=calloc(1,sizeof(*pusch_Config->codebookSubset)); + *pusch_Config->codebookSubset = NR_PUSCH_Config__codebookSubset_nonCoherent; + pusch_Config->maxRank=calloc(1,sizeof(*pusch_Config->maxRank)); + *pusch_Config->maxRank= 1; + pusch_Config->rbg_Size=NULL; + pusch_Config->uci_OnPUSCH=NULL; + pusch_Config->tp_pi2BPSK=NULL; + initialUplinkBWP->srs_Config = calloc(1,sizeof(*initialUplinkBWP->srs_Config)); + initialUplinkBWP->srs_Config->present = NR_SetupRelease_SRS_Config_PR_setup; + NR_SRS_Config_t *srs_Config = calloc(1,sizeof(*srs_Config)); + initialUplinkBWP->srs_Config->choice.setup=srs_Config; + srs_Config->srs_ResourceSetToReleaseList=NULL; + srs_Config->srs_ResourceSetToAddModList=calloc(1,sizeof(*srs_Config->srs_ResourceSetToAddModList)); + NR_SRS_ResourceSet_t *srs_resset0=calloc(1,sizeof(*srs_resset0)); + srs_resset0->srs_ResourceSetId = 0; + srs_resset0->srs_ResourceIdList=calloc(1,sizeof(*srs_resset0->srs_ResourceIdList)); + NR_SRS_ResourceId_t *srs_resset0_id=calloc(1,sizeof(*srs_resset0_id)); + *srs_resset0_id=0; + ASN_SEQUENCE_ADD(&srs_resset0->srs_ResourceIdList->list,srs_resset0_id); + srs_Config->srs_ResourceToReleaseList=NULL; + srs_resset0->resourceType.present = NR_SRS_ResourceSet__resourceType_PR_aperiodic; + srs_resset0->resourceType.choice.aperiodic = calloc(1,sizeof(*srs_resset0->resourceType.choice.aperiodic)); + srs_resset0->resourceType.choice.aperiodic->aperiodicSRS_ResourceTrigger=1; + srs_resset0->resourceType.choice.aperiodic->csi_RS=NULL; + srs_resset0->resourceType.choice.aperiodic->slotOffset= calloc(1,sizeof(*srs_resset0->resourceType.choice.aperiodic->slotOffset)); + *srs_resset0->resourceType.choice.aperiodic->slotOffset=2; + srs_resset0->resourceType.choice.aperiodic->ext1=NULL; + srs_resset0->usage=NR_SRS_ResourceSet__usage_codebook; + srs_resset0->alpha = calloc(1,sizeof(*srs_resset0->alpha)); + *srs_resset0->alpha = NR_Alpha_alpha1; + srs_resset0->p0=calloc(1,sizeof(*srs_resset0->p0)); + *srs_resset0->p0=-80; + srs_resset0->pathlossReferenceRS=NULL; + srs_resset0->srs_PowerControlAdjustmentStates=NULL; + ASN_SEQUENCE_ADD(&srs_Config->srs_ResourceSetToAddModList->list,srs_resset0); + srs_Config->srs_ResourceToReleaseList=NULL; + srs_Config->srs_ResourceToAddModList=calloc(1,sizeof(*srs_Config->srs_ResourceToAddModList)); + NR_SRS_Resource_t *srs_res0=calloc(1,sizeof(*srs_res0)); + srs_res0->srs_ResourceId=0; + srs_res0->nrofSRS_Ports=NR_SRS_Resource__nrofSRS_Ports_port1; + srs_res0->ptrs_PortIndex=NULL; + srs_res0->transmissionComb.present=NR_SRS_Resource__transmissionComb_PR_n2; + srs_res0->transmissionComb.choice.n2=calloc(1,sizeof(*srs_res0->transmissionComb.choice.n2)); + srs_res0->transmissionComb.choice.n2->combOffset_n2=0; + srs_res0->transmissionComb.choice.n2->cyclicShift_n2=0; + srs_res0->resourceMapping.startPosition=2; + srs_res0->resourceMapping.nrofSymbols=NR_SRS_Resource__resourceMapping__nrofSymbols_n1; + srs_res0->resourceMapping.repetitionFactor=NR_SRS_Resource__resourceMapping__repetitionFactor_n1; + srs_res0->freqDomainPosition=0; + srs_res0->freqDomainShift=0; + srs_res0->freqHopping.c_SRS = 61; + srs_res0->freqHopping.b_SRS=0; + srs_res0->freqHopping.b_hop=0; + srs_res0->groupOrSequenceHopping=NR_SRS_Resource__groupOrSequenceHopping_neither; + srs_res0->resourceType.present= NR_SRS_Resource__resourceType_PR_aperiodic; + srs_res0->resourceType.choice.aperiodic=calloc(1,sizeof(*srs_res0->resourceType.choice.aperiodic)); + srs_res0->sequenceId=40; + srs_res0->spatialRelationInfo=calloc(1,sizeof(*srs_res0->spatialRelationInfo)); + srs_res0->spatialRelationInfo->servingCellId=NULL; + srs_res0->spatialRelationInfo->referenceSignal.present=NR_SRS_SpatialRelationInfo__referenceSignal_PR_csi_RS_Index; + srs_res0->spatialRelationInfo->referenceSignal.choice.csi_RS_Index=0; + ASN_SEQUENCE_ADD(&srs_Config->srs_ResourceToAddModList->list,srs_res0); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToReleaseList = NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList = calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList)); + NR_BWP_Uplink_t *ubwp = calloc(1,sizeof(*ubwp)); + ubwp->bwp_Id=1; + ubwp->bwp_Common = calloc(1,sizeof(*ubwp->bwp_Common)); + // copy bwp_Common from Initial UL BWP except for bandwidth + memcpy((void *)&ubwp->bwp_Common->genericParameters, + (void *)&servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->genericParameters, + sizeof(servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->genericParameters)); + ubwp->bwp_Common->genericParameters.locationAndBandwidth=PRBalloc_to_locationandbandwidth( + servingcellconfigcommon->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth,0); + ubwp->bwp_Common->rach_ConfigCommon = servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon; + ubwp->bwp_Common->pusch_ConfigCommon = servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon; + ubwp->bwp_Common->pucch_ConfigCommon = servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon; + ubwp->bwp_Dedicated = calloc(1,sizeof(*ubwp->bwp_Dedicated)); + ubwp->bwp_Dedicated->pucch_Config = calloc(1,sizeof(*ubwp->bwp_Dedicated->pucch_Config)); + ubwp->bwp_Dedicated->pucch_Config->present = NR_SetupRelease_PUCCH_Config_PR_setup; + NR_PUCCH_Config_t *pucch_Config = calloc(1,sizeof(*pucch_Config)); + ubwp->bwp_Dedicated->pucch_Config->choice.setup=pucch_Config; + pucch_Config->resourceSetToAddModList = calloc(1,sizeof(*pucch_Config->resourceSetToAddModList)); + pucch_Config->resourceSetToReleaseList = NULL; + NR_PUCCH_ResourceSet_t *pucchresset0=calloc(1,sizeof(*pucchresset0)); + NR_PUCCH_ResourceSet_t *pucchresset1=calloc(1,sizeof(*pucchresset1)); + pucchresset0->pucch_ResourceSetId = 0; + NR_PUCCH_ResourceId_t *pucchresset0id0=calloc(1,sizeof(*pucchresset0id0)); + NR_PUCCH_ResourceId_t *pucchresset0id1=calloc(1,sizeof(*pucchresset0id1)); + *pucchresset0id0=1; + ASN_SEQUENCE_ADD(&pucchresset0->resourceList.list,pucchresset0id0); + *pucchresset0id1=2; + ASN_SEQUENCE_ADD(&pucchresset0->resourceList.list,pucchresset0id1); + pucchresset0->maxPayloadMinus1=NULL; + ASN_SEQUENCE_ADD(&pucch_Config->resourceSetToAddModList->list,pucchresset0); + pucchresset1->pucch_ResourceSetId = 1; + NR_PUCCH_ResourceId_t *pucchresset1id0=calloc(1,sizeof(*pucchresset1id0)); + NR_PUCCH_ResourceId_t *pucchresset1id1=calloc(1,sizeof(*pucchresset1id1)); + *pucchresset1id0=3; + ASN_SEQUENCE_ADD(&pucchresset1->resourceList.list,pucchresset1id0); + *pucchresset1id1=4; + ASN_SEQUENCE_ADD(&pucchresset1->resourceList.list,pucchresset1id1); + pucchresset1->maxPayloadMinus1=NULL; + ASN_SEQUENCE_ADD(&pucch_Config->resourceSetToAddModList->list,pucchresset1); + pucch_Config->resourceToAddModList = calloc(1,sizeof(*pucch_Config->resourceToAddModList)); + pucch_Config->resourceToReleaseList = NULL; + NR_PUCCH_Resource_t *pucchres0=calloc(1,sizeof(*pucchres0)); + NR_PUCCH_Resource_t *pucchres1=calloc(1,sizeof(*pucchres1)); + NR_PUCCH_Resource_t *pucchres2=calloc(1,sizeof(*pucchres2)); + NR_PUCCH_Resource_t *pucchres3=calloc(1,sizeof(*pucchres3)); + pucchres0->pucch_ResourceId=1; + pucchres0->startingPRB=48; + pucchres0->intraSlotFrequencyHopping=NULL; + pucchres0->secondHopPRB=NULL; + pucchres0->format.present= NR_PUCCH_Resource__format_PR_format0; + pucchres0->format.choice.format0=calloc(1,sizeof(*pucchres0->format.choice.format0)); + pucchres0->format.choice.format0->initialCyclicShift=0; + pucchres0->format.choice.format0->nrofSymbols=1; + pucchres0->format.choice.format0->startingSymbolIndex=13; + ASN_SEQUENCE_ADD(&pucch_Config->resourceToAddModList->list,pucchres0); + pucchres1->pucch_ResourceId=2; + pucchres1->startingPRB=48; + pucchres1->intraSlotFrequencyHopping=NULL; + pucchres1->secondHopPRB=NULL; + pucchres1->format.present= NR_PUCCH_Resource__format_PR_format0; + pucchres1->format.choice.format0=calloc(1,sizeof(*pucchres1->format.choice.format0)); + pucchres1->format.choice.format0->initialCyclicShift=0; + pucchres1->format.choice.format0->nrofSymbols=1; + pucchres1->format.choice.format0->startingSymbolIndex=12; + ASN_SEQUENCE_ADD(&pucch_Config->resourceToAddModList->list,pucchres1); + pucchres2->pucch_ResourceId=3; + pucchres2->startingPRB=40; + pucchres2->intraSlotFrequencyHopping=NULL; + pucchres2->secondHopPRB=NULL; + pucchres2->format.present= NR_PUCCH_Resource__format_PR_format2; + pucchres2->format.choice.format2=calloc(1,sizeof(*pucchres2->format.choice.format2)); + pucchres2->format.choice.format2->nrofPRBs=16; + pucchres2->format.choice.format2->nrofSymbols=1; + pucchres2->format.choice.format2->startingSymbolIndex=13; + ASN_SEQUENCE_ADD(&pucch_Config->resourceToAddModList->list,pucchres2); + pucchres3->pucch_ResourceId=4; + pucchres3->startingPRB=40; + pucchres3->intraSlotFrequencyHopping=NULL; + pucchres3->secondHopPRB=NULL; + pucchres3->format.present= NR_PUCCH_Resource__format_PR_format2; + pucchres3->format.choice.format2=calloc(1,sizeof(*pucchres3->format.choice.format2)); + pucchres3->format.choice.format2->nrofPRBs=16; + pucchres3->format.choice.format2->nrofSymbols=1; + pucchres3->format.choice.format2->startingSymbolIndex=12; + ASN_SEQUENCE_ADD(&pucch_Config->resourceToAddModList->list,pucchres3); + pucch_Config->format2=calloc(1,sizeof(*pucch_Config->format2)); + pucch_Config->format2->present=NR_SetupRelease_PUCCH_FormatConfig_PR_setup; + NR_PUCCH_FormatConfig_t *pucchfmt2 = calloc(1,sizeof(*pucchfmt2)); + pucch_Config->format2->choice.setup = pucchfmt2; + pucchfmt2->interslotFrequencyHopping=NULL; + pucchfmt2->additionalDMRS=NULL; + pucchfmt2->maxCodeRate=calloc(1,sizeof(*pucchfmt2->maxCodeRate)); + *pucchfmt2->maxCodeRate=NR_PUCCH_MaxCodeRate_zeroDot15; + pucchfmt2->nrofSlots=NULL; + pucchfmt2->pi2BPSK=NULL; + pucchfmt2->simultaneousHARQ_ACK_CSI=NULL; + pucch_Config->schedulingRequestResourceToAddModList=NULL; + pucch_Config->schedulingRequestResourceToReleaseList=NULL; + pucch_Config->multi_CSI_PUCCH_ResourceList=NULL; + pucch_Config->dl_DataToUL_ACK = calloc(1,sizeof(*pucch_Config->dl_DataToUL_ACK)); + long *delay[8]; + + for (int i=0; i<8; i++) { + delay[i] = calloc(1,sizeof(*delay[i])); + *delay[i] = (i<6) ? (i+2) : 0; + ASN_SEQUENCE_ADD(&pucch_Config->dl_DataToUL_ACK->list,delay[i]); + } + + pucch_Config->spatialRelationInfoToAddModList = calloc(1,sizeof(*pucch_Config->spatialRelationInfoToAddModList)); + NR_PUCCH_SpatialRelationInfo_t *pucchspatial = calloc(1,sizeof(*pucchspatial)); + pucchspatial->pucch_SpatialRelationInfoId = 1; + pucchspatial->servingCellId = NULL; + pucchspatial->referenceSignal.present = NR_PUCCH_SpatialRelationInfo__referenceSignal_PR_csi_RS_Index; + pucchspatial->referenceSignal.choice.csi_RS_Index = 0; + pucchspatial->pucch_PathlossReferenceRS_Id = 0; + pucchspatial->p0_PUCCH_Id = 1; + pucchspatial->closedLoopIndex = NR_PUCCH_SpatialRelationInfo__closedLoopIndex_i0; + ASN_SEQUENCE_ADD(&pucch_Config->spatialRelationInfoToAddModList->list,pucchspatial); + pucch_Config->spatialRelationInfoToReleaseList=NULL; + pucch_Config->pucch_PowerControl=calloc(1,sizeof(*pucch_Config->pucch_PowerControl)); + pucch_Config->pucch_PowerControl->deltaF_PUCCH_f0 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f0)); + *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f0 = 0; + pucch_Config->pucch_PowerControl->deltaF_PUCCH_f1 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f1)); + *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f1 = 0; + pucch_Config->pucch_PowerControl->deltaF_PUCCH_f2 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f2)); + *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f2 = 0; + pucch_Config->pucch_PowerControl->deltaF_PUCCH_f3 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f3)); + *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f3 = 0; + pucch_Config->pucch_PowerControl->deltaF_PUCCH_f4 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f4)); + *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f4 = 0; + pucch_Config->pucch_PowerControl->p0_Set = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->p0_Set)); + NR_P0_PUCCH_t *p00 = calloc(1,sizeof(*p00)); + p00->p0_PUCCH_Id=1; + p00->p0_PUCCH_Value = 0; + ASN_SEQUENCE_ADD(&pucch_Config->pucch_PowerControl->p0_Set->list,p00); + pucch_Config->pucch_PowerControl->pathlossReferenceRSs = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->pathlossReferenceRSs)); + NR_PUCCH_PathlossReferenceRS_t *pucchPLRef=calloc(1,sizeof(*pucchPLRef)); + pucchPLRef->pucch_PathlossReferenceRS_Id=0; + pucchPLRef->referenceSignal.present = NR_PUCCH_PathlossReferenceRS__referenceSignal_PR_csi_RS_Index; + pucchPLRef->referenceSignal.choice.csi_RS_Index=0; + ASN_SEQUENCE_ADD(&pucch_Config->pucch_PowerControl->pathlossReferenceRSs->list,pucchPLRef); + // copy pusch_Config from dedicated initialBWP + ubwp->bwp_Dedicated->pusch_Config = calloc(1,sizeof(*ubwp->bwp_Dedicated->pusch_Config)); + ubwp->bwp_Dedicated->pusch_Config->present = NR_SetupRelease_PUSCH_Config_PR_setup; + ubwp->bwp_Dedicated->pusch_Config->choice.setup = pusch_Config; + ubwp->bwp_Dedicated->configuredGrantConfig = NULL; + ubwp->bwp_Dedicated->srs_Config = calloc(1,sizeof(*ubwp->bwp_Dedicated->srs_Config)); + ubwp->bwp_Dedicated->srs_Config->present = NR_SetupRelease_SRS_Config_PR_setup; + ubwp->bwp_Dedicated->srs_Config->choice.setup = srs_Config; + ubwp->bwp_Dedicated->beamFailureRecoveryConfig = NULL; + ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list,ubwp); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id = calloc(1, + sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id)); + *secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id = 1; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig = NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->carrierSwitching = NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->supplementaryUplink=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdcch_ServingCellConfig=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig)); + NR_PDSCH_ServingCellConfig_t *pdsch_servingcellconfig = calloc(1,sizeof(*pdsch_servingcellconfig)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->present = NR_SetupRelease_PDSCH_ServingCellConfig_PR_setup; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup = pdsch_servingcellconfig; + pdsch_servingcellconfig->codeBlockGroupTransmission = NULL; + pdsch_servingcellconfig->xOverhead = NULL; + pdsch_servingcellconfig->nrofHARQ_ProcessesForPDSCH = NULL; + pdsch_servingcellconfig->pucch_Cell= NULL; + pdsch_servingcellconfig->ext1=calloc(1,sizeof(*pdsch_servingcellconfig->ext1)); + pdsch_servingcellconfig->ext1->maxMIMO_Layers = calloc(1,sizeof(*pdsch_servingcellconfig->ext1->maxMIMO_Layers)); + *pdsch_servingcellconfig->ext1->maxMIMO_Layers = 2; + pdsch_servingcellconfig->ext1->processingType2Enabled = NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->present = NR_SetupRelease_CSI_MeasConfig_PR_setup; + NR_CSI_MeasConfig_t *csi_MeasConfig = calloc(1,sizeof(*csi_MeasConfig)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup = csi_MeasConfig; + csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList = calloc(1,sizeof(*csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList)); + NR_NZP_CSI_RS_Resource_t *nzpres0 = calloc(1,sizeof(*nzpres0)); + nzpres0->nzp_CSI_RS_ResourceId=0; + nzpres0->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_other; + nzpres0->resourceMapping.frequencyDomainAllocation.choice.other.buf = calloc(1,1); + nzpres0->resourceMapping.frequencyDomainAllocation.choice.other.size = 1; + nzpres0->resourceMapping.frequencyDomainAllocation.choice.other.bits_unused = 2; + nzpres0->resourceMapping.frequencyDomainAllocation.choice.other.buf[0]=1<<2; + nzpres0->resourceMapping.nrofPorts = (n_physical_antenna_ports==1)? NR_CSI_RS_ResourceMapping__nrofPorts_p1 : NR_CSI_RS_ResourceMapping__nrofPorts_p2; + nzpres0->resourceMapping.firstOFDMSymbolInTimeDomain=7; + nzpres0->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres0->resourceMapping.cdm_Type = (n_physical_antenna_ports==1)? NR_CSI_RS_ResourceMapping__cdm_Type_noCDM : NR_CSI_RS_ResourceMapping__cdm_Type_fd_CDM2; + nzpres0->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_one; + nzpres0->resourceMapping.density.choice.one=(NULL_t)0; + nzpres0->resourceMapping.freqBand.startingRB=0; + nzpres0->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres0->powerControlOffset=13; + nzpres0->powerControlOffsetSS=NULL; + nzpres0->scramblingID=40; + nzpres0->periodicityAndOffset = calloc(1,sizeof(*nzpres0->periodicityAndOffset)); + nzpres0->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots320; + nzpres0->periodicityAndOffset->choice.slots320 = 2; + nzpres0->qcl_InfoPeriodicCSI_RS=NULL; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres0); + + if (n_physical_antenna_ports > 1) { + NR_NZP_CSI_RS_Resource_t *nzpres2 = calloc(1,sizeof(*nzpres2)); + nzpres2->nzp_CSI_RS_ResourceId=2; + nzpres2->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres2->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres2->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres2->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres2->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=1; + nzpres2->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres2->resourceMapping.firstOFDMSymbolInTimeDomain=4; + nzpres2->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres2->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres2->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres2->resourceMapping.density.choice.three=(NULL_t)0; + nzpres2->resourceMapping.freqBand.startingRB=0; + nzpres2->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres2->powerControlOffset=0; + nzpres2->powerControlOffsetSS=calloc(1,sizeof(*nzpres2->powerControlOffsetSS)); + *nzpres2->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres2->scramblingID=40; + nzpres2->periodicityAndOffset = calloc(1,sizeof(*nzpres2->periodicityAndOffset)); + nzpres2->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres2->periodicityAndOffset->choice.slots160 = 25; + nzpres2->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres2->qcl_InfoPeriodicCSI_RS)); + *nzpres2->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres2); + NR_NZP_CSI_RS_Resource_t *nzpres3 = calloc(1,sizeof(*nzpres3)); + nzpres3->nzp_CSI_RS_ResourceId=3; + nzpres3->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres3->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres3->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres3->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres3->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=1; + nzpres3->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres3->resourceMapping.firstOFDMSymbolInTimeDomain=8; + nzpres3->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres3->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres3->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres3->resourceMapping.density.choice.three=(NULL_t)0; + nzpres3->resourceMapping.freqBand.startingRB=0; + nzpres3->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres3->powerControlOffset=0; + nzpres3->powerControlOffsetSS=calloc(1,sizeof(*nzpres3->powerControlOffsetSS)); + *nzpres3->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres3->scramblingID=40; + nzpres3->periodicityAndOffset = calloc(1,sizeof(*nzpres3->periodicityAndOffset)); + nzpres3->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres3->periodicityAndOffset->choice.slots160 = 25; + nzpres3->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres3->qcl_InfoPeriodicCSI_RS)); + *nzpres3->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres3); + } + + if (n_physical_antenna_ports > 3) { + NR_NZP_CSI_RS_Resource_t *nzpres4 = calloc(1,sizeof(*nzpres4)); + nzpres4->nzp_CSI_RS_ResourceId=4; + nzpres4->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres4->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres4->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres4->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres4->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=1; + nzpres4->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres4->resourceMapping.firstOFDMSymbolInTimeDomain=4; + nzpres4->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres4->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres4->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres4->resourceMapping.density.choice.three=(NULL_t)0; + nzpres4->resourceMapping.freqBand.startingRB=0; + nzpres4->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres4->powerControlOffset=0; + nzpres4->powerControlOffsetSS=calloc(1,sizeof(*nzpres4->powerControlOffsetSS)); + *nzpres4->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres4->scramblingID=40; + nzpres4->periodicityAndOffset = calloc(1,sizeof(*nzpres4->periodicityAndOffset)); + nzpres4->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres4->periodicityAndOffset->choice.slots160 = 26; + nzpres4->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres4->qcl_InfoPeriodicCSI_RS)); + *nzpres4->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres4); + NR_NZP_CSI_RS_Resource_t *nzpres5 = calloc(1,sizeof(*nzpres5)); + nzpres5->nzp_CSI_RS_ResourceId=5; + nzpres5->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres5->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres5->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres5->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres5->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=1; + nzpres5->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres5->resourceMapping.firstOFDMSymbolInTimeDomain=8; + nzpres5->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres5->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres5->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres5->resourceMapping.density.choice.three=(NULL_t)0; + nzpres5->resourceMapping.freqBand.startingRB=0; + nzpres5->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres5->powerControlOffset=0; + nzpres5->powerControlOffsetSS=calloc(1,sizeof(*nzpres5->powerControlOffsetSS)); + *nzpres5->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres5->scramblingID=40; + nzpres5->periodicityAndOffset = calloc(1,sizeof(*nzpres5->periodicityAndOffset)); + nzpres5->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres5->periodicityAndOffset->choice.slots160 = 26; + nzpres5->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres5->qcl_InfoPeriodicCSI_RS)); + *nzpres5->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres5); + } + + if (n_physical_antenna_ports > 7) { + NR_NZP_CSI_RS_Resource_t *nzpres6 = calloc(1,sizeof(*nzpres6)); + nzpres6->nzp_CSI_RS_ResourceId=6; + nzpres6->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres6->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres6->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres6->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres6->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=4; + nzpres6->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres6->resourceMapping.firstOFDMSymbolInTimeDomain=4; + nzpres6->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres6->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres6->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres6->resourceMapping.density.choice.three=(NULL_t)0; + nzpres6->resourceMapping.freqBand.startingRB=0; + nzpres6->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres6->powerControlOffset=0; + nzpres6->powerControlOffsetSS=calloc(1,sizeof(*nzpres6->powerControlOffsetSS)); + *nzpres6->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres6->scramblingID=40; + nzpres6->periodicityAndOffset = calloc(1,sizeof(*nzpres6->periodicityAndOffset)); + nzpres6->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres6->periodicityAndOffset->choice.slots160 = 25; + nzpres6->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres6->qcl_InfoPeriodicCSI_RS)); + *nzpres6->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres6); + NR_NZP_CSI_RS_Resource_t *nzpres7 = calloc(1,sizeof(*nzpres7)); + nzpres7->nzp_CSI_RS_ResourceId=7; + nzpres7->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres7->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres7->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres7->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres7->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=4; + nzpres7->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres7->resourceMapping.firstOFDMSymbolInTimeDomain=8; + nzpres7->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres7->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres7->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres7->resourceMapping.density.choice.three=(NULL_t)0; + nzpres7->resourceMapping.freqBand.startingRB=0; + nzpres7->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres7->powerControlOffset=0; + nzpres7->powerControlOffsetSS=calloc(1,sizeof(*nzpres7->powerControlOffsetSS)); + *nzpres7->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres7->scramblingID=40; + nzpres7->periodicityAndOffset = calloc(1,sizeof(*nzpres7->periodicityAndOffset)); + nzpres7->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres7->periodicityAndOffset->choice.slots160 = 25; + nzpres7->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres7->qcl_InfoPeriodicCSI_RS)); + *nzpres7->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres7); + NR_NZP_CSI_RS_Resource_t *nzpres8 = calloc(1,sizeof(*nzpres8)); + nzpres8->nzp_CSI_RS_ResourceId=8; + nzpres8->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres8->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres8->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres8->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres8->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=4; + nzpres8->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres8->resourceMapping.firstOFDMSymbolInTimeDomain=4; + nzpres8->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres8->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres8->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres8->resourceMapping.density.choice.three=(NULL_t)0; + nzpres8->resourceMapping.freqBand.startingRB=0; + nzpres8->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres8->powerControlOffset=0; + nzpres8->powerControlOffsetSS=calloc(1,sizeof(*nzpres8->powerControlOffsetSS)); + *nzpres8->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres8->scramblingID=40; + nzpres8->periodicityAndOffset = calloc(1,sizeof(*nzpres8->periodicityAndOffset)); + nzpres8->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres8->periodicityAndOffset->choice.slots160 = 26; + nzpres8->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres8->qcl_InfoPeriodicCSI_RS)); + *nzpres8->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres8); + NR_NZP_CSI_RS_Resource_t *nzpres9 = calloc(1,sizeof(*nzpres9)); + nzpres9->nzp_CSI_RS_ResourceId=9; + nzpres9->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres9->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres9->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres9->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres9->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=4; + nzpres9->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres9->resourceMapping.firstOFDMSymbolInTimeDomain=8; + nzpres9->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres9->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres9->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres9->resourceMapping.density.choice.three=(NULL_t)0; + nzpres9->resourceMapping.freqBand.startingRB=0; + nzpres9->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres9->powerControlOffset=0; + nzpres9->powerControlOffsetSS=calloc(1,sizeof(*nzpres9->powerControlOffsetSS)); + *nzpres9->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres9->scramblingID=40; + nzpres9->periodicityAndOffset = calloc(1,sizeof(*nzpres9->periodicityAndOffset)); + nzpres9->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres9->periodicityAndOffset->choice.slots160 = 26; + nzpres9->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres9->qcl_InfoPeriodicCSI_RS)); + *nzpres9->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres9); + } + + if (n_physical_antenna_ports > 15) { + NR_NZP_CSI_RS_Resource_t *nzpres10 = calloc(1,sizeof(*nzpres10)); + nzpres10->nzp_CSI_RS_ResourceId=10; + nzpres10->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres10->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres10->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres10->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres10->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=2; + nzpres10->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres10->resourceMapping.firstOFDMSymbolInTimeDomain=4; + nzpres10->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres10->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres10->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres10->resourceMapping.density.choice.three=(NULL_t)0; + nzpres10->resourceMapping.freqBand.startingRB=0; + nzpres10->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres10->powerControlOffset=0; + nzpres10->powerControlOffsetSS=calloc(1,sizeof(*nzpres10->powerControlOffsetSS)); + *nzpres10->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres10->scramblingID=40; + nzpres10->periodicityAndOffset = calloc(1,sizeof(*nzpres10->periodicityAndOffset)); + nzpres10->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres10->periodicityAndOffset->choice.slots160 = 25; + nzpres10->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres10->qcl_InfoPeriodicCSI_RS)); + *nzpres10->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres10); + NR_NZP_CSI_RS_Resource_t *nzpres11 = calloc(1,sizeof(*nzpres11)); + nzpres11->nzp_CSI_RS_ResourceId=11; + nzpres11->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres11->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres11->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres11->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres11->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=2; + nzpres11->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres11->resourceMapping.firstOFDMSymbolInTimeDomain=8; + nzpres11->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres11->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres11->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres11->resourceMapping.density.choice.three=(NULL_t)0; + nzpres11->resourceMapping.freqBand.startingRB=0; + nzpres11->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres11->powerControlOffset=0; + nzpres11->powerControlOffsetSS=calloc(1,sizeof(*nzpres11->powerControlOffsetSS)); + *nzpres11->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres11->scramblingID=40; + nzpres11->periodicityAndOffset = calloc(1,sizeof(*nzpres11->periodicityAndOffset)); + nzpres11->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres11->periodicityAndOffset->choice.slots160 = 25; + nzpres11->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres11->qcl_InfoPeriodicCSI_RS)); + *nzpres11->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres11); + NR_NZP_CSI_RS_Resource_t *nzpres12 = calloc(1,sizeof(*nzpres12)); + nzpres12->nzp_CSI_RS_ResourceId=12; + nzpres12->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres12->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres12->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres12->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres12->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=2; + nzpres12->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres12->resourceMapping.firstOFDMSymbolInTimeDomain=4; + nzpres12->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres12->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres12->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres12->resourceMapping.density.choice.three=(NULL_t)0; + nzpres12->resourceMapping.freqBand.startingRB=0; + nzpres12->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres12->powerControlOffset=0; + nzpres12->powerControlOffsetSS=calloc(1,sizeof(*nzpres12->powerControlOffsetSS)); + *nzpres12->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres12->scramblingID=40; + nzpres12->periodicityAndOffset = calloc(1,sizeof(*nzpres12->periodicityAndOffset)); + nzpres12->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres12->periodicityAndOffset->choice.slots160 = 26; + nzpres12->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres12->qcl_InfoPeriodicCSI_RS)); + *nzpres12->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres12); + NR_NZP_CSI_RS_Resource_t *nzpres13 = calloc(1,sizeof(*nzpres13)); + nzpres13->nzp_CSI_RS_ResourceId=13; + nzpres13->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres13->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres13->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres13->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres13->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=2; + nzpres13->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres13->resourceMapping.firstOFDMSymbolInTimeDomain=8; + nzpres13->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres13->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres13->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres13->resourceMapping.density.choice.three=(NULL_t)0; + nzpres13->resourceMapping.freqBand.startingRB=0; + nzpres13->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres13->powerControlOffset=0; + nzpres13->powerControlOffsetSS=calloc(1,sizeof(*nzpres13->powerControlOffsetSS)); + *nzpres13->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres13->scramblingID=40; + nzpres13->periodicityAndOffset = calloc(1,sizeof(*nzpres13->periodicityAndOffset)); + nzpres13->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres13->periodicityAndOffset->choice.slots160 = 26; + nzpres13->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres13->qcl_InfoPeriodicCSI_RS)); + *nzpres13->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres13); + NR_NZP_CSI_RS_Resource_t *nzpres14 = calloc(1,sizeof(*nzpres14)); + nzpres14->nzp_CSI_RS_ResourceId=14; + nzpres14->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres14->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres14->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres14->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres14->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=8; + nzpres14->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres14->resourceMapping.firstOFDMSymbolInTimeDomain=4; + nzpres14->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres14->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres14->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres14->resourceMapping.density.choice.three=(NULL_t)0; + nzpres14->resourceMapping.freqBand.startingRB=0; + nzpres14->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres14->powerControlOffset=0; + nzpres14->powerControlOffsetSS=calloc(1,sizeof(*nzpres14->powerControlOffsetSS)); + *nzpres14->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres14->scramblingID=40; + nzpres14->periodicityAndOffset = calloc(1,sizeof(*nzpres14->periodicityAndOffset)); + nzpres14->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres14->periodicityAndOffset->choice.slots160 = 25; + nzpres14->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres14->qcl_InfoPeriodicCSI_RS)); + *nzpres14->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres14); + NR_NZP_CSI_RS_Resource_t *nzpres15 = calloc(1,sizeof(*nzpres15)); + nzpres15->nzp_CSI_RS_ResourceId=15; + nzpres15->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres15->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres15->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres15->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres15->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=8; + nzpres15->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres15->resourceMapping.firstOFDMSymbolInTimeDomain=8; + nzpres15->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres15->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres15->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres15->resourceMapping.density.choice.three=(NULL_t)0; + nzpres15->resourceMapping.freqBand.startingRB=0; + nzpres15->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres15->powerControlOffset=0; + nzpres15->powerControlOffsetSS=calloc(1,sizeof(*nzpres15->powerControlOffsetSS)); + *nzpres15->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres15->scramblingID=40; + nzpres15->periodicityAndOffset = calloc(1,sizeof(*nzpres15->periodicityAndOffset)); + nzpres15->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres15->periodicityAndOffset->choice.slots160 = 25; + nzpres15->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres15->qcl_InfoPeriodicCSI_RS)); + *nzpres15->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres15); + NR_NZP_CSI_RS_Resource_t *nzpres16 = calloc(1,sizeof(*nzpres16)); + nzpres16->nzp_CSI_RS_ResourceId=16; + nzpres16->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres16->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres16->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres16->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres16->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=8; + nzpres16->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres16->resourceMapping.firstOFDMSymbolInTimeDomain=5; + nzpres16->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres16->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres16->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres16->resourceMapping.density.choice.three=(NULL_t)0; + nzpres16->resourceMapping.freqBand.startingRB=0; + nzpres16->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres16->powerControlOffset=0; + nzpres16->powerControlOffsetSS=calloc(1,sizeof(*nzpres16->powerControlOffsetSS)); + *nzpres16->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres16->scramblingID=40; + nzpres16->periodicityAndOffset = calloc(1,sizeof(*nzpres16->periodicityAndOffset)); + nzpres16->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres16->periodicityAndOffset->choice.slots160 = 26; + nzpres16->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres16->qcl_InfoPeriodicCSI_RS)); + *nzpres16->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres16); + NR_NZP_CSI_RS_Resource_t *nzpres17 = calloc(1,sizeof(*nzpres17)); + nzpres17->nzp_CSI_RS_ResourceId=9; + nzpres17->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; + nzpres17->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); + nzpres17->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; + nzpres17->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; + nzpres17->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=8; + nzpres17->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; + nzpres17->resourceMapping.firstOFDMSymbolInTimeDomain=9; + nzpres17->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; + nzpres17->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; + nzpres17->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; + nzpres17->resourceMapping.density.choice.three=(NULL_t)0; + nzpres17->resourceMapping.freqBand.startingRB=0; + nzpres17->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; + nzpres17->powerControlOffset=0; + nzpres17->powerControlOffsetSS=calloc(1,sizeof(*nzpres17->powerControlOffsetSS)); + *nzpres17->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; + nzpres17->scramblingID=40; + nzpres17->periodicityAndOffset = calloc(1,sizeof(*nzpres17->periodicityAndOffset)); + nzpres17->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; + nzpres17->periodicityAndOffset->choice.slots160 = 26; + nzpres17->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres17->qcl_InfoPeriodicCSI_RS)); + *nzpres17->qcl_InfoPeriodicCSI_RS=8; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres17); + } + + if (n_physical_antenna_ports > 16) AssertFatal(1==0,"Fill in for more than 16 antenna elements\n"); + + csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList = calloc(1,sizeof(*csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList)); + csi_MeasConfig->nzp_CSI_RS_ResourceSetToReleaseList = NULL; + NR_NZP_CSI_RS_ResourceSet_t *nzpresset0=calloc(1,sizeof(*nzpresset0)); + nzpresset0->nzp_CSI_ResourceSetId=0; + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset00=calloc(1,sizeof(*nzpresset00)); + *nzpresset00=0; + ASN_SEQUENCE_ADD(&nzpresset0->nzp_CSI_RS_Resources.list,nzpresset00); + nzpresset0->repetition=NULL; + nzpresset0->aperiodicTriggeringOffset=NULL; + nzpresset0->trs_Info=NULL; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset0); + + if (n_physical_antenna_ports > 1) { + NR_NZP_CSI_RS_ResourceSet_t *nzpresset3=calloc(1,sizeof(*nzpresset3)); + nzpresset3->nzp_CSI_ResourceSetId=3; + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset30=calloc(1,sizeof(*nzpresset30)); + *nzpresset30=2; + ASN_SEQUENCE_ADD(&nzpresset3->nzp_CSI_RS_Resources.list,nzpresset30); + + if (n_physical_antenna_ports > 3) { + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset31=calloc(1,sizeof(*nzpresset31)); + *nzpresset31=3; + ASN_SEQUENCE_ADD(&nzpresset3->nzp_CSI_RS_Resources.list,nzpresset31); + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset32=calloc(1,sizeof(*nzpresset32)); + *nzpresset32=4; + ASN_SEQUENCE_ADD(&nzpresset3->nzp_CSI_RS_Resources.list,nzpresset32); + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset33=calloc(1,sizeof(*nzpresset33)); + *nzpresset33=5; + ASN_SEQUENCE_ADD(&nzpresset3->nzp_CSI_RS_Resources.list,nzpresset33); + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset3); + } + + nzpresset3->repetition=calloc(1,sizeof(*nzpresset3->repetition)); + *nzpresset3->repetition=NR_NZP_CSI_RS_ResourceSet__repetition_off; + nzpresset3->aperiodicTriggeringOffset=NULL; + nzpresset3->trs_Info=calloc(1,sizeof(*nzpresset3->trs_Info)); + *nzpresset3->trs_Info=NR_NZP_CSI_RS_ResourceSet__trs_Info_true; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset3); + } + + if (n_physical_antenna_ports > 7) { + NR_NZP_CSI_RS_ResourceSet_t *nzpresset4=calloc(1,sizeof(*nzpresset4)); + nzpresset4->nzp_CSI_ResourceSetId=4; + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset40=calloc(1,sizeof(*nzpresset40)); + *nzpresset40=6; + ASN_SEQUENCE_ADD(&nzpresset4->nzp_CSI_RS_Resources.list,nzpresset40); + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset41=calloc(1,sizeof(*nzpresset41)); + *nzpresset41=7; + ASN_SEQUENCE_ADD(&nzpresset4->nzp_CSI_RS_Resources.list,nzpresset41); + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset42=calloc(1,sizeof(*nzpresset42)); + *nzpresset42=8; + ASN_SEQUENCE_ADD(&nzpresset4->nzp_CSI_RS_Resources.list,nzpresset42); + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset43=calloc(1,sizeof(*nzpresset43)); + *nzpresset43=9; + ASN_SEQUENCE_ADD(&nzpresset4->nzp_CSI_RS_Resources.list,nzpresset43); + nzpresset4->repetition=calloc(1,sizeof(*nzpresset4->repetition)); + *nzpresset4->repetition=NR_NZP_CSI_RS_ResourceSet__repetition_off; + nzpresset4->aperiodicTriggeringOffset=NULL; + nzpresset4->trs_Info=calloc(1,sizeof(*nzpresset4->trs_Info)); + *nzpresset4->trs_Info=NR_NZP_CSI_RS_ResourceSet__trs_Info_true; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset4); + } + + if (n_physical_antenna_ports > 15) { + NR_NZP_CSI_RS_ResourceSet_t *nzpresset5=calloc(1,sizeof(*nzpresset5)); + nzpresset5->nzp_CSI_ResourceSetId=5; + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset50=calloc(1,sizeof(*nzpresset50)); + *nzpresset50=10; + ASN_SEQUENCE_ADD(&nzpresset5->nzp_CSI_RS_Resources.list,nzpresset50); + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset51=calloc(1,sizeof(*nzpresset51)); + *nzpresset51=11; + ASN_SEQUENCE_ADD(&nzpresset5->nzp_CSI_RS_Resources.list,nzpresset51); + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset52=calloc(1,sizeof(*nzpresset52)); + *nzpresset52=12; + ASN_SEQUENCE_ADD(&nzpresset5->nzp_CSI_RS_Resources.list,nzpresset52); + NR_NZP_CSI_RS_ResourceSetId_t *nzpresset53=calloc(1,sizeof(*nzpresset53)); + *nzpresset53=13; + ASN_SEQUENCE_ADD(&nzpresset5->nzp_CSI_RS_Resources.list,nzpresset53); + nzpresset5->repetition=calloc(1,sizeof(*nzpresset5->repetition)); + *nzpresset5->repetition=NR_NZP_CSI_RS_ResourceSet__repetition_off; + nzpresset5->aperiodicTriggeringOffset=NULL; + nzpresset5->trs_Info=calloc(1,sizeof(*nzpresset5->trs_Info)); + *nzpresset5->trs_Info=NR_NZP_CSI_RS_ResourceSet__trs_Info_true; + ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset5); + } + + csi_MeasConfig->csi_IM_ResourceToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_IM_ResourceToAddModList)); + csi_MeasConfig->csi_IM_ResourceToReleaseList = NULL; + NR_CSI_IM_Resource_t *imres0 = calloc(1,sizeof(*imres0)); + imres0->csi_IM_ResourceId=0; + imres0->csi_IM_ResourceElementPattern=calloc(1,sizeof(*imres0->csi_IM_ResourceElementPattern)); + imres0->csi_IM_ResourceElementPattern->present = NR_CSI_IM_Resource__csi_IM_ResourceElementPattern_PR_pattern1 ; + imres0->csi_IM_ResourceElementPattern->choice.pattern1=calloc(1,sizeof(*imres0->csi_IM_ResourceElementPattern->choice.pattern1)); + imres0->csi_IM_ResourceElementPattern->choice.pattern1->subcarrierLocation_p1 = NR_CSI_IM_Resource__csi_IM_ResourceElementPattern__pattern1__subcarrierLocation_p1_s4; + imres0->csi_IM_ResourceElementPattern->choice.pattern1->symbolLocation_p1=7; + imres0->freqBand=calloc(1,sizeof(*imres0->freqBand)); + imres0->freqBand->startingRB=0; + imres0->freqBand->nrofRBs=276; + imres0->periodicityAndOffset=calloc(1,sizeof(*imres0->periodicityAndOffset)); + imres0->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots320; + imres0->periodicityAndOffset->choice.slots320 = 2; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_IM_ResourceToAddModList->list,imres0); + csi_MeasConfig->csi_IM_ResourceSetToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_IM_ResourceSetToAddModList)); + csi_MeasConfig->csi_IM_ResourceSetToReleaseList = NULL; + NR_CSI_IM_ResourceSet_t *imresset0 = calloc(1,sizeof(*imresset0)); + imresset0->csi_IM_ResourceSetId=0; + NR_CSI_IM_ResourceId_t *imresset00=calloc(1,sizeof(*imresset00)); + *imresset00=0; + ASN_SEQUENCE_ADD(&imresset0->csi_IM_Resources.list,imresset00); + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_IM_ResourceSetToAddModList->list,imresset0); + csi_MeasConfig->csi_SSB_ResourceSetToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_SSB_ResourceSetToAddModList)); + csi_MeasConfig->csi_SSB_ResourceSetToReleaseList = NULL; + NR_CSI_SSB_ResourceSet_t *ssbresset0 = calloc(1,sizeof(*ssbresset0)); + ssbresset0->csi_SSB_ResourceSetId=0; + NR_SSB_Index_t *ssbresset00=calloc(1,sizeof(*ssbresset00)); + *ssbresset00=0; + ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset00); + + if (n_physical_antenna_ports > 1) { + NR_SSB_Index_t *ssbresset01=calloc(1,sizeof(*ssbresset01)); + *ssbresset01=1; + ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset01); + } + + if (n_physical_antenna_ports > 3) { + NR_SSB_Index_t *ssbresset02=calloc(1,sizeof(*ssbresset02)); + *ssbresset02=2; + ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset02); + NR_SSB_Index_t *ssbresset03=calloc(1,sizeof(*ssbresset03)); + *ssbresset03=3; + ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset03); + } + + if (n_physical_antenna_ports > 7) { + NR_SSB_Index_t *ssbresset04=calloc(1,sizeof(*ssbresset04)); + *ssbresset04=4; + ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset04); + NR_SSB_Index_t *ssbresset05=calloc(1,sizeof(*ssbresset05)); + *ssbresset05=5; + ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset05); + NR_SSB_Index_t *ssbresset06=calloc(1,sizeof(*ssbresset06)); + *ssbresset06=6; + ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset06); + NR_SSB_Index_t *ssbresset07=calloc(1,sizeof(*ssbresset07)); + *ssbresset07=7; + ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset07); + } + + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_SSB_ResourceSetToAddModList->list,ssbresset0); + csi_MeasConfig->csi_ResourceConfigToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_ResourceConfigToAddModList)); + csi_MeasConfig->csi_ResourceConfigToReleaseList = NULL; + NR_CSI_ResourceConfig_t *csires0 = calloc(1,sizeof(*csires0)); + csires0->csi_ResourceConfigId=0; + csires0->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires00 = calloc(1,sizeof(*csires00)); + *csires00 = 0; + ASN_SEQUENCE_ADD(&csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires00); + csires0->bwp_Id = 1; + csires0->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires0); + NR_CSI_ResourceConfig_t *csires11 = calloc(1,sizeof(*csires11)); + csires11->csi_ResourceConfigId=11; + csires11->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_csi_IM_ResourceSetList; + csires11->csi_RS_ResourceSetList.choice.csi_IM_ResourceSetList = calloc(1,sizeof(*csires11->csi_RS_ResourceSetList.choice.csi_IM_ResourceSetList)); + NR_NZP_CSI_RS_ResourceSetId_t *csires110 = calloc(1,sizeof(*csires110)); + *csires110 = 0; + ASN_SEQUENCE_ADD(&csires11->csi_RS_ResourceSetList.choice.csi_IM_ResourceSetList->list,csires110); + csires11->bwp_Id = 1; + csires11->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires11); + NR_CSI_ResourceConfig_t *csires10 = calloc(1,sizeof(*csires10)); + csires10->csi_ResourceConfigId=10; + csires10->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires100 = calloc(1,sizeof(*csires100)); + *csires100 = 0; + ASN_SEQUENCE_ADD(&csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires100); + csires10->bwp_Id = 1; + csires10->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires10); + NR_CSI_ResourceConfig_t *csires2 = calloc(1,sizeof(*csires2)); + csires2->csi_ResourceConfigId=2; + csires2->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires20 = calloc(1,sizeof(*csires20)); + *csires20 = 0; + ASN_SEQUENCE_ADD(&csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires20); + csires2->bwp_Id = 1; + csires2->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires2); + NR_CSI_ResourceConfig_t *csires3 = calloc(1,sizeof(*csires3)); + csires3->csi_ResourceConfigId=3; + csires3->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires30 = calloc(1,sizeof(*csires30)); + *csires30 = 0; + ASN_SEQUENCE_ADD(&csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires30); + csires3->bwp_Id = 1; + csires3->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires3); + NR_CSI_ResourceConfig_t *csires4 = calloc(1,sizeof(*csires4)); + csires4->csi_ResourceConfigId=4; + csires4->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires40 = calloc(1,sizeof(*csires40)); + *csires40 = 0; + ASN_SEQUENCE_ADD(&csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires40); + csires4->bwp_Id = 1; + csires4->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires4); + NR_CSI_ResourceConfig_t *csires5 = calloc(1,sizeof(*csires5)); + csires5->csi_ResourceConfigId=5; + csires5->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires50 = calloc(1,sizeof(*csires50)); + *csires50 = 0; + ASN_SEQUENCE_ADD(&csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires50); + csires5->bwp_Id = 1; + csires5->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires5); + NR_CSI_ResourceConfig_t *csires6 = calloc(1,sizeof(*csires6)); + csires6->csi_ResourceConfigId=6; + csires6->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires60 = calloc(1,sizeof(*csires60)); + *csires60 = 0; + ASN_SEQUENCE_ADD(&csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires60); + csires6->bwp_Id = 1; + csires6->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires6); + NR_CSI_ResourceConfig_t *csires7 = calloc(1,sizeof(*csires7)); + csires7->csi_ResourceConfigId=7; + csires7->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires70 = calloc(1,sizeof(*csires70)); + *csires70 = 0; + ASN_SEQUENCE_ADD(&csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires70); + csires7->bwp_Id = 1; + csires7->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires7); + NR_CSI_ResourceConfig_t *csires8 = calloc(1,sizeof(*csires8)); + csires8->csi_ResourceConfigId=8; + csires8->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires80 = calloc(1,sizeof(*csires80)); + *csires80 = 0; + ASN_SEQUENCE_ADD(&csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires80); + csires8->bwp_Id = 1; + csires8->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires8); + NR_CSI_ResourceConfig_t *csires9 = calloc(1,sizeof(*csires9)); + csires9->csi_ResourceConfigId=9; + csires9->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; + csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); + csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); + csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; + NR_NZP_CSI_RS_ResourceSetId_t *csires90 = calloc(1,sizeof(*csires90)); + *csires90 = 0; + ASN_SEQUENCE_ADD(&csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires90); + csires9->bwp_Id = 1; + csires9->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires9); + csi_MeasConfig->csi_ReportConfigToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_ReportConfigToAddModList)); + csi_MeasConfig->csi_ReportConfigToReleaseList = NULL; + NR_CSI_ReportConfig_t *csirep0 = calloc(1,sizeof(*csirep0)); + csirep0->reportConfigId=0; + csirep0->carrier=NULL; + csirep0->resourcesForChannelMeasurement=0; + csirep0->csi_IM_ResourcesForInterference=calloc(1,sizeof(*csirep0->csi_IM_ResourcesForInterference)); + *csirep0->csi_IM_ResourcesForInterference=11; + csirep0->nzp_CSI_RS_ResourcesForInterference=NULL; + csirep0->reportConfigType.present = NR_CSI_ReportConfig__reportConfigType_PR_periodic; + csirep0->reportConfigType.choice.periodic = calloc(1,sizeof(*csirep0->reportConfigType.choice.periodic)); + csirep0->reportConfigType.choice.periodic->reportSlotConfig.present=NR_CSI_ReportPeriodicityAndOffset_PR_slots320; + csirep0->reportConfigType.choice.periodic->reportSlotConfig.choice.slots320 = 9; + NR_PUCCH_CSI_Resource_t *pucchcsires0 = calloc(1,sizeof(*pucchcsires0)); + pucchcsires0->uplinkBandwidthPartId=1; + pucchcsires0->pucch_Resource=11; + ASN_SEQUENCE_ADD(&csirep0->reportConfigType.choice.periodic->pucch_CSI_ResourceList.list,pucchcsires0); + csirep0->reportQuantity.present = NR_CSI_ReportConfig__reportQuantity_PR_cri_RI_LI_PMI_CQI; + csirep0->reportQuantity.choice.cri_RI_PMI_CQI = (NULL_t)0; + csirep0->reportFreqConfiguration = calloc(1,sizeof(*csirep0->reportFreqConfiguration)); + csirep0->reportFreqConfiguration->cqi_FormatIndicator=NR_CSI_ReportConfig__reportFreqConfiguration__cqi_FormatIndicator_widebandCQI; + csirep0->reportFreqConfiguration->pmi_FormatIndicator=NR_CSI_ReportConfig__reportFreqConfiguration__pmi_FormatIndicator_widebandPMI; + csirep0->reportFreqConfiguration->csi_ReportingBand=calloc(1,sizeof(*csirep0->reportFreqConfiguration->csi_ReportingBand)); + AssertFatal(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id>0,"firstActiveDownlinkBWP_Id %d\n", + (int)*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id); + int NPRB = NRRIV2BW(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id + -1]->bwp_Common->genericParameters.locationAndBandwidth,275); + int sbsize = get_subband_size(NPRB,0); + int numsb = NPRB/sbsize; + + if (NPRB%sbsize == 0) numsb++; + + csirep0->reportFreqConfiguration->csi_ReportingBand->present= NR_CSI_ReportConfig__reportFreqConfiguration__csi_ReportingBand_PR_NOTHING+(numsb-2); + csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.size=numsb/8; + + if ((numsb&7) > 0) csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.size++; + + csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.bits_unused = (8-(numsb&7))&7; + csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.buf=malloc(csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.size); + + for (int i=0; ireportFreqConfiguration->csi_ReportingBand->choice.subbands18.size; i++) + csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.buf[i]=0xff; + + csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.buf[csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.size-1]&=~(( + 1<reportFreqConfiguration->csi_ReportingBand->choice.subbands18.bits_unused)-1); + csirep0->timeRestrictionForChannelMeasurements= NR_CSI_ReportConfig__timeRestrictionForChannelMeasurements_configured; + csirep0->timeRestrictionForInterferenceMeasurements=NR_CSI_ReportConfig__timeRestrictionForInterferenceMeasurements_configured; + csirep0->codebookConfig=calloc(1,sizeof(*csirep0->codebookConfig)); + csirep0->codebookConfig->codebookType.present = NR_CodebookConfig__codebookType_PR_type1; + csirep0->codebookConfig->codebookType.choice.type1 = calloc(1,sizeof(*csirep0->codebookConfig->codebookType.choice.type1)); + csirep0->codebookConfig->codebookType.choice.type1->subType.present = NR_CodebookConfig__codebookType__type1__subType_PR_typeI_SinglePanel; + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel=calloc(1,sizeof(*csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel)); + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.present= + NR_CodebookConfig__codebookType__type1__subType__typeI_SinglePanel__nrOfAntennaPorts_PR_two; + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two= + calloc(1,sizeof(*csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two)); + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.size=1; + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.bits_unused=2; + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.buf=malloc(1); + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.buf[0]=0xfc; + //'111111'B + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.size=1; + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.bits_unused=0; + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.buf=malloc(1); + csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.buf[0]=0xc0; //'00000011'B + csirep0->codebookConfig->codebookType.choice.type1->codebookMode=1; + csirep0->dummy = NULL; + csirep0->groupBasedBeamReporting.present = NR_CSI_ReportConfig__groupBasedBeamReporting_PR_disabled; + csirep0->groupBasedBeamReporting.choice.disabled=calloc(1,sizeof(*csirep0->groupBasedBeamReporting.choice.disabled)); + csirep0->groupBasedBeamReporting.choice.disabled->nrofReportedRS = NULL; + csirep0->cqi_Table = calloc(1,sizeof(*csirep0->cqi_Table)); + *csirep0->cqi_Table = NR_CSI_ReportConfig__cqi_Table_table1; + csirep0->subbandSize = NR_CSI_ReportConfig__subbandSize_value1; + csirep0->non_PMI_PortIndication = NULL; + csirep0->ext1 = NULL; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ReportConfigToAddModList->list,csirep0); + NR_CSI_ReportConfig_t *csirep1 = calloc(1,sizeof(*csirep1)); + csirep1->reportConfigId=2; + csirep1->carrier=NULL; + csirep1->resourcesForChannelMeasurement=initial_csi_index; + csirep1->csi_IM_ResourcesForInterference=NULL; + csirep1->nzp_CSI_RS_ResourcesForInterference=NULL; + csirep1->reportConfigType.present = NR_CSI_ReportConfig__reportConfigType_PR_periodic; + csirep1->reportConfigType.choice.periodic = calloc(1,sizeof(*csirep1->reportConfigType.choice.periodic)); + csirep1->reportConfigType.choice.periodic->reportSlotConfig.present=NR_CSI_ReportPeriodicityAndOffset_PR_slots320; + csirep1->reportConfigType.choice.periodic->reportSlotConfig.choice.slots320 = 49; + NR_PUCCH_CSI_Resource_t *pucchcsires1 = calloc(1,sizeof(*pucchcsires1)); + pucchcsires1->uplinkBandwidthPartId=1; + pucchcsires1->pucch_Resource=12; + ASN_SEQUENCE_ADD(&csirep1->reportConfigType.choice.periodic->pucch_CSI_ResourceList.list,pucchcsires1); + csirep1->reportQuantity.present = NR_CSI_ReportConfig__reportQuantity_PR_ssb_Index_RSRP; + csirep1->reportQuantity.choice.ssb_Index_RSRP=(NULL_t)0; + csirep1->reportFreqConfiguration = calloc(1,sizeof(*csirep1->reportFreqConfiguration)); + csirep1->reportFreqConfiguration->cqi_FormatIndicator=NR_CSI_ReportConfig__reportFreqConfiguration__cqi_FormatIndicator_widebandCQI; + csirep1->reportFreqConfiguration->pmi_FormatIndicator=NR_CSI_ReportConfig__reportFreqConfiguration__pmi_FormatIndicator_widebandPMI; + csirep1->reportFreqConfiguration->csi_ReportingBand=NULL; + csirep1->timeRestrictionForChannelMeasurements= NR_CSI_ReportConfig__timeRestrictionForChannelMeasurements_configured; + csirep1->timeRestrictionForInterferenceMeasurements=NR_CSI_ReportConfig__timeRestrictionForInterferenceMeasurements_configured; + csirep1->codebookConfig=calloc(1,sizeof(*csirep1->codebookConfig)); + csirep1->codebookConfig->codebookType.present = NR_CodebookConfig__codebookType_PR_type1; + csirep1->codebookConfig->codebookType.choice.type1 = calloc(1,sizeof(*csirep1->codebookConfig->codebookType.choice.type1)); + csirep1->codebookConfig->codebookType.choice.type1->subType.present=NR_CodebookConfig__codebookType__type1__subType_PR_typeI_SinglePanel; + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel=calloc(1,sizeof(*csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel)); + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.present= + NR_CodebookConfig__codebookType__type1__subType__typeI_SinglePanel__nrOfAntennaPorts_PR_two; + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two= + calloc(1,sizeof(*csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two)); + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.size=1; + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.bits_unused=2; + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.buf=malloc(1); + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.buf[0]=0xfc; + //'111111'B + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.size=1; + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.bits_unused=0; + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.buf=malloc(1); + csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.buf[0]=0xc0; //'00000011'B + csirep1->codebookConfig->codebookType.choice.type1->codebookMode=1; + csirep1->dummy = NULL; + csirep1->groupBasedBeamReporting.present = NR_CSI_ReportConfig__groupBasedBeamReporting_PR_disabled; + csirep1->groupBasedBeamReporting.choice.disabled=calloc(1,sizeof(*csirep1->groupBasedBeamReporting.choice.disabled)); + csirep1->groupBasedBeamReporting.choice.disabled->nrofReportedRS = calloc(1,sizeof(*csirep1->groupBasedBeamReporting.choice.disabled->nrofReportedRS)); + *csirep1->groupBasedBeamReporting.choice.disabled->nrofReportedRS=NR_CSI_ReportConfig__groupBasedBeamReporting__disabled__nrofReportedRS_n2; + // this corresponds to: + //if the UE is configured with the higher layer parameter groupBasedBeamReporting set to 'disabled', the UE is not required to update measurements for more than 64 CSI-RS and/or SSB resources, and the UE shall report in a single report nrofReportedRS (higher layer configured) different CRI or SSBRI for each report setting. + csirep1->cqi_Table = calloc(1,sizeof(*csirep1->cqi_Table)); + *csirep1->cqi_Table = NR_CSI_ReportConfig__cqi_Table_table1; + csirep1->subbandSize = NR_CSI_ReportConfig__subbandSize_value1; + csirep1->non_PMI_PortIndication = NULL; + csirep1->ext1 = NULL; + ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ReportConfigToAddModList->list,csirep1); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->sCellDeactivationTimer=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->tag_Id=0; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->dummy=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->pathlossReferenceLinking=NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->servingCellMO=NULL; } void fill_default_reconfig(NR_ServingCellConfigCommon_t *servingcellconfigcommon, - NR_RRCReconfiguration_IEs_t *reconfig, - NR_CellGroupConfig_t *secondaryCellGroup, - int n_physical_antenna_ports, - int initial_csi_index) { - + NR_RRCReconfiguration_IEs_t *reconfig, + NR_CellGroupConfig_t *secondaryCellGroup, + int n_physical_antenna_ports, + int initial_csi_index) { AssertFatal(servingcellconfigcommon!=NULL,"servingcellconfigcommon is null\n"); AssertFatal(reconfig!=NULL,"reconfig is null\n"); AssertFatal(secondaryCellGroup!=NULL,"secondaryCellGroup is null\n"); - // radioBearerConfig reconfig->radioBearerConfig=NULL; // secondaryCellGroup fill_default_secondaryCellGroup(servingcellconfigcommon,secondaryCellGroup,0,0,n_physical_antenna_ports,initial_csi_index); - xer_fprint(stdout, &asn_DEF_NR_CellGroupConfig, (const void*)secondaryCellGroup); - + xer_fprint(stdout, &asn_DEF_NR_CellGroupConfig, (const void *)secondaryCellGroup); char scg_buffer[1024]; asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CellGroupConfig, NULL, (void *)secondaryCellGroup, scg_buffer, 1024); AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", enc_rval.failed_type->name, enc_rval.encoded); - - reconfig->secondaryCellGroup = calloc(1,sizeof(*reconfig->secondaryCellGroup)); OCTET_STRING_fromBuf(reconfig->secondaryCellGroup, - (const char*)scg_buffer, - (enc_rval.encoded+7)>>3); + (const char *)scg_buffer, + (enc_rval.encoded+7)>>3); // measConfig reconfig->measConfig=NULL; // lateNonCriticalExtension @@ -2031,67 +1918,4 @@ void fill_default_reconfig(NR_ServingCellConfigCommon_t *servingcellconfigcommon // nonCriticalExtension reconfig->nonCriticalExtension = NULL; } -#if 0 -void fill_default_rbconfig(NR_RadioBearerConfig_t *rbconfig, x2ap_ENDC_sgnb_addition_req_t *m, struct NR_CG_ConfigInfo_IEs *cg_config_info) { -/* - if(cg_config_info->mcg_RB_Config) { - asn_dec_rval dec_rval = uper_decode(NULL, - &asn_DEF_NR_RadioBearerConfig, - (void**)&rbconfig, - cg_config_info->mcg_RB_Config->buf, - cg_ConfigInfo->mcg_RB_Config->size, 0, 0); - - if((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) { - AssertFatal(1==0,"[InterNode] Failed to decode mcg_rb_config (%zu bits), size of OCTET_STRING %lu\n", - dec_rval.consumed, cg_ConfigInfo->ue_CapabilityInfo->size); - } - } - */ - - #if 0 - rbconfig->srb_ToAddModList = NULL; - rbconfig->srb3_ToRelease = NULL; - rbconfig->drb_ToAddModList = calloc(1,sizeof(*rbconfig->drb_ToAddModList)); - NR_DRB_ToAddMod_t *drb_ToAddMod = calloc(1,sizeof(*drb_ToAddMod)); - drb_ToAddMod->cnAssociation = calloc(1,sizeof(*drb_ToAddMod->cnAssociation)); - drb_ToAddMod->cnAssociation->present = NR_DRB_ToAddMod__cnAssociation_PR_eps_BearerIdentity; - drb_ToAddMod->cnAssociation->choice.eps_BearerIdentity=5; - drb_ToAddMod->drb_Identity = 1; - drb_ToAddMod->reestablishPDCP = NULL; - drb_ToAddMod->recoverPDCP = NULL; - drb_ToAddMod->pdcp_Config = calloc(1,sizeof(*drb_ToAddMod->pdcp_Config)); - drb_ToAddMod->pdcp_Config->drb = calloc(1,sizeof(*drb_ToAddMod->pdcp_Config->drb)); - drb_ToAddMod->pdcp_Config->drb->discardTimer = calloc(1,sizeof(*drb_ToAddMod->pdcp_Config->drb->discardTimer)); - *drb_ToAddMod->pdcp_Config->drb->discardTimer=NR_PDCP_Config__drb__discardTimer_ms30; - drb_ToAddMod->pdcp_Config->drb->pdcp_SN_SizeUL = calloc(1,sizeof(*drb_ToAddMod->pdcp_Config->drb->pdcp_SN_SizeUL)); - *drb_ToAddMod->pdcp_Config->drb->pdcp_SN_SizeUL = NR_PDCP_Config__drb__pdcp_SN_SizeUL_len18bits; - drb_ToAddMod->pdcp_Config->drb->pdcp_SN_SizeDL = calloc(1,sizeof(*drb_ToAddMod->pdcp_Config->drb->pdcp_SN_SizeDL)); - *drb_ToAddMod->pdcp_Config->drb->pdcp_SN_SizeDL = NR_PDCP_Config__drb__pdcp_SN_SizeDL_len18bits; - drb_ToAddMod->pdcp_Config->drb->headerCompression.present = NR_PDCP_Config__drb__headerCompression_PR_notUsed; - drb_ToAddMod->pdcp_Config->drb->headerCompression.choice.notUsed = 0; - - drb_ToAddMod->pdcp_Config->drb->integrityProtection=NULL; - drb_ToAddMod->pdcp_Config->drb->statusReportRequired=NULL; - drb_ToAddMod->pdcp_Config->drb->outOfOrderDelivery=NULL; - drb_ToAddMod->pdcp_Config->moreThanOneRLC = NULL; - - drb_ToAddMod->pdcp_Config->t_Reordering = calloc(1,sizeof(*drb_ToAddMod->pdcp_Config->t_Reordering)); - *drb_ToAddMod->pdcp_Config->t_Reordering = NR_PDCP_Config__t_Reordering_ms0; - drb_ToAddMod->pdcp_Config->ext1 = NULL; - - ASN_SEQUENCE_ADD(&rbconfig->drb_ToAddModList->list,drb_ToAddMod); - - rbconfig->drb_ToReleaseList = NULL; - - rbconfig->securityConfig = calloc(1,sizeof(*rbconfig->securityConfig)); - rbconfig->securityConfig->securityAlgorithmConfig = calloc(1,sizeof(*rbconfig->securityConfig->securityAlgorithmConfig)); - rbconfig->securityConfig->securityAlgorithmConfig->cipheringAlgorithm = NR_CipheringAlgorithm_nea0; - rbconfig->securityConfig->securityAlgorithmConfig->integrityProtAlgorithm=NULL; - rbconfig->securityConfig->keyToUse = calloc(1,sizeof(*rbconfig->securityConfig->keyToUse)); - *rbconfig->securityConfig->keyToUse = NR_SecurityConfig__keyToUse_master; -#endif - - xer_fprint(stdout, &asn_DEF_NR_RadioBearerConfig, (const void*)rbconfig); -} -#endif #endif From 9cbe078ed0bfa93f31073b3aa65152c445cb56a3 Mon Sep 17 00:00:00 2001 From: "s.rampalli" Date: Wed, 20 May 2020 15:47:03 +0530 Subject: [PATCH 294/553] indentations fixed --- openair2/RRC/LTE/rrc_eNB.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index 75ed1873f5..cfafd28983 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -2124,7 +2124,6 @@ rrc_eNB_generate_RRCConnectionReestablishmentReject( PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP), ue_p->Srb0.Tx_buffer.payload_size); } -#ifdef GES_ENDC_SUPPORT #if 0 void rrc_generate_SgNBReleaseRequest( const protocol_ctxt_t *const ctxt_pP, @@ -2146,7 +2145,6 @@ void rrc_generate_SgNBReleaseRequest( return; } #endif -#endif //----------------------------------------------------------------------------- /* * Generate the RRC Connection Release to UE. @@ -2166,7 +2164,6 @@ rrc_eNB_generate_RRCConnectionRelease( memset(buffer, 0, RRC_BUF_SIZE); T(T_ENB_RRC_CONNECTION_RELEASE, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame), T_INT(ctxt_pP->subframe), T_INT(ctxt_pP->rnti)); -#ifdef GES_ENDC_SUPPORT #if 0 if(ue_context_pP != NULL) { @@ -2175,7 +2172,6 @@ rrc_eNB_generate_RRCConnectionRelease( } } -#endif #endif size = do_RRCConnectionRelease(ctxt_pP->module_id, buffer,rrc_eNB_get_next_transaction_identifier(ctxt_pP->module_id)); ue_context_pP->ue_context.ue_reestablishment_timer = 0; From b4651f244973ef001e645a48a91be68049c7e9ea Mon Sep 17 00:00:00 2001 From: "s.rampalli" Date: Fri, 29 May 2020 12:57:29 +0530 Subject: [PATCH 295/553] modified the rrc_add_nsa_user api --- openair2/RRC/NR/rrc_gNB_nsa.c | 1 - 1 file changed, 1 deletion(-) diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c index 45d56f24fa..e32d350294 100644 --- a/openair2/RRC/NR/rrc_gNB_nsa.c +++ b/openair2/RRC/NR/rrc_gNB_nsa.c @@ -138,7 +138,6 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_ ue_context_p->ue_context.secondaryCellGroup, carrier->pdsch_AntennaPorts, carrier->initial_csi_index[rrc->Nb_ue]); - ue_context_p->ue_context.rb_config = calloc(1,sizeof(NR_RRCReconfiguration_t)); ue_context_p->ue_id_rnti = ue_context_p->ue_context.secondaryCellGroup->spCellConfig->reconfigurationWithSync->newUE_Identity; NR_CG_Config_t *CG_Config = calloc(1,sizeof(*CG_Config)); memset((void *)CG_Config,0,sizeof(*CG_Config)); From 132b48ea36b87487f68e6bb9bf161d4b655e5f00 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Tue, 9 Jun 2020 11:58:57 +0200 Subject: [PATCH 296/553] Fixed bugs in pucch UE UE now sends ack/nack in format0 --- openair1/SCHED_NR_UE/fapi_nr_ue_l1.c | 1 + openair1/SCHED_NR_UE/pucch_uci_ue_nr.c | 68 ++++++++++++++++---------- openair1/SCHED_NR_UE/pucch_uci_ue_nr.h | 2 + 3 files changed, 45 insertions(+), 26 deletions(-) diff --git a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c index d8e2db7f01..da44e60f74 100644 --- a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c +++ b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c @@ -105,6 +105,7 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ dlsch0_harq->Nl=1; dlsch0_harq->mcs_table=0; dlsch0_harq->harq_ack.rx_status = downlink_harq_process(dlsch0_harq, dlsch0->current_harq_pid, dlsch_config_pdu->ndi, dlsch0->rnti_type); + dlsch0_harq->harq_ack.vDAI_DL = dlsch_config_pdu->dai; LOG_D(MAC, ">>>> \tdlsch0->g_pucch = %d\tdlsch0_harq.mcs = %d\n", dlsch0->g_pucch, dlsch0_harq->mcs); } } diff --git a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c index de6605b08d..bf0242fb99 100644 --- a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c +++ b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c @@ -347,7 +347,7 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ /**********************************************/ else if ((pucch_resource_set != MAX_NB_OF_PUCCH_RESOURCE_SETS) && (pucch_resource_id != MAX_NB_OF_PUCCH_RESOURCES)) { /* check that current configuration is supported */ - if ((mac->scg->physicalCellGroupConfig->harq_ACK_SpatialBundlingPUCCH[0] != FALSE) + if ((mac->scg->physicalCellGroupConfig->harq_ACK_SpatialBundlingPUCCH != NULL) || (mac->scg->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook != 1)) { LOG_E(PHY,"PUCCH Unsupported cell group configuration : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); return(FALSE); @@ -356,11 +356,11 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ LOG_E(PHY,"PUCCH Unsupported code block group for serving cell config : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); return(FALSE); } - pucch_resource = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceToAddModList->list.array[pucch_resource_id]; + pucch_resource = select_resource_by_id(pucch_resource_id, mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup); format = pucch_resource->format.present; nb_symbols_total = get_nb_symbols_pucch(pucch_resource, format); - starting_symbol_index = pucch_resource->startingPRB; - starting_prb = get_starting_symb_idx(pucch_resource, format); + starting_symbol_index = get_starting_symb_idx(pucch_resource, format); + starting_prb = pucch_resource->startingPRB; second_hop = starting_prb; if (format==pucch_format1_nr) time_domain_occ = pucch_resource->format.choice.format1->timeDomainOCC; @@ -779,7 +779,7 @@ uint8_t get_downlink_ack(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_t U_DAI_c = number_harq_feedback/number_of_code_word; N_m_c_rx = number_harq_feedback; int N_SPS_c = 0; /* FFS TODO_NR multicells and SPS are not supported at the moment */ - if (mac->scg->physicalCellGroupConfig->harq_ACK_SpatialBundlingPUCCH[0] == FALSE) { + if (mac->scg->physicalCellGroupConfig->harq_ACK_SpatialBundlingPUCCH == NULL) { int N_TB_max_DL = mac->DLbwp[0]->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI[0]; *n_HARQ_ACK = (((V_DAI_m_DL - U_DAI_c)%4) * N_TB_max_DL) + N_m_c_rx + N_SPS_c; NR_TST_PHY_PRINTF("PUCCH power n(%d) = ( V(%d) - U(%d) )mod4 * N_TB(%d) + N(%d) \n", *n_HARQ_ACK, V_DAI_m_DL, U_DAI_c, N_TB_max_DL, N_m_c_rx); @@ -1094,31 +1094,33 @@ boolean_t check_pucch_format(NR_UE_MAC_INST_t *mac, uint8_t gNB_id, pucch_format pucch_format_nr_t selected_pucch_format_second; NR_SetupRelease_PUCCH_FormatConfig_t *identified_format; - switch (format_pucch) { - case pucch_format1_nr: - if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1 != NULL) - identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1; - break; + if (format_pucch != pucch_format0_nr) { + switch (format_pucch) { + case pucch_format1_nr: + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1 != NULL) + identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1; + break; - case pucch_format2_nr: - if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format2 != NULL) - identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format2; - break; + case pucch_format2_nr: + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format2 != NULL) + identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format2; + break; - case pucch_format3_nr: - if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format3 != NULL) - identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format3; - break; + case pucch_format3_nr: + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format3 != NULL) + identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format3; + break; - case pucch_format4_nr: - if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format4 != NULL) - identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format4; - break; - } + case pucch_format4_nr: + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format4 != NULL) + identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format4; + break; + } - if (identified_format->choice.setup->nrofSlots != 1) { - LOG_E(PHY,"PUCCH not implemented multislots transmission : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); - return (FALSE); + if (identified_format->choice.setup->nrofSlots != 1) { + LOG_E(PHY,"PUCCH not implemented multislots transmission : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); + return (FALSE); + } } if (nb_symbols_for_tx <= 2) { @@ -1320,3 +1322,17 @@ int get_ics_pucch(NR_PUCCH_Resource_t *pucch_resource, pucch_format_nr_t format_ } } +NR_PUCCH_Resource_t *select_resource_by_id(int resource_id, NR_PUCCH_Config_t *pucch_config) +{ + int n_list = pucch_config->resourceToAddModList->list.count; + NR_PUCCH_Resource_t *pucchres; + AssertFatal(n_list>0,"PUCCH resourceToAddModList is empty\n"); + + for (int i=0; iresourceToAddModList->list.array[i]; + if (pucchres->pucch_ResourceId == resource_id) + return pucchres; + } + return NULL; +} + diff --git a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.h b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.h index 8fea1d5ab3..089fae9f55 100644 --- a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.h +++ b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.h @@ -240,4 +240,6 @@ uint8_t get_nb_symbols_pucch(NR_PUCCH_Resource_t *pucch_resource, pucch_format_n uint16_t get_starting_symb_idx(NR_PUCCH_Resource_t *pucch_resource, pucch_format_nr_t format_type); int get_ics_pucch(NR_PUCCH_Resource_t *pucch_resource, pucch_format_nr_t format_type); + +NR_PUCCH_Resource_t *select_resource_by_id(int resource_id, NR_PUCCH_Config_t *pucch_config); #endif /* PUCCH_UCI_UE_NR_H */ From dae91c60b88c8260f92f0765ba66594a3a70acb0 Mon Sep 17 00:00:00 2001 From: Ahmed Hussein Date: Tue, 9 Jun 2020 14:50:40 +0200 Subject: [PATCH 297/553] Fixing ulsim and rf simulator - no_data_in_dmrs was being used at gNB side, and not handled at UE side - nr_schedule_response wasn't being called in ulsim --- openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c | 10 +++++++--- openair1/SIMULATION/NR_PHY/ulsim.c | 16 +++++++++++----- 2 files changed, 18 insertions(+), 8 deletions(-) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c index 04a08d91aa..49ba3a83b2 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c @@ -114,6 +114,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, uint8_t data_existing =0; uint8_t L_ptrs, K_ptrs; // PTRS parameters uint16_t beta_ptrs; // PTRS parameter related to power control + uint8_t no_data_in_dmrs = 1; NR_UE_ULSCH_t *ulsch_ue; NR_UL_UE_HARQ_t *harq_process_ul_ue=NULL; @@ -147,7 +148,11 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, rnti = harq_process_ul_ue->pusch_pdu.rnti; ulsch_ue->Nid_cell = Nid_cell; - nb_dmrs_re_per_rb = ((dmrs_type == pusch_dmrs_type1) ? 6:4); + + if(no_data_in_dmrs) + nb_dmrs_re_per_rb = 12; + else + nb_dmrs_re_per_rb = ((dmrs_type == pusch_dmrs_type1) ? 6:4); N_RE_prime = NR_NB_SC_PER_RB*number_of_symbols - nb_dmrs_re_per_rb*number_dmrs_symbols - N_PRB_oh; @@ -223,7 +228,6 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, unsigned int G = nr_get_G(nb_rb, number_of_symbols, nb_dmrs_re_per_rb, number_dmrs_symbols, mod_order, Nl); - nr_ulsch_encoding(ulsch_ue, frame_parms, harq_pid, G); /////////// @@ -267,7 +271,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, /////////////////////////DMRS Modulation///////////////////////// /////////// pusch_dmrs = UE->nr_gold_pusch_dmrs[slot]; - n_dmrs = (nb_rb*nb_dmrs_re_per_rb*number_dmrs_symbols); + n_dmrs = (nb_rb*((dmrs_type == pusch_dmrs_type1) ? 6:4)*number_dmrs_symbols); int16_t mod_dmrs[n_dmrs<<1]; /////////// //////////////////////////////////////////////////////////////////////// diff --git a/openair1/SIMULATION/NR_PHY/ulsim.c b/openair1/SIMULATION/NR_PHY/ulsim.c index 9b9001d491..97cc22264a 100644 --- a/openair1/SIMULATION/NR_PHY/ulsim.c +++ b/openair1/SIMULATION/NR_PHY/ulsim.c @@ -510,9 +510,9 @@ int main(int argc, char **argv) fapi_nr_ul_config_request_t ul_config; unsigned int TBS; - uint16_t number_dmrs_symbols = 1; + uint16_t number_dmrs_symbols = 0; unsigned int available_bits; - uint8_t nb_re_dmrs; + uint8_t nb_re_dmrs, no_data_in_dmrs = 1; unsigned char mod_order; uint16_t code_rate; uint8_t ptrs_mcs1 = 2; @@ -611,8 +611,6 @@ int main(int argc, char **argv) pusch_pdu->pusch_ptrs.ptrs_ports_list = (nfapi_nr_ptrs_ports_t *) malloc(2*sizeof(nfapi_nr_ptrs_ports_t)); pusch_pdu->pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset = 0; - // prepare ULSCH/PUSCH reception - nr_schedule_response(Sched_INFO); // --------- setting parameters for UE -------- @@ -648,12 +646,20 @@ int main(int argc, char **argv) //there are plenty of other parameters that we don't seem to be using for now. e.g. ul_config.ul_config_list[0].pusch_config_pdu.absolute_delta_PUSCH = 0; - nb_re_dmrs = ((ul_config.ul_config_list[0].pusch_config_pdu.dmrs_config_type == pusch_dmrs_type1) ? 6 : 4); + if(no_data_in_dmrs) + nb_re_dmrs = 12; + else + nb_re_dmrs = ((ul_config.ul_config_list[0].pusch_config_pdu.dmrs_config_type == pusch_dmrs_type1) ? 6 : 4); + available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, number_dmrs_symbols, mod_order, 1); TBS = nr_compute_tbs(mod_order, code_rate, nb_rb, nb_symb_sch, nb_re_dmrs * number_dmrs_symbols, 0, 0, precod_nbr_layers); pusch_pdu->pusch_data.tb_size = TBS>>3; ul_config.ul_config_list[0].pusch_config_pdu.pusch_data.tb_size = TBS; + + // prepare ULSCH/PUSCH reception + nr_schedule_response(Sched_INFO); + // set FAPI parameters for UE, put them in the scheduled response and call nr_ue_scheduled_response(&scheduled_response); From 3ac51d2115e2eaafa2a22ea66008db3e00929836 Mon Sep 17 00:00:00 2001 From: Anes Rose Rigiel Antony Date: Wed, 10 Jun 2020 19:47:32 +0530 Subject: [PATCH 298/553] Removed the compilation error --- openair2/RRC/LTE/rrc_eNB.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index 8d9ce955a0..cfafd28983 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -9457,10 +9457,7 @@ rrc_enb_task( void rrc_go_nr(void); //if (go_nr) rrc_go_nr(); } -<<<<<<< HEAD } -======= ->>>>>>> 19a44bd0927547ffa58ffbcb51c840a8a770b84d } /*------------------------------------------------------------------------------*/ From 3e47e26cd1ad3c2ae3ccda0a71e9789b6ebd6926 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Wed, 10 Jun 2020 17:12:36 +0200 Subject: [PATCH 299/553] bugfix in dl harq ue --- openair1/SCHED_NR_UE/pucch_uci_ue_nr.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c index bf0242fb99..9c25b00fb0 100644 --- a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c +++ b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c @@ -743,7 +743,7 @@ uint8_t get_downlink_ack(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_t } else { - dai_current = harq_status->vDAI_DL; + dai_current = harq_status->vDAI_DL+1; // DCI DAI to counter DAI conversion if (dai_current == 0) { LOG_E(PHY,"PUCCH Downlink dai is invalid : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); @@ -756,11 +756,11 @@ uint8_t get_downlink_ack(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_t ack_data[code_word][dai_current - 1] = harq_status->ack; dai[code_word][dai_current - 1] = dai_current; } + if (do_reset == TRUE) { + init_downlink_harq_status(ue->dlsch[thread_idx][gNB_id][code_word]->harq_processes[dl_harq_pid]); + } } } - if (do_reset == TRUE) { - init_downlink_harq_status(ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][code_word]->harq_processes[dl_harq_pid]); - } } } From a4fb2e21c9b971ac27f2fe047beefc9a19e09d58 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Thu, 11 Jun 2020 09:53:10 +0200 Subject: [PATCH 300/553] linking error fix in pbchsim --- openair1/SIMULATION/NR_PHY/pbchsim.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/openair1/SIMULATION/NR_PHY/pbchsim.c b/openair1/SIMULATION/NR_PHY/pbchsim.c index 9d14391f71..4f1146384a 100644 --- a/openair1/SIMULATION/NR_PHY/pbchsim.c +++ b/openair1/SIMULATION/NR_PHY/pbchsim.c @@ -62,6 +62,8 @@ uint16_t NB_UE_INST = 1; openair0_config_t openair0_cfg[MAX_CARDS]; uint64_t get_softmodem_optmask(void) {return 0;} +void init_downlink_harq_status(NR_DL_UE_HARQ_t *dl_harq) {} + void nr_phy_config_request_sim_pbchsim(PHY_VARS_gNB *gNB, int N_RB_DL, int N_RB_UL, From 613d1e8cf0b23fed8f3e05493490f57ae1e8d97c Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Thu, 11 Jun 2020 14:24:03 +0200 Subject: [PATCH 301/553] intermediate commit --- openair1/PHY/NR_TRANSPORT/pucch_rx.c | 628 ++++++++++++------------ openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c | 18 +- 2 files changed, 337 insertions(+), 309 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/pucch_rx.c b/openair1/PHY/NR_TRANSPORT/pucch_rx.c index a822302c06..e68b495e95 100644 --- a/openair1/PHY/NR_TRANSPORT/pucch_rx.c +++ b/openair1/PHY/NR_TRANSPORT/pucch_rx.c @@ -20,15 +20,15 @@ */ /*! \file PHY/NR_TRANSPORT/pucch_rx.c -* \brief Top-level routines for decoding the PUCCH physical channel -* \author A. Mico Pereperez, Padarthi Naga Prasanth, Francesco Mani, Raymond Knopp -* \date 2020 -* \version 0.2 -* \company Eurecom -* \email: -* \note -* \warning -*/ + * \brief Top-level routines for decoding the PUCCH physical channel + * \author A. Mico Pereperez, Padarthi Naga Prasanth, Francesco Mani, Raymond Knopp + * \date 2020 + * \version 0.2 + * \company Eurecom + * \email: + * \note + * \warning + */ #include #include #include @@ -190,7 +190,7 @@ void nr_decode_pucch0(PHY_VARS_gNB *gNB, int16_t x_n_re[nr_sequences][24],x_n_im[nr_sequences][24]; for(i=0;inr_of_symbols; l++){ alpha = nr_cyclic_shift_hopping(pucch_pdu->hopping_id,pucch_pdu->initial_cyclic_shift,mcs[i],l,pucch_pdu->start_symbol_index,slot); #ifdef DEBUG_NR_PUCCH_RX @@ -200,14 +200,14 @@ void nr_decode_pucch0(PHY_VARS_gNB *gNB, alpha=0.0; for (n=0; n<12; n++){ x_n_re[i][(12*l)+n] = (int16_t)((int16_t)(((((int32_t)(round(32767*cos(alpha*n))) * table_5_2_2_2_2_Re[u][n])>>15) - - (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Im[u][n])>>15)))); // Re part of base sequence shifted by alpha + - (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Im[u][n])>>15)))); // Re part of base sequence shifted by alpha x_n_im[i][(12*l)+n] =(int16_t)((int16_t)(((((int32_t)(round(32767*cos(alpha*n))) * table_5_2_2_2_2_Im[u][n])>>15) - + (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Re[u][n])>>15)))); // Im part of base sequence shifted by alpha + + (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Re[u][n])>>15)))); // Im part of base sequence shifted by alpha #ifdef DEBUG_NR_PUCCH_RX - printf("\t [nr_generate_pucch0] sequence generation \tu=%d \tv=%d \talpha=%lf \tx_n(l=%d,n=%d)=(%d,%d) %d,%d\n", - u,v,alpha,l,n,x_n_re[i][(12*l)+n],x_n_im[i][(12*l)+n], - (int32_t)(round(32767*cos(alpha*n))), - (int32_t)(round(32767*sin(alpha*n)))); + printf("\t [nr_generate_pucch0] sequence generation \tu=%d \tv=%d \talpha=%lf \tx_n(l=%d,n=%d)=(%d,%d) %d,%d\n", + u,v,alpha,l,n,x_n_re[i][(12*l)+n],x_n_im[i][(12*l)+n], + (int32_t)(round(32767*cos(alpha*n))), + (int32_t)(round(32767*sin(alpha*n)))); #endif } } @@ -229,12 +229,12 @@ void nr_decode_pucch0(PHY_VARS_gNB *gNB, r_re[(12*l)+n]=((int16_t *)&rxdataF[0][(l2*frame_parms->ofdm_symbol_size)+re_offset])[0]; r_im[(12*l)+n]=((int16_t *)&rxdataF[0][(l2*frame_parms->ofdm_symbol_size)+re_offset])[1]; - #ifdef DEBUG_NR_PUCCH_RX - printf("\t [nr_generate_pucch0] mapping to RE \tofdm_symbol_size=%d \tN_RB_DL=%d \tfirst_carrier_offset=%d \ttxptr(%d)=(x_n(l=%d,n=%d)=(%d,%d))\n", - frame_parms->ofdm_symbol_size,frame_parms->N_RB_DL,frame_parms->first_carrier_offset,(l2*frame_parms->ofdm_symbol_size)+re_offset, - l,n,((int16_t *)&rxdataF[0][(l2*frame_parms->ofdm_symbol_size)+re_offset])[0], - ((int16_t *)&rxdataF[0][(l2*frame_parms->ofdm_symbol_size)+re_offset])[1]); - #endif +#ifdef DEBUG_NR_PUCCH_RX + printf("\t [nr_generate_pucch0] mapping to RE \tofdm_symbol_size=%d \tN_RB_DL=%d \tfirst_carrier_offset=%d \ttxptr(%d)=(x_n(l=%d,n=%d)=(%d,%d))\n", + frame_parms->ofdm_symbol_size,frame_parms->N_RB_DL,frame_parms->first_carrier_offset,(l2*frame_parms->ofdm_symbol_size)+re_offset, + l,n,((int16_t *)&rxdataF[0][(l2*frame_parms->ofdm_symbol_size)+re_offset])[0], + ((int16_t *)&rxdataF[0][(l2*frame_parms->ofdm_symbol_size)+re_offset])[1]); +#endif re_offset++; if (re_offset>= frame_parms->ofdm_symbol_size) re_offset-=frame_parms->ofdm_symbol_size; @@ -299,7 +299,7 @@ void nr_decode_pucch0(PHY_VARS_gNB *gNB, n2=0; for (l=0;lnr_of_symbols;l++) { - seq_index = (pucch_pdu->initial_cyclic_shift+ + seq_index = (pucch_pdu->initial_cyclic_shift+ mcs[i]+ gNB->pucch0_lut.lut[cs_ind][slot][l+pucch_pdu->start_symbol_index])%12; for (n=0;n<12;n++,n2+=2) { @@ -504,13 +504,13 @@ void nr_decode_pucch1( int32_t **rxdataF, if (l%2 == 0) { // mapping DM-RS signal according to TS38.211 subclause 6.4.1.3.1 z_dmrs_re_rx[i+n] = ((int16_t *)&rxdataF[0][re_offset])[0]; z_dmrs_im_rx[i+n] = ((int16_t *)&rxdataF[0][re_offset])[1]; -// printf("%d\t%d\t%d\n",l,z_dmrs_re_rx[i+n],z_dmrs_im_rx[i+n]); + // printf("%d\t%d\t%d\n",l,z_dmrs_re_rx[i+n],z_dmrs_im_rx[i+n]); #ifdef DEBUG_NR_PUCCH_RX printf("\t [nr_generate_pucch1] mapping DM-RS to RE \t amp=%d \tofdm_symbol_size=%d \tN_RB_DL=%d \tfirst_carrier_offset=%d \tz_dm-rs[%d]=txptr(%d)=(x_n(l=%d,n=%d)=(%d,%d))\n", amp,frame_parms->ofdm_symbol_size,frame_parms->N_RB_DL,frame_parms->first_carrier_offset,i+n,re_offset, l,n,((int16_t *)&rxdataF[0][re_offset])[0],((int16_t *)&rxdataF[0][re_offset])[1]); #endif -// printf("l=%d\ti=%d\tre_offset=%d\treceived dmrs re=%d\tim=%d\n",l,i,re_offset,z_dmrs_re_rx[i+n],z_dmrs_im_rx[i+n]); + // printf("l=%d\ti=%d\tre_offset=%d\treceived dmrs re=%d\tim=%d\n",l,i,re_offset,z_dmrs_re_rx[i+n],z_dmrs_im_rx[i+n]); } re_offset++; @@ -529,7 +529,7 @@ void nr_decode_pucch1( int32_t **rxdataF, l,lprime); #endif // y_n contains the complex value d multiplied by the sequence r_u_v - if ((intraSlotFrequencyHopping == 1) && (l >= (int)floor(nrofSymbols/2))) n_hop = 1; // n_hop = 1 for second hop + if ((intraSlotFrequencyHopping == 1) && (l >= (int)floor(nrofSymbols/2))) n_hop = 1; // n_hop = 1 for second hop #ifdef DEBUG_NR_PUCCH_RX printf("\t [nr_generate_pucch1] entering function nr_group_sequence_hopping with n_hop=%d, nr_tti_tx=%d\n", @@ -547,18 +547,18 @@ void nr_decode_pucch1( int32_t **rxdataF, } else{ r_u_v_alpha_delta_dmrs_re[n] = (int16_t)(((((int32_t)(round(32767*cos(alpha*n))) * table_5_2_2_2_2_Re[u][n])>>15) - - (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Im[u][n])>>15))); // Re part of DMRS base sequence shifted by alpha + - (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Im[u][n])>>15))); // Re part of DMRS base sequence shifted by alpha r_u_v_alpha_delta_dmrs_im[n] = (int16_t)(((((int32_t)(round(32767*cos(alpha*n))) * table_5_2_2_2_2_Im[u][n])>>15) - + (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Re[u][n])>>15))); // Im part of DMRS base sequence shifted by alpha + + (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Re[u][n])>>15))); // Im part of DMRS base sequence shifted by alpha r_u_v_alpha_delta_dmrs_re[n] = (int16_t)(((int32_t)(amp*r_u_v_alpha_delta_dmrs_re[n]))>>15); r_u_v_alpha_delta_dmrs_im[n] = (int16_t)(((int32_t)(amp*r_u_v_alpha_delta_dmrs_im[n]))>>15); } -// printf("symbol=%d\tr_u_rx_re=%d\tr_u_rx_im=%d\n",l,r_u_v_alpha_delta_dmrs_re[n], r_u_v_alpha_delta_dmrs_im[n]); + // printf("symbol=%d\tr_u_rx_re=%d\tr_u_rx_im=%d\n",l,r_u_v_alpha_delta_dmrs_re[n], r_u_v_alpha_delta_dmrs_im[n]); // PUCCH sequence = DM-RS sequence multiplied by d(0) -/* y_n_re[n] = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*d_re)>>15) - - (((int32_t)(r_u_v_alpha_delta_im[n])*d_im)>>15))); // Re part of y(n) - y_n_im[n] = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*d_im)>>15) - + (((int32_t)(r_u_v_alpha_delta_im[n])*d_re)>>15))); // Im part of y(n) */ + /* y_n_re[n] = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*d_re)>>15) + - (((int32_t)(r_u_v_alpha_delta_im[n])*d_im)>>15))); // Re part of y(n) + y_n_im[n] = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*d_im)>>15) + + (((int32_t)(r_u_v_alpha_delta_im[n])*d_re)>>15))); // Im part of y(n) */ #ifdef DEBUG_NR_PUCCH_RX printf("\t [nr_generate_pucch1] sequence generation \tu=%d \tv=%d \talpha=%lf \tr_u_v_alpha_delta[n=%d]=(%d,%d) \ty_n[n=%d]=(%d,%d)\n", u,v,alpha,n,r_u_v_alpha_delta_re[n],r_u_v_alpha_delta_im[n],n,y_n_re[n],y_n_im[n]); @@ -608,12 +608,12 @@ void nr_decode_pucch1( int32_t **rxdataF, if(floor(l/2)*12==(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)){ for (int n=0; n<12 ; n++) { z_re_temp = (int16_t)(((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15) - + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); + + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); z_im_temp = (int16_t)(((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15) - - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); + - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]=z_re_temp; z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]=z_im_temp; -// printf("symbol=%d\tz_re_rx=%d\tz_im_rx=%d\t",l,(int)z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(int)z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); + // printf("symbol=%d\tz_re_rx=%d\tz_im_rx=%d\t",l,(int)z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(int)z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); #ifdef DEBUG_NR_PUCCH_RX printf("\t [nr_generate_pucch1] block-wise spread with wi(m) (mprime=%d, m=%d, n=%d) z[%d] = ((%d * %d - %d * %d), (%d * %d + %d * %d)) = (%d,%d)\n", mprime, m, n, (mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n, @@ -623,15 +623,15 @@ void nr_decode_pucch1( int32_t **rxdataF, #endif // multiplying with conjugate of low papr sequence z_re_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15) - + (((int32_t)(r_u_v_alpha_delta_im[n])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); + + (((int32_t)(r_u_v_alpha_delta_im[n])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); z_im_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15) - - (((int32_t)(r_u_v_alpha_delta_im[n])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); + - (((int32_t)(r_u_v_alpha_delta_im[n])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n] = z_re_temp; z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n] = z_im_temp; -/* if(z_re_temp<0){ - printf("\nBug detection %d\t%d\t%d\t%d\n",r_u_v_alpha_delta_re[n],z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(((int32_t)(r_u_v_alpha_delta_re[n])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15),(((int32_t)(r_u_v_alpha_delta_im[n])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15)); - } - printf("z1_re_rx=%d\tz1_im_rx=%d\n",(int)z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(int)z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); */ + /* if(z_re_temp<0){ + printf("\nBug detection %d\t%d\t%d\t%d\n",r_u_v_alpha_delta_re[n],z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(((int32_t)(r_u_v_alpha_delta_re[n])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15),(((int32_t)(r_u_v_alpha_delta_im[n])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15)); + } + printf("z1_re_rx=%d\tz1_im_rx=%d\n",(int)z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(int)z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); */ } } } @@ -642,12 +642,12 @@ void nr_decode_pucch1( int32_t **rxdataF, if(floor(l/2)*12==(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)){ for (int n=0; n<12 ; n++) { z_dmrs_re_temp = (int16_t)(((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15) - + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); + + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); z_dmrs_im_temp = (int16_t)(((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15) - - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); + - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = z_dmrs_re_temp; z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = z_dmrs_im_temp; -// printf("symbol=%d\tz_dmrs_re_rx=%d\tz_dmrs_im_rx=%d\t",l,(int)z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(int)z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); + // printf("symbol=%d\tz_dmrs_re_rx=%d\tz_dmrs_im_rx=%d\t",l,(int)z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(int)z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); #ifdef DEBUG_NR_PUCCH_RX printf("\t [nr_generate_pucch1] block-wise spread with wi(m) (mprime=%d, m=%d, n=%d) z[%d] = ((%d * %d - %d * %d), (%d * %d + %d * %d)) = (%d,%d)\n", mprime, m, n, (mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n, @@ -657,17 +657,17 @@ void nr_decode_pucch1( int32_t **rxdataF, #endif //finding channel coeffcients by dividing received dmrs with actual dmrs and storing them in z_dmrs_re_rx and z_dmrs_im_rx arrays z_dmrs_re_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_dmrs_re[n])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15) - + (((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); + + (((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); z_dmrs_im_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_dmrs_re[n])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15) - - (((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); -/* if(z_dmrs_re_temp<0){ - printf("\nBug detection %d\t%d\t%d\t%d\n",r_u_v_alpha_delta_dmrs_re[n],z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(((int32_t)(r_u_v_alpha_delta_dmrs_re[n])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15),(((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15)); - }*/ + - (((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); + /* if(z_dmrs_re_temp<0){ + printf("\nBug detection %d\t%d\t%d\t%d\n",r_u_v_alpha_delta_dmrs_re[n],z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(((int32_t)(r_u_v_alpha_delta_dmrs_re[n])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15),(((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15)); + }*/ z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = z_dmrs_re_temp; z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = z_dmrs_im_temp; -// printf("z1_dmrs_re_rx=%d\tz1_dmrs_im_rx=%d\n",(int)z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(int)z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); - /* z_dmrs_re_rx[(int)(l/2)*12+n]=z_dmrs_re_rx[(int)(l/2)*12+n]/r_u_v_alpha_delta_dmrs_re[n]; - z_dmrs_im_rx[(int)(l/2)*12+n]=z_dmrs_im_rx[(int)(l/2)*12+n]/r_u_v_alpha_delta_dmrs_im[n]; */ + // printf("z1_dmrs_re_rx=%d\tz1_dmrs_im_rx=%d\n",(int)z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(int)z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); + /* z_dmrs_re_rx[(int)(l/2)*12+n]=z_dmrs_re_rx[(int)(l/2)*12+n]/r_u_v_alpha_delta_dmrs_re[n]; + z_dmrs_im_rx[(int)(l/2)*12+n]=z_dmrs_im_rx[(int)(l/2)*12+n]/r_u_v_alpha_delta_dmrs_im[n]; */ } } } @@ -694,9 +694,9 @@ void nr_decode_pucch1( int32_t **rxdataF, if(floor(l/2)*12==(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)){ for (int n=0; n<12 ; n++) { z_re_temp = (int16_t)(((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15) - + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); + + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); z_im_temp = (int16_t)(((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15) - - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); + - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n] = z_re_temp; z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n] = z_im_temp; #ifdef DEBUG_NR_PUCCH_RX @@ -707,9 +707,9 @@ void nr_decode_pucch1( int32_t **rxdataF, z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); #endif z_re_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15) - + (((int32_t)(r_u_v_alpha_delta_im[n])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); + + (((int32_t)(r_u_v_alpha_delta_im[n])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); z_im_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15) - - (((int32_t)(r_u_v_alpha_delta_im[n])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); + - (((int32_t)(r_u_v_alpha_delta_im[n])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1); z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n] = z_re_temp; z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n] = z_im_temp; } @@ -722,9 +722,9 @@ void nr_decode_pucch1( int32_t **rxdataF, if(floor(l/2)*12==(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)){ for (int n=0; n<12 ; n++) { z_dmrs_re_temp = (int16_t)(((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15) - + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); + + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); z_dmrs_im_temp = (int16_t)(((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15) - - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); + - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = z_dmrs_re_temp; z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = z_dmrs_im_temp; #ifdef DEBUG_NR_PUCCH_RX @@ -736,14 +736,14 @@ void nr_decode_pucch1( int32_t **rxdataF, #endif //finding channel coeffcients by dividing received dmrs with actual dmrs and storing them in z_dmrs_re_rx and z_dmrs_im_rx arrays z_dmrs_re_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_dmrs_re[n])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15) - + (((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); + + (((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); z_dmrs_im_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_dmrs_re[n])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15) - - (((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); + - (((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1); z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = z_dmrs_re_temp; z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = z_dmrs_im_temp; - /* z_dmrs_re_rx[(int)(l/2)*12+n]=z_dmrs_re_rx[(int)(l/2)*12+n]/r_u_v_alpha_delta_dmrs_re[n]; - z_dmrs_im_rx[(int)(l/2)*12+n]=z_dmrs_im_rx[(int)(l/2)*12+n]/r_u_v_alpha_delta_dmrs_im[n]; */ + /* z_dmrs_re_rx[(int)(l/2)*12+n]=z_dmrs_re_rx[(int)(l/2)*12+n]/r_u_v_alpha_delta_dmrs_re[n]; + z_dmrs_im_rx[(int)(l/2)*12+n]=z_dmrs_im_rx[(int)(l/2)*12+n]/r_u_v_alpha_delta_dmrs_im[n]; */ } } } @@ -795,8 +795,8 @@ void nr_decode_pucch1( int32_t **rxdataF, for(int n=0;n<12;n++){ y_n_re[n]=round(z_re_rx[l*12+n]/floor(nrofSymbols/4))+y_n_re[n]; y_n_im[n]=round(z_im_rx[l*12+n]/floor(nrofSymbols/4))+y_n_im[n]; - } - } + } + } else{ for(int n=0;n<12;n++){ y1_n_re[n]=round(z_re_rx[l*12+n]/round(nrofSymbols/4))+y1_n_re[n]; @@ -828,12 +828,12 @@ void nr_decode_pucch1( int32_t **rxdataF, } //Decoding QPSK or BPSK symbols to obtain payload bits if(nr_bit==1){ - if((d_re+d_im)>0){ - *payload=0; - } - else{ - *payload=1; - } + if((d_re+d_im)>0){ + *payload=0; + } + else{ + *payload=1; + } } else if(nr_bit==2){ if((d_re>0)&&(d_im>0)){ @@ -871,7 +871,7 @@ __m256i *pucch2_lut[9]={pucch2_3bit, pucch2_10bit, pucch2_11bit}; -__m64 pucch2_polar_8bit[256*2]; +__m64 pucch2_polar_4bit[16]; void init_pucch2_luts() { @@ -952,25 +952,17 @@ void init_pucch2_luts() { *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,15); } } - for (uint16_t i=0;i<256;i++) { - __m64 *lut_i=&pucch2_polar_8bit[i<<1]; - __m64 *lut_ip1=&pucch2_polar_8bit[1+(i<<1)]; - bit = (out&0x1) > 0 ? -1 : 1; + for (uint16_t i=0;i<16;i++) { + __m64 *lut_i=&pucch2_polar_4bit[i]; + + bit = (i&0x1) > 0 ? -1 : 1; *lut_i = _mm_insert_pi16(*lut_i,bit,0); - bit = (out&0x2) > 0 ? -1 : 1; - *lut_ip1 = _mm_insert_pi16(*lut_ip1,bit,0); - bit = (out&0x4) > 0 ? -1 : 1; + bit = (i&0x2) > 0 ? -1 : 1; *lut_i = _mm_insert_pi16(*lut_i,bit,1); - bit = (out&0x8) > 0 ? -1 : 1; - *lut_ip1 = _mm_insert_pi16(*lut_ip1,bit,1); - bit = (out&0x10) > 0 ? -1 : 1; + bit = (i&0x4) > 0 ? -1 : 1; *lut_i = _mm_insert_pi16(*lut_i,bit,2); - bit = (out&0x20) > 0 ? -1 : 1; - *lut_ip1 = _mm_insert_pi16(*lut_ip1,bit,2); - bit = (out&0x40) > 0 ? -1 : 1; + bit = (i&0x8) > 0 ? -1 : 1; *lut_i = _mm_insert_pi16(*lut_i,bit,3); - bit = (out&0x80) > 0 ? -1 : 1; - *lut_ip1 = _mm_insert_pi16(*lut_ip1,bit,3); } } @@ -1024,165 +1016,166 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB, for (int aa=0;aanr_of_symbols == 1) { - AssertFatal((pucch_pdu->prb_size&1) == 0,"prb_size %d is not a multiple of 2\n",pucch_pdu->prb_size); - // 24 PRBs contains 48x16-bit, so 6x8x16-bit - for (int prb=0;prbprb_size;prb+=2) { - for (int aa=0;aaprb_size&1) == 0,"prb_size %d is not a multiple of 2\n",pucch_pdu->prb_size); + // 24 PRBs contains 48x16-bit, so 6x8x16-bit + for (int prb=0;prbprb_size;prb+=2) { + for (int aa=0;aa (%d,%d)\n",aa,prb+(i>>2),i,rd_re_ext_p[i],rd_im_ext_p[i],i); + for (int i=0;i<8;i++) printf("Ant %d PRB %d dmrs[%d] -> (%d,%d)\n",aa,prb+(i>>2),i,rd_re_ext_p[i],rd_im_ext_p[i],i); + for (int i=0;i<16;i++) printf("Ant %d PRB %d data[%d] -> (%d,%d)\n",aa,prb+(i>>3),i,r_re_ext_p[i],r_im_ext_p[i],i); #endif - rp[aa]+=48; - } // aa - } // prb + rp[aa]+=48; + } // aa + } // prb - // first compute DMRS component - uint32_t x1, x2, s=0; - x2 = (((1<<17)*((14*slot) + (pucch_pdu->start_symbol_index) + 1)*((2*pucch_pdu->dmrs_scrambling_id) + 1)) + (2*pucch_pdu->dmrs_scrambling_id))%(1U<<31); // c_init calculation according to TS38.211 subclause + // first compute DMRS component + uint32_t x1, x2, s=0; + x2 = (((1<<17)*((14*slot) + (pucch_pdu->start_symbol_index) + 1)*((2*pucch_pdu->dmrs_scrambling_id) + 1)) + (2*pucch_pdu->dmrs_scrambling_id))%(1U<<31); // c_init calculation according to TS38.211 subclause #ifdef DEBUG_NR_PUCCH_RX - printf("slot %d, start_symbol_index %d, dmrs_scrambling_id %d\n", - slot,pucch_pdu->start_symbol_index,pucch_pdu->dmrs_scrambling_id); + printf("slot %d, start_symbol_index %d, dmrs_scrambling_id %d\n", + slot,pucch_pdu->start_symbol_index,pucch_pdu->dmrs_scrambling_id); #endif - s = lte_gold_generic(&x1, &x2, 1); + s = lte_gold_generic(&x1, &x2, 1); - for (int group=0;group>=5; - corr32_im[group][aa]>>=5; + corr32_re[group][aa]+=(rd_re_ext_p[4]*((int16_t*)&dmrs_re)[0] + rd_im_ext_p[4]*((int16_t*)&dmrs_im)[0]); + corr32_im[group][aa]+=(-rd_re_ext_p[4]*((int16_t*)&dmrs_im)[0] + rd_im_ext_p[4]*((int16_t*)&dmrs_re)[0]); + corr32_re[group][aa]+=(rd_re_ext_p[5]*((int16_t*)&dmrs_re)[1] + rd_im_ext_p[5]*((int16_t*)&dmrs_im)[1]); + corr32_im[group][aa]+=(-rd_re_ext_p[5]*((int16_t*)&dmrs_im)[1] + rd_im_ext_p[5]*((int16_t*)&dmrs_re)[1]); + corr32_re[group][aa]+=(rd_re_ext_p[6]*((int16_t*)&dmrs_re)[2] + rd_im_ext_p[6]*((int16_t*)&dmrs_im)[2]); + corr32_im[group][aa]+=(-rd_re_ext_p[6]*((int16_t*)&dmrs_im)[2] + rd_im_ext_p[6]*((int16_t*)&dmrs_re)[2]); + corr32_re[group][aa]+=(rd_re_ext_p[7]*((int16_t*)&dmrs_re)[3] + rd_im_ext_p[7]*((int16_t*)&dmrs_im)[3]); + corr32_im[group][aa]+=(-rd_re_ext_p[7]*((int16_t*)&dmrs_im)[3] + rd_im_ext_p[7]*((int16_t*)&dmrs_re)[3]); + corr32_re[group][aa]>>=5; + corr32_im[group][aa]>>=5; #ifdef DEBUG_NR_PUCCH_RX - printf("Group %d: corr32 (%d,%d)\n",group,corr32_re[group][aa],corr32_im[group][aa]); + printf("Group %d: corr32 (%d,%d)\n",group,corr32_re[group][aa],corr32_im[group][aa]); #endif - } //aa + } //aa - if ((group&1) == 1) s = lte_gold_generic(&x1, &x2, 0); - } // group + if ((group&1) == 1) s = lte_gold_generic(&x1, &x2, 0); + } // group } else { // 2 symbol case - AssertFatal(1==0, "Fill in 2 symbol PUCCH2 case\n"); + AssertFatal(1==0, "Fill in 2 symbol PUCCH2 case\n"); } uint32_t x1, x2, s=0; @@ -1207,47 +1200,47 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB, for (int aa=0;aabit_len_csi_part1 + pucch_pdu->bit_len_csi_part2 == 0,"no csi for now\n"); AssertFatal((pucch_pdu->bit_len_harq+pucch_pdu->sr_flag > 2 ) && (pucch_pdu->bit_len_harq+pucch_pdu->sr_flag < 65),"illegal length (%d,%d)\n",pucch_pdu->bit_len_harq,pucch_pdu->sr_flag); @@ -1331,6 +1327,19 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB, _mm256_mullo_epi16(pucch2_lut[nb_bit-3][(cw<<1)+1],rp_im[aa][0])),5); prod_im[aa] = _mm256_srai_epi16(_mm256_subs_epi16(_mm256_mullo_epi16(pucch2_lut[nb_bit-3][cw<<1],rp2_im[aa][0]), _mm256_mullo_epi16(pucch2_lut[nb_bit-3][(cw<<1)+1],rp2_re[aa][0])),5); +#ifdef DEBUG_NR_PUCCH_RX + printf("prod_re[%d] => (%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d)",aa, + ((int16_t*)&prod_re[aa])[0],((int16_t*)&prod_re[aa])[1],((int16_t*)&prod_re[aa])[2],((int16_t*)&prod_re[aa])[3], + ((int16_t*)&prod_re[aa])[4],((int16_t*)&prod_re[aa])[5],((int16_t*)&prod_re[aa])[6],((int16_t*)&prod_re[aa])[7], + ((int16_t*)&prod_re[aa])[8],((int16_t*)&prod_re[aa])[9],((int16_t*)&prod_re[aa])[10],((int16_t*)&prod_re[aa])[11], + ((int16_t*)&prod_re[aa])[12],((int16_t*)&prod_re[aa])[13],((int16_t*)&prod_re[aa])[14],((int16_t*)&prod_re[aa])[15]); + printf("prod_im[%d] => (%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d)",aa, + ((int16_t*)&prod_im[aa])[0],((int16_t*)&prod_im[aa])[1],((int16_t*)&prod_im[aa])[2],((int16_t*)&prod_im[aa])[3], + ((int16_t*)&prod_im[aa])[4],((int16_t*)&prod_im[aa])[5],((int16_t*)&prod_im[aa])[6],((int16_t*)&prod_im[aa])[7], + ((int16_t*)&prod_im[aa])[8],((int16_t*)&prod_im[aa])[9],((int16_t*)&prod_im[aa])[10],((int16_t*)&prod_im[aa])[11], + ((int16_t*)&prod_im[aa])[12],((int16_t*)&prod_im[aa])[13],((int16_t*)&prod_im[aa])[14],((int16_t*)&prod_im[aa])[15]); + +#endif prod_re[aa] = _mm256_hadds_epi16(prod_re[aa],prod_re[aa]);// 0+1 prod_im[aa] = _mm256_hadds_epi16(prod_im[aa],prod_im[aa]); prod_re[aa] = _mm256_hadds_epi16(prod_re[aa],prod_re[aa]);// 0+1+2+3 @@ -1383,58 +1392,69 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB, } } else { // polar coded case - __m64 *rp_re[Prx2]; - __m64 *rp2_re[Prx2]; - __m64 *rp_im[Prx2]; - __m64 *rp2_im[Prx2]; - for (int aa=0;aa>1], - ((int16_t*)&pucch2_lut[nb_bit-3][cw<<1])[1+(i>>1)]); + __m64 *rp_re[Prx2]; + __m64 *rp2_re[Prx2]; + __m64 *rp_im[Prx2]; + __m64 *rp2_im[Prx2]; + for (int aa=0;aa>1]); + } + printf("\n"); #endif - } - // non-coherent LLR computation on groups of 4 REs (half-PRBs) - for (in half_prb=0;half_prb<(2*pucch_pdu->prb_size);half_prb++) { - for (int cw=0;cw<256;cw++) { - for (int aa=0;aa>2][aa],corr32_im[half_prb>>2][aa], - ((int16_t*)(&prod_re[aa]))[0], - ((int16_t*)(&prod_im[aa]))[0], - corr32_re[half_prb>>2][aa]+((int16_t*)(&prod_re[aa]))[0], - corr32_im[half_prb>>2][aa]+((int16_t*)(&prod_im[aa]))[0]); + } + // non-coherent LLR computation on groups of 4 REs (half-PRBs) + int32_t corr_re,corr_im,corr_tmp; + for (int half_prb=0;half_prb<(2*pucch_pdu->prb_size);half_prb++) { + for (int cw=0;cw<256;cw++) { + corr_tmp=0; + for (int aa=0;aa>4],rp_im[aa][half_prb])),5); + prod_im[aa] = _mm_srai_pi16(_mm_subs_pi16(_mm_mullo_pi16(pucch2_polar_4bit[cw&15],rp2_im[aa][half_prb]), + _mm_mullo_pi16(pucch2_polar_4bit[cw>>4],rp2_re[aa][half_prb])),5); + prod_re[aa] = _mm_hadds_pi16(prod_re[aa],prod_re[aa]);// 0+1 + prod_im[aa] = _mm_hadds_pi16(prod_im[aa],prod_im[aa]); + prod_re[aa] = _mm_hadds_pi16(prod_re[aa],prod_re[aa]);// 0+1+2+3 + prod_im[aa] = _mm_hadds_pi16(prod_im[aa],prod_im[aa]); - corr_re = ( corr32_re[half_prb>>2][aa]+((int16_t*)(&prod_re[aa]))[0]); - corr_im = ( corr32_im[half_prb>>2][aa]+((int16_t*)(&prod_im[aa]))[0]); - corr_tmp += corr_re*corr_re + corr_im*corr_im; + + corr_re = ( corr32_re[half_prb>>2][aa]/(2*nc_group_size*4/2)+((int16_t*)(&prod_re[aa]))[0]); + corr_im = ( corr32_im[half_prb>>2][aa]/(2*nc_group_size*4/2)+((int16_t*)(&prod_im[aa]))[0]); + corr_tmp += corr_re*corr_re + corr_im*corr_im; + LOG_D(PHY,"pucch2 half_prb %d cw %d (%d,%d) aa %d: (%d,%d,%d,%d,%d,%d,%d,%d)x(%d,%d,%d,%d,%d,%d,%d,%d) (%d,%d)+(%d,%d) = (%d,%d) => %d\n", + half_prb,cw,cw&15,cw>>4,aa, + ((int16_t*)&pucch2_polar_4bit[cw&15])[0],((int16_t*)&pucch2_polar_4bit[cw>>4])[0], + ((int16_t*)&pucch2_polar_4bit[cw&15])[1],((int16_t*)&pucch2_polar_4bit[cw>>4])[1], + ((int16_t*)&pucch2_polar_4bit[cw&15])[2],((int16_t*)&pucch2_polar_4bit[cw>>4])[2], + ((int16_t*)&pucch2_polar_4bit[cw&15])[3],((int16_t*)&pucch2_polar_4bit[cw>>4])[3], + ((int16_t*)&rp_re[aa][half_prb])[0],((int16_t*)&rp_im[aa][half_prb])[0], + ((int16_t*)&rp_re[aa][half_prb])[1],((int16_t*)&rp_im[aa][half_prb])[1], + ((int16_t*)&rp_re[aa][half_prb])[2],((int16_t*)&rp_im[aa][half_prb])[2], + ((int16_t*)&rp_re[aa][half_prb])[3],((int16_t*)&rp_im[aa][half_prb])[3], + corr32_re[half_prb>>2][aa]/(2*nc_group_size*4/2),corr32_im[half_prb>>2][aa]/(2*nc_group_size*4/2), + ((int16_t*)(&prod_re[aa]))[0], + ((int16_t*)(&prod_im[aa]))[0], + corr_re, + corr_im, + corr_tmp); + } } - int64_t corr_tmp = corr_re*corr_re + corr_im*corr_im; - } - AssertFatal(1==0,"stopping here\n"); - } + } // half_prb + AssertFatal(1==0,"stopping here\n"); + + } // n_bit > 11 } diff --git a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c index 5b7734865b..0e18b2f440 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c +++ b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c @@ -806,19 +806,27 @@ inline void nr_pucch2_3_4_scrambling(uint16_t M_bit,uint16_t rnti,uint16_t n_id, // c_init=nRNTI*2^15+n_id according to TS 38.211 Subclause 6.3.2.6.1 //x2 = (rnti) + ((uint32_t)(1+nr_tti_tx)<<16)*(1+(fp->Nid_cell<<1)); x2 = ((rnti)<<15)+n_id; - s = lte_gold_generic(&x1, &x2, 1); #ifdef DEBUG_NR_PUCCH_TX printf("\t\t [nr_pucch2_3_4_scrambling] gold sequence s=%x\n",s); #endif - for (i=0; i>i)&1); - btilde[i] = (((B>>i)&1) ^ c); + uint8_t *btildep=btilde; + int M_bit2=M_bit > 31 ? 32 : (M_bit&31), M_bit3=M_bit; + for (int iprime=0;iprime<=(M_bit>>5);iprime++,btildep+=32) { + s = lte_gold_generic(&x1, &x2, (iprime==0) ? 1 : 0); + + for (i=0; i>i)&1); + btildep[i] = (((B>>i)&1) ^ c); #ifdef DEBUG_NR_PUCCH_TX - //printf("\t\t\t btilde[%d]=%lx from scrambled bit %d\n",i,btilde[i],((B>>i)&1)); + printf("\t\t\t btilde[%d]=%lx from unscrambled bit %d and scrambling %d (%x)\n",i+(iprime<<5),btilde[i],((B>>i)&1),c,s>>i); #endif + } + M_bit3-=32; + M_bit2=M_bit3 > 31 ? 32 : (M_bit3&31); } + #ifdef DEBUG_NR_PUCCH_TX printf("\t\t [nr_pucch2_3_4_scrambling] scrambling M_bit=%d bits\n", M_bit); #endif From 68366cb686864c4acbd43a93981c3cdf5251b299 Mon Sep 17 00:00:00 2001 From: WANG Tsu-Han Date: Thu, 11 Jun 2020 18:03:05 +0200 Subject: [PATCH 302/553] adding executional option for usrp trx thread and adding null device function for device other than usrp --- executables/nr-ru.c | 16 ++++++++++------ executables/nr-softmodem-common.h | 5 +++++ executables/nr-softmodem.c | 1 + executables/nr-softmodem.h | 1 + targets/ARCH/BLADERF/USERSPACE/LIB/bladerf_lib.c | 6 +++++- .../ARCH/ETHERNET/USERSPACE/LIB/ethernet_lib.c | 9 +++++++-- targets/ARCH/IRIS/USERSPACE/LIB/iris_lib.cpp | 6 ++++++ targets/ARCH/LMSSDR/USERSPACE/LIB/lms_lib.cpp | 5 +++++ targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp | 9 +++++---- targets/ARCH/tcp_bridge/tcp_bridge.c | 6 ++++++ 10 files changed, 51 insertions(+), 13 deletions(-) diff --git a/executables/nr-ru.c b/executables/nr-ru.c index 3ea026f6e6..69155c18d4 100644 --- a/executables/nr-ru.c +++ b/executables/nr-ru.c @@ -117,6 +117,7 @@ uint16_t sl_ahead; extern int emulate_rf; extern int numerology; +extern int usrp_tx_thread; /*************************************************************/ /* Functions to attach and configure RRU */ @@ -1465,12 +1466,15 @@ void *ru_thread( void *param ) { if ((ru->is_slave) && (ru->if_south == LOCAL_RF)) do_ru_synch(ru); // start trx write thread - if (ru->start_write_thread){ - if(ru->start_write_thread(ru) != 0){ - LOG_E(HW,"Could not start tx write thread\n"); - } - else{ - LOG_I(PHY,"tx write thread ready\n"); + if(usrp_tx_thread == 1){ +printf("~~~~~~~~~~~testing if the command is get\n"); + if (ru->start_write_thread){ + if(ru->start_write_thread(ru) != 0){ + LOG_E(HW,"Could not start tx write thread\n"); + } + else{ + LOG_I(PHY,"tx write thread ready\n"); + } } } } diff --git a/executables/nr-softmodem-common.h b/executables/nr-softmodem-common.h index ccb3f28d98..c489ad4314 100644 --- a/executables/nr-softmodem-common.h +++ b/executables/nr-softmodem-common.h @@ -89,6 +89,7 @@ #define CONFIG_HLP_EMULATE_RF "Emulated RF enabled(disable by defult)\n" #define CONFIG_HLP_PARALLEL_CMD "three config for level of parallelism 'PARALLEL_SINGLE_THREAD', 'PARALLEL_RU_L1_SPLIT', or 'PARALLEL_RU_L1_TRX_SPLIT'\n" #define CONFIG_HLP_WORKER_CMD "two option for worker 'WORKER_DISABLE' or 'WORKER_ENABLE'\n" +#define CONFIG_HLP_USRP_THREAD "having extra thead for usrp tx\n" #define CONFIG_HLP_DISABLNBIOT "disable nb-iot, even if defined in config\n" #define CONFIG_HLP_USRP_ARGS "set the arguments to identify USRP (same syntax as in UHD)\n" @@ -143,6 +144,10 @@ extern int sync_var; extern int transmission_mode; extern double cpuf; +extern int emulate_rf; +extern int numerology; +extern int usrp_tx_thread; + extern volatile int start_eNB; extern volatile int start_UE; diff --git a/executables/nr-softmodem.c b/executables/nr-softmodem.c index f473d0161b..ada032351f 100644 --- a/executables/nr-softmodem.c +++ b/executables/nr-softmodem.c @@ -182,6 +182,7 @@ extern void init_eNB_afterRU(void); int transmission_mode=1; int emulate_rf = 0; int numerology = 0; +int usrp_tx_thread = 0; static char *parallel_config = NULL; diff --git a/executables/nr-softmodem.h b/executables/nr-softmodem.h index 27e3ba1e3e..d113ae45aa 100644 --- a/executables/nr-softmodem.h +++ b/executables/nr-softmodem.h @@ -34,6 +34,7 @@ {"emulate-rf" , CONFIG_HLP_EMULATE_RF, PARAMFLAG_BOOL, iptr:&emulate_rf, defintval:0, TYPE_INT, 0}, \ {"parallel-config", CONFIG_HLP_PARALLEL_CMD,0, strptr:(char **)¶llel_config, defstrval:NULL, TYPE_STRING, 0}, \ {"worker-config", CONFIG_HLP_WORKER_CMD, 0, strptr:(char **)&worker_config, defstrval:NULL, TYPE_STRING, 0}, \ + {"usrp-tx-thread-config", CONFIG_HLP_USRP_THREAD, 0, iptr:&usrp_tx_thread, defstrval:0, TYPE_INT, 0}, \ {"s" , CONFIG_HLP_SNR, 0, dblptr:&snr_dB, defdblval:25, TYPE_DOUBLE, 0}, \ } diff --git a/targets/ARCH/BLADERF/USERSPACE/LIB/bladerf_lib.c b/targets/ARCH/BLADERF/USERSPACE/LIB/bladerf_lib.c index c4e593ca92..af5ab5ad6d 100644 --- a/targets/ARCH/BLADERF/USERSPACE/LIB/bladerf_lib.c +++ b/targets/ARCH/BLADERF/USERSPACE/LIB/bladerf_lib.c @@ -330,7 +330,10 @@ int trx_brf_set_gains(openair0_device* device, { return(0); } - +int trx_brf_write_init(openair0_device *device) +{ + return 0; +} #define RXDCLENGTH 16384 int16_t cos_fsover8[8] = {2047, 1447, 0, -1448, -2047, -1448, 0, 1447}; @@ -1145,6 +1148,7 @@ int device_init(openair0_device *device, device->trx_stop_func = trx_brf_stop; device->trx_set_freq_func = trx_brf_set_freq; device->trx_set_gains_func = trx_brf_set_gains; + device->trx_write_init = trx_brf_write_init; device->openair0_cfg = openair0_cfg; device->priv = (void *)brf; diff --git a/targets/ARCH/ETHERNET/USERSPACE/LIB/ethernet_lib.c b/targets/ARCH/ETHERNET/USERSPACE/LIB/ethernet_lib.c index c5822a3650..c72e7d4130 100644 --- a/targets/ARCH/ETHERNET/USERSPACE/LIB/ethernet_lib.c +++ b/targets/ARCH/ETHERNET/USERSPACE/LIB/ethernet_lib.c @@ -197,6 +197,10 @@ int trx_eth_reset_stats(openair0_device* device) return(0); } +int trx_eth_write_init(openair0_device *device) +{ + return 0; +} int ethernet_tune(openair0_device *device, unsigned int option, @@ -415,8 +419,9 @@ int transport_init(openair0_device *device, device->trx_reset_stats_func = trx_eth_reset_stats; device->trx_end_func = trx_eth_end; device->trx_stop_func = trx_eth_stop; - device->trx_set_freq_func = trx_eth_set_freq; - device->trx_set_gains_func = trx_eth_set_gains; + device->trx_set_freq_func = trx_eth_set_freq; + device->trx_set_gains_func = trx_eth_set_gains; + device->trx_write_init = trx_eth_write_init; if (eth->flags == ETH_RAW_MODE) { device->trx_write_func = trx_eth_write_raw; diff --git a/targets/ARCH/IRIS/USERSPACE/LIB/iris_lib.cpp b/targets/ARCH/IRIS/USERSPACE/LIB/iris_lib.cpp index 5b20d8a8c7..1273097f3b 100644 --- a/targets/ARCH/IRIS/USERSPACE/LIB/iris_lib.cpp +++ b/targets/ARCH/IRIS/USERSPACE/LIB/iris_lib.cpp @@ -510,6 +510,11 @@ int trx_iris_reset_stats(openair0_device *device) { } +int trx_iris_write_init(openair0_device *device) +{ + return 0; +} + extern "C" { /*! \brief Initialize Openair Iris target. It returns 0 if OK @@ -831,6 +836,7 @@ int device_init(openair0_device *device, openair0_config_t *openair0_cfg) { device->trx_set_freq_func = trx_iris_set_freq; device->trx_set_gains_func = trx_iris_set_gains; device->openair0_cfg = openair0_cfg; + device->trx_write_init = trx_iris_write_init; s->sample_rate = openair0_cfg[0].sample_rate; // TODO: diff --git a/targets/ARCH/LMSSDR/USERSPACE/LIB/lms_lib.cpp b/targets/ARCH/LMSSDR/USERSPACE/LIB/lms_lib.cpp index 9fcfbdf571..79a389bfeb 100644 --- a/targets/ARCH/LMSSDR/USERSPACE/LIB/lms_lib.cpp +++ b/targets/ARCH/LMSSDR/USERSPACE/LIB/lms_lib.cpp @@ -350,6 +350,10 @@ void trx_lms_end(openair0_device *device) { } +int trx_lms_write_init(openair0_device *device) +{ + return 0; +} extern "C" { /*! \brief Initialize Openair LMSSDR target. It returns 0 if OK * \param device the hardware to use @@ -406,6 +410,7 @@ int device_init(openair0_device *device, openair0_config_t *openair0_cfg){ device->trx_stop_func = trx_lms_stop; device->trx_set_freq_func = trx_lms_set_freq; device->trx_set_gains_func = trx_lms_set_gains; + device->trx_write_init = trx_lms_write_init; device->openair0_cfg = openair0_cfg; diff --git a/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp b/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp index 08f0cd720b..62f77699a4 100644 --- a/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp +++ b/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp @@ -70,6 +70,8 @@ * @{ */ +extern int usrp_tx_thread; + typedef struct { @@ -345,7 +347,6 @@ static int trx_usrp_write(openair0_device *device, int flags_msb = (flags>>8)&0xff; int end; - int write_tread = 0; openair0_thread_t *write_thread = &device->write_thread; openair0_write_package_t *write_package = write_thread->write_package; @@ -382,7 +383,7 @@ static int trx_usrp_write(openair0_device *device, last_packet_state = true; } - if(write_tread == 0){ + if(usrp_tx_thread == 0){ #if defined(__x86_64) || defined(__i386__) #ifdef __AVX2__ nsamps2 = (nsamps+7)>>3; @@ -586,7 +587,7 @@ void *trx_usrp_write_thread(void * arg){ return NULL; } -int trx_write_init(openair0_device *device){ +int trx_usrp_write_init(openair0_device *device){ uhd::set_thread_priority_safe(1.0); openair0_thread_t *write_thread = &device->write_thread; @@ -932,7 +933,7 @@ extern "C" { device->trx_stop_func = trx_usrp_stop; device->trx_set_freq_func = trx_usrp_set_freq; device->trx_set_gains_func = trx_usrp_set_gains; - device->trx_write_init = trx_write_init; + device->trx_write_init = trx_usrp_write_init; // hotfix! to be checked later diff --git a/targets/ARCH/tcp_bridge/tcp_bridge.c b/targets/ARCH/tcp_bridge/tcp_bridge.c index 8b287acfa1..f8c12dcb7a 100644 --- a/targets/ARCH/tcp_bridge/tcp_bridge.c +++ b/targets/ARCH/tcp_bridge/tcp_bridge.c @@ -243,6 +243,11 @@ ts += nsamps; return nsamps; } +int tcp_bridge_write_init(openair0_device *device) +{ + return 0; +} + __attribute__((__visibility__("default"))) int device_init(openair0_device* device, openair0_config_t *openair0_cfg) { @@ -267,6 +272,7 @@ int device_init(openair0_device* device, openair0_config_t *openair0_cfg) device->trx_set_gains_func = tcp_bridge_set_gains; device->trx_write_func = tcp_bridge_write; device->trx_read_func = tcp_bridge_read; + device->trx_write_init = tcp_bridge_write_init; device->priv = tcp_bridge; From 5f87b73451c63e98a9ea218f860a72bb9d8f6bc8 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 12 Jun 2020 08:43:17 +0200 Subject: [PATCH 303/553] small fixes --- cmake_targets/autotests/test_case_list.xml | 5 ++--- openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c | 2 +- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/cmake_targets/autotests/test_case_list.xml b/cmake_targets/autotests/test_case_list.xml index 88c7a40351..296e8d8854 100644 --- a/cmake_targets/autotests/test_case_list.xml +++ b/cmake_targets/autotests/test_case_list.xml @@ -1205,9 +1205,8 @@ -R 106 -i 1 -P 2 -b 8 -s4 -n1000 -R 106 -i 1 -P 2 -b 9 -s5 -n1000 -R 106 -i 1 -P 2 -b 10 -s6 -n1000 - -R 106 -i 1 -P 2 -b 11 -s6 -n1000 - - nr_pucchsim.test1 nr_pucchsim.test2 nr_pucchsim.test3 nr_pucchsim.test4 nr_pucchsim.test5 nr_pucchsim.test6 nr_pucchsim.test7 nr_pucchsim.test8 nr_pucchsim.test9 nr_pucchsim.test10 nr_pucchsim.test11 nr_pucchsim.test12 + -R 106 -i 1 -P 2 -b 11 -s6 -n1000 + nr_pucchsim.test1 nr_pucchsim.test2 nr_pucchsim.test3 nr_pucchsim.test4 nr_pucchsim.test5 nr_pucchsim.test6 nr_pucchsim.test7 nr_pucchsim.test8 nr_pucchsim.test9 nr_pucchsim.test10 nr_pucchsim.test11 nr_pucchsim.test12 PUCCH test OK segmentation fault|assertion|exiting|fatal 3 diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c b/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c index 61748a8e56..b2d0467d14 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c @@ -135,7 +135,7 @@ int nr_pbch_detection(UE_nr_rxtx_proc_t * proc, PHY_VARS_NR_UE *ue, int pbch_ini stop_meas(&ue->dlsch_channel_estimation_stats); #endif - current_ssb->metric = current_ssb->c_re*current_ssb->c_re + current_ssb->c_im+current_ssb->c_re; + current_ssb->metric = current_ssb->c_re*current_ssb->c_re + current_ssb->c_im+current_ssb->c_im; // generate a list of SSB structures if (best_ssb == NULL) From cec29bb240f9512f834223760e99f19be19af836 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 12 Jun 2020 09:57:23 +0200 Subject: [PATCH 304/553] bugfix nr_initial_sync.c --- openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c b/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c index b2d0467d14..cee9a45fac 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c @@ -135,7 +135,7 @@ int nr_pbch_detection(UE_nr_rxtx_proc_t * proc, PHY_VARS_NR_UE *ue, int pbch_ini stop_meas(&ue->dlsch_channel_estimation_stats); #endif - current_ssb->metric = current_ssb->c_re*current_ssb->c_re + current_ssb->c_im+current_ssb->c_im; + current_ssb->metric = current_ssb->c_re*current_ssb->c_re + current_ssb->c_im*current_ssb->c_im; // generate a list of SSB structures if (best_ssb == NULL) From 21a775817d410b5aab985dcb1cd72e498f98dfee Mon Sep 17 00:00:00 2001 From: Florian Kaltenberger Date: Fri, 12 Jun 2020 10:41:35 +0200 Subject: [PATCH 305/553] Update RUNMODEM.md --- doc/RUNMODEM.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/RUNMODEM.md b/doc/RUNMODEM.md index 70074c65ed..7591111b4b 100644 --- a/doc/RUNMODEM.md +++ b/doc/RUNMODEM.md @@ -70,7 +70,7 @@ This setup requires an EPC, an OAI eNB and gNB, and a COTS Phone. A dedicated pa ### Launch eNB -```bash sudo ./lte-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.band7.tm1.50PRB.usrpb210.conf +```bash sudo ./lte-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.band7.tm1.50PRB.usrpb210.conf``` From 28da25f420a27990da5b200b4efcd60ebbb99e4f Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Fri, 12 Jun 2020 10:50:06 +0200 Subject: [PATCH 306/553] more dummy functions for physims --- openair1/SIMULATION/NR_PHY/dlschsim.c | 2 ++ openair1/SIMULATION/NR_PHY/pucchsim.c | 2 ++ openair1/SIMULATION/NR_PHY/ulschsim.c | 2 ++ 3 files changed, 6 insertions(+) diff --git a/openair1/SIMULATION/NR_PHY/dlschsim.c b/openair1/SIMULATION/NR_PHY/dlschsim.c index fedf9394da..dba2cdafd7 100644 --- a/openair1/SIMULATION/NR_PHY/dlschsim.c +++ b/openair1/SIMULATION/NR_PHY/dlschsim.c @@ -66,6 +66,8 @@ PHY_VARS_NR_UE *PHY_vars_UE_g[1][1] = { { NULL } }; uint16_t n_rnti = 0x1234; openair0_config_t openair0_cfg[MAX_CARDS]; +void init_downlink_harq_status(NR_DL_UE_HARQ_t *dl_harq) {} + int main(int argc, char **argv) { char c; diff --git a/openair1/SIMULATION/NR_PHY/pucchsim.c b/openair1/SIMULATION/NR_PHY/pucchsim.c index a754df4763..5c88c37e53 100644 --- a/openair1/SIMULATION/NR_PHY/pucchsim.c +++ b/openair1/SIMULATION/NR_PHY/pucchsim.c @@ -59,6 +59,8 @@ uint16_t NB_UE_INST = 1; // needed for some functions PHY_VARS_NR_UE * PHY_vars_UE_g[1][1]={{NULL}}; +void init_downlink_harq_status(NR_DL_UE_HARQ_t *dl_harq) {} + int main(int argc, char **argv) { char c; diff --git a/openair1/SIMULATION/NR_PHY/ulschsim.c b/openair1/SIMULATION/NR_PHY/ulschsim.c index de28e67653..2adad730fa 100644 --- a/openair1/SIMULATION/NR_PHY/ulschsim.c +++ b/openair1/SIMULATION/NR_PHY/ulschsim.c @@ -54,6 +54,8 @@ PHY_VARS_NR_UE *UE; RAN_CONTEXT_t RC; int32_t uplink_frequency_offset[MAX_NUM_CCs][4]; +void init_downlink_harq_status(NR_DL_UE_HARQ_t *dl_harq) {} + double cpuf; uint8_t nfapi_mode = 0; uint16_t NB_UE_INST = 1; From f46e3d4c762063d0c16699f93d89b938e0a4dc52 Mon Sep 17 00:00:00 2001 From: Florian Kaltenberger Date: Fri, 12 Jun 2020 11:13:18 +0200 Subject: [PATCH 307/553] fixing an issue with libconfig --- common/config/libconfig/config_libconfig.c | 4 ++-- openair2/GNB_APP/gnb_config.c | 5 ----- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/common/config/libconfig/config_libconfig.c b/common/config/libconfig/config_libconfig.c index 2d861f2dc3..b510ca28bc 100644 --- a/common/config/libconfig/config_libconfig.c +++ b/common/config/libconfig/config_libconfig.c @@ -179,8 +179,8 @@ int config_libconfig_get(paramdef_t *cfgoptions,int numoptions, char *prefix ) { *(cfgoptions[i].u64ptr) = (uint64_t)llu; printf_params("[LIBCONFIG] %s: %llu\n", cfgpath,(long long unsigned)(*(cfgoptions[i].u64ptr)) ); } else { - *(cfgoptions[i].iptr) = llu; - printf_params("[LIBCONFIG] %s: %llu\n", cfgpath,(long long unsigned)(*(cfgoptions[i].i64ptr)) ); + *(cfgoptions[i].i64ptr) = llu; + printf_params("[LIBCONFIG] %s: %llu\n", cfgpath,(long long)(*(cfgoptions[i].i64ptr)) ); } } else { defval=config_setdefault_int64(&(cfgoptions[i]),prefix); diff --git a/openair2/GNB_APP/gnb_config.c b/openair2/GNB_APP/gnb_config.c index 3235dabb45..61aa10e47b 100644 --- a/openair2/GNB_APP/gnb_config.c +++ b/openair2/GNB_APP/gnb_config.c @@ -259,11 +259,6 @@ void fix_scc(NR_ServingCellConfigCommon_t *scc,uint64_t ssbmap) { if (*scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder!=0) scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder = NULL; - // fix libconfig (asn1c uses long) - scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.preambleReceivedTargetPower-=((long)1<<32); - *scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->p0_NominalWithGrant-=((long)1<<32); - *scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->p0_nominal-=((long)1<<32); - // fix DL and UL Allocation lists for (int i=scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count-1;i>=0;i--) { From 9be3e9f451ad9e88bbe2be5e4845c2bca21eb4f5 Mon Sep 17 00:00:00 2001 From: hardy Date: Thu, 11 Jun 2020 14:24:12 +0200 Subject: [PATCH 308/553] 4G scheduler update --- doc/FEATURE_SET.md | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/doc/FEATURE_SET.md b/doc/FEATURE_SET.md index f71b9acb33..adf85fc328 100644 --- a/doc/FEATURE_SET.md +++ b/doc/FEATURE_SET.md @@ -82,7 +82,11 @@ TDD UL: 20 MHz, 100 PRBS/ MCS **XX** | 3.0 Mbit/s | TM1: 4.21 Mbits/s The MAC layer implements a subset of the **3GPP 36.321** release v8.6 in support of BCH, DLSCH, RACH, and ULSCH channels. - RRC interface for CCCH, DCCH, and DTCH -- Proportional fair scheduler (round robin scheduler soon) +- Proportional fair scheduler (round robin scheduler soon), with the following improvements: + - Up to 30 users tested in the L2 simulator, CCE allocation in the preprocessor ; the scheduler was also simplified and made more modular + - Adaptative UL-HARQ + - Should remove out-of-sync UEs (to be clarified) + - No use of the `first_rb` in the UL scheduler ; respects `vrb_map_UL` and `vrb_map` in the DL - DCI generation - HARQ Support - RA procedures and RNTI management From e40835f96d8f690a0e7ed3acb52552cc1f5c8acf Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Thu, 11 Jun 2020 14:43:34 +0200 Subject: [PATCH 309/553] Update: eNB RRC version eNB X2AP section --- doc/FEATURE_SET.md | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/doc/FEATURE_SET.md b/doc/FEATURE_SET.md index adf85fc328..37e462979b 100644 --- a/doc/FEATURE_SET.md +++ b/doc/FEATURE_SET.md @@ -127,7 +127,7 @@ The current PDCP layer is header compliant with **3GPP 36.323** Rel 10.1.0 and i ## eNB RRC Layer ## -The RRC layer is based on **3GPP 36.331** v14.3.0 and implements the following functions: +The RRC layer is based on **3GPP 36.331** v15.6 and implements the following functions: - System Information broadcast (SIB 1, 2, 3, and 13) * SIB1: Up to 6 PLMN IDs broadcast @@ -154,6 +154,10 @@ The X2AP layer is based on **3GPP 36.423** v14.6.0 and implements the following - X2 timers (t_reloc_prep, tx2_reloc_overall) - Handover Cancel - X2-U interface implemented + - EN-DC is implemented + - X2AP : Handling of SgNB Addition Request / Addition Request Acknowledge / Reconfiguration Complete + - RRC : Handling of RRC Connection Reconfiguration with 5G cell info, configuration of 5G-NR measurements + - S1AP : Handling of E-RAB Modification Indication / Confirmation ## eNB/MCE M2AP ## @@ -175,9 +179,6 @@ The M3AP layer is based on **3GPP 36.444** v14.0.1: - M3 Session Start Request - M3 Session Start Response -## eNB Advanced Features ## - -**To be completed** # OpenAirInterface UE Feature Set # From 981d35a778d5ac30835926c9cb66101b6f25cf42 Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Thu, 11 Jun 2020 16:29:06 +0200 Subject: [PATCH 310/553] restructuring the 5G part update of the 5G feature set (gNB and UE) ref : Florian K ppt --- doc/FEATURE_SET.md | 162 ++++++++++++++++++++++++++++++--------------- 1 file changed, 108 insertions(+), 54 deletions(-) diff --git a/doc/FEATURE_SET.md b/doc/FEATURE_SET.md index 37e462979b..a539b030e4 100644 --- a/doc/FEATURE_SET.md +++ b/doc/FEATURE_SET.md @@ -1,6 +1,8 @@ **Table of Contents** -1. [OpenAirInterface eNB Feature Set](#openairinterface-enb-feature-set) +1. [Functional Split Architecture](#functional-split-architecture) +2. [OpenAirInterface Block Diagram](#openairinterface-block-diagram) +2. [OpenAirInterface 4G-LTE eNB Feature Set](#openairinterface-4g-lte-enb-feature-set) 1. [eNB PHY Layer](#enb-phy-layer) 2. [eNB MAC Layer](#enb-mac-layer) 3. [eNB RLC Layer](#enb-rlc-layer) @@ -9,29 +11,38 @@ 6. [eNB X2AP](#enb-x2ap) 7. [eNB/MCE M2AP](#enbmce-m2ap) 8. [MCE/MME M3AP](#mcemme-m3ap) - 9. [eNB Advanced Features](#enb-advanced-features) -2. [OpenAirInterface Functional Split](#openairinterface-functional-split) -3. [OpenAirInterface UE Feature Set](#openairinterface-ue-feature-set) +3. [OpenAirInterface 4G-LTE UE Feature Set](#openairinterface-4g-lte-ue-feature-set) 1. [LTE UE PHY Layer](#lte-ue-phy-layer) 2. [LTE UE MAC Layer](#lte-ue-mac-layer) 3. [LTE UE RLC Layer](#lte-ue-rlc-layer) 4. [LTE UE PDCP Layer](#lte-ue-pdcp-layer) 5. [LTE UE RRC Layer](#lte-ue-rrc-layer) -4. [OpenAirInterface Functional Split](#openairinterface-functional-split) -5. [OpenAirInterface 5G-NR Feature Set](#openairinterface-5g-nr-feature-set) +4. [OpenAirInterface 5G-NR gNB Feature Set](#openairinterface-5g-nr-feature-set) 1. [General Parameters](#general-parameters) - 2. [gNB Features](#gnb-features) - 1. [gNB Physical Layer](#gnb-phy-layer) - 2. [gNB Higher Layers](#gnb-higher-layers) - 3. [NR UE Features](#nr-ue-features) - 1. [NR UE Physical Layer](#nr-ue-phy-layer) - 2. [NR UE Higher Layers](#nr-ue-higher-layers) + 2. [gNB Physical Layer](#gnb-phy-layer) + 3. [gNB Higher Layers](#gnb-higher-layers) +5. [OpenAirInterface 5G-NR UE Feature Set](#openairinterface-5g-nr-ue-feature-set) + 1. [UE Physical Layer](#ue-phy-layer) + 2. [UE Higher Layers](#ue-higher-layers) -# OpenAirInterface Block diagram # + +# Functional Split Architecture # + +- RCC: Radio-Cloud Center +- RAU: Radio-Access Unit +- RRU: Remote Radio-Unit +- IF4.5 / IF5 : similar to IEEE P1914.1 +- FAPI (IF2) : specified by Small Cell Forum (open-nFAPI implementation) +- IF1 : F1 in 3GPP Release 15 + +![Functional Split Architecture](./oai_enb_func_split_arch.png) + + +# OpenAirInterface Block Diagram # ![Block Diagram](./oai_enb_block_diagram.png) -# OpenAirInterface eNB Feature Set # +# OpenAirInterface 4G LTE eNB Feature Set # ## eNB PHY Layer ## @@ -85,7 +96,7 @@ The MAC layer implements a subset of the **3GPP 36.321** release v8.6 in support - Proportional fair scheduler (round robin scheduler soon), with the following improvements: - Up to 30 users tested in the L2 simulator, CCE allocation in the preprocessor ; the scheduler was also simplified and made more modular - Adaptative UL-HARQ - - Should remove out-of-sync UEs (to be clarified) + - Remove out-of-sync UEs - No use of the `first_rb` in the UL scheduler ; respects `vrb_map_UL` and `vrb_map` in the DL - DCI generation - HARQ Support @@ -180,7 +191,7 @@ The M3AP layer is based on **3GPP 36.444** v14.0.1: - M3 Session Start Response -# OpenAirInterface UE Feature Set # +# OpenAirInterface 4G LTE UE Feature Set # ## LTE UE PHY Layer ## @@ -235,17 +246,6 @@ The NAS layer is based on **3GPP 24.301** and implements the following functions - EMM attach/detach, authentication, tracking area update, and more - ESM default/dedicated bearer, PDN connectivity, and more -# OpenAirInterface Functional Split # - -- RCC: Radio-Cloud Center -- RAU: Radio-Access Unit -- RRU: Remote Radio-Unit - -![Functional Split Architecture](./oai_enb_func_split_arch.png) - -- IF4.5 / IF5 : similar to IEEE P1914.1 -- FAPI (IF2) : specified by Small Cell Forum (open-nFAPI implementation) -- IF1 : F1 in 3GPP Release 15 # OpenAirInterface 5G-NR Feature Set # @@ -263,49 +263,103 @@ The following features are valid for the gNB and the 5G-NR UE. * Highly efficient 3GPP compliant polar encoder and decoder * Encoder and decoder for short blocks -## gNB Features ## -### gNB PHY Layer ### +## gNB PHY Layer ## -* Generation of PSS/SSS/PBCH for multiple beams and -* Generation of PDCCH for SIB1 (including generation of DCI, polar encoding, scrambling, modulation, RB mapping, etc) +* 30KHz SCS for FR1 and 120 KHz SCS for FR2 +* Generation of NR-PSS/NR-SSS +* NR-PBCH supports multiple SSBs and flexible periodicity +* Generation of NR-PDCCH for SIB1 (including generation of DCI, polar encoding, scrambling, modulation, RB mapping, etc) - common search space configured by MIB - user-specific search space configured by RRC - - DCI formats: 00, 10 -* Generation of PDSCH (including Segmentation, LDPC encoding, rate matching, scrambling, modulation, RB mapping, etc). - - Single symbol DMRS, dmrs-TypeA-Position Pos2, DMRS configuration type 1 - - PDSCH mapping type A + - DCI formats: 00, 10 (01 and 11 **under integration**) +* Generation of NR-PDSCH (including Segmentation, LDPC encoding, rate matching, scrambling, modulation, RB mapping, etc). + - Single symbol DMRS, DMRS-TypeA-Position Pos2, DMRS configuration type 1 + - PDSCH mapping type A +* NR-CSI Generation of sequence at PHY (**under integration**) * NR-PUSCH (including Segmentation, LDPC encoding, rate matching, scrambling, modulation, RB mapping, etc). * NR-PUCCH - - Format 0 (ACK/NACK) + - Format 0 (2 bits, mainly for ACK/NACK) + - Format 2 (up to 64 bits, mainly for CSI feedback) +* NR-PRACH + - Formats 0,1,2,3, A1-A3, B1-B3 +* Highly efficient 3GPP compliant LDPC encoder and decoder (BG1 and BG2 are supported) +* Highly efficient 3GPP compliant polar encoder and decoder +* Encoder and decoder for short block -### gNB higher Layers ### - +## gNB Higher Layers ## + +**gNB RRC** - NR RRC (38.331) Rel 15 messages using new asn1c - LTE RRC (36.331) also updated to Rel 15 -- Generation of MIB +- Generation of CellGroupConfig (for eNB) and MIB - Application to read configuration file and program gNB RRC -- RRC -> MAC configuration -- MAC -> PHY configuration (using NR FAPI P5 interface) -- FAPI P7 interface for BCH PDU, DCI PDU, PDSCH PDU +- RRC can configure PDCP, RLC, MAC -For more details see [this document](https://gitlab.eurecom.fr/oai/openairinterface5g/uploads/ba5368448d627743a28c770c29e8978e/OAI_Software_Architecture_for_Dual_Connectivity_in_E-UTRA_and_5G-NR_and_nFAPI_for_MAC-PHY_Interface.docx) +**gNB X2AP** +- X2 setup with eNB +- Handling of SgNB Addition Request / Addition Request Acknowledge / Reconfiguration Complete -## NR UE Features ## +**gNB MAC** +- MAC -> PHY configuration using NR FAPI P5 interface +- MAC <-> PHY data interface using FAPI P7 interface for BCH PDU, DCI PDU, PDSCH PDU +- Scheduler for RA procedreat gNB +- MAC downlink scheduler (fixed allocations) +- MAC header generation (including timing advance) +- ACK / NACK handling and HARQ procedures for downlink +- **As of May 2020** only DL was validated with COTS phone ; UL in progress, validated with OAI UE in noS1 mode -### NR UE PHY Layer ### -- initial synchronization -- Time tracking based on PDCCH DMRS -- Frequency offset estimation -- PBCH RX -- PDCCH RX -- PDSCH RX - - including first version of dual stream receiver for PDSCH +# OpenAirInterface 5G-NR UE Feature Set # + +**as of May 2020** only supporting "noS1" mode (DL): +- Creates TUN interface to PDCP to inject and receive user-place traffic +- Will only work with OAI gNB configured in the same mode + +## UE PHY Layer ## + +* Initial synchronization +* Time tracking based on PBCH DMRS +* Time tracking based on PBCH DMRS +* Frequency offset estimation +* PBCH RX +* PDCCH RX +* PDSCH RX, including a first version of dual stream receiver for PDSCH +* 30KHz SCS for FR1 and 120 KHz SCS for FR2 +* Generation of NR-PSS/NR-SSS +* NR-PBCH supports multiple SSBs and flexible periodicity +* Generation of NR-PDCCH for SIB1 (including generation of DCI, polar encoding, scrambling, modulation, RB mapping, etc) + - common search space configured by MIB + - user-specific search space configured by RRC + - DCI formats: 00, 10 (01 and 11 **under integration**) +* Generation of NR-PDSCH (including Segmentation, LDPC encoding, rate matching, scrambling, modulation, RB mapping, etc). + - Single symbol DMRS, DMRS-TypeA-Position Pos2, DMRS configuration type 1 + - PDSCH mapping type A +* NR-CSI Generation of sequence at PHY (**under integration**) +* NR-PUSCH (including Segmentation, LDPC encoding, rate matching, scrambling, modulation, RB mapping, etc). +* NR-PUCCH + - Format 0 (2 bits, mainly for ACK/NACK) + - Format 2 (up to 64 bits, mainly for CSI feedback) +* NR-PRACH + - Formats 0,1,2,3, A1-A3, B1-B3 +* Highly efficient 3GPP compliant LDPC encoder and decoder (BG1 and BG2 are supported) +* Highly efficient 3GPP compliant polar encoder and decoder +* Encoder and decoder for short block + + +## UE Higher Layers ## + +**gNB MAC** +- Initial sync and MIB detection +- MAC -> PHY configuration of PHY via UE FAPI P5 interface +- Basic MAC to control PHY via UE FAPI P7 interface +- Random ccess procedure + +**RLC** + +**PDCP** -### NR UE higher Layers ### -For more details see [this document](https://gitlab.eurecom.fr/oai/openairinterface5g/uploads/f7386f3a64806fd6b2ac1fc3d0252fff/UE_FAPI-like_interface.docx) [OAI wiki home](https://gitlab.eurecom.fr/oai/openairinterface5g/wikis/home) From b9f9d69bfdf6bd286d224ee546001bff9a3821c2 Mon Sep 17 00:00:00 2001 From: Florian Kaltenberger Date: Fri, 12 Jun 2020 11:31:00 +0200 Subject: [PATCH 311/553] doc update --- doc/FEATURE_SET.md | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/doc/FEATURE_SET.md b/doc/FEATURE_SET.md index a539b030e4..1e55147163 100644 --- a/doc/FEATURE_SET.md +++ b/doc/FEATURE_SET.md @@ -303,11 +303,9 @@ The following features are valid for the gNB and the 5G-NR UE. **gNB MAC** - MAC -> PHY configuration using NR FAPI P5 interface - MAC <-> PHY data interface using FAPI P7 interface for BCH PDU, DCI PDU, PDSCH PDU -- Scheduler for RA procedreat gNB +- Scheduler for RA procedure at gNB - MAC downlink scheduler (fixed allocations) - MAC header generation (including timing advance) -- ACK / NACK handling and HARQ procedures for downlink -- **As of May 2020** only DL was validated with COTS phone ; UL in progress, validated with OAI UE in noS1 mode # OpenAirInterface 5G-NR UE Feature Set # @@ -353,7 +351,7 @@ The following features are valid for the gNB and the 5G-NR UE. - Initial sync and MIB detection - MAC -> PHY configuration of PHY via UE FAPI P5 interface - Basic MAC to control PHY via UE FAPI P7 interface -- Random ccess procedure +- Random access procedure **RLC** From 186dde707333048944c6550a4d58a755b77fc3a6 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Fri, 12 Jun 2020 14:07:15 +0200 Subject: [PATCH 312/553] changes to dlsim --- openair1/SIMULATION/NR_PHY/dlsim.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/openair1/SIMULATION/NR_PHY/dlsim.c b/openair1/SIMULATION/NR_PHY/dlsim.c index 69337761e4..2e075acfb3 100644 --- a/openair1/SIMULATION/NR_PHY/dlsim.c +++ b/openair1/SIMULATION/NR_PHY/dlsim.c @@ -211,7 +211,7 @@ int main(int argc, char **argv) FILE *scg_fd=NULL; - while ((c = getopt (argc, argv, "f:hA:pf:g:i:j:n:s:S:t:x:y:z:M:N:F:GR:dPIL:Ea:b:e:m:")) != -1) { + while ((c = getopt (argc, argv, "f:hA:pf:g:i:j:n:s:S:t:x:y:z:M:N:F:GR:dPIL:Ea:b:e:m:w")) != -1) { switch (c) { case 'f': scg_fd = fopen(optarg,"r"); @@ -394,6 +394,10 @@ int main(int argc, char **argv) eff_tp_check = (float)atoi(optarg)/100; break; + case 'w': + output_fd = fopen("txdata.dat", "w+"); + break; + default: case 'h': printf("%s -h(elp) -p(extended_prefix) -N cell_id -f output_filename -F input_filename -g channel_model -n n_frames -t Delayspread -s snr0 -S snr1 -x transmission_mode -y TXant -z RXant -i Intefrence0 -j Interference1 -A interpolation_file -C(alibration offset dB) -N CellId\n", @@ -425,6 +429,7 @@ int main(int argc, char **argv) printf("-e MSC index\n"); printf("-t Acceptable effective throughput (in percentage)\n"); printf("-P Print DLSCH performances\n"); + printf("-w Write txdata to binary file (one frame)\n"); exit (-1); break; } @@ -735,7 +740,7 @@ int main(int argc, char **argv) NR_DL_UE_HARQ_t *UE_harq_process = dlsch0->harq_processes[harq_pid]; NR_gNB_DLSCH_t *gNB_dlsch = gNB->dlsch[0][0]; - nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &gNB_dlsch->harq_processes[0]->pdsch_pdu.pdsch_pdu_rel15; + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &gNB_dlsch->harq_processes[slot]->pdsch_pdu.pdsch_pdu_rel15; UE_harq_process->harq_ack.ack = 0; round = 0; @@ -802,8 +807,10 @@ int main(int argc, char **argv) if (gNB->frame_parms.nb_antennas_tx>1) LOG_M("txsig1.m","txs1", txdata[1],frame_length_complex_samples,1,1); } - if (output_fd) + if (output_fd) { + printf("writing txdata to binary file\n"); fwrite(txdata[0],sizeof(int32_t),frame_length_complex_samples,output_fd); + } int txlev = signal_energy(&txdata[0][frame_parms->get_samples_slot_timestamp(slot,frame_parms,0)+5*frame_parms->ofdm_symbol_size + 4*frame_parms->nb_prefix_samples + frame_parms->nb_prefix_samples0], frame_parms->ofdm_symbol_size + frame_parms->nb_prefix_samples); From 1552be348c357dc9014528902660c81fd0f4c395 Mon Sep 17 00:00:00 2001 From: matzakos Date: Fri, 12 Jun 2020 14:33:08 +0200 Subject: [PATCH 313/553] Fix ULSCH slot scheduling inconsistency between nrUE and gNB --- openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c | 3 +++ openair1/SCHED_NR_UE/fapi_nr_ue_l1.c | 1 + openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 4 +++- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 2 +- 4 files changed, 8 insertions(+), 2 deletions(-) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c index 49ba3a83b2..9be4a16fb5 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c @@ -466,6 +466,9 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, } //} + NR_UL_UE_HARQ_t *harq_process_ulsch=NULL; + harq_process_ulsch = UE->ulsch[thread_id][gNB_id][0]->harq_processes[harq_pid]; + harq_process_ulsch->status = SCH_IDLE; /////////// //////////////////////////////////////////////////////////////////////// diff --git a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c index 4d297f6461..6d4e995701 100644 --- a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c +++ b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c @@ -144,6 +144,7 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ memcpy(pusch_pdu, pusch_config_pdu, sizeof(nfapi_nr_ue_pusch_pdu_t)); ulsch0->f_pusch = pusch_config_pdu->absolute_delta_PUSCH; + ulsch0->harq_processes[current_harq_pid]->status = ACTIVE; break; case (FAPI_NR_UL_CONFIG_TYPE_PUCCH): diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 98aac92786..caf644932a 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -2233,7 +2233,9 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, #endif if (ue->UE_mode[gNB_id] == PUSCH || get_softmodem_params()->phy_test == 1){ - nr_ue_ulsch_procedures(ue, harq_pid, frame_tx, slot_tx, thread_id, gNB_id); + if (ue->ulsch[thread_id][gNB_id][0]->harq_processes[harq_pid]->status == ACTIVE) + nr_ue_ulsch_procedures(ue, harq_pid, frame_tx, slot_tx, thread_id, gNB_id); + /* if (ue->UE_mode[eNB_id] == PUSCH) { diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 2ccd1f369b..53ef0f62a3 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -755,7 +755,7 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in } */ } - } else if (ul_info) { + } else if (ul_info && ul_info->slot_tx == 8) { module_id_t mod_id = ul_info->module_id; uint32_t gNB_index = ul_info->gNB_index; int cc_id = ul_info->cc_id; From 702192148ef8a9ccd3c53df839afef1e1b5459ea Mon Sep 17 00:00:00 2001 From: WANG Tsu-Han Date: Fri, 12 Jun 2020 14:42:51 +0200 Subject: [PATCH 314/553] fixes for PARALLEL_RU_L1_TRX_SPLIT from Laurent --- openair1/PHY/LTE_TRANSPORT/dlsch_coding.c | 2 +- targets/RT/USER/lte-softmodem.c | 2 ++ targets/RT/USER/lte-softmodem.h | 4 ++++ 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c b/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c index 15eb5206a1..14036ad43a 100644 --- a/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c +++ b/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c @@ -422,6 +422,6 @@ int dlsch_encoding(PHY_VARS_eNB *eNB, else r_offset += Nl*Qm * ((GpmodC==0?0:1) + (Gp/C)); } - + VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING, VCD_FUNCTION_OUT); return(0); } diff --git a/targets/RT/USER/lte-softmodem.c b/targets/RT/USER/lte-softmodem.c index d8c5e25593..4715a4e995 100644 --- a/targets/RT/USER/lte-softmodem.c +++ b/targets/RT/USER/lte-softmodem.c @@ -170,6 +170,7 @@ extern void init_eNB_afterRU(void); int transmission_mode=1; int emulate_rf = 0; int numerology = 0; +int usrp_tx_thread = 0; THREAD_STRUCT thread_struct; /* struct for ethernet specific parameters given in eNB conf file */ @@ -659,6 +660,7 @@ int main ( int argc, char **argv ) initTpool("n", L1proc->threadPool, true); initNotifiedFIFO(L1proc->respEncode); initNotifiedFIFO(L1proc->respDecode); + RC.eNB[x][CC_id]->proc.L1_proc_tx.threadPool = L1proc->threadPool; } diff --git a/targets/RT/USER/lte-softmodem.h b/targets/RT/USER/lte-softmodem.h index c5fdb5f546..1c537dabe3 100644 --- a/targets/RT/USER/lte-softmodem.h +++ b/targets/RT/USER/lte-softmodem.h @@ -155,6 +155,10 @@ extern int sync_var; extern int transmission_mode; extern double cpuf; +extern int emulate_rf; +extern int numerology; +extern int usrp_tx_thread; + // In lte-enb.c extern void stop_eNB(int); extern void kill_eNB_proc(int inst); From 928c189ef08a4a750976553727e339bf552588b2 Mon Sep 17 00:00:00 2001 From: matzakos Date: Fri, 12 Jun 2020 14:44:52 +0200 Subject: [PATCH 315/553] Modify starting LCID for DTCH to start from 4 instead of 3 for both UL and DL - Make required adaptations in RLC and default DRB configuration --- openair2/LAYER2/NR_MAC_COMMON/nr_mac.h | 2 +- openair2/LAYER2/PDCP_v10.1.0/pdcp.c | 2 +- openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c | 26 +++++++++++----------- openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h | 2 +- 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h index 04b213b0d2..20b4c85dc6 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h @@ -176,7 +176,7 @@ typedef struct { #define DL_SCH_LCID_CCCH 0x00 #define DL_SCH_LCID_DCCH 0x01 #define DL_SCH_LCID_DCCH1 0x02 -#define DL_SCH_LCID_DTCH 0x03 +#define DL_SCH_LCID_DTCH 0x04 #define DL_SCH_LCID_RECOMMENDED_BITRATE 0x2F #define DL_SCH_LCID_SP_ZP_CSI_RS_RES_SET_ACT 0x30 #define DL_SCH_LCID_PUCCH_SPATIAL_RELATION_ACT 0x31 diff --git a/openair2/LAYER2/PDCP_v10.1.0/pdcp.c b/openair2/LAYER2/PDCP_v10.1.0/pdcp.c index b0e6143de1..617cb4d313 100644 --- a/openair2/LAYER2/PDCP_v10.1.0/pdcp.c +++ b/openair2/LAYER2/PDCP_v10.1.0/pdcp.c @@ -2390,7 +2390,7 @@ void nr_ip_over_LTE_DRB_preconfiguration(void){ // 1 + drb_identiy_index; DRB_config->drb_Identity = 1; DRB_config->logicalChannelIdentity = CALLOC(1, sizeof(long)); - *(DRB_config->logicalChannelIdentity) = DRB_config->drb_Identity + 2; //(long) (ue_context_pP->ue_context.e_rab[i].param.e_rab_id + 2); // value : x+2 + *(DRB_config->logicalChannelIdentity) = DRB_config->drb_Identity + 3; //(long) (ue_context_pP->ue_context.e_rab[i].param.e_rab_id + 2); // value : x+2 DRB_rlc_config = CALLOC(1, sizeof(*DRB_rlc_config)); DRB_config->rlc_Config = DRB_rlc_config; diff --git a/openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c b/openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c index ff0d446e3f..38ad658015 100644 --- a/openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c +++ b/openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c @@ -72,8 +72,8 @@ void mac_rlc_data_ind ( LOG_I(RLC, "RLC instance for the given UE was not found \n"); switch (channel_idP) { - case 1 ... 2: rb = ue->srb[channel_idP - 1]; break; - case 3 ... 7: rb = ue->drb[channel_idP - 3]; break; + case 1 ... 3: rb = ue->srb[channel_idP - 1]; break; + case 4 ... 7: rb = ue->drb[channel_idP - 4]; break; default: rb = NULL; break; } @@ -113,8 +113,8 @@ tbs_size_t mac_rlc_data_req( ue = nr_rlc_manager_get_ue(nr_rlc_ue_manager, rntiP); switch (channel_idP) { - case 1 ... 2: rb = ue->srb[channel_idP - 1]; break; - case 3 ... 7: rb = ue->drb[channel_idP - 3]; break; + case 1 ... 3: rb = ue->srb[channel_idP - 1]; break; + case 4 ... 7: rb = ue->drb[channel_idP - 4]; break; default: rb = NULL; break; } @@ -123,7 +123,7 @@ tbs_size_t mac_rlc_data_req( maxsize = tb_sizeP; ret = rb->generate_pdu(rb, buffer_pP, maxsize); } else { - LOG_E(RLC, "%s:%d:%s: fatal: data req for unknown RB\n", __FILE__, __LINE__, __FUNCTION__); + LOG_E(RLC, "%s:%d:%s: fatal: data req for unknown RB, channel_idP: %d\n", __FILE__, __LINE__, __FUNCTION__, channel_idP); exit(1); ret = 0; } @@ -166,8 +166,8 @@ mac_rlc_status_resp_t mac_rlc_status_ind( ue = nr_rlc_manager_get_ue(nr_rlc_ue_manager, rntiP); switch (channel_idP) { - case 1 ... 2: rb = ue->srb[channel_idP - 1]; break; - case 3 ... 7: rb = ue->drb[channel_idP - 3]; break; + case 1 ... 3: rb = ue->srb[channel_idP - 1]; break; + case 4 ... 7: rb = ue->drb[channel_idP - 4]; break; default: rb = NULL; break; } @@ -227,8 +227,8 @@ rlc_buffer_occupancy_t mac_rlc_get_buffer_occupancy_ind( ue = nr_rlc_manager_get_ue(nr_rlc_ue_manager, rntiP); switch (channel_idP) { - case 1 ... 2: rb = ue->srb[channel_idP - 1]; break; - case 3 ... 7: rb = ue->drb[channel_idP - 3]; break; + case 1 ... 3: rb = ue->srb[channel_idP - 1]; break; + case 4 ... 7: rb = ue->drb[channel_idP - 4]; break; default: rb = NULL; break; } @@ -654,11 +654,11 @@ static void add_drb_am(int rnti, struct LTE_DRB_ToAddMod *s) exit(1); } - if (channel_id != drb_id + 2) { + /*if (channel_id != drb_id + 2) { LOG_E(RLC, "%s:%d:%s: todo, remove this limitation\n", __FILE__, __LINE__, __FUNCTION__); exit(1); - } + }*/ logical_channel_group = *l->ul_SpecificParameters->logicalChannelGroup; @@ -737,11 +737,11 @@ static void add_drb_um(int rnti, struct LTE_DRB_ToAddMod *s) exit(1); } - if (channel_id != drb_id + 2) { + /*if (channel_id != drb_id + 2) { LOG_E(RLC, "%s:%d:%s: todo, remove this limitation\n", __FILE__, __LINE__, __FUNCTION__); exit(1); - } + }*/ logical_channel_group = *l->ul_SpecificParameters->logicalChannelGroup; diff --git a/openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h b/openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h index 464cf3d083..f578faaf38 100644 --- a/openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h +++ b/openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h @@ -28,7 +28,7 @@ typedef void nr_rlc_ue_manager_t; typedef struct nr_rlc_ue_t { int rnti; - nr_rlc_entity_t *srb[2]; + nr_rlc_entity_t *srb[3]; nr_rlc_entity_t *drb[5]; } nr_rlc_ue_t; From 89bb495799842c9c4c09bac665d11b8e717a33b6 Mon Sep 17 00:00:00 2001 From: WANG Tsu-Han Date: Fri, 12 Jun 2020 15:18:43 +0200 Subject: [PATCH 316/553] fixes for emulate-rf in lte-softmodem --- targets/RT/USER/lte-ru.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/targets/RT/USER/lte-ru.c b/targets/RT/USER/lte-ru.c index d2e734f205..3124c7a232 100644 --- a/targets/RT/USER/lte-ru.c +++ b/targets/RT/USER/lte-ru.c @@ -679,7 +679,11 @@ void rx_rf(RU_t *ru, resynch=1; } - proc->timestamp_rx = ts-ru->ts_offset; + if(get_softmodem_params()->emulate_rf) { + proc->timestamp_rx = old_ts + fp->samples_per_tti; + } else { + proc->timestamp_rx = ts-ru->ts_offset; + } // AssertFatal(rxs == fp->samples_per_tti, // "rx_rf: Asked for %d samples, got %d from SDR\n",fp->samples_per_tti,rxs); @@ -2337,7 +2341,7 @@ void init_RU_proc(RU_t *ru) { LOG_I(PHY,"%s() DJP - added creation of pthread_prach\n", __FUNCTION__); pthread_create( &proc->pthread_prach, attr_prach, ru_thread_prach, (void *)ru ); ru->state=RU_RUN; - fill_rf_config(ru,ru->rf_config_file); + /*fill_rf_config(ru,ru->rf_config_file); init_frame_parms(ru->frame_parms,1); ru->frame_parms->nb_antennas_rx = ru->nb_rx; phy_init_RU(ru); @@ -2350,7 +2354,7 @@ void init_RU_proc(RU_t *ru) { if (setup_RU_buffers(ru)!=0) { LOG_I(PHY,"Exiting, cannot initialize RU Buffers\n"); exit(1); - } + }*/ } if (get_thread_worker_conf() == WORKER_ENABLE) { From 860d4069748a69eb4859d943e5b61d1e5407c36c Mon Sep 17 00:00:00 2001 From: WANG Tsu-Han Date: Fri, 12 Jun 2020 15:58:56 +0200 Subject: [PATCH 317/553] debug print remove --- executables/nr-ru.c | 1 - 1 file changed, 1 deletion(-) diff --git a/executables/nr-ru.c b/executables/nr-ru.c index 69155c18d4..7d0090d59b 100644 --- a/executables/nr-ru.c +++ b/executables/nr-ru.c @@ -1467,7 +1467,6 @@ void *ru_thread( void *param ) { // start trx write thread if(usrp_tx_thread == 1){ -printf("~~~~~~~~~~~testing if the command is get\n"); if (ru->start_write_thread){ if(ru->start_write_thread(ru) != 0){ LOG_E(HW,"Could not start tx write thread\n"); From 14a0b772f3b0768befac4ca0156f174e120c2a0f Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Sat, 13 Jun 2020 11:48:50 +0200 Subject: [PATCH 318/553] fix for 36864 size dfts (missing initialization) --- openair1/PHY/NR_TRANSPORT/nr_prach.c | 4 ++-- openair1/PHY/NR_UE_TRANSPORT/nr_prach.c | 2 +- openair1/PHY/TOOLS/oai_dfts.c | 3 ++- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index 2f874c7602..0ade2993a9 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -800,7 +800,7 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, if (LOG_DUMPFLAG(PRACH)) { int en = dB_fixed(signal_energy((int32_t*)&rxsigF[0][0],840)); - if (en>60) { + // if (en>60) { int k = (12*n_ra_prb) - 6*fp->N_RB_UL; if (k<0) k+=fp->ofdm_symbol_size; @@ -814,7 +814,7 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, LOG_M("prach_rxF_comp0.m","prach_rxF_comp0",prachF,1024,1,1); LOG_M("Xu.m","xu",Xu,N_ZC,1,1); LOG_M("prach_ifft0.m","prach_t0",prach_ifft,1024,1,1); - } + // } } /* LOG_DUMPFLAG(PRACH) */ stop_meas(&gNB->rx_prach); diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c index 214ebd9716..b98aa9050d 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c @@ -44,7 +44,7 @@ #include "T.h" #include -#define NR_PRACH_DEBUG 1 +//#define NR_PRACH_DEBUG 1 extern uint16_t NCS_unrestricted_delta_f_RA_125[16]; extern uint16_t NCS_restricted_TypeA_delta_f_RA_125[15]; diff --git a/openair1/PHY/TOOLS/oai_dfts.c b/openair1/PHY/TOOLS/oai_dfts.c index 7d3cf0d2c0..25244eeff5 100644 --- a/openair1/PHY/TOOLS/oai_dfts.c +++ b/openair1/PHY/TOOLS/oai_dfts.c @@ -9607,6 +9607,7 @@ int dfts_autoinit(void) init_rad3(12288,twa12288,twb12288); init_rad3(18432,twa18432,twb18432); init_rad3(24576,twa24576,twb24576); + init_rad3(36864,twa36864,twb36864); init_rad3(49152,twa49152,twb49152); init_rad3(98304,twa98304,twb98304); @@ -10588,7 +10589,7 @@ int main(int argc, char**argv) reset_meas(&ts); for (i=0; i<10000; i++) { start_meas(&ts); - idft36864((int16_t *)x,(int16_t *)y,1); + dft36864((int16_t *)x,(int16_t *)y,1); stop_meas(&ts); } From f9b49d1a249057fd9f4189b9677f0ee40cba8d93 Mon Sep 17 00:00:00 2001 From: "vr.devendra" Date: Fri, 22 May 2020 20:15:12 +0530 Subject: [PATCH 319/553] GlobalEdge: CSI and TCI related MAC CE intial commit --- cmake_targets/CMakeLists.txt | 1 + openair2/LAYER2/NR_MAC_COMMON/nr_mac.h | 168 +++++--- .../LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c | 385 +++++++++++++----- openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 72 +++- 4 files changed, 468 insertions(+), 158 deletions(-) diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index 5ac5053412..15b94a1082 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -249,6 +249,7 @@ add_boolean_option(UE_AUTOTEST_TRACE False "Activate UE autotest specific logs add_boolean_option(UE_DEBUG_TRACE False "Activate UE debug trace") add_boolean_option(UE_TIMING_TRACE False "Activate UE timing trace") add_boolean_option(DEBUG_CONSOLE False "makes debugging easier, disables stdout/stderr buffering") +add_boolean_option(GES_SUPPORT True "To enable the GES Code") set (OCP_ITTI ${OPENAIR_DIR}/common/utils/ocp_itti) add_library(ITTI diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h index 20b4c85dc6..f29a5af042 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h @@ -24,8 +24,8 @@ * \author R. Knopp, K.H. HSU, G. Casati * \date 2019 * \version 0.1 - * \company Eurecom / NTUST / Fraunhofer IIS - * \email: knopp@eurecom.fr, kai-hsiang.hsu@eurecom.fr, guido.casati@iis.fraunhofer.de + * \company Eurecom / NTUST / Fraunhofer IIS + * \email: knopp@eurecom.fr, kai-hsiang.hsu@eurecom.fr, guido.casati@iis.fraunhofer.de * \note * \warning */ @@ -71,72 +71,132 @@ // R: Reserved bit, set to zero. typedef struct { - uint8_t LCID:6; // octet 1 [5:0] - uint8_t F:1; // octet 1 [6] - uint8_t R:1; // octet 1 [7] - uint8_t L:8; // octet 2 [7:0] + uint8_t LCID: 6; // octet 1 [5:0] + uint8_t F: 1; // octet 1 [6] + uint8_t R: 1; // octet 1 [7] + uint8_t L: 8; // octet 2 [7:0] } __attribute__ ((__packed__)) NR_MAC_SUBHEADER_SHORT; typedef struct { - uint8_t LCID:6; // octet 1 [5:0] - uint8_t F:1; // octet 1 [6] - uint8_t R:1; // octet 1 [7] - uint8_t L1:8; // octet 2 [7:0] - uint8_t L2:8; // octet 3 [7:0] + uint8_t LCID: 6; // octet 1 [5:0] + uint8_t F: 1; // octet 1 [6] + uint8_t R: 1; // octet 1 [7] + uint8_t L1: 8; // octet 2 [7:0] + uint8_t L2: 8; // octet 3 [7:0] } __attribute__ ((__packed__)) NR_MAC_SUBHEADER_LONG; typedef struct { - uint8_t LCID:6; // octet 1 [5:0] - uint8_t R:2; // octet 1 [7:6] + uint8_t LCID: 6; // octet 1 [5:0] + uint8_t R: 2; // octet 1 [7:6] } __attribute__ ((__packed__)) NR_MAC_SUBHEADER_FIXED; // BSR MAC CEs // TS 38.321 ch. 6.1.3.1 // Short BSR for a specific logical channel group ID typedef struct { - uint8_t Buffer_size:5; // octet 1 LSB - uint8_t LcgID:3; // octet 1 MSB + uint8_t Buffer_size: 5; // octet 1 LSB + uint8_t LcgID: 3; // octet 1 MSB } __attribute__ ((__packed__)) NR_BSR_SHORT; typedef NR_BSR_SHORT NR_BSR_SHORT_TRUNCATED; // Long BSR for all logical channel group ID typedef struct { - uint8_t Buffer_size7:8; - uint8_t Buffer_size6:8; - uint8_t Buffer_size5:8; - uint8_t Buffer_size4:8; - uint8_t Buffer_size3:8; - uint8_t Buffer_size2:8; - uint8_t Buffer_size1:8; - uint8_t Buffer_size0:8; - uint8_t LcgID0:1; - uint8_t LcgID1:1; - uint8_t LcgID2:1; - uint8_t LcgID3:1; - uint8_t LcgID4:1; - uint8_t LcgID5:1; - uint8_t LcgID6:1; - uint8_t LcgID7:1; + uint8_t Buffer_size7: 8; + uint8_t Buffer_size6: 8; + uint8_t Buffer_size5: 8; + uint8_t Buffer_size4: 8; + uint8_t Buffer_size3: 8; + uint8_t Buffer_size2: 8; + uint8_t Buffer_size1: 8; + uint8_t Buffer_size0: 8; + uint8_t LcgID0: 1; + uint8_t LcgID1: 1; + uint8_t LcgID2: 1; + uint8_t LcgID3: 1; + uint8_t LcgID4: 1; + uint8_t LcgID5: 1; + uint8_t LcgID6: 1; + uint8_t LcgID7: 1; } __attribute__ ((__packed__)) NR_BSR_LONG; typedef NR_BSR_LONG NR_BSR_LONG_TRUNCATED; // 38.321 ch. 6.1.3.4 typedef struct { - uint8_t TA_COMMAND:6; // octet 1 [5:0] - uint8_t TAGID:2; // octet 1 [7:6] + uint8_t TA_COMMAND: 6; // octet 1 [5:0] + uint8_t TAGID: 2; // octet 1 [7:6] } __attribute__ ((__packed__)) NR_MAC_CE_TA; // single Entry PHR MAC CE // TS 38.321 ch. 6.1.3.8 typedef struct { - uint8_t PH:6; - uint8_t R1:2; - uint8_t PCMAX:6; - uint8_t R2:6; + uint8_t PH: 6; + uint8_t R1: 2; + uint8_t PCMAX: 6; + uint8_t R2: 6; } __attribute__ ((__packed__)) NR_SINGLE_ENTRY_PHR_MAC_CE; +#ifdef GES_SUPPORT + +// SP ZP CSI-RS Resource Set Activation/Deactivation MAC CE +// 38.321 ch. 6.1.3.19 +typedef struct { + uint8_t BWPID: 2; // octet 1 [1:0] + uint8_t CELLID: 5; // octet 1 [6:2] + uint8_t A_D: 1; // octet 1 [7] + uint8_t CSIRS_RSC_ID: 4; // octet 2 [3:0] + uint8_t R: 4 // octet 2 [7:4] +} __attribute__ ((__packed__)) NR_MAC_CE_SP_ZP_CSI_RS_RES_SET; + +//TS 38.321 Sec 6.1.3.15, TCI State indicaton for UE-Specific PDCCH MAC CE +typedef struct { + uint8_t CoresetId1: 3; //Octect 1 [2:0] + uint8_t ServingCellId: 5; //Octect 1 [7:3] + uint8_t TciStateId: 7; //Octect 2 [6:0] + uint8_t CoresetId2: 1; //Octect 2 [7] +} __attribute__ ((__packed__)) NR_TCI_PDCCH; + +//TS 38.321 Sec 6.1.3.14, TCI State activation/deactivation for UE Specific PDSCH MAC CE +typedef struct { + uint8_t BWP_Id: 2; //Octect 1 [1:0] + uint8_t ServingCellId: 5; //Octect 1 [6:2] + uint8_t R: 1; //Octect 1 [7] + uint8_t T[]; //Octects 2 to MAX TCI States/8 +} __attribute__ ((__packed__)) NR_TCI_PDSCH_APERIODIC_CSI; + +//TS 6.1.3.16, SP CSI reporting on PUCCH Activation/Deactivation MAC CE +typedef struct { + uint8_t BWP_Id: 2; //Octect 1 [1:0] + uint8_t ServingCellId: 5; //Octect 1 [6:2] + uint8_t R1: 1; //Octect 1 [7] + uint8_t S0: 1; //Octect 2 [0] + uint8_t S1: 1; //Octect 2 [1] + uint8_t S2: 1; //Octect 2 [2] + uint8_t S3: 1; //Octect 2 [3] + uint8_t R2: 4; //Octect 2 [7:4] +} __attribute__ ((__packed__)) NR_PUCCH_CSI_REPORTING; + + +//TS 38.321 sec 6.1.3.12 +//SP CSI-RS / CSI-IM Resource Set Activation/Deactivation MAC CE +typedef struct { + uint8_t BWP_ID: 2; + uint8_t SCID: 5; + uint8_t A_D: 1; + uint8_t SP_CSI_RSID: 6; + uint8_t IM: 1; + uint8_t R1: 1; + uint8_t SP_CSI_IMID: 6; + uint8_t R2: 2; + struct TCI_S { + uint8_t TCI_STATE_ID: 6; + uint8_t R: 2; + } __attribute__ ((__packed__)) TCI_STATE; +} __attribute__ ((__packed__)) CSI_RS_CSI_IM_ACT_DEACT_MAC_CE; + +#endif + //* RAR MAC subheader // TS 38.321 ch. 6.1.5, 6.2.2 *// // - E: The Extension field is a flag indicating if the MAC subPDU including this MAC subheader is the last MAC subPDU or not in the MAC PDU // - T: The Type field is a flag indicating whether the MAC subheader contains a Random Access Preamble ID or a Backoff Indicator (0, BI) (1, RAPID) @@ -146,30 +206,30 @@ typedef struct { /*!\brief RAR MAC subheader with RAPID */ typedef struct { - uint8_t RAPID:6; - uint8_t T:1; - uint8_t E:1; + uint8_t RAPID: 6; + uint8_t T: 1; + uint8_t E: 1; } __attribute__ ((__packed__)) NR_RA_HEADER_RAPID; /*!\brief RAR MAC subheader with Backoff Indicator */ typedef struct { - uint8_t BI:4; - uint8_t R:2; - uint8_t T:1; - uint8_t E:1; + uint8_t BI: 4; + uint8_t R: 2; + uint8_t T: 1; + uint8_t E: 1; } __attribute__ ((__packed__)) NR_RA_HEADER_BI; // TS 38.321 ch. 6.2.3 typedef struct { - uint8_t TA1:7; // octet 1 [6:0] - uint8_t R:1; // octet 1 [7] - uint8_t UL_GRANT_1:3; // octet 2 [2:0] - uint8_t TA2:5; // octet 2 [7:3] - uint8_t UL_GRANT_2:8; // octet 3 [7:0] - uint8_t UL_GRANT_3:8; // octet 4 [7:0] - uint8_t UL_GRANT_4:8; // octet 5 [7:0] - uint8_t TCRNTI_1:8; // octet 6 [7:0] - uint8_t TCRNTI_2:8; // octet 7 [7:0] + uint8_t TA1: 7; // octet 1 [6:0] + uint8_t R: 1; // octet 1 [7] + uint8_t UL_GRANT_1: 3; // octet 2 [2:0] + uint8_t TA2: 5; // octet 2 [7:3] + uint8_t UL_GRANT_2: 8; // octet 3 [7:0] + uint8_t UL_GRANT_3: 8; // octet 4 [7:0] + uint8_t UL_GRANT_4: 8; // octet 5 [7:0] + uint8_t TCRNTI_1: 8; // octet 6 [7:0] + uint8_t TCRNTI_2: 8; // octet 7 [7:0] } __attribute__ ((__packed__)) NR_MAC_RAR; // 38.321 ch6.2.1, 38.331 @@ -185,7 +245,7 @@ typedef struct { #define DL_SCH_LCID_TCI_STATE_IND_UE_SPEC_PDCCH 0x34 #define DL_SCH_LCID_TCI_STATE_ACT_UE_SPEC_PDSCH 0x35 #define DL_SCH_LCID_APERIODIC_CSI_TRI_STATE_SUBSEL 0x36 -#define DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT 0X37 +#define DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT 0X37 #define DL_SCH_LCID_DUPLICATION_ACT 0X38 #define DL_SCH_LCID_SCell_ACT_4_OCT 0X39 #define DL_SCH_LCID_SCell_ACT_1_OCT 0X3A diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c index 7777e307fb..e086210e4f 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c @@ -47,6 +47,12 @@ //////////////////////////////////////////////////////// /////* DLSCH MAC PDU generation (6.1.2 TS 38.321) *///// //////////////////////////////////////////////////////// +#ifdef GES_SUPPORT +#define OCTET 8 +#define HALFWORD 16 +#define WORD 32 +//#define SIZE_OF_POINTER sizeof (void *) +#endif int nr_generate_dlsch_pdu(module_id_t module_idP, unsigned char *sdus_payload, @@ -56,127 +62,302 @@ int nr_generate_dlsch_pdu(module_id_t module_idP, unsigned char *sdu_lcids, unsigned char drx_cmd, unsigned char *ue_cont_res_id, - unsigned short post_padding){ + unsigned short post_padding) { - gNB_MAC_INST *gNB = RC.nrmac[module_idP]; + gNB_MAC_INST *gNB = RC.nrmac[module_idP]; - NR_MAC_SUBHEADER_FIXED *mac_pdu_ptr = (NR_MAC_SUBHEADER_FIXED *) mac_pdu; - unsigned char * dlsch_buffer_ptr = sdus_payload; - uint8_t last_size = 0; - int offset = 0, mac_ce_size, i, timing_advance_cmd, tag_id = 0; - // MAC CEs - uint8_t mac_header_control_elements[16], *ce_ptr; - ce_ptr = &mac_header_control_elements[0]; + NR_MAC_SUBHEADER_FIXED *mac_pdu_ptr = (NR_MAC_SUBHEADER_FIXED *) mac_pdu; + unsigned char * dlsch_buffer_ptr = sdus_payload; + uint8_t last_size = 0; + int offset = 0, mac_ce_size, i, timing_advance_cmd, tag_id = 0; + // MAC CEs + uint8_t mac_header_control_elements[16], *ce_ptr; + ce_ptr = &mac_header_control_elements[0]; +#ifdef GES_SUPPORT + uint16_t UE_id = 0; //TODO need to get as a function parameter or need to invoke api to UE_id using module Id and RNTI + gNB_MAC_INST *gNB_mac = RC.nrmac[module_idP]; + NR_UE_list_t *UE_list = &gNB_mac->UE_list; + NR_UE_sched_ctrl_t *ue_sched_ctl = NULL; + //NR_CellGroupConfig_t *config = UE_list->secondaryCellGroup[UE_id]; + ue_sched_ctl = &(UE_list->UE_sched_ctrl[UE_id]); +#endif - // 1) Compute MAC CE and related subheaders + // 1) Compute MAC CE and related subheaders - // DRX command subheader (MAC CE size 0) - if (drx_cmd != 255) { - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_DRX; - //last_size = 1; - mac_pdu_ptr++; - } - - // Timing Advance subheader - /* This was done only when timing_advance_cmd != 31 - // now TA is always send when ta_timer resets regardless of its value - // this is done to avoid issues with the timeAlignmentTimer which is - // supposed to monitor if the UE received TA or not */ - if (gNB->ta_len){ - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_TA_COMMAND; - //last_size = 1; - mac_pdu_ptr++; - - // TA MAC CE (1 octet) - timing_advance_cmd = gNB->ta_command; - AssertFatal(timing_advance_cmd < 64,"timing_advance_cmd %d > 63\n", timing_advance_cmd); - ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND = timing_advance_cmd; //(timing_advance_cmd+31)&0x3f; - if (gNB->tag->tag_Id != 0){ - tag_id = gNB->tag->tag_Id; - ((NR_MAC_CE_TA *) ce_ptr)->TAGID = tag_id; + // DRX command subheader (MAC CE size 0) + if (drx_cmd != 255) { + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_DRX; + //last_size = 1; + mac_pdu_ptr++; } - LOG_D(MAC, "NR MAC CE timing advance command = %d (%d) TAG ID = %d\n", timing_advance_cmd, ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND, tag_id); + // Timing Advance subheader + /* This was done only when timing_advance_cmd != 31 + // now TA is always send when ta_timer resets regardless of its value + // this is done to avoid issues with the timeAlignmentTimer which is + // supposed to monitor if the UE received TA or not */ + if (gNB->ta_len) { + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_TA_COMMAND; + //last_size = 1; + mac_pdu_ptr++; - mac_ce_size = sizeof(NR_MAC_CE_TA); + // TA MAC CE (1 octet) + timing_advance_cmd = gNB->ta_command; + AssertFatal(timing_advance_cmd < 64, "timing_advance_cmd %d > 63\n", timing_advance_cmd); + ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND = timing_advance_cmd; //(timing_advance_cmd+31)&0x3f; + if (gNB->tag->tag_Id != 0) { + tag_id = gNB->tag->tag_Id; + ((NR_MAC_CE_TA *) ce_ptr)->TAGID = tag_id; + } - // Copying bytes for MAC CEs to the mac pdu pointer - memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); - ce_ptr += mac_ce_size; - mac_pdu_ptr += (unsigned char) mac_ce_size; - } + LOG_D(MAC, "NR MAC CE timing advance command = %d (%d) TAG ID = %d\n", timing_advance_cmd, ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND, tag_id); - // Contention resolution fixed subheader and MAC CE - if (ue_cont_res_id) { - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_CON_RES_ID; - mac_pdu_ptr++; - //last_size = 1; + mac_ce_size = sizeof(NR_MAC_CE_TA); - // contention resolution identity MAC ce has a fixed 48 bit size - // this contains the UL CCCH SDU. If UL CCCH SDU is longer than 48 bits, - // it contains the first 48 bits of the UL CCCH SDU - LOG_T(MAC, "[gNB ][RAPROC] Generate contention resolution msg: %x.%x.%x.%x.%x.%x\n", - ue_cont_res_id[0], ue_cont_res_id[1], ue_cont_res_id[2], - ue_cont_res_id[3], ue_cont_res_id[4], ue_cont_res_id[5]); + // Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); + ce_ptr += mac_ce_size; + mac_pdu_ptr += (unsigned char) mac_ce_size; + } - // Copying bytes (6 octects) to CEs pointer - mac_ce_size = 6; - memcpy(ce_ptr, ue_cont_res_id, mac_ce_size); - - // Copying bytes for MAC CEs to mac pdu pointer - memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); - ce_ptr += mac_ce_size; - mac_pdu_ptr += (unsigned char) mac_ce_size; - } + // Contention resolution fixed subheader and MAC CE + if (ue_cont_res_id) { + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_CON_RES_ID; + mac_pdu_ptr++; + //last_size = 1; - // 2) Generation of DLSCH MAC subPDUs including subheaders and MAC SDUs - for (i = 0; i < num_sdus; i++) { - LOG_D(MAC, "[gNB] Generate DLSCH header num sdu %d len sdu %d\n", num_sdus, sdu_lengths[i]); + // contention resolution identity MAC ce has a fixed 48 bit size + // this contains the UL CCCH SDU. If UL CCCH SDU is longer than 48 bits, + // it contains the first 48 bits of the UL CCCH SDU + LOG_T(MAC, "[gNB ][RAPROC] Generate contention resolution msg: %x.%x.%x.%x.%x.%x\n", + ue_cont_res_id[0], ue_cont_res_id[1], ue_cont_res_id[2], + ue_cont_res_id[3], ue_cont_res_id[4], ue_cont_res_id[5]); + + // Copying bytes (6 octects) to CEs pointer + mac_ce_size = 6; + memcpy(ce_ptr, ue_cont_res_id, mac_ce_size); + + // Copying bytes for MAC CEs to mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); + ce_ptr += mac_ce_size; + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + +#ifdef GES_SUPPORT + + //TS 38.321 Sec 6.1.3.15 TCI State indication for UE Specific PDCCH MAC CE SubPDU generation + if (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.is_scheduled) { + //filling subheader + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_TCI_STATE_IND_UE_SPEC_PDCCH; + mac_pdu_ptr++; + //Creating the instance of CE structure + NR_TCI_PDCCH nr_UESpec_TCI_StateInd_PDCCH; + //filling the CE structre + nr_UESpec_TCI_StateInd_PDCCH.CoresetId1 = ((ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0xF) >> 1; //extracting MSB 3 bits from LS nibble + nr_UESpec_TCI_StateInd_PDCCH.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.servingCellId) & 0x1F; //extracting LSB 5 Bits + nr_UESpec_TCI_StateInd_PDCCH.TciStateId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.tciStateId) & 0x7F; //extracting LSB 7 bits + nr_UESpec_TCI_StateInd_PDCCH.CoresetId2 = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0x1; //extracting LSB 1 bit + LOG_D(MAC, "NR MAC CE TCI state indication for UE Specific PDCCH = %d \n", nr_UESpec_TCI_StateInd_PDCCH.TciStateId); + mac_ce_size = sizeof(NR_TCI_PDCCH); + // Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)&nr_UESpec_TCI_StateInd_PDCCH, mac_ce_size); + //incrementing the PDU pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + + //TS 38.321 Sec 6.1.3.16, SP CSI reporting on PUCCH Activation/Deactivation MAC CE + if (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.is_scheduled) { + //filling the subheader + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_REP_PUCCH_ACT; + mac_pdu_ptr++; + //creating the instance of CE structure + NR_PUCCH_CSI_REPORTING nr_PUCCH_CSI_reportingActDeact; + //filling the CE structure + nr_PUCCH_CSI_reportingActDeact.BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.bwpId) & 0x3; //extracting LSB 2 bibs + nr_PUCCH_CSI_reportingActDeact.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.servingCellId) & 0x1F; //extracting LSB 5 bits + nr_PUCCH_CSI_reportingActDeact.S0 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[0]; + nr_PUCCH_CSI_reportingActDeact.S1 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[1]; + nr_PUCCH_CSI_reportingActDeact.S2 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[2]; + nr_PUCCH_CSI_reportingActDeact.S3 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[3]; + nr_PUCCH_CSI_reportingActDeact.R2 = 0; + mac_ce_size = sizeof(NR_PUCCH_CSI_REPORTING); + // Copying MAC CE data to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)&nr_PUCCH_CSI_reportingActDeact, mac_ce_size); + //incrementing the PDU pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + + //TS 38.321 Sec 6.1.3.14, TCI State activation/deactivation for UE Specific PDSCH MAC CE + if (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.is_scheduled) { + //Computing the number of octects to be allocated for Flexible array member + //of MAC CE structure + uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.highestTciStateActivated) / 8 + 1; //Calculating the number of octects for allocating the memory + + //filling the subheader + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_TCI_STATE_ACT_UE_SPEC_PDSCH; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + last_size = 2; + //Incrementing the PDU pointer + mac_pdu_ptr += last_size; + //allocating memory for CE Structure + NR_TCI_PDSCH_APERIODIC_CSI *nr_UESpec_TCI_StateInd_PDSCH = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //initializing to zero + memset((void *)nr_UESpec_TCI_StateInd_PDSCH, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //filling the CE Structure + nr_UESpec_TCI_StateInd_PDSCH->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.bwpId) & 0x3; //extracting LSB 2 Bits + nr_UESpec_TCI_StateInd_PDSCH->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.servingCellId) & 0x1F; //extracting LSB 5 bits + for(i = 0; i < (num_octects * 8); i++) { + if(ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.tciStateActDeact[i]) + nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] = nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] | (1 << (i % 8)); + } + mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + //Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)nr_UESpec_TCI_StateInd_PDSCH, mac_ce_size); + //incrementing the mac pdu pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + //freeing the allocated memory + free(nr_UESpec_TCI_StateInd_PDSCH); + } + + //TS38.321 Sec 6.1.3.13 Aperiodic CSI Trigger State Subselection MAC CE + if (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.is_scheduled) { + //Computing the number of octects to be allocated for Flexible array member + //of MAC CE structure + uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.highestTriggerStateSelected) / 8 + 1; //Calculating the number of octects for allocating the memory + + //filling the subheader + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_APERIODIC_CSI_TRI_STATE_SUBSEL; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + last_size = 2; + //Incrementing the PDU pointer + mac_pdu_ptr += last_size; + //allocating memory for CE structure + NR_TCI_PDSCH_APERIODIC_CSI *nr_Aperiodic_CSI_Trigger = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //initializing to zero + memset((void *)nr_Aperiodic_CSI_Trigger, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //filling the CE Structure + nr_Aperiodic_CSI_Trigger->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.bwpId) & 0x3; //extracting LSB 2 bits + nr_Aperiodic_CSI_Trigger->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.servingCellId) & 0x1F; //extracting LSB 5 bits + nr_Aperiodic_CSI_Trigger->R = 0; + for(i = 0; i < (num_octects * 8); i++) { + if(ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.triggerStateSelection[i]) + nr_Aperiodic_CSI_Trigger->T[i / 8] = nr_Aperiodic_CSI_Trigger->T[i / 8] | (1 << (i % 8)); + } + mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + // Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)nr_Aperiodic_CSI_Trigger, mac_ce_size); + //incrementing the mac pdu pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + //freeing the allocated memory + free(nr_Aperiodic_CSI_Trigger); + } + + if (ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.is_scheduled) { + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_SP_ZP_CSI_RS_RES_SET_ACT; + mac_pdu_ptr++; + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->A_D = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.act_deact; + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CELLID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id & 0x1F; //5 bits + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->BWPID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid & 0x3; //2 bits + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CSIRS_RSC_ID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id & 0xF; //4 bits + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->R = 0; + LOG_D(MAC, "NR MAC CE of ZP CSIRS Serv cell ID = %d BWPID= %d Rsc set ID = %d\n", ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id, ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid, ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id); + mac_ce_size = sizeof(NR_MAC_CE_SP_ZP_CSI_RS_RES_SET); + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + + if (ue_sched_ctl->UE_mac_ce_ctrl.csi_im.is_scheduled) { + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT; + mac_pdu_ptr++; + CSI_RS_CSI_IM_ACT_DEACT_MAC_CE csi_rs_im_act_deact_ce; + csi_rs_im_act_deact_ce.A_D = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.act_deact; + csi_rs_im_act_deact_ce.SCID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.serv_cellid & 0x3F;//gNB_PHY -> ssb_pdu.ssb_pdu_rel15.PhysCellId; + csi_rs_im_act_deact_ce.BWP_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.bwp_id; + csi_rs_im_act_deact_ce.R1 = 0; + csi_rs_im_act_deact_ce.IM = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.im;// IF set CSI IM Rsc id will presesent else CSI IM RSC ID is abscent + csi_rs_im_act_deact_ce.SP_CSI_RSID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nzp_csi_rsc_id; + + if ( csi_rs_im_act_deact_ce.IM ) { //is_scheduled if IM is 1 else this field will not present + csi_rs_im_act_deact_ce.R2 = 0; + csi_rs_im_act_deact_ce.SP_CSI_IMID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.csi_im_rsc_id; + mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE ); + } else { + mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE ) - 1; + } + + memcpy ((void *) mac_pdu_ptr, (void *) & ( csi_rs_im_act_deact_ce), mac_ce_size); + mac_pdu_ptr += (unsigned char) mac_ce_size; + + if (csi_rs_im_act_deact_ce.A_D ) { //Following IE is_scheduled only if A/D is 1 + mac_ce_size = sizeof ( struct TCI_S); + + for ( i = 0; i < ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nb_tci_resource_set_id; i++) { + csi_rs_im_act_deact_ce.TCI_STATE.R = 0; + csi_rs_im_act_deact_ce.TCI_STATE.TCI_STATE_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.tci_state_id [i] & 0x7F; + memcpy ((void *) mac_pdu_ptr, (void *) & (csi_rs_im_act_deact_ce.TCI_STATE), mac_ce_size); + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + + } + } + +#endif + + // 2) Generation of DLSCH MAC subPDUs including subheaders and MAC SDUs + for (i = 0; i < num_sdus; i++) { + LOG_D(MAC, "[gNB] Generate DLSCH header num sdu %d len sdu %d\n", num_sdus, sdu_lengths[i]); + + if (sdu_lengths[i] < 128) { + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = sdu_lcids[i]; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = (unsigned char) sdu_lengths[i]; + last_size = 2; + } else { + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->F = 1; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->LCID = sdu_lcids[i]; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L1 = ((unsigned short) sdu_lengths[i] >> 8) & 0x7f; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L2 = (unsigned short) sdu_lengths[i] & 0xff; + last_size = 3; + } + + mac_pdu_ptr += last_size; + + // 3) cycle through SDUs, compute each relevant and place dlsch_buffer in + memcpy((void *) mac_pdu_ptr, (void *) dlsch_buffer_ptr, sdu_lengths[i]); + dlsch_buffer_ptr += sdu_lengths[i]; + mac_pdu_ptr += sdu_lengths[i]; + } + + // 4) Compute final offset for padding + if (post_padding > 0) { + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_PADDING; + mac_pdu_ptr++; - if (sdu_lengths[i] < 128) { - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = sdu_lcids[i]; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = (unsigned char) sdu_lengths[i]; - last_size = 2; } else { - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->F = 1; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->LCID = sdu_lcids[i]; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L1 = ((unsigned short) sdu_lengths[i] >> 8) & 0x7f; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L2 = (unsigned short) sdu_lengths[i] & 0xff; - last_size = 3; + // no MAC subPDU with padding } - mac_pdu_ptr += last_size; + // compute final offset + offset = ((unsigned char *) mac_pdu_ptr - mac_pdu); - // 3) cycle through SDUs, compute each relevant and place dlsch_buffer in - memcpy((void *) mac_pdu_ptr, (void *) dlsch_buffer_ptr, sdu_lengths[i]); - dlsch_buffer_ptr+= sdu_lengths[i]; - mac_pdu_ptr += sdu_lengths[i]; - } + //printf("Offset %d \n", ((unsigned char *) mac_pdu_ptr - mac_pdu)); - // 4) Compute final offset for padding - if (post_padding > 0) { - ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_PADDING; - mac_pdu_ptr++; - - } else { - // no MAC subPDU with padding - } - - // compute final offset - offset = ((unsigned char *) mac_pdu_ptr - mac_pdu); - - //printf("Offset %d \n", ((unsigned char *) mac_pdu_ptr - mac_pdu)); - - return offset; + return offset; } /* functionalities of this function have been moved to nr_schedule_uss_dlsch_phytest */ -void nr_schedule_ue_spec(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ +void nr_schedule_ue_spec(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) { } diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index 90d2310f77..bea14ed406 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -179,6 +179,71 @@ typedef struct { uint8_t num_sf_allocation_pattern; } NR_COMMON_channels_t; + +// SP ZP CSI-RS Resource Set Activation/Deactivation MAC CE +typedef struct sp_zp_csirs { + bool is_scheduled; //ZP CSI-RS ACT/Deact MAC CE is scheduled + bool act_deact; //Activation/Deactivation indication + uint8_t serv_cell_id; //Identity of Serving cell for which MAC CE applies + uint8_t bwpid; //Downlink BWP id + uint8_t rsc_id; //SP ZP CSI-RS resource set +} sp_zp_csirs_t; + +//SP CSI-RS / CSI-IM Resource Set Activation/Deactivation MAC CE +#define MAX_CSI_RESOURCE_SET 64 +typedef struct csi_rs_im { + bool is_scheduled; + bool act_deact; + uint8_t serv_cellid; + uint8_t bwp_id; + bool im; + uint8_t csi_im_rsc_id; + uint8_t nzp_csi_rsc_id; + uint8_t nb_tci_resource_set_id; + uint8_t tci_state_id [ MAX_CSI_RESOURCE_SET ]; +} csi_rs_im_t; + +typedef struct pdcchStateInd { + bool is_scheduled; + uint8_t servingCellId; + uint8_t coresetId; + uint8_t tciStateId; +} pdcchStateInd_t; + +typedef struct SPCSIReportingpucch { + bool is_scheduled; + uint8_t servingCellId; + uint8_t bwpId; + bool s0tos3_actDeact[4]; +} SPCSIReportingpucch_t; + +#define MAX_APERIODIC_TRIGGER_STATES 128 //38.331 +typedef struct aperiodicCSI_triggerStateSelection { + bool is_scheduled; + uint8_t servingCellId; + uint8_t bwpId; + uint8_t highestTriggerStateSelected; + bool triggerStateSelection[MAX_APERIODIC_TRIGGER_STATES]; +} aperiodicCSI_triggerStateSelection_t; + +#define MAX_TCI_STATES 128 //38.331 +typedef struct pdschTciStatesActDeact { + bool is_scheduled; + uint8_t servingCellId; + uint8_t bwpId; + uint8_t highestTciStateActivated; + bool tciStateActDeact[MAX_TCI_STATES]; +} pdschTciStatesActDeact_t; + +typedef struct UE_info { + sp_zp_csirs_t sp_zp_csi_rs; + csi_rs_im_t csi_im; + pdcchStateInd_t pdcch_state_ind; + SPCSIReportingpucch_t SP_CSI_reporting_pucch; + aperiodicCSI_triggerStateSelection_t aperi_CSI_trigger; + pdschTciStatesActDeact_t pdsch_TCI_States_ActDeact; +} NR_UE_mac_ce_ctrl_t; + typedef struct NR_sched_pucch { int frame; int ul_slot; @@ -188,6 +253,7 @@ typedef struct NR_sched_pucch { struct NR_sched_pucch *next_sched_pucch; } NR_sched_pucch; + /*! \brief scheduling control information set through an API */ typedef struct { uint64_t dlsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains dlsch @@ -195,6 +261,8 @@ typedef struct { NR_sched_pucch *sched_pucch; uint16_t ta_timer; int16_t ta_update; + int dummy; + NR_UE_mac_ce_ctrl_t UE_mac_ce_ctrl;// MAC CE related information } NR_UE_sched_ctrl_t; /*! \brief UE list used by gNB to order UEs/CC for scheduling*/ @@ -213,7 +281,7 @@ typedef struct { NR_CellGroupConfig_t *secondaryCellGroup[MAX_MOBILES_PER_GNB]; } NR_UE_list_t; -/*! \brief top level gNB MAC structure */ +/*! \brief top level eNB MAC structure */ typedef struct gNB_MAC_INST_s { /// Ethernet parameters for northbound midhaul interface eth_params_t eth_params_n; @@ -254,7 +322,7 @@ typedef struct gNB_MAC_INST_s { /// UL handle uint32_t ul_handle; - // MAC function execution peformance profiler + // MAC function execution peformance profiler /// processing time of eNB scheduler time_stats_t eNB_scheduler; /// processing time of eNB scheduler for SI From 7964fed747f710d0d12a38113886aa0f68a61c84 Mon Sep 17 00:00:00 2001 From: Rangaswami Date: Thu, 4 Jun 2020 11:04:43 +0530 Subject: [PATCH 320/553] Corrected indentation and removed GES macro --- cmake_targets/CMakeLists.txt | 1 - openair2/LAYER2/NR_MAC_COMMON/nr_mac.h | 176 +++--- .../LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c | 525 +++++++++--------- openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 2 - 4 files changed, 341 insertions(+), 363 deletions(-) diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index 15b94a1082..5ac5053412 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -249,7 +249,6 @@ add_boolean_option(UE_AUTOTEST_TRACE False "Activate UE autotest specific logs add_boolean_option(UE_DEBUG_TRACE False "Activate UE debug trace") add_boolean_option(UE_TIMING_TRACE False "Activate UE timing trace") add_boolean_option(DEBUG_CONSOLE False "makes debugging easier, disables stdout/stderr buffering") -add_boolean_option(GES_SUPPORT True "To enable the GES Code") set (OCP_ITTI ${OPENAIR_DIR}/common/utils/ocp_itti) add_library(ITTI diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h index f29a5af042..d133b679f1 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h @@ -71,131 +71,129 @@ // R: Reserved bit, set to zero. typedef struct { - uint8_t LCID: 6; // octet 1 [5:0] - uint8_t F: 1; // octet 1 [6] - uint8_t R: 1; // octet 1 [7] - uint8_t L: 8; // octet 2 [7:0] + uint8_t LCID: 6; // octet 1 [5:0] + uint8_t F: 1; // octet 1 [6] + uint8_t R: 1; // octet 1 [7] + uint8_t L: 8; // octet 2 [7:0] } __attribute__ ((__packed__)) NR_MAC_SUBHEADER_SHORT; typedef struct { - uint8_t LCID: 6; // octet 1 [5:0] - uint8_t F: 1; // octet 1 [6] - uint8_t R: 1; // octet 1 [7] - uint8_t L1: 8; // octet 2 [7:0] - uint8_t L2: 8; // octet 3 [7:0] + uint8_t LCID: 6; // octet 1 [5:0] + uint8_t F: 1; // octet 1 [6] + uint8_t R: 1; // octet 1 [7] + uint8_t L1: 8; // octet 2 [7:0] + uint8_t L2: 8; // octet 3 [7:0] } __attribute__ ((__packed__)) NR_MAC_SUBHEADER_LONG; typedef struct { - uint8_t LCID: 6; // octet 1 [5:0] - uint8_t R: 2; // octet 1 [7:6] + uint8_t LCID: 6; // octet 1 [5:0] + uint8_t R: 2; // octet 1 [7:6] } __attribute__ ((__packed__)) NR_MAC_SUBHEADER_FIXED; // BSR MAC CEs // TS 38.321 ch. 6.1.3.1 // Short BSR for a specific logical channel group ID typedef struct { - uint8_t Buffer_size: 5; // octet 1 LSB - uint8_t LcgID: 3; // octet 1 MSB + uint8_t Buffer_size: 5; // octet 1 LSB + uint8_t LcgID: 3; // octet 1 MSB } __attribute__ ((__packed__)) NR_BSR_SHORT; typedef NR_BSR_SHORT NR_BSR_SHORT_TRUNCATED; // Long BSR for all logical channel group ID typedef struct { - uint8_t Buffer_size7: 8; - uint8_t Buffer_size6: 8; - uint8_t Buffer_size5: 8; - uint8_t Buffer_size4: 8; - uint8_t Buffer_size3: 8; - uint8_t Buffer_size2: 8; - uint8_t Buffer_size1: 8; - uint8_t Buffer_size0: 8; - uint8_t LcgID0: 1; - uint8_t LcgID1: 1; - uint8_t LcgID2: 1; - uint8_t LcgID3: 1; - uint8_t LcgID4: 1; - uint8_t LcgID5: 1; - uint8_t LcgID6: 1; - uint8_t LcgID7: 1; + uint8_t Buffer_size7: 8; + uint8_t Buffer_size6: 8; + uint8_t Buffer_size5: 8; + uint8_t Buffer_size4: 8; + uint8_t Buffer_size3: 8; + uint8_t Buffer_size2: 8; + uint8_t Buffer_size1: 8; + uint8_t Buffer_size0: 8; + uint8_t LcgID0: 1; + uint8_t LcgID1: 1; + uint8_t LcgID2: 1; + uint8_t LcgID3: 1; + uint8_t LcgID4: 1; + uint8_t LcgID5: 1; + uint8_t LcgID6: 1; + uint8_t LcgID7: 1; } __attribute__ ((__packed__)) NR_BSR_LONG; typedef NR_BSR_LONG NR_BSR_LONG_TRUNCATED; // 38.321 ch. 6.1.3.4 typedef struct { - uint8_t TA_COMMAND: 6; // octet 1 [5:0] - uint8_t TAGID: 2; // octet 1 [7:6] + uint8_t TA_COMMAND: 6; // octet 1 [5:0] + uint8_t TAGID: 2; // octet 1 [7:6] } __attribute__ ((__packed__)) NR_MAC_CE_TA; // single Entry PHR MAC CE // TS 38.321 ch. 6.1.3.8 typedef struct { - uint8_t PH: 6; - uint8_t R1: 2; - uint8_t PCMAX: 6; - uint8_t R2: 6; + uint8_t PH: 6; + uint8_t R1: 2; + uint8_t PCMAX: 6; + uint8_t R2: 6; } __attribute__ ((__packed__)) NR_SINGLE_ENTRY_PHR_MAC_CE; -#ifdef GES_SUPPORT // SP ZP CSI-RS Resource Set Activation/Deactivation MAC CE // 38.321 ch. 6.1.3.19 typedef struct { - uint8_t BWPID: 2; // octet 1 [1:0] - uint8_t CELLID: 5; // octet 1 [6:2] - uint8_t A_D: 1; // octet 1 [7] - uint8_t CSIRS_RSC_ID: 4; // octet 2 [3:0] - uint8_t R: 4 // octet 2 [7:4] + uint8_t BWPID: 2; // octet 1 [1:0] + uint8_t CELLID: 5; // octet 1 [6:2] + uint8_t A_D: 1; // octet 1 [7] + uint8_t CSIRS_RSC_ID: 4; // octet 2 [3:0] + uint8_t R: 4; // octet 2 [7:4] } __attribute__ ((__packed__)) NR_MAC_CE_SP_ZP_CSI_RS_RES_SET; //TS 38.321 Sec 6.1.3.15, TCI State indicaton for UE-Specific PDCCH MAC CE typedef struct { - uint8_t CoresetId1: 3; //Octect 1 [2:0] - uint8_t ServingCellId: 5; //Octect 1 [7:3] - uint8_t TciStateId: 7; //Octect 2 [6:0] - uint8_t CoresetId2: 1; //Octect 2 [7] + uint8_t CoresetId1: 3; //Octect 1 [2:0] + uint8_t ServingCellId: 5; //Octect 1 [7:3] + uint8_t TciStateId: 7; //Octect 2 [6:0] + uint8_t CoresetId2: 1; //Octect 2 [7] } __attribute__ ((__packed__)) NR_TCI_PDCCH; //TS 38.321 Sec 6.1.3.14, TCI State activation/deactivation for UE Specific PDSCH MAC CE typedef struct { - uint8_t BWP_Id: 2; //Octect 1 [1:0] - uint8_t ServingCellId: 5; //Octect 1 [6:2] - uint8_t R: 1; //Octect 1 [7] - uint8_t T[]; //Octects 2 to MAX TCI States/8 + uint8_t BWP_Id: 2; //Octect 1 [1:0] + uint8_t ServingCellId: 5; //Octect 1 [6:2] + uint8_t R: 1; //Octect 1 [7] + uint8_t T[]; //Octects 2 to MAX TCI States/8 } __attribute__ ((__packed__)) NR_TCI_PDSCH_APERIODIC_CSI; //TS 6.1.3.16, SP CSI reporting on PUCCH Activation/Deactivation MAC CE typedef struct { - uint8_t BWP_Id: 2; //Octect 1 [1:0] - uint8_t ServingCellId: 5; //Octect 1 [6:2] - uint8_t R1: 1; //Octect 1 [7] - uint8_t S0: 1; //Octect 2 [0] - uint8_t S1: 1; //Octect 2 [1] - uint8_t S2: 1; //Octect 2 [2] - uint8_t S3: 1; //Octect 2 [3] - uint8_t R2: 4; //Octect 2 [7:4] + uint8_t BWP_Id: 2; //Octect 1 [1:0] + uint8_t ServingCellId: 5; //Octect 1 [6:2] + uint8_t R1: 1; //Octect 1 [7] + uint8_t S0: 1; //Octect 2 [0] + uint8_t S1: 1; //Octect 2 [1] + uint8_t S2: 1; //Octect 2 [2] + uint8_t S3: 1; //Octect 2 [3] + uint8_t R2: 4; //Octect 2 [7:4] } __attribute__ ((__packed__)) NR_PUCCH_CSI_REPORTING; //TS 38.321 sec 6.1.3.12 //SP CSI-RS / CSI-IM Resource Set Activation/Deactivation MAC CE typedef struct { - uint8_t BWP_ID: 2; - uint8_t SCID: 5; - uint8_t A_D: 1; - uint8_t SP_CSI_RSID: 6; - uint8_t IM: 1; - uint8_t R1: 1; - uint8_t SP_CSI_IMID: 6; - uint8_t R2: 2; - struct TCI_S { - uint8_t TCI_STATE_ID: 6; - uint8_t R: 2; - } __attribute__ ((__packed__)) TCI_STATE; + uint8_t BWP_ID: 2; + uint8_t SCID: 5; + uint8_t A_D: 1; + uint8_t SP_CSI_RSID: 6; + uint8_t IM: 1; + uint8_t R1: 1; + uint8_t SP_CSI_IMID: 6; + uint8_t R2: 2; + struct TCI_S { + uint8_t TCI_STATE_ID: 6; + uint8_t R: 2; + } __attribute__ ((__packed__)) TCI_STATE; } __attribute__ ((__packed__)) CSI_RS_CSI_IM_ACT_DEACT_MAC_CE; -#endif //* RAR MAC subheader // TS 38.321 ch. 6.1.5, 6.2.2 *// // - E: The Extension field is a flag indicating if the MAC subPDU including this MAC subheader is the last MAC subPDU or not in the MAC PDU @@ -206,30 +204,30 @@ typedef struct { /*!\brief RAR MAC subheader with RAPID */ typedef struct { - uint8_t RAPID: 6; - uint8_t T: 1; - uint8_t E: 1; + uint8_t RAPID: 6; + uint8_t T: 1; + uint8_t E: 1; } __attribute__ ((__packed__)) NR_RA_HEADER_RAPID; /*!\brief RAR MAC subheader with Backoff Indicator */ typedef struct { - uint8_t BI: 4; - uint8_t R: 2; - uint8_t T: 1; - uint8_t E: 1; + uint8_t BI: 4; + uint8_t R: 2; + uint8_t T: 1; + uint8_t E: 1; } __attribute__ ((__packed__)) NR_RA_HEADER_BI; // TS 38.321 ch. 6.2.3 typedef struct { - uint8_t TA1: 7; // octet 1 [6:0] - uint8_t R: 1; // octet 1 [7] - uint8_t UL_GRANT_1: 3; // octet 2 [2:0] - uint8_t TA2: 5; // octet 2 [7:3] - uint8_t UL_GRANT_2: 8; // octet 3 [7:0] - uint8_t UL_GRANT_3: 8; // octet 4 [7:0] - uint8_t UL_GRANT_4: 8; // octet 5 [7:0] - uint8_t TCRNTI_1: 8; // octet 6 [7:0] - uint8_t TCRNTI_2: 8; // octet 7 [7:0] + uint8_t TA1: 7; // octet 1 [6:0] + uint8_t R: 1; // octet 1 [7] + uint8_t UL_GRANT_1: 3; // octet 2 [2:0] + uint8_t TA2: 5; // octet 2 [7:3] + uint8_t UL_GRANT_2: 8; // octet 3 [7:0] + uint8_t UL_GRANT_3: 8; // octet 4 [7:0] + uint8_t UL_GRANT_4: 8; // octet 5 [7:0] + uint8_t TCRNTI_1: 8; // octet 6 [7:0] + uint8_t TCRNTI_2: 8; // octet 7 [7:0] } __attribute__ ((__packed__)) NR_MAC_RAR; // 38.321 ch6.2.1, 38.331 @@ -273,9 +271,9 @@ typedef struct { #define UL_SCH_LCID_L_BSR 0x3E #define UL_SCH_LCID_PADDING 0x3F -#define NR_MAX_NUM_LCID 32 -#define NR_MAX_NUM_LCGID 8 -#define MAX_RLC_SDU_SUBHEADER_SIZE 3 +#define NR_MAX_NUM_LCID 32 +#define NR_MAX_NUM_LCGID 8 +#define MAX_RLC_SDU_SUBHEADER_SIZE 3 #endif /*__LAYER2_MAC_H__ */ diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c index e086210e4f..cf2323f571 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c @@ -47,12 +47,10 @@ //////////////////////////////////////////////////////// /////* DLSCH MAC PDU generation (6.1.2 TS 38.321) *///// //////////////////////////////////////////////////////// -#ifdef GES_SUPPORT #define OCTET 8 #define HALFWORD 16 #define WORD 32 //#define SIZE_OF_POINTER sizeof (void *) -#endif int nr_generate_dlsch_pdu(module_id_t module_idP, unsigned char *sdus_payload, @@ -63,299 +61,284 @@ int nr_generate_dlsch_pdu(module_id_t module_idP, unsigned char drx_cmd, unsigned char *ue_cont_res_id, unsigned short post_padding) { + gNB_MAC_INST *gNB = RC.nrmac[module_idP]; + NR_MAC_SUBHEADER_FIXED *mac_pdu_ptr = (NR_MAC_SUBHEADER_FIXED *) mac_pdu; + unsigned char *dlsch_buffer_ptr = sdus_payload; + uint8_t last_size = 0; + int offset = 0, mac_ce_size, i, timing_advance_cmd, tag_id = 0; + // MAC CEs + uint8_t mac_header_control_elements[16], *ce_ptr; + ce_ptr = &mac_header_control_elements[0]; + uint16_t UE_id = 0; //TODO need to get as a function parameter or need to invoke api to UE_id using module Id and RNTI + gNB_MAC_INST *gNB_mac = RC.nrmac[module_idP]; + NR_UE_list_t *UE_list = &gNB_mac->UE_list; + NR_UE_sched_ctrl_t *ue_sched_ctl = NULL; + //NR_CellGroupConfig_t *config = UE_list->secondaryCellGroup[UE_id]; + ue_sched_ctl = &(UE_list->UE_sched_ctrl[UE_id]); - gNB_MAC_INST *gNB = RC.nrmac[module_idP]; + // 1) Compute MAC CE and related subheaders - NR_MAC_SUBHEADER_FIXED *mac_pdu_ptr = (NR_MAC_SUBHEADER_FIXED *) mac_pdu; - unsigned char * dlsch_buffer_ptr = sdus_payload; - uint8_t last_size = 0; - int offset = 0, mac_ce_size, i, timing_advance_cmd, tag_id = 0; - // MAC CEs - uint8_t mac_header_control_elements[16], *ce_ptr; - ce_ptr = &mac_header_control_elements[0]; -#ifdef GES_SUPPORT - uint16_t UE_id = 0; //TODO need to get as a function parameter or need to invoke api to UE_id using module Id and RNTI - gNB_MAC_INST *gNB_mac = RC.nrmac[module_idP]; - NR_UE_list_t *UE_list = &gNB_mac->UE_list; - NR_UE_sched_ctrl_t *ue_sched_ctl = NULL; - //NR_CellGroupConfig_t *config = UE_list->secondaryCellGroup[UE_id]; - ue_sched_ctl = &(UE_list->UE_sched_ctrl[UE_id]); -#endif + // DRX command subheader (MAC CE size 0) + if (drx_cmd != 255) { + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_DRX; + //last_size = 1; + mac_pdu_ptr++; + } - // 1) Compute MAC CE and related subheaders + // Timing Advance subheader + /* This was done only when timing_advance_cmd != 31 + // now TA is always send when ta_timer resets regardless of its value + // this is done to avoid issues with the timeAlignmentTimer which is + // supposed to monitor if the UE received TA or not */ + if (gNB->ta_len) { + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_TA_COMMAND; + //last_size = 1; + mac_pdu_ptr++; + // TA MAC CE (1 octet) + timing_advance_cmd = gNB->ta_command; + AssertFatal(timing_advance_cmd < 64, "timing_advance_cmd %d > 63\n", timing_advance_cmd); + ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND = timing_advance_cmd; //(timing_advance_cmd+31)&0x3f; - // DRX command subheader (MAC CE size 0) - if (drx_cmd != 255) { - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_DRX; - //last_size = 1; - mac_pdu_ptr++; + if (gNB->tag->tag_Id != 0) { + tag_id = gNB->tag->tag_Id; + ((NR_MAC_CE_TA *) ce_ptr)->TAGID = tag_id; } - // Timing Advance subheader - /* This was done only when timing_advance_cmd != 31 - // now TA is always send when ta_timer resets regardless of its value - // this is done to avoid issues with the timeAlignmentTimer which is - // supposed to monitor if the UE received TA or not */ - if (gNB->ta_len) { - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_TA_COMMAND; - //last_size = 1; - mac_pdu_ptr++; + LOG_D(MAC, "NR MAC CE timing advance command = %d (%d) TAG ID = %d\n", timing_advance_cmd, ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND, tag_id); + mac_ce_size = sizeof(NR_MAC_CE_TA); + // Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); + ce_ptr += mac_ce_size; + mac_pdu_ptr += (unsigned char) mac_ce_size; + } - // TA MAC CE (1 octet) - timing_advance_cmd = gNB->ta_command; - AssertFatal(timing_advance_cmd < 64, "timing_advance_cmd %d > 63\n", timing_advance_cmd); - ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND = timing_advance_cmd; //(timing_advance_cmd+31)&0x3f; - if (gNB->tag->tag_Id != 0) { - tag_id = gNB->tag->tag_Id; - ((NR_MAC_CE_TA *) ce_ptr)->TAGID = tag_id; - } + // Contention resolution fixed subheader and MAC CE + if (ue_cont_res_id) { + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_CON_RES_ID; + mac_pdu_ptr++; + //last_size = 1; + // contention resolution identity MAC ce has a fixed 48 bit size + // this contains the UL CCCH SDU. If UL CCCH SDU is longer than 48 bits, + // it contains the first 48 bits of the UL CCCH SDU + LOG_T(MAC, "[gNB ][RAPROC] Generate contention resolution msg: %x.%x.%x.%x.%x.%x\n", + ue_cont_res_id[0], ue_cont_res_id[1], ue_cont_res_id[2], + ue_cont_res_id[3], ue_cont_res_id[4], ue_cont_res_id[5]); + // Copying bytes (6 octects) to CEs pointer + mac_ce_size = 6; + memcpy(ce_ptr, ue_cont_res_id, mac_ce_size); + // Copying bytes for MAC CEs to mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); + ce_ptr += mac_ce_size; + mac_pdu_ptr += (unsigned char) mac_ce_size; + } - LOG_D(MAC, "NR MAC CE timing advance command = %d (%d) TAG ID = %d\n", timing_advance_cmd, ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND, tag_id); + //TS 38.321 Sec 6.1.3.15 TCI State indication for UE Specific PDCCH MAC CE SubPDU generation + if (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.is_scheduled) { + //filling subheader + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_TCI_STATE_IND_UE_SPEC_PDCCH; + mac_pdu_ptr++; + //Creating the instance of CE structure + NR_TCI_PDCCH nr_UESpec_TCI_StateInd_PDCCH; + //filling the CE structre + nr_UESpec_TCI_StateInd_PDCCH.CoresetId1 = ((ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0xF) >> 1; //extracting MSB 3 bits from LS nibble + nr_UESpec_TCI_StateInd_PDCCH.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.servingCellId) & 0x1F; //extracting LSB 5 Bits + nr_UESpec_TCI_StateInd_PDCCH.TciStateId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.tciStateId) & 0x7F; //extracting LSB 7 bits + nr_UESpec_TCI_StateInd_PDCCH.CoresetId2 = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0x1; //extracting LSB 1 bit + LOG_D(MAC, "NR MAC CE TCI state indication for UE Specific PDCCH = %d \n", nr_UESpec_TCI_StateInd_PDCCH.TciStateId); + mac_ce_size = sizeof(NR_TCI_PDCCH); + // Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)&nr_UESpec_TCI_StateInd_PDCCH, mac_ce_size); + //incrementing the PDU pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + } - mac_ce_size = sizeof(NR_MAC_CE_TA); + //TS 38.321 Sec 6.1.3.16, SP CSI reporting on PUCCH Activation/Deactivation MAC CE + if (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.is_scheduled) { + //filling the subheader + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_REP_PUCCH_ACT; + mac_pdu_ptr++; + //creating the instance of CE structure + NR_PUCCH_CSI_REPORTING nr_PUCCH_CSI_reportingActDeact; + //filling the CE structure + nr_PUCCH_CSI_reportingActDeact.BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.bwpId) & 0x3; //extracting LSB 2 bibs + nr_PUCCH_CSI_reportingActDeact.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.servingCellId) & 0x1F; //extracting LSB 5 bits + nr_PUCCH_CSI_reportingActDeact.S0 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[0]; + nr_PUCCH_CSI_reportingActDeact.S1 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[1]; + nr_PUCCH_CSI_reportingActDeact.S2 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[2]; + nr_PUCCH_CSI_reportingActDeact.S3 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[3]; + nr_PUCCH_CSI_reportingActDeact.R2 = 0; + mac_ce_size = sizeof(NR_PUCCH_CSI_REPORTING); + // Copying MAC CE data to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)&nr_PUCCH_CSI_reportingActDeact, mac_ce_size); + //incrementing the PDU pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + } - // Copying bytes for MAC CEs to the mac pdu pointer - memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); - ce_ptr += mac_ce_size; - mac_pdu_ptr += (unsigned char) mac_ce_size; + //TS 38.321 Sec 6.1.3.14, TCI State activation/deactivation for UE Specific PDSCH MAC CE + if (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.is_scheduled) { + //Computing the number of octects to be allocated for Flexible array member + //of MAC CE structure + uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.highestTciStateActivated) / 8 + 1; //Calculating the number of octects for allocating the memory + //filling the subheader + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_TCI_STATE_ACT_UE_SPEC_PDSCH; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + last_size = 2; + //Incrementing the PDU pointer + mac_pdu_ptr += last_size; + //allocating memory for CE Structure + NR_TCI_PDSCH_APERIODIC_CSI *nr_UESpec_TCI_StateInd_PDSCH = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //initializing to zero + memset((void *)nr_UESpec_TCI_StateInd_PDSCH, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //filling the CE Structure + nr_UESpec_TCI_StateInd_PDSCH->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.bwpId) & 0x3; //extracting LSB 2 Bits + nr_UESpec_TCI_StateInd_PDSCH->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.servingCellId) & 0x1F; //extracting LSB 5 bits + + for(i = 0; i < (num_octects * 8); i++) { + if(ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.tciStateActDeact[i]) + nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] = nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] | (1 << (i % 8)); } - // Contention resolution fixed subheader and MAC CE - if (ue_cont_res_id) { - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_CON_RES_ID; - mac_pdu_ptr++; - //last_size = 1; + mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + //Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)nr_UESpec_TCI_StateInd_PDSCH, mac_ce_size); + //incrementing the mac pdu pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + //freeing the allocated memory + free(nr_UESpec_TCI_StateInd_PDSCH); + } - // contention resolution identity MAC ce has a fixed 48 bit size - // this contains the UL CCCH SDU. If UL CCCH SDU is longer than 48 bits, - // it contains the first 48 bits of the UL CCCH SDU - LOG_T(MAC, "[gNB ][RAPROC] Generate contention resolution msg: %x.%x.%x.%x.%x.%x\n", - ue_cont_res_id[0], ue_cont_res_id[1], ue_cont_res_id[2], - ue_cont_res_id[3], ue_cont_res_id[4], ue_cont_res_id[5]); + //TS38.321 Sec 6.1.3.13 Aperiodic CSI Trigger State Subselection MAC CE + if (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.is_scheduled) { + //Computing the number of octects to be allocated for Flexible array member + //of MAC CE structure + uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.highestTriggerStateSelected) / 8 + 1; //Calculating the number of octects for allocating the memory + //filling the subheader + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_APERIODIC_CSI_TRI_STATE_SUBSEL; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + last_size = 2; + //Incrementing the PDU pointer + mac_pdu_ptr += last_size; + //allocating memory for CE structure + NR_TCI_PDSCH_APERIODIC_CSI *nr_Aperiodic_CSI_Trigger = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //initializing to zero + memset((void *)nr_Aperiodic_CSI_Trigger, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //filling the CE Structure + nr_Aperiodic_CSI_Trigger->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.bwpId) & 0x3; //extracting LSB 2 bits + nr_Aperiodic_CSI_Trigger->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.servingCellId) & 0x1F; //extracting LSB 5 bits + nr_Aperiodic_CSI_Trigger->R = 0; - // Copying bytes (6 octects) to CEs pointer - mac_ce_size = 6; - memcpy(ce_ptr, ue_cont_res_id, mac_ce_size); - - // Copying bytes for MAC CEs to mac pdu pointer - memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); - ce_ptr += mac_ce_size; - mac_pdu_ptr += (unsigned char) mac_ce_size; + for(i = 0; i < (num_octects * 8); i++) { + if(ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.triggerStateSelection[i]) + nr_Aperiodic_CSI_Trigger->T[i / 8] = nr_Aperiodic_CSI_Trigger->T[i / 8] | (1 << (i % 8)); } -#ifdef GES_SUPPORT + mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + // Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)nr_Aperiodic_CSI_Trigger, mac_ce_size); + //incrementing the mac pdu pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + //freeing the allocated memory + free(nr_Aperiodic_CSI_Trigger); + } - //TS 38.321 Sec 6.1.3.15 TCI State indication for UE Specific PDCCH MAC CE SubPDU generation - if (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.is_scheduled) { - //filling subheader - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_TCI_STATE_IND_UE_SPEC_PDCCH; - mac_pdu_ptr++; - //Creating the instance of CE structure - NR_TCI_PDCCH nr_UESpec_TCI_StateInd_PDCCH; - //filling the CE structre - nr_UESpec_TCI_StateInd_PDCCH.CoresetId1 = ((ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0xF) >> 1; //extracting MSB 3 bits from LS nibble - nr_UESpec_TCI_StateInd_PDCCH.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.servingCellId) & 0x1F; //extracting LSB 5 Bits - nr_UESpec_TCI_StateInd_PDCCH.TciStateId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.tciStateId) & 0x7F; //extracting LSB 7 bits - nr_UESpec_TCI_StateInd_PDCCH.CoresetId2 = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0x1; //extracting LSB 1 bit - LOG_D(MAC, "NR MAC CE TCI state indication for UE Specific PDCCH = %d \n", nr_UESpec_TCI_StateInd_PDCCH.TciStateId); - mac_ce_size = sizeof(NR_TCI_PDCCH); - // Copying bytes for MAC CEs to the mac pdu pointer - memcpy((void *) mac_pdu_ptr, (void *)&nr_UESpec_TCI_StateInd_PDCCH, mac_ce_size); - //incrementing the PDU pointer - mac_pdu_ptr += (unsigned char) mac_ce_size; - } + if (ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.is_scheduled) { + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_SP_ZP_CSI_RS_RES_SET_ACT; + mac_pdu_ptr++; + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->A_D = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.act_deact; + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CELLID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id & 0x1F; //5 bits + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->BWPID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid & 0x3; //2 bits + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CSIRS_RSC_ID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id & 0xF; //4 bits + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->R = 0; + LOG_D(MAC, "NR MAC CE of ZP CSIRS Serv cell ID = %d BWPID= %d Rsc set ID = %d\n", ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id, ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid, + ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id); + mac_ce_size = sizeof(NR_MAC_CE_SP_ZP_CSI_RS_RES_SET); + mac_pdu_ptr += (unsigned char) mac_ce_size; + } - //TS 38.321 Sec 6.1.3.16, SP CSI reporting on PUCCH Activation/Deactivation MAC CE - if (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.is_scheduled) { - //filling the subheader - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_REP_PUCCH_ACT; - mac_pdu_ptr++; - //creating the instance of CE structure - NR_PUCCH_CSI_REPORTING nr_PUCCH_CSI_reportingActDeact; - //filling the CE structure - nr_PUCCH_CSI_reportingActDeact.BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.bwpId) & 0x3; //extracting LSB 2 bibs - nr_PUCCH_CSI_reportingActDeact.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.servingCellId) & 0x1F; //extracting LSB 5 bits - nr_PUCCH_CSI_reportingActDeact.S0 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[0]; - nr_PUCCH_CSI_reportingActDeact.S1 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[1]; - nr_PUCCH_CSI_reportingActDeact.S2 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[2]; - nr_PUCCH_CSI_reportingActDeact.S3 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[3]; - nr_PUCCH_CSI_reportingActDeact.R2 = 0; - mac_ce_size = sizeof(NR_PUCCH_CSI_REPORTING); - // Copying MAC CE data to the mac pdu pointer - memcpy((void *) mac_pdu_ptr, (void *)&nr_PUCCH_CSI_reportingActDeact, mac_ce_size); - //incrementing the PDU pointer - mac_pdu_ptr += (unsigned char) mac_ce_size; - } - - //TS 38.321 Sec 6.1.3.14, TCI State activation/deactivation for UE Specific PDSCH MAC CE - if (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.is_scheduled) { - //Computing the number of octects to be allocated for Flexible array member - //of MAC CE structure - uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.highestTciStateActivated) / 8 + 1; //Calculating the number of octects for allocating the memory - - //filling the subheader - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_TCI_STATE_ACT_UE_SPEC_PDSCH; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); - last_size = 2; - //Incrementing the PDU pointer - mac_pdu_ptr += last_size; - //allocating memory for CE Structure - NR_TCI_PDSCH_APERIODIC_CSI *nr_UESpec_TCI_StateInd_PDSCH = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); - //initializing to zero - memset((void *)nr_UESpec_TCI_StateInd_PDSCH, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); - //filling the CE Structure - nr_UESpec_TCI_StateInd_PDSCH->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.bwpId) & 0x3; //extracting LSB 2 Bits - nr_UESpec_TCI_StateInd_PDSCH->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.servingCellId) & 0x1F; //extracting LSB 5 bits - for(i = 0; i < (num_octects * 8); i++) { - if(ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.tciStateActDeact[i]) - nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] = nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] | (1 << (i % 8)); - } - mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); - //Copying bytes for MAC CEs to the mac pdu pointer - memcpy((void *) mac_pdu_ptr, (void *)nr_UESpec_TCI_StateInd_PDSCH, mac_ce_size); - //incrementing the mac pdu pointer - mac_pdu_ptr += (unsigned char) mac_ce_size; - //freeing the allocated memory - free(nr_UESpec_TCI_StateInd_PDSCH); - } - - //TS38.321 Sec 6.1.3.13 Aperiodic CSI Trigger State Subselection MAC CE - if (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.is_scheduled) { - //Computing the number of octects to be allocated for Flexible array member - //of MAC CE structure - uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.highestTriggerStateSelected) / 8 + 1; //Calculating the number of octects for allocating the memory - - //filling the subheader - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_APERIODIC_CSI_TRI_STATE_SUBSEL; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); - last_size = 2; - //Incrementing the PDU pointer - mac_pdu_ptr += last_size; - //allocating memory for CE structure - NR_TCI_PDSCH_APERIODIC_CSI *nr_Aperiodic_CSI_Trigger = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); - //initializing to zero - memset((void *)nr_Aperiodic_CSI_Trigger, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); - //filling the CE Structure - nr_Aperiodic_CSI_Trigger->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.bwpId) & 0x3; //extracting LSB 2 bits - nr_Aperiodic_CSI_Trigger->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.servingCellId) & 0x1F; //extracting LSB 5 bits - nr_Aperiodic_CSI_Trigger->R = 0; - for(i = 0; i < (num_octects * 8); i++) { - if(ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.triggerStateSelection[i]) - nr_Aperiodic_CSI_Trigger->T[i / 8] = nr_Aperiodic_CSI_Trigger->T[i / 8] | (1 << (i % 8)); - } - mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); - // Copying bytes for MAC CEs to the mac pdu pointer - memcpy((void *) mac_pdu_ptr, (void *)nr_Aperiodic_CSI_Trigger, mac_ce_size); - //incrementing the mac pdu pointer - mac_pdu_ptr += (unsigned char) mac_ce_size; - //freeing the allocated memory - free(nr_Aperiodic_CSI_Trigger); - } - - if (ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.is_scheduled) { - ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_SP_ZP_CSI_RS_RES_SET_ACT; - mac_pdu_ptr++; - ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->A_D = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.act_deact; - ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CELLID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id & 0x1F; //5 bits - ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->BWPID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid & 0x3; //2 bits - ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CSIRS_RSC_ID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id & 0xF; //4 bits - ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->R = 0; - LOG_D(MAC, "NR MAC CE of ZP CSIRS Serv cell ID = %d BWPID= %d Rsc set ID = %d\n", ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id, ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid, ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id); - mac_ce_size = sizeof(NR_MAC_CE_SP_ZP_CSI_RS_RES_SET); - mac_pdu_ptr += (unsigned char) mac_ce_size; - } - - if (ue_sched_ctl->UE_mac_ce_ctrl.csi_im.is_scheduled) { - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT; - mac_pdu_ptr++; - CSI_RS_CSI_IM_ACT_DEACT_MAC_CE csi_rs_im_act_deact_ce; - csi_rs_im_act_deact_ce.A_D = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.act_deact; - csi_rs_im_act_deact_ce.SCID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.serv_cellid & 0x3F;//gNB_PHY -> ssb_pdu.ssb_pdu_rel15.PhysCellId; - csi_rs_im_act_deact_ce.BWP_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.bwp_id; - csi_rs_im_act_deact_ce.R1 = 0; - csi_rs_im_act_deact_ce.IM = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.im;// IF set CSI IM Rsc id will presesent else CSI IM RSC ID is abscent - csi_rs_im_act_deact_ce.SP_CSI_RSID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nzp_csi_rsc_id; - - if ( csi_rs_im_act_deact_ce.IM ) { //is_scheduled if IM is 1 else this field will not present - csi_rs_im_act_deact_ce.R2 = 0; - csi_rs_im_act_deact_ce.SP_CSI_IMID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.csi_im_rsc_id; - mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE ); - } else { - mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE ) - 1; - } - - memcpy ((void *) mac_pdu_ptr, (void *) & ( csi_rs_im_act_deact_ce), mac_ce_size); - mac_pdu_ptr += (unsigned char) mac_ce_size; - - if (csi_rs_im_act_deact_ce.A_D ) { //Following IE is_scheduled only if A/D is 1 - mac_ce_size = sizeof ( struct TCI_S); - - for ( i = 0; i < ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nb_tci_resource_set_id; i++) { - csi_rs_im_act_deact_ce.TCI_STATE.R = 0; - csi_rs_im_act_deact_ce.TCI_STATE.TCI_STATE_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.tci_state_id [i] & 0x7F; - memcpy ((void *) mac_pdu_ptr, (void *) & (csi_rs_im_act_deact_ce.TCI_STATE), mac_ce_size); - mac_pdu_ptr += (unsigned char) mac_ce_size; - } - - } - } - -#endif - - // 2) Generation of DLSCH MAC subPDUs including subheaders and MAC SDUs - for (i = 0; i < num_sdus; i++) { - LOG_D(MAC, "[gNB] Generate DLSCH header num sdu %d len sdu %d\n", num_sdus, sdu_lengths[i]); - - if (sdu_lengths[i] < 128) { - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = sdu_lcids[i]; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = (unsigned char) sdu_lengths[i]; - last_size = 2; - } else { - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->F = 1; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->LCID = sdu_lcids[i]; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L1 = ((unsigned short) sdu_lengths[i] >> 8) & 0x7f; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L2 = (unsigned short) sdu_lengths[i] & 0xff; - last_size = 3; - } - - mac_pdu_ptr += last_size; - - // 3) cycle through SDUs, compute each relevant and place dlsch_buffer in - memcpy((void *) mac_pdu_ptr, (void *) dlsch_buffer_ptr, sdu_lengths[i]); - dlsch_buffer_ptr += sdu_lengths[i]; - mac_pdu_ptr += sdu_lengths[i]; - } - - // 4) Compute final offset for padding - if (post_padding > 0) { - ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_PADDING; - mac_pdu_ptr++; + if (ue_sched_ctl->UE_mac_ce_ctrl.csi_im.is_scheduled) { + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT; + mac_pdu_ptr++; + CSI_RS_CSI_IM_ACT_DEACT_MAC_CE csi_rs_im_act_deact_ce; + csi_rs_im_act_deact_ce.A_D = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.act_deact; + csi_rs_im_act_deact_ce.SCID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.serv_cellid & 0x3F;//gNB_PHY -> ssb_pdu.ssb_pdu_rel15.PhysCellId; + csi_rs_im_act_deact_ce.BWP_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.bwp_id; + csi_rs_im_act_deact_ce.R1 = 0; + csi_rs_im_act_deact_ce.IM = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.im;// IF set CSI IM Rsc id will presesent else CSI IM RSC ID is abscent + csi_rs_im_act_deact_ce.SP_CSI_RSID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nzp_csi_rsc_id; + if ( csi_rs_im_act_deact_ce.IM ) { //is_scheduled if IM is 1 else this field will not present + csi_rs_im_act_deact_ce.R2 = 0; + csi_rs_im_act_deact_ce.SP_CSI_IMID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.csi_im_rsc_id; + mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE ); } else { - // no MAC subPDU with padding + mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE ) - 1; } - // compute final offset - offset = ((unsigned char *) mac_pdu_ptr - mac_pdu); + memcpy ((void *) mac_pdu_ptr, (void *) & ( csi_rs_im_act_deact_ce), mac_ce_size); + mac_pdu_ptr += (unsigned char) mac_ce_size; - //printf("Offset %d \n", ((unsigned char *) mac_pdu_ptr - mac_pdu)); + if (csi_rs_im_act_deact_ce.A_D ) { //Following IE is_scheduled only if A/D is 1 + mac_ce_size = sizeof ( struct TCI_S); - return offset; + for ( i = 0; i < ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nb_tci_resource_set_id; i++) { + csi_rs_im_act_deact_ce.TCI_STATE.R = 0; + csi_rs_im_act_deact_ce.TCI_STATE.TCI_STATE_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.tci_state_id [i] & 0x7F; + memcpy ((void *) mac_pdu_ptr, (void *) & (csi_rs_im_act_deact_ce.TCI_STATE), mac_ce_size); + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + } + } + + // 2) Generation of DLSCH MAC subPDUs including subheaders and MAC SDUs + for (i = 0; i < num_sdus; i++) { + LOG_D(MAC, "[gNB] Generate DLSCH header num sdu %d len sdu %d\n", num_sdus, sdu_lengths[i]); + + if (sdu_lengths[i] < 128) { + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = sdu_lcids[i]; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = (unsigned char) sdu_lengths[i]; + last_size = 2; + } else { + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->F = 1; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->LCID = sdu_lcids[i]; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L1 = ((unsigned short) sdu_lengths[i] >> 8) & 0x7f; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L2 = (unsigned short) sdu_lengths[i] & 0xff; + last_size = 3; + } + + mac_pdu_ptr += last_size; + // 3) cycle through SDUs, compute each relevant and place dlsch_buffer in + memcpy((void *) mac_pdu_ptr, (void *) dlsch_buffer_ptr, sdu_lengths[i]); + dlsch_buffer_ptr += sdu_lengths[i]; + mac_pdu_ptr += sdu_lengths[i]; + } + + // 4) Compute final offset for padding + if (post_padding > 0) { + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_PADDING; + mac_pdu_ptr++; + } else { + // no MAC subPDU with padding + } + + // compute final offset + offset = ((unsigned char *) mac_pdu_ptr - mac_pdu); + //printf("Offset %d \n", ((unsigned char *) mac_pdu_ptr - mac_pdu)); + return offset; } /* functionalities of this function have been moved to nr_schedule_uss_dlsch_phytest */ diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index bea14ed406..53308406a2 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -244,8 +244,6 @@ typedef struct UE_info { pdschTciStatesActDeact_t pdsch_TCI_States_ActDeact; } NR_UE_mac_ce_ctrl_t; -typedef struct NR_sched_pucch { - int frame; int ul_slot; uint8_t dai_c; uint8_t timing_indicator; From 0e3d87b44cf4ec1bdd0a34008e766d3516129b72 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Sun, 14 Jun 2020 23:10:12 +0200 Subject: [PATCH 321/553] format 2 up to 64 bits tested for 8 and 16 PRBs PUCCH format --- .../nfapi/public_inc/nfapi_nr_interface_scf.h | 6 +- openair1/PHY/CODING/nr_polar_init.c | 12 +- openair1/PHY/NR_TRANSPORT/pucch_rx.c | 207 +++++++++++++++--- openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c | 22 +- openair1/PHY/defs_gNB.h | 2 + openair1/SIMULATION/NR_PHY/pucchsim.c | 22 +- 6 files changed, 225 insertions(+), 46 deletions(-) diff --git a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h index 54b592202d..f4f06c1937 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h @@ -1498,7 +1498,7 @@ typedef struct //for dci_pusch_pdu typedef struct { - uint8_t pdu_bit_map; + uint8_t pduBitmap; uint32_t handle; uint16_t rnti; uint8_t ul_cqi; @@ -1513,7 +1513,7 @@ typedef struct //for PUCCH PDU Format 0/1 typedef struct { - uint8_t pdu_bit_map; + uint8_t pduBitmap; uint32_t handle; uint16_t rnti; uint8_t pucch_format;//PUCCH format Value: 0 -> 1 0: PUCCH Format0 1: PUCCH Format1 @@ -1529,7 +1529,7 @@ typedef struct //PUCCH PDU Format 2/3/4 typedef struct { - uint8_t pdu_bit_map; + uint8_t pduBitmap; uint32_t handle; uint16_t rnti; uint8_t pucch_format;//PUCCH format Value: 0 -> 2 0: PUCCH Format2 1: PUCCH Format3 2: PUCCH Format4 diff --git a/openair1/PHY/CODING/nr_polar_init.c b/openair1/PHY/CODING/nr_polar_init.c index 571201cf13..55bdedbc33 100644 --- a/openair1/PHY/CODING/nr_polar_init.c +++ b/openair1/PHY/CODING/nr_polar_init.c @@ -43,11 +43,12 @@ static void nr_polar_init(t_nrPolar_params * *polarParams, uint8_t aggregation_level, int decoder_flag) { t_nrPolar_params *currentPtr = *polarParams; - uint16_t aggregation_prime = nr_polar_aggregation_prime(aggregation_level); + uint16_t aggregation_prime = (messageType >= 2) ? aggregation_level : nr_polar_aggregation_prime(aggregation_level); //Parse the list. If the node is already created, return without initialization. while (currentPtr != NULL) { //printf("currentPtr->idx %d, (%d,%d)\n",currentPtr->idx,currentPtr->payloadBits,currentPtr->encoderLength); + LOG_D(PHY,"Looking for index %d\n",(messageType * messageLength * aggregation_prime)); if (currentPtr->idx == (messageType * messageLength * aggregation_prime)) return; else currentPtr = currentPtr->nextPtr; } @@ -57,6 +58,7 @@ static void nr_polar_init(t_nrPolar_params * *polarParams, t_nrPolar_params *newPolarInitNode = calloc(sizeof(t_nrPolar_params),1); if (newPolarInitNode != NULL) { + LOG_D(PHY,"Setting new polarParams index %d, messageType %d, messageLength %d, aggregation_prime %d\n",(messageType * messageLength * aggregation_prime),messageType,messageLength,aggregation_prime); newPolarInitNode->idx = (messageType * messageLength * aggregation_prime); newPolarInitNode->nextPtr = NULL; //printf("newPolarInitNode->idx %d, (%d,%d,%d:%d)\n",newPolarInitNode->idx,messageType,messageLength,aggregation_prime,aggregation_level); @@ -116,6 +118,7 @@ static void nr_polar_init(t_nrPolar_params * *polarParams, newPolarInitNode->payloadBits = messageLength; newPolarInitNode->crcCorrectionBits = NR_POLAR_PUCCH_CRC_ERROR_CORRECTION_BITS; //newPolarInitNode->crc_generator_matrix=crc24c_generator_matrix(newPolarInitNode->payloadBits+newPolarInitNode->crcParityBits);//G_P + LOG_D(PHY,"New polar node, encoderLength %d, aggregation_level %d\n",newPolarInitNode->encoderLength,aggregation_level); } else { AssertFatal(1 == 0, "[nr_polar_init] Incorrect Message Type(%d)", messageType); } @@ -219,16 +222,19 @@ t_nrPolar_params *nr_polar_params (int8_t messageType, nr_polar_init(polarList_ext != NULL ? polarList_ext : &polarList, messageType,messageLength,aggregation_level,decoding_flag); t_nrPolar_params *polarParams=polarList_ext != NULL ? *polarList_ext : polarList; - const int tag=messageType * messageLength * nr_polar_aggregation_prime(aggregation_level); + const int tag=messageType * messageLength * (messageType>=2 ? aggregation_level : nr_polar_aggregation_prime(aggregation_level)); + + while (polarParams != NULL) { + LOG_D(PHY,"nr_polar_params : tag %d (from nr_polar_init %d)\n",tag,polarParams->idx); if (polarParams->idx == tag) return polarParams; polarParams = polarParams->nextPtr; } - AssertFatal(false,"Polar Init tables internal failure\n"); + AssertFatal(false,"Polar Init tables internal failure, no polarParams found\n"); return NULL; } diff --git a/openair1/PHY/NR_TRANSPORT/pucch_rx.c b/openair1/PHY/NR_TRANSPORT/pucch_rx.c index e68b495e95..d34f7bf540 100644 --- a/openair1/PHY/NR_TRANSPORT/pucch_rx.c +++ b/openair1/PHY/NR_TRANSPORT/pucch_rx.c @@ -50,7 +50,7 @@ #include "T.h" -#define DEBUG_NR_PUCCH_RX 1 +//#define DEBUG_NR_PUCCH_RX 1 int get_pucch0_cs_lut_index(PHY_VARS_gNB *gNB,nfapi_nr_pucch_pdu_t* pucch_pdu) { @@ -326,7 +326,7 @@ void nr_decode_pucch0(PHY_VARS_gNB *gNB, index=maxpos; #endif // first bit of bitmap for sr presence and second bit for acknack presence - uci_pdu->pdu_bit_map = pucch_pdu->sr_flag | ((pucch_pdu->bit_len_harq>0)<<1); + uci_pdu->pduBitmap = pucch_pdu->sr_flag | ((pucch_pdu->bit_len_harq>0)<<1); uci_pdu->pucch_format = 0; // format 0 uci_pdu->ul_cqi = 0xff; // currently not valid uci_pdu->timing_advance = 0xffff; // currently not valid @@ -872,6 +872,7 @@ __m256i *pucch2_lut[9]={pucch2_3bit, pucch2_11bit}; __m64 pucch2_polar_4bit[16]; +__m128i pucch2_polar_llr_num_lut[256],pucch2_polar_llr_den_lut[256]; void init_pucch2_luts() { @@ -964,6 +965,50 @@ void init_pucch2_luts() { bit = (i&0x8) > 0 ? -1 : 1; *lut_i = _mm_insert_pi16(*lut_i,bit,3); } + for (int i=0;i<256;i++) { + __m128i *lut_num_i=&pucch2_polar_llr_num_lut[i]; + __m128i *lut_den_i=&pucch2_polar_llr_den_lut[i]; + bit = (i&0x1) > 0 ? 0 : 1; + *lut_num_i = _mm_insert_epi16(*lut_num_i,bit,0); + *lut_den_i = _mm_insert_epi16(*lut_den_i,1-bit,0); + + bit = (i&0x10) > 0 ? 0 : 1; + *lut_num_i = _mm_insert_epi16(*lut_num_i,bit,1); + *lut_den_i = _mm_insert_epi16(*lut_den_i,1-bit,1); + + bit = (i&0x2) > 0 ? 0 : 1; + *lut_num_i = _mm_insert_epi16(*lut_num_i,bit,2); + *lut_den_i = _mm_insert_epi16(*lut_den_i,1-bit,2); + + bit = (i&0x20) > 0 ? 0 : 1; + *lut_num_i = _mm_insert_epi16(*lut_num_i,bit,3); + *lut_den_i = _mm_insert_epi16(*lut_den_i,1-bit,3); + + bit = (i&0x4) > 0 ? 0 : 1; + *lut_num_i = _mm_insert_epi16(*lut_num_i,bit,4); + *lut_den_i = _mm_insert_epi16(*lut_den_i,1-bit,4); + + bit = (i&0x40) > 0 ? 0 : 1; + *lut_num_i = _mm_insert_epi16(*lut_num_i,bit,5); + *lut_den_i = _mm_insert_epi16(*lut_den_i,1-bit,5); + + bit = (i&0x8) > 0 ? 0 : 1; + *lut_num_i = _mm_insert_epi16(*lut_num_i,bit,6); + *lut_den_i = _mm_insert_epi16(*lut_den_i,1-bit,6); + + bit = (i&0x80) > 0 ? 0 : 1; + *lut_num_i = _mm_insert_epi16(*lut_num_i,bit,7); + *lut_den_i = _mm_insert_epi16(*lut_den_i,1-bit,7); + printf("i %d, lut_num (%d,%d,%d,%d,%d,%d,%d,%d)\n",i, + ((int16_t *)lut_num_i)[0], + ((int16_t *)lut_num_i)[1], + ((int16_t *)lut_num_i)[2], + ((int16_t *)lut_num_i)[3], + ((int16_t *)lut_num_i)[4], + ((int16_t *)lut_num_i)[5], + ((int16_t *)lut_num_i)[6], + ((int16_t *)lut_num_i)[7]); + } } @@ -976,6 +1021,8 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB, NR_DL_FRAME_PARMS *frame_parms = &gNB->frame_parms; pucch_GroupHopping_t pucch_GroupHopping = pucch_pdu->group_hop_flag + (pucch_pdu->sequence_hop_flag<<1); + + AssertFatal(pucch_pdu->nr_of_symbols==1 || pucch_pdu->nr_of_symbols==2, "Illegal number of symbols for PUCCH 2 %d\n",pucch_pdu->nr_of_symbols); @@ -1291,10 +1338,12 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB, printf("\n"); #endif } - AssertFatal(pucch_pdu->bit_len_csi_part1 + pucch_pdu->bit_len_csi_part2 == 0,"no csi for now\n"); - AssertFatal((pucch_pdu->bit_len_harq+pucch_pdu->sr_flag > 2 ) && (pucch_pdu->bit_len_harq+pucch_pdu->sr_flag < 65),"illegal length (%d,%d)\n",pucch_pdu->bit_len_harq,pucch_pdu->sr_flag); - int nb_bit = pucch_pdu->bit_len_harq+pucch_pdu->sr_flag; + int nb_bit = pucch_pdu->bit_len_harq+pucch_pdu->sr_flag+pucch_pdu->bit_len_csi_part1+pucch_pdu->bit_len_csi_part2; + AssertFatal(nb_bit > 2 && nb_bit< 65,"illegal length (%d : %d,%d,%d,%d)\n",nb_bit,pucch_pdu->bit_len_harq,pucch_pdu->sr_flag,pucch_pdu->bit_len_csi_part1,pucch_pdu->bit_len_csi_part2); + uint64_t decodedPayload[2]; + uint8_t corr_dB; + int decoderState=2; if (nb_bit < 12) { // short blocklength case __m256i *rp_re[Prx2]; __m256i *rp2_re[Prx2]; @@ -1371,31 +1420,19 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB, cw_ML=cw; } } - uint8_t corr_dB = dB_fixed64((uint64_t)corr); + corr_dB = dB_fixed64((uint64_t)corr); LOG_D(PHY,"cw_ML %d, metric %d dB\n",cw_ML,corr_dB); - uci_pdu->harq.harq_bit_len = pucch_pdu->bit_len_harq; - - - int harq_bytes=pucch_pdu->bit_len_harq>>3; - if ((pucch_pdu->bit_len_harq&7) > 0) harq_bytes++; - uci_pdu->harq.harq_payload = (nfapi_nr_harq_t*)malloc(harq_bytes); - uci_pdu->harq.harq_crc = 2; - for (int i=0;iharq.harq_payload[i] = cw_ML & 255; - cw_ML>>=8; - } - - if (pucch_pdu->sr_flag == 1) { - uci_pdu->sr.sr_bit_len = 1; - uci_pdu->sr.sr_payload = malloc(1); - uci_pdu->sr.sr_payload[0] = cw_ML; - } + decodedPayload[0]=(uint64_t)cw_ML; } else { // polar coded case + + t_nrPolar_params *currentPtr = nr_polar_params(2,nb_bit,pucch_pdu->prb_size,1,&gNB->uci_polarParams); __m64 *rp_re[Prx2]; __m64 *rp2_re[Prx2]; __m64 *rp_im[Prx2]; __m64 *rp2_im[Prx2]; + __m128i llrs[pucch_pdu->prb_size*2]; + for (int aa=0;aa>1]); } printf("\n"); + } #endif - } // non-coherent LLR computation on groups of 4 REs (half-PRBs) int32_t corr_re,corr_im,corr_tmp; + __m128i corr16,llr_num,llr_den; + uint64_t corr; + for (int half_prb=0;half_prb<(2*pucch_pdu->prb_size);half_prb++) { + llr_num=_mm_set1_epi16(0);llr_den=_mm_set1_epi16(0); for (int cw=0;cw<256;cw++) { corr_tmp=0; for (int aa=0;aa>2][aa]*corr32_re[half_prb>>2][aa])+ + ((int64_t)corr32_im[half_prb>>2][aa]*corr32_im[half_prb>>2][aa]); + corr_re = ( corr32_re[half_prb>>2][aa]/(2*nc_group_size*4/2)+((int16_t*)(&prod_re[aa]))[0]); corr_im = ( corr32_im[half_prb>>2][aa]/(2*nc_group_size*4/2)+((int16_t*)(&prod_im[aa]))[0]); corr_tmp += corr_re*corr_re + corr_im*corr_im; + /* LOG_D(PHY,"pucch2 half_prb %d cw %d (%d,%d) aa %d: (%d,%d,%d,%d,%d,%d,%d,%d)x(%d,%d,%d,%d,%d,%d,%d,%d) (%d,%d)+(%d,%d) = (%d,%d) => %d\n", half_prb,cw,cw&15,cw>>4,aa, ((int16_t*)&pucch2_polar_4bit[cw&15])[0],((int16_t*)&pucch2_polar_4bit[cw>>4])[0], @@ -1450,11 +1497,115 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB, corr_re, corr_im, corr_tmp); + */ } + corr16 = _mm_set1_epi16((int16_t)(corr_tmp>>8)); + /* + LOG_D(PHY,"half_prb %d cw %d corr16 %d\n",half_prb,cw,corr_tmp>>8); + */ + llr_num = _mm_max_epi16(_mm_mullo_epi16(corr16,pucch2_polar_llr_num_lut[cw]),llr_num); + llr_den = _mm_max_epi16(_mm_mullo_epi16(corr16,pucch2_polar_llr_den_lut[cw]),llr_den); + /* + LOG_D(PHY,"lut_num (%d,%d,%d,%d,%d,%d,%d,%d)\n", + ((int16_t*)&pucch2_polar_llr_num_lut[cw])[0], + ((int16_t*)&pucch2_polar_llr_num_lut[cw])[1], + ((int16_t*)&pucch2_polar_llr_num_lut[cw])[2], + ((int16_t*)&pucch2_polar_llr_num_lut[cw])[3], + ((int16_t*)&pucch2_polar_llr_num_lut[cw])[4], + ((int16_t*)&pucch2_polar_llr_num_lut[cw])[5], + ((int16_t*)&pucch2_polar_llr_num_lut[cw])[6], + ((int16_t*)&pucch2_polar_llr_num_lut[cw])[7]); + + LOG_D(PHY,"llr_num (%d,%d,%d,%d,%d,%d,%d,%d)\n", + ((int16_t*)&llr_num)[0], + ((int16_t*)&llr_num)[1], + ((int16_t*)&llr_num)[2], + ((int16_t*)&llr_num)[3], + ((int16_t*)&llr_num)[4], + ((int16_t*)&llr_num)[5], + ((int16_t*)&llr_num)[6], + ((int16_t*)&llr_num)[7]); + LOG_D(PHY,"llr_den (%d,%d,%d,%d,%d,%d,%d,%d)\n", + ((int16_t*)&llr_den)[0], + ((int16_t*)&llr_den)[1], + ((int16_t*)&llr_den)[2], + ((int16_t*)&llr_den)[3], + ((int16_t*)&llr_den)[4], + ((int16_t*)&llr_den)[5], + ((int16_t*)&llr_den)[6], + ((int16_t*)&llr_den)[7]); + */ } + // compute llrs + llrs[half_prb] = _mm_subs_epi16(llr_num,llr_den); + LOG_D(PHY,"llrs[%d] : (%d,%d,%d,%d,%d,%d,%d,%d)\n", + half_prb, + ((int16_t*)&llrs[half_prb])[0], + ((int16_t*)&llrs[half_prb])[1], + ((int16_t*)&llrs[half_prb])[2], + ((int16_t*)&llrs[half_prb])[3], + ((int16_t*)&llrs[half_prb])[4], + ((int16_t*)&llrs[half_prb])[5], + ((int16_t*)&llrs[half_prb])[6], + ((int16_t*)&llrs[half_prb])[7]); } // half_prb - AssertFatal(1==0,"stopping here\n"); + // run polar decoder on llrs + decoderState = polar_decoder_int16((int16_t*)llrs, decodedPayload, 0, currentPtr); + LOG_D(PHY,"UCI decoderState %d, payload[0] %llux\n",decoderState,(unsigned long long)decodedPayload[0]); + if (decoderState>0) decoderState=1; + corr_dB = dB_fixed64(corr); + LOG_D(PHY,"metric %d dB\n",corr_dB); + } + uci_pdu->harq.harq_bit_len = pucch_pdu->bit_len_harq; + uci_pdu->pduBitmap=0; + uci_pdu->rnti=pucch_pdu->rnti; + uci_pdu->handle=pucch_pdu->handle; + uci_pdu->pucch_format=0; + uci_pdu->ul_cqi=corr_dB; + // need to fill these field! + uci_pdu->timing_advance=31; + uci_pdu->rssi=0; + if (pucch_pdu->bit_len_harq>0) { + int harq_bytes=pucch_pdu->bit_len_harq>>3; + if ((pucch_pdu->bit_len_harq&7) > 0) harq_bytes++; + uci_pdu->pduBitmap|=1; + uci_pdu->harq.harq_payload = (uint8_t*)malloc(harq_bytes); + uci_pdu->harq.harq_crc = decoderState > 0 ? 1 : 0; + int i=0; + for (;iharq.harq_payload[i] = decodedPayload[0] & 255; + decodedPayload[0]>>=8; + } + uci_pdu->harq.harq_payload[i] = decodedPayload[0] & ((1<<(pucch_pdu->bit_len_harq&7))-1); + decodedPayload[0] >>= pucch_pdu->bit_len_harq; + } + + if (pucch_pdu->sr_flag == 1) { + uci_pdu->pduBitmap|=2; + uci_pdu->sr.sr_bit_len = 1; + uci_pdu->sr.sr_payload = malloc(1); + uci_pdu->sr.sr_payload[0] = decodedPayload[0]&1; + decodedPayload[0]>>1; + } + // csi + if (pucch_pdu->bit_len_csi_part1>0) { + uci_pdu->pduBitmap|=4; + int csi_part1_bytes=pucch_pdu->bit_len_csi_part1>>3; + if ((pucch_pdu->bit_len_csi_part1&7) > 0) csi_part1_bytes++; + uci_pdu->csi_part1.csi_part1_payload = (uint8_t*)malloc(csi_part1_bytes); + uci_pdu->csi_part1.csi_part1_crc = decoderState > 0 ? 1 : 0; + int i=0; + for (;icsi_part1.csi_part1_payload[i] = decodedPayload[0] & 255; + decodedPayload[0]>>=8; + } + uci_pdu->csi_part1.csi_part1_payload[i] = decodedPayload[0] & ((1<<(pucch_pdu->bit_len_csi_part1&7))-1); + decodedPayload[0] >>= pucch_pdu->bit_len_csi_part1; + } + + if (pucch_pdu->bit_len_csi_part2>0) { + uci_pdu->pduBitmap|=8; + } - } // n_bit > 11 } diff --git a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c index 0e18b2f440..c7293c3a98 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c +++ b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c @@ -798,8 +798,8 @@ void nr_generate_pucch1_old(PHY_VARS_NR_UE *ue, } #endif //0 -inline void nr_pucch2_3_4_scrambling(uint16_t M_bit,uint16_t rnti,uint16_t n_id,uint32_t B,uint8_t *btilde) __attribute__((always_inline)); -inline void nr_pucch2_3_4_scrambling(uint16_t M_bit,uint16_t rnti,uint16_t n_id,uint32_t B,uint8_t *btilde) { +inline void nr_pucch2_3_4_scrambling(uint16_t M_bit,uint16_t rnti,uint16_t n_id,uint64_t *B64,uint8_t *btilde) __attribute__((always_inline)); +inline void nr_pucch2_3_4_scrambling(uint16_t M_bit,uint16_t rnti,uint16_t n_id,uint64_t *B64,uint8_t *btilde) { uint32_t x1, x2, s=0; int i; uint8_t c; @@ -807,14 +807,26 @@ inline void nr_pucch2_3_4_scrambling(uint16_t M_bit,uint16_t rnti,uint16_t n_id, //x2 = (rnti) + ((uint32_t)(1+nr_tti_tx)<<16)*(1+(fp->Nid_cell<<1)); x2 = ((rnti)<<15)+n_id; #ifdef DEBUG_NR_PUCCH_TX - printf("\t\t [nr_pucch2_3_4_scrambling] gold sequence s=%x\n",s); + printf("\t\t [nr_pucch2_3_4_scrambling] gold sequence s=%x, M_bit %d\n",s,M_bit); #endif uint8_t *btildep=btilde; int M_bit2=M_bit > 31 ? 32 : (M_bit&31), M_bit3=M_bit; + uint32_t B; for (int iprime=0;iprime<=(M_bit>>5);iprime++,btildep+=32) { s = lte_gold_generic(&x1, &x2, (iprime==0) ? 1 : 0); - + B=((uint32_t*)B64)[iprime]; + for (int n=0;n>n)&1, + (B>>(n+1))&1, + (B>>(n+2))&1, + (B>>(n+3))&1, + (B>>(n+4))&1, + (B>>(n+5))&1, + (B>>(n+6))&1, + (B>>(n+7))&1 + ); for (i=0; i>i)&1); btildep[i] = (((B>>i)&1) ^ c); @@ -946,7 +958,7 @@ void nr_generate_pucch2(PHY_VARS_NR_UE *ue, printf("\t [nr_generate_pucch2] start function at slot(nr_tti_tx)=%d with payload=%lu and nr_bit=%d\n",nr_tti_tx, payload, nr_bit); #endif // b is the block of bits transmitted on the physical channel after payload coding - uint64_t b; + uint64_t b[16]; // limit to 1024-bit encoded length // M_bit is the number of bits of block b (payload after encoding) uint16_t M_bit; nr_uci_encoding(payload,nr_bit,pucch_format2_nr,0,nrofSymbols,nrofPRB,1,0,0,&b,&M_bit); diff --git a/openair1/PHY/defs_gNB.h b/openair1/PHY/defs_gNB.h index aa794da818..10ba7c406b 100644 --- a/openair1/PHY/defs_gNB.h +++ b/openair1/PHY/defs_gNB.h @@ -667,6 +667,8 @@ typedef struct PHY_VARS_gNB_s { NR_gNB_ULSCH_t *ulsch[NUMBER_OF_NR_ULSCH_MAX][2]; // [Nusers times][2 codewords] NR_gNB_DLSCH_t *dlsch_SI,*dlsch_ra,*dlsch_p; NR_gNB_DLSCH_t *dlsch_PCH; + t_nrPolar_params *uci_polarParams; + uint8_t pbch_configured; char gNB_generate_rar; diff --git a/openair1/SIMULATION/NR_PHY/pucchsim.c b/openair1/SIMULATION/NR_PHY/pucchsim.c index aefec7bed3..42f6438ef4 100644 --- a/openair1/SIMULATION/NR_PHY/pucchsim.c +++ b/openair1/SIMULATION/NR_PHY/pucchsim.c @@ -457,6 +457,8 @@ int main(int argc, char **argv) pucch_GroupHopping_t PUCCH_GroupHopping=UE->pucch_config_common_nr->pucch_GroupHopping; uint32_t hopping_id=UE->pucch_config_common_nr->hoppingId; uint32_t dmrs_scrambling_id = 0, data_scrambling_id=0; + t_nrPolar_params *currentPtr; + if(format==0){ // for now we are not considering SR just HARQ-ACK if (nr_bit ==0) @@ -467,7 +469,8 @@ int main(int argc, char **argv) mcs=table2_mcs[actual_payload]; else AssertFatal(1==0,"Either nr_bit %d or sr_flag %d must be non-zero\n"); } - + else if (format == 2 && nr_bit > 11) gNB->uci_polarParams = nr_polar_params(2, nr_bit, nrofPRB, 1, NULL); + for(SNR=snr0;SNR<=snr1;SNR=SNR+1){ ack_nack_errors=0; n_errors = 0; @@ -506,6 +509,8 @@ int main(int argc, char **argv) pucch_pdu.group_hop_flag = PUCCH_GroupHopping&1; pucch_pdu.sequence_hop_flag = (PUCCH_GroupHopping>>1)&1; pucch_pdu.bit_len_harq = nr_bit; + pucch_pdu.bit_len_csi_part1 = 0; + pucch_pdu.bit_len_csi_part2 = 0; pucch_pdu.sr_flag = sr_flag; pucch_pdu.nr_of_symbols = nrofSymbols; pucch_pdu.hopping_id = hopping_id; @@ -534,7 +539,9 @@ int main(int argc, char **argv) pucch_pdu.subcarrier_spacing = 1; pucch_pdu.group_hop_flag = PUCCH_GroupHopping&1; pucch_pdu.sequence_hop_flag = (PUCCH_GroupHopping>>1)&1; - pucch_pdu.bit_len_harq = nr_bit; + pucch_pdu.bit_len_csi_part1 = nr_bit; + pucch_pdu.bit_len_harq = 0; + pucch_pdu.bit_len_csi_part2 = 0; pucch_pdu.sr_flag = 0; pucch_pdu.nr_of_symbols = nrofSymbols; pucch_pdu.hopping_id = hopping_id; @@ -545,14 +552,15 @@ int main(int argc, char **argv) pucch_pdu.dmrs_scrambling_id = dmrs_scrambling_id; pucch_pdu.data_scrambling_id = data_scrambling_id; nr_decode_pucch2(gNB,nr_tti_tx,&uci_pdu,&pucch_pdu); - int harq_bytes=pucch_pdu.bit_len_harq>>3; - if ((pucch_pdu.bit_len_harq&7) > 0) harq_bytes++; - for (int i=0;i>3; + if ((pucch_pdu.bit_len_csi_part1&7) > 0) csi_part1_bytes++; + for (int i=0;i>1)+(((actual_payload^payload_received)&4)>>2)+n_errors; From 417bc7e5670062dbcf271b64a9e93ddbd87562d0 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Sun, 14 Jun 2020 23:35:01 +0200 Subject: [PATCH 322/553] added tests to CI for PUCCH2 with polar code --- cmake_targets/autotests/test_case_list.xml | 31 +++++++++++++++------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/cmake_targets/autotests/test_case_list.xml b/cmake_targets/autotests/test_case_list.xml index d424db9903..ce5a7b41d5 100644 --- a/cmake_targets/autotests/test_case_list.xml +++ b/cmake_targets/autotests/test_case_list.xml @@ -1183,15 +1183,20 @@ nr_pucchsim Test cases. (Test1: Format 0 1-bit ACK miss 106 PRB), (Test2: Format 0 2-bit ACK miss 106 PRB), (Test3: Format 0 2-bit ACK miss, 1-bit SR 106 PRB), - (Test4: Format 2 3-bit 106 PRB), - (Test5: Format 2 4-bit 106 PRB), - (Test6: Format 2 5-bit 106 PRB), - (Test7: Format 2 6-bit 106 PRB), - (Test8: Format 2 7-bit 106 PRB), - (Test9: Format 2 8-bit 106 PRB), - (Test10: Format 2 9-bit 106 PRB), - (Test11: Format 2 10-bit 106 PRB), - (Test12: Format 2 11-bit 106 PRB) + (Test4: Format 2 3-bit 2/106 PRB), + (Test5: Format 2 4-bit 2/106 PRB), + (Test6: Format 2 5-bit 2/106 PRB), + (Test7: Format 2 6-bit 2/106 PRB), + (Test8: Format 2 7-bit 2/106 PRB), + (Test9: Format 2 8-bit 2/106 PRB), + (Test10: Format 2 9-bit 2/106 PRB), + (Test11: Format 2 10-bit 2/106 PRB), + (Test12: Format 2 11-bit 2/106 PRB), + (Test13: Format 2 12-bit 8/106 PRB), + (Test14: Format 2 19-bit 8/106 PRB), + (Test15: Format 2 32-bit 8/106 PRB), + (Test16: Format 2 32-bit 16/106 PRB), + (Test17: Format 2 64-bit 16/106 PRB) $OPENAIR_DIR/cmake_targets/build_oai --phy_simulators -c @@ -1210,8 +1215,14 @@ -R 106 -i 1 -P 2 -b 9 -s5 -n1000 -R 106 -i 1 -P 2 -b 10 -s6 -n1000 -R 106 -i 1 -P 2 -b 11 -s6 -n1000 + -R 106 -i 1 -P 2 -q8 -b 12 -s-3 -n1000 + -R 106 -i 1 -P 2 -q8 -b 19 -s-3 -n1000 + -R 106 -i 1 -P 2 -q8 -b 19 -s-3 -n1000 + -R 106 -i 1 -P 2 -q8 -b 32 -s-3 -n1000 + -R 106 -i 1 -P 2 -q16 -b 32 -s-3 -n1000 + -R 106 -i 1 -P 2 -q16 -b 64 -s-3 -n1000 - nr_pucchsim.test1 nr_pucchsim.test2 nr_pucchsim.test3 nr_pucchsim.test4 nr_pucchsim.test5 nr_pucchsim.test6 nr_pucchsim.test7 nr_pucchsim.test8 nr_pucchsim.test9 nr_pucchsim.test10 nr_pucchsim.test11 nr_pucchsim.test12 + nr_pucchsim.test1 nr_pucchsim.test2 nr_pucchsim.test3 nr_pucchsim.test4 nr_pucchsim.test5 nr_pucchsim.test6 nr_pucchsim.test7 nr_pucchsim.test8 nr_pucchsim.test9 nr_pucchsim.test10 nr_pucchsim.test11 nr_pucchsim.test12 nr_pucchsim.test13 nr_pucchsim.test14 nr_pucchsim.test15 nr_pucchsim.test16 nr_pucchsim.test17 PUCCH test OK segmentation fault|assertion|exiting|fatal 3 From 9a177fd368446fcd91b8612e7da6290c5e3ef8f5 Mon Sep 17 00:00:00 2001 From: matzakos Date: Mon, 15 Jun 2020 10:42:04 +0200 Subject: [PATCH 323/553] Bring back mapping check between drb_id and channel_id --- openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c | 8 ++++---- openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c b/openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c index 38ad658015..47ffd6143c 100644 --- a/openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c +++ b/openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c @@ -654,11 +654,11 @@ static void add_drb_am(int rnti, struct LTE_DRB_ToAddMod *s) exit(1); } - /*if (channel_id != drb_id + 2) { + if (channel_id != drb_id + 3) { LOG_E(RLC, "%s:%d:%s: todo, remove this limitation\n", __FILE__, __LINE__, __FUNCTION__); exit(1); - }*/ + } logical_channel_group = *l->ul_SpecificParameters->logicalChannelGroup; @@ -737,11 +737,11 @@ static void add_drb_um(int rnti, struct LTE_DRB_ToAddMod *s) exit(1); } - /*if (channel_id != drb_id + 2) { + if (channel_id != drb_id + 3) { LOG_E(RLC, "%s:%d:%s: todo, remove this limitation\n", __FILE__, __LINE__, __FUNCTION__); exit(1); - }*/ + } logical_channel_group = *l->ul_SpecificParameters->logicalChannelGroup; diff --git a/openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h b/openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h index f578faaf38..3683e50abc 100644 --- a/openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h +++ b/openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h @@ -29,7 +29,7 @@ typedef void nr_rlc_ue_manager_t; typedef struct nr_rlc_ue_t { int rnti; nr_rlc_entity_t *srb[3]; - nr_rlc_entity_t *drb[5]; + nr_rlc_entity_t *drb[4]; } nr_rlc_ue_t; /***********************************************************************/ From 1f95ec0888605cde4857d676ab9b2f8b7788475f Mon Sep 17 00:00:00 2001 From: laurent Date: Mon, 15 Jun 2020 14:14:38 +0200 Subject: [PATCH 324/553] coarse scope cleanup --- executables/nr-softmodem.c | 4 +- executables/nr-uesoftmodem.c | 59 +- .../PHY/LTE_UE_TRANSPORT/dlsch_demodulation.c | 7 +- openair1/PHY/NR_REFSIG/scrambling_luts.c | 3 +- .../PHY/NR_TRANSPORT/nr_ulsch_demodulation.c | 1 + openair1/PHY/TOOLS/nr_phy_scope.c | 1416 ++++++++--------- openair1/PHY/TOOLS/nr_phy_scope.h | 46 +- targets/ARCH/rfsimulator/simulator.c | 13 +- 8 files changed, 694 insertions(+), 855 deletions(-) diff --git a/executables/nr-softmodem.c b/executables/nr-softmodem.c index f473d0161b..1f291cfc19 100644 --- a/executables/nr-softmodem.c +++ b/executables/nr-softmodem.c @@ -954,7 +954,9 @@ if(!IS_SOFTMODEM_NOS1) scopeParms_t p; p.argc=&argc; p.argv=argv; - startScope(&p); + p.gNB=RC.gNB[0]; + p.ru=RC.ru[0]; + gNBinitScope(&p); } if (nfapi_mode != 1 && nfapi_mode != 2) { diff --git a/executables/nr-uesoftmodem.c b/executables/nr-uesoftmodem.c index 9b2b704833..9012971b9e 100644 --- a/executables/nr-uesoftmodem.c +++ b/executables/nr-uesoftmodem.c @@ -76,36 +76,11 @@ unsigned short config_frames[4] = {2,9,11,13}; #include #include -#include - - -/* Callbacks, globals and object handlers */ - -extern void reset_stats( FL_OBJECT *, long ); -//extern void initTpool(char *params, tpool_t *pool, bool performanceMeas); - -/* Forms and Objects */ - -typedef struct { - FL_FORM *stats_form; - void *vdata; - char *cdata; - long ldata; - FL_OBJECT *stats_text; - FL_OBJECT *stats_button; -} FD_stats_form; - -extern FD_stats_form *create_form_stats_form( void ); - -#include "PHY/TOOLS/nr_phy_scope.h" //#include "stats.h" // current status is that every UE has a DL scope for a SINGLE eNB (eNB_id=0) +#include "PHY/TOOLS/nr_phy_scope.h" // at eNB 0, an UL scope for every UE -FD_phy_scope_nrue *form_nrue[NUMBER_OF_UE_MAX]; //FD_lte_phy_scope_enb *form_enb[MAX_NUM_CCs][NUMBER_OF_UE_MAX]; -//FD_stats_form *form_stats=NULL,*form_stats_l2=NULL; -char title[255]; -static pthread_t forms_thread; //xforms #include #include "executables/softmodem-common.h" @@ -304,35 +279,6 @@ void reset_stats(FL_OBJECT *button, long arg) { }*/ } -static void *scope_thread(void *arg) { - sleep(5); - - while (!oai_exit) { - phy_scope_nrUE(form_nrue[0], - PHY_vars_UE_g[0][0], - 0,0,1); - usleep(100*1000); - } - - pthread_exit((void *)arg); -} - - -void init_scope(void) { - int fl_argc=1; - - if (do_forms==1) { - char *name="5G-UE-scope"; - fl_initialize (&fl_argc, &name, NULL, 0, 0); - int UE_id = 0; - form_nrue[UE_id] = create_phy_scope_nrue(); - sprintf (title, "NR DL SCOPE UE"); - fl_show_form (form_nrue[UE_id]->phy_scope_nrue, FL_PLACE_HOTSPOT, FL_FULLBORDER, title); - threadCreate(&forms_thread, scope_thread, NULL, "scope", -1, OAI_PRIORITY_RT_LOW); - } - -} - void *l2l1_task(void *arg) { MessageDef *message_p = NULL; int result; @@ -782,7 +728,8 @@ int main( int argc, char **argv ) { memset (&UE_PF_PO[0][0], 0, sizeof(UE_PF_PO_t)*NUMBER_OF_UE_MAX*MAX_NUM_CCs); configure_linux(); mlockall(MCL_CURRENT | MCL_FUTURE); - init_scope(); + if (do_forms) + nrUEinitScope(PHY_vars_UE_g[0][0]); number_of_cards = 1; for(int CC_id=0; CC_idQm, pdsch_vars[eNB_id]->llr_length[symbol], pdsch_vars[eNB_id]->llr_offset[symbol], (int16_t*)pdsch_vars[eNB_id]->llr[0], - pllr_symbol_cw0); - */ + pllr_symbol_cw0, + signal_energy(pdsch_vars[eNB_id]->rxdataF_comp0[0], 7*2*frame_parms->N_RB_DL*12)); switch (dlsch0_harq->Qm) { case 2 : if ((rx_type==rx_standard) || (codeword_TB1 == -1)) { diff --git a/openair1/PHY/NR_REFSIG/scrambling_luts.c b/openair1/PHY/NR_REFSIG/scrambling_luts.c index 9d957de0f7..790d3f7719 100644 --- a/openair1/PHY/NR_REFSIG/scrambling_luts.c +++ b/openair1/PHY/NR_REFSIG/scrambling_luts.c @@ -27,6 +27,7 @@ #include "PHY/impl_defs_nr.h" #include "PHY/sse_intrin.h" +#include __m64 byte2m64_re[256]; __m64 byte2m64_im[256]; @@ -42,7 +43,7 @@ void init_byte2m64(void) { byte2m64_im[s] = _mm_insert_pi16(byte2m64_im[s],(1-2*((s>>5)&1)),2); byte2m64_re[s] = _mm_insert_pi16(byte2m64_re[s],(1-2*((s>>6)&1)),3); byte2m64_im[s] = _mm_insert_pi16(byte2m64_im[s],(1-2*((s>>7)&1)),3); - printf("init_scrambling_luts: s %x (%d) ((%d,%d),(%d,%d),(%d,%d),(%d,%d))\n", + LOG_T(PHY,"init_scrambling_luts: s %x (%d) ((%d,%d),(%d,%d),(%d,%d),(%d,%d))\n", ((uint16_t*)&s)[0], (1-2*(s&1)), ((int16_t*)&byte2m64_re[s])[0],((int16_t*)&byte2m64_im[s])[0], diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c index 363b67960d..dfad8e87e6 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c @@ -1145,6 +1145,7 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, //-------------------- LLRs computation -------------------- //---------------------------------------------------------- start_meas(&gNB->ulsch_llr_stats); + AssertFatal(gNB->pusch_vars[UE_id]->rxdataF_ext_offset * rel15_ul->qam_mod_order+nb_re_pusch*rel15_ul->qam_mod_order < (8*((3*8*6144)+12)) , "Mysterious llr buffer size check"); nr_ulsch_compute_llr(&gNB->pusch_vars[UE_id]->rxdataF_comp[0][symbol * rel15_ul->rb_size * NR_NB_SC_PER_RB], gNB->pusch_vars[UE_id]->ul_ch_mag0, gNB->pusch_vars[UE_id]->ul_ch_magb0, diff --git a/openair1/PHY/TOOLS/nr_phy_scope.c b/openair1/PHY/TOOLS/nr_phy_scope.c index 8c92214e68..61a38098a6 100644 --- a/openair1/PHY/TOOLS/nr_phy_scope.c +++ b/openair1/PHY/TOOLS/nr_phy_scope.c @@ -9,6 +9,8 @@ * * http://www.openairinterface.org/?page_id=698 * + * Author and copyright: Laurent Thomas, open-cells.com + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -26,6 +28,7 @@ #include "executables/nr-softmodem-common.h" #define TPUT_WINDOW_LENGTH 100 +#define localBuff(NaMe,SiZe) float NaMe[SiZe]; memset(NaMe,0,sizeof(NaMe)); int otg_enabled; FL_COLOR rx_antenna_colors[4] = {FL_RED,FL_BLUE,FL_GREEN,FL_YELLOW}; @@ -36,10 +39,40 @@ float tput_time_ue[NUMBER_OF_UE_MAX][TPUT_WINDOW_LENGTH] = {{0}}; float tput_ue[NUMBER_OF_UE_MAX][TPUT_WINDOW_LENGTH] = {{0}}; float tput_ue_max[NUMBER_OF_UE_MAX] = {0}; +typedef struct { + int16_t r; + int16_t i; +} scopeSample_t; +#define SquaredNorm(VaR) ((VaR).r*(VaR).r+(VaR).i*(VaR).i) -static void ia_receiver_on_off( FL_OBJECT *button, long arg) -{ +typedef struct OAIgraph { + FL_OBJECT *graph; + void (*gNBfunct) (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int UE_id); + void (*nrUEfunct) (FL_OBJECT *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id); +} OAIgraph_t; +/* Forms and Objects */ +typedef struct { + FL_FORM *phy_scope; + OAIgraph_t graph[20]; + FL_OBJECT *button_0; +} FD_phy_scope_t; + +typedef struct { + FL_FORM *stats_form; + void *vdata; + char *cdata; + long ldata; + FL_OBJECT *stats_text; + FL_OBJECT *stats_button; +} FD_stats_form; + +static void drawsymbol(FL_OBJECT *obj, int id, + FL_POINT *p, int n, int w, int h) { + fl_points( p, n, FL_YELLOW); +} + +static void ia_receiver_on_off( FL_OBJECT *button, long arg) { if (fl_get_button(button)) { fl_set_object_label(button, "IA Receiver ON"); // PHY_vars_UE_g[0][0]->use_ia_receiver = 1; @@ -51,9 +84,7 @@ static void ia_receiver_on_off( FL_OBJECT *button, long arg) } } -static void dl_traffic_on_off( FL_OBJECT *button, long arg) -{ - +static void dl_traffic_on_off( FL_OBJECT *button, long arg) { if (fl_get_button(button)) { fl_set_object_label(button, "DL Traffic ON"); otg_enabled = 1; @@ -65,764 +96,639 @@ static void dl_traffic_on_off( FL_OBJECT *button, long arg) } } -FD_phy_scope_gnb *create_phy_scope_gnb( void ) -{ - - FL_OBJECT *obj; - FD_phy_scope_gnb *fdui = fl_malloc( sizeof *fdui ); - - // Define form - fdui->phy_scope_gnb = fl_bgn_form( FL_NO_BOX, 800, 800 ); - - // This the whole UI box - obj = fl_add_box( FL_BORDER_BOX, 0, 0, 800, 800, "" ); - fl_set_object_color( obj, FL_BLACK, FL_BLACK ); - - // Received signal - fdui->rxsig_t = fl_add_xyplot( FL_NORMAL_XYPLOT, 20, 20, 370, 100, "Received Signal (Time-Domain, dB)" ); - fl_set_object_boxtype( fdui->rxsig_t, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->rxsig_t, FL_BLACK, FL_RED ); - fl_set_object_lcolor( fdui->rxsig_t, FL_WHITE ); // Label color - fl_set_xyplot_ybounds(fdui->rxsig_t,10,70); - - // Time-domain channel response - fdui->chest_t = fl_add_xyplot( FL_NORMAL_XYPLOT, 410, 20, 370, 100, "SRS Frequency Response (samples, abs)" ); - fl_set_object_boxtype( fdui->chest_t, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->chest_t, FL_BLACK, FL_RED ); - fl_set_object_lcolor( fdui->chest_t, FL_WHITE ); // Label color - - // Frequency-domain channel response - fdui->chest_f = fl_add_xyplot( FL_IMPULSE_XYPLOT, 20, 140, 760, 100, "Channel Frequency Response (RE, dB)" ); - fl_set_object_boxtype( fdui->chest_f, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->chest_f, FL_BLACK, FL_RED ); - fl_set_object_lcolor( fdui->chest_f, FL_WHITE ); // Label color - fl_set_xyplot_ybounds( fdui->chest_f,30,70); - - // LLR of PUSCH - fdui->pusch_llr = fl_add_xyplot( FL_POINTS_XYPLOT, 20, 260, 500, 200, "PUSCH Log-Likelihood Ratios (LLR, mag)" ); - fl_set_object_boxtype( fdui->pusch_llr, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->pusch_llr, FL_BLACK, FL_YELLOW ); - fl_set_object_lcolor( fdui->pusch_llr, FL_WHITE ); // Label color - fl_set_xyplot_symbolsize( fdui->pusch_llr,2); - - // I/Q PUSCH comp - fdui->pusch_comp = fl_add_xyplot( FL_POINTS_XYPLOT, 540, 260, 240, 200, "PUSCH I/Q of MF Output" ); - fl_set_object_boxtype( fdui->pusch_comp, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->pusch_comp, FL_BLACK, FL_YELLOW ); - fl_set_object_lcolor( fdui->pusch_comp, FL_WHITE ); // Label color - fl_set_xyplot_symbolsize( fdui->pusch_comp,2); - fl_set_xyplot_xgrid( fdui->pusch_llr,FL_GRID_MAJOR); - - // I/Q PUCCH comp (format 1) - fdui->pucch_comp1 = fl_add_xyplot( FL_POINTS_XYPLOT, 540, 480, 240, 100, "PUCCH1 Energy (SR)" ); - fl_set_object_boxtype( fdui->pucch_comp1, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->pucch_comp1, FL_BLACK, FL_YELLOW ); - fl_set_object_lcolor( fdui->pucch_comp1, FL_WHITE ); // Label color - fl_set_xyplot_symbolsize( fdui->pucch_comp1,2); - // fl_set_xyplot_xgrid( fdui->pusch_llr,FL_GRID_MAJOR); - - // I/Q PUCCH comp (fromat 1a/b) - fdui->pucch_comp = fl_add_xyplot( FL_POINTS_XYPLOT, 540, 600, 240, 100, "PUCCH I/Q of MF Output" ); - fl_set_object_boxtype( fdui->pucch_comp, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->pucch_comp, FL_BLACK, FL_YELLOW ); - fl_set_object_lcolor( fdui->pucch_comp, FL_WHITE ); // Label color - fl_set_xyplot_symbolsize( fdui->pucch_comp,2); - // fl_set_xyplot_xgrid( fdui->pusch_llr,FL_GRID_MAJOR); - - // Throughput on PUSCH - fdui->pusch_tput = fl_add_xyplot( FL_NORMAL_XYPLOT, 20, 480, 500, 100, "PUSCH Throughput [frame]/[kbit/s]" ); - fl_set_object_boxtype( fdui->pusch_tput, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->pusch_tput, FL_BLACK, FL_WHITE ); - fl_set_object_lcolor( fdui->pusch_tput, FL_WHITE ); // Label color - - // Generic eNB Button - fdui->button_0 = fl_add_button( FL_PUSH_BUTTON, 20, 600, 240, 40, "" ); - fl_set_object_lalign(fdui->button_0, FL_ALIGN_CENTER ); - fl_set_button(fdui->button_0,0); - otg_enabled = 0; - fl_set_object_label(fdui->button_0, "DL Traffic OFF"); - fl_set_object_color(fdui->button_0, FL_RED, FL_RED); - fl_set_object_callback(fdui->button_0, dl_traffic_on_off, 0 ); - - fl_end_form( ); - fdui->phy_scope_gnb->fdui = fdui; - - return fdui; +static FL_OBJECT *commonGraph( int type, FL_Coord x, FL_Coord y, FL_Coord w, FL_Coord h, const char *label, FL_COLOR pointColor) { + FL_OBJECT *graph; + graph=fl_add_xyplot(type, x, y, w, h, label); + fl_set_object_boxtype(graph, FL_EMBOSSED_BOX ); + fl_set_object_lcolor(graph, FL_WHITE ); // Label color + fl_set_xyplot_symbol(graph, 0, drawsymbol); + fl_set_object_color(graph, FL_BLACK, pointColor); + return graph; } -void phy_scope_gNB(FD_phy_scope_gnb *form, +static OAIgraph_t gNBcommonGraph( void (*funct) (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int UE_id), + int type, FL_Coord x, FL_Coord y, FL_Coord w, FL_Coord h, const char *label, FL_COLOR pointColor) { + OAIgraph_t graph; + graph.graph=commonGraph(type, x, y, w, h, label, pointColor); + graph.gNBfunct=funct; + graph.nrUEfunct=NULL; + return graph; +} + +static OAIgraph_t nrUEcommonGraph( void (*funct) (FL_OBJECT *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id), + int type, FL_Coord x, FL_Coord y, FL_Coord w, FL_Coord h, const char *label, FL_COLOR pointColor) { + OAIgraph_t graph; + graph.graph=commonGraph(type, x, y, w, h, label, pointColor); + graph.gNBfunct=NULL; + graph.nrUEfunct=funct; + return graph; +} + +void phy_scope_gNB(FD_phy_scope_t *form, PHY_VARS_gNB *phy_vars_gnb, - RU_t *phy_vars_ru, - int UE_id) -{ - int i, arx; //int i,i2,arx,atx,ind,k; - NR_DL_FRAME_PARMS *frame_parms = &phy_vars_gnb->frame_parms; - //int nsymb_ce = 12*frame_parms->N_RB_UL*frame_parms->symbols_per_tti; - uint8_t nb_antennas_rx = frame_parms->nb_antennas_rx; - //uint8_t nb_antennas_tx = 1; // frame_parms->nb_antennas_tx; // in LTE Rel. 8 and 9 only a single transmit antenna is assumed at the UE - int16_t **rxsig_t, **rxsig_f; - // int16_t **chest_t=NULL; - // int16_t **chest_f=NULL; - // int16_t *pusch_llr=NULL; - // int32_t *pusch_comp=NULL; - // int32_t *pucch1_comp=NULL; - // int32_t *pucch1_thres=NULL; - // int32_t *pucch1ab_comp=NULL; - // float Re,Im,ymax; - float *llr, *bit; - // float I[nsymb_ce*2], Q[nsymb_ce*2]; - // float I_pucch[10240],Q_pucch[10240],A_pucch[10240],B_pucch[10240],C_pucch[10240]; - float *rxsig_t_dB[nb_antennas_rx]; - float *rxsig_f_dB[nb_antennas_rx]; - float time[frame_parms->samples_per_frame]; - // float freq[nsymb_ce*nb_antennas_rx*nb_antennas_tx]; - // uint32_t total_dlsch_bitrate = phy_vars_gnb->total_dlsch_bitrate; - int coded_bits_per_codeword = 0; - // uint8_t harq_pid; // in TDD config 3 it is sf-2, i.e., can be 0,1,2 - int Qm = 2; + RU_t *phy_vars_ru, + int UE_id) { + static FD_phy_scope_t *remeberForm=NULL; - /* - if (!RC.nrmac[0]->UE_info.active[UE_id]) - return; - - // choose max MCS to compute coded_bits_per_codeword - if (phy_vars_gnb->ulsch[UE_id][0]!=NULL) { - for (harq_pid=0; harq_pid<3; harq_pid++) { - //Qm = cmax(phy_vars_gnb->ulsch[UE_id][0]->harq_processes->Qm,Qm); - } + if (form==NULL) + form=remeberForm; + else + remeberForm=form; + + if (form==NULL) return; + + int i=0; + + while (form->graph[i].graph) { + form->graph[i].gNBfunct(form->graph[i].graph, phy_vars_gnb, phy_vars_ru, UE_id); + i++; } - */ - coded_bits_per_codeword = frame_parms->N_RB_UL*12*Qm*frame_parms->symbols_per_tti; - for (arx=0; arxsamples_per_frame,sizeof(float)); - rxsig_f_dB[arx] = (float*) calloc(frame_parms->samples_per_slot_wCP,sizeof(float)); - } - llr = (float*) calloc(coded_bits_per_codeword,sizeof(float)); // init to zero - bit = malloc(coded_bits_per_codeword*sizeof(float)); - - rxsig_t = (int16_t**) phy_vars_ru->common.rxdata; - rxsig_f = (int16_t**) phy_vars_ru->common.rxdataF; - //chest_t = (int16_t**) phy_vars_gnb->pusch_vars[UE_id]->drs_ch_estimates_time[eNB_id]; - /* chest_t = (int16_t**) phy_vars_gnb->srs_vars[UE_id].srs_ch_estimates; - chest_f = (int16_t**) phy_vars_gnb->pusch_vars[UE_id]->drs_ch_estimates; - pusch_llr = (int16_t*) phy_vars_gnb->pusch_vars[UE_id]->llr; - pusch_comp = (int32_t*) phy_vars_gnb->pusch_vars[UE_id]->rxdataF_comp; - pucch1_comp = (int32_t*) phy_vars_gnb->pucch1_stats[UE_id]; - pucch1_thres = (int32_t*) phy_vars_gnb->pucch1_stats_thres[UE_id]; - pucch1ab_comp = (int32_t*) phy_vars_gnb->pucch1ab_stats[UE_id]; - */ + fl_check_forms(); +} +static void timeSignal (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int UE_id) { // Received signal in time domain of receive antenna 0 - if (rxsig_t != NULL) { - if (rxsig_t[0] != NULL) { - for (i=0; isamples_per_frame; i++) { - rxsig_t_dB[0][i] = 10*log10(1.0+(float) ((rxsig_t[0][2*i])*(rxsig_t[0][2*i])+(rxsig_t[0][2*i+1])*(rxsig_t[0][2*i+1]))); - time[i] = (float) i; + if (!phy_vars_ru->common.rxdata) + return; + + NR_DL_FRAME_PARMS *frame_parms=&phy_vars_gnb->frame_parms; + uint8_t nb_antennas_rx = frame_parms->nb_antennas_rx; + scopeSample_t **rxsig_t = (scopeSample_t **)phy_vars_ru->common.rxdata; + float rxsig_t_dB[frame_parms->samples_per_frame]; + float time[frame_parms->samples_per_frame]; + + for (int arx=0; arxsamples_per_frame; i++) { + rxsig_t_dB[i] = 10*log10(1.0+SquaredNorm(rxsig_t[arx][i])); } - fl_set_xyplot_data(form->rxsig_t,time,rxsig_t_dB[0],frame_parms->samples_per_frame,"","",""); + if (arx==0) + fl_set_xyplot_data(graph,time,rxsig_t_dB, frame_parms->samples_per_frame,"","",""); + else + fl_add_xyplot_overlay(graph,arx,time,rxsig_t_dB,frame_parms->samples_per_frame,rx_antenna_colors[arx]); } + } +} - for (arx=1; arxsamples_per_frame; i++) { - rxsig_t_dB[arx][i] = 10*log10(1.0+(float) ((rxsig_t[arx][2*i])*(rxsig_t[arx][2*i])+(rxsig_t[arx][2*i+1])*(rxsig_t[arx][2*i+1]))); - } +static void timeResponse (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int UE_id) { + if (!phy_vars_gnb->pusch_vars[UE_id]->ul_ch_estimates_time) + return; - fl_add_xyplot_overlay(form->rxsig_t,arx,time,rxsig_t_dB[arx],frame_parms->samples_per_frame,rx_antenna_colors[arx]); + NR_DL_FRAME_PARMS *frame_parms=&phy_vars_gnb->frame_parms; + uint8_t nb_antennas_rx = frame_parms->nb_antennas_rx; + scopeSample_t **chest_t = (scopeSample_t **) phy_vars_gnb->pusch_vars[UE_id]->ul_ch_estimates_time; + int ymax = 0; + float time2[2*frame_parms->ofdm_symbol_size]; + float chest_t_abs[2*frame_parms->ofdm_symbol_size]; + + for (int arx=0; arxofdm_symbol_size); i++) { + time2[i] = (float)i; + chest_t_abs[i] = 10*log10(1.0 + SquaredNorm(chest_t[0][i])); + + if (chest_t_abs[i] > ymax) + ymax = chest_t_abs[i]; + } + + if (arx==0) + fl_set_xyplot_data(graph,time2,chest_t_abs,(2*frame_parms->ofdm_symbol_size),"","",""); + else { + fl_add_xyplot_overlay(graph,arx,time2,chest_t_abs,(frame_parms->ofdm_symbol_size>>3),rx_antenna_colors[arx]); + fl_set_xyplot_overlay_type(graph,arx,FL_DASHED_XYPLOT); } } } + // Avoid flickering effect + // fl_get_xyplot_ybounds(form->chest_t,&ymin,&ymax); + fl_set_xyplot_ybounds(graph,0,ymax); +} + +static void frequencyResponse (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int UE_id) { + // Channel Frequency Response + if (!phy_vars_ru->common.rxdataF) + return; + + NR_DL_FRAME_PARMS *frame_parms=&phy_vars_gnb->frame_parms; + //uint8_t nb_antennas_rx = frame_parms->nb_antennas_rx; + scopeSample_t **rxsig_f = (scopeSample_t **) phy_vars_ru->common.rxdataF; + float rxsig_f_dB[frame_parms->samples_per_slot_wCP]; + float time[frame_parms->samples_per_slot_wCP]; + + if (rxsig_f[0] != NULL) { + for (int i=0; isamples_per_slot_wCP; i++) { + rxsig_f_dB[i] = 10*log10(1.0+ SquaredNorm(rxsig_f[0][i])); + time[i] = (float) i; + } + + fl_set_xyplot_data(graph,time,rxsig_f_dB,frame_parms->samples_per_slot_wCP,"","",""); + } + /* - // Channel Impulse Response - if (chest_t != NULL) { - ymax = 0; - - if (chest_t[0] !=NULL) { - for (i=0; i<(frame_parms->ofdm_symbol_size); i++) { - //i2 = (i+(frame_parms->ofdm_symbol_size>>1))%frame_parms->ofdm_symbol_size; - i2=i; - //time2[i] = (float)(i-(frame_parms->ofdm_symbol_size>>1)); - time2[i] = (float)i; - chest_t_abs[0][i] = 10*log10((float) (1+chest_t[0][2*i2]*chest_t[0][2*i2]+chest_t[0][2*i2+1]*chest_t[0][2*i2+1])); - - if (chest_t_abs[0][i] > ymax) - ymax = chest_t_abs[0][i]; + for (int arx=1; arxchest_t,time2,chest_t_abs[0],(frame_parms->ofdm_symbol_size),"","",""); + fl_add_xyplot_overlay(form->chest_f,1,time,chest_f_abs,nsymb_ce,rx_antenna_colors[arx]); } - - for (arx=1; arxofdm_symbol_size>>3); i++) { - chest_t_abs[arx][i] = 10*log10((float) (1+chest_t[arx][2*i]*chest_t[arx][2*i]+chest_t[arx][2*i+1]*chest_t[arx][2*i+1])); - - if (chest_t_abs[arx][i] > ymax) - ymax = chest_t_abs[arx][i]; - } - - fl_add_xyplot_overlay(form->chest_t,arx,time,chest_t_abs[arx],(frame_parms->ofdm_symbol_size>>3),rx_antenna_colors[arx]); - fl_set_xyplot_overlay_type(form->chest_t,arx,FL_DASHED_XYPLOT); - } - } - - // Avoid flickering effect - // fl_get_xyplot_ybounds(form->chest_t,&ymin,&ymax); - fl_set_xyplot_ybounds(form->chest_t,0,ymax); } */ - - // Channel Frequency Response - if (rxsig_f != NULL) { - if (rxsig_f[0] != NULL) { - for (i=0; isamples_per_slot_wCP; i++) { - rxsig_f_dB[0][i] = 10*log10(1.0+(float) ((rxsig_f[0][2*i])*(rxsig_f[0][2*i])+(rxsig_f[0][2*i+1])*(rxsig_f[0][2*i+1]))); - time[i] = (float) i; - } - - fl_set_xyplot_data(form->chest_t,time,rxsig_f_dB[0],frame_parms->samples_per_slot_wCP,"","",""); - } - } - /* - - for (arx=0; arxchest_f,0,nb_antennas_rx*nb_antennas_tx*nsymb_ce); fl_set_xyplot_xtics(form->chest_f,nb_antennas_rx*nb_antennas_tx*frame_parms->symbols_per_tti,3); fl_set_xyplot_xgrid(form->chest_f,FL_GRID_MAJOR); fl_set_xyplot_data(form->chest_f,freq,chest_f_abs,nsymb_ce,"","",""); + */ +} - for (arx=1; arxchest_f,1,&freq[arx*nsymb_ce],&chest_f_abs[arx*nsymb_ce],nsymb_ce,rx_antenna_colors[arx]); - } - - // other tx antennas - if (nb_antennas_tx > 1) { - if (nb_antennas_rx > 1) { - for (atx=1; atxchest_f,(atx<<1)+arx,&freq[((atx<<1)+arx)*nsymb_ce],&chest_f_abs[((atx<<1)+arx)*nsymb_ce],nsymb_ce,rx_antenna_colors[arx]); - } - } - } else { // 1 rx antenna - atx=1; - arx=0; - fl_add_xyplot_overlay(form->chest_f,atx,&freq[atx*nsymb_ce],&chest_f_abs[atx*nsymb_ce],nsymb_ce,rx_antenna_colors[arx]); - } - } - } - +static void puschLLR (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int UE_id) { // PUSCH LLRs - if (pusch_llr != NULL) { - for (i=0; ipusch_vars[UE_id]->llr) + return; - fl_set_xyplot_data(form->pusch_llr,bit,llr,coded_bits_per_codeword,"","",""); + //NR_DL_FRAME_PARMS *frame_parms=&phy_vars_gnb->frame_parms; + //int Qm = 2; + int16_t *pusch_llr = (int16_t *) phy_vars_gnb->pusch_vars[UE_id]->llr; + int coded_bits_per_codeword =3*8*6144+12; // (8*((3*8*6144)+12)); // frame_parms->N_RB_UL*12*Qm*frame_parms->symbols_per_tti; + float llr[coded_bits_per_codeword]; + float bit[coded_bits_per_codeword]; + + for (int i=0; ipusch_vars[UE_id]->rxdataF_comp) + return; - for (k=0; ksymbols_per_tti; k++) { - for (i=0; i<12*frame_parms->N_RB_UL; i++) { - I[ind] = pusch_comp[(2*frame_parms->N_RB_UL*12*k)+2*i]; - Q[ind] = pusch_comp[(2*frame_parms->N_RB_UL*12*k)+2*i+1]; - ind++; - } - } + NR_DL_FRAME_PARMS *frame_parms=&phy_vars_gnb->frame_parms; + scopeSample_t *pusch_comp = (scopeSample_t *) phy_vars_gnb->pusch_vars[UE_id]->rxdataF_comp[0]; + int sz=frame_parms->N_RB_UL*12*frame_parms->symbols_per_slot; + float I[sz], Q[sz]; - fl_set_xyplot_data(form->pusch_comp,I,Q,ind,"","",""); + for (int k=0; kpucch1ab_stats[UE_id]; + int32_t *pucch1_comp = (int32_t *) NULL; //phy_vars_gnb->pucch1_stats[UE_id]; + float I_pucch[10240],Q_pucch[10240],A_pucch[10240],B_pucch[10240],C_pucch[10240]; + + for (int ind=0; ind<10240; ind++) { I_pucch[ind] = (float)pucch1ab_comp[2*(ind)]; Q_pucch[ind] = (float)pucch1ab_comp[2*(ind)+1]; A_pucch[ind] = pucch1_comp?(10*log10(pucch1_comp[ind])):0; B_pucch[ind] = ind; + int32_t *pucch1_thres = (int32_t *) NULL; // phy_vars_gnb->pucch1_stats_thres[UE_id]; C_pucch[ind] = pucch1_thres?(float)pucch1_thres[ind]:0; } - fl_set_xyplot_data(form->pucch_comp,I_pucch,Q_pucch,10240,"","",""); - fl_set_xyplot_data(form->pucch_comp1,B_pucch,A_pucch,1024,"","",""); - fl_add_xyplot_overlay(form->pucch_comp1,1,B_pucch,C_pucch,1024,FL_RED); - fl_set_xyplot_ybounds(form->pucch_comp,-5000,5000); - fl_set_xyplot_xbounds(form->pucch_comp,-5000,5000); - fl_set_xyplot_ybounds(form->pucch_comp1,0,80); + fl_set_xyplot_data(graph,I_pucch,Q_pucch,10240,"","",""); + fl_set_xyplot_data(graph,B_pucch,A_pucch,1024,"","",""); + fl_add_xyplot_overlay(graph,1,B_pucch,C_pucch,1024,FL_RED); + fl_set_xyplot_ybounds(graph,-5000,5000); + fl_set_xyplot_xbounds(graph,-5000,5000); + fl_set_xyplot_ybounds(graph,0,80); } +} +static void pucchEnergy (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int UE_id) { +} +static void pucchIQ (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int UE_id) { +} + +static void puschThroughtput (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int UE_id) { // PUSCH Throughput memmove( tput_time_enb[UE_id], &tput_time_enb[UE_id][1], (TPUT_WINDOW_LENGTH-1)*sizeof(float) ); memmove( tput_enb[UE_id], &tput_enb[UE_id][1], (TPUT_WINDOW_LENGTH-1)*sizeof(float) ); - tput_time_enb[UE_id][TPUT_WINDOW_LENGTH-1] = (float) 0; -// tput_enb[UE_id][TPUT_WINDOW_LENGTH-1] = ((float) total_dlsch_bitrate)/1000.0; - - fl_set_xyplot_data(form->pusch_tput,tput_time_enb[UE_id],tput_enb[UE_id],TPUT_WINDOW_LENGTH,"","",""); - + // tput_enb[UE_id][TPUT_WINDOW_LENGTH-1] = ((float) total_dlsch_bitrate)/1000.0; + fl_set_xyplot_data(graph,tput_time_enb[UE_id],tput_enb[UE_id],TPUT_WINDOW_LENGTH,"","",""); // fl_get_xyplot_ybounds(form->pusch_tput,&ymin,&ymax); // fl_set_xyplot_ybounds(form->pusch_tput,0,ymax); - - */ - - fl_check_forms(); - - free(llr); - free(bit); } -FD_phy_scope_nrue *create_phy_scope_nrue( void ) -{ - +static FD_phy_scope_t *create_phy_scope_gnb(int UE_id ) { FL_OBJECT *obj; - FD_phy_scope_nrue *fdui = fl_malloc( sizeof *fdui ); - + FD_phy_scope_t *fdui = fl_malloc( sizeof *fdui ); // Define form - fdui->phy_scope_nrue = fl_bgn_form( FL_NO_BOX, 800, 900 ); - + fdui->phy_scope = fl_bgn_form( FL_NO_BOX, 800, 800 ); // This the whole UI box - obj = fl_add_box( FL_BORDER_BOX, 0, 0, 800, 900, "" ); + obj = fl_add_box( FL_BORDER_BOX, 0, 0, 800, 800, "" ); fl_set_object_color( obj, FL_BLACK, FL_BLACK ); - // Received signal - fdui->rxsig_t = fl_add_xyplot( FL_NORMAL_XYPLOT, 20, 20, 370, 100, "Received Signal (Time-Domain, dB)" ); - fl_set_object_boxtype( fdui->rxsig_t, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->rxsig_t, FL_BLACK, FL_RED ); - fl_set_object_lcolor( fdui->rxsig_t, FL_WHITE ); // Label color - fl_set_xyplot_ybounds(fdui->rxsig_t,10,70); - + fdui->graph[0] = gNBcommonGraph( timeSignal, FL_IMPULSE_XYPLOT, 20, 20, 370, 100, + "Received Signal (Time-Domain, dB)", FL_RED ); // Time-domain channel response - fdui->chest_t = fl_add_xyplot( FL_NORMAL_XYPLOT, 410, 20, 370, 100, "Channel Impulse Response (samples, abs)" ); - fl_set_object_boxtype( fdui->chest_t, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->chest_t, FL_BLACK, FL_RED ); - fl_set_object_lcolor( fdui->chest_t, FL_WHITE ); // Label color - + fdui->graph[1] = gNBcommonGraph( timeResponse, FL_NORMAL_XYPLOT, 410, 20, 370, 100, + "SRS Frequency Response (samples, abs)", FL_RED ); // Frequency-domain channel response - fdui->chest_f = fl_add_xyplot( FL_IMPULSE_XYPLOT, 20, 140, 760, 100, "Channel Frequency Response (RE, dB)" ); - fl_set_object_boxtype( fdui->chest_f, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->chest_f, FL_BLACK, FL_RED ); - fl_set_object_lcolor( fdui->chest_f, FL_WHITE ); // Label color - fl_set_xyplot_ybounds( fdui->chest_f,30,70); + fdui->graph[2] = gNBcommonGraph( frequencyResponse, FL_IMPULSE_XYPLOT, 20, 140, 760, 100, + "Channel Frequency Response (RE, dB)", FL_RED ); + // LLR of PUSCH + fdui->graph[3] = gNBcommonGraph( puschLLR, FL_POINTS_XYPLOT, 20, 260, 500, 200, + "PUSCH Log-Likelihood Ratios (LLR, mag)", FL_YELLOW ); + // I/Q PUSCH comp + fdui->graph[4] = gNBcommonGraph( puschIQ, FL_POINTS_XYPLOT, 540, 260, 240, 200, + "PUSCH I/Q of MF Output", FL_YELLOW ); + // I/Q PUCCH comp (format 1) + fdui->graph[5] = gNBcommonGraph( pucchEnergy, FL_POINTS_XYPLOT, 540, 480, 240, 100, + "PUCCH1 Energy (SR)", FL_YELLOW ); + // fl_set_xyplot_xgrid( fdui->pusch_llr,FL_GRID_MAJOR); + // I/Q PUCCH comp (fromat 1a/b) + fdui->graph[6] = gNBcommonGraph( pucchIQ, FL_POINTS_XYPLOT, 540, 600, 240, 100, + "PUCCH I/Q of MF Output", FL_YELLOW ); + // Throughput on PUSCH + fdui->graph[7] = gNBcommonGraph( puschThroughtput, FL_NORMAL_XYPLOT, 20, 480, 500, 100, + "PUSCH Throughput [frame]/[kbit/s]", FL_WHITE ); + fdui->graph[8].graph=NULL; - // LLR of PBCH - fdui->pbch_llr = fl_add_xyplot( FL_POINTS_XYPLOT, 20, 260, 500, 100, "PBCH Log-Likelihood Ratios (LLR, mag)" ); - fl_set_object_boxtype( fdui->pbch_llr, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->pbch_llr, FL_BLACK, FL_GREEN ); - fl_set_object_lcolor( fdui->pbch_llr, FL_WHITE ); // Label color - fl_set_xyplot_symbolsize( fdui->pbch_llr,2); - fl_set_xyplot_xgrid( fdui->pbch_llr,FL_GRID_MAJOR); - //fl_set_xyplot_xbounds( fdui->pbch_llr,0,1920); - - // I/Q PBCH comp - fdui->pbch_comp = fl_add_xyplot( FL_POINTS_XYPLOT, 540, 260, 240, 100, "PBCH I/Q of MF Output" ); - fl_set_object_boxtype( fdui->pbch_comp, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->pbch_comp, FL_BLACK, FL_GREEN ); - fl_set_object_lcolor( fdui->pbch_comp, FL_WHITE ); // Label color - fl_set_xyplot_symbolsize( fdui->pbch_comp,2); - // fl_set_xyplot_xbounds( fdui->pbch_comp,-100,100); - // fl_set_xyplot_ybounds( fdui->pbch_comp,-100,100); - - // LLR of PDCCH - fdui->pdcch_llr = fl_add_xyplot( FL_POINTS_XYPLOT, 20, 380, 500, 100, "PDCCH Log-Likelihood Ratios (LLR, mag)" ); - fl_set_object_boxtype( fdui->pdcch_llr, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->pdcch_llr, FL_BLACK, FL_CYAN ); - fl_set_object_lcolor( fdui->pdcch_llr, FL_WHITE ); // Label color - fl_set_xyplot_symbolsize( fdui->pdcch_llr,2); - - // I/Q PDCCH comp - fdui->pdcch_comp = fl_add_xyplot( FL_POINTS_XYPLOT, 540, 380, 240, 100, "PDCCH I/Q of MF Output" ); - fl_set_object_boxtype( fdui->pdcch_comp, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->pdcch_comp, FL_BLACK, FL_CYAN ); - fl_set_object_lcolor( fdui->pdcch_comp, FL_WHITE ); // Label color - fl_set_xyplot_symbolsize( fdui->pdcch_comp,2); - fl_set_xyplot_xgrid( fdui->pdcch_llr,FL_GRID_MAJOR); - - // LLR of PDSCH - fdui->pdsch_llr = fl_add_xyplot( FL_POINTS_XYPLOT, 20, 500, 500, 200, "PDSCH Log-Likelihood Ratios (LLR, mag)" ); - fl_set_object_boxtype( fdui->pdsch_llr, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->pdsch_llr, FL_BLACK, FL_YELLOW ); - fl_set_object_lcolor( fdui->pdsch_llr, FL_WHITE ); // Label color - fl_set_xyplot_symbolsize( fdui->pdsch_llr,2); - fl_set_xyplot_xgrid( fdui->pdsch_llr,FL_GRID_MAJOR); - - // I/Q PDSCH comp - fdui->pdsch_comp = fl_add_xyplot( FL_POINTS_XYPLOT, 540, 500, 240, 200, "PDSCH I/Q of MF Output" ); - fl_set_object_boxtype( fdui->pdsch_comp, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->pdsch_comp, FL_BLACK, FL_YELLOW ); - fl_set_object_lcolor( fdui->pdsch_comp, FL_WHITE ); // Label color - fl_set_xyplot_symbolsize( fdui->pdsch_comp,2); - - // Throughput on PDSCH - fdui->pdsch_tput = fl_add_xyplot( FL_NORMAL_XYPLOT, 20, 720, 500, 100, "PDSCH Throughput [frame]/[kbit/s]" ); - fl_set_object_boxtype( fdui->pdsch_tput, FL_EMBOSSED_BOX ); - fl_set_object_color( fdui->pdsch_tput, FL_BLACK, FL_WHITE ); - fl_set_object_lcolor( fdui->pdsch_tput, FL_WHITE ); // Label color - - // Generic UE Button - fdui->button_0 = fl_add_button( FL_PUSH_BUTTON, 540, 720, 240, 40, "" ); - fl_set_object_lalign(fdui->button_0, FL_ALIGN_CENTER ); - //openair_daq_vars.use_ia_receiver = 0; - fl_set_button(fdui->button_0,0); - fl_set_object_label(fdui->button_0, "IA Receiver OFF"); - fl_set_object_color(fdui->button_0, FL_RED, FL_RED); - fl_set_object_callback(fdui->button_0, ia_receiver_on_off, 0 ); - fl_hide_object(fdui->button_0); + // Generic eNB Button + if (0) { // code kept to later add command buttons + fdui->button_0 = fl_add_button( FL_PUSH_BUTTON, 20, 600, 240, 40, "" ); + fl_set_object_lalign(fdui->button_0, FL_ALIGN_CENTER ); + fl_set_button(fdui->button_0,0); + otg_enabled = 0; + fl_set_object_label(fdui->button_0, "DL Traffic OFF"); + fl_set_object_color(fdui->button_0, FL_RED, FL_RED); + fl_set_object_callback(fdui->button_0, dl_traffic_on_off, 0 ); + } fl_end_form( ); - fdui->phy_scope_nrue->fdui = fdui; - + fdui->phy_scope->fdui = fdui; + char title[100]; + sprintf (title, "LTE UL SCOPE eNB for UE %d",UE_id); + fl_show_form (fdui->phy_scope, FL_PLACE_HOTSPOT, FL_FULLBORDER, title); return fdui; } -void phy_scope_nrUE(FD_phy_scope_nrue *form, - PHY_VARS_NR_UE *phy_vars_ue, - int eNB_id, - int UE_id, - uint8_t subframe) -{ - int i,arx,atx,ind,k; - NR_DL_FRAME_PARMS *frame_parms = &phy_vars_ue->frame_parms; - //int nsymb_ce = frame_parms->ofdm_symbol_size;//*frame_parms->symbols_per_tti; - int samples_per_frame = frame_parms->samples_per_frame; - uint8_t nb_antennas_rx = frame_parms->nb_antennas_rx; - uint8_t nb_antennas_tx = frame_parms->nb_antenna_ports_gNB; - int16_t **rxsig_t; - float **rxsig_t_dB; - float *time; - float *corr; - int16_t **chest_t; - int16_t **chest_f; - int16_t *pdsch_llr; - int16_t *pdsch_comp; - //int16_t *pdsch_mag; - int8_t *pdcch_llr; - int16_t *pdcch_comp; - int16_t *pbch_llr; - int16_t *pbch_comp; - float llr_pbch[1920], bit_pbch[1920]; - float *llr, *bit; - float *llr_pdcch, *bit_pdcch; - float *I, *Q; - int num_pdcch_symbols=2; - int num_re = 4500; - int Qm = 2; - int coded_bits_per_codeword = num_re*Qm; - int symbol, first_symbol=2,nb_re; - int nb_rb_pdsch=50,nb_symb_sch=9; - float ymax=1; - float **chest_t_abs; - float Re,Im; - float *chest_f_abs; - float *freq; - static int overlay = 0; - /* - int frame = phy_vars_ue->proc.proc_rxtx[0].frame_rx; - int mcs = 0; - unsigned char harq_pid = 0; - */ +static FD_phy_scope_t *form_gnb[NUMBER_OF_UE_MAX]= {0}; +static unsigned char scope_enb_num_ue = 1; - /* - if (phy_vars_ue->dlsch[phy_vars_ue->current_thread_id[subframe]][eNB_id][0]!=NULL) { - harq_pid = phy_vars_ue->dlsch[phy_vars_ue->current_thread_id[subframe]][eNB_id][0]->current_harq_pid; +static void *scope_thread_gNB(void *arg) { + scopeParms_t *p=(scopeParms_t *) arg; + //# ifdef ENABLE_XFORMS_WRITE_STATS + // FILE *gNB_stats = fopen("gNB_stats.txt", "w"); + //#endif + size_t stksize; + pthread_attr_t atr; + pthread_attr_getstacksize(&atr, &stksize); + pthread_attr_setstacksize(&atr,32*1024*1024 ); + sleep(3); // no clean interthread barriers - if (harq_pid>=8) - return; + while (!oai_exit) { + int ue_cnt=0; - mcs = phy_vars_ue->dlsch[phy_vars_ue->current_thread_id[subframe]][eNB_id][0]->harq_processes[harq_pid]->mcs; - - // Button 0 - if(!phy_vars_ue->dlsch[phy_vars_ue->current_thread_id[subframe]][eNB_id][0]->harq_processes[harq_pid]->dl_power_off) { - // we are in TM5 - fl_show_object(form->button_0); + for(int UE_id=0; UE_idgNB, p->ru, UE_id); + ue_cnt++; + } } + + usleep(99*1000); } - if (phy_vars_ue->pdcch_vars[phy_vars_ue->current_thread_id[subframe]][eNB_id]!=NULL) { - num_pdcch_symbols = phy_vars_ue->pdcch_vars[phy_vars_ue->current_thread_id[subframe]][eNB_id]->num_pdcch_symbols; - } + // printf("%s",stats_buffer); + /*#ifdef ENABLE_XFORMS_WRITE_STATS - // coded_bits_per_codeword = frame_parms->N_RB_DL*12*get_Qm(mcs)*(frame_parms->symbols_per_tti); - if (phy_vars_ue->dlsch[phy_vars_ue->current_thread_id[subframe]][eNB_id][0]!=NULL) { - coded_bits_per_codeword = get_G(frame_parms, - phy_vars_ue->dlsch[phy_vars_ue->current_thread_id[subframe]][eNB_id][0]->harq_processes[harq_pid]->nb_rb, - phy_vars_ue->dlsch[phy_vars_ue->current_thread_id[subframe]][eNB_id][0]->harq_processes[harq_pid]->rb_alloc_even, - get_Qm(mcs), - phy_vars_ue->dlsch[phy_vars_ue->current_thread_id[subframe]][eNB_id][0]->harq_processes[harq_pid]->Nl, - num_pdcch_symbols, - frame, - subframe, - beamforming_mode); - } else { - coded_bits_per_codeword = 0; //frame_parms->N_RB_DL*12*get_Qm(mcs)*(frame_parms->symbols_per_tti); - } + if (eNB_stats) { + rewind (gNB_stats); + fwrite (stats_buffer, 1, len, gNB_stats); + fclose (gNB_stats); + } + + #endif + pthread_exit((void *)arg); + }*/ + return NULL; +} + +void gNBinitScope(scopeParms_t *p) { + //FD_stats_form *form_stats=NULL,*form_stats_l2=NULL; + fl_initialize (p->argc, p->argv, NULL, 0, 0); + + /* + form_stats_l2 = create_form_stats_form(); + fl_show_form (form_stats_l2->stats_form, FL_PLACE_HOTSPOT, FL_FULLBORDER, "l2 stats"); + form_stats = create_form_stats_form(); + fl_show_form (form_stats->stats_form, FL_PLACE_HOTSPOT, FL_FULLBORDER, "stats"); */ - I = (float*) calloc(frame_parms->ofdm_symbol_size*frame_parms->symbols_per_slot*2,sizeof(float)); - Q = (float*) calloc(frame_parms->ofdm_symbol_size*frame_parms->symbols_per_slot*2,sizeof(float)); + for(int UE_id=0; UE_idofdm_symbol_size,sizeof(float)); - } - - chest_f_abs = (float*) calloc(frame_parms->ofdm_symbol_size,sizeof(float)); - freq = (float*) calloc(frame_parms->ofdm_symbol_size,sizeof(float)); - - llr = (float*) calloc(coded_bits_per_codeword,sizeof(float)); // init to zero - bit = malloc(coded_bits_per_codeword*sizeof(float)); - - llr_pdcch = (float*) calloc(12*frame_parms->N_RB_DL*num_pdcch_symbols*2,sizeof(float)); // init to zero - bit_pdcch = (float*) calloc(12*frame_parms->N_RB_DL*num_pdcch_symbols*2,sizeof(float)); - - rxsig_t = (int16_t**) phy_vars_ue->common_vars.rxdata; - rxsig_t_dB = calloc(nb_antennas_rx,sizeof(float*)); - for (arx=0; arxpbch_vars[eNB_id]->dl_ch_estimates_time; - chest_f = (int16_t**) phy_vars_ue->pbch_vars[eNB_id]->dl_ch_estimates; - - pbch_llr = (int16_t*) phy_vars_ue->pbch_vars[eNB_id]->llr; - pbch_comp = (int16_t*) phy_vars_ue->pbch_vars[eNB_id]->rxdataF_comp[0]; - - pdcch_llr = (int8_t*) phy_vars_ue->pdcch_vars[phy_vars_ue->current_thread_id[subframe]][eNB_id]->llr; - pdcch_comp = (int16_t*) phy_vars_ue->pdcch_vars[phy_vars_ue->current_thread_id[subframe]][eNB_id]->rxdataF_comp[0]; - pdsch_llr = (int16_t*) phy_vars_ue->pdsch_vars[phy_vars_ue->current_thread_id[subframe]][eNB_id]->llr[0]; // stream 0 - // pdsch_llr = (int16_t*) phy_vars_ue->lte_ue_pdsch_vars_SI[eNB_id]->llr[0]; // stream 0 - pdsch_comp = (int16_t*) phy_vars_ue->pdsch_vars[phy_vars_ue->current_thread_id[subframe]][eNB_id]->rxdataF_comp0[0]; - //pdsch_mag = (int16_t*) phy_vars_ue->pdsch_vars[phy_vars_ue->current_thread_id[subframe]][eNB_id]->dl_ch_mag0[0]; + static scopeParms_t parms; + memcpy(&parms,p,sizeof(parms)); + pthread_t forms_thread; + threadCreate(&forms_thread, scope_thread_gNB, &parms, "scope", -1, OAI_PRIORITY_RT_LOW); +} +static void ueTimeResponse (FL_OBJECT *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { // Received signal in time domain of receive antenna 0 - if (rxsig_t != NULL) { - if (rxsig_t[0] != NULL) { - for (i=0; icommon_vars.rxdata) + return; - fl_set_xyplot_data(form->rxsig_t,time,rxsig_t_dB[0],samples_per_frame,"","",""); + NR_DL_FRAME_PARMS *frame_parms = &phy_vars_ue->frame_parms; + uint8_t nb_antennas_rx = frame_parms->nb_antennas_rx; + int samples_per_frame = frame_parms->samples_per_frame; + scopeSample_t **rxsig_t = (scopeSample_t **) phy_vars_ue->common_vars.rxdata; + float rxsig_t_dB[samples_per_frame]; + float time[samples_per_frame]; + + if (rxsig_t[0] != NULL) { + for (int i=0; irxsig_t,arx,time,rxsig_t_dB[arx],FRAME_LENGTH_COMPLEX_SAMPLES,rx_antenna_colors[arx]); + for (int arx=1; arxis_synchronized==0) { - for (ind=0;ind<3;ind++) { + //float corr[samples_per_frame]; + for (int ind=0; ind<3; ind++) { /* - if (pss_corr_ue[ind]) { - for (i=0; ichest_t,time,corr,samples_per_frame,"","",""); - else - fl_add_xyplot_overlay(form->chest_t,ind,time,corr,samples_per_frame,rx_antenna_colors[ind]); + if (pss_corr_ue[ind]) { + for (i=0; ichest_t,time,corr,samples_per_frame,"","",""); + else + fl_add_xyplot_overlay(form->chest_t,ind,time,corr,samples_per_frame,rx_antenna_colors[ind]); + + overlay = 1; + } */ } - } - else { - - if (overlay) { //there was a previous overlay - fl_clear_xyplot(form->chest_t); - overlay = 0; - } + // if the UE is not synchronized, we can make only the time*power graph + } +} + +static void ueChannelResponse (FL_OBJECT *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { // Channel Impulse Response - if (chest_t != NULL) { - ymax = 0; + if (!phy_vars_ue->pbch_vars[eNB_id]->dl_ch_estimates_time) + return; - if (chest_t[0] !=NULL) { - for (i=0; i<(frame_parms->ofdm_symbol_size>>3); i++) { - chest_t_abs[0][i] = (float) (chest_t[0][2*i]*chest_t[0][2*i]+chest_t[0][2*i+1]*chest_t[0][2*i+1]); - time[i] = (float) i; + NR_DL_FRAME_PARMS *frame_parms = &phy_vars_ue->frame_parms; + uint8_t nb_antennas_rx = frame_parms->nb_antennas_rx; + scopeSample_t **chest_t = (scopeSample_t **) phy_vars_ue->pbch_vars[eNB_id]->dl_ch_estimates_time; + int ymax = 0; + float chest_t_abs[frame_parms->ofdm_symbol_size]; + float time[frame_parms->ofdm_symbol_size>>3]; - if (chest_t_abs[0][i] > ymax) - ymax = chest_t_abs[0][i]; - } + if (chest_t[0] !=NULL) { + for (int i=0; i<(frame_parms->ofdm_symbol_size>>3); i++) { + chest_t_abs[i] = SquaredNorm(chest_t[0][i]); + time[i] = (float) i; - fl_set_xyplot_data(form->chest_t,time,chest_t_abs[0],(frame_parms->ofdm_symbol_size>>3),"","",""); + if (chest_t_abs[i] > ymax) + ymax = chest_t_abs[i]; } - /* - for (arx=1; arxofdm_symbol_size>>3); i++) { - chest_t_abs[arx][i] = (float) (chest_t[arx][4*i]*chest_t[arx][4*i]+chest_t[arx][4*i+1]*chest_t[arx][4*i+1]); - if (chest_t_abs[arx][i] > ymax) - ymax = chest_t_abs[arx][i]; - } - - fl_add_xyplot_overlay(form->chest_t,arx,time,chest_t_abs[arx],(frame_parms->ofdm_symbol_size>>3),rx_antenna_colors[arx]); - fl_set_xyplot_overlay_type(form->chest_t,arx,FL_DASHED_XYPLOT); - } - } - */ - // Avoid flickering effect - // fl_get_xyplot_ybounds(form->chest_t,&ymin,&ymax); // Does not always work... - fl_set_xyplot_ybounds(form->chest_t,0,(double) ymax); - } + fl_set_xyplot_data(graph,time,chest_t_abs,(frame_parms->ofdm_symbol_size>>3),"","",""); } + for (int arx=1; arxofdm_symbol_size>>3); i++) { + chest_t_abs[i] = SquaredNorm(chest_t[arx][i]); + + if (chest_t_abs[i] > ymax) + ymax = chest_t_abs[i]; + } + + fl_add_xyplot_overlay(graph,arx,time,chest_t_abs,(frame_parms->ofdm_symbol_size>>3),rx_antenna_colors[arx]); + fl_set_xyplot_overlay_type(graph,arx,FL_DASHED_XYPLOT); + } + } + + // Avoid flickering effect + // fl_get_xyplot_ybounds(form->chest_t,&ymin,&ymax); // Does not always work... + fl_set_xyplot_ybounds(graph,0,(double) ymax); +} + +static void uePbchFrequencyResp (FL_OBJECT *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { // Channel Frequency Response (includes 5 complex sample for filter) - if (chest_f != NULL) { - ind = 0; + if (!phy_vars_ue->pbch_vars[eNB_id]->dl_ch_estimates) + return; - for (atx=0; atxofdm_symbol_size; k++) { - freq[ind] = (float)ind; - Re = (float)(chest_f[(atx<<1)+arx][6144+(2*k)]); - Im = (float)(chest_f[(atx<<1)+arx][6144+(2*k)+1]); + NR_DL_FRAME_PARMS *frame_parms = &phy_vars_ue->frame_parms; + uint8_t nb_antennas_rx = frame_parms->nb_antennas_rx; + uint8_t nb_antennas_tx = frame_parms->nb_antenna_ports_gNB; + scopeSample_t **chest_f = (scopeSample_t **) phy_vars_ue->pbch_vars[eNB_id]->dl_ch_estimates; + int ind = 0; + float chest_f_abs[frame_parms->ofdm_symbol_size]; + float freq[frame_parms->ofdm_symbol_size]; - chest_f_abs[ind] = (short)10*log10(1.0+((double)Re*Re + (double)Im*Im)); - ind++; - } + for (int atx=0; atxofdm_symbol_size; k++) { + freq[ind] = (float)ind; + chest_f_abs[ind] = (short)10*log10(1.0+SquaredNorm(chest_f[(atx<<1)+arx][6144+k])); + ind++; } } } - - // tx antenna 0 - //fl_set_xyplot_xbounds(form->chest_f,0,nb_antennas_rx*nb_antennas_tx*nsymb_ce); - //fl_set_xyplot_xtics(form->chest_f,nb_antennas_rx*nb_antennas_tx*frame_parms->symbols_per_tti,2); - // fl_set_xyplot_xtics(form->chest_f,nb_antennas_rx*nb_antennas_tx*2,2); - //fl_set_xyplot_xgrid(form->chest_f,FL_GRID_MAJOR); - fl_set_xyplot_data(form->chest_f,freq,chest_f_abs,frame_parms->ofdm_symbol_size,"","",""); - - /* - for (arx=1; arxchest_f,1,&freq[arx*nsymb_ce],&chest_f_abs[arx*nsymb_ce],nsymb_ce,rx_antenna_colors[arx]); - } - - // other tx antennas - if (nb_antennas_tx > 1) { - if (nb_antennas_rx > 1) { - for (atx=1; atxchest_f,(atx<<1)+arx,&freq[((atx<<1)+arx)*nsymb_ce],&chest_f_abs[((atx<<1)+arx)*nsymb_ce],nsymb_ce,rx_antenna_colors[arx]); - } - } - } else { // 1 rx antenna - atx=1; - arx=0; - fl_add_xyplot_overlay(form->chest_f,atx,&freq[atx*nsymb_ce],&chest_f_abs[atx*nsymb_ce],nsymb_ce,rx_antenna_colors[arx]); - } - } - */ } - + + // tx antenna 0 + //fl_set_xyplot_xbounds(form->chest_f,0,nb_antennas_rx*nb_antennas_tx*nsymb_ce); + //fl_set_xyplot_xtics(form->chest_f,nb_antennas_rx*nb_antennas_tx*frame_parms->symbols_per_tti,2); + // fl_set_xyplot_xtics(form->chest_f,nb_antennas_rx*nb_antennas_tx*2,2); + //fl_set_xyplot_xgrid(form->chest_f,FL_GRID_MAJOR); + fl_set_xyplot_data(graph,freq,chest_f_abs,frame_parms->ofdm_symbol_size,"","",""); +} + +static void uePbchLLR (FL_OBJECT *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { // PBCH LLRs - if (pbch_llr != NULL) { - for (i=0; i<864; i++) { - llr_pbch[i] = (float) pbch_llr[i]; - bit_pbch[i] = (float) i; - } + if ( !phy_vars_ue->pbch_vars[eNB_id]->llr) + return; - fl_set_xyplot_data(form->pbch_llr,bit_pbch,llr_pbch,864,"","",""); + int16_t *pbch_llr = (int16_t *) phy_vars_ue->pbch_vars[eNB_id]->llr; + float llr_pbch[864], bit_pbch[864]; + + for (int i=0; i<864; i++) { + llr_pbch[i] = (float) pbch_llr[i]; + bit_pbch[i] = (float) i; } - first_symbol=1; + fl_set_xyplot_data(graph,bit_pbch,llr_pbch,864,"","",""); +} +static void uePbchIQ (FL_OBJECT *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { // PBCH I/Q of MF Output - if (pbch_comp!=NULL) { - for (symbol=first_symbol; symbol<(first_symbol+3); symbol++) { - if (symbol == 2 || symbol == 6) - nb_re = 72; - else - nb_re = 180; - for (i=0; ipbch_vars[eNB_id]->rxdataF_comp[0]) + return; + + int16_t *pbch_comp = (int16_t *) phy_vars_ue->pbch_vars[eNB_id]->rxdataF_comp[0]; + localBuff(I,180*3); + localBuff(Q,180*3); + int first_symbol=1; + int base=0; + + for (int symbol=first_symbol; symbol<(first_symbol+3); symbol++) { + int nb_re; + + if (symbol == 2 || symbol == 6) + nb_re = 72; + else + nb_re = 180; + + AssertFatal(base+nb_re<180*3,""); + + for (int i=0; ipbch_comp,I,Q,432,"","",""); + + base+=nb_re; } + fl_set_xyplot_data(graph,I,Q,base,"","",""); +} + +static void uePcchLLR (FL_OBJECT *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { // PDCCH LLRs - if (pdcch_llr != NULL) { - for (i=0; i<100; i++) { //12*frame_parms->N_RB_DL*2*num_pdcch_symbols - llr_pdcch[i] = (float) pdcch_llr[2*24*9 +i]; - bit_pdcch[i] = (float) i; - } + if (!phy_vars_ue->pdcch_vars[0][eNB_id]->llr) + return; - fl_set_xyplot_data(form->pdcch_llr,bit_pdcch,llr_pdcch,12*frame_parms->N_RB_DL*num_pdcch_symbols,"","",""); - } + NR_DL_FRAME_PARMS *frame_parms = &phy_vars_ue->frame_parms; + uint8_t nb_antennas_rx = frame_parms->nb_antennas_rx; + uint8_t nb_antennas_tx = frame_parms->nb_antennas_tx; + scopeSample_t **chest_f = (scopeSample_t **) phy_vars_ue->pbch_vars[eNB_id]->dl_ch_estimates; + int ind = 0; + float chest_f_abs[frame_parms->ofdm_symbol_size]; + float freq[frame_parms->ofdm_symbol_size]; - // PDCCH I/Q of MF Output - if (pdcch_comp!=NULL) { - for (i=0; i<100; i++) { - I[i] = pdcch_comp[2*50*12+2*i]; - Q[i] = pdcch_comp[2*50*12+2*i+1]; - } - fl_set_xyplot_data(form->pdcch_comp,I,Q,12*frame_parms->N_RB_DL*num_pdcch_symbols,"","",""); - } - - // PDSCH LLRs - if (pdsch_llr != NULL) { - for (i=0; ipdsch_llr,0,coded_bits_per_codeword); - fl_set_xyplot_data(form->pdsch_llr,bit,llr,coded_bits_per_codeword,"","",""); - } - - first_symbol = 2; - ind = 0; - // PDSCH I/Q of MF Output - if (pdsch_comp!=NULL) { - for (symbol=0;symbolN_RB_DL*12+i) ]; - Q[ind] = pdsch_comp[2*((first_symbol+symbol)*frame_parms->N_RB_DL*12+i)+1]; - ind++; + for (int atx=0; atxofdm_symbol_size; k++) { + freq[ind] = (float)ind; + chest_f_abs[ind] = (short)10*log10(1.0+SquaredNorm(chest_f[(atx<<1)+arx][6144+k])); + ind++; + } } } - - fl_set_xyplot_data(form->pdsch_comp,I,Q,nb_symb_sch*nb_rb_pdsch*12,"","",""); } + + // tx antenna 0 + //fl_set_xyplot_xbounds(form->chest_f,0,nb_antennas_rx*nb_antennas_tx*nsymb_ce); + //fl_set_xyplot_xtics(form->chest_f,nb_antennas_rx*nb_antennas_tx*frame_parms->symbols_per_tti,2); + // fl_set_xyplot_xtics(form->chest_f,nb_antennas_rx*nb_antennas_tx*2,2); + //fl_set_xyplot_xgrid(form->chest_f,FL_GRID_MAJOR); + fl_set_xyplot_data(graph,freq,chest_f_abs,frame_parms->ofdm_symbol_size,"","",""); +} + +static void uePcchIQ (FL_OBJECT *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { + // PDCCH I/Q of MF Output + if (!phy_vars_ue->pdcch_vars[0][eNB_id]->rxdataF_comp[0]) + return; + + int nb=12*273*4; // 12*frame_parms->N_RB_DL*num_pdcch_symbols + localBuff(I,nb*RX_NB_TH_MAX); + localBuff(Q,nb*RX_NB_TH_MAX); + int base=0; + + for (int thr=0 ; thr < RX_NB_TH_MAX ; thr ++ ) { + int16_t *pdcch_comp = (int16_t *) phy_vars_ue->pdcch_vars[thr][eNB_id]->rxdataF_comp[0]; + + for (int i=0; i< nb; i++) { + I[base+i] = pdcch_comp[i*2]; + Q[base+i] = pdcch_comp[i*2+1]; + } + + base+=nb; + } + + fl_set_xyplot_data(graph,I,Q,base,"","",""); +} + +static void uePdschLLR (FL_OBJECT *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { + // PDSCH LLRs + if (!phy_vars_ue->pdsch_vars[0][eNB_id]->llr[0]) + return; + + int num_re = 4500; + int Qm = 2; + int coded_bits_per_codeword = num_re*Qm; + localBuff(llr,coded_bits_per_codeword*RX_NB_TH_MAX); + localBuff(bit,coded_bits_per_codeword*RX_NB_TH_MAX); + int base=0; + + for (int thr=0 ; thr < RX_NB_TH_MAX ; thr ++ ) { + int16_t *pdsch_llr = (int16_t *) phy_vars_ue->pdsch_vars[thr][eNB_id]->llr[0]; // stream 0 + + for (int i=0; ipdsch_llr,0,coded_bits_per_codeword); + fl_set_xyplot_data(graph,bit,llr,base,"","",""); +} + +static void uePdschIQ (FL_OBJECT *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { + // PDSCH I/Q of MF Output + if (!phy_vars_ue->pdsch_vars[0][eNB_id]->rxdataF_comp0[0]) + return; + + NR_DL_FRAME_PARMS *frame_parms = &phy_vars_ue->frame_parms; + int sz=7*2*frame_parms->N_RB_DL*12; // size of the malloced buffer + localBuff(I,sz*RX_NB_TH_MAX); + localBuff(Q,sz*RX_NB_TH_MAX); + int base=0; + + for (int thr=0 ; thr < RX_NB_TH_MAX ; thr ++ ) { + int16_t *pdsch_comp = (int16_t *) phy_vars_ue->pdsch_vars[thr][eNB_id]->rxdataF_comp0[0]; + + for (int s=0; s tput_ue_max[UE_id]) { - tput_ue_max[UE_id] = tput_ue[UE_id][TPUT_WINDOW_LENGTH-1]; + tput_ue_max[UE_id] = tput_ue[UE_id][TPUT_WINDOW_LENGTH-1]; } fl_set_xyplot_data(form->pdsch_tput,tput_time_ue[UE_id],tput_ue[UE_id],TPUT_WINDOW_LENGTH,"","",""); fl_set_xyplot_ybounds(form->pdsch_tput,0,tput_ue_max[UE_id]); */ - - fl_check_forms(); - - free(time); - free(corr); - for (arx=0; arxphy_scope = fl_bgn_form( FL_NO_BOX, 800, 900 ); + // This the whole UI box + obj = fl_add_box( FL_BORDER_BOX, 0, 0, 800, 900, "" ); + fl_set_object_color( obj, FL_BLACK, FL_BLACK ); + // Received signal + fdui->graph[0] = nrUEcommonGraph(ueTimeResponse, + FL_IMPULSE_XYPLOT, 20, 20, 370, 100, "Received Signal (Time-Domain, dB)", FL_RED ); + // Time-domain channel response + fdui->graph[1] = nrUEcommonGraph(ueChannelResponse, + FL_NORMAL_XYPLOT, 410, 20, 370, 100, "Channel Impulse Response (samples, abs)", FL_RED ); + // Frequency-domain channel response + fdui->graph[2] = nrUEcommonGraph(uePbchFrequencyResp, + FL_IMPULSE_XYPLOT, 20, 140, 760, 100, "Channel Frequency data (RE, dB)", FL_RED ); + // LLR of PBCH + fdui->graph[3] = nrUEcommonGraph(uePbchLLR, + FL_POINTS_XYPLOT, 20, 260, 500, 100, "PBCH Log-Likelihood Ratios (LLR, mag)", FL_GREEN ); + fl_set_xyplot_xgrid(fdui->graph[3].graph,FL_GRID_MAJOR); + // I/Q PBCH comp + fdui->graph[4] = nrUEcommonGraph(uePbchIQ, + FL_POINTS_XYPLOT, 540, 260, 240, 100, "PBCH I/Q of MF Output", FL_GREEN ); + // LLR of PDCCH + fdui->graph[5] = nrUEcommonGraph(uePcchLLR, + FL_POINTS_XYPLOT, 20, 380, 500, 100, "PDCCH Log-Likelihood Ratios (LLR, mag)", FL_CYAN ); + // I/Q PDCCH comp + fdui->graph[6] = nrUEcommonGraph(uePcchIQ, + FL_POINTS_XYPLOT, 540, 380, 240, 100, "PDCCH I/Q of MF Output", FL_CYAN ); + // LLR of PDSCH + fdui->graph[7] = nrUEcommonGraph(uePdschLLR, + FL_POINTS_XYPLOT, 20, 500, 500, 200, "PDSCH Log-Likelihood Ratios (LLR, mag)", FL_YELLOW ); + // I/Q PDSCH comp + fdui->graph[8] = nrUEcommonGraph(uePdschIQ, + FL_POINTS_XYPLOT, 540, 500, 240, 200, "PDSCH I/Q of MF Output", FL_YELLOW ); + // Throughput on PDSCH + fdui->graph[9] = nrUEcommonGraph(uePdschThroughput, + FL_NORMAL_XYPLOT, 20, 720, 500, 100, "PDSCH Throughput [frame]/[kbit/s]", FL_WHITE ); + fdui->graph[10].graph=NULL; + // Generic UE Button + fdui->button_0 = fl_add_button( FL_PUSH_BUTTON, 540, 720, 240, 40, "" ); + fl_set_object_lalign(fdui->button_0, FL_ALIGN_CENTER ); + //openair_daq_vars.use_ia_receiver = 0; + fl_set_button(fdui->button_0,0); + fl_set_object_label(fdui->button_0, "IA Receiver OFF"); + fl_set_object_color(fdui->button_0, FL_RED, FL_RED); + fl_set_object_callback(fdui->button_0, ia_receiver_on_off, 0 ); + fl_hide_object(fdui->button_0); + fl_end_form( ); + fdui->phy_scope->fdui = fdui; + char buf[100]; + sprintf(buf,"NR DL SCOPE UE %d", ID); + fl_show_form (fdui->phy_scope, FL_PLACE_HOTSPOT, FL_FULLBORDER, buf); + return fdui; +} +void phy_scope_nrUE(FD_phy_scope_t *form, + PHY_VARS_NR_UE *phy_vars_ue, + int eNB_id, + int UE_id) { + static FD_phy_scope_t *remeberForm=NULL; -// current status is that every UE has a DL scope for a SINGLE eNB (gnb_id=0) -// at eNB 0, an UL scope for every UE -FD_phy_scope_gnb *form_gnb[NUMBER_OF_UE_MAX]; + if (form==NULL) + form=remeberForm; + else + remeberForm=form; + + if (form==NULL) + return; + + int i=0; + + while (form->graph[i].graph) { + form->graph[i].nrUEfunct(form->graph[i].graph, phy_vars_ue, eNB_id, UE_id); + i++; + } + + fl_check_forms(); +} + +static FD_phy_scope_t *form_nrue[NUMBER_OF_UE_MAX]; +static pthread_t forms_thread; + +static void *nrUEscopeThread(void *arg) { + PHY_VARS_NR_UE *ue=(PHY_VARS_NR_UE *)arg; + size_t stksize; + pthread_attr_t atr; + pthread_attr_getstacksize(&atr, &stksize); + pthread_attr_setstacksize(&atr,32*1024*1024 ); + + while (!oai_exit) { + phy_scope_nrUE(form_nrue[0], + ue, + 0,0); + usleep(99*1000); + } + + pthread_exit((void *)arg); +} + +void nrUEinitScope(PHY_VARS_NR_UE *ue) { + int fl_argc=1; + char *name="5G-UE-scope"; + fl_initialize (&fl_argc, &name, NULL, 0, 0); + form_nrue[0] = create_phy_scope_nrue(0); + threadCreate(&forms_thread, nrUEscopeThread, ue, "scope", -1, OAI_PRIORITY_RT_LOW); +} + +// Kept to put back the functionality soon +#if 0 //FD_stats_form *form_stats=NULL,*form_stats_l2=NULL; //char title[255]; -unsigned char scope_enb_num_ue = 1; //static pthread_t forms_thread; //xforms - - -void reset_stats_gNB(FL_OBJECT *button, - long arg) -{ +static void reset_stats_gNB(FL_OBJECT *button, + long arg) { int i,k; //PHY_VARS_gNB *phy_vars_gNB = RC.gNB[0][0]; for (i=0; idlsch[i][0]->Mlimit; j++) { - phy_vars_gNB->UE_stats[i].dlsch_NAK[k][j]=0; - phy_vars_gNB->UE_stats[i].dlsch_ACK[k][j]=0; - phy_vars_gNB->UE_stats[i].dlsch_trials[k][j]=0; - } - phy_vars_gNB->UE_stats[i].dlsch_l2_errors[k]=0; - phy_vars_gNB->UE_stats[i].ulsch_errors[k]=0; - phy_vars_gNB->UE_stats[i].ulsch_consecutive_errors=0; - phy_vars_gNB->UE_stats[i].dlsch_sliding_cnt=0; - phy_vars_gNB->UE_stats[i].dlsch_NAK_round0=0; - phy_vars_gNB->UE_stats[i].dlsch_mcs_offset=0;*/ - } - } -} - - -static void *scope_thread_gNB(void *arg) { - scopeParms_t * p=(scopeParms_t *) arg; -//# ifdef ENABLE_XFORMS_WRITE_STATS -// FILE *gNB_stats = fopen("gNB_stats.txt", "w"); -//#endif - - while (!oai_exit) { - int ue_cnt=0; - - for(int UE_id=0; UE_idgNB, p->ru, UE_id); - ue_cnt++; + phy_vars_gNB->UE_stats[i].dlsch_NAK[k][j]=0; + phy_vars_gNB->UE_stats[i].dlsch_ACK[k][j]=0; + phy_vars_gNB->UE_stats[i].dlsch_trials[k][j]=0; } + phy_vars_gNB->UE_stats[i].dlsch_l2_errors[k]=0; + phy_vars_gNB->UE_stats[i].ulsch_errors[k]=0; + phy_vars_gNB->UE_stats[i].ulsch_consecutive_errors=0; + phy_vars_gNB->UE_stats[i].dlsch_sliding_cnt=0; + phy_vars_gNB->UE_stats[i].dlsch_NAK_round0=0; + phy_vars_gNB->UE_stats[i].dlsch_mcs_offset=0;*/ } - sleep(1); } - -// printf("%s",stats_buffer); -/*#ifdef ENABLE_XFORMS_WRITE_STATS - - if (eNB_stats) { - rewind (gNB_stats); - fwrite (stats_buffer, 1, len, gNB_stats); - fclose (gNB_stats); - } - -#endif - pthread_exit((void *)arg); -}*/ - - return NULL; } -FD_stats_form * create_form_stats_form( void ) { +static FD_stats_form *create_form_stats_form(int ID) { FL_OBJECT *obj; FD_stats_form *fdui = fl_malloc( sizeof *fdui ); fdui->vdata = fdui->cdata = NULL; @@ -963,24 +905,8 @@ FD_stats_form * create_form_stats_form( void ) { fdui->stats_form->fdui = fdui; return fdui; } +#endif + + -void startScope(scopeParms_t * p) { - //FD_stats_form *form_stats=NULL,*form_stats_l2=NULL; - char title[255]; - fl_initialize (p->argc, p->argv, NULL, 0, 0); - /* - form_stats_l2 = create_form_stats_form(); - fl_show_form (form_stats_l2->stats_form, FL_PLACE_HOTSPOT, FL_FULLBORDER, "l2 stats"); - form_stats = create_form_stats_form(); - fl_show_form (form_stats->stats_form, FL_PLACE_HOTSPOT, FL_FULLBORDER, "stats"); - */ - - for(int UE_id=0; UE_idphy_scope_gnb, FL_PLACE_HOTSPOT, FL_FULLBORDER, title); - } // UE_id - pthread_t forms_thread; - threadCreate(&forms_thread, scope_thread_gNB, p, "scope", -1, OAI_PRIORITY_RT_LOW); -} diff --git a/openair1/PHY/TOOLS/nr_phy_scope.h b/openair1/PHY/TOOLS/nr_phy_scope.h index 29229d6b12..274b1a620c 100644 --- a/openair1/PHY/TOOLS/nr_phy_scope.h +++ b/openair1/PHY/TOOLS/nr_phy_scope.h @@ -35,55 +35,15 @@ //#include "PHY/impl_defs_top.h" #include "PHY/defs_nr_UE.h" -/* Forms and Objects */ -typedef struct { - FL_FORM * phy_scope_gnb; - FL_OBJECT * rxsig_t; - FL_OBJECT * chest_f; - FL_OBJECT * chest_t; - FL_OBJECT * pusch_comp; - FL_OBJECT * pucch_comp; - FL_OBJECT * pucch_comp1; - FL_OBJECT * pusch_llr; - FL_OBJECT * pusch_tput; - FL_OBJECT * button_0; -} FD_phy_scope_gnb; - -typedef struct { - FL_FORM * phy_scope_nrue; - FL_OBJECT * rxsig_t; - FL_OBJECT * chest_f; - FL_OBJECT * chest_t; - FL_OBJECT * pbch_comp; - FL_OBJECT * pbch_llr; - FL_OBJECT * pdcch_comp; - FL_OBJECT * pdcch_llr; - FL_OBJECT * pdsch_comp; - FL_OBJECT * pdsch_llr; - FL_OBJECT * pdsch_comp1; - FL_OBJECT * pdsch_llr1; - FL_OBJECT * pdsch_tput; - FL_OBJECT * button_0; -} FD_phy_scope_nrue; - typedef struct { int *argc; char **argv; - RU_t* ru; + RU_t *ru; PHY_VARS_gNB *gNB; } scopeParms_t; -extern unsigned char scope_enb_num_ue; -FD_phy_scope_nrue * create_phy_scope_nrue( void ); - -void phy_scope_nrUE(FD_phy_scope_nrue *form, - PHY_VARS_NR_UE *phy_vars_ue, - int eNB_id, - int UE_id, - uint8_t subframe); - - -void startScope(scopeParms_t * p); +void gNBinitScope(scopeParms_t *p); +void nrUEinitScope(PHY_VARS_NR_UE *ue); extern RAN_CONTEXT_t RC; #endif diff --git a/targets/ARCH/rfsimulator/simulator.c b/targets/ARCH/rfsimulator/simulator.c index 45412f9eea..ad880e3cbf 100644 --- a/targets/ARCH/rfsimulator/simulator.c +++ b/targets/ARCH/rfsimulator/simulator.c @@ -476,14 +476,16 @@ static bool flushInput(rfsimulator_state_t *t, int timeout, int nsamps_for_initi b->trashingPacket=true; } else if ( b->lastReceivedTS < b->th.timestamp) { int nbAnt= b->th.nbAnt; - + if ( b->th.timestamp-b->lastReceivedTS < CirSize ) { for (uint64_t index=b->lastReceivedTS; index < b->th.timestamp; index++ ) { for (int a=0; a < nbAnt; a++) { b->circularBuf[(index*nbAnt+a)%CirSize].r = 0; b->circularBuf[(index*nbAnt+a)%CirSize].i = 0; } } - + } else { + memset(b->circularBuf, 0, sampleToByte(CirSize,1)); + } if (b->lastReceivedTS != 0 && b->th.timestamp-b->lastReceivedTS > 50 ) LOG_W(HW,"UEsock: %d gap of: %ld in reception\n", fd, b->th.timestamp-b->lastReceivedTS ); b->lastReceivedTS=b->th.timestamp; @@ -646,10 +648,11 @@ int rfsimulator_read(openair0_device *device, openair0_timestamp *ptimestamp, vo ); else { // no channel modeling sample_t *out=(sample_t *)samplesVoid[a]; - + const int64_t base=t->nextTimestamp*nbAnt+a; for ( int i=0; i < nsamps; i++ ) { - out[i].r+=ptr->circularBuf[((t->nextTimestamp+i)*nbAnt+a)%CirSize].r; - out[i].i+=ptr->circularBuf[((t->nextTimestamp+i)*nbAnt+a)%CirSize].i; + const int idx=(i*nbAnt+base)%CirSize; + out[i].r+=ptr->circularBuf[idx].r; + out[i].i+=ptr->circularBuf[idx].i; } } // end of no channel modeling } // end for a... From 45ed1e80661325485a25db7704f2d5fd3ab381b9 Mon Sep 17 00:00:00 2001 From: Thomas Schlichter Date: Mon, 15 Jun 2020 14:44:32 +0200 Subject: [PATCH 325/553] revert the number of DRB from 4 back to 5 --- openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c | 8 ++++---- openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c b/openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c index 47ffd6143c..bbc4acbd56 100644 --- a/openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c +++ b/openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c @@ -73,7 +73,7 @@ void mac_rlc_data_ind ( switch (channel_idP) { case 1 ... 3: rb = ue->srb[channel_idP - 1]; break; - case 4 ... 7: rb = ue->drb[channel_idP - 4]; break; + case 4 ... 8: rb = ue->drb[channel_idP - 4]; break; default: rb = NULL; break; } @@ -114,7 +114,7 @@ tbs_size_t mac_rlc_data_req( switch (channel_idP) { case 1 ... 3: rb = ue->srb[channel_idP - 1]; break; - case 4 ... 7: rb = ue->drb[channel_idP - 4]; break; + case 4 ... 8: rb = ue->drb[channel_idP - 4]; break; default: rb = NULL; break; } @@ -167,7 +167,7 @@ mac_rlc_status_resp_t mac_rlc_status_ind( switch (channel_idP) { case 1 ... 3: rb = ue->srb[channel_idP - 1]; break; - case 4 ... 7: rb = ue->drb[channel_idP - 4]; break; + case 4 ... 8: rb = ue->drb[channel_idP - 4]; break; default: rb = NULL; break; } @@ -228,7 +228,7 @@ rlc_buffer_occupancy_t mac_rlc_get_buffer_occupancy_ind( switch (channel_idP) { case 1 ... 3: rb = ue->srb[channel_idP - 1]; break; - case 4 ... 7: rb = ue->drb[channel_idP - 4]; break; + case 4 ... 8: rb = ue->drb[channel_idP - 4]; break; default: rb = NULL; break; } diff --git a/openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h b/openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h index 3683e50abc..f578faaf38 100644 --- a/openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h +++ b/openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h @@ -29,7 +29,7 @@ typedef void nr_rlc_ue_manager_t; typedef struct nr_rlc_ue_t { int rnti; nr_rlc_entity_t *srb[3]; - nr_rlc_entity_t *drb[4]; + nr_rlc_entity_t *drb[5]; } nr_rlc_ue_t; /***********************************************************************/ From a0f8e5ac255ecf9fee023bdfc744f6cb6c72d493 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Mon, 15 Jun 2020 21:20:03 +0200 Subject: [PATCH 326/553] removed LOG functions from nr_polar_init, they make polartest segfault. polartest to be fixed ... --- openair1/PHY/CODING/nr_polar_init.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/openair1/PHY/CODING/nr_polar_init.c b/openair1/PHY/CODING/nr_polar_init.c index 55bdedbc33..f6a700117d 100644 --- a/openair1/PHY/CODING/nr_polar_init.c +++ b/openair1/PHY/CODING/nr_polar_init.c @@ -48,7 +48,7 @@ static void nr_polar_init(t_nrPolar_params * *polarParams, //Parse the list. If the node is already created, return without initialization. while (currentPtr != NULL) { //printf("currentPtr->idx %d, (%d,%d)\n",currentPtr->idx,currentPtr->payloadBits,currentPtr->encoderLength); - LOG_D(PHY,"Looking for index %d\n",(messageType * messageLength * aggregation_prime)); + //LOG_D(PHY,"Looking for index %d\n",(messageType * messageLength * aggregation_prime)); if (currentPtr->idx == (messageType * messageLength * aggregation_prime)) return; else currentPtr = currentPtr->nextPtr; } @@ -56,9 +56,9 @@ static void nr_polar_init(t_nrPolar_params * *polarParams, // printf("currentPtr %p (polarParams %p)\n",currentPtr,polarParams); //Else, initialize and add node to the end of the linked list. t_nrPolar_params *newPolarInitNode = calloc(sizeof(t_nrPolar_params),1); - + if (newPolarInitNode != NULL) { - LOG_D(PHY,"Setting new polarParams index %d, messageType %d, messageLength %d, aggregation_prime %d\n",(messageType * messageLength * aggregation_prime),messageType,messageLength,aggregation_prime); + // LOG_D(PHY,"Setting new polarParams index %d, messageType %d, messageLength %d, aggregation_prime %d\n",(messageType * messageLength * aggregation_prime),messageType,messageLength,aggregation_prime); newPolarInitNode->idx = (messageType * messageLength * aggregation_prime); newPolarInitNode->nextPtr = NULL; //printf("newPolarInitNode->idx %d, (%d,%d,%d:%d)\n",newPolarInitNode->idx,messageType,messageLength,aggregation_prime,aggregation_level); @@ -118,7 +118,7 @@ static void nr_polar_init(t_nrPolar_params * *polarParams, newPolarInitNode->payloadBits = messageLength; newPolarInitNode->crcCorrectionBits = NR_POLAR_PUCCH_CRC_ERROR_CORRECTION_BITS; //newPolarInitNode->crc_generator_matrix=crc24c_generator_matrix(newPolarInitNode->payloadBits+newPolarInitNode->crcParityBits);//G_P - LOG_D(PHY,"New polar node, encoderLength %d, aggregation_level %d\n",newPolarInitNode->encoderLength,aggregation_level); + //LOG_D(PHY,"New polar node, encoderLength %d, aggregation_level %d\n",newPolarInitNode->encoderLength,aggregation_level); } else { AssertFatal(1 == 0, "[nr_polar_init] Incorrect Message Type(%d)", messageType); } @@ -227,7 +227,7 @@ t_nrPolar_params *nr_polar_params (int8_t messageType, while (polarParams != NULL) { - LOG_D(PHY,"nr_polar_params : tag %d (from nr_polar_init %d)\n",tag,polarParams->idx); + // LOG_D(PHY,"nr_polar_params : tag %d (from nr_polar_init %d)\n",tag,polarParams->idx); if (polarParams->idx == tag) return polarParams; From 377cfc6f0c5c763a0403272c4eb459ff71d0f17d Mon Sep 17 00:00:00 2001 From: Florian Kaltenberger Date: Fri, 12 Jun 2020 11:13:18 +0200 Subject: [PATCH 327/553] fixing an issue with libconfig --- common/config/libconfig/config_libconfig.c | 4 ++-- openair2/GNB_APP/gnb_config.c | 5 ----- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/common/config/libconfig/config_libconfig.c b/common/config/libconfig/config_libconfig.c index 2d861f2dc3..b510ca28bc 100644 --- a/common/config/libconfig/config_libconfig.c +++ b/common/config/libconfig/config_libconfig.c @@ -179,8 +179,8 @@ int config_libconfig_get(paramdef_t *cfgoptions,int numoptions, char *prefix ) { *(cfgoptions[i].u64ptr) = (uint64_t)llu; printf_params("[LIBCONFIG] %s: %llu\n", cfgpath,(long long unsigned)(*(cfgoptions[i].u64ptr)) ); } else { - *(cfgoptions[i].iptr) = llu; - printf_params("[LIBCONFIG] %s: %llu\n", cfgpath,(long long unsigned)(*(cfgoptions[i].i64ptr)) ); + *(cfgoptions[i].i64ptr) = llu; + printf_params("[LIBCONFIG] %s: %llu\n", cfgpath,(long long)(*(cfgoptions[i].i64ptr)) ); } } else { defval=config_setdefault_int64(&(cfgoptions[i]),prefix); diff --git a/openair2/GNB_APP/gnb_config.c b/openair2/GNB_APP/gnb_config.c index 3235dabb45..61aa10e47b 100644 --- a/openair2/GNB_APP/gnb_config.c +++ b/openair2/GNB_APP/gnb_config.c @@ -259,11 +259,6 @@ void fix_scc(NR_ServingCellConfigCommon_t *scc,uint64_t ssbmap) { if (*scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder!=0) scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder = NULL; - // fix libconfig (asn1c uses long) - scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.preambleReceivedTargetPower-=((long)1<<32); - *scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->p0_NominalWithGrant-=((long)1<<32); - *scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->p0_nominal-=((long)1<<32); - // fix DL and UL Allocation lists for (int i=scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count-1;i>=0;i--) { From fd1388b61e1bb4e28de828506550c9d21aeed175 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Tue, 16 Jun 2020 10:18:36 +0200 Subject: [PATCH 328/553] power values in testing gnb file --- targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_gnb.conf | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_gnb.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_gnb.conf index db8aef33ba..fe2781d62a 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_gnb.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_gnb.conf @@ -100,7 +100,7 @@ gNBs = prach_msg1_FDM = 0; prach_msg1_FrequencyStart = 0; zeroCorrelationZoneConfig = 13; - preambleReceivedTargetPower = -118; + preambleReceivedTargetPower = -100; #preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200) preambleTransMax = 6; #powerRampingStep @@ -185,7 +185,7 @@ gNBs = nrofUplinkSlots = 2; nrofUplinkSymbols = 4; //0; //4; - ssPBCH_BlockPower = 10; + ssPBCH_BlockPower = -25; } ); From 619f82cbb7573176ca9bbaeb52fa635dc075a3e1 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Tue, 16 Jun 2020 10:32:12 +0200 Subject: [PATCH 329/553] external clock in config files and padding lcid --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 2 +- targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_enb.conf | 2 +- targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_gnb.conf | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 786e81aec8..f79dad41fb 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -653,7 +653,7 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, } //Sending SDUs with size 1 //Initialize elements of sdu_lcids and sdu_lengths - sdu_lcids[0] = 0x05; // DRB + sdu_lcids[0] = 0x3f; // DRB sdu_lengths[0] = TBS_bytes - ta_len - 3; header_length_total += 2 + (sdu_lengths[0] >= 128); sdu_length_total += sdu_lengths[0]; diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_enb.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_enb.conf index 58e4e86873..ea105d86b6 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_enb.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_enb.conf @@ -258,7 +258,7 @@ RUs = ( max_pdschReferenceSignalPower = -27; max_rxgain = 118; eNB_instances = [0]; - + clock_src = "external"; } ); diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_gnb.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_gnb.conf index fe2781d62a..b63939add2 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_gnb.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_gnb.conf @@ -259,7 +259,7 @@ RUs = ( max_pdschReferenceSignalPower = -27; max_rxgain = 114; eNB_instances = [0]; - clock_src = "internal"; + clock_src = "external"; } ); From 2bee4f49745cc2ada90ac2f432ba483d81db9a33 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Tue, 16 Jun 2020 17:03:47 +0200 Subject: [PATCH 330/553] partial fix for pdsch dmrs issue decoding performance degraded. still some issue to be solved. --- openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c | 2 +- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 12 +++++++++++- openair1/SIMULATION/NR_PHY/dlsim.c | 9 +++++---- openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c | 5 +---- 4 files changed, 18 insertions(+), 10 deletions(-) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c index 340b5894b4..1a6006c3ba 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c @@ -267,7 +267,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, uint8_t dmrs_Type = harq_process->dmrsConfigType; AssertFatal(dmrs_Type == 1 || dmrs_Type == 2,"Illegal dmrs_type %d\n",dmrs_Type); - uint8_t nb_re_dmrs = 12;//(dmrs_Type==1)?6:4; + uint8_t nb_re_dmrs = (dmrs_Type==1)?6:4; // should be changed based on MAC parameters uint16_t dmrs_length = get_num_dmrs(harq_process->dlDmrsSymbPos); AssertFatal(dmrs_length == 1 || dmrs_length == 2,"Illegal dmrs_length %d\n",dmrs_length); diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index d7e77c2886..ff2a3be88e 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -3091,7 +3091,17 @@ void nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB dlsch0->current_harq_pid); else { // This is to adjust the llr offset in the case of skipping over a dmrs symbol (i.e. in case of no PDSCH REs in DMRS) if (pdsch == RA_PDSCH) ue->pdsch_vars_ra[eNB_id]->llr_offset[m]=ue->pdsch_vars_ra[eNB_id]->llr_offset[m-1]; - else if (pdsch == PDSCH) ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->llr_offset[m]=ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->llr_offset[m-1]; + else if (pdsch == PDSCH) nr_rx_pdsch(ue, + pdsch, + eNB_id, + eNB_id_i, + proc->frame_rx, + nr_tti_rx, // nr_tti_rx, + m, + first_symbol_flag, + dual_stream_UE, + i_mod, + dlsch0->current_harq_pid); else AssertFatal(1==0,"not RA_PDSCH or PDSCH\n"); } if (pdsch == PDSCH) LOG_D(PHY,"Done processing symbol %d : llr_offset %d\n",m,ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->llr_offset[m]); diff --git a/openair1/SIMULATION/NR_PHY/dlsim.c b/openair1/SIMULATION/NR_PHY/dlsim.c index 2e3fcbbf48..7c1285491c 100644 --- a/openair1/SIMULATION/NR_PHY/dlsim.c +++ b/openair1/SIMULATION/NR_PHY/dlsim.c @@ -736,7 +736,7 @@ int main(int argc, char **argv) NR_UE_DLSCH_t *dlsch0 = UE->dlsch[UE->current_thread_id[UE_proc.nr_tti_rx]][0][0]; - int harq_pid = dlsch0->current_harq_pid; + int harq_pid = slot; NR_DL_UE_HARQ_t *UE_harq_process = dlsch0->harq_processes[harq_pid]; NR_gNB_DLSCH_t *gNB_dlsch = gNB->dlsch[0][0]; @@ -752,10 +752,11 @@ int main(int argc, char **argv) memset(RC.nrmac[0]->cce_list[1][1],0,MAX_NUM_CCE*sizeof(int)); clear_nr_nfapi_information(RC.nrmac[0], 0, frame, slot); - UE_list->UE_sched_ctrl[0].harq_processes[0].ndi = !(trial&1); + UE_list->UE_sched_ctrl[0].harq_processes[harq_pid].ndi = !(trial&1); - UE_list->UE_sched_ctrl[0].harq_processes[0].round = round; - gNB->dlsch[0][0]->harq_processes[0]->round = round; + UE_list->UE_sched_ctrl[0].harq_processes[harq_pid].round = round; + UE_list->UE_sched_ctrl[0].current_harq_pid = harq_pid; + gNB->dlsch[0][0]->harq_processes[harq_pid]->round = round; if (css_flag == 0) nr_schedule_uss_dlsch_phytest(0,frame,slot,&pucch_sched,&dlsch_config); else nr_schedule_css_dlsch_phytest(0,frame,slot); diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c index 9447ce856a..5be0f10731 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c @@ -267,10 +267,7 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl rel15->coreset.scrambling_rnti = mac->t_crnti; } else { rel15->coreset.pdcch_dmrs_scrambling_id = *scc->physCellId; - if(mac->ra_state == WAIT_RAR) - rel15->coreset.scrambling_rnti = 0; - else - rel15->coreset.scrambling_rnti = rel15->rnti; + rel15->coreset.scrambling_rnti = 0; } if (add_dci){ From 456e6c9207d7003be1d4d57ca4eddc2c51b63862 Mon Sep 17 00:00:00 2001 From: matzakos Date: Tue, 16 Jun 2020 17:40:03 +0200 Subject: [PATCH 331/553] Change return type of nr_generate_ulsch_pdu() to avoid overflow on the offset variable --- openair2/LAYER2/NR_MAC_UE/mac_proto.h | 2 +- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 7 ++++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_UE/mac_proto.h b/openair2/LAYER2/NR_MAC_UE/mac_proto.h index 2d49cc0d76..38c9244014 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_proto.h @@ -139,7 +139,7 @@ void nr_ue_process_mac_pdu(module_id_t module_idP, NR_UL_TIME_ALIGNMENT_t *ul_time_alignment); -unsigned char nr_generate_ulsch_pdu(uint8_t *sdus_payload, +uint16_t nr_generate_ulsch_pdu(uint8_t *sdus_payload, uint8_t *pdu, uint8_t num_sdus, uint16_t *sdu_lengths, diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 53ef0f62a3..8e4d092591 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -3723,7 +3723,7 @@ void nr_ue_process_mac_pdu(module_id_t module_idP, /////* ULSCH MAC PDU generation (6.1.2 TS 38.321) *///// //////////////////////////////////////////////////////// -unsigned char nr_generate_ulsch_pdu(uint8_t *sdus_payload, +uint16_t nr_generate_ulsch_pdu(uint8_t *sdus_payload, uint8_t *pdu, uint8_t num_sdus, uint16_t *sdu_lengths, @@ -3738,7 +3738,8 @@ unsigned char nr_generate_ulsch_pdu(uint8_t *sdus_payload, NR_MAC_SUBHEADER_FIXED *mac_pdu_ptr = (NR_MAC_SUBHEADER_FIXED *) pdu; unsigned char last_size = 0, i, mac_header_control_elements[16], *ce_ptr, bsr = 0; - int mac_ce_size, offset; + int mac_ce_size; + uint16_t offset = 0; LOG_D(MAC, "[UE] Generating ULSCH PDU : num_sdus %d\n", num_sdus); @@ -3888,7 +3889,7 @@ unsigned char nr_generate_ulsch_pdu(uint8_t *sdus_payload, // compute final offset offset = ((unsigned char *) mac_pdu_ptr - pdu); - //printf("Offset %d \n", ((unsigned char *) mac_pdu_ptr - mac_pdu)); + //printf("Offset %d \n", ((unsigned char *) mac_pdu_ptr - pdu)); return offset; } From 65b5a48ed196b2510c19472b38deb067bfe42d77 Mon Sep 17 00:00:00 2001 From: matzakos Date: Tue, 16 Jun 2020 17:41:34 +0200 Subject: [PATCH 332/553] Minor logs modifications at gNB ulsch scheduler --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c index 88358060e0..0e42d79fdc 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c @@ -209,7 +209,7 @@ void nr_process_mac_pdu( mac_subheader_len = 2; } - LOG_D(MAC, "[UE %d] Frame %d : DLSCH -> DL-DTCH %d (gNB %d, %d bytes)\n", module_idP, frameP, rx_lcid, module_idP, mac_sdu_len); + LOG_D(MAC, "[UE %d] Frame %d : ULSCH -> UL-DTCH %d (gNB %d, %d bytes)\n", module_idP, frameP, rx_lcid, module_idP, mac_sdu_len); #if defined(ENABLE_MAC_PAYLOAD_DEBUG) LOG_T(MAC, "[UE %d] First 32 bytes of DLSCH : \n", module_idP); @@ -249,7 +249,7 @@ void nr_process_mac_pdu( pdu_len -= ( mac_subheader_len + mac_ce_len + mac_sdu_len ); if (pdu_len < 0) { - LOG_E(MAC, "%s() residual mac pdu length < 0!\n", __func__); + LOG_E(MAC, "%s() residual mac pdu length < 0!, pdu_len: %d\n", __func__, pdu_len); return; } } From 3bce9a7b85f6f8dff8ba2f98142451a90fd8f8bd Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Wed, 17 Jun 2020 14:19:40 +0200 Subject: [PATCH 333/553] CI: increase gNB VM RAM size; display memory usage during modems runs Signed-off-by: Raphael Defosseux --- ci-scripts/oai-ci-vm-tool | 2 +- ci-scripts/runTestOnVM.sh | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/ci-scripts/oai-ci-vm-tool b/ci-scripts/oai-ci-vm-tool index 3fa91b862c..9b9fe462f1 100755 --- a/ci-scripts/oai-ci-vm-tool +++ b/ci-scripts/oai-ci-vm-tool @@ -197,7 +197,7 @@ function variant__v4__cppcheck { } function variant__v5__gnb_usrp { - VM_MEMORY=8192 + VM_MEMORY=10240 VM_CPU=8 NB_PATTERN_FILES=9 BUILD_OPTIONS="--gNB -w USRP" diff --git a/ci-scripts/runTestOnVM.sh b/ci-scripts/runTestOnVM.sh index aa3f171770..21689351c8 100755 --- a/ci-scripts/runTestOnVM.sh +++ b/ci-scripts/runTestOnVM.sh @@ -89,6 +89,9 @@ function start_basic_sim_enb { fi done ENB_SYNC=0 + echo "echo \"free -m\"" > $1 + echo "free -m" >> $1 + ssh -T -o StrictHostKeyChecking=no ubuntu@$LOC_VM_IP_ADDR < $1 rm $1 if [ $i -lt 50 ] then @@ -151,6 +154,9 @@ function start_basic_sim_ue { i=$[$i+1] fi done + echo "echo \"free -m\"" > $1 + echo "free -m" >> $1 + ssh -T -o StrictHostKeyChecking=no ubuntu@$2 < $1 rm $1 if [ $i -lt 50 ] then @@ -764,6 +770,9 @@ function start_l2_sim_enb { i=$[$i+1] fi done + echo "echo \"free -m\"" > $1 + echo "free -m" >> $1 + ssh -T -o StrictHostKeyChecking=no ubuntu@$LOC_ENB_VM_IP_ADDR < $1 rm $1 ENB_SYNC=1 if [ $i -lt 50 ] @@ -872,6 +881,9 @@ function start_l2_sim_ue { i=$[$i+1] fi done + echo "echo \"free -m\"" > $1 + echo "free -m" >> $1 + ssh -T -o StrictHostKeyChecking=no ubuntu@$LOC_UE_VM_IP_ADDR < $1 rm $1 UE_SYNC=1 if [ $i -lt 50 ] @@ -985,6 +997,9 @@ function start_rf_sim_enb { i=$[$i+1] fi done + echo "echo \"free -m\"" > $1 + echo "free -m" >> $1 + ssh -T -o StrictHostKeyChecking=no ubuntu@$LOC_ENB_VM_IP_ADDR < $1 rm $1 if [ $i -lt 50 ] then @@ -1114,6 +1129,9 @@ function start_rf_sim_ue { i=$[$i+1] fi done + echo "echo \"free -m\"" > $1 + echo "free -m" >> $1 + ssh -T -o StrictHostKeyChecking=no ubuntu@$LOC_UE_VM_IP_ADDR < $1 rm $1 if [ $i -lt 50 ] then @@ -1236,6 +1254,10 @@ function start_rf_sim_gnb { fi fi sleep 10 + echo "echo \"free -m\"" > $1 + echo "free -m" >> $1 + ssh -T -o StrictHostKeyChecking=no ubuntu@$LOC_GNB_VM_IP_ADDR < $1 + rm $1 # Copy the RAW files from the gNB run for the NR-UE scp -o StrictHostKeyChecking=no ubuntu@$LOC_GNB_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/ran_build/build/rbconfig.raw . scp -o StrictHostKeyChecking=no ubuntu@$LOC_GNB_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/ran_build/build/reconfig.raw . @@ -1310,6 +1332,9 @@ function start_rf_sim_nr_ue { i=$[$i+1] fi done + echo "echo \"free -m\"" > $1 + echo "free -m" >> $1 + ssh -T -o StrictHostKeyChecking=no ubuntu@$LOC_NR_UE_VM_IP_ADDR < $1 rm $1 if [ $i -lt 50 ] then From 795b6e02c4c48980ec4cf7e79e6d31d3252f4e0d Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Thu, 18 Jun 2020 12:29:36 +0200 Subject: [PATCH 334/553] fix for pusch num_dmrs_cdm_grps_no_data --- .../NR_UE_TRANSPORT/nr_transport_proto_ue.h | 6 ++-- openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c | 31 ++++++++++++++----- openair1/SCHED_NR/phy_procedures_nr_gNB.c | 1 + openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 4 +-- openair1/SIMULATION/NR_PHY/ulsim.c | 7 ++--- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 1 + .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 1 + openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c | 2 +- 8 files changed, 35 insertions(+), 18 deletions(-) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h index d84a56eee5..bde9ae03f1 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h @@ -1387,8 +1387,10 @@ void ulsch_modulation(int32_t **txdataF, NR_UE_ULSCH_t *ulsch); - - +uint8_t allowed_ulsch_re_in_dmrs_symbol(uint16_t k, + uint16_t start_sc, + uint8_t numDmrsCdmGrpsNoData, + uint8_t dmrs_type); int generate_ue_dlsch_params_from_dci(int frame, diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c index 1e356976d3..fb39f4c007 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c @@ -114,7 +114,6 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, uint8_t data_existing =0; uint8_t L_ptrs, K_ptrs; // PTRS parameters uint16_t beta_ptrs; // PTRS parameter related to power control - uint8_t no_data_in_dmrs = 1; NR_UE_ULSCH_t *ulsch_ue; NR_UL_UE_HARQ_t *harq_process_ul_ue=NULL; @@ -128,7 +127,6 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, N_PRB_oh = 0; // higher layer (RRC) parameter xOverhead in PUSCH-ServingCellConfig number_dmrs_symbols = 0; - for (cwd_index = 0;cwd_index < num_of_codewords; cwd_index++) { ulsch_ue = UE->ulsch[thread_id][gNB_id][cwd_index]; @@ -149,10 +147,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, rnti = harq_process_ul_ue->pusch_pdu.rnti; ulsch_ue->Nid_cell = Nid_cell; - if(no_data_in_dmrs) - nb_dmrs_re_per_rb = 12; - else - nb_dmrs_re_per_rb = ((dmrs_type == pusch_dmrs_type1) ? 6:4); + nb_dmrs_re_per_rb = ((dmrs_type == pusch_dmrs_type1) ? 6:4)*harq_process_ul_ue->pusch_pdu.num_dmrs_cdm_grps_no_data; N_RE_prime = NR_NB_SC_PER_RB*number_of_symbols - nb_dmrs_re_per_rb*number_dmrs_symbols - N_PRB_oh; @@ -174,7 +169,6 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, 0, harq_process_ul_ue->pusch_pdu.nrOfLayers); - uint8_t access_mode = SCHEDULED_ACCESS; //-----------------------------------------------------// @@ -439,7 +433,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, ptrs_idx++; - } else if (((ul_dmrs_symb_pos >> l) & 0x01) == 0) { + } else if (allowed_ulsch_re_in_dmrs_symbol(k,start_sc,harq_process_ul_ue->pusch_pdu.num_dmrs_cdm_grps_no_data,dmrs_type)) { ((int16_t*)txdataF[ap])[(sample_offsetF)<<1] = ((int16_t *) ulsch_ue->y)[m<<1]; ((int16_t*)txdataF[ap])[((sample_offsetF)<<1) + 1] = ((int16_t *) ulsch_ue->y)[(m<<1) + 1]; @@ -474,6 +468,27 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, } +uint8_t allowed_ulsch_re_in_dmrs_symbol(uint16_t k, + uint16_t start_sc, + uint8_t numDmrsCdmGrpsNoData, + uint8_t dmrs_type) { + uint8_t delta; + for (int i = 0; iulsch_decoding_stats); + if (ret > gNB->ulsch[ULSCH_id][0]->max_ldpc_iterations){ LOG_I(PHY, "ULSCH %d in error\n",ULSCH_id); nr_fill_indication(gNB,frame_rx, slot_rx, ULSCH_id, harq_pid, 1); diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index d7e77c2886..ffb4516ef4 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -2768,9 +2768,9 @@ int nr_ue_pdcch_procedures(uint8_t gNB_id, nr_tti_rx, &dci_ind); -//#ifdef NR_PDCCH_SCHED_DEBUG +#ifdef NR_PDCCH_SCHED_DEBUG LOG_I(PHY,"<-NR_PDCCH_PHY_PROCEDURES_LTE_UE (nr_ue_pdcch_procedures)-> Ending function nr_dci_decoding_procedure() -> dci_cnt=%u\n",dci_cnt); -//#endif +#endif VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DCI_DECODING, VCD_FUNCTION_OUT); //LOG_D(PHY,"[UE %d][PUSCH] Frame %d nr_tti_rx %d PHICH RX\n",ue->Mod_id,frame_rx,nr_tti_rx); diff --git a/openair1/SIMULATION/NR_PHY/ulsim.c b/openair1/SIMULATION/NR_PHY/ulsim.c index ed171ecb2f..098757d9a6 100644 --- a/openair1/SIMULATION/NR_PHY/ulsim.c +++ b/openair1/SIMULATION/NR_PHY/ulsim.c @@ -648,7 +648,7 @@ int main(int argc, char **argv) pusch_pdu->ul_dmrs_scrambling_id = *scc->physCellId; pusch_pdu->scid = 0; pusch_pdu->dmrs_ports = 1; - pusch_pdu->num_dmrs_cdm_grps_no_data = 2; + pusch_pdu->num_dmrs_cdm_grps_no_data = 1; pusch_pdu->resource_alloc = 1; pusch_pdu->rb_start = start_rb; pusch_pdu->rb_size = nb_rb; @@ -703,10 +703,7 @@ int main(int argc, char **argv) //there are plenty of other parameters that we don't seem to be using for now. e.g. ul_config.ul_config_list[0].pusch_config_pdu.absolute_delta_PUSCH = 0; - if(no_data_in_dmrs) - nb_re_dmrs = 12; - else - nb_re_dmrs = ((ul_config.ul_config_list[0].pusch_config_pdu.dmrs_config_type == pusch_dmrs_type1) ? 6 : 4); + nb_re_dmrs = ((ul_config.ul_config_list[0].pusch_config_pdu.dmrs_config_type == pusch_dmrs_type1) ? 6 : 4); available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, number_dmrs_symbols, mod_order, 1); TBS = nr_compute_tbs(mod_order, code_rate, nb_rb, nb_symb_sch, nb_re_dmrs * number_dmrs_symbols, 0, 0, precod_nbr_layers); diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index f29648dd8e..e390dec774 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -818,6 +818,7 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.dmrs_config_type = dmrs_config_type; scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.mcs_index = mcs_index; scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.mcs_table = mcs_table; + scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.num_dmrs_cdm_grps_no_data = 1; scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_data.new_data_indicator = 0; scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_data.rv_index = rv_index; scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.nrOfLayers = nrOfLayers; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index f79dad41fb..406007ef8d 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -872,6 +872,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, 0, pusch_pdu->nrOfLayers)>>3; + pusch_pdu->pusch_data.num_cb = 0; //CBG not supported //pusch_pdu->pusch_data.cb_present_and_position; //pusch_pdu->pusch_uci; diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c index 6773c3ee1c..3e1c8f3d4b 100644 --- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c @@ -283,7 +283,7 @@ int nr_ue_dcireq(nr_dcireq_t *dcireq) { dl_config->slot=UE_mac->dl_config_request.slot; dl_config->number_pdus=0; - printf(" UE_mac->dl_config_request.slot %d VS dcireq->slot %d \n", UE_mac->dl_config_request.slot, dcireq->slot); + //printf(" UE_mac->dl_config_request.slot %d VS dcireq->slot %d \n", UE_mac->dl_config_request.slot, dcireq->slot); LOG_D(PHY, "Entering UE DCI configuration frame %d slot %d \n", dcireq->frame, dcireq->slot); From 8533610e2abb78ee712ceed939c08b5d0b5e835a Mon Sep 17 00:00:00 2001 From: "vr.devendra" Date: Fri, 22 May 2020 20:15:12 +0530 Subject: [PATCH 335/553] GlobalEdge: CSI and TCI related MAC CE intial commit --- cmake_targets/CMakeLists.txt | 1 + openair2/LAYER2/NR_MAC_COMMON/nr_mac.h | 168 ++++--- .../LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c | 385 +++++++++++---- openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 447 ++++++++++++------ 4 files changed, 695 insertions(+), 306 deletions(-) diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index 5ac5053412..15b94a1082 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -249,6 +249,7 @@ add_boolean_option(UE_AUTOTEST_TRACE False "Activate UE autotest specific logs add_boolean_option(UE_DEBUG_TRACE False "Activate UE debug trace") add_boolean_option(UE_TIMING_TRACE False "Activate UE timing trace") add_boolean_option(DEBUG_CONSOLE False "makes debugging easier, disables stdout/stderr buffering") +add_boolean_option(GES_SUPPORT True "To enable the GES Code") set (OCP_ITTI ${OPENAIR_DIR}/common/utils/ocp_itti) add_library(ITTI diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h index 20b4c85dc6..f29a5af042 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h @@ -24,8 +24,8 @@ * \author R. Knopp, K.H. HSU, G. Casati * \date 2019 * \version 0.1 - * \company Eurecom / NTUST / Fraunhofer IIS - * \email: knopp@eurecom.fr, kai-hsiang.hsu@eurecom.fr, guido.casati@iis.fraunhofer.de + * \company Eurecom / NTUST / Fraunhofer IIS + * \email: knopp@eurecom.fr, kai-hsiang.hsu@eurecom.fr, guido.casati@iis.fraunhofer.de * \note * \warning */ @@ -71,72 +71,132 @@ // R: Reserved bit, set to zero. typedef struct { - uint8_t LCID:6; // octet 1 [5:0] - uint8_t F:1; // octet 1 [6] - uint8_t R:1; // octet 1 [7] - uint8_t L:8; // octet 2 [7:0] + uint8_t LCID: 6; // octet 1 [5:0] + uint8_t F: 1; // octet 1 [6] + uint8_t R: 1; // octet 1 [7] + uint8_t L: 8; // octet 2 [7:0] } __attribute__ ((__packed__)) NR_MAC_SUBHEADER_SHORT; typedef struct { - uint8_t LCID:6; // octet 1 [5:0] - uint8_t F:1; // octet 1 [6] - uint8_t R:1; // octet 1 [7] - uint8_t L1:8; // octet 2 [7:0] - uint8_t L2:8; // octet 3 [7:0] + uint8_t LCID: 6; // octet 1 [5:0] + uint8_t F: 1; // octet 1 [6] + uint8_t R: 1; // octet 1 [7] + uint8_t L1: 8; // octet 2 [7:0] + uint8_t L2: 8; // octet 3 [7:0] } __attribute__ ((__packed__)) NR_MAC_SUBHEADER_LONG; typedef struct { - uint8_t LCID:6; // octet 1 [5:0] - uint8_t R:2; // octet 1 [7:6] + uint8_t LCID: 6; // octet 1 [5:0] + uint8_t R: 2; // octet 1 [7:6] } __attribute__ ((__packed__)) NR_MAC_SUBHEADER_FIXED; // BSR MAC CEs // TS 38.321 ch. 6.1.3.1 // Short BSR for a specific logical channel group ID typedef struct { - uint8_t Buffer_size:5; // octet 1 LSB - uint8_t LcgID:3; // octet 1 MSB + uint8_t Buffer_size: 5; // octet 1 LSB + uint8_t LcgID: 3; // octet 1 MSB } __attribute__ ((__packed__)) NR_BSR_SHORT; typedef NR_BSR_SHORT NR_BSR_SHORT_TRUNCATED; // Long BSR for all logical channel group ID typedef struct { - uint8_t Buffer_size7:8; - uint8_t Buffer_size6:8; - uint8_t Buffer_size5:8; - uint8_t Buffer_size4:8; - uint8_t Buffer_size3:8; - uint8_t Buffer_size2:8; - uint8_t Buffer_size1:8; - uint8_t Buffer_size0:8; - uint8_t LcgID0:1; - uint8_t LcgID1:1; - uint8_t LcgID2:1; - uint8_t LcgID3:1; - uint8_t LcgID4:1; - uint8_t LcgID5:1; - uint8_t LcgID6:1; - uint8_t LcgID7:1; + uint8_t Buffer_size7: 8; + uint8_t Buffer_size6: 8; + uint8_t Buffer_size5: 8; + uint8_t Buffer_size4: 8; + uint8_t Buffer_size3: 8; + uint8_t Buffer_size2: 8; + uint8_t Buffer_size1: 8; + uint8_t Buffer_size0: 8; + uint8_t LcgID0: 1; + uint8_t LcgID1: 1; + uint8_t LcgID2: 1; + uint8_t LcgID3: 1; + uint8_t LcgID4: 1; + uint8_t LcgID5: 1; + uint8_t LcgID6: 1; + uint8_t LcgID7: 1; } __attribute__ ((__packed__)) NR_BSR_LONG; typedef NR_BSR_LONG NR_BSR_LONG_TRUNCATED; // 38.321 ch. 6.1.3.4 typedef struct { - uint8_t TA_COMMAND:6; // octet 1 [5:0] - uint8_t TAGID:2; // octet 1 [7:6] + uint8_t TA_COMMAND: 6; // octet 1 [5:0] + uint8_t TAGID: 2; // octet 1 [7:6] } __attribute__ ((__packed__)) NR_MAC_CE_TA; // single Entry PHR MAC CE // TS 38.321 ch. 6.1.3.8 typedef struct { - uint8_t PH:6; - uint8_t R1:2; - uint8_t PCMAX:6; - uint8_t R2:6; + uint8_t PH: 6; + uint8_t R1: 2; + uint8_t PCMAX: 6; + uint8_t R2: 6; } __attribute__ ((__packed__)) NR_SINGLE_ENTRY_PHR_MAC_CE; +#ifdef GES_SUPPORT + +// SP ZP CSI-RS Resource Set Activation/Deactivation MAC CE +// 38.321 ch. 6.1.3.19 +typedef struct { + uint8_t BWPID: 2; // octet 1 [1:0] + uint8_t CELLID: 5; // octet 1 [6:2] + uint8_t A_D: 1; // octet 1 [7] + uint8_t CSIRS_RSC_ID: 4; // octet 2 [3:0] + uint8_t R: 4 // octet 2 [7:4] +} __attribute__ ((__packed__)) NR_MAC_CE_SP_ZP_CSI_RS_RES_SET; + +//TS 38.321 Sec 6.1.3.15, TCI State indicaton for UE-Specific PDCCH MAC CE +typedef struct { + uint8_t CoresetId1: 3; //Octect 1 [2:0] + uint8_t ServingCellId: 5; //Octect 1 [7:3] + uint8_t TciStateId: 7; //Octect 2 [6:0] + uint8_t CoresetId2: 1; //Octect 2 [7] +} __attribute__ ((__packed__)) NR_TCI_PDCCH; + +//TS 38.321 Sec 6.1.3.14, TCI State activation/deactivation for UE Specific PDSCH MAC CE +typedef struct { + uint8_t BWP_Id: 2; //Octect 1 [1:0] + uint8_t ServingCellId: 5; //Octect 1 [6:2] + uint8_t R: 1; //Octect 1 [7] + uint8_t T[]; //Octects 2 to MAX TCI States/8 +} __attribute__ ((__packed__)) NR_TCI_PDSCH_APERIODIC_CSI; + +//TS 6.1.3.16, SP CSI reporting on PUCCH Activation/Deactivation MAC CE +typedef struct { + uint8_t BWP_Id: 2; //Octect 1 [1:0] + uint8_t ServingCellId: 5; //Octect 1 [6:2] + uint8_t R1: 1; //Octect 1 [7] + uint8_t S0: 1; //Octect 2 [0] + uint8_t S1: 1; //Octect 2 [1] + uint8_t S2: 1; //Octect 2 [2] + uint8_t S3: 1; //Octect 2 [3] + uint8_t R2: 4; //Octect 2 [7:4] +} __attribute__ ((__packed__)) NR_PUCCH_CSI_REPORTING; + + +//TS 38.321 sec 6.1.3.12 +//SP CSI-RS / CSI-IM Resource Set Activation/Deactivation MAC CE +typedef struct { + uint8_t BWP_ID: 2; + uint8_t SCID: 5; + uint8_t A_D: 1; + uint8_t SP_CSI_RSID: 6; + uint8_t IM: 1; + uint8_t R1: 1; + uint8_t SP_CSI_IMID: 6; + uint8_t R2: 2; + struct TCI_S { + uint8_t TCI_STATE_ID: 6; + uint8_t R: 2; + } __attribute__ ((__packed__)) TCI_STATE; +} __attribute__ ((__packed__)) CSI_RS_CSI_IM_ACT_DEACT_MAC_CE; + +#endif + //* RAR MAC subheader // TS 38.321 ch. 6.1.5, 6.2.2 *// // - E: The Extension field is a flag indicating if the MAC subPDU including this MAC subheader is the last MAC subPDU or not in the MAC PDU // - T: The Type field is a flag indicating whether the MAC subheader contains a Random Access Preamble ID or a Backoff Indicator (0, BI) (1, RAPID) @@ -146,30 +206,30 @@ typedef struct { /*!\brief RAR MAC subheader with RAPID */ typedef struct { - uint8_t RAPID:6; - uint8_t T:1; - uint8_t E:1; + uint8_t RAPID: 6; + uint8_t T: 1; + uint8_t E: 1; } __attribute__ ((__packed__)) NR_RA_HEADER_RAPID; /*!\brief RAR MAC subheader with Backoff Indicator */ typedef struct { - uint8_t BI:4; - uint8_t R:2; - uint8_t T:1; - uint8_t E:1; + uint8_t BI: 4; + uint8_t R: 2; + uint8_t T: 1; + uint8_t E: 1; } __attribute__ ((__packed__)) NR_RA_HEADER_BI; // TS 38.321 ch. 6.2.3 typedef struct { - uint8_t TA1:7; // octet 1 [6:0] - uint8_t R:1; // octet 1 [7] - uint8_t UL_GRANT_1:3; // octet 2 [2:0] - uint8_t TA2:5; // octet 2 [7:3] - uint8_t UL_GRANT_2:8; // octet 3 [7:0] - uint8_t UL_GRANT_3:8; // octet 4 [7:0] - uint8_t UL_GRANT_4:8; // octet 5 [7:0] - uint8_t TCRNTI_1:8; // octet 6 [7:0] - uint8_t TCRNTI_2:8; // octet 7 [7:0] + uint8_t TA1: 7; // octet 1 [6:0] + uint8_t R: 1; // octet 1 [7] + uint8_t UL_GRANT_1: 3; // octet 2 [2:0] + uint8_t TA2: 5; // octet 2 [7:3] + uint8_t UL_GRANT_2: 8; // octet 3 [7:0] + uint8_t UL_GRANT_3: 8; // octet 4 [7:0] + uint8_t UL_GRANT_4: 8; // octet 5 [7:0] + uint8_t TCRNTI_1: 8; // octet 6 [7:0] + uint8_t TCRNTI_2: 8; // octet 7 [7:0] } __attribute__ ((__packed__)) NR_MAC_RAR; // 38.321 ch6.2.1, 38.331 @@ -185,7 +245,7 @@ typedef struct { #define DL_SCH_LCID_TCI_STATE_IND_UE_SPEC_PDCCH 0x34 #define DL_SCH_LCID_TCI_STATE_ACT_UE_SPEC_PDSCH 0x35 #define DL_SCH_LCID_APERIODIC_CSI_TRI_STATE_SUBSEL 0x36 -#define DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT 0X37 +#define DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT 0X37 #define DL_SCH_LCID_DUPLICATION_ACT 0X38 #define DL_SCH_LCID_SCell_ACT_4_OCT 0X39 #define DL_SCH_LCID_SCell_ACT_1_OCT 0X3A diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c index 7777e307fb..e086210e4f 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c @@ -47,6 +47,12 @@ //////////////////////////////////////////////////////// /////* DLSCH MAC PDU generation (6.1.2 TS 38.321) *///// //////////////////////////////////////////////////////// +#ifdef GES_SUPPORT +#define OCTET 8 +#define HALFWORD 16 +#define WORD 32 +//#define SIZE_OF_POINTER sizeof (void *) +#endif int nr_generate_dlsch_pdu(module_id_t module_idP, unsigned char *sdus_payload, @@ -56,127 +62,302 @@ int nr_generate_dlsch_pdu(module_id_t module_idP, unsigned char *sdu_lcids, unsigned char drx_cmd, unsigned char *ue_cont_res_id, - unsigned short post_padding){ + unsigned short post_padding) { - gNB_MAC_INST *gNB = RC.nrmac[module_idP]; + gNB_MAC_INST *gNB = RC.nrmac[module_idP]; - NR_MAC_SUBHEADER_FIXED *mac_pdu_ptr = (NR_MAC_SUBHEADER_FIXED *) mac_pdu; - unsigned char * dlsch_buffer_ptr = sdus_payload; - uint8_t last_size = 0; - int offset = 0, mac_ce_size, i, timing_advance_cmd, tag_id = 0; - // MAC CEs - uint8_t mac_header_control_elements[16], *ce_ptr; - ce_ptr = &mac_header_control_elements[0]; + NR_MAC_SUBHEADER_FIXED *mac_pdu_ptr = (NR_MAC_SUBHEADER_FIXED *) mac_pdu; + unsigned char * dlsch_buffer_ptr = sdus_payload; + uint8_t last_size = 0; + int offset = 0, mac_ce_size, i, timing_advance_cmd, tag_id = 0; + // MAC CEs + uint8_t mac_header_control_elements[16], *ce_ptr; + ce_ptr = &mac_header_control_elements[0]; +#ifdef GES_SUPPORT + uint16_t UE_id = 0; //TODO need to get as a function parameter or need to invoke api to UE_id using module Id and RNTI + gNB_MAC_INST *gNB_mac = RC.nrmac[module_idP]; + NR_UE_list_t *UE_list = &gNB_mac->UE_list; + NR_UE_sched_ctrl_t *ue_sched_ctl = NULL; + //NR_CellGroupConfig_t *config = UE_list->secondaryCellGroup[UE_id]; + ue_sched_ctl = &(UE_list->UE_sched_ctrl[UE_id]); +#endif - // 1) Compute MAC CE and related subheaders + // 1) Compute MAC CE and related subheaders - // DRX command subheader (MAC CE size 0) - if (drx_cmd != 255) { - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_DRX; - //last_size = 1; - mac_pdu_ptr++; - } - - // Timing Advance subheader - /* This was done only when timing_advance_cmd != 31 - // now TA is always send when ta_timer resets regardless of its value - // this is done to avoid issues with the timeAlignmentTimer which is - // supposed to monitor if the UE received TA or not */ - if (gNB->ta_len){ - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_TA_COMMAND; - //last_size = 1; - mac_pdu_ptr++; - - // TA MAC CE (1 octet) - timing_advance_cmd = gNB->ta_command; - AssertFatal(timing_advance_cmd < 64,"timing_advance_cmd %d > 63\n", timing_advance_cmd); - ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND = timing_advance_cmd; //(timing_advance_cmd+31)&0x3f; - if (gNB->tag->tag_Id != 0){ - tag_id = gNB->tag->tag_Id; - ((NR_MAC_CE_TA *) ce_ptr)->TAGID = tag_id; + // DRX command subheader (MAC CE size 0) + if (drx_cmd != 255) { + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_DRX; + //last_size = 1; + mac_pdu_ptr++; } - LOG_D(MAC, "NR MAC CE timing advance command = %d (%d) TAG ID = %d\n", timing_advance_cmd, ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND, tag_id); + // Timing Advance subheader + /* This was done only when timing_advance_cmd != 31 + // now TA is always send when ta_timer resets regardless of its value + // this is done to avoid issues with the timeAlignmentTimer which is + // supposed to monitor if the UE received TA or not */ + if (gNB->ta_len) { + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_TA_COMMAND; + //last_size = 1; + mac_pdu_ptr++; - mac_ce_size = sizeof(NR_MAC_CE_TA); + // TA MAC CE (1 octet) + timing_advance_cmd = gNB->ta_command; + AssertFatal(timing_advance_cmd < 64, "timing_advance_cmd %d > 63\n", timing_advance_cmd); + ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND = timing_advance_cmd; //(timing_advance_cmd+31)&0x3f; + if (gNB->tag->tag_Id != 0) { + tag_id = gNB->tag->tag_Id; + ((NR_MAC_CE_TA *) ce_ptr)->TAGID = tag_id; + } - // Copying bytes for MAC CEs to the mac pdu pointer - memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); - ce_ptr += mac_ce_size; - mac_pdu_ptr += (unsigned char) mac_ce_size; - } + LOG_D(MAC, "NR MAC CE timing advance command = %d (%d) TAG ID = %d\n", timing_advance_cmd, ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND, tag_id); - // Contention resolution fixed subheader and MAC CE - if (ue_cont_res_id) { - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_CON_RES_ID; - mac_pdu_ptr++; - //last_size = 1; + mac_ce_size = sizeof(NR_MAC_CE_TA); - // contention resolution identity MAC ce has a fixed 48 bit size - // this contains the UL CCCH SDU. If UL CCCH SDU is longer than 48 bits, - // it contains the first 48 bits of the UL CCCH SDU - LOG_T(MAC, "[gNB ][RAPROC] Generate contention resolution msg: %x.%x.%x.%x.%x.%x\n", - ue_cont_res_id[0], ue_cont_res_id[1], ue_cont_res_id[2], - ue_cont_res_id[3], ue_cont_res_id[4], ue_cont_res_id[5]); + // Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); + ce_ptr += mac_ce_size; + mac_pdu_ptr += (unsigned char) mac_ce_size; + } - // Copying bytes (6 octects) to CEs pointer - mac_ce_size = 6; - memcpy(ce_ptr, ue_cont_res_id, mac_ce_size); - - // Copying bytes for MAC CEs to mac pdu pointer - memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); - ce_ptr += mac_ce_size; - mac_pdu_ptr += (unsigned char) mac_ce_size; - } + // Contention resolution fixed subheader and MAC CE + if (ue_cont_res_id) { + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_CON_RES_ID; + mac_pdu_ptr++; + //last_size = 1; - // 2) Generation of DLSCH MAC subPDUs including subheaders and MAC SDUs - for (i = 0; i < num_sdus; i++) { - LOG_D(MAC, "[gNB] Generate DLSCH header num sdu %d len sdu %d\n", num_sdus, sdu_lengths[i]); + // contention resolution identity MAC ce has a fixed 48 bit size + // this contains the UL CCCH SDU. If UL CCCH SDU is longer than 48 bits, + // it contains the first 48 bits of the UL CCCH SDU + LOG_T(MAC, "[gNB ][RAPROC] Generate contention resolution msg: %x.%x.%x.%x.%x.%x\n", + ue_cont_res_id[0], ue_cont_res_id[1], ue_cont_res_id[2], + ue_cont_res_id[3], ue_cont_res_id[4], ue_cont_res_id[5]); + + // Copying bytes (6 octects) to CEs pointer + mac_ce_size = 6; + memcpy(ce_ptr, ue_cont_res_id, mac_ce_size); + + // Copying bytes for MAC CEs to mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); + ce_ptr += mac_ce_size; + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + +#ifdef GES_SUPPORT + + //TS 38.321 Sec 6.1.3.15 TCI State indication for UE Specific PDCCH MAC CE SubPDU generation + if (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.is_scheduled) { + //filling subheader + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_TCI_STATE_IND_UE_SPEC_PDCCH; + mac_pdu_ptr++; + //Creating the instance of CE structure + NR_TCI_PDCCH nr_UESpec_TCI_StateInd_PDCCH; + //filling the CE structre + nr_UESpec_TCI_StateInd_PDCCH.CoresetId1 = ((ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0xF) >> 1; //extracting MSB 3 bits from LS nibble + nr_UESpec_TCI_StateInd_PDCCH.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.servingCellId) & 0x1F; //extracting LSB 5 Bits + nr_UESpec_TCI_StateInd_PDCCH.TciStateId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.tciStateId) & 0x7F; //extracting LSB 7 bits + nr_UESpec_TCI_StateInd_PDCCH.CoresetId2 = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0x1; //extracting LSB 1 bit + LOG_D(MAC, "NR MAC CE TCI state indication for UE Specific PDCCH = %d \n", nr_UESpec_TCI_StateInd_PDCCH.TciStateId); + mac_ce_size = sizeof(NR_TCI_PDCCH); + // Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)&nr_UESpec_TCI_StateInd_PDCCH, mac_ce_size); + //incrementing the PDU pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + + //TS 38.321 Sec 6.1.3.16, SP CSI reporting on PUCCH Activation/Deactivation MAC CE + if (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.is_scheduled) { + //filling the subheader + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_REP_PUCCH_ACT; + mac_pdu_ptr++; + //creating the instance of CE structure + NR_PUCCH_CSI_REPORTING nr_PUCCH_CSI_reportingActDeact; + //filling the CE structure + nr_PUCCH_CSI_reportingActDeact.BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.bwpId) & 0x3; //extracting LSB 2 bibs + nr_PUCCH_CSI_reportingActDeact.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.servingCellId) & 0x1F; //extracting LSB 5 bits + nr_PUCCH_CSI_reportingActDeact.S0 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[0]; + nr_PUCCH_CSI_reportingActDeact.S1 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[1]; + nr_PUCCH_CSI_reportingActDeact.S2 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[2]; + nr_PUCCH_CSI_reportingActDeact.S3 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[3]; + nr_PUCCH_CSI_reportingActDeact.R2 = 0; + mac_ce_size = sizeof(NR_PUCCH_CSI_REPORTING); + // Copying MAC CE data to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)&nr_PUCCH_CSI_reportingActDeact, mac_ce_size); + //incrementing the PDU pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + + //TS 38.321 Sec 6.1.3.14, TCI State activation/deactivation for UE Specific PDSCH MAC CE + if (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.is_scheduled) { + //Computing the number of octects to be allocated for Flexible array member + //of MAC CE structure + uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.highestTciStateActivated) / 8 + 1; //Calculating the number of octects for allocating the memory + + //filling the subheader + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_TCI_STATE_ACT_UE_SPEC_PDSCH; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + last_size = 2; + //Incrementing the PDU pointer + mac_pdu_ptr += last_size; + //allocating memory for CE Structure + NR_TCI_PDSCH_APERIODIC_CSI *nr_UESpec_TCI_StateInd_PDSCH = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //initializing to zero + memset((void *)nr_UESpec_TCI_StateInd_PDSCH, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //filling the CE Structure + nr_UESpec_TCI_StateInd_PDSCH->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.bwpId) & 0x3; //extracting LSB 2 Bits + nr_UESpec_TCI_StateInd_PDSCH->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.servingCellId) & 0x1F; //extracting LSB 5 bits + for(i = 0; i < (num_octects * 8); i++) { + if(ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.tciStateActDeact[i]) + nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] = nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] | (1 << (i % 8)); + } + mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + //Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)nr_UESpec_TCI_StateInd_PDSCH, mac_ce_size); + //incrementing the mac pdu pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + //freeing the allocated memory + free(nr_UESpec_TCI_StateInd_PDSCH); + } + + //TS38.321 Sec 6.1.3.13 Aperiodic CSI Trigger State Subselection MAC CE + if (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.is_scheduled) { + //Computing the number of octects to be allocated for Flexible array member + //of MAC CE structure + uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.highestTriggerStateSelected) / 8 + 1; //Calculating the number of octects for allocating the memory + + //filling the subheader + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_APERIODIC_CSI_TRI_STATE_SUBSEL; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + last_size = 2; + //Incrementing the PDU pointer + mac_pdu_ptr += last_size; + //allocating memory for CE structure + NR_TCI_PDSCH_APERIODIC_CSI *nr_Aperiodic_CSI_Trigger = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //initializing to zero + memset((void *)nr_Aperiodic_CSI_Trigger, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //filling the CE Structure + nr_Aperiodic_CSI_Trigger->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.bwpId) & 0x3; //extracting LSB 2 bits + nr_Aperiodic_CSI_Trigger->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.servingCellId) & 0x1F; //extracting LSB 5 bits + nr_Aperiodic_CSI_Trigger->R = 0; + for(i = 0; i < (num_octects * 8); i++) { + if(ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.triggerStateSelection[i]) + nr_Aperiodic_CSI_Trigger->T[i / 8] = nr_Aperiodic_CSI_Trigger->T[i / 8] | (1 << (i % 8)); + } + mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + // Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)nr_Aperiodic_CSI_Trigger, mac_ce_size); + //incrementing the mac pdu pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + //freeing the allocated memory + free(nr_Aperiodic_CSI_Trigger); + } + + if (ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.is_scheduled) { + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_SP_ZP_CSI_RS_RES_SET_ACT; + mac_pdu_ptr++; + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->A_D = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.act_deact; + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CELLID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id & 0x1F; //5 bits + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->BWPID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid & 0x3; //2 bits + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CSIRS_RSC_ID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id & 0xF; //4 bits + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->R = 0; + LOG_D(MAC, "NR MAC CE of ZP CSIRS Serv cell ID = %d BWPID= %d Rsc set ID = %d\n", ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id, ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid, ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id); + mac_ce_size = sizeof(NR_MAC_CE_SP_ZP_CSI_RS_RES_SET); + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + + if (ue_sched_ctl->UE_mac_ce_ctrl.csi_im.is_scheduled) { + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT; + mac_pdu_ptr++; + CSI_RS_CSI_IM_ACT_DEACT_MAC_CE csi_rs_im_act_deact_ce; + csi_rs_im_act_deact_ce.A_D = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.act_deact; + csi_rs_im_act_deact_ce.SCID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.serv_cellid & 0x3F;//gNB_PHY -> ssb_pdu.ssb_pdu_rel15.PhysCellId; + csi_rs_im_act_deact_ce.BWP_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.bwp_id; + csi_rs_im_act_deact_ce.R1 = 0; + csi_rs_im_act_deact_ce.IM = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.im;// IF set CSI IM Rsc id will presesent else CSI IM RSC ID is abscent + csi_rs_im_act_deact_ce.SP_CSI_RSID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nzp_csi_rsc_id; + + if ( csi_rs_im_act_deact_ce.IM ) { //is_scheduled if IM is 1 else this field will not present + csi_rs_im_act_deact_ce.R2 = 0; + csi_rs_im_act_deact_ce.SP_CSI_IMID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.csi_im_rsc_id; + mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE ); + } else { + mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE ) - 1; + } + + memcpy ((void *) mac_pdu_ptr, (void *) & ( csi_rs_im_act_deact_ce), mac_ce_size); + mac_pdu_ptr += (unsigned char) mac_ce_size; + + if (csi_rs_im_act_deact_ce.A_D ) { //Following IE is_scheduled only if A/D is 1 + mac_ce_size = sizeof ( struct TCI_S); + + for ( i = 0; i < ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nb_tci_resource_set_id; i++) { + csi_rs_im_act_deact_ce.TCI_STATE.R = 0; + csi_rs_im_act_deact_ce.TCI_STATE.TCI_STATE_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.tci_state_id [i] & 0x7F; + memcpy ((void *) mac_pdu_ptr, (void *) & (csi_rs_im_act_deact_ce.TCI_STATE), mac_ce_size); + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + + } + } + +#endif + + // 2) Generation of DLSCH MAC subPDUs including subheaders and MAC SDUs + for (i = 0; i < num_sdus; i++) { + LOG_D(MAC, "[gNB] Generate DLSCH header num sdu %d len sdu %d\n", num_sdus, sdu_lengths[i]); + + if (sdu_lengths[i] < 128) { + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = sdu_lcids[i]; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = (unsigned char) sdu_lengths[i]; + last_size = 2; + } else { + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->F = 1; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->LCID = sdu_lcids[i]; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L1 = ((unsigned short) sdu_lengths[i] >> 8) & 0x7f; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L2 = (unsigned short) sdu_lengths[i] & 0xff; + last_size = 3; + } + + mac_pdu_ptr += last_size; + + // 3) cycle through SDUs, compute each relevant and place dlsch_buffer in + memcpy((void *) mac_pdu_ptr, (void *) dlsch_buffer_ptr, sdu_lengths[i]); + dlsch_buffer_ptr += sdu_lengths[i]; + mac_pdu_ptr += sdu_lengths[i]; + } + + // 4) Compute final offset for padding + if (post_padding > 0) { + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_PADDING; + mac_pdu_ptr++; - if (sdu_lengths[i] < 128) { - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = sdu_lcids[i]; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = (unsigned char) sdu_lengths[i]; - last_size = 2; } else { - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->F = 1; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->LCID = sdu_lcids[i]; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L1 = ((unsigned short) sdu_lengths[i] >> 8) & 0x7f; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L2 = (unsigned short) sdu_lengths[i] & 0xff; - last_size = 3; + // no MAC subPDU with padding } - mac_pdu_ptr += last_size; + // compute final offset + offset = ((unsigned char *) mac_pdu_ptr - mac_pdu); - // 3) cycle through SDUs, compute each relevant and place dlsch_buffer in - memcpy((void *) mac_pdu_ptr, (void *) dlsch_buffer_ptr, sdu_lengths[i]); - dlsch_buffer_ptr+= sdu_lengths[i]; - mac_pdu_ptr += sdu_lengths[i]; - } + //printf("Offset %d \n", ((unsigned char *) mac_pdu_ptr - mac_pdu)); - // 4) Compute final offset for padding - if (post_padding > 0) { - ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_PADDING; - mac_pdu_ptr++; - - } else { - // no MAC subPDU with padding - } - - // compute final offset - offset = ((unsigned char *) mac_pdu_ptr - mac_pdu); - - //printf("Offset %d \n", ((unsigned char *) mac_pdu_ptr - mac_pdu)); - - return offset; + return offset; } /* functionalities of this function have been moved to nr_schedule_uss_dlsch_phytest */ -void nr_schedule_ue_spec(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ +void nr_schedule_ue_spec(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) { } diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index 90d2310f77..eaf7934128 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -76,109 +76,177 @@ #define NR_NB_RA_PROC_MAX 4 typedef enum { - RA_IDLE = 0, - Msg2 = 1, - WAIT_Msg3 = 2, - Msg4 = 3, - WAIT_Msg4_ACK = 4 + RA_IDLE = 0, + Msg2 = 1, + WAIT_Msg3 = 2, + Msg4 = 3, + WAIT_Msg4_ACK = 4 } RA_gNB_state_t; /*! \brief gNB template for the Random access information */ typedef struct { - /// Flag to indicate this process is active - RA_gNB_state_t state; - /// BWP id of RA process - int bwp_id; - /// CORESET0 configured flag - int coreset0_configured; - /// Slot where preamble was received - uint8_t preamble_slot; - /// Subframe where Msg2 is to be sent - uint8_t Msg2_slot; - /// Frame where Msg2 is to be sent - frame_t Msg2_frame; - /// Subframe where Msg3 is to be sent - sub_frame_t Msg3_slot; - /// Frame where Msg3 is to be sent - frame_t Msg3_frame; - /// Msg3 time domain allocation index - uint8_t Msg3_tda_id; - /// Subframe where Msg4 is to be sent - sub_frame_t Msg4_slot; - /// Frame where Msg4 is to be sent - frame_t Msg4_frame; - /// harq_pid used for Msg4 transmission - uint8_t harq_pid; - /// UE RNTI allocated during RAR - rnti_t rnti; - /// RA RNTI allocated from received PRACH - uint16_t RA_rnti; - /// Received preamble_index - uint8_t preamble_index; - /// Received UE Contention Resolution Identifier - uint8_t cont_res_id[6]; - /// Timing offset indicated by PHY - int16_t timing_offset; - /// Timeout for RRC connection - int16_t RRC_timer; - /// Msg3 first RB - uint8_t msg3_first_rb; - /// Msg3 number of RB - uint8_t msg3_nb_rb; - /// Msg3 TPC command - uint8_t msg3_TPC; - /// Msg3 ULdelay command - uint8_t msg3_ULdelay; - /// Msg3 cqireq command - uint8_t msg3_cqireq; - /// Round of Msg3 HARQ - uint8_t msg3_round; - /// Msg3 pusch pdu - nfapi_nr_pusch_pdu_t pusch_pdu; - /// TBS used for Msg4 - int msg4_TBsize; - /// MCS used for Msg4 - int msg4_mcs; - /// RA search space - NR_SearchSpace_t *ra_ss; + /// Flag to indicate this process is active + RA_gNB_state_t state; + /// BWP id of RA process + int bwp_id; + /// CORESET0 configured flag + int coreset0_configured; + /// Slot where preamble was received + uint8_t preamble_slot; + /// Subframe where Msg2 is to be sent + uint8_t Msg2_slot; + /// Frame where Msg2 is to be sent + frame_t Msg2_frame; + /// Subframe where Msg3 is to be sent + sub_frame_t Msg3_slot; + /// Frame where Msg3 is to be sent + frame_t Msg3_frame; + /// Msg3 time domain allocation index + uint8_t Msg3_tda_id; + /// Subframe where Msg4 is to be sent + sub_frame_t Msg4_slot; + /// Frame where Msg4 is to be sent + frame_t Msg4_frame; + /// harq_pid used for Msg4 transmission + uint8_t harq_pid; + /// UE RNTI allocated during RAR + rnti_t rnti; + /// RA RNTI allocated from received PRACH + uint16_t RA_rnti; + /// Received preamble_index + uint8_t preamble_index; + /// Received UE Contention Resolution Identifier + uint8_t cont_res_id[6]; + /// Timing offset indicated by PHY + int16_t timing_offset; + /// Timeout for RRC connection + int16_t RRC_timer; + /// Msg3 first RB + uint8_t msg3_first_rb; + /// Msg3 number of RB + uint8_t msg3_nb_rb; + /// Msg3 TPC command + uint8_t msg3_TPC; + /// Msg3 ULdelay command + uint8_t msg3_ULdelay; + /// Msg3 cqireq command + uint8_t msg3_cqireq; + /// Round of Msg3 HARQ + uint8_t msg3_round; + /// Msg3 pusch pdu + nfapi_nr_pusch_pdu_t pusch_pdu; + /// TBS used for Msg4 + int msg4_TBsize; + /// MCS used for Msg4 + int msg4_mcs; + /// RA search space + NR_SearchSpace_t *ra_ss; } NR_RA_t; /*! \brief gNB common channels */ typedef struct { - int physCellId; - int p_gNB; - int Ncp; - int nr_band; - lte_frame_type_t frame_type; - uint64_t dl_CarrierFreq; - NR_BCCH_BCH_Message_t *mib; - NR_ServingCellConfigCommon_t *ServingCellConfigCommon; - NR_ARFCN_ValueEUTRA_t ul_CarrierFreq; - long ul_Bandwidth; - /// Outgoing MIB PDU for PHY - MIB_PDU MIB_pdu; - /// Outgoing BCCH pdu for PHY - BCCH_PDU BCCH_pdu; - /// Outgoing BCCH DCI allocation - uint32_t BCCH_alloc_pdu; - /// Outgoing CCCH pdu for PHY - CCCH_PDU CCCH_pdu; - /// Outgoing PCCH DCI allocation - uint32_t PCCH_alloc_pdu; - /// Outgoing PCCH pdu for PHY - PCCH_PDU PCCH_pdu; - /// Outgoing RAR pdu for PHY - RAR_PDU RAR_pdu; - /// Template for RA computations - NR_RA_t ra[NR_NB_RA_PROC_MAX]; - /// VRB map for common channels - uint8_t vrb_map[100]; - /// VRB map for common channels and retransmissions by PHICH - uint8_t vrb_map_UL[100]; - /// number of subframe allocation pattern available for MBSFN sync area - uint8_t num_sf_allocation_pattern; + int physCellId; + int p_gNB; + int Ncp; + int nr_band; + lte_frame_type_t frame_type; + uint64_t dl_CarrierFreq; + NR_BCCH_BCH_Message_t *mib; + NR_ServingCellConfigCommon_t *ServingCellConfigCommon; + NR_ARFCN_ValueEUTRA_t ul_CarrierFreq; + long ul_Bandwidth; + /// Outgoing MIB PDU for PHY + MIB_PDU MIB_pdu; + /// Outgoing BCCH pdu for PHY + BCCH_PDU BCCH_pdu; + /// Outgoing BCCH DCI allocation + uint32_t BCCH_alloc_pdu; + /// Outgoing CCCH pdu for PHY + CCCH_PDU CCCH_pdu; + /// Outgoing PCCH DCI allocation + uint32_t PCCH_alloc_pdu; + /// Outgoing PCCH pdu for PHY + PCCH_PDU PCCH_pdu; + /// Outgoing RAR pdu for PHY + RAR_PDU RAR_pdu; + /// Template for RA computations + NR_RA_t ra[NR_NB_RA_PROC_MAX]; + /// VRB map for common channels + uint8_t vrb_map[100]; + /// VRB map for common channels and retransmissions by PHICH + uint8_t vrb_map_UL[100]; + /// number of subframe allocation pattern available for MBSFN sync area + uint8_t num_sf_allocation_pattern; } NR_COMMON_channels_t; +#ifdef GES_SUPPORT + +// SP ZP CSI-RS Resource Set Activation/Deactivation MAC CE +typedef struct sp_zp_csirs { + bool is_scheduled; //ZP CSI-RS ACT/Deact MAC CE is scheduled + bool act_deact; //Activation/Deactivation indication + uint8_t serv_cell_id; //Identity of Serving cell for which MAC CE applies + uint8_t bwpid; //Downlink BWP id + uint8_t rsc_id; //SP ZP CSI-RS resource set +} sp_zp_csirs_t; + +//SP CSI-RS / CSI-IM Resource Set Activation/Deactivation MAC CE +#define MAX_CSI_RESOURCE_SET 64 +typedef struct csi_rs_im { + bool is_scheduled; + bool act_deact; + uint8_t serv_cellid; + uint8_t bwp_id; + bool im; + uint8_t csi_im_rsc_id; + uint8_t nzp_csi_rsc_id; + uint8_t nb_tci_resource_set_id; + uint8_t tci_state_id [ MAX_CSI_RESOURCE_SET ]; +} csi_rs_im_t; + +typedef struct pdcchStateInd { + bool is_scheduled; + uint8_t servingCellId; + uint8_t coresetId; + uint8_t tciStateId; +} pdcchStateInd_t; + +typedef struct SPCSIReportingpucch { + bool is_scheduled; + uint8_t servingCellId; + uint8_t bwpId; + bool s0tos3_actDeact[4]; +} SPCSIReportingpucch_t; + +#define MAX_APERIODIC_TRIGGER_STATES 128 //38.331 +typedef struct aperiodicCSI_triggerStateSelection { + bool is_scheduled; + uint8_t servingCellId; + uint8_t bwpId; + uint8_t highestTriggerStateSelected; + bool triggerStateSelection[MAX_APERIODIC_TRIGGER_STATES]; +} aperiodicCSI_triggerStateSelection_t; + +#define MAX_TCI_STATES 128 //38.331 +typedef struct pdschTciStatesActDeact { + bool is_scheduled; + uint8_t servingCellId; + uint8_t bwpId; + uint8_t highestTciStateActivated; + bool tciStateActDeact[MAX_TCI_STATES]; +} pdschTciStatesActDeact_t; + +typedef struct UE_info { + sp_zp_csirs_t sp_zp_csi_rs; + csi_rs_im_t csi_im; + pdcchStateInd_t pdcch_state_ind; + SPCSIReportingpucch_t SP_CSI_reporting_pucch; + aperiodicCSI_triggerStateSelection_t aperi_CSI_trigger; + pdschTciStatesActDeact_t pdsch_TCI_States_ActDeact; +} NR_UE_mac_ce_ctrl_t; + +#endif + typedef struct NR_sched_pucch { int frame; int ul_slot; @@ -195,10 +263,15 @@ typedef struct { NR_sched_pucch *sched_pucch; uint16_t ta_timer; int16_t ta_update; + int dummy; +#ifdef GES_SUPPORT + NR_UE_mac_ce_ctrl_t UE_mac_ce_ctrl;// MAC CE related information +#endif } NR_UE_sched_ctrl_t; /*! \brief UE list used by gNB to order UEs/CC for scheduling*/ typedef struct { +<<<<<<< 3bce9a7b85f6f8dff8ba2f98142451a90fd8f8bd DLSCH_PDU DLSCH_pdu[4][MAX_MOBILES_PER_GNB]; /// scheduling control info NR_UE_sched_ctrl_t UE_sched_ctrl[MAX_MOBILES_PER_GNB]; @@ -211,75 +284,90 @@ typedef struct { boolean_t active[MAX_MOBILES_PER_GNB]; rnti_t rnti[MAX_MOBILES_PER_GNB]; NR_CellGroupConfig_t *secondaryCellGroup[MAX_MOBILES_PER_GNB]; +======= + DLSCH_PDU DLSCH_pdu[4][MAX_MOBILES_PER_GNB]; + /// scheduling control info + UE_sched_ctrl_t UE_sched_ctrl[MAX_MOBILES_PER_GNB]; + int next[MAX_MOBILES_PER_GNB]; + int head; + int next_ul[MAX_MOBILES_PER_GNB]; + int head_ul; + int avail; + int num_UEs; + boolean_t active[MAX_MOBILES_PER_GNB]; + rnti_t rnti[MAX_MOBILES_PER_GNB]; + NR_CellGroupConfig_t *secondaryCellGroup[MAX_MOBILES_PER_GNB]; +>>>>>>> GlobalEdge: CSI and TCI related MAC CE intial commit } NR_UE_list_t; /*! \brief top level gNB MAC structure */ typedef struct gNB_MAC_INST_s { - /// Ethernet parameters for northbound midhaul interface - eth_params_t eth_params_n; - /// Ethernet parameters for fronthaul interface - eth_params_t eth_params_s; - /// Module - module_id_t Mod_id; - /// frame counter - frame_t frame; - /// slot counter - int slot; - /// timing advance group - NR_TAG_t *tag; - /// Pointer to IF module instance for PHY - NR_IF_Module_t *if_inst; - /// TA command - int ta_command; - /// MAC CE flag indicating TA length - int ta_len; - /// Common cell resources - NR_COMMON_channels_t common_channels[NFAPI_CC_MAX]; - /// current PDU index (BCH,DLSCH) - uint16_t pdu_index[NFAPI_CC_MAX]; + /// Ethernet parameters for northbound midhaul interface + eth_params_t eth_params_n; + /// Ethernet parameters for fronthaul interface + eth_params_t eth_params_s; + /// Module + module_id_t Mod_id; + /// frame counter + frame_t frame; + /// slot counter + int slot; + /// timing advance group + NR_TAG_t *tag; + /// Pointer to IF module instance for PHY + NR_IF_Module_t *if_inst; + /// TA command + int ta_command; + /// MAC CE flag indicating TA length + int ta_len; + /// Common cell resources + NR_COMMON_channels_t common_channels[NFAPI_CC_MAX]; + /// current PDU index (BCH,DLSCH) + uint16_t pdu_index[NFAPI_CC_MAX]; - /// NFAPI Config Request Structure - nfapi_nr_config_request_scf_t config[NFAPI_CC_MAX]; - /// NFAPI DL Config Request Structure - nfapi_nr_dl_tti_request_t DL_req[NFAPI_CC_MAX]; - /// NFAPI UL TTI Request Structure (this is from the new SCF specs) - nfapi_nr_ul_tti_request_t UL_tti_req[NFAPI_CC_MAX]; - /// NFAPI HI/DCI0 Config Request Structure - nfapi_nr_ul_dci_request_t UL_dci_req[NFAPI_CC_MAX]; - /// NFAPI DL PDU structure - nfapi_nr_tx_data_request_t TX_req[NFAPI_CC_MAX]; + /// NFAPI Config Request Structure + nfapi_nr_config_request_scf_t config[NFAPI_CC_MAX]; + /// NFAPI DL Config Request Structure + nfapi_nr_dl_tti_request_t DL_req[NFAPI_CC_MAX]; + /// NFAPI UL TTI Request Structure (this is from the new SCF specs) + nfapi_nr_ul_tti_request_t UL_tti_req[NFAPI_CC_MAX]; + /// NFAPI HI/DCI0 Config Request Structure + nfapi_nr_ul_dci_request_t UL_dci_req[NFAPI_CC_MAX]; + /// NFAPI DL PDU structure + nfapi_nr_tx_data_request_t TX_req[NFAPI_CC_MAX]; - NR_UE_list_t UE_list; + NR_UE_list_t UE_list; - /// UL handle - uint32_t ul_handle; + /// UL handle + uint32_t ul_handle; // MAC function execution peformance profiler - /// processing time of eNB scheduler - time_stats_t eNB_scheduler; - /// processing time of eNB scheduler for SI - time_stats_t schedule_si; - /// processing time of eNB scheduler for Random access - time_stats_t schedule_ra; - /// processing time of eNB ULSCH scheduler - time_stats_t schedule_ulsch; - /// processing time of eNB DCI generation - time_stats_t fill_DLSCH_dci; - /// processing time of eNB MAC preprocessor - time_stats_t schedule_dlsch_preprocessor; - /// processing time of eNB DLSCH scheduler - time_stats_t schedule_dlsch; // include rlc_data_req + MAC header + preprocessor - /// processing time of eNB MCH scheduler - time_stats_t schedule_mch; - /// processing time of eNB ULSCH reception - time_stats_t rx_ulsch_sdu; // include rlc_data_ind - /// processing time of eNB PCH scheduler - time_stats_t schedule_pch; - /// CCE lists - int cce_list[MAX_NUM_BWP][MAX_NUM_CORESET][MAX_NUM_CCE]; + /// processing time of eNB scheduler + time_stats_t eNB_scheduler; + /// processing time of eNB scheduler for SI + time_stats_t schedule_si; + /// processing time of eNB scheduler for Random access + time_stats_t schedule_ra; + /// processing time of eNB ULSCH scheduler + time_stats_t schedule_ulsch; + /// processing time of eNB DCI generation + time_stats_t fill_DLSCH_dci; + /// processing time of eNB MAC preprocessor + time_stats_t schedule_dlsch_preprocessor; + /// processing time of eNB DLSCH scheduler + time_stats_t schedule_dlsch; // include rlc_data_req + MAC header + preprocessor + /// processing time of eNB MCH scheduler + time_stats_t schedule_mch; + /// processing time of eNB ULSCH reception + time_stats_t rx_ulsch_sdu; // include rlc_data_ind + /// processing time of eNB PCH scheduler + time_stats_t schedule_pch; + /// CCE lists + int cce_list[MAX_NUM_BWP][MAX_NUM_CORESET][MAX_NUM_CCE]; } gNB_MAC_INST; typedef struct { +<<<<<<< 3bce9a7b85f6f8dff8ba2f98142451a90fd8f8bd uint8_t format_indicator; //1 bit uint16_t frequency_domain_assignment; //up to 16 bits uint8_t time_domain_assignment; // 4 bits @@ -336,6 +424,65 @@ typedef struct { uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits uint16_t padding; +======= + + uint8_t format_indicator; //1 bit + uint16_t frequency_domain_assignment; //up to 16 bits + uint8_t time_domain_assignment; // 4 bits + uint8_t frequency_hopping_flag; //1 bit + + uint8_t ra_preamble_index; //6 bits + uint8_t ss_pbch_index; //6 bits + uint8_t prach_mask_index; //4 bits + + uint8_t vrb_to_prb_mapping; //0 or 1 bit + uint8_t mcs; //5 bits + uint8_t ndi; //1 bit + uint8_t rv; //2 bits + uint8_t harq_pid; //4 bits + uint8_t dai; //0, 2 or 4 bits + uint8_t dai1; //1 or 2 bits + uint8_t dai2; //0 or 2 bits + uint8_t tpc; //2 bits + uint8_t pucch_resource_indicator; //3 bits + uint8_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits + + uint8_t short_messages_indicator; //2 bits + uint8_t short_messages; //8 bits + uint8_t tb_scaling; //2 bits + + uint8_t carrier_indicator; //0 or 3 bits + uint8_t bwp_indicator; //0, 1 or 2 bits + uint8_t prb_bundling_size_indicator; //0 or 1 bits + uint8_t rate_matching_indicator; //0, 1 or 2 bits + uint8_t zp_csi_rs_trigger; //0, 1 or 2 bits + uint8_t transmission_configuration_indication; //0 or 3 bits + uint8_t srs_request; //2 bits + uint8_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits + uint8_t cbgfi; //CBG Flushing Out Information: 0 or 1 bit + uint8_t dmrs_sequence_initialization; //0 or 1 bit + + uint8_t srs_resource_indicator; + uint8_t precoding_information; + uint8_t csi_request; + uint8_t ptrs_dmrs_association; + uint8_t beta_offset_indicator; //0 or 2 bits + + uint8_t slot_format_indicator_count; + uint8_t *slot_format_indicators; + + uint8_t pre_emption_indication_count; + uint16_t *pre_emption_indications; //14 bit + + uint8_t block_number_count; + uint8_t *block_numbers; + + uint8_t ul_sul_indicator; //0 or 1 bit + uint8_t antenna_ports; + + uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits + uint16_t padding; +>>>>>>> GlobalEdge: CSI and TCI related MAC CE intial commit } dci_pdu_rel15_t; From e08878ed1c52f41a513310f540cd7e5b0567125b Mon Sep 17 00:00:00 2001 From: Rangaswami Date: Thu, 4 Jun 2020 11:04:43 +0530 Subject: [PATCH 336/553] Corrected indentation and removed GES macro --- cmake_targets/CMakeLists.txt | 1 - openair2/LAYER2/NR_MAC_COMMON/nr_mac.h | 176 +++--- .../LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c | 525 +++++++++--------- openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 462 +++++++-------- 4 files changed, 534 insertions(+), 630 deletions(-) diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index 15b94a1082..5ac5053412 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -249,7 +249,6 @@ add_boolean_option(UE_AUTOTEST_TRACE False "Activate UE autotest specific logs add_boolean_option(UE_DEBUG_TRACE False "Activate UE debug trace") add_boolean_option(UE_TIMING_TRACE False "Activate UE timing trace") add_boolean_option(DEBUG_CONSOLE False "makes debugging easier, disables stdout/stderr buffering") -add_boolean_option(GES_SUPPORT True "To enable the GES Code") set (OCP_ITTI ${OPENAIR_DIR}/common/utils/ocp_itti) add_library(ITTI diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h index f29a5af042..d133b679f1 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h @@ -71,131 +71,129 @@ // R: Reserved bit, set to zero. typedef struct { - uint8_t LCID: 6; // octet 1 [5:0] - uint8_t F: 1; // octet 1 [6] - uint8_t R: 1; // octet 1 [7] - uint8_t L: 8; // octet 2 [7:0] + uint8_t LCID: 6; // octet 1 [5:0] + uint8_t F: 1; // octet 1 [6] + uint8_t R: 1; // octet 1 [7] + uint8_t L: 8; // octet 2 [7:0] } __attribute__ ((__packed__)) NR_MAC_SUBHEADER_SHORT; typedef struct { - uint8_t LCID: 6; // octet 1 [5:0] - uint8_t F: 1; // octet 1 [6] - uint8_t R: 1; // octet 1 [7] - uint8_t L1: 8; // octet 2 [7:0] - uint8_t L2: 8; // octet 3 [7:0] + uint8_t LCID: 6; // octet 1 [5:0] + uint8_t F: 1; // octet 1 [6] + uint8_t R: 1; // octet 1 [7] + uint8_t L1: 8; // octet 2 [7:0] + uint8_t L2: 8; // octet 3 [7:0] } __attribute__ ((__packed__)) NR_MAC_SUBHEADER_LONG; typedef struct { - uint8_t LCID: 6; // octet 1 [5:0] - uint8_t R: 2; // octet 1 [7:6] + uint8_t LCID: 6; // octet 1 [5:0] + uint8_t R: 2; // octet 1 [7:6] } __attribute__ ((__packed__)) NR_MAC_SUBHEADER_FIXED; // BSR MAC CEs // TS 38.321 ch. 6.1.3.1 // Short BSR for a specific logical channel group ID typedef struct { - uint8_t Buffer_size: 5; // octet 1 LSB - uint8_t LcgID: 3; // octet 1 MSB + uint8_t Buffer_size: 5; // octet 1 LSB + uint8_t LcgID: 3; // octet 1 MSB } __attribute__ ((__packed__)) NR_BSR_SHORT; typedef NR_BSR_SHORT NR_BSR_SHORT_TRUNCATED; // Long BSR for all logical channel group ID typedef struct { - uint8_t Buffer_size7: 8; - uint8_t Buffer_size6: 8; - uint8_t Buffer_size5: 8; - uint8_t Buffer_size4: 8; - uint8_t Buffer_size3: 8; - uint8_t Buffer_size2: 8; - uint8_t Buffer_size1: 8; - uint8_t Buffer_size0: 8; - uint8_t LcgID0: 1; - uint8_t LcgID1: 1; - uint8_t LcgID2: 1; - uint8_t LcgID3: 1; - uint8_t LcgID4: 1; - uint8_t LcgID5: 1; - uint8_t LcgID6: 1; - uint8_t LcgID7: 1; + uint8_t Buffer_size7: 8; + uint8_t Buffer_size6: 8; + uint8_t Buffer_size5: 8; + uint8_t Buffer_size4: 8; + uint8_t Buffer_size3: 8; + uint8_t Buffer_size2: 8; + uint8_t Buffer_size1: 8; + uint8_t Buffer_size0: 8; + uint8_t LcgID0: 1; + uint8_t LcgID1: 1; + uint8_t LcgID2: 1; + uint8_t LcgID3: 1; + uint8_t LcgID4: 1; + uint8_t LcgID5: 1; + uint8_t LcgID6: 1; + uint8_t LcgID7: 1; } __attribute__ ((__packed__)) NR_BSR_LONG; typedef NR_BSR_LONG NR_BSR_LONG_TRUNCATED; // 38.321 ch. 6.1.3.4 typedef struct { - uint8_t TA_COMMAND: 6; // octet 1 [5:0] - uint8_t TAGID: 2; // octet 1 [7:6] + uint8_t TA_COMMAND: 6; // octet 1 [5:0] + uint8_t TAGID: 2; // octet 1 [7:6] } __attribute__ ((__packed__)) NR_MAC_CE_TA; // single Entry PHR MAC CE // TS 38.321 ch. 6.1.3.8 typedef struct { - uint8_t PH: 6; - uint8_t R1: 2; - uint8_t PCMAX: 6; - uint8_t R2: 6; + uint8_t PH: 6; + uint8_t R1: 2; + uint8_t PCMAX: 6; + uint8_t R2: 6; } __attribute__ ((__packed__)) NR_SINGLE_ENTRY_PHR_MAC_CE; -#ifdef GES_SUPPORT // SP ZP CSI-RS Resource Set Activation/Deactivation MAC CE // 38.321 ch. 6.1.3.19 typedef struct { - uint8_t BWPID: 2; // octet 1 [1:0] - uint8_t CELLID: 5; // octet 1 [6:2] - uint8_t A_D: 1; // octet 1 [7] - uint8_t CSIRS_RSC_ID: 4; // octet 2 [3:0] - uint8_t R: 4 // octet 2 [7:4] + uint8_t BWPID: 2; // octet 1 [1:0] + uint8_t CELLID: 5; // octet 1 [6:2] + uint8_t A_D: 1; // octet 1 [7] + uint8_t CSIRS_RSC_ID: 4; // octet 2 [3:0] + uint8_t R: 4; // octet 2 [7:4] } __attribute__ ((__packed__)) NR_MAC_CE_SP_ZP_CSI_RS_RES_SET; //TS 38.321 Sec 6.1.3.15, TCI State indicaton for UE-Specific PDCCH MAC CE typedef struct { - uint8_t CoresetId1: 3; //Octect 1 [2:0] - uint8_t ServingCellId: 5; //Octect 1 [7:3] - uint8_t TciStateId: 7; //Octect 2 [6:0] - uint8_t CoresetId2: 1; //Octect 2 [7] + uint8_t CoresetId1: 3; //Octect 1 [2:0] + uint8_t ServingCellId: 5; //Octect 1 [7:3] + uint8_t TciStateId: 7; //Octect 2 [6:0] + uint8_t CoresetId2: 1; //Octect 2 [7] } __attribute__ ((__packed__)) NR_TCI_PDCCH; //TS 38.321 Sec 6.1.3.14, TCI State activation/deactivation for UE Specific PDSCH MAC CE typedef struct { - uint8_t BWP_Id: 2; //Octect 1 [1:0] - uint8_t ServingCellId: 5; //Octect 1 [6:2] - uint8_t R: 1; //Octect 1 [7] - uint8_t T[]; //Octects 2 to MAX TCI States/8 + uint8_t BWP_Id: 2; //Octect 1 [1:0] + uint8_t ServingCellId: 5; //Octect 1 [6:2] + uint8_t R: 1; //Octect 1 [7] + uint8_t T[]; //Octects 2 to MAX TCI States/8 } __attribute__ ((__packed__)) NR_TCI_PDSCH_APERIODIC_CSI; //TS 6.1.3.16, SP CSI reporting on PUCCH Activation/Deactivation MAC CE typedef struct { - uint8_t BWP_Id: 2; //Octect 1 [1:0] - uint8_t ServingCellId: 5; //Octect 1 [6:2] - uint8_t R1: 1; //Octect 1 [7] - uint8_t S0: 1; //Octect 2 [0] - uint8_t S1: 1; //Octect 2 [1] - uint8_t S2: 1; //Octect 2 [2] - uint8_t S3: 1; //Octect 2 [3] - uint8_t R2: 4; //Octect 2 [7:4] + uint8_t BWP_Id: 2; //Octect 1 [1:0] + uint8_t ServingCellId: 5; //Octect 1 [6:2] + uint8_t R1: 1; //Octect 1 [7] + uint8_t S0: 1; //Octect 2 [0] + uint8_t S1: 1; //Octect 2 [1] + uint8_t S2: 1; //Octect 2 [2] + uint8_t S3: 1; //Octect 2 [3] + uint8_t R2: 4; //Octect 2 [7:4] } __attribute__ ((__packed__)) NR_PUCCH_CSI_REPORTING; //TS 38.321 sec 6.1.3.12 //SP CSI-RS / CSI-IM Resource Set Activation/Deactivation MAC CE typedef struct { - uint8_t BWP_ID: 2; - uint8_t SCID: 5; - uint8_t A_D: 1; - uint8_t SP_CSI_RSID: 6; - uint8_t IM: 1; - uint8_t R1: 1; - uint8_t SP_CSI_IMID: 6; - uint8_t R2: 2; - struct TCI_S { - uint8_t TCI_STATE_ID: 6; - uint8_t R: 2; - } __attribute__ ((__packed__)) TCI_STATE; + uint8_t BWP_ID: 2; + uint8_t SCID: 5; + uint8_t A_D: 1; + uint8_t SP_CSI_RSID: 6; + uint8_t IM: 1; + uint8_t R1: 1; + uint8_t SP_CSI_IMID: 6; + uint8_t R2: 2; + struct TCI_S { + uint8_t TCI_STATE_ID: 6; + uint8_t R: 2; + } __attribute__ ((__packed__)) TCI_STATE; } __attribute__ ((__packed__)) CSI_RS_CSI_IM_ACT_DEACT_MAC_CE; -#endif //* RAR MAC subheader // TS 38.321 ch. 6.1.5, 6.2.2 *// // - E: The Extension field is a flag indicating if the MAC subPDU including this MAC subheader is the last MAC subPDU or not in the MAC PDU @@ -206,30 +204,30 @@ typedef struct { /*!\brief RAR MAC subheader with RAPID */ typedef struct { - uint8_t RAPID: 6; - uint8_t T: 1; - uint8_t E: 1; + uint8_t RAPID: 6; + uint8_t T: 1; + uint8_t E: 1; } __attribute__ ((__packed__)) NR_RA_HEADER_RAPID; /*!\brief RAR MAC subheader with Backoff Indicator */ typedef struct { - uint8_t BI: 4; - uint8_t R: 2; - uint8_t T: 1; - uint8_t E: 1; + uint8_t BI: 4; + uint8_t R: 2; + uint8_t T: 1; + uint8_t E: 1; } __attribute__ ((__packed__)) NR_RA_HEADER_BI; // TS 38.321 ch. 6.2.3 typedef struct { - uint8_t TA1: 7; // octet 1 [6:0] - uint8_t R: 1; // octet 1 [7] - uint8_t UL_GRANT_1: 3; // octet 2 [2:0] - uint8_t TA2: 5; // octet 2 [7:3] - uint8_t UL_GRANT_2: 8; // octet 3 [7:0] - uint8_t UL_GRANT_3: 8; // octet 4 [7:0] - uint8_t UL_GRANT_4: 8; // octet 5 [7:0] - uint8_t TCRNTI_1: 8; // octet 6 [7:0] - uint8_t TCRNTI_2: 8; // octet 7 [7:0] + uint8_t TA1: 7; // octet 1 [6:0] + uint8_t R: 1; // octet 1 [7] + uint8_t UL_GRANT_1: 3; // octet 2 [2:0] + uint8_t TA2: 5; // octet 2 [7:3] + uint8_t UL_GRANT_2: 8; // octet 3 [7:0] + uint8_t UL_GRANT_3: 8; // octet 4 [7:0] + uint8_t UL_GRANT_4: 8; // octet 5 [7:0] + uint8_t TCRNTI_1: 8; // octet 6 [7:0] + uint8_t TCRNTI_2: 8; // octet 7 [7:0] } __attribute__ ((__packed__)) NR_MAC_RAR; // 38.321 ch6.2.1, 38.331 @@ -273,9 +271,9 @@ typedef struct { #define UL_SCH_LCID_L_BSR 0x3E #define UL_SCH_LCID_PADDING 0x3F -#define NR_MAX_NUM_LCID 32 -#define NR_MAX_NUM_LCGID 8 -#define MAX_RLC_SDU_SUBHEADER_SIZE 3 +#define NR_MAX_NUM_LCID 32 +#define NR_MAX_NUM_LCGID 8 +#define MAX_RLC_SDU_SUBHEADER_SIZE 3 #endif /*__LAYER2_MAC_H__ */ diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c index e086210e4f..cf2323f571 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c @@ -47,12 +47,10 @@ //////////////////////////////////////////////////////// /////* DLSCH MAC PDU generation (6.1.2 TS 38.321) *///// //////////////////////////////////////////////////////// -#ifdef GES_SUPPORT #define OCTET 8 #define HALFWORD 16 #define WORD 32 //#define SIZE_OF_POINTER sizeof (void *) -#endif int nr_generate_dlsch_pdu(module_id_t module_idP, unsigned char *sdus_payload, @@ -63,299 +61,284 @@ int nr_generate_dlsch_pdu(module_id_t module_idP, unsigned char drx_cmd, unsigned char *ue_cont_res_id, unsigned short post_padding) { + gNB_MAC_INST *gNB = RC.nrmac[module_idP]; + NR_MAC_SUBHEADER_FIXED *mac_pdu_ptr = (NR_MAC_SUBHEADER_FIXED *) mac_pdu; + unsigned char *dlsch_buffer_ptr = sdus_payload; + uint8_t last_size = 0; + int offset = 0, mac_ce_size, i, timing_advance_cmd, tag_id = 0; + // MAC CEs + uint8_t mac_header_control_elements[16], *ce_ptr; + ce_ptr = &mac_header_control_elements[0]; + uint16_t UE_id = 0; //TODO need to get as a function parameter or need to invoke api to UE_id using module Id and RNTI + gNB_MAC_INST *gNB_mac = RC.nrmac[module_idP]; + NR_UE_list_t *UE_list = &gNB_mac->UE_list; + NR_UE_sched_ctrl_t *ue_sched_ctl = NULL; + //NR_CellGroupConfig_t *config = UE_list->secondaryCellGroup[UE_id]; + ue_sched_ctl = &(UE_list->UE_sched_ctrl[UE_id]); - gNB_MAC_INST *gNB = RC.nrmac[module_idP]; + // 1) Compute MAC CE and related subheaders - NR_MAC_SUBHEADER_FIXED *mac_pdu_ptr = (NR_MAC_SUBHEADER_FIXED *) mac_pdu; - unsigned char * dlsch_buffer_ptr = sdus_payload; - uint8_t last_size = 0; - int offset = 0, mac_ce_size, i, timing_advance_cmd, tag_id = 0; - // MAC CEs - uint8_t mac_header_control_elements[16], *ce_ptr; - ce_ptr = &mac_header_control_elements[0]; -#ifdef GES_SUPPORT - uint16_t UE_id = 0; //TODO need to get as a function parameter or need to invoke api to UE_id using module Id and RNTI - gNB_MAC_INST *gNB_mac = RC.nrmac[module_idP]; - NR_UE_list_t *UE_list = &gNB_mac->UE_list; - NR_UE_sched_ctrl_t *ue_sched_ctl = NULL; - //NR_CellGroupConfig_t *config = UE_list->secondaryCellGroup[UE_id]; - ue_sched_ctl = &(UE_list->UE_sched_ctrl[UE_id]); -#endif + // DRX command subheader (MAC CE size 0) + if (drx_cmd != 255) { + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_DRX; + //last_size = 1; + mac_pdu_ptr++; + } - // 1) Compute MAC CE and related subheaders + // Timing Advance subheader + /* This was done only when timing_advance_cmd != 31 + // now TA is always send when ta_timer resets regardless of its value + // this is done to avoid issues with the timeAlignmentTimer which is + // supposed to monitor if the UE received TA or not */ + if (gNB->ta_len) { + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_TA_COMMAND; + //last_size = 1; + mac_pdu_ptr++; + // TA MAC CE (1 octet) + timing_advance_cmd = gNB->ta_command; + AssertFatal(timing_advance_cmd < 64, "timing_advance_cmd %d > 63\n", timing_advance_cmd); + ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND = timing_advance_cmd; //(timing_advance_cmd+31)&0x3f; - // DRX command subheader (MAC CE size 0) - if (drx_cmd != 255) { - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_DRX; - //last_size = 1; - mac_pdu_ptr++; + if (gNB->tag->tag_Id != 0) { + tag_id = gNB->tag->tag_Id; + ((NR_MAC_CE_TA *) ce_ptr)->TAGID = tag_id; } - // Timing Advance subheader - /* This was done only when timing_advance_cmd != 31 - // now TA is always send when ta_timer resets regardless of its value - // this is done to avoid issues with the timeAlignmentTimer which is - // supposed to monitor if the UE received TA or not */ - if (gNB->ta_len) { - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_TA_COMMAND; - //last_size = 1; - mac_pdu_ptr++; + LOG_D(MAC, "NR MAC CE timing advance command = %d (%d) TAG ID = %d\n", timing_advance_cmd, ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND, tag_id); + mac_ce_size = sizeof(NR_MAC_CE_TA); + // Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); + ce_ptr += mac_ce_size; + mac_pdu_ptr += (unsigned char) mac_ce_size; + } - // TA MAC CE (1 octet) - timing_advance_cmd = gNB->ta_command; - AssertFatal(timing_advance_cmd < 64, "timing_advance_cmd %d > 63\n", timing_advance_cmd); - ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND = timing_advance_cmd; //(timing_advance_cmd+31)&0x3f; - if (gNB->tag->tag_Id != 0) { - tag_id = gNB->tag->tag_Id; - ((NR_MAC_CE_TA *) ce_ptr)->TAGID = tag_id; - } + // Contention resolution fixed subheader and MAC CE + if (ue_cont_res_id) { + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_CON_RES_ID; + mac_pdu_ptr++; + //last_size = 1; + // contention resolution identity MAC ce has a fixed 48 bit size + // this contains the UL CCCH SDU. If UL CCCH SDU is longer than 48 bits, + // it contains the first 48 bits of the UL CCCH SDU + LOG_T(MAC, "[gNB ][RAPROC] Generate contention resolution msg: %x.%x.%x.%x.%x.%x\n", + ue_cont_res_id[0], ue_cont_res_id[1], ue_cont_res_id[2], + ue_cont_res_id[3], ue_cont_res_id[4], ue_cont_res_id[5]); + // Copying bytes (6 octects) to CEs pointer + mac_ce_size = 6; + memcpy(ce_ptr, ue_cont_res_id, mac_ce_size); + // Copying bytes for MAC CEs to mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); + ce_ptr += mac_ce_size; + mac_pdu_ptr += (unsigned char) mac_ce_size; + } - LOG_D(MAC, "NR MAC CE timing advance command = %d (%d) TAG ID = %d\n", timing_advance_cmd, ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND, tag_id); + //TS 38.321 Sec 6.1.3.15 TCI State indication for UE Specific PDCCH MAC CE SubPDU generation + if (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.is_scheduled) { + //filling subheader + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_TCI_STATE_IND_UE_SPEC_PDCCH; + mac_pdu_ptr++; + //Creating the instance of CE structure + NR_TCI_PDCCH nr_UESpec_TCI_StateInd_PDCCH; + //filling the CE structre + nr_UESpec_TCI_StateInd_PDCCH.CoresetId1 = ((ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0xF) >> 1; //extracting MSB 3 bits from LS nibble + nr_UESpec_TCI_StateInd_PDCCH.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.servingCellId) & 0x1F; //extracting LSB 5 Bits + nr_UESpec_TCI_StateInd_PDCCH.TciStateId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.tciStateId) & 0x7F; //extracting LSB 7 bits + nr_UESpec_TCI_StateInd_PDCCH.CoresetId2 = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0x1; //extracting LSB 1 bit + LOG_D(MAC, "NR MAC CE TCI state indication for UE Specific PDCCH = %d \n", nr_UESpec_TCI_StateInd_PDCCH.TciStateId); + mac_ce_size = sizeof(NR_TCI_PDCCH); + // Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)&nr_UESpec_TCI_StateInd_PDCCH, mac_ce_size); + //incrementing the PDU pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + } - mac_ce_size = sizeof(NR_MAC_CE_TA); + //TS 38.321 Sec 6.1.3.16, SP CSI reporting on PUCCH Activation/Deactivation MAC CE + if (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.is_scheduled) { + //filling the subheader + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_REP_PUCCH_ACT; + mac_pdu_ptr++; + //creating the instance of CE structure + NR_PUCCH_CSI_REPORTING nr_PUCCH_CSI_reportingActDeact; + //filling the CE structure + nr_PUCCH_CSI_reportingActDeact.BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.bwpId) & 0x3; //extracting LSB 2 bibs + nr_PUCCH_CSI_reportingActDeact.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.servingCellId) & 0x1F; //extracting LSB 5 bits + nr_PUCCH_CSI_reportingActDeact.S0 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[0]; + nr_PUCCH_CSI_reportingActDeact.S1 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[1]; + nr_PUCCH_CSI_reportingActDeact.S2 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[2]; + nr_PUCCH_CSI_reportingActDeact.S3 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[3]; + nr_PUCCH_CSI_reportingActDeact.R2 = 0; + mac_ce_size = sizeof(NR_PUCCH_CSI_REPORTING); + // Copying MAC CE data to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)&nr_PUCCH_CSI_reportingActDeact, mac_ce_size); + //incrementing the PDU pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + } - // Copying bytes for MAC CEs to the mac pdu pointer - memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); - ce_ptr += mac_ce_size; - mac_pdu_ptr += (unsigned char) mac_ce_size; + //TS 38.321 Sec 6.1.3.14, TCI State activation/deactivation for UE Specific PDSCH MAC CE + if (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.is_scheduled) { + //Computing the number of octects to be allocated for Flexible array member + //of MAC CE structure + uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.highestTciStateActivated) / 8 + 1; //Calculating the number of octects for allocating the memory + //filling the subheader + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_TCI_STATE_ACT_UE_SPEC_PDSCH; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + last_size = 2; + //Incrementing the PDU pointer + mac_pdu_ptr += last_size; + //allocating memory for CE Structure + NR_TCI_PDSCH_APERIODIC_CSI *nr_UESpec_TCI_StateInd_PDSCH = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //initializing to zero + memset((void *)nr_UESpec_TCI_StateInd_PDSCH, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //filling the CE Structure + nr_UESpec_TCI_StateInd_PDSCH->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.bwpId) & 0x3; //extracting LSB 2 Bits + nr_UESpec_TCI_StateInd_PDSCH->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.servingCellId) & 0x1F; //extracting LSB 5 bits + + for(i = 0; i < (num_octects * 8); i++) { + if(ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.tciStateActDeact[i]) + nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] = nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] | (1 << (i % 8)); } - // Contention resolution fixed subheader and MAC CE - if (ue_cont_res_id) { - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_CON_RES_ID; - mac_pdu_ptr++; - //last_size = 1; + mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + //Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)nr_UESpec_TCI_StateInd_PDSCH, mac_ce_size); + //incrementing the mac pdu pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + //freeing the allocated memory + free(nr_UESpec_TCI_StateInd_PDSCH); + } - // contention resolution identity MAC ce has a fixed 48 bit size - // this contains the UL CCCH SDU. If UL CCCH SDU is longer than 48 bits, - // it contains the first 48 bits of the UL CCCH SDU - LOG_T(MAC, "[gNB ][RAPROC] Generate contention resolution msg: %x.%x.%x.%x.%x.%x\n", - ue_cont_res_id[0], ue_cont_res_id[1], ue_cont_res_id[2], - ue_cont_res_id[3], ue_cont_res_id[4], ue_cont_res_id[5]); + //TS38.321 Sec 6.1.3.13 Aperiodic CSI Trigger State Subselection MAC CE + if (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.is_scheduled) { + //Computing the number of octects to be allocated for Flexible array member + //of MAC CE structure + uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.highestTriggerStateSelected) / 8 + 1; //Calculating the number of octects for allocating the memory + //filling the subheader + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_APERIODIC_CSI_TRI_STATE_SUBSEL; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + last_size = 2; + //Incrementing the PDU pointer + mac_pdu_ptr += last_size; + //allocating memory for CE structure + NR_TCI_PDSCH_APERIODIC_CSI *nr_Aperiodic_CSI_Trigger = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //initializing to zero + memset((void *)nr_Aperiodic_CSI_Trigger, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); + //filling the CE Structure + nr_Aperiodic_CSI_Trigger->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.bwpId) & 0x3; //extracting LSB 2 bits + nr_Aperiodic_CSI_Trigger->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.servingCellId) & 0x1F; //extracting LSB 5 bits + nr_Aperiodic_CSI_Trigger->R = 0; - // Copying bytes (6 octects) to CEs pointer - mac_ce_size = 6; - memcpy(ce_ptr, ue_cont_res_id, mac_ce_size); - - // Copying bytes for MAC CEs to mac pdu pointer - memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size); - ce_ptr += mac_ce_size; - mac_pdu_ptr += (unsigned char) mac_ce_size; + for(i = 0; i < (num_octects * 8); i++) { + if(ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.triggerStateSelection[i]) + nr_Aperiodic_CSI_Trigger->T[i / 8] = nr_Aperiodic_CSI_Trigger->T[i / 8] | (1 << (i % 8)); } -#ifdef GES_SUPPORT + mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); + // Copying bytes for MAC CEs to the mac pdu pointer + memcpy((void *) mac_pdu_ptr, (void *)nr_Aperiodic_CSI_Trigger, mac_ce_size); + //incrementing the mac pdu pointer + mac_pdu_ptr += (unsigned char) mac_ce_size; + //freeing the allocated memory + free(nr_Aperiodic_CSI_Trigger); + } - //TS 38.321 Sec 6.1.3.15 TCI State indication for UE Specific PDCCH MAC CE SubPDU generation - if (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.is_scheduled) { - //filling subheader - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_TCI_STATE_IND_UE_SPEC_PDCCH; - mac_pdu_ptr++; - //Creating the instance of CE structure - NR_TCI_PDCCH nr_UESpec_TCI_StateInd_PDCCH; - //filling the CE structre - nr_UESpec_TCI_StateInd_PDCCH.CoresetId1 = ((ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0xF) >> 1; //extracting MSB 3 bits from LS nibble - nr_UESpec_TCI_StateInd_PDCCH.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.servingCellId) & 0x1F; //extracting LSB 5 Bits - nr_UESpec_TCI_StateInd_PDCCH.TciStateId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.tciStateId) & 0x7F; //extracting LSB 7 bits - nr_UESpec_TCI_StateInd_PDCCH.CoresetId2 = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0x1; //extracting LSB 1 bit - LOG_D(MAC, "NR MAC CE TCI state indication for UE Specific PDCCH = %d \n", nr_UESpec_TCI_StateInd_PDCCH.TciStateId); - mac_ce_size = sizeof(NR_TCI_PDCCH); - // Copying bytes for MAC CEs to the mac pdu pointer - memcpy((void *) mac_pdu_ptr, (void *)&nr_UESpec_TCI_StateInd_PDCCH, mac_ce_size); - //incrementing the PDU pointer - mac_pdu_ptr += (unsigned char) mac_ce_size; - } + if (ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.is_scheduled) { + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_SP_ZP_CSI_RS_RES_SET_ACT; + mac_pdu_ptr++; + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->A_D = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.act_deact; + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CELLID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id & 0x1F; //5 bits + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->BWPID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid & 0x3; //2 bits + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CSIRS_RSC_ID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id & 0xF; //4 bits + ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->R = 0; + LOG_D(MAC, "NR MAC CE of ZP CSIRS Serv cell ID = %d BWPID= %d Rsc set ID = %d\n", ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id, ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid, + ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id); + mac_ce_size = sizeof(NR_MAC_CE_SP_ZP_CSI_RS_RES_SET); + mac_pdu_ptr += (unsigned char) mac_ce_size; + } - //TS 38.321 Sec 6.1.3.16, SP CSI reporting on PUCCH Activation/Deactivation MAC CE - if (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.is_scheduled) { - //filling the subheader - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_REP_PUCCH_ACT; - mac_pdu_ptr++; - //creating the instance of CE structure - NR_PUCCH_CSI_REPORTING nr_PUCCH_CSI_reportingActDeact; - //filling the CE structure - nr_PUCCH_CSI_reportingActDeact.BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.bwpId) & 0x3; //extracting LSB 2 bibs - nr_PUCCH_CSI_reportingActDeact.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.servingCellId) & 0x1F; //extracting LSB 5 bits - nr_PUCCH_CSI_reportingActDeact.S0 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[0]; - nr_PUCCH_CSI_reportingActDeact.S1 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[1]; - nr_PUCCH_CSI_reportingActDeact.S2 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[2]; - nr_PUCCH_CSI_reportingActDeact.S3 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[3]; - nr_PUCCH_CSI_reportingActDeact.R2 = 0; - mac_ce_size = sizeof(NR_PUCCH_CSI_REPORTING); - // Copying MAC CE data to the mac pdu pointer - memcpy((void *) mac_pdu_ptr, (void *)&nr_PUCCH_CSI_reportingActDeact, mac_ce_size); - //incrementing the PDU pointer - mac_pdu_ptr += (unsigned char) mac_ce_size; - } - - //TS 38.321 Sec 6.1.3.14, TCI State activation/deactivation for UE Specific PDSCH MAC CE - if (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.is_scheduled) { - //Computing the number of octects to be allocated for Flexible array member - //of MAC CE structure - uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.highestTciStateActivated) / 8 + 1; //Calculating the number of octects for allocating the memory - - //filling the subheader - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_TCI_STATE_ACT_UE_SPEC_PDSCH; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); - last_size = 2; - //Incrementing the PDU pointer - mac_pdu_ptr += last_size; - //allocating memory for CE Structure - NR_TCI_PDSCH_APERIODIC_CSI *nr_UESpec_TCI_StateInd_PDSCH = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); - //initializing to zero - memset((void *)nr_UESpec_TCI_StateInd_PDSCH, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); - //filling the CE Structure - nr_UESpec_TCI_StateInd_PDSCH->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.bwpId) & 0x3; //extracting LSB 2 Bits - nr_UESpec_TCI_StateInd_PDSCH->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.servingCellId) & 0x1F; //extracting LSB 5 bits - for(i = 0; i < (num_octects * 8); i++) { - if(ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.tciStateActDeact[i]) - nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] = nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] | (1 << (i % 8)); - } - mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); - //Copying bytes for MAC CEs to the mac pdu pointer - memcpy((void *) mac_pdu_ptr, (void *)nr_UESpec_TCI_StateInd_PDSCH, mac_ce_size); - //incrementing the mac pdu pointer - mac_pdu_ptr += (unsigned char) mac_ce_size; - //freeing the allocated memory - free(nr_UESpec_TCI_StateInd_PDSCH); - } - - //TS38.321 Sec 6.1.3.13 Aperiodic CSI Trigger State Subselection MAC CE - if (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.is_scheduled) { - //Computing the number of octects to be allocated for Flexible array member - //of MAC CE structure - uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.highestTriggerStateSelected) / 8 + 1; //Calculating the number of octects for allocating the memory - - //filling the subheader - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_APERIODIC_CSI_TRI_STATE_SUBSEL; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); - last_size = 2; - //Incrementing the PDU pointer - mac_pdu_ptr += last_size; - //allocating memory for CE structure - NR_TCI_PDSCH_APERIODIC_CSI *nr_Aperiodic_CSI_Trigger = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); - //initializing to zero - memset((void *)nr_Aperiodic_CSI_Trigger, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t)); - //filling the CE Structure - nr_Aperiodic_CSI_Trigger->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.bwpId) & 0x3; //extracting LSB 2 bits - nr_Aperiodic_CSI_Trigger->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.servingCellId) & 0x1F; //extracting LSB 5 bits - nr_Aperiodic_CSI_Trigger->R = 0; - for(i = 0; i < (num_octects * 8); i++) { - if(ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.triggerStateSelection[i]) - nr_Aperiodic_CSI_Trigger->T[i / 8] = nr_Aperiodic_CSI_Trigger->T[i / 8] | (1 << (i % 8)); - } - mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t); - // Copying bytes for MAC CEs to the mac pdu pointer - memcpy((void *) mac_pdu_ptr, (void *)nr_Aperiodic_CSI_Trigger, mac_ce_size); - //incrementing the mac pdu pointer - mac_pdu_ptr += (unsigned char) mac_ce_size; - //freeing the allocated memory - free(nr_Aperiodic_CSI_Trigger); - } - - if (ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.is_scheduled) { - ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_SP_ZP_CSI_RS_RES_SET_ACT; - mac_pdu_ptr++; - ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->A_D = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.act_deact; - ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CELLID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id & 0x1F; //5 bits - ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->BWPID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid & 0x3; //2 bits - ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CSIRS_RSC_ID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id & 0xF; //4 bits - ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->R = 0; - LOG_D(MAC, "NR MAC CE of ZP CSIRS Serv cell ID = %d BWPID= %d Rsc set ID = %d\n", ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id, ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid, ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id); - mac_ce_size = sizeof(NR_MAC_CE_SP_ZP_CSI_RS_RES_SET); - mac_pdu_ptr += (unsigned char) mac_ce_size; - } - - if (ue_sched_ctl->UE_mac_ce_ctrl.csi_im.is_scheduled) { - mac_pdu_ptr->R = 0; - mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT; - mac_pdu_ptr++; - CSI_RS_CSI_IM_ACT_DEACT_MAC_CE csi_rs_im_act_deact_ce; - csi_rs_im_act_deact_ce.A_D = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.act_deact; - csi_rs_im_act_deact_ce.SCID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.serv_cellid & 0x3F;//gNB_PHY -> ssb_pdu.ssb_pdu_rel15.PhysCellId; - csi_rs_im_act_deact_ce.BWP_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.bwp_id; - csi_rs_im_act_deact_ce.R1 = 0; - csi_rs_im_act_deact_ce.IM = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.im;// IF set CSI IM Rsc id will presesent else CSI IM RSC ID is abscent - csi_rs_im_act_deact_ce.SP_CSI_RSID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nzp_csi_rsc_id; - - if ( csi_rs_im_act_deact_ce.IM ) { //is_scheduled if IM is 1 else this field will not present - csi_rs_im_act_deact_ce.R2 = 0; - csi_rs_im_act_deact_ce.SP_CSI_IMID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.csi_im_rsc_id; - mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE ); - } else { - mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE ) - 1; - } - - memcpy ((void *) mac_pdu_ptr, (void *) & ( csi_rs_im_act_deact_ce), mac_ce_size); - mac_pdu_ptr += (unsigned char) mac_ce_size; - - if (csi_rs_im_act_deact_ce.A_D ) { //Following IE is_scheduled only if A/D is 1 - mac_ce_size = sizeof ( struct TCI_S); - - for ( i = 0; i < ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nb_tci_resource_set_id; i++) { - csi_rs_im_act_deact_ce.TCI_STATE.R = 0; - csi_rs_im_act_deact_ce.TCI_STATE.TCI_STATE_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.tci_state_id [i] & 0x7F; - memcpy ((void *) mac_pdu_ptr, (void *) & (csi_rs_im_act_deact_ce.TCI_STATE), mac_ce_size); - mac_pdu_ptr += (unsigned char) mac_ce_size; - } - - } - } - -#endif - - // 2) Generation of DLSCH MAC subPDUs including subheaders and MAC SDUs - for (i = 0; i < num_sdus; i++) { - LOG_D(MAC, "[gNB] Generate DLSCH header num sdu %d len sdu %d\n", num_sdus, sdu_lengths[i]); - - if (sdu_lengths[i] < 128) { - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = sdu_lcids[i]; - ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = (unsigned char) sdu_lengths[i]; - last_size = 2; - } else { - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->F = 1; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->LCID = sdu_lcids[i]; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L1 = ((unsigned short) sdu_lengths[i] >> 8) & 0x7f; - ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L2 = (unsigned short) sdu_lengths[i] & 0xff; - last_size = 3; - } - - mac_pdu_ptr += last_size; - - // 3) cycle through SDUs, compute each relevant and place dlsch_buffer in - memcpy((void *) mac_pdu_ptr, (void *) dlsch_buffer_ptr, sdu_lengths[i]); - dlsch_buffer_ptr += sdu_lengths[i]; - mac_pdu_ptr += sdu_lengths[i]; - } - - // 4) Compute final offset for padding - if (post_padding > 0) { - ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; - ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_PADDING; - mac_pdu_ptr++; + if (ue_sched_ctl->UE_mac_ce_ctrl.csi_im.is_scheduled) { + mac_pdu_ptr->R = 0; + mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT; + mac_pdu_ptr++; + CSI_RS_CSI_IM_ACT_DEACT_MAC_CE csi_rs_im_act_deact_ce; + csi_rs_im_act_deact_ce.A_D = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.act_deact; + csi_rs_im_act_deact_ce.SCID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.serv_cellid & 0x3F;//gNB_PHY -> ssb_pdu.ssb_pdu_rel15.PhysCellId; + csi_rs_im_act_deact_ce.BWP_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.bwp_id; + csi_rs_im_act_deact_ce.R1 = 0; + csi_rs_im_act_deact_ce.IM = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.im;// IF set CSI IM Rsc id will presesent else CSI IM RSC ID is abscent + csi_rs_im_act_deact_ce.SP_CSI_RSID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nzp_csi_rsc_id; + if ( csi_rs_im_act_deact_ce.IM ) { //is_scheduled if IM is 1 else this field will not present + csi_rs_im_act_deact_ce.R2 = 0; + csi_rs_im_act_deact_ce.SP_CSI_IMID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.csi_im_rsc_id; + mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE ); } else { - // no MAC subPDU with padding + mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE ) - 1; } - // compute final offset - offset = ((unsigned char *) mac_pdu_ptr - mac_pdu); + memcpy ((void *) mac_pdu_ptr, (void *) & ( csi_rs_im_act_deact_ce), mac_ce_size); + mac_pdu_ptr += (unsigned char) mac_ce_size; - //printf("Offset %d \n", ((unsigned char *) mac_pdu_ptr - mac_pdu)); + if (csi_rs_im_act_deact_ce.A_D ) { //Following IE is_scheduled only if A/D is 1 + mac_ce_size = sizeof ( struct TCI_S); - return offset; + for ( i = 0; i < ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nb_tci_resource_set_id; i++) { + csi_rs_im_act_deact_ce.TCI_STATE.R = 0; + csi_rs_im_act_deact_ce.TCI_STATE.TCI_STATE_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.tci_state_id [i] & 0x7F; + memcpy ((void *) mac_pdu_ptr, (void *) & (csi_rs_im_act_deact_ce.TCI_STATE), mac_ce_size); + mac_pdu_ptr += (unsigned char) mac_ce_size; + } + } + } + + // 2) Generation of DLSCH MAC subPDUs including subheaders and MAC SDUs + for (i = 0; i < num_sdus; i++) { + LOG_D(MAC, "[gNB] Generate DLSCH header num sdu %d len sdu %d\n", num_sdus, sdu_lengths[i]); + + if (sdu_lengths[i] < 128) { + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = sdu_lcids[i]; + ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = (unsigned char) sdu_lengths[i]; + last_size = 2; + } else { + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->F = 1; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->LCID = sdu_lcids[i]; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L1 = ((unsigned short) sdu_lengths[i] >> 8) & 0x7f; + ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L2 = (unsigned short) sdu_lengths[i] & 0xff; + last_size = 3; + } + + mac_pdu_ptr += last_size; + // 3) cycle through SDUs, compute each relevant and place dlsch_buffer in + memcpy((void *) mac_pdu_ptr, (void *) dlsch_buffer_ptr, sdu_lengths[i]); + dlsch_buffer_ptr += sdu_lengths[i]; + mac_pdu_ptr += sdu_lengths[i]; + } + + // 4) Compute final offset for padding + if (post_padding > 0) { + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0; + ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_PADDING; + mac_pdu_ptr++; + } else { + // no MAC subPDU with padding + } + + // compute final offset + offset = ((unsigned char *) mac_pdu_ptr - mac_pdu); + //printf("Offset %d \n", ((unsigned char *) mac_pdu_ptr - mac_pdu)); + return offset; } /* functionalities of this function have been moved to nr_schedule_uss_dlsch_phytest */ diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index eaf7934128..32fd5d7354 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -76,176 +76,174 @@ #define NR_NB_RA_PROC_MAX 4 typedef enum { - RA_IDLE = 0, - Msg2 = 1, - WAIT_Msg3 = 2, - Msg4 = 3, - WAIT_Msg4_ACK = 4 + RA_IDLE = 0, + Msg2 = 1, + WAIT_Msg3 = 2, + Msg4 = 3, + WAIT_Msg4_ACK = 4 } RA_gNB_state_t; /*! \brief gNB template for the Random access information */ typedef struct { - /// Flag to indicate this process is active - RA_gNB_state_t state; - /// BWP id of RA process - int bwp_id; - /// CORESET0 configured flag - int coreset0_configured; - /// Slot where preamble was received - uint8_t preamble_slot; - /// Subframe where Msg2 is to be sent - uint8_t Msg2_slot; - /// Frame where Msg2 is to be sent - frame_t Msg2_frame; - /// Subframe where Msg3 is to be sent - sub_frame_t Msg3_slot; - /// Frame where Msg3 is to be sent - frame_t Msg3_frame; - /// Msg3 time domain allocation index - uint8_t Msg3_tda_id; - /// Subframe where Msg4 is to be sent - sub_frame_t Msg4_slot; - /// Frame where Msg4 is to be sent - frame_t Msg4_frame; - /// harq_pid used for Msg4 transmission - uint8_t harq_pid; - /// UE RNTI allocated during RAR - rnti_t rnti; - /// RA RNTI allocated from received PRACH - uint16_t RA_rnti; - /// Received preamble_index - uint8_t preamble_index; - /// Received UE Contention Resolution Identifier - uint8_t cont_res_id[6]; - /// Timing offset indicated by PHY - int16_t timing_offset; - /// Timeout for RRC connection - int16_t RRC_timer; - /// Msg3 first RB - uint8_t msg3_first_rb; - /// Msg3 number of RB - uint8_t msg3_nb_rb; - /// Msg3 TPC command - uint8_t msg3_TPC; - /// Msg3 ULdelay command - uint8_t msg3_ULdelay; - /// Msg3 cqireq command - uint8_t msg3_cqireq; - /// Round of Msg3 HARQ - uint8_t msg3_round; - /// Msg3 pusch pdu - nfapi_nr_pusch_pdu_t pusch_pdu; - /// TBS used for Msg4 - int msg4_TBsize; - /// MCS used for Msg4 - int msg4_mcs; - /// RA search space - NR_SearchSpace_t *ra_ss; + /// Flag to indicate this process is active + RA_gNB_state_t state; + /// BWP id of RA process + int bwp_id; + /// CORESET0 configured flag + int coreset0_configured; + /// Slot where preamble was received + uint8_t preamble_slot; + /// Subframe where Msg2 is to be sent + uint8_t Msg2_slot; + /// Frame where Msg2 is to be sent + frame_t Msg2_frame; + /// Subframe where Msg3 is to be sent + sub_frame_t Msg3_slot; + /// Frame where Msg3 is to be sent + frame_t Msg3_frame; + /// Msg3 time domain allocation index + uint8_t Msg3_tda_id; + /// Subframe where Msg4 is to be sent + sub_frame_t Msg4_slot; + /// Frame where Msg4 is to be sent + frame_t Msg4_frame; + /// harq_pid used for Msg4 transmission + uint8_t harq_pid; + /// UE RNTI allocated during RAR + rnti_t rnti; + /// RA RNTI allocated from received PRACH + uint16_t RA_rnti; + /// Received preamble_index + uint8_t preamble_index; + /// Received UE Contention Resolution Identifier + uint8_t cont_res_id[6]; + /// Timing offset indicated by PHY + int16_t timing_offset; + /// Timeout for RRC connection + int16_t RRC_timer; + /// Msg3 first RB + uint8_t msg3_first_rb; + /// Msg3 number of RB + uint8_t msg3_nb_rb; + /// Msg3 TPC command + uint8_t msg3_TPC; + /// Msg3 ULdelay command + uint8_t msg3_ULdelay; + /// Msg3 cqireq command + uint8_t msg3_cqireq; + /// Round of Msg3 HARQ + uint8_t msg3_round; + /// Msg3 pusch pdu + nfapi_nr_pusch_pdu_t pusch_pdu; + /// TBS used for Msg4 + int msg4_TBsize; + /// MCS used for Msg4 + int msg4_mcs; + /// RA search space + NR_SearchSpace_t *ra_ss; } NR_RA_t; /*! \brief gNB common channels */ typedef struct { - int physCellId; - int p_gNB; - int Ncp; - int nr_band; - lte_frame_type_t frame_type; - uint64_t dl_CarrierFreq; - NR_BCCH_BCH_Message_t *mib; - NR_ServingCellConfigCommon_t *ServingCellConfigCommon; - NR_ARFCN_ValueEUTRA_t ul_CarrierFreq; - long ul_Bandwidth; - /// Outgoing MIB PDU for PHY - MIB_PDU MIB_pdu; - /// Outgoing BCCH pdu for PHY - BCCH_PDU BCCH_pdu; - /// Outgoing BCCH DCI allocation - uint32_t BCCH_alloc_pdu; - /// Outgoing CCCH pdu for PHY - CCCH_PDU CCCH_pdu; - /// Outgoing PCCH DCI allocation - uint32_t PCCH_alloc_pdu; - /// Outgoing PCCH pdu for PHY - PCCH_PDU PCCH_pdu; - /// Outgoing RAR pdu for PHY - RAR_PDU RAR_pdu; - /// Template for RA computations - NR_RA_t ra[NR_NB_RA_PROC_MAX]; - /// VRB map for common channels - uint8_t vrb_map[100]; - /// VRB map for common channels and retransmissions by PHICH - uint8_t vrb_map_UL[100]; - /// number of subframe allocation pattern available for MBSFN sync area - uint8_t num_sf_allocation_pattern; + int physCellId; + int p_gNB; + int Ncp; + int nr_band; + lte_frame_type_t frame_type; + uint64_t dl_CarrierFreq; + NR_BCCH_BCH_Message_t *mib; + NR_ServingCellConfigCommon_t *ServingCellConfigCommon; + NR_ARFCN_ValueEUTRA_t ul_CarrierFreq; + long ul_Bandwidth; + /// Outgoing MIB PDU for PHY + MIB_PDU MIB_pdu; + /// Outgoing BCCH pdu for PHY + BCCH_PDU BCCH_pdu; + /// Outgoing BCCH DCI allocation + uint32_t BCCH_alloc_pdu; + /// Outgoing CCCH pdu for PHY + CCCH_PDU CCCH_pdu; + /// Outgoing PCCH DCI allocation + uint32_t PCCH_alloc_pdu; + /// Outgoing PCCH pdu for PHY + PCCH_PDU PCCH_pdu; + /// Outgoing RAR pdu for PHY + RAR_PDU RAR_pdu; + /// Template for RA computations + NR_RA_t ra[NR_NB_RA_PROC_MAX]; + /// VRB map for common channels + uint8_t vrb_map[100]; + /// VRB map for common channels and retransmissions by PHICH + uint8_t vrb_map_UL[100]; + /// number of subframe allocation pattern available for MBSFN sync area + uint8_t num_sf_allocation_pattern; } NR_COMMON_channels_t; -#ifdef GES_SUPPORT // SP ZP CSI-RS Resource Set Activation/Deactivation MAC CE typedef struct sp_zp_csirs { - bool is_scheduled; //ZP CSI-RS ACT/Deact MAC CE is scheduled - bool act_deact; //Activation/Deactivation indication - uint8_t serv_cell_id; //Identity of Serving cell for which MAC CE applies - uint8_t bwpid; //Downlink BWP id - uint8_t rsc_id; //SP ZP CSI-RS resource set + bool is_scheduled; //ZP CSI-RS ACT/Deact MAC CE is scheduled + bool act_deact; //Activation/Deactivation indication + uint8_t serv_cell_id; //Identity of Serving cell for which MAC CE applies + uint8_t bwpid; //Downlink BWP id + uint8_t rsc_id; //SP ZP CSI-RS resource set } sp_zp_csirs_t; //SP CSI-RS / CSI-IM Resource Set Activation/Deactivation MAC CE #define MAX_CSI_RESOURCE_SET 64 typedef struct csi_rs_im { - bool is_scheduled; - bool act_deact; - uint8_t serv_cellid; - uint8_t bwp_id; - bool im; - uint8_t csi_im_rsc_id; - uint8_t nzp_csi_rsc_id; - uint8_t nb_tci_resource_set_id; - uint8_t tci_state_id [ MAX_CSI_RESOURCE_SET ]; + bool is_scheduled; + bool act_deact; + uint8_t serv_cellid; + uint8_t bwp_id; + bool im; + uint8_t csi_im_rsc_id; + uint8_t nzp_csi_rsc_id; + uint8_t nb_tci_resource_set_id; + uint8_t tci_state_id [ MAX_CSI_RESOURCE_SET ]; } csi_rs_im_t; typedef struct pdcchStateInd { - bool is_scheduled; - uint8_t servingCellId; - uint8_t coresetId; - uint8_t tciStateId; + bool is_scheduled; + uint8_t servingCellId; + uint8_t coresetId; + uint8_t tciStateId; } pdcchStateInd_t; typedef struct SPCSIReportingpucch { - bool is_scheduled; - uint8_t servingCellId; - uint8_t bwpId; - bool s0tos3_actDeact[4]; + bool is_scheduled; + uint8_t servingCellId; + uint8_t bwpId; + bool s0tos3_actDeact[4]; } SPCSIReportingpucch_t; #define MAX_APERIODIC_TRIGGER_STATES 128 //38.331 typedef struct aperiodicCSI_triggerStateSelection { - bool is_scheduled; - uint8_t servingCellId; - uint8_t bwpId; - uint8_t highestTriggerStateSelected; - bool triggerStateSelection[MAX_APERIODIC_TRIGGER_STATES]; + bool is_scheduled; + uint8_t servingCellId; + uint8_t bwpId; + uint8_t highestTriggerStateSelected; + bool triggerStateSelection[MAX_APERIODIC_TRIGGER_STATES]; } aperiodicCSI_triggerStateSelection_t; #define MAX_TCI_STATES 128 //38.331 typedef struct pdschTciStatesActDeact { - bool is_scheduled; - uint8_t servingCellId; - uint8_t bwpId; - uint8_t highestTciStateActivated; - bool tciStateActDeact[MAX_TCI_STATES]; + bool is_scheduled; + uint8_t servingCellId; + uint8_t bwpId; + uint8_t highestTciStateActivated; + bool tciStateActDeact[MAX_TCI_STATES]; } pdschTciStatesActDeact_t; typedef struct UE_info { - sp_zp_csirs_t sp_zp_csi_rs; - csi_rs_im_t csi_im; - pdcchStateInd_t pdcch_state_ind; - SPCSIReportingpucch_t SP_CSI_reporting_pucch; - aperiodicCSI_triggerStateSelection_t aperi_CSI_trigger; - pdschTciStatesActDeact_t pdsch_TCI_States_ActDeact; + sp_zp_csirs_t sp_zp_csi_rs; + csi_rs_im_t csi_im; + pdcchStateInd_t pdcch_state_ind; + SPCSIReportingpucch_t SP_CSI_reporting_pucch; + aperiodicCSI_triggerStateSelection_t aperi_CSI_trigger; + pdschTciStatesActDeact_t pdsch_TCI_States_ActDeact; } NR_UE_mac_ce_ctrl_t; -#endif typedef struct NR_sched_pucch { int frame; @@ -263,14 +261,13 @@ typedef struct { NR_sched_pucch *sched_pucch; uint16_t ta_timer; int16_t ta_update; - int dummy; -#ifdef GES_SUPPORT - NR_UE_mac_ce_ctrl_t UE_mac_ce_ctrl;// MAC CE related information -#endif + int dummy; + NR_UE_mac_ce_ctrl_t UE_mac_ce_ctrl;// MAC CE related information } NR_UE_sched_ctrl_t; /*! \brief UE list used by gNB to order UEs/CC for scheduling*/ typedef struct { +<<<<<<< 8533610e2abb78ee712ceed939c08b5d0b5e835a <<<<<<< 3bce9a7b85f6f8dff8ba2f98142451a90fd8f8bd DLSCH_PDU DLSCH_pdu[4][MAX_MOBILES_PER_GNB]; /// scheduling control info @@ -284,90 +281,76 @@ typedef struct { boolean_t active[MAX_MOBILES_PER_GNB]; rnti_t rnti[MAX_MOBILES_PER_GNB]; NR_CellGroupConfig_t *secondaryCellGroup[MAX_MOBILES_PER_GNB]; -======= - DLSCH_PDU DLSCH_pdu[4][MAX_MOBILES_PER_GNB]; - /// scheduling control info - UE_sched_ctrl_t UE_sched_ctrl[MAX_MOBILES_PER_GNB]; - int next[MAX_MOBILES_PER_GNB]; - int head; - int next_ul[MAX_MOBILES_PER_GNB]; - int head_ul; - int avail; - int num_UEs; - boolean_t active[MAX_MOBILES_PER_GNB]; - rnti_t rnti[MAX_MOBILES_PER_GNB]; - NR_CellGroupConfig_t *secondaryCellGroup[MAX_MOBILES_PER_GNB]; ->>>>>>> GlobalEdge: CSI and TCI related MAC CE intial commit } NR_UE_list_t; /*! \brief top level gNB MAC structure */ typedef struct gNB_MAC_INST_s { - /// Ethernet parameters for northbound midhaul interface - eth_params_t eth_params_n; - /// Ethernet parameters for fronthaul interface - eth_params_t eth_params_s; - /// Module - module_id_t Mod_id; - /// frame counter - frame_t frame; - /// slot counter - int slot; - /// timing advance group - NR_TAG_t *tag; - /// Pointer to IF module instance for PHY - NR_IF_Module_t *if_inst; - /// TA command - int ta_command; - /// MAC CE flag indicating TA length - int ta_len; - /// Common cell resources - NR_COMMON_channels_t common_channels[NFAPI_CC_MAX]; - /// current PDU index (BCH,DLSCH) - uint16_t pdu_index[NFAPI_CC_MAX]; + /// Ethernet parameters for northbound midhaul interface + eth_params_t eth_params_n; + /// Ethernet parameters for fronthaul interface + eth_params_t eth_params_s; + /// Module + module_id_t Mod_id; + /// frame counter + frame_t frame; + /// slot counter + int slot; + /// timing advance group + NR_TAG_t *tag; + /// Pointer to IF module instance for PHY + NR_IF_Module_t *if_inst; + /// TA command + int ta_command; + /// MAC CE flag indicating TA length + int ta_len; + /// Common cell resources + NR_COMMON_channels_t common_channels[NFAPI_CC_MAX]; + /// current PDU index (BCH,DLSCH) + uint16_t pdu_index[NFAPI_CC_MAX]; - /// NFAPI Config Request Structure - nfapi_nr_config_request_scf_t config[NFAPI_CC_MAX]; - /// NFAPI DL Config Request Structure - nfapi_nr_dl_tti_request_t DL_req[NFAPI_CC_MAX]; - /// NFAPI UL TTI Request Structure (this is from the new SCF specs) - nfapi_nr_ul_tti_request_t UL_tti_req[NFAPI_CC_MAX]; - /// NFAPI HI/DCI0 Config Request Structure - nfapi_nr_ul_dci_request_t UL_dci_req[NFAPI_CC_MAX]; - /// NFAPI DL PDU structure - nfapi_nr_tx_data_request_t TX_req[NFAPI_CC_MAX]; + /// NFAPI Config Request Structure + nfapi_nr_config_request_scf_t config[NFAPI_CC_MAX]; + /// NFAPI DL Config Request Structure + nfapi_nr_dl_tti_request_t DL_req[NFAPI_CC_MAX]; + /// NFAPI UL TTI Request Structure (this is from the new SCF specs) + nfapi_nr_ul_tti_request_t UL_tti_req[NFAPI_CC_MAX]; + /// NFAPI HI/DCI0 Config Request Structure + nfapi_nr_ul_dci_request_t UL_dci_req[NFAPI_CC_MAX]; + /// NFAPI DL PDU structure + nfapi_nr_tx_data_request_t TX_req[NFAPI_CC_MAX]; - NR_UE_list_t UE_list; + NR_UE_list_t UE_list; - /// UL handle - uint32_t ul_handle; + /// UL handle + uint32_t ul_handle; - // MAC function execution peformance profiler - /// processing time of eNB scheduler - time_stats_t eNB_scheduler; - /// processing time of eNB scheduler for SI - time_stats_t schedule_si; - /// processing time of eNB scheduler for Random access - time_stats_t schedule_ra; - /// processing time of eNB ULSCH scheduler - time_stats_t schedule_ulsch; - /// processing time of eNB DCI generation - time_stats_t fill_DLSCH_dci; - /// processing time of eNB MAC preprocessor - time_stats_t schedule_dlsch_preprocessor; - /// processing time of eNB DLSCH scheduler - time_stats_t schedule_dlsch; // include rlc_data_req + MAC header + preprocessor - /// processing time of eNB MCH scheduler - time_stats_t schedule_mch; - /// processing time of eNB ULSCH reception - time_stats_t rx_ulsch_sdu; // include rlc_data_ind - /// processing time of eNB PCH scheduler - time_stats_t schedule_pch; - /// CCE lists - int cce_list[MAX_NUM_BWP][MAX_NUM_CORESET][MAX_NUM_CCE]; + // MAC function execution peformance profiler + /// processing time of eNB scheduler + time_stats_t eNB_scheduler; + /// processing time of eNB scheduler for SI + time_stats_t schedule_si; + /// processing time of eNB scheduler for Random access + time_stats_t schedule_ra; + /// processing time of eNB ULSCH scheduler + time_stats_t schedule_ulsch; + /// processing time of eNB DCI generation + time_stats_t fill_DLSCH_dci; + /// processing time of eNB MAC preprocessor + time_stats_t schedule_dlsch_preprocessor; + /// processing time of eNB DLSCH scheduler + time_stats_t schedule_dlsch; // include rlc_data_req + MAC header + preprocessor + /// processing time of eNB MCH scheduler + time_stats_t schedule_mch; + /// processing time of eNB ULSCH reception + time_stats_t rx_ulsch_sdu; // include rlc_data_ind + /// processing time of eNB PCH scheduler + time_stats_t schedule_pch; + /// CCE lists + int cce_list[MAX_NUM_BWP][MAX_NUM_CORESET][MAX_NUM_CCE]; } gNB_MAC_INST; typedef struct { -<<<<<<< 3bce9a7b85f6f8dff8ba2f98142451a90fd8f8bd + uint8_t format_indicator; //1 bit uint16_t frequency_domain_assignment; //up to 16 bits uint8_t time_domain_assignment; // 4 bits @@ -424,65 +407,6 @@ typedef struct { uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits uint16_t padding; -======= - - uint8_t format_indicator; //1 bit - uint16_t frequency_domain_assignment; //up to 16 bits - uint8_t time_domain_assignment; // 4 bits - uint8_t frequency_hopping_flag; //1 bit - - uint8_t ra_preamble_index; //6 bits - uint8_t ss_pbch_index; //6 bits - uint8_t prach_mask_index; //4 bits - - uint8_t vrb_to_prb_mapping; //0 or 1 bit - uint8_t mcs; //5 bits - uint8_t ndi; //1 bit - uint8_t rv; //2 bits - uint8_t harq_pid; //4 bits - uint8_t dai; //0, 2 or 4 bits - uint8_t dai1; //1 or 2 bits - uint8_t dai2; //0 or 2 bits - uint8_t tpc; //2 bits - uint8_t pucch_resource_indicator; //3 bits - uint8_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits - - uint8_t short_messages_indicator; //2 bits - uint8_t short_messages; //8 bits - uint8_t tb_scaling; //2 bits - - uint8_t carrier_indicator; //0 or 3 bits - uint8_t bwp_indicator; //0, 1 or 2 bits - uint8_t prb_bundling_size_indicator; //0 or 1 bits - uint8_t rate_matching_indicator; //0, 1 or 2 bits - uint8_t zp_csi_rs_trigger; //0, 1 or 2 bits - uint8_t transmission_configuration_indication; //0 or 3 bits - uint8_t srs_request; //2 bits - uint8_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits - uint8_t cbgfi; //CBG Flushing Out Information: 0 or 1 bit - uint8_t dmrs_sequence_initialization; //0 or 1 bit - - uint8_t srs_resource_indicator; - uint8_t precoding_information; - uint8_t csi_request; - uint8_t ptrs_dmrs_association; - uint8_t beta_offset_indicator; //0 or 2 bits - - uint8_t slot_format_indicator_count; - uint8_t *slot_format_indicators; - - uint8_t pre_emption_indication_count; - uint16_t *pre_emption_indications; //14 bit - - uint8_t block_number_count; - uint8_t *block_numbers; - - uint8_t ul_sul_indicator; //0 or 1 bit - uint8_t antenna_ports; - - uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits - uint16_t padding; ->>>>>>> GlobalEdge: CSI and TCI related MAC CE intial commit } dci_pdu_rel15_t; From 06fa1f8e0f99e9bb1a0c7402641022249d1b9858 Mon Sep 17 00:00:00 2001 From: "vr.devendra" Date: Fri, 22 May 2020 20:15:12 +0530 Subject: [PATCH 337/553] GlobalEdge: CSI and TCI related MAC CE intial commit --- cmake_targets/CMakeLists.txt | 1 + openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 5 ++--- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index 5ac5053412..15b94a1082 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -249,6 +249,7 @@ add_boolean_option(UE_AUTOTEST_TRACE False "Activate UE autotest specific logs add_boolean_option(UE_DEBUG_TRACE False "Activate UE debug trace") add_boolean_option(UE_TIMING_TRACE False "Activate UE timing trace") add_boolean_option(DEBUG_CONSOLE False "makes debugging easier, disables stdout/stderr buffering") +add_boolean_option(GES_SUPPORT True "To enable the GES Code") set (OCP_ITTI ${OPENAIR_DIR}/common/utils/ocp_itti) add_library(ITTI diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index 32fd5d7354..23401eea58 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -254,6 +254,7 @@ typedef struct NR_sched_pucch { struct NR_sched_pucch *next_sched_pucch; } NR_sched_pucch; + /*! \brief scheduling control information set through an API */ typedef struct { uint64_t dlsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains dlsch @@ -267,8 +268,6 @@ typedef struct { /*! \brief UE list used by gNB to order UEs/CC for scheduling*/ typedef struct { -<<<<<<< 8533610e2abb78ee712ceed939c08b5d0b5e835a -<<<<<<< 3bce9a7b85f6f8dff8ba2f98142451a90fd8f8bd DLSCH_PDU DLSCH_pdu[4][MAX_MOBILES_PER_GNB]; /// scheduling control info NR_UE_sched_ctrl_t UE_sched_ctrl[MAX_MOBILES_PER_GNB]; @@ -283,7 +282,7 @@ typedef struct { NR_CellGroupConfig_t *secondaryCellGroup[MAX_MOBILES_PER_GNB]; } NR_UE_list_t; -/*! \brief top level gNB MAC structure */ +/*! \brief top level eNB MAC structure */ typedef struct gNB_MAC_INST_s { /// Ethernet parameters for northbound midhaul interface eth_params_t eth_params_n; From 8642d3e779f49be8da65d4a8a9ed24e0f18fefcb Mon Sep 17 00:00:00 2001 From: Rangaswami Date: Thu, 4 Jun 2020 11:04:43 +0530 Subject: [PATCH 338/553] Corrected indentation and removed GES macro --- cmake_targets/CMakeLists.txt | 1 - 1 file changed, 1 deletion(-) diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index 15b94a1082..5ac5053412 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -249,7 +249,6 @@ add_boolean_option(UE_AUTOTEST_TRACE False "Activate UE autotest specific logs add_boolean_option(UE_DEBUG_TRACE False "Activate UE debug trace") add_boolean_option(UE_TIMING_TRACE False "Activate UE timing trace") add_boolean_option(DEBUG_CONSOLE False "makes debugging easier, disables stdout/stderr buffering") -add_boolean_option(GES_SUPPORT True "To enable the GES Code") set (OCP_ITTI ${OPENAIR_DIR}/common/utils/ocp_itti) add_library(ITTI From 2eb799c3b6f1cfb88089912c778efe1189938607 Mon Sep 17 00:00:00 2001 From: laurent Date: Thu, 18 Jun 2020 15:52:54 +0200 Subject: [PATCH 339/553] fix pdcp race condition --- openair2/LAYER2/PDCP_v10.1.0/pdcp.c | 51 +++++++---------- openair2/LAYER2/PDCP_v10.1.0/pdcp.h | 2 +- openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c | 73 +++++++++++------------- 3 files changed, 55 insertions(+), 71 deletions(-) diff --git a/openair2/LAYER2/PDCP_v10.1.0/pdcp.c b/openair2/LAYER2/PDCP_v10.1.0/pdcp.c index 617cb4d313..3667af2698 100644 --- a/openair2/LAYER2/PDCP_v10.1.0/pdcp.c +++ b/openair2/LAYER2/PDCP_v10.1.0/pdcp.c @@ -503,8 +503,6 @@ pdcp_data_ind( //----------------------------------------------------------------------------- { pdcp_t *pdcp_p = NULL; - list_t *sdu_list_p = NULL; - mem_block_t *new_sdu_p = NULL; uint8_t pdcp_header_len = 0; uint8_t pdcp_tailer_len = 0; pdcp_sn_t sequence_number = 0; @@ -576,7 +574,6 @@ pdcp_data_ind( } } - sdu_list_p = &pdcp_sdu_list; if (sdu_buffer_sizeP == 0) { LOG_W(PDCP, "SDU buffer size is zero! Ignoring this chunk!\n"); @@ -974,9 +971,8 @@ pdcp_data_ind( #endif if (FALSE == packet_forwarded) { - new_sdu_p = get_free_mem_block(sdu_buffer_sizeP - payload_offset + sizeof (pdcp_data_ind_header_t), __func__); + notifiedFIFO_elt_t * new_sdu_p = newNotifiedFIFO_elt(sdu_buffer_sizeP - payload_offset + sizeof (pdcp_data_ind_header_t), 0, NULL, NULL); - if (new_sdu_p) { if ((MBMS_flagP == 0) && (pdcp_p->rlc_mode == RLC_MODE_AM)) { pdcp_p->last_submitted_pdcp_rx_sn = sequence_number; } @@ -984,14 +980,15 @@ pdcp_data_ind( /* * Prepend PDCP indication header which is going to be removed at pdcp_fifo_flush_sdus() */ - memset(new_sdu_p->data, 0, sizeof (pdcp_data_ind_header_t)); - ((pdcp_data_ind_header_t *) new_sdu_p->data)->data_size = sdu_buffer_sizeP - payload_offset; + pdcp_data_ind_header_t * pdcpHead=(pdcp_data_ind_header_t *)NotifiedFifoData(new_sdu_p); + memset(pdcpHead, 0, sizeof (pdcp_data_ind_header_t)); + pdcpHead->data_size = sdu_buffer_sizeP - payload_offset; AssertFatal((sdu_buffer_sizeP - payload_offset >= 0), "invalid PDCP SDU size!"); // Here there is no virtualization possible // set ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst for IP layer here if (ctxt_pP->enb_flag == ENB_FLAG_NO) { - ((pdcp_data_ind_header_t *) new_sdu_p->data)->rb_id = rb_id; + pdcpHead->rb_id = rb_id; if (EPC_MODE_ENABLED) { /* for the UE compiled in S1 mode, we need 1 here @@ -1002,45 +999,40 @@ pdcp_data_ind( #ifdef UESIM_EXPANSION if (UE_NAS_USE_TUN) { - ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst = ctxt_pP->module_id; + pdcpHead->inst = ctxt_pP->module_id; } else { - ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst = 0; + pdcpHead->inst = 0; } #else - ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst = ctxt_pP->module_id; + pdcpHead->inst = ctxt_pP->module_id; #endif } else { // nfapi_mode if (UE_NAS_USE_TUN) { - ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst = ctxt_pP->module_id; + pdcpHead->inst = ctxt_pP->module_id; } else { - ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst = 1; + pdcpHead->inst = 1; } } // nfapi_mode } } else { - ((pdcp_data_ind_header_t *) new_sdu_p->data)->rb_id = rb_id + (ctxt_pP->module_id * LTE_maxDRB); - ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst = ctxt_pP->module_id; + pdcpHead->rb_id = rb_id + (ctxt_pP->module_id * LTE_maxDRB); + pdcpHead->inst = ctxt_pP->module_id; } if( LOG_DEBUGFLAG(DEBUG_PDCP) ) { static uint32_t pdcp_inst = 0; - ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst = pdcp_inst++; - LOG_D(PDCP, "inst=%d size=%d\n", ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst, ((pdcp_data_ind_header_t *) new_sdu_p->data)->data_size); + pdcpHead->inst = pdcp_inst++; + LOG_D(PDCP, "inst=%d size=%d\n", pdcpHead->inst, pdcpHead->data_size); } - memcpy(&new_sdu_p->data[sizeof (pdcp_data_ind_header_t)], + memcpy(pdcpHead+1, &sdu_buffer_pP->data[payload_offset], sdu_buffer_sizeP - payload_offset); - - #if defined(ENABLE_PDCP_PAYLOAD_DEBUG) - LOG_I(PDCP, "Printing first bytes of PDCP SDU before adding it to the list: \n"); - for (int i=0; i<30; i++){ - LOG_I(PDCP, "%x", sdu_buffer_pP->data[i]); - } - #endif - list_add_tail_eurecom (new_sdu_p, sdu_list_p); - } + if( LOG_DEBUGFLAG(DEBUG_PDCP) ) + log_dump(PDCP, pdcpHead+1, min(sdu_buffer_sizeP - payload_offset,30) , LOG_DUMP_CHAR, + "Printing first bytes of PDCP SDU before adding it to the list: \n"); + pushNotifiedFIFO(&pdcp_sdu_list, new_sdu_p); /* Print octets of incoming data in hexadecimal form */ LOG_D(PDCP, "Following content has been received from RLC (%d,%d)(PDCP header has already been removed):\n", @@ -2467,7 +2459,7 @@ void pdcp_layer_init(void) /* * Initialize SDU list */ - list_init(&pdcp_sdu_list, NULL); + initNotifiedFIFO(&pdcp_sdu_list); pdcp_coll_p = hashtable_create ((LTE_maxDRB + 2) * NUMBER_OF_UE_MAX, NULL, pdcp_free); AssertFatal(pdcp_coll_p != NULL, "UNRECOVERABLE error, PDCP hashtable_create failed"); @@ -2540,7 +2532,8 @@ void pdcp_layer_init(void) void pdcp_layer_cleanup (void) //----------------------------------------------------------------------------- { - list_free (&pdcp_sdu_list); + //list_free (&pdcp_sdu_list); + while(pollNotifiedFIFO(&pdcp_sdu_list)) {}; hashtable_destroy(&pdcp_coll_p); #ifdef MBMS_MULTICAST_OUT diff --git a/openair2/LAYER2/PDCP_v10.1.0/pdcp.h b/openair2/LAYER2/PDCP_v10.1.0/pdcp.h index e9ac85866c..8e265e8cf1 100644 --- a/openair2/LAYER2/PDCP_v10.1.0/pdcp.h +++ b/openair2/LAYER2/PDCP_v10.1.0/pdcp.h @@ -522,7 +522,7 @@ pdcp_mbms_t pdcp_mbms_array_eNB[NUMBER_OF_eNB_MAX][LTE_maxServiceC sdu_size_t pdcp_output_sdu_bytes_to_write; sdu_size_t pdcp_output_header_bytes_to_write; -list_t pdcp_sdu_list; +notifiedFIFO_t pdcp_sdu_list; int pdcp_sent_a_sdu; pdcp_data_req_header_t pdcp_input_header; unsigned char pdcp_input_sdu_buffer[MAX_IP_PACKET_SIZE]; diff --git a/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c b/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c index d203408e55..14d95b15b3 100644 --- a/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c +++ b/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c @@ -111,69 +111,59 @@ void debug_pdcp_pc5s_sdu(sidelink_pc5s_element *sl_pc5s_msg, char *title) { } //----------------------------------------------------------------------------- int pdcp_fifo_flush_sdus(const protocol_ctxt_t *const ctxt_pP) { - mem_block_t *sdu_p; + notifiedFIFO_elt_t *sdu_p; int pdcp_nb_sdu_sent = 0; int ret=0; + while ((sdu_p = pollNotifiedFIFO(&pdcp_sdu_list)) != NULL ) { + pdcp_data_ind_header_t * pdcpHead=(pdcp_data_ind_header_t *)NotifiedFifoData(sdu_p); + AssertFatal(pdcpHead->inst==ctxt_pP->module_id, "To implement correctly multi module id\n"); - while ((sdu_p = list_get_head (&pdcp_sdu_list)) != NULL && ((pdcp_data_ind_header_t *)(sdu_p->data))->inst == ctxt_pP->module_id) { - ((pdcp_data_ind_header_t *)(sdu_p->data))->inst = 0; - int rb_id = ((pdcp_data_ind_header_t *)(sdu_p->data))->rb_id; + int rb_id = pdcpHead->rb_id; int sizeToWrite= sizeof (pdcp_data_ind_header_t) + - ((pdcp_data_ind_header_t *) sdu_p->data)->data_size; + pdcpHead->data_size; + void * pdcpData=(void*)(pdcpHead+1); if (rb_id == 10) { //hardcoded for PC5-Signaling if( LOG_DEBUGFLAG(DEBUG_PDCP) ) { - debug_pdcp_pc5s_sdu((sidelink_pc5s_element *)&(sdu_p->data[sizeof(pdcp_data_ind_header_t)]), + debug_pdcp_pc5s_sdu((sidelink_pc5s_element *)pdcpData, "pdcp_fifo_flush_sdus sends a aPC5S message"); } - ret = sendto(pdcp_pc5_sockfd, &(sdu_p->data[sizeof(pdcp_data_ind_header_t)]), + ret = sendto(pdcp_pc5_sockfd, pdcpData, sizeof(sidelink_pc5s_element), 0, (struct sockaddr *)&prose_pdcp_addr,sizeof(prose_pdcp_addr) ); } else if (UE_NAS_USE_TUN) { //ret = write(nas_sock_fd[ctxt_pP->module_id], &(sdu_p->data[sizeof(pdcp_data_ind_header_t)]),sizeToWrite ); if(rb_id == mbms_rab_id){ - ret = write(nas_sock_mbms_fd, &(sdu_p->data[sizeof(pdcp_data_ind_header_t)]),sizeToWrite ); - LOG_I(PDCP,"[PDCP_FIFOS] ret %d TRIED TO PUSH MBMS DATA TO rb_id %d handle %d sizeToWrite %d\n",ret,rb_id,nas_sock_fd[ctxt_pP->module_id],sizeToWrite); + ret = write(nas_sock_mbms_fd, pdcpData,sizeToWrite ); + LOG_I(PDCP,"[PDCP_FIFOS] ret %d TRIED TO PUSH MBMS DATA TO rb_id %d handle %d sizeToWrite %d\n", + ret,rb_id,nas_sock_fd[ctxt_pP->module_id],sizeToWrite); } else { - #if defined(ENABLE_PDCP_PAYLOAD_DEBUG) - LOG_I(PHY, "PDCP output to be sent to TUN interface: \n"); - for (int i = sizeof(pdcp_data_ind_header_t); i < sizeToWrite; i++) { - printf("%02x ",(unsigned char)sdu_p->data[i]); - } - printf("\n"); - #endif - ret = write(nas_sock_fd[ctxt_pP->module_id], &(sdu_p->data[sizeof(pdcp_data_ind_header_t)]),sizeToWrite ); - //LOG_I(PDCP,"[PDCP_FIFOS] ret %d TRIED TO PUSH DATA TO rb_id %d handle %d sizeToWrite %d\n",ret,rb_id,nas_sock_fd[ctxt_pP->module_id],sizeToWrite); + if( LOG_DEBUGFLAG(DEBUG_PDCP) ) + log_dump(PDCP, pdcpData, sizeToWrite, LOG_DUMP_CHAR,"PDCP output to be sent to TUN interface: \n"); + ret = write(nas_sock_fd[ctxt_pP->module_id], pdcpData,sizeToWrite ); + LOG_T(PDCP,"[UE PDCP_FIFOS] ret %d TRIED TO PUSH DATA TO rb_id %d handle %d sizeToWrite %d\n", + ret,rb_id,nas_sock_fd[ctxt_pP->module_id],sizeToWrite); } } else if (ENB_NAS_USE_TUN) { - #if defined(ENABLE_PDCP_PAYLOAD_DEBUG) - LOG_I(PHY, "PDCP output to be sent to TUN interface: \n"); - for (int i = sizeof(pdcp_data_ind_header_t); i < sizeToWrite; i++) { - printf("%02x ",(unsigned char)sdu_p->data[i]); - } - printf("\n"); - #endif - ret = write(nas_sock_fd[0], &(sdu_p->data[sizeof(pdcp_data_ind_header_t)]), sizeToWrite); - + if( LOG_DEBUGFLAG(DEBUG_PDCP) ) + log_dump(PDCP, pdcpData, sizeToWrite, LOG_DUMP_CHAR,"PDCP output to be sent to TUN interface: \n"); + ret = write(nas_sock_fd[0], pdcpData, sizeToWrite); + LOG_T(PDCP,"[NB PDCP_FIFOS] ret %d TRIED TO PUSH DATA TO rb_id %d handle %d sizeToWrite %d\n",ret,rb_id,nas_sock_fd[0],sizeToWrite); } else if (PDCP_USE_NETLINK) { - memcpy(NLMSG_DATA(nas_nlh_tx), (uint8_t *) sdu_p->data, sizeToWrite); + memcpy(NLMSG_DATA(nas_nlh_tx), (uint8_t *) pdcpHead, sizeToWrite); nas_nlh_tx->nlmsg_len = sizeToWrite; ret = sendmsg(nas_sock_fd[0],&nas_msg_tx,0); } // PDCP_USE_NETLINK AssertFatal(ret >= 0,"[PDCP_FIFOS] pdcp_fifo_flush_sdus (errno: %d %s), nas_sock_fd[0]: %d\n", errno, strerror(errno), nas_sock_fd[0]); - #if defined(ENABLE_PDCP_PAYLOAD_DEBUG) - LOG_I(PDCP, "Printing first bytes of PDCP SDU before removing it from the list: \n"); - for (int i=0; i<30; i++){ - LOG_I(PDCP, "%x", sdu_p->data[i]); - } - #endif - list_remove_head (&pdcp_sdu_list); - free_mem_block (sdu_p, __func__); + if( LOG_DEBUGFLAG(DEBUG_PDCP) ) + log_dump(PDCP, pdcpData, min(sizeToWrite,30) , LOG_DUMP_CHAR, + "Printing first bytes of PDCP SDU before removing it from the list: \n"); + delNotifiedFIFO_elt (sdu_p); pdcp_nb_sdu_sent ++; } @@ -181,12 +171,13 @@ int pdcp_fifo_flush_sdus(const protocol_ctxt_t *const ctxt_pP) { } int pdcp_fifo_flush_mbms_sdus(const protocol_ctxt_t *const ctxt_pP) { - mem_block_t *sdu_p; + notifiedFIFO_elt_t *sdu_p; int pdcp_nb_sdu_sent = 0; //int ret=0; - while ((sdu_p = list_get_head (&pdcp_sdu_list)) != NULL && ((pdcp_data_ind_header_t *)(sdu_p->data))->inst == ctxt_pP->module_id) { - ((pdcp_data_ind_header_t *)(sdu_p->data))->inst = 0; + while ((sdu_p = pollNotifiedFIFO(&pdcp_sdu_list)) != NULL ) { + pdcp_data_ind_header_t * pdcpHead=(pdcp_data_ind_header_t *)NotifiedFifoData(sdu_p); + AssertFatal(pdcpHead->inst==ctxt_pP->module_id, "To implement correctly multi module id\n"); //int rb_id = ((pdcp_data_ind_header_t *)(sdu_p->data))->rb_id; //int sizeToWrite= sizeof (pdcp_data_ind_header_t) + //((pdcp_data_ind_header_t *) sdu_p->data)->data_size; @@ -212,8 +203,8 @@ int pdcp_fifo_flush_mbms_sdus(const protocol_ctxt_t *const ctxt_pP) { //} // PDCP_USE_NETLINK //AssertFatal(ret >= 0,"[PDCP_FIFOS] pdcp_fifo_flush_sdus (errno: %d %s)\n", errno, strerror(errno)); - list_remove_head (&pdcp_sdu_list); - free_mem_block (sdu_p, __func__); + //AssertFatal(ret >= 0,"[PDCP_FIFOS] pdcp_fifo_flush_sdus (errno: %d %s)\n", errno, strerror(errno)); + delNotifiedFIFO_elt (sdu_p); pdcp_nb_sdu_sent ++; } From 3217b51256b18b61afd1e3afbe3dd4aa31dc9051 Mon Sep 17 00:00:00 2001 From: WANG Tsu-Han Date: Thu, 18 Jun 2020 16:55:02 +0200 Subject: [PATCH 340/553] simulation fix --- targets/RT/USER/lte-ru.c | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/targets/RT/USER/lte-ru.c b/targets/RT/USER/lte-ru.c index 3124c7a232..4d89020077 100644 --- a/targets/RT/USER/lte-ru.c +++ b/targets/RT/USER/lte-ru.c @@ -2341,20 +2341,23 @@ void init_RU_proc(RU_t *ru) { LOG_I(PHY,"%s() DJP - added creation of pthread_prach\n", __FUNCTION__); pthread_create( &proc->pthread_prach, attr_prach, ru_thread_prach, (void *)ru ); ru->state=RU_RUN; - /*fill_rf_config(ru,ru->rf_config_file); - init_frame_parms(ru->frame_parms,1); - ru->frame_parms->nb_antennas_rx = ru->nb_rx; - phy_init_RU(ru); - ret = openair0_device_load(&ru->rfdevice,&ru->openair0_cfg); - if (ret < 0) { - LOG_I(PHY,"Exiting, cannot load device. Make sure that your SDR board is connected!\n"); - exit(1); - } + if(!get_softmodem_params()->emulate_rf) + { + fill_rf_config(ru,ru->rf_config_file); + init_frame_parms(ru->frame_parms,1); + ru->frame_parms->nb_antennas_rx = ru->nb_rx; + phy_init_RU(ru); + ret = openair0_device_load(&ru->rfdevice,&ru->openair0_cfg); + if (ret < 0) { + LOG_I(PHY,"Exiting, cannot load device. Make sure that your SDR board is connected!\n"); + exit(1); + } - if (setup_RU_buffers(ru)!=0) { - LOG_I(PHY,"Exiting, cannot initialize RU Buffers\n"); - exit(1); - }*/ + if (setup_RU_buffers(ru)!=0) { + LOG_I(PHY,"Exiting, cannot initialize RU Buffers\n"); + exit(1); + } + } } if (get_thread_worker_conf() == WORKER_ENABLE) { From 2029cb93c9cb1bdc7228866aaee346eba8abdceb Mon Sep 17 00:00:00 2001 From: Thomas Schlichter Date: Wed, 17 Jun 2020 09:24:21 +0200 Subject: [PATCH 341/553] update configuration file gnb.band78.tm1.106PRB.usrpx300.conf based on gnb.band78.tm1.106PRB.usrpn300.conf --- .../CONF/gnb.band78.tm1.106PRB.usrpx300.conf | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpx300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpx300.conf index 06aa4f6f9f..2e643d8392 100644 --- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpx300.conf +++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpx300.conf @@ -33,10 +33,10 @@ gNBs = # downlinkConfigCommon #frequencyInfoDL # this is 3600 MHz + 43 PRBs@30kHz SCS (same as initial BWP) - absoluteFrequencySSB = 633032; + absoluteFrequencySSB = 641032; dl_frequencyBand = 78; - # this is 3480 MHz - dl_absoluteFrequencyPointA = 632000; + # this is 3600 MHz + dl_absoluteFrequencyPointA = 640000; #scs-SpecificCarrierList dl_offstToCarrier = 0; # subcarrierSpacing @@ -148,7 +148,7 @@ gNBs = # ssb_PositionsInBurs_BitmapPR # 1=short, 2=medium, 3=long ssb_PositionsInBurst_PR = 2; - ssb_PositionsInBurst_Bitmap = 255; + ssb_PositionsInBurst_Bitmap = 1; # ssb_periodicityServingCell # 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1 @@ -237,7 +237,8 @@ RUs = ( max_pdschReferenceSignalPower = -27; max_rxgain = 114; eNB_instances = [0]; - sdr_addrs = "type=x300"; + sdr_addrs = "type=x300"; + clock_src = "external"; } ); From f47dcb199acb447d21b222e56712eb0c59bb157b Mon Sep 17 00:00:00 2001 From: Thomas Schlichter Date: Wed, 17 Jun 2020 09:49:31 +0200 Subject: [PATCH 342/553] enable TA update in phy-test mode --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 58 ++++++++++--------- .../LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c | 2 +- 2 files changed, 31 insertions(+), 29 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index 8c8b0b9b43..e3d55711a7 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -412,38 +412,40 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, rnti = 0;//UE_RNTI(module_idP, i); CC_id = 0;//UE_PCCID(module_idP, i); - } //END if (UE_list->active[i]) - } //END for (i = 0; i < MAX_MOBILES_PER_GNB; i++) - */ - - // This schedules MIB - if((slot_txP == 0) && (frame_txP & 7) == 0){ - schedule_nr_mib(module_idP, frame_txP, slot_txP); - } + } //END if (UE_list->active[i]) + } //END for (i = 0; i < MAX_MOBILES_PER_GNB; i++) + */ - // TbD once RACH is available, start ta_timer when UE is connected -#if 0 - NR_UE_sched_ctrl_t *ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; - if (ue_sched_ctl->ta_timer) ue_sched_ctl->ta_timer--; + // This schedules MIB + if((slot_txP == 0) && (frame_txP & 7) == 0){ + schedule_nr_mib(module_idP, frame_txP, slot_txP); + } - if (ue_sched_ctl->ta_timer == 0) { - gNB->ta_command = ue_sched_ctl->ta_update; - /* if time is up, then set the timer to not send it for 5 frames - // regardless of the TA value */ - ue_sched_ctl->ta_timer = 100; - /* reset ta_update */ - ue_sched_ctl->ta_update = 31; - /* MAC CE flag indicating TA length */ - gNB->ta_len = 2; - } -#endif + // Phytest scheduling + if (get_softmodem_params()->phy_test) { + NR_UE_sched_ctrl_t *ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; - // Phytest scheduling - if (get_softmodem_params()->phy_test && slot_txP==1){ - nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, pucch_sched, NULL); + // TbD once RACH is available, start ta_timer when UE is connected + if (ue_sched_ctl->ta_timer) + ue_sched_ctl->ta_timer--; + + if (ue_sched_ctl->ta_timer == 0) { + gNB->ta_command = ue_sched_ctl->ta_update; + /* if time is up, then set the timer to not send it for 5 frames + // regardless of the TA value */ + ue_sched_ctl->ta_timer = 100; + /* reset ta_update */ + ue_sched_ctl->ta_update = 31; + /* MAC CE flag indicating TA length */ + gNB->ta_len = 2; + } + + if (slot_txP == 1){ + nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, pucch_sched, NULL); // resetting ta flag - gNB->ta_len = 0; - } + gNB->ta_len = 0; + } + } /* // Allocate CCEs for good after scheduling is done diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c index eb8d338949..2b7c2274eb 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c @@ -276,7 +276,7 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP, #endif if (sduP != NULL){ - //UE_scheduling_control->ta_update = timing_advance; + UE_scheduling_control->ta_update = timing_advance; LOG_D(MAC, "Received PDU at MAC gNB \n"); nr_process_mac_pdu(gnb_mod_idP, CC_idP, frameP, sduP, sdu_lenP); } From efb7bd8417acb28d678786a2547bc8d4c697a823 Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Thu, 18 Jun 2020 22:30:16 +0200 Subject: [PATCH 343/553] CPPCHECK: fixes Signed-off-by: Raphael Defosseux --- ci-scripts/cppcheck_suppressions.list | 1 + common/config/libconfig/config_libconfig.c | 2 +- openair1/PHY/NR_TRANSPORT/nr_prach.c | 3 --- openair1/PHY/NR_TRANSPORT/pucch_rx.c | 2 +- openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c | 5 ++++- openair1/PHY/TOOLS/nr_phy_scope.c | 3 +++ openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 3 ++- openair1/SIMULATION/NR_PHY/nr_dummy_functions_prach.c | 2 +- openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 2 +- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 2 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 2 +- 11 files changed, 16 insertions(+), 11 deletions(-) diff --git a/ci-scripts/cppcheck_suppressions.list b/ci-scripts/cppcheck_suppressions.list index cad2aab88b..727fd22e74 100644 --- a/ci-scripts/cppcheck_suppressions.list +++ b/ci-scripts/cppcheck_suppressions.list @@ -37,6 +37,7 @@ memleak:openair2/UTIL/OMG/omg_hashtable.c // _emm_as_encode function creates the encoded buffer // memleak:openair3/NAS/UE/EMM/SAP/emm_as.c +memleak:openair1/PHY/INIT/nr_init_ue.c //----------------------------------------------------------------------------- //***************************************************************************** // section for files not used in oai exec's included in CI. diff --git a/common/config/libconfig/config_libconfig.c b/common/config/libconfig/config_libconfig.c index b510ca28bc..2e9fd614c5 100644 --- a/common/config/libconfig/config_libconfig.c +++ b/common/config/libconfig/config_libconfig.c @@ -180,7 +180,7 @@ int config_libconfig_get(paramdef_t *cfgoptions,int numoptions, char *prefix ) { printf_params("[LIBCONFIG] %s: %llu\n", cfgpath,(long long unsigned)(*(cfgoptions[i].u64ptr)) ); } else { *(cfgoptions[i].i64ptr) = llu; - printf_params("[LIBCONFIG] %s: %llu\n", cfgpath,(long long)(*(cfgoptions[i].i64ptr)) ); + printf_params("[LIBCONFIG] %s: %lld\n", cfgpath,(long long)(*(cfgoptions[i].i64ptr)) ); } } else { defval=config_setdefault_int64(&(cfgoptions[i]),prefix); diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index 85e4df62cf..c4951ffe4e 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -563,9 +563,6 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, int16_t prach_ifft_tmp[2048*2] __attribute__((aligned(32))); int32_t *prach_ifft=(int32_t*)NULL; - - AssertFatal(gNB!=NULL,"gNB is null\n"); - fp = &gNB->frame_parms; nb_rx = gNB->gNB_config.carrier_config.num_rx_ant.value; diff --git a/openair1/PHY/NR_TRANSPORT/pucch_rx.c b/openair1/PHY/NR_TRANSPORT/pucch_rx.c index dccaccacaa..166e2d7d78 100644 --- a/openair1/PHY/NR_TRANSPORT/pucch_rx.c +++ b/openair1/PHY/NR_TRANSPORT/pucch_rx.c @@ -1456,7 +1456,7 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB, // non-coherent LLR computation on groups of 4 REs (half-PRBs) int32_t corr_re,corr_im,corr_tmp; __m128i corr16,llr_num,llr_den; - uint64_t corr; + uint64_t corr = 0; for (int half_prb=0;half_prb<(2*pucch_pdu->prb_size);half_prb++) { llr_num=_mm_set1_epi16(0);llr_den=_mm_set1_epi16(0); diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c index 693284a052..d7441c01fd 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c @@ -211,7 +211,7 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, dlsch1_harq = dlsch[1]->harq_processes[codeword_TB1]; #ifdef DEBUG_HARQ - printf("[DEMOD] I am assuming only TB1 is active, it is in cw %d\n", dlsch0_harq->codeword); + printf("[DEMOD] I am assuming only TB1 is active, it is in cw %d\n", dlsch1_harq->codeword); #endif AssertFatal(1 == 0, "[UE][FATAL] DLSCH: TB0 not active and TB1 active case is not supported %d\n"); @@ -230,6 +230,9 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, } + if (dlsch0_harq = NULL) + AssertFatal(1 == 0, "Done\n"); + dlsch0_harq->Qm = nr_get_Qm_dl(dlsch[0]->harq_processes[harq_pid]->mcs, dlsch[0]->harq_processes[harq_pid]->mcs_table); dlsch0_harq->R = nr_get_code_rate_dl(dlsch[0]->harq_processes[harq_pid]->mcs, dlsch[0]->harq_processes[harq_pid]->mcs_table); diff --git a/openair1/PHY/TOOLS/nr_phy_scope.c b/openair1/PHY/TOOLS/nr_phy_scope.c index 61a38098a6..e7f83c5f76 100644 --- a/openair1/PHY/TOOLS/nr_phy_scope.c +++ b/openair1/PHY/TOOLS/nr_phy_scope.c @@ -286,6 +286,8 @@ static void puschIQ (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_var fl_set_xyplot_data(graph,I,Q,sz,"","",""); // PUSCH I/Q of MF Output +// Code to fixed, disabled for cppcheck +#if 0 if (NULL) { int32_t *pucch1ab_comp = (int32_t *) NULL; //phy_vars_gnb->pucch1ab_stats[UE_id]; int32_t *pucch1_comp = (int32_t *) NULL; //phy_vars_gnb->pucch1_stats[UE_id]; @@ -307,6 +309,7 @@ static void puschIQ (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_var fl_set_xyplot_xbounds(graph,-5000,5000); fl_set_xyplot_ybounds(graph,0,80); } +#endif } static void pucchEnergy (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int UE_id) { diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index caf644932a..6c0aacadc2 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -4111,12 +4111,13 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, LOG_D(PHY,"[UE %d] Frame %d, nr_tti_rx %d: found %d DCIs\n", ue->Mod_id, frame_rx, nr_tti_rx, dci_cnt); - NR_UE_DLSCH_t *dlsch; + NR_UE_DLSCH_t *dlsch = NULL; if (ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->active == 1){ dlsch = ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]; } else if (ue->dlsch_ra[0]->active == 1){ dlsch = ue->dlsch_ra[0]; } + AssertFatal(dlsch != NULL, "Unsupported mode\n"); uint8_t harq_pid = dlsch->current_harq_pid; NR_DL_UE_HARQ_t *dlsch0_harq = dlsch->harq_processes[harq_pid]; uint16_t nb_symb_sch = dlsch0_harq->nb_symbols; diff --git a/openair1/SIMULATION/NR_PHY/nr_dummy_functions_prach.c b/openair1/SIMULATION/NR_PHY/nr_dummy_functions_prach.c index e62155e54e..bfb9150868 100644 --- a/openair1/SIMULATION/NR_PHY/nr_dummy_functions_prach.c +++ b/openair1/SIMULATION/NR_PHY/nr_dummy_functions_prach.c @@ -91,7 +91,7 @@ void nr_get_prach_resources(module_id_t mod_id, NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon; // NR_BeamFailureRecoveryConfig_t *beam_failure_recovery_config = &mac->RA_BeamFailureRecoveryConfig; // todo - int messagePowerOffsetGroupB, messageSizeGroupA, PLThreshold, sizeOfRA_PreamblesGroupA, numberOfRA_Preambles, i, deltaPreamble_Msg3; + int messagePowerOffsetGroupB = 0, messageSizeGroupA, PLThreshold, sizeOfRA_PreamblesGroupA, numberOfRA_Preambles, i, deltaPreamble_Msg3 = 0; uint8_t noGroupB = 0, s_id, f_id, ul_carrier_id, msg1_FDM, prach_ConfigIndex, SFN_nbr, Msg3_size; // NR_RSRP_Range_t rsrp_ThresholdSSB; // todo diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c index f948cd43fb..b7aea902a9 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -88,7 +88,7 @@ void nr_get_prach_resources(module_id_t mod_id, // NR_BeamFailureRecoveryConfig_t *beam_failure_recovery_config = &mac->RA_BeamFailureRecoveryConfig; // todo - int messagePowerOffsetGroupB, messageSizeGroupA, PLThreshold, sizeOfRA_PreamblesGroupA, numberOfRA_Preambles, i, deltaPreamble_Msg3; + int messagePowerOffsetGroupB = 0, messageSizeGroupA, PLThreshold, sizeOfRA_PreamblesGroupA, numberOfRA_Preambles, i, deltaPreamble_Msg3 = 0; uint8_t noGroupB = 0, s_id, f_id, ul_carrier_id, prach_ConfigIndex, SFN_nbr, Msg3_size; AssertFatal(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 8e4d092591..0da02bd7d1 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -934,7 +934,7 @@ void nr_ue_msg2_scheduler(module_id_t mod_id, // and if the slot is not among the PDCCH monitored ones (38.213 10.1) while ((*msg2_slot > slot_limit) || ((*msg2_frame*nr_slots_per_frame[mu] + *msg2_slot - monitoring_offset) % monitoring_slot_period != 0)) { if((*msg2_slot % tdd_period_slot) > 0) - *msg2_slot--; + (*msg2_slot)--; else AssertFatal(1 == 0, "No available DL slot to schedule reception of msg2 has been found"); } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index 719571e29c..ba45def3f5 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -225,7 +225,7 @@ void nr_schedule_msg2(uint16_t rach_frame, uint16_t rach_slot, // and if the slot is not among the PDCCH monitored ones (38.213 10.1) while ((*msg2_slot>slot_limit) || ((*msg2_frame*nr_slots_per_frame[mu]+*msg2_slot-monitoring_offset)%monitoring_slot_period !=0)) { if((*msg2_slot%tdd_period_slot) > 0) - *msg2_slot--; + (*msg2_slot)--; else AssertFatal(1==0,"No available DL slot to schedule msg2 has been found"); } From 1ff1f3dda91845d7897422fd36523aed149b6a49 Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Thu, 18 Jun 2020 23:51:51 +0200 Subject: [PATCH 344/553] fix a bunch of compilation warnings --- openair1/PHY/NR_TRANSPORT/nr_prach.c | 2 +- openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c | 2 +- openair1/PHY/NR_TRANSPORT/pucch_rx.c | 2 +- openair1/PHY/NR_UE_TRANSPORT/dci_nr.c | 2 +- openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c | 4 ++-- openair1/PHY/NR_UE_TRANSPORT/nr_prach.c | 2 +- openair1/SCHED_NR_UE/fapi_nr_ue_l1.c | 6 +++--- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 2 +- openair1/SIMULATION/NR_PHY/prachsim.c | 2 +- openair1/SIMULATION/NR_PHY/pucchsim.c | 6 +++--- openair1/SIMULATION/NR_PHY/ulsim.c | 8 ++++---- openair2/GNB_APP/gnb_app.c | 4 ++-- openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c | 3 ++- openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 9 +++++---- openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c | 2 +- openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c | 2 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 5 +++-- openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c | 4 ++-- openair3/GTPV1-U/gtpv1u_gNB.c | 8 ++++---- openair3/S1AP/s1ap_eNB_nas_procedures.c | 10 +++++----- 20 files changed, 44 insertions(+), 41 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index c4951ffe4e..312ad6a475 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -164,7 +164,7 @@ void rx_nr_prach_ru(RU_t *ru, int dftlen=0; int mu = fp->numerology_index; - int Ncp; + int Ncp = 0; int16_t *prach2; if (prach_sequence_length == 0) { diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c index 17c6fe5336..d1282a90e7 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c +++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c @@ -232,7 +232,7 @@ void nr_ulsch_extract_rbs_single(int32_t **rxdataF, unsigned short start_re, re, nb_re_pusch; unsigned char aarx; - uint8_t K_ptrs; + uint8_t K_ptrs = 0; uint32_t rxF_ext_index = 0; uint32_t ul_ch0_ext_index = 0; uint32_t ul_ch0_index = 0; diff --git a/openair1/PHY/NR_TRANSPORT/pucch_rx.c b/openair1/PHY/NR_TRANSPORT/pucch_rx.c index 166e2d7d78..e17a549d8c 100644 --- a/openair1/PHY/NR_TRANSPORT/pucch_rx.c +++ b/openair1/PHY/NR_TRANSPORT/pucch_rx.c @@ -1585,7 +1585,7 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB, uci_pdu->sr.sr_bit_len = 1; uci_pdu->sr.sr_payload = malloc(1); uci_pdu->sr.sr_payload[0] = decodedPayload[0]&1; - decodedPayload[0]>>1; + decodedPayload[0] = decodedPayload[0]>>1; } // csi if (pucch_pdu->bit_len_csi_part1>0) { diff --git a/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c b/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c index 04dd321db2..7cde6e31c1 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c +++ b/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c @@ -846,7 +846,7 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue, rel15 = &pdcch_vars->pdcch_config[i]; int dci_length = rel15->dci_length; - int gNB_id = 0; + //int gNB_id = 0; int16_t tmp_e[16*108]; rnti_t n_rnti; diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c index d7441c01fd..7f941e5567 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c @@ -214,7 +214,7 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, printf("[DEMOD] I am assuming only TB1 is active, it is in cw %d\n", dlsch1_harq->codeword); #endif - AssertFatal(1 == 0, "[UE][FATAL] DLSCH: TB0 not active and TB1 active case is not supported %d\n"); + AssertFatal(1 == 0, "[UE][FATAL] DLSCH: TB0 not active and TB1 active case is not supported\n"); } else { LOG_E(PHY,"[UE][FATAL] nr_tti_rx %d: no active DLSCH\n", nr_tti_rx); @@ -230,7 +230,7 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, } - if (dlsch0_harq = NULL) + if (dlsch0_harq == NULL) AssertFatal(1 == 0, "Done\n"); dlsch0_harq->Qm = nr_get_Qm_dl(dlsch[0]->harq_processes[harq_pid]->mcs, dlsch[0]->harq_processes[harq_pid]->mcs_table); diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c index c8dcfdd3f9..e9e36f2c77 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c @@ -78,7 +78,7 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t slot){ uint16_t rootSequenceIndex, prach_fmt_id, NCS, *prach_root_sequence_map, preamble_offset = 0; uint16_t preamble_shift = 0, preamble_index0, n_shift_ra, n_shift_ra_bar, d_start, numshift, N_ZC, u, offset, offset2, first_nonzero_root_idx; int16_t prach_tmp[98304*2*4] __attribute__((aligned(32))); - int16_t Ncp, amp, *prach, *prach2, *prachF, *Xu; + int16_t Ncp = 0, amp, *prach, *prach2, *prachF, *Xu; int32_t Xu_re, Xu_im, samp_count; int prach_start, prach_sequence_length, i, prach_len, dftlen, mu, kbar, K, n_ra_prb, k; //int restricted_Type; diff --git a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c index 6d4e995701..f7e03b7dfe 100644 --- a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c +++ b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c @@ -51,7 +51,7 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ // Note: we have to handle the thread IDs for this. To be revisited completely. thread_id = PHY_vars_UE_g[module_id][cc_id]->current_thread_id[slot]; - NR_UE_DLSCH_t *dlsch0; + NR_UE_DLSCH_t *dlsch0 = NULL; NR_UE_PDCCH *pdcch_vars = PHY_vars_UE_g[module_id][cc_id]->pdcch_vars[thread_id][0]; NR_UE_ULSCH_t *ulsch0 = PHY_vars_UE_g[module_id][cc_id]->ulsch[thread_id][0][0]; @@ -123,7 +123,7 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ uint8_t pdu_type = ul_config->ul_config_list[i].pdu_type, pucch_resource_id, current_harq_pid, format, gNB_id = 0; /* PRACH */ - NR_PRACH_RESOURCES_t *prach_resources; + //NR_PRACH_RESOURCES_t *prach_resources; fapi_nr_ul_config_prach_pdu *prach_config_pdu; /* PUSCH */ nfapi_nr_ue_pusch_pdu_t *pusch_config_pdu; @@ -193,7 +193,7 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ case (FAPI_NR_UL_CONFIG_TYPE_PRACH): // prach config pdu - prach_resources = PHY_vars_UE_g[module_id][cc_id]->prach_resources[gNB_id]; + //prach_resources = PHY_vars_UE_g[module_id][cc_id]->prach_resources[gNB_id]; prach_config_pdu = &ul_config->ul_config_list[i].prach_config_pdu; memcpy((void*)&(PHY_vars_UE_g[module_id][cc_id]->prach_vars[gNB_id]->prach_pdu), (void*)prach_config_pdu, sizeof(fapi_nr_ul_config_prach_pdu)); PHY_vars_UE_g[module_id][cc_id]->prach_vars[gNB_id]->prach_Config_enabled = 1; diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 6c0aacadc2..8bcd5cbe26 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -4487,7 +4487,7 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t uint8_t mod_id = ue->Mod_id; UE_MODE_t UE_mode = get_nrUE_mode(mod_id, ue->CC_id, gNB_id); NR_PRACH_RESOURCES_t * prach_resources = ue->prach_resources[gNB_id]; - uint8_t nr_prach; + uint8_t nr_prach = 0; VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_IN); diff --git a/openair1/SIMULATION/NR_PHY/prachsim.c b/openair1/SIMULATION/NR_PHY/prachsim.c index f1aab42bc1..5fddf3290d 100644 --- a/openair1/SIMULATION/NR_PHY/prachsim.c +++ b/openair1/SIMULATION/NR_PHY/prachsim.c @@ -87,7 +87,7 @@ int main(int argc, char **argv){ double **s_re, **s_im, **r_re, **r_im, iqim = 0.0, delay_avg = 0, ue_speed = 0, fs, bw; int i, aa, aarx, **txdata, trial, n_frames = 1, prach_start, rx_prach_start; //, ntrials=1; int N_RB_UL = 106, delay = 0, NCS_config = 13, rootSequenceIndex = 1, threequarter_fs = 0, mu = 1, fd_occasion = 0, loglvl = OAILOG_INFO, numRA = 0, prachStartSymbol = 0; - uint8_t snr1set = 0, ue_speed1set = 0, transmission_mode = 1, n_tx = 1, n_rx = 1, awgn_flag = 0, msg1_frequencystart = 0, num_prach_fd_occasions = 1, prach_format; + uint8_t snr1set = 0, ue_speed1set = 0, transmission_mode = 1, n_tx = 1, n_rx = 1, awgn_flag = 0, msg1_frequencystart = 0, num_prach_fd_occasions = 1, prach_format = 0; uint8_t frame = 1, subframe = 19, config_index = 98, prach_sequence_length = 1, num_root_sequences = 16, restrictedSetConfig = 0, N_dur, N_t_slot, start_symbol; uint16_t Nid_cell = 0, preamble_tx = 0, preamble_delay, format, format0, format1; uint32_t tx_lev = 10000, prach_errors = 0, samp_count; //,tx_lev_dB; diff --git a/openair1/SIMULATION/NR_PHY/pucchsim.c b/openair1/SIMULATION/NR_PHY/pucchsim.c index bb64036cb7..dc5089a622 100644 --- a/openair1/SIMULATION/NR_PHY/pucchsim.c +++ b/openair1/SIMULATION/NR_PHY/pucchsim.c @@ -84,7 +84,7 @@ int main(int argc, char **argv) int format=0; //uint8_t extended_prefix_flag=0; FILE *input_fd=NULL; - uint8_t nacktoack_flag=0; + //uint8_t nacktoack_flag=0; int16_t amp=0x7FFF; int nr_tti_tx=0; uint64_t actual_payload=0,payload_received; @@ -283,7 +283,7 @@ int main(int argc, char **argv) actual_payload=atoi(optarg); break; case 'T': - nacktoack_flag=(uint8_t)atoi(optarg); + //nacktoack_flag=(uint8_t)atoi(optarg); target_error_rate=0.001; break; default: @@ -457,7 +457,7 @@ int main(int argc, char **argv) pucch_GroupHopping_t PUCCH_GroupHopping=UE->pucch_config_common_nr->pucch_GroupHopping; uint32_t hopping_id=UE->pucch_config_common_nr->hoppingId; uint32_t dmrs_scrambling_id = 0, data_scrambling_id=0; - t_nrPolar_params *currentPtr; + //t_nrPolar_params *currentPtr; if(format==0){ // for now we are not considering SR just HARQ-ACK diff --git a/openair1/SIMULATION/NR_PHY/ulsim.c b/openair1/SIMULATION/NR_PHY/ulsim.c index 97cc22264a..40653600e8 100644 --- a/openair1/SIMULATION/NR_PHY/ulsim.c +++ b/openair1/SIMULATION/NR_PHY/ulsim.c @@ -118,7 +118,7 @@ int main(int argc, char **argv) int trial, n_trials = 1, n_errors = 0, n_false_positive = 0, delay = 0; uint8_t n_tx = 1, n_rx = 1; //uint8_t transmission_mode = 1; - uint16_t Nid_cell = 0; + //uint16_t Nid_cell = 0; channel_desc_t *gNB2UE; uint8_t extended_prefix_flag = 0; //int8_t interf1 = -21, interf2 = -21; @@ -129,7 +129,7 @@ int main(int argc, char **argv) int frame_length_complex_samples,frame_length_complex_samples_no_prefix; NR_DL_FRAME_PARMS *frame_parms; int loglvl = OAILOG_WARNING; - uint64_t SSB_positions=0x01; + //uint64_t SSB_positions=0x01; uint16_t nb_symb_sch = 12; int start_symbol = 2; uint16_t nb_rb = 50; @@ -294,11 +294,11 @@ int main(int argc, char **argv) break; case 'M': - SSB_positions = atoi(optarg); + //SSB_positions = atoi(optarg); break; case 'N': - Nid_cell = atoi(optarg); + //Nid_cell = atoi(optarg); break; case 'R': diff --git a/openair2/GNB_APP/gnb_app.c b/openair2/GNB_APP/gnb_app.c index b8b14649d1..0a6f906312 100644 --- a/openair2/GNB_APP/gnb_app.c +++ b/openair2/GNB_APP/gnb_app.c @@ -75,12 +75,12 @@ static void configure_nr_rrc(uint32_t gnb_id) static uint32_t gNB_app_register(uint32_t gnb_id_start, uint32_t gnb_id_end)//, const Enb_properties_array_t *enb_properties) { uint32_t gnb_id; - MessageDef *msg_p; + //MessageDef *msg_p; uint32_t register_gnb_pending = 0; for (gnb_id = gnb_id_start; (gnb_id < gnb_id_end) ; gnb_id++) { { - s1ap_register_enb_req_t *s1ap_register_gNB; //Type Temporarily reuse + //s1ap_register_enb_req_t *s1ap_register_gNB; //Type Temporarily reuse // note: there is an implicit relationship between the data structure and the message name /*msg_p = itti_alloc_new_message (TASK_GNB_APP, S1AP_REGISTER_ENB_REQ); //Message Temporarily reuse diff --git a/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c b/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c index 5d99acfc3a..9d7f3264c5 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c @@ -130,6 +130,7 @@ int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id, uint16_t prach_forma AssertFatal(1 == 0, "[UE %d] ue_procedures.c: FATAL, Illegal preambleFormat %d, prachConfigIndex %d\n", mod_id, prach_format, prachConfigIndex); } } + return 0; } /* TS 38.321 subclause 5.1.3 - RA preamble transmission - ra_PREAMBLE_RECEIVED_TARGET_POWER configuration */ @@ -149,4 +150,4 @@ int nr_get_Po_NOMINAL_PUSCH(NR_PRACH_RESOURCES_t *prach_resources, module_id_t m receivedTargerPower = preambleReceivedTargetPower + delta_preamble + (mac->RA_PREAMBLE_POWER_RAMPING_COUNTER - 1) * prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP; return receivedTargerPower; -} \ No newline at end of file +} diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c index b7aea902a9..6a3f4ad902 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -88,7 +88,7 @@ void nr_get_prach_resources(module_id_t mod_id, // NR_BeamFailureRecoveryConfig_t *beam_failure_recovery_config = &mac->RA_BeamFailureRecoveryConfig; // todo - int messagePowerOffsetGroupB = 0, messageSizeGroupA, PLThreshold, sizeOfRA_PreamblesGroupA, numberOfRA_Preambles, i, deltaPreamble_Msg3 = 0; + int messagePowerOffsetGroupB = 0, messageSizeGroupA, PLThreshold, sizeOfRA_PreamblesGroupA = 0, numberOfRA_Preambles, i, deltaPreamble_Msg3 = 0; uint8_t noGroupB = 0, s_id, f_id, ul_carrier_id, prach_ConfigIndex, SFN_nbr, Msg3_size; AssertFatal(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id); @@ -344,14 +344,15 @@ uint8_t nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id); uint8_t mac_sdus[MAX_NR_ULSCH_PAYLOAD_BYTES]; - uint8_t lcid = UL_SCH_LCID_CCCH_MSG3, *payload, ra_ResponseWindow; + uint8_t lcid = UL_SCH_LCID_CCCH_MSG3, *payload; + //uint8_t ra_ResponseWindow; uint16_t size_sdu = 0; unsigned short post_padding; - fapi_nr_config_request_t *cfg = &mac->phy_config.config_req; + //fapi_nr_config_request_t *cfg = &mac->phy_config.config_req; NR_ServingCellConfigCommon_t *scc = mac->scc; NR_RACH_ConfigCommon_t *setup = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup; NR_RACH_ConfigGeneric_t *rach_ConfigGeneric = &setup->rach_ConfigGeneric; - NR_FrequencyInfoDL_t *frequencyInfoDL = scc->downlinkConfigCommon->frequencyInfoDL; + //NR_FrequencyInfoDL_t *frequencyInfoDL = scc->downlinkConfigCommon->frequencyInfoDL; NR_RACH_ConfigDedicated_t *rach_ConfigDedicated = mac->rach_ConfigDedicated; // int32_t frame_diff = 0; diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c index 8c7be8f725..a98a2b1211 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c @@ -157,7 +157,7 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl if (mac->crnti > 0) { NR_SearchSpace_t *css; - NR_SearchSpace_t *uss; + NR_SearchSpace_t *uss = NULL; NR_ServingCellConfigCommon_t *scc; NR_SearchSpaceId_t ra_SearchSpaceId; rel15 = &dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15; diff --git a/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c b/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c index e9d3f8c327..bfd2d3dbeb 100644 --- a/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c +++ b/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c @@ -105,7 +105,7 @@ uint16_t nr_ue_process_rar(module_id_t mod_id, NR_MAC_RAR *rar = (NR_MAC_RAR *) (dlsch_buffer + 1); // RAR subPDU pointer uint8_t n_subPDUs = 0; // number of RAR payloads uint8_t n_subheaders = 0; // number of MAC RAR subheaders - uint8_t best_rx_rapid = -1; // the closest RAPID receive from all RARs + //uint8_t best_rx_rapid = -1; // the closest RAPID receive from all RARs unsigned char freq_hopping, msg3_t_alloc, mcs, tpc_command, csi_req; uint16_t ta_command = 0, msg3_f_alloc, bwp_size; int f_alloc, mask; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index ba45def3f5..6ce72059fd 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -219,7 +219,7 @@ void nr_schedule_msg2(uint16_t rach_frame, uint16_t rach_slot, // slot and frame limit to transmit msg2 according to response window uint8_t slot_limit = (rach_slot + slot_window)%nr_slots_per_frame[mu]; - uint8_t frame_limit = (slot_limit>(rach_slot))? rach_frame : (rach_frame +1); + //uint8_t frame_limit = (slot_limit>(rach_slot))? rach_frame : (rach_frame +1); // go to previous slot if the current scheduled slot is beyond the response window // and if the slot is not among the PDCCH monitored ones (38.213 10.1) @@ -762,7 +762,8 @@ void nr_fill_rar(uint8_t Mod_idP, NR_RA_HEADER_RAPID *rarh = (NR_RA_HEADER_RAPID *) dlsch_buffer; NR_MAC_RAR *rar = (NR_MAC_RAR *) (dlsch_buffer + 1); unsigned char csi_req = 0, tpc_command; - uint8_t N_UL_Hop, valid_bits; + //uint8_t N_UL_Hop; + uint8_t valid_bits; uint32_t ul_grant; uint16_t f_alloc, prb_alloc, bwp_size, truncation=0; diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c index 6773c3ee1c..43f43922a8 100644 --- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c @@ -118,7 +118,7 @@ int nr_ue_ul_indication(nr_uplink_indication_t *ul_info){ if (is_nr_UL_slot(mac->scc, ul_info->slot_tx) && get_softmodem_params()->do_ra){ nr_ue_prach_scheduler(module_id, ul_info->frame_tx, ul_info->slot_tx); if (mac->generate_nr_prach){ - uint16_t monitoring_slot_period, monitoring_offset; + //uint16_t monitoring_slot_period, monitoring_offset; uint16_t rach_frame = mac->scheduled_response.ul_config->sfn; uint16_t rx_rach_frame = (rach_frame + mac->RA_offset) % MAX_FRAME_NUMBER; // compensate 2 frames offset delay at gNB side uint16_t rach_slot = mac->scheduled_response.ul_config->slot; @@ -244,8 +244,8 @@ int nr_ue_dl_indication(nr_downlink_indication_t *dl_info, NR_UL_TIME_ALIGNMENT_ dl_info->rx_ind = NULL; dl_info->dci_ind = NULL; - return 0; } + return 0; } nr_ue_if_module_t *nr_ue_if_module_init(uint32_t module_id){ diff --git a/openair3/GTPV1-U/gtpv1u_gNB.c b/openair3/GTPV1-U/gtpv1u_gNB.c index 1a75214d65..f13bf13794 100644 --- a/openair3/GTPV1-U/gtpv1u_gNB.c +++ b/openair3/GTPV1-U/gtpv1u_gNB.c @@ -129,14 +129,14 @@ NwGtpv1uRcT gtpv1u_gNB_process_stack_req( case NW_GTPV1U_ULP_API_RECV_TPDU: { uint8_t buffer[4096]; uint32_t buffer_len; - uint16_t msgType = NW_GTP_GPDU; - NwGtpv1uMsgT *pMsg = NULL; + //uint16_t msgType = NW_GTP_GPDU; + //NwGtpv1uMsgT *pMsg = NULL; /* Nw-gptv1u stack has processed a PDU. we can schedule it to PDCP * for transmission. */ teid = pUlpApi->apiInfo.recvMsgInfo.teid; - pMsg = (NwGtpv1uMsgT *) pUlpApi->apiInfo.recvMsgInfo.hMsg; - msgType = pMsg->msgType; + //pMsg = (NwGtpv1uMsgT *) pUlpApi->apiInfo.recvMsgInfo.hMsg; + //msgType = pMsg->msgType; if (NW_GTPV1U_OK != nwGtpv1uMsgGetTpdu(pUlpApi->apiInfo.recvMsgInfo.hMsg, buffer, &buffer_len)) { diff --git a/openair3/S1AP/s1ap_eNB_nas_procedures.c b/openair3/S1AP/s1ap_eNB_nas_procedures.c index b8a4b98fef..c668e32d1b 100644 --- a/openair3/S1AP/s1ap_eNB_nas_procedures.c +++ b/openair3/S1AP/s1ap_eNB_nas_procedures.c @@ -1791,8 +1791,8 @@ int s1ap_eNB_generate_E_RAB_Modification_Indication( S1AP_E_RABToBeModifiedItemBearerModInd_t *E_RAB_ToBeModifiedItem_BearerModInd = NULL; S1AP_E_RABToBeModifiedItemBearerModIndIEs_t *E_RAB_ToBeModifiedItem_BearerModInd_IEs = NULL; - S1AP_E_RABNotToBeModifiedItemBearerModInd_t *E_RAB_NotToBeModifiedItem_BearerModInd = NULL; - S1AP_E_RABNotToBeModifiedItemBearerModIndIEs_t *E_RAB_NotToBeModifiedItem_BearerModInd_IEs = NULL; + //S1AP_E_RABNotToBeModifiedItemBearerModInd_t *E_RAB_NotToBeModifiedItem_BearerModInd = NULL; + //S1AP_E_RABNotToBeModifiedItemBearerModIndIEs_t *E_RAB_NotToBeModifiedItem_BearerModInd_IEs = NULL; s1ap_eNB_instance_t *s1ap_eNB_instance_p = NULL; @@ -1804,10 +1804,10 @@ int s1ap_eNB_generate_E_RAB_Modification_Indication( DevAssert(e_rab_modification_ind != NULL); int num_e_rabs_tobemodified = e_rab_modification_ind->nb_of_e_rabs_tobemodified; - int num_e_rabs_nottobemodified = e_rab_modification_ind->nb_of_e_rabs_nottobemodified; + //int num_e_rabs_nottobemodified = e_rab_modification_ind->nb_of_e_rabs_nottobemodified; - uint32_t CSG_id = 0; - uint32_t pseudo_gtp_teid = 10; + //uint32_t CSG_id = 0; + //uint32_t pseudo_gtp_teid = 10; if ((ue_context_p = s1ap_eNB_get_ue_context(s1ap_eNB_instance_p, e_rab_modification_ind->eNB_ue_s1ap_id)) == NULL) { From 9c4bb6bf4b56a7f8b0e333e66ffc66467e3358cf Mon Sep 17 00:00:00 2001 From: matzakos Date: Fri, 19 Jun 2020 13:01:50 +0200 Subject: [PATCH 345/553] Fix DLSCH PDU corruption issue for phytest mode (random traffic generation) - Payload was filled with zeros instead of random bytes --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 7cf3920d81..8bbb99c3ae 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -623,8 +623,8 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, // fill dlsch_buffer with random data for (i = 0; i < TBS_bytes; i++){ - //mac_sdus[i] = (unsigned char) rand(); - ((uint8_t *)gNB_mac->UE_list.DLSCH_pdu[0][0].payload[0])[i] = (unsigned char) (lrand48()&0xff); + mac_sdus[i] = (unsigned char) (lrand48()&0xff); + //((uint8_t *)gNB_mac->UE_list.DLSCH_pdu[0][0].payload[0])[i] = (unsigned char) (lrand48()&0xff); } //Sending SDUs with size 1 //Initialize elements of sdu_lcids and sdu_lengths @@ -662,7 +662,7 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, offset = nr_generate_dlsch_pdu(module_idP, (unsigned char *) mac_sdus, - (unsigned char *) gNB_mac->UE_list.DLSCH_pdu[0][0].payload[0], //(unsigned char *) mac_pdu, + (unsigned char *) gNB_mac->UE_list.DLSCH_pdu[0][0].payload[0], num_sdus, //num_sdus sdu_lengths, sdu_lcids, From dcadc24ad6cd8b54261fe970ee8b472503fc939f Mon Sep 17 00:00:00 2001 From: hardy Date: Wed, 17 Jun 2020 11:58:54 +0200 Subject: [PATCH 346/553] complete and working version supporting phy-simulators --- ci-scripts/cls_physim.py | 155 ++++++++++++++++++++++ ci-scripts/main.py | 25 +++- ci-scripts/xml_files/rh_ldpc_gpu_test.xml | 50 +++++++ 3 files changed, 229 insertions(+), 1 deletion(-) create mode 100644 ci-scripts/cls_physim.py create mode 100644 ci-scripts/xml_files/rh_ldpc_gpu_test.xml diff --git a/ci-scripts/cls_physim.py b/ci-scripts/cls_physim.py new file mode 100644 index 0000000000..c06c818327 --- /dev/null +++ b/ci-scripts/cls_physim.py @@ -0,0 +1,155 @@ +# * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more +# * contributor license agreements. See the NOTICE file distributed with +# * this work for additional information regarding copyright ownership. +# * The OpenAirInterface Software Alliance licenses this file to You under +# * the OAI Public License, Version 1.1 (the "License"); you may not use this file +# * except in compliance with the License. +# * You may obtain a copy of the License at +# * +# * http://www.openairinterface.org/?page_id=698 +# * +# * Unless required by applicable law or agreed to in writing, software +# * distributed under the License is distributed on an "AS IS" BASIS, +# * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# * See the License for the specific language governing permissions and +# * limitations under the License. +# *------------------------------------------------------------------------------- +# * For more information about the OpenAirInterface (OAI) Software Alliance: +# * contact@openairinterface.org +# */ +#--------------------------------------------------------------------- +# Python for CI of OAI-eNB + COTS-UE +# +# Required Python Version +# Python 3.x +# +# Required Python Package +# pexpect +#--------------------------------------------------------------------- + +#to create a SSH object locally in the methods +import sshconnection +#to update the HTML object +import html +from multiprocessing import SimpleQueue + + +class PhySim: + def __init__(self): + self.buildargs = "" + self.runargs = "" + self.eNBIpAddr = "" + self.eNBUserName = "" + self.eNBPassWord = "" + self.eNBSourceCodePath = "" + self.ranRepository = "" + self.ranBranch = "" + self.ranCommitID= "" + self.ranAllowMerge= "" + self.ranTargetBranch= "" + self.exitStatus=0 + self.workSpacePath='' + self.buildLogFile='compile_oai_enb.log' + self.runLogFile='ldpctest_run_results.log' + self.runResults=[] + + def __CheckResults_PhySim(self,HTML,CONST): + mySSH = sshconnection.SSHConnection() + mySSH.open(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord) + #retrieve run log file locally$ + mySSH.copyin(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord, self.workSpacePath+self.runLogFile, '.') + mySSH.close() + with open(self.runLogFile) as f: + for line in f: + if 'mean' in line: + self.runResults.append(line) + info=self.runResults[-1]+self.runResults[-2] + + html_cell = '
' + info  + '
' + html_queue=SimpleQueue() + html_queue.put(html_cell) + HTML.CreateHtmlTestRowQueue(self.runargs, 'OK', 1, html_queue) + return HTML + + + def __CheckBuild_PhySim(self, HTML, CONST): + self.workSpacePath=self.eNBSourceCodePath+'/cmake_targets/' + mySSH = sshconnection.SSHConnection() + mySSH.open(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord) + #retrieve compile log file locally + mySSH.copyin(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord, self.workSpacePath+self.buildLogFile, '.') + #delete older run log file + mySSH.command('rm ' + self.workSpacePath+self.runLogFile, '\$', 5) + mySSH.close() + #check build result from local compile log file + buildStatus=False + with open(self.buildLogFile) as f: + if 'nr_prachsim compiled' in f.read(): + buildStatus=True + #update HTML based on build status + if buildStatus: + HTML.CreateHtmlTestRow(self.buildargs, 'OK', CONST.ALL_PROCESSES_OK, 'LDPC') + self.exitStatus=0 + else: + logging.error('\u001B[1m Building OAI UE Failed\u001B[0m') + HTML.CreateHtmlTestRow(self.buildargs, 'KO', CONST.ALL_PROCESSES_OK, 'LDPC') + HTML.CreateHtmlTabFooter(False) + self.exitStatus=1 + return HTML + + def Build_PhySim(self,htmlObj,constObj): + mySSH = sshconnection.SSHConnection() + mySSH.open(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord) + + #create working dir + mySSH.command('mkdir -p ' + self.eNBSourceCodePath, '\$', 5) + mySSH.command('cd ' + self.eNBSourceCodePath, '\$', 5) + + if not self.ranRepository.lower().endswith('.git'): + self.ranRepository+='.git' + + #git clone + mySSH.command('if [ ! -e .git ]; then stdbuf -o0 git clone ' + self.ranRepository + ' .; else stdbuf -o0 git fetch --prune; fi', '\$', 600) + #git config + mySSH.command('git config user.email "jenkins@openairinterface.org"', '\$', 5) + mySSH.command('git config user.name "OAI Jenkins"', '\$', 5) + + #git clean + mySSH.command('echo ' + self.eNBPassWord + ' | sudo -S git clean -x -d -ff', '\$', 30) + + # if the commit ID is provided, use it to point to it + if self.ranCommitID != '': + mySSH.command('git checkout -f ' + self.ranCommitID, '\$', 5) + # if the branch is not develop, then it is a merge request and we need to do + # the potential merge. Note that merge conflicts should have already been checked earlier + if (self.ranAllowMerge): + if self.ranTargetBranch == '': + if (self.ranBranch != 'develop') and (self.ranBranch != 'origin/develop'): + mySSH.command('git merge --ff origin/develop -m "Temporary merge for CI"', '\$', 5) + else: + print('Merging with the target branch: ' + self.ranTargetBranch) + mySSH.command('git merge --ff origin/' + self.ranTargetBranch + ' -m "Temporary merge for CI"', '\$', 5) + + #build + mySSH.command('source oaienv', '\$', 5) + mySSH.command('cd cmake_targets', '\$', 5) + mySSH.command('mkdir -p log', '\$', 5) + mySSH.command('chmod 777 log', '\$', 5) + mySSH.command('stdbuf -o0 ./build_oai ' + self.buildargs + ' 2>&1 | stdbuf -o0 tee compile_oai_enb.log', 'Bypassing the Tests|build have failed', 1500) + + mySSH.close() + #check build status and update HTML object + lHTML = html.HTMLManagement() + lHTML=self.__CheckBuild_PhySim(htmlObj,constObj) + return lHTML + + + def Run_PhySim(self,htmlObj,constObj): + mySSH = sshconnection.SSHConnection() + mySSH.open(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord) + mySSH.command('cd '+self.workSpacePath,'\$',5) + mySSH.command(self.workSpacePath+'phy_simulators/build/ldpctest ' + self.runargs + ' >> '+self.runLogFile, '\$', 30) + mySSH.close() + lHTML = html.HTMLManagement() + lHTML=self.__CheckResults_PhySim(htmlObj,constObj) + return lHTML diff --git a/ci-scripts/main.py b/ci-scripts/main.py index e9313051fc..164b4fc6af 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -30,6 +30,7 @@ import constants as CONST + #----------------------------------------------------------- # Import #----------------------------------------------------------- @@ -3061,7 +3062,7 @@ class OaiCiTest(): logging.debug('\u001B[1m----------------------------------------\u001B[0m') def CheckClassValidity(action,id): - if action != 'Build_eNB' and action != 'WaitEndBuild_eNB' and action != 'Initialize_eNB' and action != 'Terminate_eNB' and action != 'Initialize_UE' and action != 'Terminate_UE' and action != 'Attach_UE' and action != 'Detach_UE' and action != 'Build_OAI_UE' and action != 'Initialize_OAI_UE' and action != 'Terminate_OAI_UE' and action != 'DataDisable_UE' and action != 'DataEnable_UE' and action != 'CheckStatusUE' and action != 'Ping' and action != 'Iperf' and action != 'Reboot_UE' and action != 'Initialize_FlexranCtrl' and action != 'Terminate_FlexranCtrl' and action != 'Initialize_HSS' and action != 'Terminate_HSS' and action != 'Initialize_MME' and action != 'Terminate_MME' and action != 'Initialize_SPGW' and action != 'Terminate_SPGW' and action != 'Initialize_CatM_module' and action != 'Terminate_CatM_module' and action != 'Attach_CatM_module' and action != 'Detach_CatM_module' and action != 'Ping_CatM_module' and action != 'IdleSleep' and action != 'Perform_X2_Handover': + if action!='Build_PhySim' and action!='Run_PhySim' and action != 'Build_eNB' and action != 'WaitEndBuild_eNB' and action != 'Initialize_eNB' and action != 'Terminate_eNB' and action != 'Initialize_UE' and action != 'Terminate_UE' and action != 'Attach_UE' and action != 'Detach_UE' and action != 'Build_OAI_UE' and action != 'Initialize_OAI_UE' and action != 'Terminate_OAI_UE' and action != 'DataDisable_UE' and action != 'DataEnable_UE' and action != 'CheckStatusUE' and action != 'Ping' and action != 'Iperf' and action != 'Reboot_UE' and action != 'Initialize_FlexranCtrl' and action != 'Terminate_FlexranCtrl' and action != 'Initialize_HSS' and action != 'Terminate_HSS' and action != 'Initialize_MME' and action != 'Terminate_MME' and action != 'Initialize_SPGW' and action != 'Terminate_SPGW' and action != 'Initialize_CatM_module' and action != 'Terminate_CatM_module' and action != 'Attach_CatM_module' and action != 'Detach_CatM_module' and action != 'Ping_CatM_module' and action != 'IdleSleep' and action != 'Perform_X2_Handover': logging.debug('ERROR: test-case ' + id + ' has wrong class ' + action) return False return True @@ -3208,6 +3209,11 @@ def GetParametersFromXML(action): else: CiTestObj.x2_ho_options = string_field + if action == 'Build_PhySim': + ldpc.buildargs = test.findtext('physim_build_args') + + if action == 'Run_PhySim': + ldpc.runargs = test.findtext('physim_run_args') #check if given test is in list #it is in list if one of the strings in 'list' is at the beginning of 'test' @@ -3243,6 +3249,9 @@ EPC.SetHtmlObj(HTML) RAN.SetHtmlObj(HTML) RAN.SetEpcObj(EPC) +import cls_physim #class PhySim for physical simulators build and test +ldpc=cls_physim.PhySim() #create an instance for LDPC test using GPU or CPU build + argvs = sys.argv argc = len(argvs) cwd = os.getcwd() @@ -3264,12 +3273,14 @@ while len(argvs) > 1: CiTestObj.ranRepository = matchReg.group(1) RAN.SetranRepository(matchReg.group(1)) HTML.SetranRepository(matchReg.group(1)) + ldpc.ranRepository=matchReg.group(1) elif re.match('^\-\-eNB_AllowMerge=(.+)$|^\-\-ranAllowMerge=(.+)$', myArgv, re.IGNORECASE): if re.match('^\-\-eNB_AllowMerge=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB_AllowMerge=(.+)$', myArgv, re.IGNORECASE) else: matchReg = re.match('^\-\-ranAllowMerge=(.+)$', myArgv, re.IGNORECASE) doMerge = matchReg.group(1) + ldpc.ranAllowMerge=matchReg.group(1) if ((doMerge == 'true') or (doMerge == 'True')): CiTestObj.ranAllowMerge = True RAN.SetranAllowMerge(True) @@ -3282,6 +3293,7 @@ while len(argvs) > 1: CiTestObj.ranBranch = matchReg.group(1) RAN.SetranBranch(matchReg.group(1)) HTML.SetranBranch(matchReg.group(1)) + ldpc.ranBranch=matchReg.group(1) elif re.match('^\-\-eNBCommitID=(.*)$|^\-\-ranCommitID=(.*)$', myArgv, re.IGNORECASE): if re.match('^\-\-eNBCommitID=(.*)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNBCommitID=(.*)$', myArgv, re.IGNORECASE) @@ -3290,6 +3302,7 @@ while len(argvs) > 1: CiTestObj.ranCommitID = matchReg.group(1) RAN.SetranCommitID(matchReg.group(1)) HTML.SetranCommitID(matchReg.group(1)) + ldpc.ranCommitID=matchReg.group(1) elif re.match('^\-\-eNBTargetBranch=(.*)$|^\-\-ranTargetBranch=(.*)$', myArgv, re.IGNORECASE): if re.match('^\-\-eNBTargetBranch=(.*)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNBTargetBranch=(.*)$', myArgv, re.IGNORECASE) @@ -3298,10 +3311,12 @@ while len(argvs) > 1: CiTestObj.ranTargetBranch = matchReg.group(1) RAN.SetranTargetBranch(matchReg.group(1)) HTML.SetranTargetBranch(matchReg.group(1)) + ldpc.ranTargetBranch=matchReg.group(1) elif re.match('^\-\-eNBIPAddress=(.+)$|^\-\-eNB[1-2]IPAddress=(.+)$', myArgv, re.IGNORECASE): if re.match('^\-\-eNBIPAddress=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNBIPAddress=(.+)$', myArgv, re.IGNORECASE) RAN.SeteNBIPAddress(matchReg.group(1)) + ldpc.eNBIpAddr=matchReg.group(1) elif re.match('^\-\-eNB1IPAddress=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB1IPAddress=(.+)$', myArgv, re.IGNORECASE) RAN.SeteNB1IPAddress(matchReg.group(1)) @@ -3312,6 +3327,7 @@ while len(argvs) > 1: if re.match('^\-\-eNBUserName=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNBUserName=(.+)$', myArgv, re.IGNORECASE) RAN.SeteNBUserName(matchReg.group(1)) + ldpc.eNBUserName=matchReg.group(1) elif re.match('^\-\-eNB1UserName=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB1UserName=(.+)$', myArgv, re.IGNORECASE) RAN.SeteNB1UserName(matchReg.group(1)) @@ -3322,6 +3338,7 @@ while len(argvs) > 1: if re.match('^\-\-eNBPassword=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNBPassword=(.+)$', myArgv, re.IGNORECASE) RAN.SeteNBPassword(matchReg.group(1)) + ldpc.eNBPassWord=matchReg.group(1) elif re.match('^\-\-eNB1Password=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB1Password=(.+)$', myArgv, re.IGNORECASE) RAN.SeteNB1Password(matchReg.group(1)) @@ -3332,6 +3349,7 @@ while len(argvs) > 1: if re.match('^\-\-eNBSourceCodePath=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNBSourceCodePath=(.+)$', myArgv, re.IGNORECASE) RAN.SeteNBSourceCodePath(matchReg.group(1)) + ldpc.eNBSourceCodePath=matchReg.group(1) elif re.match('^\-\-eNB1SourceCodePath=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB1SourceCodePath=(.+)$', myArgv, re.IGNORECASE) RAN.SeteNB1SourceCodePath(matchReg.group(1)) @@ -3702,6 +3720,11 @@ elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re CiTestObj.IdleSleep() elif action == 'Perform_X2_Handover': CiTestObj.Perform_X2_Handover() + elif action == 'Build_PhySim': + HTML=ldpc.Build_PhySim(HTML,CONST) + if ldpc.exitStatus==1:sys.exit() + elif action == 'Run_PhySim': + ldpc.Run_PhySim(HTML,CONST) else: sys.exit('Invalid action') CiTestObj.FailReportCnt += 1 diff --git a/ci-scripts/xml_files/rh_ldpc_gpu_test.xml b/ci-scripts/xml_files/rh_ldpc_gpu_test.xml new file mode 100644 index 0000000000..6df90915d3 --- /dev/null +++ b/ci-scripts/xml_files/rh_ldpc_gpu_test.xml @@ -0,0 +1,50 @@ + + + test-ldpc-gpu + Test-ldpc-GPU + tasks + 1 + 000001 000002 000003 + + + + Build_PhySim + Build for physical simulator + --phy_simulators + + + + Run_PhySim + Run LDPC Test with CPU + -l 8448 -s10 -n100 + + + + Run_PhySim + Run LDPC Test with GPU + -l 8448 -s10 -n100 -G 1 + + + From a9dbcf6b93477c1474c4694deb6ebd0fad9ddf1d Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Fri, 19 Jun 2020 14:18:13 +0200 Subject: [PATCH 347/553] added in-code comments and changed attr to private --- ci-scripts/cls_physim.py | 51 +++++++++++++++++++++++++++------------- 1 file changed, 35 insertions(+), 16 deletions(-) diff --git a/ci-scripts/cls_physim.py b/ci-scripts/cls_physim.py index c06c818327..baf8144f88 100644 --- a/ci-scripts/cls_physim.py +++ b/ci-scripts/cls_physim.py @@ -48,23 +48,32 @@ class PhySim: self.ranAllowMerge= "" self.ranTargetBranch= "" self.exitStatus=0 - self.workSpacePath='' - self.buildLogFile='compile_oai_enb.log' - self.runLogFile='ldpctest_run_results.log' - self.runResults=[] + #private attributes + self.__workSpacePath='' + self.__buildLogFile='compile_oai_enb.log' + self.__runLogFile='ldpctest_run_results.log' + self.__runResults=[] + + +#----------------- +#PRIVATE Methods +#----------------- def __CheckResults_PhySim(self,HTML,CONST): mySSH = sshconnection.SSHConnection() mySSH.open(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord) - #retrieve run log file locally$ - mySSH.copyin(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord, self.workSpacePath+self.runLogFile, '.') + #retrieve run log file and store it locally$ + mySSH.copyin(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord, self.__workSpacePath+self.__runLogFile, '.') mySSH.close() - with open(self.runLogFile) as f: + #parse results looking for Encoding and Decoding mean values + with open(self.__runLogFile) as f: for line in f: if 'mean' in line: - self.runResults.append(line) - info=self.runResults[-1]+self.runResults[-2] + self.__runResults.append(line) + #the value are appended for each test, so we take the last 2 values from the list + info=self.__runResults[-1]+self.__runResults[-2] + #updating the HTML with results html_cell = '
' + info  + '
' html_queue=SimpleQueue() html_queue.put(html_cell) @@ -73,17 +82,18 @@ class PhySim: def __CheckBuild_PhySim(self, HTML, CONST): - self.workSpacePath=self.eNBSourceCodePath+'/cmake_targets/' + self.__workSpacePath=self.eNBSourceCodePath+'/cmake_targets/' mySSH = sshconnection.SSHConnection() mySSH.open(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord) - #retrieve compile log file locally - mySSH.copyin(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord, self.workSpacePath+self.buildLogFile, '.') + #retrieve compile log file and store it locally + mySSH.copyin(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord, self.__workSpacePath+self.__buildLogFile, '.') #delete older run log file - mySSH.command('rm ' + self.workSpacePath+self.runLogFile, '\$', 5) + mySSH.command('rm ' + self.__workSpacePath+self.__runLogFile, '\$', 5) mySSH.close() #check build result from local compile log file buildStatus=False - with open(self.buildLogFile) as f: + with open(self.__buildLogFile) as f: + #nr_prachsim is the last compile step if 'nr_prachsim compiled' in f.read(): buildStatus=True #update HTML based on build status @@ -94,9 +104,15 @@ class PhySim: logging.error('\u001B[1m Building OAI UE Failed\u001B[0m') HTML.CreateHtmlTestRow(self.buildargs, 'KO', CONST.ALL_PROCESSES_OK, 'LDPC') HTML.CreateHtmlTabFooter(False) + #exitStatus=1 will do a sys.exit in main self.exitStatus=1 return HTML + +#-----------------$ +#PUBLIC Methods$ +#-----------------$ + def Build_PhySim(self,htmlObj,constObj): mySSH = sshconnection.SSHConnection() mySSH.open(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord) @@ -145,11 +161,14 @@ class PhySim: def Run_PhySim(self,htmlObj,constObj): + #open a session for test run mySSH = sshconnection.SSHConnection() mySSH.open(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord) - mySSH.command('cd '+self.workSpacePath,'\$',5) - mySSH.command(self.workSpacePath+'phy_simulators/build/ldpctest ' + self.runargs + ' >> '+self.runLogFile, '\$', 30) + mySSH.command('cd '+self.__workSpacePath,'\$',5) + #run and redirect the results to a log file + mySSH.command(self.__workSpacePath+'phy_simulators/build/ldpctest ' + self.runargs + ' >> '+self.__runLogFile, '\$', 30) mySSH.close() + #return updated HTML to main lHTML = html.HTMLManagement() lHTML=self.__CheckResults_PhySim(htmlObj,constObj) return lHTML From 0354a7399b57241060c517e586cf55ee07df9f17 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 19 Jun 2020 14:32:26 +0200 Subject: [PATCH 348/553] bugfix nr_ulsch_ue.c --- openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c index d296573971..35841d7fda 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c @@ -433,7 +433,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, ptrs_idx++; - } else if (allowed_ulsch_re_in_dmrs_symbol(k,start_sc,harq_process_ul_ue->pusch_pdu.num_dmrs_cdm_grps_no_data,dmrs_type)) { + } else if (!is_dmrs || allowed_ulsch_re_in_dmrs_symbol(k,start_sc,harq_process_ul_ue->pusch_pdu.num_dmrs_cdm_grps_no_data,dmrs_type)) { ((int16_t*)txdataF[ap])[(sample_offsetF)<<1] = ((int16_t *) ulsch_ue->y)[m<<1]; ((int16_t*)txdataF[ap])[((sample_offsetF)<<1) + 1] = ((int16_t *) ulsch_ue->y)[(m<<1) + 1]; From 9411438dd0e10e9cdfa1512c625bd45065f1efed Mon Sep 17 00:00:00 2001 From: Florian Kaltenberger Date: Fri, 19 Jun 2020 15:00:00 +0200 Subject: [PATCH 349/553] small fix --- openair1/PHY/TOOLS/nr_phy_scope.c | 1 + 1 file changed, 1 insertion(+) diff --git a/openair1/PHY/TOOLS/nr_phy_scope.c b/openair1/PHY/TOOLS/nr_phy_scope.c index 61a38098a6..6480535b21 100644 --- a/openair1/PHY/TOOLS/nr_phy_scope.c +++ b/openair1/PHY/TOOLS/nr_phy_scope.c @@ -162,6 +162,7 @@ static void timeSignal (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_ if (rxsig_t[arx] != NULL) { for (int i=0; isamples_per_frame; i++) { rxsig_t_dB[i] = 10*log10(1.0+SquaredNorm(rxsig_t[arx][i])); + time[i] = i; } if (arx==0) From e189e06a16ddc372d3f61427228003d40dc08199 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 19 Jun 2020 15:25:28 +0200 Subject: [PATCH 350/553] Yet another bugfix in nr_ulsch_ue.c --- openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c index 35841d7fda..77b2d84871 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c @@ -366,7 +366,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, uint8_t k_prime=0; - uint8_t is_dmrs, is_ptrs; + uint8_t is_dmrs, is_ptrs, is_dmrs_symbol; uint16_t m=0, n=0, dmrs_idx=0, ptrs_idx = 0; for (l=start_symbol; l> l) & 0x01) { + is_dmrs_symbol = 1; if (k == ((start_sc+get_dmrs_freq_idx_ul(n, k_prime, delta, dmrs_type))%frame_parms->ofdm_symbol_size)) is_dmrs = 1; } @@ -433,7 +435,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, ptrs_idx++; - } else if (!is_dmrs || allowed_ulsch_re_in_dmrs_symbol(k,start_sc,harq_process_ul_ue->pusch_pdu.num_dmrs_cdm_grps_no_data,dmrs_type)) { + } else if (!is_dmrs_symbol || allowed_ulsch_re_in_dmrs_symbol(k,start_sc,harq_process_ul_ue->pusch_pdu.num_dmrs_cdm_grps_no_data,dmrs_type)) { ((int16_t*)txdataF[ap])[(sample_offsetF)<<1] = ((int16_t *) ulsch_ue->y)[m<<1]; ((int16_t*)txdataF[ap])[((sample_offsetF)<<1) + 1] = ((int16_t *) ulsch_ue->y)[(m<<1) + 1]; From 8a3feeb5f68c9e1a826400d37503c3509502f6e9 Mon Sep 17 00:00:00 2001 From: Florian Kaltenberger Date: Fri, 19 Jun 2020 16:11:19 +0200 Subject: [PATCH 351/553] fix from Walter Maguire --- openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c b/openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c index 60306d8e53..612dc6283d 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c @@ -505,7 +505,7 @@ int nr_rx_pbch( PHY_VARS_NR_UE *ue, return(-1); } */ - if (symbol==1) { + if (symbol==2) { nr_pbch_quantize(pbch_e_rx, (short *)&(nr_ue_pbch_vars->rxdataF_comp[0][symbol*240]), 144); From 2e9cd58d483b19b90783a8181f9d33438527fe1d Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Fri, 19 Jun 2020 17:18:15 +0200 Subject: [PATCH 352/553] nb_re_dmrs fixed in one more place this fixed dlsch crc fails --- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 6 +++--- openair1/SIMULATION/NR_PHY/dlsim.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 0e19f2ed90..cca7d0cfbb 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -3287,9 +3287,9 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, NR_UE_PDSCH *pdsch_vars; uint8_t is_cw0_active = 0; uint8_t is_cw1_active = 0; - //nfapi_nr_config_request_t *cfg = &ue->nrUE_config; - //uint8_t dmrs_type = cfg->pdsch_config.dmrs_type.value; - uint8_t nb_re_dmrs = 12; //(dmrs_type==NFAPI_NR_DMRS_TYPE1)?6:4; + nfapi_nr_config_request_t *cfg = &ue->nrUE_config; + uint8_t dmrs_type = cfg->pdsch_config.PDSCHTimeDomainResourceAllocation_mappingType[0].value; // TODO: HARDCODED pdsch index + uint8_t nb_re_dmrs = (dmrs_type==NFAPI_NR_DMRS_TYPE1)?6:4; // TODO: should changed my mac uint16_t length_dmrs = 1; //cfg->pdsch_config.dmrs_max_length.value; uint16_t nb_symb_sch = 9; nr_downlink_indication_t dl_indication; diff --git a/openair1/SIMULATION/NR_PHY/dlsim.c b/openair1/SIMULATION/NR_PHY/dlsim.c index 7c1285491c..b8229e3712 100644 --- a/openair1/SIMULATION/NR_PHY/dlsim.c +++ b/openair1/SIMULATION/NR_PHY/dlsim.c @@ -866,7 +866,7 @@ int main(int argc, char **argv) NR_UE_PDSCH **pdsch_vars = UE->pdsch_vars[UE->current_thread_id[UE_proc.nr_tti_rx]]; int16_t *UE_llr = pdsch_vars[0]->llr[0]; - TBS = rel15->TBSize[0]; + TBS = UE_harq_process->TBS;//rel15->TBSize[0]; uint16_t length_dmrs = 1; uint16_t nb_rb = rel15->rbSize; uint8_t nb_re_dmrs = rel15->dmrsConfigType == NFAPI_NR_DMRS_TYPE1 ? 6 : 4; From 94fa9c5f1f576b2e624f196709deaed0d90581da Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 19 Jun 2020 18:16:53 +0200 Subject: [PATCH 353/553] fix in function to check data in dmrs symbol --- openair1/PHY/NR_REFSIG/dmrs_nr.c | 27 ++++++++++++++++++++++ openair1/PHY/NR_REFSIG/dmrs_nr.h | 5 ++++ openair1/PHY/NR_TRANSPORT/nr_dlsch.c | 3 ++- openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.c | 21 ----------------- openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.h | 5 ---- openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c | 23 +----------------- 6 files changed, 35 insertions(+), 49 deletions(-) diff --git a/openair1/PHY/NR_REFSIG/dmrs_nr.c b/openair1/PHY/NR_REFSIG/dmrs_nr.c index dd2f32dfff..7042c152fd 100644 --- a/openair1/PHY/NR_REFSIG/dmrs_nr.c +++ b/openair1/PHY/NR_REFSIG/dmrs_nr.c @@ -34,6 +34,33 @@ #include "PHY/NR_REFSIG/dmrs_nr.h" + +uint8_t allowed_xlsch_re_in_dmrs_symbol(uint16_t k, + uint16_t start_sc, + uint8_t numDmrsCdmGrpsNoData, + uint8_t dmrs_type) { + uint8_t delta; + uint16_t diff; + if (k>start_sc) + diff = k-start_sc; + else + diff = start_sc-k; + for (int i = 0; inumDmrsCdmGrpsNoData,dmrs_Type)) { + if( (l != dmrs_symbol) || allowed_xlsch_re_in_dmrs_symbol(k,start_sc,rel15->numDmrsCdmGrpsNoData,dmrs_Type)) { ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + (2*txdataF_offset)] = (amp * tx_layers[ap][m<<1]) >> 15; ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + 1 + (2*txdataF_offset)] = (amp * tx_layers[ap][(m<<1) + 1]) >> 15; #ifdef DEBUG_DLSCH_MAPPING diff --git a/openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.c b/openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.c index d74819f87f..04045380eb 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.c +++ b/openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.c @@ -84,27 +84,6 @@ uint16_t get_dmrs_freq_idx(uint16_t n, uint8_t k_prime, uint8_t delta, uint8_t d return dmrs_idx; } - -uint8_t allowed_pdsch_re_in_dmrs_symbol(uint16_t k, - uint16_t start_sc, - uint8_t numDmrsCdmGrpsNoData, - uint8_t dmrs_type) { - uint8_t delta; - for (int i = 0; ipusch_pdu.num_dmrs_cdm_grps_no_data,dmrs_type)) { + } else if (!is_dmrs_symbol || allowed_xlsch_re_in_dmrs_symbol(k,start_sc,harq_process_ul_ue->pusch_pdu.num_dmrs_cdm_grps_no_data,dmrs_type)) { ((int16_t*)txdataF[ap])[(sample_offsetF)<<1] = ((int16_t *) ulsch_ue->y)[m<<1]; ((int16_t*)txdataF[ap])[((sample_offsetF)<<1) + 1] = ((int16_t *) ulsch_ue->y)[(m<<1) + 1]; @@ -473,27 +473,6 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, } -uint8_t allowed_ulsch_re_in_dmrs_symbol(uint16_t k, - uint16_t start_sc, - uint8_t numDmrsCdmGrpsNoData, - uint8_t dmrs_type) { - uint8_t delta; - for (int i = 0; i Date: Fri, 19 Jun 2020 13:01:50 +0200 Subject: [PATCH 354/553] Fix DLSCH PDU corruption issue for phytest mode (random traffic generation) - Payload was filled with zeros instead of random bytes --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 406007ef8d..c7538751f4 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -648,8 +648,8 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, // fill dlsch_buffer with random data for (i = 0; i < TBS_bytes; i++){ - //mac_sdus[i] = (unsigned char) rand(); - ((uint8_t *)gNB_mac->UE_list.DLSCH_pdu[0][0].payload[0])[i] = (unsigned char) (lrand48()&0xff); + mac_sdus[i] = (unsigned char) (lrand48()&0xff); + //((uint8_t *)gNB_mac->UE_list.DLSCH_pdu[0][0].payload[0])[i] = (unsigned char) (lrand48()&0xff); } //Sending SDUs with size 1 //Initialize elements of sdu_lcids and sdu_lengths @@ -687,7 +687,7 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, offset = nr_generate_dlsch_pdu(module_idP, (unsigned char *) mac_sdus, - (unsigned char *) gNB_mac->UE_list.DLSCH_pdu[0][0].payload[0], //(unsigned char *) mac_pdu, + (unsigned char *) gNB_mac->UE_list.DLSCH_pdu[0][0].payload[0], num_sdus, //num_sdus sdu_lengths, sdu_lcids, From 75b271a8096d970691f63ce4585be256829fe832 Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Mon, 22 Jun 2020 11:56:55 +0200 Subject: [PATCH 355/553] CI: adding more error messages to HTML report Signed-off-by: Raphael Defosseux --- ci-scripts/ran.py | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/ci-scripts/ran.py b/ci-scripts/ran.py index dd2c291528..9c66b1863c 100644 --- a/ci-scripts/ran.py +++ b/ci-scripts/ran.py @@ -807,6 +807,8 @@ class RANManagement(): uciStatMsgCount = 0 pdcpFailure = 0 ulschFailure = 0 + ulschAllocateCCEerror = 0 + uplinkSegmentsAborted = 0 ulschReceiveOK = 0 gnbRxTxWakeUpFailure = 0 cdrxActivationMessageCount = 0 @@ -925,6 +927,12 @@ class RANManagement(): result = re.search('ULSCH in error in round|ULSCH 0 in error', str(line)) if result is not None: ulschFailure += 1 + result = re.search('ERROR ALLOCATING CCEs', str(line)) + if result is not None: + ulschAllocateCCEerror += 1 + result = re.search('uplink segment error.*aborted [1-9] segments', str(line)) + if result is not None: + uplinkSegmentsAborted += 1 result = re.search('ULSCH received ok', str(line)) if result is not None: ulschReceiveOK += 1 @@ -968,6 +976,14 @@ class RANManagement(): statMsg = nodeB_prefix + 'NB showed ' + str(ulschFailure) + ' "ULSCH in error in round" message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') htmleNBFailureMsg += statMsg + '\n' + if ulschAllocateCCEerror > 0: + statMsg = nodeB_prefix + 'NB showed ' + str(ulschAllocateCCEerror) + ' "eNB_dlsch_ulsch_scheduler(); ERROR ALLOCATING CCEs" message(s)' + logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') + htmleNBFailureMsg += statMsg + '\n' + if uplinkSegmentsAborted > 0: + statMsg = nodeB_prefix + 'NB showed ' + str(uplinkSegmentsAborted) + ' "uplink segment error 0/2, aborted * segments" message(s)' + logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') + htmleNBFailureMsg += statMsg + '\n' if dropNotEnoughRBs > 0: statMsg = 'eNB showed ' + str(dropNotEnoughRBs) + ' "dropping, not enough RBs" message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') From 6d65930fd0723302f43212069e90de7af625afea Mon Sep 17 00:00:00 2001 From: hardy Date: Mon, 22 Jun 2020 12:10:53 +0200 Subject: [PATCH 356/553] initial push to make branch visible --- doc/BUILD.md | 1 - 1 file changed, 1 deletion(-) diff --git a/doc/BUILD.md b/doc/BUILD.md index 9ada32e532..97f9047596 100644 --- a/doc/BUILD.md +++ b/doc/BUILD.md @@ -16,7 +16,6 @@ This page is valid on tags starting from **`2019.w09`**. # Soft Modem Build Script -oai EPC is developed in a distinct project with it's own [documentation](https://github.com/OPENAIRINTERFACE/openair-cn/wiki) , it is not described here. OAI softmodem sources, which aim to implement 3GPP compliant UEs, eNodeB and gNodeB can be downloaded from the Eurecom [gitlab repository](./GET_SOURCES.md). From bc9ee1071c6a6647e69cb7244daf7a51f701bdbe Mon Sep 17 00:00:00 2001 From: hardy Date: Mon, 22 Jun 2020 14:33:42 +0200 Subject: [PATCH 357/553] creation, empty file --- doc/TESTING_GNB_W_COTS_UE.md | 0 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100644 doc/TESTING_GNB_W_COTS_UE.md diff --git a/doc/TESTING_GNB_W_COTS_UE.md b/doc/TESTING_GNB_W_COTS_UE.md new file mode 100644 index 0000000000..e69de29bb2 From 6cb01bd58d6c9185d150567035d8d6d551b3dda2 Mon Sep 17 00:00:00 2001 From: hardy Date: Mon, 22 Jun 2020 15:11:11 +0200 Subject: [PATCH 358/553] folder for .md resources --- doc/testing_gnb_w_cots_ue_resources/oppo.jpg | Bin 0 -> 36458 bytes 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100755 doc/testing_gnb_w_cots_ue_resources/oppo.jpg diff --git a/doc/testing_gnb_w_cots_ue_resources/oppo.jpg b/doc/testing_gnb_w_cots_ue_resources/oppo.jpg new file mode 100755 index 0000000000000000000000000000000000000000..1ff76c0e8264252d8797ccd424d667bbb50b6afa GIT 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zwS>g%V_m>-d)Fwxd-0-*^)T(&@Udxg4Q^QO1YT8YrX#8kpTEqL_%>0=)A{ z8i05dQAk9Gy)q|b)c2x_K#q$~A1eJSJ$6S+AC-vbwG>n>&W?n>47ZC>x-s6boSS+Q zYhFz%#ct#R*$7tP9&!26MGd=|#VZtbFd>A9l~8&p#bR1W=6+c9qKZYG3{JuUgH&$i zlW*QMQ9#UFmtw~!wN?~SK@V|9TCx#w(uygPHGl`DM*R=giYW+4n5@Xka6=3l_fG-L z<`l~wf{H5XnN&Kz5kVB1EYi9IBtt0O*1Y!SN89(0J!qo2u^$oZWv%kDx-GO<-Xha2 zZqv+$YpBvhCmWQvBZ~TYR3e2?6<2@&;0h?HqC9ha$aNG^T?d{N9+Xi?1fq&405p_Q zKm`<0K*EYBpkYN6Qvs%!)KN)+8+0`h>qQkKLmH!Qv{6WCV^bQ6DjA|8YGYAFCR!>? z>?FW6-NdgZiYg03PkM>X6jpLBBo2DiFVc!DHfo4TG~CfeW?0v#`_V;G0qN9LfN@0? qq9kxU(ziiH6-15AHHpO(R6WK Date: Mon, 22 Jun 2020 15:49:21 +0200 Subject: [PATCH 359/553] Update TESTING_GNB_W_COTS_UE.md --- doc/TESTING_GNB_W_COTS_UE.md | 105 +++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/doc/TESTING_GNB_W_COTS_UE.md b/doc/TESTING_GNB_W_COTS_UE.md index e69de29bb2..d3ab9c175b 100644 --- a/doc/TESTING_GNB_W_COTS_UE.md +++ b/doc/TESTING_GNB_W_COTS_UE.md @@ -0,0 +1,105 @@ + +## Configuration Overview: + +* Non Standalone (NSA) configuration : initial Control Plane established between UE and RAN eNB, then User Plane established between UE and gNB, Core network is 4G based supporting rel 15 + +* Commercial UE: Oppo Reno 5G +* OAI Software Defined gNB and eNB +* eNB RF front end: USRP (ETTUS) B200 Mini or B210 +* gNB RF front end: USRP (ETTUS) B200 Mini or B210 (N300 will be needed for MIMO and wider BW's) +* 5G TDD duplexing mode +* 5G FR1 Band n78 (3.5 GHz) +* BW: 40MHz +* Antenna scheme: SISO + +## SW Repository / Branch + +https://gitlab.eurecom.fr/oai/openairinterface5g/tree/develop + +## Architecture Setup + +photos and schemes + +![image info](https://gitlab.eurecom.fr/oai/openairinterface5g/-/blob/rh_doc_update_3/doc/testing_gnb_w_cots_ue_resources/oppo.jpg) + + +## Build and Install + +General guidelines for building : +See https://gitlab.eurecom.fr/oai/openairinterface5g/blob/develop/doc/BUILD.md#building-ues-enodeb-and-gnodeb-executables + +### **EPC** + +for reference: +https://github.com/OPENAIRINTERFACE/openair-epc-fed/blob/master-documentation/docs/DEPLOY_HOME.md + +``` +sudo bash +cd /opt/hss_sim0609 +./starthss_real +``` + +### **eNB** + +``` +sudo bash +cd /opt/hss_sim0609 +./starthss_real +``` + +### **gNB** + +``` +sudo bash +cd /opt/hss_sim0609 +./starthss_real +``` + +## Testing + +* EPC launching (on EPC host): + +``` +sudo bash +cd /opt/hss_sim0609 +./starthss_real +``` + +Open another window and: + +``` +sudo bash +cd /opt/ltebox/tools +./stop_ltebox +./start_ltebox +``` + +Note: when terminated the testing session, you shall stop the EPC by "./stop_ltebox" + + +* eNB launching (on the eNB host): + +~/openairinterface5g/cmake_targets/ran_build/build$ sudo ./lte-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.band7.tm1.50PRB.usrpb210.conf (-E) + + +eNB is using branch NR_RRCConfiguration patched with enb.diff + + +* gNB launching (on the gNB host) + +~/openairinterface5g/cmake_targets/ran_build/build$ sudo ./nr-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf (-E) + +Note: gNB is using branch NR_RRC_PRACH_procedures patched with gnb.diff + + +Status of the interoperability is as follows: +- setup of the CP in 4G +- setup of the measurements in 5G +- Random access procedure initiation by the UE in the 5G cell +- msg1, msg2, msg3 correctly exchanged and decoded + + +[enb.conf](uploads/48bbbcc8016a33ce6d2faf62e3845005/enb.conf) +[enb.diff](uploads/9763bd6d18256612d007251bc371ca46/enb.diff) +[gnb.conf](uploads/59ae03deccb2186f544451034c297838/gnb.conf) +[gnb.diff](uploads/bb756b2b165cb70f89405d7a8c4c36a8/gnb.diff) \ No newline at end of file From 497c611080a9454710edda07f712f24f83c677a3 Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Mon, 22 Jun 2020 16:59:15 +0200 Subject: [PATCH 360/553] update 1 after review --- ci-scripts/cls_physim.py | 8 +++++--- ci-scripts/main.py | 2 +- .../xml_files/{rh_ldpc_gpu_test.xml => ldpc_gpu_test.xml} | 2 +- 3 files changed, 7 insertions(+), 5 deletions(-) rename ci-scripts/xml_files/{rh_ldpc_gpu_test.xml => ldpc_gpu_test.xml} (96%) diff --git a/ci-scripts/cls_physim.py b/ci-scripts/cls_physim.py index baf8144f88..99c6342697 100644 --- a/ci-scripts/cls_physim.py +++ b/ci-scripts/cls_physim.py @@ -27,6 +27,8 @@ # pexpect #--------------------------------------------------------------------- +#to use logging.info() +import logging #to create a SSH object locally in the methods import sshconnection #to update the HTML object @@ -50,7 +52,7 @@ class PhySim: self.exitStatus=0 #private attributes self.__workSpacePath='' - self.__buildLogFile='compile_oai_enb.log' + self.__buildLogFile='compile_phy_sim.log' self.__runLogFile='ldpctest_run_results.log' self.__runResults=[] @@ -101,7 +103,7 @@ class PhySim: HTML.CreateHtmlTestRow(self.buildargs, 'OK', CONST.ALL_PROCESSES_OK, 'LDPC') self.exitStatus=0 else: - logging.error('\u001B[1m Building OAI UE Failed\u001B[0m') + logging.error('\u001B[1m Building Physical Simulators Failed\u001B[0m') HTML.CreateHtmlTestRow(self.buildargs, 'KO', CONST.ALL_PROCESSES_OK, 'LDPC') HTML.CreateHtmlTabFooter(False) #exitStatus=1 will do a sys.exit in main @@ -143,7 +145,7 @@ class PhySim: if (self.ranBranch != 'develop') and (self.ranBranch != 'origin/develop'): mySSH.command('git merge --ff origin/develop -m "Temporary merge for CI"', '\$', 5) else: - print('Merging with the target branch: ' + self.ranTargetBranch) + logging.info('Merging with the target branch: ' + self.ranTargetBranch) mySSH.command('git merge --ff origin/' + self.ranTargetBranch + ' -m "Temporary merge for CI"', '\$', 5) #build diff --git a/ci-scripts/main.py b/ci-scripts/main.py index 164b4fc6af..ed2a56e688 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -3517,7 +3517,7 @@ elif re.match('^InitiateHtml$', mode, re.IGNORECASE): foundCount += 1 count += 1 if foundCount != HTML.GetnbTestXMLfiles(): - HTML.SetnbTestXMLfiles(foundcount) + HTML.SetnbTestXMLfiles(foundCount) if (CiTestObj.ADBIPAddress != 'none'): terminate_ue_flag = False diff --git a/ci-scripts/xml_files/rh_ldpc_gpu_test.xml b/ci-scripts/xml_files/ldpc_gpu_test.xml similarity index 96% rename from ci-scripts/xml_files/rh_ldpc_gpu_test.xml rename to ci-scripts/xml_files/ldpc_gpu_test.xml index 6df90915d3..4d398bc995 100644 --- a/ci-scripts/xml_files/rh_ldpc_gpu_test.xml +++ b/ci-scripts/xml_files/ldpc_gpu_test.xml @@ -32,7 +32,7 @@ Build_PhySim Build for physical simulator - --phy_simulators + --phy_simulators --ninja From 8517f1314a9c1e08537c4fe755a1adf454e8f41a Mon Sep 17 00:00:00 2001 From: Florian Kaltenberger Date: Mon, 22 Jun 2020 17:07:59 +0200 Subject: [PATCH 361/553] Update RUNMODEM.md --- doc/RUNMODEM.md | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/doc/RUNMODEM.md b/doc/RUNMODEM.md index 7591111b4b..91da029f76 100644 --- a/doc/RUNMODEM.md +++ b/doc/RUNMODEM.md @@ -93,6 +93,14 @@ At the UE the --phy-test flag will ```bash sudo ./nr-uesoftmodem --phy-test [--rrc_config_path ../../../ci-scripts/rrc-files]``` +Some other useful paramters of the UE are + +--ue-fo-compensation: enables the frequency offset compenstation at the UE. This is useful when running over the air and/or without an external clock/time source +--usrp-args: this is the equivalend paramter of sdr_addrs field in the gNB config file and can be used to identify the USRP and set some basic paramters (like the clock source) +--clock-source: sets the clock-source (internal or external). +--time-source: sets the time-source (internal or external). + + ## noS1 setup with OAI UE Instead of randomly generated payload, in the phy-test mode we can also inject/receive user-plane traffic over a TUN interface. This is the so-called noS1 mode. From b31861bac397ddfa13f62266cee3452e810c1fbd Mon Sep 17 00:00:00 2001 From: Florian Kaltenberger Date: Mon, 22 Jun 2020 17:08:32 +0200 Subject: [PATCH 362/553] Update RUNMODEM.md --- doc/RUNMODEM.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/doc/RUNMODEM.md b/doc/RUNMODEM.md index 91da029f76..37eadd92f3 100644 --- a/doc/RUNMODEM.md +++ b/doc/RUNMODEM.md @@ -95,10 +95,10 @@ At the UE the --phy-test flag will Some other useful paramters of the UE are ---ue-fo-compensation: enables the frequency offset compenstation at the UE. This is useful when running over the air and/or without an external clock/time source ---usrp-args: this is the equivalend paramter of sdr_addrs field in the gNB config file and can be used to identify the USRP and set some basic paramters (like the clock source) ---clock-source: sets the clock-source (internal or external). ---time-source: sets the time-source (internal or external). + - --ue-fo-compensation: enables the frequency offset compenstation at the UE. This is useful when running over the air and/or without an external clock/time source + - --usrp-args: this is the equivalend paramter of sdr_addrs field in the gNB config file and can be used to identify the USRP and set some basic paramters (like the clock source) + - --clock-source: sets the clock-source (internal or external). + - --time-source: sets the time-source (internal or external). ## noS1 setup with OAI UE From dbbe79ad85db7903866161ba69b70d1503d0e661 Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Mon, 22 Jun 2020 21:35:38 +0200 Subject: [PATCH 363/553] Update TESTING_GNB_W_COTS_UE.md --- doc/TESTING_GNB_W_COTS_UE.md | 39 ++++++++++++++++++++++++++---------- 1 file changed, 28 insertions(+), 11 deletions(-) diff --git a/doc/TESTING_GNB_W_COTS_UE.md b/doc/TESTING_GNB_W_COTS_UE.md index d3ab9c175b..1e074a2f93 100644 --- a/doc/TESTING_GNB_W_COTS_UE.md +++ b/doc/TESTING_GNB_W_COTS_UE.md @@ -1,4 +1,3 @@ - ## Configuration Overview: * Non Standalone (NSA) configuration : initial Control Plane established between UE and RAN eNB, then User Plane established between UE and gNB, Core network is 4G based supporting rel 15 @@ -20,15 +19,15 @@ https://gitlab.eurecom.fr/oai/openairinterface5g/tree/develop photos and schemes -![image info](https://gitlab.eurecom.fr/oai/openairinterface5g/-/blob/rh_doc_update_3/doc/testing_gnb_w_cots_ue_resources/oppo.jpg) +![image info](./testing_gnb_w_cots_ue_resources/oppo.jpg) -## Build and Install +## Build / Install General guidelines for building : See https://gitlab.eurecom.fr/oai/openairinterface5g/blob/develop/doc/BUILD.md#building-ues-enodeb-and-gnodeb-executables -### **EPC** +- **EPC** for reference: https://github.com/OPENAIRINTERFACE/openair-epc-fed/blob/master-documentation/docs/DEPLOY_HOME.md @@ -39,7 +38,7 @@ cd /opt/hss_sim0609 ./starthss_real ``` -### **eNB** +- **eNB** ``` sudo bash @@ -47,7 +46,7 @@ cd /opt/hss_sim0609 ./starthss_real ``` -### **gNB** +- **gNB** ``` sudo bash @@ -55,9 +54,15 @@ cd /opt/hss_sim0609 ./starthss_real ``` -## Testing +## Conf Files -* EPC launching (on EPC host): +where are they +usage + +## Run / Test + + +- **EPC** (on EPC host): ``` sudo bash @@ -77,7 +82,7 @@ cd /opt/ltebox/tools Note: when terminated the testing session, you shall stop the EPC by "./stop_ltebox" -* eNB launching (on the eNB host): +- **eNB** (on the eNB host): ~/openairinterface5g/cmake_targets/ran_build/build$ sudo ./lte-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.band7.tm1.50PRB.usrpb210.conf (-E) @@ -85,14 +90,26 @@ Note: when terminated the testing session, you shall stop the EPC by "./stop_lte eNB is using branch NR_RRCConfiguration patched with enb.diff -* gNB launching (on the gNB host) +- **gNB** (on the gNB host) ~/openairinterface5g/cmake_targets/ran_build/build$ sudo ./nr-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf (-E) Note: gNB is using branch NR_RRC_PRACH_procedures patched with gnb.diff -Status of the interoperability is as follows: +## Test Case + +Test case description + +## Expected Logs to check + +what and where to check + +## Required traces for debug + + + +## Status of the interoperability - setup of the CP in 4G - setup of the measurements in 5G - Random access procedure initiation by the UE in the 5G cell From 779b7537ccff65932ac37e78edad6549a0170645 Mon Sep 17 00:00:00 2001 From: hardy Date: Mon, 22 Jun 2020 23:34:34 +0200 Subject: [PATCH 364/553] uploading fr1 setup scheme --- .../oai_fr1_setup.jpg | Bin 0 -> 198598 bytes .../oai_fr1_setup.vsdx | Bin 0 -> 560725 bytes 2 files changed, 0 insertions(+), 0 deletions(-) create mode 100755 doc/testing_gnb_w_cots_ue_resources/oai_fr1_setup.jpg create mode 100755 doc/testing_gnb_w_cots_ue_resources/oai_fr1_setup.vsdx diff --git a/doc/testing_gnb_w_cots_ue_resources/oai_fr1_setup.jpg b/doc/testing_gnb_w_cots_ue_resources/oai_fr1_setup.jpg new file mode 100755 index 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z%X4n|!?CZR07kLo6|c8|q(4^L7Wn$dN*x1SII_Lt2>gYEK)L^? z)`CFn|Jnxx^791p$TQAU4KRpQ5eMPt{u9_J3J?fMK3~@VTPuwP PoZ}!jE=)&4$o~HTE&KLJ From b33993f542e00fc0b39053fb51af78fc43d5e311 Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Tue, 23 Jun 2020 10:42:43 +0200 Subject: [PATCH 368/553] Update TESTING_GNB_W_COTS_UE.md --- doc/TESTING_GNB_W_COTS_UE.md | 34 +++++++++++++--------------------- 1 file changed, 13 insertions(+), 21 deletions(-) diff --git a/doc/TESTING_GNB_W_COTS_UE.md b/doc/TESTING_GNB_W_COTS_UE.md index 4e4d6e6863..e0d5edb119 100644 --- a/doc/TESTING_GNB_W_COTS_UE.md +++ b/doc/TESTING_GNB_W_COTS_UE.md @@ -5,7 +5,7 @@ * Commercial UE: Oppo Reno 5G * OAI Software Defined gNB and eNB * eNB RF front end: USRP (ETTUS) B200 Mini or B210 -* gNB RF front end: USRP (ETTUS) B200 Mini or B210 (N300 will be needed for MIMO and wider BW's) +* gNB RF front end: USRP (ETTUS) B200 Mini or B210 (N310 will be needed for MIMO and wider BW's) * 5G TDD duplexing mode * 5G FR1 Band n78 (3.5 GHz) * BW: 40MHz @@ -17,7 +17,7 @@ https://gitlab.eurecom.fr/oai/openairinterface5g/tree/develop ## Architecture Setup -photos and schemes +The scheme below depicts our typical setup: ![image info](./testing_gnb_w_cots_ue_resources/oai_fr1_setup.jpg) @@ -32,32 +32,27 @@ See https://gitlab.eurecom.fr/oai/openairinterface5g/blob/develop/doc/BUILD.md#b for reference: https://github.com/OPENAIRINTERFACE/openair-epc-fed/blob/master-documentation/docs/DEPLOY_HOME.md + ``` -sudo bash -cd /opt/hss_sim0609 -./starthss_real +sudo ``` - **eNB** ``` -sudo bash -cd /opt/hss_sim0609 -./starthss_real +sudo ``` - **gNB** ``` -sudo bash -cd /opt/hss_sim0609 -./starthss_real +sudo ``` ## Conf Files -where are they -usage +where are the config files located +how to use them ## Run / Test @@ -65,9 +60,7 @@ usage - **EPC** (on EPC host): ``` -sudo bash -cd /opt/hss_sim0609 -./starthss_real +sudo ``` Open another window and: @@ -75,8 +68,7 @@ Open another window and: ``` sudo bash cd /opt/ltebox/tools -./stop_ltebox -./start_ltebox + ``` Note: when terminated the testing session, you shall stop the EPC by "./stop_ltebox" @@ -99,15 +91,15 @@ Note: gNB is using branch NR_RRC_PRACH_procedures patched with gnb.diff ## Test Case -Test case description +Test case description : UE attachement ## Expected Logs to check -what and where to check +what logs and where to check, to ensure that your setup works fine ## Required traces for debug - +What info/traces/logs are needed for us to support the debug ## Status of the interoperability - setup of the CP in 4G From 16d9e27d5d8622e1885b8a44d31aeaad671d7f8d Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Tue, 23 Jun 2020 10:43:53 +0200 Subject: [PATCH 369/553] Update TESTING_GNB_W_COTS_UE.md --- doc/TESTING_GNB_W_COTS_UE.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/doc/TESTING_GNB_W_COTS_UE.md b/doc/TESTING_GNB_W_COTS_UE.md index e0d5edb119..3aad387465 100644 --- a/doc/TESTING_GNB_W_COTS_UE.md +++ b/doc/TESTING_GNB_W_COTS_UE.md @@ -1,3 +1,5 @@ +DISCLAIMER : This page is under complete review and update, thanks for your patience + ## Configuration Overview: * Non Standalone (NSA) configuration : initial Control Plane established between UE and RAN eNB, then User Plane established between UE and gNB, Core network is 4G based supporting rel 15 From 03ff1ef3044f6a6fdcedddaf1daf7430abcf23a5 Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Tue, 23 Jun 2020 22:29:23 +0200 Subject: [PATCH 370/553] update 2 after review --- ci-scripts/cls_physim.py | 26 ++++-- ci-scripts/main.py | 2 +- ci-scripts/xml_files/ldpc_gpu_test.xml | 114 ++++++++++++++++++++++++- 3 files changed, 131 insertions(+), 11 deletions(-) diff --git a/ci-scripts/cls_physim.py b/ci-scripts/cls_physim.py index 99c6342697..09ed1c8363 100644 --- a/ci-scripts/cls_physim.py +++ b/ci-scripts/cls_physim.py @@ -34,7 +34,8 @@ import sshconnection #to update the HTML object import html from multiprocessing import SimpleQueue - +#for log folder maintenance +import os class PhySim: def __init__(self): @@ -53,27 +54,32 @@ class PhySim: #private attributes self.__workSpacePath='' self.__buildLogFile='compile_phy_sim.log' - self.__runLogFile='ldpctest_run_results.log' + self.__runLogFile='' self.__runResults=[] + self.__runLogPath='phy_sim_logs' #----------------- #PRIVATE Methods #----------------- - def __CheckResults_PhySim(self,HTML,CONST): + def __CheckResults_PhySim(self,HTML,CONST,testcase_id): mySSH = sshconnection.SSHConnection() mySSH.open(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord) #retrieve run log file and store it locally$ mySSH.copyin(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord, self.__workSpacePath+self.__runLogFile, '.') mySSH.close() #parse results looking for Encoding and Decoding mean values + self.__runResults=[] with open(self.__runLogFile) as f: for line in f: if 'mean' in line: self.__runResults.append(line) - #the value are appended for each test, so we take the last 2 values from the list - info=self.__runResults[-1]+self.__runResults[-2] + #the value are appended for each mean value (2), so we take these 2 values from the list + info=self.__runResults[0]+self.__runResults[1] + + #once parsed move the local logfile to its folder for tidiness + os.system('mv '+self.__runLogFile+' '+ self.__runLogPath+'/.') #updating the HTML with results html_cell = '

' + info  + '
' @@ -153,7 +159,7 @@ class PhySim: mySSH.command('cd cmake_targets', '\$', 5) mySSH.command('mkdir -p log', '\$', 5) mySSH.command('chmod 777 log', '\$', 5) - mySSH.command('stdbuf -o0 ./build_oai ' + self.buildargs + ' 2>&1 | stdbuf -o0 tee compile_oai_enb.log', 'Bypassing the Tests|build have failed', 1500) + mySSH.command('stdbuf -o0 ./build_oai ' + self.buildargs + ' 2>&1 | stdbuf -o0 tee ' + self.__buildLogFile, 'Bypassing the Tests|build have failed', 1500) mySSH.close() #check build status and update HTML object @@ -162,7 +168,11 @@ class PhySim: return lHTML - def Run_PhySim(self,htmlObj,constObj): + def Run_PhySim(self,htmlObj,constObj,testcase_id): + #create run logs folder locally + os.system('mkdir -p ./'+self.__runLogPath) + #log file is tc_.log remotely + self.__runLogFile='physim_'+str(testcase_id)+'.log' #open a session for test run mySSH = sshconnection.SSHConnection() mySSH.open(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord) @@ -172,5 +182,5 @@ class PhySim: mySSH.close() #return updated HTML to main lHTML = html.HTMLManagement() - lHTML=self.__CheckResults_PhySim(htmlObj,constObj) + lHTML=self.__CheckResults_PhySim(htmlObj,constObj,testcase_id) return lHTML diff --git a/ci-scripts/main.py b/ci-scripts/main.py index ed2a56e688..a1c1ac7ec0 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -3724,7 +3724,7 @@ elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re HTML=ldpc.Build_PhySim(HTML,CONST) if ldpc.exitStatus==1:sys.exit() elif action == 'Run_PhySim': - ldpc.Run_PhySim(HTML,CONST) + HTML=ldpc.Run_PhySim(HTML,CONST,id) else: sys.exit('Invalid action') CiTestObj.FailReportCnt += 1 diff --git a/ci-scripts/xml_files/ldpc_gpu_test.xml b/ci-scripts/xml_files/ldpc_gpu_test.xml index 4d398bc995..029c49ecf5 100644 --- a/ci-scripts/xml_files/ldpc_gpu_test.xml +++ b/ci-scripts/xml_files/ldpc_gpu_test.xml @@ -26,7 +26,7 @@ Test-ldpc-GPU tasks 1 - 000001 000002 000003 + 000001 000002 000003 000004 000005 000006 000007 000008 000009 000010 000011 000012 000013 000014 000015 000016 000017 000018 000019 000020 000021 @@ -38,13 +38,123 @@ Run_PhySim Run LDPC Test with CPU - -l 8448 -s10 -n100 + -l 3872 -s10 -n100 + Run_PhySim + Run LDPC Test with GPU + -l 3872 -s10 -n100 -G 1 + + + + Run_PhySim + Run LDPC Test with CPU + -l 4224 -s10 -n100 + + + + Run_PhySim + Run LDPC Test with GPU + -l 4224 -s10 -n100 -G 1 + + + + Run_PhySim + Run LDPC Test with CPU + -l 4576 -s10 -n100 + + + + Run_PhySim + Run LDPC Test with GPU + -l 4576 -s10 -n100 -G 1 + + + + Run_PhySim + Run LDPC Test with CPU + -l 4928 -s10 -n100 + + + + Run_PhySim + Run LDPC Test with GPU + -l 4928 -s10 -n100 -G 1 + + + + Run_PhySim + Run LDPC Test with CPU + -l 5280 -s10 -n100 + + + + Run_PhySim + Run LDPC Test with GPU + -l 5280 -s10 -n100 -G 1 + + + + Run_PhySim + Run LDPC Test with CPU + -l 5632 -s10 -n100 + + + + Run_PhySim + Run LDPC Test with GPU + -l 5632 -s10 -n100 -G 1 + + + + Run_PhySim + Run LDPC Test with CPU + -l 6336 -s10 -n100 + + + + Run_PhySim + Run LDPC Test with GPU + -l 6336 -s10 -n100 -G 1 + + + + Run_PhySim + Run LDPC Test with CPU + -l 7040 -s10 -n100 + + + + Run_PhySim + Run LDPC Test with GPU + -l 7040 -s10 -n100 -G 1 + + + + Run_PhySim + Run LDPC Test with CPU + -l 7744 -s10 -n100 + + + + Run_PhySim + Run LDPC Test with GPU + -l 7744 -s10 -n100 -G 1 + + + + Run_PhySim + Run LDPC Test with CPU + -l 8448 -s10 -n100 + + + Run_PhySim Run LDPC Test with GPU -l 8448 -s10 -n100 -G 1 + + From aad868d8fac9e31fcb2be79d0410680276dd2509 Mon Sep 17 00:00:00 2001 From: laurent Date: Wed, 24 Jun 2020 09:48:35 +0200 Subject: [PATCH 371/553] 5G scope cleaning round 2 --- executables/nr-uesoftmodem.c | 2 +- openair1/PHY/TOOLS/nr_phy_scope.c | 634 +++++++++------------ openair1/PHY/TOOLS/nr_phy_scope.h | 1 - openair1/SCHED_NR/phy_frame_config_nr.h | 2 + openair2/LAYER2/NR_MAC_UE/mac_proto.h | 1 + openair2/LAYER2/NR_MAC_UE/main_ue_nr.c | 2 +- openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c | 2 +- openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c | 1 + openair2/LAYER2/PDCP_v10.1.0/pdcp.h | 4 - openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c | 3 - 10 files changed, 276 insertions(+), 376 deletions(-) diff --git a/executables/nr-uesoftmodem.c b/executables/nr-uesoftmodem.c index b96f98e1f2..5d3edbfcb1 100644 --- a/executables/nr-uesoftmodem.c +++ b/executables/nr-uesoftmodem.c @@ -249,7 +249,7 @@ void exit_function(const char *file, const char *function, const int line, const } -void reset_stats(FL_OBJECT *button, long arg) { +void reset_stats(long arg) { //int i,j,k; /*PHY_VARS_eNB *phy_vars_eNB = PHY_vars_eNB_g[0][0]; diff --git a/openair1/PHY/TOOLS/nr_phy_scope.c b/openair1/PHY/TOOLS/nr_phy_scope.c index 45eb66b4e3..dfb148d34e 100644 --- a/openair1/PHY/TOOLS/nr_phy_scope.c +++ b/openair1/PHY/TOOLS/nr_phy_scope.c @@ -26,6 +26,7 @@ #include #include "nr_phy_scope.h" #include "executables/nr-softmodem-common.h" +#include #define TPUT_WINDOW_LENGTH 100 #define localBuff(NaMe,SiZe) float NaMe[SiZe]; memset(NaMe,0,sizeof(NaMe)); @@ -47,8 +48,13 @@ typedef struct { typedef struct OAIgraph { FL_OBJECT *graph; - void (*gNBfunct) (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int UE_id); - void (*nrUEfunct) (FL_OBJECT *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id); + float maxX; + float maxY; + float minX; + float minY; + int iteration; + void (*gNBfunct) (struct OAIgraph *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int UE_id); + void (*nrUEfunct)(struct OAIgraph *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id); } OAIgraph_t; /* Forms and Objects */ @@ -56,7 +62,7 @@ typedef struct { FL_FORM *phy_scope; OAIgraph_t graph[20]; FL_OBJECT *button_0; -} FD_phy_scope_t; +} OAI_phy_scope_t; typedef struct { FL_FORM *stats_form; @@ -72,18 +78,8 @@ static void drawsymbol(FL_OBJECT *obj, int id, fl_points( p, n, FL_YELLOW); } -static void ia_receiver_on_off( FL_OBJECT *button, long arg) { - if (fl_get_button(button)) { - fl_set_object_label(button, "IA Receiver ON"); - // PHY_vars_UE_g[0][0]->use_ia_receiver = 1; - fl_set_object_color(button, FL_GREEN, FL_GREEN); - } else { - fl_set_object_label(button, "IA Receiver OFF"); - // PHY_vars_UE_g[0][0]->use_ia_receiver = 0; - fl_set_object_color(button, FL_RED, FL_RED); - } -} - +// button callback example +#if 0 static void dl_traffic_on_off( FL_OBJECT *button, long arg) { if (fl_get_button(button)) { fl_set_object_label(button, "DL Traffic ON"); @@ -95,201 +91,197 @@ static void dl_traffic_on_off( FL_OBJECT *button, long arg) { fl_set_object_color(button, FL_RED, FL_RED); } } +#endif static FL_OBJECT *commonGraph( int type, FL_Coord x, FL_Coord y, FL_Coord w, FL_Coord h, const char *label, FL_COLOR pointColor) { FL_OBJECT *graph; graph=fl_add_xyplot(type, x, y, w, h, label); - fl_set_object_boxtype(graph, FL_EMBOSSED_BOX ); fl_set_object_lcolor(graph, FL_WHITE ); // Label color - fl_set_xyplot_symbol(graph, 0, drawsymbol); fl_set_object_color(graph, FL_BLACK, pointColor); + fl_set_xyplot_symbol(graph, -1, drawsymbol); return graph; } -static OAIgraph_t gNBcommonGraph( void (*funct) (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int UE_id), +static OAIgraph_t gNBcommonGraph( void (*funct) (OAIgraph_t *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int UE_id), int type, FL_Coord x, FL_Coord y, FL_Coord w, FL_Coord h, const char *label, FL_COLOR pointColor) { OAIgraph_t graph; graph.graph=commonGraph(type, x, y, w, h, label, pointColor); graph.gNBfunct=funct; graph.nrUEfunct=NULL; + graph.maxX=0; + graph.maxY=0; + graph.minX=0; + graph.minY=0; return graph; } -static OAIgraph_t nrUEcommonGraph( void (*funct) (FL_OBJECT *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id), +static OAIgraph_t nrUEcommonGraph( void (*funct) (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id), int type, FL_Coord x, FL_Coord y, FL_Coord w, FL_Coord h, const char *label, FL_COLOR pointColor) { OAIgraph_t graph; graph.graph=commonGraph(type, x, y, w, h, label, pointColor); graph.gNBfunct=NULL; graph.nrUEfunct=funct; + graph.maxX=0; + graph.maxY=0; + graph.minX=0; + graph.minY=0; return graph; } -void phy_scope_gNB(FD_phy_scope_t *form, - PHY_VARS_gNB *phy_vars_gnb, - RU_t *phy_vars_ru, - int UE_id) { - static FD_phy_scope_t *remeberForm=NULL; - - if (form==NULL) - form=remeberForm; - else - remeberForm=form; - - if (form==NULL) return; - - int i=0; - - while (form->graph[i].graph) { - form->graph[i].gNBfunct(form->graph[i].graph, phy_vars_gnb, phy_vars_ru, UE_id); - i++; +static void setRange(OAIgraph_t *graph, float minX, float maxX, float minY, float maxY) { + if ( maxX > graph->maxX || maxY > graph->maxY || minX < graph->minX || minY < graph->minY ) { + graph->maxX=max(graph->maxX,maxX); + graph->minX=min(graph->minX,minX); + graph->maxY=max(graph->maxY,maxY); + graph->minY=min(graph->minY,minY); + fl_set_xyplot_ybounds(graph->graph, graph->minY, graph->maxY); + fl_set_xyplot_xbounds(graph->graph, graph->minX, graph->maxX); } - - fl_check_forms(); } -static void timeSignal (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int UE_id) { +static void oai_xygraph(OAIgraph_t *graph, float *x, float *y, int len, int layer, int NoAutoScale) { + if (layer==0) + fl_set_xyplot_data(graph->graph,x,y,len,"","",""); + else + fl_add_xyplot_overlay(graph->graph,layer,x,y,len,rx_antenna_colors[layer]); + + if ( NoAutoScale && graph->iteration%NoAutoScale == 0) { + float maxX=0, maxY=0, minX=0, minY=0; + + for (int k=0; kiteration++; +} + +static void genericLogPowerPerAntena(OAIgraph_t *graph, const int nb_ant, const scopeSample_t **data, const int len) { + float *values=malloc(len*sizeof(*values)); + float *time=malloc(len*sizeof(*time)); + + for (int ant=0; antcommon.rxdata) return; NR_DL_FRAME_PARMS *frame_parms=&phy_vars_gnb->frame_parms; - uint8_t nb_antennas_rx = frame_parms->nb_antennas_rx; - scopeSample_t **rxsig_t = (scopeSample_t **)phy_vars_ru->common.rxdata; - float rxsig_t_dB[frame_parms->samples_per_frame]; - float time[frame_parms->samples_per_frame]; + genericLogPowerPerAntena(graph, frame_parms->nb_antennas_rx, + (const scopeSample_t **)phy_vars_ru->common.rxdata, + frame_parms->samples_per_frame); +} - for (int arx=0; arxsamples_per_frame; i++) { - rxsig_t_dB[i] = 10*log10(1.0+SquaredNorm(rxsig_t[arx][i])); - time[i] = i; +static void timeResponse (OAIgraph_t *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int nb_UEs) { + const int len=2*phy_vars_gnb->frame_parms.ofdm_symbol_size; + float values[len]; + float time[len]; + const int ant=0; // display antenna 0 for each UE + + for (int ue=0; uepusch_vars[ue]->ul_ch_estimates_time[ant]; + + if (data != NULL) { + for (int i=0; isamples_per_frame,"","",""); - else - fl_add_xyplot_overlay(graph,arx,time,rxsig_t_dB,frame_parms->samples_per_frame,rx_antenna_colors[arx]); + oai_xygraph(graph,time,values, len, ue, 10); } } } -static void timeResponse (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int UE_id) { - if (!phy_vars_gnb->pusch_vars[UE_id]->ul_ch_estimates_time) - return; - +static void frequencyResponse (OAIgraph_t *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int nb_UEs) { NR_DL_FRAME_PARMS *frame_parms=&phy_vars_gnb->frame_parms; - uint8_t nb_antennas_rx = frame_parms->nb_antennas_rx; - scopeSample_t **chest_t = (scopeSample_t **) phy_vars_gnb->pusch_vars[UE_id]->ul_ch_estimates_time; - int ymax = 0; - float time2[2*frame_parms->ofdm_symbol_size]; - float chest_t_abs[2*frame_parms->ofdm_symbol_size]; - - for (int arx=0; arxofdm_symbol_size); i++) { - time2[i] = (float)i; - chest_t_abs[i] = 10*log10(1.0 + SquaredNorm(chest_t[0][i])); - - if (chest_t_abs[i] > ymax) - ymax = chest_t_abs[i]; - } - - if (arx==0) - fl_set_xyplot_data(graph,time2,chest_t_abs,(2*frame_parms->ofdm_symbol_size),"","",""); - else { - fl_add_xyplot_overlay(graph,arx,time2,chest_t_abs,(frame_parms->ofdm_symbol_size>>3),rx_antenna_colors[arx]); - fl_set_xyplot_overlay_type(graph,arx,FL_DASHED_XYPLOT); - } - } - } - - // Avoid flickering effect - // fl_get_xyplot_ybounds(form->chest_t,&ymin,&ymax); - fl_set_xyplot_ybounds(graph,0,ymax); + genericLogPowerPerAntena(graph, frame_parms->nb_antennas_rx, + (const scopeSample_t **)phy_vars_ru->common.rxdataF, + frame_parms->samples_per_slot_wCP); } -static void frequencyResponse (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int UE_id) { - // Channel Frequency Response - if (!phy_vars_ru->common.rxdataF) - return; - - NR_DL_FRAME_PARMS *frame_parms=&phy_vars_gnb->frame_parms; - //uint8_t nb_antennas_rx = frame_parms->nb_antennas_rx; - scopeSample_t **rxsig_f = (scopeSample_t **) phy_vars_ru->common.rxdataF; - float rxsig_f_dB[frame_parms->samples_per_slot_wCP]; - float time[frame_parms->samples_per_slot_wCP]; - - if (rxsig_f[0] != NULL) { - for (int i=0; isamples_per_slot_wCP; i++) { - rxsig_f_dB[i] = 10*log10(1.0+ SquaredNorm(rxsig_f[0][i])); - time[i] = (float) i; - } - - fl_set_xyplot_data(graph,time,rxsig_f_dB,frame_parms->samples_per_slot_wCP,"","",""); - } - - /* - for (int arx=1; arxchest_f,1,time,chest_f_abs,nsymb_ce,rx_antenna_colors[arx]); - } - } - */ - /* - // tx antenna 0 - fl_set_xyplot_xbounds(form->chest_f,0,nb_antennas_rx*nb_antennas_tx*nsymb_ce); - fl_set_xyplot_xtics(form->chest_f,nb_antennas_rx*nb_antennas_tx*frame_parms->symbols_per_tti,3); - fl_set_xyplot_xgrid(form->chest_f,FL_GRID_MAJOR); - fl_set_xyplot_data(form->chest_f,freq,chest_f_abs,nsymb_ce,"","",""); - */ -} - -static void puschLLR (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int UE_id) { - // PUSCH LLRs - if (!phy_vars_gnb->pusch_vars[UE_id]->llr) - return; - - //NR_DL_FRAME_PARMS *frame_parms=&phy_vars_gnb->frame_parms; +static void puschLLR (OAIgraph_t *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int nb_UEs) { //int Qm = 2; - int16_t *pusch_llr = (int16_t *) phy_vars_gnb->pusch_vars[UE_id]->llr; int coded_bits_per_codeword =3*8*6144+12; // (8*((3*8*6144)+12)); // frame_parms->N_RB_UL*12*Qm*frame_parms->symbols_per_tti; float llr[coded_bits_per_codeword]; float bit[coded_bits_per_codeword]; - for (int i=0; ipusch_vars[ue]->llr; - fl_set_xyplot_data(graph,bit,llr,coded_bits_per_codeword,"","",""); + if (pusch_llr) { + for (int i=0; ipusch_vars[UE_id]->rxdataF_comp) - return; - +static void puschIQ (OAIgraph_t *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int nb_UEs) { NR_DL_FRAME_PARMS *frame_parms=&phy_vars_gnb->frame_parms; - scopeSample_t *pusch_comp = (scopeSample_t *) phy_vars_gnb->pusch_vars[UE_id]->rxdataF_comp[0]; int sz=frame_parms->N_RB_UL*12*frame_parms->symbols_per_slot; float I[sz], Q[sz]; - for (int k=0; kpusch_vars[ue]->rxdataF_comp[0]; + + if (pusch_comp) { + for (int k=0; kpucch1ab_stats[UE_id]; int32_t *pucch1_comp = (int32_t *) NULL; //phy_vars_gnb->pucch1_stats[UE_id]; float I_pucch[10240],Q_pucch[10240],A_pucch[10240],B_pucch[10240],C_pucch[10240]; @@ -310,17 +302,15 @@ static void puschIQ (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_var fl_set_xyplot_xbounds(graph,-5000,5000); fl_set_xyplot_ybounds(graph,0,80); } -#endif + */ } -static void pucchEnergy (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int UE_id) { +static void pucchIQ (OAIgraph_t *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int nb_UEs) { } -static void pucchIQ (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int UE_id) { -} - -static void puschThroughtput (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int UE_id) { +static void puschThroughtput (OAIgraph_t *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int nb_UEs) { // PUSCH Throughput + /* memmove( tput_time_enb[UE_id], &tput_time_enb[UE_id][1], (TPUT_WINDOW_LENGTH-1)*sizeof(float) ); memmove( tput_enb[UE_id], &tput_enb[UE_id][1], (TPUT_WINDOW_LENGTH-1)*sizeof(float) ); tput_time_enb[UE_id][TPUT_WINDOW_LENGTH-1] = (float) 0; @@ -328,224 +318,126 @@ static void puschThroughtput (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t fl_set_xyplot_data(graph,tput_time_enb[UE_id],tput_enb[UE_id],TPUT_WINDOW_LENGTH,"","",""); // fl_get_xyplot_ybounds(form->pusch_tput,&ymin,&ymax); // fl_set_xyplot_ybounds(form->pusch_tput,0,ymax); + */ } -static FD_phy_scope_t *create_phy_scope_gnb(int UE_id ) { +static OAI_phy_scope_t *create_phy_scope_gnb(void) { FL_OBJECT *obj; - FD_phy_scope_t *fdui = fl_malloc( sizeof *fdui ); + OAI_phy_scope_t *fdui = calloc(( sizeof *fdui ),1); // Define form fdui->phy_scope = fl_bgn_form( FL_NO_BOX, 800, 800 ); // This the whole UI box obj = fl_add_box( FL_BORDER_BOX, 0, 0, 800, 800, "" ); - fl_set_object_color( obj, FL_BLACK, FL_BLACK ); + fl_set_object_color( obj, FL_BLACK, FL_WHITE ); + int curY=0,x,y,w,h; // Received signal - fdui->graph[0] = gNBcommonGraph( timeSignal, FL_IMPULSE_XYPLOT, 20, 20, 370, 100, + fdui->graph[0] = gNBcommonGraph( timeSignal, FL_NORMAL_XYPLOT, 0, curY, 400, 100, "Received Signal (Time-Domain, dB)", FL_RED ); // Time-domain channel response - fdui->graph[1] = gNBcommonGraph( timeResponse, FL_NORMAL_XYPLOT, 410, 20, 370, 100, + fdui->graph[1] = gNBcommonGraph( timeResponse, FL_NORMAL_XYPLOT, 410, curY, 400, 100, "SRS Frequency Response (samples, abs)", FL_RED ); + fl_get_object_bbox(fdui->graph[0].graph,&x, &y,&w, &h); + curY+=h; // Frequency-domain channel response - fdui->graph[2] = gNBcommonGraph( frequencyResponse, FL_IMPULSE_XYPLOT, 20, 140, 760, 100, + fdui->graph[2] = gNBcommonGraph( frequencyResponse, FL_NORMAL_XYPLOT, 0, curY, 800, 100, "Channel Frequency Response (RE, dB)", FL_RED ); + fl_get_object_bbox(fdui->graph[2].graph,&x, &y,&w, &h); + curY+=h; // LLR of PUSCH - fdui->graph[3] = gNBcommonGraph( puschLLR, FL_POINTS_XYPLOT, 20, 260, 500, 200, + fdui->graph[3] = gNBcommonGraph( puschLLR, FL_POINTS_XYPLOT, 0, curY, 500, 200, "PUSCH Log-Likelihood Ratios (LLR, mag)", FL_YELLOW ); // I/Q PUSCH comp - fdui->graph[4] = gNBcommonGraph( puschIQ, FL_POINTS_XYPLOT, 540, 260, 240, 200, + fdui->graph[4] = gNBcommonGraph( puschIQ, FL_POINTS_XYPLOT, 500, curY, 300, 200, "PUSCH I/Q of MF Output", FL_YELLOW ); + fl_get_object_bbox(fdui->graph[3].graph,&x, &y,&w, &h); + curY+=h; // I/Q PUCCH comp (format 1) - fdui->graph[5] = gNBcommonGraph( pucchEnergy, FL_POINTS_XYPLOT, 540, 480, 240, 100, + fdui->graph[5] = gNBcommonGraph( pucchEnergy, FL_POINTS_XYPLOT, 0, curY, 300, 100, "PUCCH1 Energy (SR)", FL_YELLOW ); // fl_set_xyplot_xgrid( fdui->pusch_llr,FL_GRID_MAJOR); // I/Q PUCCH comp (fromat 1a/b) - fdui->graph[6] = gNBcommonGraph( pucchIQ, FL_POINTS_XYPLOT, 540, 600, 240, 100, + fdui->graph[6] = gNBcommonGraph( pucchIQ, FL_POINTS_XYPLOT, 500, curY, 300, 100, "PUCCH I/Q of MF Output", FL_YELLOW ); + fl_get_object_bbox(fdui->graph[6].graph,&x, &y,&w, &h); + curY+=h; // Throughput on PUSCH - fdui->graph[7] = gNBcommonGraph( puschThroughtput, FL_NORMAL_XYPLOT, 20, 480, 500, 100, + fdui->graph[7] = gNBcommonGraph( puschThroughtput, FL_NORMAL_XYPLOT, 0, curY, 500, 100, "PUSCH Throughput [frame]/[kbit/s]", FL_WHITE ); fdui->graph[8].graph=NULL; - - // Generic eNB Button - if (0) { // code kept to later add command buttons - fdui->button_0 = fl_add_button( FL_PUSH_BUTTON, 20, 600, 240, 40, "" ); - fl_set_object_lalign(fdui->button_0, FL_ALIGN_CENTER ); - fl_set_button(fdui->button_0,0); - otg_enabled = 0; - fl_set_object_label(fdui->button_0, "DL Traffic OFF"); - fl_set_object_color(fdui->button_0, FL_RED, FL_RED); - fl_set_object_callback(fdui->button_0, dl_traffic_on_off, 0 ); - } - fl_end_form( ); fdui->phy_scope->fdui = fdui; - char title[100]; - sprintf (title, "LTE UL SCOPE eNB for UE %d",UE_id); - fl_show_form (fdui->phy_scope, FL_PLACE_HOTSPOT, FL_FULLBORDER, title); + fl_show_form (fdui->phy_scope, FL_PLACE_HOTSPOT, FL_FULLBORDER, "LTE UL SCOPE gNB"); return fdui; } -static FD_phy_scope_t *form_gnb[NUMBER_OF_UE_MAX]= {0}; -static unsigned char scope_enb_num_ue = 1; +static const int scope_enb_num_ue = 1; +void phy_scope_gNB(OAI_phy_scope_t *form, + PHY_VARS_gNB *phy_vars_gnb, + RU_t *phy_vars_ru, + int UE_id) { + static OAI_phy_scope_t *remeberForm=NULL; + + if (form==NULL) + form=remeberForm; + else + remeberForm=form; + + if (form==NULL) return; + + int i=0; + + while (form->graph[i].graph) { + form->graph[i].gNBfunct(form->graph+i, phy_vars_gnb, phy_vars_ru, UE_id); + i++; + } + + fl_check_forms(); +} static void *scope_thread_gNB(void *arg) { scopeParms_t *p=(scopeParms_t *) arg; //# ifdef ENABLE_XFORMS_WRITE_STATS // FILE *gNB_stats = fopen("gNB_stats.txt", "w"); //#endif - size_t stksize; - pthread_attr_t atr; + size_t stksize=0; + pthread_attr_t atr= {0}; pthread_attr_getstacksize(&atr, &stksize); pthread_attr_setstacksize(&atr,32*1024*1024 ); sleep(3); // no clean interthread barriers + fl_initialize (p->argc, p->argv, NULL, 0, 0); + int nb_ue=min(NUMBER_OF_UE_MAX, scope_enb_num_ue); + OAI_phy_scope_t *form_gnb = create_phy_scope_gnb(); while (!oai_exit) { - int ue_cnt=0; - - for(int UE_id=0; UE_idgNB, p->ru, UE_id); - ue_cnt++; - } - } - + phy_scope_gNB(form_gnb, p->gNB, p->ru, nb_ue); usleep(99*1000); } - // printf("%s",stats_buffer); - /*#ifdef ENABLE_XFORMS_WRITE_STATS - - if (eNB_stats) { - rewind (gNB_stats); - fwrite (stats_buffer, 1, len, gNB_stats); - fclose (gNB_stats); - } - - #endif - pthread_exit((void *)arg); - }*/ return NULL; } void gNBinitScope(scopeParms_t *p) { - //FD_stats_form *form_stats=NULL,*form_stats_l2=NULL; - fl_initialize (p->argc, p->argv, NULL, 0, 0); - - /* - form_stats_l2 = create_form_stats_form(); - fl_show_form (form_stats_l2->stats_form, FL_PLACE_HOTSPOT, FL_FULLBORDER, "l2 stats"); - form_stats = create_form_stats_form(); - fl_show_form (form_stats->stats_form, FL_PLACE_HOTSPOT, FL_FULLBORDER, "stats"); - */ - for(int UE_id=0; UE_idcommon_vars.rxdata) - return; - - NR_DL_FRAME_PARMS *frame_parms = &phy_vars_ue->frame_parms; - uint8_t nb_antennas_rx = frame_parms->nb_antennas_rx; - int samples_per_frame = frame_parms->samples_per_frame; - scopeSample_t **rxsig_t = (scopeSample_t **) phy_vars_ue->common_vars.rxdata; - float rxsig_t_dB[samples_per_frame]; - float time[samples_per_frame]; - - if (rxsig_t[0] != NULL) { - for (int i=0; iis_synchronized==0) { - //float corr[samples_per_frame]; - for (int ind=0; ind<3; ind++) { - /* - if (pss_corr_ue[ind]) { - for (i=0; ichest_t,time,corr,samples_per_frame,"","",""); - else - fl_add_xyplot_overlay(form->chest_t,ind,time,corr,samples_per_frame,rx_antenna_colors[ind]); - - overlay = 1; - } - */ - } - - // if the UE is not synchronized, we can make only the time*power graph - } + genericLogPowerPerAntena(graph, phy_vars_ue->frame_parms.nb_antennas_rx, + (const scopeSample_t **) phy_vars_ue->common_vars.rxdata, + phy_vars_ue->frame_parms.samples_per_frame); } -static void ueChannelResponse (FL_OBJECT *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { +static void ueChannelResponse (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { // Channel Impulse Response - if (!phy_vars_ue->pbch_vars[eNB_id]->dl_ch_estimates_time) - return; - - NR_DL_FRAME_PARMS *frame_parms = &phy_vars_ue->frame_parms; - uint8_t nb_antennas_rx = frame_parms->nb_antennas_rx; - scopeSample_t **chest_t = (scopeSample_t **) phy_vars_ue->pbch_vars[eNB_id]->dl_ch_estimates_time; - int ymax = 0; - float chest_t_abs[frame_parms->ofdm_symbol_size]; - float time[frame_parms->ofdm_symbol_size>>3]; - - if (chest_t[0] !=NULL) { - for (int i=0; i<(frame_parms->ofdm_symbol_size>>3); i++) { - chest_t_abs[i] = SquaredNorm(chest_t[0][i]); - time[i] = (float) i; - - if (chest_t_abs[i] > ymax) - ymax = chest_t_abs[i]; - } - - fl_set_xyplot_data(graph,time,chest_t_abs,(frame_parms->ofdm_symbol_size>>3),"","",""); - } - - for (int arx=1; arxofdm_symbol_size>>3); i++) { - chest_t_abs[i] = SquaredNorm(chest_t[arx][i]); - - if (chest_t_abs[i] > ymax) - ymax = chest_t_abs[i]; - } - - fl_add_xyplot_overlay(graph,arx,time,chest_t_abs,(frame_parms->ofdm_symbol_size>>3),rx_antenna_colors[arx]); - fl_set_xyplot_overlay_type(graph,arx,FL_DASHED_XYPLOT); - } - } - - // Avoid flickering effect - // fl_get_xyplot_ybounds(form->chest_t,&ymin,&ymax); // Does not always work... - fl_set_xyplot_ybounds(graph,0,(double) ymax); + genericPowerPerAntena(graph, phy_vars_ue->frame_parms.nb_antennas_rx, + (const scopeSample_t **) phy_vars_ue->pbch_vars[eNB_id]->dl_ch_estimates_time, + phy_vars_ue->frame_parms.ofdm_symbol_size>>3); } -static void uePbchFrequencyResp (FL_OBJECT *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { +static void uePbchFrequencyResp (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { // Channel Frequency Response (includes 5 complex sample for filter) if (!phy_vars_ue->pbch_vars[eNB_id]->dl_ch_estimates) return; @@ -575,10 +467,10 @@ static void uePbchFrequencyResp (FL_OBJECT *graph, PHY_VARS_NR_UE *phy_vars_ue, //fl_set_xyplot_xtics(form->chest_f,nb_antennas_rx*nb_antennas_tx*frame_parms->symbols_per_tti,2); // fl_set_xyplot_xtics(form->chest_f,nb_antennas_rx*nb_antennas_tx*2,2); //fl_set_xyplot_xgrid(form->chest_f,FL_GRID_MAJOR); - fl_set_xyplot_data(graph,freq,chest_f_abs,frame_parms->ofdm_symbol_size,"","",""); + oai_xygraph(graph,freq,chest_f_abs,frame_parms->ofdm_symbol_size,0,10); } -static void uePbchLLR (FL_OBJECT *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { +static void uePbchLLR (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { // PBCH LLRs if ( !phy_vars_ue->pbch_vars[eNB_id]->llr) return; @@ -591,15 +483,15 @@ static void uePbchLLR (FL_OBJECT *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_i bit_pbch[i] = (float) i; } - fl_set_xyplot_data(graph,bit_pbch,llr_pbch,864,"","",""); + oai_xygraph(graph,bit_pbch,llr_pbch,864,0,10); } -static void uePbchIQ (FL_OBJECT *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { +static void uePbchIQ (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { // PBCH I/Q of MF Output if (!phy_vars_ue->pbch_vars[eNB_id]->rxdataF_comp[0]) return; - int16_t *pbch_comp = (int16_t *) phy_vars_ue->pbch_vars[eNB_id]->rxdataF_comp[0]; + scopeSample_t *pbch_comp = (scopeSample_t *) phy_vars_ue->pbch_vars[eNB_id]->rxdataF_comp[0]; localBuff(I,180*3); localBuff(Q,180*3); int first_symbol=1; @@ -616,17 +508,17 @@ static void uePbchIQ (FL_OBJECT *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id AssertFatal(base+nb_re<180*3,""); for (int i=0; ipdcch_vars[0][eNB_id]->llr) return; @@ -656,34 +548,34 @@ static void uePcchLLR (FL_OBJECT *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_i //fl_set_xyplot_xtics(form->chest_f,nb_antennas_rx*nb_antennas_tx*frame_parms->symbols_per_tti,2); // fl_set_xyplot_xtics(form->chest_f,nb_antennas_rx*nb_antennas_tx*2,2); //fl_set_xyplot_xgrid(form->chest_f,FL_GRID_MAJOR); - fl_set_xyplot_data(graph,freq,chest_f_abs,frame_parms->ofdm_symbol_size,"","",""); + oai_xygraph(graph,freq,chest_f_abs,frame_parms->ofdm_symbol_size,0,10); } -static void uePcchIQ (FL_OBJECT *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { +static void uePcchIQ (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { // PDCCH I/Q of MF Output if (!phy_vars_ue->pdcch_vars[0][eNB_id]->rxdataF_comp[0]) return; - int nb=12*273*4; // 12*frame_parms->N_RB_DL*num_pdcch_symbols + int nb=4*273*12; // 12*frame_parms->N_RB_DL*num_pdcch_symbols localBuff(I,nb*RX_NB_TH_MAX); localBuff(Q,nb*RX_NB_TH_MAX); int base=0; for (int thr=0 ; thr < RX_NB_TH_MAX ; thr ++ ) { - int16_t *pdcch_comp = (int16_t *) phy_vars_ue->pdcch_vars[thr][eNB_id]->rxdataF_comp[0]; + scopeSample_t *pdcch_comp = (scopeSample_t *) phy_vars_ue->pdcch_vars[thr][eNB_id]->rxdataF_comp[0]; for (int i=0; i< nb; i++) { - I[base+i] = pdcch_comp[i*2]; - Q[base+i] = pdcch_comp[i*2+1]; + I[base+i] = pdcch_comp[i].r; + Q[base+i] = pdcch_comp[i].i; } base+=nb; } - fl_set_xyplot_data(graph,I,Q,base,"","",""); + oai_xygraph(graph,I,Q,base,0,10); } -static void uePdschLLR (FL_OBJECT *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { +static void uePdschLLR (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { // PDSCH LLRs if (!phy_vars_ue->pdsch_vars[0][eNB_id]->llr[0]) return; @@ -707,10 +599,10 @@ static void uePdschLLR (FL_OBJECT *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_ } //fl_set_xyplot_xbounds(form->pdsch_llr,0,coded_bits_per_codeword); - fl_set_xyplot_data(graph,bit,llr,base,"","",""); + oai_xygraph(graph,bit,llr,base,0,10); } -static void uePdschIQ (FL_OBJECT *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { +static void uePdschIQ (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { // PDSCH I/Q of MF Output if (!phy_vars_ue->pdsch_vars[0][eNB_id]->rxdataF_comp0[0]) return; @@ -722,17 +614,20 @@ static void uePdschIQ (FL_OBJECT *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_i int base=0; for (int thr=0 ; thr < RX_NB_TH_MAX ; thr ++ ) { - int16_t *pdsch_comp = (int16_t *) phy_vars_ue->pdsch_vars[thr][eNB_id]->rxdataF_comp0[0]; + scopeSample_t *pdsch_comp = (scopeSample_t *) phy_vars_ue->pdsch_vars[thr][eNB_id]->rxdataF_comp0[0]; for (int s=0; sphy_scope = fl_bgn_form( FL_NO_BOX, 800, 900 ); // This the whole UI box obj = fl_add_box( FL_BORDER_BOX, 0, 0, 800, 900, "" ); fl_set_object_color( obj, FL_BLACK, FL_BLACK ); + int curY=0,x,y,w,h; // Received signal fdui->graph[0] = nrUEcommonGraph(ueTimeResponse, - FL_IMPULSE_XYPLOT, 20, 20, 370, 100, "Received Signal (Time-Domain, dB)", FL_RED ); + FL_NORMAL_XYPLOT, 0, curY, 400, 100, "Received Signal (Time-Domain, dB)", FL_RED ); // Time-domain channel response fdui->graph[1] = nrUEcommonGraph(ueChannelResponse, - FL_NORMAL_XYPLOT, 410, 20, 370, 100, "Channel Impulse Response (samples, abs)", FL_RED ); + FL_NORMAL_XYPLOT, 400, curY, 400, 100, "Channel Impulse Response (samples, abs)", FL_RED ); + fl_get_object_bbox(fdui->graph[0].graph,&x, &y,&w, &h); + curY+=h; // Frequency-domain channel response fdui->graph[2] = nrUEcommonGraph(uePbchFrequencyResp, - FL_IMPULSE_XYPLOT, 20, 140, 760, 100, "Channel Frequency data (RE, dB)", FL_RED ); + FL_IMPULSE_XYPLOT, 0, curY, 800, 100, "Channel Frequency data (RE, dB)", FL_RED ); + fl_get_object_bbox(fdui->graph[2].graph,&x, &y,&w, &h); + curY+=h; // LLR of PBCH fdui->graph[3] = nrUEcommonGraph(uePbchLLR, - FL_POINTS_XYPLOT, 20, 260, 500, 100, "PBCH Log-Likelihood Ratios (LLR, mag)", FL_GREEN ); + FL_POINTS_XYPLOT, 0, curY, 500, 100, "PBCH Log-Likelihood Ratios (LLR, mag)", FL_GREEN ); fl_set_xyplot_xgrid(fdui->graph[3].graph,FL_GRID_MAJOR); // I/Q PBCH comp fdui->graph[4] = nrUEcommonGraph(uePbchIQ, - FL_POINTS_XYPLOT, 540, 260, 240, 100, "PBCH I/Q of MF Output", FL_GREEN ); + FL_POINTS_XYPLOT, 500, curY, 300, 100, "PBCH I/Q of MF Output", FL_GREEN ); + fl_get_object_bbox(fdui->graph[3].graph,&x, &y,&w, &h); + curY+=h; // LLR of PDCCH fdui->graph[5] = nrUEcommonGraph(uePcchLLR, - FL_POINTS_XYPLOT, 20, 380, 500, 100, "PDCCH Log-Likelihood Ratios (LLR, mag)", FL_CYAN ); + FL_POINTS_XYPLOT, 0, curY, 500, 100, "PDCCH Log-Likelihood Ratios (LLR, mag)", FL_CYAN ); // I/Q PDCCH comp fdui->graph[6] = nrUEcommonGraph(uePcchIQ, - FL_POINTS_XYPLOT, 540, 380, 240, 100, "PDCCH I/Q of MF Output", FL_CYAN ); + FL_POINTS_XYPLOT, 500, curY, 300, 100, "PDCCH I/Q of MF Output", FL_CYAN ); + fl_get_object_bbox(fdui->graph[5].graph,&x, &y,&w, &h); + curY+=h; // LLR of PDSCH fdui->graph[7] = nrUEcommonGraph(uePdschLLR, - FL_POINTS_XYPLOT, 20, 500, 500, 200, "PDSCH Log-Likelihood Ratios (LLR, mag)", FL_YELLOW ); + FL_POINTS_XYPLOT, 0, curY, 500, 200, "PDSCH Log-Likelihood Ratios (LLR, mag)", FL_YELLOW ); // I/Q PDSCH comp fdui->graph[8] = nrUEcommonGraph(uePdschIQ, - FL_POINTS_XYPLOT, 540, 500, 240, 200, "PDSCH I/Q of MF Output", FL_YELLOW ); + FL_POINTS_XYPLOT, 500, curY, 300, 200, "PDSCH I/Q of MF Output", FL_YELLOW ); + fl_get_object_bbox(fdui->graph[8].graph,&x, &y,&w, &h); + curY+=h; // Throughput on PDSCH fdui->graph[9] = nrUEcommonGraph(uePdschThroughput, - FL_NORMAL_XYPLOT, 20, 720, 500, 100, "PDSCH Throughput [frame]/[kbit/s]", FL_WHITE ); + FL_NORMAL_XYPLOT, 0, curY, 500, 100, "PDSCH Throughput [frame]/[kbit/s]", FL_WHITE ); fdui->graph[10].graph=NULL; // Generic UE Button +#if 0 fdui->button_0 = fl_add_button( FL_PUSH_BUTTON, 540, 720, 240, 40, "" ); fl_set_object_lalign(fdui->button_0, FL_ALIGN_CENTER ); //openair_daq_vars.use_ia_receiver = 0; @@ -804,6 +708,7 @@ static FD_phy_scope_t *create_phy_scope_nrue( int ID ) { fl_set_object_color(fdui->button_0, FL_RED, FL_RED); fl_set_object_callback(fdui->button_0, ia_receiver_on_off, 0 ); fl_hide_object(fdui->button_0); +#endif fl_end_form( ); fdui->phy_scope->fdui = fdui; char buf[100]; @@ -812,11 +717,11 @@ static FD_phy_scope_t *create_phy_scope_nrue( int ID ) { return fdui; } -void phy_scope_nrUE(FD_phy_scope_t *form, +void phy_scope_nrUE(OAI_phy_scope_t *form, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) { - static FD_phy_scope_t *remeberForm=NULL; + static OAI_phy_scope_t *remeberForm=NULL; if (form==NULL) form=remeberForm; @@ -829,15 +734,13 @@ void phy_scope_nrUE(FD_phy_scope_t *form, int i=0; while (form->graph[i].graph) { - form->graph[i].nrUEfunct(form->graph[i].graph, phy_vars_ue, eNB_id, UE_id); + form->graph[i].nrUEfunct(form->graph+i, phy_vars_ue, eNB_id, UE_id); i++; } fl_check_forms(); } -static FD_phy_scope_t *form_nrue[NUMBER_OF_UE_MAX]; -static pthread_t forms_thread; static void *nrUEscopeThread(void *arg) { PHY_VARS_NR_UE *ue=(PHY_VARS_NR_UE *)arg; @@ -845,9 +748,13 @@ static void *nrUEscopeThread(void *arg) { pthread_attr_t atr; pthread_attr_getstacksize(&atr, &stksize); pthread_attr_setstacksize(&atr,32*1024*1024 ); + int fl_argc=1; + char *name="5G-UE-scope"; + fl_initialize (&fl_argc, &name, NULL, 0, 0); + OAI_phy_scope_t *form_nrue=create_phy_scope_nrue(0); while (!oai_exit) { - phy_scope_nrUE(form_nrue[0], + phy_scope_nrUE(form_nrue, ue, 0,0); usleep(99*1000); @@ -857,10 +764,7 @@ static void *nrUEscopeThread(void *arg) { } void nrUEinitScope(PHY_VARS_NR_UE *ue) { - int fl_argc=1; - char *name="5G-UE-scope"; - fl_initialize (&fl_argc, &name, NULL, 0, 0); - form_nrue[0] = create_phy_scope_nrue(0); + pthread_t forms_thread; threadCreate(&forms_thread, nrUEscopeThread, ue, "scope", -1, OAI_PRIORITY_RT_LOW); } @@ -893,7 +797,7 @@ static void reset_stats_gNB(FL_OBJECT *button, static FD_stats_form *create_form_stats_form(int ID) { FL_OBJECT *obj; - FD_stats_form *fdui = fl_malloc( sizeof *fdui ); + FD_stats_form *fdui = calloc(( sizeof *fdui ),1); fdui->vdata = fdui->cdata = NULL; fdui->ldata = 0; fdui->stats_form = fl_bgn_form( FL_NO_BOX, 1115, 900 ); diff --git a/openair1/PHY/TOOLS/nr_phy_scope.h b/openair1/PHY/TOOLS/nr_phy_scope.h index cf28680a94..429537141a 100644 --- a/openair1/PHY/TOOLS/nr_phy_scope.h +++ b/openair1/PHY/TOOLS/nr_phy_scope.h @@ -28,7 +28,6 @@ #include #include "common/ran_context.h" #include -#include #include "PHY/defs_gNB.h" //#include "PHY/defs_nrUE.h" //#include "PHY/impl_defs_top.h" diff --git a/openair1/SCHED_NR/phy_frame_config_nr.h b/openair1/SCHED_NR/phy_frame_config_nr.h index d1ec5c80d8..e17638f7f3 100644 --- a/openair1/SCHED_NR/phy_frame_config_nr.h +++ b/openair1/SCHED_NR/phy_frame_config_nr.h @@ -32,6 +32,7 @@ #ifndef PHY_FRAME_CONFIG_NR_H #define PHY_FRAME_CONFIG_NR_H +#include /************** DEFINE ********************************************/ #define TDD_CONFIG_NB_FRAMES (2) @@ -79,6 +80,7 @@ int set_tdd_configuration_dedicated_nr(NR_DL_FRAME_PARMS *frame_parms); @returns nr_slot_t : downlink or uplink */ nr_slot_t nr_slot_select(nfapi_nr_config_request_scf_t *cfg, int nr_frame, int nr_tti); +int nr_ue_slot_select(fapi_nr_config_request_t *cfg, int nr_frame, int nr_tti); /** \brief This function frees tdd configuration for nr * @param frame_parms NR DL Frame parameters diff --git a/openair2/LAYER2/NR_MAC_UE/mac_proto.h b/openair2/LAYER2/NR_MAC_UE/mac_proto.h index 38c9244014..760ff9386c 100755 --- a/openair2/LAYER2/NR_MAC_UE/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_proto.h @@ -263,5 +263,6 @@ void nr_Msg1_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id); +void nr_ue_msg2_scheduler(module_id_t mod_id, uint16_t rach_frame, uint16_t rach_slot, uint16_t *msg2_frame, uint16_t *msg2_slot); #endif /** @}*/ diff --git a/openair2/LAYER2/NR_MAC_UE/main_ue_nr.c b/openair2/LAYER2/NR_MAC_UE/main_ue_nr.c index 61f9ab601e..c5154d7a1f 100644 --- a/openair2/LAYER2/NR_MAC_UE/main_ue_nr.c +++ b/openair2/LAYER2/NR_MAC_UE/main_ue_nr.c @@ -50,7 +50,7 @@ NR_UE_MAC_INST_t * nr_l2_init_ue(NR_UE_RRC_INST_t* rrc_inst) //LOG_I(MAC, "[MAIN] init UE MAC functions \n"); //init mac here - nr_ue_mac_inst = (NR_UE_MAC_INST_t *)malloc(sizeof(NR_UE_MAC_INST_t)*NB_NR_UE_MAC_INST); + nr_ue_mac_inst = (NR_UE_MAC_INST_t *)calloc(sizeof(NR_UE_MAC_INST_t),NB_NR_UE_MAC_INST); if (rrc_inst) { nr_rrc_mac_config_req_ue(0,0,0,NULL,rrc_inst->cell_group_config->spCellConfig); diff --git a/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c b/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c index 9d7f3264c5..f8bb1e5f8e 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c @@ -91,8 +91,8 @@ int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id, uint16_t prach_forma prachConfigIndex = nr_rach_ConfigCommon->rach_ConfigGeneric.prach_ConfigurationIndex; if (prach_sequence_length == 0) { + AssertFatal(prach_format < 4, "Illegal PRACH format %d for sequence length 839\n", prach_format); switch (prach_format) { - AssertFatal(prach_format < 4, "Illegal PRACH format %d for sequence length 839\n", prach_format); // long preamble formats case 0: diff --git a/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c b/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c index bfd2d3dbeb..31a865f317 100644 --- a/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c +++ b/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c @@ -44,6 +44,7 @@ #include "NR_MAC_UE/mac.h" #include "NR_MAC_UE/mac_proto.h" #include "NR_MAC_COMMON/nr_mac_extern.h" +#include #define DEBUG_RAR diff --git a/openair2/LAYER2/PDCP_v10.1.0/pdcp.h b/openair2/LAYER2/PDCP_v10.1.0/pdcp.h index 8e265e8cf1..de8a1b385b 100644 --- a/openair2/LAYER2/PDCP_v10.1.0/pdcp.h +++ b/openair2/LAYER2/PDCP_v10.1.0/pdcp.h @@ -34,10 +34,6 @@ #ifndef __PDCP_H__ # define __PDCP_H__ //----------------------------------------------------------------------------- -#ifndef NON_ACCESS_STRATUM - #include "UTIL/MEM/mem_block.h" - #include "UTIL/LISTS/list.h" -#endif //NON_ACCESS_STRATUM //----------------------------------------------------------------------------- #include "RRC/LTE/rrc_defs.h" #include "COMMON/platform_constants.h" diff --git a/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c b/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c index 14d95b15b3..6c23332687 100644 --- a/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c +++ b/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c @@ -55,7 +55,6 @@ extern int otg_enabled; #include "common/utils/LOG/log.h" #include "UTIL/OTG/otg_tx.h" #include "nfapi/oai_integration/vendor_ext.h" -#include "UTIL/FIFO/pad_list.h" #include "common/utils/LOG/vcd_signal_dumper.h" #include "platform_constants.h" #include "msc.h" @@ -91,7 +90,6 @@ extern struct msghdr nas_msg_rx; extern uint16_t inst_pdcp_list[NUMBER_OF_UE_MAX]; #endif -extern Packet_OTG_List_t *otg_pdcp_buffer; # include "gtpv1u_eNB_task.h" @@ -122,7 +120,6 @@ int pdcp_fifo_flush_sdus(const protocol_ctxt_t *const ctxt_pP) { int sizeToWrite= sizeof (pdcp_data_ind_header_t) + pdcpHead->data_size; void * pdcpData=(void*)(pdcpHead+1); - if (rb_id == 10) { //hardcoded for PC5-Signaling if( LOG_DEBUGFLAG(DEBUG_PDCP) ) { debug_pdcp_pc5s_sdu((sidelink_pc5s_element *)pdcpData, From ebbff46cde9e2889ddce1656ae60d4dc5839399f Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Wed, 24 Jun 2020 11:58:41 +0200 Subject: [PATCH 372/553] update 3 after review --- ci-scripts/cls_physim.py | 11 ++++++++--- ci-scripts/main.py | 8 ++++++++ ci-scripts/xml_files/ldpc_gpu_test.xml | 1 + 3 files changed, 17 insertions(+), 3 deletions(-) diff --git a/ci-scripts/cls_physim.py b/ci-scripts/cls_physim.py index 09ed1c8363..4ca36b8cf0 100644 --- a/ci-scripts/cls_physim.py +++ b/ci-scripts/cls_physim.py @@ -51,6 +51,7 @@ class PhySim: self.ranAllowMerge= "" self.ranTargetBranch= "" self.exitStatus=0 + self.forced_workspace_cleanup=False #private attributes self.__workSpacePath='' self.__buildLogFile='compile_phy_sim.log' @@ -75,7 +76,7 @@ class PhySim: for line in f: if 'mean' in line: self.__runResults.append(line) - #the value are appended for each mean value (2), so we take these 2 values from the list + #the values are appended for each mean value (2), so we take these 2 values from the list info=self.__runResults[0]+self.__runResults[1] #once parsed move the local logfile to its folder for tidiness @@ -138,8 +139,12 @@ class PhySim: mySSH.command('git config user.email "jenkins@openairinterface.org"', '\$', 5) mySSH.command('git config user.name "OAI Jenkins"', '\$', 5) - #git clean - mySSH.command('echo ' + self.eNBPassWord + ' | sudo -S git clean -x -d -ff', '\$', 30) + #git clean depending on self.forced_workspace_cleanup captured in xml + if self.forced_workspace_cleanup==True: + logging.info('Cleaning workspace ...') + mySSH.command('echo ' + self.eNBPassWord + ' | sudo -S git clean -x -d -ff', '\$', 30) + else: + logging.info('Workspace cleaning was disabled') # if the commit ID is provided, use it to point to it if self.ranCommitID != '': diff --git a/ci-scripts/main.py b/ci-scripts/main.py index a1c1ac7ec0..b105c19f13 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -3211,6 +3211,14 @@ def GetParametersFromXML(action): if action == 'Build_PhySim': ldpc.buildargs = test.findtext('physim_build_args') + forced_workspace_cleanup = test.findtext('forced_workspace_cleanup') + if (forced_workspace_cleanup is None): + ldpc.forced_workspace_cleanup=False + else: + if re.match('true', forced_workspace_cleanup, re.IGNORECASE): + ldpc.forced_workspace_cleanup=True + else: + ldpc.forced_workspace_cleanup=False if action == 'Run_PhySim': ldpc.runargs = test.findtext('physim_run_args') diff --git a/ci-scripts/xml_files/ldpc_gpu_test.xml b/ci-scripts/xml_files/ldpc_gpu_test.xml index 029c49ecf5..136cd72b1e 100644 --- a/ci-scripts/xml_files/ldpc_gpu_test.xml +++ b/ci-scripts/xml_files/ldpc_gpu_test.xml @@ -33,6 +33,7 @@ Build_PhySim Build for physical simulator --phy_simulators --ninja + TRUE From 03d9bca1011663d1316728c51752339f4f08b44c Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Wed, 24 Jun 2020 16:45:08 +0200 Subject: [PATCH 373/553] Update TESTING_GNB_W_COTS_UE.md --- doc/TESTING_GNB_W_COTS_UE.md | 171 ++++++++++++++++++++++++++++------- 1 file changed, 139 insertions(+), 32 deletions(-) diff --git a/doc/TESTING_GNB_W_COTS_UE.md b/doc/TESTING_GNB_W_COTS_UE.md index 3aad387465..cd2da4eda5 100644 --- a/doc/TESTING_GNB_W_COTS_UE.md +++ b/doc/TESTING_GNB_W_COTS_UE.md @@ -35,9 +35,6 @@ for reference: https://github.com/OPENAIRINTERFACE/openair-epc-fed/blob/master-documentation/docs/DEPLOY_HOME.md -``` -sudo -``` - **eNB** @@ -51,44 +48,136 @@ sudo sudo ``` -## Conf Files +## Configuration Files + +Each component (EPC, eNB, gNB) has its own configuration file. +These config files are passed as arguments of the run command line, using the option -O \ + +Some config examples can be found in the following folder: +https://gitlab.eurecom.fr/oai/openairinterface5g/-/tree/develop/targets/PROJECTS/GENERIC-LTE-EPC/CONF + +These files have to be updated manually to set the IP addresses and frequency. + +1- In the **eNB configuration file** : +- look for MME IP address, and update the **ipv4 field** with the IP address of the **EPC** server +``` + ////////// MME parameters: + mme_ip_address = ( { ipv4 = "**YOUR_EPC_IP_ADDR**"; + ipv6 = "192:168:30::17"; + active = "yes"; + preference = "ipv4"; + } + ); + +``` + +- look for S1 IP address, and update the **3 fields below** with the IP address of the **eNB** server +``` + NETWORK_INTERFACES : + { + ENB_INTERFACE_NAME_FOR_S1_MME = "eth0"; + ENB_IPV4_ADDRESS_FOR_S1_MME = "**YOUR_ENB_IP_ADDR**"; + ENB_INTERFACE_NAME_FOR_S1U = "eth0"; + ENB_IPV4_ADDRESS_FOR_S1U = "**YOUR_ENB_IP_ADDR**"; + ENB_PORT_FOR_S1U = 2152; # Spec 2152 + ENB_IPV4_ADDRESS_FOR_X2C = "**YOUR_ENB_IP_ADDR**"; + ENB_PORT_FOR_X2C = 36422; # Spec 36422 + }; + +``` + +2- In the **gNB configuration file** : +- look for MME IP address, and update the **ipv4 field** with the IP address of the **EPC** server +``` + ////////// MME parameters: + mme_ip_address = ( { ipv4 = "**YOUR_EPC_IP_ADDR**"; + ipv6 = "192:168:30::17"; + active = "yes"; + preference = "ipv4"; + } + ); +``` +- look for X2 IP address, and update the **4 fields** with the IP address of the **eNB** server (notice : even if -in principle- S1 MME is not required for gNB setting) +``` + + ///X2 + enable_x2 = "yes"; + t_reloc_prep = 1000; /* unit: millisecond */ + tx2_reloc_overall = 2000; /* unit: millisecond */ + target_enb_x2_ip_address = ( + { ipv4 = "**YOUR_ENB_IP_ADDR**"; + ipv6 = "192:168:30::17"; + preference = "ipv4"; + } + ); + + NETWORK_INTERFACES : + { + + GNB_INTERFACE_NAME_FOR_S1_MME = "eth0"; + GNB_IPV4_ADDRESS_FOR_S1_MME = "**YOUR_ENB_IP_ADDR**"; + GNB_INTERFACE_NAME_FOR_S1U = "eth0"; + GNB_IPV4_ADDRESS_FOR_S1U = "**YOUR_ENB_IP_ADDR**"; + GNB_PORT_FOR_S1U = 2152; # Spec 2152 + GNB_IPV4_ADDRESS_FOR_X2C = "**YOUR_ENB_IP_ADDR**"; + GNB_PORT_FOR_X2C = 36422; # Spec 36422 + }; + + +``` + + + +3- The frequency setting requires a manual update in the .C and in the gNB conf file: + + +In the C file **openair2/RRC/LTE/rrc_eNB.c:3217** +set the nrarfcn to the same value as absoluteFrequencySSB in the **gNB config file**, that is **641272** in the example below + +C file : +``` +MeasObj2->measObject.choice.measObjectNR_r15.carrierFreq_r15 =641272; +``` + +gNB config file : + +``` + # absoluteFrequencySSB is the central frequency of SSB + absoluteFrequencySSB = 641272; + dl_frequencyBand = 78; + # the carrier frequency is assumed to be in the middle of the carrier, i.e. dl_absoluteFrequencyPointA_kHz + dl_carrierBandwidth*12*SCS_kHz/2 + dl_absoluteFrequencyPointA = 640000; + #scs-SpecificCarrierList + dl_offstToCarrier = 0; + # subcarrierSpacing + # 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + dl_subcarrierSpacing = 1; + dl_carrierBandwidth = 106; +``` -where are the config files located -how to use them ## Run / Test - **EPC** (on EPC host): -``` -sudo -``` +for reference: +https://github.com/OPENAIRINTERFACE/openair-epc-fed/blob/master-documentation/docs/DEPLOY_HOME.md -Open another window and: - -``` -sudo bash -cd /opt/ltebox/tools - -``` - -Note: when terminated the testing session, you shall stop the EPC by "./stop_ltebox" - **eNB** (on the eNB host): +``` ~/openairinterface5g/cmake_targets/ran_build/build$ sudo ./lte-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.band7.tm1.50PRB.usrpb210.conf (-E) - - -eNB is using branch NR_RRCConfiguration patched with enb.diff +``` - **gNB** (on the gNB host) +``` ~/openairinterface5g/cmake_targets/ran_build/build$ sudo ./nr-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf (-E) - -Note: gNB is using branch NR_RRC_PRACH_procedures patched with gnb.diff +``` ## Test Case @@ -97,20 +186,38 @@ Test case description : UE attachement ## Expected Logs to check -what logs and where to check, to ensure that your setup works fine +what logs and where to check, to ensure that your setup works fine (or not ...) ## Required traces for debug What info/traces/logs are needed for us to support the debug ## Status of the interoperability -- setup of the CP in 4G -- setup of the measurements in 5G -- Random access procedure initiation by the UE in the 5G cell -- msg1, msg2, msg3 correctly exchanged and decoded + +The following parts have been validated with FR1 COTS UE: + +- Phone accepts the configurtion provided by OAI eNB: + this validates RRC and X2AP + +- Successful Random Access Procedure: + PRACH is correctly decoded at gNB + Phone correctly receives and decodes msg2 (NR PDCCH Format 1_0 and NR PDSCH) + msg3 is transmitted to gNB according to the configuration sent in msg2, and received correctly at gNB + +- Successful path switch of user plane traffic from 4G to 5G cell (E-RAB modification message): + this validates S1AP + +- Downlink traffic: + PDCCH DCI format 1_1 and correponding PDSCH are decoded correctlyby the phone + ACK/NACK (PUCCH format 0) are successfully received at gNB + +- On going: + validation of HARQ procedures + Integration with higher layers to replace dummy data with real traffic + +- Known limitations as of May 2020: + only dummy DL traffic + no UL traffic + no end-to-end traffic possible -[enb.conf](uploads/48bbbcc8016a33ce6d2faf62e3845005/enb.conf) -[enb.diff](uploads/9763bd6d18256612d007251bc371ca46/enb.diff) -[gnb.conf](uploads/59ae03deccb2186f544451034c297838/gnb.conf) -[gnb.diff](uploads/bb756b2b165cb70f89405d7a8c4c36a8/gnb.diff) \ No newline at end of file From f79f6351d8737652a6af48fbe6e79a1b9d3f1024 Mon Sep 17 00:00:00 2001 From: hardy Date: Thu, 25 Jun 2020 09:58:08 +0200 Subject: [PATCH 374/553] uploading fr1 setup lab photo --- .../oai_fr1_lab.jpg | Bin 0 -> 307236 bytes 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100755 doc/testing_gnb_w_cots_ue_resources/oai_fr1_lab.jpg diff --git a/doc/testing_gnb_w_cots_ue_resources/oai_fr1_lab.jpg b/doc/testing_gnb_w_cots_ue_resources/oai_fr1_lab.jpg new file mode 100755 index 0000000000000000000000000000000000000000..8c6e08b2e155aaadfc0bdb2dfe6203e4f86cab41 GIT binary patch literal 307236 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z_>bmnHhxez+E1yXioMC|0$hW&Rhzl?sQ3J*18`Bv^#1@jqKeC*L6Zvg+mq?}(8Y?W zJe&s4PxHkTQ;7phtdIALaC62EJt-9gjkl>o%Krd`6jLmWDyYh@%aiY%bsw!GsEIT8 zcnl6t89(GvMIw5OwR5?CWhb85KTpb$)uNksA9pyw>Hh%M#S~UG4XMR9saNbx{{TIk S{`mg@>(NCOpDC}iiT~MoB_g;0 From 55828cbbabd2aa224dff6d7b67bfebe41741d3d8 Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Thu, 25 Jun 2020 12:16:48 +0200 Subject: [PATCH 377/553] Update TESTING_GNB_W_COTS_UE.md --- doc/TESTING_GNB_W_COTS_UE.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/doc/TESTING_GNB_W_COTS_UE.md b/doc/TESTING_GNB_W_COTS_UE.md index a6a45c0a97..cc58600904 100644 --- a/doc/TESTING_GNB_W_COTS_UE.md +++ b/doc/TESTING_GNB_W_COTS_UE.md @@ -23,6 +23,9 @@ The scheme below depicts our typical setup: ![image info](./testing_gnb_w_cots_ue_resources/oai_fr1_setup.jpg) +The photo depicts the FR1 setup part of the scheme above: + + ![image info](./testing_gnb_w_cots_ue_resources/oai_fr1_lab.jpg) ## Build / Install From 0553332b26c25960730adb13cba633d2440a1172 Mon Sep 17 00:00:00 2001 From: matzakos Date: Thu, 25 Jun 2020 18:47:10 +0200 Subject: [PATCH 378/553] Bring back default RB configuration as it is required for phytest mode --- openair2/RRC/NR/rrc_gNB_nsa.c | 6 +++- openair2/RRC/NR/rrc_gNB_reconfig.c | 47 ++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+), 1 deletion(-) diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c index e32d350294..0bdfb274ea 100644 --- a/openair2/RRC/NR/rrc_gNB_nsa.c +++ b/openair2/RRC/NR/rrc_gNB_nsa.c @@ -38,6 +38,7 @@ #include "NR_CG-Config.h" #include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h" #include "openair2/RRC/LTE/rrc_eNB_GTPV1U.h" +#include "executables/softmodem-common.h" void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList, x2ap_ENDC_sgnb_addition_req_t *m, NR_CG_ConfigInfo_IEs_t *cg_config_info) { struct rrc_gNB_ue_context_s *ue_context_p = NULL; @@ -133,6 +134,10 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_ NR_RRCReconfiguration_IEs_t *reconfig_ies=calloc(1,sizeof(NR_RRCReconfiguration_IEs_t)); ue_context_p->ue_context.reconfig->criticalExtensions.choice.rrcReconfiguration = reconfig_ies; carrier->initial_csi_index[rrc->Nb_ue] = 0; + if (get_softmodem_params()->phy_test == 1 || get_softmodem_params()->do_ra == 1){ + ue_context_p->ue_context.rb_config = calloc(1,sizeof(NR_RRCReconfiguration_t)); + fill_default_rbconfig(ue_context_p->ue_context.rb_config); + } fill_default_reconfig(carrier->servingcellconfigcommon, reconfig_ies, ue_context_p->ue_context.secondaryCellGroup, @@ -170,7 +175,6 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_ create_tunnel_req.sgw_S1u_teid[i]); } - //PM: Is this where we should extract the rnti from? create_tunnel_req.rnti = ue_context_p->ue_id_rnti; create_tunnel_req.num_tunnels = m->nb_e_rabs_tobeadded; RB_INSERT(rrc_nr_ue_tree_s, &RC.nrrrc[rrc->module_id]->rrc_ue_head, ue_context_p); diff --git a/openair2/RRC/NR/rrc_gNB_reconfig.c b/openair2/RRC/NR/rrc_gNB_reconfig.c index 8f93b42ef4..ba1d20e9ab 100644 --- a/openair2/RRC/NR/rrc_gNB_reconfig.c +++ b/openair2/RRC/NR/rrc_gNB_reconfig.c @@ -1918,4 +1918,51 @@ void fill_default_reconfig(NR_ServingCellConfigCommon_t *servingcellconfigcommon // nonCriticalExtension reconfig->nonCriticalExtension = NULL; } + +void fill_default_rbconfig(NR_RadioBearerConfig_t *rbconfig) { + + rbconfig->srb_ToAddModList = NULL; + rbconfig->srb3_ToRelease = NULL; + rbconfig->drb_ToAddModList = calloc(1,sizeof(*rbconfig->drb_ToAddModList)); + NR_DRB_ToAddMod_t *drb_ToAddMod = calloc(1,sizeof(*drb_ToAddMod)); + drb_ToAddMod->cnAssociation = calloc(1,sizeof(*drb_ToAddMod->cnAssociation)); + drb_ToAddMod->cnAssociation->present = NR_DRB_ToAddMod__cnAssociation_PR_eps_BearerIdentity; + drb_ToAddMod->cnAssociation->choice.eps_BearerIdentity=5; + drb_ToAddMod->drb_Identity = 1; + drb_ToAddMod->reestablishPDCP = NULL; + drb_ToAddMod->recoverPDCP = NULL; + drb_ToAddMod->pdcp_Config = calloc(1,sizeof(*drb_ToAddMod->pdcp_Config)); + drb_ToAddMod->pdcp_Config->drb = calloc(1,sizeof(*drb_ToAddMod->pdcp_Config->drb)); + drb_ToAddMod->pdcp_Config->drb->discardTimer = calloc(1,sizeof(*drb_ToAddMod->pdcp_Config->drb->discardTimer)); + *drb_ToAddMod->pdcp_Config->drb->discardTimer=NR_PDCP_Config__drb__discardTimer_ms30; + drb_ToAddMod->pdcp_Config->drb->pdcp_SN_SizeUL = calloc(1,sizeof(*drb_ToAddMod->pdcp_Config->drb->pdcp_SN_SizeUL)); + *drb_ToAddMod->pdcp_Config->drb->pdcp_SN_SizeUL = NR_PDCP_Config__drb__pdcp_SN_SizeUL_len18bits; + drb_ToAddMod->pdcp_Config->drb->pdcp_SN_SizeDL = calloc(1,sizeof(*drb_ToAddMod->pdcp_Config->drb->pdcp_SN_SizeDL)); + *drb_ToAddMod->pdcp_Config->drb->pdcp_SN_SizeDL = NR_PDCP_Config__drb__pdcp_SN_SizeDL_len18bits; + drb_ToAddMod->pdcp_Config->drb->headerCompression.present = NR_PDCP_Config__drb__headerCompression_PR_notUsed; + drb_ToAddMod->pdcp_Config->drb->headerCompression.choice.notUsed = 0; + + drb_ToAddMod->pdcp_Config->drb->integrityProtection=NULL; + drb_ToAddMod->pdcp_Config->drb->statusReportRequired=NULL; + drb_ToAddMod->pdcp_Config->drb->outOfOrderDelivery=NULL; + drb_ToAddMod->pdcp_Config->moreThanOneRLC = NULL; + + drb_ToAddMod->pdcp_Config->t_Reordering = calloc(1,sizeof(*drb_ToAddMod->pdcp_Config->t_Reordering)); + *drb_ToAddMod->pdcp_Config->t_Reordering = NR_PDCP_Config__t_Reordering_ms0; + drb_ToAddMod->pdcp_Config->ext1 = NULL; + + ASN_SEQUENCE_ADD(&rbconfig->drb_ToAddModList->list,drb_ToAddMod); + + rbconfig->drb_ToReleaseList = NULL; + + rbconfig->securityConfig = calloc(1,sizeof(*rbconfig->securityConfig)); + rbconfig->securityConfig->securityAlgorithmConfig = calloc(1,sizeof(*rbconfig->securityConfig->securityAlgorithmConfig)); + rbconfig->securityConfig->securityAlgorithmConfig->cipheringAlgorithm = NR_CipheringAlgorithm_nea0; + rbconfig->securityConfig->securityAlgorithmConfig->integrityProtAlgorithm=NULL; + rbconfig->securityConfig->keyToUse = calloc(1,sizeof(*rbconfig->securityConfig->keyToUse)); + *rbconfig->securityConfig->keyToUse = NR_SecurityConfig__keyToUse_master; + + xer_fprint(stdout, &asn_DEF_NR_RadioBearerConfig, (const void*)rbconfig); +} + #endif From 7c116c7981f1b390b24d897bd6c3842ec347e109 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Fri, 26 Jun 2020 04:23:24 +0200 Subject: [PATCH 379/553] small bugfix in pullarray8 in nfapi.c --- nfapi/open-nFAPI/nfapi/src/nfapi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nfapi/open-nFAPI/nfapi/src/nfapi.c b/nfapi/open-nFAPI/nfapi/src/nfapi.c index 156a48ec05..61c6875bc6 100644 --- a/nfapi/open-nFAPI/nfapi/src/nfapi.c +++ b/nfapi/open-nFAPI/nfapi/src/nfapi.c @@ -526,7 +526,7 @@ uint32_t pullarray8(uint8_t **in, uint8_t out[], uint32_t max_len, uint32_t len, return 0; } - if((end - out) >= sizeof(uint8_t) * len) + if((end - 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TESTING_GNB_W_COTS_UE.md --- doc/TESTING_GNB_W_COTS_UE.md | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/doc/TESTING_GNB_W_COTS_UE.md b/doc/TESTING_GNB_W_COTS_UE.md index cc58600904..8a370b8c35 100644 --- a/doc/TESTING_GNB_W_COTS_UE.md +++ b/doc/TESTING_GNB_W_COTS_UE.md @@ -162,6 +162,16 @@ gNB config file : ## Run / Test +The order to run the different components is important: +1- first, CN +2- then, eNB +3- then, gNB +4- finally, switch UE from airplane mode OFF to ON + +It is recommended to redirect the run commands to the same log file (fur further analysis and debug), using ```| tee **YOUR_LOG_FILE**``` especially for eNB and gNB. +It is not very useful for the CN. + +The test takes typically a few seconds, max 10-15 seconds. If it takes more than 30 seconds, there is a problem. - **EPC** (on EPC host): @@ -172,15 +182,31 @@ https://github.com/OPENAIRINTERFACE/openair-epc-fed/blob/master-documentation/do - **eNB** (on the eNB host): +Execute: ``` -~/openairinterface5g/cmake_targets/ran_build/build$ sudo ./lte-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.band7.tm1.50PRB.usrpb210.conf (-E) +~/openairinterface5g/cmake_targets/ran_build/build$ sudo ./lte-softmodem -O **YOUR_ENB_CONF_FILE** | tee **YOUR_LOG_FILE** + ``` +for example: +``` +~/openairinterface5g/cmake_targets/ran_build/build$ sudo ./lte-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.band7.tm1.50PRB.usrpb210.conf | tee mylogfile.log +``` + + - **gNB** (on the gNB host) + +Execute: ``` -~/openairinterface5g/cmake_targets/ran_build/build$ sudo ./nr-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf (-E) +~/openairinterface5g/cmake_targets/ran_build/build$ sudo ./nr-softmodem -O **YOUR_GNB_CONF_FILE** | tee **YOUR_LOG_FILE** + +``` + +for example: +``` +~/openairinterface5g/cmake_targets/ran_build/build$ sudo ./nr-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf | tee mylogfile.log ``` From 9ef54616feeb63d5025e42458fd8d1a74910c1b5 Mon Sep 17 00:00:00 2001 From: hardy Date: Fri, 26 Jun 2020 10:05:45 +0200 Subject: [PATCH 382/553] upload signaling scheme --- .../attach_signaling_scheme.jpg | Bin 0 -> 48290 bytes 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100755 doc/testing_gnb_w_cots_ue_resources/attach_signaling_scheme.jpg diff --git a/doc/testing_gnb_w_cots_ue_resources/attach_signaling_scheme.jpg b/doc/testing_gnb_w_cots_ue_resources/attach_signaling_scheme.jpg new file mode 100755 index 0000000000000000000000000000000000000000..085c3f8d88ee1caefb2ff12674f3289f579da6aa GIT binary patch literal 48290 zcmeFZ1yo$iwl2J|pn*VecbDMqK^g)CcXt|x#t8%h!8Jf|5<-Ar!QCAK1b250?(%vc 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es~-Hi{9?)N1d0C)mWzOEUvTWP7$|YZ|2F}Z<34Ku literal 0 HcmV?d00001 From f9a2829b447a4d811e2a3597906670ea19df64cf Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Fri, 26 Jun 2020 11:17:36 +0200 Subject: [PATCH 383/553] Update TESTING_GNB_W_COTS_UE.md --- doc/TESTING_GNB_W_COTS_UE.md | 61 +++++++++++++++++++++++++++++------- 1 file changed, 49 insertions(+), 12 deletions(-) diff --git a/doc/TESTING_GNB_W_COTS_UE.md b/doc/TESTING_GNB_W_COTS_UE.md index 8a370b8c35..d203fa68aa 100644 --- a/doc/TESTING_GNB_W_COTS_UE.md +++ b/doc/TESTING_GNB_W_COTS_UE.md @@ -1,6 +1,18 @@ DISCLAIMER : This page is under complete review and update, thanks for your patience -## Configuration Overview: +## Table of Contents ## + +1. [Configuration Overview](#configuration-overview) +2. [SW Repository / Branch](#repository) +3. [Architecture Setup](#architecture-setup) +4. [Build / Install](#build-and-install) +5. [Run / Test](#run-and-test) +6. [Test case](#test-case) +7. [Log file monitoring](#log-file-monitoring) +6. [Required tools for debug](#required-tools-for-debug) +7. [Status of interoperability](#status-of-interoperability) + +## Configuration Overview * Non Standalone (NSA) configuration : initial Control Plane established between UE and RAN eNB, then User Plane established between UE and gNB, Core network is 4G based supporting rel 15 @@ -13,7 +25,7 @@ DISCLAIMER : This page is under complete review and update, thanks for your pati * BW: 40MHz * Antenna scheme: SISO -## SW Repository / Branch +## Repository https://gitlab.eurecom.fr/oai/openairinterface5g/tree/develop @@ -28,7 +40,7 @@ The photo depicts the FR1 setup part of the scheme above: ![image info](./testing_gnb_w_cots_ue_resources/oai_fr1_lab.jpg) -## Build / Install +## Build and Install General guidelines for building : See https://gitlab.eurecom.fr/oai/openairinterface5g/blob/develop/doc/BUILD.md#building-ues-enodeb-and-gnodeb-executables @@ -60,6 +72,8 @@ These config files are passed as arguments of the run command line, using the op Some config examples can be found in the following folder: https://gitlab.eurecom.fr/oai/openairinterface5g/-/tree/develop/targets/PROJECTS/GENERIC-LTE-EPC/CONF +TO DO : attach base confif files + These files have to be updated manually to set the IP addresses and frequency. 1- In the **eNB configuration file** : @@ -160,7 +174,7 @@ gNB config file : ``` -## Run / Test +## Run and Test The order to run the different components is important: 1- first, CN @@ -188,7 +202,7 @@ Execute: ``` -for example: +For example: ``` ~/openairinterface5g/cmake_targets/ran_build/build$ sudo ./lte-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.band7.tm1.50PRB.usrpb210.conf | tee mylogfile.log ``` @@ -204,7 +218,7 @@ Execute: ``` -for example: +For example: ``` ~/openairinterface5g/cmake_targets/ran_build/build$ sudo ./nr-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf | tee mylogfile.log ``` @@ -212,17 +226,40 @@ for example: ## Test Case -Test case description : UE attachement +The test case corresponds to the UE attachement, that is the UE connection and its initial access in 5G, as depicted below: -## Expected Logs to check +**Source** : https://www.sharetechnote.com/html/5G/5G_LTE_Interworking.html -what logs and where to check, to ensure that your setup works fine (or not ...) +![image info](./testing_gnb_w_cots_ue_resources/attach_signaling_scheme.jpg) -## Required traces for debug +The test reaches step **12. E-RAB modifcation confirmation** , eventhough not all the messages will appear in the log file. -What info/traces/logs are needed for us to support the debug +## Log file monitoring -## Status of the interoperability +From the log file that is generated, we can monitor several important steps, to assess that the test was successful: + +Step **6. Random Access Procedure** is successfully reached when the following messages are shown: +[X2AP ... Received elements for X2P] +... +[LSCH received ok] + +The next message to check is: +[DCI type I payload] indicating some DL traffic for signaling + +Eventually, step **12. E-RAB Modification Confirmation** is successfully reached when the following message is visible: +[E-RAB Modification Confirmation], the message is properly received but not treated. + + +TO DO : attach typical succcessful log file as example, add snaps of msg + +## Required tools for debug + +- **Wireshark** to trace X2AP and S1AP protocols +- **Ttracer** for 5G messages +- **GDB debugger** to check function calls + + +## Status of interoperability The following parts have been validated with FR1 COTS UE: From c3ccb6cc1db1f0b86fe174aef8912ded20c4ff69 Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Fri, 26 Jun 2020 11:32:43 +0200 Subject: [PATCH 384/553] Update TESTING_GNB_W_COTS_UE.md --- doc/TESTING_GNB_W_COTS_UE.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/TESTING_GNB_W_COTS_UE.md b/doc/TESTING_GNB_W_COTS_UE.md index d203fa68aa..955afe817a 100644 --- a/doc/TESTING_GNB_W_COTS_UE.md +++ b/doc/TESTING_GNB_W_COTS_UE.md @@ -1,4 +1,4 @@ -DISCLAIMER : This page is under complete review and update, thanks for your patience +STATUS 2020/06/26 : information is up to date, but under continuous improvement ## Table of Contents ## From 0d914eecaefbf2b7ffcb15d3ca220658b2e8e2a3 Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Fri, 26 Jun 2020 11:43:04 +0200 Subject: [PATCH 385/553] Update CONTRIBUTING.md --- CONTRIBUTING.md | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 61e44bdd55..7a8634f468 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -2,13 +2,12 @@ We want to make contributing to this project as easy and transparent as possible. -Please refer to the steps described on our website: [How to contribute to OAI](https://www.openairinterface.org/?page_id=112) - 1. Sign and return a Contributor License Agreement to OAI team. -2. Create an account on [Eurecom GitLab Server](https://gitlab.eurecom.fr). -3. Provide the identifiant of this account to the OAI team (mailto:contact@openairinterface.org) so you have developer rights on this repository. +2. We recommend that you provide us with a professional or student email address +2. Register on [Eurecom GitLab Server](https://gitlab.eurecom.fr/users/sign_in) +3. Provide the OAI team with the **username** of this account to (mailto:contact@openairinterface.org) ; we will give you the developer rights on this repository. 4. The policies are described in these wiki pages: [OAI Policies](https://gitlab.eurecom.fr/oai/openairinterface5g/wikis/oai-policies-home) - - PLEASE DO NOT FORK the OAI repository on your own Eurecom GitLab account. It just eats up space on our servers. + - PLEASE DO NOT FORK the OAI repository on your own Eurecom GitLab account. It just eats up space on our servers. - You can fork onto another hosting system. But we will NOT accept a merge request from a forked repository. * This decision was made for the license reasons. * The Continuous Integration will reject your merge request. From bc6f6a6067a2a69fbcfd65dd08391a944a3ab62f Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Fri, 26 Jun 2020 16:54:56 +0200 Subject: [PATCH 386/553] CI: no workspace clean when running phy-sim Signed-off-by: Raphael Defosseux --- ci-scripts/xml_files/ldpc_gpu_test.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ci-scripts/xml_files/ldpc_gpu_test.xml b/ci-scripts/xml_files/ldpc_gpu_test.xml index 136cd72b1e..a0191fbd76 100644 --- a/ci-scripts/xml_files/ldpc_gpu_test.xml +++ b/ci-scripts/xml_files/ldpc_gpu_test.xml @@ -33,7 +33,7 @@ Build_PhySim Build for physical simulator --phy_simulators --ninja - TRUE + FALSE From 27080aa60770d7e194973b6495082b2ba53ee9e5 Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Fri, 26 Jun 2020 16:55:47 +0200 Subject: [PATCH 387/553] DOC: remove obsolete pipeline reference Signed-off-by: Raphael Defosseux --- ci-scripts/doc/vm_based_simulator_env.md | 1 - 1 file changed, 1 deletion(-) diff --git a/ci-scripts/doc/vm_based_simulator_env.md b/ci-scripts/doc/vm_based_simulator_env.md index 5dbcfbd931..95b9d920d5 100644 --- a/ci-scripts/doc/vm_based_simulator_env.md +++ b/ci-scripts/doc/vm_based_simulator_env.md @@ -38,7 +38,6 @@ Last point, this documentation is valid for all CI-supported branches: * `master` * `develop` -* `develop-nr` But the feature set may not be aligned. **The principles still apply.** From e1888940b6e9640c0e82b7290e9d1dfe9c77e46a Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Fri, 26 Jun 2020 16:59:05 +0200 Subject: [PATCH 388/553] CI: retry on typical unstable scenarios Signed-off-by: Raphael Defosseux --- ...nb_usrp210_band7_test_05mhz_tm1_rrc_inactivity_no_flexran.xml | 1 + ci-scripts/xml_files/if4p5_usrp210_band40_test_10mhz.xml | 1 + 2 files changed, 2 insertions(+) diff --git a/ci-scripts/xml_files/enb_usrp210_band7_test_05mhz_tm1_rrc_inactivity_no_flexran.xml b/ci-scripts/xml_files/enb_usrp210_band7_test_05mhz_tm1_rrc_inactivity_no_flexran.xml index 41e746bc85..73d1216199 100644 --- a/ci-scripts/xml_files/enb_usrp210_band7_test_05mhz_tm1_rrc_inactivity_no_flexran.xml +++ b/ci-scripts/xml_files/enb_usrp210_band7_test_05mhz_tm1_rrc_inactivity_no_flexran.xml @@ -24,6 +24,7 @@ test-05-tm1-rrc-no-flex Test-05MHz-TM1-RRC-Inactivity tasks + 2 030201 040101 diff --git a/ci-scripts/xml_files/if4p5_usrp210_band40_test_10mhz.xml b/ci-scripts/xml_files/if4p5_usrp210_band40_test_10mhz.xml index e1644f3931..8276294e9a 100644 --- a/ci-scripts/xml_files/if4p5_usrp210_band40_test_10mhz.xml +++ b/ci-scripts/xml_files/if4p5_usrp210_band40_test_10mhz.xml @@ -24,6 +24,7 @@ test-10 Test-10MHz tasks + 2 030201 040101 From 233f51957c4d57f8e9e84a1aceb1de3d355389f7 Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Fri, 26 Jun 2020 17:01:59 +0200 Subject: [PATCH 389/553] CI: add phy-sim runs to eNB logCollector. this is temporary Signed-off-by: Raphael Defosseux --- ci-scripts/ran.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ci-scripts/ran.py b/ci-scripts/ran.py index 9c66b1863c..c968521bda 100644 --- a/ci-scripts/ran.py +++ b/ci-scripts/ran.py @@ -781,7 +781,7 @@ class RANManagement(): mySSH.command('cd ' + self.eNBSourceCodePath, '\$', 5) mySSH.command('cd cmake_targets', '\$', 5) mySSH.command('echo ' + self.eNBPassword + ' | sudo -S rm -f enb.log.zip', '\$', 5) - mySSH.command('echo ' + self.eNBPassword + ' | sudo -S zip enb.log.zip enb*.log core* enb_*record.raw enb_*.pcap enb_*txt', '\$', 60) + mySSH.command('echo ' + self.eNBPassword + ' | sudo -S zip enb.log.zip enb*.log core* enb_*record.raw enb_*.pcap enb_*txt physim_*.log', '\$', 60) mySSH.command('echo ' + self.eNBPassword + ' | sudo -S rm enb*.log core* enb_*record.raw enb_*.pcap enb_*txt', '\$', 5) mySSH.close() From 150ef017f2a29189fbd4457779665d2c37873791 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Mon, 29 Jun 2020 10:17:52 +0200 Subject: [PATCH 390/553] fixed rv for phy-test mode --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 406007ef8d..ff7dfb423e 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -314,7 +314,7 @@ int configure_fapi_dl_pdu(int Mod_idP, pdsch_pdu_rel15->qamModOrder[0] = 2; pdsch_pdu_rel15->mcsIndex[0] = mcs; pdsch_pdu_rel15->mcsTable[0] = 0; - pdsch_pdu_rel15->rvIndex[0] = UE_list->UE_sched_ctrl[UE_id].harq_processes[current_harq_pid].round; + pdsch_pdu_rel15->rvIndex[0] = (get_softmodem_params()->phy_test==1) ? 0 : UE_list->UE_sched_ctrl[UE_id].harq_processes[current_harq_pid].round; pdsch_pdu_rel15->dataScramblingId = *scc->physCellId; pdsch_pdu_rel15->nrOfLayers = 1; pdsch_pdu_rel15->transmissionScheme = 0; From 3f461d680dafa11d29e9b3a2820c020afb7a037f Mon Sep 17 00:00:00 2001 From: WANG Tsu-Han Date: Mon, 29 Jun 2020 10:29:40 +0200 Subject: [PATCH 391/553] adding parameter in uesoftmodem for uhd trx thread --- targets/RT/USER/lte-uesoftmodem.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/targets/RT/USER/lte-uesoftmodem.c b/targets/RT/USER/lte-uesoftmodem.c index 2c9271888b..a45ecd2298 100644 --- a/targets/RT/USER/lte-uesoftmodem.c +++ b/targets/RT/USER/lte-uesoftmodem.c @@ -171,6 +171,8 @@ extern void get_uethreads_params(void); int transmission_mode=1; +int usrp_tx_thread = 0; + char *usrp_args=NULL; char *usrp_clksrc=NULL; From b90e57549ce137fb601f03af30f5f3bb8f8b43f2 Mon Sep 17 00:00:00 2001 From: Thomas Schlichter Date: Wed, 17 Jun 2020 09:53:36 +0200 Subject: [PATCH 392/553] ignore inconsistent DCI instead of exiting --- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 32 +++++++++++--------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 0da02bd7d1..b0437ea972 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -2232,9 +2232,14 @@ int8_t nr_ue_process_dci_time_dom_resource_assignment(NR_UE_MAC_INST_t *mac, pdsch_TimeDomainAllocationList = mac->DLbwp[0]->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList; if (pdsch_TimeDomainAllocationList) { - AssertFatal(pdsch_TimeDomainAllocationList->list.count > time_domain_ind, - "time_domain_ind %d >= pdsch->TimeDomainAllocationList->list.count %d\n", - time_domain_ind,pdsch_TimeDomainAllocationList->list.count); + if (time_domain_ind >= pdsch_TimeDomainAllocationList->list.count) { + LOG_E(MAC, "time_domain_ind %d >= pdsch->TimeDomainAllocationList->list.count %d\n", + time_domain_ind, pdsch_TimeDomainAllocationList->list.count); + dlsch_config_pdu->start_symbol = 0; + dlsch_config_pdu->number_symbols = 0; + return -1; + } + int startSymbolAndLength = pdsch_TimeDomainAllocationList->list.array[time_domain_ind]->startSymbolAndLength; int S,L; SLIV2SL(startSymbolAndLength,&S,&L); @@ -2342,10 +2347,8 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr /* FREQ_DOM_RESOURCE_ASSIGNMENT_UL */ nr_ue_process_dci_freq_dom_resource_assignment(pusch_config_pdu_0_0,NULL,n_RB_ULBWP,0,dci->freq_dom_resource_assignment_UL); /* TIME_DOM_RESOURCE_ASSIGNMENT */ - nr_ue_process_dci_time_dom_resource_assignment(mac, - pusch_config_pdu_0_0,NULL, - dci->time_dom_resource_assignment); - + if (nr_ue_process_dci_time_dom_resource_assignment(mac,pusch_config_pdu_0_0,NULL,dci->time_dom_resource_assignment) < 0) + break; /* FREQ_HOPPING_FLAG */ if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.resource_allocation != 0) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.frequency_hopping !=0)) @@ -2417,8 +2420,8 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr /* FREQ_DOM_RESOURCE_ASSIGNMENT_UL */ nr_ue_process_dci_freq_dom_resource_assignment(pusch_config_pdu_0_1,NULL,n_RB_ULBWP,0,dci->freq_dom_resource_assignment_UL); /* TIME_DOM_RESOURCE_ASSIGNMENT */ - nr_ue_process_dci_time_dom_resource_assignment(mac,pusch_config_pdu_0_1,NULL, - dci->time_dom_resource_assignment); + if (nr_ue_process_dci_time_dom_resource_assignment(mac,pusch_config_pdu_0_1,NULL,dci->time_dom_resource_assignment) < 0) + break; /* FREQ_HOPPING_FLAG */ if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.resource_allocation != 0) && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.frequency_hopping !=0)) @@ -2748,9 +2751,8 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr /* FREQ_DOM_RESOURCE_ASSIGNMENT_DL */ nr_ue_process_dci_freq_dom_resource_assignment(NULL,dlsch_config_pdu_1_0,0,n_RB_DLBWP,dci->freq_dom_resource_assignment_DL); /* TIME_DOM_RESOURCE_ASSIGNMENT */ - nr_ue_process_dci_time_dom_resource_assignment(mac,NULL,dlsch_config_pdu_1_0, - dci->time_dom_resource_assignment); - + if (nr_ue_process_dci_time_dom_resource_assignment(mac,NULL,dlsch_config_pdu_1_0,dci->time_dom_resource_assignment) < 0) + break; /* dmrs symbol positions*/ dlsch_config_pdu_1_0->dlDmrsSymbPos = fill_dmrs_mask(pdsch_config, mac->scc->dmrs_TypeA_Position, @@ -2868,8 +2870,8 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr /* FREQ_DOM_RESOURCE_ASSIGNMENT_DL */ nr_ue_process_dci_freq_dom_resource_assignment(NULL,dlsch_config_pdu_1_1,0,n_RB_DLBWP,dci->freq_dom_resource_assignment_DL); /* TIME_DOM_RESOURCE_ASSIGNMENT */ - nr_ue_process_dci_time_dom_resource_assignment(mac,NULL,dlsch_config_pdu_1_1, - dci->time_dom_resource_assignment); + if (nr_ue_process_dci_time_dom_resource_assignment(mac,NULL,dlsch_config_pdu_1_1,dci->time_dom_resource_assignment) < 0) + break; /* VRB_TO_PRB_MAPPING */ if (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.resource_allocation != 0) dlsch_config_pdu_1_1->vrb_to_prb_mapping = (dci->vrb_to_prb_mapping == 0) ? vrb_to_prb_mapping_non_interleaved:vrb_to_prb_mapping_interleaved; @@ -3140,7 +3142,7 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, pos+=4; dci_pdu_rel15->time_dom_resource_assignment = (*dci_pdu >> (dci_size-pos))&0xf; #ifdef DEBUG_EXTRACT_DCI - LOG_D(MAC,"time-domain assignment %d (3 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_dom_resource_assignment,dci_size-pos,*dci_pdu); + LOG_D(MAC,"time-domain assignment %d (4 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_dom_resource_assignment,dci_size-pos,*dci_pdu); #endif // VRB to PRB mapping From a5a1d7b918d9d26a7601aa3b53026427d01c31ef Mon Sep 17 00:00:00 2001 From: Thomas Schlichter Date: Mon, 29 Jun 2020 12:13:27 +0200 Subject: [PATCH 393/553] Improve stability by replacing AssertFatal() with LOG_E() in nr_rx_pdsch() --- openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c index 7f941e5567..a8827b4e92 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c @@ -214,7 +214,8 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, printf("[DEMOD] I am assuming only TB1 is active, it is in cw %d\n", dlsch1_harq->codeword); #endif - AssertFatal(1 == 0, "[UE][FATAL] DLSCH: TB0 not active and TB1 active case is not supported\n"); + LOG_E(PHY, "[UE][FATAL] DLSCH: TB0 not active and TB1 active case is not supported\n"); + return -1; } else { LOG_E(PHY,"[UE][FATAL] nr_tti_rx %d: no active DLSCH\n", nr_tti_rx); @@ -224,14 +225,16 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, break; default: - AssertFatal(1 == 0, "[UE][FATAL] nr_tti_rx %d: Unknown PDSCH format %d\n", nr_tti_rx, type); + LOG_E(PHY, "[UE][FATAL] nr_tti_rx %d: Unknown PDSCH format %d\n", nr_tti_rx, type); return(-1); break; } - if (dlsch0_harq == NULL) - AssertFatal(1 == 0, "Done\n"); + if (dlsch0_harq == NULL) { + LOG_E(PHY, "Done\n"); + return -1; + } dlsch0_harq->Qm = nr_get_Qm_dl(dlsch[0]->harq_processes[harq_pid]->mcs, dlsch[0]->harq_processes[harq_pid]->mcs_table); dlsch0_harq->R = nr_get_code_rate_dl(dlsch[0]->harq_processes[harq_pid]->mcs, dlsch[0]->harq_processes[harq_pid]->mcs_table); From e5ab435173411ce1d99f55fd37d31fbe16af85e9 Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Mon, 29 Jun 2020 12:21:55 +0200 Subject: [PATCH 394/553] Update TESTING_GNB_W_COTS_UE.md --- doc/TESTING_GNB_W_COTS_UE.md | 106 ++++++++++++++++++++++++++++++++--- 1 file changed, 97 insertions(+), 9 deletions(-) diff --git a/doc/TESTING_GNB_W_COTS_UE.md b/doc/TESTING_GNB_W_COTS_UE.md index 955afe817a..bcec2179f4 100644 --- a/doc/TESTING_GNB_W_COTS_UE.md +++ b/doc/TESTING_GNB_W_COTS_UE.md @@ -238,19 +238,107 @@ The test reaches step **12. E-RAB modifcation confirmation** , eventhough not al From the log file that is generated, we can monitor several important steps, to assess that the test was successful: -Step **6. Random Access Procedure** is successfully reached when the following messages are shown: -[X2AP ... Received elements for X2P] -... -[LSCH received ok] -The next message to check is: -[DCI type I payload] indicating some DL traffic for signaling +- eNB receives UE capabilities information, including its NR capabilites, and triggers sGNB Addition Request message: -Eventually, step **12. E-RAB Modification Confirmation** is successfully reached when the following message is visible: -[E-RAB Modification Confirmation], the message is properly received but not treated. +***eNBlog.1315 :*** +``` +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] received ueCapabilityInformation on UL-DCCH 1 from UE +... +[RRC] [eNB 0] frame 0 subframe 0: UE rnti 43eb switching to NSA mode +... + + + 27 + + + + + + 111 + + + 0 + + +``` + +- gNB receives sGNB Addition request, processes UE capabilities for the corresponding UE and triggers sGNB Addition Request ACK, carrying NR RRC Reconfiguration message: + + +***gNBlog.2291 :*** +``` + + + 27 + + + + + + 111 + + + 0 + + +``` + + +- Upon reception of the sGNB Addition Request ACK, the eNB sends a new RRCConnectionReconfiguration message containing the NR Reconfiguration. +The UE replies with a Reconfiguration Complete message: + +***eNBlog.1686 :*** +``` +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] UE State = RRC_RECONFIGURED (default DRB, xid 1) +``` + +- The Random Access procedure of the UE to the gNB takes place: + +***gNBlog.2382 :*** +``` +[PHY] [gNB 0][RAPROC] Frame 751, slot 19 Initiating RA procedure with +preamble 63, energy 35.7 dB, delay 6 + [0m [0m[MAC] [gNB 0][RAPROC] CC_id 0 Frame 751, Slot 19 Initiating RA +procedure for preamble index 63 + [0m [0m[MAC] [gNB 0][RAPROC] CC_id 0 Frame 751 Activating Msg2 +generation in frame 752, slot 7 using RA rnti 10b + [0m [0m[MAC] [gNB 0] [RAPROC] CC_id 0 Frame 752, slotP 7: Generating +RAR DCI, state 1 + [0m [0m[MAC] [RAPROC] DCI type 1 payload: freq_alloc 120 (0,6,24), +time_alloc 3, vrb to prb 0, mcs 0 tb_scaling 0 + [0m [0m[MAC] Frame 752: Subframe 7 : Adding common DL DCI for RA_RNTI 10b + [0m [0m[MAC] Frame 752, Subframe 7: Setting Msg3 reception for Frame +752 Subframe 17 + [0m [0m[PHY] ULSCH received ok +``` + +- The eNB triggers the path switch procedure towards the MME, so that +the traffic can be routed now from the SGW towards the gNB on the S1-U +plane. + +***eNBlog.1691 :*** +``` + + + 50 + + + + + + 0 + + +553648130 + + +``` + + +Eventually, step **12. E-RAB Modification Confirmation** is successfully reached -TO DO : attach typical succcessful log file as example, add snaps of msg ## Required tools for debug From fa66f18c75ffd4a25543ac7265c63b15e282b947 Mon Sep 17 00:00:00 2001 From: hardy Date: Mon, 29 Jun 2020 13:53:41 +0200 Subject: [PATCH 395/553] uploading conf and log example files --- doc/testing_gnb_w_cots_ue_resources/enb.conf | 281 + doc/testing_gnb_w_cots_ue_resources/gnb.conf | 293 + .../oai_enb.log | 1912 + .../oai_gnb.log | 38680 ++++++++++++++++ 4 files changed, 41166 insertions(+) create mode 100755 doc/testing_gnb_w_cots_ue_resources/enb.conf create mode 100755 doc/testing_gnb_w_cots_ue_resources/gnb.conf create mode 100755 doc/testing_gnb_w_cots_ue_resources/oai_enb.log create mode 100755 doc/testing_gnb_w_cots_ue_resources/oai_gnb.log diff --git a/doc/testing_gnb_w_cots_ue_resources/enb.conf b/doc/testing_gnb_w_cots_ue_resources/enb.conf new file mode 100755 index 0000000000..58e4e86873 --- /dev/null +++ b/doc/testing_gnb_w_cots_ue_resources/enb.conf @@ -0,0 +1,281 @@ +Active_eNBs = ( "eNB-Eurecom-LTEBox"); +# Asn1_verbosity, choice in: none, info, annoying +Asn1_verbosity = "none"; + +eNBs = +( + { + # real_time choice in {hard, rt-preempt, no} + real_time = "no"; + ////////// Identification parameters: + eNB_ID = 0xe01; + + cell_type = "CELL_MACRO_ENB"; + + eNB_name = "eNB-Eurecom-LTEBox"; + + // Tracking area code, 0x0000 and 0xfffe are reserved values + tracking_area_code = 1; + plmn_list = ( + { mcc = 222; mnc = 01; mnc_length = 2; } + ); + + tr_s_preference = "local_mac" + + ////////// Physical parameters: + + component_carriers = ( + { + node_function = "eNodeB_3GPP"; + node_timing = "synch_to_ext_device"; + node_synch_ref = 0; + nb_antenna_ports = 1; + ue_TransmissionMode = 1; + frame_type = "FDD"; + tdd_config = 3; + tdd_config_s = 0; + prefix_type = "NORMAL"; + eutra_band = 7; + downlink_frequency = 2680000000L; //2655000000L; + uplink_frequency_offset = -120000000; + + Nid_cell = 0; + N_RB_DL = 25; //100; + Nid_cell_mbsfn = 0; + nb_antennas_tx = 1; + nb_antennas_rx = 1; + prach_root = 0; + tx_gain = 90; + rx_gain = 115; + pbch_repetition = "FALSE"; + prach_config_index = 0; + prach_high_speed = "DISABLE"; + prach_zero_correlation = 1; + prach_freq_offset = 2; + pucch_delta_shift = 1; + pucch_nRB_CQI = 0; + pucch_nCS_AN = 0; + pucch_n1_AN = 0; + pdsch_referenceSignalPower = -29; + pdsch_p_b = 0; + pusch_n_SB = 1; + pusch_enable64QAM = "DISABLE"; + pusch_hoppingMode = "interSubFrame"; + pusch_hoppingOffset = 0; + pusch_groupHoppingEnabled = "ENABLE"; + pusch_groupAssignment = 0; + pusch_sequenceHoppingEnabled = "DISABLE"; + pusch_nDMRS1 = 1; + phich_duration = "NORMAL"; + phich_resource = "ONESIXTH"; + srs_enable = "DISABLE"; + /* srs_BandwidthConfig =; + srs_SubframeConfig =; + srs_ackNackST =; + srs_MaxUpPts =;*/ + + pusch_p0_Nominal = -96; + pusch_alpha = "AL1"; + pucch_p0_Nominal = -96; + msg3_delta_Preamble = 6; + pucch_deltaF_Format1 = "deltaF2"; + pucch_deltaF_Format1b = "deltaF3"; + pucch_deltaF_Format2 = "deltaF0"; + pucch_deltaF_Format2a = "deltaF0"; + pucch_deltaF_Format2b = "deltaF0"; + + rach_numberOfRA_Preambles = 64; + rach_preamblesGroupAConfig = "DISABLE"; +/* + rach_sizeOfRA_PreamblesGroupA = ; + rach_messageSizeGroupA = ; + rach_messagePowerOffsetGroupB = ; +*/ + rach_powerRampingStep = 4; + rach_preambleInitialReceivedTargetPower = -108; + rach_preambleTransMax = 10; + rach_raResponseWindowSize = 10; + rach_macContentionResolutionTimer = 48; + rach_maxHARQ_Msg3Tx = 4; + + pcch_default_PagingCycle = 128; + pcch_nB = "oneT"; + bcch_modificationPeriodCoeff = 2; + ue_TimersAndConstants_t300 = 1000; + ue_TimersAndConstants_t301 = 1000; + ue_TimersAndConstants_t310 = 1000; + ue_TimersAndConstants_t311 = 10000; + ue_TimersAndConstants_n310 = 20; + ue_TimersAndConstants_n311 = 1; + + //Parameters for SIB18 + rxPool_sc_CP_Len = "normal"; + rxPool_sc_Period = "sf40"; + rxPool_data_CP_Len = "normal"; + rxPool_ResourceConfig_prb_Num = 20; + rxPool_ResourceConfig_prb_Start = 5; + rxPool_ResourceConfig_prb_End = 44; + rxPool_ResourceConfig_offsetIndicator_present = "prSmall"; + rxPool_ResourceConfig_offsetIndicator_choice = 0; + rxPool_ResourceConfig_subframeBitmap_present = "prBs40"; + rxPool_ResourceConfig_subframeBitmap_choice_bs_buf = "00000000000000000000"; + rxPool_ResourceConfig_subframeBitmap_choice_bs_size = 5; + rxPool_ResourceConfig_subframeBitmap_choice_bs_bits_unused = 0; +/* rxPool_dataHoppingConfig_hoppingParameter = 0; + rxPool_dataHoppingConfig_numSubbands = "ns1"; + rxPool_dataHoppingConfig_rbOffset = 0; + rxPool_commTxResourceUC-ReqAllowed = "TRUE"; +*/ + // Parameters for SIB19 + discRxPool_cp_Len = "normal" + discRxPool_discPeriod = "rf32" + discRxPool_numRetx = 1; + discRxPool_numRepetition = 2; + discRxPool_ResourceConfig_prb_Num = 5; + discRxPool_ResourceConfig_prb_Start = 3; + discRxPool_ResourceConfig_prb_End = 21; + discRxPool_ResourceConfig_offsetIndicator_present = "prSmall"; + discRxPool_ResourceConfig_offsetIndicator_choice = 0; + discRxPool_ResourceConfig_subframeBitmap_present = "prBs40"; + discRxPool_ResourceConfig_subframeBitmap_choice_bs_buf = "f0ffffffff"; + discRxPool_ResourceConfig_subframeBitmap_choice_bs_size = 5; + discRxPool_ResourceConfig_subframeBitmap_choice_bs_bits_unused = 0; + + } + ); + + srb1_parameters : + { + # timer_poll_retransmit = (ms) [5, 10, 15, 20,... 250, 300, 350, ... 500] + timer_poll_retransmit = 80; + + # timer_reordering = (ms) [0,5, ... 100, 110, 120, ... ,200] + timer_reordering = 35; + + # timer_reordering = (ms) [0,5, ... 250, 300, 350, ... ,500] + timer_status_prohibit = 0; + + # poll_pdu = [4, 8, 16, 32 , 64, 128, 256, infinity(>10000)] + poll_pdu = 4; + + # poll_byte = (kB) [25,50,75,100,125,250,375,500,750,1000,1250,1500,2000,3000,infinity(>10000)] + poll_byte = 99999; + + # max_retx_threshold = [1, 2, 3, 4 , 6, 8, 16, 32] + max_retx_threshold = 4; + } + + # ------- SCTP definitions + SCTP : + { + # Number of streams to use in input/output + SCTP_INSTREAMS = 2; + SCTP_OUTSTREAMS = 2; + }; + + enable_measurement_reports = "yes"; + + ////////// MME parameters: + mme_ip_address = ( { ipv4 = "192.168.18.99"; + ipv6 = "192:168:30::17"; + active = "yes"; + preference = "ipv4"; + } + ); + + ///X2 + enable_x2 = "yes"; + t_reloc_prep = 1000; /* unit: millisecond */ + tx2_reloc_overall = 2000; /* unit: millisecond */ + + NETWORK_INTERFACES : + { + ENB_INTERFACE_NAME_FOR_S1_MME = "eth1"; + ENB_IPV4_ADDRESS_FOR_S1_MME = "192.168.18.199/24"; + + ENB_INTERFACE_NAME_FOR_S1U = "eth1"; + ENB_IPV4_ADDRESS_FOR_S1U = "192.168.18.199/24"; + ENB_PORT_FOR_S1U = 2152; # Spec 2152 + + ENB_IPV4_ADDRESS_FOR_X2C = "192.168.18.199/24"; + ENB_PORT_FOR_X2C = 36422; # Spec 36422 + }; + + log_config : + { + global_log_level ="info"; + global_log_verbosity ="high"; + hw_log_level ="info"; + hw_log_verbosity ="medium"; + phy_log_level ="info"; + phy_log_verbosity ="medium"; + mac_log_level ="info"; + mac_log_verbosity ="high"; + rlc_log_level ="debug"; + rlc_log_verbosity ="high"; + pdcp_log_level ="info"; + pdcp_log_verbosity ="high"; + rrc_log_level ="info"; + rrc_log_verbosity ="medium"; + }; + + } +); + +MACRLCs = ( + { + num_cc = 1; + tr_s_preference = "local_L1"; + tr_n_preference = "local_RRC"; + phy_test_mode = 0; + puSch10xSnr = 160; + puCch10xSnr = 160; + } +); + +THREAD_STRUCT = ( + { + parallel_config = "PARALLEL_RU_L1_TRX_SPLITaaaaaa"; + worker_config = "ENABLE"; + } +); + +L1s = ( + { + num_cc = 1; + tr_n_preference = "local_mac"; + } +); + +RUs = ( + { + local_rf = "yes" + nb_tx = 1 + nb_rx = 1 + att_tx = 0 + att_rx = 0; + bands = [7]; + max_pdschReferenceSignalPower = -27; + max_rxgain = 118; + eNB_instances = [0]; + + } +); + + log_config : + { + global_log_level ="info"; + global_log_verbosity ="high"; + hw_log_level ="info"; + hw_log_verbosity ="medium"; + phy_log_level ="info"; + phy_log_verbosity ="medium"; + mac_log_level ="info"; + mac_log_verbosity ="high"; + rlc_log_level ="info"; + rlc_log_verbosity ="high"; + pdcp_log_level ="info"; + pdcp_log_verbosity ="high"; + rrc_log_level ="info"; + rrc_log_verbosity ="medium"; + }; diff --git a/doc/testing_gnb_w_cots_ue_resources/gnb.conf b/doc/testing_gnb_w_cots_ue_resources/gnb.conf new file mode 100755 index 0000000000..db8aef33ba --- /dev/null +++ b/doc/testing_gnb_w_cots_ue_resources/gnb.conf @@ -0,0 +1,293 @@ +Active_gNBs = ( "gNB-Eurecom-5GNRBox"); +# Asn1_verbosity, choice in: none, info, annoying +Asn1_verbosity = "none"; + +gNBs = +( + { + ////////// Identification parameters: + gNB_ID = 0xe00; + + cell_type = "CELL_MACRO_GNB"; + + gNB_name = "gNB-Eurecom-5GNRBox"; + + // Tracking area code, 0x0000 and 0xfffe are reserved values + tracking_area_code = 1; + + plmn_list = ({mcc = 222; mnc = 01; mnc_length = 2;}); + + tr_s_preference = "local_mac" + + ////////// Physical parameters: + + ssb_SubcarrierOffset = 31; //0; + pdsch_AntennaPorts = 1; + + servingCellConfigCommon = ( + { + #spCellConfigCommon + + physCellId = 0; + +# downlinkConfigCommon + #frequencyInfoDL + # this is 3600 MHz + 84 PRBs@30kHz SCS (same as initial BWP) + absoluteFrequencySSB = 641272; //641032; #641968; 641968=start of ssb at 3600MHz + 82 RBs 641032=center of SSB at center of cell + dl_frequencyBand = 78; + # this is 3600 MHz + dl_absoluteFrequencyPointA = 640000; + #scs-SpecificCarrierList + dl_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + dl_subcarrierSpacing = 1; + dl_carrierBandwidth = 106; + #initialDownlinkBWP + #genericParameters + # this is RBstart=84,L=13 (275*(L-1))+RBstart + initialDLBWPlocationAndBandwidth = 6366; //28875; //6366; #6407; #3384; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialDLBWPsubcarrierSpacing = 1; + #pdcch-ConfigCommon + initialDLBWPcontrolResourceSetZero = 0; + initialDLBWPsearchSpaceZero = 0; + #pdsch-ConfigCommon + #pdschTimeDomainAllocationList (up to 16 entries) + initialDLBWPk0_0 = 0; + #initialULBWPmappingType + #0=typeA,1=typeB + initialDLBWPmappingType_0 = 0; + #this is SS=1,L=13 + initialDLBWPstartSymbolAndLength_0 = 40; + + initialDLBWPk0_1 = 0; + initialDLBWPmappingType_1 = 0; + #this is SS=2,L=12 + initialDLBWPstartSymbolAndLength_1 = 53; + + initialDLBWPk0_2 = 0; + initialDLBWPmappingType_2 = 0; + #this is SS=1,L=12 + initialDLBWPstartSymbolAndLength_2 = 54; + + initialDLBWPk0_3 = 0; + initialDLBWPmappingType_3 = 0; + #this is SS=1,L=4 //5 (4 is for 43, 5 is for 57) + initialDLBWPstartSymbolAndLength_3 = 57; //43; //57; + #uplinkConfigCommon + #frequencyInfoUL + ul_frequencyBand = 78; + #scs-SpecificCarrierList + ul_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + ul_subcarrierSpacing = 1; + ul_carrierBandwidth = 106; + pMax = 20; + #initialUplinkBWP + #genericParameters + initialULBWPlocationAndBandwidth = 6366; //28875; //6366; #6407; #3384; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialULBWPsubcarrierSpacing = 1; + #rach-ConfigCommon + #rach-ConfigGeneric + prach_ConfigurationIndex = 98; +#prach_msg1_FDM +#0 = one, 1=two, 2=four, 3=eight + prach_msg1_FDM = 0; + prach_msg1_FrequencyStart = 0; + zeroCorrelationZoneConfig = 13; + preambleReceivedTargetPower = -118; +#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200) + preambleTransMax = 6; +#powerRampingStep +# 0=dB0,1=dB2,2=dB4,3=dB6 + powerRampingStep = 1; +#ra_ReponseWindow +#1,2,4,8,10,20,40,80 + ra_ResponseWindow = 5; +#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR +#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4; +#oneHalf (0..15) 4,8,12,16,...60,64 + ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 14; //15; +#ra_ContentionResolutionTimer +#(0..7) 8,16,24,32,40,48,56,64 + ra_ContentionResolutionTimer = 7; + rsrp_ThresholdSSB = 19; +#prach-RootSequenceIndex_PR +#1 = 839, 2 = 139 + prach_RootSequenceIndex_PR = 2; + prach_RootSequenceIndex = 1; + # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex + # + msg1_SubcarrierSpacing = 1, + +# restrictedSetConfig +# 0=unrestricted, 1=restricted type A, 2=restricted type B + restrictedSetConfig = 0, + # pusch-ConfigCommon (up to 16 elements) + initialULBWPk2_0 = 2; + initialULBWPmappingType_0 = 1 + # this is SS=0 L=11 + initialULBWPstartSymbolAndLength_0 = 55; + + initialULBWPk2_1 = 2; + initialULBWPmappingType_1 = 1; + # this is SS=0 L=12 + initialULBWPstartSymbolAndLength_1 = 69; + + initialULBWPk2_2 = 7; + initialULBWPmappingType_2 = 1; + # this is SS=10 L=4 + initialULBWPstartSymbolAndLength_2 = 52; + + msg3_DeltaPreamble = 1; + p0_NominalWithGrant =-90; + +# pucch-ConfigCommon setup : +# pucchGroupHopping +# 0 = neither, 1= group hopping, 2=sequence hopping + pucchGroupHopping = 0; + hoppingId = 40; + p0_nominal = -90; +# ssb_PositionsInBurs_BitmapPR +# 1=short, 2=medium, 3=long + ssb_PositionsInBurst_PR = 2; + ssb_PositionsInBurst_Bitmap = 1; #0x80; + +# ssb_periodicityServingCell +# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1 + ssb_periodicityServingCell = 2; + +# dmrs_TypeA_position +# 0 = pos2, 1 = pos3 + dmrs_TypeA_Position = 0; + +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + subcarrierSpacing = 1; + + + #tdd-UL-DL-ConfigurationCommon +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + referenceSubcarrierSpacing = 1; + # pattern1 + # dl_UL_TransmissionPeriodicity + # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10 + dl_UL_TransmissionPeriodicity = 6; + nrofDownlinkSlots = 7; //8; //7; + nrofDownlinkSymbols = 6; //0; //6; + nrofUplinkSlots = 2; + nrofUplinkSymbols = 4; //0; //4; + + ssPBCH_BlockPower = 10; + } + + ); + + + # ------- SCTP definitions + SCTP : + { + # Number of streams to use in input/output + SCTP_INSTREAMS = 2; + SCTP_OUTSTREAMS = 2; + }; + + + ////////// MME parameters: + mme_ip_address = ( { ipv4 = "192.168.18.99"; + ipv6 = "192:168:30::17"; + active = "yes"; + preference = "ipv4"; + } + ); + + ///X2 + enable_x2 = "yes"; + t_reloc_prep = 1000; /* unit: millisecond */ + tx2_reloc_overall = 2000; /* unit: millisecond */ + target_enb_x2_ip_address = ( + { ipv4 = "192.168.18.199"; + ipv6 = "192:168:30::17"; + preference = "ipv4"; + } + ); + + NETWORK_INTERFACES : + { + + GNB_INTERFACE_NAME_FOR_S1_MME = "eth0"; + GNB_IPV4_ADDRESS_FOR_S1_MME = "192.168.18.198/24"; + GNB_INTERFACE_NAME_FOR_S1U = "eth0"; + GNB_IPV4_ADDRESS_FOR_S1U = "192.168.18.198/24"; + GNB_PORT_FOR_S1U = 2152; # Spec 2152 + GNB_IPV4_ADDRESS_FOR_X2C = "192.168.18.198/24"; + GNB_PORT_FOR_X2C = 36422; # Spec 36422 + }; + } +); + +MACRLCs = ( + { + num_cc = 1; + tr_s_preference = "local_L1"; + tr_n_preference = "local_RRC"; + } +); + +L1s = ( + { + num_cc = 1; + tr_n_preference = "local_mac"; + } +); + +RUs = ( + { + local_rf = "yes" + nb_tx = 1 + nb_rx = 1 + att_tx = 0 + att_rx = 0; + bands = [7]; + max_pdschReferenceSignalPower = -27; + max_rxgain = 114; + eNB_instances = [0]; + clock_src = "internal"; + } +); + +THREAD_STRUCT = ( + { + #three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT" + //parallel_config = "PARALLEL_RU_L1_TRX_SPLIT"; + parallel_config = "PARALLEL_SINGLE_THREAD"; + #two option for worker "WORKER_DISABLE" or "WORKER_ENABLE" + worker_config = "WORKER_ENABLE"; + } +); + + log_config : + { + global_log_level ="info"; + global_log_verbosity ="medium"; + hw_log_level ="info"; + hw_log_verbosity ="medium"; + phy_log_level ="info"; + phy_log_verbosity ="medium"; + mac_log_level ="info"; + mac_log_verbosity ="high"; + rlc_log_level ="info"; + rlc_log_verbosity ="medium"; + pdcp_log_level ="info"; + pdcp_log_verbosity ="medium"; + rrc_log_level ="info"; + rrc_log_verbosity ="medium"; + }; + diff --git a/doc/testing_gnb_w_cots_ue_resources/oai_enb.log b/doc/testing_gnb_w_cots_ue_resources/oai_enb.log new file mode 100755 index 0000000000..9b9de24a86 --- /dev/null +++ b/doc/testing_gnb_w_cots_ue_resources/oai_enb.log @@ -0,0 +1,1912 @@ +[CONFIG] get parameters from libconfig ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.minimassive.master.conf , debug flags: 0x00000000 +[CONFIG] function config_libconfig_init returned 0 +[CONFIG] config module libconfig loaded +[LIBCONFIG] config: 1/1 parameters successfully set, (1 to default value) +# /dev/cpu_dma_latency set to 0us +[LIBCONFIG] log_config: 3/3 parameters successfully set, (1 to default value) +[LIBCONFIG] log_config: 52/52 parameters successfully set, (46 to default value) +[LIBCONFIG] log_config: 52/52 parameters successfully set, (52 to default value) +[LIBCONFIG] log_config: 15/15 parameters successfully set, (15 to default value) +[LIBCONFIG] log_config: 15/15 parameters successfully set, (15 to default value) +log init done +Reading in command-line options +[LIBCONFIG] (root): 23/23 parameters successfully set, (19 to default value) +[LIBCONFIG] (root): 5/5 parameters successfully set, (4 to default value) +Getting ENBSParams +[LIBCONFIG] (root): 3/3 parameters successfully set, (1 to default value) +[LIBCONFIG] THREAD_STRUCT.[0]: 2/2 parameters successfully set, (0 to default value) +[ENB_APP] Impossible value: PARALLEL_RU_L1_TRX_SPLITaaaaaa +[CONFIG] parallel_conf is set to 0 +[LIBCONFIG] THREAD_STRUCT.[0]: 2/2 parameters successfully set, (0 to default value) +[ENB_APP] Impossible value: ENABLE +[CONFIG] worker_conf is set to 0 +Configuration: nb_rrc_inst 1, nb_L1_inst 1, nb_ru 1 +[LIBCONFIG] loader: 2/2 parameters successfully set, (2 to default value) +[LIBCONFIG] loader.NB_IoT: 2/2 parameters successfully set, (1 to default value) + nb_nbiot_rrc_inst 0, nb_nbiot_L1_inst 0, nb_nbiot_macrlc_inst 0 +[LIBCONFIG] TTracer: 4/4 parameters successfully set, (4 to default value) +configuring for RAU/RRU +CPU Freq is 2.992899 +ITTI init, useMME: 1 +[TMR] Starting itti queue: TASK_UNKNOWN as task 0 +[TMR] Starting itti queue: TASK_TIMER as task 1 +[TMR] Starting itti queue: TASK_L2L1 as task 2 +[TMR] Starting itti queue: TASK_BM as task 3 +[TMR] Starting itti queue: TASK_PHY_ENB as task 4 +[TMR] Starting itti queue: TASK_MAC_ENB as task 5 +[TMR] Starting itti queue: TASK_RLC_ENB as task 6 +[TMR] Starting itti queue: TASK_RRC_ENB_NB_IoT as task 7 +[TMR] Starting itti queue: TASK_PDCP_ENB as task 8 +[TMR] Starting itti queue: TASK_DATA_FORWARDING as task 9 +[TMR] Starting itti queue: TASK_END_MARKER as task 10 +[TMR] Starting itti queue: TASK_RRC_ENB as task 11 +[TMR] Starting itti queue: TASK_RRC_GNB as task 12 +[TMR] Starting itti queue: TASK_RAL_ENB as task 13 +[TMR] Starting itti queue: TASK_S1AP as task 14 +[TMR] Starting itti queue: TASK_X2AP as task 15 +[TMR] Starting itti queue: TASK_M2AP_ENB as task 16 +[TMR] Starting itti queue: TASK_M2AP_MCE as task 17 +[TMR] Starting itti queue: TASK_M3AP as task 18 +[TMR] Starting itti queue: TASK_M3AP_MME as task 19 +[TMR] Starting itti queue: TASK_M3AP_MCE as task 20 +[TMR] Starting itti queue: TASK_SCTP as task 21 +[TMR] Starting itti queue: TASK_ENB_APP as task 22 +[TMR] Starting itti queue: TASK_GNB_APP as task 23 +[TMR] Starting itti queue: TASK_MCE_APP as task 24 +[TMR] Starting itti queue: TASK_MME_APP as task 25 +[TMR] Starting itti queue: TASK_FLEXRAN_AGENT as task 26 +[TMR] Starting itti queue: TASK_PHY_UE as task 27 +[TMR] Starting itti queue: TASK_MAC_UE as task 28 +[TMR] Starting itti queue: TASK_RLC_UE as task 29 +[TMR] Starting itti queue: TASK_PDCP_UE as task 30 +[TMR] Starting itti queue: TASK_RRC_UE as task 31 +[TMR] Starting itti queue: TASK_NAS_UE as task 32 +[TMR] Starting itti queue: TASK_RAL_UE as task 33 +[TMR] Starting itti queue: TASK_MSC as task 34 +[TMR] Starting itti queue: TASK_GTPV1_U as task 35 +[TMR] Starting itti queue: TASK_UDP as task 36 +[TMR] Starting itti queue: TASK_CU_F1 as task 37 +[TMR] Starting itti queue: TASK_DU_F1 as task 38 +[LIBCONFIG] opt: 3/3 parameters successfully set, (3 to default value) +[OPT] OPT disabled +reported resolution = 1 ns +[HW] Version: Branch: NR_RRC_harq_hacks Abrev. Hash: 94fa9c5 Date: Fri Jun 19 18:16:53 2020 +0200 +Runtime table +[PHY] RC.eNB = 0x2b10b70 +[LIBCONFIG] L1s.[0]: 24/24 parameters successfully set, (22 to default value) +[PHY] RC.eNB[0] = 0x2b10c20 +[PHY] RC.eNB[0][0] = 0x7f9fab347010 +[ENB_APP] Initializing northbound interface for L1 +[PHY] l1_north_init_eNB() RC.nb_L1_inst:1 +[PHY] l1_north_init_eNB() RC.nb_L1_CC[0]:1 +[PHY] l1_north_init_eNB() RC.eNB[0][0] installing callbacks +[PHY] read_config_and_init() RC.nb_L1_inst: 1 +[LIBCONFIG] MACRLCs.[0]: 20/20 parameters successfully set, (15 to default value) +[LIBCONFIG] MACRLCs.[0]: 20/20 parameters successfully set, (15 to default value) +[MAC] [MAIN] Init function start:nb_macrlc_inst=1 +[PDCP] PDCP layer has been initialized +Configuring local RRC for MACRLC +[ENB_APP] sched mode = default 0 [default] +[MAC] read_config_and_init() RC.nb_macrlc_inst: 1 +[PHY] l1_north_init_eNB() RC.nb_L1_inst:1 +[PHY] l1_north_init_eNB() RC.nb_L1_CC[0]:1 +[PHY] l1_north_init_eNB() RC.eNB[0][0] installing callbacks +[LIBCONFIG] (root): 3/3 parameters successfully set, (1 to default value) +[LIBCONFIG] eNBs.[0]: 20/20 parameters successfully set, (11 to default value) +[RRC] Instance 0: Southbound Transport local_mac +[RRC] Setting node_type to ngran_eNB +[LIBCONFIG] eNBs.[0].plmn_list.[0]: 3/3 parameters successfully set, (0 to default value) +[RRC] num component carriers 1 +[RRC] enb_config::RCconfig_RRC() parameter number: 0, total number of parameters: 78, ccspath: eNBs.[0].component_carriers.[0] + +[LIBCONFIG] eNBs.[0].component_carriers.[0]: 78/78 parameters successfully set, (17 to default value) +phich.resource 0 (ONESIXTH), phich.duration 0 (NORMAL) +No eMBMS configuration, skipping it +[LIBCONFIG] eNBs.[0].component_carriers.[0].emtc_parameters: 88/88 parameters successfully set, (88 to default value) +No eMTC configuration, skipping it +[LIBCONFIG] eNBs.[0].component_carriers.[0].SLparameters: 39/39 parameters successfully set, (39 to default value) +No SL configuration skipping it +[LIBCONFIG] eNBs.[0].srb1_parameters: 6/6 parameters successfully set, (0 to default value) +[RRC] Node type 0 + [LIBCONFIG] (root): 3/3 parameters successfully set, (1 to default value) +[LIBCONFIG] NETWORK_CONTROLLER: 6/6 parameters successfully set, (6 to default value) +[LIBCONFIG] RUs.[0]: 27/27 parameters successfully set, (18 to default value) +Creating RC.ru[0]:0x2b41780 +Setting function for RU 0 to eNodeB_3GPP +[PHY] number of L1 instances 1, number of RU 1, number of CPU cores 4 +[FLEXRAN_AGENT] FlexRAN Agent for eNB 0 is DISABLED +[PDCP] PDCP layer has been initialized +[PDCP] pdcp init,usegtp +[PDCP] ENB pdcp will use tun interface for MBMS +[NETLINK]Opened socket oaitun_enm1 with fd 84 +returnValue 0 +returnValue 0 +returnValue 0 +[OIP] Interface oaitun_enm1 successfully configured, ip address 10.0.2.1, mask 255.255.255.0 broadcast address 10.0.2.255 +[ENB_APP] Creating ENB_APP eNB Task +[TMR] Created Posix thread TASK_ENB_APP +[RRC] Creating RRC eNB Task +[LIBCONFIG] (root): 3/3 parameters successfully set, (1 to default value) +[TMR] Created Posix thread TASK_RRC_ENB +[LIBCONFIG] eNBs.[0]: 20/20 parameters successfully set, (11 to default value) +[TMR] Created Posix thread TASK_SCTP +[RRC] Entering main loop of RRC message task +[LIBCONFIG] eNBs.[0].plmn_list.[0]: 3/3 parameters successfully set, (0 to default value) +[TMR] Created Posix thread TASK_S1AP +[TMR] Created Posix thread TASK_UDP +[SCTP] Starting SCTP layer +[S1AP] Starting S1AP layer +[UDP] Initializing UDP task interface +[UDP] Initializing UDP task interface: DONE +[LIBCONFIG] eNBs.[0].component_carriers.[0]: 78/78 parameters successfully set, (17 to default value) +[LIBCONFIG] eNBs.[0].mme_ip_address.[0]: 5/5 parameters successfully set, (0 to default value) +[LIBCONFIG] eNBs.[0].SCTP: 2/2 parameters successfully set, (0 to default value) +[LIBCONFIG] eNBs.[0].NETWORK_INTERFACES: 11/11 parameters successfully set, (2 to default value) +[TMR] Created Posix thread TASK_GTPV1_U +[GTPV1U] Configuring GTPu +[LIBCONFIG] (root): 3/3 parameters successfully set, (1 to default value) +[LIBCONFIG] eNBs.[0]: 1/1 parameters successfully set, (0 to default value) +[LIBCONFIG] gNBs.[0]: 1/1 parameters successfully set, (1 to default value) +[LIBCONFIG] eNBs.[0].NETWORK_INTERFACES: 3/3 parameters successfully set, (0 to default value) +[GTPV1U] Configuring GTPu address : 192.168.18.199 -> c712a8c0 +[ENB_APP] default drx 2 +[ENB_APP] [eNB 0] eNB_app_register via S1AP for instance 0 +[LIBCONFIG] (root): 3/3 parameters successfully set, (1 to default value) +[GTPV1U] Initializing GTPU stack 0x16968b0 +[LIBCONFIG] eNBs.[0]: 20/20 parameters successfully set, (11 to default value) +[LIBCONFIG] eNBs.[0].plmn_list.[0]: 3/3 parameters successfully set, (0 to default value) +[S1AP] Registered new eNB[0] and macro eNB id 3585 +[S1AP] [eNB 0] check the mme registration state +[GTPV1U] Tx UDP_INIT IP addr 192.168.18.199 (868) +[UDP] Initializing UDP for local address 192.168.18.199 with port 2152 +[TMR] Created Posix thread TASK_X2AP +[MAC] Creating MAC eNB Task +[LIBCONFIG] eNBs.[0].component_carriers.[0]: 78/78 parameters successfully set, (17 to default value) +[LIBCONFIG] list eNBs.[0].target_enb_x2_ip_address not found in config file ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.minimassive.master.conf +[LIBCONFIG] eNBs.[0]: 2/2 parameters successfully set, (0 to default value) +[LIBCONFIG] eNBs.[0].SCTP: 2/2 parameters successfully set, (0 to default value) +[UDP] Inserting new descriptor for task 35, sd 85 +[LIBCONFIG] eNBs.[0].NETWORK_INTERFACES: 11/11 parameters successfully set, (2 to default value) +[UDP] Initializing UDP for local address 192.168.18.199 with port 2152: DONE +[MAC] Starting main loop of MAC message task +[LIBCONFIG] eNBs.[0]: 1/1 parameters successfully set, (1 to default value) +[SCTP] sctp_bindx SCTP_BINDX_ADD_ADDR socket bound to : 192.168.18.199 +[X2AP] Registered new eNB[0] and macro eNB id 3585 +[X2AP] eNB[0] eNB id 3585 acting as a listner (server) +[TMR] Created Posix thread TASK_MAC_ENB +[SCTP] Converted ipv4 address 192.168.18.99 to network type +[RRC] [eNB 0] Received RRC_CONFIGURATION_REQ : 0x2b4a80c +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 0] Init... +[SCTP] connectx assoc_id 903 in progress..., used 1 addresses +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 0] Checking release +[SCTP] Inserted new descriptor for sd 86 in list, nb elements 1, assoc_id 903 +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 0] Rel14 RRC detected, MBMS flag 0 +[SCTP] Received SCTP_INIT_MSG_MULTI_REQ +[RRC] [eNB 0] Node type 0 + [SCTP] Creating new listen socket on port 36422 with +[SCTP] ipv4 addresses: +[SCTP] - 192.168.18.199 +[RRC] configuration->schedulingInfoSIB1_BR_r13[CC_id] 0 +[RRC] Configuring MIB (N_RB_DL 25,phich_Resource 0,phich_Duration 0) +[RRC] [MIB] systemBandwidth 2, phich_duration 0, phich_resource 0, sfn 0 +[RRC] [MIB] schedulingInfoSIB1 0 +[RRC] [eNB 0] Configuration SIB2/3, eMBMS = 0 +[RRC] do_SIB23, size 38 + [MAC] Configuring MIB for instance 0, CCid 0 : (band 7,N_RB_DL 25,Nid_cell 0,p 1,DL freq 2680000000,phich_config.resource 0, phich_config.duration 0) +[MAC] config_mib() NFAPI_CONFIG_REQUEST(num_tlv:16) DL_BW:25 UL_BW:25 Ncp 0,p_eNB 1,earfcn 3350,band 7,phich_resource 0 phich_duration 0 phich_power_offset 6000 PSS 6000 SSS 6000 PCI 0 PBCH repetition 0 +[MAC] [CONFIG]SIB2/3 Contents (partial) +[MAC] [CONFIG]pusch_config_common.n_SB = 1 +[MAC] [CONFIG]pusch_config_common.hoppingMode = 0 +[MAC] [CONFIG]pusch_config_common.pusch_HoppingOffset = 0 +[MAC] [CONFIG]pusch_config_common.enable64QAM = 0 +[MAC] [CONFIG]pusch_config_common.groupHoppingEnabled = 1 +[MAC] [CONFIG]pusch_config_common.groupAssignmentPUSCH = 0 +[MAC] [CONFIG]pusch_config_common.sequenceHoppingEnabled = 0 +[MAC] [CONFIG]pusch_config_common.cyclicShift = 1 +[PHY] Configuring MIB for instance 0, CCid 0 : (band 7,N_RB_DL 25, N_RB_UL 25, Nid_cell 0,eNB_tx_antenna_ports 1,Ncp 0,DL freq 3350,phich_config.resource 0, phich_config.duration 0) +[PHY] Initializing frame parms for N_RB_DL 25, Ncp 0, osf 1 +[PHY] lte_parms.c: Setting N_RB_DL to 25, ofdm_symbol_size 512 +[SCTP] Found data for descriptor 86 +[SCTP] Received notification for sd 86, type 32769 +[SCTP] Client association changed: 0 +[SCTP] ---------------------- +[SCTP] Peer addresses: +[SCTP] - [192.168.18.99] +[SCTP] ---------------------- +[SCTP] ---------------------- +[SCTP] SCTP Status: +[SCTP] assoc id .....: 903 +[SCTP] state ........: 4 +[SCTP] instrms ......: 2 +[SCTP] outstrms .....: 2 +[SCTP] fragmentation : 1452 +[SCTP] pending data .: 0 +[SCTP] unack data ...: 0 +[SCTP] rwnd .........: 106496 +[SCTP] peer info : +[SCTP] state ....: 2 +[SCTP] cwnd .....: 4380 +[SCTP] srtt .....: 0 +[SCTP] rto ......: 3000 +[SCTP] mtu ......: 1500 +[SCTP] ---------------------- +[SCTP] Comm up notified for sd 86, assigned assoc_id 903 +[S1AP] 3585 -> 00e010 + + + 17 + + + + + + 59 + + + + 22 F2 10 + + + 00000000111000000001 + + + + + + + 60 + + + eNB-Eurecom-LTEBox + + + + 64 + + + + + 00 01 + + 22 F2 10 + + + + + + + 137 + + + + + + + + + + +[SCTP] Successfully sent 59 bytes on stream 0 for assoc_id 903 +[LIBCONFIG] loader.coding: 2/2 parameters successfully set, (1 to default value) +[SCTP] Found data for descriptor 86 +[SCTP] Received notification for sd 86, type 32777 +[SCTP] Found data for descriptor 86 +[SCTP] [903][86] Msg of length 58 received from port 36412, on stream 0, PPID 18 +[S1AP] servedGUMMEIs.list.count 3 +[S1AP] servedPLMNs.list.count 1 +[S1AP] servedPLMNs.list.count 1 +[S1AP] servedPLMNs.list.count 1 +[ENB_APP] [eNB 0] Received S1AP_REGISTER_ENB_CNF: associated MME 1 +[LOADER] library libcoding.so successfully loaded +[PHY] prach_config_common.rootSequenceIndex = 0 +[PHY] prach_config_common.prach_ConfigInfo.prach_ConfigIndex = 0 +[PHY] prach_config_common.prach_ConfigInfo.highSpeedFlag = 0 +[PHY] prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig = 1 +[PHY] prach_config_common.prach_ConfigInfo.prach_FreqOffset = 2 +[PHY] pusch_config_common.n_SB = 1 +[PHY] pusch_config_common.hoppingMode = 0 +[PHY] pusch_config_common.pusch_HoppingOffset = 0 +[PHY] pusch_config_common.enable64QAM = 0 +[PHY] pusch_config_common.ul_ReferenceSignalsPUSCH.groupHoppingEnabled = 1 +[PHY] pusch_config_common.ul_ReferenceSignalsPUSCH.groupAssignmentPUSCH = 0 +[PHY] pusch_config_common.ul_ReferenceSignalsPUSCH.sequenceHoppingEnabled = 0 +[PHY] pusch_config_common.ul_ReferenceSignalsPUSCH.cyclicShift = 2 +[PHY] eNB 0/0 configured +[RRC] [eNB] handover active state is 0 +[RRC] [eNB] eMBMS active state is 0 +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 0] ENB:OPENAIR RRC IN.... +[ENB_APP] START MAIN THREADS +RC.nb_L1_inst:1 +Initializing eNB threads single_thread_flag:0 wait_for_sync:0 +[PHY] [lte-softmodem.c] eNB structure about to allocated RC.nb_L1_inst:1 RC.nb_L1_CC[0]:1 +[PHY] [lte-softmodem.c] eNB structure RC.eNB allocated +[PHY] Initializing eNB 0 CC_id 0 single_thread_flag:0 +[PHY] Initializing eNB 0 CC_id 0 +[PHY] Registering with MAC interface module +[PHY] Setting indication lists +[PHY] [lte-softmodem.c] eNB structure allocated +wait_eNBs() +Waiting for eNB L1 instances to all get configured ... sleeping 50ms (nb_L1_inst 1) +RC.nb_L1_CC[0]:1 +eNB L1 are configured +About to Init RU threads RC.nb_RU:1 +Initializing RU threads +[PHY] DJP - delete code above this /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/targets/RT/USER/lte-ru.c:2739 +[PHY] Copying frame parms from eNB 0 to ru 0 +[PHY] Initializing RRU descriptor 0 : (local RF,synch_to_ext_device,0) +configuring ru_id 0 (start_rf 0x5b1a00) +[PHY] Starting ru_thread 0, is_slave 0, send_dmrs 0 +[PHY] Initializing RU proc 0 (eNodeB_3GPP,synch_to_ext_device), +[PHY] init_RU_proc() DJP - added creation of pthread_prach +[HW] thread_top_init() called with affinity>0, but overruled by #ifndef CPU_AFFINITY. +[HW] [SCHED][eNB] ru_thread started on CPU 1, sched_policy = SCHED_FIFO , priority = 99, CPU Affinity= CPU_0 CPU_1 CPU_2 CPU_3 +[PHY] thread ru created id=7295 +[PHY] Starting RU 0 (eNodeB_3GPP,synch_to_ext_device), +waiting for sync (ru_thread,-1/0xff4968,0x17af520,0x16952a0) +channel 0, Setting tx_gain offset 0.000000, rx_gain offset 118.000000, tx_freq 2680000000.000000, rx_freq 2560000000.000000 +[HW] thread_top_init() called with affinity>0, but overruled by #ifndef CPU_AFFINITY. +[PHY] Initializing frame parms for N_RB_DL 25, Ncp 0, osf 1 +[PHY] lte_parms.c: Setting N_RB_DL to 25, ofdm_symbol_size 512 +[PHY] Initializing RU signal buffers (if_south local RF) nb_tx 1 +[HW] [SCHED][eNB] ru_thread_prach started on CPU 2, sched_policy = SCHED_FIFO , priority = 99, CPU Affinity= CPU_0 CPU_1 CPU_2 CPU_3 +[PHY] [INIT] common.txdata[0] = 0x7f9fafc66010 (307200 bytes) +[PHY] ru_thread_prach() RU configured - RACH processing thread running +[LIBCONFIG] loader.dfts: 2/2 parameters successfully set, (1 to default value) +[LOADER] library libdfts.so successfully loaded +[PHY] nb_tx 1 +[PHY] rxdata_7_5kHz[0] 0x2b9c1c0 for RU 0 +[PHY] [INIT] common.txdata_BF= 0x2b4ae80 (8 bytes) +[PHY] txdataF_BF[0] 0x2bba1e0 for RU 0 +[PHY] rxdataF[0] 0x2bc1200 for RU 0 +[LIBCONFIG] device.recplay: 7/7 parameters successfully set, (7 to default value) +[LIBCONFIG] device: 1/1 parameters successfully set, (1 to default value) +[LIBCONFIG] loader.oai_device: 2/2 parameters successfully set, (1 to default value) +[LOADER] library liboai_device.so successfully loaded +[HW] UHD version 3.13.0.HEAD-0-g0ddc19e5 (3.13.0) +[HW] Found USRP b200 +Found USRP b200 +[HW] Clock source set neither in usrp_args nor on command line, using default! +[HW] Time source set neither in usrp_args nor on command line, using default! +[SCTP] Found data for descriptor 87 +[SCTP] Received notification for sd 87, type 32769 +[SCTP] Client association changed: 0 +[SCTP] Comm up notified for sd 87, assigned assoc_id 904 +[SCTP] ---------------------- +[SCTP] SCTP Status: +[SCTP] assoc id .....: 904 +[SCTP] state ........: 4 +[SCTP] instrms ......: 32 +[SCTP] outstrms .....: 32 +[SCTP] fragmentation : 1452 +[SCTP] pending data .: 0 +[SCTP] unack data ...: 0 +[SCTP] rwnd .........: 106496 +[SCTP] peer info : +[SCTP] state ....: 2 +[SCTP] cwnd .....: 4380 +[SCTP] srtt .....: 0 +[SCTP] rto ......: 3000 +[SCTP] mtu ......: 1500 +[SCTP] ---------------------- +x2ap_eNB_handle_sctp_association_ind at 1 (called for instance 0) +here comes the tree (instance 0): +--------------------------------------------- +--------------------------------------------- +x2ap_eNB_handle_sctp_association_ind at 2 +here comes the tree (instance 0): +--------------------------------------------- +----------------------- +eNB id 0 (null) +state 2 +nextstream 0 +in_streams 0 out_streams 0 +cnx_id 1 assoc_id 0 +--------------------------------------------- +x2ap_eNB_handle_sctp_association_ind at 3 +here comes the tree (instance 0): +--------------------------------------------- +----------------------- +eNB id 0 (null) +state 2 +nextstream 0 +in_streams 32 out_streams 32 +cnx_id 1 assoc_id 904 +--------------------------------------------- +[SCTP] Found data for descriptor 95 +[SCTP] [904][95] Msg of length 66 received from port 36422, on stream 0, PPID 27 + + + 36 + + + + + + 244 + + + + + + 252 + + + + 22 F2 10 + + + 00000000000000000000111000000000 + + + + + + + 253 + + + + + + 0 + + 22 F2 10 + + 000000000000000000000000111000000000 + + + 00 64 90 + + 22 F2 10 + + + + + 0 + + + 1 + + + 80 + + + + + + + + + + + + 00 + + + + + + + + + + + + + + +[X2AP] X2AP_ProcedureCode_id_endcX2Setup message! +[X2AP] TAC: 006490 +[X2AP] PLMN: 22f210 + + + 36 + + + + + + 246 + + + + + + 21 + + + + 22 F2 10 + + + 00000000111000000001 + + + + + + + 250 + + + + + + 0 + + 22 F2 10 + + 0000000011100000000100000000 + + + 00 01 + + 22 F2 10 + + + + 21350 + 3350 + + + + + + + + + + + + + + + + + + +[SCTP] Successfully sent 53 bytes on stream 0 for assoc_id 904 +[SCTP] Found data for descriptor 95 +[SCTP] Received notification for sd 95, type 32777 +[HW] cal 0: freq 3500000000.000000, offset 44.000000, diff 940000000.000000 +[HW] cal 1: freq 2660000000.000000, offset 49.800000, diff 100000000.000000 +[HW] cal 2: freq 2300000000.000000, offset 51.000000, diff 260000000.000000 +[HW] cal 3: freq 1880000000.000000, offset 53.000000, diff 680000000.000000 +[HW] cal 4: freq 816000000.000000, offset 57.000000, diff 1744000000.000000 +[HW] RX Gain 0 118.000000 (55.800000) => 62.200000 (max 76.000000) +[HW] USRP TX_GAIN:89.75 gain_range:89.75 tx_gain:0.00 +[HW] Actual master clock: 30.720000MHz... +[HW] Actual clock source internal... +[HW] Actual time source internal... +[HW] RF board max packet size 1916, size for 100µs jitter 768 +[HW] rx_max_num_samps 768 +[HW] RX Channel 0 +[HW] Actual RX sample rate: 7.680000MSps... +[HW] Actual RX frequency: 2.560000GHz... +[HW] Actual RX gain: 62.000000... +[HW] Actual RX bandwidth: 20.000000M... +[HW] Actual RX antenna: RX2... +[HW] TX Channel 0 +[HW] Actual TX sample rate: 7.680000MSps... +[HW] Actual TX frequency: 2.680000GHz... +[HW] Actual TX gain: 89.750000... +[HW] Actual TX bandwidth: 20.000000M... +[HW] Actual TX antenna: TX/RX... +[HW] Actual TX packet size: 1916 +[HW] Device timestamp: 1.703971... +[HW] [RAU] has loaded USRP B200 device. +setup_RU_buffers: frame_parms = 0x7f9fab347e68 +[PHY] Signaling main thread that RU 0 (is_slave 0,send_dmrs 0) is ready in state RU_RUN +wait RUs +[ENB_APP] Waiting for RUs to be configured ... RC.ru_mask:00 +[PHY] RUs configured +[ENB_APP] RC.nb_RU:1 +ALL RUs ready - init eNBs +[ENB_APP] Not NFAPI mode - call init_eNB_afterRU() +[PHY] init_eNB_afterRU() RC.nb_inst:1 +[PHY] RC.nb_CC[inst]:1 +[PHY] RC.nb_CC[inst:0][CC_id:0]:0x7f9fab347010 +[PHY] [eNB 0] phy_init_lte_eNB() About to wait for eNB to be configured[PHY] [eNB 0] Initializing DL_FRAME_PARMS : N_RB_DL 25, PHICH Resource 1, PHICH Duration 0 nb_antennas_tx:0 nb_antennas_rx:1 nb_antenna_ports_eNB:1 PRACH[rootSequenceIndex:0 prach_Config_enabled:1 configIndex:0 highSpeed:0 zeroCorrelationZoneConfig:1 freqOffset:2] +[PHY] [eNB 0] Initializing DL_FRAME_PARMS : N_RB_DL 25, PHICH Resource 1, PHICH Duration 0 +pcfich_reg : 0,12,25,37 +[PHY] [INIT] NB_ANTENNA_PORTS_ENB:6 fp->nb_antenna_ports_eNB:1 +[PHY] [INIT] common_vars->txdataF[0] = 0x7f9fafb87010 (286720 bytes) +[PHY] [INIT] common_vars->txdataF[5] = 0x7f9fa80ff010 (286720 bytes) +[PHY] Mapping RX ports from 1 RUs to eNB 0 +[PHY] Overwriting eNB->prach_vars.rxsigF[0]:0x330a6c0 +[PHY] Overwriting eNB->prach_vars_br.rxsigF.rxsigF[0]:(nil) +[PHY] Overwriting eNB->prach_vars_br.rxsigF.rxsigF[0]:(nil) +[PHY] Overwriting eNB->prach_vars_br.rxsigF.rxsigF[0]:(nil) +[PHY] Overwriting eNB->prach_vars_br.rxsigF.rxsigF[0]:(nil) +[PHY] eNB->num_RU:1 +[PHY] Attaching RU 0 antenna 0 to eNB antenna 0 +[PHY] init_eNB_afterRU() ************* DJP ***** eNB->frame_parms.nb_antennas_tx:0 - GOING TO HARD CODE TO 1[PHY] inst 0, CC_id 0 : nb_antennas_rx 1 +[PHY] Initialise transport +[PHY] init_eNB_proc(inst:0) RC.nb_CC[inst]:1 +[PHY] Initializing eNB processes instance:0 CC_id 0 +[PHY] eNB->single_thread_flag:0 +[HW] thread_top_init() called with affinity>0, but overruled by #ifndef CPU_AFFINITY. +[HW] [SCHED][eNB] eNB_thread_prach started on CPU 0, sched_policy = SCHED_FIFO , priority = 99, CPU Affinity= CPU_0 CPU_1 CPU_2 CPU_3 +[ENB_APP] ALL RUs ready - ALL eNBs ready +[HW] thread_top_init() called with affinity>0, but overruled by #ifndef CPU_AFFINITY. +[HW] [SCHED][eNB] eNB_thread_prach_br started on CPU 0, sched_policy = SCHED_FIFO , priority = 99, CPU Affinity= CPU_0 CPU_1 CPU_2 CPU_3 +[ENB_APP] Sending sync to all threads +[MME_APP] Creating MME_APP eNB Task +got sync (ru_thread) +[TMR] Created Posix thread TASK_MME_APP +[HW] Time in secs now: 22168192 +[LIBCONFIG] MMEs.[0]: 1/1 parameters successfully set, (1 to default value) +[MCE_APP] Creating MCE_APP eNB Task +[HW] Time in secs last pps: 21747824 +[PHY] RU 0 rf device ready +[TMR] Created Posix thread TASK_MCE_APP +[LIBCONFIG] MCEs.[0]: 1/1 parameters successfully set, (1 to default value) +[LIBCONFIG] MCEs.[0]: 1/1 parameters successfully set, (1 to default value) +[ENB_APP] TYPE TO TERMINATE +[ENB_APP] [MCE 0] MCE_app_register via M3AP for instance 0 +[HW] [recv] received 0 samples out of 7680 +[HW] ERROR_CODE_OVERFLOW (Out of sequence error) + +[PHY] rx_rf: Asked for 7680 samples, got 0 from SDR +[PHY] problem receiving samples[MAC] SCHED_MODE = 0 +[PHY] rx_rf: rfdevice timing drift of 22200737 samples (ts_off 0) +[PHY] prach_I0 = 0.0 dB +[PHY] max_I0 18, min_I0 0 +[PHY] fill_ulsch UE_id 0 nb_rb = 0 +[RRC] [FRAME 00738][eNB][MOD 00][RNTI 43eb] Decoding UL CCCH 59.e8.a9.2.18.72 (0x3a52693) +[RRC] [FRAME 00738][eNB][MOD 00][RNTI 43eb] Accept new connection from UE random UE identity (0x8721908a9e000000) MME code 0 TMSI 0 cause 1 +[MAC] UE 0 RNTI 43eb adding LC 1 idx 0 to scheduling control (total 1) +[MAC] UE 0 RNTI 43eb adding LC 2 idx 1 to scheduling control (total 2) +[MAC] Added physicalConfigDedicated 0x7f9f600085d0 for 0.0 +[RRC] [FRAME 00738][eNB][MOD 00][RNTI 43eb]CALLING RLC CONFIG SRB1 (rbid 1) +add new uid is 0 43eb + +[PDCP] [FRAME 00738][eNB][MOD 00][RNTI 43eb][SRB 01] Action ADD LCID 1 (SRB id 1) configured with SN size 5 bits and RLC AM +[MAC] generate_Msg4 ra->Msg4_frame SFN/SF: 739.2, frameP SFN/SF: 739.2 FOR eNB_Mod: 0 +[MAC] [eNB 0][RAPROC] CC_id 0 Frame 739, subframeP 2: Generating Msg4 with RRC Piggyback (RNTI 43eb) +[PHY] fill_ulsch UE_id 0 nb_rb = 0 +[MAC] [eNB 0][PUSCH 6] CC_id 0 740.6 ULSCH in error in round 0, ul_cqi 132, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 6] CC_id 0 741.4 ULSCH in error in round 1, ul_cqi 138, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 6] CC_id 0 742.2 ULSCH in error in round 2, ul_cqi 134, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 6] CC_id 0 743.0 ULSCH in error in round 3, ul_cqi 132, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 6] CC_id 0 743.8 ULSCH in error in round 0, ul_cqi 140, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 6] CC_id 0 744.6 ULSCH in error in round 1, ul_cqi 140, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 6] CC_id 0 745.4 ULSCH in error in round 2, ul_cqi 142, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 6] CC_id 0 746.2 ULSCH in error in round 3, ul_cqi 143, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 6] CC_id 0 747.0 ULSCH in error in round 0, ul_cqi 143, UE_id 0, RNTI 43eb (len 63) +[PHY] fill_ulsch UE_id 0 nb_rb = 0 +[MAC] [eNB 0][PUSCH 0] CC_id 0 748.8 ULSCH in error in round 0, ul_cqi 146, UE_id 0, RNTI 43eb (len 63) +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] [RAPROC] Logical Channel UL-DCCH, processing LTE_RRCConnectionSetupComplete from UE (SRB1 Active) +[NAS] AttachRequest.c:40 EMM - attach_request len = 97 +[NAS] UeNetworkCapability.c:46 decode_ue_network_capability len = 7 +[NAS] UeNetworkCapability.c:63 uenetworkcapability decoded UMTS + +[NAS] UeNetworkCapability.c:74 uenetworkcapability decoded GPRS + +[NAS] UeNetworkCapability.c:82 uenetworkcapability decoded=6 + +[NAS] UeNetworkCapability.c:86 uenetworkcapability then decoded=8 + +[NAS] AttachRequest.c:285 EMM: Can't decode the message with iei 111 + +[S1AP] [eNB 0] Build S1AP_NAS_FIRST_REQ adding in s_TMSI: GUMMEI mme_code 1 mme_group_id 32768 ue 43eb +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] UE State = RRC_CONNECTED +[S1AP] [eNB 0] Chose MME 'MME 1' (assoc_id 903) through GUMMEI MCC 222 MNC 1 MMEGI 32768 MMEC 1 +[S1AP] Found usable eNB_ue_s1ap_id: 0x06692d 420141(10) +[S1AP] GUMMEI_ID_PRESENT + + + 12 + + + + + + 8 + + + 420141 + + + + 26 + + + + 17 A0 9C 9B 3F 04 07 41 02 0B F6 22 F2 10 80 00 + 01 00 00 00 37 07 F0 70 C0 40 10 00 10 00 2A 02 + 1F D0 11 D1 27 23 80 80 21 10 01 00 00 10 81 06 + 00 00 00 00 83 06 00 00 00 00 00 0D 00 00 0A 00 + 00 05 00 00 10 00 00 11 00 52 22 F2 10 00 01 5C + 0A 00 31 04 E5 E0 34 01 90 11 03 57 58 A6 5D 01 + 00 E0 C1 6F 04 F0 00 70 00 + + + + + 67 + + + + 22 F2 10 + 00 01 + + + + + 100 + + + + 22 F2 10 + + 0000000011100000000100000000 + + + + + + 134 + + + + + + + 75 + + + + 22 F2 10 + 80 00 + 01 + + + + + + + + +[SCTP] Successfully sent 164 bytes on stream 1 for assoc_id 903 +[RLC] /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/openair2/LAYER2/rlc_v2/rlc_entity_am.c:941:generate_status: warning: cannot generate status PDU, not enough room +[RLC] /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/openair2/LAYER2/rlc_v2/rlc_entity_am.c:941:generate_status: warning: cannot generate status PDU, not enough room +[RLC] /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/openair2/LAYER2/rlc_v2/rlc_entity_am.c:941:generate_status: warning: cannot generate status PDU, not enough room +[RLC] /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/openair2/LAYER2/rlc_v2/rlc_entity_am.c:941:generate_status: warning: cannot generate status PDU, not enough room +[SCTP] Found data for descriptor 86 +[SCTP] Received notification for sd 86, type 32777 +[SCTP] Found data for descriptor 86 +[SCTP] [903][86] Msg of length 32 received from port 36412, on stream 1, PPID 18 +[RRC] [eNB 0] Received S1AP_DOWNLINK_NAS: ue_initial_id 1, eNB_ue_s1ap_id 420141 +[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB +[PHY] fill_ulsch UE_id 0 nb_rb = 0 +[MAC] [eNB 0][PUSCH 3] CC_id 0 752.3 ULSCH in error in round 0, ul_cqi 146, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 752.8 ULSCH in error in round 0, ul_cqi 152, UE_id 0, RNTI 43eb (len 63) + + + 13 + + + + + + 0 + + + 553648130 + + + + 8 + + + 420141 + + + + 26 + + + + 17 A8 76 C5 F5 05 07 56 08 29 22 10 10 00 00 11 + 04 + + + + + 100 + + + + 22 F2 10 + + 0000000011100000000100000000 + + + + + + 67 + + + + 22 F2 10 + 00 01 + + + + + + + + +[SCTP] Successfully sent 68 bytes on stream 1 for assoc_id 903 +[SCTP] Found data for descriptor 86 +[SCTP] Received notification for sd 86, type 32777 +[SCTP] Found data for descriptor 86 +[SCTP] [903][86] Msg of length 65 received from port 36412, on stream 1, PPID 18 +[RRC] [eNB 0] Received S1AP_DOWNLINK_NAS: ue_initial_id 1, eNB_ue_s1ap_id 420141 +[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB +[PHY] fill_ulsch UE_id 0 nb_rb = 0 +[MAC] [eNB 0][PUSCH 4] CC_id 0 761.2 ULSCH in error in round 0, ul_cqi 158, UE_id 0, RNTI 43eb (len 63) +[PHY] fill_ulsch UE_id 0 nb_rb = 0 +[PHY] fill_ulsch UE_id 0 nb_rb = 0 +[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 10 PUCCH SNR 10 + + + 13 + + + + + + 0 + + + 553648130 + + + + 8 + + + 420141 + + + + 26 + + + + 17 9B EE 3B BF 06 07 53 08 ED CA A1 31 56 26 D7 + E1 + + + + + 100 + + + + 22 F2 10 + + 0000000011100000000100000000 + + + + + + 67 + + + + 22 F2 10 + 00 01 + + + + + + + + +[SCTP] Successfully sent 68 bytes on stream 1 for assoc_id 903 +[SCTP] Found data for descriptor 86 +[SCTP] Received notification for sd 86, type 32777 +[SCTP] Found data for descriptor 86 +[SCTP] [903][86] Msg of length 51 received from port 36412, on stream 1, PPID 18 +[RRC] [eNB 0] Received S1AP_DOWNLINK_NAS: ue_initial_id 1, eNB_ue_s1ap_id 420141 +[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB + + + 13 + + + + + + 0 + + + 553648130 + + + + 8 + + + 420141 + + + + 26 + + + 47 86 59 47 B7 00 07 5E + + + + 100 + + + + 22 F2 10 + + 0000000011100000000100000000 + + + + + + 67 + + + + 22 F2 10 + 00 01 + + + + + + + + +[SCTP] Successfully sent 59 bytes on stream 1 for assoc_id 903 +[SCTP] Found data for descriptor 86 +[SCTP] Received notification for sd 86, type 32777 +[SCTP] Found data for descriptor 86 +[SCTP] [903][86] Msg of length 38 received from port 36412, on stream 1, PPID 18 +[RRC] [eNB 0] Received S1AP_DOWNLINK_NAS: ue_initial_id 1, eNB_ue_s1ap_id 420141 +[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB + + + 13 + + + + + + 0 + + + 553648130 + + + + 8 + + + 420141 + + + + 26 + + + + 27 F5 4A 60 81 01 02 1F DA 28 09 03 6F 61 69 04 + 69 70 76 34 + + + + + 100 + + + + 22 F2 10 + + 0000000011100000000100000000 + + + + + + 67 + + + + 22 F2 10 + 00 01 + + + + + + + + +[SCTP] Successfully sent 71 bytes on stream 1 for assoc_id 903 +[PHY] fill_ulsch UE_id 0 nb_rb = 0 +[SCTP] Found data for descriptor 86 +[SCTP] Received notification for sd 86, type 32777 +[SCTP] Found data for descriptor 86 +[SCTP] [903][86] Msg of length 235 received from port 36412, on stream 1, PPID 18 +[S1AP] Received NAS message with the E_RAB setup procedure +[RRC] [eNB 0] Received S1AP_INITIAL_CONTEXT_SETUP_REQ: ue_initial_id 1, eNB_ue_s1ap_id 420141, nb_of_e_rabs 1 +[GTPV1U] Configured GTPu address : c712a8c0 +[GTPV1U] Copied to create_tunnel_resp tunnel: index 0 target gNB ip 192.168.18.199 length 4 gtp teid 3396329693 +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] rrc_eNB_process_GTPV1U_CREATE_TUNNEL_RESP tunnel (3396329693, 3396329693) bearer UE context index 0, msg index 0, id 5, gtp addr len 4 +[RRC] [eNB 0][UE 43eb] Selected security algorithms (0x7f9f9400213c): 0, 2, changed +[RRC] [eNB 0][UE 43eb] Saved security key 107FB5D1A79727631F15C38738093134AAF72931EA06D9495605EDB00D8D8044 +[RRC]  +KeNB:10 7f b5 d1 a7 97 27 63 1f 15 c3 87 38 09 31 34 aa f7 29 31 ea 06 d9 49 56 05 ed b0 0d 8d 80 44 +[RRC]  +KRRCenc:1b 33 28 35 5a 74 f3 6a 05 c6 cf 34 e9 be 54 63 7b a8 5a 48 1d 72 54 67 ae b0 12 a4 1d 3b 7d 86 +[RRC]  +KRRCint:ba a3 e0 18 79 1e 68 44 c6 60 dd c9 a8 8c 65 c2 e8 74 09 da 28 d6 f2 d9 6f ad da 41 d7 ec 8e 71 +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] Logical Channel DL-DCCH, Generate SecurityModeCommand (bytes 3) +[RRC] calling rrc_data_req :securityModeCommand +[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] received securityModeComplete on UL-DCCH 1 from UE +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] Logical Channel DL-DCCH, Generate UECapabilityEnquiry (bytes 3) +[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] received ueCapabilityInformation on UL-DCCH 1 from UE +[RRC] got UE capabilities for UE 43eb +[RRC] drx_Configuration parameter is NULL, cannot configure local UE parameters or CDRX is deactivated +[RRC] [eNB 0] frame 0: requesting A2, A3, A4, and A5 event reporting + + + 22 + + + + + + 0 + + + 553648130 + + + + 8 + + + 420141 + + + + 74 + + + + 04 43 DA 01 08 87 7D DB 80 51 81 80 01 04 0C 20 + 71 63 08 11 24 4C C1 93 67 0F A1 4A 99 3A 85 AF + CC 58 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF + FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE + C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF + 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F + FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F + FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF + FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 + 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 + 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF + FF FF 2B FF D8 FF FF FF 95 FF DF F3 FF AF A2 0C + 00 8C 85 3C 10 65 3A 54 95 1F C0 77 7E 00 00 00 + 00 02 04 BD 80 00 00 08 09 DF 00 00 00 02 F5 C0 + 0C 00 A0 04 00 04 00 A0 06 00 48 20 0C 10 06 08 + 03 04 01 82 00 C1 08 60 84 30 42 18 21 0A 08 03 + 04 01 82 00 C1 00 60 84 30 42 18 20 0C 10 06 08 + 03 04 01 82 00 A1 80 01 04 30 00 20 86 00 04 10 + C0 00 82 18 00 10 43 00 02 08 40 00 61 00 01 84 + 00 82 10 00 18 40 08 21 00 01 84 00 82 10 00 18 + 40 08 21 00 01 84 00 82 10 02 08 60 08 43 0C 01 + 08 61 80 21 0C 30 04 21 84 00 86 10 02 18 40 08 + 61 00 21 84 00 86 10 02 18 60 08 43 0C 01 08 61 + 80 21 0C 30 04 21 84 00 86 10 02 18 40 08 61 00 + 21 84 00 86 10 02 18 41 08 61 04 21 84 10 86 08 + 43 04 21 82 10 C1 08 60 04 84 00 86 10 02 18 40 + 08 61 00 21 84 00 86 10 02 18 21 0C 10 86 10 00 + 18 40 00 60 80 30 03 00 25 A0 7D 54 6C 1E 00 00 + 35 81 8C 00 08 20 60 00 02 08 18 20 00 80 06 10 + 00 20 81 86 00 08 00 62 00 02 00 18 E0 00 80 06 + 58 00 20 01 98 00 08 00 68 00 02 00 1A 20 00 80 + 06 90 00 20 01 A6 00 08 00 6C 00 02 00 1B 20 00 + 80 06 D8 00 20 00 B8 10 00 5F 08 00 70 80 02 00 + 1C A0 00 82 07 30 00 20 01 CE 00 08 20 74 00 02 + 08 0D A1 00 0F F0 00 40 05 7C 20 63 00 02 08 3B + 60 00 80 8C 10 41 5B 08 18 C0 00 82 0E 98 00 20 + 23 04 10 54 C2 06 30 00 20 83 8C 00 08 28 41 04 + 14 60 83 84 00 08 20 E3 00 02 0A 00 41 05 18 20 + E0 00 02 08 2B E1 03 00 00 10 01 DB 00 04 04 00 + 82 0A D8 40 C0 00 04 10 74 C0 01 01 00 20 82 A6 + 10 30 00 01 04 1C 20 00 41 40 08 20 A1 04 1C 00 + 00 41 05 7C 20 61 00 02 08 3B 60 00 80 84 10 41 + 5B 08 18 40 00 82 0E 98 00 20 21 04 10 54 C2 06 + 10 00 20 82 BE 10 34 C0 01 00 35 F0 81 A6 00 08 + 08 C1 05 08 20 06 BE 10 14 C2 06 30 00 20 A1 04 + 00 D7 C2 02 98 40 46 08 38 40 00 80 1A F8 40 D3 + 00 04 04 60 82 80 10 03 5F 08 0A 61 03 18 00 10 + 50 02 00 6B E1 01 4C 20 23 04 1C 00 00 40 09 7C + 20 69 80 02 02 30 41 09 7C 20 29 84 0C 60 00 41 + 09 7C 20 63 00 02 0A 10 48 09 7C 20 63 00 02 02 + 10 49 09 7C 20 23 04 1C 20 00 48 09 7C 20 23 04 + 0C 20 00 49 09 7C 20 63 00 02 0A 10 40 09 7C 20 + 63 00 02 02 10 41 09 7C 20 23 04 1C 20 00 40 09 + 7C 20 23 04 0C 20 00 41 09 7C 20 63 00 02 0A 00 + 40 09 7C 20 23 04 1C 00 00 40 0F 6C 00 10 11 82 + 0A 10 41 40 08 21 AD 84 0C 60 00 41 42 08 28 01 + 04 35 B0 80 8C 10 70 80 01 05 00 20 86 B6 10 11 + 82 0A 10 41 C0 00 04 10 B6 C0 01 01 18 20 A1 04 + 10 96 C2 06 30 00 20 A1 04 10 96 C2 02 30 41 C2 + 00 04 10 B6 C0 01 01 18 20 A0 04 10 96 C2 06 30 + 00 20 A0 04 10 96 C2 02 30 41 C0 00 04 10 F4 C0 + 01 01 18 20 A1 04 14 00 82 1A 98 40 C6 00 04 14 + 20 82 80 10 43 53 08 08 C1 07 08 00 10 50 02 08 + 6A 61 01 18 20 A1 04 1C 00 00 41 0B 4C 00 10 11 + 82 0A 10 41 09 4C 20 63 00 02 0A 10 41 09 4C 20 + 23 04 1C 20 00 41 0B 4C 00 10 11 82 0A 00 41 09 + 4C 20 63 00 02 0A 00 41 09 4C 20 23 04 1C 00 00 + 41 0B 18 00 10 50 82 0A 00 41 09 18 20 E1 00 02 + 0A 00 41 09 18 20 A1 04 1C 00 00 41 07 18 04 12 + 50 82 08 28 C1 27 08 00 10 41 C6 00 04 14 20 92 + 0A 30 41 C2 01 04 90 31 80 41 24 25 F0 81 A6 00 + 08 08 01 00 25 F0 80 A6 10 30 00 01 00 2D B0 00 + 40 42 08 28 01 04 25 B0 81 84 00 08 28 01 04 25 + B0 80 84 10 70 00 01 04 2D 30 00 40 42 08 28 01 + 04 25 30 81 84 00 08 28 01 04 25 30 80 84 10 70 + 00 01 04 1C 20 00 41 40 09 20 A1 04 1C 00 00 49 + 09 7C 20 69 80 02 02 10 41 09 7C 20 29 84 0C 20 + 00 41 05 7C 20 61 00 02 48 18 40 20 92 07 28 08 + 24 EB B1 FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F + FF FF CA FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF + FD 8F FF FF F9 5F FE C7 FF FF FC AF FF 63 FF FF + FE 57 FF B1 FF FF FF 2B FF D8 FF FF FF 95 FF EC + 7F FF FF CA FF F6 3F FF FF E5 7F FB 1F FF FF F2 + BF FD 8F FF FF F9 5F FE C7 FF FF FC AF FF 63 FF + FF FE 57 FF B1 FF FF FF 2B FF D8 FF FF FF 95 FF + EC 7F FF FF CA FF F6 3F FF FF E5 7F FB 1F FF FF + F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC AF FF 63 + FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF FF FF 95 + FF EC 7F FF FF CA FF F6 3F FF FF E5 7F FB 1F FF + FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC AF FF + 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF FF FF + 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 7F FB 1F + FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC AF + FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF FF + FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 7F FB + 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC + AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF + FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 7F + FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF + FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 + FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 + 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF + FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF + D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF + E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 + FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B + FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF + FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE + C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF + 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F + FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F + FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF + FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 + 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 + 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF + FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF + F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF + F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 + FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA + FF F6 3F FF FF E5 7F F6 CE C0 00 0F D8 81 B3 B0 + 00 00 8F 9D 80 00 1A C0 00 00 08 78 78 BC 5E 1E + 1E 1E 1D 0F 0E 43 C3 A1 E1 E1 E1 E1 C0 00 08 78 + 78 78 71 17 8B C5 E1 E1 E1 E1 E1 E1 E1 E2 F1 78 + BC 3C 3C 3C 3C 39 17 00 01 F5 80 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 80 82 00 80 20 08 02 00 80 20 08 02 00 + 80 20 08 02 00 80 20 08 02 00 80 20 08 02 00 80 + 60 01 80 06 00 18 00 60 01 80 04 00 40 04 00 40 + 04 00 40 04 00 40 04 00 40 04 00 40 06 00 18 00 + 60 01 80 04 00 40 04 00 40 04 00 40 06 00 18 00 + 60 01 80 04 00 40 04 00 40 04 00 40 04 00 40 04 + 00 20 08 02 00 80 00 40 04 00 40 04 00 40 04 00 + 40 04 00 20 08 04 00 40 02 00 00 1F 04 01 20 03 + E6 57 9A 04 01 4B 1F FF FF FF FF FF FE 69 4B BC + 50 0F 80 04 20 09 86 00 00 00 00 00 05 50 92 48 + 81 01 00 02 F2 42 0B 51 40 01 34 00 00 00 + + + + + [RRC] RRCConnectionReconfiguration Encoded 1796 bits (225 bytes) +[RRC] [eNB 0] Frame 0, Logical Channel DL-DCCH, Generate LTE_RRCConnectionReconfiguration (bytes 225, UE id 43eb) + [RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB + + + [PDCP] [FRAME 00000][eNB][MOD 00][RNTI 43eb][SRB 02] Action ADD LCID 2 (SRB id 2) configured with SN size 5 bits and RLC AM + + +[PDCP] [FRAME 00000][eNB][MOD 00][RNTI 43eb][DRB 01] Action ADD LCID 3 (DRB id 1) configured with SN size 12 bits and RLC AM +[SCTP] Successfully sent 2206 bytes on stream 1 for assoc_id 903 +[SCTP] Found data for descriptor 86 +[SCTP] Received notification for sd 86, type 32777 +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] UE State = RRC_RECONFIGURED (default DRB, xid 2) +[PDCP] [FRAME 00000][eNB][MOD 00][RNTI 43eb][SRB 02] Action MODIFY LCID 2 RB id 2 reconfigured with SN size 5 and RLC AM +[PDCP] [FRAME 00000][eNB][MOD 00][RNTI 43eb][DRB 01] Action MODIFY LCID 3 RB id 1 reconfigured with SN size 1 and RLC AM +[RRC] [eNB 0] Frame 0 CC 0 : SRB2 is now active +[RRC] [eNB 0] Frame 0 : Logical Channel UL-DCCH, Received LTE_RRCConnectionReconfigurationComplete from UE rnti 43eb, reconfiguring DRB 1/LCID 3 +[RRC] [eNB 0] Frame 0 : Logical Channel UL-DCCH, Received LTE_RRCConnectionReconfigurationComplete from UE 0, reconfiguring DRB 1/LCID 3 +[MAC] UE 0 RNTI 43eb adding LC 3 idx 2 to scheduling control (total 3) +[MAC] Added physicalConfigDedicated 0x7f9f600085d0 for 0.0 +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] Logical Channel DL-DCCH, Generate NR UECapabilityEnquiry (bytes 27) +[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB +[S1AP] initial_ctxt_resp_p: e_rab ID 5, enb_addr 192.168.18.199, SIZE 4 + + + 13 + + + + + + 0 + + + 553648130 + + + + 8 + + + 420141 + + + + 26 + + + 27 22 5C 78 F3 02 07 43 00 03 52 00 C2 + + + + 100 + + + + 22 F2 10 + + 0000000011100000000100000000 + + + + + + 67 + + + + 22 F2 10 + 00 01 + + + + + + + + +[SCTP] Successfully sent 64 bytes on stream 1 for assoc_id 903 +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] received ueCapabilityInformation on UL-DCCH 1 from UE +[RRC] got UE capabilities for UE 43eb +[MAC] [eNB 0][PUSCH 7] CC_id 0 796.7 ULSCH in error in round 0, ul_cqi 152, UE_id 0, RNTI 43eb (len 63) +[RRC] [eNB 0] frame 0 subframe 0: UE rnti 43eb switching to NSA mode +[RRC] Read in 2056 bytes for uecap + + + 27 + + + + + + 111 + + + 0 + + + + 248 + + + + + 0000000000000000 + + + 0000000000000000 + + + + + + 203 + + + + 0000000000000000000000000000000000000000000000000000000000000000 + 0000000000000000000000000000000000000000000000000000000000000000 + 0000000000000000000000000000000000000000000000000000000000000000 + 0000000000000000000000000000000000000000000000000000000000000000 + + + + + 204 + + + + 100000000 + 100000000 + + + + + 205 + + + + + 209 + + + + 5 + 1 + + + + + + + + + 1 + + 15 + + + + + + + 11000000101010000001001001100011 + + 00 00 00 02 + + + + + + + + + + + 206 + + + + 3A 03 08 78 8D DB 80 51 81 80 01 04 0C 20 71 63 + 08 11 24 4C C1 93 67 0F A1 4A 99 3A 85 AF CC 58 + FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 + 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF + FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF + D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF + E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 + FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B + FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF + FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE + C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF + 2B FF D8 FF FF FF 95 FF DF F3 FF AF A2 0C 00 8C + 85 3C 10 65 3A 54 97 1F C0 68 FE 00 00 00 00 02 + 04 BD 80 00 00 08 09 DF 00 00 00 02 EE C0 0C 00 + A0 04 00 04 00 A0 06 00 48 20 0C 10 06 08 03 04 + 01 82 10 C1 08 60 84 30 42 18 20 0C 10 06 08 43 + 04 21 82 00 C1 00 60 80 30 40 18 20 0C 10 06 18 + 02 10 C3 00 42 18 60 08 43 0C 01 08 61 80 21 0C + 30 04 21 86 00 84 30 C0 10 86 10 02 18 40 08 61 + 00 21 84 00 86 10 02 18 40 08 61 00 21 84 00 86 + 10 02 18 20 0C 10 06 18 02 10 C3 00 42 18 60 08 + 43 0C 01 08 61 00 21 84 00 86 10 02 18 41 08 61 + 04 21 84 10 86 10 42 18 41 08 61 04 21 84 10 86 + 10 42 18 41 08 60 84 30 42 18 21 0C 10 86 00 61 + 00 21 84 00 86 10 02 18 40 08 61 00 21 84 00 86 + 08 43 04 21 82 00 C1 00 60 04 B4 7D 54 6C 1E 00 + 00 2E 81 8C 00 08 20 60 00 02 08 18 20 00 80 06 + 10 00 20 81 86 00 08 00 62 00 02 00 18 E0 00 80 + 06 58 00 20 01 98 00 08 00 68 00 02 00 1A 20 00 + 80 06 90 00 20 01 A6 00 08 00 6C 00 02 00 1B 20 + 00 80 06 D8 00 20 00 B8 10 00 5F 08 00 70 80 02 + 00 1C A0 00 82 07 30 00 20 01 CE 00 08 20 74 00 + 02 08 0D A1 00 0F F0 00 40 07 4C 00 10 11 82 08 + 2A 61 03 18 00 10 41 C7 00 04 04 60 82 0A 38 40 + C6 00 04 10 71 80 01 05 08 20 82 8C 10 70 80 01 + 04 1C 60 00 41 40 08 20 A3 04 1C 00 00 41 07 4C + 00 10 10 02 08 2A 61 03 00 00 10 41 C2 00 04 14 + 00 82 0A 10 41 C0 00 04 10 76 C0 01 01 08 20 82 + B6 10 30 80 01 04 1D 30 00 40 42 08 20 A9 84 0C + 20 00 41 07 1C 00 10 10 82 08 28 E1 03 08 00 10 + 43 D3 00 04 04 60 82 84 12 50 02 08 6A 61 03 18 + 00 10 50 82 4A 00 41 0D 4C 20 23 04 1C 20 00 49 + 40 08 21 A9 84 04 60 82 84 12 70 00 01 04 3D 30 + 00 40 46 08 28 41 05 00 20 86 A6 10 31 80 01 05 + 08 20 A0 04 10 D4 C2 02 30 41 C2 00 04 14 00 82 + 1A 98 40 46 08 28 41 07 00 00 10 42 D3 00 04 04 + 60 82 84 12 42 53 08 18 C0 00 82 84 12 42 53 08 + 08 C1 07 08 00 12 42 D3 00 04 04 60 82 84 10 42 + 53 08 18 C0 00 82 84 10 42 53 08 08 C1 07 08 00 + 10 42 D3 00 04 04 60 82 80 10 42 53 08 18 C0 00 + 82 80 10 42 53 08 08 C1 07 00 00 10 41 D3 00 04 + 04 60 92 0A 98 40 C6 00 04 90 F1 C0 01 01 18 20 + A1 04 14 00 82 1A 38 40 C6 00 04 14 20 82 80 10 + 43 47 08 08 C1 07 08 00 10 50 02 08 68 E1 01 18 + 20 A1 04 1C 00 00 41 0B 1C 00 10 11 82 0A 10 41 + 09 1C 20 63 00 02 0A 10 41 09 1C 20 23 04 1C 20 + 00 41 0B 18 00 12 50 82 0A 00 41 09 18 24 E1 00 + 02 0A 00 41 09 18 24 A1 04 1C 00 00 41 0B 18 00 + 10 50 82 4A 00 41 09 18 20 E1 00 02 4A 00 41 09 + 18 20 A1 04 9C 00 00 41 0B 18 00 10 50 82 0A 00 + 41 09 18 20 E1 00 02 0A 00 41 09 18 20 A1 04 1C + 00 00 41 07 18 04 12 50 82 08 28 C1 27 08 00 10 + 41 C6 00 04 14 20 92 0A 30 41 C2 01 04 90 31 80 + 41 24 2D 30 00 40 42 09 28 01 04 25 30 81 84 00 + 09 28 01 04 25 30 80 84 12 70 00 01 04 2D 30 00 + 40 42 08 28 01 04 25 30 81 84 00 08 28 01 04 25 + 30 80 84 10 70 00 01 04 1C 20 10 49 40 08 20 A1 + 04 9C 00 00 41 07 4C 00 10 10 82 48 2A 61 03 08 + 00 12 40 C2 01 04 9B B6 3F FF FF E5 7F FB 1F FF + FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC AF FF + 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF FF FF + 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 7F FB 1F + FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC AF + FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF FF + FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 7F FB + 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC + AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF + FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 7F + FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF + FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 + FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 + 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF + FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF + D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF + E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 + FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B + FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF + FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE + C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF + 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F + FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F + FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF + FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 + 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 + 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF + FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF + F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF + F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 + FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA + FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF + FF F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF + B1 FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF + CA FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F + FF FF F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 + FF B1 FF FF FF 2B FF B6 76 00 00 7E C4 0D 9D 80 + 00 04 7C EC 00 00 BA 00 00 00 8B C5 E2 F1 78 78 + 78 78 72 1E 1E 1E 1E 1E 1E 3F 8F C2 1E 1E 1E 1E + 1E 1E 1E 1E 1E 1E 2F 17 8B 90 F0 F0 F0 F1 78 BC + 5E 1E 1E 1E 1E 1E 1E 1E 1E 1E 1E 1C 8B 80 0F 74 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 04 04 10 04 01 00 40 10 + 04 01 00 40 10 04 01 00 40 10 04 01 00 40 10 04 + 03 00 0C 00 30 00 C0 03 00 0C 00 30 00 C0 02 00 + 20 02 00 20 02 00 20 02 00 20 02 00 10 04 03 00 + 0C 00 30 00 C0 02 00 20 02 00 20 02 00 20 02 00 + 20 02 00 20 02 00 20 01 00 40 10 04 00 02 00 20 + 02 00 20 02 00 20 01 00 40 10 04 00 3E 08 02 40 + 07 CC AF 34 08 02 96 3F FF FF FF FF FF FC D2 97 + 78 A0 1F 00 08 40 13 0C 00 00 00 00 00 0A A1 34 + 91 02 02 00 05 E4 84 12 E2 80 02 6B C0 C0 04 00 + 01 04 10 40 00 28 C8 00 00 08 80 00 05 58 E1 00 + 00 00 01 4F 7E 03 02 00 00 01 40 48 07 06 0E 22 + 0C 00 02 13 60 10 73 E4 20 F0 00 82 40 31 10 00 + A0 58 9B A0 21 94 34 08 81 07 41 86 04 C0 42 54 + 41 01 00 80 06 08 1C 1C 22 03 C8 0F 00 20 1A 02 + 6E 26 F0 00 09 00 00 00 00 72 A6 80 00 80 00 02 + 0C 30 00 1A 55 30 62 00 11 C0 48 16 0C 01 C4 D0 + 00 00 00 40 04 03 40 4D 01 04 40 41 4E 9C 00 02 + 00 01 00 80 80 10 02 00 + + + + + + + + +[SCTP] Successfully sent 2161 bytes on stream 0 for assoc_id 904 +[SCTP] Found data for descriptor 95 +[SCTP] Received notification for sd 95, type 32777 +[SCTP] Found data for descriptor 95 +[SCTP] [904][95] Msg of length 371 received from port 36422, on stream 0, PPID 27 + + + 27 + + + + + + 111 + + + 0 + + + + 207 + + + 0 + + + + 210 + + + + + 213 + + + + 5 + + + + + + + + + + 11000000101010000001001011000110 + + 92 CC 30 02 + + + + + + + + + + + 211 + + + + 18 04 09 A8 44 09 92 E2 07 8E 01 90 43 7E 30 D0 + 41 E6 41 C8 54 1E 21 00 83 2B A1 6E 63 00 1A 4E + 47 C0 13 49 C4 00 00 00 26 96 18 DE 35 00 05 38 + 05 10 0D 60 1B 40 39 D2 02 68 00 01 34 E4 E1 8D + E3 2A 31 00 0D 66 66 BE E4 E0 24 BC A1 5B C2 C5 + 8F 68 9C 2E 00 50 E0 18 04 21 60 3B 00 91 19 1F + 5E 24 62 00 1A CC CD 00 03 F0 DB 00 10 1C 02 D9 + 00 92 00 20 24 04 63 2C E1 96 65 14 0F FF F8 00 + 00 00 08 70 00 41 03 08 14 30 73 70 44 30 00 00 + 80 80 1A 70 0A 20 1A C0 36 80 72 CA 80 40 FF FF + 80 00 00 00 87 00 04 10 30 81 43 07 0D C2 10 C0 + 00 08 05 90 01 01 20 23 25 61 52 C0 E1 04 16 0E + 0C 10 E1 00 71 28 1C 00 00 20 5E F4 01 00 02 00 + 00 0F 40 01 41 00 19 73 86 59 95 18 80 06 B3 33 + 5F 72 70 12 5E 50 AD E1 62 C7 B4 4E 17 00 28 70 + 6A A4 1A 80 81 04 42 0C 20 30 08 C0 03 40 43 00 + 0C 01 8A 17 B4 08 28 5E C9 07 91 A2 B3 80 00 40 + 00 7F 42 10 84 00 80 40 25 81 C2 08 2C 1C 18 21 + C2 00 E2 50 38 00 00 40 BD E8 02 00 04 00 00 1E + 80 02 82 00 70 01 01 88 00 40 A0 49 40 BC 16 00 + 60 00 + + + + + + + + +[X2AP] x2ap_eNB_decode_successfuloutcome_message! +[X2AP] X2AP Association id: 904 +322: 180409a8440992e2078e0190437e30d041e641c8541e2100832ba16e63001a4e47c01349c4000000269618de3500053805100d601b4039d20268000134e4e18de32a31000d6666bee4e024bca15bc2c58f689c2e0050e0180421603b0091191f5e2462001acccd0003f0db00101c02d9009200202404632ce19665140ffff8000000087000410308143073704430000080801a700a201ac0368072ca8040ffff8000000087000410308143070dc210c00008059001012023256152c0e104160e0c10e10071281c0000205ef401000200000f400141001973865995188006b3335f7270125e50ade162c7b44e170028706aa41a808104420c203008c0034043000c018a17b408285ec90791a2b3800040007f4210840080402581c2082c1c1821c200e25038000040bde802000400001e80028200700101880040a04940bc16006000 + + + + + + 08 81 32 5C 40 F1 C0 32 08 6F C6 1A 08 3C C8 39 + 0A 83 C4 20 10 65 74 2D CC 60 03 49 C8 F8 02 69 + 38 80 00 00 04 D2 C3 1B C6 A0 00 A7 00 A2 01 AC + 03 68 07 3A 40 4D 00 00 26 9C 9C 31 BC 65 46 20 + 01 AC CC D7 DC 9C 04 97 94 2B 78 58 B1 ED 13 85 + C0 0A 1C 03 00 84 2C 07 60 12 23 23 EB C4 8C 40 + 03 59 99 A0 00 7E 1B 60 02 03 80 5B 20 12 40 04 + 04 80 8C 65 9C 32 CC A2 81 FF FF 00 00 00 01 0E + 00 08 20 61 02 86 0E 6E 08 86 00 00 10 10 03 4E + 01 44 03 58 06 D0 0E 59 50 08 1F FF F0 00 00 00 + 10 E0 00 82 06 10 28 60 E1 B8 42 18 00 01 00 B2 + 00 20 24 04 64 AC 2A 58 1C 20 82 C1 C1 82 1C 20 + 0E 25 03 80 00 04 0B DE 80 20 00 40 00 01 E8 00 + 28 20 03 2E 70 CB 32 A3 10 00 D6 66 6B EE 4E 02 + 4B CA 15 BC 2C 58 F6 89 C2 E0 05 0E 0D 54 83 50 + 10 20 88 41 84 06 01 18 00 68 08 60 01 80 31 42 + F6 81 05 0B D9 20 F2 34 56 70 00 08 00 0F E8 42 + 10 80 10 08 04 B0 38 41 05 83 83 04 38 40 1C 4A + 07 00 00 08 17 BD 00 40 00 80 00 03 D0 00 50 40 + 0E 00 20 31 00 + + 14 09 28 17 82 C0 0C 00 + + + + +[RRC] Dumping scg_CellGroupConfig: 3090881325c40f1c032086fc61a083cc8390a83c4201065742dcc600349c8f802693880000004d2c31bc6a000a700a201ac0368073a404d0000269c9c31bc65462001acccd7dc9c0497942b7858b1ed1385c00a1c0300842c0760122323ebc48c40035999a0007e1b600203805b2012400404808c659c32cca281ffff000000010e0008206102860e6e088600001010034e0144035806d00e5950081ffff000000010e0008206102860e1b84218000100b20020240464ac2a581c2082c1c1821c200e25038000040bde802000400001e8002820032e70cb32a31000d6666bee4e024bca15bc2c58f689c2e0050e0d54835010208841840601180068086001803142f681050bd920f23456700008000fe8421080100804b038410583830438401c4a0700000817bd004000800003d00050400e00203100 +[RRC] Dumping scg_RB_Config: 81409281782c00c00 +[RRC] Dumping nr_SecondaryCellGroupConfig: 3090881325c40f1c032086fc61a083cc8390a83c4201065742dcc600349c8f802693880000004d2c31bc6a000a700a201ac0368073a404d0000269c9c31bc65462001acccd7dc9c0497942b7858b1ed1385c00a1c0300842c0760122323ebc48c40035999a0007e1b600203805b2012400404808c659c32cca281ffff000000010e0008206102860e6e088600001010034e0144035806d00e5950081ffff000000010e0008206102860e1b84218000100b20020240464ac2a581c2082c1c1821c200e25038000040bde802000400001e8002820032e70cb32a31000d6666bee4e024bca15bc2c58f689c2e0050e0d54835010208841840601180068086001803142f681050bd920f23456700008000fe8421080100804b038410583830438401c4a0700000817bd004000800003d00050400e00203100 +[RRC] Dumping nr_RadioBearerConfig1: 81409281782c00c00 +len = 336 + 22 02 8c 00 23 08 10 00 ac 24 a0 82 1e 32 04 d4 22 04 c9 71 03 c7 00 c8 21 bf 18 68 20 f3 20 e4 2a 0f 10 80 41 95 d0 b7 31 80 0d 27 23 e0 09 a4 e2 00 00 00 13 4b 0c 6f 1a 80 02 9c 02 88 06 b0 0d a0 1c e9 01 34 00 00 9a 72 70 c6 f1 95 18 80 06 b3 33 5f 72 70 12 5e 50 ad e1 62 c7 b4 4e 17 00 28 70 0c 02 10 b0 1d 80 48 8c 8f af 12 31 00 0d 66 66 80 01 f8 6d 80 08 0e 01 6c 80 49 00 10 12 02 31 96 70 cb 32 8a 07 ff fc 00 00 00 04 38 00 20 81 84 0a 18 39 b8 22 18 00 00 40 40 0d 38 05 10 0d 60 1b 40 39 65 40 20 7f ff c0 00 00 00 43 80 02 08 18 40 a1 83 86 e1 08 60 00 04 02 c8 00 80 90 11 92 b0 a9 60 70 82 0b 07 06 08 70 80 38 94 0e 00 00 10 2f 7a 00 80 01 00 00 07 a0 00 a0 80 0c b9 c3 2c ca 8c 40 03 59 99 af b9 38 09 2f 28 56 f0 b1 63 da 27 0b 80 14 38 35 52 0d 40 40 82 21 06 10 18 04 60 01 a0 21 80 06 00 c5 0b da 04 14 2f 64 83 c8 d1 59 c0 00 20 00 3f a1 08 42 00 40 20 12 c0 e1 04 16 0e 0c 10 e1 00 71 28 1c 00 00 20 5e f4 01 00 02 00 00 0f 40 01 41 00 38 00 80 c4 00 00 00 20 50 24 a0 5e 0b 00 30 00 +[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] UE State = RRC_RECONFIGURED (default DRB, xid 1) +[RRC] E-RAB modification indication: nb nb_of_e_rabs 1 status 4 +[RRC] S1AP_E_RAB_MODIFICATION_IND: sending the message: nb_of_erabstobemodified 1, total e_rabs 1, index 1 + + + 50 + + + + + + 0 + + + 553648130 + + + + 8 + + + 420141 + + + + 199 + + + + + 200 + + + + 5 + + 11000000101010000001001011000110 + + 92 CC 30 02 + + + + + + + + + + + +[S1AP] Size of encoded message: 43 +[S1AP] initial context setup response: failed e_rab ID 5 +[SCTP] Successfully sent 43 bytes on stream 1 for assoc_id 903 +[SCTP] Sctp_sendmsg failed: Message too long +[GTPV1U] NW_GTP_END_MARKER +[PDCP] Handed SDU is of size 0! Ignoring... +[GTPV1U] PDCP data request failed, cause: [UE:43eb]RB is not configured! +[SCTP] Found data for descriptor 86 +[SCTP] Received notification for sd 86, type 32777 +[SCTP] Found data for descriptor 86 +[SCTP] [903][86] Msg of length 34 received from port 36412, on stream 1, PPID 18 +[S1AP] Implementation of S1AP E-RAB Modification confirm handler is pending... +[MAC] [eNB 0][PUSCH 1] CC_id 0 874.5 ULSCH in error in round 0, ul_cqi 158, UE_id 0, RNTI 43eb (len 63) +[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 18 PUCCH SNR 15 +[X2AP] X2 has 1 process ongoing +[X2AP] X2 has 1 process ongoing +[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 15 PUCCH SNR 16 +[RRC] UE rnti 43eb failure timer 0/8 +[PHY] prach_I0 = 0.0 dB +[PHY] max_I0 19, min_I0 12 +[MAC] [eNB 0][PUSCH 4] CC_id 0 73.2 ULSCH in error in round 0, ul_cqi 159, UE_id 0, RNTI 43eb (len 63) +[X2AP] X2 has 1 process ongoing +[MAC] [eNB 0][PUSCH 7] CC_id 0 114.3 ULSCH in error in round 0, ul_cqi 165, UE_id 0, RNTI 43eb (len 63) +[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 13 PUCCH SNR 10 +[X2AP] X2 has 1 process ongoing +[MAC] [eNB 0][PUSCH 0] CC_id 0 218.4 ULSCH in error in round 0, ul_cqi 158, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 6] CC_id 0 226.2 ULSCH in error in round 0, ul_cqi 164, UE_id 0, RNTI 43eb (len 63) +[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 13 PUCCH SNR 13 +[X2AP] X2 has 1 process ongoing +[X2AP] X2 has 1 process ongoing +[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 19 PUCCH SNR 15 +[X2AP] X2 has 1 process ongoing +[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 18 PUCCH SNR 13 +[X2AP] X2 has 1 process ongoing +[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 13 PUCCH SNR 15 +[X2AP] X2 has 1 process ongoing +[MAC] [eNB 0][PUSCH 2] CC_id 0 753.0 ULSCH in error in round 0, ul_cqi 164, UE_id 0, RNTI 43eb (len 63) +[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 18 PUCCH SNR 15 +[X2AP] X2 has 1 process ongoing +[X2AP] X2 has 1 process ongoing +[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 15 PUCCH SNR 16 + + + 13 + + + + + + 0 + + + 553648130 + + + + 8 + + + 420141 + + + + 26 + + + + 27 D6 DB 4F 5E 03 07 45 0B 0B F6 22 F2 10 80 00 + 01 00 00 00 37 + + + + + 100 + + + + 22 F2 10 + + 0000000011100000000100000000 + + + + + + 67 + + + + 22 F2 10 + 00 01 + + + + + + + + +[SCTP] Successfully sent 72 bytes on stream 1 for assoc_id 903 +[SCTP] Found data for descriptor 86 +[SCTP] Received notification for sd 86, type 32777 +[SCTP] Found data for descriptor 86 +[SCTP] [903][86] Msg of length 25 received from port 36412, on stream 1, PPID 18 +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] Logical Channel DL-DCCH, Generate RRCConnectionRelease (bytes 3) +[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB +[MAC] [eNB 0][PUSCH 3] CC_id 0 927.5 ULSCH in error in round 0, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 3] CC_id 0 928.3 ULSCH in error in round 1, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 3] CC_id 0 929.1 ULSCH in error in round 2, ul_cqi 112, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 3] CC_id 0 929.9 ULSCH in error in round 3, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 3] CC_id 0 930.7 ULSCH in error in round 0, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 3] CC_id 0 931.5 ULSCH in error in round 1, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 3] CC_id 0 932.3 ULSCH in error in round 2, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 3] CC_id 0 933.1 ULSCH in error in round 3, ul_cqi 128, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 3] CC_id 0 933.9 ULSCH in error in round 0, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 3] CC_id 0 934.7 ULSCH in error in round 1, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 3] CC_id 0 935.5 ULSCH in error in round 2, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 3] CC_id 0 936.3 ULSCH in error in round 3, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 936.8 ULSCH in error in round 0, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 937.6 ULSCH in error in round 1, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 938.4 ULSCH in error in round 2, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 939.2 ULSCH in error in round 3, ul_cqi 112, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 940.0 ULSCH in error in round 0, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 940.8 ULSCH in error in round 1, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 941.6 ULSCH in error in round 2, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 942.4 ULSCH in error in round 3, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 943.2 ULSCH in error in round 0, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 944.0 ULSCH in error in round 1, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 944.8 ULSCH in error in round 2, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 945.6 ULSCH in error in round 3, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 946.4 ULSCH in error in round 0, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 947.2 ULSCH in error in round 1, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 948.0 ULSCH in error in round 2, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 948.8 ULSCH in error in round 3, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 949.6 ULSCH in error in round 0, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 950.4 ULSCH in error in round 1, ul_cqi 112, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 951.2 ULSCH in error in round 2, ul_cqi 112, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 952.0 ULSCH in error in round 3, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 952.8 ULSCH in error in round 0, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 953.6 ULSCH in error in round 1, ul_cqi 112, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 954.4 ULSCH in error in round 2, ul_cqi 112, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 955.2 ULSCH in error in round 3, ul_cqi 112, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 956.0 ULSCH in error in round 0, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 956.8 ULSCH in error in round 1, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 957.6 ULSCH in error in round 2, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 958.4 ULSCH in error in round 3, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 959.2 ULSCH in error in round 0, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 960.0 ULSCH in error in round 1, ul_cqi 112, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 960.8 ULSCH in error in round 2, ul_cqi 122, UE_id 0, RNTI 43eb (len 63) +[MAC] [eNB 0][PUSCH 0] CC_id 0 961.6 ULSCH in error in round 3, ul_cqi 116, UE_id 0, RNTI 43eb (len 63) +[MAC] UE 0 rnti 43eb: UL Failure timer 1 +[RRC] S1AP removed entry in hashtable s1ap_id2_s1ap_ids for eNB_ue_s1ap_id 420141 +[RRC] S1AP removed entry in hashtable initial_id2_s1ap_ids for ue_initial_id 1 +[S1AP] Removed UE context eNB_ue_s1ap_id 420141 +[SCTP] Successfully sent 24 bytes on stream 1 for assoc_id 903 +[RRC] Removing UE 43eb instance after UE_CONTEXT_RELEASE_Complete (ue_release_timer_rrc timeout) +[RRC] [eNB 0] Removing UE RNTI 43eb +[RRC] Put UE 43eb into freeList +[RRC] clean_eNb_dlsch dlsch[2] UE 43eb +[MAC] clean eNb uci_vars[0] UE 43eb +[MAC] clean eNb uci_vars[1] UE 43eb +[MAC] clean eNb uci_vars[2] UE 43eb +[MAC] clean eNb uci_vars[3] UE 43eb +[RRC] remove UE 43eb from ul_config_pdu_list 0/1 +[MAC] Removing UE 0 from Primary CC_id 0 (rnti 43eb) +[PDCP] remove uid is 0/0 43eb +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] Removed UE context +[RRC] [release_UE_in_freeList] remove UE 43eb from freeList +[X2AP] X2 has 1 process ongoing +[SCTP] Found data for descriptor 86 +[SCTP] Received notification for sd 86, type 32777 +[PHY] prach_I0 = 0.0 dB +[PHY] max_I0 18, min_I0 12 +[X2AP] X2 has 1 process ongoing +[X2AP] X2 has 1 process ongoing +[X2AP] X2 has 1 process ongoing + \ No newline at end of file diff --git a/doc/testing_gnb_w_cots_ue_resources/oai_gnb.log b/doc/testing_gnb_w_cots_ue_resources/oai_gnb.log new file mode 100755 index 0000000000..37b3c10516 --- /dev/null +++ b/doc/testing_gnb_w_cots_ue_resources/oai_gnb.log @@ -0,0 +1,38680 @@ +[CONFIG] get parameters from libconfig ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.mozart.slave.conf , debug flags: 0x00000000 +[CONFIG] function config_libconfig_init returned 0 +[CONFIG] config module libconfig loaded +[LIBCONFIG] config: 1/1 parameters successfully set, (1 to default value) +Send signal 35 to display resource usage... +[LIBCONFIG] log_config: 3/3 parameters successfully set, (1 to default value) +[LIBCONFIG] log_config: 52/52 parameters successfully set, (46 to default value) +[LIBCONFIG] log_config: 52/52 parameters successfully set, (52 to default value) +[LIBCONFIG] log_config: 15/15 parameters successfully set, (15 to default value) +[LIBCONFIG] log_config: 15/15 parameters successfully set, (15 to default value) +log init done +[HW] # /dev/cpu_dma_latency set to 10 us +[HW] Can't set cpu frequency +Reading in command-line options +[GNB_APP] Getting GNBSParams +[LIBCONFIG] (root): 2/2 parameters successfully set, (0 to default value) +[LIBCONFIG] THREAD_STRUCT.[0]: 2/2 parameters successfully set, (0 to default value) +[LIBCONFIG] THREAD_STRUCT.[0]: 2/2 parameters successfully set, (0 to default value) +[CONFIG] parallel_conf is set to 0 +[CONFIG] worker_conf is set to 1 +Configuration: nb_rrc_inst 1, nb_nr_L1_inst 1, nb_ru 1 +[LIBCONFIG] (root): 23/23 parameters successfully set, (19 to default value) +[LIBCONFIG] (root): 5/5 parameters successfully set, (4 to default value) +[LIBCONFIG] TTracer: 4/4 parameters successfully set, (4 to default value) +configuring for RAU/RRU +CPU Freq is 3.092986 +[TMR] Starting itti queue: TASK_UNKNOWN as task 0 +[TMR] Starting itti queue: TASK_TIMER as task 1 +[TMR] Starting itti queue: TASK_L2L1 as task 2 +[TMR] Starting itti queue: TASK_BM as task 3 +[TMR] Starting itti queue: TASK_PHY_ENB as task 4 +[TMR] Starting itti queue: TASK_MAC_ENB as task 5 +[TMR] Starting itti queue: TASK_RLC_ENB as task 6 +[TMR] Starting itti queue: TASK_RRC_ENB_NB_IoT as task 7 +[TMR] Starting itti queue: TASK_PDCP_ENB as task 8 +[TMR] Starting itti queue: TASK_DATA_FORWARDING as task 9 +[TMR] Starting itti queue: TASK_END_MARKER as task 10 +[TMR] Starting itti queue: TASK_RRC_ENB as task 11 +[TMR] Starting itti queue: TASK_RRC_GNB as task 12 +[TMR] Starting itti queue: TASK_RAL_ENB as task 13 +[TMR] Starting itti queue: TASK_S1AP as task 14 +[TMR] Starting itti queue: TASK_X2AP as task 15 +[TMR] Starting itti queue: TASK_M2AP_ENB as task 16 +[TMR] Starting itti queue: TASK_M2AP_MCE as task 17 +[TMR] Starting itti queue: TASK_M3AP as task 18 +[TMR] Starting itti queue: TASK_M3AP_MME as task 19 +[TMR] Starting itti queue: TASK_M3AP_MCE as task 20 +[TMR] Starting itti queue: TASK_SCTP as task 21 +[TMR] Starting itti queue: TASK_ENB_APP as task 22 +[TMR] Starting itti queue: TASK_GNB_APP as task 23 +[TMR] Starting itti queue: TASK_MCE_APP as task 24 +[TMR] Starting itti queue: TASK_MME_APP as task 25 +[TMR] Starting itti queue: TASK_FLEXRAN_AGENT as task 26 +[TMR] Starting itti queue: TASK_PHY_UE as task 27 +[TMR] Starting itti queue: TASK_MAC_UE as task 28 +[TMR] Starting itti queue: TASK_RLC_UE as task 29 +[TMR] Starting itti queue: TASK_PDCP_UE as task 30 +[TMR] Starting itti queue: TASK_RRC_UE as task 31 +[TMR] Starting itti queue: TASK_NAS_UE as task 32 +[TMR] Starting itti queue: TASK_RAL_UE as task 33 +[TMR] Starting itti queue: TASK_MSC as task 34 +[TMR] Starting itti queue: TASK_GTPV1_U as task 35 +[TMR] Starting itti queue: TASK_UDP as task 36 +[TMR] Starting itti queue: TASK_CU_F1 as task 37 +[TMR] Starting itti queue: TASK_DU_F1 as task 38 +[LIBCONFIG] opt: 3/3 parameters successfully set, (3 to default value) +[OPT] OPT disabled +[NETLINK] Error opening socket -1 (93:Protocol not supported) +[NETLINK] Opened socket with fd -1 +[NETLINK] Error fcntl (9:Bad file descriptor) +[HW] Version: Branch: NR_RRC_harq_hacks Abrev. Hash: 94fa9c5 Date: Fri Jun 19 18:16:53 2020 +0200 +Wait for the ITTI initialize message +[TMR] Created Posix thread TASK_L2L1 +[SCTP] Starting SCTP layer +[TMR] Created Posix thread TASK_SCTP +[LIBCONFIG] eNBs.[0]: 1/1 parameters successfully set, (1 to default value) +[LIBCONFIG] gNBs.[0]: 1/1 parameters successfully set, (0 to default value) +[TMR] Created Posix thread TASK_X2AP +[UDP] Initializing UDP task interface +[UDP] Initializing UDP task interface: DONE +[TMR] Created Posix thread TASK_UDP +[TMR] Created Posix thread TASK_GTPV1_U +[GTPV1U] Initializing GTPU stack 0x17ce250 +[PHY] gNB_app_task() Task ready initialize structures +[TMR] Created Posix thread TASK_GNB_APP +[NR_RRC] Creating NR RRC gNB Task +[NR_PHY] RC.gNB = 0x7f518c0008c0 +[LIBCONFIG] L1s.[0]: 24/24 parameters successfully set, (22 to default value) +[NR_PHY] RC.gNB[0] = 0x7f51a2f08010 +[NR_RRC] Entering main loop of NR_RRC message task +[TMR] Created Posix thread TASK_RRC_GNB +Initializing northbound interface for L1 +[PHY] l1_north_init_gNB() RC.nb_nr_L1_inst:1 +[PHY] Installing callbacks for IF_Module - UL_indication +[MAC] Allocating shared L1/L2 interface structure for instance 0 @ 0x7f518c001970 +[PHY] l1_north_init_gNB() RC.gNB[0] installing callbacks +[LIBCONFIG] MACRLCs.[0]: 20/20 parameters successfully set, (17 to default value) +[MAC] [MAIN] Init function start:nb_nr_macrlc_inst=1 +NFAPI MODE:MONOLITHIC +START MAIN THREADS +RC.nb_nr_L1_inst:1 +Initializing gNB threads single_thread_flag:1 wait_for_sync:0 +[PHY] gNB L1 structure RC.gNB allocated @ 0x7f518c0008c0 +[PHY] [lte-softmodem.c] gNB structure RC.gNB[0] allocated @ 0x7f51a2f08010 +[PHY] Initializing gNB 0 single_thread_flag:1 +[PHY] Initializing gNB 0 +[PHY] Registering with MAC interface module (before 0x7f518c001970) +[PHY] Installing callbacks for IF_Module - UL_indication +[PHY] Registering with MAC interface module (after 0x7f518c001970) +[PHY] Setting indication lists +[PHY] [nr-softmodem.c] gNB structure allocated +wait_gNBs() +Waiting for gNB L1 instances to all get configured ... sleeping 50ms (nb_nr_sL1_inst 1) +[PDCP] PDCP layer has been initialized +[PHY] Installing callbacks for IF_Module - UL_indication +[PHY] gNB_app_task() RC.nb_nr_L1_inst:1 +[PHY] l1_north_init_gNB() RC.nb_nr_L1_inst:1 +[PHY] Installing callbacks for IF_Module - UL_indication +[PHY] l1_north_init_gNB() RC.gNB[0] installing callbacks +[GNB_APP] Allocating gNB_RRC_INST for 1 instances +[PHY] gNB_app_task() RC.nb_nr_inst:1 RC.nrrrc:0x7f518c002860 +[PHY] gNB_app_task() Creating RRC instance RC.nrrrc[0]:0x7f518c002ad0 (1 of 1) +[LIBCONFIG] (root): 2/2 parameters successfully set, (0 to default value) +[LIBCONFIG] gNBs.[0]: 14/14 parameters successfully set, (8 to default value) +[LIBCONFIG] gNBs.[0].servingCellConfigCommon.[0]: 155/155 parameters successfully set, (83 to default value) +[RRC] Read in ServingCellConfigCommon (PhysCellId 0, ABSFREQSSB 641272, DLBand 78, ABSFREQPOINTA 640000, DLBW 106,RACH_TargetReceivedPower -100 +Checking element 15 : 4294967295 +removing pdsch_TimeDomainAllocationList element 15 +List size now 15 +Checking element 14 : 4294967295 +removing pdsch_TimeDomainAllocationList element 14 +List size now 14 +Checking element 13 : 4294967295 +removing pdsch_TimeDomainAllocationList element 13 +List size now 13 +Checking element 12 : 4294967295 +removing pdsch_TimeDomainAllocationList element 12 +List size now 12 +Checking element 11 : 4294967295 +removing pdsch_TimeDomainAllocationList element 11 +List size now 11 +Checking element 10 : 4294967295 +removing pdsch_TimeDomainAllocationList element 10 +List size now 10 +Checking element 9 : 4294967295 +removing pdsch_TimeDomainAllocationList element 9 +List size now 9 +Checking element 8 : 4294967295 +removing pdsch_TimeDomainAllocationList element 8 +List size now 8 +Checking element 7 : 4294967295 +removing pdsch_TimeDomainAllocationList element 7 +List size now 7 +Checking element 6 : 4294967295 +removing pdsch_TimeDomainAllocationList element 6 +List size now 6 +Checking element 5 : 4294967295 +removing pdsch_TimeDomainAllocationList element 5 +List size now 5 +Checking element 4 : 4294967295 +removing pdsch_TimeDomainAllocationList element 4 +List size now 4 +Checking element 3 : 0 +Checking element 2 : 0 +Checking element 1 : 0 +Checking element 0 : 0 +NRRRC 0: Southbound Transport local_mac +[LIBCONFIG] gNBs.[0].plmn_list.[0]: 3/3 parameters successfully set, (0 to default value) +SSB SCO 31 +pdsch_AntennaPorts 1 +[GNB_APP] Sending configuration message to NR_RRC task +[X2AP] X2AP enabled +[X2AP] GNB_ID: 0 +[LIBCONFIG] (root): 2/2 parameters successfully set, (0 to default value) +[NR_RRC] Received message NRRRC_CONFIGURATION_REQ +[NR_RRC] [gNB 0] Received NRRRC_CONFIGURATION_REQ : 0x7f518c00407c +[NR_RRC] [FRAME 00000][eNB][MOD 00][RNTI 0] Init... +[LIBCONFIG] gNBs.[0]: 14/14 parameters successfully set, (8 to default value) +[LIBCONFIG] gNBs.[0].plmn_list.[0]: 3/3 parameters successfully set, (0 to default value) +[LIBCONFIG] gNBs.[0].target_enb_x2_ip_address.[0]: 3/3 parameters successfully set, (0 to default value) +[LIBCONFIG] gNBs.[0]: 2/2 parameters successfully set, (0 to default value) +[LIBCONFIG] gNBs.[0].SCTP: 2/2 parameters successfully set, (0 to default value) +[NR_RRC] [FRAME 00000][eNB][MOD 00][RNTI 0] Checking release +[LIBCONFIG] gNBs.[0].NETWORK_INTERFACES: 7/7 parameters successfully set, (0 to default value) +[GTPV1U] Configuring GTPu +[LIBCONFIG] (root): 2/2 parameters successfully set, (0 to default value) +[NR_RRC] Done init_NR_SI +[LIBCONFIG] gNBs.[0].NETWORK_INTERFACES: 3/3 parameters successfully set, (0 to default value) +[MAC] Configuring common parameters from NR ServingCellConfig +[PHY] config_common() dl_BandwidthP:40 +[GTPV1U] Configuring GTPu address : 192.168.18.198 -> c612a8c0 +[PHY] Computing dl_frequency (pointA 640000 => 3600000000 (dlmin 3300000, nr_bandtable[27].N_OFFs_DL 620000)) +[PHY] config_common() dl_BandwidthP:40 +[GNB_APP] [gNB 0] gNB_app_register for instance 0 +[GTPV1U] Tx UDP_INIT IP addr 192.168.18.198 (868) +[PHY] Computing dl_frequency (pointA 640000 => 3600000000 (dlmin 3300000, nr_bandtable[27].N_OFFs_DL 620000)) +[PHY] Scanning band 1, dl_min 2110000, ul_min 1920000 +[PHY] Scanning band 2, dl_min 1930000, ul_min 1850000 +[PHY] Scanning band 3, dl_min 1805000, ul_min 1710000 +[PHY] Scanning band 5, dl_min 869000, ul_min 824000 +[PHY] Scanning band 7, dl_min 2620000, ul_min 2500000 +[UDP] Initializing UDP for local address 192.168.18.198 with port 2152 +[PHY] Scanning band 8, dl_min 925000, ul_min 880000 +[PHY] Scanning band 12, dl_min 728000, ul_min 698000 +[PHY] Scanning band 20, dl_min 791000, ul_min 832000 +[PHY] Scanning band 25, dl_min 1930000, ul_min 1850000 +[PHY] Scanning band 28, dl_min 758000, ul_min 703000 +[PHY] Scanning band 34, dl_min 2010000, ul_min 2010000 +[PHY] Scanning band 38, dl_min 2570000, ul_min 2570000 +[PHY] Scanning band 39, dl_min 1880000, ul_min 1880000 +[PHY] Scanning band 40, dl_min 2300000, ul_min 2300000 +[PHY] Scanning band 41, dl_min 2496000, ul_min 2496000 +[PHY] Scanning band 41, dl_min 2496000, ul_min 2496000 +[PHY] Scanning band 50, dl_min 1432000, ul_min 1432000 +[PHY] Scanning band 51, dl_min 1427000, ul_min 1427000 +[PHY] Scanning band 66, dl_min 2110000, ul_min 1710000 +[PHY] Scanning band 70, dl_min 1995000, ul_min 1695000 +[PHY] Scanning band 71, dl_min 617000, ul_min 663000 +[PHY] Scanning band 74, dl_min 1475000, ul_min 1427000 +[PHY] Scanning band 75, dl_min 1432000, ul_min 0 +[PHY] Scanning band 76, dl_min 1427000, ul_min 0 +[PHY] Scanning band 77, dl_min 3300000, ul_min 3300000 +[PHY] Scanning band 77, dl_min 3300000, ul_min 3300000 +[PHY] Scanning band 78, dl_min 3300000, ul_min 3300000 +[PHY] Scanning band 78, dl_min 3300000, ul_min 3300000 +[PHY] Scanning band 79, dl_min 4400000, ul_min 4400000 +[PHY] Scanning band 79, dl_min 4400000, ul_min 4400000 +[PHY] Scanning band 80, dl_min 0, ul_min 1710000 +[PHY] Scanning band 81, dl_min 0, ul_min 860000 +[PHY] Scanning band 82, dl_min 0, ul_min 832000 +[PHY] Scanning band 83, dl_min 0, ul_min 703000 +[PHY] Scanning band 84, dl_min 0, ul_min 1920000 +[PHY] Scanning band 86, dl_min 0, ul_min 1710000 +[PHY] Scanning band 257, dl_min 26500000, ul_min 26500000 +[PHY] Scanning band 257, dl_min 26500000, ul_min 26500000 +[PHY] Scanning band 258, dl_min 24250000, ul_min 24250000 +[PHY] Scanning band 258, dl_min 24250000, ul_min 24250000 +[PHY] Scanning band 260, dl_min 37000000, ul_min 37000000 +[PHY] Scanning band 260, dl_min 37000000, ul_min 37000000 +[PHY] Scanning band 261, dl_min 27500000, ul_min 27500000 +[PHY] Scanning band 261, dl_min 27500000, ul_min 27500000 +[PHY] DL frequency 3600000000: band 78, frame_type 1, UL frequency 3600000000 + found_sequences 16 +[MAC] Set TX/RX antenna number to 1 (num ssb 1: 80000000,0) +[MAC] Setting TDD configuration period to 6 +[PHY] TDD has been properly configurated +[MAC] rrc_mac_config_req_gNB() /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/openair2/LAYER2/NR_MAC_gNB/config.c:345 RC.nrmac[Mod_idP]->if_inst->NR_PHY_config_req:0x60f680 +[PHY] Scanning band 1, dl_min 2110000, ul_min 1920000 +[PHY] Scanning band 2, dl_min 1930000, ul_min 1850000 +[PHY] Scanning band 3, dl_min 1805000, ul_min 1710000 +[PHY] Scanning band 5, dl_min 869000, ul_min 824000 +[PHY] Scanning band 7, dl_min 2620000, ul_min 2500000 +[PHY] Scanning band 8, dl_min 925000, ul_min 880000 +[PHY] Scanning band 12, dl_min 728000, ul_min 698000 +[PHY] Scanning band 20, dl_min 791000, ul_min 832000 +[PHY] Scanning band 25, dl_min 1930000, ul_min 1850000 +[PHY] Scanning band 28, dl_min 758000, ul_min 703000 +[PHY] Scanning band 34, dl_min 2010000, ul_min 2010000 +[PHY] Scanning band 38, dl_min 2570000, ul_min 2570000 +[PHY] Scanning band 39, dl_min 1880000, ul_min 1880000 +[PHY] Scanning band 40, dl_min 2300000, ul_min 2300000 +[PHY] Scanning band 41, dl_min 2496000, ul_min 2496000 +[PHY] Scanning band 41, dl_min 2496000, ul_min 2496000 +[PHY] Scanning band 50, dl_min 1432000, ul_min 1432000 +[PHY] Scanning band 51, dl_min 1427000, ul_min 1427000 +[PHY] Scanning band 66, dl_min 2110000, ul_min 1710000 +[PHY] Scanning band 70, dl_min 1995000, ul_min 1695000 +[PHY] Scanning band 71, dl_min 617000, ul_min 663000 +[PHY] Scanning band 74, dl_min 1475000, ul_min 1427000 +[PHY] Scanning band 75, dl_min 1432000, ul_min 0 +[PHY] Scanning band 76, dl_min 1427000, ul_min 0 +[PHY] Scanning band 77, dl_min 3300000, ul_min 3300000 +[PHY] Scanning band 77, dl_min 3300000, ul_min 3300000 +[PHY] Scanning band 78, dl_min 3300000, ul_min 3300000 +[PHY] Scanning band 78, dl_min 3300000, ul_min 3300000 +[PHY] Scanning band 79, dl_min 4400000, ul_min 4400000 +[PHY] Scanning band 79, dl_min 4400000, ul_min 4400000 +[PHY] Scanning band 80, dl_min 0, ul_min 1710000 +[PHY] Scanning band 81, dl_min 0, ul_min 860000 +[PHY] Scanning band 82, dl_min 0, ul_min 832000 +[PHY] Scanning band 83, dl_min 0, ul_min 703000 +[PHY] Scanning band 84, dl_min 0, ul_min 1920000 +[PHY] Scanning band 86, dl_min 0, ul_min 1710000 +[PHY] Scanning band 257, dl_min 26500000, ul_min 26500000 +[PHY] Scanning band 257, dl_min 26500000, ul_min 26500000 +[PHY] Scanning band 258, dl_min 24250000, ul_min 24250000 +[PHY] Scanning band 258, dl_min 24250000, ul_min 24250000 +[PHY] Scanning band 260, dl_min 37000000, ul_min 37000000 +[PHY] Scanning band 260, dl_min 37000000, ul_min 37000000 +[PHY] Scanning band 261, dl_min 27500000, ul_min 27500000 +[PHY] Scanning band 261, dl_min 27500000, ul_min 27500000 +[PHY] DL frequency 3619080000: band 78, frame_type 1, UL frequency 3619080000 +[PHY] Configuring MIB for instance 0, : (Nid_cell 0,DL freq 3619080000, UL freq 3619080000) +[PHY] Initializing frame parms for mu 1, N_RB 106, Ncp 0 +[X2AP] Registered new eNB[0] and home eNB id 3584 +[X2AP] eNB[0] eNB id 3584 acting as a listner (server) +[SCTP] Received SCTP_INIT_MSG_MULTI_REQ +[UDP] Inserting new descriptor for task 35, sd 85 +[UDP] Initializing UDP for local address 192.168.18.198 with port 2152: DONE +[PHY] gNB 0 configured +[NR_RRC] [FRAME 00000][eNB][MOD 00][RNTI 0] gNB:OPENAIR NR RRC IN.... +[SCTP] Creating new listen socket on port 36422 with +[SCTP] ipv4 addresses: +[SCTP] - 192.168.18.198 +[X2AP] eNB[0] eNB id 3584 acting as an initiator (client) +[SCTP] Converted ipv4 address 192.168.18.199 to network type +[SCTP] sctp_connectx SUCCESS, used 1 addresses assoc_id 136 +[SCTP] Inserted new descriptor for sd 87 in list, nb elements 2, assoc_id 136 +[SCTP] Found data for descriptor 87 +[SCTP] Received notification for sd 87, type 32769 +[SCTP] Client association changed: 0 +[SCTP] ---------------------- +[SCTP] Peer addresses: +[SCTP] - [192.168.18.199] +[SCTP] ---------------------- +[SCTP] ---------------------- +[SCTP] SCTP Status: +[SCTP] assoc id .....: 136 +[SCTP] state ........: 4 +[SCTP] instrms ......: 32 +[SCTP] outstrms .....: 32 +[SCTP] fragmentation : 1452 +[SCTP] pending data .: 0 +[SCTP] unack data ...: 0 +[SCTP] rwnd .........: 106496 +[SCTP] peer info : +[SCTP] state ....: 2 +[SCTP] cwnd .....: 4380 +[SCTP] srtt .....: 0 +[SCTP] rto ......: 3000 +[SCTP] mtu ......: 1500 +[SCTP] ---------------------- +[SCTP] Comm up notified for sd 87, assigned assoc_id 136 +here comes the tree (instance 0): +--------------------------------------------- +----------------------- +eNB id 0 (null) +state 1 +nextstream 0 +in_streams 0 out_streams 0 +cnx_id 1 assoc_id -1 +--------------------------------------------- +here comes the tree (instance 0): +--------------------------------------------- +----------------------- +eNB id 0 (null) +state 1 +nextstream 0 +in_streams 0 out_streams 0 +cnx_id 1 assoc_id -1 +--------------------------------------------- +here comes the tree (instance 0): +--------------------------------------------- +----------------------- +eNB id 0 (null) +state 1 +nextstream 0 +in_streams 0 out_streams 0 +cnx_id 1 assoc_id -1 +--------------------------------------------- +here comes the tree (instance 0): +--------------------------------------------- +----------------------- +eNB id 0 (null) +state 1 +nextstream 0 +in_streams 32 out_streams 32 +cnx_id 1 assoc_id 136 +--------------------------------------------- +[X2AP] 3584 -> 00000e +[X2AP] TAC: 25744 -> 006490 + + + 36 + + + + + + 244 + + + + + + 252 + + + + 22 F2 10 + + + 00000000000000000000111000000000 + + + + + + + 253 + + + + + + 0 + + 22 F2 10 + + 000000000000000000000000111000000000 + + + 00 64 90 + + 22 F2 10 + + + + + 0 + + + 1 + + + 80 + + + + + + + + + + + + 00 + + + + + + + + + + + + + + +[SCTP] Successfully sent 66 bytes on stream 0 for assoc_id 136 +[SCTP] Found data for descriptor 87 +[SCTP] Received notification for sd 87, type 32777 +[SCTP] Found data for descriptor 87 +[SCTP] [136][87] Msg of length 53 received from port 36422, on stream 0, PPID 27 + + + 36 + + + + + + 246 + + + + + + 21 + + + + 22 F2 10 + + + 00000000111000000001 + + + + + + + 250 + + + + + + 0 + + 22 F2 10 + + 0000000011100000000100000000 + + + 00 01 + + 22 F2 10 + + + + 21350 + 3350 + + + + + + + + + + + + + + + + + + +[X2AP] x2ap_eNB_decode_successfuloutcome_message! +gNB L1 are configured +About to Init RU threads RC.nb_RU:1 +Initializing RU threads +configuring RU from file +[LIBCONFIG] RUs.[0]: 27/27 parameters successfully set, (17 to default value) +Set RU mask to 1 +Creating RC.ru[0]:0x3ae67d0 +Setting function for RU 0 to gNodeB_3GPP +[PHY] number of L1 instances 1, number of RU 1, number of CPU cores 10 +[PHY] DJP - delete code above this /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/executables/nr-ru.c:2251 +[PHY] Copying frame parms from gNB in RC to gNB 0 in ru 0 and frame_parms in ru +configuring ru_id 0 (start_rf 0x5b7120) +[PHY] Starting ru_thread 0 +[PHY] Initializing RU proc 0 (,synch_to_ext_device), +[PHY] Starting RU 0 (,synch_to_ext_device), +[PHY] Initializing frame parms for mu 1, N_RB 106, Ncp 0 +[PHY] fp->scs=30000 +[PHY] fp->ofdm_symbol_size=1536 +[PHY] fp->nb_prefix_samples0=132 +[PHY] fp->nb_prefix_samples=108 +[PHY] fp->slots_per_subframe=2 +[PHY] fp->samples_per_subframe_wCP=43008 +[PHY] init_RU_proc() DJP - added creation of pthread_prach +[PHY] fp->samples_per_frame_wCP=430080 +[PHY] fp->samples_per_subframe=46080 +[PHY] fp->samples_per_frame=460800 +[PHY] fp->dl_CarrierFreq=3619080000 +[PHY] fp->ul_CarrierFreq=3619080000 +channel 0, Setting tx_gain offset 0.000000, rx_gain offset 114.000000, tx_freq 3619080000.000000, rx_freq 3619080000.000000 +[PHY] Initializing RU signal buffers (if_south local RF) nb_tx 1 +[PHY] [INIT] common.txdata[0] = 0x7f5198339040 (1843200 bytes) +[PHY] nb_tx 1 +[PHY] rxdata_7_5kHz[0] 0x7f51980c1040 for RU 0 +[PHY] init feptx thread 0 +[PHY] [INIT] common.txdata_BF= 0x7f517c000aa0 (8 bytes) +[PHY] txdataF_BF[0] 0x7f51a2e9c040 for RU 0 +[PHY] init feptx thread 1 +wait RUs +[PHY] Waiting for RUs to be configured ... RC.ru_mask:01 +[PHY] rxdataF[0] 0x7f51a2e47040 for RU 0 +[PHY] [INIT] nr_phy_init_RU() RC.nb_nr_L1_inst:1 +[LIBCONFIG] device.recplay: 7/7 parameters successfully set, (7 to default value) +[LIBCONFIG] device: 1/1 parameters successfully set, (1 to default value) +[LIBCONFIG] loader: 2/2 parameters successfully set, (2 to default value) +[LIBCONFIG] loader.oai_device: 2/2 parameters successfully set, (1 to default value) +[LOADER] library liboai_device.so successfully loaded +[HW] UHD version 3.15.0.0-0-gaea0e2de (3.15.0) +[HW] Found USRP b200 +Found USRP b200 +[PHY] ru_thread_prach() RACH waiting for RU to be configured +[HW] Time source set neither in usrp_args nor on command line, using default! +[HW] cal 0: freq 3500000000.000000, offset 44.000000, diff 119080000.000000 +[HW] cal 1: freq 2660000000.000000, offset 49.800000, diff 959080000.000000 +[HW] cal 2: freq 2300000000.000000, offset 51.000000, diff 1319080000.000000 +[HW] cal 3: freq 1880000000.000000, offset 53.000000, diff 1739080000.000000 +[HW] cal 4: freq 816000000.000000, offset 57.000000, diff 2803080000.000000 +[HW] RX Gain 0 114.000000 (44.000000) => 70.000000 (max 76.000000) +[HW] USRP TX_GAIN:89.75 gain_range:89.75 tx_gain:0.00 +[HW] Actual master clock: 46.080000MHz... +[HW] Actual clock source internal... +[HW] Actual time source internal... +[PHY] ru_thread_prach() RACH waiting for RU to be configured +[HW] RF board max packet size 1916, size for 100µs jitter 4608 +[HW] rx_max_num_samps 1916 +[HW] RX Channel 0 +[HW] Actual RX sample rate: 46.080000MSps... +[HW] Actual RX frequency: 3.619080GHz... +[HW] Actual RX gain: 70.000000... +[HW] Actual RX bandwidth: 40.000000M... +[HW] Actual RX antenna: RX2... +[HW] TX Channel 0 +[HW] Actual TX sample rate: 46.080000MSps... +[HW] Actual TX frequency: 3.619080GHz... +[HW] Actual TX gain: 89.750000... +[HW] Actual TX bandwidth: 40.000000M... +[HW] Actual TX antenna: TX/RX... +[HW] Actual TX packet size: 1916 +[HW] Device timestamp: 2.171687... +[HW] [RAU] has loaded USRP B200 device. +setup_RU_buffers: frame_parms = 0x7f51a2ec7010 +[PHY] RU 0 Setting N_TA_offset to 600 samples (factor 1.500000, UL Freq 3600000, N_RB 106) +[PHY] Signaling main thread that RU 0 is ready +waiting for sync (ru_thread,-1/0xf53a58,0x18e6f00,0x17ccc40) +RC.ru_mask:00 +[PHY] RUs configured +ALL RUs READY! +RC.nb_RU:1 +ALL RUs ready - init gNBs +Not NFAPI mode - call init_eNB_afterRU() +[PHY] init_eNB_afterRU() RC.nb_nr_inst:1 +[PHY] RC.nb_nr_CC[inst:0]:0x7f51a2f08010 +[PHY] [gNB 0] phy_init_nr_gNB() About to wait for gNB to be configured +[LIBCONFIG] loader.dfts: 2/2 parameters successfully set, (1 to default value) +[LOADER] library libdfts.so successfully loaded +init_scrambling_luts: s 0 (1) ((1,1),(1,1),(1,1),(1,1)) +init_scrambling_luts: s 1 (-1) ((-1,1),(1,1),(1,1),(1,1)) +init_scrambling_luts: s 2 (1) ((1,-1),(1,1),(1,1),(1,1)) +init_scrambling_luts: s 3 (-1) ((-1,-1),(1,1),(1,1),(1,1)) +init_scrambling_luts: s 4 (1) ((1,1),(-1,1),(1,1),(1,1)) +init_scrambling_luts: s 5 (-1) ((-1,1),(-1,1),(1,1),(1,1)) +init_scrambling_luts: s 6 (1) ((1,-1),(-1,1),(1,1),(1,1)) +init_scrambling_luts: s 7 (-1) ((-1,-1),(-1,1),(1,1),(1,1)) +init_scrambling_luts: s 8 (1) ((1,1),(1,-1),(1,1),(1,1)) +init_scrambling_luts: s 9 (-1) ((-1,1),(1,-1),(1,1),(1,1)) +init_scrambling_luts: s a (1) ((1,-1),(1,-1),(1,1),(1,1)) +init_scrambling_luts: s b (-1) ((-1,-1),(1,-1),(1,1),(1,1)) +init_scrambling_luts: s c (1) ((1,1),(-1,-1),(1,1),(1,1)) +init_scrambling_luts: s d (-1) ((-1,1),(-1,-1),(1,1),(1,1)) +init_scrambling_luts: s e (1) ((1,-1),(-1,-1),(1,1),(1,1)) +init_scrambling_luts: s f (-1) ((-1,-1),(-1,-1),(1,1),(1,1)) +init_scrambling_luts: s 10 (1) ((1,1),(1,1),(-1,1),(1,1)) +init_scrambling_luts: s 11 (-1) ((-1,1),(1,1),(-1,1),(1,1)) +init_scrambling_luts: s 12 (1) ((1,-1),(1,1),(-1,1),(1,1)) +init_scrambling_luts: s 13 (-1) ((-1,-1),(1,1),(-1,1),(1,1)) +init_scrambling_luts: s 14 (1) ((1,1),(-1,1),(-1,1),(1,1)) +init_scrambling_luts: s 15 (-1) ((-1,1),(-1,1),(-1,1),(1,1)) +init_scrambling_luts: s 16 (1) ((1,-1),(-1,1),(-1,1),(1,1)) +init_scrambling_luts: s 17 (-1) ((-1,-1),(-1,1),(-1,1),(1,1)) +init_scrambling_luts: s 18 (1) ((1,1),(1,-1),(-1,1),(1,1)) +init_scrambling_luts: s 19 (-1) ((-1,1),(1,-1),(-1,1),(1,1)) +init_scrambling_luts: s 1a (1) ((1,-1),(1,-1),(-1,1),(1,1)) +init_scrambling_luts: s 1b (-1) ((-1,-1),(1,-1),(-1,1),(1,1)) +init_scrambling_luts: s 1c (1) ((1,1),(-1,-1),(-1,1),(1,1)) +init_scrambling_luts: s 1d (-1) ((-1,1),(-1,-1),(-1,1),(1,1)) +init_scrambling_luts: s 1e (1) ((1,-1),(-1,-1),(-1,1),(1,1)) +init_scrambling_luts: s 1f (-1) ((-1,-1),(-1,-1),(-1,1),(1,1)) +init_scrambling_luts: s 20 (1) ((1,1),(1,1),(1,-1),(1,1)) +init_scrambling_luts: s 21 (-1) ((-1,1),(1,1),(1,-1),(1,1)) +init_scrambling_luts: s 22 (1) ((1,-1),(1,1),(1,-1),(1,1)) +init_scrambling_luts: s 23 (-1) ((-1,-1),(1,1),(1,-1),(1,1)) +init_scrambling_luts: s 24 (1) ((1,1),(-1,1),(1,-1),(1,1)) +init_scrambling_luts: s 25 (-1) ((-1,1),(-1,1),(1,-1),(1,1)) +init_scrambling_luts: s 26 (1) ((1,-1),(-1,1),(1,-1),(1,1)) +init_scrambling_luts: s 27 (-1) ((-1,-1),(-1,1),(1,-1),(1,1)) +init_scrambling_luts: s 28 (1) ((1,1),(1,-1),(1,-1),(1,1)) +init_scrambling_luts: s 29 (-1) ((-1,1),(1,-1),(1,-1),(1,1)) +init_scrambling_luts: s 2a (1) ((1,-1),(1,-1),(1,-1),(1,1)) +init_scrambling_luts: s 2b (-1) ((-1,-1),(1,-1),(1,-1),(1,1)) +init_scrambling_luts: s 2c (1) ((1,1),(-1,-1),(1,-1),(1,1)) +init_scrambling_luts: s 2d (-1) ((-1,1),(-1,-1),(1,-1),(1,1)) +init_scrambling_luts: s 2e (1) ((1,-1),(-1,-1),(1,-1),(1,1)) +init_scrambling_luts: s 2f (-1) ((-1,-1),(-1,-1),(1,-1),(1,1)) +init_scrambling_luts: s 30 (1) ((1,1),(1,1),(-1,-1),(1,1)) +init_scrambling_luts: s 31 (-1) ((-1,1),(1,1),(-1,-1),(1,1)) +init_scrambling_luts: s 32 (1) ((1,-1),(1,1),(-1,-1),(1,1)) +init_scrambling_luts: s 33 (-1) ((-1,-1),(1,1),(-1,-1),(1,1)) +init_scrambling_luts: s 34 (1) ((1,1),(-1,1),(-1,-1),(1,1)) +init_scrambling_luts: s 35 (-1) ((-1,1),(-1,1),(-1,-1),(1,1)) +init_scrambling_luts: s 36 (1) ((1,-1),(-1,1),(-1,-1),(1,1)) +init_scrambling_luts: s 37 (-1) ((-1,-1),(-1,1),(-1,-1),(1,1)) +init_scrambling_luts: s 38 (1) ((1,1),(1,-1),(-1,-1),(1,1)) +init_scrambling_luts: s 39 (-1) ((-1,1),(1,-1),(-1,-1),(1,1)) +init_scrambling_luts: s 3a (1) ((1,-1),(1,-1),(-1,-1),(1,1)) +init_scrambling_luts: s 3b (-1) ((-1,-1),(1,-1),(-1,-1),(1,1)) +init_scrambling_luts: s 3c (1) ((1,1),(-1,-1),(-1,-1),(1,1)) +init_scrambling_luts: s 3d (-1) ((-1,1),(-1,-1),(-1,-1),(1,1)) +init_scrambling_luts: s 3e (1) ((1,-1),(-1,-1),(-1,-1),(1,1)) +init_scrambling_luts: s 3f (-1) ((-1,-1),(-1,-1),(-1,-1),(1,1)) +init_scrambling_luts: s 40 (1) ((1,1),(1,1),(1,1),(-1,1)) +init_scrambling_luts: s 41 (-1) ((-1,1),(1,1),(1,1),(-1,1)) +init_scrambling_luts: s 42 (1) ((1,-1),(1,1),(1,1),(-1,1)) +init_scrambling_luts: s 43 (-1) ((-1,-1),(1,1),(1,1),(-1,1)) +init_scrambling_luts: s 44 (1) ((1,1),(-1,1),(1,1),(-1,1)) +init_scrambling_luts: s 45 (-1) ((-1,1),(-1,1),(1,1),(-1,1)) +init_scrambling_luts: s 46 (1) ((1,-1),(-1,1),(1,1),(-1,1)) +init_scrambling_luts: s 47 (-1) ((-1,-1),(-1,1),(1,1),(-1,1)) +init_scrambling_luts: s 48 (1) ((1,1),(1,-1),(1,1),(-1,1)) +init_scrambling_luts: s 49 (-1) ((-1,1),(1,-1),(1,1),(-1,1)) +init_scrambling_luts: s 4a (1) ((1,-1),(1,-1),(1,1),(-1,1)) +init_scrambling_luts: s 4b (-1) ((-1,-1),(1,-1),(1,1),(-1,1)) +init_scrambling_luts: s 4c (1) ((1,1),(-1,-1),(1,1),(-1,1)) +init_scrambling_luts: s 4d (-1) ((-1,1),(-1,-1),(1,1),(-1,1)) +init_scrambling_luts: s 4e (1) ((1,-1),(-1,-1),(1,1),(-1,1)) +init_scrambling_luts: s 4f (-1) ((-1,-1),(-1,-1),(1,1),(-1,1)) +init_scrambling_luts: s 50 (1) ((1,1),(1,1),(-1,1),(-1,1)) +init_scrambling_luts: s 51 (-1) ((-1,1),(1,1),(-1,1),(-1,1)) +init_scrambling_luts: s 52 (1) ((1,-1),(1,1),(-1,1),(-1,1)) +init_scrambling_luts: s 53 (-1) ((-1,-1),(1,1),(-1,1),(-1,1)) +init_scrambling_luts: s 54 (1) ((1,1),(-1,1),(-1,1),(-1,1)) +init_scrambling_luts: s 55 (-1) ((-1,1),(-1,1),(-1,1),(-1,1)) +init_scrambling_luts: s 56 (1) ((1,-1),(-1,1),(-1,1),(-1,1)) +init_scrambling_luts: s 57 (-1) ((-1,-1),(-1,1),(-1,1),(-1,1)) +init_scrambling_luts: s 58 (1) ((1,1),(1,-1),(-1,1),(-1,1)) +init_scrambling_luts: s 59 (-1) ((-1,1),(1,-1),(-1,1),(-1,1)) +init_scrambling_luts: s 5a (1) ((1,-1),(1,-1),(-1,1),(-1,1)) +init_scrambling_luts: s 5b (-1) ((-1,-1),(1,-1),(-1,1),(-1,1)) +init_scrambling_luts: s 5c (1) ((1,1),(-1,-1),(-1,1),(-1,1)) +init_scrambling_luts: s 5d (-1) ((-1,1),(-1,-1),(-1,1),(-1,1)) +init_scrambling_luts: s 5e (1) ((1,-1),(-1,-1),(-1,1),(-1,1)) +init_scrambling_luts: s 5f (-1) ((-1,-1),(-1,-1),(-1,1),(-1,1)) +init_scrambling_luts: s 60 (1) ((1,1),(1,1),(1,-1),(-1,1)) +init_scrambling_luts: s 61 (-1) ((-1,1),(1,1),(1,-1),(-1,1)) +init_scrambling_luts: s 62 (1) ((1,-1),(1,1),(1,-1),(-1,1)) +init_scrambling_luts: s 63 (-1) ((-1,-1),(1,1),(1,-1),(-1,1)) +init_scrambling_luts: s 64 (1) ((1,1),(-1,1),(1,-1),(-1,1)) +init_scrambling_luts: s 65 (-1) ((-1,1),(-1,1),(1,-1),(-1,1)) +init_scrambling_luts: s 66 (1) ((1,-1),(-1,1),(1,-1),(-1,1)) +init_scrambling_luts: s 67 (-1) ((-1,-1),(-1,1),(1,-1),(-1,1)) +init_scrambling_luts: s 68 (1) ((1,1),(1,-1),(1,-1),(-1,1)) +init_scrambling_luts: s 69 (-1) ((-1,1),(1,-1),(1,-1),(-1,1)) +init_scrambling_luts: s 6a (1) ((1,-1),(1,-1),(1,-1),(-1,1)) +init_scrambling_luts: s 6b (-1) ((-1,-1),(1,-1),(1,-1),(-1,1)) +init_scrambling_luts: s 6c (1) ((1,1),(-1,-1),(1,-1),(-1,1)) +init_scrambling_luts: s 6d (-1) ((-1,1),(-1,-1),(1,-1),(-1,1)) +init_scrambling_luts: s 6e (1) ((1,-1),(-1,-1),(1,-1),(-1,1)) +init_scrambling_luts: s 6f (-1) ((-1,-1),(-1,-1),(1,-1),(-1,1)) +init_scrambling_luts: s 70 (1) ((1,1),(1,1),(-1,-1),(-1,1)) +init_scrambling_luts: s 71 (-1) ((-1,1),(1,1),(-1,-1),(-1,1)) +init_scrambling_luts: s 72 (1) ((1,-1),(1,1),(-1,-1),(-1,1)) +init_scrambling_luts: s 73 (-1) ((-1,-1),(1,1),(-1,-1),(-1,1)) +init_scrambling_luts: s 74 (1) ((1,1),(-1,1),(-1,-1),(-1,1)) +init_scrambling_luts: s 75 (-1) ((-1,1),(-1,1),(-1,-1),(-1,1)) +init_scrambling_luts: s 76 (1) ((1,-1),(-1,1),(-1,-1),(-1,1)) +init_scrambling_luts: s 77 (-1) ((-1,-1),(-1,1),(-1,-1),(-1,1)) +init_scrambling_luts: s 78 (1) ((1,1),(1,-1),(-1,-1),(-1,1)) +init_scrambling_luts: s 79 (-1) ((-1,1),(1,-1),(-1,-1),(-1,1)) +init_scrambling_luts: s 7a (1) ((1,-1),(1,-1),(-1,-1),(-1,1)) +init_scrambling_luts: s 7b (-1) ((-1,-1),(1,-1),(-1,-1),(-1,1)) +init_scrambling_luts: s 7c (1) ((1,1),(-1,-1),(-1,-1),(-1,1)) +init_scrambling_luts: s 7d (-1) ((-1,1),(-1,-1),(-1,-1),(-1,1)) +init_scrambling_luts: s 7e (1) ((1,-1),(-1,-1),(-1,-1),(-1,1)) +init_scrambling_luts: s 7f (-1) ((-1,-1),(-1,-1),(-1,-1),(-1,1)) +init_scrambling_luts: s 80 (1) ((1,1),(1,1),(1,1),(1,-1)) +init_scrambling_luts: s 81 (-1) ((-1,1),(1,1),(1,1),(1,-1)) +init_scrambling_luts: s 82 (1) ((1,-1),(1,1),(1,1),(1,-1)) +init_scrambling_luts: s 83 (-1) ((-1,-1),(1,1),(1,1),(1,-1)) +init_scrambling_luts: s 84 (1) ((1,1),(-1,1),(1,1),(1,-1)) +init_scrambling_luts: s 85 (-1) ((-1,1),(-1,1),(1,1),(1,-1)) +init_scrambling_luts: s 86 (1) ((1,-1),(-1,1),(1,1),(1,-1)) +init_scrambling_luts: s 87 (-1) ((-1,-1),(-1,1),(1,1),(1,-1)) +init_scrambling_luts: s 88 (1) ((1,1),(1,-1),(1,1),(1,-1)) +init_scrambling_luts: s 89 (-1) ((-1,1),(1,-1),(1,1),(1,-1)) +init_scrambling_luts: s 8a (1) ((1,-1),(1,-1),(1,1),(1,-1)) +init_scrambling_luts: s 8b (-1) ((-1,-1),(1,-1),(1,1),(1,-1)) +init_scrambling_luts: s 8c (1) ((1,1),(-1,-1),(1,1),(1,-1)) +init_scrambling_luts: s 8d (-1) ((-1,1),(-1,-1),(1,1),(1,-1)) +init_scrambling_luts: s 8e (1) ((1,-1),(-1,-1),(1,1),(1,-1)) +init_scrambling_luts: s 8f (-1) ((-1,-1),(-1,-1),(1,1),(1,-1)) +init_scrambling_luts: s 90 (1) ((1,1),(1,1),(-1,1),(1,-1)) +init_scrambling_luts: s 91 (-1) ((-1,1),(1,1),(-1,1),(1,-1)) +init_scrambling_luts: s 92 (1) ((1,-1),(1,1),(-1,1),(1,-1)) +init_scrambling_luts: s 93 (-1) ((-1,-1),(1,1),(-1,1),(1,-1)) +init_scrambling_luts: s 94 (1) ((1,1),(-1,1),(-1,1),(1,-1)) +init_scrambling_luts: s 95 (-1) ((-1,1),(-1,1),(-1,1),(1,-1)) +init_scrambling_luts: s 96 (1) ((1,-1),(-1,1),(-1,1),(1,-1)) +init_scrambling_luts: s 97 (-1) ((-1,-1),(-1,1),(-1,1),(1,-1)) +init_scrambling_luts: s 98 (1) ((1,1),(1,-1),(-1,1),(1,-1)) +init_scrambling_luts: s 99 (-1) ((-1,1),(1,-1),(-1,1),(1,-1)) +init_scrambling_luts: s 9a (1) ((1,-1),(1,-1),(-1,1),(1,-1)) +init_scrambling_luts: s 9b (-1) ((-1,-1),(1,-1),(-1,1),(1,-1)) +init_scrambling_luts: s 9c (1) ((1,1),(-1,-1),(-1,1),(1,-1)) +init_scrambling_luts: s 9d (-1) ((-1,1),(-1,-1),(-1,1),(1,-1)) +init_scrambling_luts: s 9e (1) ((1,-1),(-1,-1),(-1,1),(1,-1)) +init_scrambling_luts: s 9f (-1) ((-1,-1),(-1,-1),(-1,1),(1,-1)) +init_scrambling_luts: s a0 (1) ((1,1),(1,1),(1,-1),(1,-1)) +init_scrambling_luts: s a1 (-1) ((-1,1),(1,1),(1,-1),(1,-1)) +init_scrambling_luts: s a2 (1) ((1,-1),(1,1),(1,-1),(1,-1)) +init_scrambling_luts: s a3 (-1) ((-1,-1),(1,1),(1,-1),(1,-1)) +init_scrambling_luts: s a4 (1) ((1,1),(-1,1),(1,-1),(1,-1)) +init_scrambling_luts: s a5 (-1) ((-1,1),(-1,1),(1,-1),(1,-1)) +init_scrambling_luts: s a6 (1) ((1,-1),(-1,1),(1,-1),(1,-1)) +init_scrambling_luts: s a7 (-1) ((-1,-1),(-1,1),(1,-1),(1,-1)) +init_scrambling_luts: s a8 (1) ((1,1),(1,-1),(1,-1),(1,-1)) +init_scrambling_luts: s a9 (-1) ((-1,1),(1,-1),(1,-1),(1,-1)) +init_scrambling_luts: s aa (1) ((1,-1),(1,-1),(1,-1),(1,-1)) +init_scrambling_luts: s ab (-1) ((-1,-1),(1,-1),(1,-1),(1,-1)) +init_scrambling_luts: s ac (1) ((1,1),(-1,-1),(1,-1),(1,-1)) +init_scrambling_luts: s ad (-1) ((-1,1),(-1,-1),(1,-1),(1,-1)) +init_scrambling_luts: s ae (1) ((1,-1),(-1,-1),(1,-1),(1,-1)) +init_scrambling_luts: s af (-1) ((-1,-1),(-1,-1),(1,-1),(1,-1)) +init_scrambling_luts: s b0 (1) ((1,1),(1,1),(-1,-1),(1,-1)) +init_scrambling_luts: s b1 (-1) ((-1,1),(1,1),(-1,-1),(1,-1)) +init_scrambling_luts: s b2 (1) ((1,-1),(1,1),(-1,-1),(1,-1)) +init_scrambling_luts: s b3 (-1) ((-1,-1),(1,1),(-1,-1),(1,-1)) +init_scrambling_luts: s b4 (1) ((1,1),(-1,1),(-1,-1),(1,-1)) +init_scrambling_luts: s b5 (-1) ((-1,1),(-1,1),(-1,-1),(1,-1)) +init_scrambling_luts: s b6 (1) ((1,-1),(-1,1),(-1,-1),(1,-1)) +init_scrambling_luts: s b7 (-1) ((-1,-1),(-1,1),(-1,-1),(1,-1)) +init_scrambling_luts: s b8 (1) ((1,1),(1,-1),(-1,-1),(1,-1)) +init_scrambling_luts: s b9 (-1) ((-1,1),(1,-1),(-1,-1),(1,-1)) +init_scrambling_luts: s ba (1) ((1,-1),(1,-1),(-1,-1),(1,-1)) +init_scrambling_luts: s bb (-1) ((-1,-1),(1,-1),(-1,-1),(1,-1)) +init_scrambling_luts: s bc (1) ((1,1),(-1,-1),(-1,-1),(1,-1)) +init_scrambling_luts: s bd (-1) ((-1,1),(-1,-1),(-1,-1),(1,-1)) +init_scrambling_luts: s be (1) ((1,-1),(-1,-1),(-1,-1),(1,-1)) +init_scrambling_luts: s bf (-1) ((-1,-1),(-1,-1),(-1,-1),(1,-1)) +init_scrambling_luts: s c0 (1) ((1,1),(1,1),(1,1),(-1,-1)) +init_scrambling_luts: s c1 (-1) ((-1,1),(1,1),(1,1),(-1,-1)) +init_scrambling_luts: s c2 (1) ((1,-1),(1,1),(1,1),(-1,-1)) +init_scrambling_luts: s c3 (-1) ((-1,-1),(1,1),(1,1),(-1,-1)) +init_scrambling_luts: s c4 (1) ((1,1),(-1,1),(1,1),(-1,-1)) +init_scrambling_luts: s c5 (-1) ((-1,1),(-1,1),(1,1),(-1,-1)) +init_scrambling_luts: s c6 (1) ((1,-1),(-1,1),(1,1),(-1,-1)) +init_scrambling_luts: s c7 (-1) ((-1,-1),(-1,1),(1,1),(-1,-1)) +init_scrambling_luts: s c8 (1) ((1,1),(1,-1),(1,1),(-1,-1)) +init_scrambling_luts: s c9 (-1) ((-1,1),(1,-1),(1,1),(-1,-1)) +init_scrambling_luts: s ca (1) ((1,-1),(1,-1),(1,1),(-1,-1)) +init_scrambling_luts: s cb (-1) ((-1,-1),(1,-1),(1,1),(-1,-1)) +init_scrambling_luts: s cc (1) ((1,1),(-1,-1),(1,1),(-1,-1)) +init_scrambling_luts: s cd (-1) ((-1,1),(-1,-1),(1,1),(-1,-1)) +init_scrambling_luts: s ce (1) ((1,-1),(-1,-1),(1,1),(-1,-1)) +init_scrambling_luts: s cf (-1) ((-1,-1),(-1,-1),(1,1),(-1,-1)) +init_scrambling_luts: s d0 (1) ((1,1),(1,1),(-1,1),(-1,-1)) +init_scrambling_luts: s d1 (-1) ((-1,1),(1,1),(-1,1),(-1,-1)) +init_scrambling_luts: s d2 (1) ((1,-1),(1,1),(-1,1),(-1,-1)) +init_scrambling_luts: s d3 (-1) ((-1,-1),(1,1),(-1,1),(-1,-1)) +init_scrambling_luts: s d4 (1) ((1,1),(-1,1),(-1,1),(-1,-1)) +init_scrambling_luts: s d5 (-1) ((-1,1),(-1,1),(-1,1),(-1,-1)) +init_scrambling_luts: s d6 (1) ((1,-1),(-1,1),(-1,1),(-1,-1)) +init_scrambling_luts: s d7 (-1) ((-1,-1),(-1,1),(-1,1),(-1,-1)) +init_scrambling_luts: s d8 (1) ((1,1),(1,-1),(-1,1),(-1,-1)) +init_scrambling_luts: s d9 (-1) ((-1,1),(1,-1),(-1,1),(-1,-1)) +init_scrambling_luts: s da (1) ((1,-1),(1,-1),(-1,1),(-1,-1)) +init_scrambling_luts: s db (-1) ((-1,-1),(1,-1),(-1,1),(-1,-1)) +init_scrambling_luts: s dc (1) ((1,1),(-1,-1),(-1,1),(-1,-1)) +init_scrambling_luts: s dd (-1) ((-1,1),(-1,-1),(-1,1),(-1,-1)) +init_scrambling_luts: s de (1) ((1,-1),(-1,-1),(-1,1),(-1,-1)) +init_scrambling_luts: s df (-1) ((-1,-1),(-1,-1),(-1,1),(-1,-1)) +init_scrambling_luts: s e0 (1) ((1,1),(1,1),(1,-1),(-1,-1)) +init_scrambling_luts: s e1 (-1) ((-1,1),(1,1),(1,-1),(-1,-1)) +init_scrambling_luts: s e2 (1) ((1,-1),(1,1),(1,-1),(-1,-1)) +init_scrambling_luts: s e3 (-1) ((-1,-1),(1,1),(1,-1),(-1,-1)) +init_scrambling_luts: s e4 (1) ((1,1),(-1,1),(1,-1),(-1,-1)) +init_scrambling_luts: s e5 (-1) ((-1,1),(-1,1),(1,-1),(-1,-1)) +init_scrambling_luts: s e6 (1) ((1,-1),(-1,1),(1,-1),(-1,-1)) +init_scrambling_luts: s e7 (-1) ((-1,-1),(-1,1),(1,-1),(-1,-1)) +init_scrambling_luts: s e8 (1) ((1,1),(1,-1),(1,-1),(-1,-1)) +init_scrambling_luts: s e9 (-1) ((-1,1),(1,-1),(1,-1),(-1,-1)) +init_scrambling_luts: s ea (1) ((1,-1),(1,-1),(1,-1),(-1,-1)) +init_scrambling_luts: s eb (-1) ((-1,-1),(1,-1),(1,-1),(-1,-1)) +init_scrambling_luts: s ec (1) ((1,1),(-1,-1),(1,-1),(-1,-1)) +init_scrambling_luts: s ed (-1) ((-1,1),(-1,-1),(1,-1),(-1,-1)) +init_scrambling_luts: s ee (1) ((1,-1),(-1,-1),(1,-1),(-1,-1)) +init_scrambling_luts: s ef (-1) ((-1,-1),(-1,-1),(1,-1),(-1,-1)) +init_scrambling_luts: s f0 (1) ((1,1),(1,1),(-1,-1),(-1,-1)) +init_scrambling_luts: s f1 (-1) ((-1,1),(1,1),(-1,-1),(-1,-1)) +init_scrambling_luts: s f2 (1) ((1,-1),(1,1),(-1,-1),(-1,-1)) +init_scrambling_luts: s f3 (-1) ((-1,-1),(1,1),(-1,-1),(-1,-1)) +init_scrambling_luts: s f4 (1) ((1,1),(-1,1),(-1,-1),(-1,-1)) +init_scrambling_luts: s f5 (-1) ((-1,1),(-1,1),(-1,-1),(-1,-1)) +init_scrambling_luts: s f6 (1) ((1,-1),(-1,1),(-1,-1),(-1,-1)) +init_scrambling_luts: s f7 (-1) ((-1,-1),(-1,1),(-1,-1),(-1,-1)) +init_scrambling_luts: s f8 (1) ((1,1),(1,-1),(-1,-1),(-1,-1)) +init_scrambling_luts: s f9 (-1) ((-1,1),(1,-1),(-1,-1),(-1,-1)) +init_scrambling_luts: s fa (1) ((1,-1),(1,-1),(-1,-1),(-1,-1)) +init_scrambling_luts: s fb (-1) ((-1,-1),(1,-1),(-1,-1),(-1,-1)) +init_scrambling_luts: s fc (1) ((1,1),(-1,-1),(-1,-1),(-1,-1)) +init_scrambling_luts: s fd (-1) ((-1,1),(-1,-1),(-1,-1),(-1,-1)) +init_scrambling_luts: s fe (1) ((1,-1),(-1,-1),(-1,-1),(-1,-1)) +init_scrambling_luts: s ff (-1) ((-1,-1),(-1,-1),(-1,-1),(-1,-1)) +in 0, out 0 +in 1, out ffffffff +in 2, out 4ba5a933 +in 3, out b45a56cc +in 4, out 7d910e5a +in 5, out 826ef1a5 +in 6, out 3634a769 +in 7, out c9cb5896 +[LIBCONFIG] loader.ldpc: 2/2 parameters successfully set, (1 to default value) +[LOADER] library libldpc.so successfully loaded +[PHY] Initialise nr transport +[PHY] Allocating Transport Channel Buffers for PUCCH 0/2 +[PHY] Allocating Transport Channel Buffers for PUCCH 1/2 +[PHY] Allocating Transport Channel Buffers for DLSCH 0/2 +[PHY] Allocating Transport Channel Buffers for DLSCH 1/2 +[PHY] Allocating Transport Channel Buffer for ULSCH, UE 0 +[PHY] Allocating Transport Channel Buffer for ULSCH, UE 1 +Before ULSCH init : 0x3f4b300 +ULSCH_id 0 : 0x3f4b300 +ULSCH_id 0 (before rx antenna alloc) : 0x3f4b300 +ULSCH_id 0 (before llr alloc) : 0x3f4b300 +ULSCH_id 0 (after llr alloc) : 0x3f4b300 +ULSCH_id 1 : 0x3f4b300 +ULSCH_id 1 (before rx antenna alloc) : 0x3f4b300 +ULSCH_id 1 (before llr alloc) : 0x3f4b300 +ULSCH_id 1 (after llr alloc) : 0x3f4b300 +After ULSCH init : 0x3f4b300 +[PHY] Mapping RX ports from 1 RUs to gNB 0 +[PHY] gNB->num_RU:1 +[PHY] Attaching RU 0 antenna 0 to gNB antenna 0 +[PHY] Initializing gNB processes instance:0 CC_id 0 +[PHY] gNB->single_thread_flag:1 +ALL RUs ready - ALL gNBs ready +Sending sync to all threads +About to call end_configmodule() from main() /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/executables/nr-softmodem.c:983 +[CONFIG] calling config module end function... +got sync (ru_thread) +[CONFIG] free 398 config value pointers +Called end_configmodule() from main() /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/executables/nr-softmodem.c:985 +TYPE TO TERMINATE +Entering ITTI signals handler +[HW] Time in secs now: 112963128 +[HW] Time in secs last pps: 80717015 +[PHY] RU 0 rf device ready +[PHY] RU 0 no asynch_south interface +initializing tx write thread +end of tx write thread +[PHY] tx write thread ready +[MAC] Frame 8, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 8 : MIB->BCH CC_id 0, Received 3 bytes +[PHY] ru_thread_prach() RACH waiting for RU to be configured +[PHY] ru_thread_prach() RU configured - RACH processing thread running +[MAC] Frame 16, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 16 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] Frame 24, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 24 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] Frame 32, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 32 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] Frame 40, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 40 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] Frame 48, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 48 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] Frame 56, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 56 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] Frame 64, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 64 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] Frame 72, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 72 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] Frame 80, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 88, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 96, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 104, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 112, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 120, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 128, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 136, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 144, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 152, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 160, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 168, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 176, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 184, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 192, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 200, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 208, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 216, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 224, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 232, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 240, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 248, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 256, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 264, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 272, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 280, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 288, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 296, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 304, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 312, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 320, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 328, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 336, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 344, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 352, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 360, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 368, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 376, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 384, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 392, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 400, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 408, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 416, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 424, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 432, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 440, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 448, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 456, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 464, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 472, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 480, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 488, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 496, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 504, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 512, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 520, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 528, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 536, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 544, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 552, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 560, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 568, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 576, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 584, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 592, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 600, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 608, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 616, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 624, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 632, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 640, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 648, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 656, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 664, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 672, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 680, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 688, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 696, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 704, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 712, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 720, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 728, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 736, slot 0: Adding BCH PDU in position 0 (length 3) +[SCTP] Found data for descriptor 87 +[SCTP] [136][87] Msg of length 2161 received from port 36422, on stream 0, PPID 27 + + + 27 + + + + + + 111 + + + 0 + + + + 248 + + + + + 0000000000000000 + + + 0000000000000000 + + + + + + 203 + + + + 0000000000000000000000000000000000000000000000000000000000000000 + 0000000000000000000000000000000000000000000000000000000000000000 + 0000000000000000000000000000000000000000000000000000000000000000 + 0000000000000000000000000000000000000000000000000000000000000000 + + + + + 204 + + + + 100000000 + 100000000 + + + + + 205 + + + + + 209 + + + + 5 + 1 + + + + + + + + + 1 + + 15 + + + + + + + 11000000101010000001001001100011 + + 00 00 00 02 + + + + + + + + + + + 206 + + + + 3A 03 08 78 8D DB 80 51 81 80 01 04 0C 20 71 63 + 08 11 24 4C C1 93 67 0F A1 4A 99 3A 85 AF CC 58 + FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 + 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF + FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF + D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF + E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 + FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B + FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF + FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE + C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF + 2B FF D8 FF FF FF 95 FF DF F3 FF AF A2 0C 00 8C + 85 3C 10 65 3A 54 97 1F C0 68 FE 00 00 00 00 02 + 04 BD 80 00 00 08 09 DF 00 00 00 02 EE C0 0C 00 + A0 04 00 04 00 A0 06 00 48 20 0C 10 06 08 03 04 + 01 82 10 C1 08 60 84 30 42 18 20 0C 10 06 08 43 + 04 21 82 00 C1 00 60 80 30 40 18 20 0C 10 06 18 + 02 10 C3 00 42 18 60 08 43 0C 01 08 61 80 21 0C + 30 04 21 86 00 84 30 C0 10 86 10 02 18 40 08 61 + 00 21 84 00 86 10 02 18 40 08 61 00 21 84 00 86 + 10 02 18 20 0C 10 06 18 02 10 C3 00 42 18 60 08 + 43 0C 01 08 61 00 21 84 00 86 10 02 18 41 08 61 + 04 21 84 10 86 10 42 18 41 08 61 04 21 84 10 86 + 10 42 18 41 08 60 84 30 42 18 21 0C 10 86 00 61 + 00 21 84 00 86 10 02 18 40 08 61 00 21 84 00 86 + 08 43 04 21 82 00 C1 00 60 04 B4 7D 54 6C 1E 00 + 00 2E 81 8C 00 08 20 60 00 02 08 18 20 00 80 06 + 10 00 20 81 86 00 08 00 62 00 02 00 18 E0 00 80 + 06 58 00 20 01 98 00 08 00 68 00 02 00 1A 20 00 + 80 06 90 00 20 01 A6 00 08 00 6C 00 02 00 1B 20 + 00 80 06 D8 00 20 00 B8 10 00 5F 08 00 70 80 02 + 00 1C A0 00 82 07 30 00 20 01 CE 00 08 20 74 00 + 02 08 0D A1 00 0F F0 00 40 07 4C 00 10 11 82 08 + 2A 61 03 18 00 10 41 C7 00 04 04 60 82 0A 38 40 + C6 00 04 10 71 80 01 05 08 20 82 8C 10 70 80 01 + 04 1C 60 00 41 40 08 20 A3 04 1C 00 00 41 07 4C + 00 10 10 02 08 2A 61 03 00 00 10 41 C2 00 04 14 + 00 82 0A 10 41 C0 00 04 10 76 C0 01 01 08 20 82 + B6 10 30 80 01 04 1D 30 00 40 42 08 20 A9 84 0C + 20 00 41 07 1C 00 10 10 82 08 28 E1 03 08 00 10 + 43 D3 00 04 04 60 82 84 12 50 02 08 6A 61 03 18 + 00 10 50 82 4A 00 41 0D 4C 20 23 04 1C 20 00 49 + 40 08 21 A9 84 04 60 82 84 12 70 00 01 04 3D 30 + 00 40 46 08 28 41 05 00 20 86 A6 10 31 80 01 05 + 08 20 A0 04 10 D4 C2 02 30 41 C2 00 04 14 00 82 + 1A 98 40 46 08 28 41 07 00 00 10 42 D3 00 04 04 + 60 82 84 12 42 53 08 18 C0 00 82 84 12 42 53 08 + 08 C1 07 08 00 12 42 D3 00 04 04 60 82 84 10 42 + 53 08 18 C0 00 82 84 10 42 53 08 08 C1 07 08 00 + 10 42 D3 00 04 04 60 82 80 10 42 53 08 18 C0 00 + 82 80 10 42 53 08 08 C1 07 00 00 10 41 D3 00 04 + 04 60 92 0A 98 40 C6 00 04 90 F1 C0 01 01 18 20 + A1 04 14 00 82 1A 38 40 C6 00 04 14 20 82 80 10 + 43 47 08 08 C1 07 08 00 10 50 02 08 68 E1 01 18 + 20 A1 04 1C 00 00 41 0B 1C 00 10 11 82 0A 10 41 + 09 1C 20 63 00 02 0A 10 41 09 1C 20 23 04 1C 20 + 00 41 0B 18 00 12 50 82 0A 00 41 09 18 24 E1 00 + 02 0A 00 41 09 18 24 A1 04 1C 00 00 41 0B 18 00 + 10 50 82 4A 00 41 09 18 20 E1 00 02 4A 00 41 09 + 18 20 A1 04 9C 00 00 41 0B 18 00 10 50 82 0A 00 + 41 09 18 20 E1 00 02 0A 00 41 09 18 20 A1 04 1C + 00 00 41 07 18 04 12 50 82 08 28 C1 27 08 00 10 + 41 C6 00 04 14 20 92 0A 30 41 C2 01 04 90 31 80 + 41 24 2D 30 00 40 42 09 28 01 04 25 30 81 84 00 + 09 28 01 04 25 30 80 84 12 70 00 01 04 2D 30 00 + 40 42 08 28 01 04 25 30 81 84 00 08 28 01 04 25 + 30 80 84 10 70 00 01 04 1C 20 10 49 40 08 20 A1 + 04 9C 00 00 41 07 4C 00 10 10 82 48 2A 61 03 08 + 00 12 40 C2 01 04 9B B6 3F FF FF E5 7F FB 1F FF + FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC AF FF + 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF FF FF + 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 7F FB 1F + FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC AF + FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF FF + FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 7F FB + 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC + AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF + FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 7F + FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF + FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 + FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 + 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF + FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF + D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF + E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 + FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B + FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF + FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE + C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF + 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F + FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F + FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF + FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 + 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 + 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF + FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF + F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF + F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 + FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA + FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF + FF F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF + B1 FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF + CA FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F + FF FF F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 + FF B1 FF FF FF 2B FF B6 76 00 00 7E C4 0D 9D 80 + 00 04 7C EC 00 00 BA 00 00 00 8B C5 E2 F1 78 78 + 78 78 72 1E 1E 1E 1E 1E 1E 3F 8F C2 1E 1E 1E 1E + 1E 1E 1E 1E 1E 1E 2F 17 8B 90 F0 F0 F0 F1 78 BC + 5E 1E 1E 1E 1E 1E 1E 1E 1E 1E 1E 1C 8B 80 0F 74 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 04 04 10 04 01 00 40 10 + 04 01 00 40 10 04 01 00 40 10 04 01 00 40 10 04 + 03 00 0C 00 30 00 C0 03 00 0C 00 30 00 C0 02 00 + 20 02 00 20 02 00 20 02 00 20 02 00 10 04 03 00 + 0C 00 30 00 C0 02 00 20 02 00 20 02 00 20 02 00 + 20 02 00 20 02 00 20 01 00 40 10 04 00 02 00 20 + 02 00 20 02 00 20 01 00 40 10 04 00 3E 08 02 40 + 07 CC AF 34 08 02 96 3F FF FF FF FF FF FC D2 97 + 78 A0 1F 00 08 40 13 0C 00 00 00 00 00 0A A1 34 + 91 02 02 00 05 E4 84 12 E2 80 02 6B C0 C0 04 00 + 01 04 10 40 00 28 C8 00 00 08 80 00 05 58 E1 00 + 00 00 01 4F 7E 03 02 00 00 01 40 48 07 06 0E 22 + 0C 00 02 13 60 10 73 E4 20 F0 00 82 40 31 10 00 + A0 58 9B A0 21 94 34 08 81 07 41 86 04 C0 42 54 + 41 01 00 80 06 08 1C 1C 22 03 C8 0F 00 20 1A 02 + 6E 26 F0 00 09 00 00 00 00 72 A6 80 00 80 00 02 + 0C 30 00 1A 55 30 62 00 11 C0 48 16 0C 01 C4 D0 + 00 00 00 40 04 03 40 4D 01 04 40 41 4E 9C 00 02 + 00 01 00 80 80 10 02 00 + + + + + + + + +[X2AP] X2AP_ProcedureCode_id_sgNBAdditionPreparation message! +[X2AP] X2AP Association id: 136 +[RRC] x2u tunnel: index 0 target sgw ip 192.168.18.99 length 32 gtp teid 0 +[NR_RRC] Received message X2AP_ENDC_SGNB_ADDITION_REQ +[NR_RRC] Received ENDC sgNB addition request from X2AP + + + + + 1 + + + + + + + + DD B8 05 18 18 00 10 40 C2 07 16 30 81 12 44 CC + 19 36 70 FA 14 A9 93 A8 5A FC C5 8F FF FF F9 5F + FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF + FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 + 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 + 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF + FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF + F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF + F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 + FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA + FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF + FF F9 5F FD FF 3F FA FA 20 C0 08 C8 53 C1 06 53 + A5 49 71 FC 06 8F E0 00 00 00 00 20 4B D8 00 00 + 00 80 9D F0 00 00 00 2E EC 00 C0 0A 00 40 00 40 + 0A 00 60 04 82 00 C1 00 60 80 30 40 18 21 0C 10 + 86 08 43 04 21 82 00 C1 00 60 84 30 42 18 20 0C + 10 06 08 03 04 01 82 00 C1 00 61 80 21 0C 30 04 + 21 86 00 84 30 C0 10 86 18 02 10 C3 00 42 18 60 + 08 43 0C 01 08 61 00 21 84 00 86 10 02 18 40 08 + 61 00 21 84 00 86 10 02 18 40 08 61 00 21 82 00 + C1 00 61 80 21 0C 30 04 21 86 00 84 30 C0 10 86 + 10 02 18 40 08 61 00 21 84 10 86 10 42 18 41 08 + 61 04 21 84 10 86 10 42 18 41 08 61 04 21 84 10 + 86 08 43 04 21 82 10 C1 08 60 06 10 02 18 40 08 + 61 00 21 84 00 86 10 02 18 40 08 60 84 30 42 18 + 20 0C 10 06 00 4B 47 D5 46 C1 E0 00 02 E8 18 C0 + 00 82 06 00 00 20 81 82 00 08 00 61 00 02 08 18 + 60 00 80 06 20 00 20 01 8E 00 08 00 65 80 02 00 + 19 80 00 80 06 80 00 20 01 A2 00 08 00 69 00 02 + 00 1A 60 00 80 06 C0 00 20 01 B2 00 08 00 6D 80 + 02 00 0B 81 00 05 F0 80 07 08 00 20 01 CA 00 08 + 20 73 00 02 00 1C E0 00 82 07 40 00 20 80 DA 10 + 00 FF 00 04 00 74 C0 01 01 18 20 82 A6 10 31 80 + 01 04 1C 70 00 40 46 08 20 A3 84 0C 60 00 41 07 + 18 00 10 50 82 08 28 C1 07 08 00 10 41 C6 00 04 + 14 00 82 0A 30 41 C0 00 04 10 74 C0 01 01 00 20 + 82 A6 10 30 00 01 04 1C 20 00 41 40 08 20 A1 04 + 1C 00 00 41 07 6C 00 10 10 82 08 2B 61 03 08 00 + 10 41 D3 00 04 04 20 82 0A 98 40 C2 00 04 10 71 + C0 01 01 08 20 82 8E 10 30 80 01 04 3D 30 00 40 + 46 08 28 41 25 00 20 86 A6 10 31 80 01 05 08 24 + A0 04 10 D4 C2 02 30 41 C2 00 04 94 00 82 1A 98 + 40 46 08 28 41 27 00 00 10 43 D3 00 04 04 60 82 + 84 10 50 02 08 6A 61 03 18 00 10 50 82 0A 00 41 + 0D 4C 20 23 04 1C 20 00 41 40 08 21 A9 84 04 60 + 82 84 10 70 00 01 04 2D 30 00 40 46 08 28 41 24 + 25 30 81 8C 00 08 28 41 24 25 30 80 8C 10 70 80 + 01 24 2D 30 00 40 46 08 28 41 04 25 30 81 8C 00 + 08 28 41 04 25 30 80 8C 10 70 80 01 04 2D 30 00 + 40 46 08 28 01 04 25 30 81 8C 00 08 28 01 04 25 + 30 80 8C 10 70 00 01 04 1D 30 00 40 46 09 20 A9 + 84 0C 60 00 49 0F 1C 00 10 11 82 0A 10 41 40 08 + 21 A3 84 0C 60 00 41 42 08 28 01 04 34 70 80 8C + 10 70 80 01 05 00 20 86 8E 10 11 82 0A 10 41 C0 + 00 04 10 B1 C0 01 01 18 20 A1 04 10 91 C2 06 30 + 00 20 A1 04 10 91 C2 02 30 41 C2 00 04 10 B1 80 + 01 25 08 20 A0 04 10 91 82 4E 10 00 20 A0 04 10 + 91 82 4A 10 41 C0 00 04 10 B1 80 01 05 08 24 A0 + 04 10 91 82 0E 10 00 24 A0 04 10 91 82 0A 10 49 + C0 00 04 10 B1 80 01 05 08 20 A0 04 10 91 82 0E + 10 00 20 A0 04 10 91 82 0A 10 41 C0 00 04 10 71 + 80 41 25 08 20 82 8C 12 70 80 01 04 1C 60 00 41 + 42 09 20 A3 04 1C 20 10 49 03 18 04 12 42 D3 00 + 04 04 20 92 80 10 42 53 08 18 40 00 92 80 10 42 + 53 08 08 41 27 00 00 10 42 D3 00 04 04 20 82 80 + 10 42 53 08 18 40 00 82 80 10 42 53 08 08 41 07 + 00 00 10 41 C2 01 04 94 00 82 0A 10 49 C0 00 04 + 10 74 C0 01 01 08 24 82 A6 10 30 80 01 24 0C 20 + 10 49 BB 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 + FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 + 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF + FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF + D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF + E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 + FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B + FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF + FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE + C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF + 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F + FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F + FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF + FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 + 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 + 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF + FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF + F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF + F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 + FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA + FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF + FF F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF + B1 FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF + CA FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F + FF FF F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 + FF B1 FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF + FF CA FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD + 8F FF FF F9 5F FE C7 FF FF FC AF FF 63 FF FF FE + 57 FF B1 FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F + FF FF CA FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF + FD 8F FF FF F9 5F FE C7 FF FF FC AF FF 63 FF FF + FE 57 FF B1 FF FF FF 2B FF D8 FF FF FF 95 FF EC + 7F FF FF CA FF F6 3F FF FF E5 7F FB 1F FF FF F2 + BF FD 8F FF FF F9 5F FE C7 FF FF FC AF FF 63 FF + FF FE 57 FF B1 FF FF FF 2B FF D8 FF FF FF 95 FF + EC 7F FF FF CA FF F6 3F FF FF E5 7F FB 1F FF FF + F2 BF FB 67 60 00 07 EC 40 D9 D8 00 00 47 CE C0 + 00 0B A0 00 00 08 BC 5E 2F 17 87 87 87 87 21 E1 + E1 E1 E1 E1 E3 F8 FC 21 E1 E1 E1 E1 E1 E1 E1 E1 + E1 E2 F1 78 B9 0F 0F 0F 0F 17 8B C5 E1 E1 E1 E1 + E1 E1 E1 E1 E1 E1 E1 C8 B8 00 F7 40 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 40 41 00 40 10 04 01 00 40 10 04 01 + 00 40 10 04 01 00 40 10 04 01 00 40 30 00 C0 03 + 00 0C 00 30 00 C0 03 00 0C 00 20 02 00 20 02 00 + 20 02 00 20 02 00 20 01 00 40 30 00 C0 03 00 0C + 00 20 02 00 20 02 00 20 02 00 20 02 00 20 02 00 + 20 02 00 10 04 01 00 40 00 20 02 00 20 02 00 20 + 02 00 10 04 01 00 40 03 E0 80 24 00 7C CA F3 40 + 80 29 63 FF FF FF FF FF FF CD 29 77 8A 01 F0 00 + 84 01 30 C0 00 00 00 00 00 AA 13 49 10 20 20 00 + 5E 48 41 2E 28 00 26 BC 0C 00 40 00 10 41 04 00 + 02 8C 80 00 00 88 00 00 + + + + + + E1 00 00 00 01 4F 7E 03 02 00 00 01 40 48 07 06 + 0E 22 0C 00 02 13 60 10 73 E4 20 F0 00 82 40 31 + 10 00 A0 58 9B A0 21 94 34 08 81 07 41 86 04 C0 + 42 54 41 01 00 80 06 08 1C 1C 22 03 C8 0F 00 20 + 1A 02 6E 26 F0 00 09 00 00 00 00 72 A6 80 00 80 + 00 02 0C 30 00 1A 55 30 + + + + + + 01 1C 04 81 60 C0 1C 4D 00 00 00 04 00 40 34 04 + D0 10 44 04 14 E9 C0 00 20 00 10 08 08 01 00 20 + + + + + + + + + + +[NR_RRC] Returning new UE context at 0x7f5188003980 + + 1 + + + 4 + + 1 + + + + + + + + + + + + + + + + + + + + + 1 + + + 1 + + + + + + + + + + + + + + + 0 + + + + + + + + + + + + + + + + + + + 20 + + + + 1 + + + 0 + + + 641272 + + 78 + + 640000 + + + 0 + + 106 + + + + + + 6366 + + + + + 0 + 0 + + + + + + + 0 + + 40 + + + 0 + + 53 + + + 0 + + 54 + + + 0 + + 57 + + + + + + + + + + 78 + + + + 0 + + 106 + + + 20 + + + + 6366 + + + + + + 98 + + 0 + 13 + -100 + + + + + + + + + 19 + + 1 + + + + + + + + + + + 2 + + 55 + + + 2 + + 69 + + + 7 + + 52 + + + 1 + -90 + + + + + 0 + + 40 + -90 + + + + + + + + 10000000 + + + + + + + + + + 7 + 6 + 2 + 4 + + + -25 + + 9195 + + + + + + + 98 + + 0 + 13 + -100 + + + + + + + + + + 0 + 63 + + + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 + + + 28875 + + + + + + 1 + + 111111111111111100000000000000000000000000000 + + 1 + + + + + + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + + + 1 + 1 + + + + + 11000000000000 + + + + + + + + + + + + + + + + + 1 + + + + + + + 0 + + 40 + + + 0 + + 53 + + + 0 + + 54 + + + 0 + + 57 + + + + + + + + + + + 1 + + 111111111111111100000000000000000000000000000 + + 1 + + + + + + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + + + + 2 + 1 + + + + + 11000000000000 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 + 1 + + + + + + + + + + + + + + + + 0 + 0 + + + + + + 0 + + 0 + + + + + + + + 1 + + + + + + + 0 + + 0 + + + + 1 + 2 + + + + + -80 + + + + + 0 + + + + 0 + 0 + + + + 2 + + + + 0 + 0 + + 61 + 0 + 0 + + + + + + + 40 + + + 0 + + + + + + + + + + 1 + + + 28875 + + + + + + 98 + + 0 + 13 + -100 + + + + + + + + + 19 + + 1 + + + + + + + + + + + 2 + + 55 + + + 2 + + 69 + + + 7 + + 52 + + + 1 + -90 + + + + + 0 + + 40 + -90 + + + + + + + + + 0 + + 1 + 2 + + + + 1 + + 3 + 4 + + + + + + 1 + 48 + + + 0 + 1 + 13 + + + + + 2 + 48 + + + 0 + 1 + 12 + + + + + 3 + 40 + + + 16 + 1 + 13 + + + + + 4 + 40 + + + 16 + 1 + 12 + + + + + + + + + + + 2 + 3 + 4 + 5 + 6 + 7 + 0 + 0 + + + + 1 + + 0 + + 0 + 1 + + + + + 0 + 0 + 0 + 0 + 0 + + + 1 + 0 + + + + + 0 + + 0 + + + + + + + + + + + + + + + + + + + + 0 + 0 + + + + + + 0 + + 0 + + + + + + + + 1 + + + + + + + 0 + + 0 + + + + 1 + 2 + + + + + -80 + + + + + 0 + + + + 0 + 0 + + + + 2 + + + + 0 + 0 + + 61 + 0 + 0 + + + + + + + 40 + + + 0 + + + + + + + + + + 1 + + + + + 2 + + + + 0 + + + + + + + + 5 + + 1 + + + + + + + + + + + + + + + + + + + + +[RRC] Dumping NR_RRCReconfiguration message (309 bytes) +0881325c40f1c032086fc61a083cc8390a83c4201065742dcc600349c8f802693880000004d2c31bc6a000a700a201ac0368073a404d0000269c9c31bc65462001acccd7dc9c0497942b7858b1ed1385c00a1c0300842c0760122323ebc48c40035999a0007e1b600203805b2012400404808c659c32cca281ffff000000010e0008206102860e6e088600001010034e0144035806d00e5950081ffff000000010e0008206102860e1b84218000100b20020240464ac2a581c2082c1c1821c200e25038000040bde802000400001e8002820032e70cb32a31000d6666bee4e024bca15bc2c58f689c2e0050e0d54835010208841840601180068086001803142f681050bd920f23456700008000fe8421080100804b038410583830438401c4a0700000817bd004000800003d00050400e00203100 +[RRC] Dumping scg_RB_Config message (8 bytes) +1409281782c00c00 +[RRC] S1-U tunnel: index 0 target sgw ip 192.168.18.99 length 32 gtp teid 2 +[GTPV1U] Configured GTPu address : c612a8c0 +[GTPV1U] Copied to create_tunnel_resp tunnel: index 0 target gNB ip 192.168.18.198 length 4 gtp teid 2462855170 +[RRC] [FRAME 00000][eNB][MOD 00][RNTI 23eb] rrc_eNB_process_GTPV1U_CREATE_TUNNEL_RESP tunnel (2462855170, 2462855170) bearer UE context index 0, msg index 0, id 5, gtp addr len 4 +[RRC] S1-U create_tunnel_resp tunnel: index 0 target gNB ip 192.168.18.198 length 4 gtp teid 2462855170 +[RRC] X2AP sGNB Addition Request: index 0 target gNB ip 192.168.18.198 length 32 gtp teid 2462855170 +[MAC] [gNB 0] Adding UE with rnti 23eb (next avail 0, num_UEs 0) +[MAC] gNB 0] Add NR UE_id 0 : rnti 23eb +[PHY] Added new UE_id 0/23eb with initial secondaryCellGroup + + + 27 + + + + + + 111 + + + 0 + + + + 207 + + + 0 + + + + 210 + + + + + 213 + + + + 5 + + + + + + + + + + 11000000101010000001001011000110 + + 92 CC 30 02 + + + + + + + + + + + 211 + + + + 18 04 09 A8 44 09 92 E2 07 8E 01 90 43 7E 30 D0 + 41 E6 41 C8 54 1E 21 00 83 2B A1 6E 63 00 1A 4E + 47 C0 13 49 C4 00 00 00 26 96 18 DE 35 00 05 38 + 05 10 0D 60 1B 40 39 D2 02 68 00 01 34 E4 E1 8D + E3 2A 31 00 0D 66 66 BE E4 E0 24 BC A1 5B C2 C5 + 8F 68 9C 2E 00 50 E0 18 04 21 60 3B 00 91 19 1F + 5E 24 62 00 1A CC CD 00 03 F0 DB 00 10 1C 02 D9 + 00 92 00 20 24 04 63 2C E1 96 65 14 0F FF F8 00 + 00 00 08 70 00 41 03 08 14 30 73 70 44 30 00 00 + 80 80 1A 70 0A 20 1A C0 36 80 72 CA 80 40 FF FF + 80 00 00 00 87 00 04 10 30 81 43 07 0D C2 10 C0 + 00 08 05 90 01 01 20 23 25 61 52 C0 E1 04 16 0E + 0C 10 E1 00 71 28 1C 00 00 20 5E F4 01 00 02 00 + 00 0F 40 01 41 00 19 73 86 59 95 18 80 06 B3 33 + 5F 72 70 12 5E 50 AD E1 62 C7 B4 4E 17 00 28 70 + 6A A4 1A 80 81 04 42 0C 20 30 08 C0 03 40 43 00 + 0C 01 8A 17 B4 08 28 5E C9 07 91 A2 B3 80 00 40 + 00 7F 42 10 84 00 80 40 25 81 C2 08 2C 1C 18 21 + C2 00 E2 50 38 00 00 40 BD E8 02 00 04 00 00 1E + 80 02 82 00 70 01 01 88 00 40 A0 49 40 BC 16 00 + 60 00 + + + + + + + + +[X2AP] Received elements for X2AP_ENDC_SGNB_ADDITION_REQ_ACK +[SCTP] Successfully sent 371 bytes on stream 0 for assoc_id 136 +[MAC] Frame 744, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] Frame 752, slot 0: Adding BCH PDU in position 0 (length 3) +[PHY] [gNB 0][RAPROC] Frame 751, slot 19 Initiating RA procedure with preamble 63, energy 35.7 dB, delay 6 +[MAC] [gNB 0][RAPROC] CC_id 0 Frame 751, Slot 19 Initiating RA procedure for preamble index 63 +[MAC] [gNB 0][RAPROC] CC_id 0 Frame 751 Activating Msg2 generation in frame 752, slot 7 using RA rnti 10b +[MAC] [gNB 0] [RAPROC] CC_id 0 Frame 752, slotP 7: Generating RAR DCI, state 1 +[MAC] [RAPROC] DCI type 1 payload: freq_alloc 120 (0,6,24), time_alloc 3, vrb to prb 0, mcs 0 tb_scaling 0 +[MAC] Frame 752: Subframe 7 : Adding common DL DCI for RA_RNTI 10b +[MAC] Frame 752, Subframe 7: Setting Msg3 reception for Frame 752 Subframe 17 +[PHY] ULSCH received ok +[MAC] [gNB 0][RAPROC] PUSCH with TC_RNTI c497 received correctly and UE_id 0 is now 5G connected +[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 753 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 753 slot 8 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 754 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 754 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 754 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 755 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 755 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 755 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 756 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 756 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 756 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[SCTP] Found data for descriptor 87 +[SCTP] Received notification for sd 87, type 32777 +[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 757 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 757 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 757 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 758 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 758 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 758 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 759 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 759 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 759 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 760, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 760 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 760 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 760 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 761 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 761 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 761 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 762 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 762 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 762 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 763 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 763 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 763 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 764 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 764 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 764 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 765 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 765 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 765 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 766 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 766 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 766 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 767 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 767 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 767 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 768, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 768 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 768 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 768 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 769 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 769 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 769 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 770 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 770 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 770 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 771 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 771 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 771 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 772 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 772 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 772 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 773 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 773 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 773 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 774 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 774 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 774 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 775 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 775 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 775 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 776, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 776 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 776 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 776 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 777 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 777 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 777 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 778 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 778 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 778 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 779 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 779 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 779 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 780 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 780 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 780 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 781 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 781 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 781 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 782 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 782 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 782 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 783 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 783 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 783 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 784, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 784 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 784 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 784 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 785 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 785 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 785 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 786 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 786 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 786 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 787 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 787 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 787 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 788 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 788 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 788 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 789 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 789 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 789 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 790 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 790 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 790 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 791 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 791 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 791 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 792, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 792 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 792 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 792 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 793 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 793 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 793 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 794 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 794 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 794 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 795 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 795 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 795 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 796 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 796 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 796 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 797 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 797 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 797 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 798 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 798 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 798 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 799 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 799 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 799 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 800, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 800 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 800 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 800 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 801 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 801 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 801 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 802 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 802 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 802 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 803 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 803 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 803 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 804 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 804 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 804 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 805 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 805 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 805 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 806 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 806 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 806 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 807 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 807 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 807 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 808, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 808 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 808 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 808 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 809 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 809 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 809 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 810 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 810 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 810 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 811 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 811 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 811 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 812 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 812 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 812 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 813 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 813 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 813 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 814 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 814 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 814 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 815 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 815 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 815 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 816, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 816 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 816 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 816 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 817 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 817 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 817 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 818 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 818 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 818 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 819 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 819 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 819 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 820 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 820 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 820 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 821 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 821 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 821 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 822 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 822 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 822 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 823 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 823 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 823 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 824, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 824 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 824 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 824 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 825 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 825 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 825 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 826 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 826 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 826 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 827 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 827 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 827 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 828 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 828 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 828 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 829 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 829 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 829 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 830 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 830 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 830 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 831 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 831 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 831 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 832, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 832 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 832 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 832 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 833 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 833 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 833 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 834 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 834 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 834 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 835 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 835 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 835 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 836 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 836 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 836 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 837 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 837 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 837 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 838 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 838 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 838 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 839 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 839 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 839 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 840, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 840 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 840 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 840 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 841 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 841 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 841 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 842 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 842 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 842 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 843 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 843 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 843 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 844 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 844 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 844 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 845 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 845 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 845 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 846 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 846 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 846 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 847 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 847 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 847 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 848, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 848 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 848 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 848 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 849 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 849 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 849 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 850 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 850 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 850 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 851 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 851 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 851 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 852 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 852 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 852 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 853 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 853 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 853 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 854 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 854 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 854 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 855 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 855 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 855 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 856, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 856 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 856 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 856 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 857 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 857 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 857 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 858 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 858 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 858 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 859 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 859 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 859 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 860 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 860 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 860 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 861 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 861 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 861 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 862 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 862 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 862 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 863 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 863 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 863 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 864, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 864 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 864 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 864 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 865 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 865 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 865 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 866 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 866 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 866 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 867 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 867 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 867 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 868 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 868 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 868 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 869 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 869 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 869 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 870 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 870 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 870 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 871 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 871 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 871 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 872, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 872 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 872 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 872 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 873 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 873 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 873 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 874 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 874 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 874 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 875 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 875 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 875 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 876 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 876 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 876 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 877 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 877 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 877 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 878 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 878 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 878 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 879 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 879 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 879 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 880, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 880 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 880 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 880 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 881 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 881 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 881 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 882 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 882 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 882 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 883 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 883 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 883 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 884 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 884 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 884 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 885 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 885 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 885 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 886 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 886 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 886 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 887 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 887 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 887 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 888, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 888 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 888 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 888 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 889 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 889 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 889 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 890 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 890 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 890 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 891 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 891 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 891 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 892 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 892 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 892 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 893 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 893 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 893 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 894 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 894 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 894 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 895 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 895 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 895 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 896, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 896 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 896 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 896 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 897 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 897 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 897 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 898 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 898 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 898 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 899 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 899 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 899 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 900 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 900 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 900 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 901 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 901 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 901 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 902 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 902 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 902 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 903 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 903 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 903 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 904, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 904 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 904 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 904 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 905 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 905 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 905 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 906 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 906 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 906 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 907 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 907 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 907 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 908 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 908 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 908 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 909 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 909 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 909 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 910 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 910 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 910 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 911 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 911 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 911 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 912, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 912 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 912 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 912 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 913 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 913 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 913 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 914 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 914 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 914 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 915 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 915 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 915 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 916 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 916 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 916 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 917 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 917 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 917 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 918 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 918 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 918 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 919 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 919 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 919 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 920, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 920 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 920 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 920 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 921 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 921 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 921 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 922 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 922 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 922 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 923 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 923 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 923 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 924 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 924 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 924 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 925 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 925 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 925 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 926 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 926 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 926 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 927 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 927 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 927 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 928, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 928 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 928 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 928 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 929 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 929 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 929 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 930 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 930 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 930 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 931 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 931 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 931 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 932 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 932 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 932 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 933 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 933 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 933 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 934 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 934 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 934 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 935 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 935 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 935 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 936, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 936 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 936 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 936 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 937 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 937 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 937 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 938 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 938 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 938 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 939 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 939 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 939 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 940 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 940 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 940 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 941 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 941 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 941 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 942 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 942 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 942 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 943 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 943 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 943 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 944, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 944 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 944 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 944 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 945 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 945 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 945 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 946 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 946 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 946 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 947 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 947 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 947 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 948 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 948 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 948 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 949 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 949 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 949 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 950 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 950 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 950 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 951 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 951 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 951 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 952, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 952 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 952 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 952 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 953 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 953 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 953 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 954 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 954 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 954 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 955 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 955 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 955 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 956 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 956 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 956 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 957 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 957 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 957 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 958 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 958 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 958 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 959 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 959 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 959 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 960, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 960 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 960 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 960 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 961 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 961 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 961 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 962 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 962 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 962 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 963 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 963 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 963 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 964 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 964 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 964 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 965 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 965 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 965 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 966 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 966 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 966 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 967 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 967 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 967 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 968, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 968 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 968 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 968 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 969 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 969 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 969 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 970 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 970 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 970 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 971 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 971 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 971 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 972 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 972 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 972 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 973 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 973 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 973 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 974 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 974 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 974 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 975 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 975 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 975 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 976, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 976 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 976 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 976 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 977 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 977 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 977 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 978 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 978 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 978 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 979 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 979 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 979 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 980 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 980 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 980 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 981 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 981 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 981 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 982 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 982 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 982 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 983 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 983 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 983 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 984, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 984 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 984 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 984 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 985 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 985 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 985 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 986 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 986 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 986 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 987 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 987 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 987 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 988 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 988 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 988 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 989 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 989 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 989 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 990 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 990 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 990 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 991 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 991 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 991 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 992, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 992 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 992 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 992 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 993 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 993 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 993 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 994 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 994 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 994 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 995 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 995 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 995 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 996 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 996 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 996 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 997 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 997 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 997 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 998 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 998 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 998 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 999 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 999 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 999 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 1000, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1000 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1000 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1000 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1001 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1001 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1001 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1002 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1002 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1002 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1003 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1003 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1003 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1004 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1004 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1004 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1005 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1005 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1005 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1006 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1006 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1006 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1007 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1007 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1007 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 1008, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1008 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1008 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1008 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1009 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1009 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1009 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1010 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1010 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1010 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1011 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1011 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1011 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1012 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1012 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1012 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1013 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1013 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1013 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1014 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1014 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1014 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1015 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1015 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1015 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 1016, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1016 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1016 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1016 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1017 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1017 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1017 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1018 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1018 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1018 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1019 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1019 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1019 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1020 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1020 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1020 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1021 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1021 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1021 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1022 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1022 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1022 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1023 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1023 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1023 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 0, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 0 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 0 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 0 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 0 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 2 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 2 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 2 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 3 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 3 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 3 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 4 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 4 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 4 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 5 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 5 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 5 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 6 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 6 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 6 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 7 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 7 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 7 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 8, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 8 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 8 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 8 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 8 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 9 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 9 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 9 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 10 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 10 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 10 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 11 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 11 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 11 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 12 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 12 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 12 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 13 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 13 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 13 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 14 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 14 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 14 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 15 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 15 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 15 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 16, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 16 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 16 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 16 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 16 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 17 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 17 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 17 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 18 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 18 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 18 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 19 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 19 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 19 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 20 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 20 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 20 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 21 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 21 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 21 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 22 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 22 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 22 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 23 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 23 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 23 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 24, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 24 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 24 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 24 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 24 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 25 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 25 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 25 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 26 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 26 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 26 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 27 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 27 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 27 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 28 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 28 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 28 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 29 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 29 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 29 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 30 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 30 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 30 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 31 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 31 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 31 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 32, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 32 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 32 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 32 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 32 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 33 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 33 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 33 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 34 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 34 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 34 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 35 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 35 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 35 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 36 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 36 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 36 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 37 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 37 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 37 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 38 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 38 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 38 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 39 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 39 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 39 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 40, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 40 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 40 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 40 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 40 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 41 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 41 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 41 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 42 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 42 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 42 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 43 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 43 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 43 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 44 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 44 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 44 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 45 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 45 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 45 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 46 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 46 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 46 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 47 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 47 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 47 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 48, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 48 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 48 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 48 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 48 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 49 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 49 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 49 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 50 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 50 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 50 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 51 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 51 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 51 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 52 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 52 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 52 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 53 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 53 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 53 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 54 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 54 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 54 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 55 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 55 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 55 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 56, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 56 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 56 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 56 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 56 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 57 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 57 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 57 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 58 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 58 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 58 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 59 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 59 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 59 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 60 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 60 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 60 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 61 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 61 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 61 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 62 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 62 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 62 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 63 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 63 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 63 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 64, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 64 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 64 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 64 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 64 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 65 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 65 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 65 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 66 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 66 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 66 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 67 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 67 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 67 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 68 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 68 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 68 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 69 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 69 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 69 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 70 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 70 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 70 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 71 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 71 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 71 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 72, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 72 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 72 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 72 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 72 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 73 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 73 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 73 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 74 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 74 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 74 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 75 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 75 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 75 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 76 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 76 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 76 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 77 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 77 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 77 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 78 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 78 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 78 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 79 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 79 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 79 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 80, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 80 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 80 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 80 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 81 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 81 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 81 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 82 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 82 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 82 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 83 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 83 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 83 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 84 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 84 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 84 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 85 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 85 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 85 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 86 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 86 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 86 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 87 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 87 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 87 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 88, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 88 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 88 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 88 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 89 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 89 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 89 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 90 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 90 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 90 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 91 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 91 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 91 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 92 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 92 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 92 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 93 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 93 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 93 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 94 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 94 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 94 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 95 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 95 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 95 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 96, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 96 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 96 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 96 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 97 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 97 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 97 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 98 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 98 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 98 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 99 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 99 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 99 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 100 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 100 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 100 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 101 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 101 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 101 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 102 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 102 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 102 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 103 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 103 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 103 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 104, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 104 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 104 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 104 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 105 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 105 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 105 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 106 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 106 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 106 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 107 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 107 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 107 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 108 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 108 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 108 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 109 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 109 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 109 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 110 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 110 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 110 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 111 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 111 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 111 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 112, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 112 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 112 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 112 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 113 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 113 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 113 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 114 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 114 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 114 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 115 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 115 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 115 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 116 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 116 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 116 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 117 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 117 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 117 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 118 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 118 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 118 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 119 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 119 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 119 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 120, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 120 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 120 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 120 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 121 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 121 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 121 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 122 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 122 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 122 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 123 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 123 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 123 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 124 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 124 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 124 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 125 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 125 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 125 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 126 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 126 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 126 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 127 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 127 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 127 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 128, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 128 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 128 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 128 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 129 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 129 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 129 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 130 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 130 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 130 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 131 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 131 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 131 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 132 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 132 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 132 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 133 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 133 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 133 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 134 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 134 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 134 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 135 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 135 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 135 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 136, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 136 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 136 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 136 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 137 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 137 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 137 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 138 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 138 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 138 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 139 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 139 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 139 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 140 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 140 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 140 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 141 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 141 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 141 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 142 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 142 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 142 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 143 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 143 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 143 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 144, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 144 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 144 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 144 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 145 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 145 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 145 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 146 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 146 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 146 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 147 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 147 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 147 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 148 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 148 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 148 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 149 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 149 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 149 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 150 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 150 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 150 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 151 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 151 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 151 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 152, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 152 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 152 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 152 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 153 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 153 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 153 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 154 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 154 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 154 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 155 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 155 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 155 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 156 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 156 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 156 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 157 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 157 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 157 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 158 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 158 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 158 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 159 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 159 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 159 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 160, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 160 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 160 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 160 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 161 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 161 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 161 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 162 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 162 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 162 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 163 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 163 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 163 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 164 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 164 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 164 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 165 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 165 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 165 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 166 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 166 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 166 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 167 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 167 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 167 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 168, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 168 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 168 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 168 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 169 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 169 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 169 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 170 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 170 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 170 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 171 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 171 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 171 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 172 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 172 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 172 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 173 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 173 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 173 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 174 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 174 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 174 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 175 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 175 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 175 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 176, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 176 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 176 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 176 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 177 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 177 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 177 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 178 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 178 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 178 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 179 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 179 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 179 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 180 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 180 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 180 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 181 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 181 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 181 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 182 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 182 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 182 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 183 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 183 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 183 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 184, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 184 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 184 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 184 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 185 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 185 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 185 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 186 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 186 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 186 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 187 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 187 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 187 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 188 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 188 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 188 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 189 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 189 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 189 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 190 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 190 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 190 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 191 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 191 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 191 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 192, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 192 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 192 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 192 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 193 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 193 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 193 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 194 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 194 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 194 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 195 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 195 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 195 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 196 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 196 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 196 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 197 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 197 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 197 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 198 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 198 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 198 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 199 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 199 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 199 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 200, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 200 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 200 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 200 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 201 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 201 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 201 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 202 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 202 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 202 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 203 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 203 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 203 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 204 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 204 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 204 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 205 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 205 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 205 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 206 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 206 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 206 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 207 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 207 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 207 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 208, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 208 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 208 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 208 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 208 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 208 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 208 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 208 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 208 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 208 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 209 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 209 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 209 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 209 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 209 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 209 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 209 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 209 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 209 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 210 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 210 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 210 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 210 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 210 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 210 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 210 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 210 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 210 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 211 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 211 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 211 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 211 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 211 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 211 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 211 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 211 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 211 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 212 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 212 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 212 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 212 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 212 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 212 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 212 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 212 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 212 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 213 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 213 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 213 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 213 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 213 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 213 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 213 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 213 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 213 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 214 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 214 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 214 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 214 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 214 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 214 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 214 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 214 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 214 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 215 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 215 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 215 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 215 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 215 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 215 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 215 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 215 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 215 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 216, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 216 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 216 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 216 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 216 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 216 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 216 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 216 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 216 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 216 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 217 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 217 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 217 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 217 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 217 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 217 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 217 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 217 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 217 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 218 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 218 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 218 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 218 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 218 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 218 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 218 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 218 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 218 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 219 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 219 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 219 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 219 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 219 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 219 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 219 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 219 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 219 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 220 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 220 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 220 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 220 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 220 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 220 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 220 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 220 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 220 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 221 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 221 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 221 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 221 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 221 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 221 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 221 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 221 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 221 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 222 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 222 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 222 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 222 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 222 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 222 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 222 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 222 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 222 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 223 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 223 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 223 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 223 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 223 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 223 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 223 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 223 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 223 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 224, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 224 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 224 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 224 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 224 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 224 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 224 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 224 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 224 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 224 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 225 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 225 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 225 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 225 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 225 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 225 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 225 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 225 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 225 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 226 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 226 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 226 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 226 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 226 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 226 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 226 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 226 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 226 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 227 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 227 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 227 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 227 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 227 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 227 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 227 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 227 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 227 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 228 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 228 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 228 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 228 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 228 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 228 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 228 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 228 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 228 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 229 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 229 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 229 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 229 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 229 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 229 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 229 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 229 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 229 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 230 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 230 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 230 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 230 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 230 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 230 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 230 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 230 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 230 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 231 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 231 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 231 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 231 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 231 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 231 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 231 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 231 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 231 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 232, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 232 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 232 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 232 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 232 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 232 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 232 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 232 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 232 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 232 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 233 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 233 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 233 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 233 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 233 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 233 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 233 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 233 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 233 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 234 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 234 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 234 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 234 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 234 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 234 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 234 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 234 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 234 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 235 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 235 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 235 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 235 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 235 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 235 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 235 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 235 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 235 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 236 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 236 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 236 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 236 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 236 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 236 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 236 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 236 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 236 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 237 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 237 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 237 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 237 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 237 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 237 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 237 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 237 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 237 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 238 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 238 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 238 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 238 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 238 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 238 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 238 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 238 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 238 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 239 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 239 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 239 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 239 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 239 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 239 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 239 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 239 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 239 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 240, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 240 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 240 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 240 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 240 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 240 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 240 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 240 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 240 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 240 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 241 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 241 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 241 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 241 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 241 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 241 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 241 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 241 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 241 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 242 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 242 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 242 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 242 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 242 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 242 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 242 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 242 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 242 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 243 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 243 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 243 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 243 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 243 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 243 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 243 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 243 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 243 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 244 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 244 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 244 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 244 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 244 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 244 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 244 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 244 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 244 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 245 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 245 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 245 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 245 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 245 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 245 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 245 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 245 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 245 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 246 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 246 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 246 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 246 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 246 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 246 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 246 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 246 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 246 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 247 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 247 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 247 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 247 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 247 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 247 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 247 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 247 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 247 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 248, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 248 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 248 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 248 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 248 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 248 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 248 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 248 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 248 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 248 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 249 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 249 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 249 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 249 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 249 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 249 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 249 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 249 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 249 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 250 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 250 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 250 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 250 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 250 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 250 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 250 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 250 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 250 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 251 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 251 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 251 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 251 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 251 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 251 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 251 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 251 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 251 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 252 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 252 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 252 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 252 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 252 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 252 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 252 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 252 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 252 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 253 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 253 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 253 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 253 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 253 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 253 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 253 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 253 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 253 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 254 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 254 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 254 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 254 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 254 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 254 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 254 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 254 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 254 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 255 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 255 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 255 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 255 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 255 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 255 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 255 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 255 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 255 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 256, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 256 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 256 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 256 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 256 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 256 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 256 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 256 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 256 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 256 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 257 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 257 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 257 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 257 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 257 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 257 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 257 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 257 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 257 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 258 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 258 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 258 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 258 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 258 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 258 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 258 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 258 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 258 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 259 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 259 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 259 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 259 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 259 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 259 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 259 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 259 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 259 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 260 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 260 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 260 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 260 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 260 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 260 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 260 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 260 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 260 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 261 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 261 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 261 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 261 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 261 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 261 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 261 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 261 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 261 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 262 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 262 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 262 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 262 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 262 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 262 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 262 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 262 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 262 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 263 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 263 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 263 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 263 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 263 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 263 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 263 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 263 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 263 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 264, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 264 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 264 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 264 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 264 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 264 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 264 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 264 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 264 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 264 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 265 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 265 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 265 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 265 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 265 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 265 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 265 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 265 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 265 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 266 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 266 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 266 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 266 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 266 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 266 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 266 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 266 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 266 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 267 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 267 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 267 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 267 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 267 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 267 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 267 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 267 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 267 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 268 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 268 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 268 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 268 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 268 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 268 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 268 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 268 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 268 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 269 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 269 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 269 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 269 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 269 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 269 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 269 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 269 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 269 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 270 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 270 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 270 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 270 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 270 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 270 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 270 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 270 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 270 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 271 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 271 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 271 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 271 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 271 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 271 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 271 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 271 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 271 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 272, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 272 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 272 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 272 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 272 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 272 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 272 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 272 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 272 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 272 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 273 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 273 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 273 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 273 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 273 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 273 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 273 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 273 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 273 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 274 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 274 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 274 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 274 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 274 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 274 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 274 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 274 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 274 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 275 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 275 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 275 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 275 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 275 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 275 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 275 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 275 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 275 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 276 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 276 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 276 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 276 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 276 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 276 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 276 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 276 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 276 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 277 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 277 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 277 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 277 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 277 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 277 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 277 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 277 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 277 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 278 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 278 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 278 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 278 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 278 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 278 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 278 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 278 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 278 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 279 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 279 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 279 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 279 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 279 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 279 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 279 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 279 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 279 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 280, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 280 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 280 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 280 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 280 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 280 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 280 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 280 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 280 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 280 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 281 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 281 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 281 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 281 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 281 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 281 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 281 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 281 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 281 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 282 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 282 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 282 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 282 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 282 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 282 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 282 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 282 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 282 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 283 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 283 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 283 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 283 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 283 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 283 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 283 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 283 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 283 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 284 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 284 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 284 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 284 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 284 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 284 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 284 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 284 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 284 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 285 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 285 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 285 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 285 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 285 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 285 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 285 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 285 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 285 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 286 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 286 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 286 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 286 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 286 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 286 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 286 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 286 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 286 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 287 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 287 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 287 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 287 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 287 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 287 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 287 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 287 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 287 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 288, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 288 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 288 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 288 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 288 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 288 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 288 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 288 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 288 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 288 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 289 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 289 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 289 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 289 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 289 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 289 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 289 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 289 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 289 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 290 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 290 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 290 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 290 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 290 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 290 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 290 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 290 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 290 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 291 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 291 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 291 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 291 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 291 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 291 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 291 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 291 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 291 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 292 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 292 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 292 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 292 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 292 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 292 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 292 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 292 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 292 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 293 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 293 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 293 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 293 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 293 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 293 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 293 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 293 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 293 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 294 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 294 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 294 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 294 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 294 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 294 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 294 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 294 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 294 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 295 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 295 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 295 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 295 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 295 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 295 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 295 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 295 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 295 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 296, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 296 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 296 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 296 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 296 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 296 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 296 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 296 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 296 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 296 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 297 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 297 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 297 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 297 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 297 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 297 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 297 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 297 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 297 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 298 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 298 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 298 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 298 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 298 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 298 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 298 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 298 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 298 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 299 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 299 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 299 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 299 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 299 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 299 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 299 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 299 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 299 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 300 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 300 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 300 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 300 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 300 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 300 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 300 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 300 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 300 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 301 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 301 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 301 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 301 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 301 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 301 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 301 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 301 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 301 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 302 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 302 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 302 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 302 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 302 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 302 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 302 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 302 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 302 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 303 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 303 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 303 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 303 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 303 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 303 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 303 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 303 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 303 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 304, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 304 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 304 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 304 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 304 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 304 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 304 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 304 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 304 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 304 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 305 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 305 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 305 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 305 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 305 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 305 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 305 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 305 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 305 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 306 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 306 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 306 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 306 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 306 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 306 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 306 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 306 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 306 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 307 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 307 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 307 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 307 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 307 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 307 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 307 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 307 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 307 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 308 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 308 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 308 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 308 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 308 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 308 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 308 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 308 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 308 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 309 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 309 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 309 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 309 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 309 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 309 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 309 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 309 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 309 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 310 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 310 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 310 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 310 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 310 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 310 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 310 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 310 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 310 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 311 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 311 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 311 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 311 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 311 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 311 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 311 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 311 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 311 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 312, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 312 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 312 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 312 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 312 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 312 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 312 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 312 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 312 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 312 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 313 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 313 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 313 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 313 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 313 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 313 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 313 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 313 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 313 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 314 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 314 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 314 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 314 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 314 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 314 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 314 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 314 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 314 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 315 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 315 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 315 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 315 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 315 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 315 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 315 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 315 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 315 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 316 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 316 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 316 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 316 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 316 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 316 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 316 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 316 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 316 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 317 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 317 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 317 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 317 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 317 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 317 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 317 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 317 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 317 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 318 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 318 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 318 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 318 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 318 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 318 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 318 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 318 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 318 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 319 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 319 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 319 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 319 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 319 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 319 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 319 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 319 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 319 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 320, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 320 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 320 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 320 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 320 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 320 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 320 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 320 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 320 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 320 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 321 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 321 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 321 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 321 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 321 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 321 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 321 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 321 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 321 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 322 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 322 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 322 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 322 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 322 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 322 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 322 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 322 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 322 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 323 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 323 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 323 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 323 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 323 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 323 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 323 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 323 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 323 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 324 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 324 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 324 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 324 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 324 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 324 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 324 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 324 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 324 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 325 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 325 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 325 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 325 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 325 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 325 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 325 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 325 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 325 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 326 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 326 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 326 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 326 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 326 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 326 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 326 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 326 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 326 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 327 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 327 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 327 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 327 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 327 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 327 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 327 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 327 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 327 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 328, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 328 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 328 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 328 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 328 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 328 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 328 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 328 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 328 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 328 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 329 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 329 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 329 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 329 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 329 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 329 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 329 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 329 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 329 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 330 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 330 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 330 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 330 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 330 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 330 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 330 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 330 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 330 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 331 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 331 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 331 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 331 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 331 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 331 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 331 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 331 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 331 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 332 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 332 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 332 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 332 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 332 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 332 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 332 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 332 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 332 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 333 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 333 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 333 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 333 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 333 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 333 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 333 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 333 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 333 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 334 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 334 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 334 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 334 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 334 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 334 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 334 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 334 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 334 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 335 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 335 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 335 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 335 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 335 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 335 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 335 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 335 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 335 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 336, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 336 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 336 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 336 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 336 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 336 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 336 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 336 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 336 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 336 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 337 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 337 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 337 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 337 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 337 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 337 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 337 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 337 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 337 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 338 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 338 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 338 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 338 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 338 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 338 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 338 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 338 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 338 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 339 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 339 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 339 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 339 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 339 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 339 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 339 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 339 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 339 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 340 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 340 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 340 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 340 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 340 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 340 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 340 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 340 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 340 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 341 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 341 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 341 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 341 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 341 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 341 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 341 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 341 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 341 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 342 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 342 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 342 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 342 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 342 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 342 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 342 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 342 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 342 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 343 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 343 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 343 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 343 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 343 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 343 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 343 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 343 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 343 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 344, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 344 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 344 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 344 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 344 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 344 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 344 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 344 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 344 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 344 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 345 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 345 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 345 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 345 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 345 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 345 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 345 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 345 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 345 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 346 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 346 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 346 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 346 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 346 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 346 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 346 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 346 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 346 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 347 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 347 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 347 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 347 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 347 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 347 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 347 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 347 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 347 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 348 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 348 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 348 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 348 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 348 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 348 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 348 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 348 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 348 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 349 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 349 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 349 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 349 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 349 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 349 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 349 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 349 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 349 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 350 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 350 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 350 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 350 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 350 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 350 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 350 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 350 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 350 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 351 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 351 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 351 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 351 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 351 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 351 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 351 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 351 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 351 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 352, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 352 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 352 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 352 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 352 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 352 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 352 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 352 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 352 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 352 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 353 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 353 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 353 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 353 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 353 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 353 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 353 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 353 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 353 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 354 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 354 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 354 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 354 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 354 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 354 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 354 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 354 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 354 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 355 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 355 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 355 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 355 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 355 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 355 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 355 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 355 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 355 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 356 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 356 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 356 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 356 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 356 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 356 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 356 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 356 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 356 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 357 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 357 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 357 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 357 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 357 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 357 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 357 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 357 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 357 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 358 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 358 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 358 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 358 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 358 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 358 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 358 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 358 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 358 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 359 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 359 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 359 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 359 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 359 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 359 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 359 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 359 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 359 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 360, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 360 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 360 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 360 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 360 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 360 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 360 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 360 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 360 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 360 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 361 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 361 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 361 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 361 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 361 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 361 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 361 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 361 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 361 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 362 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 362 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 362 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 362 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 362 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 362 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 362 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 362 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 362 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 363 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 363 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 363 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 363 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 363 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 363 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 363 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 363 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 363 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 364 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 364 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 364 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 364 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 364 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 364 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 364 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 364 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 364 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 365 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 365 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 365 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 365 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 365 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 365 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 365 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 365 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 365 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 366 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 366 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 366 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 366 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 366 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 366 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 366 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 366 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 366 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 367 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 367 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 367 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 367 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 367 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 367 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 367 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 367 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 367 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 368, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 368 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 368 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 368 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 368 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 368 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 368 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 368 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 368 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 368 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 369 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 369 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 369 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 369 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 369 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 369 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 369 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 369 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 369 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 370 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 370 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 370 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 370 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 370 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 370 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 370 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 370 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 370 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 371 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 371 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 371 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 371 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 371 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 371 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 371 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 371 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 371 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 372 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 372 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 372 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 372 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 372 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 372 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 372 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 372 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 372 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 373 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 373 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 373 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 373 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 373 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 373 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 373 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 373 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 373 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 374 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 374 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 374 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 374 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 374 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 374 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 374 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 374 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 374 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 375 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 375 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 375 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 375 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 375 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 375 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 375 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 375 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 375 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 376, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 376 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 376 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 376 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 376 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 376 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 376 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 376 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 376 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 376 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 377 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 377 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 377 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 377 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 377 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 377 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 377 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 377 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 377 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 378 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 378 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 378 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 378 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 378 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 378 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 378 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 378 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 378 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 379 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 379 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 379 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 379 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 379 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 379 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 379 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 379 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 379 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 380 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 380 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 380 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 380 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 380 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 380 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 380 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 380 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 380 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 381 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 381 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 381 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 381 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 381 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 381 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 381 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 381 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 381 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 382 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 382 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 382 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 382 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 382 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 382 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 382 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 382 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 382 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 383 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 383 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 383 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 383 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 383 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 383 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 383 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 383 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 383 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 384, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 384 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 384 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 384 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 384 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 384 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 384 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 384 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 384 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 384 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 385 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 385 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 385 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 385 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 385 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 385 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 385 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 385 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 385 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 386 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 386 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 386 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 386 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 386 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 386 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 386 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 386 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 386 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 387 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 387 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 387 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 387 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 387 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 387 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 387 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 387 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 387 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 388 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 388 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 388 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 388 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 388 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 388 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 388 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 388 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 388 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 389 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 389 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 389 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 389 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 389 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 389 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 389 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 389 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 389 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 390 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 390 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 390 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 390 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 390 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 390 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 390 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 390 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 390 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 391 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 391 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 391 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 391 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 391 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 391 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 391 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 391 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 391 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 392, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 392 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 392 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 392 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 392 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 392 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 392 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 392 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 392 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 392 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 393 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 393 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 393 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 393 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 393 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 393 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 393 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 393 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 393 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 394 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 394 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 394 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 394 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 394 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 394 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 394 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 394 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 394 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 395 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 395 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 395 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 395 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 395 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 395 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 395 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 395 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 395 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 396 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 396 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 396 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 396 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 396 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 396 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 396 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 396 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 396 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 397 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 397 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 397 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 397 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 397 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 397 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 397 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 397 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 397 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 398 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 398 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 398 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 398 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 398 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 398 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 398 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 398 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 398 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 399 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 399 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 399 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 399 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 399 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 399 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 399 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 399 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 399 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 400, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 400 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 400 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 400 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 400 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 400 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 400 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 400 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 400 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 400 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 401 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 401 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 401 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 401 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 401 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 401 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 401 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 401 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 401 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 402 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 402 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 402 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 402 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 402 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 402 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 402 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 402 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 402 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 403 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 403 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 403 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 403 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 403 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 403 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 403 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 403 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 403 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 404 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 404 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 404 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 404 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 404 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 404 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 404 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 404 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 404 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 405 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 405 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 405 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 405 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 405 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 405 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 405 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 405 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 405 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 406 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 406 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 406 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 406 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 406 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 406 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 406 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 406 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 406 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 407 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 407 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 407 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 407 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 407 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 407 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 407 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 407 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 407 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 408, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 408 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 408 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 408 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 408 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 408 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 408 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 408 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 408 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 408 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 409 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 409 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 409 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 409 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 409 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 409 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 409 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 409 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 409 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 410 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 410 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 410 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 410 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 410 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 410 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 410 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 410 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 410 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 411 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 411 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 411 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 411 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 411 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 411 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 411 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 411 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 411 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 412 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 412 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 412 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 412 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 412 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 412 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 412 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 412 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 412 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 413 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 413 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 413 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 413 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 413 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 413 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 413 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 413 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 413 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 414 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 414 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 414 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 414 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 414 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 414 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 414 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 414 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 414 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 415 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 415 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 415 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 415 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 415 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 415 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 415 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 415 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 415 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 416, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 416 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 416 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 416 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 416 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 416 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 416 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 416 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 416 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 416 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 417 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 417 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 417 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 417 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 417 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 417 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 417 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 417 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 417 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 418 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 418 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 418 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 418 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 418 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 418 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 418 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 418 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 418 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 419 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 419 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 419 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 419 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 419 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 419 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 419 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 419 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 419 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 420 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 420 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 420 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 420 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 420 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 420 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 420 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 420 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 420 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 421 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 421 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 421 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 421 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 421 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 421 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 421 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 421 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 421 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 422 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 422 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 422 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 422 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 422 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 422 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 422 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 422 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 422 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 423 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 423 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 423 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 423 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 423 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 423 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 423 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 423 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 423 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 424, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 424 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 424 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 424 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 424 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 424 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 424 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 424 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 424 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 424 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 425 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 425 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 425 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 425 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 425 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 425 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 425 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 425 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 425 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 426 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 426 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 426 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 426 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 426 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 426 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 426 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 426 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 426 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 427 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 427 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 427 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 427 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 427 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 427 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 427 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 427 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 427 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 428 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 428 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 428 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 428 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 428 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 428 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 428 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 428 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 428 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 429 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 429 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 429 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 429 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 429 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 429 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 429 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 429 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 429 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 430 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 430 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 430 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 430 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 430 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 430 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 430 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 430 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 430 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 431 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 431 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 431 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 431 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 431 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 431 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 431 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 431 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 431 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 432, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 432 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 432 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 432 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 432 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 432 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 432 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 432 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 432 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 432 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 433 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 433 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 433 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 433 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 433 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 433 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 433 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 433 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 433 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 434 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 434 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 434 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 434 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 434 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 434 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 434 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 434 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 434 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 435 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 435 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 435 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 435 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 435 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 435 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 435 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 435 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 435 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 436 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 436 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 436 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 436 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 436 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 436 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 436 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 436 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 436 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 437 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 437 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 437 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 437 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 437 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 437 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 437 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 437 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 437 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 438 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 438 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 438 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 438 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 438 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 438 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 438 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 438 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 438 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 439 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 439 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 439 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 439 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 439 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 439 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 439 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 439 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 439 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 440, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 440 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 440 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 440 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 440 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 440 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 440 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 440 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 440 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 440 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 441 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 441 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 441 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 441 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 441 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 441 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 441 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 441 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 441 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 442 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 442 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 442 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 442 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 442 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 442 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 442 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 442 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 442 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 443 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 443 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 443 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 443 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 443 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 443 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 443 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 443 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 443 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 444 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 444 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 444 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 444 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 444 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 444 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 444 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 444 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 444 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 445 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 445 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 445 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 445 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 445 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 445 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 445 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 445 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 445 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 446 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 446 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 446 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 446 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 446 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 446 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 446 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 446 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 446 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 447 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 447 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 447 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 447 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 447 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 447 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 447 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 447 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 447 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 448, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 448 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 448 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 448 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 448 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 448 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 448 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 448 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 448 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 448 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 449 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 449 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 449 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 449 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 449 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 449 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 449 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 449 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 449 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 450 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 450 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 450 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 450 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 450 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 450 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 450 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 450 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 450 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 451 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 451 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 451 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 451 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 451 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 451 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 451 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 451 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 451 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 452 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 452 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 452 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 452 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 452 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 452 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 452 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 452 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 452 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 453 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 453 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 453 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 453 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 453 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 453 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 453 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 453 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 453 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 454 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 454 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 454 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 454 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 454 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 454 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 454 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 454 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 454 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 455 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 455 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 455 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 455 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 455 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 455 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 455 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 455 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 455 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 456, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 456 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 456 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 456 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 456 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 456 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 456 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 456 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 456 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 456 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 457 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 457 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 457 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 457 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 457 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 457 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 457 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 457 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 457 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 458 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 458 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 458 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 458 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 458 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 458 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 458 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 458 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 458 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 459 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 459 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 459 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 459 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 459 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 459 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 459 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 459 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 459 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 460 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 460 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 460 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 460 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 460 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 460 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 460 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 460 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 460 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 461 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 461 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 461 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 461 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 461 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 461 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 461 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 461 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 461 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 462 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 462 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 462 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 462 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 462 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 462 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 462 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 462 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 462 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 463 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 463 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 463 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 463 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 463 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 463 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 463 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 463 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 463 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 464, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 464 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 464 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 464 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 464 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 464 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 464 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 464 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 464 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 464 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 465 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 465 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 465 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 465 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 465 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 465 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 465 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 465 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 465 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 466 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 466 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 466 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 466 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 466 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 466 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 466 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 466 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 466 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 467 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 467 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 467 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 467 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 467 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 467 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 467 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 467 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 467 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 468 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 468 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 468 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 468 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 468 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 468 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 468 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 468 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 468 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 469 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 469 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 469 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 469 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 469 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 469 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 469 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 469 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 469 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 470 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 470 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 470 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 470 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 470 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 470 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 470 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 470 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 470 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 471 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 471 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 471 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 471 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 471 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 471 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 471 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 471 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 471 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 472, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 472 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 472 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 472 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 472 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 472 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 472 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 472 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 472 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 472 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 473 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 473 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 473 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 473 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 473 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 473 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 473 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 473 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 473 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 474 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 474 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 474 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 474 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 474 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 474 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 474 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 474 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 474 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 475 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 475 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 475 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 475 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 475 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 475 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 475 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 475 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 475 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 476 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 476 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 476 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 476 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 476 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 476 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 476 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 476 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 476 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 477 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 477 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 477 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 477 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 477 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 477 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 477 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 477 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 477 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 478 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 478 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 478 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 478 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 478 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 478 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 478 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 478 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 478 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 479 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 479 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 479 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 479 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 479 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 479 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 479 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 479 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 479 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 480, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 480 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 480 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 480 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 480 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 480 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 480 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 480 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 480 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 480 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 481 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 481 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 481 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 481 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 481 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 481 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 481 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 481 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 481 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 482 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 482 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 482 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 482 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 482 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 482 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 482 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 482 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 482 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 483 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 483 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 483 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 483 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 483 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 483 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 483 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 483 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 483 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 484 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 484 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 484 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 484 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 484 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 484 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 484 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 484 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 484 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 485 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 485 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 485 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 485 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 485 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 485 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 485 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 485 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 485 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 486 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 486 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 486 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 486 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 486 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 486 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 486 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 486 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 486 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 487 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 487 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 487 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 487 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 487 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 487 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 487 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 487 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 487 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 488, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 488 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 488 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 488 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 488 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 488 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 488 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 488 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 488 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 488 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 489 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 489 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 489 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 489 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 489 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 489 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 489 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 489 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 489 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 490 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 490 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 490 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 490 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 490 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 490 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 490 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 490 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 490 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 491 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 491 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 491 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 491 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 491 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 491 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 491 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 491 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 491 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 492 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 492 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 492 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 492 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 492 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 492 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 492 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 492 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 492 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 493 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 493 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 493 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 493 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 493 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 493 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 493 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 493 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 493 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 494 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 494 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 494 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 494 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 494 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 494 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 494 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 494 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 494 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 495 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 495 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 495 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 495 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 495 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 495 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 495 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 495 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 495 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 496, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 496 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 496 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 496 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 496 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 496 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 496 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 496 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 496 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 496 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 497 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 497 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 497 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 497 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 497 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 497 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 497 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 497 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 497 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 498 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 498 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 498 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 498 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 498 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 498 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 498 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 498 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 498 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 499 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 499 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 499 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 499 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 499 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 499 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 499 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 499 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 499 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 500 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 500 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 500 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 500 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 500 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 500 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 500 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 500 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 500 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 501 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 501 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 501 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 501 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 501 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 501 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 501 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 501 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 501 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 502 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 502 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 502 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 502 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 502 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 502 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 502 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 502 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 502 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 503 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 503 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 503 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 503 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 503 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 503 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 503 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 503 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 503 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 504, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 504 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 504 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 504 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 504 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 504 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 504 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 504 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 504 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 504 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 505 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 505 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 505 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 505 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 505 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 505 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 505 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 505 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 505 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 506 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 506 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 506 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 506 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 506 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 506 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 506 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 506 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 506 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 507 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 507 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 507 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 507 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 507 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 507 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 507 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 507 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 507 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 508 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 508 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 508 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 508 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 508 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 508 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 508 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 508 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 508 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 509 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 509 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 509 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 509 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 509 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 509 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 509 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 509 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 509 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 510 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 510 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 510 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 510 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 510 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 510 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 510 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 510 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 510 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 511 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 511 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 511 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 511 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 511 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 511 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 511 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 511 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 511 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 512, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 512 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 512 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 512 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 512 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 512 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 512 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 512 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 512 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 512 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 513 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 513 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 513 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 513 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 513 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 513 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 513 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 513 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 513 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 514 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 514 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 514 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 514 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 514 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 514 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 514 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 514 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 514 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 515 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 515 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 515 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 515 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 515 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 515 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 515 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 515 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 515 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 516 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 516 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 516 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 516 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 516 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 516 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 516 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 516 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 516 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 517 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 517 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 517 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 517 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 517 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 517 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 517 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 517 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 517 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 518 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 518 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 518 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 518 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 518 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 518 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 518 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 518 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 518 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 519 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 519 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 519 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 519 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 519 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 519 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 519 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 519 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 519 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 520, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 520 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 520 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 520 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 520 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 520 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 520 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 520 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 520 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 520 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 521 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 521 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 521 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 521 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 521 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 521 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 521 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 521 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 521 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 522 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 522 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 522 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 522 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 522 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 522 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 522 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 522 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 522 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 523 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 523 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 523 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 523 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 523 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 523 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 523 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 523 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 523 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 524 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 524 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 524 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 524 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 524 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 524 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 524 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 524 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 524 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 525 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 525 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 525 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 525 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 525 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 525 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 525 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 525 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 525 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 526 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 526 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 526 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 526 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 526 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 526 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 526 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 526 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 526 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 527 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 527 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 527 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 527 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 527 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 527 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 527 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 527 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 527 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 528, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 528 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 528 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 528 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 528 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 528 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 528 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 528 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 528 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 528 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 529 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 529 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 529 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 529 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 529 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 529 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 529 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 529 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 529 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 530 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 530 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 530 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 530 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 530 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 530 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 530 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 530 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 530 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 531 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 531 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 531 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 531 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 531 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 531 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 531 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 531 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 531 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 532 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 532 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 532 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 532 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 532 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 532 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 532 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 532 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 532 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 533 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 533 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 533 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 533 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 533 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 533 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 533 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 533 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 533 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 534 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 534 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 534 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 534 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 534 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 534 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 534 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 534 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 534 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 535 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 535 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 535 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 535 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 535 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 535 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 535 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 535 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 535 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 536, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 536 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 536 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 536 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 536 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 536 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 536 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 536 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 536 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 536 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 537 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 537 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 537 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 537 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 537 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 537 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 537 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 537 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 537 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 538 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 538 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 538 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 538 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 538 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 538 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 538 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 538 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 538 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 539 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 539 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 539 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 539 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 539 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 539 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 539 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 539 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 539 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 540 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 540 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 540 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 540 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 540 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 540 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 540 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 540 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 540 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 541 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 541 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 541 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 541 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 541 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 541 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 541 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 541 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 541 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 542 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 542 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 542 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 542 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 542 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 542 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 542 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 542 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 542 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 543 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 543 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 543 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 543 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 543 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 543 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 543 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 543 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 543 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 544, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 544 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 544 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 544 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 544 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 544 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 544 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 544 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 544 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 544 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 545 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 545 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 545 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 545 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 545 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 545 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 545 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 545 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 545 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 546 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 546 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 546 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 546 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 546 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 546 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 546 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 546 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 546 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 547 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 547 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 547 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 547 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 547 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 547 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 547 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 547 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 547 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 548 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 548 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 548 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 548 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 548 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 548 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 548 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 548 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 548 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 549 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 549 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 549 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 549 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 549 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 549 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 549 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 549 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 549 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 550 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 550 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 550 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 550 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 550 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 550 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 550 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 550 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 550 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 551 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 551 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 551 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 551 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 551 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 551 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 551 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 551 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 551 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 552, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 552 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 552 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 552 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 552 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 552 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 552 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 552 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 552 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 552 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 553 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 553 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 553 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 553 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 553 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 553 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 553 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 553 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 553 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 554 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 554 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 554 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 554 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 554 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 554 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 554 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 554 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 554 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 555 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 555 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 555 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 555 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 555 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 555 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 555 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 555 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 555 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 556 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 556 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 556 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 556 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 556 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 556 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 556 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 556 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 556 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 557 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 557 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 557 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 557 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 557 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 557 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 557 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 557 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 557 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 558 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 558 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 558 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 558 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 558 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 558 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 558 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 558 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 558 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 559 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 559 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 559 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 559 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 559 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 559 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 559 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 559 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 559 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 560, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 560 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 560 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 560 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 560 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 560 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 560 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 560 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 560 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 560 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 561 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 561 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 561 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 561 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 561 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 561 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 561 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 561 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 561 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 562 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 562 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 562 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 562 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 562 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 562 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 562 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 562 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 562 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 563 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 563 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 563 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 563 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 563 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 563 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 563 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 563 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 563 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 564 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 564 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 564 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 564 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 564 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 564 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 564 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 564 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 564 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 565 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 565 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 565 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 565 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 565 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 565 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 565 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 565 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 565 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 566 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 566 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 566 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 566 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 566 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 566 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 566 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 566 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 566 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 567 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 567 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 567 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 567 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 567 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 567 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 567 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 567 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 567 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 568, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 568 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 568 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 568 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 568 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 568 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 568 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 568 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 568 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 568 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 569 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 569 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 569 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 569 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 569 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 569 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 569 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 569 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 569 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 570 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 570 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 570 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 570 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 570 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 570 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 570 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 570 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 570 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 571 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 571 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 571 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 571 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 571 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 571 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 571 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 571 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 571 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 572 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 572 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 572 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 572 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 572 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 572 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 572 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 572 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 572 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 573 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 573 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 573 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 573 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 573 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 573 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 573 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 573 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 573 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 574 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 574 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 574 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 574 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 574 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 574 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 574 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 574 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 574 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 575 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 575 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 575 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 575 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 575 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 575 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 575 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 575 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 575 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 576, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 576 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 576 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 576 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 576 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 576 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 576 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 576 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 576 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 576 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 577 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 577 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 577 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 577 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 577 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 577 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 577 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 577 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 577 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 578 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 578 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 578 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 578 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 578 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 578 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 578 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 578 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 578 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 579 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 579 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 579 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 579 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 579 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 579 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 579 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 579 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 579 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 580 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 580 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 580 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 580 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 580 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 580 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 580 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 580 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 580 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 581 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 581 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 581 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 581 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 581 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 581 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 581 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 581 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 581 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 582 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 582 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 582 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 582 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 582 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 582 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 582 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 582 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 582 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 583 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 583 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 583 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 583 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 583 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 583 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 583 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 583 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 583 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 584, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 584 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 584 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 584 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 584 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 584 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 584 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 584 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 584 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 584 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 585 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 585 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 585 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 585 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 585 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 585 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 585 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 585 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 585 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 586 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 586 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 586 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 586 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 586 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 586 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 586 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 586 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 586 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 587 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 587 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 587 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 587 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 587 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 587 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 587 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 587 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 587 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 588 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 588 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 588 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 588 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 588 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 588 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 588 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 588 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 588 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 589 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 589 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 589 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 589 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 589 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 589 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 589 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 589 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 589 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 590 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 590 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 590 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 590 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 590 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 590 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 590 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 590 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 590 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 591 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 591 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 591 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 591 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 591 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 591 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 591 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 591 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 591 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 592, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 592 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 592 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 592 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 592 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 592 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 592 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 592 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 592 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 592 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 593 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 593 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 593 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 593 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 593 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 593 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 593 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 593 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 593 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 594 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 594 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 594 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 594 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 594 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 594 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 594 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 594 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 594 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 595 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 595 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 595 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 595 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 595 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 595 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 595 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 595 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 595 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 596 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 596 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 596 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 596 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 596 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 596 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 596 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 596 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 596 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 597 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 597 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 597 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 597 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 597 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 597 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 597 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 597 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 597 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 598 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 598 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 598 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 598 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 598 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 598 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 598 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 598 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 598 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 599 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 599 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 599 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 599 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 599 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 599 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 599 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 599 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 599 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 600, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 600 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 600 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 600 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 600 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 600 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 600 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 600 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 600 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 600 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 601 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 601 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 601 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 601 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 601 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 601 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 601 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 601 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 601 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 602 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 602 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 602 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 602 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 602 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 602 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 602 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 602 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 602 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 603 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 603 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 603 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 603 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 603 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 603 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 603 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 603 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 603 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 604 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 604 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 604 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 604 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 604 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 604 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 604 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 604 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 604 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 605 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 605 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 605 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 605 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 605 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 605 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 605 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 605 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 605 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 606 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 606 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 606 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 606 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 606 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 606 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 606 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 606 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 606 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 607 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 607 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 607 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 607 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 607 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 607 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 607 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 607 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 607 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 608, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 608 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 608 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 608 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 608 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 608 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 608 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 608 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 608 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 608 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 609 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 609 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 609 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 609 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 609 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 609 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 609 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 609 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 609 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 610 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 610 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 610 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 610 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 610 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 610 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 610 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 610 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 610 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 611 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 611 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 611 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 611 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 611 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 611 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 611 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 611 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 611 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 612 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 612 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 612 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 612 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 612 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 612 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 612 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 612 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 612 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 613 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 613 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 613 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 613 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 613 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 613 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 613 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 613 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 613 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 614 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 614 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 614 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 614 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 614 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 614 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 614 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 614 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 614 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 615 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 615 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 615 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 615 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 615 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 615 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 615 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 615 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 615 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 616, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 616 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 616 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 616 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 616 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 616 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 616 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 616 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 616 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 616 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 617 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 617 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 617 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 617 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 617 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 617 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 617 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 617 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 617 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 618 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 618 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 618 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 618 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 618 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 618 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 618 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 618 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 618 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 619 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 619 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 619 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 619 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 619 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 619 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 619 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 619 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 619 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 620 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 620 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 620 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 620 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 620 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 620 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 620 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 620 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 620 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 621 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 621 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 621 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 621 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 621 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 621 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 621 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 621 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 621 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 622 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 622 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 622 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 622 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 622 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 622 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 622 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 622 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 622 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 623 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 623 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 623 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 623 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 623 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 623 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 623 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 623 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 623 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 624, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 624 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 624 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 624 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 624 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 624 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 624 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 624 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 624 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 624 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 625 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 625 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 625 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 625 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 625 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 625 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 625 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 625 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 625 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 626 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 626 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 626 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 626 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 626 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 626 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 626 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 626 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 626 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 627 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 627 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 627 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 627 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 627 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 627 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 627 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 627 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 627 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 628 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 628 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 628 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 628 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 628 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 628 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 628 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 628 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 628 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 629 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 629 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 629 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 629 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 629 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 629 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 629 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 629 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 629 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 630 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 630 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 630 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 630 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 630 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 630 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 630 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 630 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 630 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 631 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 631 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 631 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 631 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 631 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 631 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 631 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 631 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 631 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 632, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 632 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 632 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 632 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 632 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 632 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 632 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 632 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 632 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 632 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 633 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 633 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 633 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 633 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 633 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 633 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 633 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 633 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 633 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 634 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 634 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 634 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 634 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 634 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 634 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 634 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 634 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 634 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 635 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 635 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 635 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 635 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 635 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 635 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 635 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 635 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 635 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 636 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 636 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 636 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 636 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 636 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 636 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 636 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 636 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 636 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 637 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 637 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 637 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 637 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 637 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 637 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 637 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 637 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 637 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 638 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 638 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 638 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 638 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 638 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 638 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 638 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 638 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 638 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 639 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 639 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 639 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 639 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 639 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 639 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 639 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 639 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 639 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 640, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 640 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 640 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 640 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 640 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 640 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 640 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 640 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 640 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 640 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 641 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 641 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 641 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 641 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 641 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 641 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 641 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 641 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 641 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 642 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 642 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 642 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 642 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 642 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 642 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 642 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 642 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 642 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 643 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 643 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 643 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 643 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 643 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 643 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 643 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 643 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 643 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 644 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 644 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 644 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 644 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 644 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 644 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 644 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 644 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 644 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 645 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 645 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 645 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 645 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 645 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 645 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 645 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 645 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 645 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 646 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 646 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 646 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 646 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 646 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 646 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 646 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 646 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 646 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 647 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 647 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 647 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 647 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 647 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 647 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 647 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 647 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 647 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 648, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 648 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 648 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 648 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 648 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 648 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 648 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 648 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 648 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 648 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 649 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 649 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 649 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 649 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 649 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 649 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 649 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 649 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 649 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 650 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 650 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 650 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 650 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 650 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 650 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 650 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 650 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 650 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 651 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 651 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 651 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 651 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 651 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 651 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 651 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 651 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 651 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 652 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 652 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 652 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 652 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 652 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 652 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 652 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 652 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 652 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 653 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 653 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 653 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 653 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 653 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 653 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 653 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 653 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 653 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 654 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 654 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 654 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 654 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 654 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 654 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 654 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 654 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 654 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 655 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 655 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 655 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 655 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 655 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 655 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 655 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 655 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 655 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 656, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 656 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 656 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 656 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 656 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 656 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 656 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 656 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 656 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 656 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 657 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 657 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 657 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 657 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 657 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 657 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 657 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 657 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 657 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 658 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 658 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 658 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 658 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 658 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 658 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 658 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 658 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 658 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 659 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 659 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 659 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 659 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 659 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 659 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 659 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 659 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 659 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 660 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 660 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 660 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 660 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 660 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 660 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 660 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 660 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 660 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 661 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 661 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 661 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 661 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 661 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 661 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 661 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 661 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 661 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 662 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 662 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 662 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 662 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 662 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 662 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 662 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 662 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 662 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 663 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 663 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 663 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 663 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 663 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 663 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 663 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 663 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 663 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 664, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 664 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 664 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 664 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 664 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 664 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 664 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 664 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 664 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 664 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 665 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 665 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 665 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 665 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 665 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 665 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 665 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 665 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 665 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 666 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 666 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 666 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 666 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 666 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 666 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 666 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 666 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 666 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 667 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 667 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 667 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 667 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 667 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 667 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 667 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 667 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 667 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 668 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 668 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 668 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 668 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 668 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 668 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 668 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 668 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 668 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 669 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 669 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 669 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 669 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 669 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 669 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 669 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 669 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 669 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 670 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 670 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 670 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 670 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 670 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 670 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 670 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 670 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 670 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 671 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 671 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 671 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 671 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 671 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 671 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 671 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 671 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 671 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 672, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 672 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 672 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 672 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 672 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 672 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 672 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 672 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 672 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 672 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 673 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 673 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 673 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 673 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 673 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 673 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 673 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 673 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 673 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 674 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 674 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 674 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 674 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 674 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 674 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 674 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 674 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 674 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 675 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 675 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 675 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 675 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 675 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 675 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 675 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 675 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 675 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 676 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 676 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 676 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 676 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 676 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 676 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 676 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 676 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 676 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 677 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 677 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 677 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 677 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 677 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 677 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 677 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 677 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 677 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 678 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 678 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 678 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 678 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 678 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 678 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 678 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 678 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 678 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 679 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 679 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 679 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 679 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 679 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 679 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 679 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 679 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 679 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 680, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 680 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 680 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 680 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 680 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 680 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 680 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 680 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 680 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 680 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 681 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 681 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 681 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 681 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 681 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 681 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 681 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 681 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 681 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 682 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 682 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 682 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 682 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 682 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 682 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 682 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 682 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 682 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 683 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 683 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 683 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 683 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 683 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 683 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 683 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 683 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 683 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 684 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 684 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 684 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 684 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 684 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 684 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 684 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 684 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 684 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 685 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 685 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 685 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 685 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 685 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 685 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 685 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 685 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 685 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 686 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 686 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 686 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 686 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 686 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 686 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 686 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 686 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 686 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 687 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 687 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 687 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 687 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 687 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 687 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 687 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 687 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 687 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 688, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 688 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 688 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 688 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 688 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 688 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 688 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 688 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 688 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 688 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 689 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 689 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 689 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 689 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 689 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 689 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 689 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 689 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 689 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 690 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 690 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 690 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 690 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 690 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 690 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 690 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 690 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 690 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 691 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 691 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 691 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 691 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 691 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 691 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 691 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 691 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 691 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 692 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 692 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 692 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 692 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 692 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 692 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 692 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 692 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 692 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 693 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 693 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 693 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 693 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 693 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 693 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 693 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 693 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 693 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 694 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 694 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 694 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 694 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 694 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 694 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 694 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 694 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 694 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 695 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 695 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 695 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 695 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 695 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 695 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 695 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 695 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 695 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 696, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 696 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 696 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 696 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 696 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 696 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 696 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 696 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 696 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 696 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 697 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 697 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 697 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 697 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 697 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 697 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 697 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 697 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 697 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 698 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 698 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 698 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 698 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 698 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 698 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 698 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 698 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 698 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 699 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 699 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 699 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 699 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 699 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 699 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 699 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 699 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 699 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 700 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 700 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 700 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 700 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 700 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 700 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 700 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 700 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 700 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 701 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 701 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 701 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 701 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 701 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 701 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 701 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 701 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 701 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 702 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 702 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 702 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 702 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 702 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 702 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 702 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 702 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 702 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 703 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 703 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 703 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 703 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 703 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 703 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 703 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 703 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 703 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 704, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 704 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 704 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 704 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 704 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 704 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 704 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 704 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 704 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 704 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 705 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 705 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 705 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 705 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 705 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 705 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 705 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 705 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 705 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 706 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 706 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 706 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 706 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 706 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 706 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 706 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 706 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 706 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 707 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 707 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 707 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 707 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 707 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 707 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 707 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 707 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 707 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 708 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 708 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 708 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 708 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 708 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 708 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 708 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 708 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 708 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 709 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 709 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 709 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 709 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 709 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 709 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 709 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 709 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 709 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 710 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 710 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 710 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 710 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 710 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 710 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 710 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 710 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 710 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 711 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 711 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 711 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 711 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 711 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 711 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 711 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 711 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 711 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 712, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 712 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 712 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 712 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 712 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 712 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 712 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 712 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 712 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 712 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 713 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 713 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 713 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 713 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 713 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 713 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 713 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 713 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 713 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 714 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 714 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 714 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 714 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 714 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 714 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 714 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 714 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 714 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 715 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 715 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 715 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 715 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 715 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 715 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 715 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 715 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 715 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 716 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 716 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 716 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 716 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 716 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 716 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 716 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 716 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 716 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 717 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 717 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 717 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 717 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 717 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 717 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 717 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 717 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 717 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 718 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 718 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 718 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 718 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 718 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 718 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 718 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 718 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 718 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 719 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 719 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 719 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 719 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 719 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 719 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 719 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 719 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 719 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 720, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 720 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 720 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 720 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 720 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 720 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 720 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 720 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 720 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 720 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 721 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 721 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 721 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 721 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 721 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 721 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 721 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 721 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 721 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 722 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 722 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 722 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 722 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 722 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 722 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 722 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 722 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 722 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 723 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 723 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 723 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 723 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 723 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 723 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 723 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 723 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 723 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 724 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 724 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 724 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 724 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 724 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 724 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 724 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 724 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 724 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 725 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 725 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 725 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 725 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 725 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 725 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 725 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 725 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 725 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 726 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 726 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 726 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 726 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 726 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 726 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 726 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 726 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 726 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 727 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 727 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 727 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 727 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 727 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 727 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 727 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 727 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 727 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 728, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 728 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 728 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 728 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 728 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 728 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 728 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 728 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 728 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 728 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 729 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 729 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 729 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 729 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 729 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 729 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 729 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 729 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 729 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 730 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 730 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 730 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 730 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 730 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 730 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 730 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 730 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 730 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 731 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 731 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 731 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 731 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 731 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 731 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 731 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 731 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 731 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 732 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 732 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 732 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 732 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 732 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 732 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 732 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 732 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 732 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 733 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 733 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 733 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 733 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 733 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 733 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 733 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 733 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 733 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 734 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 734 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 734 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 734 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 734 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 734 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 734 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 734 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 734 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 735 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 735 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 735 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 735 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 735 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 735 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 735 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 735 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 735 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 736, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 736 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 736 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 736 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 736 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 736 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 736 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 736 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 736 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 736 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 737 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 737 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 737 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 737 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 737 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 737 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 737 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 737 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 737 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 738 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 738 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 738 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 738 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 738 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 738 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 738 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 738 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 738 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 739 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 739 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 739 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 739 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 739 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 739 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 739 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 739 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 739 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 740 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 740 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 740 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 740 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 740 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 740 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 740 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 740 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 740 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 741 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 741 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 741 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 741 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 741 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 741 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 741 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 741 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 741 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 742 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 742 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 742 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 742 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 742 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 742 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 742 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 742 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 742 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 743 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 743 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 743 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 743 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 743 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 743 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 743 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 743 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 743 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 744, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 744 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 744 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 744 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 744 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 744 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 744 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 744 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 744 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 744 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 745 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 745 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 745 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 745 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 745 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 745 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 745 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 745 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 745 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 746 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 746 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 746 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 746 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 746 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 746 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 746 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 746 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 746 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 747 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 747 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 747 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 747 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 747 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 747 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 747 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 747 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 747 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 748 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 748 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 748 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 748 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 748 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 748 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 748 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 748 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 748 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 749 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 749 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 749 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 749 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 749 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 749 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 749 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 749 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 749 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 750 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 750 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 750 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 750 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 750 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 750 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 750 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 750 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 750 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 751 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 751 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 751 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 751 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 751 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 751 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 751 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 751 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 751 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 752, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 752 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 752 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 752 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 752 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 752 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 752 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 752 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 752 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 752 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 753 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 753 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 753 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 754 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 754 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 754 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 755 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 755 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 755 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 756 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 756 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 756 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 757 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 757 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 757 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 758 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 758 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 758 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 759 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 759 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 759 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 760, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 760 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 760 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 760 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 761 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 761 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 761 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 762 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 762 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 762 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 763 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 763 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 763 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 764 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 764 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 764 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 765 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 765 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 765 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 766 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 766 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 766 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 767 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 767 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 767 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 768, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 768 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 768 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 768 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 769 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 769 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 769 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 770 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 770 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 770 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 771 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 771 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 771 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 772 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 772 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 772 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 773 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 773 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 773 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 774 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 774 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 774 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 775 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 775 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 775 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 776, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 776 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 776 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 776 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 777 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 777 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 777 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 778 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 778 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 778 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 779 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 779 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 779 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 780 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 780 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 780 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 781 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 781 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 781 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 782 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 782 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 782 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 783 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 783 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 783 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 784, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 784 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 784 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 784 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 785 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 785 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 785 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 786 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 786 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 786 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 787 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 787 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 787 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 788 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 788 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 788 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 789 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 789 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 789 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 790 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 790 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 790 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 791 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 791 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 791 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 792, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 792 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 792 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 792 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 793 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 793 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 793 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 794 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 794 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 794 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 795 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 795 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 795 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 796 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 796 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 796 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 797 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 797 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 797 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 798 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 798 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 798 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 799 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 799 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 799 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 800, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 800 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 800 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 800 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 801 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 801 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 801 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 802 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 802 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 802 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 803 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 803 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 803 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 804 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 804 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 804 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 805 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 805 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 805 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 806 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 806 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 806 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 807 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 807 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 807 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 808, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 808 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 808 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 808 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 809 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 809 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 809 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 810 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 810 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 810 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 811 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 811 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 811 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 812 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 812 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 812 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 813 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 813 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 813 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 814 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 814 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 814 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 815 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 815 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 815 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 816, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 816 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 816 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 816 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 817 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 817 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 817 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 818 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 818 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 818 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 819 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 819 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 819 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 820 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 820 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 820 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 821 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 821 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 821 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 822 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 822 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 822 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 823 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 823 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 823 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 824, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 824 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 824 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 824 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 825 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 825 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 825 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 826 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 826 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 826 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 827 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 827 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 827 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 828 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 828 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 828 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 829 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 829 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 829 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 830 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 830 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 830 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 831 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 831 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 831 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 832, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 832 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 832 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 832 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 833 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 833 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 833 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 834 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 834 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 834 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 835 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 835 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 835 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 836 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 836 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 836 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 837 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 837 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 837 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 838 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 838 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 838 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 839 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 839 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 839 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 840, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 840 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 840 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 840 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 841 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 841 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 841 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 842 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 842 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 842 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 843 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 843 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 843 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 844 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 844 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 844 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 845 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 845 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 845 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 846 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 846 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 846 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 847 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 847 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 847 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 848, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 848 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 848 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 848 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 849 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 849 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 849 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 850 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 850 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 850 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 851 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 851 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 851 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 852 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 852 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 852 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 853 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 853 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 853 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 854 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 854 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 854 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 855 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 855 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 855 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 856, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 856 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 856 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 856 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 857 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 857 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 857 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 858 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 858 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 858 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 859 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 859 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 859 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 860 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 860 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 860 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 861 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 861 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 861 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 862 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 862 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 862 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 863 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 863 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 863 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 864, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 864 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 864 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 864 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 865 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 865 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 865 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 866 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 866 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 866 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 867 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 867 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 867 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 868 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 868 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 868 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 869 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 869 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 869 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 870 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 870 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 870 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 871 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 871 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 871 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 872, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 872 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 872 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 872 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 873 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 873 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 873 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 874 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 874 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 874 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 875 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 875 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 875 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 876 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 876 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 876 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 877 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 877 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 877 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 878 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 878 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 878 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 879 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 879 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 879 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 880, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 880 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 880 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 880 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 881 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 881 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 881 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 882 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 882 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 882 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 883 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 883 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 883 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 884 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 884 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 884 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 885 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 885 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 885 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 886 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 886 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 886 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 887 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 887 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 887 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 888, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 888 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 888 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 888 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 889 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 889 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 889 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 890 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 890 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 890 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 891 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 891 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 891 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 892 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 892 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 892 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 893 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 893 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 893 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 894 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 894 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 894 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 895 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 895 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 895 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 896, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 896 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 896 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 896 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 897 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 897 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 897 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 898 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 898 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 898 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 899 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 899 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 899 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 900 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 900 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 900 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 901 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 901 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 901 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 902 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 902 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 902 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 903 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 903 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 903 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 904, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 904 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 904 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 904 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 905 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 905 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 905 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 906 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 906 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 906 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 907 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 907 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 907 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 908 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 908 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 908 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 909 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 909 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 909 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 910 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 910 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 910 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 911 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 911 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 911 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 912, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 912 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 912 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 912 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 913 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 913 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 913 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 914 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 914 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 914 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 915 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 915 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 915 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 916 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 916 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 916 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 917 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 917 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 917 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 918 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 918 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 918 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 919 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 919 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 919 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 920, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 920 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 920 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 920 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 921 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 921 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 921 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 922 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 922 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 922 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 923 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 923 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 923 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 924 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 924 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 924 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 925 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 925 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 925 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 926 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 926 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 926 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 927 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 927 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 927 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 928, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 928 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 928 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 928 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 929 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 929 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 929 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 930 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 930 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 930 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 931 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 931 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 931 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 932 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 932 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 932 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 933 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 933 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 933 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 934 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 934 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 934 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 935 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 935 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 935 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 936, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 936 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 936 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 936 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 937 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 937 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 937 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 938 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 938 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 938 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 939 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 939 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 939 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 940 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 940 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 940 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 941 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 941 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 941 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 942 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 942 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 942 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 943 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 943 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 943 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 944, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 944 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 944 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 944 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 945 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 945 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 945 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 946 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 946 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 946 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 947 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 947 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 947 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 948 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 948 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 948 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 949 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 949 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 949 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 950 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 950 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 950 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 951 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 951 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 951 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 952, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 952 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 952 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 952 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 953 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 953 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 953 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 954 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 954 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 954 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 955 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 955 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 955 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 956 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 956 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 956 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 957 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 957 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 957 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 958 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 958 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 958 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 959 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 959 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 959 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 960, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 960 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 960 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 960 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 961 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 961 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 961 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 962 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 962 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 962 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 963 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 963 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 963 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 964 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 964 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 964 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 965 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 965 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 965 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 966 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 966 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 966 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 967 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 967 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 967 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 968, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 968 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 968 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 968 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 969 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 969 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 969 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 970 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 970 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 970 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 971 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 971 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 971 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 972 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 972 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 972 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 973 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 973 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 973 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 974 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 974 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 974 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 975 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 975 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 975 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 976, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 976 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 976 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 976 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 977 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 977 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 977 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 978 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 978 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 978 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 979 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 979 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 979 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 980 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 980 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 980 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 981 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 981 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 981 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 982 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 982 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 982 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 983 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 983 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 983 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 984, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 984 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 984 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 984 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 985 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 985 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 985 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 986 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 986 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 986 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 987 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 987 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 987 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 988 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 988 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 988 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 989 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 989 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 989 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 990 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 990 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 990 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 991 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 991 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 991 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 992, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 992 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 992 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 992 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 993 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 993 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 993 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 994 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 994 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 994 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 995 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 995 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 995 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 996 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 996 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 996 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 997 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 997 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 997 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 998 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 998 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 998 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 999 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 999 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 999 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 1000, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1000 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1000 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1000 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1001 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1001 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1001 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1002 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1002 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1002 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1003 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1003 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1003 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1004 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1004 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1004 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1005 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1005 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1005 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1006 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1006 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1006 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1007 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1007 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1007 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 1008, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1008 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1008 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1008 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1009 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1009 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1009 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1010 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1010 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1010 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1011 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1011 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1011 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1012 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1012 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1012 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1013 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1013 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1013 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1014 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1014 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1014 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1015 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1015 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1015 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 1016, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1016 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1016 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1016 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1017 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1017 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1017 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1018 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1018 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1018 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1019 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1019 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1019 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1020 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1020 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1020 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1021 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1021 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1021 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1022 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1022 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1022 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1023 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 1023 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 1023 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 0, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 0 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 0 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 0 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 0 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 1 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 1 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 1 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 2 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 2 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 2 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 3 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 3 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 3 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 4 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 4 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 4 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 5 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 5 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 5 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 6 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 6 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 6 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 7 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 7 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 7 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 8, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 8 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 8 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 8 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 8 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 9 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 9 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 9 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 10 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 10 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 10 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 11 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 11 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 11 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 12 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 12 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 12 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 13 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 13 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 13 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 14 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 14 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 14 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 15 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 15 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 15 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 16, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 16 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 16 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 16 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 16 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 17 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 17 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 17 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 18 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 18 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 18 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 19 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 19 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 19 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 20 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 20 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 20 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 21 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 21 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 21 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 22 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 22 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 22 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 23 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 23 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 23 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 24, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 24 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 24 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 24 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 24 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 25 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 25 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 25 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 26 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 26 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 26 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 27 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 27 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 27 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 28 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 28 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 28 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 29 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 29 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 29 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 30 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 30 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 30 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 31 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 31 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 31 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 32, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 32 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 32 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 32 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 32 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 33 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 33 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 33 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 34 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 34 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 34 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 35 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 35 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 35 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 36 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 36 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 36 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 37 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 37 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 37 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 38 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 38 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 38 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 39 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 39 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 39 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 40, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 40 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 40 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 40 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 40 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 41 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 41 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 41 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 42 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 42 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 42 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 43 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 43 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 43 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 44 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 44 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 44 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 45 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 45 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 45 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 46 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 46 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 46 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 47 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 47 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 47 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 48, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 48 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 48 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 48 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 48 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 49 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 49 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 49 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 50 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 50 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 50 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 51 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 51 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 51 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 52 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 52 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 52 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 53 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 53 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 53 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 54 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 54 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 54 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 55 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 55 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 55 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 56, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 56 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 56 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 56 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 56 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 57 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 57 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 57 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 58 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 58 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 58 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 59 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 59 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 59 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 60 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 60 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 60 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 61 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 61 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 61 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 62 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 62 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 62 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 63 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 63 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 63 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 64, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 64 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 64 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 64 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 64 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 65 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 65 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 65 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 66 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 66 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 66 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 67 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 67 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 67 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 68 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 68 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 68 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 69 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 69 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 69 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 70 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 70 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 70 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 71 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 71 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 71 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 72, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] [gNB 0] Frame 72 : MIB->BCH CC_id 0, Received 3 bytes +[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 72 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 72 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 72 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 73 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 73 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 73 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 74 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 74 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 74 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 75 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 75 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 75 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 76 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 76 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 76 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 77 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 77 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 77 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 78 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 78 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 78 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 79 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 79 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 79 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 80, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 80 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 80 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 80 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 81 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 81 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 81 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 82 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 82 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 82 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 83 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 83 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 83 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 84 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 84 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 84 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 85 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 85 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 85 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 86 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 86 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 86 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 87 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 87 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 87 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 88, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 88 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 88 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 88 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 89 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 89 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 89 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 90 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 90 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 90 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 91 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 91 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 91 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 92 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 92 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 92 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 93 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 93 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 93 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 94 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 94 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 94 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 95 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 95 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 95 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 96, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 96 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 96 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 96 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 97 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 97 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 97 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 98 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 98 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 98 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 99 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 99 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 99 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 100 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 100 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 100 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 101 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 101 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 101 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 102 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 102 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 102 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 103 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 103 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 103 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 104, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 104 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 104 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 104 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 105 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 105 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 105 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 106 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 106 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 106 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 107 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 107 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 107 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 108 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 108 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 108 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 109 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 109 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 109 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 110 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 110 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 110 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 111 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 111 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 111 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 112, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 112 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 112 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 112 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 113 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 113 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 113 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 114 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 114 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 114 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 115 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 115 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 115 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 116 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 116 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 116 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 117 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 117 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 117 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 118 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 118 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 118 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 119 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 119 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 119 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 120, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 120 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 120 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 120 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 121 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 121 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 121 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 122 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 122 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 122 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 123 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 123 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 123 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 124 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 124 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 124 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 125 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 125 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 125 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 126 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 126 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 126 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 127 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 127 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 127 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 128, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 128 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 128 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 128 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 129 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 129 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 129 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 130 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 130 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 130 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 131 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 131 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 131 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 132 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 132 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 132 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 133 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 133 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 133 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 134 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 134 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 134 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 135 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 135 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 135 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 136, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 136 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 136 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 136 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 137 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 137 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 137 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 138 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 138 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 138 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 139 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 139 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 139 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 140 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 140 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 140 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 141 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 141 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 141 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 142 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 142 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 142 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 143 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 143 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 143 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 144, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 144 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 144 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 144 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 145 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 145 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 145 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 146 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 146 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 146 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 147 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 147 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 147 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 148 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 148 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 148 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 149 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 149 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 149 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 150 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 150 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 150 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 151 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 151 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 151 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 152, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 152 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 152 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 152 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 153 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 153 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 153 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 154 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 154 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 154 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 155 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 155 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 155 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 156 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 156 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 156 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 157 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 157 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 157 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 158 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 158 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 158 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 159 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 159 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 159 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 160, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 160 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 160 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 160 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 161 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 161 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 161 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 162 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 162 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 162 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 163 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 163 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 163 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 164 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 164 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 164 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 165 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 165 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 165 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 166 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 166 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 166 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 167 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 167 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 167 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 168, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 168 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 168 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 168 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 169 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 169 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 169 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 170 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 170 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 170 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 171 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 171 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 171 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 172 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 172 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 172 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 173 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 173 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 173 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 174 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 174 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 174 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 175 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 175 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 175 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 176, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 176 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 176 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 176 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 177 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 177 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 177 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 178 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 178 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 178 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 179 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 179 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 179 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 180 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 180 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 180 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 181 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 181 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 181 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 182 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 182 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 182 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 183 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 183 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 183 slot 9 +PUCCH 0 : maxpos 2 +[MAC] Frame 184, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 184 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 184 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 184 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 185 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 185 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 185 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 186 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 186 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 186 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 187 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 187 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 187 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 188 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 188 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 188 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 189 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 189 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 189 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 190 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 190 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 190 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 191 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 191 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 191 slot 9 +PUCCH 0 : maxpos 1 +[MAC] Frame 192, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 192 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 192 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 192 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 193 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 193 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 193 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 194 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 194 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 194 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 195 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 195 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 195 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 196 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 196 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 196 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 197 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 197 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 197 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 198 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 198 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 198 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 199 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 199 slot 8 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 199 slot 9 +PUCCH 0 : maxpos 0 +[MAC] Frame 200, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 200 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 200 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 200 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 201 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 201 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 201 slot 9 +PUCCH 0 : maxpos 1 +[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 202 slot 7 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 202 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 202 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 203 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 203 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 203 slot 9 +PUCCH 0 : maxpos 3 +[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 204 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 204 slot 8 +PUCCH 0 : maxpos 0 +[MAC] Scheduling pucch reception for frame 204 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 205 slot 7 +PUCCH 0 : maxpos 3 +[MAC] Scheduling pucch reception for frame 205 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 205 slot 9 +PUCCH 0 : maxpos 2 +[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 206 slot 7 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 206 slot 8 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 206 slot 9 +PUCCH 0 : maxpos 0 +[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 2 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 3 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 4 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 5 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 6 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[MAC] Scheduling pucch reception for frame 207 slot 7 +PUCCH 0 : maxpos 1 +[MAC] Scheduling pucch reception for frame 207 slot 8 +PUCCH 0 : maxpos 2 +[MAC] Scheduling pucch reception for frame 207 slot 9 +PUCCH 0 : maxpos 3 +[MAC] Frame 208, slot 0: Adding BCH PDU in position 0 (length 3) +[MAC] In nr_schedule_uss_dlsch_phytest frame 208 slot 1 +[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1 +[SCTP] Found data for descriptor 87 +[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433 +[SCTP] Received notification for sd 87, type 32773 +here comes the tree (instance 0): +--------------------------------------------- +----------------------- +eNB id 3585 (null) +state 1 +nextstream 0 +in_streams 32 out_streams 32 +cnx_id 1 assoc_id 136 +--------------------------------------------- +[X2AP] x2ap_enb_data_p not NULL and sctp state not SCTP_STATE_ESTABLISHED, what to do? +Linux signal Aborted... +/home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/executables/softmodem-common.c:187 signal_handler() Exiting OAI softmodem: softmodem starting exit procedure + +Exiting ru_thread From e7ab8f83c6b657cbf4da245a66b6cb5673581628 Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Mon, 29 Jun 2020 13:57:23 +0200 Subject: [PATCH 396/553] Update TESTING_GNB_W_COTS_UE.md --- doc/TESTING_GNB_W_COTS_UE.md | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/doc/TESTING_GNB_W_COTS_UE.md b/doc/TESTING_GNB_W_COTS_UE.md index bcec2179f4..aeb2ad6630 100644 --- a/doc/TESTING_GNB_W_COTS_UE.md +++ b/doc/TESTING_GNB_W_COTS_UE.md @@ -72,6 +72,10 @@ These config files are passed as arguments of the run command line, using the op Some config examples can be found in the following folder: https://gitlab.eurecom.fr/oai/openairinterface5g/-/tree/develop/targets/PROJECTS/GENERIC-LTE-EPC/CONF +Also base config files can be found here: +[enb conf file](https://gitlab.eurecom.fr/oai/openairinterface5g/-/blob/rh_doc_update_3/doc/testing_gnb_w_cots_ue_resources/enb.conf) +[gnb conf file](https://gitlab.eurecom.fr/oai/openairinterface5g/-/blob/rh_doc_update_3/doc/testing_gnb_w_cots_ue_resources/gnb.conf) + TO DO : attach base confif files These files have to be updated manually to set the IP addresses and frequency. @@ -236,7 +240,10 @@ The test reaches step **12. E-RAB modifcation confirmation** , eventhough not al ## Log file monitoring -From the log file that is generated, we can monitor several important steps, to assess that the test was successful: +From the log file that is generated, we can monitor several important steps, to assess that the test was successful. +Log files examples can be found here: +[enb log file](https://gitlab.eurecom.fr/oai/openairinterface5g/-/blob/rh_doc_update_3/doc/testing_gnb_w_cots_ue_resources/oai_enb.log) +[gnb log file](https://gitlab.eurecom.fr/oai/openairinterface5g/-/blob/rh_doc_update_3/doc/testing_gnb_w_cots_ue_resources/oai_gnb.log) - eNB receives UE capabilities information, including its NR capabilites, and triggers sGNB Addition Request message: From 099169831e14a01f81448a04d2fef3129db80714 Mon Sep 17 00:00:00 2001 From: WANG Tsu-Han Date: Mon, 29 Jun 2020 16:23:10 +0200 Subject: [PATCH 397/553] adding parameter in nr uesoftmodem for usrp trx thread --- executables/nr-uesoftmodem.c | 1 + 1 file changed, 1 insertion(+) diff --git a/executables/nr-uesoftmodem.c b/executables/nr-uesoftmodem.c index b96f98e1f2..68308085a9 100644 --- a/executables/nr-uesoftmodem.c +++ b/executables/nr-uesoftmodem.c @@ -173,6 +173,7 @@ uint64_t num_missed_slots=0; // counter for the number of missed slots int transmission_mode=1; int numerology = 0; +int usrp_tx_thread = 0; /* flag set by eNB conf file to specify if the radio head is local or remote (default option is local) */ //uint8_t local_remote_radio = BBU_LOCAL_RADIO_HEAD; From 0516a452c1e1a92be26c64a1c3905da68594fd80 Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Tue, 30 Jun 2020 12:37:00 +0200 Subject: [PATCH 398/553] BUILD: explicitely stop build when compilation/linking issues Signed-off-by: Raphael Defosseux --- cmake_targets/build_oai | 1 + cmake_targets/tools/build_helper | 24 ++++++++++++++++++++++-- 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/cmake_targets/build_oai b/cmake_targets/build_oai index 91f33ea625..88b8811575 100755 --- a/cmake_targets/build_oai +++ b/cmake_targets/build_oai @@ -959,6 +959,7 @@ function main() { wait else echo_info "10. Bypassing the Tests ..." + echo_success "BUILD SHOULD BE SUCCESSFUL" fi } diff --git a/cmake_targets/tools/build_helper b/cmake_targets/tools/build_helper index 5a59b9a8cc..b8f0125b10 100755 --- a/cmake_targets/tools/build_helper +++ b/cmake_targets/tools/build_helper @@ -175,8 +175,21 @@ check_warnings() { fi } +#check_errors: +# print error message if the compilation had errors +#argument: +# $1: log file +check_errors() { + #we look for 'warning:' in the compilation log file + error_count=`grep "error:" "$1" | wc -l` + if [ $error_count -gt 0 ]; then + echo_error "ERROR: $error_count error. See $1" + fi +} + compilations() { cd $OPENAIR_DIR/cmake_targets/$1/build + echo_info "Log file for compilation is being written to: $dlog/$2.$REL.txt" set +e { if [ "$BUILD_COVERITY_SCAN" == "1" ]; then @@ -193,15 +206,22 @@ compilations() { $COV_SCAN_PREFIX make -j`nproc` $2 fi fi - + ret=$? } > $dlog/$2.$REL.txt 2>&1 set -e - echo_info "Log file for compilation has been written to: $dlog/$2.$REL.txt" + if [[ $ret -ne 0 ]]; then + check_warnings "$dlog/$2.$REL.txt" + check_errors "$dlog/$2.$REL.txt" + echo_error "$2 compilation failed" + exit 1 + fi if [ -s $3 ] ; then cp $3 $4 echo_success "$2 compiled" check_warnings "$dlog/$2.$REL.txt" else + check_warnings "$dlog/$2.$REL.txt" + check_errors "$dlog/$2.$REL.txt" echo_error "$2 compilation failed" exit 1 fi From 56f8827bde397c0318f10eb6749b4c1d0ca4efd5 Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Tue, 30 Jun 2020 14:42:22 +0200 Subject: [PATCH 399/553] Update TESTING_GNB_W_COTS_UE.md --- doc/TESTING_GNB_W_COTS_UE.md | 35 ++++++++++++++++++++++------------- 1 file changed, 22 insertions(+), 13 deletions(-) diff --git a/doc/TESTING_GNB_W_COTS_UE.md b/doc/TESTING_GNB_W_COTS_UE.md index aeb2ad6630..e507050239 100644 --- a/doc/TESTING_GNB_W_COTS_UE.md +++ b/doc/TESTING_GNB_W_COTS_UE.md @@ -42,9 +42,30 @@ The photo depicts the FR1 setup part of the scheme above: ## Build and Install -General guidelines for building : +General guidelines to build eNB and gNB : See https://gitlab.eurecom.fr/oai/openairinterface5g/blob/develop/doc/BUILD.md#building-ues-enodeb-and-gnodeb-executables + +- **eNB** + +``` +cd /openairinterface5g/ +source oaienv +cd cmake_targets/ +./build_oai -I -w USRP --eNB + +``` + +- **gNB** + +``` +cd /openairinterface5g/ +source oaienv +cd cmake_targets/ +./build_oai -I -w USRP --gNB +``` + + - **EPC** for reference: @@ -52,18 +73,6 @@ https://github.com/OPENAIRINTERFACE/openair-epc-fed/blob/master-documentation/do -- **eNB** - -``` -sudo -``` - -- **gNB** - -``` -sudo -``` - ## Configuration Files Each component (EPC, eNB, gNB) has its own configuration file. From b5cce24e83cad1832d3521972911f41f13cdbb82 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Tue, 30 Jun 2020 15:07:43 +0200 Subject: [PATCH 400/553] fixed rv in phy-test mode --- openair2/NR_PHY_INTERFACE/NR_IF_Module.c | 55 +++++++++++++----------- 1 file changed, 29 insertions(+), 26 deletions(-) diff --git a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c index 2b8dc0ec02..ec969c6741 100644 --- a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c @@ -38,6 +38,7 @@ #include "LAYER2/MAC/mac_proto.h" #include "LAYER2/NR_MAC_gNB/mac_proto.h" #include "common/ran_context.h" +#include "executables/softmodem-common.h" #define MAX_IF_MODULES 100 @@ -87,34 +88,36 @@ void handle_nr_uci(NR_UL_IND_t *UL_info, NR_UE_sched_ctrl_t *sched_ctrl) { case NFAPI_NR_UCI_PDCCH_PDU_TYPE: break; case NFAPI_NR_UCI_FORMAT_0_1_PDU_TYPE: { - nfapi_nr_uci_pucch_pdu_format_0_1_t *uci_pdu = &uci_list[i].pucch_pdu_format_0_1; - // handle harq - int harq_idx_s = 0; - // iterate over received harq bits - for (int harq_bit = 0; harq_bit < uci_pdu->harq->num_harq; harq_bit++) { - // search for the right harq process - for (int harq_idx = harq_idx_s; harq_idx < NR_MAX_NB_HARQ_PROCESSES-1; harq_idx++) { - if ((UL_info->slot-1) == sched_ctrl->harq_processes[harq_idx].feedback_slot) { - if (uci_pdu->harq->harq_list[harq_bit].harq_value == 0) + if (get_softmodem_params()->phy_test == 0) { + nfapi_nr_uci_pucch_pdu_format_0_1_t *uci_pdu = &uci_list[i].pucch_pdu_format_0_1; + // handle harq + int harq_idx_s = 0; + // iterate over received harq bits + for (int harq_bit = 0; harq_bit < uci_pdu->harq->num_harq; harq_bit++) { + // search for the right harq process + for (int harq_idx = harq_idx_s; harq_idx < NR_MAX_NB_HARQ_PROCESSES-1; harq_idx++) { + if ((UL_info->slot-1) == sched_ctrl->harq_processes[harq_idx].feedback_slot) { + if (uci_pdu->harq->harq_list[harq_bit].harq_value == 0) + sched_ctrl->harq_processes[harq_idx].round++; + if ((uci_pdu->harq->harq_list[harq_bit].harq_value == 1) || + (sched_ctrl->harq_processes[harq_idx].round == max_harq_rounds)) { + sched_ctrl->harq_processes[harq_idx].ndi ^= 1; + sched_ctrl->harq_processes[harq_idx].round = 0; + } + sched_ctrl->harq_processes[harq_idx].is_waiting = 0; + harq_idx_s = harq_idx + 1; + break; + } + // if gNB fails to receive a ACK/NACK + else if (((UL_info->slot-1) > sched_ctrl->harq_processes[harq_idx].feedback_slot) && + (sched_ctrl->harq_processes[harq_idx].is_waiting)) { sched_ctrl->harq_processes[harq_idx].round++; - if ((uci_pdu->harq->harq_list[harq_bit].harq_value == 1) || - (sched_ctrl->harq_processes[harq_idx].round == max_harq_rounds)) { - sched_ctrl->harq_processes[harq_idx].ndi ^= 1; - sched_ctrl->harq_processes[harq_idx].round = 0; + if (sched_ctrl->harq_processes[harq_idx].round == max_harq_rounds) { + sched_ctrl->harq_processes[harq_idx].ndi ^= 1; + sched_ctrl->harq_processes[harq_idx].round = 0; + } + sched_ctrl->harq_processes[harq_idx].is_waiting = 0; } - sched_ctrl->harq_processes[harq_idx].is_waiting = 0; - harq_idx_s = harq_idx + 1; - break; - } - // if gNB fails to receive a ACK/NACK - else if (((UL_info->slot-1) > sched_ctrl->harq_processes[harq_idx].feedback_slot) && - (sched_ctrl->harq_processes[harq_idx].is_waiting)) { - sched_ctrl->harq_processes[harq_idx].round++; - if (sched_ctrl->harq_processes[harq_idx].round == max_harq_rounds) { - sched_ctrl->harq_processes[harq_idx].ndi ^= 1; - sched_ctrl->harq_processes[harq_idx].round = 0; - } - sched_ctrl->harq_processes[harq_idx].is_waiting = 0; } } } From 7ddfa636f81c676ada7480b7ca099a7e9778a53b Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Fri, 12 Jun 2020 19:30:17 +0200 Subject: [PATCH 401/553] Add detection of NR scgFailureInformation message at rrc eNB --- openair2/RRC/LTE/rrc_eNB.c | 59 ++++++++++++++++++++++++-------------- 1 file changed, 38 insertions(+), 21 deletions(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index 2fed550d35..7e8eaaae65 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -8084,29 +8084,46 @@ rrc_eNB_decode_dcch( break; case LTE_UL_DCCH_MessageType__messageClassExtension_PR_c2: //SidelinkUEInformation - //case UL_DCCH_MessageType__messageClassExtension__c2_PR_sidelinkUEInformation_r12: //SidelinkUEInformation - LOG_I(RRC,"THINH [LTE_UL_DCCH_MessageType__messageClassExtension_PR_c2]\n"); - LOG_DUMPMSG(RRC,DEBUG_RRC,(char *)Rx_sdu,sdu_sizeP, + if(ul_dcch_msg->message.choice.messageClassExtension.choice.c2.present == + LTE_UL_DCCH_MessageType__messageClassExtension__c2_PR_scgFailureInformationNR_r15){ + if (ul_dcch_msg->message.choice.messageClassExtension.choice.c2.choice.scgFailureInformationNR_r15. + criticalExtensions.present == LTE_SCGFailureInformationNR_r15__criticalExtensions_PR_c1){ + if (ul_dcch_msg->message.choice.messageClassExtension.choice.c2.choice.scgFailureInformationNR_r15.criticalExtensions. + choice.c1.present == LTE_SCGFailureInformationNR_r15__criticalExtensions__c1_PR_scgFailureInformationNR_r15){ + if (ul_dcch_msg->message.choice.messageClassExtension.choice.c2.choice.scgFailureInformationNR_r15.criticalExtensions. + choice.c1.choice.scgFailureInformationNR_r15.failureReportSCG_NR_r15!=NULL) { + LOG_E(RRC, "Received NR scgFailureInformation from UE, failure type: %ld \n", + ul_dcch_msg->message.choice.messageClassExtension.choice.c2.choice.scgFailureInformationNR_r15.criticalExtensions. + choice.c1.choice.scgFailureInformationNR_r15.failureReportSCG_NR_r15->failureType_r15); + } + } + } + } + else if(ul_dcch_msg->message.choice.messageClassExtension.choice.c2.present == LTE_UL_DCCH_MessageType__messageClassExtension__c2_PR_sidelinkUEInformation_r12){ + //case UL_DCCH_MessageType__messageClassExtension__c2_PR_sidelinkUEInformation_r12: //SidelinkUEInformation + LOG_I(RRC,"THINH [LTE_UL_DCCH_MessageType__messageClassExtension_PR_c2]\n"); + LOG_DUMPMSG(RRC,DEBUG_RRC,(char *)Rx_sdu,sdu_sizeP, "[MSG] RRC SidelinkUEInformation \n"); - MSC_LOG_RX_MESSAGE( - MSC_RRC_ENB, - MSC_RRC_UE, - Rx_sdu, - sdu_sizeP, - MSC_AS_TIME_FMT" SidelinkUEInformation UE %x size %u", - MSC_AS_TIME_ARGS(ctxt_pP), - ue_context_p->ue_context.rnti, - sdu_sizeP); - LOG_I(RRC, - PROTOCOL_RRC_CTXT_UE_FMT" RLC RB %02d --- RLC_DATA_IND %d bytes " - "(SidelinkUEInformation) ---> RRC_eNB\n", - PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP), - DCCH, + MSC_LOG_RX_MESSAGE( + MSC_RRC_ENB, + MSC_RRC_UE, + Rx_sdu, + sdu_sizeP, + MSC_AS_TIME_FMT" SidelinkUEInformation UE %x size %u", + MSC_AS_TIME_ARGS(ctxt_pP), + ue_context_p->ue_context.rnti, sdu_sizeP); - rrc_eNB_process_SidelinkUEInformation( - ctxt_pP, - ue_context_p, - &ul_dcch_msg->message.choice.messageClassExtension.choice.c2.choice.sidelinkUEInformation_r12); + LOG_I(RRC, + PROTOCOL_RRC_CTXT_UE_FMT" RLC RB %02d --- RLC_DATA_IND %d bytes " + "(SidelinkUEInformation) ---> RRC_eNB\n", + PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP), + DCCH, + sdu_sizeP); + rrc_eNB_process_SidelinkUEInformation( + ctxt_pP, + ue_context_p, + &ul_dcch_msg->message.choice.messageClassExtension.choice.c2.choice.sidelinkUEInformation_r12); + } break; default: From c301b62d8ac2c362ea71b08b820e3f296f7b8a5b Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Fri, 19 Jun 2020 14:00:34 +0200 Subject: [PATCH 402/553] Add printing contents of NR scgFailureInformation message at rrc eNB --- openair2/RRC/LTE/rrc_eNB.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index 7e8eaaae65..ff36f24872 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -8077,7 +8077,7 @@ rrc_eNB_decode_dcch( return 0; //TTN for D2D } else if (ul_dcch_msg->message.present == LTE_UL_DCCH_MessageType_PR_messageClassExtension) { - LOG_I(RRC, "THINH [LTE_UL_DCCH_MessageType_PR_messageClassExtension]\n"); + LOG_I(RRC, "[LTE_UL_DCCH_MessageType_PR_messageClassExtension]\n"); switch (ul_dcch_msg->message.choice.messageClassExtension.present) { case LTE_UL_DCCH_MessageType__messageClassExtension_PR_NOTHING: /* No components present */ @@ -8095,6 +8095,7 @@ rrc_eNB_decode_dcch( LOG_E(RRC, "Received NR scgFailureInformation from UE, failure type: %ld \n", ul_dcch_msg->message.choice.messageClassExtension.choice.c2.choice.scgFailureInformationNR_r15.criticalExtensions. choice.c1.choice.scgFailureInformationNR_r15.failureReportSCG_NR_r15->failureType_r15); + xer_fprint(stdout, &asn_DEF_LTE_UL_DCCH_Message, (void *)ul_dcch_msg); } } } From a40f119a808ad6d2782ed69fb3de6b5c6c47a6d1 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Tue, 30 Jun 2020 18:04:32 +0200 Subject: [PATCH 403/553] revert to dl only in slot 1 before merge --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index f30f4ee29d..37dcbcd98a 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -401,7 +401,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, // hardcoding dlsch to be in slot 1 if (!(slot_txP%num_slots_per_tdd)) { if(slot_txP==0) - *dlsch_in_slot_bitmap = 0x7e; + *dlsch_in_slot_bitmap = 0x02; else *dlsch_in_slot_bitmap = 0x00; } From 6edff47db2f414a05dccafe7983d33cd82ad6c11 Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Tue, 30 Jun 2020 17:24:20 +0200 Subject: [PATCH 404/553] CI: fix cppcheck error Signed-off-by: Raphael Defosseux --- openair2/RRC/LTE/rrc_eNB.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index cfafd28983..08c322f9b8 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -4490,7 +4490,7 @@ static int encode_CG_ConfigInfo( ue_cap_rat_container_list = calloc(1,sizeof(LTE_UE_CapabilityRAT_ContainerList_t)); ue_cap_rat_container_list->list.count = RAT_Container_count; - ue_cap_rat_container_list->list.size = sizeof(RAT_Container_count * sizeof(LTE_UE_CapabilityRAT_Container_t)); + ue_cap_rat_container_list->list.size = RAT_Container_count * sizeof(LTE_UE_CapabilityRAT_Container_t); ue_cap_rat_container_list->list.array = calloc(RAT_Container_count,sizeof(LTE_UE_CapabilityRAT_Container_t *)); if(ue_context_pP->ue_context.UE_Capability_MRDC) { From c5fdcd85cc936677e65daa378c11b6b35a8cb0cf Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Sat, 11 Apr 2020 15:42:13 +0200 Subject: [PATCH 405/553] Bugfix FlexRAN: if a UE is in RRC but not S1AP, treat as no bug --- openair2/ENB_APP/flexran_agent_ran_api.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair2/ENB_APP/flexran_agent_ran_api.c b/openair2/ENB_APP/flexran_agent_ran_api.c index 32cb8c74e1..abade20846 100644 --- a/openair2/ENB_APP/flexran_agent_ran_api.c +++ b/openair2/ENB_APP/flexran_agent_ran_api.c @@ -3644,7 +3644,7 @@ int flexran_get_s1ap_ue(mid_t mod_id, rnti_t rnti, Protocol__FlexS1apUe * ue_con RB_FOREACH(ue, s1ap_ue_map, &s1ap->s1ap_ue_head){ if (ue->eNB_ue_s1ap_id == enb_ue_s1ap_id) break; } - if (ue == NULL) return -1; + if (!ue) return 0; // UE does not exist: it might be connected but CN did not answer if (ue->mme_ref->mme_s1_ip.ipv4) ue_conf->mme_s1_ip = (char*) &ue->mme_ref->mme_s1_ip.ipv4_address[0]; From 9072101a1a9c802de3334aa4e020417b6849b9ae Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Wed, 15 Apr 2020 21:25:42 +0200 Subject: [PATCH 406/553] Correctly decode IMSI also when not integrity protected --- openair2/RRC/LTE/rrc_eNB_S1AP.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/openair2/RRC/LTE/rrc_eNB_S1AP.c b/openair2/RRC/LTE/rrc_eNB_S1AP.c index 27a442ed05..9f92be366b 100644 --- a/openair2/RRC/LTE/rrc_eNB_S1AP.c +++ b/openair2/RRC/LTE/rrc_eNB_S1AP.c @@ -96,36 +96,34 @@ void extract_imsi(uint8_t *pdu_buf, uint32_t pdu_len, rrc_eNB_ue_context_t *ue_c && pdu_len > NAS_MESSAGE_SECURITY_HEADER_SIZE)) return; + /* Decode plain NAS message */ + EMM_msg *e_msg = &nas_msg.plain.emm; + emm_msg_header_t *emm_header = &e_msg->header; + if (header->security_header_type != SECURITY_HEADER_TYPE_NOT_PROTECTED) { /* Decode the message authentication code */ DECODE_U32((char *) pdu_buf+size, header->message_authentication_code, size); /* Decode the sequence number */ DECODE_U8((char *) pdu_buf+size, header->sequence_number, size); - } + /* Decode the security header type and the protocol discriminator */ + DECODE_U8(pdu_buf + size, *(uint8_t *)(emm_header), size); - /* Note: the value of the pointer (i.e. the address) is given by value, so we - * can modify it as we want. The callee retains the original address! */ + /* Check that this is the right message */ + if (emm_header->protocol_discriminator != EPS_MOBILITY_MANAGEMENT_MESSAGE) + return; + } pdu_buf += size; pdu_len -= size; - /* Decode plain NAS message */ - EMM_msg *e_msg = &nas_msg.plain.emm; - emm_msg_header_t *emm_header = &e_msg->header; - /* First decode the EMM message header */ - int e_head_size = 0; /* Check that buffer contains more than only the header */ if (pdu_len <= sizeof(emm_msg_header_t)) return; - /* Decode the security header type and the protocol discriminator */ - DECODE_U8(pdu_buf + e_head_size, *(uint8_t *)(emm_header), e_head_size); + /* First decode the EMM message header */ + int e_head_size = 0; /* Decode the message type */ DECODE_U8(pdu_buf + e_head_size, emm_header->message_type, e_head_size); - /* Check that this is the right message */ - if (emm_header->protocol_discriminator != EPS_MOBILITY_MANAGEMENT_MESSAGE) - return; - pdu_buf += e_head_size; pdu_len -= e_head_size; From b01d63ba4ecf7995c35a3fbbc097cc2bdda1dbf4 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Sat, 11 Apr 2020 00:20:24 +0200 Subject: [PATCH 407/553] Do not check for register_enb_pending The test seemingly ensures that this code block is hit only once. However, if we enable later activation of MMEs, it will be hit a second (and third, ...) time. The only thing in guards against, though, is an INIT message to the L1L2 thread, when register_enb_pending == 0, which should only be sent once. Therefore, functionality won't be changed if register_enb_pending becomes negative, and the assert can be removed. --- openair2/ENB_APP/enb_app.c | 1 - 1 file changed, 1 deletion(-) diff --git a/openair2/ENB_APP/enb_app.c b/openair2/ENB_APP/enb_app.c index 0e1c7e64bc..7c91e57813 100644 --- a/openair2/ENB_APP/enb_app.c +++ b/openair2/ENB_APP/enb_app.c @@ -273,7 +273,6 @@ void *eNB_app_task(void *args_p) { if (EPC_MODE_ENABLED) { LOG_I(ENB_APP, "[eNB %d] Received %s: associated MME %d\n", instance, ITTI_MSG_NAME (msg_p), S1AP_REGISTER_ENB_CNF(msg_p).nb_mme); - DevAssert(register_enb_pending > 0); register_enb_pending--; /* Check if at least eNB is registered with one MME */ From 1363a53dd070fd49bf3efb21dea94abad288887d Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Sat, 11 Apr 2020 00:23:40 +0200 Subject: [PATCH 408/553] S1AP: Only register MME if we do not know it yet --- openair3/S1AP/s1ap_eNB.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/openair3/S1AP/s1ap_eNB.c b/openair3/S1AP/s1ap_eNB.c index c228034245..c703501847 100644 --- a/openair3/S1AP/s1ap_eNB.c +++ b/openair3/S1AP/s1ap_eNB.c @@ -220,8 +220,21 @@ void s1ap_eNB_handle_register_eNB(instance_t instance, s1ap_register_enb_req_t * /* Trying to connect to provided list of MME ip address */ for (index = 0; index < s1ap_register_eNB->nb_mme; index++) { + net_ip_address_t *mme_ip = &s1ap_register_eNB->mme_ip_address[index]; + struct s1ap_eNB_mme_data_s *mme = NULL; + RB_FOREACH(mme, s1ap_mme_map, &new_instance->s1ap_mme_head) { + /* Compare whether IPv4 and IPv6 information is already present, in which + * wase we do not register again */ + if (mme->mme_s1_ip.ipv4 == mme_ip->ipv4 && (!mme_ip->ipv4 + || strncmp(mme->mme_s1_ip.ipv4_address, mme_ip->ipv4_address, 16) == 0) + && mme->mme_s1_ip.ipv6 == mme_ip->ipv6 && (!mme_ip->ipv6 + || strncmp(mme->mme_s1_ip.ipv6_address, mme_ip->ipv6_address, 46) == 0)) + break; + } + if (mme) + continue; s1ap_eNB_register_mme(new_instance, - &s1ap_register_eNB->mme_ip_address[index], + mme_ip, &s1ap_register_eNB->enb_ip_address, s1ap_register_eNB->sctp_in_streams, s1ap_register_eNB->sctp_out_streams, From df3f7e1ecfe0556bc3363c643ed811a1c3772ec1 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Fri, 10 Apr 2020 23:17:36 +0200 Subject: [PATCH 409/553] FlexRAN: Enable MME adding/removing --- .../CONTROL_MODULES/S1AP/flexran_agent_s1ap.c | 33 +++++++ .../CONTROL_MODULES/S1AP/flexran_agent_s1ap.h | 5 + openair2/ENB_APP/flexran_agent_common.c | 47 +++++----- openair2/ENB_APP/flexran_agent_ran_api.c | 91 +++++++++++++++++++ openair2/ENB_APP/flexran_agent_ran_api.h | 6 ++ 5 files changed, 160 insertions(+), 22 deletions(-) diff --git a/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.c b/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.c index 04a47406e1..d5fc5627a0 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.c +++ b/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.c @@ -125,6 +125,39 @@ void flexran_agent_s1ap_destroy_stats_reply(Protocol__FlexStatsReply *reply) { } } +void flexran_agent_handle_mme_update(mid_t mod_id, + size_t n_mme, + Protocol__FlexS1apMme **mme) { + if (n_mme == 0 || n_mme > 1) { + LOG_E(FLEXRAN_AGENT, "cannot handle %lu MMEs yet\n", n_mme); + return; + } + + if (!mme[0]->s1_ip) { + LOG_E(FLEXRAN_AGENT, "no S1 IP present, cannot handle request\n"); + return; + } + + if (mme[0]->has_state + && mme[0]->state == PROTOCOL__FLEX_MME_STATE__FLMMES_DISCONNECTED) { + int rc = flexran_remove_s1ap_mme(mod_id, 1, &mme[0]->s1_ip); + if (rc == 0) + LOG_I(FLEXRAN_AGENT, "remove MME at IP %s\n", mme[0]->s1_ip); + else + LOG_W(FLEXRAN_AGENT, + "could not remove MME: flexran_remove_s1ap_mme() returned %d\n", + rc); + } else { + int rc = flexran_add_s1ap_mme(mod_id, 1, &mme[0]->s1_ip); + if (rc == 0) + LOG_I(FLEXRAN_AGENT, "add MME at IP %s\n", mme[0]->s1_ip); + else + LOG_W(FLEXRAN_AGENT, + "could not add MME: flexran_add_s1ap_mme() returned %d\n", + rc); + } +} + int flexran_agent_register_s1ap_xface(mid_t mod_id) { if (agent_s1ap_xface[mod_id]) { LOG_E(FLEXRAN_AGENT, "S1AP agent CM for eNB %d is already registered\n", mod_id); diff --git a/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.h b/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.h index 1cca6ac9c1..54ea2926a8 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.h +++ b/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.h @@ -60,6 +60,11 @@ int flexran_agent_s1ap_stats_reply(mid_t mod_id, /* Free allocated S1AP stats message */ void flexran_agent_s1ap_destroy_stats_reply(Protocol__FlexStatsReply *reply); +/* Add or remove MME updates */ +void flexran_agent_handle_mme_update(mid_t mod_id, + size_t n_mme, + Protocol__FlexS1apMme **mme); + /* Register technology specific interface callbacks */ int flexran_agent_register_s1ap_xface(mid_t mod_id); diff --git a/openair2/ENB_APP/flexran_agent_common.c b/openair2/ENB_APP/flexran_agent_common.c index dc320ef974..ec0b780a3a 100644 --- a/openair2/ENB_APP/flexran_agent_common.c +++ b/openair2/ENB_APP/flexran_agent_common.c @@ -893,31 +893,34 @@ int flexran_agent_handle_enb_config_reply(mid_t mod_id, const void *params, Prot Protocol__FlexranMessage *input = (Protocol__FlexranMessage *)params; Protocol__FlexEnbConfigReply *enb_config = input->enb_config_reply_msg; - if (enb_config->n_cell_config == 0) { - LOG_W(FLEXRAN_AGENT, - "received enb_config_reply message does not contain a cell_config\n"); - *msg = NULL; - return 0; - } - if (enb_config->n_cell_config > 1) LOG_W(FLEXRAN_AGENT, "ignoring slice configs for other cell except cell 0\n"); - if (flexran_agent_get_mac_xface(mod_id) && enb_config->cell_config[0]->slice_config) { - prepare_update_slice_config(mod_id, enb_config->cell_config[0]->slice_config); - } else if (enb_config->cell_config[0]->has_eutra_band - && enb_config->cell_config[0]->has_dl_freq - && enb_config->cell_config[0]->has_ul_freq - && enb_config->cell_config[0]->has_dl_bandwidth) { - initiate_soft_restart(mod_id, enb_config->cell_config[0]); - } else if (flexran_agent_get_rrc_xface(mod_id) - && enb_config->cell_config[0]->has_x2_ho_net_control) { - LOG_I(FLEXRAN_AGENT, - "setting X2 HO NetControl to %d\n", - enb_config->cell_config[0]->x2_ho_net_control); - const int rc = flexran_set_x2_ho_net_control(mod_id, enb_config->cell_config[0]->x2_ho_net_control); - if (rc < 0) - LOG_E(FLEXRAN_AGENT, "Error in configuring X2 handover controlled by network"); + if (enb_config->n_cell_config > 0) { + if (flexran_agent_get_mac_xface(mod_id) && enb_config->cell_config[0]->slice_config) { + prepare_update_slice_config(mod_id, enb_config->cell_config[0]->slice_config); + } + if (enb_config->cell_config[0]->has_eutra_band + && enb_config->cell_config[0]->has_dl_freq + && enb_config->cell_config[0]->has_ul_freq + && enb_config->cell_config[0]->has_dl_bandwidth) { + initiate_soft_restart(mod_id, enb_config->cell_config[0]); + } + if (flexran_agent_get_rrc_xface(mod_id) + && enb_config->cell_config[0]->has_x2_ho_net_control) { + LOG_I(FLEXRAN_AGENT, + "setting X2 HO NetControl to %d\n", + enb_config->cell_config[0]->x2_ho_net_control); + const int rc = flexran_set_x2_ho_net_control(mod_id, enb_config->cell_config[0]->x2_ho_net_control); + if (rc < 0) + LOG_E(FLEXRAN_AGENT, "Error in configuring X2 handover controlled by network"); + } + } + + if (flexran_agent_get_s1ap_xface(mod_id) && enb_config->s1ap) { + flexran_agent_handle_mme_update(mod_id, + enb_config->s1ap->n_mme, + enb_config->s1ap->mme); } *msg = NULL; diff --git a/openair2/ENB_APP/flexran_agent_ran_api.c b/openair2/ENB_APP/flexran_agent_ran_api.c index abade20846..3306dfe61b 100644 --- a/openair2/ENB_APP/flexran_agent_ran_api.c +++ b/openair2/ENB_APP/flexran_agent_ran_api.c @@ -3634,6 +3634,97 @@ int flexran_get_s1ap_mme_conf(mid_t mod_id, mid_t mme_index, Protocol__FlexS1apM return 0; } +int flexran_add_s1ap_mme(mid_t mod_id, size_t n_mme, char **mme_ipv4) { + s1ap_eNB_instance_t *s1ap = s1ap_eNB_get_instance(mod_id); + if (!s1ap) return -1; + if (!rrc_is_present(mod_id)) return -2; + + /* Reconstruct S1AP_REGISTER_ENB_REQ */ + MessageDef *m = itti_alloc_new_message(TASK_FLEXRAN_AGENT, S1AP_REGISTER_ENB_REQ); + RCconfig_S1(m, mod_id); + + const int CC_id = 0; + eNB_RRC_INST *rrc = RC.rrc[CC_id]; + RrcConfigurationReq *conf = &rrc->configuration; + S1AP_REGISTER_ENB_REQ(m).num_plmn = conf->num_plmn; + for (int i = 0; i < conf->num_plmn; ++i) { + S1AP_REGISTER_ENB_REQ(m).mcc[i] = conf->mcc[i]; + S1AP_REGISTER_ENB_REQ(m).mnc[i] = conf->mnc[i]; + S1AP_REGISTER_ENB_REQ(m).mnc_digit_length[i] = conf->mnc_digit_length[i]; + } + + /* reconstruct MME list, it might have been updated since initial + * configuration */ + S1AP_REGISTER_ENB_REQ(m).nb_mme = 0; + struct s1ap_eNB_mme_data_s *mme = NULL; + RB_FOREACH(mme, s1ap_mme_map, &s1ap->s1ap_mme_head) { + const int n = S1AP_REGISTER_ENB_REQ(m).nb_mme; + S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv4 = mme->mme_s1_ip.ipv4; + strcpy(S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv4_address, mme->mme_s1_ip.ipv4_address); + S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv6 = mme->mme_s1_ip.ipv6; + strcpy(S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv6_address, mme->mme_s1_ip.ipv6_address); + S1AP_REGISTER_ENB_REQ(m).broadcast_plmn_num[n] = mme->broadcast_plmn_num; + for (int i = 0; i < mme->broadcast_plmn_num; ++i) + S1AP_REGISTER_ENB_REQ(m).broadcast_plmn_index[n][i] = mme->broadcast_plmn_index[i]; + S1AP_REGISTER_ENB_REQ(m).nb_mme += 1; + } + + if (S1AP_REGISTER_ENB_REQ(m).nb_mme + n_mme > S1AP_MAX_NB_MME_IP_ADDRESS) + return -1; + + for (int i = 0; i < n_mme; ++i) { + const int n = S1AP_REGISTER_ENB_REQ(m).nb_mme; + strcpy(S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv4_address, mme_ipv4[0]); + S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv4 = 1; + S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv6 = 0; + S1AP_REGISTER_ENB_REQ(m).broadcast_plmn_num[n] = S1AP_REGISTER_ENB_REQ(m).num_plmn; + for (int i = 0; i < S1AP_REGISTER_ENB_REQ(m).num_plmn; ++i) + S1AP_REGISTER_ENB_REQ(m).broadcast_plmn_index[n][i] = i; + S1AP_REGISTER_ENB_REQ(m).nb_mme += 1; + } + + itti_send_msg_to_task (TASK_S1AP, ENB_MODULE_ID_TO_INSTANCE(mod_id), m); + + return 0; +} + +int flexran_remove_s1ap_mme(mid_t mod_id, size_t n_mme, char **mme_ipv4) { + s1ap_eNB_instance_t *s1ap = s1ap_eNB_get_instance(mod_id); + if (!s1ap) return -1; + struct s1ap_eNB_mme_data_s *mme = NULL; + RB_FOREACH(mme, s1ap_mme_map, &s1ap->s1ap_mme_head) { + if (mme->mme_s1_ip.ipv4 + && strncmp(mme->mme_s1_ip.ipv4_address, mme_ipv4[0], 16) == 0) + break; + } + if (!mme) + return -2; + + MessageDef *m = itti_alloc_new_message(TASK_FLEXRAN_AGENT, SCTP_CLOSE_ASSOCIATION); + SCTP_CLOSE_ASSOCIATION(m).assoc_id = mme->assoc_id; + itti_send_msg_to_task (TASK_SCTP, ENB_MODULE_ID_TO_INSTANCE(mod_id), m); + + switch (mme->state) { + case S1AP_ENB_STATE_WAITING: + s1ap->s1ap_mme_nb -= 1; + if (s1ap->s1ap_mme_pending_nb > 0) + s1ap->s1ap_mme_pending_nb -= 1; + break; + case S1AP_ENB_STATE_CONNECTED: + case S1AP_ENB_OVERLOAD: /* I am not sure the decrements are right here */ + s1ap->s1ap_mme_nb -= 1; + s1ap->s1ap_mme_associated_nb -= 1; + break; + case S1AP_ENB_STATE_DISCONNECTED: + default: + break; + } + RB_REMOVE(s1ap_mme_map, &s1ap->s1ap_mme_head, mme); + + return 0; +} + + int flexran_get_s1ap_ue(mid_t mod_id, rnti_t rnti, Protocol__FlexS1apUe * ue_conf){ if (!rrc_is_present(mod_id)) return -1; s1ap_eNB_instance_t *s1ap = s1ap_eNB_get_instance(mod_id); diff --git a/openair2/ENB_APP/flexran_agent_ran_api.h b/openair2/ENB_APP/flexran_agent_ran_api.h index ce32883852..3c2803d663 100644 --- a/openair2/ENB_APP/flexran_agent_ran_api.h +++ b/openair2/ENB_APP/flexran_agent_ran_api.h @@ -832,6 +832,12 @@ int flexran_get_s1ap_mme_conf(mid_t mod_id, mid_t mme_index, Protocol__FlexS1apM /* Get the S1AP UE conf */ int flexran_get_s1ap_ue(mid_t mod_id, rnti_t rnti, Protocol__FlexS1apUe * ue_conf); +/* Add MMEs and re-issue S1AP Registration Request */ +int flexran_add_s1ap_mme(mid_t mod_id, size_t n_mme, char **mme_ipv4); + +/* Remove MMEs and and cut SCTP to MME */ +int flexran_remove_s1ap_mme(mid_t mod_id, size_t n_mme, char **mme_ipv4); + /********************* general information *****************/ /* get an ID for this BS (or part of a BS) */ uint64_t flexran_get_bs_id(mid_t mod_id); From f895a28645b277bfb3c061789594044839a6751a Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Sat, 11 Apr 2020 13:40:50 +0200 Subject: [PATCH 410/553] FlexRAN: Manage PLMNs --- .../CONTROL_MODULES/S1AP/flexran_agent_s1ap.c | 24 +++++++ .../CONTROL_MODULES/S1AP/flexran_agent_s1ap.h | 6 ++ openair2/ENB_APP/flexran_agent_common.c | 6 ++ openair2/ENB_APP/flexran_agent_ran_api.c | 71 +++++++++++++++++++ openair2/ENB_APP/flexran_agent_ran_api.h | 3 + 5 files changed, 110 insertions(+) diff --git a/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.c b/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.c index d5fc5627a0..c2d7cb9e55 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.c +++ b/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.c @@ -158,6 +158,30 @@ void flexran_agent_handle_mme_update(mid_t mod_id, } } +void flexran_agent_handle_plmn_update(mid_t mod_id, + int CC_id, + size_t n_plmn, + Protocol__FlexPlmn **plmn_id) { + if (n_plmn < 1 || n_plmn > 6) { + LOG_E(FLEXRAN_AGENT, "cannot handle %lu PLMNs\n", n_plmn); + return; + } + + /* We assume the controller has checked all the parameters within each + * plmn_id */ + int rc = flexran_set_new_plmn_id(mod_id, CC_id, n_plmn, plmn_id); + if (rc == 0) { + LOG_I(FLEXRAN_AGENT, "set %lu new PLMNs:\n", n_plmn); + for (int i = 0; i < (int)n_plmn; ++i) + LOG_I(FLEXRAN_AGENT, " MCC %d MNC %d MNC length %d\n", + plmn_id[i]->mcc, plmn_id[i]->mnc, plmn_id[0]->mnc_length); + } else { + LOG_W(FLEXRAN_AGENT, + "could not set new PLMN configuration: flexran_set_new_plmn_id() returned %d\n", + rc); + } +} + int flexran_agent_register_s1ap_xface(mid_t mod_id) { if (agent_s1ap_xface[mod_id]) { LOG_E(FLEXRAN_AGENT, "S1AP agent CM for eNB %d is already registered\n", mod_id); diff --git a/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.h b/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.h index 54ea2926a8..006eaa1d3c 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.h +++ b/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.h @@ -65,6 +65,12 @@ void flexran_agent_handle_mme_update(mid_t mod_id, size_t n_mme, Protocol__FlexS1apMme **mme); +/* Set a new PLMN configuration */ +void flexran_agent_handle_plmn_update(mid_t mod_id, + int CC_id, + size_t n_plmn, + Protocol__FlexPlmn **plmn_id); + /* Register technology specific interface callbacks */ int flexran_agent_register_s1ap_xface(mid_t mod_id); diff --git a/openair2/ENB_APP/flexran_agent_common.c b/openair2/ENB_APP/flexran_agent_common.c index ec0b780a3a..e77b2fb386 100644 --- a/openair2/ENB_APP/flexran_agent_common.c +++ b/openair2/ENB_APP/flexran_agent_common.c @@ -915,6 +915,12 @@ int flexran_agent_handle_enb_config_reply(mid_t mod_id, const void *params, Prot if (rc < 0) LOG_E(FLEXRAN_AGENT, "Error in configuring X2 handover controlled by network"); } + if (flexran_agent_get_rrc_xface(mod_id) && enb_config->cell_config[0]->n_plmn_id > 0) { + flexran_agent_handle_plmn_update(mod_id, + 0, + enb_config->cell_config[0]->n_plmn_id, + enb_config->cell_config[0]->plmn_id); + } } if (flexran_agent_get_s1ap_xface(mod_id) && enb_config->s1ap) { diff --git a/openair2/ENB_APP/flexran_agent_ran_api.c b/openair2/ENB_APP/flexran_agent_ran_api.c index 3306dfe61b..0fcc51782e 100644 --- a/openair2/ENB_APP/flexran_agent_ran_api.c +++ b/openair2/ENB_APP/flexran_agent_ran_api.c @@ -3724,6 +3724,77 @@ int flexran_remove_s1ap_mme(mid_t mod_id, size_t n_mme, char **mme_ipv4) { return 0; } +int flexran_set_new_plmn_id(mid_t mod_id, int CC_id, size_t n_plmn, Protocol__FlexPlmn **plmn_id) { + if (!rrc_is_present(mod_id)) + return -1; + s1ap_eNB_instance_t *s1ap = s1ap_eNB_get_instance(mod_id); + if (!s1ap) + return -2; + + eNB_RRC_INST *rrc = RC.rrc[CC_id]; + RrcConfigurationReq *conf = &rrc->configuration; + + uint8_t num_plmn_old = conf->num_plmn; + uint16_t mcc[PLMN_LIST_MAX_SIZE]; + uint16_t mnc[PLMN_LIST_MAX_SIZE]; + uint8_t mnc_digit_length[PLMN_LIST_MAX_SIZE]; + for (int i = 0; i < num_plmn_old; ++i) { + mcc[i] = conf->mcc[i]; + mnc[i] = conf->mnc[i]; + mnc_digit_length[i] = conf->mnc_digit_length[i]; + } + + conf->num_plmn = (uint8_t) n_plmn; + for (int i = 0; i < conf->num_plmn; ++i) { + conf->mcc[i] = plmn_id[i]->mcc; + conf->mnc[i] = plmn_id[i]->mnc; + conf->mnc_digit_length[i] = plmn_id[i]->mnc_length; + } + + rrc_eNB_carrier_data_t *carrier = &rrc->carrier[CC_id]; + extern uint8_t do_SIB1(rrc_eNB_carrier_data_t *carrier, + int Mod_id, + int CC_id, + BOOLEAN_t brOption, + RrcConfigurationReq *configuration); + carrier->sizeof_SIB1 = do_SIB1(carrier, mod_id, CC_id, FALSE, conf); + if (carrier->sizeof_SIB1 < 0) + return -1337; /* SIB1 encoding failed, hell will probably break loose */ + + s1ap->num_plmn = (uint8_t) n_plmn; + for (int i = 0; i < conf->num_plmn; ++i) { + s1ap->mcc[i] = plmn_id[i]->mcc; + s1ap->mnc[i] = plmn_id[i]->mnc; + s1ap->mnc_digit_length[i] = plmn_id[i]->mnc_length; + } + + int bpn_failed = 0; + struct s1ap_eNB_mme_data_s *mme = NULL; + RB_FOREACH(mme, s1ap_mme_map, &s1ap->s1ap_mme_head) { + for (int i = 0; i < mme->broadcast_plmn_num; ++i) { + /* search the new index and update. If we don't find, we count this using + * bpn_failed to now how many broadcast_plmns could not be updated */ + int idx = mme->broadcast_plmn_index[i]; + int omcc = mcc[idx]; + int omnc = mnc[idx]; + int omncl = mnc_digit_length[idx]; + int j = 0; + for (j = 0; j < s1ap->num_plmn; ++j) { + if (s1ap->mcc[j] == omcc + && s1ap->mnc[j] == omnc + && s1ap->mnc_digit_length[j] == omncl) { + mme->broadcast_plmn_index[i] = j; + break; + } + } + if (j == s1ap->num_plmn) /* could not find the old PLMN in the new ones */ + bpn_failed++; + } + } + if (bpn_failed > 0) + return -10000 - bpn_failed; + return 0; +} int flexran_get_s1ap_ue(mid_t mod_id, rnti_t rnti, Protocol__FlexS1apUe * ue_conf){ if (!rrc_is_present(mod_id)) return -1; diff --git a/openair2/ENB_APP/flexran_agent_ran_api.h b/openair2/ENB_APP/flexran_agent_ran_api.h index 3c2803d663..9d1bfb9d3e 100644 --- a/openair2/ENB_APP/flexran_agent_ran_api.h +++ b/openair2/ENB_APP/flexran_agent_ran_api.h @@ -838,6 +838,9 @@ int flexran_add_s1ap_mme(mid_t mod_id, size_t n_mme, char **mme_ipv4); /* Remove MMEs and and cut SCTP to MME */ int flexran_remove_s1ap_mme(mid_t mod_id, size_t n_mme, char **mme_ipv4); +/* Set a new PLMN configuration */ +int flexran_set_new_plmn_id(mid_t mod_id, int CC_id, size_t n_plmn, Protocol__FlexPlmn **plmn_id); + /********************* general information *****************/ /* get an ID for this BS (or part of a BS) */ uint64_t flexran_get_bs_id(mid_t mod_id); From d2cc43b4e772de499a406f0e199e1c26851d42d3 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Tue, 14 Apr 2020 14:47:27 +0200 Subject: [PATCH 411/553] UE: Print all SIB1 decoded PLMNs --- openair2/RRC/LTE/rrc_UE.c | 65 +++++++++++++++++++-------------------- 1 file changed, 32 insertions(+), 33 deletions(-) diff --git a/openair2/RRC/LTE/rrc_UE.c b/openair2/RRC/LTE/rrc_UE.c index 4116f5367e..53348f5621 100644 --- a/openair2/RRC/LTE/rrc_UE.c +++ b/openair2/RRC/LTE/rrc_UE.c @@ -2794,44 +2794,43 @@ int decode_SIB1( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB_index, LTE_SystemInformationBlockType1_t *sib1 = UE_rrc_inst[ctxt_pP->module_id].sib1[eNB_index]; VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_RRC_UE_DECODE_SIB1, VCD_FUNCTION_IN ); LOG_I( RRC, "[UE %d] : Dumping SIB 1\n", ctxt_pP->module_id ); - LTE_PLMN_Identity_t *PLMN_identity = &sib1->cellAccessRelatedInfo.plmn_IdentityList.list.array[0]->plmn_Identity; - int mccdigits = PLMN_identity->mcc->list.count; - int mncdigits = PLMN_identity->mnc.list.count; - int mcc; + const int n = sib1->cellAccessRelatedInfo.plmn_IdentityList.list.count; + for (int i = 0; i < n; ++i) { + LTE_PLMN_Identity_t *PLMN_identity = &sib1->cellAccessRelatedInfo.plmn_IdentityList.list.array[i]->plmn_Identity; + int mccdigits = PLMN_identity->mcc->list.count; + int mncdigits = PLMN_identity->mnc.list.count; - if (mccdigits == 2) { - mcc = *PLMN_identity->mcc->list.array[0]*10 + *PLMN_identity->mcc->list.array[1]; - } else { - mcc = *PLMN_identity->mcc->list.array[0]*100 + *PLMN_identity->mcc->list.array[1]*10 + *PLMN_identity->mcc->list.array[2]; + int mcc; + if (mccdigits == 2) { + mcc = *PLMN_identity->mcc->list.array[0]*10 + *PLMN_identity->mcc->list.array[1]; + } else { + mcc = *PLMN_identity->mcc->list.array[0]*100 + *PLMN_identity->mcc->list.array[1]*10 + *PLMN_identity->mcc->list.array[2]; + } + + int mnc; + if (mncdigits == 2) { + mnc = *PLMN_identity->mnc.list.array[0]*10 + *PLMN_identity->mnc.list.array[1]; + } else { + mnc = *PLMN_identity->mnc.list.array[0]*100 + *PLMN_identity->mnc.list.array[1]*10 + *PLMN_identity->mnc.list.array[2]; + } + + LOG_I( RRC, "PLMN %d MCC %0*d, MNC %0*d\n", i + 1, mccdigits, mcc, mncdigits, mnc); + // search internal table for provider name + int plmn_ind = 0; + + while (plmn_data[plmn_ind].mcc > 0) { + if ((plmn_data[plmn_ind].mcc == mcc) && (plmn_data[plmn_ind].mnc == mnc)) { + LOG_I( RRC, "Found %s (name from internal table)\n", plmn_data[plmn_ind].oper_short ); + break; + } + + plmn_ind++; + } } - - int mnc; - - if (mncdigits == 2) { - mnc = *PLMN_identity->mnc.list.array[0]*10 + *PLMN_identity->mnc.list.array[1]; - } else { - mnc = *PLMN_identity->mnc.list.array[0]*100 + *PLMN_identity->mnc.list.array[1]*10 + *PLMN_identity->mnc.list.array[2]; - } - - LOG_I( RRC, "PLMN MCC %0*d, MNC %0*d, TAC 0x%04x\n", mccdigits, mcc, mncdigits, mnc, + LOG_I( RRC, "TAC 0x%04x\n", ((sib1->cellAccessRelatedInfo.trackingAreaCode.size == 2)?((sib1->cellAccessRelatedInfo.trackingAreaCode.buf[0]<<8) + sib1->cellAccessRelatedInfo.trackingAreaCode.buf[1]):0)); LOG_I( RRC, "cellReservedForOperatorUse : raw:%ld decoded:%s\n", sib1->cellAccessRelatedInfo.plmn_IdentityList.list.array[0]->cellReservedForOperatorUse, SIBreserved(sib1->cellAccessRelatedInfo.plmn_IdentityList.list.array[0]->cellReservedForOperatorUse) ); - // search internal table for provider name - int plmn_ind = 0; - - while (plmn_data[plmn_ind].mcc > 0) { - if ((plmn_data[plmn_ind].mcc == mcc) && (plmn_data[plmn_ind].mnc == mnc)) { - LOG_I( RRC, "Found %s (name from internal table)\n", plmn_data[plmn_ind].oper_short ); - break; - } - - plmn_ind++; - } - - if (plmn_data[plmn_ind].mcc < 0) { - LOG_I( RRC, "Found Unknown operator (no entry in internal table)\n" ); - } LOG_I( RRC, "cellAccessRelatedInfo.cellIdentity : raw:%"PRIu32" decoded:%02x.%02x.%02x.%02x\n", BIT_STRING_to_uint32( &sib1->cellAccessRelatedInfo.cellIdentity ), From 9d5a46dcfa12985d5e52b8066bdfa6b696e008ef Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Tue, 14 Apr 2020 14:47:59 +0200 Subject: [PATCH 412/553] UE: Set correct selected PLMN Identity --- openair2/RRC/LTE/MESSAGES/asn1_msg.c | 4 ++-- openair2/RRC/LTE/MESSAGES/asn1_msg.h | 6 +++++- openair2/RRC/LTE/rrc_UE.c | 26 +++++++++++++++++++++----- openair2/RRC/LTE/rrc_defs.h | 1 + 4 files changed, 29 insertions(+), 8 deletions(-) diff --git a/openair2/RRC/LTE/MESSAGES/asn1_msg.c b/openair2/RRC/LTE/MESSAGES/asn1_msg.c index 583e10da94..9ede543003 100644 --- a/openair2/RRC/LTE/MESSAGES/asn1_msg.c +++ b/openair2/RRC/LTE/MESSAGES/asn1_msg.c @@ -2310,7 +2310,7 @@ uint8_t do_SidelinkUEInformation(uint8_t Mod_id, uint8_t *buffer, LTE_SL_Destin return((enc_rval.encoded+7)/8); } -uint8_t do_RRCConnectionSetupComplete(uint8_t Mod_id, uint8_t *buffer, const uint8_t Transaction_id, const int dedicatedInfoNASLength, const char *dedicatedInfoNAS) { +uint8_t do_RRCConnectionSetupComplete(uint8_t Mod_id, uint8_t *buffer, const uint8_t Transaction_id, uint8_t sel_plmn_id, const int dedicatedInfoNASLength, const char *dedicatedInfoNAS) { asn_enc_rval_t enc_rval; LTE_UL_DCCH_Message_t ul_dcch_msg; LTE_RRCConnectionSetupComplete_t *rrcConnectionSetupComplete; @@ -2323,7 +2323,7 @@ uint8_t do_RRCConnectionSetupComplete(uint8_t Mod_id, uint8_t *buffer, const uin rrcConnectionSetupComplete->criticalExtensions.choice.c1.present = LTE_RRCConnectionSetupComplete__criticalExtensions__c1_PR_rrcConnectionSetupComplete_r8; rrcConnectionSetupComplete->criticalExtensions.choice.c1.choice.rrcConnectionSetupComplete_r8.nonCriticalExtension=CALLOC(1, sizeof(*rrcConnectionSetupComplete->criticalExtensions.choice.c1.choice.rrcConnectionSetupComplete_r8.nonCriticalExtension)); - rrcConnectionSetupComplete->criticalExtensions.choice.c1.choice.rrcConnectionSetupComplete_r8.selectedPLMN_Identity= 1; + rrcConnectionSetupComplete->criticalExtensions.choice.c1.choice.rrcConnectionSetupComplete_r8.selectedPLMN_Identity= sel_plmn_id; rrcConnectionSetupComplete->criticalExtensions.choice.c1.choice.rrcConnectionSetupComplete_r8.registeredMME = NULL;//calloc(1,sizeof(*rrcConnectionSetupComplete->criticalExtensions.choice.c1.choice.rrcConnectionSetupComplete_r8.registeredMME)); /* diff --git a/openair2/RRC/LTE/MESSAGES/asn1_msg.h b/openair2/RRC/LTE/MESSAGES/asn1_msg.h index dda2340610..640d18a61f 100644 --- a/openair2/RRC/LTE/MESSAGES/asn1_msg.h +++ b/openair2/RRC/LTE/MESSAGES/asn1_msg.h @@ -142,7 +142,11 @@ uint8_t do_SidelinkUEInformation(uint8_t Mod_id, uint8_t *buffer, LTE_SL_Destina /** \brief Generate an RRCConnectionSetupComplete UL-DCCH-Message (UE) @param buffer Pointer to PER-encoded ASN.1 description of UL-DCCH-Message PDU @returns Size of encoded bit stream in bytes*/ -uint8_t do_RRCConnectionSetupComplete(uint8_t Mod_id, uint8_t *buffer, const uint8_t Transaction_id, const int dedicatedInfoNASLength, +uint8_t do_RRCConnectionSetupComplete(uint8_t Mod_id, + uint8_t *buffer, + const uint8_t Transaction_id, + uint8_t sel_plmn_id, + const int dedicatedInfoNASLength, const char *dedicatedInfoNAS); /** \brief Generate an RRCConnectionReconfigurationComplete UL-DCCH-Message (UE) diff --git a/openair2/RRC/LTE/rrc_UE.c b/openair2/RRC/LTE/rrc_UE.c index 53348f5621..bdf992c76a 100644 --- a/openair2/RRC/LTE/rrc_UE.c +++ b/openair2/RRC/LTE/rrc_UE.c @@ -128,8 +128,13 @@ static int decode_SIB1_MBMS( const protocol_ctxt_t *const ctxt_pP, const uint8_t * \param ctxt_pP Running context * \param eNB_index Index of corresponding eNB/CH * \param Transaction_id Transaction identifier + * \param sel_plmn_id selected PLMN Identity */ -static void rrc_ue_generate_RRCConnectionSetupComplete( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB_index, const uint8_t Transaction_id ); +static void rrc_ue_generate_RRCConnectionSetupComplete( + const protocol_ctxt_t *const ctxt_pP, + const uint8_t eNB_index, + const uint8_t Transaction_id, + uint8_t sel_plmn_id); /** \brief Generates/Encodes RRCConnectionReconfigurationComplete message at UE * \param ctxt_pP Running context @@ -367,6 +372,7 @@ char openair_rrc_ue_init( const module_id_t ue_mod_idP, const unsigned char eNB_ rrc_set_state (ue_mod_idP, RRC_STATE_INACTIVE); rrc_set_sub_state (ue_mod_idP, RRC_SUB_STATE_INACTIVE); LOG_I(RRC,"[UE %d] INIT State = RRC_IDLE (eNB %d)\n",ctxt.module_id,eNB_index); + UE_rrc_inst[ctxt.module_id].selected_plmn_identity = 1; UE_rrc_inst[ctxt.module_id].Info[eNB_index].State=RRC_IDLE; UE_rrc_inst[ctxt.module_id].Info[eNB_index].T300_active = 0; UE_rrc_inst[ctxt.module_id].Info[eNB_index].T304_active = 0; @@ -490,7 +496,11 @@ rrc_t310_expiration( } //----------------------------------------------------------------------------- -static void rrc_ue_generate_RRCConnectionSetupComplete( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB_index, const uint8_t Transaction_id ) { +static void rrc_ue_generate_RRCConnectionSetupComplete( + const protocol_ctxt_t *const ctxt_pP, + const uint8_t eNB_index, + const uint8_t Transaction_id, + uint8_t sel_plmn_id) { uint8_t buffer[100]; uint8_t size; const char *nas_msg; @@ -504,7 +514,7 @@ static void rrc_ue_generate_RRCConnectionSetupComplete( const protocol_ctxt_t *c nas_msg_length = sizeof(nas_attach_req_imsi); } - size = do_RRCConnectionSetupComplete(ctxt_pP->module_id, buffer, Transaction_id, nas_msg_length, nas_msg); + size = do_RRCConnectionSetupComplete(ctxt_pP->module_id, buffer, Transaction_id, sel_plmn_id, nas_msg_length, nas_msg); LOG_I(RRC,"[UE %d][RAPROC] Frame %d : Logical Channel UL-DCCH (SRB1), Generating RRCConnectionSetupComplete (bytes%d, eNB %d)\n", ctxt_pP->module_id,ctxt_pP->frame, size, eNB_index); LOG_D(RLC, @@ -624,7 +634,8 @@ int rrc_ue_decode_ccch( const protocol_ctxt_t *const ctxt_pP, const SRB_INFO *co rrc_ue_generate_RRCConnectionSetupComplete( ctxt_pP, eNB_index, - dl_ccch_msg->message.choice.c1.choice.rrcConnectionSetup.rrc_TransactionIdentifier); + dl_ccch_msg->message.choice.c1.choice.rrcConnectionSetup.rrc_TransactionIdentifier, + UE_rrc_inst[ctxt_pP->module_id].selected_plmn_identity); rval = 0; break; @@ -2969,6 +2980,7 @@ int decode_SIB1( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB_index, NAS_CELL_SELECTION_CNF (msg_p).rsrp = rsrp; itti_send_msg_to_task(TASK_NAS_UE, ctxt_pP->instance, msg_p); cell_valid = 1; + UE_rrc_inst[ctxt_pP->module_id].selected_plmn_identity = plmn + 1; break; } } @@ -2979,7 +2991,11 @@ int decode_SIB1( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB_index, MessageDef *msg_p; msg_p = itti_alloc_new_message(TASK_RRC_UE, PHY_FIND_NEXT_CELL_REQ); itti_send_msg_to_task(TASK_PHY_UE, ctxt_pP->instance, msg_p); - LOG_E(RRC, "Synched with a cell, but PLMN doesn't match our SIM, the message PHY_FIND_NEXT_CELL_REQ is sent but lost in current UE implementation! \n"); + LOG_E(RRC, + "Synched with a cell, but PLMN doesn't match our SIM " + "(selected_plmn_identity %d), the message PHY_FIND_NEXT_CELL_REQ " + "is sent but lost in current UE implementation!\n", + UE_rrc_inst[ctxt_pP->module_id].selected_plmn_identity); } } diff --git a/openair2/RRC/LTE/rrc_defs.h b/openair2/RRC/LTE/rrc_defs.h index 42fa5f6de1..03b6c759b6 100644 --- a/openair2/RRC/LTE/rrc_defs.h +++ b/openair2/RRC/LTE/rrc_defs.h @@ -808,6 +808,7 @@ typedef struct UE_RRC_INST_s { Rrc_Sub_State_t RrcSubState; plmn_t plmnID; Byte_t rat; + uint8_t selected_plmn_identity; as_nas_info_t initialNasMsg; OAI_UECapability_t *UECap; uint8_t *UECapability; From 476d58a8deef0f15ce3a59870e4cc80a122313e8 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Thu, 21 May 2020 21:18:26 +0200 Subject: [PATCH 413/553] Log TBS in every window --- openair2/LAYER2/MAC/eNB_scheduler_dlsch.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c index 7621994ab2..2382af3636 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c @@ -588,6 +588,7 @@ schedule_ue_spec(module_id_t module_idP, UE_sched_ctrl_t *ue_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; UE_TEMPLATE *ue_template = &UE_info->UE_template[CC_id][UE_id]; eNB_UE_STATS *eNB_UE_stats = &UE_info->eNB_UE_stats[CC_id][UE_id]; + eNB_UE_stats->TBS = 0; const rnti_t rnti = ue_template->rnti; // If TDD @@ -799,6 +800,7 @@ schedule_ue_spec(module_id_t module_idP, eNB_UE_stats->rbs_used_retx = nb_rb; eNB_UE_stats->total_rbs_used_retx += nb_rb; eNB_UE_stats->dlsch_mcs2 = eNB_UE_stats->dlsch_mcs1; + eNB_UE_stats->TBS = TBS; } else { // Now check RLC information to compute number of required RBs // get maximum TBS size for RLC request From 71647eb4effe80bf5defada0e314acbd4e98f7a1 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Fri, 12 Jun 2020 19:25:44 +0200 Subject: [PATCH 414/553] DLSCH: limit LC bytes according to preprocessor --- openair2/LAYER2/MAC/eNB_scheduler_dlsch.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c index 2382af3636..c35af34a7f 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c @@ -844,13 +844,18 @@ schedule_ue_spec(module_id_t module_idP, if (ue_sched_ctrl->dl_lc_bytes[i] == 0) // no data in this LC! continue; - LOG_D(MAC, "[eNB %d] SFN/SF %d.%d, LC%d->DLSCH CC_id %d, Requesting %d bytes from RLC (RRC message)\n", + const uint32_t data = + min(ue_sched_ctrl->dl_lc_bytes[i], + TBS - ta_len - header_length_total - sdu_length_total - 3); + LOG_D(MAC, + "[eNB %d] SFN/SF %d.%d, LC%d->DLSCH CC_id %d, Requesting %d " + "bytes from RLC (RRC message)\n", module_idP, frameP, subframeP, lcid, CC_id, - TBS - ta_len - header_length_total - sdu_length_total - 3); + data); sdu_lengths[num_sdus] = mac_rlc_data_req(module_idP, rnti, @@ -859,7 +864,7 @@ schedule_ue_spec(module_id_t module_idP, ENB_FLAG_YES, MBMS_FLAG_NO, lcid, - TBS - ta_len - header_length_total - sdu_length_total - 3, + data, (char *)&dlsch_buffer[sdu_length_total], 0, 0 From b06dadbdb0d25162149d016650740f2b6a75f3e2 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Wed, 24 Jun 2020 14:24:02 +0200 Subject: [PATCH 415/553] Bugfix DLSCH: only warn when retx with less RB The preprocessor pre-allocates a CCE. Thus, when arriving at the check for the number of RBs for retransmission, it is too late to skip the UE. Therefore, only print a warning. The default schedulers allocate a correct amount of RBs for retransmissions, therefore it is ok. --- openair2/LAYER2/MAC/eNB_scheduler_dlsch.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c index c35af34a7f..783d4e8b1a 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c @@ -680,15 +680,15 @@ schedule_ue_spec(module_id_t module_idP, const uint32_t rbc = allocate_prbs_sub( nb_rb, N_RB_DL, N_RBG, ue_sched_ctrl->rballoc_sub_UE[CC_id]); - if (nb_rb > ue_sched_ctrl->pre_nb_available_rbs[CC_id]) { - LOG_D(MAC, - "[eNB %d] Frame %d CC_id %d : don't schedule UE %d, its retransmission takes more resources than we have\n", + if (nb_rb > ue_sched_ctrl->pre_nb_available_rbs[CC_id]) + LOG_W(MAC, + "[eNB %d] %d.%d CC_id %d : should not schedule UE %d, its " + "retransmission takes more resources than we have\n", module_idP, frameP, + subframeP, CC_id, UE_id); - continue; - } /* CDRX */ ue_sched_ctrl->harq_rtt_timer[CC_id][harq_pid] = 1; // restart HARQ RTT timer From 1401d21081805d42f45ced99becbb2dbd5907ee8 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Wed, 20 May 2020 12:45:35 +0200 Subject: [PATCH 416/553] Default SCHED RR algo: optimize algo and defer RB calc. - Loop only to next UE instead of jumping multiple - mark used RBGs in rbg_mask - Only calculate number of RBs based on CQI when UE is selected, instead of calculating for all UEs which might be unnecessary. - When looping the list of UEs for RB allocation, remove UEs that have no data anymore instead of skipping them. --- openair2/LAYER2/MAC/pre_processor.c | 72 ++++++++++------------------- 1 file changed, 25 insertions(+), 47 deletions(-) diff --git a/openair2/LAYER2/MAC/pre_processor.c b/openair2/LAYER2/MAC/pre_processor.c index 8569d8f166..d4e39b2b6b 100644 --- a/openair2/LAYER2/MAC/pre_processor.c +++ b/openair2/LAYER2/MAC/pre_processor.c @@ -86,9 +86,6 @@ int round_robin_dl(module_id_t Mod_id, int num_ue_req = 0; UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; - int rb_required[MAX_MOBILES_PER_ENB]; // how much UEs request - memset(rb_required, 0, sizeof(rb_required)); - int rbg = 0; for (; !rbgalloc_mask[rbg]; rbg++) ; /* fast-forward to first allowed RBG */ @@ -133,6 +130,7 @@ int round_robin_dl(module_id_t Mod_id, if (!rbgalloc_mask[rbg]) continue; ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1; + rbgalloc_mask[rbg] = 0; nb_rbg--; } LOG_D(MAC, @@ -150,22 +148,8 @@ int round_robin_dl(module_id_t Mod_id, return n_rbg_sched; for (; !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ; } else { - const int dlsch_mcs1 = cqi_to_mcs[UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id]]; - UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1 = dlsch_mcs1; - rb_required[UE_id] = - find_nb_rb_DL(dlsch_mcs1, - UE_info->UE_template[CC_id][UE_id].dl_buffer_total, - n_rbg_sched * RBGsize, - RBGsize); - if (rb_required[UE_id] > 0) + if (UE_info->UE_template[CC_id][UE_id].dl_buffer_total > 0) num_ue_req++; - LOG_D(MAC, - "%d/%d UE_id %d rb_required %d n_rbg_sched %d\n", - frame, - subframe, - UE_id, - rb_required[UE_id], - n_rbg_sched); } } @@ -178,12 +162,13 @@ int round_robin_dl(module_id_t Mod_id, g_start_ue_dl = UE_list->head; int UE_id = g_start_ue_dl; UE_list_t UE_sched; - int rb_required_total = 0; + int *cur_UE = &UE_sched.head; + int num_ue_sched = 0; max_num_ue = min(min(max_num_ue, num_ue_req), n_rbg_sched); - int *cur_UE = &UE_sched.head; + int rb_required[MAX_MOBILES_PER_ENB]; // how much UEs request while (num_ue_sched < max_num_ue) { - while (rb_required[UE_id] == 0) + while (UE_info->UE_template[CC_id][UE_id].dl_buffer_total <= 0) UE_id = next_ue_list_looped(UE_list, UE_id); const uint8_t cqi = UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id]; const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi); @@ -195,42 +180,42 @@ int round_robin_dl(module_id_t Mod_id, continue; } UE_info->UE_sched_ctrl[UE_id].pre_dci_dl_pdu_idx = idx; + const int mcs = cqi_to_mcs[cqi]; + UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1 = mcs; + const uint32_t B = UE_info->UE_template[CC_id][UE_id].dl_buffer_total; + rb_required[UE_id] = find_nb_rb_DL(mcs, B, n_rbg_sched * RBGsize, RBGsize); *cur_UE = UE_id; cur_UE = &UE_sched.next[UE_id]; - rb_required_total += rb_required[UE_id]; num_ue_sched++; UE_id = next_ue_list_looped(UE_list, UE_id); // next candidate } *cur_UE = -1; /* for one UE after the next: allocate resources */ - for (int UE_id = UE_sched.head; UE_id >= 0; - UE_id = next_ue_list_looped(&UE_sched, UE_id)) { - if (rb_required[UE_id] <= 0) - continue; + cur_UE = &UE_sched.head; + while (*cur_UE >= 0) { + const int UE_id = *cur_UE; UE_sched_ctrl_t *ue_ctrl = &UE_info->UE_sched_ctrl[UE_id]; ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1; + rbgalloc_mask[rbg] = 0; const int sRBG = rbg == N_RBG - 1 ? RBGlastsize : RBGsize; ue_ctrl->pre_nb_available_rbs[CC_id] += sRBG; rb_required[UE_id] -= sRBG; - rb_required_total -= sRBG; - if (rb_required_total <= 0) - break; + if (rb_required[UE_id] <= 0) { + *cur_UE = UE_sched.next[*cur_UE]; + if (*cur_UE < 0) + cur_UE = &UE_sched.head; + } else { + cur_UE = UE_sched.next[*cur_UE] < 0 ? &UE_sched.head : &UE_sched.next[*cur_UE]; + } n_rbg_sched--; if (n_rbg_sched <= 0) break; for (rbg++; !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ; } - /* if not all UEs could be allocated in this round */ - if (num_ue_req > max_num_ue) { - /* go to the first one we missed */ - for (int i = 0; i < max_num_ue; ++i) - g_start_ue_dl = next_ue_list_looped(UE_list, g_start_ue_dl); - } else { - /* else, just start with the next UE next time */ - g_start_ue_dl = next_ue_list_looped(UE_list, g_start_ue_dl); - } + /* just start with the next UE next time */ + g_start_ue_dl = next_ue_list_looped(UE_list, g_start_ue_dl); return n_rbg_sched; } @@ -730,15 +715,8 @@ int round_robin_ul(module_id_t Mod_id, } } - /* if not all UEs could be allocated in this round */ - if (num_ue_req > max_num_ue) { - /* go to the first one we missed */ - for (int i = 0; i < max_num_ue; ++i) - g_start_ue_ul = next_ue_list_looped(UE_list, g_start_ue_ul); - } else { - /* else, just start with the next UE next time */ - g_start_ue_ul = next_ue_list_looped(UE_list, g_start_ue_ul); - } + /* just start with the next UE next time */ + g_start_ue_ul = next_ue_list_looped(UE_list, g_start_ue_ul); return rbs[0].length + (num_contig_rb > 1 ? rbs[1].length : 0); } From 31ad66e146b0ceaabe45688e43bf9ae131bfd8ce Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Wed, 24 Jun 2020 14:20:27 +0200 Subject: [PATCH 417/553] Bugfix RR DL: a retx UE might not be allocated again --- openair2/LAYER2/MAC/pre_processor.c | 68 ++++++++++++++--------------- 1 file changed, 33 insertions(+), 35 deletions(-) diff --git a/openair2/LAYER2/MAC/pre_processor.c b/openair2/LAYER2/MAC/pre_processor.c index d4e39b2b6b..eea3b55f6e 100644 --- a/openair2/LAYER2/MAC/pre_processor.c +++ b/openair2/LAYER2/MAC/pre_processor.c @@ -83,15 +83,22 @@ int round_robin_dl(module_id_t Mod_id, const int N_RBG = to_rbg(RC.mac[Mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth); const int RBGsize = get_min_rb_unit(Mod_id, CC_id); const int RBGlastsize = get_rbg_size_last(Mod_id, CC_id); - int num_ue_req = 0; UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; int rbg = 0; for (; !rbgalloc_mask[rbg]; rbg++) ; /* fast-forward to first allowed RBG */ - // Calculate the amount of RBs every UE wants to send. - for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { + /* just start with the UE after the one we had last time. If it does not + * exist, this will start at the head */ + int g_start_ue_dl = data; + g_start_ue_dl = next_ue_list_looped(UE_list, g_start_ue_dl); + + int UE_id = g_start_ue_dl; + UE_list_t UE_sched; + int *cur_UE = &UE_sched.head; + // Allocate retransmissions, and mark UEs with new transmissions + do { // check whether there are HARQ retransmissions const COMMON_channels_t *cc = &RC.mac[Mod_id]->common_channels[CC_id]; const uint8_t harq_pid = frame_subframe2_dl_harq_pid(cc->tdd_Config, frame, subframe); @@ -100,14 +107,14 @@ int round_robin_dl(module_id_t Mod_id, if (round != 8) { // retransmission: allocate const int nb_rb = UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid]; if (nb_rb == 0) - continue; + goto skip_ue; int nb_rbg = (nb_rb + (nb_rb % RBGsize)) / RBGsize; // needs more RBGs than we can allocate if (nb_rbg > n_rbg_sched) { LOG_D(MAC, "retransmission of UE %d needs more RBGs (%d) than we have (%d)\n", UE_id, nb_rbg, n_rbg_sched); - continue; + goto skip_ue; } // ensure that the number of RBs can be contained by the RBGs (!), i.e. // if we allocate the last RBG this one should have the full RBGsize @@ -116,12 +123,12 @@ int round_robin_dl(module_id_t Mod_id, LOG_D(MAC, "retransmission of UE %d needs %d RBs, but the last RBG %d is too small (%d, normal %d)\n", UE_id, nb_rb, N_RBG - 1, RBGlastsize, RBGsize); - continue; + goto skip_ue; } const uint8_t cqi = ue_ctrl->dl_cqi[CC_id]; const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi); if (idx < 0) - continue; // cannot allocate CCE + goto skip_ue; // cannot allocate CCE ue_ctrl->pre_dci_dl_pdu_idx = idx; // retransmissions: directly allocate n_rbg_sched -= nb_rbg; @@ -148,35 +155,32 @@ int round_robin_dl(module_id_t Mod_id, return n_rbg_sched; for (; !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ; } else { - if (UE_info->UE_template[CC_id][UE_id].dl_buffer_total > 0) - num_ue_req++; + if (UE_info->UE_template[CC_id][UE_id].dl_buffer_total > 0) { + *cur_UE = UE_id; + cur_UE = &UE_sched.next[UE_id]; + } } - } - if (num_ue_req == 0) +skip_ue: + UE_id = next_ue_list_looped(UE_list, UE_id); + } while (UE_id != g_start_ue_dl); + *cur_UE = -1; // mark end + + if (UE_sched.head < 0) return n_rbg_sched; // no UE has a transmission - // after allocating retransmissions: build list of UE to allocate. - // if start_UE does not exist anymore (detach etc), start at first UE - if (g_start_ue_dl == -1) - g_start_ue_dl = UE_list->head; - int UE_id = g_start_ue_dl; - UE_list_t UE_sched; - int *cur_UE = &UE_sched.head; - - int num_ue_sched = 0; - max_num_ue = min(min(max_num_ue, num_ue_req), n_rbg_sched); + // after allocating retransmissions: pre-allocate CCE, compute number of + // requested RBGs + max_num_ue = min(max_num_ue, n_rbg_sched); int rb_required[MAX_MOBILES_PER_ENB]; // how much UEs request - while (num_ue_sched < max_num_ue) { - while (UE_info->UE_template[CC_id][UE_id].dl_buffer_total <= 0) - UE_id = next_ue_list_looped(UE_list, UE_id); + cur_UE = &UE_sched.head; + while (*cur_UE >= 0 && max_num_ue > 0) { + const int UE_id = *cur_UE; + cur_UE = &UE_sched.next[UE_id]; // go to next const uint8_t cqi = UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id]; const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi); if (idx < 0) { LOG_D(MAC, "cannot allocate CCE for UE %d, skipping\n", UE_id); - num_ue_req--; - max_num_ue = min(min(max_num_ue, num_ue_req), n_rbg_sched); - UE_id = next_ue_list_looped(UE_list, UE_id); // next candidate continue; } UE_info->UE_sched_ctrl[UE_id].pre_dci_dl_pdu_idx = idx; @@ -184,12 +188,9 @@ int round_robin_dl(module_id_t Mod_id, UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1 = mcs; const uint32_t B = UE_info->UE_template[CC_id][UE_id].dl_buffer_total; rb_required[UE_id] = find_nb_rb_DL(mcs, B, n_rbg_sched * RBGsize, RBGsize); - *cur_UE = UE_id; - cur_UE = &UE_sched.next[UE_id]; - num_ue_sched++; - UE_id = next_ue_list_looped(UE_list, UE_id); // next candidate + max_num_ue--; } - *cur_UE = -1; + *cur_UE = -1; // not all UEs might be allocated, mark end /* for one UE after the next: allocate resources */ cur_UE = &UE_sched.head; @@ -214,9 +215,6 @@ int round_robin_dl(module_id_t Mod_id, for (rbg++; !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ; } - /* just start with the next UE next time */ - g_start_ue_dl = next_ue_list_looped(UE_list, g_start_ue_dl); - return n_rbg_sched; } From dc5357ca13d6dda0768e047168522c503bf3fb4a Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Wed, 17 Jun 2020 11:05:35 +0200 Subject: [PATCH 418/553] Format to dynamically handle default DL SCHED algo --- openair2/LAYER2/MAC/mac.h | 15 +++++++ openair2/LAYER2/MAC/main.c | 6 ++- openair2/LAYER2/MAC/pre_processor.c | 69 +++++++++++++++++++---------- 3 files changed, 65 insertions(+), 25 deletions(-) diff --git a/openair2/LAYER2/MAC/mac.h b/openair2/LAYER2/MAC/mac.h index 329e262c82..0264951683 100644 --- a/openair2/LAYER2/MAC/mac.h +++ b/openair2/LAYER2/MAC/mac.h @@ -1274,6 +1274,19 @@ typedef struct { int length; } contig_rbs_t; +/** + * definition of a scheduling algorithm implementation used in the + * default scheduler + */ +typedef struct { + char *name; + void *(*setup)(void); + void (*unset)(void **); + int (*run)( + module_id_t, int, int, int, UE_list_t *, int, int, uint8_t *, void *); + void *data; +} default_sched_dl_algo_t; + /*! \brief eNB common channels */ typedef struct { int physCellId; @@ -1432,6 +1445,8 @@ typedef struct eNB_MAC_INST_s { UE_free_list_t UE_free_list; /// for scheduling selection SCHEDULER_MODES scheduler_mode; + /// scheduling algorithm used in default scheduler + default_sched_dl_algo_t dl_algo; int32_t puSch10xSnr; int32_t puCch10xSnr; diff --git a/openair2/LAYER2/MAC/main.c b/openair2/LAYER2/MAC/main.c index 1a88623a1f..39e342cba0 100644 --- a/openair2/LAYER2/MAC/main.c +++ b/openair2/LAYER2/MAC/main.c @@ -128,7 +128,11 @@ void mac_top_init_eNB(void) } mac[i]->if_inst = IF_Module_init(i); - + char *s = "round_robin_dl"; + void *d = dlsym(NULL, s); + AssertFatal(d, "%s(): no scheduler algo '%s' found\n", __func__, s); + mac[i]->dl_algo = *(default_sched_dl_algo_t *) d; + mac[i]->dl_algo.data = mac[i]->dl_algo.setup(); init_UE_info(&mac[i]->UE_info); init_slice_info(&mac[i]->slice_info); } diff --git a/openair2/LAYER2/MAC/pre_processor.c b/openair2/LAYER2/MAC/pre_processor.c index eea3b55f6e..8c4b91ce87 100644 --- a/openair2/LAYER2/MAC/pre_processor.c +++ b/openair2/LAYER2/MAC/pre_processor.c @@ -69,15 +69,26 @@ int get_rbg_size_last(module_id_t Mod_id, int CC_id) { return RBGsize; } -int g_start_ue_dl = -1; -int round_robin_dl(module_id_t Mod_id, - int CC_id, - int frame, - int subframe, - UE_list_t *UE_list, - int max_num_ue, - int n_rbg_sched, - uint8_t *rbgalloc_mask) { +void *rr_dl_setup(void) { + void *data = malloc(sizeof(int)); + *(int *) data = 0; + AssertFatal(data, "could not allocate data in %s()\n", __func__); + return data; +} +void rr_dl_unset(void **data) { + if (*data) + free(*data); + *data = NULL; +} +int rr_dl_run(module_id_t Mod_id, + int CC_id, + int frame, + int subframe, + UE_list_t *UE_list, + int max_num_ue, + int n_rbg_sched, + uint8_t *rbgalloc_mask, + void *data) { DevAssert(UE_list->head >= 0); DevAssert(n_rbg_sched > 0); const int N_RBG = to_rbg(RC.mac[Mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth); @@ -91,10 +102,10 @@ int round_robin_dl(module_id_t Mod_id, /* just start with the UE after the one we had last time. If it does not * exist, this will start at the head */ - int g_start_ue_dl = data; - g_start_ue_dl = next_ue_list_looped(UE_list, g_start_ue_dl); + int *start_ue = data; + *start_ue = next_ue_list_looped(UE_list, *start_ue); - int UE_id = g_start_ue_dl; + int UE_id = *start_ue; UE_list_t UE_sched; int *cur_UE = &UE_sched.head; // Allocate retransmissions, and mark UEs with new transmissions @@ -163,7 +174,7 @@ int round_robin_dl(module_id_t Mod_id, skip_ue: UE_id = next_ue_list_looped(UE_list, UE_id); - } while (UE_id != g_start_ue_dl); + } while (UE_id != *start_ue); *cur_UE = -1; // mark end if (UE_sched.head < 0) @@ -217,6 +228,14 @@ skip_ue: return n_rbg_sched; } +default_sched_dl_algo_t round_robin_dl = { + .name = "round_robin_dl", + .setup = rr_dl_setup, + .unset = rr_dl_unset, + .run = rr_dl_run, + .data = NULL +}; + // This function stores the downlink buffer for all the logical channels void @@ -294,8 +313,9 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id, int CC_id, frame_t frameP, sub_frame_t subframeP) { - UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; - const int N_RBG = to_rbg(RC.mac[Mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth); + eNB_MAC_INST *mac = RC.mac[Mod_id]; + UE_info_t *UE_info = &mac->UE_info; + const int N_RBG = to_rbg(mac->common_channels[CC_id].mib->message.dl_Bandwidth); const int RBGsize = get_min_rb_unit(Mod_id, CC_id); store_dlsch_buffer(Mod_id, CC_id, frameP, subframeP); @@ -352,7 +372,7 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id, if (UE_to_sched.head < 0) return; - uint8_t *vrb_map = RC.mac[Mod_id]->common_channels[CC_id].vrb_map; + uint8_t *vrb_map = mac->common_channels[CC_id].vrb_map; uint8_t rbgalloc_mask[N_RBG_MAX]; int n_rbg_sched = 0; for (int i = 0; i < N_RBG; i++) { @@ -364,14 +384,15 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id, n_rbg_sched += rbgalloc_mask[i]; } - round_robin_dl(Mod_id, - CC_id, - frameP, - subframeP, - &UE_to_sched, - 4, // max_num_ue - n_rbg_sched, - rbgalloc_mask); + mac->dl_algo.run(Mod_id, + CC_id, + frameP, + subframeP, + &UE_to_sched, + 4, // max_num_ue + n_rbg_sched, + rbgalloc_mask, + mac->dl_algo.data); // the following block is meant for validation of the pre-processor to check // whether all UE allocations are non-overlapping and is not necessary for From a0b331415fc13ca49f5afbb9203f9ad5ee1fc83c Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Thu, 28 May 2020 16:17:52 +0200 Subject: [PATCH 419/553] Add Proportional Fair scheduler, wbCqi Selects UE with highest coefficient. Allocates until there are no more RBGs to allocate, or UE has no more data. In the latter case, continues with the next UE (second-highest coefficient). --- openair2/LAYER2/MAC/pre_processor.c | 164 ++++++++++++++++++++++++++++ 1 file changed, 164 insertions(+) diff --git a/openair2/LAYER2/MAC/pre_processor.c b/openair2/LAYER2/MAC/pre_processor.c index 8c4b91ce87..5c2b72d199 100644 --- a/openair2/LAYER2/MAC/pre_processor.c +++ b/openair2/LAYER2/MAC/pre_processor.c @@ -237,6 +237,170 @@ default_sched_dl_algo_t round_robin_dl = { }; +void *pf_dl_setup(void) { + void *data = calloc(MAX_MOBILES_PER_ENB, sizeof(float)); + for (int i = 0; i < MAX_MOBILES_PER_ENB; i++) + *(float *) data = 0.0f; + AssertFatal(data, "could not allocate data in %s()\n", __func__); + return data; +} +void pf_dl_unset(void **data) { + if (*data) + free(*data); + *data = NULL; +} +int pf_wbcqi_dl_run(module_id_t Mod_id, + int CC_id, + int frame, + int subframe, + UE_list_t *UE_list, + int max_num_ue, + int n_rbg_sched, + uint8_t *rbgalloc_mask, + void *data) { + DevAssert(UE_list->head >= 0); + DevAssert(n_rbg_sched > 0); + const int N_RBG = to_rbg(RC.mac[Mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth); + const int RBGsize = get_min_rb_unit(Mod_id, CC_id); + const int RBGlastsize = get_rbg_size_last(Mod_id, CC_id); + UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; + + int rbg = 0; + for (; !rbgalloc_mask[rbg]; rbg++) + ; /* fast-forward to first allowed RBG */ + + UE_list_t UE_sched; // UEs that could be scheduled + int *uep = &UE_sched.head; + float *thr_ue = data; + float coeff_ue[MAX_MOBILES_PER_ENB]; + + for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { + const float a = 0.0005f; // corresponds to 200ms window + const uint32_t b = UE_info->eNB_UE_stats[CC_id][UE_id].TBS; + thr_ue[UE_id] = (1 - a) * thr_ue[UE_id] + a * b; + + // check whether there are HARQ retransmissions + const COMMON_channels_t *cc = &RC.mac[Mod_id]->common_channels[CC_id]; + const uint8_t harq_pid = frame_subframe2_dl_harq_pid(cc->tdd_Config, frame, subframe); + UE_sched_ctrl_t *ue_ctrl = &UE_info->UE_sched_ctrl[UE_id]; + const uint8_t round = ue_ctrl->round[CC_id][harq_pid]; + if (round != 8) { // retransmission: allocate + const int nb_rb = UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid]; + if (nb_rb == 0) + continue; + int nb_rbg = (nb_rb + (nb_rb % RBGsize)) / RBGsize; + // needs more RBGs than we can allocate + if (nb_rbg > n_rbg_sched) { + LOG_D(MAC, + "retransmission of UE %d needs more RBGs (%d) than we have (%d)\n", + UE_id, nb_rbg, n_rbg_sched); + continue; + } + // ensure that the number of RBs can be contained by the RBGs (!), i.e. + // if we allocate the last RBG this one should have the full RBGsize + if ((nb_rb % RBGsize) == 0 && nb_rbg == n_rbg_sched + && rbgalloc_mask[N_RBG - 1] && RBGlastsize != RBGsize) { + LOG_D(MAC, + "retransmission of UE %d needs %d RBs, but the last RBG %d is too small (%d, normal %d)\n", + UE_id, nb_rb, N_RBG - 1, RBGlastsize, RBGsize); + continue; + } + const uint8_t cqi = ue_ctrl->dl_cqi[CC_id]; + const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi); + if (idx < 0) + continue; // cannot allocate CCE + ue_ctrl->pre_dci_dl_pdu_idx = idx; + // retransmissions: directly allocate + n_rbg_sched -= nb_rbg; + ue_ctrl->pre_nb_available_rbs[CC_id] += nb_rb; + for (; nb_rbg > 0; rbg++) { + if (!rbgalloc_mask[rbg]) + continue; + ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1; + rbgalloc_mask[rbg] = 0; + nb_rbg--; + } + LOG_D(MAC, + "%4d.%d n_rbg_sched %d after retransmission reservation for UE %d " + "round %d retx nb_rb %d pre_nb_available_rbs %d\n", + frame, subframe, n_rbg_sched, UE_id, round, + UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid], + ue_ctrl->pre_nb_available_rbs[CC_id]); + /* if there are no more RBG to give, return */ + if (n_rbg_sched <= 0) + return 0; + max_num_ue--; + /* if there are no UEs that can be allocated anymore, return */ + if (max_num_ue == 0) + return n_rbg_sched; + for (; !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ; + } else { + if (UE_info->UE_template[CC_id][UE_id].dl_buffer_total == 0) + continue; + + const int mcs = cqi_to_mcs[UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id]]; + const uint32_t tbs = get_TBS_DL(mcs, RBGsize); + coeff_ue[UE_id] = (float) tbs / thr_ue[UE_id]; + //LOG_I(MAC, " pf UE %d: old TBS %d thr %f MCS %d TBS %d coeff %f\n", + // UE_id, b, thr_ue[UE_id], mcs, tbs, coeff_ue[UE_id]); + *uep = UE_id; + uep = &UE_sched.next[UE_id]; + } + } + *uep = -1; + + while (max_num_ue > 0 && n_rbg_sched > 0 && UE_sched.head >= 0) { + int *max = &UE_sched.head; /* assume head is max */ + int *p = &UE_sched.next[*max]; + while (*p >= 0) { + /* if the current one has larger coeff, save for later */ + if (coeff_ue[*p] > coeff_ue[*max]) + max = p; + p = &UE_sched.next[*p]; + } + /* remove the max one */ + const int UE_id = *max; + p = &UE_sched.next[*max]; + *max = UE_sched.next[*max]; + *p = -1; + + const uint8_t cqi = UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id]; + const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi); + if (idx < 0) + continue; + UE_info->UE_sched_ctrl[UE_id].pre_dci_dl_pdu_idx = idx; + + max_num_ue--; + + /* allocate as much as possible */ + const int mcs = cqi_to_mcs[cqi]; + UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1 = mcs; + int req = find_nb_rb_DL(mcs, + UE_info->UE_template[CC_id][UE_id].dl_buffer_total, + n_rbg_sched * RBGsize, + RBGsize); + UE_sched_ctrl_t *ue_ctrl = &UE_info->UE_sched_ctrl[UE_id]; + while (req > 0 && n_rbg_sched > 0) { + ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1; + rbgalloc_mask[rbg] = 0; + const int sRBG = rbg == N_RBG - 1 ? RBGlastsize : RBGsize; + ue_ctrl->pre_nb_available_rbs[CC_id] += sRBG; + req -= sRBG; + n_rbg_sched--; + for (rbg++; n_rbg_sched > 0 && !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ; + } + } + + return n_rbg_sched; +} +default_sched_dl_algo_t proportional_fair_wbcqi_dl = { + .name = "proportional_fair_wbcqi_dl", + .setup = pf_dl_setup, + .unset = pf_dl_unset, + .run = pf_wbcqi_dl_run, + .data = NULL +}; + // This function stores the downlink buffer for all the logical channels void store_dlsch_buffer(module_id_t Mod_id, From 36cd697b626a6133d9c0eecb1dfb8a659640fa4b Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Fri, 22 May 2020 16:43:24 +0200 Subject: [PATCH 420/553] Add Maximum Throughput scheduler, wbCqi Selects the UE with the highest CQI. If two UEs have the same CQI, choses the one with highest number of bytes in RLC queue. Allocates as many RBGs as possible, and potentially continues with the next UE. --- openair2/LAYER2/MAC/pre_processor.c | 150 ++++++++++++++++++++++++++++ 1 file changed, 150 insertions(+) diff --git a/openair2/LAYER2/MAC/pre_processor.c b/openair2/LAYER2/MAC/pre_processor.c index 5c2b72d199..e7adbb7c80 100644 --- a/openair2/LAYER2/MAC/pre_processor.c +++ b/openair2/LAYER2/MAC/pre_processor.c @@ -401,6 +401,156 @@ default_sched_dl_algo_t proportional_fair_wbcqi_dl = { .data = NULL }; +void *mt_dl_setup(void) { + return NULL; +} +void mt_dl_unset(void **data) { + *data = NULL; +} +int mt_wbcqi_dl_run(module_id_t Mod_id, + int CC_id, + int frame, + int subframe, + UE_list_t *UE_list, + int max_num_ue, + int n_rbg_sched, + uint8_t *rbgalloc_mask, + void *data) { + DevAssert(UE_list->head >= 0); + DevAssert(n_rbg_sched > 0); + const int N_RBG = to_rbg(RC.mac[Mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth); + const int RBGsize = get_min_rb_unit(Mod_id, CC_id); + const int RBGlastsize = get_rbg_size_last(Mod_id, CC_id); + UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; + + int rbg = 0; + for (; !rbgalloc_mask[rbg]; rbg++) + ; /* fast-forward to first allowed RBG */ + + UE_list_t UE_sched; // UEs that could be scheduled + int *uep = &UE_sched.head; + + for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { + // check whether there are HARQ retransmissions + const COMMON_channels_t *cc = &RC.mac[Mod_id]->common_channels[CC_id]; + const uint8_t harq_pid = frame_subframe2_dl_harq_pid(cc->tdd_Config, frame, subframe); + UE_sched_ctrl_t *ue_ctrl = &UE_info->UE_sched_ctrl[UE_id]; + const uint8_t round = ue_ctrl->round[CC_id][harq_pid]; + if (round != 8) { // retransmission: allocate + const int nb_rb = UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid]; + if (nb_rb == 0) + continue; + int nb_rbg = (nb_rb + (nb_rb % RBGsize)) / RBGsize; + // needs more RBGs than we can allocate + if (nb_rbg > n_rbg_sched) { + LOG_D(MAC, + "retransmission of UE %d needs more RBGs (%d) than we have (%d)\n", + UE_id, nb_rbg, n_rbg_sched); + continue; + } + // ensure that the number of RBs can be contained by the RBGs (!), i.e. + // if we allocate the last RBG this one should have the full RBGsize + if ((nb_rb % RBGsize) == 0 && nb_rbg == n_rbg_sched + && rbgalloc_mask[N_RBG - 1] && RBGlastsize != RBGsize) { + LOG_D(MAC, + "retransmission of UE %d needs %d RBs, but the last RBG %d is too small (%d, normal %d)\n", + UE_id, nb_rb, N_RBG - 1, RBGlastsize, RBGsize); + continue; + } + const uint8_t cqi = ue_ctrl->dl_cqi[CC_id]; + const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi); + if (idx < 0) + continue; // cannot allocate CCE + ue_ctrl->pre_dci_dl_pdu_idx = idx; + // retransmissions: directly allocate + n_rbg_sched -= nb_rbg; + ue_ctrl->pre_nb_available_rbs[CC_id] += nb_rb; + for (; nb_rbg > 0; rbg++) { + if (!rbgalloc_mask[rbg]) + continue; + ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1; + rbgalloc_mask[rbg] = 0; + nb_rbg--; + } + LOG_D(MAC, + "%4d.%d n_rbg_sched %d after retransmission reservation for UE %d " + "round %d retx nb_rb %d pre_nb_available_rbs %d\n", + frame, subframe, n_rbg_sched, UE_id, round, + UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid], + ue_ctrl->pre_nb_available_rbs[CC_id]); + /* if there are no more RBG to give, return */ + if (n_rbg_sched <= 0) + return 0; + max_num_ue--; + /* if there are no UEs that can be allocated anymore, return */ + if (max_num_ue == 0) + return n_rbg_sched; + for (; !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ; + } else { + if (UE_info->UE_template[CC_id][UE_id].dl_buffer_total == 0) + continue; + *uep = UE_id; + uep = &UE_sched.next[UE_id]; + } + } + *uep = -1; + + while (max_num_ue > 0 && n_rbg_sched > 0 && UE_sched.head >= 0) { + int *max = &UE_sched.head; /* assume head is max */ + int *p = &UE_sched.next[*max]; + while (*p >= 0) { + /* if the current one has better CQI, or the same and more data */ + const uint8_t maxCqi = UE_info->UE_sched_ctrl[*max].dl_cqi[CC_id]; + const uint32_t maxB = UE_info->UE_template[CC_id][*max].dl_buffer_total; + const uint8_t pCqi = UE_info->UE_sched_ctrl[*p].dl_cqi[CC_id]; + const uint32_t pB = UE_info->UE_template[CC_id][*p].dl_buffer_total; + if (pCqi > maxCqi || (pCqi == maxCqi && pB > maxB)) + max = p; + p = &UE_sched.next[*p]; + } + /* remove the max one */ + const int UE_id = *max; + p = &UE_sched.next[*max]; + *max = UE_sched.next[*max]; + *p = -1; + + const uint8_t cqi = UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id]; + const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi); + if (idx < 0) + continue; + UE_info->UE_sched_ctrl[UE_id].pre_dci_dl_pdu_idx = idx; + + max_num_ue--; + + /* allocate as much as possible */ + const int mcs = cqi_to_mcs[cqi]; + UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1 = mcs; + int req = find_nb_rb_DL(mcs, + UE_info->UE_template[CC_id][UE_id].dl_buffer_total, + n_rbg_sched * RBGsize, + RBGsize); + UE_sched_ctrl_t *ue_ctrl = &UE_info->UE_sched_ctrl[UE_id]; + while (req > 0 && n_rbg_sched > 0) { + ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1; + rbgalloc_mask[rbg] = 0; + const int sRBG = rbg == N_RBG - 1 ? RBGlastsize : RBGsize; + ue_ctrl->pre_nb_available_rbs[CC_id] += sRBG; + req -= sRBG; + n_rbg_sched--; + for (rbg++; n_rbg_sched > 0 && !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ; + } + } + + return n_rbg_sched; +} +default_sched_dl_algo_t maximum_throughput_wbcqi_dl = { + .name = "maximum_throughput_wbcqi_dl", + .setup = mt_dl_setup, + .unset = mt_dl_unset, + .run = mt_wbcqi_dl_run, + .data = NULL +}; + // This function stores the downlink buffer for all the logical channels void store_dlsch_buffer(module_id_t Mod_id, From 5d1d2bcd1c17e6e12d36e94f77babd8d7a8c4da5 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Wed, 17 Jun 2020 18:40:48 +0200 Subject: [PATCH 421/553] Configurable Default Scheduler DL Algo --- openair2/ENB_APP/MACRLC_paramdef.h | 3 +++ openair2/ENB_APP/enb_config.c | 10 ++++++++++ 2 files changed, 13 insertions(+) diff --git a/openair2/ENB_APP/MACRLC_paramdef.h b/openair2/ENB_APP/MACRLC_paramdef.h index 55ce9d5059..fcee6142f0 100644 --- a/openair2/ENB_APP/MACRLC_paramdef.h +++ b/openair2/ENB_APP/MACRLC_paramdef.h @@ -58,6 +58,7 @@ #define CONFIG_STRING_MACRLC_SCHED_MODE "scheduler_mode" #define CONFIG_MACRLC_PUSCH10xSNR "puSch10xSnr" #define CONFIG_MACRLC_PUCCH10xSNR "puCch10xSnr" +#define CONFIG_STRING_MACRLC_DEFAULT_SCHED_DL_ALGO "default_sched_dl_algo" /*-------------------------------------------------------------------------------------------------------------------------------------------------------*/ /* MacRLC configuration parameters */ @@ -84,6 +85,7 @@ {CONFIG_STRING_MACRLC_SCHED_MODE, NULL, 0, strptr:NULL, defstrval:"default", TYPE_STRING, 0}, \ {CONFIG_MACRLC_PUSCH10xSNR, NULL, 0, iptr:NULL, defintval:200, TYPE_INT, 0}, \ {CONFIG_MACRLC_PUCCH10xSNR, NULL, 0, iptr:NULL, defintval:200, TYPE_INT, 0}, \ +{CONFIG_STRING_MACRLC_DEFAULT_SCHED_DL_ALGO, NULL, 0, strptr:NULL, defstrval:"round_robin_dl", TYPE_STRING, 0}, \ } #define MACRLC_CC_IDX 0 #define MACRLC_TRANSPORT_N_PREFERENCE_IDX 1 @@ -105,6 +107,7 @@ #define MACRLC_SCHED_MODE_IDX 17 #define MACRLC_PUSCH10xSNR_IDX 18 #define MACRLC_PUCCH10xSNR_IDX 19 +#define MACRLC_DEFAULT_SCHED_DL_ALGO_IDX 20 /*---------------------------------------------------------------------------------------------------------------------------------------------------------*/ #endif diff --git a/openair2/ENB_APP/enb_config.c b/openair2/ENB_APP/enb_config.c index 6dcc574746..3bde7da02c 100644 --- a/openair2/ENB_APP/enb_config.c +++ b/openair2/ENB_APP/enb_config.c @@ -29,6 +29,7 @@ #include #include +#include #include "common/utils/LOG/log.h" #include "assertions.h" @@ -260,6 +261,15 @@ void RCconfig_macrlc(int macrlc_has_f1[MAX_MAC_INST]) { global_scheduler_mode=SCHED_MODE_DEFAULT; printf("sched mode = default %d [%s]\n",global_scheduler_mode,*(MacRLC_ParamList.paramarray[j][MACRLC_SCHED_MODE_IDX].strptr)); } + + char *s = *MacRLC_ParamList.paramarray[j][MACRLC_DEFAULT_SCHED_DL_ALGO_IDX].strptr; + void *d = dlsym(NULL, s); + AssertFatal(d, "%s(): no default scheduler DL algo '%s' found\n", __func__, s); + // release default, add new + RC.mac[j]->dl_algo.unset(&RC.mac[j]->dl_algo.data); + RC.mac[j]->dl_algo = *(default_sched_dl_algo_t *) d; + RC.mac[j]->dl_algo.data = RC.mac[j]->dl_algo.setup(); + LOG_I(ENB_APP, "using default scheduler DL algo '%s'\n", RC.mac[j]->dl_algo.name); }// j=0..num_inst } /*else {// MacRLC_ParamList.numelt > 0 // ignore it From 41de51b18744901df1368ae700b4b639d832d987 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Thu, 18 Jun 2020 17:32:01 +0200 Subject: [PATCH 422/553] Format to dynamically handle UL SCHED --- openair2/LAYER2/MAC/mac.h | 16 +++++- openair2/LAYER2/MAC/main.c | 5 ++ openair2/LAYER2/MAC/pre_processor.c | 79 ++++++++++++++++++----------- 3 files changed, 70 insertions(+), 30 deletions(-) diff --git a/openair2/LAYER2/MAC/mac.h b/openair2/LAYER2/MAC/mac.h index 0264951683..09585fae55 100644 --- a/openair2/LAYER2/MAC/mac.h +++ b/openair2/LAYER2/MAC/mac.h @@ -1276,7 +1276,7 @@ typedef struct { /** * definition of a scheduling algorithm implementation used in the - * default scheduler + * default DL scheduler */ typedef struct { char *name; @@ -1287,6 +1287,19 @@ typedef struct { void *data; } default_sched_dl_algo_t; +/** + * definition of a scheduling algorithm implementation used in the + * default UL scheduler + */ +typedef struct { + char *name; + void *(*setup)(void); + void (*unset)(void **); + int (*run)( + module_id_t, int, int, int, int, int, UE_list_t *, int, int, contig_rbs_t *, void *); + void *data; +} default_sched_ul_algo_t; + /*! \brief eNB common channels */ typedef struct { int physCellId; @@ -1447,6 +1460,7 @@ typedef struct eNB_MAC_INST_s { SCHEDULER_MODES scheduler_mode; /// scheduling algorithm used in default scheduler default_sched_dl_algo_t dl_algo; + default_sched_ul_algo_t ul_algo; int32_t puSch10xSnr; int32_t puCch10xSnr; diff --git a/openair2/LAYER2/MAC/main.c b/openair2/LAYER2/MAC/main.c index 39e342cba0..294eb12159 100644 --- a/openair2/LAYER2/MAC/main.c +++ b/openair2/LAYER2/MAC/main.c @@ -133,6 +133,11 @@ void mac_top_init_eNB(void) AssertFatal(d, "%s(): no scheduler algo '%s' found\n", __func__, s); mac[i]->dl_algo = *(default_sched_dl_algo_t *) d; mac[i]->dl_algo.data = mac[i]->dl_algo.setup(); + s = "round_robin_ul"; + d = dlsym(NULL, s); + AssertFatal(d, "%s(): no scheduler algo '%s' found\n", __func__, s); + mac[i]->ul_algo = *(default_sched_ul_algo_t *) d; + mac[i]->ul_algo.data = mac[i]->ul_algo.setup(); init_UE_info(&mac[i]->UE_info); init_slice_info(&mac[i]->slice_info); } diff --git a/openair2/LAYER2/MAC/pre_processor.c b/openair2/LAYER2/MAC/pre_processor.c index e7adbb7c80..72455f7125 100644 --- a/openair2/LAYER2/MAC/pre_processor.c +++ b/openair2/LAYER2/MAC/pre_processor.c @@ -818,17 +818,28 @@ int pp_find_rb_table_index(int approximate) { return p + 1; } -int g_start_ue_ul = -1; -int round_robin_ul(module_id_t Mod_id, - int CC_id, - int frame, - int subframe, - int sched_frame, - int sched_subframe, - UE_list_t *UE_list, - int max_num_ue, - int num_contig_rb, - contig_rbs_t *rbs) { +void *rr_ul_setup(void) { + void *data = malloc(sizeof(int)); + *(int *) data = 0; + AssertFatal(data, "could not allocate data in %s()\n", __func__); + return data; +} +void rr_ul_unset(void **data) { + if (*data) + free(*data); + *data = NULL; +} +int rr_ul_run(module_id_t Mod_id, + int CC_id, + int frame, + int subframe, + int sched_frame, + int sched_subframe, + UE_list_t *UE_list, + int max_num_ue, + int num_contig_rb, + contig_rbs_t *rbs, + void *data) { AssertFatal(num_contig_rb <= 2, "cannot handle more than two contiguous RB regions\n"); UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; const int max_rb = num_contig_rb > 1 ? MAX(rbs[0].length, rbs[1].length) : rbs[0].length; @@ -968,9 +979,10 @@ int round_robin_ul(module_id_t Mod_id, end = la > lb ? 2 : -1; } - if (g_start_ue_ul == -1) - g_start_ue_ul = UE_list->head; - int sUE_id = g_start_ue_ul; + int *start_ue = data; + if (*start_ue == -1) + *start_ue = UE_list->head; + int sUE_id = *start_ue; int rb_idx_given[MAX_MOBILES_PER_ENB]; memset(rb_idx_given, 0, sizeof(rb_idx_given)); @@ -1049,10 +1061,17 @@ int round_robin_ul(module_id_t Mod_id, } /* just start with the next UE next time */ - g_start_ue_ul = next_ue_list_looped(UE_list, g_start_ue_ul); + *start_ue = next_ue_list_looped(UE_list, *start_ue); return rbs[0].length + (num_contig_rb > 1 ? rbs[1].length : 0); } +default_sched_ul_algo_t round_robin_ul = { + .name = "round_robin_ul", + .setup = rr_ul_setup, + .unset = rr_ul_unset, + .run = rr_ul_run, + .data = NULL +}; void ulsch_scheduler_pre_processor(module_id_t Mod_id, int CC_id, @@ -1060,9 +1079,10 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id, sub_frame_t subframeP, int sched_frameP, unsigned char sched_subframeP) { - UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; - const int N_RB_UL = to_prb(RC.mac[Mod_id]->common_channels[CC_id].ul_Bandwidth); - COMMON_channels_t *cc = &RC.mac[Mod_id]->common_channels[CC_id]; + eNB_MAC_INST *mac = RC.mac[Mod_id]; + UE_info_t *UE_info = &mac->UE_info; + const int N_RB_UL = to_prb(mac->common_channels[CC_id].ul_Bandwidth); + COMMON_channels_t *cc = &mac->common_channels[CC_id]; UE_list_t UE_to_sched; UE_to_sched.head = -1; @@ -1119,16 +1139,17 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id, } } - round_robin_ul(Mod_id, - CC_id, - frameP, - subframeP, - sched_frameP, - sched_subframeP, - &UE_to_sched, - 4, // max_num_ue - n_contig, - rbs); + mac->ul_algo.run(Mod_id, + CC_id, + frameP, + subframeP, + sched_frameP, + sched_subframeP, + &UE_to_sched, + 4, // max_num_ue + n_contig, + rbs, + mac->ul_algo.data); // the following block is meant for validation of the pre-processor to check // whether all UE allocations are non-overlapping and is not necessary for @@ -1147,7 +1168,7 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id, continue; print = 1; - uint8_t harq_pid = subframe2harqpid(&RC.mac[Mod_id]->common_channels[CC_id], + uint8_t harq_pid = subframe2harqpid(&mac->common_channels[CC_id], sched_frameP, sched_subframeP); LOG_D(MAC, "%4d.%d UE%d %d RBs (index %d) at start %d, pre MCS %d %s\n", frameP, From 9f26028ded0201efb7906c682568eb1519f4eb12 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Tue, 23 Jun 2020 10:27:45 +0200 Subject: [PATCH 423/553] Default pre-processor: efficiently build UE list --- openair2/LAYER2/MAC/pre_processor.c | 27 ++++++++------------------- 1 file changed, 8 insertions(+), 19 deletions(-) diff --git a/openair2/LAYER2/MAC/pre_processor.c b/openair2/LAYER2/MAC/pre_processor.c index 72455f7125..5eb27699be 100644 --- a/openair2/LAYER2/MAC/pre_processor.c +++ b/openair2/LAYER2/MAC/pre_processor.c @@ -635,12 +635,10 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id, store_dlsch_buffer(Mod_id, CC_id, frameP, subframeP); UE_list_t UE_to_sched; - UE_to_sched.head = -1; for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) UE_to_sched.next[i] = -1; + int *cur = &UE_to_sched.head; - int first = 1; - int last_UE_id = -1; for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { UE_sched_ctrl_t *ue_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; const UE_TEMPLATE *ue_template = &UE_info->UE_template[CC_id][UE_id]; @@ -673,15 +671,10 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id, } /* define UEs to schedule */ - if (first) { - first = 0; - UE_to_sched.head = UE_id; - } else { - UE_to_sched.next[last_UE_id] = UE_id; - } - UE_to_sched.next[UE_id] = -1; - last_UE_id = UE_id; + *cur = UE_id; + cur = &UE_to_sched.next[UE_id]; } + *cur = -1; if (UE_to_sched.head < 0) return; @@ -1085,11 +1078,10 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id, COMMON_channels_t *cc = &mac->common_channels[CC_id]; UE_list_t UE_to_sched; - UE_to_sched.head = -1; for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) UE_to_sched.next[i] = -1; + int *cur = &UE_to_sched.head; - int last_UE_id = -1; for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { UE_TEMPLATE *UE_template = &UE_info->UE_template[CC_id][UE_id]; UE_sched_ctrl_t *ue_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; @@ -1112,13 +1104,10 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id, continue; /* define UEs to schedule */ - if (UE_to_sched.head < 0) - UE_to_sched.head = UE_id; - else - UE_to_sched.next[last_UE_id] = UE_id; - UE_to_sched.next[UE_id] = -1; - last_UE_id = UE_id; + *cur = UE_id; + cur = &UE_to_sched.next[UE_id]; } + *cur = -1; if (UE_to_sched.head < 0) return; From 198822aa17cc47b8b563491f2a76bb0d4da51813 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Sun, 12 Apr 2020 12:00:43 +0200 Subject: [PATCH 424/553] Remove any slice-related information from OAI --- .../CONTROL_MODULES/MAC/flexran_agent_mac.c | 13 - .../MAC/flexran_agent_mac_internal.c | 28 +- .../flexran_agent_mac_slice_verification.c | 4 +- openair2/ENB_APP/flexran_agent_ran_api.c | 314 ++---------------- openair2/LAYER2/MAC/mac.h | 104 ------ openair2/LAYER2/MAC/mac_proto.h | 2 - openair2/LAYER2/MAC/main.c | 27 -- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 2 - 8 files changed, 39 insertions(+), 455 deletions(-) diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c index 603ff25198..669eb33ea3 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c @@ -49,19 +49,6 @@ struct lfds700_misc_prng_state ps[NUM_MAX_ENB]; struct lfds700_ringbuffer_element *dl_mac_config_array[NUM_MAX_ENB]; struct lfds700_ringbuffer_state ringbuffer_state[NUM_MAX_ENB]; -/* the slice config as kept in the underlying system */ -Protocol__FlexSliceConfig *slice_config[MAX_NUM_SLICES]; -/* a structure that keeps updates which will be reflected in slice_config later */ -Protocol__FlexSliceConfig *sc_update[MAX_NUM_SLICES]; -/* indicates whether sc_update contains new data */ -int perform_slice_config_update_count = 1; -/* queue of incoming new UE<>slice association commands */ -Protocol__FlexUeConfig *ue_slice_assoc_update[MAX_NUM_SLICES]; -int n_ue_slice_assoc_updates = 0; -/* mutex for sc_update: do not receive new config and write it at the same time */ -pthread_mutex_t sc_update_mtx = PTHREAD_MUTEX_INITIALIZER; - - int flexran_agent_mac_stats_reply_ue(mid_t mod_id, Protocol__FlexUeStatsReport **ue_report, int n_ue, diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c index a85cbac543..84a28683b7 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c @@ -33,14 +33,6 @@ #include "flexran_agent_mac_internal.h" #include "flexran_agent_mac_slice_verification.h" -/* from flexran_agent_mac.c */ -extern Protocol__FlexSliceConfig *slice_config[MAX_NUM_SLICES]; -extern Protocol__FlexSliceConfig *sc_update[MAX_NUM_SLICES]; -extern int perform_slice_config_update_count; -extern Protocol__FlexUeConfig *ue_slice_assoc_update[MAX_NUM_SLICES]; -extern int n_ue_slice_assoc_updates; -extern pthread_mutex_t sc_update_mtx; - Protocol__FlexranMessage * flexran_agent_generate_diff_mac_stats_report(Protocol__FlexranMessage *new_message, Protocol__FlexranMessage *old_message) { @@ -1040,12 +1032,12 @@ Protocol__FlexSliceConfig *flexran_agent_create_slice_config(int n_dl, int m_ul) if (!fsc) return NULL; protocol__flex_slice_config__init(fsc); - /* say there are n_dl slices but reserve memory for up to MAX_NUM_SLICES so + /* say there are n_dl slices but reserve memory for up to 10 so * we don't need to reserve again later */ fsc->n_dl = n_dl; - fsc->dl = calloc(MAX_NUM_SLICES, sizeof(Protocol__FlexDlSlice *)); + fsc->dl = calloc(10, sizeof(Protocol__FlexDlSlice *)); if (!fsc->dl) fsc->n_dl = 0; - for (i = 0; i < MAX_NUM_SLICES; i++) { + for (i = 0; i < 10; i++) { fsc->dl[i] = malloc(sizeof(Protocol__FlexDlSlice)); if (!fsc->dl[i]) continue; protocol__flex_dl_slice__init(fsc->dl[i]); @@ -1053,9 +1045,9 @@ Protocol__FlexSliceConfig *flexran_agent_create_slice_config(int n_dl, int m_ul) /* as above */ fsc->n_ul = m_ul; - fsc->ul = calloc(MAX_NUM_SLICES, sizeof(Protocol__FlexUlSlice *)); + fsc->ul = calloc(10, sizeof(Protocol__FlexUlSlice *)); if (!fsc->ul) fsc->n_ul = 0; - for (i = 0; i < MAX_NUM_SLICES; i++) { + for (i = 0; i < 10; i++) { fsc->ul[i] = malloc(sizeof(Protocol__FlexUlSlice)); if (!fsc->ul[i]) continue; protocol__flex_ul_slice__init(fsc->ul[i]); @@ -1401,8 +1393,8 @@ Protocol__FlexDlSlice *create_new_dl_slice(mid_t mod_id, int id) mod_id, id); Protocol__FlexDlSlice *to = sc_update[mod_id]->dl[sc_update[mod_id]->n_dl]; sc_update[mod_id]->n_dl++; - AssertFatal(sc_update[mod_id]->n_dl <= MAX_NUM_SLICES, - "cannot create more than MAX_NUM_SLICES\n"); + AssertFatal(sc_update[mod_id]->n_dl <= 10, + "cannot create more than 10\n"); to->id = id; return to; } @@ -1468,8 +1460,8 @@ Protocol__FlexUlSlice *create_new_ul_slice(mid_t mod_id, int id) mod_id, id); Protocol__FlexUlSlice *to = sc_update[mod_id]->ul[sc_update[mod_id]->n_ul]; sc_update[mod_id]->n_ul++; - AssertFatal(sc_update[mod_id]->n_ul <= MAX_NUM_SLICES, - "cannot create more than MAX_NUM_SLICES\n"); + AssertFatal(sc_update[mod_id]->n_ul <= 10, + "cannot create more than 10\n"); to->id = id; return to; } @@ -1698,7 +1690,7 @@ int apply_new_slice_ul_config(mid_t mod_id, Protocol__FlexUlSlice *oldc, Protoco void prepare_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig *ue_config) { - if (n_ue_slice_assoc_updates == MAX_NUM_SLICES) { + if (n_ue_slice_assoc_updates == 10) { LOG_E(FLEXRAN_AGENT, "[%d] can not handle flex_ue_config message, buffer is full; try again later\n", mod_id); diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.c index 67329e91be..f7f60541f5 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.c +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.c @@ -132,7 +132,7 @@ int flexran_verify_group_dl_slices(mid_t mod_id, Protocol__FlexDlSlice **existin /* else "only" an update */ } - if (n < 1 || n > MAX_NUM_SLICES) { + if (n < 1 || n > 10) { LOG_E(FLEXRAN_AGENT, "[%d] Illegal number of resulting DL slices (%d -> %d)\n", mod_id, n_ex, n); return 0; @@ -253,7 +253,7 @@ int flexran_verify_group_ul_slices(mid_t mod_id, Protocol__FlexUlSlice **existin /* else "only" an update */ } - if (n < 1 || n > MAX_NUM_SLICES) { + if (n < 1 || n > 10) { LOG_E(FLEXRAN_AGENT, "[%d] Illegal number of resulting UL slices (%d -> %d)\n", mod_id, n_ex, n); return 0; diff --git a/openair2/ENB_APP/flexran_agent_ran_api.c b/openair2/ENB_APP/flexran_agent_ran_api.c index 0fcc51782e..291c4dc7d8 100644 --- a/openair2/ENB_APP/flexran_agent_ran_api.c +++ b/openair2/ENB_APP/flexran_agent_ran_api.c @@ -3015,469 +3015,209 @@ uint32_t flexran_get_rrc_enb_ue_s1ap_id(mid_t mod_id, rnti_t rnti) /**************************** SLICING ****************************/ int flexran_get_ue_dl_slice_id(mid_t mod_id, mid_t ue_id) { if (!mac_is_present(mod_id)) return -1; - - int slice_idx = 0; //RC.mac[mod_id]->UE_info.assoc_dl_slice_idx[ue_id]; - - if (slice_idx >= 0 && slice_idx < RC.mac[mod_id]->slice_info.n_dl) - return RC.mac[mod_id]->slice_info.dl[slice_idx].id; - return 0; } void flexran_set_ue_dl_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx) { if (!mac_is_present(mod_id)) return; - - if (flexran_get_mac_ue_crnti(mod_id, ue_id) == NOT_A_RNTI) return; - - if (!flexran_dl_slice_exists(mod_id, slice_idx)) return; - - //RC.mac[mod_id]->UE_info.assoc_dl_slice_idx[ue_id] = slice_idx; } int flexran_get_ue_ul_slice_id(mid_t mod_id, mid_t ue_id) { if (!mac_is_present(mod_id)) return -1; - - int slice_idx = 0; //RC.mac[mod_id]->UE_info.assoc_ul_slice_idx[ue_id]; - - if (slice_idx >= 0 && slice_idx < RC.mac[mod_id]->slice_info.n_ul) - return RC.mac[mod_id]->slice_info.ul[slice_idx].id; - return 0; } void flexran_set_ue_ul_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx) { if (!mac_is_present(mod_id)) return; - - if (flexran_get_mac_ue_crnti(mod_id, ue_id) == NOT_A_RNTI) return; - - if (!flexran_ul_slice_exists(mod_id, slice_idx)) return; - - //RC.mac[mod_id]->UE_info.assoc_ul_slice_idx[ue_id] = slice_idx; } int flexran_dl_slice_exists(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - return slice_idx >= 0 && slice_idx < RC.mac[mod_id]->slice_info.n_dl; + return 0; } int flexran_create_dl_slice(mid_t mod_id, slice_id_t slice_id) { if (!mac_is_present(mod_id)) return -1; - - int newidx = RC.mac[mod_id]->slice_info.n_dl; - - if (newidx >= MAX_NUM_SLICES) return -1; - - ++RC.mac[mod_id]->slice_info.n_dl; - flexran_set_dl_slice_id(mod_id, newidx, slice_id); - return newidx; + return -1; } int flexran_find_dl_slice(mid_t mod_id, slice_id_t slice_id) { if (!mac_is_present(mod_id)) return -1; - - slice_info_t *sli = &RC.mac[mod_id]->slice_info; - int n = sli->n_dl; - - for (int i = 0; i < n; i++) { - if (sli->dl[i].id == slice_id) return i; - } - return -1; } int flexran_remove_dl_slice(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - slice_info_t *sli = &RC.mac[mod_id]->slice_info; - - if (sli->n_dl <= 1) return -1; - - if (sli->dl[slice_idx].sched_name) free(sli->dl[slice_idx].sched_name); - - --sli->n_dl; - - /* move last element to the position of the removed one */ - if (slice_idx != sli->n_dl) - memcpy(&sli->dl[slice_idx], &sli->dl[sli->n_dl], sizeof(sli->dl[sli->n_dl])); - - memset(&sli->dl[sli->n_dl], 0, sizeof(sli->dl[sli->n_dl])); - /* all UEs that have been in the old slice are put into slice index 0 */ - //int *assoc_list = RC.mac[mod_id]->UE_info.assoc_dl_slice_idx; - - //for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) { - // if (assoc_list[i] == slice_idx) - // assoc_list[i] = 0; - //} - - return 1; + return -1; } int flexran_get_num_dl_slices(mid_t mod_id) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.n_dl; + return 0; } int flexran_get_intraslice_sharing_active(mid_t mod_id) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.intraslice_share_active; + return -1; } void flexran_set_intraslice_sharing_active(mid_t mod_id, int intraslice_active) { if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.intraslice_share_active = intraslice_active; } int flexran_get_interslice_sharing_active(mid_t mod_id) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.interslice_share_active; + return -1; } void flexran_set_interslice_sharing_active(mid_t mod_id, int interslice_active) { if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.interslice_share_active = interslice_active; } slice_id_t flexran_get_dl_slice_id(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.dl[slice_idx].id; + return -1; } void flexran_set_dl_slice_id(mid_t mod_id, int slice_idx, slice_id_t slice_id) { if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.dl[slice_idx].id = slice_id; } int flexran_get_dl_slice_percentage(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.dl[slice_idx].pct * 100.0f; + return -1; } void flexran_set_dl_slice_percentage(mid_t mod_id, int slice_idx, int percentage) { if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.dl[slice_idx].pct = percentage / 100.0f; } int flexran_get_dl_slice_isolation(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.dl[slice_idx].isol; + return -1; } void flexran_set_dl_slice_isolation(mid_t mod_id, int slice_idx, int is_isolated) { if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.dl[slice_idx].isol = is_isolated; } int flexran_get_dl_slice_priority(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.dl[slice_idx].prio; + return -1; } void flexran_set_dl_slice_priority(mid_t mod_id, int slice_idx, int priority) { if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.dl[slice_idx].prio = priority; } int flexran_get_dl_slice_position_low(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.dl[slice_idx].pos_low; + return -1; } void flexran_set_dl_slice_position_low(mid_t mod_id, int slice_idx, int poslow) { if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.dl[slice_idx].pos_low = poslow; } int flexran_get_dl_slice_position_high(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.dl[slice_idx].pos_high; + return -1; } void flexran_set_dl_slice_position_high(mid_t mod_id, int slice_idx, int poshigh) { if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.dl[slice_idx].pos_high = poshigh; } int flexran_get_dl_slice_maxmcs(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.dl[slice_idx].maxmcs; + return -1; } void flexran_set_dl_slice_maxmcs(mid_t mod_id, int slice_idx, int maxmcs) { if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.dl[slice_idx].maxmcs = maxmcs; } int flexran_get_dl_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexDlSorting **sorting_list) { if (!mac_is_present(mod_id)) return -1; - - if (!(*sorting_list)) { - *sorting_list = calloc(CR_NUM, sizeof(Protocol__FlexDlSorting)); - - if (!(*sorting_list)) return -1; - } - - uint32_t policy = RC.mac[mod_id]->slice_info.dl[slice_idx].sorting; - - for (int i = 0; i < CR_NUM; i++) { - switch (policy >> 4 * (CR_NUM - 1 - i) & 0xF) { - case CR_ROUND: - (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_ROUND; - break; - - case CR_SRB12: - (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_SRB12; - break; - - case CR_HOL: - (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_HOL; - break; - - case CR_LC: - (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_LC; - break; - - case CR_CQI: - (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_CQI; - break; - - case CR_LCP: - (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_LCP; - break; - - default: - /* this should not happen, but a "default" */ - (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_ROUND; - break; - } - } - - return CR_NUM; + return -1; } void flexran_set_dl_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexDlSorting *sorting_list, int n) { if (!mac_is_present(mod_id)) return; - - uint32_t policy = 0; - - for (int i = 0; i < n && i < CR_NUM; i++) { - switch (sorting_list[i]) { - case PROTOCOL__FLEX_DL_SORTING__CR_ROUND: - policy = policy << 4 | CR_ROUND; - break; - - case PROTOCOL__FLEX_DL_SORTING__CR_SRB12: - policy = policy << 4 | CR_SRB12; - break; - - case PROTOCOL__FLEX_DL_SORTING__CR_HOL: - policy = policy << 4 | CR_HOL; - break; - - case PROTOCOL__FLEX_DL_SORTING__CR_LC: - policy = policy << 4 | CR_LC; - break; - - case PROTOCOL__FLEX_DL_SORTING__CR_CQI: - policy = policy << 4 | CR_CQI; - break; - - case PROTOCOL__FLEX_DL_SORTING__CR_LCP: - policy = policy << 4 | CR_LCP; - break; - - default: /* suppresses warnings */ - policy = policy << 4 | CR_ROUND; - break; - } - } - - /* fill up with 0 == CR_ROUND */ - if (CR_NUM > n) policy = policy << 4 * (CR_NUM - n); - - RC.mac[mod_id]->slice_info.dl[slice_idx].sorting = policy; } Protocol__FlexDlAccountingPolicy flexran_get_dl_slice_accounting_policy(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_FAIR; - - switch (RC.mac[mod_id]->slice_info.dl[slice_idx].accounting) { - case POL_FAIR: - return PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_FAIR; - - case POL_GREEDY: - return PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_GREEDY; - - default: - return PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_FAIR; - } + return PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_FAIR; } void flexran_set_dl_slice_accounting_policy(mid_t mod_id, int slice_idx, Protocol__FlexDlAccountingPolicy accounting) { if (!mac_is_present(mod_id)) return; - - switch (accounting) { - case PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_FAIR: - RC.mac[mod_id]->slice_info.dl[slice_idx].accounting = POL_FAIR; - return; - - case PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_GREEDY: - RC.mac[mod_id]->slice_info.dl[slice_idx].accounting = POL_GREEDY; - return; - - default: - RC.mac[mod_id]->slice_info.dl[slice_idx].accounting = POL_FAIR; - return; - } } char *flexran_get_dl_slice_scheduler(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return NULL; - - return RC.mac[mod_id]->slice_info.dl[slice_idx].sched_name; + return NULL; } int flexran_set_dl_slice_scheduler(mid_t mod_id, int slice_idx, char *name) { if (!mac_is_present(mod_id)) return 0; - - if (RC.mac[mod_id]->slice_info.dl[slice_idx].sched_name) - free(RC.mac[mod_id]->slice_info.dl[slice_idx].sched_name); - - RC.mac[mod_id]->slice_info.dl[slice_idx].sched_name = strdup(name); - RC.mac[mod_id]->slice_info.dl[slice_idx].sched_cb = dlsym(NULL, name); - return RC.mac[mod_id]->slice_info.dl[slice_idx].sched_cb != NULL; + return 0; } int flexran_create_ul_slice(mid_t mod_id, slice_id_t slice_id) { if (!mac_is_present(mod_id)) return -1; - - int newidx = RC.mac[mod_id]->slice_info.n_ul; - - if (newidx >= MAX_NUM_SLICES) return -1; - - ++RC.mac[mod_id]->slice_info.n_ul; - flexran_set_ul_slice_id(mod_id, newidx, slice_id); - return newidx; + return -1; } int flexran_find_ul_slice(mid_t mod_id, slice_id_t slice_id) { if (!mac_is_present(mod_id)) return -1; - - slice_info_t *sli = &RC.mac[mod_id]->slice_info; - int n = sli->n_ul; - - for (int i = 0; i < n; i++) { - if (sli->ul[i].id == slice_id) return i; - } - return -1; } int flexran_remove_ul_slice(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - slice_info_t *sli = &RC.mac[mod_id]->slice_info; - - if (sli->n_ul <= 1) return -1; - - if (sli->ul[slice_idx].sched_name) free(sli->ul[slice_idx].sched_name); - - --sli->n_ul; - - /* move last element to the position of the removed one */ - if (slice_idx != sli->n_ul) - memcpy(&sli->ul[slice_idx], &sli->ul[sli->n_ul], sizeof(sli->ul[sli->n_ul])); - - memset(&sli->ul[sli->n_ul], 0, sizeof(sli->ul[sli->n_ul])); - /* all UEs that have been in the old slice are put into slice index 0 */ - //int *assoc_list = RC.mac[mod_id]->UE_info.assoc_ul_slice_idx; - - //for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) { - // if (assoc_list[i] == slice_idx) - // assoc_list[i] = 0; - //} - - return sli->n_ul; + return -1; } int flexran_get_num_ul_slices(mid_t mod_id) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.n_ul; + return 0; } int flexran_ul_slice_exists(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - return slice_idx >= 0 && slice_idx < RC.mac[mod_id]->slice_info.n_ul; + return 0; } slice_id_t flexran_get_ul_slice_id(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.ul[slice_idx].id; + return -1; } void flexran_set_ul_slice_id(mid_t mod_id, int slice_idx, slice_id_t slice_id) { if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.ul[slice_idx].id = slice_id; } int flexran_get_ul_slice_percentage(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.ul[slice_idx].pct * 100.0f; + return -1; } void flexran_set_ul_slice_percentage(mid_t mod_id, int slice_idx, int percentage) { if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.ul[slice_idx].pct = percentage / 100.0f; } int flexran_get_ul_slice_first_rb(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.ul[slice_idx].first_rb; + return -1; } void flexran_set_ul_slice_first_rb(mid_t mod_id, int slice_idx, int first_rb) { if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.ul[slice_idx].first_rb = first_rb; } int flexran_get_ul_slice_maxmcs(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.ul[slice_idx].maxmcs; + return -1; } void flexran_set_ul_slice_maxmcs(mid_t mod_id, int slice_idx, int maxmcs) { if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.ul[slice_idx].maxmcs = maxmcs; } char *flexran_get_ul_slice_scheduler(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return NULL; - - return RC.mac[mod_id]->slice_info.ul[slice_idx].sched_name; + return ""; } int flexran_set_ul_slice_scheduler(mid_t mod_id, int slice_idx, char *name) { if (!mac_is_present(mod_id)) return 0; - - if (RC.mac[mod_id]->slice_info.ul[slice_idx].sched_name) - free(RC.mac[mod_id]->slice_info.ul[slice_idx].sched_name); - - RC.mac[mod_id]->slice_info.ul[slice_idx].sched_name = strdup(name); - RC.mac[mod_id]->slice_info.ul[slice_idx].sched_cb = dlsym(NULL, name); - return RC.mac[mod_id]->slice_info.ul[slice_idx].sched_cb != NULL; + return 0; } /************************** S1AP **************************/ diff --git a/openair2/LAYER2/MAC/mac.h b/openair2/LAYER2/MAC/mac.h index 09585fae55..8349d84d48 100644 --- a/openair2/LAYER2/MAC/mac.h +++ b/openair2/LAYER2/MAC/mac.h @@ -155,9 +155,6 @@ /*!\brief minimum MAC data needed for transmitting 1 min RLC PDU size + 1 byte MAC subHeader */ #define MIN_MAC_HDR_RLC_SIZE (1 + MIN_RLC_PDU_SIZE) -/*!\brief maximum number of slices / groups */ -#define MAX_NUM_SLICES 10 - #define U_PLANE_INACTIVITY_VALUE 0 /* defined 10ms order (zero means infinity) */ @@ -1150,9 +1147,6 @@ typedef struct { UE_list_t list; int num_UEs; boolean_t active[MAX_MOBILES_PER_ENB]; - - /// Sorting criteria for the UE list in the MAC preprocessor - uint16_t sorting_criteria[MAX_NUM_SLICES][CR_NUM]; } UE_info_t; /*! \brief deleting control information*/ @@ -1171,101 +1165,6 @@ typedef struct { int tail_freelist; ///the tail position of the delete list } UE_free_list_t; -/** - * slice specific scheduler for the DL - */ -typedef void (*slice_scheduler_dl)(module_id_t mod_id, - int slice_idx, - frame_t frame, - sub_frame_t subframe, - int *mbsfn_flag); - -typedef struct { - slice_id_t id; - - /// RB share for each slice - float pct; - - /// whether this slice is isolated from the others - int isol; - - int prio; - - /// Frequency ranges for slice positioning - int pos_low; - int pos_high; - - // max mcs for each slice - int maxmcs; - - /// criteria for sorting policies of the slices - uint32_t sorting; - - /// Accounting policy (just greedy(1) or fair(0) setting for now) - int accounting; - - /// name of available scheduler - char *sched_name; - - /// pointer to the slice specific scheduler in DL - slice_scheduler_dl sched_cb; - -} slice_sched_conf_dl_t; - -typedef void (*slice_scheduler_ul)(module_id_t mod_id, - int slice_idx, - frame_t frame, - sub_frame_t subframe, - unsigned char sched_subframe, - uint16_t *first_rb); - -typedef struct { - slice_id_t id; - - /// RB share for each slice - float pct; - - // MAX MCS for each slice - int maxmcs; - - /// criteria for sorting policies of the slices - uint32_t sorting; - - /// starting RB (RB offset) of UL scheduling - int first_rb; - - /// name of available scheduler - char *sched_name; - - /// pointer to the slice specific scheduler in UL - slice_scheduler_ul sched_cb; - -} slice_sched_conf_ul_t; - - -typedef struct { - /// counter used to indicate when all slices have pre-allocated UEs - //int slice_counter; - - /// indicates whether remaining RBs after first intra-slice allocation will - /// be allocated to UEs of the same slice - int intraslice_share_active; - /// indicates whether remaining RBs after slice allocation will be - /// allocated to UEs of another slice. Isolated slices will be ignored - int interslice_share_active; - - /// number of active DL slices - int n_dl; - slice_sched_conf_dl_t dl[MAX_NUM_SLICES]; - - /// number of active UL slices - int n_ul; - slice_sched_conf_ul_t ul[MAX_NUM_SLICES]; - - /// common rb allocation list between slices - uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX]; -} slice_info_t; - /** * describes contiguous RBs */ @@ -1421,9 +1320,6 @@ typedef struct eNB_MAC_INST_s { uint32_t ul_handle; UE_info_t UE_info; - /// slice-related configuration - slice_info_t slice_info; - ///subband bitmap configuration SBMAP_CONF sbmap_conf; /// CCE table used to build DCI scheduling information diff --git a/openair2/LAYER2/MAC/mac_proto.h b/openair2/LAYER2/MAC/mac_proto.h index 2cb86c25af..61251ef088 100644 --- a/openair2/LAYER2/MAC/mac_proto.h +++ b/openair2/LAYER2/MAC/mac_proto.h @@ -187,8 +187,6 @@ void add_msg3(module_id_t module_idP, int CC_id, RA_t *ra, frame_t frameP, void init_UE_info(UE_info_t *UE_info); -void init_slice_info(slice_info_t *sli); - int mac_top_init(int eMBMS_active, char *uecap_xer, uint8_t cba_group_active, uint8_t HO_active); diff --git a/openair2/LAYER2/MAC/main.c b/openair2/LAYER2/MAC/main.c index 294eb12159..35b5136889 100644 --- a/openair2/LAYER2/MAC/main.c +++ b/openair2/LAYER2/MAC/main.c @@ -57,32 +57,6 @@ void init_UE_info(UE_info_t *UE_info) memset(UE_info->active, 0, sizeof(UE_info->active)); } -void init_slice_info(slice_info_t *sli) -{ - sli->intraslice_share_active = 1; - sli->interslice_share_active = 1; - - sli->n_dl = 1; - memset(sli->dl, 0, sizeof(slice_sched_conf_dl_t) * MAX_NUM_SLICES); - sli->dl[0].pct = 1.0; - sli->dl[0].prio = 10; - sli->dl[0].pos_high = N_RBG_MAX; - sli->dl[0].maxmcs = 28; - sli->dl[0].sorting = 0x012345; - sli->dl[0].sched_name = "schedule_ue_spec"; - sli->dl[0].sched_cb = dlsym(NULL, sli->dl[0].sched_name); - AssertFatal(sli->dl[0].sched_cb, "DLSCH scheduler callback is NULL\n"); - - sli->n_ul = 1; - memset(sli->ul, 0, sizeof(slice_sched_conf_ul_t) * MAX_NUM_SLICES); - sli->ul[0].pct = 1.0; - sli->ul[0].maxmcs = 20; - sli->ul[0].sorting = 0x0123; - sli->ul[0].sched_name = "schedule_ulsch_rnti"; - sli->ul[0].sched_cb = dlsym(NULL, sli->ul[0].sched_name); - AssertFatal(sli->ul[0].sched_cb, "ULSCH scheduler callback is NULL\n"); -} - void mac_top_init_eNB(void) { module_id_t i, j; @@ -139,7 +113,6 @@ void mac_top_init_eNB(void) mac[i]->ul_algo = *(default_sched_ul_algo_t *) d; mac[i]->ul_algo.data = mac[i]->ul_algo.setup(); init_UE_info(&mac[i]->UE_info); - init_slice_info(&mac[i]->slice_info); } RC.mac = mac; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index d3412095e3..8afa3a04f5 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -68,8 +68,6 @@ extern RAN_CONTEXT_t RC; -extern int n_active_slices; - // Note the 2 scs values in the table names represent resp. scs_common and pdcch_scs /// LUT for the number of symbols in the coreset indexed by coreset index (4 MSB rmsi_pdcch_config) uint8_t nr_coreset_nsymb_pdcch_type_0_scs_15_15[15] = {2,2,2,3,3,3,1,1,2,2,3,3,1,2,3}; From 8c76d6ab57e6088d317db51d454257f9bde0b463 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Tue, 14 Apr 2020 16:17:56 +0200 Subject: [PATCH 425/553] Delete old protobuf slice types flex_slice_{dl,ul} --- .../CONTROL_MODULES/MAC/flexran_agent_mac.c | 206 +----- .../MAC/flexran_agent_mac_internal.c | 666 +----------------- .../MAC/flexran_agent_mac_internal.h | 20 - .../flexran_agent_mac_slice_verification.c | 343 --------- .../flexran_agent_mac_slice_verification.h | 6 - .../ENB_APP/MESSAGES/V2/config_common.proto | 77 -- .../ENB_APP/MESSAGES/V2/config_messages.proto | 8 - openair2/ENB_APP/flexran_agent_common.c | 20 +- openair2/ENB_APP/flexran_agent_ran_api.c | 178 +---- openair2/ENB_APP/flexran_agent_ran_api.h | 149 +--- 10 files changed, 47 insertions(+), 1626 deletions(-) diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c index 669eb33ea3..4800fccea9 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c @@ -1468,10 +1468,12 @@ void flexran_agent_fill_mac_ue_config(mid_t mod_id, mid_t ue_id, ue_conf->rnti = flexran_get_mac_ue_crnti(mod_id, ue_id); ue_conf->has_rnti = 1; - ue_conf->dl_slice_id = flexran_get_ue_dl_slice_id(mod_id, ue_id); - ue_conf->has_dl_slice_id = 1; - ue_conf->ul_slice_id = flexran_get_ue_ul_slice_id(mod_id, ue_id); - ue_conf->has_ul_slice_id = 1; + int dl_id = flexran_get_ue_dl_slice_id(mod_id, ue_id); + ue_conf->dl_slice_id = dl_id; + ue_conf->has_dl_slice_id = dl_id >= 0; + int ul_id = flexran_get_ue_ul_slice_id(mod_id, ue_id); + ue_conf->ul_slice_id = ul_id; + ue_conf->has_ul_slice_id = ul_id >= 0; ue_conf->ue_aggregated_max_bitrate_ul = flexran_get_ue_aggregated_max_bitrate_ul(mod_id, ue_id); ue_conf->has_ue_aggregated_max_bitrate_ul = 1; @@ -1576,149 +1578,24 @@ void flexran_create_config_structures(mid_t mod_id) sc_update[mod_id] = flexran_agent_create_slice_config(n_dl, m_ul); if (!slice_config[mod_id] || !sc_update[mod_id]) return; - flexran_agent_read_slice_config(mod_id, slice_config[mod_id]); - flexran_agent_read_slice_config(mod_id, sc_update[mod_id]); + //flexran_agent_read_slice_config(mod_id, slice_config[mod_id]); + //flexran_agent_read_slice_config(mod_id, sc_update[mod_id]); for (i = 0; i < n_dl; i++) { - flexran_agent_read_slice_dl_config(mod_id, i, slice_config[mod_id]->dl[i]); - flexran_agent_read_slice_dl_config(mod_id, i, sc_update[mod_id]->dl[i]); + //flexran_agent_read_slice_dl_config(mod_id, i, slice_config[mod_id]->dl[i]); + //flexran_agent_read_slice_dl_config(mod_id, i, sc_update[mod_id]->dl[i]); } for (i = 0; i < m_ul; i++) { - flexran_agent_read_slice_ul_config(mod_id, i, slice_config[mod_id]->ul[i]); - flexran_agent_read_slice_ul_config(mod_id, i, sc_update[mod_id]->ul[i]); + //flexran_agent_read_slice_ul_config(mod_id, i, slice_config[mod_id]->ul[i]); + //flexran_agent_read_slice_ul_config(mod_id, i, sc_update[mod_id]->ul[i]); } } void flexran_check_and_remove_slices(mid_t mod_id) { - Protocol__FlexDlSlice **dl = sc_update[mod_id]->dl; - Protocol__FlexDlSlice **dlreal = slice_config[mod_id]->dl; - int i = 0; - while (i < sc_update[mod_id]->n_dl) { - /* remove slices whose percentage is zero */ - if (dl[i]->percentage > 0) { - ++i; - continue; - } - if (flexran_remove_dl_slice(mod_id, i) < 1) { - LOG_W(FLEXRAN_AGENT, "[%d] can not remove slice index %d ID %d\n", - mod_id, i, dl[i]->id); - ++i; - continue; - } - LOG_I(FLEXRAN_AGENT, "[%d] removed slice index %d ID %d\n", - mod_id, i, dl[i]->id); - if (dl[i]->n_sorting > 0) free(dl[i]->sorting); - free(dl[i]->scheduler_name); - if (dlreal[i]->n_sorting > 0) { - dlreal[i]->n_sorting = 0; - free(dlreal[i]->sorting); - } - free(dlreal[i]->scheduler_name); - --sc_update[mod_id]->n_dl; - --slice_config[mod_id]->n_dl; - const size_t last = sc_update[mod_id]->n_dl; - /* we need to memcpy the higher slice to the position we just deleted */ - memcpy(dl[i], dl[last], sizeof(*dl[last])); - memset(dl[last], 0, sizeof(*dl[last])); - memcpy(dlreal[i], dlreal[last], sizeof(*dlreal[last])); - memset(dlreal[last], 0, sizeof(*dlreal[last])); - /* dont increase i but recheck the slice which has been copied to here */ - } - Protocol__FlexUlSlice **ul = sc_update[mod_id]->ul; - Protocol__FlexUlSlice **ulreal = slice_config[mod_id]->ul; - i = 0; - while (i < sc_update[mod_id]->n_ul) { - if (ul[i]->percentage > 0) { - ++i; - continue; - } - if (flexran_remove_ul_slice(mod_id, i) < 1) { - LOG_W(FLEXRAN_AGENT, "[%d] can not remove slice index %d ID %d\n", - mod_id, i, ul[i]->id); - ++i; - continue; - } - LOG_I(FLEXRAN_AGENT, "[%d] removed slice index %d ID %d\n", - mod_id, i, ul[i]->id); - free(ul[i]->scheduler_name); - free(ulreal[i]->scheduler_name); - --sc_update[mod_id]->n_ul; - --slice_config[mod_id]->n_ul; - const size_t last = sc_update[mod_id]->n_ul; - /* see DL remarks */ - memcpy(ul[i], ul[last], sizeof(*ul[last])); - memset(ul[last], 0, sizeof(*ul[last])); - memcpy(ulreal[i], ulreal[last], sizeof(*ulreal[last])); - memset(ulreal[last], 0, sizeof(*ulreal[last])); - /* dont increase i but recheck the slice which has been copied to here */ - } } void flexran_agent_slice_update(mid_t mod_id) { - int i; - int changes = 0; - - if (perform_slice_config_update_count <= 0) return; - perform_slice_config_update_count--; - - pthread_mutex_lock(&sc_update_mtx); - - if (!slice_config[mod_id]) { - /* if the configuration does not exist for agent, create from eNB structure - * and exit */ - flexran_create_config_structures(mod_id); - pthread_mutex_unlock(&sc_update_mtx); - return; - } - - /********* read existing config *********/ - /* simply update slice_config all the time and write new config - * (apply_new_slice_dl_config() only updates if changes are necessary) */ - slice_config[mod_id]->n_dl = flexran_get_num_dl_slices(mod_id); - slice_config[mod_id]->n_ul = flexran_get_num_ul_slices(mod_id); - for (i = 0; i < slice_config[mod_id]->n_dl; i++) { - flexran_agent_read_slice_dl_config(mod_id, i, slice_config[mod_id]->dl[i]); - } - for (i = 0; i < slice_config[mod_id]->n_ul; i++) { - flexran_agent_read_slice_ul_config(mod_id, i, slice_config[mod_id]->ul[i]); - } - - /********* write new config *********/ - /* check for removal (sc_update[X]->dl[Y].percentage == 0) - * and update sc_update & slice_config accordingly */ - flexran_check_and_remove_slices(mod_id); - - /* create new DL and UL slices if necessary */ - for (i = slice_config[mod_id]->n_dl; i < sc_update[mod_id]->n_dl; i++) { - flexran_create_dl_slice(mod_id, sc_update[mod_id]->dl[i]->id); - } - for (i = slice_config[mod_id]->n_ul; i < sc_update[mod_id]->n_ul; i++) { - flexran_create_ul_slice(mod_id, sc_update[mod_id]->ul[i]->id); - } - slice_config[mod_id]->n_dl = flexran_get_num_dl_slices(mod_id); - slice_config[mod_id]->n_ul = flexran_get_num_ul_slices(mod_id); - changes += apply_new_slice_config(mod_id, slice_config[mod_id], sc_update[mod_id]); - for (i = 0; i < slice_config[mod_id]->n_dl; i++) { - changes += apply_new_slice_dl_config(mod_id, - slice_config[mod_id]->dl[i], - sc_update[mod_id]->dl[i]); - flexran_agent_read_slice_dl_config(mod_id, i, slice_config[mod_id]->dl[i]); - } - for (i = 0; i < slice_config[mod_id]->n_ul; i++) { - changes += apply_new_slice_ul_config(mod_id, - slice_config[mod_id]->ul[i], - sc_update[mod_id]->ul[i]); - flexran_agent_read_slice_ul_config(mod_id, i, slice_config[mod_id]->ul[i]); - } - flexran_agent_read_slice_config(mod_id, slice_config[mod_id]); - if (n_ue_slice_assoc_updates > 0) { - changes += apply_ue_slice_assoc_update(mod_id); - } - if (changes > 0) - LOG_I(FLEXRAN_AGENT, "[%d] slice configuration: applied %d changes\n", mod_id, changes); - - pthread_mutex_unlock(&sc_update_mtx); } Protocol__FlexSliceConfig *flexran_agent_get_slice_config(mid_t mod_id) @@ -1727,69 +1604,10 @@ Protocol__FlexSliceConfig *flexran_agent_get_slice_config(mid_t mod_id) Protocol__FlexSliceConfig *config = NULL; pthread_mutex_lock(&sc_update_mtx); - config = flexran_agent_create_slice_config(slice_config[mod_id]->n_dl, - slice_config[mod_id]->n_ul); if (!config) { pthread_mutex_unlock(&sc_update_mtx); return NULL; } - config->has_intraslice_share_active = 1; - config->intraslice_share_active = slice_config[mod_id]->intraslice_share_active; - config->has_interslice_share_active = 1; - config->interslice_share_active = slice_config[mod_id]->interslice_share_active; - for (int i = 0; i < slice_config[mod_id]->n_dl; ++i) { - if (!config->dl[i]) continue; - config->dl[i]->has_id = 1; - config->dl[i]->id = slice_config[mod_id]->dl[i]->id; - config->dl[i]->has_label = 1; - config->dl[i]->label = slice_config[mod_id]->dl[i]->label; - config->dl[i]->has_percentage = 1; - config->dl[i]->percentage = slice_config[mod_id]->dl[i]->percentage; - config->dl[i]->has_isolation = 1; - config->dl[i]->isolation = slice_config[mod_id]->dl[i]->isolation; - config->dl[i]->has_priority = 1; - config->dl[i]->priority = slice_config[mod_id]->dl[i]->priority; - config->dl[i]->has_position_low = 1; - config->dl[i]->position_low = slice_config[mod_id]->dl[i]->position_low; - config->dl[i]->has_position_high = 1; - config->dl[i]->position_high = slice_config[mod_id]->dl[i]->position_high; - config->dl[i]->has_maxmcs = 1; - config->dl[i]->maxmcs = slice_config[mod_id]->dl[i]->maxmcs; - config->dl[i]->n_sorting = slice_config[mod_id]->dl[i]->n_sorting; - config->dl[i]->sorting = calloc(config->dl[i]->n_sorting, sizeof(Protocol__FlexDlSorting)); - if (!config->dl[i]->sorting) config->dl[i]->n_sorting = 0; - for (int j = 0; j < config->dl[i]->n_sorting; ++j) - config->dl[i]->sorting[j] = slice_config[mod_id]->dl[i]->sorting[j]; - config->dl[i]->has_accounting = 1; - config->dl[i]->accounting = slice_config[mod_id]->dl[i]->accounting; - config->dl[i]->scheduler_name = strdup(slice_config[mod_id]->dl[i]->scheduler_name); - } - for (int i = 0; i < slice_config[mod_id]->n_ul; ++i) { - if (!config->ul[i]) continue; - config->ul[i]->has_id = 1; - config->ul[i]->id = slice_config[mod_id]->ul[i]->id; - config->ul[i]->has_label = 1; - config->ul[i]->label = slice_config[mod_id]->ul[i]->label; - config->ul[i]->has_percentage = 1; - config->ul[i]->percentage = slice_config[mod_id]->ul[i]->percentage; - config->ul[i]->has_isolation = 1; - config->ul[i]->isolation = slice_config[mod_id]->ul[i]->isolation; - config->ul[i]->has_priority = 1; - config->ul[i]->priority = slice_config[mod_id]->ul[i]->priority; - config->ul[i]->has_first_rb = 1; - config->ul[i]->first_rb = slice_config[mod_id]->ul[i]->first_rb; - config->ul[i]->has_maxmcs = 1; - config->ul[i]->maxmcs = slice_config[mod_id]->ul[i]->maxmcs; - config->ul[i]->n_sorting = slice_config[mod_id]->ul[i]->n_sorting; - config->ul[i]->sorting = calloc(config->ul[i]->n_sorting, sizeof(Protocol__FlexUlSorting)); - if (!config->ul[i]->sorting) config->ul[i]->n_sorting = 0; - for (int j = 0; j < config->ul[i]->n_sorting; ++j) - config->ul[i]->sorting[j] = slice_config[mod_id]->ul[i]->sorting[j]; - config->ul[i]->has_accounting = 1; - config->ul[i]->accounting = slice_config[mod_id]->ul[i]->accounting; - config->ul[i]->scheduler_name = strdup(slice_config[mod_id]->ul[i]->scheduler_name); - } - pthread_mutex_unlock(&sc_update_mtx); return config; } diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c index 84a28683b7..4c80c561ee 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c @@ -1027,666 +1027,18 @@ int load_dl_scheduler_function(mid_t mod_id, const char *function_name) { Protocol__FlexSliceConfig *flexran_agent_create_slice_config(int n_dl, int m_ul) { - int i; Protocol__FlexSliceConfig *fsc = malloc(sizeof(Protocol__FlexSliceConfig)); if (!fsc) return NULL; protocol__flex_slice_config__init(fsc); - /* say there are n_dl slices but reserve memory for up to 10 so - * we don't need to reserve again later */ - fsc->n_dl = n_dl; - fsc->dl = calloc(10, sizeof(Protocol__FlexDlSlice *)); - if (!fsc->dl) fsc->n_dl = 0; - for (i = 0; i < 10; i++) { - fsc->dl[i] = malloc(sizeof(Protocol__FlexDlSlice)); - if (!fsc->dl[i]) continue; - protocol__flex_dl_slice__init(fsc->dl[i]); - } - - /* as above */ - fsc->n_ul = m_ul; - fsc->ul = calloc(10, sizeof(Protocol__FlexUlSlice *)); - if (!fsc->ul) fsc->n_ul = 0; - for (i = 0; i < 10; i++) { - fsc->ul[i] = malloc(sizeof(Protocol__FlexUlSlice)); - if (!fsc->ul[i]) continue; - protocol__flex_ul_slice__init(fsc->ul[i]); - } + /* TODO */ return fsc; } -void flexran_agent_read_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *s) -{ - s->intraslice_share_active = flexran_get_intraslice_sharing_active(mod_id); - s->has_intraslice_share_active = 1; - s->interslice_share_active = flexran_get_interslice_sharing_active(mod_id); - s->has_interslice_share_active = 1; -} - -void flexran_agent_read_slice_dl_config(mid_t mod_id, int slice_idx, Protocol__FlexDlSlice *dl_slice) -{ - dl_slice->id = flexran_get_dl_slice_id(mod_id, slice_idx); - dl_slice->has_id = 1; - /* read label from corresponding sc_update entry or give default */ - dl_slice->label = PROTOCOL__FLEX_SLICE_LABEL__xMBB; - dl_slice->has_label = 1; - for (int i = 0; i < sc_update[mod_id]->n_dl; i++) { - if (sc_update[mod_id]->dl[i]->id == dl_slice->id - && sc_update[mod_id]->dl[i]->has_label) { - dl_slice->label = sc_update[mod_id]->dl[i]->label; - break; - } - } - dl_slice->percentage = flexran_get_dl_slice_percentage(mod_id, slice_idx); - dl_slice->has_percentage = 1; - dl_slice->isolation = flexran_get_dl_slice_isolation(mod_id, slice_idx); - dl_slice->has_isolation = 1; - dl_slice->priority = flexran_get_dl_slice_priority(mod_id, slice_idx); - dl_slice->has_priority = 1; - dl_slice->position_low = flexran_get_dl_slice_position_low(mod_id, slice_idx); - dl_slice->has_position_low = 1; - dl_slice->position_high = flexran_get_dl_slice_position_high(mod_id, slice_idx); - dl_slice->has_position_high = 1; - dl_slice->maxmcs = flexran_get_dl_slice_maxmcs(mod_id, slice_idx); - dl_slice->has_maxmcs = 1; - dl_slice->n_sorting = flexran_get_dl_slice_sorting(mod_id, slice_idx, &dl_slice->sorting); - if (dl_slice->n_sorting < 1) dl_slice->sorting = NULL; - dl_slice->accounting = flexran_get_dl_slice_accounting_policy(mod_id, slice_idx); - dl_slice->has_accounting = 1; - const char *s_name = flexran_get_dl_slice_scheduler(mod_id, slice_idx); - if (!dl_slice->scheduler_name - || strcmp(dl_slice->scheduler_name, s_name) != 0) { - dl_slice->scheduler_name = realloc(dl_slice->scheduler_name, strlen(s_name) + 1); - strcpy(dl_slice->scheduler_name, s_name); - } -} - -void flexran_agent_read_slice_ul_config(mid_t mod_id, int slice_idx, Protocol__FlexUlSlice *ul_slice) -{ - ul_slice->id = flexran_get_ul_slice_id(mod_id, slice_idx); - ul_slice->has_id = 1; - /* read label from corresponding sc_update entry or give default */ - ul_slice->label = PROTOCOL__FLEX_SLICE_LABEL__xMBB; - ul_slice->has_label = 1; - for (int i = 0; i < sc_update[mod_id]->n_ul; i++) { - if (sc_update[mod_id]->ul[i]->id == ul_slice->id - && sc_update[mod_id]->ul[i]->has_label) { - ul_slice->label = sc_update[mod_id]->ul[i]->label; - break; - } - } - ul_slice->percentage = flexran_get_ul_slice_percentage(mod_id, slice_idx); - ul_slice->has_percentage = 1; - /*ul_slice->isolation = flexran_get_ul_slice_isolation(mod_id, slice_idx);*/ - ul_slice->has_isolation = 0; - /*ul_slice->priority = flexran_get_ul_slice_priority(mod_id, slice_idx);*/ - ul_slice->has_priority = 0; - ul_slice->first_rb = flexran_get_ul_slice_first_rb(mod_id, slice_idx); - ul_slice->has_first_rb = 1; - /*ul_slice-> = flexran_get_ul_slice_length_rb(mod_id, slice_idx); - ul_slice->has_length_rb = 0;*/ - ul_slice->maxmcs = flexran_get_ul_slice_maxmcs(mod_id, slice_idx); - ul_slice->has_maxmcs = 1; - ul_slice->n_sorting = 0; - /*if (ul_slice->sorting) { - free(ul_slice->sorting); - ul_slice->sorting = NULL; - } - ul_slice->n_sorting = flexran_get_ul_slice_sorting(mod_id, slice_idx, &ul_slice->sorting); - if (ul_slice->n_sorting < 1) ul_slice->sorting = NULL;*/ - /*ul_slice->accounting = flexran_get_ul_slice_accounting_policy(mod_id, slice_idx);*/ - ul_slice->has_accounting = 0; - const char *s_name = flexran_get_ul_slice_scheduler(mod_id, slice_idx); - if (!ul_slice->scheduler_name - || strcmp(ul_slice->scheduler_name, s_name) != 0) { - ul_slice->scheduler_name = realloc(ul_slice->scheduler_name, strlen(s_name) + 1); - strcpy(ul_slice->scheduler_name, s_name); - } -} - -int check_dl_sorting_update(Protocol__FlexDlSlice *old, Protocol__FlexDlSlice *new) -{ - /* sorting_update => true when old->n_sorting == 0 or different numbers of - * elements; otherwise will check * element-wise */ - int sorting_update = old->n_sorting == 0 || (old->n_sorting != new->n_sorting); - for (int i = 0; i < old->n_sorting && !sorting_update; ++i) { - sorting_update = sorting_update || (new->sorting[i] != old->sorting[i]); - } - return sorting_update; -} - -int check_ul_sorting_update(Protocol__FlexUlSlice *old, Protocol__FlexUlSlice *new) -{ - /* sorting_update => true when old->n_sorting == 0 or different numbers of - * elements; otherwise will check * element-wise */ - int sorting_update = old->n_sorting == 0 || (old->n_sorting != new->n_sorting); - for (int i = 0; i < old->n_sorting && !sorting_update; ++i) { - sorting_update = sorting_update || (new->sorting[i] != old->sorting[i]); - } - return sorting_update; -} - -void overwrite_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *exist, Protocol__FlexSliceConfig *update) -{ - if (update->has_intraslice_share_active - && exist->intraslice_share_active != update->intraslice_share_active) { - LOG_I(FLEXRAN_AGENT, "[%d] update intraslice_share_active: %d -> %d\n", - mod_id, exist->intraslice_share_active, update->intraslice_share_active); - exist->intraslice_share_active = update->intraslice_share_active; - exist->has_intraslice_share_active = 1; - } - if (update->has_interslice_share_active - && exist->interslice_share_active != update->interslice_share_active) { - LOG_I(FLEXRAN_AGENT, "[%d] update interslice_share_active: %d -> %d\n", - mod_id, exist->interslice_share_active, update->interslice_share_active); - exist->interslice_share_active = update->interslice_share_active; - exist->has_interslice_share_active = 1; - } -} - -void overwrite_slice_config_dl(mid_t mod_id, Protocol__FlexDlSlice *exist, Protocol__FlexDlSlice *update) -{ - if (update->label != exist->label) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update label: %d -> %d\n", - mod_id, update->id, exist->label, update->label); - exist->label = update->label; - exist->has_label = 1; - } - if (update->percentage != exist->percentage) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update percentage: %d -> %d\n", - mod_id, update->id, exist->percentage, update->percentage); - exist->percentage = update->percentage; - exist->has_percentage = 1; - } - if (update->isolation != exist->isolation) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update isolation: %d -> %d\n", - mod_id, update->id, exist->isolation, update->isolation); - exist->isolation = update->isolation; - exist->has_isolation = 1; - } - if (update->priority != exist->priority) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update priority: %d -> %d\n", - mod_id, update->id, exist->priority, update->priority); - exist->priority = update->priority; - exist->has_priority = 1; - } - if (update->position_low != exist->position_low) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update position_low: %d -> %d\n", - mod_id, update->id, exist->position_low, update->position_low); - exist->position_low = update->position_low; - exist->has_position_low = 1; - } - if (update->position_high != exist->position_high) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update position_high: %d -> %d\n", - mod_id, update->id, exist->position_high, update->position_high); - exist->position_high = update->position_high; - exist->has_position_high = 1; - } - if (update->maxmcs != exist->maxmcs) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update maxmcs: %d -> %d\n", - mod_id, update->id, exist->maxmcs, update->maxmcs); - exist->maxmcs = update->maxmcs; - exist->has_maxmcs = 1; - } - if (check_dl_sorting_update(exist, update)) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update sorting array\n", mod_id, update->id); - if (exist->n_sorting != update->n_sorting) { - exist->n_sorting = update->n_sorting; - exist->sorting = realloc(exist->sorting, exist->n_sorting * sizeof(Protocol__FlexDlSorting)); - if (!exist->sorting) exist->n_sorting = 0; - } - for (int i = 0; i < exist->n_sorting; i++) - exist->sorting[i] = update->sorting[i]; - } - if (update->accounting != exist->accounting) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update accounting: %d -> %d\n", - mod_id, update->id, exist->accounting, update->accounting); - exist->accounting = update->accounting; - exist->has_accounting = 1; - } - if (!exist->scheduler_name - || strcmp(update->scheduler_name, exist->scheduler_name) != 0) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update scheduler: %s -> %s\n", - mod_id, update->id, exist->scheduler_name, update->scheduler_name); - if (exist->scheduler_name) free(exist->scheduler_name); - exist->scheduler_name = strdup(update->scheduler_name); - } -} - -void overwrite_slice_config_ul(mid_t mod_id, Protocol__FlexUlSlice *exist, Protocol__FlexUlSlice *update) -{ - if (update->label != exist->label) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update label: %d -> %d\n", - mod_id, update->id, exist->label, update->label); - exist->label = update->label; - exist->has_label = 1; - } - if (update->percentage != exist->percentage) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update percentage: %d -> %d\n", - mod_id, update->id, exist->percentage, update->percentage); - exist->percentage = update->percentage; - exist->has_percentage = 1; - } - if (update->isolation != exist->isolation) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update isolation: %d -> %d\n", - mod_id, update->id, exist->isolation, update->isolation); - exist->isolation = update->isolation; - exist->has_isolation = 1; - } - if (update->priority != exist->priority) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update priority: %d -> %d\n", - mod_id, update->id, exist->priority, update->priority); - exist->priority = update->priority; - exist->has_priority = 1; - } - if (update->first_rb != exist->first_rb) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update first_rb: %d -> %d\n", - mod_id, update->id, exist->first_rb, update->first_rb); - exist->first_rb = update ->first_rb; - exist->has_first_rb = 1; - } - /*if (update->lenght_rb != exist->lenght_rb) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update lenght_rb: %d -> %d\n", - mod_id, update->id, exist->lenght_rb, update->lenght_rb); - exist->lenght_rb = update->lenght_rb; - }*/ - if (update->maxmcs != exist->maxmcs) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update maxmcs: %d -> %d\n", - mod_id, update->id, exist->maxmcs, update->maxmcs); - exist->maxmcs = update->maxmcs; - exist->has_maxmcs = 1; - } - /* TODO - int sorting_update = 0; - int n = min(exist->n_sorting, update->n_sorting); - int i = 0; - while (i < n && !sorting_update) { - sorting_update = sorting_update || (update->sorting[i] != exist->sorting[i]); - i++; - } - if (sorting_update) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update sorting array\n", update->id, mod_id); - if (exist->n_sorting != update->n_sorting) - LOG_W(FLEXRAN_AGENT, "[%d][UL slice %d] only writing %d elements\n", - mod_id, update->id, n); - for (i = 0; i < n; i++) - exist->sorting[i] = update->sorting[i]; - } - */ - if (update->accounting != exist->accounting) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update accounting: %d -> %d\n", - mod_id, update->id, exist->accounting, update->accounting); - exist->accounting = update->accounting; - exist->has_accounting = 1; - } - if (!exist->scheduler_name - || strcmp(update->scheduler_name, exist->scheduler_name) != 0) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update scheduler: %s -> %s\n", - mod_id, update->id, exist->scheduler_name, update->scheduler_name); - if (exist->scheduler_name) free(exist->scheduler_name); - exist->scheduler_name = strdup(update->scheduler_name); - } -} - -void fill_dl_slice(mid_t mod_id, Protocol__FlexDlSlice *s, Protocol__FlexDlSlice *from) -{ - /* function fills slice with information from another slice or with default - * values (currently slice 0) if from is NULL */ - /* TODO fill the slice depending on the chosen label */ - if (!s->has_label) { - s->has_label = 1; - s->label = from ? from->label : sc_update[mod_id]->dl[0]->label; - } - if (!s->has_percentage) { - s->has_percentage = 1; - s->percentage = from ? from->percentage : sc_update[mod_id]->dl[0]->percentage; - } - if (!s->has_isolation) { - s->has_isolation = 1; - s->isolation = from ? from->isolation : sc_update[mod_id]->dl[0]->isolation; - } - if (!s->has_priority) { - s->has_priority = 1; - s->priority = from ? from->priority : sc_update[mod_id]->dl[0]->priority; - } - if (!s->has_position_low) { - s->has_position_low = 1; - s->position_low = from ? from->position_low : sc_update[mod_id]->dl[0]->position_low; - } - if (!s->has_position_high) { - s->has_position_high = 1; - s->position_high = from ? from->position_high : sc_update[mod_id]->dl[0]->position_high; - } - if (!s->has_maxmcs) { - s->has_maxmcs = 1; - s->maxmcs = from ? from->maxmcs : sc_update[mod_id]->dl[0]->maxmcs; - } - if (s->n_sorting == 0) { - s->n_sorting = from ? from->n_sorting : sc_update[mod_id]->dl[0]->n_sorting; - s->sorting = calloc(s->n_sorting, sizeof(Protocol__FlexDlSorting)); - if (!s->sorting) s->n_sorting = 0; - for (int i = 0; i < s->n_sorting; ++i) - s->sorting[i] = from ? from->sorting[i] : sc_update[0]->dl[0]->sorting[i]; - } - if (!s->has_accounting) { - s->accounting = from ? from->accounting : sc_update[mod_id]->dl[0]->accounting; - } - if (!s->scheduler_name) { - s->scheduler_name = strdup(from ? from->scheduler_name : sc_update[mod_id]->dl[0]->scheduler_name); - } -} - -Protocol__FlexDlSlice *get_existing_dl_slice(mid_t mod_id, int id) -{ - for (int i = 0; i < sc_update[mod_id]->n_dl; ++i) { - if (id == sc_update[mod_id]->dl[i]->id) { - return sc_update[mod_id]->dl[i]; - } - } - return NULL; -} - -Protocol__FlexDlSlice *create_new_dl_slice(mid_t mod_id, int id) -{ - LOG_I(FLEXRAN_AGENT, - "[%d] Creating DL slice with ID %d, taking default values from DL slice 0\n", - mod_id, id); - Protocol__FlexDlSlice *to = sc_update[mod_id]->dl[sc_update[mod_id]->n_dl]; - sc_update[mod_id]->n_dl++; - AssertFatal(sc_update[mod_id]->n_dl <= 10, - "cannot create more than 10\n"); - to->id = id; - return to; -} - -void fill_ul_slice(mid_t mod_id, Protocol__FlexUlSlice *s, Protocol__FlexUlSlice *from) -{ - /* function fills slice with information from another slice or with default - * values (currently slice 0) if from is NULL */ - /* TODO fill the slice depending on the chosen label */ - if (!s->has_label) { - s->has_label = 1; - s->label = from ? from->label : sc_update[mod_id]->ul[0]->label; - } - if (!s->has_percentage) { - s->has_percentage = 1; - s->percentage = from ? from->percentage : sc_update[mod_id]->ul[0]->percentage; - } - if (!s->has_isolation) { - s->has_isolation = 1; - s->isolation = from ? from->isolation : sc_update[mod_id]->ul[0]->isolation; - } - if (!s->has_priority) { - s->has_priority = 1; - s->priority = from ? from->priority : sc_update[mod_id]->ul[0]->priority; - } - if (!s->has_first_rb) { - s->has_first_rb = 1; - s->first_rb = from ? from->first_rb : sc_update[mod_id]->ul[0]->first_rb; - } - if (!s->has_maxmcs) { - s->has_maxmcs = 1; - s->maxmcs = from ? from->maxmcs : sc_update[mod_id]->ul[0]->maxmcs; - } - if (s->n_sorting == 0) { - s->n_sorting = from ? from->n_sorting : sc_update[0]->ul[0]->n_sorting; - s->sorting = calloc(s->n_sorting, sizeof(Protocol__FlexUlSorting)); - if (!s->sorting) s->n_sorting = 0; - for (int i = 0; i < s->n_sorting; ++i) - s->sorting[i] = from ? from->sorting[i] : sc_update[0]->ul[0]->sorting[i]; - } - if (!s->has_accounting) { - s->accounting = from ? from->accounting : sc_update[0]->ul[0]->accounting; - } - if (!s->scheduler_name) { - s->scheduler_name = strdup(from ? from->scheduler_name : sc_update[mod_id]->ul[0]->scheduler_name); - } -} - -Protocol__FlexUlSlice *get_existing_ul_slice(mid_t mod_id, int id) -{ - for (int i = 0; i < sc_update[mod_id]->n_ul; ++i) { - if (id == sc_update[mod_id]->ul[i]->id) { - return sc_update[mod_id]->ul[i]; - } - } - return NULL; -} - -Protocol__FlexUlSlice *create_new_ul_slice(mid_t mod_id, int id) -{ - LOG_I(FLEXRAN_AGENT, - "[%d] Creating UL slice with ID %d, taking default values from UL slice 0\n", - mod_id, id); - Protocol__FlexUlSlice *to = sc_update[mod_id]->ul[sc_update[mod_id]->n_ul]; - sc_update[mod_id]->n_ul++; - AssertFatal(sc_update[mod_id]->n_ul <= 10, - "cannot create more than 10\n"); - to->id = id; - return to; -} - void prepare_update_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *sup) { - int verified = 1; - if (!sc_update[mod_id]) { - LOG_E(FLEXRAN_AGENT, "Can not update slice policy (no existing slice profile)\n"); - return; - } - - pthread_mutex_lock(&sc_update_mtx); - /* no need for tests in the current state as there are only two protobuf - * bools for intra-/interslice sharing. The function applies new values if - * applicable */ - overwrite_slice_config(mod_id, sc_update[mod_id], sup); - - if (sup->n_dl == 0) { - LOG_I(FLEXRAN_AGENT, "[%d] no DL slice configuration in flex_slice_config message\n", mod_id); - } else { - /* verify slice parameters */ - for (int i = 0; i < sup->n_dl; i++) { - if (!sup->dl[i]->has_id) { - verified = 0; - break; - } - Protocol__FlexDlSlice *dls = get_existing_dl_slice(mod_id, sup->dl[i]->id); - /* fill up so that the slice is complete. This way, we don't need to - * worry about it later */ - fill_dl_slice(mod_id, sup->dl[i], dls); - verified = verified && flexran_verify_dl_slice(mod_id, sup->dl[i]); - if (!verified) break; - } - - /* verify group-based parameters (e.g. sum percentage should not exceed - * 100%). Can be used to perform admission control */ - verified = verified && flexran_verify_group_dl_slices(mod_id, - sc_update[mod_id]->dl, sc_update[mod_id]->n_dl, sup->dl, sup->n_dl); - - if (verified) { - for (int i = 0; i < sup->n_dl; i++) { - /* if all verifications were successful, get existing slice for ID or - * create new one and overwrite with the update */ - Protocol__FlexDlSlice *dls = get_existing_dl_slice(mod_id, sup->dl[i]->id); - if (!dls) dls = create_new_dl_slice(mod_id, sup->dl[i]->id); - overwrite_slice_config_dl(mod_id, dls, sup->dl[i]); - } - } else { - LOG_E(FLEXRAN_AGENT, "[%d] DL slice verification failed, refusing application\n", mod_id); - } - } - - verified = 1; - if (sup->n_ul == 0) { - LOG_I(FLEXRAN_AGENT, "[%d] no UL slice configuration in flex_slice_config message\n", mod_id); - } else { - /* verify slice parameters */ - for (int i = 0; i < sup->n_ul; i++) { - if (!sup->ul[i]->has_id) { - verified = 0; - break; - } - Protocol__FlexUlSlice *uls = get_existing_ul_slice(mod_id, sup->ul[i]->id); - /* fill up so that the slice is complete. This way, we don't need to - * worry about it later */ - fill_ul_slice(mod_id, sup->ul[i], uls); - verified = verified && flexran_verify_ul_slice(mod_id, sup->ul[i]); - if (!verified) break; - } - - /* verify group-based parameters (e.g. sum percentage should not exceed - * 100%). Can be used to perform admission control */ - verified = verified && flexran_verify_group_ul_slices(mod_id, - sc_update[mod_id]->ul, sc_update[mod_id]->n_ul, sup->ul, sup->n_ul); - - if (verified) { - for (int i = 0; i < sup->n_ul; i++) { - /* if all verifications were successful, get existing slice for ID or - * create new one and overwrite with the update */ - Protocol__FlexUlSlice *uls = get_existing_ul_slice(mod_id, sup->ul[i]->id); - if (!uls) uls = create_new_ul_slice(mod_id, sup->ul[i]->id); - overwrite_slice_config_ul(mod_id, uls, sup->ul[i]); - } - } else { - LOG_E(FLEXRAN_AGENT, "[%d] UL slice verification failed, refusing application\n", mod_id); - } - } - pthread_mutex_unlock(&sc_update_mtx); - - perform_slice_config_update_count = 1; } -int apply_new_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *olds, Protocol__FlexSliceConfig *news) -{ - /* not setting the old configuration is intentional, as it will be picked up - * later when reading the configuration. There is thus a direct feedback - * whether it has been set. */ - int changes = 0; - if (olds->intraslice_share_active != news->intraslice_share_active) { - flexran_set_intraslice_sharing_active(mod_id, news->intraslice_share_active); - changes++; - } - if (olds->interslice_share_active != news->interslice_share_active) { - flexran_set_interslice_sharing_active(mod_id, news->interslice_share_active); - changes++; - } - return changes; -} - -int apply_new_slice_dl_config(mid_t mod_id, Protocol__FlexDlSlice *oldc, Protocol__FlexDlSlice *newc) -{ - /* not setting the old configuration is intentional, as it will be picked up - * later when reading the configuration. There is thus a direct feedback - * whether it has been set. */ - int changes = 0; - int slice_idx = flexran_find_dl_slice(mod_id, newc->id); - if (slice_idx < 0) { - LOG_W(FLEXRAN_AGENT, "[%d] cannot find index for slice ID %d\n", mod_id, newc->id); - return 0; - } - if (oldc->percentage != newc->percentage) { - flexran_set_dl_slice_percentage(mod_id, slice_idx, newc->percentage); - changes++; - } - if (oldc->isolation != newc->isolation) { - flexran_set_dl_slice_isolation(mod_id, slice_idx, newc->isolation); - changes++; - } - if (oldc->priority != newc->priority) { - flexran_set_dl_slice_priority(mod_id, slice_idx, newc->priority); - changes++; - } - if (oldc->position_low != newc->position_low) { - flexran_set_dl_slice_position_low(mod_id, slice_idx, newc->position_low); - changes++; - } - if (oldc->position_high != newc->position_high) { - flexran_set_dl_slice_position_high(mod_id, slice_idx, newc->position_high); - changes++; - } - if (oldc->maxmcs != newc->maxmcs) { - flexran_set_dl_slice_maxmcs(mod_id, slice_idx, newc->maxmcs); - changes++; - } - if (check_dl_sorting_update(oldc, newc)) { - flexran_set_dl_slice_sorting(mod_id, slice_idx, newc->sorting, newc->n_sorting); - changes++; - } - if (oldc->accounting != newc->accounting) { - flexran_set_dl_slice_accounting_policy(mod_id, slice_idx, newc->accounting); - changes++; - } - if (!oldc->scheduler_name - || strcmp(oldc->scheduler_name, newc->scheduler_name) != 0) { - int ret = flexran_set_dl_slice_scheduler(mod_id, slice_idx, newc->scheduler_name); - AssertFatal(ret, "could not set DL slice scheduler for slice %d idx %d\n", - newc->id, slice_idx); - changes++; - } - return changes; -} - -int apply_new_slice_ul_config(mid_t mod_id, Protocol__FlexUlSlice *oldc, Protocol__FlexUlSlice *newc) -{ - /* not setting the old configuration is intentional, as it will be picked up - * later when reading the configuration. There is thus a direct feedback - * whether it has been set. */ - int changes = 0; - int slice_idx = flexran_find_ul_slice(mod_id, newc->id); - if (slice_idx < 0) { - LOG_W(FLEXRAN_AGENT, "[%d] cannot find index for slice ID %d\n", mod_id, newc->id); - return 0; - } - if (oldc->percentage != newc->percentage) { - flexran_set_ul_slice_percentage(mod_id, slice_idx, newc->percentage); - changes++; - } - if (oldc->isolation != newc->isolation) { - /*flexran_set_ul_slice_isolation(mod_id, slice_idx, newc->isolation); - *changes++;*/ - LOG_W(FLEXRAN_AGENT, "[%d][UL slice %d] setting isolation is not supported\n", - mod_id, newc->id); - } - if (oldc->priority != newc->priority) { - /*flexran_set_ul_slice_priority(mod_id, slice_idx, newc->priority); - *changes++;*/ - LOG_W(FLEXRAN_AGENT, "[%d][UL slice %d] setting the priority is not supported\n", - mod_id, newc->id); - } - if (oldc->first_rb != newc->first_rb) { - flexran_set_ul_slice_first_rb(mod_id, slice_idx, newc->first_rb); - changes++; - } - /*if (oldc->length_rb != newc->length_rb) { - flexran_set_ul_slice_length_rb(mod_id, slice_idx, newc->length_rb); - changes++; - LOG_W(FLEXRAN_AGENT, "[%d][UL slice %d] setting length_rb is not supported\n", - mod_id, newc->id); - }*/ - if (oldc->maxmcs != newc->maxmcs) { - flexran_set_ul_slice_maxmcs(mod_id, slice_idx, newc->maxmcs); - changes++; - } - /*if (check_ul_sorting_update(oldc, newc)) { - flexran_set_ul_slice_sorting(mod_id, slice_idx, newc->sorting, n); - changes++; - LOG_W(FLEXRAN_AGENT, "[%d][UL slice %d] setting the sorting is not supported\n", - mod_id, newc->id); - }*/ - if (oldc->accounting != newc->accounting) { - /*flexran_set_ul_slice_accounting_policy(mod_id, slice_idx, newc->accounting); - *changes++;*/ - LOG_W(FLEXRAN_AGENT, "[%d][UL slice %d] setting the accounting is not supported\n", - mod_id, newc->id); - } - if (!oldc->scheduler_name - || strcmp(oldc->scheduler_name, newc->scheduler_name) != 0) { - int ret = flexran_set_ul_slice_scheduler(mod_id, slice_idx, newc->scheduler_name); - AssertFatal(ret, "could not set DL slice scheduler for slice %d idx %d\n", - newc->id, slice_idx); - changes++; - } - return changes; -} void prepare_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig *ue_config) { @@ -1723,24 +1075,8 @@ int apply_ue_slice_assoc_update(mid_t mod_id) continue; } if (ue_slice_assoc_update[i]->has_dl_slice_id) { - int slice_idx = flexran_find_dl_slice(mod_id, ue_slice_assoc_update[i]->dl_slice_id); - if (flexran_dl_slice_exists(mod_id, slice_idx)) { - flexran_set_ue_dl_slice_idx(mod_id, ue_id, slice_idx); - changes++; - } else { - LOG_W(FLEXRAN_AGENT, "[%d] DL slice %d does not exist, refusing change\n", - mod_id, ue_slice_assoc_update[i]->dl_slice_id); - } } if (ue_slice_assoc_update[i]->has_ul_slice_id) { - int slice_idx = flexran_find_ul_slice(mod_id, ue_slice_assoc_update[i]->ul_slice_id); - if (flexran_ul_slice_exists(mod_id, slice_idx)) { - flexran_set_ue_ul_slice_idx(mod_id, ue_id, slice_idx); - changes++; - } else { - LOG_W(FLEXRAN_AGENT, "[%d] UL slice %d does not exist, refusing change\n", - mod_id, ue_slice_assoc_update[i]->ul_slice_id); - } } } n_ue_slice_assoc_updates = 0; diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.h b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.h index 957fe6065e..ef2a7e40a9 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.h +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.h @@ -111,30 +111,10 @@ Protocol__FlexSliceConfig *flexran_agent_create_slice_config(int n_dl, int m_ul) * Protocol__FlexSliceConfig struct */ void flexran_agent_read_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *s); -/* read the DL slice config via the RAN into a given Protocol__FlexDlSlice - * struct */ -void flexran_agent_read_slice_dl_config(mid_t mod_id, int slice_idx, Protocol__FlexDlSlice *dl_slice); - -/* read the UL slice config via the RAN into a given Protocol__FlexUlSlice - * struct */ -void flexran_agent_read_slice_ul_config(mid_t mod_id, int slice_idx, Protocol__FlexUlSlice *ul_slice); - /* reads content of slice over the sc_update structure, so that it can be * applied later by performing a diff between slice_config and sc_update */ void prepare_update_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *slice); -/* apply generic slice parameters (e.g. intra-/interslice sharing activated or - * not) if there are changes. Returns the number of changed parameters. */ -int apply_new_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *olds, Protocol__FlexSliceConfig *news); - -/* apply new configuration of slice in DL if there are changes between the - * parameters. Returns the number of changed parameters. */ -int apply_new_slice_dl_config(mid_t mod_id, Protocol__FlexDlSlice *oldc, Protocol__FlexDlSlice *newc); - -/* apply new configuration of slice in UL if there are changes between the - * parameters. Returns the number of changed parameters. */ -int apply_new_slice_ul_config(mid_t mod_id, Protocol__FlexUlSlice *oldc, Protocol__FlexUlSlice *newc); - /* inserts a new ue_config into the structure keeping ue to slice association * updates and marks so it can be applied */ void prepare_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig *ue_config); diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.c index f7f60541f5..6e54e155c2 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.c +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.c @@ -28,346 +28,3 @@ #include "flexran_agent_mac_slice_verification.h" - -/* overlap check for UL slices, helper type */ -struct sregion_s { - int start; - int length; -}; - -/* forward declaration of locally-used verification functions */ -int flexran_dl_slice_verify_pct(int pct); -int flexran_dl_slice_verify_priority(int prio); -int flexran_dl_slice_verify_position(int pos_low, int pos_high); -int flexran_dl_slice_verify_maxmcs(int maxmcs); -int flexran_ul_slice_verify_pct(int pct); -int flexran_ul_slice_verify_priority(int prio); -int flexran_ul_slice_verify_first_rb(int first_rb); -int flexran_ul_slice_verify_maxmcs(int maxmcs); -int check_ul_slice_overlap(mid_t mod_id, struct sregion_s *sr, int n); - -int flexran_verify_dl_slice(mid_t mod_id, Protocol__FlexDlSlice *dls) -{ - /* check mandatory parameters */ - if (!dls->has_id) { - LOG_E(FLEXRAN_AGENT, "[%d] Incoming DL slice configuration has no ID\n", mod_id); - return 0; - } - - /* verify parameters individualy */ - /* label is enum */ - if (!flexran_dl_slice_verify_pct(dls->percentage)) { - LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] illegal DL slice percentage (%d)\n", - mod_id, dls->id, dls->percentage); - return 0; - } - /* isolation is a protobuf bool */ - if (!flexran_dl_slice_verify_priority(dls->priority)) { - LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] illegal DL slice priority (%d)\n", - mod_id, dls->id, dls->priority); - return 0; - } - if (!flexran_dl_slice_verify_position(dls->position_low, dls->position_high)) { - LOG_E(FLEXRAN_AGENT, - "[%d][DL slice %d] illegal DL slice position low (%d) and/or high (%d)\n", - mod_id, dls->id, dls->position_low, dls->position_high); - return 0; - } - if (!flexran_dl_slice_verify_maxmcs(dls->maxmcs)) { - LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] illegal DL slice max mcs %d\n", - mod_id, dls->id, dls->maxmcs); - return 0; - } - if (dls->n_sorting == 0) { - LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] no sorting in DL slice\n", - mod_id, dls->id); - return 0; - } - if (!dls->sorting) { - LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] no sorting found in DL slice\n", - mod_id, dls->id); - return 0; - } - /* sorting is an enum */ - /* accounting is an enum */ - if (!dls->scheduler_name) { - LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] no scheduler name found\n", - mod_id, dls->id); - return 0; - } - if (strcmp(dls->scheduler_name, "schedule_ue_spec") != 0) { - LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] setting the scheduler to something " - "different than schedule_ue_spec is currently not allowed\n", - mod_id, dls->id); - return 0; - } - - return 1; -} - -int flexran_verify_group_dl_slices(mid_t mod_id, Protocol__FlexDlSlice **existing, - int n_ex, Protocol__FlexDlSlice **update, int n_up) -{ - int i, j, n; - int pct, pct_orig; - /* for every update, array points to existing slice, or NULL if update - * creates new slice */ - Protocol__FlexDlSlice *s[n_up]; - for (i = 0; i < n_up; i++) { - s[i] = NULL; - for (j = 0; j < n_ex; j++) { - if (existing[j]->id == update[i]->id) - s[i] = existing[j]; - } - } - - /* check that number of created and number of added slices in total matches - * [1,10] */ - n = n_ex; - for (i = 0; i < n_up; i++) { - /* new slice */ - if (!s[i]) n += 1; - /* slice will be deleted */ - else if (s[i]->percentage == 0) n -= 1; - /* else "only" an update */ - } - - if (n < 1 || n > 10) { - LOG_E(FLEXRAN_AGENT, "[%d] Illegal number of resulting DL slices (%d -> %d)\n", - mod_id, n_ex, n); - return 0; - } - - /* check that the sum of all slices percentages (including removed/added - * slices) matches [1,100] */ - pct = 0; - for (i = 0; i < n_ex; i++) { - pct += existing[i]->percentage; - } - pct_orig = pct; - for (i = 0; i < n_up; i++) { - /* if there is an existing slice, subtract its percentage and add the - * update's percentage */ - if (s[i]) - pct -= s[i]->percentage; - pct += update[i]->percentage; - } - if (pct < 1 || pct > 100) { - LOG_E(FLEXRAN_AGENT, - "[%d] invalid total RB share for DL slices (%d%% -> %d%%)\n", - mod_id, pct_orig, pct); - return 0; - } - - return 1; -} - -int flexran_verify_ul_slice(mid_t mod_id, Protocol__FlexUlSlice *uls) -{ - /* check mandatory parameters */ - if (!uls->has_id) { - LOG_E(FLEXRAN_AGENT, "[%d] Incoming UL slice configuration has no ID\n", mod_id); - return 0; - } - - /* verify parameters individually */ - /* label is enum */ - if (!flexran_ul_slice_verify_pct(uls->percentage)) { - LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] illegal UL slice percentage (%d)\n", - mod_id, uls->id, uls->percentage); - return 0; - } - /* isolation is a protobuf bool */ - if (!flexran_ul_slice_verify_priority(uls->priority)) { - LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] illegal UL slice percentage (%d)\n", - mod_id, uls->id, uls->priority); - return 0; - } - if (!flexran_ul_slice_verify_first_rb(uls->first_rb)) { - LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] illegal UL slice first RB (%d)\n", - mod_id, uls->id, uls->first_rb); - return 0; - } - if (!flexran_ul_slice_verify_maxmcs(uls->maxmcs)) { - LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] illegal UL slice max mcs (%d)\n", - mod_id, uls->id, uls->maxmcs); - return 0; - } - /* TODO - if (uls->n_sorting == 0) { - LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] no sorting in UL slice\n", - mod_id, uls->id); - return 0; - } - if (!uls->sorting) { - LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] no sorting found in UL slice\n", - mod_id, uls->id); - return 0; - } - */ - /* sorting is an enum */ - /* accounting is an enum */ - if (!uls->scheduler_name) { - LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] no scheduler name found\n", - mod_id, uls->id); - return 0; - } - if (strcmp(uls->scheduler_name, "schedule_ulsch_rnti") != 0) { - LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] setting the scheduler to something " - "different than schedule_ulsch_rnti is currently not allowed\n", - mod_id, uls->id); - return 0; - } - - return 1; -} - -int flexran_verify_group_ul_slices(mid_t mod_id, Protocol__FlexUlSlice **existing, - int n_ex, Protocol__FlexUlSlice **update, int n_up) -{ - int i, j, n; - int pct, pct_orig; - /* for every update, array "s" points to existing slice, or NULL if update - * creates new slice; array "offs" gives the offset of this slice */ - Protocol__FlexUlSlice *s[n_up]; - int offs[n_up]; - for (i = 0; i < n_up; i++) { - s[i] = NULL; - offs[i] = 0; - for (j = 0; j < n_ex; j++) { - if (existing[j]->id == update[i]->id) { - s[i] = existing[j]; - offs[i] = j; - } - } - } - - /* check that number of created and number of added slices in total matches - * [1,10] */ - n = n_ex; - for (i = 0; i < n_up; i++) { - /* new slice */ - if (!s[i]) n += 1; - /* slice will be deleted */ - else if (s[i]->percentage == 0) n -= 1; - /* else "only" an update */ - } - - if (n < 1 || n > 10) { - LOG_E(FLEXRAN_AGENT, "[%d] Illegal number of resulting UL slices (%d -> %d)\n", - mod_id, n_ex, n); - return 0; - } - - /* check that the sum of all slices percentages (including removed/added - * slices) matches [1,100] */ - pct = 0; - for (i = 0; i < n_ex; i++) { - pct += existing[i]->percentage; - } - pct_orig = pct; - for (i = 0; i < n_up; i++) { - /* if there is an existing slice, subtract its percentage and add the - * update's percentage */ - if (s[i]) - pct -= s[i]->percentage; - pct += update[i]->percentage; - } - if (pct < 1 || pct > 100) { - LOG_E(FLEXRAN_AGENT, "[%d] invalid total RB share (%d%% -> %d%%)\n", - mod_id, pct_orig, pct); - return 0; - } - - /* check that there is no overlap in slices resulting as the combination of - * first_rb and percentage */ - struct sregion_s sregion[n]; - const int N_RB = flexran_get_N_RB_UL(mod_id, 0); /* assume PCC */ - int k = n_ex; - for (i = 0; i < n_ex; i++) { - sregion[i].start = existing[i]->first_rb; - sregion[i].length = existing[i]->percentage * N_RB / 100; - } - for (i = 0; i < n_up; i++) { - ptrdiff_t d = s[i] ? offs[i] : k++; - AssertFatal(d >= 0 && d < k, "illegal pointer offset (%ld, k=%d)\n", d, k); - sregion[d].start = update[i]->first_rb; - sregion[d].length = update[i]->percentage * N_RB / 100; - } - AssertFatal(k == n, "illegal number of slices while calculating overlap\n"); - if (!check_ul_slice_overlap(mod_id, sregion, k)) { - LOG_E(FLEXRAN_AGENT, "[%d] UL slices are overlapping\n", mod_id); - return 0; - } - - return 1; -} - -int flexran_dl_slice_verify_pct(int pct) -{ - return pct >= 0 && pct <= 100; -} - -int flexran_dl_slice_verify_priority(int prio) -{ - return prio >= 0; -} - -int flexran_dl_slice_verify_position(int pos_low, int pos_high) -{ - return pos_low < pos_high && pos_low >= 0 && pos_high <= N_RBG_MAX; -} - -int flexran_dl_slice_verify_maxmcs(int maxmcs) -{ - return maxmcs >= 0 && maxmcs <= 28; -} - -int flexran_ul_slice_verify_pct(int pct) -{ - return pct >= 0 && pct <= 100; -} - -int flexran_ul_slice_verify_priority(int prio) -{ - return prio >= 0; -} - -int flexran_ul_slice_verify_first_rb(int first_rb) -{ - return first_rb >= 0 && first_rb < 100; -} - -int flexran_ul_slice_verify_maxmcs(int maxmcs) -{ - return maxmcs >= 0 && maxmcs <= 20; -} - -int sregion_compare(const void *_a, const void *_b) -{ - const struct sregion_s *a = (const struct sregion_s *)_a; - const struct sregion_s *b = (const struct sregion_s *)_b; - const int res = a->start - b->start; - if (res < 0) return -1; - else if (res == 0) return 0; - else return 1; -} - -int check_ul_slice_overlap(mid_t mod_id, struct sregion_s *sr, int n) -{ - int i; - int overlap, op, u; - const int N_RB = flexran_get_N_RB_UL(mod_id, 0); /* assume PCC */ - qsort(sr, n, sizeof(sr[0]), sregion_compare); - for (i = 0; i < n; i++) { - u = i == n-1 ? N_RB : sr[i+1].start; - AssertFatal(sr[i].start <= u, "unsorted slice list\n"); - overlap = sr[i].start + sr[i].length - u; - if (overlap <= 0) continue; - op = overlap * 100 / sr[i].length; - LOG_W(FLEXRAN_AGENT, "[%d] slice overlap of %d%% detected\n", mod_id, op); - if (op >= 10) /* more than 10% overlap -> refuse */ - return 0; - } - return 1; -} diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.h b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.h index a8f4030d36..c9e66b6f88 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.h +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.h @@ -29,9 +29,3 @@ #include "flexran_agent_common_internal.h" #include "flexran_agent_mac_internal.h" -int flexran_verify_dl_slice(mid_t mod_id, Protocol__FlexDlSlice *dls); -int flexran_verify_group_dl_slices(mid_t mod_id, Protocol__FlexDlSlice **existing, - int n_ex, Protocol__FlexDlSlice **update, int n_up); -int flexran_verify_ul_slice(mid_t mod_id, Protocol__FlexUlSlice *uls); -int flexran_verify_group_ul_slices(mid_t mod_id, Protocol__FlexUlSlice **existing, - int n_ex, Protocol__FlexUlSlice **update, int n_up); diff --git a/openair2/ENB_APP/MESSAGES/V2/config_common.proto b/openair2/ENB_APP/MESSAGES/V2/config_common.proto index 733d883c92..e5d01ebdc0 100644 --- a/openair2/ENB_APP/MESSAGES/V2/config_common.proto +++ b/openair2/ENB_APP/MESSAGES/V2/config_common.proto @@ -61,83 +61,6 @@ enum flex_qam { // // Slice config related structures and enums // -enum flex_dl_sorting { - - CR_ROUND = 0; // Highest HARQ first - CR_SRB12 = 1; // Highest SRB1+2 first - CR_HOL = 2; // Highest HOL first - CR_LC = 3; // Greatest RLC buffer first - CR_CQI = 4; // Highest CQI first - CR_LCP = 5; // Highest LC priority first -} - -enum flex_ul_sorting { - CRU_ROUND = 0; // Highest HARQ first - CRU_BUF = 1; // Highest BSR first - CRU_BTS = 2; // More bytes to schedule first - CRU_MCS = 3; // Highest MCS first - CRU_LCP = 4; // Highest LC priority first - CRU_HOL = 5; // Highest HOL first -} - -enum flex_dl_accounting_policy { - POL_FAIR = 0; - POL_GREEDY = 1; - POL_NUM = 2; -} - -enum flex_ul_accounting_policy { - POLU_FAIR = 0; - POLU_GREEDY = 1; - POLU_NUM = 2; -} - -enum flex_slice_label { - xMBB = 0; - URLLC = 1; - mMTC = 2; - xMTC = 3; - Other = 4; -} - -message flex_dl_slice { - optional uint32 id = 1; - optional flex_slice_label label = 2; - // should be between 0 and 100 - optional uint32 percentage = 3; - // whether this slice should be exempted form interslice sharing - optional bool isolation = 4; - // increasing value means increasing prio - optional uint32 priority = 5; - // min and max RB to use (in frequency) in the range [0, N_RBG_MAX] - optional uint32 position_low = 6; - optional uint32 position_high = 7; - // maximum MCS to be allowed in this slice - optional uint32 maxmcs = 8; - repeated flex_dl_sorting sorting = 9; - optional flex_dl_accounting_policy accounting = 10; - optional string scheduler_name = 11; -} - -message flex_ul_slice { - optional uint32 id = 1; - optional flex_slice_label label = 2; - // should be between 0 and 100 - optional uint32 percentage = 3; - // whether this slice should be exempted form interslice sharing - optional bool isolation = 4; - // increasing value means increasing prio - optional uint32 priority = 5; - // RB start to use (in frequency) in the range [0, N_RB_MAX] - optional uint32 first_rb = 6; - // TODO RB number - //optional uint32 length_rb = 7; - // maximum MCS to be allowed in this slice - optional uint32 maxmcs = 8; - repeated flex_ul_sorting sorting = 9; - optional flex_ul_accounting_policy accounting = 10; - optional string scheduler_name = 11; -} // // UE config related structures and enums diff --git a/openair2/ENB_APP/MESSAGES/V2/config_messages.proto b/openair2/ENB_APP/MESSAGES/V2/config_messages.proto index 324153613d..1a66a4f20f 100644 --- a/openair2/ENB_APP/MESSAGES/V2/config_messages.proto +++ b/openair2/ENB_APP/MESSAGES/V2/config_messages.proto @@ -49,14 +49,6 @@ message flex_cell_config { } message flex_slice_config { - // whether remaining RBs after first intra-slice allocation will - // be allocated to UEs of the same slice - optional bool intraslice_share_active = 3; - // whether remaining RBs after slice allocation will be allocated - // to UEs of another slice. Isolated slices will be ignored. - optional bool interslice_share_active = 4; - repeated flex_dl_slice dl = 1; - repeated flex_ul_slice ul = 2; } message flex_ue_config { diff --git a/openair2/ENB_APP/flexran_agent_common.c b/openair2/ENB_APP/flexran_agent_common.c index e77b2fb386..3dd9f5b957 100644 --- a/openair2/ENB_APP/flexran_agent_common.c +++ b/openair2/ENB_APP/flexran_agent_common.c @@ -316,25 +316,7 @@ int flexran_agent_destroy_enb_config_reply(Protocol__FlexranMessage *msg) { } if (reply->cell_config[i]->slice_config) { - for (int j = 0; j < reply->cell_config[i]->slice_config->n_dl; ++j) { - if (reply->cell_config[i]->slice_config->dl[j]->n_sorting > 0) - free(reply->cell_config[i]->slice_config->dl[j]->sorting); - - free(reply->cell_config[i]->slice_config->dl[j]->scheduler_name); - free(reply->cell_config[i]->slice_config->dl[j]); - } - - free(reply->cell_config[i]->slice_config->dl); - - for (int j = 0; j < reply->cell_config[i]->slice_config->n_ul; ++j) { - if (reply->cell_config[i]->slice_config->ul[j]->n_sorting > 0) - free(reply->cell_config[i]->slice_config->ul[j]->sorting); - - free(reply->cell_config[i]->slice_config->ul[j]->scheduler_name); - free(reply->cell_config[i]->slice_config->ul[j]); - } - - free(reply->cell_config[i]->slice_config->ul); + /* TODO */ free(reply->cell_config[i]->slice_config); } diff --git a/openair2/ENB_APP/flexran_agent_ran_api.c b/openair2/ENB_APP/flexran_agent_ran_api.c index 291c4dc7d8..cd8b0b8f67 100644 --- a/openair2/ENB_APP/flexran_agent_ran_api.c +++ b/openair2/ENB_APP/flexran_agent_ran_api.c @@ -3018,142 +3018,44 @@ int flexran_get_ue_dl_slice_id(mid_t mod_id, mid_t ue_id) { return 0; } -void flexran_set_ue_dl_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx) { - if (!mac_is_present(mod_id)) return; -} - int flexran_get_ue_ul_slice_id(mid_t mod_id, mid_t ue_id) { if (!mac_is_present(mod_id)) return -1; return 0; } -void flexran_set_ue_ul_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx) { - if (!mac_is_present(mod_id)) return; -} - -int flexran_dl_slice_exists(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return 0; -} - +/* TODO */ int flexran_create_dl_slice(mid_t mod_id, slice_id_t slice_id) { if (!mac_is_present(mod_id)) return -1; return -1; } +/* TODO */ +int flexran_remove_dl_slice(mid_t mod_id, int slice_idx) { + if (!mac_is_present(mod_id)) return -1; + return -1; +} + int flexran_find_dl_slice(mid_t mod_id, slice_id_t slice_id) { if (!mac_is_present(mod_id)) return -1; return -1; } -int flexran_remove_dl_slice(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} +//int flexran_get_dl_slice(mid_t mod_id, int slice_idx, Protocol__FlexSlice *s) { +//} int flexran_get_num_dl_slices(mid_t mod_id) { if (!mac_is_present(mod_id)) return -1; return 0; } -int flexran_get_intraslice_sharing_active(mid_t mod_id) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} -void flexran_set_intraslice_sharing_active(mid_t mod_id, int intraslice_active) { +/* TODO */ +void flexran_create_ul_slice(mid_t mod_id, slice_id_t slice_id) { if (!mac_is_present(mod_id)) return; + return; } -int flexran_get_interslice_sharing_active(mid_t mod_id) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} -void flexran_set_interslice_sharing_active(mid_t mod_id, int interslice_active) { - if (!mac_is_present(mod_id)) return; -} - -slice_id_t flexran_get_dl_slice_id(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} -void flexran_set_dl_slice_id(mid_t mod_id, int slice_idx, slice_id_t slice_id) { - if (!mac_is_present(mod_id)) return; -} - -int flexran_get_dl_slice_percentage(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} -void flexran_set_dl_slice_percentage(mid_t mod_id, int slice_idx, int percentage) { - if (!mac_is_present(mod_id)) return; -} - -int flexran_get_dl_slice_isolation(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} -void flexran_set_dl_slice_isolation(mid_t mod_id, int slice_idx, int is_isolated) { - if (!mac_is_present(mod_id)) return; -} - -int flexran_get_dl_slice_priority(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} -void flexran_set_dl_slice_priority(mid_t mod_id, int slice_idx, int priority) { - if (!mac_is_present(mod_id)) return; -} - -int flexran_get_dl_slice_position_low(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} -void flexran_set_dl_slice_position_low(mid_t mod_id, int slice_idx, int poslow) { - if (!mac_is_present(mod_id)) return; -} - -int flexran_get_dl_slice_position_high(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} -void flexran_set_dl_slice_position_high(mid_t mod_id, int slice_idx, int poshigh) { - if (!mac_is_present(mod_id)) return; -} - -int flexran_get_dl_slice_maxmcs(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} -void flexran_set_dl_slice_maxmcs(mid_t mod_id, int slice_idx, int maxmcs) { - if (!mac_is_present(mod_id)) return; -} - -int flexran_get_dl_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexDlSorting **sorting_list) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} -void flexran_set_dl_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexDlSorting *sorting_list, int n) { - if (!mac_is_present(mod_id)) return; -} - -Protocol__FlexDlAccountingPolicy flexran_get_dl_slice_accounting_policy(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_FAIR; - return PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_FAIR; -} -void flexran_set_dl_slice_accounting_policy(mid_t mod_id, int slice_idx, Protocol__FlexDlAccountingPolicy accounting) { - if (!mac_is_present(mod_id)) return; -} - -char *flexran_get_dl_slice_scheduler(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return NULL; - return NULL; -} -int flexran_set_dl_slice_scheduler(mid_t mod_id, int slice_idx, char *name) { - if (!mac_is_present(mod_id)) return 0; - return 0; -} - -int flexran_create_ul_slice(mid_t mod_id, slice_id_t slice_id) { +/* TODO */ +int flexran_remove_ul_slice(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; return -1; } @@ -3163,62 +3065,14 @@ int flexran_find_ul_slice(mid_t mod_id, slice_id_t slice_id) { return -1; } -int flexran_remove_ul_slice(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} +//int flexran_get_ul_slice(mid_t mod_id, int slice_idx, Protocol__FlexSlice *s) { +//} int flexran_get_num_ul_slices(mid_t mod_id) { if (!mac_is_present(mod_id)) return -1; return 0; } -int flexran_ul_slice_exists(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return 0; -} - -slice_id_t flexran_get_ul_slice_id(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} -void flexran_set_ul_slice_id(mid_t mod_id, int slice_idx, slice_id_t slice_id) { - if (!mac_is_present(mod_id)) return; -} - -int flexran_get_ul_slice_percentage(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} -void flexran_set_ul_slice_percentage(mid_t mod_id, int slice_idx, int percentage) { - if (!mac_is_present(mod_id)) return; -} - -int flexran_get_ul_slice_first_rb(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} - -void flexran_set_ul_slice_first_rb(mid_t mod_id, int slice_idx, int first_rb) { - if (!mac_is_present(mod_id)) return; -} - -int flexran_get_ul_slice_maxmcs(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} -void flexran_set_ul_slice_maxmcs(mid_t mod_id, int slice_idx, int maxmcs) { - if (!mac_is_present(mod_id)) return; -} - -char *flexran_get_ul_slice_scheduler(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return NULL; - return ""; -} -int flexran_set_ul_slice_scheduler(mid_t mod_id, int slice_idx, char *name) { - if (!mac_is_present(mod_id)) return 0; - return 0; -} /************************** S1AP **************************/ int flexran_get_s1ap_mme_pending(mid_t mod_id){ diff --git a/openair2/ENB_APP/flexran_agent_ran_api.h b/openair2/ENB_APP/flexran_agent_ran_api.h index 9d1bfb9d3e..c29ba53c11 100644 --- a/openair2/ENB_APP/flexran_agent_ran_api.h +++ b/openair2/ENB_APP/flexran_agent_ran_api.h @@ -659,153 +659,38 @@ uint32_t flexran_get_rrc_enb_ue_s1ap_id(mid_t mod_id, rnti_t rnti); /* Get the DL slice ID for a UE */ int flexran_get_ue_dl_slice_id(mid_t mod_id, mid_t ue_id); - /* Set the DL slice index(!) for a UE */ -void flexran_set_ue_dl_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx); +//void flexran_set_ue_dl_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx); /* Get the UL slice ID for a UE */ int flexran_get_ue_ul_slice_id(mid_t mod_id, mid_t ue_id); - /* Set the UL slice index(!) for a UE */ -void flexran_set_ue_ul_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx); +//void flexran_set_ue_ul_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx); -/* Whether intraslice sharing is active, return boolean */ -int flexran_get_intraslice_sharing_active(mid_t mod_id); -/* Set whether intraslice sharing is active */ -void flexran_set_intraslice_sharing_active(mid_t mod_id, int intraslice_active); - -/* Whether intraslice sharing is active, return boolean */ -int flexran_get_interslice_sharing_active(mid_t mod_id); -/* Set whether intraslice sharing is active */ -void flexran_set_interslice_sharing_active(mid_t mod_id, int interslice_active); +/* Create slice in DL, returns the new slice index */ +//int flexran_create_dl_slice(mid_t mod_id, slice_id_t slice_id); +/* Remove slice in DL, returns new number of slices or -1 on error */ +//int flexran_remove_dl_slice(mid_t mod_id, int slice_idx); +/* Finds slice in DL with given slice_id and returns slice index */ +int flexran_find_dl_slice(mid_t mod_id, slice_id_t slice_id); +/* Return the parameters of slice at index slice_idx */ +//void flexran_get_dl_slice(mid_t mod_id, int slice_idx, Protocol__FlexSlice *s); /* Get the number of slices in DL */ int flexran_get_num_dl_slices(mid_t mod_id); -/* Query slice existence in DL. Return is boolean value */ -int flexran_dl_slice_exists(mid_t mod_id, int slice_idx); +/* Create slice in UL, returns the new slice index */ +//int flexran_create_ul_slice(mid_t mod_id, slice_id_t slice_id); +/* Remove slice in UL */ +//int flexran_remove_ul_slice(mid_t mod_id, int slice_idx); -/* Create slice in DL, returns the new slice index */ -int flexran_create_dl_slice(mid_t mod_id, slice_id_t slice_id); /* Finds slice in DL with given slice_id and returns slice index */ -int flexran_find_dl_slice(mid_t mod_id, slice_id_t slice_id); -/* Remove slice in DL, returns new number of slices or -1 on error */ -int flexran_remove_dl_slice(mid_t mod_id, int slice_idx); - -/* Get the ID of a slice in DL */ -slice_id_t flexran_get_dl_slice_id(mid_t mod_id, int slice_idx); -/* Set the ID of a slice in DL */ -void flexran_set_dl_slice_id(mid_t mod_id, int slice_idx, slice_id_t slice_id); - -/* Get the RB share a slice in DL, value 0-100 */ -int flexran_get_dl_slice_percentage(mid_t mod_id, int slice_idx); -/* Set the RB share a slice in DL, value 0-100 */ -void flexran_set_dl_slice_percentage(mid_t mod_id, int slice_idx, int percentage); - -/* Whether a slice in DL is isolated */ -int flexran_get_dl_slice_isolation(mid_t mod_id, int slice_idx); -/* Set whether a slice in DL is isolated */ -void flexran_set_dl_slice_isolation(mid_t mod_id, int slice_idx, int is_isolated); - -/* Get the priority of a slice in DL */ -int flexran_get_dl_slice_priority(mid_t mod_id, int slice_idx); -/* Get the priority of a slice in DL */ -void flexran_set_dl_slice_priority(mid_t mod_id, int slice_idx, int priority); - -/* Get the lower end of the frequency range for the slice positioning in DL */ -int flexran_get_dl_slice_position_low(mid_t mod_id, int slice_idx); -/* Set the lower end of the frequency range for the slice positioning in DL */ -void flexran_set_dl_slice_position_low(mid_t mod_id, int slice_idx, int poslow); - -/* Get the higher end of the frequency range for the slice positioning in DL */ -int flexran_get_dl_slice_position_high(mid_t mod_id, int slice_idx); -/* Set the higher end of the frequency range for the slice positioning in DL */ -void flexran_set_dl_slice_position_high(mid_t mod_id, int slice_idx, int poshigh); - -/* Get the maximum MCS for slice in DL */ -int flexran_get_dl_slice_maxmcs(mid_t mod_id, int slice_idx); -/* Set the maximum MCS for slice in DL */ -void flexran_set_dl_slice_maxmcs(mid_t mod_id, int slice_idx, int maxmcs); - -/* Get the sorting order of a slice in DL, return value is number of elements - * in sorting_list */ -int flexran_get_dl_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexDlSorting **sorting_list); -/* Set the sorting order of a slice in DL */ -void flexran_set_dl_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexDlSorting *sorting_list, int n); - -/* Get the accounting policy for a slice in DL */ -Protocol__FlexDlAccountingPolicy flexran_get_dl_slice_accounting_policy(mid_t mod_id, int slice_idx); -/* Set the accounting policy for a slice in DL */ -void flexran_set_dl_slice_accounting_policy(mid_t mod_id, int slice_idx, Protocol__FlexDlAccountingPolicy accounting); - -/* Get the scheduler name for a slice in DL */ -char *flexran_get_dl_slice_scheduler(mid_t mod_id, int slice_idx); -/* Set the scheduler name for a slice in DL */ -int flexran_set_dl_slice_scheduler(mid_t mod_id, int slice_idx, char *name); - +int flexran_find_ul_slice(mid_t mod_id, slice_id_t slice_id); +/* Return the parameters of slice at index slice_idx */ +//void flexran_get_ul_slice(mid_t mod_id, int slice_idx, Protocol__FlexSlice *s); /* Get the number of slices in UL */ int flexran_get_num_ul_slices(mid_t mod_id); -/* Query slice existence in UL. Return is boolean value */ -int flexran_ul_slice_exists(mid_t mod_id, int slice_idx); - -/* Create slice in UL, returns the new slice index */ -int flexran_create_ul_slice(mid_t mod_id, slice_id_t slice_id); -/* Finds slice in UL with given slice_id and returns slice index */ -int flexran_find_ul_slice(mid_t mod_id, slice_id_t slice_id); -/* Remove slice in UL */ -int flexran_remove_ul_slice(mid_t mod_id, int slice_idx); - -/* Get the ID of a slice in UL */ -slice_id_t flexran_get_ul_slice_id(mid_t mod_id, int slice_idx); -/* Set the ID of a slice in UL */ -void flexran_set_ul_slice_id(mid_t mod_id, int slice_idx, slice_id_t slice_id); - -/* Get the RB share a slice in UL, value 0-100 */ -int flexran_get_ul_slice_percentage(mid_t mod_id, int slice_idx); -/* Set the RB share a slice in UL, value 0-100 */ -void flexran_set_ul_slice_percentage(mid_t mod_id, int slice_idx, int percentage); - -/* TODO Whether a slice in UL is isolated */ -/*int flexran_get_ul_slice_isolation(mid_t mod_id, int slice_idx);*/ -/* TODO Set whether a slice in UL is isolated */ -/*void flexran_set_ul_slice_isolation(mid_t mod_id, int slice_idx, int is_isolated);*/ - -/* TODO Get the priority of a slice in UL */ -/*int flexran_get_ul_slice_priority(mid_t mod_id, int slice_idx);*/ -/* TODO Set the priority of a slice in UL */ -/*void flexran_set_ul_slice_priority(mid_t mod_id, int slice_idx, int priority);*/ - -/* Get the first RB for allocation in a slice in UL */ -int flexran_get_ul_slice_first_rb(mid_t mod_id, int slice_idx); -/* Set the first RB for allocation in a slice in UL */ -void flexran_set_ul_slice_first_rb(mid_t mod_id, int slice_idx, int first_rb); - -/* TODO Get the number of RB for the allocation in a slice in UL */ -/*int flexran_get_ul_slice_length_rb(mid_t mod_id, int slice_idx);*/ -/* TODO Set the of number of RB for the allocation in a slice in UL */ -/*void flexran_set_ul_slice_length_rb(mid_t mod_id, int slice_idx, int poshigh);*/ - -/* Get the maximum MCS for slice in UL */ -int flexran_get_ul_slice_maxmcs(mid_t mod_id, int slice_idx); -/* Set the maximum MCS for slice in UL */ -void flexran_set_ul_slice_maxmcs(mid_t mod_id, int slice_idx, int maxmcs); - -/* TODO Get the sorting order of a slice in UL, return value is number of elements - * in sorting_list */ -/*int flexran_get_ul_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexUlSorting **sorting_list);*/ -/* TODO Set the sorting order of a slice in UL */ -/*void flexran_set_ul_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexUlSorting *sorting_list, int n);*/ - -/* TODO Get the accounting policy for a slice in UL */ -/*Protocol__UlAccountingPolicy flexran_get_ul_slice_accounting_policy(mid_t mod_id, int slice_idx);*/ -/* TODO Set the accounting policy for a slice in UL */ -/*void flexran_get_ul_slice_accounting_policy(mid_t mod_id, int slice_idx, Protocol__UlAccountingPolicy accountin);*/ - -/* Get the scheduler name for a slice in UL */ -char *flexran_get_ul_slice_scheduler(mid_t mod_id, int slice_idx); -/* Set the scheduler name for a slice in UL */ -int flexran_set_ul_slice_scheduler(mid_t mod_id, int slice_idx, char *name); /************************** S1AP **************************/ /* Get the number of MMEs to be connected */ From a21e9aa6ef4a840a343abab0da7e5df9153e8f4b Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Sun, 12 Apr 2020 15:16:21 +0200 Subject: [PATCH 426/553] Simplify add_ue_list(), remove_ue_list(); add init_ue_list() --- .../LAYER2/MAC/eNB_scheduler_primitives.c | 43 ++++++++++--------- openair2/LAYER2/MAC/mac_proto.h | 1 + openair2/LAYER2/MAC/main.c | 5 +-- 3 files changed, 25 insertions(+), 24 deletions(-) diff --git a/openair2/LAYER2/MAC/eNB_scheduler_primitives.c b/openair2/LAYER2/MAC/eNB_scheduler_primitives.c index 78d6f6a3d7..b75ab774c6 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_primitives.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_primitives.c @@ -2131,33 +2131,36 @@ dump_ue_list(UE_list_t *listP) { * Add a UE to UE_list listP */ inline void add_ue_list(UE_list_t *listP, int UE_id) { - if (listP->head == -1) { - listP->head = UE_id; - listP->next[UE_id] = -1; - } else { - int i = listP->head; - while (listP->next[i] >= 0) - i = listP->next[i]; - listP->next[i] = UE_id; - listP->next[UE_id] = -1; - } + int *cur = &listP->head; + while (*cur >= 0) + cur = &listP->next[*cur]; + *cur = UE_id; } //------------------------------------------------------------------------------ /* - * Remove a UE from the UE_list listP, return the previous element + * Remove a UE from the UE_list listP */ inline int remove_ue_list(UE_list_t *listP, int UE_id) { - listP->next[UE_id] = -1; - if (listP->head == UE_id) { - listP->head = listP->next[UE_id]; - return -1; - } + int *cur = &listP->head; + while (*cur != -1 && *cur != UE_id) + cur = &listP->next[*cur]; + if (*cur == -1) + return 0; + int *next = &listP->next[*cur]; + *cur = listP->next[*cur]; + *next = -1; + return 1; +} - int previous = prev(listP, UE_id); - if (previous != -1) - listP->next[previous] = listP->next[UE_id]; - return previous; +//------------------------------------------------------------------------------ +/* + * Initialize the UE_list listP + */ +inline void init_ue_list(UE_list_t *listP) { + listP->head = -1; + for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) + listP->next[i] = -1; } //------------------------------------------------------------------------------ diff --git a/openair2/LAYER2/MAC/mac_proto.h b/openair2/LAYER2/MAC/mac_proto.h index 61251ef088..818eb834fb 100644 --- a/openair2/LAYER2/MAC/mac_proto.h +++ b/openair2/LAYER2/MAC/mac_proto.h @@ -659,6 +659,7 @@ int prev(UE_list_t *listP, int nodeP); void add_ue_list(UE_list_t *listP, int UE_id); int remove_ue_list(UE_list_t *listP, int UE_id); void dump_ue_list(UE_list_t *listP); +void init_ue_list(UE_list_t *listP); int UE_num_active_CC(UE_info_t *listP, int ue_idP); int UE_PCCID(module_id_t mod_idP, int ue_idP); rnti_t UE_RNTI(module_id_t mod_idP, int ue_idP); diff --git a/openair2/LAYER2/MAC/main.c b/openair2/LAYER2/MAC/main.c index 35b5136889..659c7250e8 100644 --- a/openair2/LAYER2/MAC/main.c +++ b/openair2/LAYER2/MAC/main.c @@ -45,11 +45,8 @@ extern RAN_CONTEXT_t RC; void init_UE_info(UE_info_t *UE_info) { - int list_el; UE_info->num_UEs = 0; - UE_info->list.head = -1; - for (list_el = 0; list_el < MAX_MOBILES_PER_ENB; list_el++) - UE_info->list.next[list_el] = -1; + init_ue_list(&UE_info->list); memset(UE_info->DLSCH_pdu, 0, sizeof(UE_info->DLSCH_pdu)); memset(UE_info->UE_template, 0, sizeof(UE_info->UE_template)); memset(UE_info->eNB_UE_stats, 0, sizeof(UE_info->eNB_UE_stats)); From 115c1f38f6164786123c443ecac0df727123a07f Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Sun, 12 Apr 2020 14:38:05 +0200 Subject: [PATCH 427/553] Use fptr for preproc and align UL PP definition --- openair2/ENB_APP/enb_config.c | 9 +-- openair2/LAYER2/MAC/eNB_scheduler_dlsch.c | 5 +- .../LAYER2/MAC/eNB_scheduler_primitives.c | 12 ++++ openair2/LAYER2/MAC/eNB_scheduler_ulsch.c | 4 +- openair2/LAYER2/MAC/mac.h | 59 +++++++++++++++++-- openair2/LAYER2/MAC/mac_proto.h | 6 +- openair2/LAYER2/MAC/main.c | 13 ++-- openair2/LAYER2/MAC/pre_processor.c | 46 +++++++-------- 8 files changed, 110 insertions(+), 44 deletions(-) diff --git a/openair2/ENB_APP/enb_config.c b/openair2/ENB_APP/enb_config.c index 3bde7da02c..2e8ee0329f 100644 --- a/openair2/ENB_APP/enb_config.c +++ b/openair2/ENB_APP/enb_config.c @@ -266,10 +266,11 @@ void RCconfig_macrlc(int macrlc_has_f1[MAX_MAC_INST]) { void *d = dlsym(NULL, s); AssertFatal(d, "%s(): no default scheduler DL algo '%s' found\n", __func__, s); // release default, add new - RC.mac[j]->dl_algo.unset(&RC.mac[j]->dl_algo.data); - RC.mac[j]->dl_algo = *(default_sched_dl_algo_t *) d; - RC.mac[j]->dl_algo.data = RC.mac[j]->dl_algo.setup(); - LOG_I(ENB_APP, "using default scheduler DL algo '%s'\n", RC.mac[j]->dl_algo.name); + pp_impl_param_t *dl_pp = &RC.mac[j]->pre_processor_dl; + dl_pp->dl_algo.unset(&dl_pp->dl_algo.data); + dl_pp->dl_algo = *(default_sched_dl_algo_t *) d; + dl_pp->dl_algo.data = dl_pp->dl_algo.setup(); + LOG_I(ENB_APP, "using default scheduler DL algo '%s'\n", dl_pp->dl_algo.name); }// j=0..num_inst } /*else {// MacRLC_ParamList.numelt > 0 // ignore it diff --git a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c index 783d4e8b1a..1f99f50ece 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c @@ -573,10 +573,7 @@ schedule_ue_spec(module_id_t module_idP, VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DLSCH_PREPROCESSOR, VCD_FUNCTION_IN); start_meas(&eNB->schedule_dlsch_preprocessor); - dlsch_scheduler_pre_processor(module_idP, - CC_id, - frameP, - subframeP); + eNB->pre_processor_dl.dl(module_idP, CC_id, frameP, subframeP); stop_meas(&eNB->schedule_dlsch_preprocessor); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DLSCH_PREPROCESSOR, VCD_FUNCTION_OUT); diff --git a/openair2/LAYER2/MAC/eNB_scheduler_primitives.c b/openair2/LAYER2/MAC/eNB_scheduler_primitives.c index b75ab774c6..89c2ecc83d 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_primitives.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_primitives.c @@ -2199,6 +2199,12 @@ add_new_ue(module_id_t mod_idP, UE_info->active[UE_id] = TRUE; add_ue_list(&UE_info->list, UE_id); dump_ue_list(&UE_info->list); + pp_impl_param_t* dl = &RC.mac[mod_idP]->pre_processor_dl; + if (dl->slices) // inform slice implementation about new UE + dl->add_UE(dl->slices, UE_id); + pp_impl_param_t* ul = &RC.mac[mod_idP]->pre_processor_ul; + if (ul->slices) // inform slice implementation about new UE + ul->add_UE(ul->slices, UE_id); if (IS_SOFTMODEM_IQPLAYER)// not specific to record/playback ? UE_info->UE_template[cc_idP][UE_id].pre_assigned_mcs_ul = 0; UE_info->UE_template[cc_idP][UE_id].rach_resource_type = rach_resource_type; @@ -2262,6 +2268,12 @@ rrc_mac_remove_ue(module_id_t mod_idP, UE_info->num_UEs--; remove_ue_list(&UE_info->list, UE_id); + pp_impl_param_t* dl = &RC.mac[mod_idP]->pre_processor_dl; + if (dl->slices) // inform slice implementation about new UE + dl->remove_UE(dl->slices, UE_id); + pp_impl_param_t* ul = &RC.mac[mod_idP]->pre_processor_ul; + if (ul->slices) // inform slice implementation about new UE + ul->remove_UE(ul->slices, UE_id); /* Clear all remaining pending transmissions */ memset(&UE_info->UE_template[pCC_id][UE_id], 0, sizeof(UE_TEMPLATE)); diff --git a/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c b/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c index 3062e5c964..2de45db856 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c @@ -1301,11 +1301,11 @@ schedule_ulsch_rnti(module_id_t module_idP, /* * ULSCH preprocessor: set UE_template-> - * pre_allocated_nb_rb_ul[slice_idx] + * pre_allocated_nb_rb_ul * pre_assigned_mcs_ul * pre_allocated_rb_table_index_ul */ - ulsch_scheduler_pre_processor(module_idP, CC_id, frameP, subframeP, sched_frame, sched_subframeP); + mac->pre_processor_ul.ul(module_idP, CC_id, frameP, subframeP, sched_frame, sched_subframeP); for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { if (UE_info->UE_template[CC_id][UE_id].rach_resource_type > 0) diff --git a/openair2/LAYER2/MAC/mac.h b/openair2/LAYER2/MAC/mac.h index 8349d84d48..faefc481f6 100644 --- a/openair2/LAYER2/MAC/mac.h +++ b/openair2/LAYER2/MAC/mac.h @@ -540,7 +540,6 @@ typedef enum { SCHED_MODE_FAIR_RR /// fair raund robin } SCHEDULER_MODES; - /*! \brief temporary struct for ULSCH sched */ typedef struct { rnti_t rnti; @@ -1199,6 +1198,56 @@ typedef struct { void *data; } default_sched_ul_algo_t; +typedef void (*pp_impl_dl)(module_id_t mod_id, + int CC_id, + frame_t frame, + sub_frame_t subframe); +typedef void (*pp_impl_ul)(module_id_t mod_id, + int CC_id, + frame_t frame, + sub_frame_t subframe, + frame_t sched_frame, + sub_frame_t sched_subframe); + +struct slice_info_s; +typedef struct { + int algorithm; + + /// inform the slice algorithm about a new UE + void (*add_UE)(struct slice_info_s *s, int UE_id); + /// inform the slice algorithm about a UE that disconnected + void (*remove_UE)(struct slice_info_s *s, int UE_id); + /// move a UE to a slice in DL/UL, -1 means don't move (no-op). + void (*move_UE)(struct slice_info_s *s, int UE_id, int idx); + + /// Adds a new slice through admission control. slice_params are + /// algorithm-specific parameters. sched is either a default_sched_ul_algo_t + /// or default_sched_dl_algo_t, depending on whether this implementation + /// handles UL/DL. If slice at index exists, updates existing + /// slice. Returns index of new slice or -1 on failure. + int (*addmod_slice)(struct slice_info_s *s, + int id, + char *label, + void *sched, + void *slice_params); + /// Returns slice through slice_idx. 1 if successful, 0 if not. + int (*remove_slice)(struct slice_info_s *s, uint8_t slice_idx); + + union { + pp_impl_dl dl; + pp_impl_ul ul; + }; + + union { + default_sched_ul_algo_t ul_algo; + default_sched_dl_algo_t dl_algo; + }; + + void (*destroy)(struct slice_info_s **s); + + struct slice_info_s *slices; +} pp_impl_param_t; + /*! \brief eNB common channels */ typedef struct { int physCellId; @@ -1354,9 +1403,11 @@ typedef struct eNB_MAC_INST_s { UE_free_list_t UE_free_list; /// for scheduling selection SCHEDULER_MODES scheduler_mode; - /// scheduling algorithm used in default scheduler - default_sched_dl_algo_t dl_algo; - default_sched_ul_algo_t ul_algo; + /// Default scheduler: Pre-processor implementation. Algorithms for UL/DL + /// are called by ULSCH/DLSCH, respectively. Pro-processor implementation can + /// encapsulate slicing. + pp_impl_param_t pre_processor_dl; + pp_impl_param_t pre_processor_ul; int32_t puSch10xSnr; int32_t puCch10xSnr; diff --git a/openair2/LAYER2/MAC/mac_proto.h b/openair2/LAYER2/MAC/mac_proto.h index 818eb834fb..9d49fdffd5 100644 --- a/openair2/LAYER2/MAC/mac_proto.h +++ b/openair2/LAYER2/MAC/mac_proto.h @@ -674,10 +674,10 @@ void set_ul_DAI(int module_idP, void ulsch_scheduler_pre_processor(module_id_t module_idP, int CC_id, - int frameP, + frame_t frameP, sub_frame_t subframeP, - int sched_frameP, - unsigned char sched_subframeP); + frame_t sched_frameP, + sub_frame_t sched_subframeP); int phy_stats_exist(module_id_t Mod_id, int rnti); diff --git a/openair2/LAYER2/MAC/main.c b/openair2/LAYER2/MAC/main.c index 659c7250e8..24038e60d5 100644 --- a/openair2/LAYER2/MAC/main.c +++ b/openair2/LAYER2/MAC/main.c @@ -99,16 +99,21 @@ void mac_top_init_eNB(void) } mac[i]->if_inst = IF_Module_init(i); + + mac[i]->pre_processor_dl.dl = dlsch_scheduler_pre_processor; char *s = "round_robin_dl"; void *d = dlsym(NULL, s); AssertFatal(d, "%s(): no scheduler algo '%s' found\n", __func__, s); - mac[i]->dl_algo = *(default_sched_dl_algo_t *) d; - mac[i]->dl_algo.data = mac[i]->dl_algo.setup(); + mac[i]->pre_processor_dl.dl_algo = *(default_sched_dl_algo_t *) d; + mac[i]->pre_processor_dl.dl_algo.data = mac[i]->pre_processor_dl.dl_algo.setup(); + + mac[i]->pre_processor_ul.ul = ulsch_scheduler_pre_processor; s = "round_robin_ul"; d = dlsym(NULL, s); AssertFatal(d, "%s(): no scheduler algo '%s' found\n", __func__, s); - mac[i]->ul_algo = *(default_sched_ul_algo_t *) d; - mac[i]->ul_algo.data = mac[i]->ul_algo.setup(); + mac[i]->pre_processor_ul.ul_algo = *(default_sched_ul_algo_t *) d; + mac[i]->pre_processor_ul.ul_algo.data = mac[i]->pre_processor_ul.ul_algo.setup(); + init_UE_info(&mac[i]->UE_info); } diff --git a/openair2/LAYER2/MAC/pre_processor.c b/openair2/LAYER2/MAC/pre_processor.c index 5eb27699be..b39ce62bb7 100644 --- a/openair2/LAYER2/MAC/pre_processor.c +++ b/openair2/LAYER2/MAC/pre_processor.c @@ -691,15 +691,15 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id, n_rbg_sched += rbgalloc_mask[i]; } - mac->dl_algo.run(Mod_id, - CC_id, - frameP, - subframeP, - &UE_to_sched, - 4, // max_num_ue - n_rbg_sched, - rbgalloc_mask, - mac->dl_algo.data); + mac->pre_processor_dl.dl_algo.run(Mod_id, + CC_id, + frameP, + subframeP, + &UE_to_sched, + 4, // max_num_ue + n_rbg_sched, + rbgalloc_mask, + mac->pre_processor_dl.dl_algo.data); // the following block is meant for validation of the pre-processor to check // whether all UE allocations are non-overlapping and is not necessary for @@ -1068,10 +1068,10 @@ default_sched_ul_algo_t round_robin_ul = { void ulsch_scheduler_pre_processor(module_id_t Mod_id, int CC_id, - int frameP, + frame_t frameP, sub_frame_t subframeP, - int sched_frameP, - unsigned char sched_subframeP) { + frame_t sched_frameP, + sub_frame_t sched_subframeP) { eNB_MAC_INST *mac = RC.mac[Mod_id]; UE_info_t *UE_info = &mac->UE_info; const int N_RB_UL = to_prb(mac->common_channels[CC_id].ul_Bandwidth); @@ -1128,17 +1128,17 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id, } } - mac->ul_algo.run(Mod_id, - CC_id, - frameP, - subframeP, - sched_frameP, - sched_subframeP, - &UE_to_sched, - 4, // max_num_ue - n_contig, - rbs, - mac->ul_algo.data); + mac->pre_processor_ul.ul_algo.run(Mod_id, + CC_id, + frameP, + subframeP, + sched_frameP, + sched_subframeP, + &UE_to_sched, + 4, // max_num_ue + n_contig, + rbs, + mac->pre_processor_ul.ul_algo.data); // the following block is meant for validation of the pre-processor to check // whether all UE allocations are non-overlapping and is not necessary for From d2fe5af67a844744c3b455a0129397ee5e4c1e2f Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Sun, 12 Apr 2020 18:33:55 +0200 Subject: [PATCH 428/553] Implement Static Slicing --- cmake_targets/CMakeLists.txt | 1 + openair2/LAYER2/MAC/slicing/slicing.c | 586 ++++++++++++++++++ openair2/LAYER2/MAC/slicing/slicing.h | 74 +++ .../LAYER2/MAC/slicing/slicing_internal.h | 46 ++ 4 files changed, 707 insertions(+) create mode 100644 openair2/LAYER2/MAC/slicing/slicing.c create mode 100644 openair2/LAYER2/MAC/slicing/slicing.h create mode 100644 openair2/LAYER2/MAC/slicing/slicing_internal.h diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index 525c9eae56..8d964821c0 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -1830,6 +1830,7 @@ set (MAC_SRC ${MAC_DIR}/eNB_scheduler_fairRR.c ${MAC_DIR}/eNB_scheduler_phytest.c ${MAC_DIR}/pre_processor.c + ${MAC_DIR}/slicing/slicing.c ${MAC_DIR}/config.c ${MAC_DIR}/config_ue.c ) diff --git a/openair2/LAYER2/MAC/slicing/slicing.c b/openair2/LAYER2/MAC/slicing/slicing.c new file mode 100644 index 0000000000..a1de326df0 --- /dev/null +++ b/openair2/LAYER2/MAC/slicing/slicing.c @@ -0,0 +1,586 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! + * \file slicing.c + * \brief Generic slicing helper functions and Static Slicing Implementation + * \author Robert Schmidt + * \date 2020 + * \email robert.schmidt@eurecom.fr + */ + +#define _GNU_SOURCE +#include +#include + +#include "assertions.h" +#include "common/utils/LOG/log.h" + +#include "slicing.h" +#include "slicing_internal.h" + +#include "common/ran_context.h" +extern RAN_CONTEXT_t RC; + +#define RET_FAIL(ret, x...) do { LOG_E(MAC, x); return ret; } while (0) + +int slicing_get_UE_slice_idx(slice_info_t *si, int UE_id) { + return si->UE_assoc_slice[UE_id]; +} + +void slicing_add_UE(slice_info_t *si, int UE_id) { + add_ue_list(&si->s[0]->UEs, UE_id); + si->UE_assoc_slice[UE_id] = 0; +} + +void _remove_UE(slice_t **s, uint8_t *assoc, int UE_id) { + const uint8_t i = assoc[UE_id]; + DevAssert(remove_ue_list(&s[i]->UEs, UE_id)); + assoc[UE_id] = -1; +} + +void slicing_remove_UE(slice_info_t *si, int UE_id) { + _remove_UE(si->s, si->UE_assoc_slice, UE_id); +} + +void _move_UE(slice_t **s, uint8_t *assoc, int UE_id, int to) { + const uint8_t i = assoc[UE_id]; + const int ri = remove_ue_list(&s[i]->UEs, UE_id); + if (!ri) + LOG_W(MAC, "did not find UE %d in DL slice index %d\n", UE_id, i); + add_ue_list(&s[to]->UEs, UE_id); + assoc[UE_id] = to; +} + +void slicing_move_UE(slice_info_t *si, int UE_id, int idx) { + DevAssert(idx >= -1 && idx < si->num); + if (idx >= 0) + _move_UE(si->s, si->UE_assoc_slice, UE_id, idx); +} + +int _exists_slice(uint8_t n, slice_t **s, int id) { + for (int i = 0; i < n; ++i) + if (s[i]->id == id) + return i; + return -1; +} + +slice_t *_add_slice(uint8_t *n, slice_t **s) { + s[*n] = calloc(1, sizeof(slice_t)); + if (!s[*n]) + return NULL; + init_ue_list(&s[*n]->UEs); + *n += 1; + return s[*n - 1]; +} + +slice_t *_remove_slice(uint8_t *n, slice_t **s, uint8_t *assoc, int idx) { + if (idx >= *n) + return NULL; + + slice_t *sr = s[idx]; + while (sr->UEs.head >= 0) + _move_UE(s, assoc, sr->UEs.head, 0); + + for (int i = idx + 1; i < *n; ++i) + s[i - 1] = s[i]; + *n -= 1; + s[*n] = NULL; + + for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) + if (assoc[i] > idx) + assoc[i] -= 1; + + if (sr->label) + free(sr->label); + + return sr; +} + +/************************ Static Slicing Implementation ************************/ + +int addmod_static_slice_dl(slice_info_t *si, + int id, + char *label, + void *algo, + void *slice_params_dl) { + static_slice_param_t *dl = slice_params_dl; + if (dl && dl->posLow > dl->posHigh) + RET_FAIL(-1, "%s(): slice id %d posLow > posHigh\n", __func__, id); + + uint8_t rbgMap[25] = { 0 }; + int index = _exists_slice(si->num, si->s, id); + if (index >= 0) { + for (int s = 0; s < si->num; ++s) { + static_slice_param_t *sd = dl && si->s[s]->id == id ? dl : si->s[s]->algo_data; + for (int i = sd->posLow; i <= sd->posHigh; ++i) { + if (rbgMap[i]) + RET_FAIL(-33, "%s(): overlap of slices detected at RBG %d\n", __func__, i); + rbgMap[i] = 1; + } + } + /* no problem, can allocate */ + slice_t *s = si->s[index]; + if (label) { + if (s->label) free(s->label); + s->label = label; + } + if (algo) { + s->dl_algo.unset(&s->dl_algo.data); + s->dl_algo = *(default_sched_dl_algo_t *) algo; + if (!s->dl_algo.data) + s->dl_algo.data = s->dl_algo.setup(); + } + if (dl) { + free(s->algo_data); + s->algo_data = dl; + } + return index; + } + + if (!dl) + RET_FAIL(-100, "%s(): no parameters for new slice %d, aborting\n", __func__, id); + + if (si->num >= MAX_STATIC_SLICES) + RET_FAIL(-2, "%s(): cannot have more than %d slices\n", __func__, MAX_STATIC_SLICES); + for (int s = 0; s < si->num; ++s) { + static_slice_param_t *sd = si->s[s]->algo_data; + for (int i = sd->posLow; i <= sd->posHigh; ++i) + rbgMap[i] = 1; + } + + for (int i = dl->posLow; i <= dl->posHigh; ++i) + if (rbgMap[i]) + RET_FAIL(-3, "%s(): overlap of slices detected at RBG %d\n", __func__, i); + + if (!algo) + RET_FAIL(-14, "%s(): no scheduler algorithm provided\n", __func__); + + slice_t *ns = _add_slice(&si->num, si->s); + if (!ns) + RET_FAIL(-4, "%s(): could not create new slice\n", __func__); + ns->id = id; + ns->label = label; + ns->dl_algo = *(default_sched_dl_algo_t *) algo; + if (!ns->dl_algo.data) + ns->dl_algo.data = ns->dl_algo.setup(); + ns->algo_data = dl; + + return si->num - 1; +} + +int addmod_static_slice_ul(slice_info_t *si, + int id, + char *label, + void *algo, + void *slice_params_ul) { + static_slice_param_t *ul = slice_params_ul; + /* Minimum 3RBs, because LTE stack requires this */ + if (ul && ul->posLow + 2 > ul->posHigh) + RET_FAIL(-1, "%s(): slice id %d posLow + 2 > posHigh\n", __func__, id); + + uint8_t rbMap[110] = { 0 }; + int index = _exists_slice(si->num, si->s, id); + if (index >= 0) { + for (int s = 0; s < si->num; ++s) { + static_slice_param_t *su = ul && si->s[s]->id == id && ul ? ul : si->s[s]->algo_data; + for (int i = su->posLow; i <= su->posHigh; ++i) { + if (rbMap[i]) + RET_FAIL(-33, "%s(): overlap of slices detected at RBG %d\n", __func__, i); + rbMap[i] = 1; + } + } + /* no problem, can allocate */ + slice_t *s = si->s[index]; + if (algo) { + s->ul_algo.unset(&s->ul_algo.data); + s->ul_algo = *(default_sched_ul_algo_t *) algo; + if (!s->ul_algo.data) + s->ul_algo.data = s->ul_algo.setup(); + } + if (label) { + if (s->label) free(s->label); + s->label = label; + } + if (ul) { + free(s->algo_data); + s->algo_data = ul; + } + return index; + } + + if (!ul) + RET_FAIL(-100, "%s(): no parameters for new slice %d, aborting\n", __func__, id); + + if (si->num >= MAX_STATIC_SLICES) + RET_FAIL(-2, "%s(): cannot have more than %d slices\n", __func__, MAX_STATIC_SLICES); + for (int s = 0; s < si->num; ++s) { + static_slice_param_t *sd = si->s[s]->algo_data; + for (int i = sd->posLow; i <= sd->posHigh; ++i) + rbMap[i] = 1; + } + + for (int i = ul->posLow; i <= ul->posHigh; ++i) + if (rbMap[i]) + RET_FAIL(-3, "%s(): overlap of slices detected at RBG %d\n", __func__, i); + + if (!algo) + RET_FAIL(-14, "%s(): no scheduler algorithm provided\n", __func__); + + slice_t *ns = _add_slice(&si->num, si->s); + if (!ns) + RET_FAIL(-4, "%s(): could not create new slice\n", __func__); + ns->id = id; + ns->label = label; + ns->ul_algo = *(default_sched_ul_algo_t *) algo; + if (!ns->ul_algo.data) + ns->ul_algo.data = ns->ul_algo.setup(); + ns->algo_data = ul; + + return si->num - 1; +} + +int remove_static_slice(slice_info_t *si, uint8_t slice_idx) { + if (slice_idx == 0) + return 0; + slice_t *sr = _remove_slice(&si->num, si->s, si->UE_assoc_slice, slice_idx); + if (!sr) + return 0; + free(sr->algo_data); + free(sr); + return 1; +} + +void static_dl(module_id_t mod_id, + int CC_id, + frame_t frame, + sub_frame_t subframe) { + UE_info_t *UE_info = &RC.mac[mod_id]->UE_info; + + store_dlsch_buffer(mod_id, CC_id, frame, subframe); + + for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { + UE_sched_ctrl_t *ue_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; + + /* initialize per-UE scheduling information */ + ue_sched_ctrl->pre_nb_available_rbs[CC_id] = 0; + ue_sched_ctrl->dl_pow_off[CC_id] = 2; + memset(ue_sched_ctrl->rballoc_sub_UE[CC_id], 0, sizeof(ue_sched_ctrl->rballoc_sub_UE[CC_id])); + ue_sched_ctrl->pre_dci_dl_pdu_idx = -1; + } + + const int N_RBG = to_rbg(RC.mac[mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth); + const int RBGsize = get_min_rb_unit(mod_id, CC_id); + uint8_t *vrb_map = RC.mac[mod_id]->common_channels[CC_id].vrb_map; + uint8_t rbgalloc_mask[N_RBG_MAX]; + for (int i = 0; i < N_RBG; i++) { + // calculate mask: init to one + "AND" with vrb_map: + // if any RB in vrb_map is blocked (1), the current RBG will be 0 + rbgalloc_mask[i] = 1; + for (int j = 0; j < RBGsize; j++) + rbgalloc_mask[i] &= !vrb_map[RBGsize * i + j]; + } + + slice_info_t *s = RC.mac[mod_id]->pre_processor_dl.slices; + int max_num_ue; + switch (s->num) { + case 1: + max_num_ue = 4; + break; + case 2: + max_num_ue = 2; + break; + default: + max_num_ue = 1; + break; + } + for (int i = 0; i < s->num; ++i) { + if (s->s[i]->UEs.head < 0) + continue; + uint8_t rbgalloc_slice_mask[N_RBG_MAX]; + memset(rbgalloc_slice_mask, 0, sizeof(rbgalloc_slice_mask)); + static_slice_param_t *p = s->s[i]->algo_data; + int n_rbg_sched = 0; + for (int rbg = p->posLow; rbg <= p->posHigh && rbg <= N_RBG; ++rbg) { + rbgalloc_slice_mask[rbg] = rbgalloc_mask[rbg]; + n_rbg_sched += rbgalloc_mask[rbg]; + } + + s->s[i]->dl_algo.run(mod_id, + CC_id, + frame, + subframe, + &s->s[i]->UEs, + max_num_ue, // max_num_ue + n_rbg_sched, + rbgalloc_slice_mask, + s->s[i]->dl_algo.data); + } + + // the following block is meant for validation of the pre-processor to check + // whether all UE allocations are non-overlapping and is not necessary for + // scheduling functionality + char t[26] = "_________________________"; + t[N_RBG] = 0; + for (int i = 0; i < N_RBG; i++) + for (int j = 0; j < RBGsize; j++) + if (vrb_map[RBGsize*i+j] != 0) + t[i] = 'x'; + int print = 0; + for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { + const UE_sched_ctrl_t *ue_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; + + if (ue_sched_ctrl->pre_nb_available_rbs[CC_id] == 0) + continue; + + LOG_D(MAC, + "%4d.%d UE%d %d RBs allocated, pre MCS %d\n", + frame, + subframe, + UE_id, + ue_sched_ctrl->pre_nb_available_rbs[CC_id], + UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1); + + print = 1; + + for (int i = 0; i < N_RBG; i++) { + if (!ue_sched_ctrl->rballoc_sub_UE[CC_id][i]) + continue; + for (int j = 0; j < RBGsize; j++) { + if (vrb_map[RBGsize*i+j] != 0) { + LOG_I(MAC, "%4d.%d DL scheduler allocation list: %s\n", frame, subframe, t); + LOG_E(MAC, "%4d.%d: UE %d allocated at locked RB %d/RBG %d\n", frame, + subframe, UE_id, RBGsize * i + j, i); + } + vrb_map[RBGsize*i+j] = 1; + } + t[i] = '0' + UE_id; + } + } + if (print) + LOG_D(MAC, "%4d.%d DL scheduler allocation list: %s\n", frame, subframe, t); +} + +void static_ul(module_id_t mod_id, + int CC_id, + frame_t frame, + sub_frame_t subframe, + frame_t sched_frame, + sub_frame_t sched_subframe) { + UE_info_t *UE_info = &RC.mac[mod_id]->UE_info; + const int N_RB_UL = to_prb(RC.mac[mod_id]->common_channels[CC_id].ul_Bandwidth); + COMMON_channels_t *cc = &RC.mac[mod_id]->common_channels[CC_id]; + + for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { + UE_TEMPLATE *UE_template = &UE_info->UE_template[CC_id][UE_id]; + UE_template->pre_assigned_mcs_ul = 0; + UE_template->pre_allocated_nb_rb_ul = 0; + UE_template->pre_allocated_rb_table_index_ul = -1; + UE_template->pre_first_nb_rb_ul = 0; + UE_template->pre_dci_ul_pdu_idx = -1; + } + + slice_info_t *s = RC.mac[mod_id]->pre_processor_ul.slices; + int max_num_ue; + switch (s->num) { + case 1: + max_num_ue = 4; + break; + case 2: + max_num_ue = 2; + break; + default: + max_num_ue = 1; + break; + } + for (int i = 0; i < s->num; ++i) { + if (s->s[i]->UEs.head < 0) + continue; + int last_rb_blocked = 1; + int n_contig = 0; + contig_rbs_t rbs[2]; // up to two contig RBs for PRACH in between + static_slice_param_t *p = s->s[i]->algo_data; + for (int rb = p->posLow; rb <= p->posHigh && rb < N_RB_UL; ++rb) { + if (cc->vrb_map_UL[rb] == 0 && last_rb_blocked) { + last_rb_blocked = 0; + n_contig++; + AssertFatal(n_contig <= 2, "cannot handle more than two contiguous RB regions\n"); + rbs[n_contig - 1].start = rb; + } + if (cc->vrb_map_UL[rb] == 1 && !last_rb_blocked) { + last_rb_blocked = 1; + rbs[n_contig - 1].length = rb - rbs[n_contig - 1].start; + } + } + if (!last_rb_blocked) + rbs[n_contig - 1].length = p->posHigh - rbs[n_contig - 1].start + 1; + + s->s[i]->ul_algo.run(mod_id, + CC_id, + frame, + subframe, + sched_frame, + sched_subframe, + &s->s[i]->UEs, + max_num_ue, // max_num_ue + n_contig, + rbs, + s->s[i]->ul_algo.data); + } + + // the following block is meant for validation of the pre-processor to check + // whether all UE allocations are non-overlapping and is not necessary for + // scheduling functionality + char t[101] = "__________________________________________________" + "__________________________________________________"; + t[N_RB_UL] = 0; + for (int j = 0; j < N_RB_UL; j++) + if (cc->vrb_map_UL[j] != 0) + t[j] = 'x'; + int print = 0; + for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { + UE_TEMPLATE *UE_template = &UE_info->UE_template[CC_id][UE_id]; + if (UE_template->pre_allocated_nb_rb_ul == 0) + continue; + + print = 1; + uint8_t harq_pid = subframe2harqpid(&RC.mac[mod_id]->common_channels[CC_id], + sched_frame, sched_subframe); + LOG_D(MAC, "%4d.%d UE%d %d RBs (index %d) at start %d, pre MCS %d %s\n", + frame, + subframe, + UE_id, + UE_template->pre_allocated_nb_rb_ul, + UE_template->pre_allocated_rb_table_index_ul, + UE_template->pre_first_nb_rb_ul, + UE_template->pre_assigned_mcs_ul, + UE_info->UE_sched_ctrl[UE_id].round_UL[CC_id][harq_pid] > 0 ? "(retx)" : ""); + + for (int i = 0; i < UE_template->pre_allocated_nb_rb_ul; ++i) { + /* only check if this is not a retransmission */ + if (UE_info->UE_sched_ctrl[UE_id].round_UL[CC_id][harq_pid] == 0 + && cc->vrb_map_UL[UE_template->pre_first_nb_rb_ul + i] == 1) { + + LOG_I(MAC, "%4d.%d UL scheduler allocation list: %s\n", frame, subframe, t); + LOG_E(MAC, + "%4d.%d: UE %d allocated at locked RB %d (is: allocated start " + "%d/length %d)\n", + frame, subframe, UE_id, UE_template->pre_first_nb_rb_ul + i, + UE_template->pre_first_nb_rb_ul, + UE_template->pre_allocated_nb_rb_ul); + } + cc->vrb_map_UL[UE_template->pre_first_nb_rb_ul + i] = 1; + t[UE_template->pre_first_nb_rb_ul + i] = UE_id + '0'; + } + } + if (print) + LOG_D(MAC, + "%4d.%d UL scheduler allocation list: %s\n", + sched_frame, + sched_subframe, + t); +} + +void static_destroy(slice_info_t **si) { + const int n = (*si)->num; + (*si)->num = 0; + for (int i = 0; i < n; ++i) { + slice_t *s = (*si)->s[i]; + if (s->label) + free(s->label); + free(s->algo_data); + free(s); + } + free((*si)->s); + free(*si); +} + +pp_impl_param_t static_dl_init(module_id_t mod_id, int CC_id) { + slice_info_t *si = calloc(1, sizeof(slice_info_t)); + DevAssert(si); + + si->num = 0; + si->s = calloc(MAX_STATIC_SLICES, sizeof(slice_t)); + DevAssert(si->s); + for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) + si->UE_assoc_slice[i] = -1; + + /* insert default slice, all resources */ + static_slice_param_t *dlp = malloc(sizeof(static_slice_param_t)); + dlp->posLow = 0; + dlp->posHigh = to_rbg(RC.mac[mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth) - 1; + default_sched_dl_algo_t *algo = &RC.mac[mod_id]->pre_processor_dl.dl_algo; + DevAssert(0 == addmod_static_slice_dl(si, 0, strdup("default"), algo, dlp)); + const UE_list_t *UE_list = &RC.mac[mod_id]->UE_info.list; + for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) + slicing_add_UE(si, UE_id); + + pp_impl_param_t sttc; + sttc.algorithm = STATIC_SLICING; + sttc.add_UE = slicing_add_UE; + sttc.remove_UE = slicing_remove_UE; + sttc.move_UE = slicing_move_UE; + sttc.addmod_slice = addmod_static_slice_dl; + sttc.remove_slice = remove_static_slice; + sttc.dl = static_dl; + // current DL algo becomes default scheduler + sttc.dl_algo = *algo; + sttc.destroy = static_destroy; + sttc.slices = si; + + return sttc; +} + +pp_impl_param_t static_ul_init(module_id_t mod_id, int CC_id) { + slice_info_t *si = calloc(1, sizeof(slice_info_t)); + DevAssert(si); + + si->num = 0; + si->s = calloc(MAX_STATIC_SLICES, sizeof(slice_t)); + DevAssert(si->s); + for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) + si->UE_assoc_slice[i] = -1; + + /* insert default slice, all resources */ + static_slice_param_t *ulp = malloc(sizeof(static_slice_param_t)); + ulp->posLow = 0; + ulp->posHigh = to_prb(RC.mac[mod_id]->common_channels[CC_id].ul_Bandwidth) - 1; + default_sched_ul_algo_t *algo = &RC.mac[mod_id]->pre_processor_ul.ul_algo; + DevAssert(0 == addmod_static_slice_ul(si, 0, strdup("default"), algo, ulp)); + const UE_list_t *UE_list = &RC.mac[mod_id]->UE_info.list; + for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) + slicing_add_UE(si, UE_id); + + pp_impl_param_t sttc; + sttc.algorithm = STATIC_SLICING; + sttc.add_UE = slicing_add_UE; + sttc.remove_UE = slicing_remove_UE; + sttc.move_UE = slicing_move_UE; + sttc.addmod_slice = addmod_static_slice_ul; + sttc.remove_slice = remove_static_slice; + sttc.ul = static_ul; + // current DL algo becomes default scheduler + sttc.ul_algo = *algo; + sttc.destroy = static_destroy; + sttc.slices = si; + + return sttc; +} diff --git a/openair2/LAYER2/MAC/slicing/slicing.h b/openair2/LAYER2/MAC/slicing/slicing.h new file mode 100644 index 0000000000..1099b50ea0 --- /dev/null +++ b/openair2/LAYER2/MAC/slicing/slicing.h @@ -0,0 +1,74 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! + * \file slicing.h + * \brief General slice definition and helper parameters + * \author Robert Schmidt + * \date 2020 + * \email robert.schmidt@eurecom.fr + */ + +#ifndef __SLICING_H__ +#define __SLICING_H__ + +#include "openair2/LAYER2/MAC/mac.h" + +typedef struct slice_s { + /// Arbitrary ID + slice_id_t id; + /// Arbitrary label + char *label; + + union { + default_sched_dl_algo_t dl_algo; + default_sched_ul_algo_t ul_algo; + }; + + /// A specific algorithm's implementation parameters + void *algo_data; + /// Internal data that might be kept alongside a slice's params + void *int_data; + + // list of users in this slice + UE_list_t UEs; +} slice_t; + +typedef struct slice_info_s { + uint8_t num; + slice_t **s; + uint8_t UE_assoc_slice[MAX_MOBILES_PER_ENB]; +} slice_info_t; + +int slicing_get_UE_slice_idx(slice_info_t *si, int UE_id); + +#define STATIC_SLICING 10 +/* only four static slices for UL, DL resp. (not enough DCIs) */ +#define MAX_STATIC_SLICES 4 +typedef struct { + uint16_t posLow; + uint16_t posHigh; +} static_slice_param_t; +pp_impl_param_t static_dl_init(module_id_t mod_id, int CC_id); +pp_impl_param_t static_ul_init(module_id_t mod_id, int CC_id); + + +#endif /* __SLICING_H__ */ diff --git a/openair2/LAYER2/MAC/slicing/slicing_internal.h b/openair2/LAYER2/MAC/slicing/slicing_internal.h new file mode 100644 index 0000000000..744f8924d9 --- /dev/null +++ b/openair2/LAYER2/MAC/slicing/slicing_internal.h @@ -0,0 +1,46 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! + * \file slicing_internal.h + * \brief Internal slice helper functions + * \author Robert Schmidt + * \date 2020 + * \email robert.schmidt@eurecom.fr + */ + +#ifndef __SLICING_INTERNAL_H__ +#define __SLICING_INTERNAL_H__ + +#include "slicing.h" + +void slicing_add_UE(slice_info_t *si, int UE_id); + +void _remove_UE(slice_t **s, uint8_t *assoc, int UE_id); +void slicing_remove_UE(slice_info_t *si, int UE_id); + +void _move_UE(slice_t **s, uint8_t *assoc, int UE_id, int to); +void slicing_move_UE(slice_info_t *si, int UE_id, int idx); + +slice_t *_add_slice(uint8_t *n, slice_t **s); +slice_t *_remove_slice(uint8_t *n, slice_t **s, uint8_t *assoc, int idx); + +#endif /* __SLICING_INTERNAL_H__ */ From d926a9a9c818e01fff34e3b96e0611929325faca Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Thu, 18 Jun 2020 19:12:15 +0200 Subject: [PATCH 429/553] FlexRAN: New protobuf slice structure + Static Slice handling --- .../CONTROL_MODULES/MAC/flexran_agent_mac.c | 139 ++++++--- .../CONTROL_MODULES/MAC/flexran_agent_mac.h | 13 +- .../MAC/flexran_agent_mac_internal.c | 202 ++++++++++--- .../MAC/flexran_agent_mac_internal.h | 20 +- .../ENB_APP/MESSAGES/V2/config_common.proto | 25 ++ .../ENB_APP/MESSAGES/V2/config_messages.proto | 2 + openair2/ENB_APP/flexran_agent_common.c | 12 +- openair2/ENB_APP/flexran_agent_ran_api.c | 277 ++++++++++++++++-- openair2/ENB_APP/flexran_agent_ran_api.h | 45 ++- openair2/LAYER2/MAC/main.c | 2 + openair2/LAYER2/MAC/slicing/slicing.c | 21 +- 11 files changed, 614 insertions(+), 144 deletions(-) diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c index 4800fccea9..e5d1c94c95 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c @@ -1452,9 +1452,74 @@ void flexran_agent_fill_mac_cell_config(mid_t mod_id, uint8_t cc_id, conf->si_config->has_sfn = 1; } - /* get a pointer to the config which is maintained in the agent throughout - * its lifetime */ - conf->slice_config = flexran_agent_get_slice_config(mod_id); + conf->slice_config = malloc(sizeof(Protocol__FlexSliceConfig)); + if (conf->slice_config) { + protocol__flex_slice_config__init(conf->slice_config); + Protocol__FlexSliceConfig *sc = conf->slice_config; + + sc->dl = malloc(sizeof(Protocol__FlexSliceDlUlConfig)); + DevAssert(sc->dl); + protocol__flex_slice_dl_ul_config__init(sc->dl); + sc->dl->algorithm = flexran_get_dl_slice_algo(mod_id); + sc->dl->has_algorithm = 1; + sc->dl->n_slices = flexran_get_num_dl_slices(mod_id); + if (sc->dl->n_slices > 0) { + sc->dl->slices = calloc(sc->dl->n_slices, sizeof(Protocol__FlexSlice *)); + DevAssert(sc->dl->slices); + for (int i = 0; i < sc->dl->n_slices; ++i) { + sc->dl->slices[i] = malloc(sizeof(Protocol__FlexSlice)); + DevAssert(sc->dl->slices[i]); + protocol__flex_slice__init(sc->dl->slices[i]); + flexran_get_dl_slice(mod_id, i, sc->dl->slices[i], sc->dl->algorithm); + } + } else { + sc->dl->scheduler = flexran_get_dl_scheduler_name(mod_id); + } + + sc->ul = malloc(sizeof(Protocol__FlexSliceDlUlConfig)); + DevAssert(sc->ul); + protocol__flex_slice_dl_ul_config__init(sc->ul); + sc->ul->algorithm = flexran_get_ul_slice_algo(mod_id); + sc->ul->has_algorithm = 1; + sc->ul->n_slices = flexran_get_num_ul_slices(mod_id); + if (sc->ul->n_slices > 0) { + sc->ul->slices = calloc(sc->ul->n_slices, sizeof(Protocol__FlexSlice *)); + DevAssert(sc->ul->slices); + for (int i = 0; i < sc->ul->n_slices; ++i) { + sc->ul->slices[i] = malloc(sizeof(Protocol__FlexSlice)); + DevAssert(sc->ul->slices[i]); + protocol__flex_slice__init(sc->ul->slices[i]); + flexran_get_ul_slice(mod_id, i, sc->ul->slices[i], sc->ul->algorithm); + } + } else { + sc->ul->scheduler = flexran_get_ul_scheduler_name(mod_id); + } + } +} + +void flexran_agent_destroy_mac_slice_config(Protocol__FlexCellConfig *conf) { + Protocol__FlexSliceConfig *sc = conf->slice_config; + for (int i = 0; i < sc->dl->n_slices; ++i) { + free(sc->dl->slices[i]); + sc->dl->slices[i] = NULL; + /* scheduler names are not freed: we assume we read them directly from the + * underlying memory and do not dispose it */ + } + free(sc->dl->slices); + /* scheduler name is not freed */ + free(sc->dl); + sc->dl = NULL; + for (int i = 0; i < sc->ul->n_slices; ++i) { + free(sc->ul->slices[i]); + sc->ul->slices[i] = NULL; + /* scheduler names are not freed */ + } + free(sc->ul->slices); + /* scheduler name is not freed */ + free(sc->ul); + sc->ul = NULL; + free(conf->slice_config); + conf->slice_config = NULL; } void flexran_agent_fill_mac_ue_config(mid_t mod_id, mid_t ue_id, @@ -1568,46 +1633,46 @@ int flexran_agent_unregister_mac_xface(mid_t mod_id) return 0; } - -void flexran_create_config_structures(mid_t mod_id) -{ - int i; - int n_dl = flexran_get_num_dl_slices(mod_id); - int m_ul = flexran_get_num_ul_slices(mod_id); - slice_config[mod_id] = flexran_agent_create_slice_config(n_dl, m_ul); - sc_update[mod_id] = flexran_agent_create_slice_config(n_dl, m_ul); - if (!slice_config[mod_id] || !sc_update[mod_id]) return; - - //flexran_agent_read_slice_config(mod_id, slice_config[mod_id]); - //flexran_agent_read_slice_config(mod_id, sc_update[mod_id]); - for (i = 0; i < n_dl; i++) { - //flexran_agent_read_slice_dl_config(mod_id, i, slice_config[mod_id]->dl[i]); - //flexran_agent_read_slice_dl_config(mod_id, i, sc_update[mod_id]->dl[i]); +void helper_destroy_mac_slice_config(Protocol__FlexSliceConfig *slice_config) { + if (slice_config->dl) { + if (slice_config->dl->scheduler) + free(slice_config->dl->scheduler); + for (int i = 0; i < slice_config->dl->n_slices; i++) + if (slice_config->dl->slices[i]->scheduler) + free(slice_config->dl->slices[i]->scheduler); } - for (i = 0; i < m_ul; i++) { - //flexran_agent_read_slice_ul_config(mod_id, i, slice_config[mod_id]->ul[i]); - //flexran_agent_read_slice_ul_config(mod_id, i, sc_update[mod_id]->ul[i]); + if (slice_config->ul) { + if (slice_config->ul->scheduler) + free(slice_config->ul->scheduler); + for (int i = 0; i < slice_config->ul->n_slices; i++) + if (slice_config->ul->slices[i]->scheduler) + free(slice_config->ul->slices[i]->scheduler); } + + Protocol__FlexCellConfig helper; + helper.slice_config = slice_config; + flexran_agent_destroy_mac_slice_config(&helper); } -void flexran_check_and_remove_slices(mid_t mod_id) -{ +void prepare_update_slice_config(mid_t mod_id, Protocol__FlexSliceConfig **slice_config) { + if (!*slice_config) return; + Protocol__FlexSliceConfig *sc = *slice_config; + *slice_config = NULL; + + /* TODO handle using lock-free queue */ + apply_update_dl_slice_config(mod_id, sc->dl); + apply_update_ul_slice_config(mod_id, sc->ul); + + helper_destroy_mac_slice_config(*slice_config); } -void flexran_agent_slice_update(mid_t mod_id) -{ +void prepare_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig **ue_config) { + /* TODO handle using lock-free queue */ + apply_ue_slice_assoc_update(mod_id, *ue_config); + + free(*ue_config); + *ue_config = NULL; } -Protocol__FlexSliceConfig *flexran_agent_get_slice_config(mid_t mod_id) -{ - if (!slice_config[mod_id]) return NULL; - Protocol__FlexSliceConfig *config = NULL; - - pthread_mutex_lock(&sc_update_mtx); - if (!config) { - pthread_mutex_unlock(&sc_update_mtx); - return NULL; - } - pthread_mutex_unlock(&sc_update_mtx); - return config; +void flexran_agent_slice_update(mid_t mod_id) { } diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.h b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.h index 2f9f99c740..5a8d4f31aa 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.h +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.h @@ -115,7 +115,16 @@ int flexran_agent_unregister_mac_xface(mid_t mod_id); /* Inform controller about possibility to update slice configuration */ void flexran_agent_slice_update(mid_t mod_id); -/* return a pointer to the current config */ -Protocol__FlexSliceConfig *flexran_agent_get_slice_config(mid_t mod_id); +/* marks slice_config so that it can be applied later. Takes ownership of the + * FlexSliceConfig message */ +void prepare_update_slice_config(mid_t mod_id, Protocol__FlexSliceConfig **slice); + +/* inserts a new ue_config into the structure keeping ue to slice association + * updates and marks so it can be applied. Takes ownership of the FlexUeConfig message */ +void prepare_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig **ue_config); + +/* free slice_config part of flexCellConfig, filled in + * flexran_agent_fill_mac_cell_config() */ +void flexran_agent_destroy_mac_slice_config(Protocol__FlexCellConfig *conf); #endif diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c index 4c80c561ee..93de0b11ec 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c @@ -1025,60 +1025,166 @@ int load_dl_scheduler_function(mid_t mod_id, const char *function_name) { } -Protocol__FlexSliceConfig *flexran_agent_create_slice_config(int n_dl, int m_ul) -{ - Protocol__FlexSliceConfig *fsc = malloc(sizeof(Protocol__FlexSliceConfig)); - if (!fsc) return NULL; - protocol__flex_slice_config__init(fsc); - - /* TODO */ - return fsc; -} - -void prepare_update_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *sup) -{ -} - - -void prepare_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig *ue_config) -{ - if (n_ue_slice_assoc_updates == 10) { - LOG_E(FLEXRAN_AGENT, - "[%d] can not handle flex_ue_config message, buffer is full; try again later\n", - mod_id); - return; +void update_or_remove_dl(mid_t mod_id, Protocol__FlexSlice *s) { + if (s->params_case == PROTOCOL__FLEX_SLICE__PARAMS__NOT_SET + && !s->label && !s->scheduler) { + LOG_I(FLEXRAN_AGENT, "remove DL slice ID %d\n", s->id); + const int rc = flexran_remove_dl_slice(mod_id, s); + if (!rc) + LOG_W(FLEXRAN_AGENT, "error while removing slice ID %d\n", s->id); + } else { + LOG_I(FLEXRAN_AGENT, "updating DL slice ID %d\n", s->id); + const int rc = flexran_create_dl_slice(mod_id, s); + if (rc < 0) + LOG_W(FLEXRAN_AGENT, + "error while update slice ID %d: flexran_create_dl_slice() -> %d\n", + s->id, rc); } +} + +void update_or_remove_ul(mid_t mod_id, Protocol__FlexSlice *s) { + if (s->params_case == PROTOCOL__FLEX_SLICE__PARAMS__NOT_SET + && !s->label && !s->scheduler) { + LOG_I(FLEXRAN_AGENT, "remove UL slice ID %d\n", s->id); + const int rc = flexran_remove_ul_slice(mod_id, s); + if (!rc) + LOG_W(FLEXRAN_AGENT, "error while removing slice ID %d\n", s->id); + } else { + LOG_I(FLEXRAN_AGENT, "updating UL slice ID %d\n", s->id); + const int rc = flexran_create_ul_slice(mod_id, s); + if (rc < 0) + LOG_W(FLEXRAN_AGENT, + "error while updating slice ID %d: flexran_create_ul_slice() -> %d)\n", + s->id, rc); + } +} + +void apply_update_dl_slice_config(mid_t mod_id, Protocol__FlexSliceDlUlConfig *dl) { + if (!dl) + return; + + Protocol__FlexSliceAlgorithm dl_algo = flexran_get_dl_slice_algo(mod_id); + if (dl->has_algorithm && dl_algo != dl->algorithm) { + LOG_I(FLEXRAN_AGENT, "loading new DL slice algorithm %d\n", dl->algorithm); + dl_algo = dl->algorithm; + flexran_set_dl_slice_algo(mod_id, dl_algo); + } + + /* first update existing slices, then create new. Thus, we go through the + * list twice. First round, if a slice exists, handle and mark as such. Then, + * apply all others in the second round */ + if (dl->n_slices > 0) { + if (dl_algo == PROTOCOL__FLEX_SLICE_ALGORITHM__None) { + LOG_E(FLEXRAN_AGENT, "cannot update slices: no algorithm loaded\n"); + return; + } + int handled_dl[dl->n_slices]; + for (int i = 0; i < dl->n_slices; ++i) { + if (flexran_find_dl_slice(mod_id, dl->slices[i]->id) < 0) { + handled_dl[i] = 0; + continue; + } + update_or_remove_dl(mod_id, dl->slices[i]); + handled_dl[i] = 1; + } + for (int i = 0; i < dl->n_slices; ++i) { + if (handled_dl[i]) + continue; + update_or_remove_dl(mod_id, dl->slices[i]); + } + } + + if (dl->scheduler) { + if (dl_algo != PROTOCOL__FLEX_SLICE_ALGORITHM__None) { + LOG_E(FLEXRAN_AGENT, "cannot update scheduling algorithm: slice algorithm loaded\n"); + return; + } + LOG_I(FLEXRAN_AGENT, "loading DL new scheduling algorithm '%s'\n", dl->scheduler); + const int rc = flexran_set_dl_scheduler(mod_id, dl->scheduler); + if (rc < 0) { + LOG_E(FLEXRAN_AGENT, + "error while updating scheduling algorithm: " + "flexran_update_dl_sched_algo() -> %d)\n", + rc); + return; + } + } +} + +void apply_update_ul_slice_config(mid_t mod_id, Protocol__FlexSliceDlUlConfig *ul) { + if (!ul) + return; + + Protocol__FlexSliceAlgorithm ul_algo = flexran_get_ul_slice_algo(mod_id); + if (ul->has_algorithm && ul_algo != ul->algorithm) { + LOG_I(FLEXRAN_AGENT, "loading new UL slice algorithm %d\n", ul->algorithm); + ul_algo = ul->algorithm; + flexran_set_ul_slice_algo(mod_id, ul_algo); + } + if (ul->n_slices > 0) { + if (ul_algo == PROTOCOL__FLEX_SLICE_ALGORITHM__None) { + LOG_E(FLEXRAN_AGENT, "cannot update slices: no algorithm loaded\n"); + return; + } + int handled_ul[ul->n_slices]; + for (int i = 0; i < ul->n_slices; ++i) { + if (flexran_find_ul_slice(mod_id, ul->slices[i]->id) < 0) { + handled_ul[i] = 0; + continue; + } + update_or_remove_ul(mod_id, ul->slices[i]); + handled_ul[i] = 1; + } + for (int i = 0; i < ul->n_slices; ++i) { + if (handled_ul[i]) + continue; + update_or_remove_ul(mod_id, ul->slices[i]); + } + } + + if (ul->scheduler) { + if (ul_algo != PROTOCOL__FLEX_SLICE_ALGORITHM__None) { + LOG_E(FLEXRAN_AGENT, "cannot update scheduling algorithm: slice algorithm loaded\n"); + return; + } + LOG_I(FLEXRAN_AGENT, "loading new UL scheduling algorithm '%s'\n", ul->scheduler); + const int rc = flexran_set_ul_scheduler(mod_id, ul->scheduler); + if (rc < 0) { + LOG_E(FLEXRAN_AGENT, + "error while updating scheduling algorithm: " + "flexran_update_dl_sched_algo() -> %d)\n", + rc); + return; + } + } +} + +int apply_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig *ue_config) +{ if (!ue_config->has_rnti) { LOG_E(FLEXRAN_AGENT, "[%d] cannot update UE to slice association, no RNTI in flex_ue_config message\n", mod_id); - return; + return 0; } - if (ue_config->has_dl_slice_id) - LOG_I(FLEXRAN_AGENT, "[%d] associating UE RNTI %#x to DL slice ID %d\n", - mod_id, ue_config->rnti, ue_config->dl_slice_id); - if (ue_config->has_ul_slice_id) - LOG_I(FLEXRAN_AGENT, "[%d] associating UE RNTI %#x to UL slice ID %d\n", - mod_id, ue_config->rnti, ue_config->ul_slice_id); - ue_slice_assoc_update[n_ue_slice_assoc_updates++] = ue_config; - perform_slice_config_update_count = 2; -} - -int apply_ue_slice_assoc_update(mid_t mod_id) -{ - int i; - int changes = 0; - for (i = 0; i < n_ue_slice_assoc_updates; i++) { - int ue_id = find_UE_id(mod_id, ue_slice_assoc_update[i]->rnti); - if (ue_id < 0 || ue_id > MAX_MOBILES_PER_ENB){ - LOG_E(FLEXRAN_AGENT,"UE_id %d is wrong!!\n",ue_id); - continue; - } - if (ue_slice_assoc_update[i]->has_dl_slice_id) { - } - if (ue_slice_assoc_update[i]->has_ul_slice_id) { + int UE_id = flexran_get_mac_ue_id_rnti(mod_id, ue_config->rnti); + if (ue_config->has_dl_slice_id) { + if (flexran_get_dl_slice_algo(mod_id) == PROTOCOL__FLEX_SLICE_ALGORITHM__None) { + LOG_E(FLEXRAN_AGENT, "no DL slice algorithm loaded\n"); + } else { + LOG_I(FLEXRAN_AGENT, "[%d] associating UE RNTI %04x - %d/UE %d to DL slice ID %d\n", + mod_id, ue_config->rnti, ue_config->rnti, UE_id, ue_config->dl_slice_id); + flexran_set_ue_dl_slice_id(mod_id, UE_id, ue_config->dl_slice_id); } } - n_ue_slice_assoc_updates = 0; - return changes; + if (ue_config->has_ul_slice_id) { + if (flexran_get_ul_slice_algo(mod_id) == PROTOCOL__FLEX_SLICE_ALGORITHM__None) { + LOG_E(FLEXRAN_AGENT, "no UL slice algorithm loaded\n"); + } else { + LOG_I(FLEXRAN_AGENT, "[%d] associating UE RNTI %04x - %d/UE %d to UL slice ID %d\n", + mod_id, ue_config->rnti, ue_config->rnti, UE_id, ue_config->ul_slice_id); + flexran_set_ue_ul_slice_id(mod_id, UE_id, ue_config->ul_slice_id); + } + } + return 0; } diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.h b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.h index ef2a7e40a9..9db5d61a11 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.h +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.h @@ -103,23 +103,11 @@ int load_dl_scheduler_function(mid_t mod_id, const char *function_name); /*** Functions for handling a slice config ***/ -/* allocate memory for a Protocol__FlexSliceConfig structure with n_dl DL slice - * configs and m_ul UL slice configs */ -Protocol__FlexSliceConfig *flexran_agent_create_slice_config(int n_dl, int m_ul); - -/* read the general slice parameters via RAN into the given - * Protocol__FlexSliceConfig struct */ -void flexran_agent_read_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *s); - -/* reads content of slice over the sc_update structure, so that it can be - * applied later by performing a diff between slice_config and sc_update */ -void prepare_update_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *slice); - -/* inserts a new ue_config into the structure keeping ue to slice association - * updates and marks so it can be applied */ -void prepare_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig *ue_config); +/* Prepare the application of a slicing config */ +void apply_update_dl_slice_config(mid_t mod_id, Protocol__FlexSliceDlUlConfig *slice); +void apply_update_ul_slice_config(mid_t mod_id, Protocol__FlexSliceDlUlConfig *slice); /* apply a new association between a UE and a slice (both DL and UL) */ -int apply_ue_slice_assoc_update(mid_t mod_id); +int apply_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig *ue_config); #endif /*FLEXRAN_AGENT_MAC_INTERNAL_H_*/ diff --git a/openair2/ENB_APP/MESSAGES/V2/config_common.proto b/openair2/ENB_APP/MESSAGES/V2/config_common.proto index e5d01ebdc0..2f2267b628 100644 --- a/openair2/ENB_APP/MESSAGES/V2/config_common.proto +++ b/openair2/ENB_APP/MESSAGES/V2/config_common.proto @@ -61,6 +61,31 @@ enum flex_qam { // // Slice config related structures and enums // +enum flex_slice_algorithm { + None = 0; + Static = 1; + NVS = 2; +} + +message flex_slice_static { + optional uint32 posLow = 1; + optional uint32 posHigh = 2; +} + +message flex_slice { + optional uint32 id = 1; + optional string label = 2; + optional string scheduler = 3; + oneof params { + flex_slice_static static = 10; + } +} + +message flex_slice_dl_ul_config { + optional flex_slice_algorithm algorithm = 1; + repeated flex_slice slices = 2; + optional string scheduler = 3; // if no slicing +} // // UE config related structures and enums diff --git a/openair2/ENB_APP/MESSAGES/V2/config_messages.proto b/openair2/ENB_APP/MESSAGES/V2/config_messages.proto index 1a66a4f20f..1a69deec71 100644 --- a/openair2/ENB_APP/MESSAGES/V2/config_messages.proto +++ b/openair2/ENB_APP/MESSAGES/V2/config_messages.proto @@ -49,6 +49,8 @@ message flex_cell_config { } message flex_slice_config { + optional flex_slice_dl_ul_config dl = 6; + optional flex_slice_dl_ul_config ul = 7; } message flex_ue_config { diff --git a/openair2/ENB_APP/flexran_agent_common.c b/openair2/ENB_APP/flexran_agent_common.c index 3dd9f5b957..7569ca1ac1 100644 --- a/openair2/ENB_APP/flexran_agent_common.c +++ b/openair2/ENB_APP/flexran_agent_common.c @@ -306,6 +306,7 @@ int flexran_agent_destroy_enb_config_reply(Protocol__FlexranMessage *msg) { if (reply->cell_config[i]->mbsfn_subframe_config_sfalloc) free(reply->cell_config[i]->mbsfn_subframe_config_sfalloc); + /* si_config is shared between MAC and RRC, free here */ if (reply->cell_config[i]->si_config) { for(int j = 0; j < reply->cell_config[i]->si_config->n_si_message; j++) { free(reply->cell_config[i]->si_config->si_message[j]); @@ -316,8 +317,7 @@ int flexran_agent_destroy_enb_config_reply(Protocol__FlexranMessage *msg) { } if (reply->cell_config[i]->slice_config) { - /* TODO */ - free(reply->cell_config[i]->slice_config); + flexran_agent_destroy_mac_slice_config(reply->cell_config[i]); } free(reply->cell_config[i]); @@ -880,7 +880,7 @@ int flexran_agent_handle_enb_config_reply(mid_t mod_id, const void *params, Prot if (enb_config->n_cell_config > 0) { if (flexran_agent_get_mac_xface(mod_id) && enb_config->cell_config[0]->slice_config) { - prepare_update_slice_config(mod_id, enb_config->cell_config[0]->slice_config); + prepare_update_slice_config(mod_id, &enb_config->cell_config[0]->slice_config); } if (enb_config->cell_config[0]->has_eutra_band && enb_config->cell_config[0]->has_dl_freq @@ -921,7 +921,11 @@ int flexran_agent_handle_ue_config_reply(mid_t mod_id, const void *params, Proto Protocol__FlexUeConfigReply *ue_config_reply = input->ue_config_reply_msg; for (i = 0; flexran_agent_get_mac_xface(mod_id) && i < ue_config_reply->n_ue_config; i++) - prepare_ue_slice_assoc_update(mod_id, ue_config_reply->ue_config[i]); + prepare_ue_slice_assoc_update(mod_id, &ue_config_reply->ue_config[i]); + /* prepare_ue_slice_assoc_update takes ownership of the individual + * FlexUeConfig messages. Therefore, mark zero messages to not accidentally + * free them twice */ + ue_config_reply->n_ue_config = 0; *msg = NULL; return 0; diff --git a/openair2/ENB_APP/flexran_agent_ran_api.c b/openair2/ENB_APP/flexran_agent_ran_api.c index cd8b0b8f67..79c992a4d7 100644 --- a/openair2/ENB_APP/flexran_agent_ran_api.c +++ b/openair2/ENB_APP/flexran_agent_ran_api.c @@ -30,6 +30,7 @@ #include "flexran_agent_ran_api.h" #include "s1ap_eNB_ue_context.h" #include "s1ap_eNB_management_procedures.h" +#include "openair2/LAYER2/MAC/slicing/slicing.h" static inline int phy_is_present(mid_t mod_id, uint8_t cc_id) { return RC.eNB && RC.eNB[mod_id] && RC.eNB[mod_id][cc_id]; @@ -3013,66 +3014,294 @@ uint32_t flexran_get_rrc_enb_ue_s1ap_id(mid_t mod_id, rnti_t rnti) } /**************************** SLICING ****************************/ +Protocol__FlexSliceAlgorithm flexran_get_dl_slice_algo(mid_t mod_id) { + if (!mac_is_present(mod_id)) return PROTOCOL__FLEX_SLICE_ALGORITHM__None; + + switch (RC.mac[mod_id]->pre_processor_dl.algorithm) { + case STATIC_SLICING: + return PROTOCOL__FLEX_SLICE_ALGORITHM__Static; + default: + return PROTOCOL__FLEX_SLICE_ALGORITHM__None; + } +} + +int flexran_set_dl_slice_algo(mid_t mod_id, Protocol__FlexSliceAlgorithm algo) { + if (!mac_is_present(mod_id)) return 0; + eNB_MAC_INST *mac = RC.mac[mod_id]; + const int cc_id = 0; + + pp_impl_param_t dl = mac->pre_processor_dl; + switch (algo) { + case PROTOCOL__FLEX_SLICE_ALGORITHM__Static: + mac->pre_processor_dl = static_dl_init(mod_id, cc_id); + break; + default: + mac->pre_processor_dl.algorithm = 0; + mac->pre_processor_dl.dl = dlsch_scheduler_pre_processor; + mac->pre_processor_dl.dl_algo.data = mac->pre_processor_dl.dl_algo.setup(); + mac->pre_processor_dl.slices = NULL; + break; + } + if (dl.slices) + dl.destroy(&dl.slices); + if (dl.dl_algo.data) + dl.dl_algo.unset(&dl.dl_algo.data); + return 1; +} + +Protocol__FlexSliceAlgorithm flexran_get_ul_slice_algo(mid_t mod_id) { + if (!mac_is_present(mod_id)) return PROTOCOL__FLEX_SLICE_ALGORITHM__None; + + switch (RC.mac[mod_id]->pre_processor_ul.algorithm) { + case STATIC_SLICING: + return PROTOCOL__FLEX_SLICE_ALGORITHM__Static; + default: + return PROTOCOL__FLEX_SLICE_ALGORITHM__None; + } +} + +int flexran_set_ul_slice_algo(mid_t mod_id, Protocol__FlexSliceAlgorithm algo) { + if (!mac_is_present(mod_id)) return 0; + eNB_MAC_INST *mac = RC.mac[mod_id]; + const int cc_id = 0; + + pp_impl_param_t ul = mac->pre_processor_ul; + switch (algo) { + case PROTOCOL__FLEX_SLICE_ALGORITHM__Static: + mac->pre_processor_ul = static_ul_init(mod_id, cc_id); + break; + default: + mac->pre_processor_ul.algorithm = 0; + mac->pre_processor_ul.ul = ulsch_scheduler_pre_processor; + mac->pre_processor_ul.ul_algo.data = mac->pre_processor_ul.ul_algo.setup(); + mac->pre_processor_ul.slices = NULL; + break; + } + if (ul.slices) + ul.destroy(&ul.slices); + if (ul.ul_algo.data) + ul.ul_algo.unset(&ul.ul_algo.data); + return 1; +} + int flexran_get_ue_dl_slice_id(mid_t mod_id, mid_t ue_id) { if (!mac_is_present(mod_id)) return -1; - return 0; + slice_info_t *slices = RC.mac[mod_id]->pre_processor_dl.slices; + if (!slices) return -1; + const int idx = slices->UE_assoc_slice[ue_id]; + return slices->s[idx]->id; +} + +void flexran_set_ue_dl_slice_id(mid_t mod_id, mid_t ue_id, slice_id_t slice_id) { + if (!mac_is_present(mod_id)) return; + int idx = flexran_find_dl_slice(mod_id, slice_id); + if (idx < 0) return; + pp_impl_param_t *dl = &RC.mac[mod_id]->pre_processor_dl; + dl->move_UE(dl->slices, ue_id, idx); } int flexran_get_ue_ul_slice_id(mid_t mod_id, mid_t ue_id) { if (!mac_is_present(mod_id)) return -1; - return 0; + slice_info_t *slices = RC.mac[mod_id]->pre_processor_ul.slices; + if (!slices) return -1; + const int idx = slices->UE_assoc_slice[ue_id]; + return slices->s[idx]->id; } -/* TODO */ -int flexran_create_dl_slice(mid_t mod_id, slice_id_t slice_id) { - if (!mac_is_present(mod_id)) return -1; - return -1; +void flexran_set_ue_ul_slice_id(mid_t mod_id, mid_t ue_id, slice_id_t slice_id) { + if (!mac_is_present(mod_id)) return; + int idx = flexran_find_ul_slice(mod_id, slice_id); + if (idx < 0) return; + pp_impl_param_t *ul = &RC.mac[mod_id]->pre_processor_ul; + ul->move_UE(ul->slices, ue_id, idx); } -/* TODO */ -int flexran_remove_dl_slice(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; +int flexran_create_dl_slice(mid_t mod_id, const Protocol__FlexSlice *s) { + if (!mac_is_present(mod_id)) return 0; + void *params = NULL; + switch (s->params_case) { + case PROTOCOL__FLEX_SLICE__PARAMS_STATIC: + params = malloc(sizeof(static_slice_param_t)); + if (!params) return 0; + ((static_slice_param_t *)params)->posLow = s->static_->poslow; + ((static_slice_param_t *)params)->posHigh = s->static_->poshigh; + break; + default: + break; + } + pp_impl_param_t *dl = &RC.mac[mod_id]->pre_processor_dl; + char *l = s->label ? strdup(s->label) : NULL; + void *algo = &dl->dl_algo; // default scheduler + if (s->scheduler) { + algo = dlsym(NULL, s->scheduler); + if (!algo) { + free(params); + LOG_E(FLEXRAN_AGENT, "cannot locate scheduler '%s'\n", s->scheduler); + return -15; + } + } + return dl->addmod_slice(dl->slices, s->id, l, algo, params); +} + +int flexran_remove_dl_slice(mid_t mod_id, const Protocol__FlexSlice *s) { + if (!mac_is_present(mod_id)) return 0; + const int idx = flexran_find_dl_slice(mod_id, s->id); + if (idx < 0) return 0; + pp_impl_param_t *dl = &RC.mac[mod_id]->pre_processor_dl; + return dl->remove_slice(dl->slices, idx); } int flexran_find_dl_slice(mid_t mod_id, slice_id_t slice_id) { if (!mac_is_present(mod_id)) return -1; + slice_info_t *si = RC.mac[mod_id]->pre_processor_dl.slices; + for (int i = 0; i < si->num; ++i) + if (si->s[i]->id == slice_id) + return i; return -1; } -//int flexran_get_dl_slice(mid_t mod_id, int slice_idx, Protocol__FlexSlice *s) { -//} +void flexran_get_dl_slice(mid_t mod_id, + int slice_idx, + Protocol__FlexSlice *slice, + Protocol__FlexSliceAlgorithm algo) { + if (!mac_is_present(mod_id)) return; + slice_t *s_ = RC.mac[mod_id]->pre_processor_dl.slices->s[slice_idx]; + slice->has_id = 1; + slice->id = s_->id; + slice->label = s_->label; + slice->scheduler = s_->dl_algo.name; + slice->params_case = PROTOCOL__FLEX_SLICE__PARAMS__NOT_SET; + switch (algo) { + case PROTOCOL__FLEX_SLICE_ALGORITHM__Static: + slice->static_ = malloc(sizeof(Protocol__FlexSliceStatic)); + if (!slice->static_) return; + protocol__flex_slice_static__init(slice->static_); + slice->static_->has_poslow = 1; + slice->static_->poslow = ((static_slice_param_t *)s_->algo_data)->posLow; + slice->static_->has_poshigh = 1; + slice->static_->poshigh = ((static_slice_param_t *)s_->algo_data)->posHigh; + slice->params_case = PROTOCOL__FLEX_SLICE__PARAMS_STATIC; + break; + default: + break; + } +} int flexran_get_num_dl_slices(mid_t mod_id) { - if (!mac_is_present(mod_id)) return -1; - return 0; + if (!mac_is_present(mod_id)) return 0; + if (!RC.mac[mod_id]->pre_processor_dl.slices) return 0; + return RC.mac[mod_id]->pre_processor_dl.slices->num; } -/* TODO */ -void flexran_create_ul_slice(mid_t mod_id, slice_id_t slice_id) { - if (!mac_is_present(mod_id)) return; - return; +int flexran_create_ul_slice(mid_t mod_id, const Protocol__FlexSlice *s) { + if (!mac_is_present(mod_id)) return -1; + void *params = NULL; + switch (s->params_case) { + case PROTOCOL__FLEX_SLICE__PARAMS_STATIC: + params = malloc(sizeof(static_slice_param_t)); + if (!params) return 0; + ((static_slice_param_t *)params)->posLow = s->static_->poslow; + ((static_slice_param_t *)params)->posHigh = s->static_->poshigh; + break; + default: + break; + } + pp_impl_param_t *ul = &RC.mac[mod_id]->pre_processor_ul; + char *l = s->label ? strdup(s->label) : NULL; + void *algo = &ul->ul_algo; // default scheduler + if (s->scheduler) { + algo = dlsym(NULL, s->scheduler); + if (!algo) { + free(params); + LOG_E(FLEXRAN_AGENT, "cannot locate scheduler '%s'\n", s->scheduler); + return -15; + } + } + return ul->addmod_slice(ul->slices, s->id, l, algo, params); } -/* TODO */ -int flexran_remove_ul_slice(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; +int flexran_remove_ul_slice(mid_t mod_id, const Protocol__FlexSlice *s) { + if (!mac_is_present(mod_id)) return 0; + const int idx = flexran_find_ul_slice(mod_id, s->id); + if (idx < 0) return 0; + pp_impl_param_t *ul = &RC.mac[mod_id]->pre_processor_ul; + return ul->remove_slice(ul->slices, idx); } int flexran_find_ul_slice(mid_t mod_id, slice_id_t slice_id) { if (!mac_is_present(mod_id)) return -1; + slice_info_t *si = RC.mac[mod_id]->pre_processor_ul.slices; + for (int i = 0; i < si->num; ++i) + if (si->s[i]->id == slice_id) + return i; return -1; } -//int flexran_get_ul_slice(mid_t mod_id, int slice_idx, Protocol__FlexSlice *s) { -//} +void flexran_get_ul_slice(mid_t mod_id, + int slice_idx, + Protocol__FlexSlice *slice, + Protocol__FlexSliceAlgorithm algo) { + if (!mac_is_present(mod_id)) return; + slice_t *s_ = RC.mac[mod_id]->pre_processor_ul.slices->s[slice_idx]; + slice->has_id = 1; + slice->id = s_->id; + slice->label = s_->label; + slice->scheduler = s_->ul_algo.name; + slice->params_case = PROTOCOL__FLEX_SLICE__PARAMS__NOT_SET; + switch (algo) { + case PROTOCOL__FLEX_SLICE_ALGORITHM__Static: + slice->static_ = malloc(sizeof(Protocol__FlexSliceStatic)); + if (!slice->static_) return; + protocol__flex_slice_static__init(slice->static_); + slice->static_->has_poslow = 1; + slice->static_->poslow = ((static_slice_param_t *)s_->algo_data)->posLow; + slice->static_->has_poshigh = 1; + slice->static_->poshigh = ((static_slice_param_t *)s_->algo_data)->posHigh; + slice->params_case = PROTOCOL__FLEX_SLICE__PARAMS_STATIC; + break; + default: + break; + } + +} int flexran_get_num_ul_slices(mid_t mod_id) { + if (!mac_is_present(mod_id)) return 0; + if (!RC.mac[mod_id]->pre_processor_ul.slices) return 0; + return RC.mac[mod_id]->pre_processor_ul.slices->num; +} + +char *flexran_get_dl_scheduler_name(mid_t mod_id) { + if (!mac_is_present(mod_id)) return NULL; + return RC.mac[mod_id]->pre_processor_dl.dl_algo.name; +} + +int flexran_set_dl_scheduler(mid_t mod_id, char *sched) { if (!mac_is_present(mod_id)) return -1; + void *d = dlsym(NULL, sched); + if (!d) return -2; + pp_impl_param_t *dl_pp = &RC.mac[mod_id]->pre_processor_dl; + dl_pp->dl_algo.unset(&dl_pp->dl_algo.data); + dl_pp->dl_algo = *(default_sched_dl_algo_t *) d; + dl_pp->dl_algo.data = dl_pp->dl_algo.setup(); return 0; } +char *flexran_get_ul_scheduler_name(mid_t mod_id) { + if (!mac_is_present(mod_id)) return NULL; + return RC.mac[mod_id]->pre_processor_ul.ul_algo.name; +} + +int flexran_set_ul_scheduler(mid_t mod_id, char *sched) { + if (!mac_is_present(mod_id)) return -1; + void *d = dlsym(NULL, sched); + if (!d) return -2; + pp_impl_param_t *ul_pp = &RC.mac[mod_id]->pre_processor_ul; + ul_pp->ul_algo.unset(&ul_pp->ul_algo.data); + ul_pp->ul_algo = *(default_sched_ul_algo_t *) d; + ul_pp->ul_algo.data = ul_pp->ul_algo.setup(); + return 0; +} /************************** S1AP **************************/ int flexran_get_s1ap_mme_pending(mid_t mod_id){ diff --git a/openair2/ENB_APP/flexran_agent_ran_api.h b/openair2/ENB_APP/flexran_agent_ran_api.h index c29ba53c11..2d8a86f7d0 100644 --- a/openair2/ENB_APP/flexran_agent_ran_api.h +++ b/openair2/ENB_APP/flexran_agent_ran_api.h @@ -656,41 +656,66 @@ int flexran_agent_rrc_gtp_get_teid_sgw(mid_t mod_id, rnti_t rnti, int index); uint32_t flexran_get_rrc_enb_ue_s1ap_id(mid_t mod_id, rnti_t rnti); /************************** Slice configuration **************************/ +/* Get the currently active DL slicing algorithm */ +Protocol__FlexSliceAlgorithm flexran_get_dl_slice_algo(mid_t mod_id); +/* Set the active DL slicing algorithm */ +int flexran_set_dl_slice_algo(mid_t mod_id, Protocol__FlexSliceAlgorithm algo); + +/* Get the currently active UL slicing algorithm */ +Protocol__FlexSliceAlgorithm flexran_get_ul_slice_algo(mid_t mod_id); +/* Set the active UL slicing algorithm */ +int flexran_set_ul_slice_algo(mid_t mod_id, Protocol__FlexSliceAlgorithm algo); /* Get the DL slice ID for a UE */ int flexran_get_ue_dl_slice_id(mid_t mod_id, mid_t ue_id); -/* Set the DL slice index(!) for a UE */ -//void flexran_set_ue_dl_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx); +/* Set the DL slice for a UE */ +void flexran_set_ue_dl_slice_id(mid_t mod_id, mid_t ue_id, slice_id_t slice_id); /* Get the UL slice ID for a UE */ int flexran_get_ue_ul_slice_id(mid_t mod_id, mid_t ue_id); -/* Set the UL slice index(!) for a UE */ -//void flexran_set_ue_ul_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx); +/* Set the UL slice for a UE */ +void flexran_set_ue_ul_slice_id(mid_t mod_id, mid_t ue_id, slice_id_t slice_id); /* Create slice in DL, returns the new slice index */ -//int flexran_create_dl_slice(mid_t mod_id, slice_id_t slice_id); +int flexran_create_dl_slice(mid_t mod_id, const Protocol__FlexSlice *s); /* Remove slice in DL, returns new number of slices or -1 on error */ -//int flexran_remove_dl_slice(mid_t mod_id, int slice_idx); +int flexran_remove_dl_slice(mid_t mod_id, const Protocol__FlexSlice *s); /* Finds slice in DL with given slice_id and returns slice index */ int flexran_find_dl_slice(mid_t mod_id, slice_id_t slice_id); /* Return the parameters of slice at index slice_idx */ -//void flexran_get_dl_slice(mid_t mod_id, int slice_idx, Protocol__FlexSlice *s); +void flexran_get_dl_slice(mid_t mod_id, + int slice_idx, + Protocol__FlexSlice *slice, + Protocol__FlexSliceAlgorithm algo); /* Get the number of slices in DL */ int flexran_get_num_dl_slices(mid_t mod_id); /* Create slice in UL, returns the new slice index */ -//int flexran_create_ul_slice(mid_t mod_id, slice_id_t slice_id); +int flexran_create_ul_slice(mid_t mod_id, const Protocol__FlexSlice *s); /* Remove slice in UL */ -//int flexran_remove_ul_slice(mid_t mod_id, int slice_idx); +int flexran_remove_ul_slice(mid_t mod_id, const Protocol__FlexSlice *s); /* Finds slice in DL with given slice_id and returns slice index */ int flexran_find_ul_slice(mid_t mod_id, slice_id_t slice_id); /* Return the parameters of slice at index slice_idx */ -//void flexran_get_ul_slice(mid_t mod_id, int slice_idx, Protocol__FlexSlice *s); +void flexran_get_ul_slice(mid_t mod_id, + int slice_idx, + Protocol__FlexSlice *slice, + Protocol__FlexSliceAlgorithm algo); /* Get the number of slices in UL */ int flexran_get_num_ul_slices(mid_t mod_id); +/* Get the name of/Set the DL scheduling algorithm. If slicing is active, this + * corresponds to the default algorithm for slices, otherwise the currently + * used one. */ +char *flexran_get_dl_scheduler_name(mid_t mod_id); +int flexran_set_dl_scheduler(mid_t mod_id, char *sched); + +/* Get the name of/Set the UL scheduler algorithm. Same applies as for the DL + * case */ +char *flexran_get_ul_scheduler_name(mid_t mod_id); +int flexran_set_ul_scheduler(mid_t mod_id, char *sched); /************************** S1AP **************************/ /* Get the number of MMEs to be connected */ diff --git a/openair2/LAYER2/MAC/main.c b/openair2/LAYER2/MAC/main.c index 24038e60d5..af6d1a7ac3 100644 --- a/openair2/LAYER2/MAC/main.c +++ b/openair2/LAYER2/MAC/main.c @@ -100,6 +100,7 @@ void mac_top_init_eNB(void) mac[i]->if_inst = IF_Module_init(i); + mac[i]->pre_processor_dl.algorithm = 0; mac[i]->pre_processor_dl.dl = dlsch_scheduler_pre_processor; char *s = "round_robin_dl"; void *d = dlsym(NULL, s); @@ -107,6 +108,7 @@ void mac_top_init_eNB(void) mac[i]->pre_processor_dl.dl_algo = *(default_sched_dl_algo_t *) d; mac[i]->pre_processor_dl.dl_algo.data = mac[i]->pre_processor_dl.dl_algo.setup(); + mac[i]->pre_processor_ul.algorithm = 0; mac[i]->pre_processor_ul.ul = ulsch_scheduler_pre_processor; s = "round_robin_ul"; d = dlsym(NULL, s); diff --git a/openair2/LAYER2/MAC/slicing/slicing.c b/openair2/LAYER2/MAC/slicing/slicing.c index a1de326df0..9c88f6cffb 100644 --- a/openair2/LAYER2/MAC/slicing/slicing.c +++ b/openair2/LAYER2/MAC/slicing/slicing.c @@ -258,13 +258,26 @@ int addmod_static_slice_ul(slice_info_t *si, return si->num - 1; } -int remove_static_slice(slice_info_t *si, uint8_t slice_idx) { +int remove_static_slice_dl(slice_info_t *si, uint8_t slice_idx) { if (slice_idx == 0) return 0; slice_t *sr = _remove_slice(&si->num, si->s, si->UE_assoc_slice, slice_idx); if (!sr) return 0; free(sr->algo_data); + sr->dl_algo.unset(&sr->dl_algo.data); + free(sr); + return 1; +} + +int remove_static_slice_ul(slice_info_t *si, uint8_t slice_idx) { + if (slice_idx == 0) + return 0; + slice_t *sr = _remove_slice(&si->num, si->s, si->UE_assoc_slice, slice_idx); + if (!sr) + return 0; + free(sr->algo_data); + sr->ul_algo.unset(&sr->ul_algo.data); free(sr); return 1; } @@ -528,6 +541,7 @@ pp_impl_param_t static_dl_init(module_id_t mod_id, int CC_id) { dlp->posLow = 0; dlp->posHigh = to_rbg(RC.mac[mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth) - 1; default_sched_dl_algo_t *algo = &RC.mac[mod_id]->pre_processor_dl.dl_algo; + algo->data = NULL; DevAssert(0 == addmod_static_slice_dl(si, 0, strdup("default"), algo, dlp)); const UE_list_t *UE_list = &RC.mac[mod_id]->UE_info.list; for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) @@ -539,7 +553,7 @@ pp_impl_param_t static_dl_init(module_id_t mod_id, int CC_id) { sttc.remove_UE = slicing_remove_UE; sttc.move_UE = slicing_move_UE; sttc.addmod_slice = addmod_static_slice_dl; - sttc.remove_slice = remove_static_slice; + sttc.remove_slice = remove_static_slice_dl; sttc.dl = static_dl; // current DL algo becomes default scheduler sttc.dl_algo = *algo; @@ -564,6 +578,7 @@ pp_impl_param_t static_ul_init(module_id_t mod_id, int CC_id) { ulp->posLow = 0; ulp->posHigh = to_prb(RC.mac[mod_id]->common_channels[CC_id].ul_Bandwidth) - 1; default_sched_ul_algo_t *algo = &RC.mac[mod_id]->pre_processor_ul.ul_algo; + algo->data = NULL; DevAssert(0 == addmod_static_slice_ul(si, 0, strdup("default"), algo, ulp)); const UE_list_t *UE_list = &RC.mac[mod_id]->UE_info.list; for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) @@ -575,7 +590,7 @@ pp_impl_param_t static_ul_init(module_id_t mod_id, int CC_id) { sttc.remove_UE = slicing_remove_UE; sttc.move_UE = slicing_move_UE; sttc.addmod_slice = addmod_static_slice_ul; - sttc.remove_slice = remove_static_slice; + sttc.remove_slice = remove_static_slice_ul; sttc.ul = static_ul; // current DL algo becomes default scheduler sttc.ul_algo = *algo; From 05c10662daf0ee11dee115e473cf7681000a2fc1 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Tue, 23 Jun 2020 13:25:28 +0200 Subject: [PATCH 430/553] FlexRAN Bugfix: Free Ringbuffer on exit --- openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c index e5d1c94c95..4c5f3e5609 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c @@ -1619,6 +1619,11 @@ int flexran_agent_unregister_mac_xface(mid_t mod_id) LOG_E(FLEXRAN_AGENT, "MAC agent CM for eNB %d is not registered\n", mod_id); return -1; } + + lfds700_ringbuffer_cleanup(&ringbuffer_state[mod_id], NULL ); + free(dl_mac_config_array[mod_id]); + lfds700_misc_library_cleanup(); + AGENT_MAC_xface *xface = agent_mac_xface[mod_id]; xface->flexran_agent_send_sr_info = NULL; xface->flexran_agent_send_sf_trigger = NULL; From dcd43c1526104567d052e6138f9fd799ee3befa6 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Tue, 23 Jun 2020 13:50:59 +0200 Subject: [PATCH 431/553] FlexRAN: use lock-free ringbuffers for slice conf Use LFDS 7.0.0 Ringbuffer implementation to handle * Slice Configuration * UE slice association which is then uploaded through MAC scheduling thread --- .../CONTROL_MODULES/MAC/flexran_agent_mac.c | 100 ++++++++++++++++-- 1 file changed, 92 insertions(+), 8 deletions(-) diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c index 4c5f3e5609..f1daacbb65 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c @@ -49,6 +49,14 @@ struct lfds700_misc_prng_state ps[NUM_MAX_ENB]; struct lfds700_ringbuffer_element *dl_mac_config_array[NUM_MAX_ENB]; struct lfds700_ringbuffer_state ringbuffer_state[NUM_MAX_ENB]; +/* Ringbuffer-related to slice configuration */ +struct lfds700_ringbuffer_element *slice_config_array[NUM_MAX_ENB]; +struct lfds700_ringbuffer_state slice_config_ringbuffer_state[NUM_MAX_ENB]; + +/* Ringbuffer-related to slice configuration */ +struct lfds700_ringbuffer_element *ue_assoc_array[NUM_MAX_ENB]; +struct lfds700_ringbuffer_state ue_assoc_ringbuffer_state[NUM_MAX_ENB]; + int flexran_agent_mac_stats_reply_ue(mid_t mod_id, Protocol__FlexUeStatsReport **ue_report, int n_ue, @@ -1341,6 +1349,33 @@ void flexran_agent_init_mac_agent(mid_t mod_id) { AssertFatal(i == 0, "posix_memalign(): could not allocate aligned memory for lfds library\n"); lfds700_ringbuffer_init_valid_on_current_logical_core(&ringbuffer_state[mod_id], dl_mac_config_array[mod_id], num_elements, &ps[mod_id], NULL); + + struct lfds700_misc_prng_state scrng; + i = posix_memalign((void **) &slice_config_array[mod_id], + LFDS700_PAL_ATOMIC_ISOLATION_IN_BYTES, + sizeof(struct lfds700_ringbuffer_element) * num_elements); + AssertFatal(i == 0, + "posix_memalign(): could not allocate aligned memory\n"); + lfds700_ringbuffer_init_valid_on_current_logical_core( + &slice_config_ringbuffer_state[mod_id], + slice_config_array[mod_id], + num_elements, + &scrng, + NULL); + + struct lfds700_misc_prng_state uarng; + i = posix_memalign((void **) &ue_assoc_array[mod_id], + LFDS700_PAL_ATOMIC_ISOLATION_IN_BYTES, + sizeof(struct lfds700_ringbuffer_element) * num_elements); + AssertFatal(i == 0, + "posix_memalign(): could not allocate aligned memory\n"); + lfds700_ringbuffer_init_valid_on_current_logical_core( + &ue_assoc_ringbuffer_state[mod_id], + ue_assoc_array[mod_id], + num_elements, + &uarng, + NULL); + for (i = 0; i < MAX_MOBILES_PER_ENB; i++) { for (j = 0; j < 8; j++) { if (RC.mac && RC.mac[mod_id]) @@ -1622,6 +1657,10 @@ int flexran_agent_unregister_mac_xface(mid_t mod_id) lfds700_ringbuffer_cleanup(&ringbuffer_state[mod_id], NULL ); free(dl_mac_config_array[mod_id]); + lfds700_ringbuffer_cleanup(&slice_config_ringbuffer_state[mod_id], NULL ); + free(slice_config_array[mod_id]); + lfds700_ringbuffer_cleanup(&ue_assoc_ringbuffer_state[mod_id], NULL ); + free(ue_assoc_array[mod_id]); lfds700_misc_library_cleanup(); AGENT_MAC_xface *xface = agent_mac_xface[mod_id]; @@ -1661,23 +1700,68 @@ void helper_destroy_mac_slice_config(Protocol__FlexSliceConfig *slice_config) { void prepare_update_slice_config(mid_t mod_id, Protocol__FlexSliceConfig **slice_config) { if (!*slice_config) return; + /* just use the memory and set to NULL in original */ Protocol__FlexSliceConfig *sc = *slice_config; *slice_config = NULL; - /* TODO handle using lock-free queue */ - apply_update_dl_slice_config(mod_id, sc->dl); - apply_update_ul_slice_config(mod_id, sc->ul); + struct lfds700_misc_prng_state ls; + LFDS700_MISC_MAKE_VALID_ON_CURRENT_LOGICAL_CORE_INITS_COMPLETED_BEFORE_NOW_ON_ANY_OTHER_LOGICAL_CORE; + lfds700_misc_prng_init(&ls); + enum lfds700_misc_flag overwrite_occurred_flag; - helper_destroy_mac_slice_config(*slice_config); + Protocol__FlexSliceConfig *overwritten_sc; + lfds700_ringbuffer_write(&slice_config_ringbuffer_state[mod_id], + NULL, + (void *)sc, + &overwrite_occurred_flag, + NULL, + (void **)&overwritten_sc, + &ls); + + if (overwrite_occurred_flag == LFDS700_MISC_FLAG_RAISED) { + helper_destroy_mac_slice_config(overwritten_sc); + LOG_E(FLEXRAN_AGENT, "lost slice config: too many reconfigurations at once\n"); + } } void prepare_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig **ue_config) { - /* TODO handle using lock-free queue */ - apply_ue_slice_assoc_update(mod_id, *ue_config); + struct lfds700_misc_prng_state ls; + LFDS700_MISC_MAKE_VALID_ON_CURRENT_LOGICAL_CORE_INITS_COMPLETED_BEFORE_NOW_ON_ANY_OTHER_LOGICAL_CORE; + lfds700_misc_prng_init(&ls); + enum lfds700_misc_flag overwrite_occurred_flag; - free(*ue_config); - *ue_config = NULL; + Protocol__FlexUeConfig *overwritten_ue_config; + lfds700_ringbuffer_write(&ue_assoc_ringbuffer_state[mod_id], + NULL, + (void *) *ue_config, + &overwrite_occurred_flag, + NULL, + (void **)&overwritten_ue_config, + &ls); + + if (overwrite_occurred_flag == LFDS700_MISC_FLAG_RAISED) { + free(overwritten_ue_config); + LOG_E(FLEXRAN_AGENT, "lost UE-slice association: too many UE-slice associations at once\n"); + } } void flexran_agent_slice_update(mid_t mod_id) { + struct lfds700_misc_prng_state ls; + LFDS700_MISC_MAKE_VALID_ON_CURRENT_LOGICAL_CORE_INITS_COMPLETED_BEFORE_NOW_ON_ANY_OTHER_LOGICAL_CORE; + lfds700_misc_prng_init(&ls); + + Protocol__FlexSliceConfig *sc = NULL; + struct lfds700_ringbuffer_state *state = &slice_config_ringbuffer_state[mod_id]; + if (lfds700_ringbuffer_read(state, NULL, (void **) &sc, &ls) != 0) { + apply_update_dl_slice_config(mod_id, sc->dl); + apply_update_ul_slice_config(mod_id, sc->ul); + helper_destroy_mac_slice_config(sc); + } + + Protocol__FlexUeConfig *ue_config = NULL; + state = &ue_assoc_ringbuffer_state[mod_id]; + if (lfds700_ringbuffer_read(state, NULL, (void **) &ue_config, &ls) != 0) { + apply_ue_slice_assoc_update(mod_id, ue_config); + free(ue_config); + } } From 548e8f87972f04965eeba83cde0ef2fde4bc7e53 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Wed, 1 Jul 2020 10:16:48 +0200 Subject: [PATCH 432/553] fix ulsim compilation --- openair1/SIMULATION/NR_PHY/ulsim.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openair1/SIMULATION/NR_PHY/ulsim.c b/openair1/SIMULATION/NR_PHY/ulsim.c index 76ed96d7a4..b6b432f216 100644 --- a/openair1/SIMULATION/NR_PHY/ulsim.c +++ b/openair1/SIMULATION/NR_PHY/ulsim.c @@ -320,11 +320,11 @@ int main(int argc, char **argv) break; case 'M': - SSB_positions = atoi(optarg); + // SSB_positions = atoi(optarg); break; case 'N': - Nid_cell = atoi(optarg); + // Nid_cell = atoi(optarg); break; case 'R': From fa5213dfedc94e417d661529e774ffe203ada4ae Mon Sep 17 00:00:00 2001 From: Florian Kaltenberger Date: Wed, 1 Jul 2020 14:43:44 +0200 Subject: [PATCH 433/553] removing some of the s1ap and x2ap xer prints --- openair2/X2AP/x2ap_eNB_decoder.c | 4 ++-- openair3/S1AP/s1ap_eNB_encoder.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/openair2/X2AP/x2ap_eNB_decoder.c b/openair2/X2AP/x2ap_eNB_decoder.c index 93b82c2765..3762bc06dc 100644 --- a/openair2/X2AP/x2ap_eNB_decoder.c +++ b/openair2/X2AP/x2ap_eNB_decoder.c @@ -144,9 +144,9 @@ int x2ap_eNB_decode_pdu(X2AP_X2AP_PDU_t *pdu, const uint8_t *const buffer, uint3 length, 0, 0); - //if (asn1_xer_print) { + if (asn1_xer_print) { xer_fprint(stdout, &asn_DEF_X2AP_X2AP_PDU, pdu); - //} + } if (dec_ret.code != RC_OK) { X2AP_ERROR("Failed to decode pdu\n"); diff --git a/openair3/S1AP/s1ap_eNB_encoder.c b/openair3/S1AP/s1ap_eNB_encoder.c index 86536ac525..227a3cb6a9 100644 --- a/openair3/S1AP/s1ap_eNB_encoder.c +++ b/openair3/S1AP/s1ap_eNB_encoder.c @@ -129,9 +129,9 @@ int s1ap_eNB_encode_initiating(S1AP_S1AP_PDU_t *pdu, return -1; } - //if (asn1_xer_print) { + if (asn1_xer_print) { xer_fprint(stdout, &asn_DEF_S1AP_S1AP_PDU, (void *)pdu); - //} + } memset(&res, 0, sizeof(res)); res = asn_encode_to_new_buffer(NULL, ATS_ALIGNED_CANONICAL_PER, &asn_DEF_S1AP_S1AP_PDU, pdu); From 71f75a3d889c924cb4d773f34a54ff13eb9bf676 Mon Sep 17 00:00:00 2001 From: Cedric Roux Date: Thu, 2 Jul 2020 09:13:45 +0200 Subject: [PATCH 434/553] hack for RLC AM ACK reporting hack: in schedule_ue_spec, 3 bytes are "reserved" (this should be done better). An RLC AM entity may ask for only 2 bytes for ACKing and get a TBS of 32 bits and due to these 3 reserved bytes we may end up with only 1 byte left for RLC, which is not enough. This hack prevents the problem. To be done better at some point. If the function schedule_ue_spec is (has been) reworked, this hack can be removed. Dig for "TBS - ta_len - header_length_total - sdu_length_total - 3" in schedule_ue_spec. This should be done better at some point. --- openair2/LAYER2/MAC/pre_processor.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/openair2/LAYER2/MAC/pre_processor.c b/openair2/LAYER2/MAC/pre_processor.c index 8569d8f166..4f3baf1783 100644 --- a/openair2/LAYER2/MAC/pre_processor.c +++ b/openair2/LAYER2/MAC/pre_processor.c @@ -295,6 +295,18 @@ store_dlsch_buffer(module_id_t Mod_id, #endif } + /* hack: in schedule_ue_spec, 3 bytes are "reserved" (this should be + * done better). An RLC AM entity may ask for only 2 bytes for + * ACKing and get a TBS of 32 bits and due to these 3 reserved bytes we may + * end up with only 1 byte left for RLC, which is not enough. This hack + * prevents the problem. To be done better at some point. If the function + * schedule_ue_spec is (has been) reworked, this hack can be removed. + * Dig for "TBS - ta_len - header_length_total - sdu_length_total - 3" + * in schedule_ue_spec. + */ + if (UE_template->dl_buffer_total > 0 && UE_template->dl_buffer_total <= 2) + UE_template->dl_buffer_total += 3; + if (UE_template->dl_buffer_total > 0) LOG_D(MAC, "[eNB %d] Frame %d Subframe %d : RLC status for UE %d : total DL buffer size %d and total number of pdu %d \n", From e7d2b8eeb1935850fd54fd2508f4c55a6ae9486e Mon Sep 17 00:00:00 2001 From: matzakos Date: Wed, 1 Jul 2020 14:54:59 +0200 Subject: [PATCH 435/553] Resolve remaining conflicts after merge of develop into NR_RRC_harq_hacks --- openair2/RRC/NR/rrc_gNB_nsa.c | 75 -- openair2/RRC/NR/rrc_gNB_reconfig.c | 1710 +--------------------------- 2 files changed, 1 insertion(+), 1784 deletions(-) diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c index c50557e6a8..64c762dd42 100644 --- a/openair2/RRC/NR/rrc_gNB_nsa.c +++ b/openair2/RRC/NR/rrc_gNB_nsa.c @@ -147,80 +147,6 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_ carrier->initial_csi_index[rrc->Nb_ue]); ue_context_p->ue_id_rnti = ue_context_p->ue_context.secondaryCellGroup->spCellConfig->reconfigurationWithSync->newUE_Identity; NR_CG_Config_t *CG_Config = calloc(1,sizeof(*CG_Config)); -<<<<<<< HEAD - memset((void*)CG_Config,0,sizeof(*CG_Config)); - - __attribute__((unused))int CG_Config_size = generate_CG_Config(rrc,CG_Config,ue_context_p->ue_context.reconfig,ue_context_p->ue_context.rb_config); - - if(m!=NULL){ - uint8_t inde_list[m->nb_e_rabs_tobeadded]; - memset(inde_list, 0, m->nb_e_rabs_tobeadded*sizeof(uint8_t)); - - if (m->nb_e_rabs_tobeadded>0){ - for (int i=0; inb_e_rabs_tobeadded; i++){ - // Add the new E-RABs at the corresponding rrc ue context of the gNB - ue_context_p->ue_context.e_rab[i].param.e_rab_id = m->e_rabs_tobeadded[i].e_rab_id; - ue_context_p->ue_context.e_rab[i].param.gtp_teid = m->e_rabs_tobeadded[i].gtp_teid; - memcpy(&ue_context_p->ue_context.e_rab[i].param.sgw_addr, &m->e_rabs_tobeadded[i].sgw_addr, sizeof(transport_layer_addr_t)); - ue_context_p->ue_context.nb_of_e_rabs++; - //Fill the required E-RAB specific information for the creation of the S1-U tunnel between the gNB and the SGW - create_tunnel_req.eps_bearer_id[i] = ue_context_p->ue_context.e_rab[i].param.e_rab_id; - create_tunnel_req.sgw_S1u_teid[i] = ue_context_p->ue_context.e_rab[i].param.gtp_teid; - memcpy(&create_tunnel_req.sgw_addr[i], &ue_context_p->ue_context.e_rab[i].param.sgw_addr, sizeof(transport_layer_addr_t)); - inde_list[i] = i; - LOG_I(RRC,"S1-U tunnel: index %d target sgw ip %d.%d.%d.%d length %d gtp teid %u\n", - i, - create_tunnel_req.sgw_addr[i].buffer[0], - create_tunnel_req.sgw_addr[i].buffer[1], - create_tunnel_req.sgw_addr[i].buffer[2], - create_tunnel_req.sgw_addr[i].buffer[3], - create_tunnel_req.sgw_addr[i].length, - create_tunnel_req.sgw_S1u_teid[i]); - } - //PM: Is this where we should extract the rnti from? - create_tunnel_req.rnti = ue_context_p->ue_id_rnti; - create_tunnel_req.num_tunnels = m->nb_e_rabs_tobeadded; - RB_INSERT(rrc_nr_ue_tree_s, &RC.nrrrc[rrc->module_id]->rrc_ue_head, ue_context_p); - - PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, rrc->module_id, GNB_FLAG_YES, ue_context_p->ue_id_rnti, 0, 0,rrc->module_id); - gtpv1u_create_s1u_tunnel( - ctxt.instance, - &create_tunnel_req, - &create_tunnel_resp); - rrc_gNB_process_GTPV1U_CREATE_TUNNEL_RESP( - &ctxt, - &create_tunnel_resp, - &inde_list[0]); - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).nb_e_rabs_admitted_tobeadded = m->nb_e_rabs_tobeadded; - for(int i=0; iue_context.nb_of_e_rabs; i++){ - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].e_rab_id = ue_context_p->ue_context.e_rab[i].param.e_rab_id; - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gtp_teid = create_tunnel_resp.enb_S1u_teid[i]; - memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr, &create_tunnel_resp.enb_addr, sizeof(transport_layer_addr_t)); - - //The length field in the X2AP targetting structure is expected in bits but the create_tunnel_resp returns the address length in bytes - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.length = create_tunnel_resp.enb_addr.length*8; - - LOG_I(RRC,"S1-U create_tunnel_resp tunnel: index %d target gNB ip %d.%d.%d.%d length %d gtp teid %u\n", - i, - create_tunnel_resp.enb_addr.buffer[0], - create_tunnel_resp.enb_addr.buffer[1], - create_tunnel_resp.enb_addr.buffer[2], - create_tunnel_resp.enb_addr.buffer[3], - create_tunnel_resp.enb_addr.length, - create_tunnel_resp.enb_S1u_teid[i]); - LOG_I(RRC,"X2AP sGNB Addition Request: index %d target gNB ip %d.%d.%d.%d length %d gtp teid %u\n", - i, - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[0], - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[1], - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[2], - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[3], - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.length, - X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gtp_teid); - } - } - else - LOG_W(RRC, "No E-RAB to be added received from SgNB Addition Request message \n"); -======= memset((void *)CG_Config,0,sizeof(*CG_Config)); //int CG_Config_size = generate_CG_Config(rrc,CG_Config,ue_context_p->ue_context.reconfig,ue_context_p->ue_context.rb_config); generate_CG_Config(rrc,CG_Config,ue_context_p->ue_context.reconfig,ue_context_p->ue_context.rb_config); @@ -291,7 +217,6 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_ } } else LOG_W(RRC, "No E-RAB to be added received from SgNB Addition Request message \n"); ->>>>>>> origin/develop } //X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).rrc_buffer_size = CG_Config_size; //Need to verify correct value for the buffer_size diff --git a/openair2/RRC/NR/rrc_gNB_reconfig.c b/openair2/RRC/NR/rrc_gNB_reconfig.c index dede5c275e..7b0bb099f7 100644 --- a/openair2/RRC/NR/rrc_gNB_reconfig.c +++ b/openair2/RRC/NR/rrc_gNB_reconfig.c @@ -182,7 +182,6 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA = calloc(1, sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA)); secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->present= NR_SetupRelease_DMRS_DownlinkConfig_PR_setup; -<<<<<<< HEAD secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup)); secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type=NULL; @@ -551,346 +550,12 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco bwp->bwp_Dedicated->pdsch_Config = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config)); -======= - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup = calloc(1, - sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->maxLength=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->scramblingID0=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->scramblingID1=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->phaseTrackingRS=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = calloc(1, - sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition)); - *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = - NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList=calloc(1, - sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList)); - NR_TCI_State_t *tci0=calloc(1,sizeof(*tci0)); - tci0->tci_StateId=0; - tci0->qcl_Type1.cell=NULL; - tci0->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci0->qcl_Type1.bwp_Id)); - *tci0->qcl_Type1.bwp_Id=1; - tci0->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tci0->qcl_Type1.referenceSignal.choice.csi_rs = 2; - tci0->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci0); - NR_TCI_State_t *tci1=calloc(1,sizeof(*tci1)); - tci1->tci_StateId=1; - tci1->qcl_Type1.cell=NULL; - tci1->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci1->qcl_Type1.bwp_Id)); - *tci1->qcl_Type1.bwp_Id=1; - tci1->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tci1->qcl_Type1.referenceSignal.choice.csi_rs = 6; - tci1->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci1); - NR_TCI_State_t *tci2=calloc(1,sizeof(*tci2)); - tci2->tci_StateId=2; - tci2->qcl_Type1.cell=NULL; - tci2->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci2->qcl_Type1.bwp_Id)); - *tci2->qcl_Type1.bwp_Id=1; - tci2->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tci2->qcl_Type1.referenceSignal.choice.csi_rs = 10; - tci2->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci2); - NR_TCI_State_t *tci3=calloc(1,sizeof(*tci3)); - tci3->tci_StateId=3; - tci3->qcl_Type1.cell=NULL; - tci3->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci3->qcl_Type1.bwp_Id)); - *tci3->qcl_Type1.bwp_Id=1; - tci3->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tci3->qcl_Type1.referenceSignal.choice.csi_rs = 14; - tci3->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci3); - NR_TCI_State_t *tci4=calloc(1,sizeof(*tci4)); - tci4->tci_StateId=4; - tci4->qcl_Type1.cell=NULL; - tci4->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci4->qcl_Type1.bwp_Id)); - *tci4->qcl_Type1.bwp_Id=1; - tci4->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tci4->qcl_Type1.referenceSignal.choice.csi_rs = 18; - tci4->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci4); - NR_TCI_State_t *tci5=calloc(1,sizeof(*tci5)); - tci5->tci_StateId=5; - tci5->qcl_Type1.cell=NULL; - tci5->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci5->qcl_Type1.bwp_Id)); - *tci5->qcl_Type1.bwp_Id=1; - tci5->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tci5->qcl_Type1.referenceSignal.choice.csi_rs = 22; - tci5->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci5); - NR_TCI_State_t *tci6=calloc(1,sizeof(*tci6)); - tci6->tci_StateId=6; - tci6->qcl_Type1.cell=NULL; - tci6->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci6->qcl_Type1.bwp_Id)); - *tci6->qcl_Type1.bwp_Id=1; - tci6->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tci6->qcl_Type1.referenceSignal.choice.csi_rs = 26; - tci6->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci6); - NR_TCI_State_t *tci7=calloc(1,sizeof(*tci7)); - tci7->tci_StateId=7; - tci7->qcl_Type1.cell=NULL; - tci7->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci7->qcl_Type1.bwp_Id)); - *tci7->qcl_Type1.bwp_Id=1; - tci7->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tci7->qcl_Type1.referenceSignal.choice.csi_rs = 30; - tci7->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci7); - NR_TCI_State_t *tci8=calloc(1,sizeof(*tci8)); - tci8->tci_StateId=8; - tci8->qcl_Type1.cell=NULL; - tci8->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci8->qcl_Type1.bwp_Id)); - *tci8->qcl_Type1.bwp_Id=1; - tci8->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tci8->qcl_Type1.referenceSignal.choice.ssb = 0; - tci8->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci8); - NR_TCI_State_t *tci9=calloc(1,sizeof(*tci9)); - tci9->tci_StateId=9; - tci9->qcl_Type1.cell=NULL; - tci9->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci9->qcl_Type1.bwp_Id)); - *tci9->qcl_Type1.bwp_Id=1; - tci9->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tci9->qcl_Type1.referenceSignal.choice.ssb = 1; - tci9->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci9); - NR_TCI_State_t *tci10=calloc(1,sizeof(*tci10)); - tci10->tci_StateId=10; - tci10->qcl_Type1.cell=NULL; - tci10->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci10->qcl_Type1.bwp_Id)); - *tci10->qcl_Type1.bwp_Id=1; - tci10->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tci10->qcl_Type1.referenceSignal.choice.ssb = 2; - tci10->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci10); - NR_TCI_State_t *tci11=calloc(1,sizeof(*tci11)); - tci11->tci_StateId=11; - tci11->qcl_Type1.cell=NULL; - tci11->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci11->qcl_Type1.bwp_Id)); - *tci11->qcl_Type1.bwp_Id=1; - tci11->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tci11->qcl_Type1.referenceSignal.choice.ssb = 3; - tci11->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci11); - NR_TCI_State_t *tci12=calloc(1,sizeof(*tci12)); - tci12->tci_StateId=12; - tci12->qcl_Type1.cell=NULL; - tci12->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci12->qcl_Type1.bwp_Id)); - *tci12->qcl_Type1.bwp_Id=1; - tci12->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tci12->qcl_Type1.referenceSignal.choice.ssb = 4; - tci12->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci12); - NR_TCI_State_t *tci13=calloc(1,sizeof(*tci13)); - tci13->tci_StateId=13; - tci13->qcl_Type1.cell=NULL; - tci13->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci13->qcl_Type1.bwp_Id)); - *tci13->qcl_Type1.bwp_Id=1; - tci13->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tci13->qcl_Type1.referenceSignal.choice.ssb = 5; - tci13->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci13); - NR_TCI_State_t *tci14=calloc(1,sizeof(*tci14)); - tci14->tci_StateId=14; - tci14->qcl_Type1.cell=NULL; - tci14->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci14->qcl_Type1.bwp_Id)); - *tci14->qcl_Type1.bwp_Id=1; - tci14->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tci14->qcl_Type1.referenceSignal.choice.ssb = 6; - tci14->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci14); - NR_TCI_State_t *tci15=calloc(1,sizeof(*tci15)); - tci15->tci_StateId=15; - tci15->qcl_Type1.cell=NULL; - tci15->qcl_Type1.bwp_Id=calloc(1,sizeof(*tci15->qcl_Type1.bwp_Id)); - *tci15->qcl_Type1.bwp_Id=1; - tci15->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tci15->qcl_Type1.referenceSignal.choice.ssb = 7; - tci15->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci15); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternToReleaseList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup1=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup2=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rbg_Size=NR_PDSCH_Config__rbg_Size_config1; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->mcs_Table=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = calloc(1, - sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI)); - *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = NR_PDSCH_Config__maxNrofCodeWordsScheduledByDCI_n1; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.present = NR_PDSCH_Config__prb_BundlingType_PR_staticBundling; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling = calloc(1, - sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = - calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize)); - *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = - NR_PDSCH_Config__prb_BundlingType__staticBundling__bundleSize_wideband; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToAddModList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToReleaseList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToAddModList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->sps_Config = NULL; //calloc(1,sizeof(struct NR_SetupRelease_SPS_Config)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig = calloc(1, - sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->present = NR_SetupRelease_RadioLinkMonitoringConfig_PR_setup; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup = calloc(1, - sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->failureDetectionResourcesToAddModList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->failureDetectionResourcesToReleaseList=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = calloc(1, - sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount)); - *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = - NR_RadioLinkMonitoringConfig__beamFailureInstanceMaxCount_n3; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = calloc(1, - sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer)); - *secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = - NR_RadioLinkMonitoringConfig__beamFailureDetectionTimer_pbfd2; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToReleaseList= NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList)); - NR_BWP_Downlink_t *bwp=calloc(1,sizeof(*bwp)); - bwp->bwp_Id=1; - bwp->bwp_Common=calloc(1,sizeof(*bwp->bwp_Common)); - // copy common BWP size from initial BWP except for bandwdith - memcpy((void *)&bwp->bwp_Common->genericParameters, - &servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->genericParameters, - sizeof(bwp->bwp_Common->genericParameters)); - bwp->bwp_Common->genericParameters.locationAndBandwidth=PRBalloc_to_locationandbandwidth( - servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth,0); - bwp->bwp_Common->pdcch_ConfigCommon=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon)); - bwp->bwp_Common->pdcch_ConfigCommon->present = NR_SetupRelease_PDCCH_ConfigCommon_PR_setup; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup = calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup)); - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->controlResourceSetZero=NULL; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet)); - NR_ControlResourceSet_t *coreset = calloc(1,sizeof(*coreset)); - coreset->controlResourceSetId=1; - // frequencyDomainResources '11111111 11111111 00000000 00000000 00000000 00000'B, - coreset->frequencyDomainResources.buf = calloc(1,6); - coreset->frequencyDomainResources.buf[0] = 0xff; - coreset->frequencyDomainResources.buf[1] = 0xff; - coreset->frequencyDomainResources.buf[2] = 0; - coreset->frequencyDomainResources.buf[3] = 0; - coreset->frequencyDomainResources.buf[4] = 0; - coreset->frequencyDomainResources.buf[5] = 0; - coreset->frequencyDomainResources.size = 6; - coreset->frequencyDomainResources.bits_unused = 3; - coreset->duration=1; - coreset->cce_REG_MappingType.present = NR_ControlResourceSet__cce_REG_MappingType_PR_nonInterleaved; - coreset->precoderGranularity = NR_ControlResourceSet__precoderGranularity_sameAsREG_bundle; - coreset->tci_StatesPDCCH_ToAddList=calloc(1,sizeof(*coreset->tci_StatesPDCCH_ToAddList)); - NR_TCI_StateId_t *tci[8]; - - for (int i=0; i<8; i++) { - tci[i]=calloc(1,sizeof(*tci[i])); - *tci[i] = i; - ASN_SEQUENCE_ADD(&coreset->tci_StatesPDCCH_ToAddList->list,tci[i]); - } - - coreset->tci_StatesPDCCH_ToReleaseList = NULL; - coreset->tci_PresentInDCI = NULL; - coreset->pdcch_DMRS_ScramblingID = NULL; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet = coreset; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->searchSpaceZero=NULL; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList=NULL; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList)); - NR_SearchSpace_t *ss=calloc(1,sizeof(*ss)); - ss->searchSpaceId = 1; - ss->controlResourceSetId=calloc(1,sizeof(*ss->controlResourceSetId)); - *ss->controlResourceSetId=1; - ss->monitoringSlotPeriodicityAndOffset = calloc(1,sizeof(*ss->monitoringSlotPeriodicityAndOffset)); - ss->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1; - ss->duration=NULL; - ss->monitoringSymbolsWithinSlot = calloc(1,sizeof(*ss->monitoringSymbolsWithinSlot)); - ss->monitoringSymbolsWithinSlot->buf = calloc(1,2); - // should be '1100 0000 0000 00'B (LSB first!), first two symols in slot, adjust if needed - ss->monitoringSymbolsWithinSlot->buf[1] = 0; - ss->monitoringSymbolsWithinSlot->buf[0] = (1<<7) | (1<<6); - ss->monitoringSymbolsWithinSlot->size = 2; - ss->monitoringSymbolsWithinSlot->bits_unused = 2; - ss->nrofCandidates = calloc(1,sizeof(*ss->nrofCandidates)); - ss->nrofCandidates->aggregationLevel1 = NR_SearchSpace__nrofCandidates__aggregationLevel1_n0; - ss->nrofCandidates->aggregationLevel2 = NR_SearchSpace__nrofCandidates__aggregationLevel2_n0; - ss->nrofCandidates->aggregationLevel4 = NR_SearchSpace__nrofCandidates__aggregationLevel4_n1; - ss->nrofCandidates->aggregationLevel8 = NR_SearchSpace__nrofCandidates__aggregationLevel8_n0; - ss->nrofCandidates->aggregationLevel16 = NR_SearchSpace__nrofCandidates__aggregationLevel16_n0; - ss->searchSpaceType = calloc(1,sizeof(*ss->searchSpaceType)); - ss->searchSpaceType->present = NR_SearchSpace__searchSpaceType_PR_common; - ss->searchSpaceType->choice.common=calloc(1,sizeof(*ss->searchSpaceType->choice.common)); - ss->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0 = calloc(1,sizeof(*ss->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0)); - ASN_SEQUENCE_ADD(&bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList->list,ss); - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->searchSpaceSIB1=NULL; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->searchSpaceOtherSystemInformation=NULL; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->pagingSearchSpace=NULL; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace)); - *bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace=1; - bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ext1=NULL; - bwp->bwp_Common->pdsch_ConfigCommon=calloc(1,sizeof(*bwp->bwp_Common->pdsch_ConfigCommon)); - bwp->bwp_Common->pdsch_ConfigCommon->present = NR_SetupRelease_PDSCH_ConfigCommon_PR_setup; - bwp->bwp_Common->pdsch_ConfigCommon->choice.setup = calloc(1,sizeof(*bwp->bwp_Common->pdsch_ConfigCommon->choice.setup)); - bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList = calloc(1,sizeof(*bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList)); - // copy PDSCH TimeDomainResourceAllocation from InitialBWP - NR_PDSCH_TimeDomainResourceAllocation_t *pdschi; - - for (int i=0; idownlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count; i++) { - pdschi= calloc(1,sizeof(*pdschi)); - AssertFatal(servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->k0!=NULL,"element %d is null\n",i); - pdschi->k0 = calloc(1,sizeof(*pdschi->k0)); - *pdschi->k0 = *servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->k0; - pdschi->mappingType = servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->mappingType; - pdschi->startSymbolAndLength = servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->startSymbolAndLength; - ASN_SEQUENCE_ADD(&bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list,pdschi); - } - - bwp->bwp_Dedicated=calloc(1,sizeof(*bwp->bwp_Dedicated)); - bwp->bwp_Dedicated->pdcch_Config=calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config)); - bwp->bwp_Dedicated->pdcch_Config->present = NR_SetupRelease_PDCCH_Config_PR_setup; - bwp->bwp_Dedicated->pdcch_Config->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup)); - bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList)); - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list, - coreset); - bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList)); - NR_SearchSpace_t *ss2 = calloc(1,sizeof(*ss2)); - ss2->searchSpaceId=2; - ss2->controlResourceSetId=calloc(1,sizeof(*ss2->controlResourceSetId)); - *ss2->controlResourceSetId=1; - ss2->monitoringSlotPeriodicityAndOffset=calloc(1,sizeof(*ss2->monitoringSlotPeriodicityAndOffset)); - ss2->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1; - ss2->monitoringSlotPeriodicityAndOffset->choice.sl1=(NULL_t)0; - ss2->duration=NULL; - ss2->monitoringSymbolsWithinSlot = calloc(1,sizeof(*ss2->monitoringSymbolsWithinSlot)); - ss2->monitoringSymbolsWithinSlot->buf = calloc(1,2); - ss2->monitoringSymbolsWithinSlot->size = 2; - ss2->monitoringSymbolsWithinSlot->bits_unused = 2; - ss2->monitoringSymbolsWithinSlot->buf[0]=0xc0; - ss2->monitoringSymbolsWithinSlot->buf[1]=0x0; - ss2->nrofCandidates=calloc(1,sizeof(*ss2->nrofCandidates)); - ss2->nrofCandidates->aggregationLevel1 = NR_SearchSpace__nrofCandidates__aggregationLevel1_n0; - ss2->nrofCandidates->aggregationLevel2 = NR_SearchSpace__nrofCandidates__aggregationLevel2_n0; - ss2->nrofCandidates->aggregationLevel4 = NR_SearchSpace__nrofCandidates__aggregationLevel4_n4; - ss2->nrofCandidates->aggregationLevel8 = NR_SearchSpace__nrofCandidates__aggregationLevel8_n0; - ss2->nrofCandidates->aggregationLevel16 = NR_SearchSpace__nrofCandidates__aggregationLevel16_n0; - ss2->searchSpaceType=calloc(1,sizeof(*ss2->searchSpaceType)); - ss2->searchSpaceType->present = NR_SearchSpace__searchSpaceType_PR_ue_Specific; - ss2->searchSpaceType->choice.ue_Specific = calloc(1,sizeof(*ss2->searchSpaceType->choice.ue_Specific)); - ss2->searchSpaceType->choice.ue_Specific->dci_Formats=NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_0_And_1_0; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list, - ss2); - bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToReleaseList = NULL; - bwp->bwp_Dedicated->pdsch_Config = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config)); ->>>>>>> origin/develop bwp->bwp_Dedicated->pdsch_Config->present = NR_SetupRelease_PDSCH_Config_PR_setup; bwp->bwp_Dedicated->pdsch_Config->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup)); bwp->bwp_Dedicated->pdsch_Config->choice.setup->dataScramblingIdentityPDSCH = NULL; bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA)); bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->present= NR_SetupRelease_DMRS_DownlinkConfig_PR_setup; -<<<<<<< HEAD + bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup)); bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type=NULL; @@ -2331,1379 +1996,6 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->spCellConfig->spCellConfigDedicated->pathlossReferenceLinking=NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->servingCellMO=NULL; -======= - bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup = calloc(1, - sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup)); - bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->maxLength=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->scramblingID0=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->scramblingID1=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->phaseTrackingRS=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = calloc(1, - sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition)); - *bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList=calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList)); - NR_TCI_State_t *tcid0=calloc(1,sizeof(*tcid0)); - tcid0->tci_StateId=0; - tcid0->qcl_Type1.cell=NULL; - tcid0->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid0->qcl_Type1.bwp_Id)); - *tcid0->qcl_Type1.bwp_Id=1; - tcid0->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tcid0->qcl_Type1.referenceSignal.choice.csi_rs = 2; - tcid0->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid0); - NR_TCI_State_t *tcid1=calloc(1,sizeof(*tcid1)); - tcid1->tci_StateId=0; - tcid1->qcl_Type1.cell=NULL; - tcid1->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid1->qcl_Type1.bwp_Id)); - *tcid1->qcl_Type1.bwp_Id=1; - tcid1->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tcid1->qcl_Type1.referenceSignal.choice.csi_rs = 6; - tcid1->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid1); - NR_TCI_State_t *tcid2=calloc(1,sizeof(*tcid2)); - tcid2->tci_StateId=2; - tcid2->qcl_Type1.cell=NULL; - tcid2->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid2->qcl_Type1.bwp_Id)); - *tcid2->qcl_Type1.bwp_Id=1; - tcid2->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tcid2->qcl_Type1.referenceSignal.choice.csi_rs = 10; - tcid2->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid2); - NR_TCI_State_t *tcid3=calloc(1,sizeof(*tcid3)); - tcid3->tci_StateId=3; - tcid3->qcl_Type1.cell=NULL; - tcid3->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid3->qcl_Type1.bwp_Id)); - *tcid3->qcl_Type1.bwp_Id=1; - tcid3->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tcid3->qcl_Type1.referenceSignal.choice.csi_rs = 14; - tcid3->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid3); - NR_TCI_State_t *tcid4=calloc(1,sizeof(*tcid4)); - tcid4->tci_StateId=4; - tcid4->qcl_Type1.cell=NULL; - tcid4->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid4->qcl_Type1.bwp_Id)); - *tcid4->qcl_Type1.bwp_Id=1; - tcid4->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tcid4->qcl_Type1.referenceSignal.choice.csi_rs = 18; - tcid4->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid4); - NR_TCI_State_t *tcid5=calloc(1,sizeof(*tcid5)); - tcid5->tci_StateId=5; - tcid5->qcl_Type1.cell=NULL; - tcid5->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid5->qcl_Type1.bwp_Id)); - *tcid5->qcl_Type1.bwp_Id=1; - tcid5->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tcid5->qcl_Type1.referenceSignal.choice.csi_rs = 22; - tcid5->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid5); - NR_TCI_State_t *tcid6=calloc(1,sizeof(*tcid6)); - tcid6->tci_StateId=6; - tcid6->qcl_Type1.cell=NULL; - tcid6->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid6->qcl_Type1.bwp_Id)); - *tcid6->qcl_Type1.bwp_Id=1; - tcid6->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tcid6->qcl_Type1.referenceSignal.choice.csi_rs = 26; - tcid6->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid6); - NR_TCI_State_t *tcid7=calloc(1,sizeof(*tcid7)); - tcid7->tci_StateId=7; - tcid7->qcl_Type1.cell=NULL; - tcid7->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid7->qcl_Type1.bwp_Id)); - *tcid7->qcl_Type1.bwp_Id=1; - tcid7->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_csi_rs; - tcid7->qcl_Type1.referenceSignal.choice.csi_rs = 30; - tcid7->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeA; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid7); - NR_TCI_State_t *tcid8=calloc(1,sizeof(*tcid8)); - tcid8->tci_StateId=8; - tcid8->qcl_Type1.cell=NULL; - tcid8->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid8->qcl_Type1.bwp_Id)); - *tcid8->qcl_Type1.bwp_Id=1; - tcid8->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tcid8->qcl_Type1.referenceSignal.choice.ssb = 0; - tcid8->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid8); - NR_TCI_State_t *tcid9=calloc(1,sizeof(*tcid9)); - tcid9->tci_StateId=9; - tcid9->qcl_Type1.cell=NULL; - tcid9->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid9->qcl_Type1.bwp_Id)); - *tcid9->qcl_Type1.bwp_Id=1; - tcid9->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tcid9->qcl_Type1.referenceSignal.choice.ssb = 1; - tcid9->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid9); - NR_TCI_State_t *tcid10=calloc(1,sizeof(*tcid10)); - tcid10->tci_StateId=10; - tcid10->qcl_Type1.cell=NULL; - tcid10->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid10->qcl_Type1.bwp_Id)); - *tcid10->qcl_Type1.bwp_Id=1; - tcid10->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tcid10->qcl_Type1.referenceSignal.choice.ssb = 2; - tcid10->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid10); - NR_TCI_State_t *tcid11=calloc(1,sizeof(*tcid11)); - tcid11->tci_StateId=11; - tcid11->qcl_Type1.cell=NULL; - tcid11->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid11->qcl_Type1.bwp_Id)); - *tcid11->qcl_Type1.bwp_Id=1; - tcid11->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tcid11->qcl_Type1.referenceSignal.choice.ssb = 3; - tcid11->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid11); - NR_TCI_State_t *tcid12=calloc(1,sizeof(*tcid12)); - tcid12->tci_StateId=12; - tcid12->qcl_Type1.cell=NULL; - tcid12->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid12->qcl_Type1.bwp_Id)); - *tcid12->qcl_Type1.bwp_Id=1; - tcid12->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tcid12->qcl_Type1.referenceSignal.choice.ssb = 4; - tcid12->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid12); - NR_TCI_State_t *tcid13=calloc(1,sizeof(*tcid13)); - tcid13->tci_StateId=13; - tcid13->qcl_Type1.cell=NULL; - tcid13->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid13->qcl_Type1.bwp_Id)); - *tcid13->qcl_Type1.bwp_Id=1; - tcid13->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tcid13->qcl_Type1.referenceSignal.choice.ssb = 5; - tcid13->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid13); - NR_TCI_State_t *tcid14=calloc(1,sizeof(*tcid14)); - tcid14->tci_StateId=14; - tcid14->qcl_Type1.cell=NULL; - tcid14->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid14->qcl_Type1.bwp_Id)); - *tcid14->qcl_Type1.bwp_Id=1; - tcid14->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tcid14->qcl_Type1.referenceSignal.choice.ssb = 6; - tcid14->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid14); - NR_TCI_State_t *tcid15=calloc(1,sizeof(*tcid15)); - tcid15->tci_StateId=15; - tcid15->qcl_Type1.cell=NULL; - tcid15->qcl_Type1.bwp_Id=calloc(1,sizeof(*tcid15->qcl_Type1.bwp_Id)); - *tcid15->qcl_Type1.bwp_Id=1; - tcid15->qcl_Type1.referenceSignal.present = NR_QCL_Info__referenceSignal_PR_ssb; - tcid15->qcl_Type1.referenceSignal.choice.ssb = 7; - tcid15->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC; - ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid15); - bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup1=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup2=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rbg_Size=NR_PDSCH_Config__rbg_Size_config1; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->mcs_Table=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI)); - *bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = NR_PDSCH_Config__maxNrofCodeWordsScheduledByDCI_n1; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.present = NR_PDSCH_Config__prb_BundlingType_PR_staticBundling; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling)); - bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = - calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize)); - *bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = NR_PDSCH_Config__prb_BundlingType__staticBundling__bundleSize_wideband; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToAddModList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToAddModList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup1=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup2=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->rbg_Size=NR_PDSCH_Config__rbg_Size_config1; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->mcs_Table=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI)); - *bwp->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI = NR_PDSCH_Config__maxNrofCodeWordsScheduledByDCI_n1; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.present = NR_PDSCH_Config__prb_BundlingType_PR_staticBundling; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling)); - bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = - calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize)); - *bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.choice.staticBundling->bundleSize = NR_PDSCH_Config__prb_BundlingType__staticBundling__bundleSize_wideband; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToAddModList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->zp_CSI_RS_ResourceToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToAddModList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->sp_ZP_CSI_RS_ResourceSetsToReleaseList=NULL; - bwp->bwp_Dedicated->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL; - bwp->bwp_Dedicated->sps_Config = NULL; //calloc(1,sizeof(struct NR_SetupRelease_SPS_Config)); - bwp->bwp_Dedicated->radioLinkMonitoringConfig = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig)); - bwp->bwp_Dedicated->radioLinkMonitoringConfig->present = NR_SetupRelease_RadioLinkMonitoringConfig_PR_setup; - bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup)); - bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->failureDetectionResourcesToAddModList=NULL; - bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->failureDetectionResourcesToReleaseList=NULL; - bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount)); - *bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = NR_RadioLinkMonitoringConfig__beamFailureInstanceMaxCount_n3; - bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer)); - *bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = NR_RadioLinkMonitoringConfig__beamFailureDetectionTimer_pbfd2; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list,bwp); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id)); - *secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id=1; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->bwp_InactivityTimer = NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->defaultDownlinkBWP_Id = NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig)); - NR_BWP_UplinkDedicated_t *initialUplinkBWP = calloc(1,sizeof(*initialUplinkBWP)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->initialUplinkBWP = initialUplinkBWP; - initialUplinkBWP->pucch_Config = NULL; - initialUplinkBWP->pusch_Config = calloc(1,sizeof(*initialUplinkBWP->pusch_Config)); - initialUplinkBWP->pusch_Config->present = NR_SetupRelease_PUSCH_Config_PR_setup; - NR_PUSCH_Config_t *pusch_Config = calloc(1,sizeof(*pusch_Config)); - initialUplinkBWP->pusch_Config->choice.setup = pusch_Config; - pusch_Config->txConfig=calloc(1,sizeof(*pusch_Config->txConfig)); - *pusch_Config->txConfig= NR_PUSCH_Config__txConfig_codebook; - pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA = NULL; - pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB = calloc(1,sizeof(*pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB)); - pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->present = NR_SetupRelease_DMRS_UplinkConfig_PR_setup; - pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup = calloc(1,sizeof(*pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup)); - NR_DMRS_UplinkConfig_t *NR_DMRS_UplinkConfig = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup; - NR_DMRS_UplinkConfig->dmrs_Type = NULL; - NR_DMRS_UplinkConfig->dmrs_AdditionalPosition =NR_DMRS_UplinkConfig__dmrs_AdditionalPosition_pos0; - NR_DMRS_UplinkConfig->phaseTrackingRS=NULL; - NR_DMRS_UplinkConfig->maxLength=NULL; - NR_DMRS_UplinkConfig->transformPrecodingDisabled = calloc(1,sizeof(*NR_DMRS_UplinkConfig->transformPrecodingDisabled)); - NR_DMRS_UplinkConfig->transformPrecodingDisabled->scramblingID0 = NULL; - NR_DMRS_UplinkConfig->transformPrecodingDisabled->scramblingID1 = NULL; - NR_DMRS_UplinkConfig->transformPrecodingEnabled = NULL; - pusch_Config->pusch_PowerControl = calloc(1,sizeof(*pusch_Config->pusch_PowerControl)); - pusch_Config->pusch_PowerControl->tpc_Accumulation = NULL; - pusch_Config->pusch_PowerControl->msg3_Alpha = calloc(1,sizeof(*pusch_Config->pusch_PowerControl->msg3_Alpha)); - *pusch_Config->pusch_PowerControl->msg3_Alpha = NR_Alpha_alpha1; - pusch_Config->pusch_PowerControl->p0_NominalWithoutGrant = NULL; - pusch_Config->pusch_PowerControl->p0_AlphaSets = calloc(1,sizeof(*pusch_Config->pusch_PowerControl->p0_AlphaSets)); - NR_P0_PUSCH_AlphaSet_t *aset = calloc(1,sizeof(*aset)); - aset->p0_PUSCH_AlphaSetId=0; - aset->p0=calloc(1,sizeof(*aset->p0)); - *aset->p0 = 0; - aset->alpha=calloc(1,sizeof(*aset->alpha)); - *aset->alpha=NR_Alpha_alpha1; - ASN_SEQUENCE_ADD(&pusch_Config->pusch_PowerControl->p0_AlphaSets->list,aset); - pusch_Config->pusch_PowerControl->pathlossReferenceRSToAddModList = calloc(1,sizeof(*pusch_Config->pusch_PowerControl->pathlossReferenceRSToAddModList)); - NR_PUSCH_PathlossReferenceRS_t *pl = calloc(1,sizeof(*pl)); - pl->pusch_PathlossReferenceRS_Id=0; - pl->referenceSignal.present = NR_PUSCH_PathlossReferenceRS__referenceSignal_PR_csi_RS_Index; - pl->referenceSignal.choice.csi_RS_Index=0; - ASN_SEQUENCE_ADD(&pusch_Config->pusch_PowerControl->pathlossReferenceRSToAddModList->list,pl); - pusch_Config->pusch_PowerControl->pathlossReferenceRSToReleaseList = NULL; - pusch_Config->pusch_PowerControl->twoPUSCH_PC_AdjustmentStates = NULL; - pusch_Config->pusch_PowerControl->deltaMCS = NULL; - pusch_Config->pusch_PowerControl->sri_PUSCH_MappingToAddModList = NULL; - pusch_Config->pusch_PowerControl->sri_PUSCH_MappingToReleaseList = NULL; - pusch_Config->frequencyHopping=NULL; - pusch_Config->frequencyHoppingOffsetLists=NULL; - pusch_Config->resourceAllocation = NR_PUSCH_Config__resourceAllocation_resourceAllocationType1; - pusch_Config->pusch_TimeDomainAllocationList = NULL; - pusch_Config->pusch_AggregationFactor=NULL; - pusch_Config->mcs_Table=NULL; - pusch_Config->mcs_TableTransformPrecoder=NULL; - pusch_Config->transformPrecoder=calloc(1,sizeof(*pusch_Config->transformPrecoder)); - *pusch_Config->transformPrecoder = NR_PUSCH_Config__transformPrecoder_disabled; - pusch_Config->codebookSubset=calloc(1,sizeof(*pusch_Config->codebookSubset)); - *pusch_Config->codebookSubset = NR_PUSCH_Config__codebookSubset_nonCoherent; - pusch_Config->maxRank=calloc(1,sizeof(*pusch_Config->maxRank)); - *pusch_Config->maxRank= 1; - pusch_Config->rbg_Size=NULL; - pusch_Config->uci_OnPUSCH=NULL; - pusch_Config->tp_pi2BPSK=NULL; - initialUplinkBWP->srs_Config = calloc(1,sizeof(*initialUplinkBWP->srs_Config)); - initialUplinkBWP->srs_Config->present = NR_SetupRelease_SRS_Config_PR_setup; - NR_SRS_Config_t *srs_Config = calloc(1,sizeof(*srs_Config)); - initialUplinkBWP->srs_Config->choice.setup=srs_Config; - srs_Config->srs_ResourceSetToReleaseList=NULL; - srs_Config->srs_ResourceSetToAddModList=calloc(1,sizeof(*srs_Config->srs_ResourceSetToAddModList)); - NR_SRS_ResourceSet_t *srs_resset0=calloc(1,sizeof(*srs_resset0)); - srs_resset0->srs_ResourceSetId = 0; - srs_resset0->srs_ResourceIdList=calloc(1,sizeof(*srs_resset0->srs_ResourceIdList)); - NR_SRS_ResourceId_t *srs_resset0_id=calloc(1,sizeof(*srs_resset0_id)); - *srs_resset0_id=0; - ASN_SEQUENCE_ADD(&srs_resset0->srs_ResourceIdList->list,srs_resset0_id); - srs_Config->srs_ResourceToReleaseList=NULL; - srs_resset0->resourceType.present = NR_SRS_ResourceSet__resourceType_PR_aperiodic; - srs_resset0->resourceType.choice.aperiodic = calloc(1,sizeof(*srs_resset0->resourceType.choice.aperiodic)); - srs_resset0->resourceType.choice.aperiodic->aperiodicSRS_ResourceTrigger=1; - srs_resset0->resourceType.choice.aperiodic->csi_RS=NULL; - srs_resset0->resourceType.choice.aperiodic->slotOffset= calloc(1,sizeof(*srs_resset0->resourceType.choice.aperiodic->slotOffset)); - *srs_resset0->resourceType.choice.aperiodic->slotOffset=2; - srs_resset0->resourceType.choice.aperiodic->ext1=NULL; - srs_resset0->usage=NR_SRS_ResourceSet__usage_codebook; - srs_resset0->alpha = calloc(1,sizeof(*srs_resset0->alpha)); - *srs_resset0->alpha = NR_Alpha_alpha1; - srs_resset0->p0=calloc(1,sizeof(*srs_resset0->p0)); - *srs_resset0->p0=-80; - srs_resset0->pathlossReferenceRS=NULL; - srs_resset0->srs_PowerControlAdjustmentStates=NULL; - ASN_SEQUENCE_ADD(&srs_Config->srs_ResourceSetToAddModList->list,srs_resset0); - srs_Config->srs_ResourceToReleaseList=NULL; - srs_Config->srs_ResourceToAddModList=calloc(1,sizeof(*srs_Config->srs_ResourceToAddModList)); - NR_SRS_Resource_t *srs_res0=calloc(1,sizeof(*srs_res0)); - srs_res0->srs_ResourceId=0; - srs_res0->nrofSRS_Ports=NR_SRS_Resource__nrofSRS_Ports_port1; - srs_res0->ptrs_PortIndex=NULL; - srs_res0->transmissionComb.present=NR_SRS_Resource__transmissionComb_PR_n2; - srs_res0->transmissionComb.choice.n2=calloc(1,sizeof(*srs_res0->transmissionComb.choice.n2)); - srs_res0->transmissionComb.choice.n2->combOffset_n2=0; - srs_res0->transmissionComb.choice.n2->cyclicShift_n2=0; - srs_res0->resourceMapping.startPosition=2; - srs_res0->resourceMapping.nrofSymbols=NR_SRS_Resource__resourceMapping__nrofSymbols_n1; - srs_res0->resourceMapping.repetitionFactor=NR_SRS_Resource__resourceMapping__repetitionFactor_n1; - srs_res0->freqDomainPosition=0; - srs_res0->freqDomainShift=0; - srs_res0->freqHopping.c_SRS = 61; - srs_res0->freqHopping.b_SRS=0; - srs_res0->freqHopping.b_hop=0; - srs_res0->groupOrSequenceHopping=NR_SRS_Resource__groupOrSequenceHopping_neither; - srs_res0->resourceType.present= NR_SRS_Resource__resourceType_PR_aperiodic; - srs_res0->resourceType.choice.aperiodic=calloc(1,sizeof(*srs_res0->resourceType.choice.aperiodic)); - srs_res0->sequenceId=40; - srs_res0->spatialRelationInfo=calloc(1,sizeof(*srs_res0->spatialRelationInfo)); - srs_res0->spatialRelationInfo->servingCellId=NULL; - srs_res0->spatialRelationInfo->referenceSignal.present=NR_SRS_SpatialRelationInfo__referenceSignal_PR_csi_RS_Index; - srs_res0->spatialRelationInfo->referenceSignal.choice.csi_RS_Index=0; - ASN_SEQUENCE_ADD(&srs_Config->srs_ResourceToAddModList->list,srs_res0); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToReleaseList = NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList = calloc(1, - sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList)); - NR_BWP_Uplink_t *ubwp = calloc(1,sizeof(*ubwp)); - ubwp->bwp_Id=1; - ubwp->bwp_Common = calloc(1,sizeof(*ubwp->bwp_Common)); - // copy bwp_Common from Initial UL BWP except for bandwidth - memcpy((void *)&ubwp->bwp_Common->genericParameters, - (void *)&servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->genericParameters, - sizeof(servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->genericParameters)); - ubwp->bwp_Common->genericParameters.locationAndBandwidth=PRBalloc_to_locationandbandwidth( - servingcellconfigcommon->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth,0); - ubwp->bwp_Common->rach_ConfigCommon = servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon; - ubwp->bwp_Common->pusch_ConfigCommon = servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon; - ubwp->bwp_Common->pucch_ConfigCommon = servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon; - ubwp->bwp_Dedicated = calloc(1,sizeof(*ubwp->bwp_Dedicated)); - ubwp->bwp_Dedicated->pucch_Config = calloc(1,sizeof(*ubwp->bwp_Dedicated->pucch_Config)); - ubwp->bwp_Dedicated->pucch_Config->present = NR_SetupRelease_PUCCH_Config_PR_setup; - NR_PUCCH_Config_t *pucch_Config = calloc(1,sizeof(*pucch_Config)); - ubwp->bwp_Dedicated->pucch_Config->choice.setup=pucch_Config; - pucch_Config->resourceSetToAddModList = calloc(1,sizeof(*pucch_Config->resourceSetToAddModList)); - pucch_Config->resourceSetToReleaseList = NULL; - NR_PUCCH_ResourceSet_t *pucchresset0=calloc(1,sizeof(*pucchresset0)); - NR_PUCCH_ResourceSet_t *pucchresset1=calloc(1,sizeof(*pucchresset1)); - pucchresset0->pucch_ResourceSetId = 0; - NR_PUCCH_ResourceId_t *pucchresset0id0=calloc(1,sizeof(*pucchresset0id0)); - NR_PUCCH_ResourceId_t *pucchresset0id1=calloc(1,sizeof(*pucchresset0id1)); - *pucchresset0id0=1; - ASN_SEQUENCE_ADD(&pucchresset0->resourceList.list,pucchresset0id0); - *pucchresset0id1=2; - ASN_SEQUENCE_ADD(&pucchresset0->resourceList.list,pucchresset0id1); - pucchresset0->maxPayloadMinus1=NULL; - ASN_SEQUENCE_ADD(&pucch_Config->resourceSetToAddModList->list,pucchresset0); - pucchresset1->pucch_ResourceSetId = 1; - NR_PUCCH_ResourceId_t *pucchresset1id0=calloc(1,sizeof(*pucchresset1id0)); - NR_PUCCH_ResourceId_t *pucchresset1id1=calloc(1,sizeof(*pucchresset1id1)); - *pucchresset1id0=3; - ASN_SEQUENCE_ADD(&pucchresset1->resourceList.list,pucchresset1id0); - *pucchresset1id1=4; - ASN_SEQUENCE_ADD(&pucchresset1->resourceList.list,pucchresset1id1); - pucchresset1->maxPayloadMinus1=NULL; - ASN_SEQUENCE_ADD(&pucch_Config->resourceSetToAddModList->list,pucchresset1); - pucch_Config->resourceToAddModList = calloc(1,sizeof(*pucch_Config->resourceToAddModList)); - pucch_Config->resourceToReleaseList = NULL; - NR_PUCCH_Resource_t *pucchres0=calloc(1,sizeof(*pucchres0)); - NR_PUCCH_Resource_t *pucchres1=calloc(1,sizeof(*pucchres1)); - NR_PUCCH_Resource_t *pucchres2=calloc(1,sizeof(*pucchres2)); - NR_PUCCH_Resource_t *pucchres3=calloc(1,sizeof(*pucchres3)); - pucchres0->pucch_ResourceId=1; - pucchres0->startingPRB=48; - pucchres0->intraSlotFrequencyHopping=NULL; - pucchres0->secondHopPRB=NULL; - pucchres0->format.present= NR_PUCCH_Resource__format_PR_format0; - pucchres0->format.choice.format0=calloc(1,sizeof(*pucchres0->format.choice.format0)); - pucchres0->format.choice.format0->initialCyclicShift=0; - pucchres0->format.choice.format0->nrofSymbols=1; - pucchres0->format.choice.format0->startingSymbolIndex=13; - ASN_SEQUENCE_ADD(&pucch_Config->resourceToAddModList->list,pucchres0); - pucchres1->pucch_ResourceId=2; - pucchres1->startingPRB=48; - pucchres1->intraSlotFrequencyHopping=NULL; - pucchres1->secondHopPRB=NULL; - pucchres1->format.present= NR_PUCCH_Resource__format_PR_format0; - pucchres1->format.choice.format0=calloc(1,sizeof(*pucchres1->format.choice.format0)); - pucchres1->format.choice.format0->initialCyclicShift=0; - pucchres1->format.choice.format0->nrofSymbols=1; - pucchres1->format.choice.format0->startingSymbolIndex=12; - ASN_SEQUENCE_ADD(&pucch_Config->resourceToAddModList->list,pucchres1); - pucchres2->pucch_ResourceId=3; - pucchres2->startingPRB=40; - pucchres2->intraSlotFrequencyHopping=NULL; - pucchres2->secondHopPRB=NULL; - pucchres2->format.present= NR_PUCCH_Resource__format_PR_format2; - pucchres2->format.choice.format2=calloc(1,sizeof(*pucchres2->format.choice.format2)); - pucchres2->format.choice.format2->nrofPRBs=16; - pucchres2->format.choice.format2->nrofSymbols=1; - pucchres2->format.choice.format2->startingSymbolIndex=13; - ASN_SEQUENCE_ADD(&pucch_Config->resourceToAddModList->list,pucchres2); - pucchres3->pucch_ResourceId=4; - pucchres3->startingPRB=40; - pucchres3->intraSlotFrequencyHopping=NULL; - pucchres3->secondHopPRB=NULL; - pucchres3->format.present= NR_PUCCH_Resource__format_PR_format2; - pucchres3->format.choice.format2=calloc(1,sizeof(*pucchres3->format.choice.format2)); - pucchres3->format.choice.format2->nrofPRBs=16; - pucchres3->format.choice.format2->nrofSymbols=1; - pucchres3->format.choice.format2->startingSymbolIndex=12; - ASN_SEQUENCE_ADD(&pucch_Config->resourceToAddModList->list,pucchres3); - pucch_Config->format2=calloc(1,sizeof(*pucch_Config->format2)); - pucch_Config->format2->present=NR_SetupRelease_PUCCH_FormatConfig_PR_setup; - NR_PUCCH_FormatConfig_t *pucchfmt2 = calloc(1,sizeof(*pucchfmt2)); - pucch_Config->format2->choice.setup = pucchfmt2; - pucchfmt2->interslotFrequencyHopping=NULL; - pucchfmt2->additionalDMRS=NULL; - pucchfmt2->maxCodeRate=calloc(1,sizeof(*pucchfmt2->maxCodeRate)); - *pucchfmt2->maxCodeRate=NR_PUCCH_MaxCodeRate_zeroDot15; - pucchfmt2->nrofSlots=NULL; - pucchfmt2->pi2BPSK=NULL; - pucchfmt2->simultaneousHARQ_ACK_CSI=NULL; - pucch_Config->schedulingRequestResourceToAddModList=NULL; - pucch_Config->schedulingRequestResourceToReleaseList=NULL; - pucch_Config->multi_CSI_PUCCH_ResourceList=NULL; - pucch_Config->dl_DataToUL_ACK = calloc(1,sizeof(*pucch_Config->dl_DataToUL_ACK)); - long *delay[8]; - - for (int i=0; i<8; i++) { - delay[i] = calloc(1,sizeof(*delay[i])); - *delay[i] = (i<6) ? (i+2) : 0; - ASN_SEQUENCE_ADD(&pucch_Config->dl_DataToUL_ACK->list,delay[i]); - } - - pucch_Config->spatialRelationInfoToAddModList = calloc(1,sizeof(*pucch_Config->spatialRelationInfoToAddModList)); - NR_PUCCH_SpatialRelationInfo_t *pucchspatial = calloc(1,sizeof(*pucchspatial)); - pucchspatial->pucch_SpatialRelationInfoId = 1; - pucchspatial->servingCellId = NULL; - pucchspatial->referenceSignal.present = NR_PUCCH_SpatialRelationInfo__referenceSignal_PR_csi_RS_Index; - pucchspatial->referenceSignal.choice.csi_RS_Index = 0; - pucchspatial->pucch_PathlossReferenceRS_Id = 0; - pucchspatial->p0_PUCCH_Id = 1; - pucchspatial->closedLoopIndex = NR_PUCCH_SpatialRelationInfo__closedLoopIndex_i0; - ASN_SEQUENCE_ADD(&pucch_Config->spatialRelationInfoToAddModList->list,pucchspatial); - pucch_Config->spatialRelationInfoToReleaseList=NULL; - pucch_Config->pucch_PowerControl=calloc(1,sizeof(*pucch_Config->pucch_PowerControl)); - pucch_Config->pucch_PowerControl->deltaF_PUCCH_f0 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f0)); - *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f0 = 0; - pucch_Config->pucch_PowerControl->deltaF_PUCCH_f1 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f1)); - *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f1 = 0; - pucch_Config->pucch_PowerControl->deltaF_PUCCH_f2 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f2)); - *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f2 = 0; - pucch_Config->pucch_PowerControl->deltaF_PUCCH_f3 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f3)); - *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f3 = 0; - pucch_Config->pucch_PowerControl->deltaF_PUCCH_f4 = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->deltaF_PUCCH_f4)); - *pucch_Config->pucch_PowerControl->deltaF_PUCCH_f4 = 0; - pucch_Config->pucch_PowerControl->p0_Set = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->p0_Set)); - NR_P0_PUCCH_t *p00 = calloc(1,sizeof(*p00)); - p00->p0_PUCCH_Id=1; - p00->p0_PUCCH_Value = 0; - ASN_SEQUENCE_ADD(&pucch_Config->pucch_PowerControl->p0_Set->list,p00); - pucch_Config->pucch_PowerControl->pathlossReferenceRSs = calloc(1,sizeof(*pucch_Config->pucch_PowerControl->pathlossReferenceRSs)); - NR_PUCCH_PathlossReferenceRS_t *pucchPLRef=calloc(1,sizeof(*pucchPLRef)); - pucchPLRef->pucch_PathlossReferenceRS_Id=0; - pucchPLRef->referenceSignal.present = NR_PUCCH_PathlossReferenceRS__referenceSignal_PR_csi_RS_Index; - pucchPLRef->referenceSignal.choice.csi_RS_Index=0; - ASN_SEQUENCE_ADD(&pucch_Config->pucch_PowerControl->pathlossReferenceRSs->list,pucchPLRef); - // copy pusch_Config from dedicated initialBWP - ubwp->bwp_Dedicated->pusch_Config = calloc(1,sizeof(*ubwp->bwp_Dedicated->pusch_Config)); - ubwp->bwp_Dedicated->pusch_Config->present = NR_SetupRelease_PUSCH_Config_PR_setup; - ubwp->bwp_Dedicated->pusch_Config->choice.setup = pusch_Config; - ubwp->bwp_Dedicated->configuredGrantConfig = NULL; - ubwp->bwp_Dedicated->srs_Config = calloc(1,sizeof(*ubwp->bwp_Dedicated->srs_Config)); - ubwp->bwp_Dedicated->srs_Config->present = NR_SetupRelease_SRS_Config_PR_setup; - ubwp->bwp_Dedicated->srs_Config->choice.setup = srs_Config; - ubwp->bwp_Dedicated->beamFailureRecoveryConfig = NULL; - ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list,ubwp); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id = calloc(1, - sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id)); - *secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id = 1; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig = NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->carrierSwitching = NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->supplementaryUplink=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdcch_ServingCellConfig=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig)); - NR_PDSCH_ServingCellConfig_t *pdsch_servingcellconfig = calloc(1,sizeof(*pdsch_servingcellconfig)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->present = NR_SetupRelease_PDSCH_ServingCellConfig_PR_setup; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup = pdsch_servingcellconfig; - pdsch_servingcellconfig->codeBlockGroupTransmission = NULL; - pdsch_servingcellconfig->xOverhead = NULL; - pdsch_servingcellconfig->nrofHARQ_ProcessesForPDSCH = NULL; - pdsch_servingcellconfig->pucch_Cell= NULL; - pdsch_servingcellconfig->ext1=calloc(1,sizeof(*pdsch_servingcellconfig->ext1)); - pdsch_servingcellconfig->ext1->maxMIMO_Layers = calloc(1,sizeof(*pdsch_servingcellconfig->ext1->maxMIMO_Layers)); - *pdsch_servingcellconfig->ext1->maxMIMO_Layers = 2; - pdsch_servingcellconfig->ext1->processingType2Enabled = NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->present = NR_SetupRelease_CSI_MeasConfig_PR_setup; - NR_CSI_MeasConfig_t *csi_MeasConfig = calloc(1,sizeof(*csi_MeasConfig)); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup = csi_MeasConfig; - csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList = calloc(1,sizeof(*csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList)); - NR_NZP_CSI_RS_Resource_t *nzpres0 = calloc(1,sizeof(*nzpres0)); - nzpres0->nzp_CSI_RS_ResourceId=0; - nzpres0->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_other; - nzpres0->resourceMapping.frequencyDomainAllocation.choice.other.buf = calloc(1,1); - nzpres0->resourceMapping.frequencyDomainAllocation.choice.other.size = 1; - nzpres0->resourceMapping.frequencyDomainAllocation.choice.other.bits_unused = 2; - nzpres0->resourceMapping.frequencyDomainAllocation.choice.other.buf[0]=1<<2; - nzpres0->resourceMapping.nrofPorts = (n_physical_antenna_ports==1)? NR_CSI_RS_ResourceMapping__nrofPorts_p1 : NR_CSI_RS_ResourceMapping__nrofPorts_p2; - nzpres0->resourceMapping.firstOFDMSymbolInTimeDomain=7; - nzpres0->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres0->resourceMapping.cdm_Type = (n_physical_antenna_ports==1)? NR_CSI_RS_ResourceMapping__cdm_Type_noCDM : NR_CSI_RS_ResourceMapping__cdm_Type_fd_CDM2; - nzpres0->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_one; - nzpres0->resourceMapping.density.choice.one=(NULL_t)0; - nzpres0->resourceMapping.freqBand.startingRB=0; - nzpres0->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres0->powerControlOffset=13; - nzpres0->powerControlOffsetSS=NULL; - nzpres0->scramblingID=40; - nzpres0->periodicityAndOffset = calloc(1,sizeof(*nzpres0->periodicityAndOffset)); - nzpres0->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots320; - nzpres0->periodicityAndOffset->choice.slots320 = 2; - nzpres0->qcl_InfoPeriodicCSI_RS=NULL; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres0); - - if (n_physical_antenna_ports > 1) { - NR_NZP_CSI_RS_Resource_t *nzpres2 = calloc(1,sizeof(*nzpres2)); - nzpres2->nzp_CSI_RS_ResourceId=2; - nzpres2->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres2->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres2->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres2->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres2->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=1; - nzpres2->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres2->resourceMapping.firstOFDMSymbolInTimeDomain=4; - nzpres2->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres2->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres2->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres2->resourceMapping.density.choice.three=(NULL_t)0; - nzpres2->resourceMapping.freqBand.startingRB=0; - nzpres2->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres2->powerControlOffset=0; - nzpres2->powerControlOffsetSS=calloc(1,sizeof(*nzpres2->powerControlOffsetSS)); - *nzpres2->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres2->scramblingID=40; - nzpres2->periodicityAndOffset = calloc(1,sizeof(*nzpres2->periodicityAndOffset)); - nzpres2->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres2->periodicityAndOffset->choice.slots160 = 25; - nzpres2->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres2->qcl_InfoPeriodicCSI_RS)); - *nzpres2->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres2); - NR_NZP_CSI_RS_Resource_t *nzpres3 = calloc(1,sizeof(*nzpres3)); - nzpres3->nzp_CSI_RS_ResourceId=3; - nzpres3->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres3->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres3->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres3->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres3->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=1; - nzpres3->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres3->resourceMapping.firstOFDMSymbolInTimeDomain=8; - nzpres3->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres3->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres3->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres3->resourceMapping.density.choice.three=(NULL_t)0; - nzpres3->resourceMapping.freqBand.startingRB=0; - nzpres3->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres3->powerControlOffset=0; - nzpres3->powerControlOffsetSS=calloc(1,sizeof(*nzpres3->powerControlOffsetSS)); - *nzpres3->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres3->scramblingID=40; - nzpres3->periodicityAndOffset = calloc(1,sizeof(*nzpres3->periodicityAndOffset)); - nzpres3->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres3->periodicityAndOffset->choice.slots160 = 25; - nzpres3->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres3->qcl_InfoPeriodicCSI_RS)); - *nzpres3->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres3); - } - - if (n_physical_antenna_ports > 3) { - NR_NZP_CSI_RS_Resource_t *nzpres4 = calloc(1,sizeof(*nzpres4)); - nzpres4->nzp_CSI_RS_ResourceId=4; - nzpres4->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres4->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres4->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres4->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres4->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=1; - nzpres4->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres4->resourceMapping.firstOFDMSymbolInTimeDomain=4; - nzpres4->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres4->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres4->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres4->resourceMapping.density.choice.three=(NULL_t)0; - nzpres4->resourceMapping.freqBand.startingRB=0; - nzpres4->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres4->powerControlOffset=0; - nzpres4->powerControlOffsetSS=calloc(1,sizeof(*nzpres4->powerControlOffsetSS)); - *nzpres4->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres4->scramblingID=40; - nzpres4->periodicityAndOffset = calloc(1,sizeof(*nzpres4->periodicityAndOffset)); - nzpres4->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres4->periodicityAndOffset->choice.slots160 = 26; - nzpres4->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres4->qcl_InfoPeriodicCSI_RS)); - *nzpres4->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres4); - NR_NZP_CSI_RS_Resource_t *nzpres5 = calloc(1,sizeof(*nzpres5)); - nzpres5->nzp_CSI_RS_ResourceId=5; - nzpres5->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres5->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres5->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres5->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres5->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=1; - nzpres5->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres5->resourceMapping.firstOFDMSymbolInTimeDomain=8; - nzpres5->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres5->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres5->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres5->resourceMapping.density.choice.three=(NULL_t)0; - nzpres5->resourceMapping.freqBand.startingRB=0; - nzpres5->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres5->powerControlOffset=0; - nzpres5->powerControlOffsetSS=calloc(1,sizeof(*nzpres5->powerControlOffsetSS)); - *nzpres5->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres5->scramblingID=40; - nzpres5->periodicityAndOffset = calloc(1,sizeof(*nzpres5->periodicityAndOffset)); - nzpres5->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres5->periodicityAndOffset->choice.slots160 = 26; - nzpres5->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres5->qcl_InfoPeriodicCSI_RS)); - *nzpres5->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres5); - } - - if (n_physical_antenna_ports > 7) { - NR_NZP_CSI_RS_Resource_t *nzpres6 = calloc(1,sizeof(*nzpres6)); - nzpres6->nzp_CSI_RS_ResourceId=6; - nzpres6->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres6->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres6->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres6->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres6->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=4; - nzpres6->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres6->resourceMapping.firstOFDMSymbolInTimeDomain=4; - nzpres6->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres6->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres6->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres6->resourceMapping.density.choice.three=(NULL_t)0; - nzpres6->resourceMapping.freqBand.startingRB=0; - nzpres6->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres6->powerControlOffset=0; - nzpres6->powerControlOffsetSS=calloc(1,sizeof(*nzpres6->powerControlOffsetSS)); - *nzpres6->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres6->scramblingID=40; - nzpres6->periodicityAndOffset = calloc(1,sizeof(*nzpres6->periodicityAndOffset)); - nzpres6->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres6->periodicityAndOffset->choice.slots160 = 25; - nzpres6->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres6->qcl_InfoPeriodicCSI_RS)); - *nzpres6->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres6); - NR_NZP_CSI_RS_Resource_t *nzpres7 = calloc(1,sizeof(*nzpres7)); - nzpres7->nzp_CSI_RS_ResourceId=7; - nzpres7->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres7->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres7->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres7->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres7->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=4; - nzpres7->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres7->resourceMapping.firstOFDMSymbolInTimeDomain=8; - nzpres7->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres7->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres7->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres7->resourceMapping.density.choice.three=(NULL_t)0; - nzpres7->resourceMapping.freqBand.startingRB=0; - nzpres7->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres7->powerControlOffset=0; - nzpres7->powerControlOffsetSS=calloc(1,sizeof(*nzpres7->powerControlOffsetSS)); - *nzpres7->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres7->scramblingID=40; - nzpres7->periodicityAndOffset = calloc(1,sizeof(*nzpres7->periodicityAndOffset)); - nzpres7->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres7->periodicityAndOffset->choice.slots160 = 25; - nzpres7->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres7->qcl_InfoPeriodicCSI_RS)); - *nzpres7->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres7); - NR_NZP_CSI_RS_Resource_t *nzpres8 = calloc(1,sizeof(*nzpres8)); - nzpres8->nzp_CSI_RS_ResourceId=8; - nzpres8->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres8->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres8->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres8->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres8->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=4; - nzpres8->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres8->resourceMapping.firstOFDMSymbolInTimeDomain=4; - nzpres8->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres8->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres8->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres8->resourceMapping.density.choice.three=(NULL_t)0; - nzpres8->resourceMapping.freqBand.startingRB=0; - nzpres8->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres8->powerControlOffset=0; - nzpres8->powerControlOffsetSS=calloc(1,sizeof(*nzpres8->powerControlOffsetSS)); - *nzpres8->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres8->scramblingID=40; - nzpres8->periodicityAndOffset = calloc(1,sizeof(*nzpres8->periodicityAndOffset)); - nzpres8->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres8->periodicityAndOffset->choice.slots160 = 26; - nzpres8->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres8->qcl_InfoPeriodicCSI_RS)); - *nzpres8->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres8); - NR_NZP_CSI_RS_Resource_t *nzpres9 = calloc(1,sizeof(*nzpres9)); - nzpres9->nzp_CSI_RS_ResourceId=9; - nzpres9->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres9->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres9->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres9->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres9->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=4; - nzpres9->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres9->resourceMapping.firstOFDMSymbolInTimeDomain=8; - nzpres9->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres9->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres9->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres9->resourceMapping.density.choice.three=(NULL_t)0; - nzpres9->resourceMapping.freqBand.startingRB=0; - nzpres9->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres9->powerControlOffset=0; - nzpres9->powerControlOffsetSS=calloc(1,sizeof(*nzpres9->powerControlOffsetSS)); - *nzpres9->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres9->scramblingID=40; - nzpres9->periodicityAndOffset = calloc(1,sizeof(*nzpres9->periodicityAndOffset)); - nzpres9->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres9->periodicityAndOffset->choice.slots160 = 26; - nzpres9->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres9->qcl_InfoPeriodicCSI_RS)); - *nzpres9->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres9); - } - - if (n_physical_antenna_ports > 15) { - NR_NZP_CSI_RS_Resource_t *nzpres10 = calloc(1,sizeof(*nzpres10)); - nzpres10->nzp_CSI_RS_ResourceId=10; - nzpres10->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres10->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres10->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres10->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres10->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=2; - nzpres10->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres10->resourceMapping.firstOFDMSymbolInTimeDomain=4; - nzpres10->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres10->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres10->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres10->resourceMapping.density.choice.three=(NULL_t)0; - nzpres10->resourceMapping.freqBand.startingRB=0; - nzpres10->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres10->powerControlOffset=0; - nzpres10->powerControlOffsetSS=calloc(1,sizeof(*nzpres10->powerControlOffsetSS)); - *nzpres10->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres10->scramblingID=40; - nzpres10->periodicityAndOffset = calloc(1,sizeof(*nzpres10->periodicityAndOffset)); - nzpres10->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres10->periodicityAndOffset->choice.slots160 = 25; - nzpres10->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres10->qcl_InfoPeriodicCSI_RS)); - *nzpres10->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres10); - NR_NZP_CSI_RS_Resource_t *nzpres11 = calloc(1,sizeof(*nzpres11)); - nzpres11->nzp_CSI_RS_ResourceId=11; - nzpres11->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres11->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres11->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres11->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres11->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=2; - nzpres11->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres11->resourceMapping.firstOFDMSymbolInTimeDomain=8; - nzpres11->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres11->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres11->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres11->resourceMapping.density.choice.three=(NULL_t)0; - nzpres11->resourceMapping.freqBand.startingRB=0; - nzpres11->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres11->powerControlOffset=0; - nzpres11->powerControlOffsetSS=calloc(1,sizeof(*nzpres11->powerControlOffsetSS)); - *nzpres11->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres11->scramblingID=40; - nzpres11->periodicityAndOffset = calloc(1,sizeof(*nzpres11->periodicityAndOffset)); - nzpres11->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres11->periodicityAndOffset->choice.slots160 = 25; - nzpres11->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres11->qcl_InfoPeriodicCSI_RS)); - *nzpres11->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres11); - NR_NZP_CSI_RS_Resource_t *nzpres12 = calloc(1,sizeof(*nzpres12)); - nzpres12->nzp_CSI_RS_ResourceId=12; - nzpres12->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres12->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres12->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres12->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres12->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=2; - nzpres12->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres12->resourceMapping.firstOFDMSymbolInTimeDomain=4; - nzpres12->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres12->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres12->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres12->resourceMapping.density.choice.three=(NULL_t)0; - nzpres12->resourceMapping.freqBand.startingRB=0; - nzpres12->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres12->powerControlOffset=0; - nzpres12->powerControlOffsetSS=calloc(1,sizeof(*nzpres12->powerControlOffsetSS)); - *nzpres12->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres12->scramblingID=40; - nzpres12->periodicityAndOffset = calloc(1,sizeof(*nzpres12->periodicityAndOffset)); - nzpres12->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres12->periodicityAndOffset->choice.slots160 = 26; - nzpres12->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres12->qcl_InfoPeriodicCSI_RS)); - *nzpres12->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres12); - NR_NZP_CSI_RS_Resource_t *nzpres13 = calloc(1,sizeof(*nzpres13)); - nzpres13->nzp_CSI_RS_ResourceId=13; - nzpres13->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres13->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres13->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres13->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres13->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=2; - nzpres13->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres13->resourceMapping.firstOFDMSymbolInTimeDomain=8; - nzpres13->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres13->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres13->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres13->resourceMapping.density.choice.three=(NULL_t)0; - nzpres13->resourceMapping.freqBand.startingRB=0; - nzpres13->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres13->powerControlOffset=0; - nzpres13->powerControlOffsetSS=calloc(1,sizeof(*nzpres13->powerControlOffsetSS)); - *nzpres13->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres13->scramblingID=40; - nzpres13->periodicityAndOffset = calloc(1,sizeof(*nzpres13->periodicityAndOffset)); - nzpres13->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres13->periodicityAndOffset->choice.slots160 = 26; - nzpres13->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres13->qcl_InfoPeriodicCSI_RS)); - *nzpres13->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres13); - NR_NZP_CSI_RS_Resource_t *nzpres14 = calloc(1,sizeof(*nzpres14)); - nzpres14->nzp_CSI_RS_ResourceId=14; - nzpres14->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres14->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres14->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres14->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres14->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=8; - nzpres14->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres14->resourceMapping.firstOFDMSymbolInTimeDomain=4; - nzpres14->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres14->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres14->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres14->resourceMapping.density.choice.three=(NULL_t)0; - nzpres14->resourceMapping.freqBand.startingRB=0; - nzpres14->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres14->powerControlOffset=0; - nzpres14->powerControlOffsetSS=calloc(1,sizeof(*nzpres14->powerControlOffsetSS)); - *nzpres14->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres14->scramblingID=40; - nzpres14->periodicityAndOffset = calloc(1,sizeof(*nzpres14->periodicityAndOffset)); - nzpres14->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres14->periodicityAndOffset->choice.slots160 = 25; - nzpres14->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres14->qcl_InfoPeriodicCSI_RS)); - *nzpres14->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres14); - NR_NZP_CSI_RS_Resource_t *nzpres15 = calloc(1,sizeof(*nzpres15)); - nzpres15->nzp_CSI_RS_ResourceId=15; - nzpres15->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres15->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres15->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres15->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres15->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=8; - nzpres15->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres15->resourceMapping.firstOFDMSymbolInTimeDomain=8; - nzpres15->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres15->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres15->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres15->resourceMapping.density.choice.three=(NULL_t)0; - nzpres15->resourceMapping.freqBand.startingRB=0; - nzpres15->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres15->powerControlOffset=0; - nzpres15->powerControlOffsetSS=calloc(1,sizeof(*nzpres15->powerControlOffsetSS)); - *nzpres15->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres15->scramblingID=40; - nzpres15->periodicityAndOffset = calloc(1,sizeof(*nzpres15->periodicityAndOffset)); - nzpres15->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres15->periodicityAndOffset->choice.slots160 = 25; - nzpres15->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres15->qcl_InfoPeriodicCSI_RS)); - *nzpres15->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres15); - NR_NZP_CSI_RS_Resource_t *nzpres16 = calloc(1,sizeof(*nzpres16)); - nzpres16->nzp_CSI_RS_ResourceId=16; - nzpres16->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres16->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres16->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres16->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres16->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=8; - nzpres16->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres16->resourceMapping.firstOFDMSymbolInTimeDomain=5; - nzpres16->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres16->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres16->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres16->resourceMapping.density.choice.three=(NULL_t)0; - nzpres16->resourceMapping.freqBand.startingRB=0; - nzpres16->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres16->powerControlOffset=0; - nzpres16->powerControlOffsetSS=calloc(1,sizeof(*nzpres16->powerControlOffsetSS)); - *nzpres16->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres16->scramblingID=40; - nzpres16->periodicityAndOffset = calloc(1,sizeof(*nzpres16->periodicityAndOffset)); - nzpres16->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres16->periodicityAndOffset->choice.slots160 = 26; - nzpres16->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres16->qcl_InfoPeriodicCSI_RS)); - *nzpres16->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres16); - NR_NZP_CSI_RS_Resource_t *nzpres17 = calloc(1,sizeof(*nzpres17)); - nzpres17->nzp_CSI_RS_ResourceId=9; - nzpres17->resourceMapping.frequencyDomainAllocation.present = NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row1; - nzpres17->resourceMapping.frequencyDomainAllocation.choice.row1.buf = calloc(1,1); - nzpres17->resourceMapping.frequencyDomainAllocation.choice.row1.size = 1; - nzpres17->resourceMapping.frequencyDomainAllocation.choice.row1.bits_unused = 4; - nzpres17->resourceMapping.frequencyDomainAllocation.choice.row1.buf[0]=8; - nzpres17->resourceMapping.nrofPorts = NR_CSI_RS_ResourceMapping__nrofPorts_p1; - nzpres17->resourceMapping.firstOFDMSymbolInTimeDomain=9; - nzpres17->resourceMapping.firstOFDMSymbolInTimeDomain2=NULL; - nzpres17->resourceMapping.cdm_Type = NR_CSI_RS_ResourceMapping__cdm_Type_noCDM; - nzpres17->resourceMapping.density.present=NR_CSI_RS_ResourceMapping__density_PR_three; - nzpres17->resourceMapping.density.choice.three=(NULL_t)0; - nzpres17->resourceMapping.freqBand.startingRB=0; - nzpres17->resourceMapping.freqBand.nrofRBs= servingcellconfigcommon->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - nzpres17->powerControlOffset=0; - nzpres17->powerControlOffsetSS=calloc(1,sizeof(*nzpres17->powerControlOffsetSS)); - *nzpres17->powerControlOffsetSS=NR_NZP_CSI_RS_Resource__powerControlOffsetSS_db0; - nzpres17->scramblingID=40; - nzpres17->periodicityAndOffset = calloc(1,sizeof(*nzpres17->periodicityAndOffset)); - nzpres17->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots160; - nzpres17->periodicityAndOffset->choice.slots160 = 26; - nzpres17->qcl_InfoPeriodicCSI_RS=calloc(1,sizeof(*nzpres17->qcl_InfoPeriodicCSI_RS)); - *nzpres17->qcl_InfoPeriodicCSI_RS=8; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList->list,nzpres17); - } - - if (n_physical_antenna_ports > 16) AssertFatal(1==0,"Fill in for more than 16 antenna elements\n"); - - csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList = calloc(1,sizeof(*csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList)); - csi_MeasConfig->nzp_CSI_RS_ResourceSetToReleaseList = NULL; - NR_NZP_CSI_RS_ResourceSet_t *nzpresset0=calloc(1,sizeof(*nzpresset0)); - nzpresset0->nzp_CSI_ResourceSetId=0; - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset00=calloc(1,sizeof(*nzpresset00)); - *nzpresset00=0; - ASN_SEQUENCE_ADD(&nzpresset0->nzp_CSI_RS_Resources.list,nzpresset00); - nzpresset0->repetition=NULL; - nzpresset0->aperiodicTriggeringOffset=NULL; - nzpresset0->trs_Info=NULL; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset0); - - if (n_physical_antenna_ports > 1) { - NR_NZP_CSI_RS_ResourceSet_t *nzpresset3=calloc(1,sizeof(*nzpresset3)); - nzpresset3->nzp_CSI_ResourceSetId=3; - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset30=calloc(1,sizeof(*nzpresset30)); - *nzpresset30=2; - ASN_SEQUENCE_ADD(&nzpresset3->nzp_CSI_RS_Resources.list,nzpresset30); - - if (n_physical_antenna_ports > 3) { - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset31=calloc(1,sizeof(*nzpresset31)); - *nzpresset31=3; - ASN_SEQUENCE_ADD(&nzpresset3->nzp_CSI_RS_Resources.list,nzpresset31); - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset32=calloc(1,sizeof(*nzpresset32)); - *nzpresset32=4; - ASN_SEQUENCE_ADD(&nzpresset3->nzp_CSI_RS_Resources.list,nzpresset32); - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset33=calloc(1,sizeof(*nzpresset33)); - *nzpresset33=5; - ASN_SEQUENCE_ADD(&nzpresset3->nzp_CSI_RS_Resources.list,nzpresset33); - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset3); - } - - nzpresset3->repetition=calloc(1,sizeof(*nzpresset3->repetition)); - *nzpresset3->repetition=NR_NZP_CSI_RS_ResourceSet__repetition_off; - nzpresset3->aperiodicTriggeringOffset=NULL; - nzpresset3->trs_Info=calloc(1,sizeof(*nzpresset3->trs_Info)); - *nzpresset3->trs_Info=NR_NZP_CSI_RS_ResourceSet__trs_Info_true; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset3); - } - - if (n_physical_antenna_ports > 7) { - NR_NZP_CSI_RS_ResourceSet_t *nzpresset4=calloc(1,sizeof(*nzpresset4)); - nzpresset4->nzp_CSI_ResourceSetId=4; - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset40=calloc(1,sizeof(*nzpresset40)); - *nzpresset40=6; - ASN_SEQUENCE_ADD(&nzpresset4->nzp_CSI_RS_Resources.list,nzpresset40); - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset41=calloc(1,sizeof(*nzpresset41)); - *nzpresset41=7; - ASN_SEQUENCE_ADD(&nzpresset4->nzp_CSI_RS_Resources.list,nzpresset41); - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset42=calloc(1,sizeof(*nzpresset42)); - *nzpresset42=8; - ASN_SEQUENCE_ADD(&nzpresset4->nzp_CSI_RS_Resources.list,nzpresset42); - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset43=calloc(1,sizeof(*nzpresset43)); - *nzpresset43=9; - ASN_SEQUENCE_ADD(&nzpresset4->nzp_CSI_RS_Resources.list,nzpresset43); - nzpresset4->repetition=calloc(1,sizeof(*nzpresset4->repetition)); - *nzpresset4->repetition=NR_NZP_CSI_RS_ResourceSet__repetition_off; - nzpresset4->aperiodicTriggeringOffset=NULL; - nzpresset4->trs_Info=calloc(1,sizeof(*nzpresset4->trs_Info)); - *nzpresset4->trs_Info=NR_NZP_CSI_RS_ResourceSet__trs_Info_true; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset4); - } - - if (n_physical_antenna_ports > 15) { - NR_NZP_CSI_RS_ResourceSet_t *nzpresset5=calloc(1,sizeof(*nzpresset5)); - nzpresset5->nzp_CSI_ResourceSetId=5; - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset50=calloc(1,sizeof(*nzpresset50)); - *nzpresset50=10; - ASN_SEQUENCE_ADD(&nzpresset5->nzp_CSI_RS_Resources.list,nzpresset50); - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset51=calloc(1,sizeof(*nzpresset51)); - *nzpresset51=11; - ASN_SEQUENCE_ADD(&nzpresset5->nzp_CSI_RS_Resources.list,nzpresset51); - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset52=calloc(1,sizeof(*nzpresset52)); - *nzpresset52=12; - ASN_SEQUENCE_ADD(&nzpresset5->nzp_CSI_RS_Resources.list,nzpresset52); - NR_NZP_CSI_RS_ResourceSetId_t *nzpresset53=calloc(1,sizeof(*nzpresset53)); - *nzpresset53=13; - ASN_SEQUENCE_ADD(&nzpresset5->nzp_CSI_RS_Resources.list,nzpresset53); - nzpresset5->repetition=calloc(1,sizeof(*nzpresset5->repetition)); - *nzpresset5->repetition=NR_NZP_CSI_RS_ResourceSet__repetition_off; - nzpresset5->aperiodicTriggeringOffset=NULL; - nzpresset5->trs_Info=calloc(1,sizeof(*nzpresset5->trs_Info)); - *nzpresset5->trs_Info=NR_NZP_CSI_RS_ResourceSet__trs_Info_true; - ASN_SEQUENCE_ADD(&csi_MeasConfig->nzp_CSI_RS_ResourceSetToAddModList->list,nzpresset5); - } - - csi_MeasConfig->csi_IM_ResourceToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_IM_ResourceToAddModList)); - csi_MeasConfig->csi_IM_ResourceToReleaseList = NULL; - NR_CSI_IM_Resource_t *imres0 = calloc(1,sizeof(*imres0)); - imres0->csi_IM_ResourceId=0; - imres0->csi_IM_ResourceElementPattern=calloc(1,sizeof(*imres0->csi_IM_ResourceElementPattern)); - imres0->csi_IM_ResourceElementPattern->present = NR_CSI_IM_Resource__csi_IM_ResourceElementPattern_PR_pattern1 ; - imres0->csi_IM_ResourceElementPattern->choice.pattern1=calloc(1,sizeof(*imres0->csi_IM_ResourceElementPattern->choice.pattern1)); - imres0->csi_IM_ResourceElementPattern->choice.pattern1->subcarrierLocation_p1 = NR_CSI_IM_Resource__csi_IM_ResourceElementPattern__pattern1__subcarrierLocation_p1_s4; - imres0->csi_IM_ResourceElementPattern->choice.pattern1->symbolLocation_p1=7; - imres0->freqBand=calloc(1,sizeof(*imres0->freqBand)); - imres0->freqBand->startingRB=0; - imres0->freqBand->nrofRBs=276; - imres0->periodicityAndOffset=calloc(1,sizeof(*imres0->periodicityAndOffset)); - imres0->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots320; - imres0->periodicityAndOffset->choice.slots320 = 2; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_IM_ResourceToAddModList->list,imres0); - csi_MeasConfig->csi_IM_ResourceSetToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_IM_ResourceSetToAddModList)); - csi_MeasConfig->csi_IM_ResourceSetToReleaseList = NULL; - NR_CSI_IM_ResourceSet_t *imresset0 = calloc(1,sizeof(*imresset0)); - imresset0->csi_IM_ResourceSetId=0; - NR_CSI_IM_ResourceId_t *imresset00=calloc(1,sizeof(*imresset00)); - *imresset00=0; - ASN_SEQUENCE_ADD(&imresset0->csi_IM_Resources.list,imresset00); - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_IM_ResourceSetToAddModList->list,imresset0); - csi_MeasConfig->csi_SSB_ResourceSetToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_SSB_ResourceSetToAddModList)); - csi_MeasConfig->csi_SSB_ResourceSetToReleaseList = NULL; - NR_CSI_SSB_ResourceSet_t *ssbresset0 = calloc(1,sizeof(*ssbresset0)); - ssbresset0->csi_SSB_ResourceSetId=0; - NR_SSB_Index_t *ssbresset00=calloc(1,sizeof(*ssbresset00)); - *ssbresset00=0; - ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset00); - - if (n_physical_antenna_ports > 1) { - NR_SSB_Index_t *ssbresset01=calloc(1,sizeof(*ssbresset01)); - *ssbresset01=1; - ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset01); - } - - if (n_physical_antenna_ports > 3) { - NR_SSB_Index_t *ssbresset02=calloc(1,sizeof(*ssbresset02)); - *ssbresset02=2; - ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset02); - NR_SSB_Index_t *ssbresset03=calloc(1,sizeof(*ssbresset03)); - *ssbresset03=3; - ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset03); - } - - if (n_physical_antenna_ports > 7) { - NR_SSB_Index_t *ssbresset04=calloc(1,sizeof(*ssbresset04)); - *ssbresset04=4; - ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset04); - NR_SSB_Index_t *ssbresset05=calloc(1,sizeof(*ssbresset05)); - *ssbresset05=5; - ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset05); - NR_SSB_Index_t *ssbresset06=calloc(1,sizeof(*ssbresset06)); - *ssbresset06=6; - ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset06); - NR_SSB_Index_t *ssbresset07=calloc(1,sizeof(*ssbresset07)); - *ssbresset07=7; - ASN_SEQUENCE_ADD(&ssbresset0->csi_SSB_ResourceList.list,ssbresset07); - } - - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_SSB_ResourceSetToAddModList->list,ssbresset0); - csi_MeasConfig->csi_ResourceConfigToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_ResourceConfigToAddModList)); - csi_MeasConfig->csi_ResourceConfigToReleaseList = NULL; - NR_CSI_ResourceConfig_t *csires0 = calloc(1,sizeof(*csires0)); - csires0->csi_ResourceConfigId=0; - csires0->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires00 = calloc(1,sizeof(*csires00)); - *csires00 = 0; - ASN_SEQUENCE_ADD(&csires0->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires00); - csires0->bwp_Id = 1; - csires0->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires0); - NR_CSI_ResourceConfig_t *csires11 = calloc(1,sizeof(*csires11)); - csires11->csi_ResourceConfigId=11; - csires11->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_csi_IM_ResourceSetList; - csires11->csi_RS_ResourceSetList.choice.csi_IM_ResourceSetList = calloc(1,sizeof(*csires11->csi_RS_ResourceSetList.choice.csi_IM_ResourceSetList)); - NR_NZP_CSI_RS_ResourceSetId_t *csires110 = calloc(1,sizeof(*csires110)); - *csires110 = 0; - ASN_SEQUENCE_ADD(&csires11->csi_RS_ResourceSetList.choice.csi_IM_ResourceSetList->list,csires110); - csires11->bwp_Id = 1; - csires11->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires11); - NR_CSI_ResourceConfig_t *csires10 = calloc(1,sizeof(*csires10)); - csires10->csi_ResourceConfigId=10; - csires10->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires100 = calloc(1,sizeof(*csires100)); - *csires100 = 0; - ASN_SEQUENCE_ADD(&csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires100); - csires10->bwp_Id = 1; - csires10->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires10); - NR_CSI_ResourceConfig_t *csires2 = calloc(1,sizeof(*csires2)); - csires2->csi_ResourceConfigId=2; - csires2->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires20 = calloc(1,sizeof(*csires20)); - *csires20 = 0; - ASN_SEQUENCE_ADD(&csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires20); - csires2->bwp_Id = 1; - csires2->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires2); - NR_CSI_ResourceConfig_t *csires3 = calloc(1,sizeof(*csires3)); - csires3->csi_ResourceConfigId=3; - csires3->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires30 = calloc(1,sizeof(*csires30)); - *csires30 = 0; - ASN_SEQUENCE_ADD(&csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires30); - csires3->bwp_Id = 1; - csires3->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires3); - NR_CSI_ResourceConfig_t *csires4 = calloc(1,sizeof(*csires4)); - csires4->csi_ResourceConfigId=4; - csires4->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires40 = calloc(1,sizeof(*csires40)); - *csires40 = 0; - ASN_SEQUENCE_ADD(&csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires40); - csires4->bwp_Id = 1; - csires4->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires4); - NR_CSI_ResourceConfig_t *csires5 = calloc(1,sizeof(*csires5)); - csires5->csi_ResourceConfigId=5; - csires5->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires50 = calloc(1,sizeof(*csires50)); - *csires50 = 0; - ASN_SEQUENCE_ADD(&csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires50); - csires5->bwp_Id = 1; - csires5->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires5); - NR_CSI_ResourceConfig_t *csires6 = calloc(1,sizeof(*csires6)); - csires6->csi_ResourceConfigId=6; - csires6->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires60 = calloc(1,sizeof(*csires60)); - *csires60 = 0; - ASN_SEQUENCE_ADD(&csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires60); - csires6->bwp_Id = 1; - csires6->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires6); - NR_CSI_ResourceConfig_t *csires7 = calloc(1,sizeof(*csires7)); - csires7->csi_ResourceConfigId=7; - csires7->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires70 = calloc(1,sizeof(*csires70)); - *csires70 = 0; - ASN_SEQUENCE_ADD(&csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires70); - csires7->bwp_Id = 1; - csires7->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires7); - NR_CSI_ResourceConfig_t *csires8 = calloc(1,sizeof(*csires8)); - csires8->csi_ResourceConfigId=8; - csires8->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires80 = calloc(1,sizeof(*csires80)); - *csires80 = 0; - ASN_SEQUENCE_ADD(&csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires80); - csires8->bwp_Id = 1; - csires8->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires8); - NR_CSI_ResourceConfig_t *csires9 = calloc(1,sizeof(*csires9)); - csires9->csi_ResourceConfigId=9; - csires9->csi_RS_ResourceSetList.present = NR_CSI_ResourceConfig__csi_RS_ResourceSetList_PR_nzp_CSI_RS_SSB; - csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB = calloc(1,sizeof(*csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB)); - csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList = calloc(1,sizeof(*csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList)); - csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->csi_SSB_ResourceSetList = NULL; - NR_NZP_CSI_RS_ResourceSetId_t *csires90 = calloc(1,sizeof(*csires90)); - *csires90 = 0; - ASN_SEQUENCE_ADD(&csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires90); - csires9->bwp_Id = 1; - csires9->resourceType = NR_CSI_ResourceConfig__resourceType_periodic; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires9); - csi_MeasConfig->csi_ReportConfigToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_ReportConfigToAddModList)); - csi_MeasConfig->csi_ReportConfigToReleaseList = NULL; - NR_CSI_ReportConfig_t *csirep0 = calloc(1,sizeof(*csirep0)); - csirep0->reportConfigId=0; - csirep0->carrier=NULL; - csirep0->resourcesForChannelMeasurement=0; - csirep0->csi_IM_ResourcesForInterference=calloc(1,sizeof(*csirep0->csi_IM_ResourcesForInterference)); - *csirep0->csi_IM_ResourcesForInterference=11; - csirep0->nzp_CSI_RS_ResourcesForInterference=NULL; - csirep0->reportConfigType.present = NR_CSI_ReportConfig__reportConfigType_PR_periodic; - csirep0->reportConfigType.choice.periodic = calloc(1,sizeof(*csirep0->reportConfigType.choice.periodic)); - csirep0->reportConfigType.choice.periodic->reportSlotConfig.present=NR_CSI_ReportPeriodicityAndOffset_PR_slots320; - csirep0->reportConfigType.choice.periodic->reportSlotConfig.choice.slots320 = 9; - NR_PUCCH_CSI_Resource_t *pucchcsires0 = calloc(1,sizeof(*pucchcsires0)); - pucchcsires0->uplinkBandwidthPartId=1; - pucchcsires0->pucch_Resource=11; - ASN_SEQUENCE_ADD(&csirep0->reportConfigType.choice.periodic->pucch_CSI_ResourceList.list,pucchcsires0); - csirep0->reportQuantity.present = NR_CSI_ReportConfig__reportQuantity_PR_cri_RI_LI_PMI_CQI; - csirep0->reportQuantity.choice.cri_RI_PMI_CQI = (NULL_t)0; - csirep0->reportFreqConfiguration = calloc(1,sizeof(*csirep0->reportFreqConfiguration)); - csirep0->reportFreqConfiguration->cqi_FormatIndicator=NR_CSI_ReportConfig__reportFreqConfiguration__cqi_FormatIndicator_widebandCQI; - csirep0->reportFreqConfiguration->pmi_FormatIndicator=NR_CSI_ReportConfig__reportFreqConfiguration__pmi_FormatIndicator_widebandPMI; - csirep0->reportFreqConfiguration->csi_ReportingBand=calloc(1,sizeof(*csirep0->reportFreqConfiguration->csi_ReportingBand)); - AssertFatal(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id>0,"firstActiveDownlinkBWP_Id %d\n", - (int)*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id); - int NPRB = NRRIV2BW(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id - -1]->bwp_Common->genericParameters.locationAndBandwidth,275); - int sbsize = get_subband_size(NPRB,0); - int numsb = NPRB/sbsize; - - if (NPRB%sbsize == 0) numsb++; - - csirep0->reportFreqConfiguration->csi_ReportingBand->present= NR_CSI_ReportConfig__reportFreqConfiguration__csi_ReportingBand_PR_NOTHING+(numsb-2); - csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.size=numsb/8; - - if ((numsb&7) > 0) csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.size++; - - csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.bits_unused = (8-(numsb&7))&7; - csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.buf=malloc(csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.size); - - for (int i=0; ireportFreqConfiguration->csi_ReportingBand->choice.subbands18.size; i++) - csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.buf[i]=0xff; - - csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.buf[csirep0->reportFreqConfiguration->csi_ReportingBand->choice.subbands18.size-1]&=~(( - 1<reportFreqConfiguration->csi_ReportingBand->choice.subbands18.bits_unused)-1); - csirep0->timeRestrictionForChannelMeasurements= NR_CSI_ReportConfig__timeRestrictionForChannelMeasurements_configured; - csirep0->timeRestrictionForInterferenceMeasurements=NR_CSI_ReportConfig__timeRestrictionForInterferenceMeasurements_configured; - csirep0->codebookConfig=calloc(1,sizeof(*csirep0->codebookConfig)); - csirep0->codebookConfig->codebookType.present = NR_CodebookConfig__codebookType_PR_type1; - csirep0->codebookConfig->codebookType.choice.type1 = calloc(1,sizeof(*csirep0->codebookConfig->codebookType.choice.type1)); - csirep0->codebookConfig->codebookType.choice.type1->subType.present = NR_CodebookConfig__codebookType__type1__subType_PR_typeI_SinglePanel; - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel=calloc(1,sizeof(*csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel)); - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.present= - NR_CodebookConfig__codebookType__type1__subType__typeI_SinglePanel__nrOfAntennaPorts_PR_two; - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two= - calloc(1,sizeof(*csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two)); - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.size=1; - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.bits_unused=2; - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.buf=malloc(1); - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.buf[0]=0xfc; - //'111111'B - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.size=1; - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.bits_unused=0; - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.buf=malloc(1); - csirep0->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.buf[0]=0xc0; //'00000011'B - csirep0->codebookConfig->codebookType.choice.type1->codebookMode=1; - csirep0->dummy = NULL; - csirep0->groupBasedBeamReporting.present = NR_CSI_ReportConfig__groupBasedBeamReporting_PR_disabled; - csirep0->groupBasedBeamReporting.choice.disabled=calloc(1,sizeof(*csirep0->groupBasedBeamReporting.choice.disabled)); - csirep0->groupBasedBeamReporting.choice.disabled->nrofReportedRS = NULL; - csirep0->cqi_Table = calloc(1,sizeof(*csirep0->cqi_Table)); - *csirep0->cqi_Table = NR_CSI_ReportConfig__cqi_Table_table1; - csirep0->subbandSize = NR_CSI_ReportConfig__subbandSize_value1; - csirep0->non_PMI_PortIndication = NULL; - csirep0->ext1 = NULL; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ReportConfigToAddModList->list,csirep0); - NR_CSI_ReportConfig_t *csirep1 = calloc(1,sizeof(*csirep1)); - csirep1->reportConfigId=2; - csirep1->carrier=NULL; - csirep1->resourcesForChannelMeasurement=initial_csi_index; - csirep1->csi_IM_ResourcesForInterference=NULL; - csirep1->nzp_CSI_RS_ResourcesForInterference=NULL; - csirep1->reportConfigType.present = NR_CSI_ReportConfig__reportConfigType_PR_periodic; - csirep1->reportConfigType.choice.periodic = calloc(1,sizeof(*csirep1->reportConfigType.choice.periodic)); - csirep1->reportConfigType.choice.periodic->reportSlotConfig.present=NR_CSI_ReportPeriodicityAndOffset_PR_slots320; - csirep1->reportConfigType.choice.periodic->reportSlotConfig.choice.slots320 = 49; - NR_PUCCH_CSI_Resource_t *pucchcsires1 = calloc(1,sizeof(*pucchcsires1)); - pucchcsires1->uplinkBandwidthPartId=1; - pucchcsires1->pucch_Resource=12; - ASN_SEQUENCE_ADD(&csirep1->reportConfigType.choice.periodic->pucch_CSI_ResourceList.list,pucchcsires1); - csirep1->reportQuantity.present = NR_CSI_ReportConfig__reportQuantity_PR_ssb_Index_RSRP; - csirep1->reportQuantity.choice.ssb_Index_RSRP=(NULL_t)0; - csirep1->reportFreqConfiguration = calloc(1,sizeof(*csirep1->reportFreqConfiguration)); - csirep1->reportFreqConfiguration->cqi_FormatIndicator=NR_CSI_ReportConfig__reportFreqConfiguration__cqi_FormatIndicator_widebandCQI; - csirep1->reportFreqConfiguration->pmi_FormatIndicator=NR_CSI_ReportConfig__reportFreqConfiguration__pmi_FormatIndicator_widebandPMI; - csirep1->reportFreqConfiguration->csi_ReportingBand=NULL; - csirep1->timeRestrictionForChannelMeasurements= NR_CSI_ReportConfig__timeRestrictionForChannelMeasurements_configured; - csirep1->timeRestrictionForInterferenceMeasurements=NR_CSI_ReportConfig__timeRestrictionForInterferenceMeasurements_configured; - csirep1->codebookConfig=calloc(1,sizeof(*csirep1->codebookConfig)); - csirep1->codebookConfig->codebookType.present = NR_CodebookConfig__codebookType_PR_type1; - csirep1->codebookConfig->codebookType.choice.type1 = calloc(1,sizeof(*csirep1->codebookConfig->codebookType.choice.type1)); - csirep1->codebookConfig->codebookType.choice.type1->subType.present=NR_CodebookConfig__codebookType__type1__subType_PR_typeI_SinglePanel; - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel=calloc(1,sizeof(*csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel)); - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.present= - NR_CodebookConfig__codebookType__type1__subType__typeI_SinglePanel__nrOfAntennaPorts_PR_two; - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two= - calloc(1,sizeof(*csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two)); - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.size=1; - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.bits_unused=2; - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.buf=malloc(1); - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->nrOfAntennaPorts.choice.two->twoTX_CodebookSubsetRestriction.buf[0]=0xfc; - //'111111'B - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.size=1; - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.bits_unused=0; - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.buf=malloc(1); - csirep1->codebookConfig->codebookType.choice.type1->subType.choice.typeI_SinglePanel->typeI_SinglePanel_ri_Restriction.buf[0]=0xc0; //'00000011'B - csirep1->codebookConfig->codebookType.choice.type1->codebookMode=1; - csirep1->dummy = NULL; - csirep1->groupBasedBeamReporting.present = NR_CSI_ReportConfig__groupBasedBeamReporting_PR_disabled; - csirep1->groupBasedBeamReporting.choice.disabled=calloc(1,sizeof(*csirep1->groupBasedBeamReporting.choice.disabled)); - csirep1->groupBasedBeamReporting.choice.disabled->nrofReportedRS = calloc(1,sizeof(*csirep1->groupBasedBeamReporting.choice.disabled->nrofReportedRS)); - *csirep1->groupBasedBeamReporting.choice.disabled->nrofReportedRS=NR_CSI_ReportConfig__groupBasedBeamReporting__disabled__nrofReportedRS_n2; - // this corresponds to: - //if the UE is configured with the higher layer parameter groupBasedBeamReporting set to 'disabled', the UE is not required to update measurements for more than 64 CSI-RS and/or SSB resources, and the UE shall report in a single report nrofReportedRS (higher layer configured) different CRI or SSBRI for each report setting. - csirep1->cqi_Table = calloc(1,sizeof(*csirep1->cqi_Table)); - *csirep1->cqi_Table = NR_CSI_ReportConfig__cqi_Table_table1; - csirep1->subbandSize = NR_CSI_ReportConfig__subbandSize_value1; - csirep1->non_PMI_PortIndication = NULL; - csirep1->ext1 = NULL; - ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ReportConfigToAddModList->list,csirep1); - secondaryCellGroup->spCellConfig->spCellConfigDedicated->sCellDeactivationTimer=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->tag_Id=0; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->dummy=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->pathlossReferenceLinking=NULL; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->servingCellMO=NULL; ->>>>>>> origin/develop } void fill_default_reconfig(NR_ServingCellConfigCommon_t *servingcellconfigcommon, NR_RRCReconfiguration_IEs_t *reconfig, From f73ecda99552aa1c90ee69ef4570a8179878a757 Mon Sep 17 00:00:00 2001 From: Florian Kaltenberger Date: Thu, 2 Jul 2020 10:49:18 +0200 Subject: [PATCH 436/553] nr_prachsim -F now reads full subframe --- openair1/SIMULATION/NR_PHY/prachsim.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openair1/SIMULATION/NR_PHY/prachsim.c b/openair1/SIMULATION/NR_PHY/prachsim.c index bffd70d588..2df54ca1cf 100644 --- a/openair1/SIMULATION/NR_PHY/prachsim.c +++ b/openair1/SIMULATION/NR_PHY/prachsim.c @@ -691,10 +691,10 @@ int main(int argc, char **argv){ } } } else { - n_bytes = fread(&ru->common.rxdata[0][rx_prach_start+frame_parms->samples_per_subframe/2],sizeof(int32_t),frame_parms->samples_per_subframe/2,input_fd); + n_bytes = fread(&ru->common.rxdata[0][rx_prach_start],sizeof(int32_t),frame_parms->samples_per_subframe,input_fd); printf("fread %d bytes from file %s\n",n_bytes,input_file); - if (n_bytes!=frame_parms->samples_per_subframe/2) { - printf("expected %d bytes\n",frame_parms->samples_per_subframe/2); + if (n_bytes!=frame_parms->samples_per_subframe) { + printf("expected %d bytes\n",frame_parms->samples_per_subframe); exit(-1); } } From 4b58b9d38a573e55a2cf94a3397f9be97453ec65 Mon Sep 17 00:00:00 2001 From: laurent Date: Thu, 2 Jul 2020 16:32:07 +0200 Subject: [PATCH 437/553] gcc warnings --- common/utils/ocp_itti/intertask_interface.h | 2 +- executables/nr-ru.c | 4 ++-- executables/nr-uesoftmodem.c | 4 ++-- openair1/PHY/CODING/nrPolar_tools/nr_polar_defs.h | 2 +- openair1/PHY/CODING/nrPolar_tools/nr_polar_encoder.c | 4 ++-- openair1/PHY/NR_TRANSPORT/nr_dci.c | 2 +- openair1/PHY/NR_TRANSPORT/nr_pbch.c | 2 +- openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c | 6 +++--- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 6 ++---- openair2/ENB_APP/enb_config.c | 4 ++-- openair2/F1AP/f1ap_cu_ue_context_management.c | 2 +- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 2 +- openair2/RRC/NR/rrc_gNB_nsa.c | 1 + 13 files changed, 20 insertions(+), 21 deletions(-) diff --git a/common/utils/ocp_itti/intertask_interface.h b/common/utils/ocp_itti/intertask_interface.h index 9e27ecf358..026c8270d7 100644 --- a/common/utils/ocp_itti/intertask_interface.h +++ b/common/utils/ocp_itti/intertask_interface.h @@ -415,7 +415,7 @@ static const message_info_t messages_info[] = { #undef MESSAGE_DEF }; -typedef struct __attribute__ ((__packed__)) MessageDef_s { +typedef struct MessageDef_s { MessageHeader ittiMsgHeader; /**< Message header */ msg_t ittiMsg; } MessageDef; diff --git a/executables/nr-ru.c b/executables/nr-ru.c index b2c6e94acf..969ad21b8e 100644 --- a/executables/nr-ru.c +++ b/executables/nr-ru.c @@ -772,8 +772,8 @@ void tx_rf(RU_t *ru,int frame,int slot, uint64_t timestamp) { siglen+sf_extension, ru->nb_tx, flags); - LOG_D(PHY,"[TXPATH] RU %d tx_rf, writing to TS %llu, frame %d, unwrapped_frame %d, slot %d\n",ru->idx, - (long long unsigned int)timestamp,frame,proc->frame_tx_unwrap,slot); + LOG_D(PHY,"[TXPATH] RU %d tx_rf, writing to TS %llu, frame %d, unwrapped_frame %d, slot %di, returned %d\n",ru->idx, + (long long unsigned int)timestamp,frame,proc->frame_tx_unwrap,slot, txs); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_WRITE, 0 ); //AssertFatal(txs == 0,"trx write function error %d\n", txs); } diff --git a/executables/nr-uesoftmodem.c b/executables/nr-uesoftmodem.c index dd881c409b..6d3bbc9038 100644 --- a/executables/nr-uesoftmodem.c +++ b/executables/nr-uesoftmodem.c @@ -71,8 +71,8 @@ unsigned short config_frames[4] = {2,9,11,13}; #include "PHY/INIT/phy_init.h" #include "system.h" #include -#include "NR_MAC_UE/mac_defs.h" -#include "NR_MAC_UE/mac_proto.h" +#include +#include #include #include diff --git a/openair1/PHY/CODING/nrPolar_tools/nr_polar_defs.h b/openair1/PHY/CODING/nrPolar_tools/nr_polar_defs.h index 6e01a05d0f..a44a08a701 100644 --- a/openair1/PHY/CODING/nrPolar_tools/nr_polar_defs.h +++ b/openair1/PHY/CODING/nrPolar_tools/nr_polar_defs.h @@ -146,7 +146,7 @@ void polar_encoder_dci(uint32_t *in, uint16_t n_RNTI); void polar_encoder_fast(uint64_t *A, - uint32_t *out, + void *out, int32_t crcmask, uint8_t ones_flag, t_nrPolar_params *polarParams); diff --git a/openair1/PHY/CODING/nrPolar_tools/nr_polar_encoder.c b/openair1/PHY/CODING/nrPolar_tools/nr_polar_encoder.c index 70791302cc..27c062c217 100644 --- a/openair1/PHY/CODING/nrPolar_tools/nr_polar_encoder.c +++ b/openair1/PHY/CODING/nrPolar_tools/nr_polar_encoder.c @@ -408,7 +408,7 @@ void build_polar_tables(t_nrPolar_params *polarParams) { } void polar_encoder_fast(uint64_t *A, - uint32_t *out, + void *out, int32_t crcmask, uint8_t ones_flag, t_nrPolar_params *polarParams) { @@ -676,5 +676,5 @@ void polar_encoder_fast(uint64_t *A, } } memset((void*)out,0,polarParams->encoderLength>>3); - polar_rate_matching(polarParams,(void *)D,(void *)out); + polar_rate_matching(polarParams,(void *)D, out); } diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.c b/openair1/PHY/NR_TRANSPORT/nr_dci.c index 8508621ae5..6298de3c60 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.c @@ -237,7 +237,7 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d], pdcch_pdu_rel15->dci_pdu.AggregationLevel[d], 0,NULL); - polar_encoder_fast((uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[d], encoder_output, n_RNTI,1,currentPtr); + polar_encoder_fast((uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[d], (void*)encoder_output, n_RNTI,1,currentPtr); #ifdef DEBUG_CHANNEL_CODING printf("polar rnti %x,length %d, L %d\n",n_RNTI, pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d],pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]); printf("DCI PDU: [0]->0x%lx \t [1]->0x%lx\n", diff --git a/openair1/PHY/NR_TRANSPORT/nr_pbch.c b/openair1/PHY/NR_TRANSPORT/nr_pbch.c index f5a26aec80..bc33d93811 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_pbch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_pbch.c @@ -297,7 +297,7 @@ int nr_generate_pbch(NR_gNB_PBCH *pbch, a_reversed |= (((uint64_t)pbch->pbch_a_prime>>i)&1)<<(31-i); /// CRC, coding and rate matching - polar_encoder_fast (&a_reversed, (uint32_t *)pbch->pbch_e, 0, 0, + polar_encoder_fast (&a_reversed, (void*)pbch->pbch_e, 0, 0, nr_polar_params( NR_POLAR_PBCH_MESSAGE_TYPE, NR_POLAR_PBCH_PAYLOAD_BITS, NR_POLAR_PBCH_AGGREGATION_LEVEL,0,NULL) ); #ifdef DEBUG_PBCH_ENCODING diff --git a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c index e1358602ce..823de0a63e 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c +++ b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c @@ -962,7 +962,7 @@ void nr_generate_pucch2(PHY_VARS_NR_UE *ue, uint64_t b[16]; // limit to 1024-bit encoded length // M_bit is the number of bits of block b (payload after encoding) uint16_t M_bit; - nr_uci_encoding(payload,nr_bit,pucch_format2_nr,0,nrofSymbols,nrofPRB,1,0,0,&b,&M_bit); + nr_uci_encoding(payload,nr_bit,pucch_format2_nr,0,nrofSymbols,nrofPRB,1,0,0,(void*)b,&M_bit); /* * Implementing TS 38.211 * Subclauses 6.3.2.5.1 Scrambling (PUCCH format 2) @@ -1128,7 +1128,7 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue, printf("\t [nr_generate_pucch3_4] start function at slot(nr_tti_tx)=%d with payload=%lu and nr_bit=%d\n", nr_tti_tx, payload, nr_bit); #endif // b is the block of bits transmitted on the physical channel after payload coding - uint64_t b; + uint64_t b[16]; // M_bit is the number of bits of block b (payload after encoding) uint16_t M_bit; // parameter PUCCH-F4-preDFT-OCC-length set of {2,4} -> to use table -1 or -2 @@ -1153,7 +1153,7 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue, //nrofPRB = 2; // only for test purposes if (fmt == pucch_format4_nr) nrofPRB = 1; - nr_uci_encoding(payload,nr_bit,fmt,is_pi_over_2_bpsk_enabled,nrofSymbols,nrofPRB,n_SF_PUCCH_s,intraSlotFrequencyHopping,add_dmrs,&b,&M_bit); + nr_uci_encoding(payload,nr_bit,fmt,is_pi_over_2_bpsk_enabled,nrofSymbols,nrofPRB,n_SF_PUCCH_s,intraSlotFrequencyHopping,add_dmrs,(void*)b,&M_bit); /* * Implementing TS 38.211 * Subclauses 6.3.2.6.1 Scrambling (PUCCH formats 3 and 4) diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 8bcd5cbe26..124290da25 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -2753,10 +2753,8 @@ int nr_ue_pdcch_procedures(uint8_t gNB_id, pdcch_vars->nb_search_space); #endif - fapi_nr_dci_indication_t dci_ind; - nr_downlink_indication_t dl_indication; - memset((void*)&dci_ind,0,sizeof(dci_ind)); - memset((void*)&dl_indication,0,sizeof(dl_indication)); + fapi_nr_dci_indication_t dci_ind={0}; + nr_downlink_indication_t dl_indication={0}; dci_cnt = nr_dci_decoding_procedure(ue, proc->frame_rx, nr_tti_rx, diff --git a/openair2/ENB_APP/enb_config.c b/openair2/ENB_APP/enb_config.c index 6dcc574746..2200c8f013 100644 --- a/openair2/ENB_APP/enb_config.c +++ b/openair2/ENB_APP/enb_config.c @@ -1545,7 +1545,7 @@ int RCconfig_RRC(uint32_t i, eNB_RRC_INST *rrc, int macrlc_has_f1) { RRC_CONFIGURATION_REQ(msg_p).eMBMS_configured = 0; printf("No eMBMS configuration, skipping it\n"); // eMTC configuration - char brparamspath[MAX_OPTNAME_SIZE*2 + 16]; + char brparamspath[MAX_OPTNAME_SIZE*2 + 160]; sprintf(brparamspath,"%s.%s", ccspath, ENB_CONFIG_STRING_EMTC_PARAMETERS); config_get(eMTCParams, sizeof(eMTCParams)/sizeof(paramdef_t), brparamspath); RRC_CONFIGURATION_REQ(msg_p).eMTC_configured = eMTCconfig.eMTC_configured&1; @@ -1554,7 +1554,7 @@ int RCconfig_RRC(uint32_t i, eNB_RRC_INST *rrc, int macrlc_has_f1) { else printf("No eMTC configuration, skipping it\n"); // Sidelink configuration - char SLparamspath[MAX_OPTNAME_SIZE*2 + 16]; + char SLparamspath[MAX_OPTNAME_SIZE*2 + 160]; sprintf(SLparamspath,"%s.%s", ccspath, ENB_CONFIG_STRING_SL_PARAMETERS); config_get( SLParams, sizeof(SLParams)/sizeof(paramdef_t), SLparamspath); // Sidelink Resource pool information diff --git a/openair2/F1AP/f1ap_cu_ue_context_management.c b/openair2/F1AP/f1ap_cu_ue_context_management.c index a64f2d529b..789ce4c715 100644 --- a/openair2/F1AP/f1ap_cu_ue_context_management.c +++ b/openair2/F1AP/f1ap_cu_ue_context_management.c @@ -226,7 +226,7 @@ int CU_send_UE_CONTEXT_SETUP_REQUEST(instance_t instance, ie->value.choice.ResourceCoordinationTransferContainer.buf = malloc(4); ie->value.choice.ResourceCoordinationTransferContainer.size = 4; - strncpy((char *)ie->value.choice.ResourceCoordinationTransferContainer.buf, "123", 3); + strncpy((char *)ie->value.choice.ResourceCoordinationTransferContainer.buf, "123", 4); OCTET_STRING_fromBuf(&ie->value.choice.ResourceCoordinationTransferContainer, "asdsa1d32sa1d31asd31as", diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 0da02bd7d1..1cfa083ca4 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -272,7 +272,7 @@ int8_t nr_ue_decode_mib(module_id_t module_id, uint16_t frame_number_4lsb = 0; for (int i=0; i<4; i++) frame_number_4lsb |= ((extra_bits>>i)&1)<<(3-i); - uint8_t half_frame_bit = ( extra_bits >> 4 ) & 0x1; // extra bits[4] + //uint8_t half_frame_bit = ( extra_bits >> 4 ) & 0x1; // extra bits[4] uint8_t ssb_subcarrier_offset_msb = ( extra_bits >> 5 ) & 0x1; // extra bits[5] uint8_t ssb_subcarrier_offset = (uint8_t)mac->mib->ssb_SubcarrierOffset; diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c index 0bdfb274ea..3604336c6d 100644 --- a/openair2/RRC/NR/rrc_gNB_nsa.c +++ b/openair2/RRC/NR/rrc_gNB_nsa.c @@ -39,6 +39,7 @@ #include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h" #include "openair2/RRC/LTE/rrc_eNB_GTPV1U.h" #include "executables/softmodem-common.h" +#include void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList, x2ap_ENDC_sgnb_addition_req_t *m, NR_CG_ConfigInfo_IEs_t *cg_config_info) { struct rrc_gNB_ue_context_s *ue_context_p = NULL; From b0d65fd6cbe6ffa07a326e21247ecb6786e5e22d Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Thu, 2 Jul 2020 17:06:43 +0200 Subject: [PATCH 438/553] CI: adding test on caracal with TX Write Thread enabled Signed-off-by: Raphael Defosseux --- ci-scripts/.gitignore | 1 + ci-scripts/ran.py | 8 +++ .../gnb_nr_ue_usrp_run_multi_thread.xml | 71 +++++++++++++++++++ ci-scripts/xml_files/gnb_usrp_build.xml | 1 + ci-scripts/xml_files/nr_ue_usrp_build.xml | 1 + 5 files changed, 82 insertions(+) create mode 100644 ci-scripts/xml_files/gnb_nr_ue_usrp_run_multi_thread.xml diff --git a/ci-scripts/.gitignore b/ci-scripts/.gitignore index dc5e7c7476..34d19403a7 100644 --- a/ci-scripts/.gitignore +++ b/ci-scripts/.gitignore @@ -1,3 +1,4 @@ +r*.raw enb_*.log ue_*.log ping_*.* diff --git a/ci-scripts/ran.py b/ci-scripts/ran.py index c968521bda..79fe1e2fc0 100644 --- a/ci-scripts/ran.py +++ b/ci-scripts/ran.py @@ -811,6 +811,7 @@ class RANManagement(): uplinkSegmentsAborted = 0 ulschReceiveOK = 0 gnbRxTxWakeUpFailure = 0 + gnbTxWriteThreadEnabled = False cdrxActivationMessageCount = 0 dropNotEnoughRBs = 0 mbmsRequestMsg = 0 @@ -924,6 +925,9 @@ class RANManagement(): result = re.search('could not wakeup gNB rxtx process', str(line)) if result is not None: gnbRxTxWakeUpFailure += 1 + result = re.search('tx write thread ready', str(line)) + if result is not None: + gnbTxWriteThreadEnabled = True result = re.search('ULSCH in error in round|ULSCH 0 in error', str(line)) if result is not None: ulschFailure += 1 @@ -964,6 +968,10 @@ class RANManagement(): statMsg = nodeB_prefix + 'NB showed ' + str(gnbRxTxWakeUpFailure) + ' "could not wakeup gNB rxtx process" message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') htmleNBFailureMsg += statMsg + '\n' + if gnbTxWriteThreadEnabled: + statMsg = nodeB_prefix + 'NB ran with TX Write thread enabled' + logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') + htmleNBFailureMsg += statMsg + '\n' if uciStatMsgCount > 0: statMsg = nodeB_prefix + 'NB showed ' + str(uciStatMsgCount) + ' "uci->stat" message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') diff --git a/ci-scripts/xml_files/gnb_nr_ue_usrp_run_multi_thread.xml b/ci-scripts/xml_files/gnb_nr_ue_usrp_run_multi_thread.xml new file mode 100644 index 0000000000..ad91807a9b --- /dev/null +++ b/ci-scripts/xml_files/gnb_nr_ue_usrp_run_multi_thread.xml @@ -0,0 +1,71 @@ + + + run-oai-gnb-nr-ue + Run-gNB-and-NR-UE + tasks + 2 + +090103 000001 090104 000002 090108 090109 + + + + + Initialize_eNB + Initialize gNB USRP (Multi-Threading enabled) + -O ci-scripts/conf_files/gnb.band78.tm1.106PRB.usrpn300.conf --phy-test --usrp-tx-thread-config 1 + NR + + + + IdleSleep + Sleep + 5 + + + + IdleSleep + Waiting for NR UE to synchronize w/ gNB + 180 + + + + Initialize_OAI_UE + Initialize NR UE USRP + --phy-test --usrp-args "addr=192.168.30.2,second_addr=192.168.50.2,clock_source=external,time_source=external" --threadoffset 16 --rrc_config_path . + NR + + + + Terminate_OAI_UE + Terminate NR UE + NR + + + + Terminate_eNB + Terminate gNB + NR + + + diff --git a/ci-scripts/xml_files/gnb_usrp_build.xml b/ci-scripts/xml_files/gnb_usrp_build.xml index bba92930c5..97d6ef06f6 100644 --- a/ci-scripts/xml_files/gnb_usrp_build.xml +++ b/ci-scripts/xml_files/gnb_usrp_build.xml @@ -24,6 +24,7 @@ gnb-build-tab Build-gNB wrench + 4 010101 diff --git a/ci-scripts/xml_files/nr_ue_usrp_build.xml b/ci-scripts/xml_files/nr_ue_usrp_build.xml index 7d8d97d2c5..c3c842b85a 100644 --- a/ci-scripts/xml_files/nr_ue_usrp_build.xml +++ b/ci-scripts/xml_files/nr_ue_usrp_build.xml @@ -24,6 +24,7 @@ nr-ue-build-tab Build-NR-UE wrench + 2 010102 From 9205b4d00421592e542564067d4c6fc2becc4aee Mon Sep 17 00:00:00 2001 From: laurent Date: Thu, 2 Jul 2020 22:29:44 +0200 Subject: [PATCH 439/553] fix gaussain noise seed in rfsimulator --- targets/ARCH/rfsimulator/simulator.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/targets/ARCH/rfsimulator/simulator.c b/targets/ARCH/rfsimulator/simulator.c index ad880e3cbf..b7b435f2d9 100644 --- a/targets/ARCH/rfsimulator/simulator.c +++ b/targets/ARCH/rfsimulator/simulator.c @@ -149,8 +149,12 @@ void allocCirBuf(rfsimulator_state_t *bridge, int sock) { // while calling new_channel_desc_scm() with path losses = 0 static bool init_done=false; if (!init_done) { - randominit(0); - tableNor(0); + uint64_t rand; + FILE *h=fopen("/dev/random","r"); + fread(&rand,sizeof(rand),1,h); + fclose(h); + randominit(rand); + tableNor(rand); init_done=true; } ptr->channel_model=new_channel_desc_scm(bridge->tx_num_channels,bridge->rx_num_channels, From 67a8f8dab4bc93c957de22074b51b84e09ffecb6 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 3 Jul 2020 11:10:56 +0200 Subject: [PATCH 440/553] minor fixes --- cmake_targets/autotests/test_case_list.xml | 5 ++--- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 12 +++++++----- openair1/SIMULATION/NR_PHY/ulsim.c | 5 +++-- 3 files changed, 12 insertions(+), 10 deletions(-) diff --git a/cmake_targets/autotests/test_case_list.xml b/cmake_targets/autotests/test_case_list.xml index 346aa8bfef..9bdf60476f 100644 --- a/cmake_targets/autotests/test_case_list.xml +++ b/cmake_targets/autotests/test_case_list.xml @@ -1116,7 +1116,7 @@ -n100 -s1 -t33 -n100 -s1 -t50 - nr_dlsim.test1 nr_dlsim.test2 nr_dlsim.test3 nr_dlsim.test4 nr_dlsim.test5 nr_dlsim.test6 nr_dlsim.test7 nr_dlsim.test8 nr_dlsim.test9 nr_dlsim.test10 nr_dlsim.test11 nr_dlsim.test12 nr_dlsim.test13 + nr_dlsim.test1 nr_dlsim.test2 nr_dlsim.test3 nr_dlsim.test4 nr_dlsim.test5 nr_dlsim.test6 nr_dlsim.test7 nr_dlsim.test8 nr_dlsim.test9 nr_dlsim.test10 nr_dlsim.test11 nr_dlsim.test12 nr_dlsim.test13 PDSCH test OK segmentation fault|assertion|exiting|fatal 3 @@ -1227,8 +1227,7 @@ -R 106 -i 1 -P 2 -q8 -b 19 -s-3 -n1000 -R 106 -i 1 -P 2 -q8 -b 32 -s-3 -n1000 -R 106 -i 1 -P 2 -q16 -b 32 -s-3 -n1000 - -R 106 -i 1 -P 2 -q16 -b 64 -s-3 -n1000 - + -R 106 -i 1 -P 2 -q16 -b 64 -s-3 -n1000 nr_pucchsim.test1 nr_pucchsim.test2 nr_pucchsim.test3 nr_pucchsim.test4 nr_pucchsim.test5 nr_pucchsim.test6 nr_pucchsim.test7 nr_pucchsim.test8 nr_pucchsim.test9 nr_pucchsim.test10 nr_pucchsim.test11 nr_pucchsim.test12 nr_pucchsim.test13 nr_pucchsim.test14 nr_pucchsim.test15 nr_pucchsim.test16 nr_pucchsim.test17 PUCCH test OK segmentation fault|assertion|exiting|fatal diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 1b309438b8..4170f6b6be 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -2247,11 +2247,13 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, } // UE_mode==PUSCH */ - LOG_D(PHY, "Sending PUCCH\n"); - pucch_procedures_ue_nr(ue, - gNB_id, - proc, - TRUE); + if (get_softmodem_params()->do_ra==1) { + LOG_D(PHY, "Sending PUCCH\n"); + pucch_procedures_ue_nr(ue, + gNB_id, + proc, + TRUE); + } LOG_D(PHY, "Sending data \n"); nr_ue_pusch_common_procedures(ue, diff --git a/openair1/SIMULATION/NR_PHY/ulsim.c b/openair1/SIMULATION/NR_PHY/ulsim.c index b6b432f216..e0e7a3c166 100644 --- a/openair1/SIMULATION/NR_PHY/ulsim.c +++ b/openair1/SIMULATION/NR_PHY/ulsim.c @@ -113,7 +113,7 @@ int main(int argc, char **argv) double sigma, sigma_dB; double snr_step = 1; uint8_t snr1set = 0; - int slot = 17, frame = 0; + int slot = 8, frame = 0; FILE *output_fd = NULL; //uint8_t write_output_file = 0; int trial, n_trials = 1, n_errors = 0, n_false_positive = 0, delay = 0; @@ -693,6 +693,7 @@ int main(int argc, char **argv) ul_config.ul_config_list[0].pusch_config_pdu.dmrs_config_type = 0; ul_config.ul_config_list[0].pusch_config_pdu.mcs_index = Imcs; ul_config.ul_config_list[0].pusch_config_pdu.mcs_table = mcs_table; + ul_config.ul_config_list[0].pusch_config_pdu.num_dmrs_cdm_grps_no_data = 1; ul_config.ul_config_list[0].pusch_config_pdu.pusch_data.new_data_indicator = 0; ul_config.ul_config_list[0].pusch_config_pdu.pusch_data.rv_index = 0; ul_config.ul_config_list[0].pusch_config_pdu.nrOfLayers = precod_nbr_layers; @@ -710,7 +711,7 @@ int main(int argc, char **argv) TBS = nr_compute_tbs(mod_order, code_rate, nb_rb, nb_symb_sch, nb_re_dmrs * number_dmrs_symbols, 0, 0, precod_nbr_layers); - if (input_fd != NULL) { + if (input_fd == NULL) { pusch_pdu->pusch_data.tb_size = TBS>>3; ul_config.ul_config_list[0].pusch_config_pdu.pusch_data.tb_size = TBS; // set FAPI parameters for UE, put them in the scheduled response and call From f13398e17b9f61a0d6316d8300acd153311bb6b0 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Fri, 3 Jul 2020 13:42:10 +0200 Subject: [PATCH 441/553] fixed pucch config in ue --- openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c | 5 +++-- openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h | 3 ++- openair1/SCHED_NR_UE/pucch_uci_ue_nr.c | 3 ++- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c index e1358602ce..b0c0519735 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c +++ b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c @@ -54,7 +54,8 @@ void nr_generate_pucch0(PHY_VARS_NR_UE *ue, int32_t **txdataF, NR_DL_FRAME_PARMS *frame_parms, - PUCCH_CONFIG_DEDICATED *pucch_config_dedicated, + long pucch_GroupHopping, + long hoppingId, int16_t amp, int nr_tti_tx, uint8_t m0, @@ -111,7 +112,7 @@ void nr_generate_pucch0(PHY_VARS_NR_UE *ue, for (int l=0; lpucch_config_common_nr->pucch_GroupHopping,ue->pucch_config_common_nr->hoppingId,n_hop,nr_tti_tx,&u,&v); // calculating u and v value + nr_group_sequence_hopping(pucch_GroupHopping,hoppingId,n_hop,nr_tti_tx,&u,&v); // calculating u and v value alpha = nr_cyclic_shift_hopping(ue->pucch_config_common_nr->hoppingId,m0,mcs,l,startingSymbolIndex,nr_tti_tx); #ifdef DEBUG_NR_PUCCH_TX printf("\t [nr_generate_pucch0] sequence generation \tu=%d \tv=%d \talpha=%lf \t(for symbol l=%d)\n",u,v,alpha,l); diff --git a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h index a2446dccf9..0e81045d66 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h +++ b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h @@ -49,7 +49,8 @@ void nr_generate_pucch0(PHY_VARS_NR_UE *ue, int32_t **txdataF, NR_DL_FRAME_PARMS *frame_parms, - PUCCH_CONFIG_DEDICATED *pucch_config_dedicated, + long pucch_GroupHopping, + long hoppingId, int16_t amp, int nr_tti_tx, uint8_t m0, diff --git a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c index 9c25b00fb0..4b2ee9a3a1 100644 --- a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c +++ b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c @@ -580,7 +580,8 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ { nr_generate_pucch0(ue,ue->common_vars.txdataF, &ue->frame_parms, - &ue->pucch_config_dedicated[gNB_id], + mac->ULbwp[bwp_id-1]->bwp_Common->pucch_ConfigCommon->choice.setup->pucch_GroupHopping, + mac->ULbwp[bwp_id-1]->bwp_Common->pucch_ConfigCommon->choice.setup->hoppingId[0], tx_amp, nr_tti_tx, (uint8_t)m_0, From a7dae03d738883a6c3bac958dcd9238273f9bccb Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Fri, 3 Jul 2020 13:43:43 +0200 Subject: [PATCH 442/553] set txdataF to 0 at beginning of slots --- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 1b309438b8..9391067607 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -2227,6 +2227,8 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX,VCD_FUNCTION_IN); + memset(ue->common_vars.txdataF[0], 0, sizeof(int)*14*ue->frame_parms.ofdm_symbol_size); + LOG_I(PHY,"****** start TX-Chain for AbsSubframe %d.%d ******\n", frame_tx, slot_tx); #if UE_TIMING_TRACE From 12354bb6c6db75599ad1c1f87a59b8089f5665df Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 3 Jul 2020 13:57:46 +0200 Subject: [PATCH 443/553] bugfixes in dlschsim --- openair1/SIMULATION/NR_PHY/dlschsim.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openair1/SIMULATION/NR_PHY/dlschsim.c b/openair1/SIMULATION/NR_PHY/dlschsim.c index 0a2145abee..9374050e58 100644 --- a/openair1/SIMULATION/NR_PHY/dlschsim.c +++ b/openair1/SIMULATION/NR_PHY/dlschsim.c @@ -430,7 +430,7 @@ int main(int argc, char **argv) uint8_t is_crnti = 0, llr8_flag = 0; unsigned int TBS = 8424; unsigned int available_bits; - uint8_t nb_re_dmrs = 12; // No data in dmrs symbol + uint8_t nb_re_dmrs = 6; // No data in dmrs symbol uint16_t length_dmrs = 1; unsigned char mod_order; uint16_t rate; @@ -457,6 +457,7 @@ int main(int argc, char **argv) rel15->dmrsConfigType = NFAPI_NR_DMRS_TYPE1; rel15->dlDmrsSymbPos = 4; rel15->mcsIndex[0] = Imcs; + rel15->numDmrsCdmGrpsNoData = 1; double *modulated_input = malloc16(sizeof(double) * 16 * 68 * 384); // [hna] 16 segments, 68*Zc short *channel_output_fixed = malloc16(sizeof(short) * 16 * 68 * 384); short *channel_output_uncoded = malloc16(sizeof(unsigned short) * 16 * 68 * 384); From cabff5b73b8827c2b7f3a417a19a08f0c4776a4b Mon Sep 17 00:00:00 2001 From: laurent Date: Fri, 3 Jul 2020 14:57:27 +0200 Subject: [PATCH 444/553] fix itti issue in memory management --- common/utils/ocp_itti/intertask_interface.cpp | 12 ++++++++++-- executables/main-ocp.c | 2 ++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/common/utils/ocp_itti/intertask_interface.cpp b/common/utils/ocp_itti/intertask_interface.cpp index 3d4d356dcf..22933fdd5b 100644 --- a/common/utils/ocp_itti/intertask_interface.cpp +++ b/common/utils/ocp_itti/intertask_interface.cpp @@ -91,8 +91,16 @@ task_list_t tasks[TASK_MAX]; return (EXIT_SUCCESS); } + // in the two following functions, the +32 in malloc is there to deal with gcc memory alignment + // because a struct size can be larger than sum(sizeof(struct components)) + // We should remove the itti principle of a huge union for all types of messages in paramter "msg_t ittiMsg" + // to use a more C classical pointer casting "void * ittiMsg", later casted in the right struct + // but we would have to change all legacy macros, as per this example + // #define S1AP_REGISTER_ENB_REQ(mSGpTR) (mSGpTR)->ittiMsg.s1ap_register_enb_req + // would become + // #define S1AP_REGISTER_ENB_REQ(mSGpTR) (s1ap_register_enb_req) mSGpTR)->ittiMsg MessageDef *itti_alloc_new_message_sized(task_id_t origin_task_id, MessagesIds message_id, MessageHeaderSize size) { - MessageDef *temp = (MessageDef *)itti_malloc (origin_task_id, TASK_UNKNOWN, sizeof(MessageHeader) + size); + MessageDef *temp = (MessageDef *)itti_malloc (origin_task_id, TASK_UNKNOWN, sizeof(MessageHeader) +32 + size); temp->ittiMsgHeader.messageId = message_id; temp->ittiMsgHeader.originTaskId = origin_task_id; temp->ittiMsgHeader.ittiMsgSize = size; @@ -100,7 +108,7 @@ task_list_t tasks[TASK_MAX]; } MessageDef *itti_alloc_new_message(task_id_t origin_task_id, MessagesIds message_id) { - int size=sizeof(MessageHeader) + messages_info[message_id].size; + int size=sizeof(MessageHeader) + 32 + messages_info[message_id].size; MessageDef *temp = (MessageDef *)itti_malloc (origin_task_id, TASK_UNKNOWN, size); temp->ittiMsgHeader.messageId = message_id; temp->ittiMsgHeader.originTaskId = origin_task_id; diff --git a/executables/main-ocp.c b/executables/main-ocp.c index d2ee9418dc..e4e42b4f23 100644 --- a/executables/main-ocp.c +++ b/executables/main-ocp.c @@ -80,6 +80,7 @@ int32_t uplink_frequency_offset[MAX_NUM_CCs][4]; int split73; char * split73_config; int split73; +int usrp_tx_thread = 0; static void *ru_thread( void *param ); void kill_RU_proc(RU_t *ru) { @@ -1152,6 +1153,7 @@ int restart_L1L2(module_id_t enb_id) { } int main ( int argc, char **argv ) { + //mtrace(); int i; int CC_id = 0; int node_type = ngran_eNB; From f5b81b4eb0a88792fb12ae22c598e70187660741 Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Fri, 3 Jul 2020 15:06:31 +0200 Subject: [PATCH 445/553] CI: fix html tab name Signed-off-by: Raphael Defosseux --- ci-scripts/xml_files/gnb_nr_ue_usrp_run_multi_thread.xml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/ci-scripts/xml_files/gnb_nr_ue_usrp_run_multi_thread.xml b/ci-scripts/xml_files/gnb_nr_ue_usrp_run_multi_thread.xml index ad91807a9b..b4290ae6a3 100644 --- a/ci-scripts/xml_files/gnb_nr_ue_usrp_run_multi_thread.xml +++ b/ci-scripts/xml_files/gnb_nr_ue_usrp_run_multi_thread.xml @@ -21,8 +21,8 @@ --> - run-oai-gnb-nr-ue - Run-gNB-and-NR-UE + run-oai-gnb-nr-ue-tx-write-thread + Run-gNB-and-NR-UE-TX-Write-Thread tasks 2 @@ -32,7 +32,7 @@ Initialize_eNB - Initialize gNB USRP (Multi-Threading enabled) + Initialize gNB USRP (Tx-Write-Threading enabled) -O ci-scripts/conf_files/gnb.band78.tm1.106PRB.usrpn300.conf --phy-test --usrp-tx-thread-config 1 NR From 3f38b447c69399dae7d165222823cc68fcbfcb2d Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Sat, 4 Jul 2020 12:58:18 +0200 Subject: [PATCH 446/553] prachsim functional for format A2 and 0. added format 0 test to CI autotests --- cmake_targets/autotests/test_case_list.xml | 14 ++++++----- openair1/PHY/NR_TRANSPORT/nr_prach.c | 3 +-- openair1/PHY/NR_TRANSPORT/nr_prach_common.c | 2 +- openair1/SIMULATION/NR_PHY/prachsim.c | 23 +++++++++---------- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 3 +++ 5 files changed, 24 insertions(+), 21 deletions(-) diff --git a/cmake_targets/autotests/test_case_list.xml b/cmake_targets/autotests/test_case_list.xml index 346aa8bfef..14435934f5 100644 --- a/cmake_targets/autotests/test_case_list.xml +++ b/cmake_targets/autotests/test_case_list.xml @@ -1299,18 +1299,20 @@ execution - nr_prachsim Test cases. (Test1: 106 PRBs), - (Test2: 217 PRBs), - (Test3: 273 PRBs) + nr_prachsim Test cases. (Test1: 106 PRBs - Prach format A2), + (Test2: 217 PRBs - Prach format A2), + (Test3: 273 PRBs - Prach format A2), + (Test4: 106 PRBs - Prach format 0) $OPENAIR_DIR/cmake_targets/build_oai --phy_simulators -c $OPENAIR_DIR/cmake_targets/autotests/tools/free_mem.bash $OPENAIR_DIR/targets/bin/nr_prachsim.Rel15 - -a -s -30 -n 100 -p 16 -R 106 - -a -s -30 -n 100 -p 16 -R 217 - -a -s -30 -n 100 -p 16 -R 273 + -a -s -30 -n 100 -p 63 -R 106 + -a -s -30 -n 100 -p 63 -R 217 + -a -s -30 -n 100 -p 63 -R 273 + -a -s -30 -n 100 -p 63 -R 106 -c 4 nr_prachsim.test1 nr_prachsim.test2 nr_prachsim.test3 PRACH test OK segmentation fault|assertion|exiting|fatal diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index dc754fb3b0..e4d79822f9 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -752,8 +752,7 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, // check energy in nth time shift, for preamble_shift2 = ((preamble_shift==0) ? 0 : ((preamble_shift< u=%d\n",index,u); inv_u = nr_ZC_inv[u]; // multiplicative inverse of u diff --git a/openair1/SIMULATION/NR_PHY/prachsim.c b/openair1/SIMULATION/NR_PHY/prachsim.c index 2df54ca1cf..2db5bc905c 100644 --- a/openair1/SIMULATION/NR_PHY/prachsim.c +++ b/openair1/SIMULATION/NR_PHY/prachsim.c @@ -339,6 +339,8 @@ int main(int argc, char **argv){ if (config_index<67) { prach_sequence_length=0; slot = subframe*2; slot_gNB = 1+(subframe*2); } + uint16_t N_ZC; + N_ZC = prach_sequence_length == 0 ? 839 : 139; printf("Config_index %d, prach_sequence_length %d\n",config_index,prach_sequence_length); @@ -485,8 +487,8 @@ int main(int argc, char **argv){ prach_config->num_prach_fd_occasions_list[fd_occasion].k1.value = msg1_frequencystart; prach_config->restricted_set_config.value = restrictedSetConfig; prach_config->prach_sequence_length.value = prach_sequence_length; - prach_config->num_prach_fd_occasions_list[fd_occasion].num_root_sequences.value = num_root_sequences; prach_pdu->num_cs = get_NCS(NCS_config, format0, restrictedSetConfig); + prach_config->num_prach_fd_occasions_list[fd_occasion].num_root_sequences.value = 1+(64/(N_ZC/prach_pdu->num_cs)); prach_pdu->prach_format = prach_format; memcpy((void*)&ru->config,(void*)&RC.gNB[0]->gNB_config,sizeof(ru->config)); @@ -525,7 +527,7 @@ int main(int argc, char **argv){ ue_prach_config->prach_sub_c_spacing = mu; ue_prach_config->prach_sequence_length = prach_sequence_length; ue_prach_config->restricted_set_config = restrictedSetConfig; - ue_prach_config->num_prach_fd_occasions_list[fd_occasion].num_root_sequences = num_root_sequences; + ue_prach_config->num_prach_fd_occasions_list[fd_occasion].num_root_sequences = prach_config->num_prach_fd_occasions_list[fd_occasion].num_root_sequences.value ; ue_prach_config->num_prach_fd_occasions_list[fd_occasion].prach_root_sequence_index = rootSequenceIndex; ue_prach_config->num_prach_fd_occasions_list[fd_occasion].k1 = msg1_frequencystart; @@ -601,13 +603,10 @@ int main(int argc, char **argv){ /* tx_lev_dB not used later, no need to set */ //tx_lev_dB = (unsigned int) dB_fixed(tx_lev); - samp_count=0; - for (int s=0; sget_samples_per_slot(s,frame_parms); - - prach_start = samp_count - UE->N_TA_offset; + prach_start = subframe*frame_parms->samples_per_subframe-UE->N_TA_offset; #ifdef NR_PRACH_DEBUG - LOG_M("txsig0.m", "txs0", &txdata[0][prach_start], frame_parms->samples_per_subframe, 1, 1); + LOG_M("txsig0.m", "txs0", &txdata[0][subframe*frame_parms->samples_per_subframe], frame_parms->samples_per_subframe, 1, 1); LOG_M("txsig0_frame.m","txs0", txdata[0],frame_parms->samples_per_frame,1,1); #endif @@ -651,8 +650,8 @@ int main(int argc, char **argv){ rx_prach_start = subframe*frame_parms->samples_per_subframe; if (n_frames==1) printf("slot %d, rx_prach_start %d\n",slot,rx_prach_start); - uint16_t preamble_rx, preamble_energy, N_ZC; - N_ZC = prach_sequence_length == 0 ? 839 : 139; + uint16_t preamble_rx, preamble_energy; + for (SNR=snr0; SNRprach_vars.rxsigF = ru->prach_rxsigF; - + if (n_frames == 1) printf("ncs %d,num_seq %d\n",prach_pdu->num_cs, prach_config->num_prach_fd_occasions_list[fd_occasion].num_root_sequences.value); rx_nr_prach(gNB, prach_pdu, frame, subframe, &preamble_rx, &preamble_energy, &preamble_delay); // printf(" preamble_energy %d preamble_rx %d preamble_tx %d \n", preamble_energy, preamble_rx, preamble_tx); @@ -720,8 +719,8 @@ int main(int argc, char **argv){ #ifdef NR_PRACH_DEBUG LOG_M("prach0.m","prach0", &txdata[0][prach_start], frame_parms->samples_per_subframe, 1, 1); LOG_M("prachF0.m","prachF0", &gNB->prach_vars.prachF[0], N_ZC, 1, 1); - LOG_M("rxsig0.m","rxs0", &gNB->common_vars.rxdata[0][rx_prach_start], frame_parms->samples_per_subframe, 1, 1); - LOG_M("ru_rxsig0.m","rxs0", &ru->common.rxdata[0][rx_prach_start], frame_parms->samples_per_subframe, 1, 1); + LOG_M("rxsig0.m","rxs0", &gNB->common_vars.rxdata[0][subframe*frame_parms->samples_per_subframe], frame_parms->samples_per_subframe, 1, 1); + LOG_M("ru_rxsig0.m","rxs0", &ru->common.rxdata[0][subframe*frame_parms->samples_per_subframe], frame_parms->samples_per_subframe, 1, 1); LOG_M("rxsigF0.m","rxsF0", gNB->prach_vars.rxsigF[0], N_ZC, 1, 1); LOG_M("prach_preamble.m","prachp", &gNB->X_u[0], N_ZC, 1, 1); LOG_M("ue_prach_preamble.m","prachp", &UE->X_u[0], N_ZC, 1, 1); diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index fd45a791c4..8ff0aff5dc 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -52,6 +52,9 @@ const char *prachfmt03[]={"0","1","2","3"}; uint16_t get_NCS(uint8_t index, uint16_t format0, uint8_t restricted_set_config) { + LOG_D(MAC,"get_NCS: indx %d,format0 %d, restriced_set_config %d\n", + index,format0,restricted_set_config); + if (format0 < 3) { switch(restricted_set_config){ case 0: From 2ca4137c1c89b1ea4aefc7ca0e3480b2690c83ae Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Sat, 4 Jul 2020 12:59:08 +0200 Subject: [PATCH 447/553] forgot one line in autotest xml file --- cmake_targets/autotests/test_case_list.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmake_targets/autotests/test_case_list.xml b/cmake_targets/autotests/test_case_list.xml index 14435934f5..802dc9940b 100644 --- a/cmake_targets/autotests/test_case_list.xml +++ b/cmake_targets/autotests/test_case_list.xml @@ -1313,7 +1313,7 @@ -a -s -30 -n 100 -p 63 -R 217 -a -s -30 -n 100 -p 63 -R 273 -a -s -30 -n 100 -p 63 -R 106 -c 4 - nr_prachsim.test1 nr_prachsim.test2 nr_prachsim.test3 + nr_prachsim.test1 nr_prachsim.test2 nr_prachsim.test3 nr_prachsim.test4 PRACH test OK segmentation fault|assertion|exiting|fatal 3 From bea3385f28a90c75b0481ff2d73e2dd901a4a8c4 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Mon, 6 Jul 2020 01:53:46 +0200 Subject: [PATCH 448/553] changes for ulsim to get functionality back. simulation behaviour for PUSCH is not good (BLER waterfall is way too steep even if SNR threshold is ok). Note develop does more or less the same thing but SNR threshold is lower. --- openair1/PHY/CODING/crc_byte.c | 1 + openair1/PHY/MODULATION/nr_modulation.c | 2 + openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c | 3 +- openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c | 2 + openair1/SIMULATION/NR_PHY/ulsim.c | 118 +++++++++++------- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 6 +- 6 files changed, 79 insertions(+), 53 deletions(-) diff --git a/openair1/PHY/CODING/crc_byte.c b/openair1/PHY/CODING/crc_byte.c index 0769ab992a..555f314429 100644 --- a/openair1/PHY/CODING/crc_byte.c +++ b/openair1/PHY/CODING/crc_byte.c @@ -324,6 +324,7 @@ int check_crc(uint8_t* decoded_bytes, uint32_t n, uint32_t F, uint8_t crc_type) AssertFatal(1,"Invalid crc_type \n"); } + if (crc == oldcrc) return(1); else diff --git a/openair1/PHY/MODULATION/nr_modulation.c b/openair1/PHY/MODULATION/nr_modulation.c index b27b692e66..dbfe93adee 100644 --- a/openair1/PHY/MODULATION/nr_modulation.c +++ b/openair1/PHY/MODULATION/nr_modulation.c @@ -34,6 +34,8 @@ void nr_modulation(uint32_t *in, offset = (mod_order==2)? NR_MOD_TABLE_QPSK_OFFSET : (mod_order==4)? NR_MOD_TABLE_QAM16_OFFSET : \ (mod_order==6)? NR_MOD_TABLE_QAM64_OFFSET: (mod_order==8)? NR_MOD_TABLE_QAM256_OFFSET : 0; + LOG_D(PHY,"nr_modulation: length %d, mod_order %d\n",length,mod_order); + for (int i=0; id[0][0],(3*8*Kr_bytes)+12,1,0); + write_output("decoder_in.m","dec",&harq_process->d[0][0],E,1,0); } printf("decoder input(segment %u) :", r); @@ -608,7 +608,6 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB, #endif ret = ulsch->max_ldpc_iterations + 1; } - nb_total_decod++; if (no_iteration_ldpc > ulsch->max_ldpc_iterations){ diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c index 887a3b8a9e..93acda23f8 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c @@ -98,6 +98,8 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, uint8_t thread_id, int gNB_id) { + LOG_D(PHY,"nr_ue_ulsch_procedures hard_id %d %d.%d\n",harq_pid,frame,slot); + uint32_t available_bits, TBS; uint8_t mod_order, cwd_index, num_of_codewords, l; uint32_t scrambled_output[NR_MAX_NB_CODEWORDS][NR_MAX_PDSCH_ENCODED_LENGTH>>5]; diff --git a/openair1/SIMULATION/NR_PHY/ulsim.c b/openair1/SIMULATION/NR_PHY/ulsim.c index e0e7a3c166..0da7db5029 100644 --- a/openair1/SIMULATION/NR_PHY/ulsim.c +++ b/openair1/SIMULATION/NR_PHY/ulsim.c @@ -111,7 +111,7 @@ int main(int argc, char **argv) int i; double SNR, snr0 = -2.0, snr1 = 2.0; double sigma, sigma_dB; - double snr_step = 1; + double snr_step = .2; uint8_t snr1set = 0; int slot = 8, frame = 0; FILE *output_fd = NULL; @@ -127,7 +127,6 @@ int main(int argc, char **argv) SCM_t channel_model = AWGN; //Rayleigh1_anticorr; uint16_t N_RB_DL = 106, N_RB_UL = 106, mu = 1; //unsigned char frame_type = 0; - int frame_length_complex_samples,frame_length_complex_samples_no_prefix; NR_DL_FRAME_PARMS *frame_parms; int loglvl = OAILOG_WARNING; //uint64_t SSB_positions=0x01; @@ -466,8 +465,6 @@ int main(int argc, char **argv) //nr_phy_config_request_sim(gNB, N_RB_DL, N_RB_UL, mu, Nid_cell, SSB_positions); - frame_length_complex_samples = frame_parms->samples_per_subframe; - frame_length_complex_samples_no_prefix = frame_parms->samples_per_subframe_wCP; //configure UE UE = malloc(sizeof(PHY_VARS_NR_UE)); @@ -575,6 +572,7 @@ int main(int argc, char **argv) printf("\n"); + for (int i=0;i<16;i++) printf("%f\n",gaussdouble(0.0,1.0)); for (SNR = snr0; SNR < snr1; SNR += snr_step) { varArray_t *table_rx=initVarArray(1000,sizeof(double)); @@ -709,54 +707,68 @@ int main(int argc, char **argv) available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, number_dmrs_symbols, mod_order, 1); TBS = nr_compute_tbs(mod_order, code_rate, nb_rb, nb_symb_sch, nb_re_dmrs * number_dmrs_symbols, 0, 0, precod_nbr_layers); + pusch_pdu->pusch_data.tb_size = TBS>>3; + ul_config.ul_config_list[0].pusch_config_pdu.pusch_data.tb_size = TBS; + nr_fill_ulsch(gNB,frame,slot,pusch_pdu); + int slot_offset = frame_parms->get_samples_slot_timestamp(slot,frame_parms,0);// - (int)(800*factor); + int slot_length = slot_offset - frame_parms->get_samples_slot_timestamp(slot-1,frame_parms,0); + for (int i=0;i<(TBS>>3);i++) ulsch_ue[0]->harq_processes[harq_pid]->a[i]=i&0xff; if (input_fd == NULL) { - pusch_pdu->pusch_data.tb_size = TBS>>3; - ul_config.ul_config_list[0].pusch_config_pdu.pusch_data.tb_size = TBS; - // set FAPI parameters for UE, put them in the scheduled response and call - nr_ue_scheduled_response(&scheduled_response); - - /////////////////////////phy_procedures_nr_ue_TX/////////////////////// - /////////// - - phy_procedures_nrUE_TX(UE, &UE_proc, gNB_id, 0); - - if (n_trials==1) - LOG_M("txsig0.m","txs0", UE->common_vars.txdata[0],frame_length_complex_samples,1,1); - - /////////// - //////////////////////////////////////////////////// - tx_offset = frame_parms->get_samples_slot_timestamp(slot,frame_parms,0); - - txlev = signal_energy_amp_shift(&UE->common_vars.txdata[0][tx_offset + 5*frame_parms->ofdm_symbol_size + 4*frame_parms->nb_prefix_samples + frame_parms->nb_prefix_samples0], - frame_parms->ofdm_symbol_size + frame_parms->nb_prefix_samples); - - txlev_float = (double)txlev/(double)AMP; // output of signal_energy is fixed point representation - - n_errors = 0; - n_false_positive = 0; - - //AWGN - sigma_dB = 10*log10(txlev_float)-SNR; - sigma = pow(10,sigma_dB/10); - } + if (SNR==snr0) { + // set FAPI parameters for UE, put them in the scheduled response and call + nr_ue_scheduled_response(&scheduled_response); + + + /////////////////////////phy_procedures_nr_ue_TX/////////////////////// + /////////// + + phy_procedures_nrUE_TX(UE, &UE_proc, gNB_id, 0); + + + if (n_trials==1) { + LOG_M("txsig0.m","txs0", UE->common_vars.txdata[0],frame_parms->samples_per_subframe*10,1,1); + LOG_M("txsig0F.m","txs0F", UE->common_vars.txdataF[0],frame_parms->ofdm_symbol_size*14,1,1); + } + /////////// + //////////////////////////////////////////////////// + tx_offset = frame_parms->get_samples_slot_timestamp(slot,frame_parms,0); + + txlev = signal_energy(&UE->common_vars.txdata[0][tx_offset + 5*frame_parms->ofdm_symbol_size + 4*frame_parms->nb_prefix_samples + frame_parms->nb_prefix_samples0], + frame_parms->ofdm_symbol_size + frame_parms->nb_prefix_samples); + + txlev_float = (double)txlev/256; // output of signal_energy is fixed point representation + + + //AWGN + } + } else n_trials = 1; + sigma_dB = 10*log10(txlev_float)-SNR; + sigma = pow(10,sigma_dB/10); + printf("txlev_float %f, sigma_dB %f\n",10*log10(txlev_float),sigma_dB); + + n_errors = 0; + n_false_positive = 0; + + errors_scrambling = 0; + errors_decoding = 0; + + int error_flag; for (trial = 0; trial < n_trials; trial++) { - errors_scrambling = 0; - errors_decoding = 0; - + error_flag = 0; //---------------------------------------------------------- //------------------------ add noise ----------------------- //---------------------------------------------------------- if (input_fd == NULL ) { - for (i=0; inb_antennas_rx; ap++) { - ((short*) gNB->common_vars.rxdata[ap])[(2*i) + (delay*2)] = (((int16_t *)UE->common_vars.txdata[ap])[(i<<1)]) + (int16_t)(sqrt(sigma/2)*gaussdouble(0.0,1.0)); // convert to fixed point - ((short*) gNB->common_vars.rxdata[ap])[2*i+1 + (delay*2)] = (((int16_t *)UE->common_vars.txdata[ap])[(i<<1)+1]) + (int16_t)(sqrt(sigma/2)*gaussdouble(0.0,1.0)); + ((int16_t*) &gNB->common_vars.rxdata[ap][slot_offset])[(2*i) + (delay*2)] = (int16_t)((double)(((int16_t *)&UE->common_vars.txdata[ap][slot_offset])[(i<<1)])/16.0 + (sqrt(sigma/2)*gaussdouble(0.0,1.0))); // convert to fixed point + ((int16_t*) &gNB->common_vars.rxdata[ap][slot_offset])[(2*i)+1 + (delay*2)] = (int16_t)((double)(((int16_t *)&UE->common_vars.txdata[ap][slot_offset])[(i<<1)+1])/16.0 + (sqrt(sigma/2)*gaussdouble(0.0,1.0))); } } } @@ -770,8 +782,6 @@ int main(int argc, char **argv) if (N_RB_DL <217) ta_offset=800; else if (N_RB_DL < 106) ta_offset = 400; - int slot_offset = frame_parms->get_samples_slot_timestamp(slot,frame_parms,0);// - (int)(800*factor); - int slot_length = slot_offset - frame_parms->get_samples_slot_timestamp(slot-1,frame_parms,0); fread((void*)&gNB->common_vars.rxdata[0][slot_offset], sizeof(int16_t), slot_length<<1, @@ -781,7 +791,6 @@ int main(int argc, char **argv) ((int16_t*)&gNB->common_vars.rxdata[0][slot_offset])[i], ((int16_t*)&gNB->common_vars.rxdata[0][slot_offset])[1+i]); fclose(input_fd); - LOG_M("rxsig0.m","rx0",gNB->common_vars.rxdata[0][slot_offset],slot_length,1,1); } //////////////////////////////////////////////////////////// @@ -795,6 +804,8 @@ int main(int argc, char **argv) phy_procedures_gNB_common_RX(gNB, frame, slot); if (n_trials==1) { + LOG_M("rxsig0.m","rx0",&gNB->common_vars.rxdata[0][0],frame_parms->samples_per_subframe*10,1,1); + LOG_M("rxsigF0.m","rxsF0",gNB->common_vars.rxdataF[0]+start_symbol*frame_parms->ofdm_symbol_size,nb_symb_sch*frame_parms->ofdm_symbol_size,1,1); } @@ -813,9 +824,11 @@ int main(int argc, char **argv) //////////////////////////////////////////////////////////// if (gNB->ulsch[0][0]->last_iteration_cnt >= - gNB->ulsch[0][0]->max_ldpc_iterations+1) + gNB->ulsch[0][0]->max_ldpc_iterations+1) { + error_flag = 1; n_errors++; - + } + //---------------------------------------------------------- //----------------- count and print errors ----------------- //---------------------------------------------------------- @@ -847,8 +860,17 @@ int main(int argc, char **argv) errors_decoding++; } } - - if (errors_decoding > 0) { + if (n_trials == 1) { + for (int r=0;rharq_processes[harq_pid]->C;r++) + for (int i=0;iharq_processes[harq_pid]->K>>3;i++) { + if ((ulsch_ue[0]->harq_processes[harq_pid]->c[r][i]^ulsch_gNB->harq_processes[harq_pid]->c[r][i]) != 0) printf("************"); + printf("r %d: in[%d] %x, out[%d] %x (%x)\n",r, + i,ulsch_ue[0]->harq_processes[harq_pid]->c[r][i], + i,ulsch_gNB->harq_processes[harq_pid]->c[r][i], + ulsch_ue[0]->harq_processes[harq_pid]->c[r][i]^ulsch_gNB->harq_processes[harq_pid]->c[r][i]); + } + } + if (errors_decoding > 0 && error_flag == 0) { n_false_positive++; if (n_trials==1) printf("\x1B[31m""[frame %d][trial %d]\tnumber of errors in decoding = %u\n" "\x1B[0m", frame, trial, errors_decoding); @@ -857,12 +879,12 @@ int main(int argc, char **argv) } // trial loop printf("*****************************************\n"); - printf("SNR %f: n_errors (negative CRC) = %d/%d, false_positive %d/%d, errors_scrambling %u/%d\n", SNR, n_errors, n_trials, n_false_positive, n_trials, errors_scrambling, n_trials); + printf("SNR %f: n_errors (negative CRC) = %d/%d, false_positive %d/%d, errors_scrambling %u/%d\n", SNR, n_errors, n_trials, n_false_positive, n_trials, errors_scrambling, available_bits*n_trials); printf("\n"); printf("SNR %f: Channel BLER %e, Channel BER %e\n", SNR,(double)n_errors/n_trials,(double)errors_scrambling/available_bits/n_trials); printf("*****************************************\n"); printf("\n"); - + if (print_perf==1) { printDistribution(&gNB->phy_proc_rx,table_rx,"Total PHY proc rx"); printStatIndent(&gNB->ulsch_channel_estimation_stats,"ULSCH channel estimation time"); diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 6b1ef4eb09..a9bc3447aa 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -382,7 +382,7 @@ int configure_fapi_dl_pdu(int Mod_idP, // antenna ports dci_pdu_rel15[0].antenna_ports.val = 0; // nb of cdm groups w/o data 1 and dmrs port 0 - LOG_I(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n", + LOG_D(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n", dci_pdu_rel15[0].frequency_domain_assignment.val, pdsch_pdu_rel15->rbStart, pdsch_pdu_rel15->rbSize, @@ -452,7 +452,7 @@ int configure_fapi_dl_pdu(int Mod_idP, // Hardcode it for now TBS = dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15.TBSize[0]; - LOG_I(MAC, "DLSCH PDU: start PRB %d n_PRB %d startSymbolAndLength %d start symbol %d nb_symbols %d nb_layers %d nb_codewords %d mcs %d TBS: %d\n", + LOG_D(MAC, "DLSCH PDU: start PRB %d n_PRB %d startSymbolAndLength %d start symbol %d nb_symbols %d nb_layers %d nb_codewords %d mcs %d TBS: %d\n", pdsch_pdu_rel15->rbStart, pdsch_pdu_rel15->rbSize, startSymbolAndLength, @@ -543,7 +543,7 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, NR_sched_pucch *pucch_sched, nfapi_nr_dl_tti_pdsch_pdu_rel15_t *dlsch_config){ - LOG_I(MAC, "In nr_schedule_uss_dlsch_phytest frame %d slot %d\n",frameP,slotP); + LOG_D(MAC, "In nr_schedule_uss_dlsch_phytest frame %d slot %d\n",frameP,slotP); int post_padding = 0, ta_len = 0, header_length_total = 0, sdu_length_total = 0, num_sdus = 0; int lcid, offset, i, header_length_last, TBS_bytes; From 1fee40a5906067a84de2542df8b003b2205fcad0 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Mon, 6 Jul 2020 10:38:36 +0200 Subject: [PATCH 449/553] fix in pucchsim --- openair1/SIMULATION/NR_PHY/pucchsim.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair1/SIMULATION/NR_PHY/pucchsim.c b/openair1/SIMULATION/NR_PHY/pucchsim.c index e1ffe7eb6c..004a7b8de8 100644 --- a/openair1/SIMULATION/NR_PHY/pucchsim.c +++ b/openair1/SIMULATION/NR_PHY/pucchsim.c @@ -479,7 +479,7 @@ int main(int argc, char **argv) for (trial=0; trialofdm_symbol_size*sizeof(int)); if(format==0){ - nr_generate_pucch0(UE,txdataF,frame_parms,UE->pucch_config_dedicated,amp,nr_tti_tx,m0,mcs,nrofSymbols,startingSymbolIndex,startingPRB); + nr_generate_pucch0(UE,txdataF,frame_parms,PUCCH_GroupHopping,hopping_id,amp,nr_tti_tx,m0,mcs,nrofSymbols,startingSymbolIndex,startingPRB); } else if (format == 1){ nr_generate_pucch1(UE,txdataF,frame_parms,UE->pucch_config_dedicated,actual_payload,amp,nr_tti_tx,m0,nrofSymbols,startingSymbolIndex,startingPRB,startingPRB_intraSlotHopping,0,nr_bit); From 62df572aed0d69ee9209fd29b7cb1dd589b6d2b1 Mon Sep 17 00:00:00 2001 From: Cedric Roux Date: Mon, 6 Jul 2020 11:24:55 +0200 Subject: [PATCH 450/553] nr-rlc: small bugfix --- openair2/LAYER2/nr_rlc/nr_rlc_entity_um.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openair2/LAYER2/nr_rlc/nr_rlc_entity_um.c b/openair2/LAYER2/nr_rlc/nr_rlc_entity_um.c index 09f29ebe67..4ef952667d 100644 --- a/openair2/LAYER2/nr_rlc/nr_rlc_entity_um.c +++ b/openair2/LAYER2/nr_rlc/nr_rlc_entity_um.c @@ -588,9 +588,10 @@ static void check_t_reassembly(nr_rlc_entity_um_t *entity) cur = entity->rx_list; while (cur != NULL && sn_compare_rx(entity, cur->sn, entity->rx_next_reassembly) < 0) { - nr_rlc_free_pdu(cur); + nr_rlc_pdu_t *p = cur; cur = cur->next; entity->rx_list = cur; + nr_rlc_free_pdu(p); } if (sn_compare_rx(entity, entity->rx_next_highest, From 64e9629b8ce177a1c9faaff5160b4abc4bfbc530 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Mon, 6 Jul 2020 14:37:31 +0200 Subject: [PATCH 451/553] patch for pucch in ulsim --- cmake_targets/autotests/test_case_list.xml | 8 +++----- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 4 ++-- openair1/SIMULATION/NR_PHY/ulsim.c | 2 ++ 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/cmake_targets/autotests/test_case_list.xml b/cmake_targets/autotests/test_case_list.xml index e110f14c7c..786002e982 100644 --- a/cmake_targets/autotests/test_case_list.xml +++ b/cmake_targets/autotests/test_case_list.xml @@ -1071,9 +1071,9 @@ $OPENAIR_DIR/targets/bin/nr_pbchsim.Rel15 -s0 -S1 -n1000 -R106 -s0 -S1 -n10 -I -R106 - -s0 -S1 -n1000 -R217 + -s0 -S1 -n1000 -R217 -s0 -S1 -n10 -I -R217 - -s0 -S1 -n1000 -R273 + -s0 -S1 -n1000 -R273 -s0 -S1 -n10 -I -R273 nr_pbchsim.test1 nr_pbchsim.test2 nr_pbchsim.test3 nr_pbchsim.test4 nr_pbchsim.test5 nr_pbchsim.test6 PBCH test OK @@ -1114,8 +1114,7 @@ -n100 -e16 -s10 -n100 -s1 -t25 -n100 -s1 -t33 - -n100 -s1 -t50 - + -n100 -s1 -t50 nr_dlsim.test1 nr_dlsim.test2 nr_dlsim.test3 nr_dlsim.test4 nr_dlsim.test5 nr_dlsim.test6 nr_dlsim.test7 nr_dlsim.test8 nr_dlsim.test9 nr_dlsim.test10 nr_dlsim.test11 nr_dlsim.test12 nr_dlsim.test13 PDSCH test OK segmentation fault|assertion|exiting|fatal @@ -1224,7 +1223,6 @@ -R 106 -i 1 -P 2 -b 11 -s6 -n1000 -R 106 -i 1 -P 2 -q8 -b 12 -s-3 -n1000 -R 106 -i 1 -P 2 -q8 -b 19 -s-3 -n1000 - -R 106 -i 1 -P 2 -q8 -b 19 -s-3 -n1000 -R 106 -i 1 -P 2 -q8 -b 32 -s-3 -n1000 -R 106 -i 1 -P 2 -q16 -b 32 -s-3 -n1000 -R 106 -i 1 -P 2 -q16 -b 64 -s-3 -n1000 diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index dae6229657..c40358b8f9 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -2249,13 +2249,13 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, } // UE_mode==PUSCH */ - if (get_softmodem_params()->do_ra==1) { + if (get_softmodem_params()->usim_test==0) { LOG_D(PHY, "Sending PUCCH\n"); pucch_procedures_ue_nr(ue, gNB_id, proc, TRUE); - } + } LOG_D(PHY, "Sending data \n"); nr_ue_pusch_common_procedures(ue, diff --git a/openair1/SIMULATION/NR_PHY/ulsim.c b/openair1/SIMULATION/NR_PHY/ulsim.c index 0da7db5029..8e378709f8 100644 --- a/openair1/SIMULATION/NR_PHY/ulsim.c +++ b/openair1/SIMULATION/NR_PHY/ulsim.c @@ -386,6 +386,8 @@ int main(int argc, char **argv) get_softmodem_params()->phy_test = 1; get_softmodem_params()->do_ra = 0; + get_softmodem_params()->usim_test = 1; + if (snr1set == 0) snr1 = snr0 + 10; From 9a662fbcb34144bc5793edb21a9468924815e9d8 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Mon, 6 Jul 2020 15:36:20 +0200 Subject: [PATCH 452/553] fixed ulsim performance issues --- openair1/SIMULATION/NR_PHY/ulsim.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/openair1/SIMULATION/NR_PHY/ulsim.c b/openair1/SIMULATION/NR_PHY/ulsim.c index 0da7db5029..f4617ea765 100644 --- a/openair1/SIMULATION/NR_PHY/ulsim.c +++ b/openair1/SIMULATION/NR_PHY/ulsim.c @@ -715,6 +715,8 @@ int main(int argc, char **argv) int slot_length = slot_offset - frame_parms->get_samples_slot_timestamp(slot-1,frame_parms,0); for (int i=0;i<(TBS>>3);i++) ulsch_ue[0]->harq_processes[harq_pid]->a[i]=i&0xff; + double scale = 1; + if (input_fd == NULL) { if (SNR==snr0) { @@ -739,7 +741,7 @@ int main(int argc, char **argv) txlev = signal_energy(&UE->common_vars.txdata[0][tx_offset + 5*frame_parms->ofdm_symbol_size + 4*frame_parms->nb_prefix_samples + frame_parms->nb_prefix_samples0], frame_parms->ofdm_symbol_size + frame_parms->nb_prefix_samples); - txlev_float = (double)txlev/256; // output of signal_energy is fixed point representation + txlev_float = (double)txlev/scale; // output of signal_energy is fixed point representation //AWGN @@ -747,6 +749,7 @@ int main(int argc, char **argv) } else n_trials = 1; + sigma_dB = 10*log10(txlev_float)-SNR; sigma = pow(10,sigma_dB/10); printf("txlev_float %f, sigma_dB %f\n",10*log10(txlev_float),sigma_dB); @@ -767,8 +770,8 @@ int main(int argc, char **argv) if (input_fd == NULL ) { for (i=0; inb_antennas_rx; ap++) { - ((int16_t*) &gNB->common_vars.rxdata[ap][slot_offset])[(2*i) + (delay*2)] = (int16_t)((double)(((int16_t *)&UE->common_vars.txdata[ap][slot_offset])[(i<<1)])/16.0 + (sqrt(sigma/2)*gaussdouble(0.0,1.0))); // convert to fixed point - ((int16_t*) &gNB->common_vars.rxdata[ap][slot_offset])[(2*i)+1 + (delay*2)] = (int16_t)((double)(((int16_t *)&UE->common_vars.txdata[ap][slot_offset])[(i<<1)+1])/16.0 + (sqrt(sigma/2)*gaussdouble(0.0,1.0))); + ((int16_t*) &gNB->common_vars.rxdata[ap][slot_offset])[(2*i) + (delay*2)] = (int16_t)((double)(((int16_t *)&UE->common_vars.txdata[ap][slot_offset])[(i<<1)])/sqrt(scale) + (sqrt(sigma/2)*gaussdouble(0.0,1.0))); // convert to fixed point + ((int16_t*) &gNB->common_vars.rxdata[ap][slot_offset])[(2*i)+1 + (delay*2)] = (int16_t)((double)(((int16_t *)&UE->common_vars.txdata[ap][slot_offset])[(i<<1)+1])/sqrt(scale) + (sqrt(sigma/2)*gaussdouble(0.0,1.0))); } } } From cc7c66feea4e25340da4d950dc36bf5130de97f2 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Tue, 7 Jul 2020 15:22:01 +0200 Subject: [PATCH 453/553] Introduce new UE context status state at the eNB for the NSA procedure - UE context status enters RRC_NR_NSA_RECONFIGURED state, after the eNB receives an RRCConnectionReconfigurationComplete message including the scg_ConfigResponseNR_r15 container. - Use this state to avoid triggering sGNB Addition Request multiple times --- openair2/RRC/LTE/rrc_defs.h | 1 + openair2/RRC/LTE/rrc_eNB.c | 67 ++++++++++++++++++------------------- 2 files changed, 33 insertions(+), 35 deletions(-) diff --git a/openair2/RRC/LTE/rrc_defs.h b/openair2/RRC/LTE/rrc_defs.h index 42fa5f6de1..e366061674 100644 --- a/openair2/RRC/LTE/rrc_defs.h +++ b/openair2/RRC/LTE/rrc_defs.h @@ -271,6 +271,7 @@ typedef enum UE_STATE_e { RRC_RECONFIGURED, RRC_HO_EXECUTION, RRC_NR_NSA, + RRC_NR_NSA_RECONFIGURED } UE_STATE_t; typedef enum HO_STATE_e { diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index 12f079f772..cf4b088dd0 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -4613,7 +4613,7 @@ rrc_eNB_process_MeasurementReport( /* TODO: improve NR triggering */ if (measResults2->measId == 7) { - if (ue_context_pP->ue_context.Status != RRC_NR_NSA) { + if ((ue_context_pP->ue_context.Status != RRC_NR_NSA) && (ue_context_pP->ue_context.Status != RRC_NR_NSA_RECONFIGURED)) { MessageDef *msg; ue_context_pP->ue_context.Status = RRC_NR_NSA; @@ -7773,7 +7773,37 @@ rrc_eNB_decode_dcch( LOG_I(RRC, PROTOCOL_RRC_CTXT_UE_FMT" UE State = RRC_HO_EXECUTION (xid %ld)\n", PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP),ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.rrc_TransactionIdentifier); - } else { + } + else if(ue_context_p->ue_context.Status == RRC_NR_NSA){ + //Looking for a condition to trigger S1AP E-RAB-Modification-indication, based on the reception of RRCConnectionReconfigurationComplete + //including NR specific elements. + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension!=NULL) { + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension!=NULL) { + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) { + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) { + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) { + if (ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) { + if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. + nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension + ->scg_ConfigResponseNR_r15!=NULL) { + ue_context_p->ue_context.Status = RRC_NR_NSA_RECONFIGURED; + /*Trigger E-RAB Modification Indication */ + rrc_eNB_send_E_RAB_Modification_Indication(ctxt_pP, ue_context_p); + } + } + } + } + } + } + } + } + else { dedicated_DRB = 0; ue_context_p->ue_context.Status = RRC_RECONFIGURED; LOG_I(RRC, @@ -7783,39 +7813,6 @@ rrc_eNB_decode_dcch( ue_context_p->ue_context.reestablishment_xid = -1; - //Looking for a condition to trigger S1AP E-RAB-Modification-indication, based on the reception of RRCConnectionReconfigurationComplete - //including NR specific elements. Not sure if this is the correct one and the correct placement - /*if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. - nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension-> - scg_ConfigResponseNR_r15->buf!=NULL){ - //Trigger E-RAB Modification Indication - rrc_eNB_send_E_RAB_Modification_Indication(ctxt_pP, ue_context_p); - }*/ - - if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. - nonCriticalExtension!=NULL) { - if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. - nonCriticalExtension->nonCriticalExtension!=NULL) { - if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. - nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) { - if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. - nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) { - if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. - nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) { - if (ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. - nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) { - if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8. - nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension - ->scg_ConfigResponseNR_r15!=NULL) { - /*Trigger E-RAB Modification Indication */ - rrc_eNB_send_E_RAB_Modification_Indication(ctxt_pP, ue_context_p); - } - } - } - } - } - } - } } else { dedicated_DRB = 1; ue_context_p->ue_context.Status = RRC_RECONFIGURED; From 24bdbde2a1d78533ddb4ce0bb83d1d8219ad03d5 Mon Sep 17 00:00:00 2001 From: Rakesh Date: Tue, 7 Jul 2020 16:53:13 +0200 Subject: [PATCH 454/553] bugfix --- common/utils/LOG/vcd_signal_dumper.h | 2 +- common/utils/T/T_messages.txt | 4 ++-- targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/common/utils/LOG/vcd_signal_dumper.h b/common/utils/LOG/vcd_signal_dumper.h index 07fedf917d..601465c628 100644 --- a/common/utils/LOG/vcd_signal_dumper.h +++ b/common/utils/LOG/vcd_signal_dumper.h @@ -532,7 +532,7 @@ typedef enum { VCD_SIGNAL_DUMPER_FUNCTIONS_PSS_SYNCHRO_NR, VCD_SIGNAL_DUMPER_FUNCTIONS_PSS_SEARCH_TIME_NR, VCD_SIGNAL_DUMPER_FUNCTIONS_NR_INITIAL_UE_SYNC, - VCD_SIGNAL_DUMPER_FUNCTIONS_BEAM_GPIO, + VCD_SIGNAL_DUMPER_FUNCTIONS_BEAM_SWITCHING_GPIO, VCD_SIGNAL_DUMPER_FUNCTIONS_END diff --git a/common/utils/T/T_messages.txt b/common/utils/T/T_messages.txt index 272b9af070..d036b40560 100644 --- a/common/utils/T/T_messages.txt +++ b/common/utils/T/T_messages.txt @@ -3490,8 +3490,8 @@ ID = VCD_FUNCTION_NR_INITIAL_UE_SYNC GROUP = ALL:VCD:UE:VCD_FUNCTION FORMAT = int,value VCD_NAME = nr_initial_ue_sync -ID = VCD_SIGNAL_DUMPER_FUNCTIONS_BEAM_GPIO - DESC = VCD function BEAM_GPIO +ID = VCD_FUNCTION_BEAM_SWITCHING_GPIO + DESC = VCD function BEAM_SWITCHING_GPIO GROUP = ALL:VCD:ENB:VCD_FUNCTION FORMAT = int,value VCD_NAME = beam_switching_gpio diff --git a/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp b/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp index 70a8197c7d..1377086e8f 100644 --- a/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp +++ b/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp @@ -420,7 +420,7 @@ static int trx_usrp_write(openair0_device *device, s->tx_md.time_spec = uhd::time_spec_t::from_ticks(timestamp, s->sample_rate); s->tx_count++; -VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_BEAM_GPIO,1); +VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_BEAM_SWITCHING_GPIO,1); // bit 3 enables gpio (for backward compatibility) if (flags_msb&8) { // push GPIO bits 7-9 from flags_msb @@ -429,7 +429,7 @@ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_BEAM_GPIO,1) s->usrp->set_gpio_attr("FP0", "OUT", gpio789, 0x380); s->usrp->clear_command_time(); } -VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_BEAM_GPIO,0); +VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_BEAM_SWITCHING_GPIO,0); if (cc>1) { std::vector buff_ptrs; From 614af99745cadb58e701c69b0b0f3579187a3ecd Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Tue, 7 Jul 2020 18:36:58 +0200 Subject: [PATCH 455/553] Remove hardcoding of DRB id to be added for NSA --- openair2/RRC/LTE/rrc_eNB.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index cf4b088dd0..1d44751dca 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -4636,7 +4636,7 @@ rrc_eNB_process_MeasurementReport( for (int e_rab=0; e_rab < X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded; e_rab++) { X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].e_rab_id = ue_context_pP->ue_context.e_rab[e_rab].param.e_rab_id; X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].gtp_teid = ue_context_pP->ue_context.e_rab[e_rab].param.gtp_teid; - X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].drb_ID = 1; + X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].drb_ID = ue_context_pP->ue_context.DRB_configList->list.array[e_rab]->drb_Identity; memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr, &ue_context_pP->ue_context.e_rab[e_rab].param.sgw_addr, sizeof(transport_layer_addr_t)); From 5fc3a991c91ac117c10b6a5e268f2441b6015cb8 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Wed, 8 Jul 2020 18:44:34 +0200 Subject: [PATCH 456/553] dci size for 0_1 and some other modifications --- openair2/LAYER2/NR_MAC_COMMON/nr_mac.h | 4 +- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 232 +++++++++++++++++- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h | 5 +- .../NR_MAC_UE/nr_ue_dci_configuration.c | 4 +- openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 2 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 2 +- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 154 ++++++++---- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 34 ++- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 12 +- openair2/RRC/NR/rrc_gNB_reconfig.c | 14 +- 10 files changed, 389 insertions(+), 74 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h index 591c2448b8..d8583167dd 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h @@ -251,9 +251,8 @@ typedef struct { uint8_t short_messages; //8 bits uint8_t tb_scaling; //2 bits uint8_t pucch_resource_indicator; //3 bits - uint8_t dmrs_sequence_initialization; //1 bit uint8_t system_info_indicator; //1 bit - + uint8_t ulsch_indicator; uint8_t slot_format_indicator_count; uint8_t *slot_format_indicators; @@ -290,6 +289,7 @@ typedef struct { dci_field_t cloded_loop_indicator; //variable dci_field_t ul_sul_indicator; //variable dci_field_t antenna_ports; //variable + dci_field_t dmrs_sequence_initialization; dci_field_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits } dci_pdu_rel15_t; diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index 8ff0aff5dc..a4097e4d32 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -31,6 +31,7 @@ */ #include "LAYER2/NR_MAC_gNB/mac_proto.h" +#include const uint8_t nr_slots_per_frame[5] = {10, 20, 40, 80, 160}; @@ -1879,7 +1880,8 @@ uint8_t get_K_ptrs(uint16_t nrb0, uint16_t nrb1, uint16_t N_RB) { return 1; } -uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, +uint16_t nr_dci_size(NR_ServingCellConfigCommon_t *scc, + NR_CellGroupConfig_t *secondaryCellGroup, dci_pdu_rel15_t *dci_pdu, nr_dci_format_t format, nr_rnti_type_t rnti_type, @@ -1887,9 +1889,15 @@ uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, int bwp_id) { uint16_t size = 0; + uint16_t numRBG = 0; + long rbg_size_config; + int num_entries = 0; + int pusch_antenna_ports = 1; // TODO hardcoded number of antenna ports for pusch NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[bwp_id-1]; NR_PDSCH_Config_t *pdsch_config = bwp->bwp_Dedicated->pdsch_Config->choice.setup; + NR_PUSCH_Config_t *pusch_Config = ubwp->bwp_Dedicated->pusch_Config->choice.setup; + NR_SRS_Config_t *srs_config = ubwp->bwp_Dedicated->srs_Config->choice.setup; switch(format) { /*Only sizes for 0_0 and 1_0 are correct at the moment*/ @@ -1897,30 +1905,197 @@ uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, /// fixed: Format identifier 1, Hop flag 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2 Time Domain assgnmt 4 --20 size += 20; size += (uint8_t)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); // Freq domain assignment -- hopping scenario to be updated - size += nr_dci_size(secondaryCellGroup,dci_pdu,NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB, bwp_id) - size; // Padding to match 1_0 size + size += nr_dci_size(scc,secondaryCellGroup,dci_pdu,NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB, bwp_id) - size; // Padding to match 1_0 size // UL/SUL indicator assumed to be 0 break; case NR_UL_DCI_FORMAT_0_1: - /// fixed: Format identifier 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2, SRS request 2 --17 - size += 17; + /// fixed: Format identifier 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2, ULSCH indicator 1 --16 + size += 16; // Carrier indicator + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig != NULL) { + dci_pdu->carrier_indicator.nbits=3; + size += dci_pdu->carrier_indicator.nbits; + } // UL/SUL indicator + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->supplementaryUplink != NULL) { + dci_pdu->carrier_indicator.nbits=1; + size += dci_pdu->ul_sul_indicator.nbits; + } // BWP Indicator + uint8_t n_ul_bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.count; + if (n_ul_bwp < 2) + dci_pdu->bwp_indicator.nbits = n_ul_bwp; + else + dci_pdu->bwp_indicator.nbits = 2; + size += dci_pdu->bwp_indicator.nbits; // Freq domain assignment + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->initialUplinkBWP->pusch_Config->choice.setup->rbg_Size != NULL) + rbg_size_config = 1; + else + rbg_size_config = 0; + numRBG = getNRBG(NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275), + NRRIV2PRBOFFSET(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275), + rbg_size_config); + if (pusch_Config->resourceAllocation == 0) + dci_pdu->frequency_domain_assignment.nbits = numRBG; + else if (pusch_Config->resourceAllocation == 1) + dci_pdu->frequency_domain_assignment.nbits = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + else + dci_pdu->frequency_domain_assignment.nbits = ((int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )>numRBG) ? (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )+1 : numRBG+1; + size += dci_pdu->frequency_domain_assignment.nbits; // Time domain assignment - // VRB to PRB mapping + if (pusch_Config->pusch_TimeDomainAllocationList==NULL) { + if (ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList==NULL) + num_entries = 16; // num of entries in default table + else + num_entries = ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.count; + } + else + num_entries = pusch_Config->pusch_TimeDomainAllocationList->choice.setup->list.count; + dci_pdu->time_domain_assignment.nbits = (int)ceil(log2(num_entries)); + size += dci_pdu->time_domain_assignment.nbits; // Frequency Hopping flag + if ((pusch_Config->frequencyHopping!=NULL) && (pusch_Config->resourceAllocation != NR_PUSCH_Config__resourceAllocation_resourceAllocationType0)) { + dci_pdu->frequency_hopping_flag.nbits = 1; + size += 1; + } // 1st DAI + if (secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook==NR_PhysicalCellGroupConfig__pdsch_HARQ_ACK_Codebook_dynamic) + dci_pdu->dai[0].nbits = 2; + else + dci_pdu->dai[0].nbits = 1; + size += dci_pdu->dai[0].nbits; // 2nd DAI + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission != NULL) { //TODO not sure about that + dci_pdu->dai[1].nbits = 2; + size += dci_pdu->dai[1].nbits; + } // SRS resource indicator + if (pusch_Config->txConfig != NULL){ + int count=0; + if (*pusch_Config->txConfig == NR_PUSCH_Config__txConfig_codebook){ + for (int i=0; isrs_ResourceSetToAddModList->list.count; i++) { + if (srs_config->srs_ResourceSetToAddModList->list.array[i]->usage == NR_SRS_ResourceSet__usage_codebook) + count++; + } + if (count>1) + dci_pdu->srs_resource_indicator.nbits = 1; + } + else { + int lmin,Lmax = 0; + int lsum = 0; + if ( secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig != NULL) { + if ( secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig->choice.setup->ext1->maxMIMO_Layers != NULL) + Lmax = *secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig->choice.setup->ext1->maxMIMO_Layers; + else + AssertFatal(1==0,"MIMO on PUSCH not supported, maxMIMO_Layers needs to be set to 1\n"); + } + else + AssertFatal(1==0,"MIMO on PUSCH not supported, maxMIMO_Layers needs to be set to 1\n"); + for (int i=0; isrs_ResourceSetToAddModList->list.count; i++) { + if (srs_config->srs_ResourceSetToAddModList->list.array[i]->usage == NR_SRS_ResourceSet__usage_nonCodebook) + count++; + if (count < Lmax) lmin = count; + else lmin = Lmax; + for (int k=1;k<=lmin;k++) { + lsum += binomial(count,k); + } + } + dci_pdu->srs_resource_indicator.nbits = (int)ceil(log2(lsum)); + } + } + size += dci_pdu->srs_resource_indicator.nbits; // Precoding info and number of layers + long transformPrecoder; + if (pusch_Config->transformPrecoder == NULL){ + // if transform precoder is null, apply the values from msg3 + if(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder == NULL) + transformPrecoder = 1; + else + transformPrecoder = 0; + } + else + transformPrecoder = *pusch_Config->transformPrecoder; + if (pusch_Config->txConfig != NULL){ + if (*pusch_Config->txConfig == NR_PUSCH_Config__txConfig_codebook){ + if (pusch_antenna_ports > 1) { + if (pusch_antenna_ports == 4) { + if ((transformPrecoder == NR_PUSCH_Config__transformPrecoder_disabled) && (*pusch_Config->maxRank>1)) + dci_pdu->precoding_information.nbits = 6-(*pusch_Config->codebookSubset); + else { + if(*pusch_Config->codebookSubset == NR_PUSCH_Config__codebookSubset_nonCoherent) + dci_pdu->precoding_information.nbits = 2; + else + dci_pdu->precoding_information.nbits = 5-(*pusch_Config->codebookSubset); + } + } + else { + AssertFatal(pusch_antenna_ports==2,"Not valid number of antenna ports"); + if ((transformPrecoder == NR_PUSCH_Config__transformPrecoder_disabled) && (*pusch_Config->maxRank==2)) + dci_pdu->precoding_information.nbits = 4-(*pusch_Config->codebookSubset); + else + dci_pdu->precoding_information.nbits = 3-(*pusch_Config->codebookSubset); + } + } + } + } + size += dci_pdu->precoding_information.nbits; // Antenna ports + NR_DMRS_UplinkConfig_t *NR_DMRS_UplinkConfig = NULL; + int xa=0; + int xb=0; + if(pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA != NULL){ + NR_DMRS_UplinkConfig = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA->choice.setup; + xa = ul_ant_bits(NR_DMRS_UplinkConfig,transformPrecoder); + } + if(pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB != NULL){ + NR_DMRS_UplinkConfig = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup; + xb = ul_ant_bits(NR_DMRS_UplinkConfig,transformPrecoder); + } + if (xa>xb) + dci_pdu->antenna_ports.nbits = xa; + else + dci_pdu->antenna_ports.nbits = xb; + size += dci_pdu->antenna_ports.nbits; + // SRS request + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->supplementaryUplink==NULL) + dci_pdu->srs_request.nbits = 2; + else + dci_pdu->srs_request.nbits = 3; + size += dci_pdu->srs_request.nbits; // CSI request + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig != NULL) { + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup->reportTriggerSize != NULL) { + dci_pdu->csi_request.nbits = *secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup->reportTriggerSize; + size += dci_pdu->csi_request.nbits; + } + } // CBGTI + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig->choice.setup->codeBlockGroupTransmission != NULL) { + int num = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig->choice.setup->codeBlockGroupTransmission->choice.setup->maxCodeBlockGroupsPerTransportBlock; + dci_pdu->cbgti.nbits = 2 + (num<<1); + size += dci_pdu->cbgti.nbits; + } // PTRS - DMRS association + if ( (NR_DMRS_UplinkConfig->phaseTrackingRS == NULL && transformPrecoder == NR_PUSCH_Config__transformPrecoder_disabled) || + transformPrecoder == NR_PUSCH_Config__transformPrecoder_enabled || (*pusch_Config->maxRank==1) ) + dci_pdu->ptrs_dmrs_association.nbits = 0; + else + dci_pdu->ptrs_dmrs_association.nbits = 2; + size += dci_pdu->ptrs_dmrs_association.nbits; // beta offset indicator + if (pusch_Config->uci_OnPUSCH!=NULL){ + if (pusch_Config->uci_OnPUSCH->choice.setup->betaOffsets->present == NR_UCI_OnPUSCH__betaOffsets_PR_dynamic) { + dci_pdu->beta_offset_indicator.nbits = 2; + size += dci_pdu->beta_offset_indicator.nbits; + } + } // DMRS sequence init + if (transformPrecoder == NR_PUSCH_Config__transformPrecoder_disabled) { + dci_pdu->dmrs_sequence_initialization.nbits = 1; + size += dci_pdu->dmrs_sequence_initialization.nbits; + } break; case NR_DL_DCI_FORMAT_1_0: @@ -1946,10 +2121,10 @@ uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, dci_pdu->bwp_indicator.nbits = 2; size += dci_pdu->bwp_indicator.nbits; // Freq domain assignment - long rbg_size_config = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rbg_Size; - uint16_t numRBG = getNRBG(NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275), - NRRIV2PRBOFFSET(bwp->bwp_Common->genericParameters.locationAndBandwidth,275), - rbg_size_config); + rbg_size_config = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rbg_Size; + numRBG = getNRBG(NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275), + NRRIV2PRBOFFSET(bwp->bwp_Common->genericParameters.locationAndBandwidth,275), + rbg_size_config); if (pdsch_config->resourceAllocation == 0) dci_pdu->frequency_domain_assignment.nbits = numRBG; else if (pdsch_config->resourceAllocation == 1) @@ -1958,7 +2133,6 @@ uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, dci_pdu->frequency_domain_assignment.nbits = ((int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )>numRBG) ? (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )+1 : numRBG+1; size += dci_pdu->frequency_domain_assignment.nbits; // Time domain assignment (see table 5.1.2.1.1-1 in 38.214 - int num_entries; if (pdsch_config->pdsch_TimeDomainAllocationList==NULL) { if (bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList==NULL) num_entries = 16; // num of entries in default table @@ -2068,6 +2242,27 @@ uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, return size; } +int ul_ant_bits(NR_DMRS_UplinkConfig_t *NR_DMRS_UplinkConfig, long transformPrecoder) { + + uint8_t type,maxl; + if(NR_DMRS_UplinkConfig->dmrs_Type == NULL) + type = 1; + else + type = 2; + if(NR_DMRS_UplinkConfig->maxLength == NULL) + maxl = 1; + else + maxl = 2; + if (transformPrecoder == NR_PUSCH_Config__transformPrecoder_disabled) + return( maxl+type+1); + else { + if (type==1) + return (maxl<<1); + else + AssertFatal(1==0,"DMRS type not valid for this choice"); + } +} + int tdd_period_to_num[8] = {500,625,1000,1250,2000,2500,5000,10000}; int is_nr_DL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slot) { @@ -2208,3 +2403,20 @@ int16_t fill_dmrs_mask(NR_PDSCH_Config_t *pdsch_Config,int dmrs_TypeA_Position,i AssertFatal(1==0,"Shouldn't get here\n"); return(-1); } + + +int binomial(int n, int k) { + int c = 1, i; + + if (k > n-k) + k = n-k; + + for (i = 1; i <= k; i++, n--) { + if (c/i > UINT_MAX/n) // return 0 on overflow + return 0; + + c = c / i * n + c % i * n / i; + } + return c; +} + diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h index 2f7f144983..a5e38bf128 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h @@ -77,7 +77,8 @@ int is_nr_DL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP); int is_nr_UL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP); -uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup, +uint16_t nr_dci_size(NR_ServingCellConfigCommon_t *scc, + NR_CellGroupConfig_t *secondaryCellGroup, dci_pdu_rel15_t *dci_pdu, nr_dci_format_t format, nr_rnti_type_t rnti_type, @@ -103,6 +104,8 @@ uint8_t compute_nr_root_seq(NR_RACH_ConfigCommon_t *rach_config, uint8_t nb_preambles, uint8_t unpaired); +int ul_ant_bits(NR_DMRS_UplinkConfig_t *NR_DMRS_UplinkConfig,long transformPrecoder); + int get_format0(uint8_t index, uint8_t unpaired); uint16_t get_NCS(uint8_t index, uint16_t format, uint8_t restricted_set_config); diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c index a79b4083e3..53263747fc 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c @@ -223,7 +223,7 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl rel15->BWPSize = NRRIV2BW(initialDownlinkBWP->genericParameters.locationAndBandwidth, 275); rel15->BWPStart = NRRIV2PRBOFFSET(bwp_Common->genericParameters.locationAndBandwidth, 275); // NRRIV2PRBOFFSET(initialDownlinkBWP->genericParameters.locationAndBandwidth, 275); rel15->SubcarrierSpacing = initialDownlinkBWP->genericParameters.subcarrierSpacing; - rel15->dci_length = nr_dci_size(mac->scg,def_dci_pdu_rel15,rel15->dci_format,NR_RNTI_C,rel15->BWPSize,bwp_id); + rel15->dci_length = nr_dci_size(scc,mac->scg,def_dci_pdu_rel15,rel15->dci_format,NR_RNTI_C,rel15->BWPSize,bwp_id); for (int i = 0; i < sps; i++) if ((monitoringSymbolsWithinSlot >> (sps - 1 - i)) & 1) { rel15->coreset.StartSymbolIndex = i; @@ -243,7 +243,7 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl rel15->BWPSize = NRRIV2BW(bwp_Common->genericParameters.locationAndBandwidth, 275); rel15->BWPStart = NRRIV2PRBOFFSET(bwp_Common->genericParameters.locationAndBandwidth, 275); rel15->SubcarrierSpacing = bwp_Common->genericParameters.subcarrierSpacing; - rel15->dci_length = nr_dci_size(mac->scg,def_dci_pdu_rel15,rel15->dci_format,NR_RNTI_C,rel15->BWPSize,bwp_id); + rel15->dci_length = nr_dci_size(scc,mac->scg,def_dci_pdu_rel15,rel15->dci_format,NR_RNTI_C,rel15->BWPSize,bwp_id); // get UE-specific search space for (ss_id = 0; ss_id < FAPI_NR_MAX_SS_PER_CORESET && mac->SSpace[0][0][ss_id] != NULL; ss_id++){ uss = mac->SSpace[0][0][ss_id]; diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 163855a093..2f264d9c7e 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -3530,7 +3530,7 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac, dci_pdu_rel15->cbgfi.val = (*dci_pdu>>(dci_size-pos))&((1<cbgfi.nbits)-1); // DMRS sequence init pos+=1; - dci_pdu_rel15->dmrs_sequence_initialization = (*dci_pdu>>(dci_size-pos))&0x1; + dci_pdu_rel15->dmrs_sequence_initialization.val = (*dci_pdu>>(dci_size-pos))&0x1; break; } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index db93734a7d..2eb4ad498b 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -688,7 +688,7 @@ void nr_generate_Msg2(module_id_t module_idP, pdcch_pdu_rel15->StartSymbolIndex, pdcch_pdu_rel15->DurationSymbols); - fill_dci_pdu_rel15(secondaryCellGroup,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types,dci10_bw,ra->bwp_id); + fill_dci_pdu_rel15(scc,secondaryCellGroup,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types,dci10_bw,ra->bwp_id); dl_req->nPDUs+=2; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index a9bc3447aa..e9fbdf489c 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -329,7 +329,7 @@ int configure_fapi_dl_pdu(int Mod_idP, pdsch_pdu_rel15->rbStart = (rbStart!=NULL) ? *rbStart : 0; pdsch_pdu_rel15->rbSize = (rbSize!=NULL) ? *rbSize : pdsch_pdu_rel15->BWPSize; pdsch_pdu_rel15->VRBtoPRBMapping = 1; // non-interleaved, check if this is ok for initialBWP - // choose shortest PDSCH + int startSymbolAndLength=0; int time_domain_assignment=2; int StartSymbolIndex,NrOfSymbols; @@ -362,10 +362,10 @@ int configure_fapi_dl_pdu(int Mod_idP, AssertFatal(1==0,"Only frequency resource allocation type 1 is currently supported\n"); // time domain assignment dci_pdu_rel15[0].time_domain_assignment.val = time_domain_assignment; // row index used here instead of SLIV; - // mcs ndi and rv + // mcs and rv dci_pdu_rel15[0].mcs = pdsch_pdu_rel15->mcsIndex[0]; dci_pdu_rel15[0].rv = pdsch_pdu_rel15->rvIndex[0]; - // harq pid + // harq pid and ndi dci_pdu_rel15[0].harq_pid = current_harq_pid; dci_pdu_rel15[0].ndi = UE_list->UE_sched_ctrl[UE_id].harq_processes[current_harq_pid].ndi; // DAI @@ -381,7 +381,8 @@ int configure_fapi_dl_pdu(int Mod_idP, UE_list->UE_sched_ctrl[UE_id].harq_processes[current_harq_pid].is_waiting = 1; // antenna ports dci_pdu_rel15[0].antenna_ports.val = 0; // nb of cdm groups w/o data 1 and dmrs port 0 - + // dmrs sequence initialization + dci_pdu_rel15[0].dmrs_sequence_initialization.val = pdsch_pdu_rel15->SCID; LOG_D(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n", dci_pdu_rel15[0].frequency_domain_assignment.val, pdsch_pdu_rel15->rbStart, @@ -436,7 +437,7 @@ int configure_fapi_dl_pdu(int Mod_idP, rnti_types[0] = NR_RNTI_C; - fill_dci_pdu_rel15(secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types,pdsch_pdu_rel15->BWPSize,bwp_id); + fill_dci_pdu_rel15(scc,secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types,pdsch_pdu_rel15->BWPSize,bwp_id); LOG_D(MAC, "DCI params: rnti %x, rnti_type %d, dci_format %d\n \ coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n", @@ -466,22 +467,69 @@ int configure_fapi_dl_pdu(int Mod_idP, return TBS; //Return TBS in bytes } -void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types) { +void config_uldci(NR_BWP_Uplink_t *ubwp, + nfapi_nr_pusch_pdu_t *pusch_pdu, + nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, + dci_pdu_rel15_t *dci_pdu_rel15, + int *dci_formats, int *rnti_types, + int n_ubwp, int bwp_id) { - dci_pdu_rel15->frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size, - pusch_pdu->rb_start, - NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275)); + switch(dci_formats[(pdcch_pdu_rel15->numDlDci)-1]) { + case NR_UL_DCI_FORMAT_0_0: + dci_pdu_rel15->frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size, + pusch_pdu->rb_start, + NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275)); + + dci_pdu_rel15->time_domain_assignment.val = 2; // row index used here instead of SLIV; + dci_pdu_rel15->frequency_hopping_flag.val = pusch_pdu->frequency_hopping; + dci_pdu_rel15->mcs = 9; + + dci_pdu_rel15->format_indicator = 0; + dci_pdu_rel15->ndi = 1; + dci_pdu_rel15->rv = 0; + dci_pdu_rel15->harq_pid = 0; + dci_pdu_rel15->tpc = 2; + break; + case NR_UL_DCI_FORMAT_0_1: + dci_pdu_rel15->ndi = pusch_pdu->pusch_data.new_data_indicator; + dci_pdu_rel15->rv = pusch_pdu->pusch_data.rv_index; + dci_pdu_rel15->harq_pid = pusch_pdu->pusch_data.harq_process_id; + dci_pdu_rel15->frequency_hopping_flag.val = pusch_pdu->frequency_hopping; + //dci_pdu_rel15->dai[0].val = ???; //TODO + // bwp indicator + if (n_ubwp < 4) + dci_pdu_rel15->bwp_indicator.val = bwp_id; + else + dci_pdu_rel15->bwp_indicator.val = bwp_id - 1; // as per table 7.3.1.1.2-1 in 38.212 + // frequency domain assignment + if (ubwp->bwp_Dedicated->pusch_Config->choice.setup->resourceAllocation==NR_PUSCH_Config__resourceAllocation_resourceAllocationType1) + dci_pdu_rel15->frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size, + pusch_pdu->rb_start, + NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275)); + else + AssertFatal(1==0,"Only frequency resource allocation type 1 is currently supported\n"); + // time domain assignment + dci_pdu_rel15->time_domain_assignment.val = 2; + // mcs + dci_pdu_rel15->mcs = pusch_pdu->mcs_index; + // tpc command for pusch + dci_pdu_rel15->tpc = 2; //TODO + // SRS resource indicator + if (ubwp->bwp_Dedicated->pusch_Config->choice.setup->txConfig != NULL) { + if (*ubwp->bwp_Dedicated->pusch_Config->choice.setup->txConfig == NR_PUSCH_Config__txConfig_codebook) + dci_pdu_rel15->srs_resource_indicator.val = 0; // taking resource 0 for SRS + else + AssertFatal(1==0,"Non Codebook configuration non supported\n"); + } + // Antenna Ports + dci_pdu_rel15->antenna_ports.val = 0; // TODO for now it is hardcoded, it should depends on cdm group no data and rank + // DMRS sequence initialization + dci_pdu_rel15->dmrs_sequence_initialization.val = pusch_pdu->scid; + break; + default : + AssertFatal(1==0,"Valid UL formats are 0_0 and 0_1 \n"); + } - dci_pdu_rel15->time_domain_assignment.val = 2; // row index used here instead of SLIV; - dci_pdu_rel15->frequency_hopping_flag.val = 0; - dci_pdu_rel15->mcs = 9; - - dci_pdu_rel15->format_indicator = 0; - dci_pdu_rel15->ndi = 1; - dci_pdu_rel15->rv = 0; - dci_pdu_rel15->harq_pid = 0; - dci_pdu_rel15->tpc = 2; - LOG_D(MAC, "[gNB scheduler phytest] ULDCI type 0 payload: PDCCH CCEIndex %d, freq_alloc %d, time_alloc %d, freq_hop_flag %d, mcs %d tpc %d ndi %d rv %d\n", pdcch_pdu_rel15->dci_pdu.CceIndex[pdcch_pdu_rel15->numDlDci], dci_pdu_rel15->frequency_domain_assignment.val, @@ -491,10 +539,6 @@ void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr dci_pdu_rel15->tpc, dci_pdu_rel15->ndi, dci_pdu_rel15->rv); - - dci_formats[pdcch_pdu_rel15->numDlDci] = NR_UL_DCI_FORMAT_0_0; - rnti_types[pdcch_pdu_rel15->numDlDci] = NR_RNTI_C; - pdcch_pdu_rel15->numDlDci++; } @@ -736,7 +780,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; int bwp_id=1; - + int mu = scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.subcarrierSpacing; int UE_id = 0; NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list; AssertFatal(UE_list->active[UE_id] >=0,"Cannot find UE_id %d is not active\n",UE_id); @@ -746,7 +790,9 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, "downlinkBWP_ToAddModList has %d BWP!\n", secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count); NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[bwp_id-1]; + int n_ubwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.count; NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; + NR_PUSCH_Config_t *pusch_Config = ubwp->bwp_Dedicated->pusch_Config->choice.setup; nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[Mod_idP]->UL_tti_req[0]; nfapi_nr_ul_dci_request_t *UL_dci_req = &RC.nrmac[Mod_idP]->UL_dci_req[0]; @@ -767,20 +813,27 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, LOG_D(MAC, "Scheduling UE specific PUSCH\n"); //UL_tti_req = &nr_mac->UL_tti_req[CC_id]; - /* - // original configuration - rel15_ul->rnti = 0x1234; - rel15_ul->ulsch_pdu_rel15.start_rb = 30; - rel15_ul->ulsch_pdu_rel15.number_rbs = 50; - rel15_ul->ulsch_pdu_rel15.start_symbol = 2; - rel15_ul->ulsch_pdu_rel15.number_symbols = 12; - rel15_ul->ulsch_pdu_rel15.nb_re_dmrs = 6; - rel15_ul->ulsch_pdu_rel15.length_dmrs = 1; - rel15_ul->ulsch_pdu_rel15.Qm = 2; - rel15_ul->ulsch_pdu_rel15.mcs = 9; - rel15_ul->ulsch_pdu_rel15.rv = 0; - rel15_ul->ulsch_pdu_rel15.n_layers = 1; - */ + + //Resource Allocation in time domain + int startSymbolAndLength=0; + int time_domain_assignment=1; + int StartSymbolIndex,NrOfSymbols,K2,mapping_type; + + AssertFatal(time_domain_assignmentbwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.count, + "time_domain_assignment %d>=%d\n",time_domain_assignment,ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.count); + startSymbolAndLength = ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[time_domain_assignment]->startSymbolAndLength; + SLIV2SL(startSymbolAndLength,&StartSymbolIndex,&NrOfSymbols); + pusch_pdu->start_symbol_index = StartSymbolIndex; + pusch_pdu->nr_of_symbols = NrOfSymbols; + mapping_type = ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[time_domain_assignment]->mappingType; + if (ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[time_domain_assignment]->k2 != NULL) + K2 = *ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[time_domain_assignment]->k2; + else { + if (mu<2) K2=1; + else if(mu==2) K2=2; + else K2=3; + } + pusch_pdu->pdu_bit_map = PUSCH_PDU_BITMAP_PUSCH_DATA; pusch_pdu->rnti = rnti; pusch_pdu->handle = 0; //not yet used @@ -800,17 +853,22 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, pusch_pdu->nrOfLayers = 1; //Pusch Allocation in frequency domain [TS38.214, sec 6.1.2.2] - pusch_pdu->resource_alloc = 1; //type 1 - //pusch_pdu->rb_bitmap;// for ressource alloc type 0 - pusch_pdu->rb_start = 0; - pusch_pdu->rb_size = 50; + if (pusch_Config->resourceAllocation==NR_PUSCH_Config__resourceAllocation_resourceAllocationType1) { + pusch_pdu->resource_alloc = 1; //type 1 + pusch_pdu->rb_start = 0; + pusch_pdu->rb_size = 50; + } + else + AssertFatal(1==0,"Only frequency resource allocation type 1 is currently supported\n"); + pusch_pdu->vrb_to_prb_mapping = 0; - pusch_pdu->frequency_hopping = 0; + if (pusch_Config->frequencyHopping==NULL) + pusch_pdu->frequency_hopping = 0; + else + pusch_pdu->frequency_hopping = 1; //pusch_pdu->tx_direct_current_location;//The uplink Tx Direct Current location for the carrier. Only values in the value range of this field between 0 and 3299, which indicate the subcarrier index within the carrier corresponding 1o the numerology of the corresponding uplink BWP and value 3300, which indicates "Outside the carrier" and value 3301, which indicates "Undetermined position within the carrier" are used. [TS38.331, UplinkTxDirectCurrentBWP IE] pusch_pdu->uplink_frequency_shift_7p5khz = 0; - //Resource Allocation in time domain - pusch_pdu->start_symbol_index = 2; - pusch_pdu->nr_of_symbols = 12; + // -------------------- // ------- DMRS ------- @@ -934,8 +992,8 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, } else { dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET]; - config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); - fill_dci_pdu_rel15(secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types,pusch_pdu->bwp_size,bwp_id); + config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types,n_ubwp,bwp_id); + fill_dci_pdu_rel15(scc,secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types,pusch_pdu->bwp_size,bwp_id); } } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 44f4edd3ea..8253dbc4be 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -734,6 +734,19 @@ void prepare_dci(NR_CellGroupConfig_t *secondaryCellGroup, NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; switch(format) { + case NR_UL_DCI_FORMAT_0_1: + // format indicator + dci_pdu_rel15->format_indicator = 0; + // carrier indicator + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig != NULL) + AssertFatal(1==0,"Cross Carrier Scheduling Config currently not supported\n"); + // supplementary uplink + if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->supplementaryUplink != NULL) + AssertFatal(1==0,"Supplementary Uplink currently not supported\n"); + // SRS request + dci_pdu_rel15->srs_request.val = 0; + dci_pdu_rel15->ulsch_indicator = 1; + break; case NR_DL_DCI_FORMAT_1_1: // format indicator dci_pdu_rel15->format_indicator = 1; @@ -782,16 +795,15 @@ void prepare_dci(NR_CellGroupConfig_t *secondaryCellGroup, // CBGTI and CBGFI if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission != NULL) AssertFatal(1==0,"CBG transmission currently not supported\n"); - // dmrs sequence initialization - dci_pdu_rel15->dmrs_sequence_initialization = 0; // FIXME no information on what this bit should be in 38.212 break; default : - AssertFatal(1==0,"Prepare dci currently only implemented for 1_1 \n"); + AssertFatal(1==0,"Prepare dci currently only implemented for 1_1 and 0_1 \n"); } } -void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, +void fill_dci_pdu_rel15(NR_ServingCellConfigCommon_t *scc, + NR_CellGroupConfig_t *secondaryCellGroup, nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, @@ -805,7 +817,7 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, for (int d=0;dnumDlDci;d++) { uint64_t *dci_pdu = (uint64_t *)pdcch_pdu_rel15->dci_pdu.Payload[d]; - int dci_size = nr_dci_size(secondaryCellGroup,&dci_pdu_rel15[d],dci_formats[d],rnti_types[d],N_RB,bwp_id); + int dci_size = nr_dci_size(scc,secondaryCellGroup,&dci_pdu_rel15[d],dci_formats[d],rnti_types[d],N_RB,bwp_id); pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d] = dci_size; AssertFatal(pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d]<=64, "DCI sizes above 64 bits not yet supported"); @@ -1119,6 +1131,16 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, } break; + case NR_UL_DCI_FORMAT_0_1: + switch(rnti_types[d]) + { + case NR_RNTI_C: + // Frequency domain resource assignment + // add potential MSB for N_UL_HOP + break; + } + break; + case NR_DL_DCI_FORMAT_1_1: // Indicating a DL DCI format 1bit pos=1; @@ -1224,7 +1246,7 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, // DMRS sequence init pos+=1; - *dci_pdu |= ((uint64_t)dci_pdu_rel15->dmrs_sequence_initialization&0x1)<<(dci_size-pos); + *dci_pdu |= ((uint64_t)dci_pdu_rel15->dmrs_sequence_initialization.val&0x1)<<(dci_size-pos); } } } diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index 78920dd2ea..8b38c357c6 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -132,7 +132,12 @@ int configure_fapi_dl_pdu(int Mod_id, uint16_t *rbSize, uint16_t *rbStart); -void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types); +void config_uldci(NR_BWP_Uplink_t *ubwp, + nfapi_nr_pusch_pdu_t *pusch_pdu, + nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, + dci_pdu_rel15_t *dci_pdu_rel15, + int *dci_formats, int *rnti_types, + int n_ubwp, int bwp_id); void configure_fapi_dl_Tx(module_id_t Mod_idP, frame_t frameP, @@ -203,7 +208,8 @@ int nr_configure_pdcch(gNB_MAC_INST *nr_mac, NR_ServingCellConfigCommon_t *scc, NR_BWP_Downlink_t *bwp); -void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, +void fill_dci_pdu_rel15(NR_ServingCellConfigCommon_t *scc, + NR_CellGroupConfig_t *secondaryCellGroup, nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, @@ -289,6 +295,8 @@ void nr_process_mac_pdu( uint8_t *pduP, uint16_t mac_pdu_len); +int binomial(int n, int k); + /* \brief Function to indicate a received SDU on ULSCH. @param Mod_id Instance ID of gNB diff --git a/openair2/RRC/NR/rrc_gNB_reconfig.c b/openair2/RRC/NR/rrc_gNB_reconfig.c index 7b0bb099f7..a99c1125e4 100644 --- a/openair2/RRC/NR/rrc_gNB_reconfig.c +++ b/openair2/RRC/NR/rrc_gNB_reconfig.c @@ -1095,7 +1095,19 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id)); *secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id = 1; - secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig = NULL; + + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig)); + NR_PUSCH_ServingCellConfig_t *pusch_scc = calloc(1,sizeof(*pusch_scc)); + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig->present = NR_SetupRelease_PUSCH_ServingCellConfig_PR_setup; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig->choice.setup = pusch_scc; + pusch_scc->codeBlockGroupTransmission = NULL; + pusch_scc->rateMatching = NULL; + pusch_scc->xOverhead = NULL; + pusch_scc->ext1=calloc(1,sizeof(*pusch_scc->ext1)); + pusch_scc->ext1->maxMIMO_Layers = calloc(1,sizeof(*pusch_scc->ext1->maxMIMO_Layers)); + *pusch_scc->ext1->maxMIMO_Layers = 1; + pusch_scc->ext1->processingType2Enabled = NULL; + secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->carrierSwitching = NULL; secondaryCellGroup->spCellConfig->spCellConfigDedicated->supplementaryUplink=NULL; From e0231398cad4f519efa0db8b57929f6e200763c4 Mon Sep 17 00:00:00 2001 From: Florian Kaltenberger Date: Wed, 8 Jul 2020 21:02:33 +0200 Subject: [PATCH 457/553] update from Walter Maguire --- openair1/PHY/CODING/nrPolar_tools/nr_polar_decoding_tools.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoding_tools.c b/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoding_tools.c index daa2346098..42d500ae86 100644 --- a/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoding_tools.c +++ b/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoding_tools.c @@ -197,8 +197,10 @@ decoder_node_t *add_nodes(int level, int first_leaf_index, t_nrPolar_params *pol } for (int i=0;iinformation_bit_pattern[i+first_leaf_index]>0) - all_frozen_below=0; + if (polarParams->information_bit_pattern[i+first_leaf_index]>0) { + all_frozen_below=0; + break; + } } if (all_frozen_below==0) From 1fa7a61b2bc6ed7500cd4141d45d5cd8fa330518 Mon Sep 17 00:00:00 2001 From: Cedric Roux Date: Thu, 9 Jul 2020 10:50:17 +0200 Subject: [PATCH 458/553] nr: fix compilation warning --- openair2/RRC/NR/rrc_gNB_nsa.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c index 64c762dd42..f2bda868dc 100644 --- a/openair2/RRC/NR/rrc_gNB_nsa.c +++ b/openair2/RRC/NR/rrc_gNB_nsa.c @@ -118,6 +118,10 @@ void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_Container rrc_add_nsa_user(rrc,ue_context_p, m); } +/* generate prototypes for the tree management functions (RB_INSERT used in rrc_add_nsa_user) */ +RB_PROTOTYPE(rrc_nr_ue_tree_s, rrc_gNB_ue_context_s, entries, + rrc_gNB_compare_ue_rnti_id); + void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p, x2ap_ENDC_sgnb_addition_req_t *m) { // generate nr-Config-r15 containers for LTE RRC : inside message for X2 EN-DC (CG-Config Message from 38.331) rrc_gNB_carrier_data_t *carrier=&rrc->carrier; From d474f4a1b81e341bd52f512bd2cf6f8f0d9d8b88 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Thu, 9 Jul 2020 10:55:41 +0200 Subject: [PATCH 459/553] fix some warnings --- openair1/PHY/INIT/nr_init_ru.c | 3 --- .../NR_ESTIMATION/nr_ul_channel_estimation.c | 12 +++++------ openair1/PHY/NR_TRANSPORT/nr_prach.c | 2 +- openair1/SCHED_NR_UE/fapi_nr_ue_l1.c | 2 +- openair1/SCHED_NR_UE/phy_procedures_nr_ue.c | 20 +++++++++---------- openair1/SIMULATION/NR_PHY/dlsim.c | 6 +++--- openair1/SIMULATION/NR_PHY/ulsim.c | 8 +++----- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 2 +- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 2 ++ .../NR_MAC_gNB/gNB_scheduler_primitives.c | 1 - 10 files changed, 26 insertions(+), 32 deletions(-) diff --git a/openair1/PHY/INIT/nr_init_ru.c b/openair1/PHY/INIT/nr_init_ru.c index 5deca65aed..8b70b523a5 100644 --- a/openair1/PHY/INIT/nr_init_ru.c +++ b/openair1/PHY/INIT/nr_init_ru.c @@ -40,9 +40,6 @@ int nr_phy_init_RU(RU_t *ru) { int p; int re; - // For memory allocation of ru->prach_rxsigF - int mu = fp->numerology_index; - LOG_I(PHY,"Initializing RU signal buffers (if_south %s) nb_tx %d\n",ru_if_types[ru->if_south],ru->nb_tx); nfapi_nr_config_request_scf_t *cfg; diff --git a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c index c515fe1263..3f7c7817f7 100644 --- a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c +++ b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c @@ -204,8 +204,8 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); #ifdef DEBUG_PUSCH - printf("pilot %d : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); - printf("data %d : rxF - > (%d,%d)\n",pilot_cnt,rxF[2],rxF[3]); + printf("pilot %u : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); + printf("data %u : rxF - > (%d,%d)\n",pilot_cnt,rxF[2],rxF[3]); #endif multadd_real_vector_complex_scalar(fml, ch, @@ -221,7 +221,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, #ifdef DEBUG_PUSCH printf("pilot %u : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt+1,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); - printf("data %d : rxF - > (%d,%d)\n",pilot_cnt+1,rxF[2],rxF[3]); + printf("data %u : rxF - > (%d,%d)\n",pilot_cnt+1,rxF[2],rxF[3]); #endif multadd_real_vector_complex_scalar(fmm, ch, @@ -243,7 +243,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); #ifdef DEBUG_PUSCH printf("pilot %u : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); - printf("data %d : rxF - > (%d,%d)\n",pilot_cnt,rxF[2],rxF[3]); + printf("data %u : rxF - > (%d,%d)\n",pilot_cnt,rxF[2],rxF[3]); #endif multadd_real_vector_complex_scalar(fm, ch, @@ -262,7 +262,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, #ifdef DEBUG_PUSCH printf("ch 0 %d\n",((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])); printf("pilot %u: rxF - > (%d,%d) addr %p ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt+1,rxF[0],rxF[1],&rxF[0],ch[0],ch[1],pil[0],pil[1]); - printf("data %d : rxF - > (%d,%d)\n",pilot_cnt+1,rxF[2],rxF[3]); + printf("data %u : rxF - > (%d,%d)\n",pilot_cnt+1,rxF[2],rxF[3]); #endif multadd_real_vector_complex_scalar(fmr, ch, @@ -278,7 +278,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB, ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15); #ifdef DEBUG_PUSCH printf("pilot %u: rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt+2,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]); - printf("data %d : rxF - > (%d,%d)\n",pilot_cnt+2,rxF[2],rxF[3]); + printf("data %u : rxF - > (%d,%d)\n",pilot_cnt+2,rxF[2],rxF[3]); #endif multadd_real_vector_complex_scalar(fr, ch, diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index e4d79822f9..2640a86240 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -791,7 +791,7 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, if (LOG_DUMPFLAG(PRACH)) { - int en = dB_fixed(signal_energy((int32_t*)&rxsigF[0][0],840)); + //int en = dB_fixed(signal_energy((int32_t*)&rxsigF[0][0],840)); // if (en>60) { int k = (12*n_ra_prb) - 6*fp->N_RB_UL; diff --git a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c index e41bdd4ccc..f852ae4ae1 100644 --- a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c +++ b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c @@ -57,7 +57,7 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ NR_UE_PDCCH *pdcch_vars = PHY_vars_UE_g[module_id][cc_id]->pdcch_vars[thread_id][0]; NR_UE_ULSCH_t *ulsch0 = PHY_vars_UE_g[module_id][cc_id]->ulsch[thread_id][0][0]; NR_DL_FRAME_PARMS frame_parms = PHY_vars_UE_g[module_id][cc_id]->frame_parms; - PRACH_RESOURCES_t *prach_resources = PHY_vars_UE_g[module_id][cc_id]->prach_resources[0]; + //PRACH_RESOURCES_t *prach_resources = PHY_vars_UE_g[module_id][cc_id]->prach_resources[0]; // PUCCH_ConfigCommon_nr_t *pucch_config_common = PHY_vars_UE_g[module_id][cc_id]->pucch_config_common_nr[0]; // PUCCH_Config_t *pucch_config_dedicated = PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0]; diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index c40358b8f9..7de941cfc8 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -3284,15 +3284,14 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, int *dlsch_errors, runmode_t mode) { - int harq_pid; + int harq_pid = dlsch0->current_harq_pid; int frame_rx = proc->frame_rx; int nr_tti_rx = proc->nr_tti_rx; int ret=0, ret1=0; NR_UE_PDSCH *pdsch_vars; uint8_t is_cw0_active = 0; uint8_t is_cw1_active = 0; - nfapi_nr_config_request_t *cfg = &ue->nrUE_config; - uint8_t dmrs_type = cfg->pdsch_config.PDSCHTimeDomainResourceAllocation_mappingType[0].value; // TODO: HARDCODED pdsch index + uint8_t dmrs_type = dlsch0->harq_processes[harq_pid]->dmrsConfigType; uint8_t nb_re_dmrs = (dmrs_type==NFAPI_NR_DMRS_TYPE1)?6:4; // TODO: should changed my mac uint16_t length_dmrs = 1; //cfg->pdsch_config.dmrs_max_length.value; uint16_t nb_symb_sch = 9; @@ -3316,7 +3315,6 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, if (dlsch0==NULL) AssertFatal(0,"dlsch0 should be defined at this level \n"); - harq_pid = dlsch0->current_harq_pid; is_cw0_active = dlsch0->harq_processes[harq_pid]->status; nb_symb_sch = dlsch0->harq_processes[harq_pid]->nb_symbols; start_symbol = dlsch0->harq_processes[harq_pid]->start_symbol; @@ -3376,13 +3374,13 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, } - // start ldpc decode for CW 0 - dlsch0->harq_processes[harq_pid]->G = nr_get_G(dlsch0->harq_processes[harq_pid]->nb_rb, - nb_symb_sch, - nb_re_dmrs, - length_dmrs, - dlsch0->harq_processes[harq_pid]->Qm, - dlsch0->harq_processes[harq_pid]->Nl); + // start ldpc decode for CW 0 + dlsch0->harq_processes[harq_pid]->G = nr_get_G(dlsch0->harq_processes[harq_pid]->nb_rb, + nb_symb_sch, + nb_re_dmrs, + length_dmrs, + dlsch0->harq_processes[harq_pid]->Qm, + dlsch0->harq_processes[harq_pid]->Nl); #if UE_TIMING_TRACE start_meas(&ue->dlsch_unscrambling_stats); #endif diff --git a/openair1/SIMULATION/NR_PHY/dlsim.c b/openair1/SIMULATION/NR_PHY/dlsim.c index b8229e3712..137c358d7f 100644 --- a/openair1/SIMULATION/NR_PHY/dlsim.c +++ b/openair1/SIMULATION/NR_PHY/dlsim.c @@ -139,7 +139,7 @@ int main(int argc, char **argv) uint8_t snr1set=0; float roundStats[50]; float effRate; - float psnr; + //float psnr; float eff_tp_check = 0.7; uint8_t snrRun; uint32_t TBS; @@ -696,7 +696,7 @@ int main(int argc, char **argv) nr_ue_phy_config_request(&UE_mac->phy_config); NR_UE_list_t *UE_list = &RC.nrmac[0]->UE_list; - NR_COMMON_channels_t *cc = RC.nrmac[0]->common_channels; + //NR_COMMON_channels_t *cc = RC.nrmac[0]->common_channels; snrRun = 0; for (SNR = snr0; SNR < snr1; SNR += .2) { @@ -924,7 +924,7 @@ int main(int argc, char **argv) (float) n_errors / (float) n_trials); printf("*****************************************\n"); printf("\n"); - printf("SNR %f : n_errors (negative CRC) = %d/%d, Avg round %.2f, Channel BER %e, Eff Rate %.4f bits/slot, Eff Throughput %.2f\%, TBS %d bits/slot\n", SNR, n_errors, n_trials,roundStats[snrRun],(double)errors_scrambling/available_bits/n_trials,effRate,effRate/TBS*100,TBS); + printf("SNR %f : n_errors (negative CRC) = %d/%d, Avg round %.2f, Channel BER %e, Eff Rate %.4f bits/slot, Eff Throughput %.2f, TBS %d bits/slot\n", SNR, n_errors, n_trials,roundStats[snrRun],(double)errors_scrambling/available_bits/n_trials,effRate,effRate/TBS*100,TBS); printf("\n"); if (n_trials == 1) { diff --git a/openair1/SIMULATION/NR_PHY/ulsim.c b/openair1/SIMULATION/NR_PHY/ulsim.c index 7f63bf1f3f..bcaa967a30 100644 --- a/openair1/SIMULATION/NR_PHY/ulsim.c +++ b/openair1/SIMULATION/NR_PHY/ulsim.c @@ -150,7 +150,7 @@ int main(int argc, char **argv) UE_nr_rxtx_proc_t UE_proc; FILE *scg_fd=NULL; - int ibwp_size=24; + int ibwps=24; int ibwp_rboffset=41; if ( load_configmodule(argc,argv,CONFIG_ENABLECMDLINEONLY) == 0 ) { exit_fun("[NR_ULSIM] Error, configuration module init failed\n"); @@ -618,7 +618,7 @@ int main(int argc, char **argv) int abwp_size = NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275); int abwp_start = NRRIV2PRBOFFSET(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275); - int ibwp_size = ibwp_size; + int ibwp_size = ibwps; int ibwp_start = ibwp_rboffset; if (msg3_flag == 1) { if ((ibwp_start < abwp_start) || (ibwp_size > abwp_size)) @@ -880,11 +880,10 @@ int main(int argc, char **argv) if (n_trials==1) printf("\x1B[31m""[frame %d][trial %d]\tnumber of errors in decoding = %u\n" "\x1B[0m", frame, trial, errors_decoding); } - } // trial loop printf("*****************************************\n"); - printf("SNR %f: n_errors (negative CRC) = %d/%d, false_positive %d/%d, errors_scrambling %u/%d\n", SNR, n_errors, n_trials, n_false_positive, n_trials, errors_scrambling, available_bits*n_trials); + printf("SNR %f: n_errors (negative CRC) = %d/%d, false_positive %d/%d, errors_scrambling %u/%u\n", SNR, n_errors, n_trials, n_false_positive, n_trials, errors_scrambling, available_bits*n_trials); printf("\n"); printf("SNR %f: Channel BLER %e, Channel BER %e\n", SNR,(double)n_errors/n_trials,(double)errors_scrambling/available_bits/n_trials); printf("*****************************************\n"); @@ -915,7 +914,6 @@ int main(int argc, char **argv) } } // SNR loop - printf("\n"); free(test_input_bit); diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index 8ff0aff5dc..074908022c 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -1739,7 +1739,7 @@ uint8_t getRBGSize(uint16_t bwp_size, long rbg_size_config) { if (bwp_size < 37) return (rbg_size_config ? 4 : 2); if (bwp_size < 73) return (rbg_size_config ? 8 : 4); if (bwp_size < 145) return (rbg_size_config ? 16 : 8); - if (bwp_size < 276) return 16; + else return 16; } uint8_t getNRBG(uint16_t bwp_size, uint16_t bwp_start, long rbg_size_config) { diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index a9bc3447aa..338c94776b 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -423,6 +423,7 @@ int configure_fapi_dl_pdu(int Mod_idP, bwp); if (ret < 0) { LOG_I(MAC,"CCE list not empty, couldn't schedule PDSCH\n"); + free(dci_pdu_rel15); return (0); } @@ -463,6 +464,7 @@ int configure_fapi_dl_pdu(int Mod_idP, pdsch_pdu_rel15->mcsIndex[0], TBS); + free(dci_pdu_rel15); return TBS; //Return TBS in bytes } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 44f4edd3ea..fc2a2e18cf 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -800,7 +800,6 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, int bwp_id) { uint8_t fsize=0, pos=0; - uint8_t nbits=0; for (int d=0;dnumDlDci;d++) { From 94905c0f43c3a1ce2627b3b27cc01e7f73405979 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Thu, 9 Jul 2020 11:37:03 +0200 Subject: [PATCH 460/553] fixing warnings --- openair1/SCHED_NR_UE/pucch_uci_ue_nr.c | 62 +++++++++++++++----------- 1 file changed, 35 insertions(+), 27 deletions(-) diff --git a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c index 4b2ee9a3a1..2110cf2ad1 100644 --- a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c +++ b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c @@ -370,6 +370,7 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ } m_0 = get_ics_pucch(pucch_resource, format); + AssertFatal(m_0 >= 0, "Invalid m_0\n"); if (format == pucch_format3_nr) { if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format3->choice.setup->additionalDMRS[0] == 1) { index_additional_dmrs = I_PUCCH_ADDITIONAL_DMRS; @@ -699,7 +700,7 @@ uint8_t get_downlink_ack(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_t int V_DAI_m_DL = 0; NR_UE_MAC_INST_t *mac = get_mac_inst(0); - if (mac->DLbwp[0] == NULL) return; + if (mac->DLbwp[0] == NULL) return 0; if (mac->DLbwp[0]->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI[0] == 2) { two_transport_blocks = TRUE; @@ -897,7 +898,7 @@ boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, NR_UE_MAC_INST_t *mac, uint8 /* No resource set has been already configured so pucch_configCommon from Sib1 should be used in this case */ if (ue->UE_mode[gNB_id] != PUSCH) { - *initial_pucch_id = mac->ULbwp[bwp_id-1]->bwp_Common->pucch_ConfigCommon->choice.setup->pucch_ResourceCommon; + *initial_pucch_id = mac->ULbwp[bwp_id-1]->bwp_Common->pucch_ConfigCommon->choice.setup->pucch_ResourceCommon[0]; if (*initial_pucch_id >= NB_INITIAL_PUCCH_RESOURCE) { LOG_E(PHY,"PUCCH Invalid initial resource index : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); *initial_pucch_id = NB_INITIAL_PUCCH_RESOURCE; @@ -1060,7 +1061,7 @@ int find_pucch_resource_set(NR_UE_MAC_INST_t *mac, uint8_t gNB_id, int uci_size) /* look for the first resource set which supports uci_size number of bits for payload */ while (pucch_resource_set_id < MAX_NB_OF_PUCCH_RESOURCE_SETS) { if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[pucch_resource_set_id] != NULL) { - if (uci_size <= mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[pucch_resource_set_id]->maxPayloadMinus1 + 1) { + if (uci_size <= mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[pucch_resource_set_id]->maxPayloadMinus1[0] + 1) { NR_TST_PHY_PRINTF("PUCCH found resource set %d \n", pucch_resource_set_id); return (pucch_resource_set_id); break; @@ -1093,35 +1094,36 @@ boolean_t check_pucch_format(NR_UE_MAC_INST_t *mac, uint8_t gNB_id, pucch_format { pucch_format_nr_t selected_pucch_format; pucch_format_nr_t selected_pucch_format_second; - NR_SetupRelease_PUCCH_FormatConfig_t *identified_format; + NR_SetupRelease_PUCCH_FormatConfig_t *identified_format = NULL; - if (format_pucch != pucch_format0_nr) { - switch (format_pucch) { - case pucch_format1_nr: - if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1 != NULL) - identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1; - break; + switch (format_pucch) { + case pucch_format1_nr: + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1 != NULL) + identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1; + break; - case pucch_format2_nr: - if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format2 != NULL) - identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format2; - break; + case pucch_format2_nr: + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format2 != NULL) + identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format2; + break; - case pucch_format3_nr: - if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format3 != NULL) - identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format3; - break; + case pucch_format3_nr: + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format3 != NULL) + identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format3; + break; - case pucch_format4_nr: - if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format4 != NULL) - identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format4; - break; - } + case pucch_format4_nr: + if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format4 != NULL) + identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format4; + break; - if (identified_format->choice.setup->nrofSlots != 1) { - LOG_E(PHY,"PUCCH not implemented multislots transmission : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); - return (FALSE); - } + default: + break; + } + + if ((identified_format != NULL) && (identified_format->choice.setup->nrofSlots[0] != 1)) { + LOG_E(PHY,"PUCCH not implemented multislots transmission : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME); + return (FALSE); } if (nb_symbols_for_tx <= 2) { @@ -1290,6 +1292,7 @@ uint8_t get_nb_symbols_pucch(NR_PUCCH_Resource_t *pucch_resource, pucch_format_n case pucch_format4_nr: return pucch_resource->format.choice.format4->nrofSymbols; } + return 0; } uint16_t get_starting_symb_idx(NR_PUCCH_Resource_t *pucch_resource, pucch_format_nr_t format_type) @@ -1310,6 +1313,7 @@ uint16_t get_starting_symb_idx(NR_PUCCH_Resource_t *pucch_resource, pucch_format case pucch_format4_nr: return pucch_resource->format.choice.format4->startingSymbolIndex; } + return 0; } int get_ics_pucch(NR_PUCCH_Resource_t *pucch_resource, pucch_format_nr_t format_type) @@ -1320,7 +1324,11 @@ int get_ics_pucch(NR_PUCCH_Resource_t *pucch_resource, pucch_format_nr_t format_ case pucch_format1_nr: return pucch_resource->format.choice.format1->initialCyclicShift; + + default: + return -1; } + return -1; } NR_PUCCH_Resource_t *select_resource_by_id(int resource_id, NR_PUCCH_Config_t *pucch_config) From 0f9519925d95a7fc5ad5f250bfda56116ef538e4 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Thu, 9 Jul 2020 11:58:15 +0200 Subject: [PATCH 461/553] fill dci pdu --- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 96 ++++++++++++++++++- 1 file changed, 95 insertions(+), 1 deletion(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 8253dbc4be..9eab75e7bc 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -1135,8 +1135,102 @@ void fill_dci_pdu_rel15(NR_ServingCellConfigCommon_t *scc, switch(rnti_types[d]) { case NR_RNTI_C: + // Indicating a DL DCI format 1bit + pos=1; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&0x1)<<(dci_size-pos); + + // Carrier indicator + pos+=dci_pdu_rel15->carrier_indicator.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->carrier_indicator.val&((1<carrier_indicator.nbits)-1))<<(dci_size-pos); + + // UL/SUL Indicator + pos+=dci_pdu_rel15->ul_sul_indicator.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator.val&((1<ul_sul_indicator.nbits)-1))<<(dci_size-pos); + + // BWP indicator + pos+=dci_pdu_rel15->bwp_indicator.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->bwp_indicator.val&((1<bwp_indicator.nbits)-1))<<(dci_size-pos); + // Frequency domain resource assignment - // add potential MSB for N_UL_HOP + pos+=dci_pdu_rel15->frequency_domain_assignment.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val&((1<frequency_domain_assignment.nbits)-1)) << (dci_size-pos); + + // Time domain resource assignment + pos+=dci_pdu_rel15->time_domain_assignment.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->time_domain_assignment.val&((1<time_domain_assignment.nbits)-1)) << (dci_size-pos); + + // Frequency hopping + pos+=dci_pdu_rel15->frequency_hopping_flag.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag.val&((1<frequency_hopping_flag.nbits)-1)) << (dci_size-pos); + + // MCS 5bit + pos+=5; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos); + + // New data indicator 1bit + pos+=1; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&0x1)<<(dci_size-pos); + + // Redundancy version 2bit + pos+=2; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->rv&0x3)<<(dci_size-pos); + + // HARQ process number 4bit + pos+=4; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid&0xf)<<(dci_size-pos); + + // 1st Downlink assignment index + pos+=dci_pdu_rel15->dai[0].nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->dai[0].val&((1<dai[0].nbits)-1))<<(dci_size-pos); + + // 2nd Downlink assignment index + pos+=dci_pdu_rel15->dai[1].nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->dai[1].val&((1<dai[1].nbits)-1))<<(dci_size-pos); + + // TPC command for scheduled PUSCH 2bit + pos+=2; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->tpc&0x3)<<(dci_size-pos); + + // SRS resource indicator + pos+=dci_pdu_rel15->srs_resource_indicator.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->srs_resource_indicator.val&((1<srs_resource_indicator.nbits)-1))<<(dci_size-pos); + + // Precoding info and n. of layers + pos+=dci_pdu_rel15->precoding_information.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->precoding_information.val&((1<precoding_information.nbits)-1))<<(dci_size-pos); + + // Antenna ports + pos+=dci_pdu_rel15->antenna_ports.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->antenna_ports.val&((1<antenna_ports.nbits)-1))<<(dci_size-pos); + + // SRS request + pos+=dci_pdu_rel15->srs_request.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->srs_request.val&((1<srs_request.nbits)-1))<<(dci_size-pos); + + // CSI request + pos+=dci_pdu_rel15->csi_request.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->csi_request.val&((1<csi_request.nbits)-1))<<(dci_size-pos); + + // CBG transmission information + pos+=dci_pdu_rel15->cbgti.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->cbgti.val&((1<cbgti.nbits)-1))<<(dci_size-pos); + + // PTRS DMRS association + pos+=dci_pdu_rel15->ptrs_dmrs_association.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ptrs_dmrs_association.val&((1<ptrs_dmrs_association.nbits)-1))<<(dci_size-pos); + + // Beta offset indicator + pos+=dci_pdu_rel15->beta_offset_indicator.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->beta_offset_indicator.val&((1<beta_offset_indicator.nbits)-1))<<(dci_size-pos); + + // DMRS sequence initialization + pos+=dci_pdu_rel15->dmrs_sequence_initialization.nbits; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->dmrs_sequence_initialization.val&((1<dmrs_sequence_initialization.nbits)-1))<<(dci_size-pos); + + // UL-SCH indicator + pos+=1; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ulsch_indicator&0x1)<<(dci_size-pos); + break; } break; From 79210715184a71aa5aec4457bc4704df4d22d018 Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Thu, 9 Jul 2020 12:32:21 +0200 Subject: [PATCH 462/553] CI: fix when retrieving the DL Carrier Frequency in UE Run log Signed-off-by: Raphael Defosseux --- ci-scripts/main.py | 6 +++--- .../xml_files/enb_ue_usrp210_band7_epc_start.xml | 13 ------------- 2 files changed, 3 insertions(+), 16 deletions(-) diff --git a/ci-scripts/main.py b/ci-scripts/main.py index 6bec183255..1f84c449bf 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -2560,14 +2560,14 @@ class OaiCiTest(): logging.debug('\033[94m' + mibMsg + '\033[0m') except Exception as e: logging.error('\033[91m' + "SIB5 InterFreqCarrierFreq element not found" + '\033[0m') - result = re.search("DL Carrier Frequency/ARFCN : (?P\d{1,15}/\d{1,4})", str(line)) + result = re.search("DL Carrier Frequency/ARFCN : \-*(?P\d{1,15}/\d{1,4})", str(line)) if result is not None: try: freq = result.group('carrier_frequency') new_freq = re.sub('/[0-9]+','',freq) float_freq = float(new_freq) / 1000000 - HTMLSethtmlUEFailureMsg(HTMLGethtmlUEFailureMsg() + 'DL Freq: ' + ('%.1f' % float_freq) + ' MHz') - logging.debug('\033[94m' + " DL Carrier Frequency is: " + freq + '\033[0m') + HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + 'DL Freq: ' + ('%.1f' % float_freq) + ' MHz') + logging.debug('\033[94m' + " DL Carrier Frequency is: " + str(freq) + '\033[0m') except Exception as e: logging.error('\033[91m' + " DL Carrier Frequency not found" + '\033[0m') result = re.search("AllowedMeasBandwidth : (?P\d{1,7})", str(line)) diff --git a/ci-scripts/xml_files/enb_ue_usrp210_band7_epc_start.xml b/ci-scripts/xml_files/enb_ue_usrp210_band7_epc_start.xml index 4dbfe00821..aac71198f1 100644 --- a/ci-scripts/xml_files/enb_ue_usrp210_band7_epc_start.xml +++ b/ci-scripts/xml_files/enb_ue_usrp210_band7_epc_start.xml @@ -25,23 +25,10 @@ EPC-Start log-in - 010101 090101 050101 060101 070101 - - Build_eNB - Build eNB (USRP) - -w USRP -c --eNB - - - - Build_OAI_UE - Build OAI UE - -w USRP --UE - - Initialize_HSS Initialize HSS From f6999282f2cf8b47af1d9860f2c3695135e7791e Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Thu, 9 Jul 2020 13:36:47 +0200 Subject: [PATCH 463/553] DOC: update on the 5G Rf simulator Signed-off-by: Raphael Defosseux --- ci-scripts/main.py | 2 +- ci-scripts/ran.py | 2 +- targets/ARCH/rfsimulator/README.md | 14 +++++++++++--- 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/ci-scripts/main.py b/ci-scripts/main.py index 1f84c449bf..63358eca38 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -349,7 +349,7 @@ class OaiCiTest(): SSH.command('echo ' + self.UEPassword + ' | sudo -S ../../../targets/bin/conf2uedata -c ../../../openair3/NAS/TOOLS/ci-ue_eurecom_test_sfr.conf -o .', '\$', 5) else: SSH.command('if [ -e rbconfig.raw ]; then echo ' + self.UEPassword + ' | sudo -S rm rbconfig.raw; fi', '\$', 5) - SSH.command('if [ -e rbconfig.raw ]; then echo ' + self.UEPassword + ' | sudo -S rm reconfig.raw; fi', '\$', 5) + SSH.command('if [ -e reconfig.raw ]; then echo ' + self.UEPassword + ' | sudo -S rm reconfig.raw; fi', '\$', 5) # Copy the RAW files from gNB running directory (maybe on another machine) copyin_res = SSH.copyin(RAN.GeteNBIPAddress(), RAN.GeteNBUserName(), RAN.GeteNBPassword(), RAN.GeteNBSourceCodePath() + '/cmake_targets/rbconfig.raw', '.') if (copyin_res == 0): diff --git a/ci-scripts/ran.py b/ci-scripts/ran.py index 79fe1e2fc0..287c18021e 100644 --- a/ci-scripts/ran.py +++ b/ci-scripts/ran.py @@ -548,7 +548,7 @@ class RANManagement(): mySSH.command('cd cmake_targets', '\$', 5) if self.air_interface == 'nr': mySSH.command('if [ -e rbconfig.raw ]; then echo ' + lPassWord + ' | sudo -S rm rbconfig.raw; fi', '\$', 5) - mySSH.command('if [ -e rbconfig.raw ]; then echo ' + lPassWord + ' | sudo -S rm reconfig.raw; fi', '\$', 5) + mySSH.command('if [ -e reconfig.raw ]; then echo ' + lPassWord + ' | sudo -S rm reconfig.raw; fi', '\$', 5) mySSH.command('echo "ulimit -c unlimited && ./ran_build/build/' + self.air_interface + '-softmodem -O ' + lSourcePath + '/' + ci_full_config_file + extra_options + '" > ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh', '\$', 5) mySSH.command('chmod 775 ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh', '\$', 5) mySSH.command('echo ' + lPassWord + ' | sudo -S rm -Rf enb_' + self.testCase_id + '.log', '\$', 5) diff --git a/targets/ARCH/rfsimulator/README.md b/targets/ARCH/rfsimulator/README.md index 421cc662bb..9ec0ae5065 100644 --- a/targets/ARCH/rfsimulator/README.md +++ b/targets/ARCH/rfsimulator/README.md @@ -96,11 +96,19 @@ sudo RFSIMULATOR=server ./nr-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE- ### Launch UE in another window ```bash -sudo RFSIMULATOR= ./nr-uesoftmodem --rfsim --phy-test --rrc_config_path ../../../ci-scripts/rrc-files +sudo RFSIMULATOR= ./nr-uesoftmodem --rfsim --phy-test --rrc_config_path . ``` -Note: + +Notes: + 1. can be 127.0.0.1 if both gNB and nrUE executables run on the same host, OR the IP interface address of the remote host running the gNB executable, if the gNB and nrUE run on separate hosts -2. the --rrc_config_path parameter can be omitted (but not necessarily) if the gNB and nrUE run on the same host, in which case the gNB provides the nrUE with the necessary rrc configuration +2. the --rrc_config_path parameter SHALL specify where the 2 RAW files are located (`rbconfig.raw` and `reconfig.raw`). + - If you are running on the same machine and launched the 2 executables (`nr-softmodem` and `nr-uesoftmodem`) from the same directory, nothing has to be done. + - If you launched the 2 executables from 2 different folders, just point to the location where you launched the `nr-softmodem`: + * `sudo RFSIMULATOR= ./nr-uesoftmodem --rfsim --phy-test --rrc_config_path /the/path/where/you/launched/nr-softmodem` + - If you are not running on the same machine or launched the 2 executables from 2 different folders, you need to **COPY** the 2 raw files + * `scp usera@machineA:/the/path/where/you/launched/nr-softmodem/r*config.raw userb@machineB:/the/path/where/you/will/launch/nr-uesoftmodem/` + * Obviously this operation SHALL be done before launching the `nr-uesoftmodem` executable. 3. to enable the noS1 mode --noS1 and --nokrnmod 1 options should be added to the command line From 8d75cb61bc91c40bebca59e7c5dc8e3894ae54a7 Mon Sep 17 00:00:00 2001 From: hardy Date: Thu, 9 Jul 2020 14:37:18 +0200 Subject: [PATCH 464/553] to support OCP eNB build and test --- ci-scripts/main.py | 43 ++++-- ci-scripts/ran.py | 71 +++++---- .../enb_ocp_usrp210_band7_test_05mhz_tm1.xml | 146 ++++++++++++++++++ .../xml_files/enb_ocp_usrp210_build.xml | 38 +++++ cmake_targets/build_oai | 17 +- 5 files changed, 265 insertions(+), 50 deletions(-) create mode 100644 ci-scripts/xml_files/enb_ocp_usrp210_band7_test_05mhz_tm1.xml create mode 100644 ci-scripts/xml_files/enb_ocp_usrp210_build.xml diff --git a/ci-scripts/main.py b/ci-scripts/main.py index ce37b0c8ba..7175be7c87 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -3110,11 +3110,15 @@ def GetParametersFromXML(action): RAN.SeteNB_serverId(test.findtext('eNB_serverId')) if (RAN.GeteNB_serverId() is None): RAN.SeteNB_serverId('0') - CiTestObj.air_interface = test.findtext('air_interface') - if (CiTestObj.air_interface is None): - CiTestObj.air_interface = 'lte' - else: - CiTestObj.air_interface = CiTestObj.air_interface.lower() + + #local variable air_interface + air_interface = test.findtext('air_interface') + if (air_interface is None) or (air_interface.lower() not in ['nr','lte','ocp']): + CiTestObj.air_interface = 'lte-softmodem' + elif (air_interface.lower() in ['nr','lte']): + CiTestObj.air_interface = air_interface.lower() +'-softmodem' + else : + CiTestObj.air_interface = air_interface.lower() +'ocp-enb' RAN.Setair_interface(CiTestObj.air_interface) if action == 'Terminate_eNB': @@ -3124,11 +3128,15 @@ def GetParametersFromXML(action): RAN.SeteNB_serverId(test.findtext('eNB_serverId')) if (RAN.GeteNB_serverId() is None): RAN.SeteNB_serverId('0') - CiTestObj.air_interface = test.findtext('air_interface') - if (CiTestObj.air_interface is None): - CiTestObj.air_interface = 'lte' - else: - CiTestObj.air_interface = CiTestObj.air_interface.lower() + + #local variable air_interface + air_interface = test.findtext('air_interface') + if (air_interface is None) or (air_interface.lower() not in ['nr','lte','ocp']): + CiTestObj.air_interface = 'lte-softmodem' + elif (air_interface.lower() in ['nr','lte']): + CiTestObj.air_interface = air_interface.lower() +'-softmodem' + else : + CiTestObj.air_interface = air_interface.lower() +'ocp-enb' RAN.Setair_interface(CiTestObj.air_interface) if action == 'Attach_UE': @@ -3158,11 +3166,16 @@ def GetParametersFromXML(action): CiTestObj.UE_instance = test.findtext('UE_instance') if (CiTestObj.UE_instance is None): CiTestObj.UE_instance = '0' - CiTestObj.air_interface = test.findtext('air_interface') - if (CiTestObj.air_interface is None): - CiTestObj.air_interface = 'lte' - else: - CiTestObj.air_interface = CiTestObj.air_interface.lower() + + #local variable air_interface + air_interface = test.findtext('air_interface') + if (air_interface is None) or (air_interface.lower() not in ['nr','lte','ocp']): + CiTestObj.air_interface = 'lte-softmodem' + elif (air_interface.lower() in ['nr','lte']): + CiTestObj.air_interface = air_interface.lower() +'-softmodem' + else : + CiTestObj.air_interface = air_interface.lower() +'ocp-enb' + RAN.Setair_interface(CiTestObj.air_interface) if action == 'Terminate_OAI_UE': RAN.SeteNB_instance(test.findtext('UE_instance')) diff --git a/ci-scripts/ran.py b/ci-scripts/ran.py index 5f05a2ae4f..93ba859903 100644 --- a/ci-scripts/ran.py +++ b/ci-scripts/ran.py @@ -77,7 +77,7 @@ class RANManagement(): self.backgroundBuildTestId = ['', '', ''] self.Build_eNB_forced_workspace_cleanup = False self.Initialize_eNB_args = '' - self.air_interface = 'lte' + self.air_interface = '' #changed from 'lte' to '' may lead to side effects in main self.eNB_instance = '' self.eNB_serverId = '' self.eNBLogFiles = ['', '', ''] @@ -91,6 +91,8 @@ class RANManagement(): self.htmlObj = None self.epcObj = None + + #----------------------------------------------------------- # Setters and Getters on Public members #----------------------------------------------------------- @@ -254,12 +256,18 @@ class RANManagement(): sys.exit('Insufficient Parameter') mySSH = SSH.SSHConnection() mySSH.open(lIpAddr, lUserName, lPassWord) - # Check if we build an 5G-NR gNB or an LTE eNB - result = re.search('--gNB', self.Build_eNB_args) + + # Check if we build an 5G-NR gNB or an LTE eNB or an OCP eNB + result = re.search('--eNBocp', self.Build_eNB_args) if result is not None: - self.air_interface = 'nr' - else: - self.air_interface = 'lte' + self.air_interface='ocp-enb' + else: + result = re.search('--gNB', self.Build_eNB_args) + if result is not None: + self.air_interface = 'nr-softmodem' + else: + self.air_interface = 'lte-softmodem' + # Worakround for some servers, we need to erase completely the workspace if self.Build_eNB_forced_workspace_cleanup: mySSH.command('echo ' + lPassWord + ' | sudo -S rm -Rf ' + lSourcePath, '\$', 15) @@ -379,20 +387,19 @@ class RANManagement(): def checkBuildeNB(self, lIpAddr, lUserName, lPassWord, lSourcePath, testcaseId): if self.htmlObj is not None: self.htmlObj.SettestCase_id(testcaseId) + mySSH = SSH.SSHConnection() mySSH.open(lIpAddr, lUserName, lPassWord) mySSH.command('cd ' + lSourcePath + '/cmake_targets', '\$', 3) mySSH.command('ls ran_build/build', '\$', 3) mySSH.command('ls ran_build/build', '\$', 3) - if self.air_interface == 'nr': - nodeB_prefix = 'g' - else: - nodeB_prefix = 'e' - buildStatus = True - result = re.search(self.air_interface + '-softmodem', mySSH.getBefore()) + + #check if we have the build corresponding to the air interface keywords (nr-softmode, lte-softmodem, ocp-enb) + result = re.search(self.air_interface, mySSH.getBefore()) if result is None: - buildStatus = False + buildStatus = False #if not, build failed else: + buildStatus = True # Generating a BUILD INFO file mySSH.command('echo "SRC_BRANCH: ' + self.ranBranch + '" > ../LAST_BUILD_INFO.txt', '\$', 2) mySSH.command('echo "SRC_COMMIT: ' + self.ranCommitID + '" >> ../LAST_BUILD_INFO.txt', '\$', 2) @@ -404,6 +411,8 @@ class RANManagement(): mySSH.command('echo "TGT_BRANCH: ' + self.ranTargetBranch + '" >> ../LAST_BUILD_INFO.txt', '\$', 2) else: mySSH.command('echo "MERGED_W_TGT_BRANCH: NO" >> ../LAST_BUILD_INFO.txt', '\$', 2) + + mySSH.command('mkdir -p build_log_' + testcaseId, '\$', 5) mySSH.command('mv log/* ' + 'build_log_' + testcaseId, '\$', 5) mySSH.command('mv compile_oai_enb.log ' + 'build_log_' + testcaseId, '\$', 5) @@ -426,12 +435,13 @@ class RANManagement(): else: mySSH.close() + #generate logging info depending on buildStatus and air interface if buildStatus: - logging.info('\u001B[1m Building OAI ' + nodeB_prefix + 'NB Pass\u001B[0m') + logging.info('\u001B[1m Building OAI ' + self.air_interface + ' Pass\u001B[0m') if self.htmlObj is not None: - self.htmlObj.CreateHtmlTestRow(self.Build_eNB_args, 'OK', CONST.ALL_PROCESSES_OK) - else: - logging.error('\u001B[1m Building OAI ' + nodeB_prefix + 'NB Failed\u001B[0m') + self.htmlObj.CreateHtmlTestRow(self.Build_eNB_args, 'OK', CONST.ALL_PROCESSES_OK) + else + logging.error('\u001B[1m Building OAI ' + self.air_interface + ' Failed\u001B[0m') if self.htmlObj is not None: self.htmlObj.CreateHtmlTestRow(self.Build_eNB_args, 'KO', CONST.ALL_PROCESSES_OK) self.htmlObj.CreateHtmlTabFooter(False) @@ -546,7 +556,7 @@ class RANManagement(): # Launch eNB with the modified config file mySSH.command('source oaienv', '\$', 5) mySSH.command('cd cmake_targets', '\$', 5) - mySSH.command('echo "ulimit -c unlimited && ./ran_build/build/' + self.air_interface + '-softmodem -O ' + lSourcePath + '/' + ci_full_config_file + extra_options + '" > ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh', '\$', 5) + mySSH.command('echo "ulimit -c unlimited && ./ran_build/build/' + self.air_interface + ' -O ' + lSourcePath + '/' + ci_full_config_file + extra_options + '" > ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh', '\$', 5) mySSH.command('chmod 775 ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh', '\$', 5) mySSH.command('echo ' + lPassWord + ' | sudo -S rm -Rf enb_' + self.testCase_id + '.log', '\$', 5) mySSH.command('hostnamectl','\$', 5) @@ -655,8 +665,8 @@ class RANManagement(): lPassWord = self.eNBPassword mySSH = SSH.SSHConnection() mySSH.open(lIpAddr, lUserName, lPassWord) - mySSH.command('stdbuf -o0 ps -aux | grep --color=never ' + self.air_interface + '-softmodem | grep -v grep', '\$', 5) - result = re.search(self.air_interface + '-softmodem', mySSH.getBefore()) + mySSH.command('stdbuf -o0 ps -aux | grep --color=never ' + self.air_interface + ' | grep -v grep', '\$', 5) + result = re.search(self.air_interface, mySSH.getBefore()) if result is None: logging.debug('\u001B[1;37;41m eNB Process Not Found! \u001B[0m') status_queue.put(CONST.ENB_PROCESS_FAILED) @@ -688,20 +698,20 @@ class RANManagement(): mySSH = SSH.SSHConnection() mySSH.open(lIpAddr, lUserName, lPassWord) mySSH.command('cd ' + lSourcePath + '/cmake_targets', '\$', 5) - if self.air_interface == 'lte': + if (self.air_interface == 'lte-softmodem') or (self.air_interface == 'ocp-enb'): nodeB_prefix = 'e' else: nodeB_prefix = 'g' - mySSH.command('stdbuf -o0 ps -aux | grep --color=never softmodem | grep -v grep', '\$', 5) - result = re.search('-softmodem', mySSH.getBefore()) + mySSH.command('stdbuf -o0 ps -aux | grep --color=never -e softmodem -e ocp-enb | grep -v grep', '\$', 5) + result = re.search('(-softmodem|ocp)', mySSH.getBefore()) if result is not None: mySSH.command('echo ' + lPassWord + ' | sudo -S daemon --name=enb' + str(self.eNB_instance) + '_daemon --stop', '\$', 5) - mySSH.command('echo ' + lPassWord + ' | sudo -S killall --signal SIGINT -r .*-softmodem || true', '\$', 5) + mySSH.command('echo ' + lPassWord + ' | sudo -S killall --signal SIGINT -r .*-softmodem .ocp-enb || true', '\$', 5) time.sleep(10) - mySSH.command('stdbuf -o0 ps -aux | grep --color=never softmodem | grep -v grep', '\$', 5) - result = re.search('-softmodem', mySSH.getBefore()) + mySSH.command('stdbuf -o0 ps -aux | grep --color=never -e softmodem -e ocp-enb | grep -v grep', '\$', 5) + result = re.search('(-softmodem|ocp)', mySSH.getBefore()) if result is not None: - mySSH.command('echo ' + lPassWord + ' | sudo -S killall --signal SIGKILL -r .*-softmodem || true', '\$', 5) + mySSH.command('echo ' + lPassWord + ' | sudo -S killall --signal SIGKILL -r .*-softmodem .ocp-enb || true', '\$', 5) time.sleep(5) mySSH.command('rm -f my-lte-softmodem-run' + str(self.eNB_instance) + '.sh', '\$', 5) mySSH.close() @@ -890,8 +900,7 @@ class RANManagement(): if result is not None: rrcSetupComplete += 1 result = re.search('Generate LTE_RRCConnectionRelease|Generate RRCConnectionRelease', str(line)) - if result is not None: - rrcReleaseRequest += 1 + if result is not None: rrcReleaseRequest += 1 result = re.search('Generate LTE_RRCConnectionReconfiguration', str(line)) if result is not None: rrcReconfigRequest += 1 @@ -940,11 +949,11 @@ class RANManagement(): mbmsRequestMsg += 1 enb_log_file.close() logging.debug(' File analysis completed') - if self.air_interface == 'lte': + if (self.air_interface == 'lte-softmodem') or (self.air_interface == 'ocp-enb'): nodeB_prefix = 'e' else: nodeB_prefix = 'g' - if self.air_interface == 'nr': + if self.air_interface == 'nr-softmodem': if ulschReceiveOK > 0: statMsg = nodeB_prefix + 'NB showed ' + str(ulschReceiveOK) + ' "ULSCH received ok" message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') diff --git a/ci-scripts/xml_files/enb_ocp_usrp210_band7_test_05mhz_tm1.xml b/ci-scripts/xml_files/enb_ocp_usrp210_band7_test_05mhz_tm1.xml new file mode 100644 index 0000000000..5326973cc2 --- /dev/null +++ b/ci-scripts/xml_files/enb_ocp_usrp210_band7_test_05mhz_tm1.xml @@ -0,0 +1,146 @@ + + + test-05-tm1 + Test-05MHz-TM1 + tasks + + 030201 + 040101 + 030101 040301 040501 040603 040604 040605 040606 040607 040641 040642 040643 040644 040401 040201 030201 + + + + + Initialize_eNB + Initialize eNB (FDD/Band7/5MHz) + -O ci-scripts/conf_files/enb.band7.tm1.25PRB.usrpb210.conf + ocp + + + + Terminate_eNB + Terminate eNB + ocp + + + + Initialize_UE + Initialize UE + + + + Terminate_UE + Terminate UE + + + + Attach_UE + Attach UE + + + + Detach_UE + Detach UE + + + + Ping + ping (5MHz - 20 sec) + -c 20 + 5 + + + + Iperf + iperf (5MHz - DL/15Mbps/UDP)(30 sec)(balanced profile) + -u -b 15M -t 30 -i 1 + 50 + balanced + + + + Iperf + iperf (5MHz - DL/15Mbps/UDP)(30 sec)(single-ue profile) + -u -b 15M -t 30 -i 1 + 50 + single-ue + + + + Iperf + iperf (5MHz - DL/15Mbps/UDP)(30 sec)(unbalanced profile) + -u -b 15M -t 30 -i 1 + 50 + unbalanced + + + + Iperf + iperf (5MHz - DL/TCP)(30 sec)(single-ue profile) + -t 30 -i 1 -fm + 50 + single-ue + + + + Iperf + iperf (5MHz - DL/TCP)(30 sec)(balanced profile) + -t 30 -i 1 -fm + 50 + balanced + + + + Iperf + iperf (5MHz - UL/9Mbps/UDP)(30 sec)(balanced profile) + -u -b 9M -t 30 -i 1 -R + 50 + balanced + + + + Iperf + iperf (5MHz - UL/9Mbps/UDP)(30 sec)(single-ue profile) + -u -b 9M -t 30 -i 1 -R + 50 + single-ue + + + + Iperf + iperf (5MHz - UL/TCP)(30 sec)(single-ue profile) + -t 30 -i 1 -fm -R + 50 + single-ue + + + + Iperf + iperf (5MHz - UL/TCP)(30 sec)(balanced profile) + -t 30 -i 1 -fm -R + 50 + balanced + + + diff --git a/ci-scripts/xml_files/enb_ocp_usrp210_build.xml b/ci-scripts/xml_files/enb_ocp_usrp210_build.xml new file mode 100644 index 0000000000..5729846818 --- /dev/null +++ b/ci-scripts/xml_files/enb_ocp_usrp210_build.xml @@ -0,0 +1,38 @@ + + + build-tab + Build + wrench + + 010101 + + + + + Build_eNB + Build eNB OCP (USRP) + -I -w USRP -c --eNBocp --ninja + + + diff --git a/cmake_targets/build_oai b/cmake_targets/build_oai index 91f33ea625..469c840b4d 100755 --- a/cmake_targets/build_oai +++ b/cmake_targets/build_oai @@ -96,7 +96,9 @@ Options enable cmake debugging messages --eNB Makes the LTE softmodem ---gNB +--eNBocp + Makes the OCP LTE softmodem +-gNB Makes the NR softmodem --nrUE Makes the NR UE softmodem @@ -237,7 +239,11 @@ function main() { eNB=1 echo_info "Will compile eNB" shift;; - --gNB) + --eNBocp) + eNBocp=1 + echo_info "Will compile OCP eNB" + shift;; + --gNB) gNB=1 NR="True" echo_info "Will compile gNB" @@ -443,7 +449,7 @@ function main() { ######################################################## # to be discussed - if [ "$eNB" = "1" -o "$gNB" = "1" ] ; then + if [ "$eNB" = "1" -o "$eNBocp" = "1" -o "$gNB" = "1" ] ; then if [ "$HW" = "None" -a "$TP" = "None" ] ; then echo_info "No local radio head and no transport protocol selected" fi @@ -574,7 +580,7 @@ function main() { config_libconfig_shlib=params_libconfig # first generate the CMakefile in the right directory - if [ "$eNB" = "1" -o "$UE" = "1" -o "$gNB" = "1" -o "$nrUE" = "1" -o "$HW" = "EXMIMO" ] ; then + if [ "$eNB" = "1" -o "$eNBocp" = "1" -o "$UE" = "1" -o "$gNB" = "1" -o "$nrUE" = "1" -o "$HW" = "EXMIMO" ] ; then # softmodem compilation @@ -606,6 +612,9 @@ function main() { if [ "$eNB" = "1" ] ; then execlist="$execlist lte-softmodem" fi + if [ "$eNBocp" = "1" ] ; then + execlist="$execlist ocp-enb" + fi if [ "$gNB" = "1" ] ; then execlist="$execlist nr-softmodem" fi From f157d41e2f46ceab31aed3d3c5dab9bb91a2cf2c Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Thu, 9 Jul 2020 15:40:11 +0200 Subject: [PATCH 465/553] BUILD: missing dependency for NR_GTPV1U lib Signed-off-by: Raphael Defosseux --- cmake_targets/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index 525c9eae56..aac70e53aa 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -3083,7 +3083,7 @@ if (${T_TRACER}) NFAPI_COMMON_LIB NFAPI_LIB NFAPI_PNF_LIB NFAPI_VNF_LIB NFAPI_USER_LIB PHY_COMMON PHY PHY_UE PHY_NR PHY_NR_COMMON PHY_NR_UE PHY_RU PHY_MEX L2 L2_LTE L2_NR L2_UE NR_L2_UE MAC_NR_COMMON MAC_NR MAC_UE_NR - CN_UTILS GTPV1U SCTP_CLIENT MME_APP UDP LIB_NAS_UE NB_IoT LFDS LFDS7 SIMU_COMMON SIMU SIMU_ETH OPENAIR0_LIB + CN_UTILS GTPV1U NR_GTPV1U SCTP_CLIENT MME_APP UDP LIB_NAS_UE NB_IoT LFDS LFDS7 SIMU_COMMON SIMU SIMU_ETH OPENAIR0_LIB ldpc_orig ldpc_optim ldpc_optim8seg ldpc PROTO_AGENT dfts) if (TARGET ${i}) add_dependencies(${i} generate_T) From d32b45dd1af0bc02eea50b2a7dbd8901eab3bc47 Mon Sep 17 00:00:00 2001 From: Cedric Roux Date: Thu, 9 Jul 2020 15:50:14 +0200 Subject: [PATCH 466/553] bugfix: uplink ACK/NACK reporting through T was gone Let's get it back! --- openair1/SCHED/phy_procedures_lte_eNb.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/openair1/SCHED/phy_procedures_lte_eNb.c b/openair1/SCHED/phy_procedures_lte_eNb.c index fc9407f8d0..558fa8d4eb 100644 --- a/openair1/SCHED/phy_procedures_lte_eNb.c +++ b/openair1/SCHED/phy_procedures_lte_eNb.c @@ -1211,6 +1211,8 @@ void postDecode(L1_rxtx_proc_t *proc, notifiedFIFO_elt_t *req) { } if (!decodeSucess) { + T(T_ENB_PHY_ULSCH_UE_NACK, T_INT(eNB->Mod_id), T_INT(rdata->frame), T_INT(rdata->subframe), T_INT(ulsch->rnti), + T_INT(rdata->harq_pid)); fill_crc_indication(eNB,i,rdata->frame,rdata->subframe,1); // indicate NAK to MAC fill_rx_indication(eNB,i,rdata->frame,rdata->subframe); // indicate SDU to MAC LOG_D(PHY,"[eNB %d][PUSCH %d] frame %d subframe %d UE %d Error receiving ULSCH, round %d/%d (ACK %d,%d)\n", @@ -1239,6 +1241,8 @@ void postDecode(L1_rxtx_proc_t *proc, notifiedFIFO_elt_t *req) { fill_rx_indication(eNB,i,rdata->frame,rdata->subframe); // indicate SDU to MAC ulsch_harq->status = SCH_IDLE; ulsch->harq_mask &= ~(1 << rdata->harq_pid); + T (T_ENB_PHY_ULSCH_UE_ACK, T_INT(eNB->Mod_id), T_INT(rdata->frame), T_INT(rdata->subframe), T_INT(ulsch->rnti), + T_INT(rdata->harq_pid)); } // ulsch not in error if (ulsch_harq->O_ACK>0) From b0b03700caa9c5dadc424a05855c0df9695cf836 Mon Sep 17 00:00:00 2001 From: Sakthivel Velumani Date: Thu, 9 Jul 2020 16:16:44 +0200 Subject: [PATCH 467/553] bugfix in pucch tx --- openair1/SCHED_NR_UE/pucch_uci_ue_nr.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c index 2110cf2ad1..ccbe502194 100644 --- a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c +++ b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c @@ -1050,6 +1050,7 @@ boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, NR_UE_MAC_INST_t *mac, uint8 int find_pucch_resource_set(NR_UE_MAC_INST_t *mac, uint8_t gNB_id, int uci_size) { int pucch_resource_set_id = 0; + long *pucch_max_pl_bits = NULL; /* from TS 38.331 field maxPayloadMinus1 -- Maximum number of payload bits minus 1 that the UE may transmit using this PUCCH resource set. In a PUCCH occurrence, the UE @@ -1061,7 +1062,8 @@ int find_pucch_resource_set(NR_UE_MAC_INST_t *mac, uint8_t gNB_id, int uci_size) /* look for the first resource set which supports uci_size number of bits for payload */ while (pucch_resource_set_id < MAX_NB_OF_PUCCH_RESOURCE_SETS) { if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[pucch_resource_set_id] != NULL) { - if (uci_size <= mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[pucch_resource_set_id]->maxPayloadMinus1[0] + 1) { + pucch_max_pl_bits = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[pucch_resource_set_id]->maxPayloadMinus1; + if (uci_size <= (((pucch_max_pl_bits != NULL) ? *pucch_max_pl_bits : 1706) + 1)) { NR_TST_PHY_PRINTF("PUCCH found resource set %d \n", pucch_resource_set_id); return (pucch_resource_set_id); break; From d66aea3fe610037008070018caa255237ce8fd9e Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Thu, 9 Jul 2020 17:57:39 +0200 Subject: [PATCH 468/553] bugfixes in dci size --- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index a4097e4d32..3ffa1beaad 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -1979,8 +1979,10 @@ uint16_t nr_dci_size(NR_ServingCellConfigCommon_t *scc, if (srs_config->srs_ResourceSetToAddModList->list.array[i]->usage == NR_SRS_ResourceSet__usage_codebook) count++; } - if (count>1) + if (count>1) { dci_pdu->srs_resource_indicator.nbits = 1; + size += dci_pdu->srs_resource_indicator.nbits; + } } else { int lmin,Lmax = 0; @@ -2003,11 +2005,12 @@ uint16_t nr_dci_size(NR_ServingCellConfigCommon_t *scc, } } dci_pdu->srs_resource_indicator.nbits = (int)ceil(log2(lsum)); + size += dci_pdu->srs_resource_indicator.nbits; } } - size += dci_pdu->srs_resource_indicator.nbits; // Precoding info and number of layers long transformPrecoder; + dci_pdu->precoding_information.nbits = 0; if (pusch_Config->transformPrecoder == NULL){ // if transform precoder is null, apply the values from msg3 if(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder == NULL) From 5651b9073ce1af0b238954d6744863a273e5ad98 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Fri, 10 Jul 2020 09:16:11 +0200 Subject: [PATCH 469/553] pusch config in mac gnb from rrc --- .../nfapi/public_inc/nfapi_nr_interface_scf.h | 1 + openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c | 4 +- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 107 ++++++++++++++---- openair2/RRC/NR/rrc_gNB_reconfig.c | 3 +- 4 files changed, 88 insertions(+), 27 deletions(-) diff --git a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h index fea64e3f3e..e342ab0b67 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h @@ -1120,6 +1120,7 @@ typedef struct uint16_t ul_dmrs_symb_pos; uint8_t dmrs_config_type; uint16_t ul_dmrs_scrambling_id; + uint16_t pusch_identity; uint8_t scid; uint8_t num_dmrs_cdm_grps_no_data; uint16_t dmrs_ports;//DMRS ports. [TS38.212 7.3.1.1.2] provides description between DCI 0-1 content and DMRS ports. Bitmap occupying the 11 LSBs with: bit 0: antenna port 1000 bit 11: antenna port 1011 and for each bit 0: DMRS port not used 1: DMRS port used diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 2f264d9c7e..d02d9afcce 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -773,8 +773,8 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in uint16_t rnti = 0x1234; uint32_t rb_size = 50; uint32_t rb_start = 0; - uint8_t nr_of_symbols = 12; - uint8_t start_symbol_index = 2; + uint8_t nr_of_symbols = 11; + uint8_t start_symbol_index = 0; uint8_t nrOfLayers = 1; uint8_t mcs_index = 9; uint8_t mcs_table = 0; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index e9fbdf489c..a1ada71538 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -825,6 +825,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, SLIV2SL(startSymbolAndLength,&StartSymbolIndex,&NrOfSymbols); pusch_pdu->start_symbol_index = StartSymbolIndex; pusch_pdu->nr_of_symbols = NrOfSymbols; + mapping_type = ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[time_domain_assignment]->mappingType; if (ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[time_domain_assignment]->k2 != NULL) K2 = *ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[time_domain_assignment]->k2; @@ -848,8 +849,19 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, pusch_pdu->mcs_table = 0; //0: notqam256 [TS38.214, table 5.1.3.1-1] - corresponds to nr_target_code_rate_table1 in PHY pusch_pdu->target_code_rate = nr_get_code_rate_ul(pusch_pdu->mcs_index,pusch_pdu->mcs_table) ; pusch_pdu->qam_mod_order = nr_get_Qm_ul(pusch_pdu->mcs_index,pusch_pdu->mcs_table) ; - pusch_pdu->transform_precoding = 0; - pusch_pdu->data_scrambling_id = 0; //It equals the higher-layer parameter Data-scrambling-Identity if configured and the RNTI equals the C-RNTI, otherwise L2 needs to set it to physical cell id.; + if (pusch_Config->transformPrecoder == NULL) { + if (scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder == NULL) + pusch_pdu->transform_precoding = 1; + else + pusch_pdu->transform_precoding = 0; + } + else + pusch_pdu->transform_precoding = *pusch_Config->transformPrecoder; + if (pusch_Config->dataScramblingIdentityPUSCH != NULL) + pusch_pdu->data_scrambling_id = *pusch_Config->dataScramblingIdentityPUSCH; + else + pusch_pdu->data_scrambling_id = *scc->physCellId; + pusch_pdu->nrOfLayers = 1; //Pusch Allocation in frequency domain [TS38.214, sec 6.1.2.2] @@ -862,51 +874,98 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, AssertFatal(1==0,"Only frequency resource allocation type 1 is currently supported\n"); pusch_pdu->vrb_to_prb_mapping = 0; + if (pusch_Config->frequencyHopping==NULL) pusch_pdu->frequency_hopping = 0; else pusch_pdu->frequency_hopping = 1; + //pusch_pdu->tx_direct_current_location;//The uplink Tx Direct Current location for the carrier. Only values in the value range of this field between 0 and 3299, which indicate the subcarrier index within the carrier corresponding 1o the numerology of the corresponding uplink BWP and value 3300, which indicates "Outside the carrier" and value 3301, which indicates "Undetermined position within the carrier" are used. [TS38.331, UplinkTxDirectCurrentBWP IE] - pusch_pdu->uplink_frequency_shift_7p5khz = 0; + //pusch_pdu->uplink_frequency_shift_7p5khz = 0; // -------------------- // ------- DMRS ------- // -------------------- - uint16_t l_prime_mask = get_l_prime(pusch_pdu->nr_of_symbols, typeB, pusch_dmrs_pos0, pusch_len1); - pusch_pdu->ul_dmrs_symb_pos = l_prime_mask << pusch_pdu->start_symbol_index; - pusch_pdu->dmrs_config_type = 0; // dmrs-type 1 (the one with a single DMRS symbol in the beginning) - pusch_pdu->ul_dmrs_scrambling_id = 0; // If provided and the PUSCH is not a msg3 PUSCH, otherwise, L2 should set this to physical cell id - pusch_pdu->scid = 0; // DMRS sequence initialization [TS38.211, sec 6.4.1.1.1] - // Should match what is sent in DCI 0_1, otherwise set to 0 + NR_DMRS_UplinkConfig_t *NR_DMRS_UplinkConfig; + if (mapping_type == NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeA) + NR_DMRS_UplinkConfig = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA->choice.setup; + else + NR_DMRS_UplinkConfig = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup; + if (NR_DMRS_UplinkConfig->dmrs_Type == NULL) + pusch_pdu->dmrs_config_type = 0; + else + pusch_pdu->dmrs_config_type = 1; + pusch_pdu->scid = 0; // DMRS sequence initialization [TS38.211, sec 6.4.1.1.1] + if (pusch_pdu->transform_precoding) { // transform precoding disabled + long *scramblingid; + if (pusch_pdu->scid == 0) + scramblingid = NR_DMRS_UplinkConfig->transformPrecodingDisabled->scramblingID0; + else + scramblingid = NR_DMRS_UplinkConfig->transformPrecodingDisabled->scramblingID1; + if (scramblingid == NULL) + pusch_pdu->ul_dmrs_scrambling_id = *scc->physCellId; + else + pusch_pdu->ul_dmrs_scrambling_id = *scramblingid; + } + else { + pusch_pdu->ul_dmrs_scrambling_id = *scc->physCellId; + if (NR_DMRS_UplinkConfig->transformPrecodingEnabled->nPUSCH_Identity != NULL) + pusch_pdu->pusch_identity = *NR_DMRS_UplinkConfig->transformPrecodingEnabled->nPUSCH_Identity; + else + pusch_pdu->pusch_identity = *scc->physCellId; + } + pusch_dmrs_AdditionalPosition_t additional_pos; + if (NR_DMRS_UplinkConfig->dmrs_AdditionalPosition == NULL){printf("%d\n",2); + additional_pos = 2;} + else { + if (*NR_DMRS_UplinkConfig->dmrs_AdditionalPosition == NR_DMRS_UplinkConfig__dmrs_AdditionalPosition_pos3) + additional_pos = 3; + else + additional_pos = *NR_DMRS_UplinkConfig->dmrs_AdditionalPosition; + } + pusch_maxLength_t pusch_maxLength; + if (NR_DMRS_UplinkConfig->maxLength == NULL) + pusch_maxLength = 1; + else + pusch_maxLength = 2; + uint16_t l_prime_mask = get_l_prime(pusch_pdu->nr_of_symbols, mapping_type, additional_pos, pusch_maxLength); + pusch_pdu->ul_dmrs_symb_pos = l_prime_mask << pusch_pdu->start_symbol_index; + pusch_pdu->num_dmrs_cdm_grps_no_data = 1; - //pusch_pdu->dmrs_ports; // DMRS ports. [TS38.212 7.3.1.1.2] provides description between DCI 0-1 content and DMRS ports - // Bitmap occupying the 11 LSBs with: bit 0: antenna port 1000 bit 11: antenna port 1011, - // and for each bit 0: DMRS port not used 1: DMRS port used + pusch_pdu->dmrs_ports = 1; // -------------------------------------------------------------------------------------------------------------------------------------------- // -------------------- // ------- PTRS ------- // -------------------- - uint8_t ptrs_mcs1 = 2; // higher layer parameter in PTRS-UplinkConfig - uint8_t ptrs_mcs2 = 4; // higher layer parameter in PTRS-UplinkConfig - uint8_t ptrs_mcs3 = 10; // higher layer parameter in PTRS-UplinkConfig - uint16_t n_rb0 = 25; // higher layer parameter in PTRS-UplinkConfig - uint16_t n_rb1 = 75; // higher layer parameter in PTRS-UplinkConfig - pusch_pdu->pusch_ptrs.ptrs_time_density = get_L_ptrs(ptrs_mcs1, ptrs_mcs2, ptrs_mcs3, pusch_pdu->mcs_index, pusch_pdu->mcs_table); - pusch_pdu->pusch_ptrs.ptrs_freq_density = get_K_ptrs(n_rb0, n_rb1, pusch_pdu->rb_size); - pusch_pdu->pusch_ptrs.ptrs_ports_list = (nfapi_nr_ptrs_ports_t *) malloc(2*sizeof(nfapi_nr_ptrs_ports_t)); - pusch_pdu->pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset = 0; + if (NR_DMRS_UplinkConfig->phaseTrackingRS != NULL) { + // TODO to be fixed from RRC config + uint8_t ptrs_mcs1 = 2; // higher layer parameter in PTRS-UplinkConfig + uint8_t ptrs_mcs2 = 4; // higher layer parameter in PTRS-UplinkConfig + uint8_t ptrs_mcs3 = 10; // higher layer parameter in PTRS-UplinkConfig + uint16_t n_rb0 = 25; // higher layer parameter in PTRS-UplinkConfig + uint16_t n_rb1 = 75; // higher layer parameter in PTRS-UplinkConfig + pusch_pdu->pusch_ptrs.ptrs_time_density = get_L_ptrs(ptrs_mcs1, ptrs_mcs2, ptrs_mcs3, pusch_pdu->mcs_index, pusch_pdu->mcs_table); + pusch_pdu->pusch_ptrs.ptrs_freq_density = get_K_ptrs(n_rb0, n_rb1, pusch_pdu->rb_size); + pusch_pdu->pusch_ptrs.ptrs_ports_list = (nfapi_nr_ptrs_ports_t *) malloc(2*sizeof(nfapi_nr_ptrs_ports_t)); + pusch_pdu->pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset = 0; + + pusch_pdu->pdu_bit_map &= PUSCH_PDU_BITMAP_PUSCH_PTRS; // enable PUSCH PTRS + } + else{ +// if(1<pusch_ptrs.ptrs_time_density >= pusch_pdu->nr_of_symbols) + pusch_pdu->pdu_bit_map &= ~PUSCH_PDU_BITMAP_PUSCH_PTRS; // disable PUSCH PTRS + } - if(1<pusch_ptrs.ptrs_time_density >= pusch_pdu->nr_of_symbols) - pusch_pdu->pdu_bit_map &= ~PUSCH_PDU_BITMAP_PUSCH_PTRS; // disable PUSCH PTRS // -------------------------------------------------------------------------------------------------------------------------------------------- //Pusch Allocation in frequency domain [TS38.214, sec 6.1.2.2] //Optional Data only included if indicated in pduBitmap + // TODO from harq function as in pdsch pusch_pdu->pusch_data.rv_index = 0; pusch_pdu->pusch_data.harq_process_id = 0; - pusch_pdu->pusch_data.new_data_indicator = 0; + pusch_pdu->pusch_data.new_data_indicator = 1; uint8_t num_dmrs_symb = 0; diff --git a/openair2/RRC/NR/rrc_gNB_reconfig.c b/openair2/RRC/NR/rrc_gNB_reconfig.c index a99c1125e4..a7aa38dfe3 100644 --- a/openair2/RRC/NR/rrc_gNB_reconfig.c +++ b/openair2/RRC/NR/rrc_gNB_reconfig.c @@ -825,7 +825,8 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup = calloc(1,sizeof(*pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup)); NR_DMRS_UplinkConfig_t *NR_DMRS_UplinkConfig = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup; NR_DMRS_UplinkConfig->dmrs_Type = NULL; - NR_DMRS_UplinkConfig->dmrs_AdditionalPosition =NR_DMRS_UplinkConfig__dmrs_AdditionalPosition_pos0; + NR_DMRS_UplinkConfig->dmrs_AdditionalPosition = calloc(1,sizeof(*NR_DMRS_UplinkConfig->dmrs_AdditionalPosition)); + *NR_DMRS_UplinkConfig->dmrs_AdditionalPosition = NR_DMRS_UplinkConfig__dmrs_AdditionalPosition_pos0; NR_DMRS_UplinkConfig->phaseTrackingRS=NULL; NR_DMRS_UplinkConfig->maxLength=NULL; NR_DMRS_UplinkConfig->transformPrecodingDisabled = calloc(1,sizeof(*NR_DMRS_UplinkConfig->transformPrecodingDisabled)); From 96b5380b0282fb0a3fc70cfee22bf45288e3b2f4 Mon Sep 17 00:00:00 2001 From: Cedric Roux Date: Fri, 10 Jul 2020 12:44:59 +0200 Subject: [PATCH 470/553] minor: remove a LOG_E that should not be here anymore When running the softmodem, we get the error: fill_ulsch UE_id 0 nb_rb = 0 The code has changed some time ago and this log was left but is not meaningful anymore. --- openair1/PHY/LTE_TRANSPORT/dci_tools.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/openair1/PHY/LTE_TRANSPORT/dci_tools.c b/openair1/PHY/LTE_TRANSPORT/dci_tools.c index ce409de131..8de011acef 100644 --- a/openair1/PHY/LTE_TRANSPORT/dci_tools.c +++ b/openair1/PHY/LTE_TRANSPORT/dci_tools.c @@ -2006,11 +2006,6 @@ void fill_ulsch(PHY_VARS_eNB *eNB,int UE_id,nfapi_ul_config_ulsch_pdu *ulsch_pdu return; } - //AssertFatal(ulsch->harq_processes[harq_pid]->nb_rb>0,"nb_rb = 0\n"); - if(ulsch->harq_processes[harq_pid]->nb_rb == 0) { - LOG_E(PHY, "fill_ulsch UE_id %d nb_rb = 0\n", UE_id); - } - ulsch->harq_processes[harq_pid]->frame = frame; ulsch->harq_processes[harq_pid]->subframe = subframe; ulsch->harq_processes[harq_pid]->handled = 0; From 91480dccce68f740308c54be0ad7ae9c6d1d8b74 Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Mon, 13 Jul 2020 15:17:54 +0200 Subject: [PATCH 471/553] support for ocp enb build and test (unit test ok) --- ci-scripts/ran.py | 2 +- .../xml_files/enb_ocp_usrp210_build.xml | 2 +- ci-scripts/xml_files/fr1_multi_node_build.xml | 67 +++++++++++++++++++ 3 files changed, 69 insertions(+), 2 deletions(-) create mode 100644 ci-scripts/xml_files/fr1_multi_node_build.xml diff --git a/ci-scripts/ran.py b/ci-scripts/ran.py index 93ba859903..e09ce55634 100644 --- a/ci-scripts/ran.py +++ b/ci-scripts/ran.py @@ -440,7 +440,7 @@ class RANManagement(): logging.info('\u001B[1m Building OAI ' + self.air_interface + ' Pass\u001B[0m') if self.htmlObj is not None: self.htmlObj.CreateHtmlTestRow(self.Build_eNB_args, 'OK', CONST.ALL_PROCESSES_OK) - else + else: logging.error('\u001B[1m Building OAI ' + self.air_interface + ' Failed\u001B[0m') if self.htmlObj is not None: self.htmlObj.CreateHtmlTestRow(self.Build_eNB_args, 'KO', CONST.ALL_PROCESSES_OK) diff --git a/ci-scripts/xml_files/enb_ocp_usrp210_build.xml b/ci-scripts/xml_files/enb_ocp_usrp210_build.xml index 5729846818..8110c7f1b6 100644 --- a/ci-scripts/xml_files/enb_ocp_usrp210_build.xml +++ b/ci-scripts/xml_files/enb_ocp_usrp210_build.xml @@ -32,7 +32,7 @@ Build_eNB Build eNB OCP (USRP) - -I -w USRP -c --eNBocp --ninja + -w USRP -c --eNBocp diff --git a/ci-scripts/xml_files/fr1_multi_node_build.xml b/ci-scripts/xml_files/fr1_multi_node_build.xml new file mode 100644 index 0000000000..b2c0daa74e --- /dev/null +++ b/ci-scripts/xml_files/fr1_multi_node_build.xml @@ -0,0 +1,67 @@ + + + build-tab + Build + wrench + + 010101 010102 + 000101 000102 + + + + + Build_eNB + Build eNB + -w USRP -c --eNB --ninja + 0 + 0 + True + + + + WaitEndBuild_eNB + Wait for end of Build eNB + -w USRP -c --eNB --ninja + 0 + 0 + + + + Build_eNB + Build gNB + -w USRP -c --gNB --ninja + 1 + 1 + True + + + + WaitEndBuild_eNB + Wait for end of Build gNB + -w USRP -c --gNB --ninja + 1 + 1 + + + From 2e5d0db742c53972f462c05fb594272a728b0bd8 Mon Sep 17 00:00:00 2001 From: hardy Date: Mon, 13 Jul 2020 16:45:32 +0200 Subject: [PATCH 472/553] removed getter/setter from RAM class --- ci-scripts/main.py | 276 ++++++++++++++++++++++----------------------- ci-scripts/ran.py | 4 +- 2 files changed, 141 insertions(+), 139 deletions(-) diff --git a/ci-scripts/main.py b/ci-scripts/main.py index 22e4c8ad72..f7feeb08d4 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -112,10 +112,10 @@ class OaiCiTest(): SSH.open(self.UEIPAddress, self.UEUserName, self.UEPassword) result = re.search('--nrUE', self.Build_OAI_UE_args) if result is not None: - RAN.Setair_interface('nr') + RAN.air_interface='nr' ue_prefix = 'NR ' else: - RAN.Setair_interface('lte') + RAN.air_interface='lte' ue_prefix = '' result = re.search('([a-zA-Z0-9\:\-\.\/])+\.git', self.ranRepository) if result is not None: @@ -155,7 +155,7 @@ class OaiCiTest(): mismatch = True if not mismatch: SSH.close() - HTML.CreateHtmlTestRow(RAN.GetBuild_eNB_args(), 'OK', CONST.ALL_PROCESSES_OK) + HTML.CreateHtmlTestRow(RAN.Build_eNB_args, 'OK', CONST.ALL_PROCESSES_OK) return SSH.command('echo ' + self.UEPassword + ' | sudo -S git clean -x -d -ff', '\$', 30) @@ -181,7 +181,7 @@ class OaiCiTest(): SSH.command('ls ran_build/build', '\$', 3) SSH.command('ls ran_build/build', '\$', 3) buildStatus = True - result = re.search(RAN.Getair_interface() + '-uesoftmodem', SSH.getBefore()) + result = re.search(RAN.air_interface + '-uesoftmodem', SSH.getBefore()) if result is None: buildStatus = False SSH.command('mkdir -p build_log_' + self.testCase_id, '\$', 5) @@ -215,12 +215,12 @@ class OaiCiTest(): SSH.command('ls -ls /opt/flexran_rtc/*/rt_controller', '\$', 5) result = re.search('/opt/flexran_rtc/build/rt_controller', SSH.getBefore()) if result is not None: - RAN.SetflexranCtrlInstalled(True) + RAN.flexranCtrlInstalled=True logging.debug('Flexran Controller is installed') SSH.close() def InitializeFlexranCtrl(self): - if RAN.GetflexranCtrlInstalled() == False: + if RAN.flexranCtrlInstalled == False: return if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '': HELP.GenericHelp(CONST.Version) @@ -235,7 +235,7 @@ class OaiCiTest(): result = re.search('rt_controller -c ', SSH.getBefore()) if result is not None: logging.debug('\u001B[1m Initialize FlexRan Controller Completed\u001B[0m') - RAN.SetflexranCtrlStarted(True) + RAN.flexranCtrlStarted=True SSH.close() HTML.CreateHtmlTestRow('N/A', 'OK', CONST.ALL_PROCESSES_OK) @@ -306,7 +306,7 @@ class OaiCiTest(): if self.UEIPAddress == '' or self.UEUserName == '' or self.UEPassword == '' or self.UESourceCodePath == '': HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - if RAN.Getair_interface() == 'lte': + if RAN.air_interface == 'lte': result = re.search('--no-L2-connect', str(self.Initialize_OAI_UE_args)) if result is None: check_eNB = True @@ -335,13 +335,13 @@ class OaiCiTest(): # Initialize_OAI_UE_args usually start with -C and followed by the location in repository # in case of NR-UE, we may have rrc_config_path (Temporary?) modifiedUeOptions = str(self.Initialize_OAI_UE_args) - if RAN.Getair_interface() == 'nr': + if RAN.air_interface == 'nr': result = re.search('--rrc_config_path ', modifiedUeOptions) if result is not None: modifiedUeOptions = modifiedUeOptions.replace('rrc_config_path ', 'rrc_config_path ' + self.UESourceCodePath + '/') SSH.command('source oaienv', '\$', 5) SSH.command('cd cmake_targets/ran_build/build', '\$', 5) - if RAN.Getair_interface() == 'lte': + if RAN.air_interface == 'lte': result = re.search('--no-L2-connect', str(self.Initialize_OAI_UE_args)) # We may have to regenerate the .u* files if result is None: @@ -353,7 +353,7 @@ class OaiCiTest(): SSH.command('sed -e "s#93#92#" -e "s#8baf473f2f8fd09487cccbd7097c6862#fec86ba6eb707ed08905757b1bb44b8f#" -e "s#e734f8734007d6c5ce7a0508809e7e9c#C42449363BBAD02B66D16BC975D77CC1#" ../../../openair3/NAS/TOOLS/ue_eurecom_test_sfr.conf > ../../../openair3/NAS/TOOLS/ci-ue_eurecom_test_sfr.conf', '\$', 5) SSH.command('echo ' + self.UEPassword + ' | sudo -S rm -Rf .u*', '\$', 5) SSH.command('echo ' + self.UEPassword + ' | sudo -S ../../../targets/bin/conf2uedata -c ../../../openair3/NAS/TOOLS/ci-ue_eurecom_test_sfr.conf -o .', '\$', 5) - SSH.command('echo "ulimit -c unlimited && ./'+ RAN.Getair_interface() +'-uesoftmodem ' + modifiedUeOptions + '" > ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5) + SSH.command('echo "ulimit -c unlimited && ./'+ RAN.air_interface +'-uesoftmodem ' + modifiedUeOptions + '" > ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5) SSH.command('chmod 775 ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5) SSH.command('echo ' + self.UEPassword + ' | sudo -S rm -Rf ' + self.UESourceCodePath + '/cmake_targets/ue_' + self.testCase_id + '.log', '\$', 5) self.UELogFile = 'ue_' + self.testCase_id + '.log' @@ -384,7 +384,7 @@ class OaiCiTest(): doLoop = False continue SSH.command('stdbuf -o0 cat ue_' + self.testCase_id + '.log | egrep --text --color=never -i "wait|sync"', '\$', 4) - if RAN.Getair_interface() == 'nr': + if RAN.air_interface == 'nr': result = re.search('Starting sync detection', SSH.getBefore()) else: result = re.search('got sync', SSH.getBefore()) @@ -409,7 +409,7 @@ class OaiCiTest(): # That is the case for LTE # In NR case, it's a positive message that will show if synchronization occurs doLoop = True - if RAN.Getair_interface() == 'nr': + if RAN.air_interface == 'nr': loopCounter = 10 else: # We are now checking if sync w/ eNB DOES NOT OCCUR @@ -418,7 +418,7 @@ class OaiCiTest(): while (doLoop): loopCounter = loopCounter - 1 if (loopCounter == 0): - if RAN.Getair_interface() == 'nr': + if RAN.air_interface == 'nr': # Here we do have great chances that UE did NOT cell-sync w/ gNB doLoop = False fullSyncStatus = False @@ -437,7 +437,7 @@ class OaiCiTest(): fullSyncStatus = True continue SSH.command('stdbuf -o0 cat ue_' + self.testCase_id + '.log | egrep --text --color=never -i "wait|sync|Frequency"', '\$', 4) - if RAN.Getair_interface() == 'nr': + if RAN.air_interface == 'nr': # Positive messaging --> result = re.search('Measured Carrier Frequency', SSH.getBefore()) if result is not None: @@ -466,12 +466,12 @@ class OaiCiTest(): if fullSyncStatus and gotSyncStatus: doInterfaceCheck = False - if RAN.Getair_interface() == 'lte': + if RAN.air_interface == 'lte': result = re.search('--no-L2-connect', str(self.Initialize_OAI_UE_args)) if result is None: doInterfaceCheck = True # For the moment, only in explicit noS1 without kernel module (ie w/ tunnel interface) - if RAN.Getair_interface() == 'nr': + if RAN.air_interface == 'nr': result = re.search('--noS1 --nokrnmod 1', str(self.Initialize_OAI_UE_args)) if result is not None: doInterfaceCheck = True @@ -487,7 +487,7 @@ class OaiCiTest(): logging.debug(SSH.getBefore()) logging.error('\u001B[1m oaitun_ue1 interface is either NOT mounted or NOT configured\u001B[0m') tunnelInterfaceStatus = False - if RAN.GeteNBmbmsEnable(0): + if RAN.eNBmbmsEnables[0]: SSH.command('ifconfig oaitun_uem1', '\$', 4) result = re.search('inet addr', SSH.getBefore()) if result is not None: @@ -511,8 +511,8 @@ class OaiCiTest(): self.UEDevicesStatus = [] self.UEDevicesStatus.append(CONST.UE_STATUS_DETACHED) else: - if RAN.Getair_interface() == 'lte': - if RAN.GeteNBmbmsEnable(0): + if RAN.air_interface == 'lte': + if RAN.eNBmbmsEnables[0]: HTML.SethtmlUEFailureMsg('oaitun_ue1/oaitun_uem1 interfaces are either NOT mounted or NOT configured') else: HTML.SethtmlUEFailureMsg('oaitun_ue1 interface is either NOT mounted or NOT configured') @@ -887,7 +887,7 @@ class OaiCiTest(): self.UEDevicesStatus[cnt] = CONST.UE_STATUS_ATTACHED cnt += 1 HTML.CreateHtmlTestRowQueue('N/A', 'OK', len(self.UEDevices), html_queue) - result = re.search('T_stdout', str(RAN.GetInitialize_eNB_args())) + result = re.search('T_stdout', str(RAN.Initialize_eNB_args)) if result is not None: logging.debug('Waiting 5 seconds to fill up record file') time.sleep(5) @@ -933,7 +933,7 @@ class OaiCiTest(): for job in multi_jobs: job.join() HTML.CreateHtmlTestRow('N/A', 'OK', CONST.ALL_PROCESSES_OK) - result = re.search('T_stdout', str(RAN.GetInitialize_eNB_args())) + result = re.search('T_stdout', str(RAN.Initialize_eNB_args)) if result is not None: logging.debug('Waiting 5 seconds to fill up record file') time.sleep(5) @@ -1199,7 +1199,7 @@ class OaiCiTest(): i += 1 for job in multi_jobs: job.join() - if RAN.GetflexranCtrlInstalled() and RAN.GetflexranCtrlStarted(): + if RAN.flexranCtrlInstalled and RAN.flexranCtrlStarted: SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) SSH.command('cd /opt/flexran_rtc', '\$', 5) SSH.command('curl http://localhost:9999/stats | jq \'.\' > log/check_status_' + self.testCase_id + '.log 2>&1', '\$', 5) @@ -1409,7 +1409,7 @@ class OaiCiTest(): return ping_from_eNB = re.search('oaitun_enb1', str(self.ping_args)) if ping_from_eNB is not None: - if RAN.GeteNBIPAddress() == '' or RAN.GeteNBUserName() == '' or RAN.GeteNBPassword() == '': + if RAN.eNBIPAddress == '' or RAN.eNBUserName == '' or RAN.eNBPassword == '': HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') else: @@ -1418,8 +1418,8 @@ class OaiCiTest(): sys.exit('Insufficient Parameter') try: if ping_from_eNB is not None: - SSH.open(RAN.GeteNBIPAddress(), RAN.GeteNBUserName(), RAN.GeteNBPassword()) - SSH.command('cd ' + RAN.GeteNBSourceCodePath() + '/cmake_targets/', '\$', 5) + SSH.open(RAN.eNBIPAddress, RAN.eNBUserName, RAN.eNBPassword) + SSH.command('cd ' + RAN.eNBSourceCodePath + '/cmake_targets/', '\$', 5) else: SSH.open(self.UEIPAddress, self.UEUserName, self.UEPassword) SSH.command('cd ' + self.UESourceCodePath + '/cmake_targets/', '\$', 5) @@ -1483,7 +1483,7 @@ class OaiCiTest(): # copying on the EPC server for logCollection if ping_from_eNB is not None: - copyin_res = SSH.copyin(RAN.GeteNBIPAddress(), RAN.GeteNBUserName(), RAN.GeteNBPassword(), RAN.GeteNBSourceCodePath() + '/cmake_targets/ping_' + self.testCase_id + '.log', '.') + copyin_res = SSH.copyin(RAN.eNBIPAddress, RAN.eNBUserName, RAN.eNBPassword, RAN.eNBSourceCodePath + '/cmake_targets/ping_' + self.testCase_id + '.log', '.') else: copyin_res = SSH.copyin(self.UEIPAddress, self.UEUserName, self.UEPassword, self.UESourceCodePath + '/cmake_targets/ping_' + self.testCase_id + '.log', '.') if (copyin_res == 0): @@ -1492,7 +1492,7 @@ class OaiCiTest(): os.kill(os.getppid(),signal.SIGUSR1) def Ping(self): - result = re.search('noS1', str(RAN.GetInitialize_eNB_args())) + result = re.search('noS1', str(RAN.Initialize_eNB_args)) if result is not None: self.PingNoS1() return @@ -2123,7 +2123,7 @@ class OaiCiTest(): os.kill(os.getppid(),signal.SIGUSR1) def IperfNoS1(self): - if RAN.GeteNBIPAddress() == '' or RAN.GeteNBUserName() == '' or RAN.GeteNBPassword() == '' or self.UEIPAddress == '' or self.UEUserName == '' or self.UEPassword == '': + if RAN.eNBIPAddress == '' or RAN.eNBUserName == '' or RAN.eNBPassword == '' or self.UEIPAddress == '' or self.UEUserName == '' or self.UEPassword == '': HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') check_eNB = True @@ -2135,9 +2135,9 @@ class OaiCiTest(): return server_on_enb = re.search('-R', str(self.iperf_args)) if server_on_enb is not None: - iServerIPAddr = RAN.GeteNBIPAddress() - iServerUser = RAN.GeteNBUserName() - iServerPasswd = RAN.GeteNBPassword() + iServerIPAddr = RAN.eNBIPAddress + iServerUser = RAN.eNBUserName + iServerPasswd = RAN.eNBPassword iClientIPAddr = self.UEIPAddress iClientUser = self.UEUserName iClientPasswd = self.UEPassword @@ -2145,9 +2145,9 @@ class OaiCiTest(): iServerIPAddr = self.UEIPAddress iServerUser = self.UEUserName iServerPasswd = self.UEPassword - iClientIPAddr = RAN.GeteNBIPAddress() - iClientUser = RAN.GeteNBUserName() - iClientPasswd = RAN.GeteNBPassword() + iClientIPAddr = RAN.eNBIPAddress + iClientUser = RAN.eNBUserName + iClientPasswd = RAN.eNBPassword if self.iperf_options != 'sink': # Starting the iperf server SSH.open(iServerIPAddr, iServerUser, iServerPasswd) @@ -2232,7 +2232,7 @@ class OaiCiTest(): self.AutoTerminateUEandeNB() def Iperf(self): - result = re.search('noS1', str(RAN.GetInitialize_eNB_args())) + result = re.search('noS1', str(RAN.Initialize_eNB_args)) if result is not None: self.IperfNoS1() return @@ -2313,7 +2313,7 @@ class OaiCiTest(): status_queue = SimpleQueue() # in noS1 config, no need to check status from EPC # in gNB also currently no need to check - result = re.search('noS1|band78', str(RAN.GetInitialize_eNB_args())) + result = re.search('noS1|band78', str(RAN.Initialize_eNB_args)) if result is None: p = Process(target = EPC.CheckHSSProcess, args = (status_queue,)) p.daemon = True @@ -2352,14 +2352,14 @@ class OaiCiTest(): if (status < 0): result = status if result == CONST.ENB_PROCESS_FAILED: - fileCheck = re.search('enb_', str(RAN.GeteNBLogFile(0))) + fileCheck = re.search('enb_', str(RAN.eNBLogFiles[0])) if fileCheck is not None: - SSH.copyin(RAN.GeteNBIPAddress(), RAN.GeteNBUserName(), RAN.GeteNBPassword(), RAN.GeteNBSourceCodePath() + '/cmake_targets/' + RAN.GeteNBLogFile(0), '.') - logStatus = RAN.AnalyzeLogFile_eNB(RAN.GeteNBLogFile[0]) + SSH.copyin(RAN.eNBIPAddress, RAN.eNBUserName, RAN.eNBPassword, RAN.eNBSourceCodePath + '/cmake_targets/' + RAN.eNBLogFiles[0], '.') + logStatus = RAN.AnalyzeLogFile_eNB(RAN.eNBLogFiles[0]) if logStatus < 0: result = logStatus - RAN.SeteNBLogFile('', 0) - if RAN.GetflexranCtrlInstalled() and RAN.GetflexranCtrlStarted(): + RAN.eNBLogFiles[0]='' + if RAN.flexranCtrlInstalled and RAN.flexranCtrlStarted: self.TerminateFlexranCtrl() return result @@ -2394,8 +2394,8 @@ class OaiCiTest(): def CheckOAIUEProcess(self, status_queue): try: SSH.open(self.UEIPAddress, self.UEUserName, self.UEPassword) - SSH.command('stdbuf -o0 ps -aux | grep --color=never ' + RAN.Getair_interface() + '-uesoftmodem | grep -v grep', '\$', 5) - result = re.search(RAN.Getair_interface() + '-uesoftmodem', SSH.getBefore()) + SSH.command('stdbuf -o0 ps -aux | grep --color=never ' + RAN.air_interface + '-uesoftmodem | grep -v grep', '\$', 5) + result = re.search(RAN.air_interface + '-uesoftmodem', SSH.getBefore()) if result is None: logging.debug('\u001B[1;37;41m OAI UE Process Not Found! \u001B[0m') status_queue.put(CONST.OAI_UE_PROCESS_FAILED) @@ -2494,7 +2494,7 @@ class OaiCiTest(): result = re.search('No cell synchronization found, abandoning', str(line)) if result is not None: no_cell_sync_found = True - if RAN.GeteNBmbmsEnable(0): + if RAN.eNBmbmsEnables[0]: result = re.search('TRIED TO PUSH MBMS DATA', str(line)) if result is not None: mbms_messages += 1 @@ -2620,7 +2620,7 @@ class OaiCiTest(): statMsg = 'UE showed ' + str(fatalErrorCount) + ' "MAC BSR Triggered ReTxBSR Timer expiry" message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n') - if RAN.GeteNBmbmsEnable(0): + if RAN.eNBmbmsEnables[0]: if mbms_messages > 0: statMsg = 'UE showed ' + str(mbms_messages) + ' "TRIED TO PUSH MBMS DATA" message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') @@ -2660,7 +2660,7 @@ class OaiCiTest(): def TerminateFlexranCtrl(self): - if RAN.GetflexranCtrlInstalled() == False or RAN.GetflexranCtrlStarted() == False: + if RAN.flexranCtrlInstalled == False or RAN.flexranCtrlStarted == False: return if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '': HELP.GenericHelp(CONST.Version) @@ -2671,7 +2671,7 @@ class OaiCiTest(): SSH.command('echo ' + EPC.GetPassword() + ' | sudo -S killall --signal SIGKILL rt_controller', '\$', 5) time.sleep(1) SSH.close() - RAN.SetflexranCtrlStarted(False) + RAN.flexranCtrlStarted=False HTML.CreateHtmlTestRow('N/A', 'OK', CONST.ALL_PROCESSES_OK) def TerminateUE_common(self, device_id, idx): @@ -2752,7 +2752,7 @@ class OaiCiTest(): logging.debug('\u001B[1m' + ueAction + ' Failed \u001B[0m') HTML.SethtmlUEFailureMsg('' + ueAction + ' Failed\n' + HTML.GethtmlUEFailureMsg()) HTML.CreateHtmlTestRow('N/A', 'KO', logStatus, 'UE') - if RAN.Getair_interface() == 'lte': + if RAN.air_interface == 'lte': # In case of sniffing on commercial eNBs we have random results # Not an error then if (logStatus != CONST.OAI_UE_PROCESS_COULD_NOT_SYNC) or (ueAction != 'Sniffing'): @@ -2785,22 +2785,22 @@ class OaiCiTest(): HTML.Setdesc('Automatic Termination of OAI-UE') self.ShowTestID() self.TerminateOAIUE() - if (RAN.GetInitialize_eNB_args() != ''): + if (RAN.Initialize_eNB_args != ''): self.testCase_id = 'AUTO-KILL-eNB' HTML.SettestCase_id(self.testCase_id) self.desc = 'Automatic Termination of eNB' HTML.Setdesc('Automatic Termination of eNB') self.ShowTestID() - RAN.SeteNB_instance('0') + RAN.eNB_instance='0' RAN.TerminateeNB() - if RAN.GetflexranCtrlInstalled() and RAN.GetflexranCtrlStarted(): + if RAN.flexranCtrlInstalled and RAN.flexranCtrlStarted: self.testCase_id = 'AUTO-KILL-flexran-ctl' HTML.SettestCase_id(self.testCase_id) self.desc = 'Automatic Termination of FlexRan CTL' HTML.Setdesc('Automatic Termination of FlexRan CTL') self.ShowTestID() self.TerminateFlexranCtrl() - RAN.SetprematureExit(True) + RAN.prematureExit=True def IdleSleep(self): time.sleep(self.idle_sleep_time) @@ -2856,7 +2856,7 @@ class OaiCiTest(): logging.debug(msg) fullMessage += msg + '\n' if self.x2_ho_options == 'network': - if RAN.GetflexranCtrlInstalled() and RAN.GetflexranCtrlStarted(): + if RAN.flexranCtrlInstalled and RAN.flexranCtrlStarted: self.x2ENBBsIds = [] self.x2ENBConnectedUEs = [] self.x2ENBBsIds.append([]) @@ -2917,11 +2917,11 @@ class OaiCiTest(): HTML.CreateHtmlTestRow('Cannot perform requested X2 Handover', 'KO', CONST.ALL_PROCESSES_OK) def LogCollectBuild(self): - if (RAN.GeteNBIPAddress() != '' and RAN.GeteNBUserName() != '' and RAN.GeteNBPassword() != ''): - IPAddress = RAN.GeteNBIPAddress() - UserName = RAN.GeteNBUserName() - Password = RAN.GeteNBPassword() - SourceCodePath = RAN.GeteNBSourceCodePath() + if (RAN.eNBIPAddress != '' and RAN.eNBUserName != '' and RAN.eNBPassword != ''): + IPAddress = RAN.eNBIPAddress + UserName = RAN.eNBUserName + Password = RAN.eNBPassword + SourceCodePath = RAN.eNBSourceCodePath elif (self.UEIPAddress != '' and self.UEUserName != '' and self.UEPassword != ''): IPAddress = self.UEIPAddress UserName = self.UEUserName @@ -2963,7 +2963,7 @@ class OaiCiTest(): SSH.close() def RetrieveSystemVersion(self, machine): - if RAN.GeteNBIPAddress() == 'none' or self.UEIPAddress == 'none': + if RAN.eNBIPAddress == 'none' or self.UEIPAddress == 'none': HTML.SetOsVersion('Ubuntu 16.04.5 LTS', 0) HTML.SetKernelVersion('4.15.0-45-generic', 0) HTML.SetUhdVersion('3.13.0.1-0', 0) @@ -2973,10 +2973,10 @@ class OaiCiTest(): HTML.SetCpuMHz('2399.996 MHz', 0) return 0 if machine == 'eNB': - if RAN.GeteNBIPAddress() != '' and RAN.GeteNBUserName() != '' and RAN.GeteNBPassword() != '': - IPAddress = RAN.GeteNBIPAddress() - UserName = RAN.GeteNBUserName() - Password = RAN.GeteNBPassword() + if RAN.eNBIPAddress != '' and RAN.eNBUserName != '' and RAN.eNBPassword != '': + IPAddress = RAN.eNBIPAddress + UserName = RAN.eNBUserName + Password = RAN.eNBPassword idx = 0 else: return -1 @@ -3070,47 +3070,47 @@ def CheckClassValidity(action,id): def GetParametersFromXML(action): if action == 'Build_eNB': - RAN.SetBuild_eNB_args(test.findtext('Build_eNB_args')) + RAN.Build_eNB_args=test.findtext('Build_eNB_args') forced_workspace_cleanup = test.findtext('forced_workspace_cleanup') if (forced_workspace_cleanup is None): - RAN.SetBuild_eNB_forced_workspace_cleanup(False) + RAN.Build_eNB_forced_workspace_cleanup=False else: if re.match('true', forced_workspace_cleanup, re.IGNORECASE): - RAN.SetBuild_eNB_forced_workspace_cleanup(True) + RAN.Build_eNB_forced_workspace_cleanup=True else: - RAN.SetBuild_eNB_forced_workspace_cleanup(False) - RAN.SeteNB_instance(test.findtext('eNB_instance')) - if (RAN.GeteNB_instance() is None): - RAN.SeteNB_instance('0') - RAN.SeteNB_serverId(test.findtext('eNB_serverId')) - if (RAN.GeteNB_serverId() is None): - RAN.SeteNB_serverId('0') + RAN.Build_eNB_forced_workspace_cleanup=False + RAN.eNB_instance=test.findtext('eNB_instance') + if (RAN.eNB_instance is None): + RAN.eNB_instance='0' + RAN.eNB_serverId=test.findtext('eNB_serverId') + if (RAN.eNB_serverId is None): + RAN.eNB_serverId='0' xmlBgBuildField = test.findtext('backgroundBuild') if (xmlBgBuildField is None): - RAN.SetbackgroundBuild(False) + RAN.backgroundBuild=False else: if re.match('true', xmlBgBuildField, re.IGNORECASE): - RAN.SetbackgroundBuild(True) + RAN.backgroundBuild=True else: - RAN.SetbackgroundBuild(False) + RAN.backgroundBuild=False if action == 'WaitEndBuild_eNB': - RAN.SetBuild_eNB_args(test.findtext('Build_eNB_args')) - RAN.SeteNB_instance(test.findtext('eNB_instance')) - if (RAN.GeteNB_instance() is None): - RAN.SeteNB_instance('0') - RAN.SeteNB_serverId(test.findtext('eNB_serverId')) - if (RAN.GeteNB_serverId() is None): - RAN.SeteNB_serverId('0') + RAN.Build_eNB_args=test.findtext('Build_eNB_args') + RAN.eNB_instance=test.findtext('eNB_instance') + if (RAN.eNB_instance is None): + RAN.eNB_instance='0' + RAN.eNB_serverId=test.findtext('eNB_serverId') + if (RAN.eNB_serverId is None): + RAN.eNB_serverId='0' if action == 'Initialize_eNB': - RAN.SetInitialize_eNB_args(test.findtext('Initialize_eNB_args')) - RAN.SeteNB_instance(test.findtext('eNB_instance')) - if (RAN.GeteNB_instance() is None): - RAN.SeteNB_instance('0') - RAN.SeteNB_serverId(test.findtext('eNB_serverId')) - if (RAN.GeteNB_serverId() is None): - RAN.SeteNB_serverId('0') + RAN.Initialize_eNB_args=test.findtext('Initialize_eNB_args') + RAN.eNB_instance=test.findtext('eNB_instance') + if (RAN.eNB_instance is None): + RAN.eNB_instance='0' + RAN.eNB_serverId=test.findtext('eNB_serverId') + if (RAN.eNB_serverId is None): + RAN.eNB_serverId='0' #local variable air_interface air_interface = test.findtext('air_interface') @@ -3120,15 +3120,15 @@ def GetParametersFromXML(action): CiTestObj.air_interface = air_interface.lower() +'-softmodem' else : CiTestObj.air_interface = air_interface.lower() +'ocp-enb' - RAN.Setair_interface(CiTestObj.air_interface) + RAN.air_interface(CiTestObj.air_interface) if action == 'Terminate_eNB': - RAN.SeteNB_instance(test.findtext('eNB_instance')) - if (RAN.GeteNB_instance() is None): - RAN.SeteNB_instance('0') - RAN.SeteNB_serverId(test.findtext('eNB_serverId')) - if (RAN.GeteNB_serverId() is None): - RAN.SeteNB_serverId('0') + RAN.eNB_instance=test.findtext('eNB_instance') + if (RAN.eNB_instance is None): + RAN.eNB_instance='0' + RAN.eNB_serverId=test.findtext('eNB_serverId') + if (RAN.eNB_serverId is None): + RAN.eNB_serverId='0' #local variable air_interface air_interface = test.findtext('air_interface') @@ -3138,7 +3138,7 @@ def GetParametersFromXML(action): CiTestObj.air_interface = air_interface.lower() +'-softmodem' else : CiTestObj.air_interface = air_interface.lower() +'ocp-enb' - RAN.Setair_interface(CiTestObj.air_interface) + RAN.air_interface=CiTestObj.air_interface if action == 'Attach_UE': nbMaxUEtoAttach = test.findtext('nbMaxUEtoAttach') @@ -3176,10 +3176,10 @@ def GetParametersFromXML(action): CiTestObj.air_interface = air_interface.lower() +'-softmodem' else : CiTestObj.air_interface = air_interface.lower() +'ocp-enb' - RAN.Setair_interface(CiTestObj.air_interface) + RAN.air_interface=CiTestObj.air_interface if action == 'Terminate_OAI_UE': - RAN.SeteNB_instance(test.findtext('UE_instance')) + RAN.eNB_instance=test.findtext('UE_instance') if (CiTestObj.UE_instance is None): CiTestObj.UE_instance = '0' @@ -3268,8 +3268,8 @@ RAN = ran.RANManagement() HTML = html.HTMLManagement() EPC.SetHtmlObj(HTML) -RAN.SetHtmlObj(HTML) -RAN.SetEpcObj(EPC) +RAN.HtmlObj=HTML +RAN.EpcObj=EPC import cls_physim #class PhySim for physical simulators build and test ldpc=cls_physim.PhySim() #create an instance for LDPC test using GPU or CPU build @@ -3293,7 +3293,7 @@ while len(argvs) > 1: else: matchReg = re.match('^\-\-ranRepository=(.+)$', myArgv, re.IGNORECASE) CiTestObj.ranRepository = matchReg.group(1) - RAN.SetranRepository(matchReg.group(1)) + RAN.ranRepository=matchReg.group(1) HTML.SetranRepository(matchReg.group(1)) ldpc.ranRepository=matchReg.group(1) elif re.match('^\-\-eNB_AllowMerge=(.+)$|^\-\-ranAllowMerge=(.+)$', myArgv, re.IGNORECASE): @@ -3305,7 +3305,7 @@ while len(argvs) > 1: ldpc.ranAllowMerge=matchReg.group(1) if ((doMerge == 'true') or (doMerge == 'True')): CiTestObj.ranAllowMerge = True - RAN.SetranAllowMerge(True) + RAN.ranAllowMerge=True HTML.SetranAllowMerge(True) elif re.match('^\-\-eNBBranch=(.+)$|^\-\-ranBranch=(.+)$', myArgv, re.IGNORECASE): if re.match('^\-\-eNBBranch=(.+)$', myArgv, re.IGNORECASE): @@ -3313,7 +3313,7 @@ while len(argvs) > 1: else: matchReg = re.match('^\-\-ranBranch=(.+)$', myArgv, re.IGNORECASE) CiTestObj.ranBranch = matchReg.group(1) - RAN.SetranBranch(matchReg.group(1)) + RAN.ranBranch=matchReg.group(1) HTML.SetranBranch(matchReg.group(1)) ldpc.ranBranch=matchReg.group(1) elif re.match('^\-\-eNBCommitID=(.*)$|^\-\-ranCommitID=(.*)$', myArgv, re.IGNORECASE): @@ -3322,7 +3322,7 @@ while len(argvs) > 1: else: matchReg = re.match('^\-\-ranCommitID=(.*)$', myArgv, re.IGNORECASE) CiTestObj.ranCommitID = matchReg.group(1) - RAN.SetranCommitID(matchReg.group(1)) + RAN.ranCommitID=matchReg.group(1) HTML.SetranCommitID(matchReg.group(1)) ldpc.ranCommitID=matchReg.group(1) elif re.match('^\-\-eNBTargetBranch=(.*)$|^\-\-ranTargetBranch=(.*)$', myArgv, re.IGNORECASE): @@ -3331,53 +3331,53 @@ while len(argvs) > 1: else: matchReg = re.match('^\-\-ranTargetBranch=(.*)$', myArgv, re.IGNORECASE) CiTestObj.ranTargetBranch = matchReg.group(1) - RAN.SetranTargetBranch(matchReg.group(1)) + RAN.ranTargetBranch=matchReg.group(1) HTML.SetranTargetBranch(matchReg.group(1)) ldpc.ranTargetBranch=matchReg.group(1) elif re.match('^\-\-eNBIPAddress=(.+)$|^\-\-eNB[1-2]IPAddress=(.+)$', myArgv, re.IGNORECASE): if re.match('^\-\-eNBIPAddress=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNBIPAddress=(.+)$', myArgv, re.IGNORECASE) - RAN.SeteNBIPAddress(matchReg.group(1)) + RAN.eNBIPAddress=matchReg.group(1) ldpc.eNBIpAddr=matchReg.group(1) elif re.match('^\-\-eNB1IPAddress=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB1IPAddress=(.+)$', myArgv, re.IGNORECASE) - RAN.SeteNB1IPAddress(matchReg.group(1)) + RAN.eNB1IPAddress=matchReg.group(1) elif re.match('^\-\-eNB2IPAddress=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB2IPAddress=(.+)$', myArgv, re.IGNORECASE) - RAN.SeteNB2IPAddress(matchReg.group(1)) + RAN.eNB2IPAddress=matchReg.group(1) elif re.match('^\-\-eNBUserName=(.+)$|^\-\-eNB[1-2]UserName=(.+)$', myArgv, re.IGNORECASE): if re.match('^\-\-eNBUserName=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNBUserName=(.+)$', myArgv, re.IGNORECASE) - RAN.SeteNBUserName(matchReg.group(1)) + RAN.eNBUserName=matchReg.group(1) ldpc.eNBUserName=matchReg.group(1) elif re.match('^\-\-eNB1UserName=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB1UserName=(.+)$', myArgv, re.IGNORECASE) - RAN.SeteNB1UserName(matchReg.group(1)) + RAN.eNB1UserName=matchReg.group(1) elif re.match('^\-\-eNB2UserName=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB2UserName=(.+)$', myArgv, re.IGNORECASE) - RAN.SeteNB2UserName(matchReg.group(1)) + RAN.eNB2UserName=matchReg.group(1) elif re.match('^\-\-eNBPassword=(.+)$|^\-\-eNB[1-2]Password=(.+)$', myArgv, re.IGNORECASE): if re.match('^\-\-eNBPassword=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNBPassword=(.+)$', myArgv, re.IGNORECASE) - RAN.SeteNBPassword(matchReg.group(1)) + RAN.eNBPassword=matchReg.group(1) ldpc.eNBPassWord=matchReg.group(1) elif re.match('^\-\-eNB1Password=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB1Password=(.+)$', myArgv, re.IGNORECASE) - RAN.SeteNB1Password(matchReg.group(1)) + RAN.eNB1Password=matchReg.group(1) elif re.match('^\-\-eNB2Password=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB2Password=(.+)$', myArgv, re.IGNORECASE) - RAN.SeteNB2Password(matchReg.group(1)) + RAN.eNB2Password=matchReg.group(1) elif re.match('^\-\-eNBSourceCodePath=(.+)$|^\-\-eNB[1-2]SourceCodePath=(.+)$', myArgv, re.IGNORECASE): if re.match('^\-\-eNBSourceCodePath=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNBSourceCodePath=(.+)$', myArgv, re.IGNORECASE) - RAN.SeteNBSourceCodePath(matchReg.group(1)) + RAN.eNBSourceCodePath=matchReg.group(1) ldpc.eNBSourceCodePath=matchReg.group(1) elif re.match('^\-\-eNB1SourceCodePath=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB1SourceCodePath=(.+)$', myArgv, re.IGNORECASE) - RAN.SeteNB1SourceCodePath(matchReg.group(1)) + RAN.eNB1SourceCodePath=matchReg.group(1) elif re.match('^\-\-eNB2SourceCodePath=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNB2SourceCodePath=(.+)$', myArgv, re.IGNORECASE) - RAN.SeteNB2SourceCodePath(matchReg.group(1)) + RAN.eNB2SourceCodePath=matchReg.group(1) elif re.match('^\-\-EPCIPAddress=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-EPCIPAddress=(.+)$', myArgv, re.IGNORECASE) EPC.SetIPAddress(matchReg.group(1)) @@ -3444,12 +3444,12 @@ while len(argvs) > 1: sys.exit('Invalid Parameter: ' + myArgv) if re.match('^TerminateeNB$', mode, re.IGNORECASE): - if RAN.GeteNBIPAddress() == '' or RAN.GeteNBUserName() == '' or RAN.GeteNBPassword() == '': + if RAN.eNBIPAddress == '' or RAN.eNBUserName == '' or RAN.eNBPassword == '': HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - RAN.SeteNB_serverId('0') - RAN.SeteNB_instance('0') - RAN.SeteNBSourceCodePath('/tmp/') + RAN.eNB_serverId='0' + RAN.eNB_instance='0' + RAN.eNBSourceCodePath='/tmp/' RAN.TerminateeNB() elif re.match('^TerminateUE$', mode, re.IGNORECASE): if (CiTestObj.ADBIPAddress == '' or CiTestObj.ADBUserName == '' or CiTestObj.ADBPassword == ''): @@ -3479,12 +3479,12 @@ elif re.match('^TerminateSPGW$', mode, re.IGNORECASE): sys.exit('Insufficient Parameter') EPC.TerminateSPGW() elif re.match('^LogCollectBuild$', mode, re.IGNORECASE): - if (RAN.GeteNBIPAddress() == '' or RAN.GeteNBUserName() == '' or RAN.GeteNBPassword() == '' or RAN.GeteNBSourceCodePath() == '') and (CiTestObj.UEIPAddress == '' or CiTestObj.UEUserName == '' or CiTestObj.UEPassword == '' or CiTestObj.UESourceCodePath == ''): + if (RAN.eNBIPAddress == '' or RAN.eNBUserName == '' or RAN.eNBPassword == '' or RAN.eNBSourceCodePath == '') and (CiTestObj.UEIPAddress == '' or CiTestObj.UEUserName == '' or CiTestObj.UEPassword == '' or CiTestObj.UESourceCodePath == ''): HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') CiTestObj.LogCollectBuild() elif re.match('^LogCollecteNB$', mode, re.IGNORECASE): - if RAN.GeteNBIPAddress() == '' or RAN.GeteNBUserName() == '' or RAN.GeteNBPassword() == '' or RAN.GeteNBSourceCodePath() == '': + if RAN.eNBIPAddress == '' or RAN.eNBUserName == '' or RAN.eNBPassword == '' or RAN.eNBSourceCodePath == '': HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') RAN.LogCollecteNB() @@ -3559,14 +3559,14 @@ elif re.match('^FinalizeHtml$', mode, re.IGNORECASE): HTML.CreateHtmlFooter(CiTestObj.finalStatus) elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re.IGNORECASE): if re.match('^TesteNB$', mode, re.IGNORECASE): - if RAN.GeteNBIPAddress() == '' or RAN.GetranRepository() == '' or RAN.GetranBranch() == '' or RAN.GeteNBUserName() == '' or RAN.GeteNBPassword() == '' or RAN.GeteNBSourceCodePath() == '' or EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetType() == '' or EPC.GetSourceCodePath() == '' or CiTestObj.ADBIPAddress == '' or CiTestObj.ADBUserName == '' or CiTestObj.ADBPassword == '': + if RAN.eNBIPAddress == '' or RAN.ranRepository == '' or RAN.ranBranch == '' or RAN.eNBUserName == '' or RAN.eNBPassword == '' or RAN.eNBSourceCodePath == '' or EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.Type == '' or EPC.SourceCodePath == '' or CiTestObj.ADBIPAddress == '' or CiTestObj.ADBUserName == '' or CiTestObj.ADBPassword == '': HELP.GenericHelp(CONST.Version) if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetSourceCodePath() == '' or EPC.GetType() == '': HELP.EPCSrvHelp(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), EPC.GetSourceCodePath(), EPC.GetType()) - if RAN.GetranRepository() == '': - HELP.GitSrvHelp(RAN.GetranRepository(), RAN.GetranBranch(), RAN.GetranCommitID(), RAN.GetranAllowMerge(), RAN.GetranTargetBranch()) - if RAN.GeteNBIPAddress() == '' or RAN.GeteNBUserName() == '' or RAN.GeteNBPassword() == '' or RAN.GeteNBSourceCodePath() == '': - HELP.eNBSrvHelp(RAN.GeteNBIPAddress(), RAN.GeteNBUserName(), RAN.GeteNBPassword(), RAN.GeteNBSourceCodePath()) + if RAN.ranRepository == '': + HELP.GitSrvHelp(RAN.ranRepository, RAN.ranBranch, RAN.ranCommitID, RAN.ranAllowMerge, RAN.ranTargetBranch) + if RAN.eNBIPAddress == '' or RAN.eNBUserName == '' or RAN.eNBPassword == '' or RAN.eNBSourceCodePath == '': + HELP.eNBSrvHelp(RAN.eNBIPAddress, RAN.eNBUserName, RAN.eNBPassword, RAN.eNBSourceCodePath) sys.exit('Insufficient Parameter') if (EPC.GetIPAddress() != '') and (EPC.GetIPAddress() != 'none'): @@ -3644,18 +3644,18 @@ elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re HTML.CreateHtmlTabHeader() CiTestObj.FailReportCnt = 0 - RAN.SetprematureExit(True) + RAN.prematureExit=True HTML.SetstartTime(int(round(time.time() * 1000))) - while CiTestObj.FailReportCnt < CiTestObj.repeatCounts[0] and RAN.GetprematureExit(): - RAN.SetprematureExit(False) + while CiTestObj.FailReportCnt < CiTestObj.repeatCounts[0] and RAN.prematureExit: + RAN.prematureExit=False # At every iteratin of the retry loop, a separator will be added # pass CiTestObj.FailReportCnt as parameter of HTML.CreateHtmlRetrySeparator HTML.CreateHtmlRetrySeparator(CiTestObj.FailReportCnt) for test_case_id in todo_tests: - if RAN.GetprematureExit(): + if RAN.prematureExit: break for test in all_tests: - if RAN.GetprematureExit(): + if RAN.prematureExit: break id = test.get('id') if test_case_id != id: @@ -3681,7 +3681,7 @@ elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re elif action == 'Initialize_eNB': check_eNB = False check_OAI_UE = False - RAN.SetpStatus(CiTestObj.CheckProcessExist(check_eNB, check_OAI_UE)) + RAN.pStatus=CiTestObj.CheckProcessExist(check_eNB, check_OAI_UE) RAN.InitializeeNB() elif action == 'Terminate_eNB': @@ -3750,7 +3750,7 @@ elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re else: sys.exit('Invalid action') CiTestObj.FailReportCnt += 1 - if CiTestObj.FailReportCnt == CiTestObj.repeatCounts[0] and RAN.GetprematureExit(): + if CiTestObj.FailReportCnt == CiTestObj.repeatCounts[0] and RAN.prematureExit: logging.debug('Testsuite failed ' + str(CiTestObj.FailReportCnt) + ' time(s)') HTML.CreateHtmlTabFooter(False) sys.exit('Failed Scenario') diff --git a/ci-scripts/ran.py b/ci-scripts/ran.py index e09ce55634..32f21fe2f7 100644 --- a/ci-scripts/ran.py +++ b/ci-scripts/ran.py @@ -92,7 +92,7 @@ class RANManagement(): self.epcObj = None - +""" #----------------------------------------------------------- # Setters and Getters on Public members #----------------------------------------------------------- @@ -228,6 +228,8 @@ class RANManagement(): def GetprematureExit(self): return self.prematureExit +""" + #----------------------------------------------------------- # RAN management functions #----------------------------------------------------------- From d273ae84f3c9dc9adaf1c432a78cab0cc459ffb9 Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Fri, 17 Jul 2020 15:28:34 +0200 Subject: [PATCH 473/553] added a class function to check adb returned values from a list --- ci-scripts/sshconnection.py | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/ci-scripts/sshconnection.py b/ci-scripts/sshconnection.py index ba0f900f29..ed0cf5379a 100644 --- a/ci-scripts/sshconnection.py +++ b/ci-scripts/sshconnection.py @@ -101,6 +101,18 @@ class SSHConnection(): else: sys.exit('SSH Connection Failed') + + + + def cde_check_value(self, commandline, expected, timeout): + logging.debug(commandline) + self.ssh.timeout = timeout + self.ssh.sendline(commandline) + expected.append(pexpect.EOF) + expected.append(pexpect.TIMEOUT) + self.sshresponse = self.ssh.expect(expected) + return self.sshresponse + def command(self, commandline, expectedline, timeout): logging.debug(commandline) self.ssh.timeout = timeout From 8b4498cd119b848216c3f9d1f150cab935b0ca81 Mon Sep 17 00:00:00 2001 From: frtabu Date: Fri, 17 Jul 2020 15:59:38 +0200 Subject: [PATCH 474/553] nr scope as a dynamically loaded shared lib --- cmake_targets/CMakeLists.txt | 4 ++-- executables/nr-softmodem.c | 14 ++++++++------ executables/nr-softmodem.h | 9 --------- executables/nr-uesoftmodem.c | 9 ++++++--- executables/nr-uesoftmodem.h | 8 -------- openair1/PHY/TOOLS/nr_phy_scope.c | 4 ++-- openair1/PHY/TOOLS/nr_phy_scope.h | 2 -- openair1/PHY/TOOLS/phy_scope_interface.c | 4 ++-- openair1/PHY/TOOLS/phy_scope_interface.h | 2 +- targets/RT/USER/lte-softmodem.c | 2 +- targets/RT/USER/lte-uesoftmodem.c | 2 +- 11 files changed, 23 insertions(+), 37 deletions(-) diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index 7e59f38e8d..d5b90d3454 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -2730,7 +2730,7 @@ add_executable(nr-softmodem ${OPENAIR_DIR}/common/utils/system.c ${OPENAIR_DIR}/common/utils/nr/nr_common.c ${GTPU_need_ITTI} - ${XFORMS_SOURCE_NR} + ${XFORMSINTERFACE_SOURCE} ${T_SOURCE} ${CONFIG_SOURCES} ${SHLIB_LOADER_SOURCES} @@ -2772,7 +2772,7 @@ add_executable(nr-uesoftmodem ${OPENAIR_DIR}/common/utils/utils.c ${OPENAIR_DIR}/common/utils/system.c ${OPENAIR_DIR}/common/utils/nr/nr_common.c - ${XFORMS_SOURCE_NR} + ${XFORMSINTERFACE_SOURCE} ${T_SOURCE} ${UTIL_SRC} ${CONFIG_SOURCES} diff --git a/executables/nr-softmodem.c b/executables/nr-softmodem.c index bf77125975..8f68485d29 100644 --- a/executables/nr-softmodem.c +++ b/executables/nr-softmodem.c @@ -75,7 +75,7 @@ unsigned short config_frames[4] = {2,9,11,13}; #include "system.h" #include - +#include "PHY/TOOLS/phy_scope_interface.h" #include "PHY/TOOLS/nr_phy_scope.h" #include "stats.h" #include "nr-softmodem.h" @@ -156,7 +156,6 @@ char channels[128] = "0"; int rx_input_level_dBm; -uint32_t do_forms=0; int otg_enabled; //int number_of_cards = 1; @@ -454,7 +453,11 @@ static void get_options(void) { paramdef_t cmdline_params[] = CMDLINE_PARAMS_DESC_GNB ; + CONFIG_SETRTFLAG(CONFIG_NOEXITONHELP); + get_common_options(SOFTMODEM_GNB_BIT ); config_process_cmdline( cmdline_params,sizeof(cmdline_params)/sizeof(paramdef_t),NULL); + CONFIG_CLEARRTFLAG(CONFIG_NOEXITONHELP); + @@ -817,7 +820,6 @@ int main( int argc, char **argv ) configure_linux(); printf("Reading in command-line options\n"); get_options (); - get_common_options(SOFTMODEM_GNB_BIT ); if (CONFIG_ISFLAGSET(CONFIG_ABORT) ) { fprintf(stderr,"Getting configuration failed\n"); @@ -959,14 +961,14 @@ if(!IS_SOFTMODEM_NOS1) printf("RC.nb_RU:%d\n", RC.nb_RU); // once all RUs are ready initialize the rest of the gNBs ((dependence on final RU parameters after configuration) printf("ALL RUs ready - init gNBs\n"); - - if (do_forms==1) { + if(IS_SOFTMODEM_DOFORMS) { + scopeParms_t p; p.argc=&argc; p.argv=argv; p.gNB=RC.gNB[0]; p.ru=RC.ru[0]; - gNBinitScope(&p); + load_softscope("gnb",&p); } if (nfapi_mode != 1 && nfapi_mode != 2) { diff --git a/executables/nr-softmodem.h b/executables/nr-softmodem.h index d113ae45aa..d6cfe6b906 100644 --- a/executables/nr-softmodem.h +++ b/executables/nr-softmodem.h @@ -19,21 +19,12 @@ /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ #define CMDLINE_PARAMS_DESC_GNB { \ {"mmapped-dma", CONFIG_HLP_DMAMAP, PARAMFLAG_BOOL, uptr:&mmapped_dma, defintval:0, TYPE_INT, 0}, \ - {"wait-for-sync", NULL, PARAMFLAG_BOOL, iptr:&wait_for_sync, defintval:0, TYPE_INT, 0}, \ {"single-thread-disable", CONFIG_HLP_NOSNGLT, PARAMFLAG_BOOL, iptr:&single_thread_flag, defintval:1, TYPE_INT, 0}, \ {"A" , CONFIG_HLP_TADV, 0, uptr:&timing_advance, defintval:0, TYPE_UINT, 0}, \ - {"C" , CONFIG_HLP_DLF, 0, u64ptr:&(downlink_frequency[0][0]), defuintval:DEFAULT_DLF, TYPE_UINT64, 0}, \ - {"a" , CONFIG_HLP_CHOFF, 0, iptr:&chain_offset, defintval:0, TYPE_INT, 0}, \ - {"d" , CONFIG_HLP_SOFTS, PARAMFLAG_BOOL, uptr:(uint32_t *)&do_forms, defintval:0, TYPE_INT8, 0}, \ {"E" , CONFIG_HLP_TQFS, PARAMFLAG_BOOL, i8ptr:&threequarter_fs, defintval:0, TYPE_INT8, 0}, \ {"K" , CONFIG_HLP_ITTIL, PARAMFLAG_NOFREE, strptr:&itti_dump_file, defstrval:"/tmp/itti.dump", TYPE_STRING, 0}, \ {"m" , CONFIG_HLP_DLMCS, 0, uptr:&target_dl_mcs, defintval:0, TYPE_UINT, 0}, \ {"t" , CONFIG_HLP_ULMCS, 0, uptr:&target_ul_mcs, defintval:0, TYPE_UINT, 0}, \ - {"q" , CONFIG_HLP_STMON, PARAMFLAG_BOOL, iptr:&opp_enabled, defintval:0, TYPE_INT, 0}, \ - {"numerology" , CONFIG_HLP_NUMEROLOGY, PARAMFLAG_BOOL, iptr:&numerology, defintval:0, TYPE_INT, 0}, \ - {"emulate-rf" , CONFIG_HLP_EMULATE_RF, PARAMFLAG_BOOL, iptr:&emulate_rf, defintval:0, TYPE_INT, 0}, \ - {"parallel-config", CONFIG_HLP_PARALLEL_CMD,0, strptr:(char **)¶llel_config, defstrval:NULL, TYPE_STRING, 0}, \ - {"worker-config", CONFIG_HLP_WORKER_CMD, 0, strptr:(char **)&worker_config, defstrval:NULL, TYPE_STRING, 0}, \ {"usrp-tx-thread-config", CONFIG_HLP_USRP_THREAD, 0, iptr:&usrp_tx_thread, defstrval:0, TYPE_INT, 0}, \ {"s" , CONFIG_HLP_SNR, 0, dblptr:&snr_dB, defdblval:25, TYPE_DOUBLE, 0}, \ } diff --git a/executables/nr-uesoftmodem.c b/executables/nr-uesoftmodem.c index 6d3bbc9038..b36a041a70 100644 --- a/executables/nr-uesoftmodem.c +++ b/executables/nr-uesoftmodem.c @@ -78,6 +78,7 @@ unsigned short config_frames[4] = {2,9,11,13}; //#include "stats.h" // current status is that every UE has a DL scope for a SINGLE eNB (eNB_id=0) +#include "PHY/TOOLS/phy_scope_interface.h" #include "PHY/TOOLS/nr_phy_scope.h" // at eNB 0, an UL scope for every UE //FD_lte_phy_scope_enb *form_enb[MAX_NUM_CCs][NUMBER_OF_UE_MAX]; @@ -158,7 +159,7 @@ int rx_input_level_dBm; //static int online_log_messages=0; -uint32_t do_forms=0; + int otg_enabled; //int number_of_cards = 1; @@ -761,8 +762,10 @@ int main( int argc, char **argv ) { memset (&UE_PF_PO[0][0], 0, sizeof(UE_PF_PO_t)*NUMBER_OF_UE_MAX*MAX_NUM_CCs); configure_linux(); mlockall(MCL_CURRENT | MCL_FUTURE); - if (do_forms) - nrUEinitScope(PHY_vars_UE_g[0][0]); + + if(IS_SOFTMODEM_DOFORMS) { + load_softscope("gnb",PHY_vars_UE_g[0][0]); + } number_of_cards = 1; for(int CC_id=0; CC_id Date: Sun, 19 Jul 2020 17:56:00 +0200 Subject: [PATCH 475/553] removed all Getters and Setters from EPC, HTML classes (as all attributes are public) --- ci-scripts/epc.py | 56 ++++---- ci-scripts/html.py | 116 ++++++++--------- ci-scripts/main.py | 316 ++++++++++++++++++++++----------------------- ci-scripts/ran.py | 262 ++++++++++++++++++------------------- 4 files changed, 373 insertions(+), 377 deletions(-) diff --git a/ci-scripts/epc.py b/ci-scripts/epc.py index 09d500f203..14bbcd0540 100644 --- a/ci-scripts/epc.py +++ b/ci-scripts/epc.py @@ -70,34 +70,34 @@ class EPCManagement(): # Setter and Getters on Public Members #----------------------------------------------------------- - def SetIPAddress(self, ipaddress): - self.IPAddress = ipaddress - def GetIPAddress(self): - return self.IPAddress - def SetUserName(self, username): - self.UserName = username - def GetUserName(self): - return self.UserName - def SetPassword(self, password): - self.Password = password - def GetPassword(self): - return self.Password - def SetSourceCodePath(self, sourcecodepath): - self.SourceCodePath = sourcecodepath - def GetSourceCodePath(self): - return self.SourceCodePath - def SetType(self, kind): - self.Type = kind - def GetType(self): - return self.Type - def SetHtmlObj(self, obj): - self.htmlObj = obj - def SetTestCase_id(self, idx): - self.testCase_id = idx - def GetMmeIPAddress(self): - return self.MmeIPAddress - def SetContainerPrefix(self, prefix): - self.containerPrefix = prefix +# def SetIPAddress(self, ipaddress): +# self.IPAddress = ipaddress +# def GetIPAddress(self): +# return self.IPAddress +# def SetUserName(self, username): +# self.UserName = username +# def GetUserName(self): +# return self.UserName +# def SetPassword(self, password): +# self.Password = password +# def GetPassword(self): +# return self.Password +# def SetSourceCodePath(self, sourcecodepath): +# self.SourceCodePath = sourcecodepath +# def GetSourceCodePath(self): +# return self.SourceCodePath +# def SetType(self, kind): +# self.Type = kind +# def GetType(self): +# return self.Type +# def SetHtmlObj(self, obj): +# self.htmlObj = obj +# def SetTestCase_id(self, idx): +# self.testCase_id = idx +# def GetMmeIPAddress(self): +# return self.MmeIPAddress +# def SetContainerPrefix(self, prefix): +# self.containerPrefix = prefix #----------------------------------------------------------- # EPC management functions diff --git a/ci-scripts/html.py b/ci-scripts/html.py index 8fa99fa61b..b7b3c31fad 100644 --- a/ci-scripts/html.py +++ b/ci-scripts/html.py @@ -82,73 +82,69 @@ class HTMLManagement(): #----------------------------------------------------------- # Setters and Getters #----------------------------------------------------------- - def SethtmlUEFailureMsg(self,huefa): - self.htmlUEFailureMsg = huefa - def GethtmlUEFailureMsg(self): - return self.htmlUEFailureMsg - def SetHmleNBFailureMsg(self, msg): - self.htmleNBFailureMsg = msg - - def Setdesc(self, dsc): - self.desc = dsc - - def SetstartTime(self, sttime): - self.startTime = sttime - - def SettestCase_id(self, tcid): - self.testCase_id = tcid - def GettestCase_id(self): - return self.testCase_id - - def SetranRepository(self, repository): - self.ranRepository = repository - def SetranAllowMerge(self, merge): - self.ranAllowMerge = merge - def SetranBranch(self, branch): - self.ranBranch = branch - def SetranCommitID(self, commitid): - self.ranCommitID = commitid - def SetranTargetBranch(self, tbranch): - self.ranTargetBranch = tbranch - + def SethtmlUEConnected(self, nbUEs): if nbUEs > 0: self.htmlUEConnected = nbUEs else: self.htmlUEConnected = 1 - def SethtmlNb_Smartphones(self, nbUEs): - self.htmlNb_Smartphones = nbUEs - def SethtmlNb_CATM_Modules(self, nbUEs): - self.htmlNb_CATM_Modules = nbUEs + - def SetnbTestXMLfiles(self, nb): - self.nbTestXMLfiles = nb - def GetnbTestXMLfiles(self): - return self.nbTestXMLfiles +# def SethtmlUEFailureMsg(self,huefa): +# self.htmlUEFailureMsg = huefa +# def GethtmlUEFailureMsg(self): +# return self.htmlUEFailureMsg +# def SetHmleNBFailureMsg(self, msg): +# self.htmleNBFailureMsg = msg +# def Setdesc(self, dsc): +# self.desc = dsc +# def SetstartTime(self, sttime): +# self.startTime = sttime +# def SettestCase_id(self, tcid): +# self.testCase_id = tcid +# def GettestCase_id(self): +# return self.testCase_id +# def SetranRepository(self, repository): +# self.ranRepository = repository +# def SetranAllowMerge(self, merge): +# self.ranAllowMerge = merge +# def SetranBranch(self, branch): +# self.ranBranch = branch +# def SetranCommitID(self, commitid): +# self.ranCommitID = commitid +# def SetranTargetBranch(self, tbranch): +# self.ranTargetBranch = tbranch +# def SethtmlNb_Smartphones(self, nbUEs): +# self.htmlNb_Smartphones = nbUEs +# def SethtmlNb_CATM_Modules(self, nbUEs): +# self.htmlNb_CATM_Modules = nbUEs +# def SetnbTestXMLfiles(self, nb): +# self.nbTestXMLfiles = nb +# def GetnbTestXMLfiles(self): +# return self.nbTestXMLfiles +# def SettestXMLfiles(self, xmlFile): +# self.testXMLfiles.append(xmlFile) +# def SethtmlTabRefs(self, tabRef): +# self.htmlTabRefs.append(tabRef) +# def SethtmlTabNames(self, tabName): +# self.htmlTabNames.append(tabName) +# def SethtmlTabIcons(self, tabIcon): +# self.htmlTabIcons.append(tabIcon) +# def SetOsVersion(self, version, idx): +# self.OsVersion[idx] = version +# def SetKernelVersion(self, version, idx): +# self.KernelVersion[idx] = version +# def SetUhdVersion(self, version, idx): +# self.UhdVersion[idx] = version +# def SetUsrpBoard(self, version, idx): +# self.UsrpBoard[idx] = version +# def SetCpuNb(self, nb, idx): +# self.CpuNb[idx] = nb +# def SetCpuModel(self, model, idx): +# self.CpuModel[idx] = model +# def SetCpuMHz(self, freq, idx): +# self.CpuMHz[idx] = freq - def SettestXMLfiles(self, xmlFile): - self.testXMLfiles.append(xmlFile) - def SethtmlTabRefs(self, tabRef): - self.htmlTabRefs.append(tabRef) - def SethtmlTabNames(self, tabName): - self.htmlTabNames.append(tabName) - def SethtmlTabIcons(self, tabIcon): - self.htmlTabIcons.append(tabIcon) - - def SetOsVersion(self, version, idx): - self.OsVersion[idx] = version - def SetKernelVersion(self, version, idx): - self.KernelVersion[idx] = version - def SetUhdVersion(self, version, idx): - self.UhdVersion[idx] = version - def SetUsrpBoard(self, version, idx): - self.UsrpBoard[idx] = version - def SetCpuNb(self, nb, idx): - self.CpuNb[idx] = nb - def SetCpuModel(self, model, idx): - self.CpuModel[idx] = model - def SetCpuMHz(self, freq, idx): - self.CpuMHz[idx] = freq #----------------------------------------------------------- # HTML structure creation functions diff --git a/ci-scripts/main.py b/ci-scripts/main.py index f7feeb08d4..7bfe331fc2 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -209,9 +209,9 @@ class OaiCiTest(): sys.exit(1) def CheckFlexranCtrlInstallation(self): - if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '': + if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '': return - SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) + SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password) SSH.command('ls -ls /opt/flexran_rtc/*/rt_controller', '\$', 5) result = re.search('/opt/flexran_rtc/build/rt_controller', SSH.getBefore()) if result is not None: @@ -222,15 +222,15 @@ class OaiCiTest(): def InitializeFlexranCtrl(self): if RAN.flexranCtrlInstalled == False: return - if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '': + if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '': HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) + SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password) SSH.command('cd /opt/flexran_rtc', '\$', 5) - SSH.command('echo ' + EPC.GetPassword() + ' | sudo -S rm -f log/*.log', '\$', 5) - SSH.command('echo ' + EPC.GetPassword() + ' | sudo -S echo "build/rt_controller -c log_config/basic_log" > ./my-flexran-ctl.sh', '\$', 5) - SSH.command('echo ' + EPC.GetPassword() + ' | sudo -S chmod 755 ./my-flexran-ctl.sh', '\$', 5) - SSH.command('echo ' + EPC.GetPassword() + ' | sudo -S daemon --unsafe --name=flexran_rtc_daemon --chdir=/opt/flexran_rtc -o /opt/flexran_rtc/log/flexranctl_' + self.testCase_id + '.log ././my-flexran-ctl.sh', '\$', 5) + SSH.command('echo ' + EPC.Password + ' | sudo -S rm -f log/*.log', '\$', 5) + SSH.command('echo ' + EPC.Password + ' | sudo -S echo "build/rt_controller -c log_config/basic_log" > ./my-flexran-ctl.sh', '\$', 5) + SSH.command('echo ' + EPC.Password + ' | sudo -S chmod 755 ./my-flexran-ctl.sh', '\$', 5) + SSH.command('echo ' + EPC.Password + ' | sudo -S daemon --unsafe --name=flexran_rtc_daemon --chdir=/opt/flexran_rtc -o /opt/flexran_rtc/log/flexranctl_' + self.testCase_id + '.log ././my-flexran-ctl.sh', '\$', 5) SSH.command('ps -aux | grep --color=never rt_controller', '\$', 5) result = re.search('rt_controller -c ', SSH.getBefore()) if result is not None: @@ -513,12 +513,12 @@ class OaiCiTest(): else: if RAN.air_interface == 'lte': if RAN.eNBmbmsEnables[0]: - HTML.SethtmlUEFailureMsg('oaitun_ue1/oaitun_uem1 interfaces are either NOT mounted or NOT configured') + HTML.htmlUEFailureMsg='oaitun_ue1/oaitun_uem1 interfaces are either NOT mounted or NOT configured' else: - HTML.SethtmlUEFailureMsg('oaitun_ue1 interface is either NOT mounted or NOT configured') + HTML.htmlUEFailureMsg='oaitun_ue1 interface is either NOT mounted or NOT configured' HTML.CreateHtmlTestRow(self.Initialize_OAI_UE_args, 'KO', CONST.OAI_UE_PROCESS_NO_TUNNEL_INTERFACE, 'OAI UE') else: - HTML.SethtmlUEFailureMsg('nr-uesoftmodem did NOT synced') + HTML.htmlUEFailureMsg='nr-uesoftmodem did NOT synced' HTML.CreateHtmlTestRow(self.Initialize_OAI_UE_args, 'KO', CONST.OAI_UE_PROCESS_COULD_NOT_SYNC, 'OAI UE') logging.error('\033[91mInitialize OAI UE Failed! \033[0m') self.AutoTerminateUEandeNB() @@ -671,7 +671,7 @@ class OaiCiTest(): self.AutoTerminateUEandeNB() def PingCatM(self): - if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetSourceCodePath() == '': + if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.SourceCodePath == '': HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') check_eNB = True @@ -684,10 +684,10 @@ class OaiCiTest(): try: statusQueue = SimpleQueue() lock = Lock() - SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) - SSH.command('cd ' + EPC.GetSourceCodePath(), '\$', 5) + SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password) + SSH.command('cd ' + EPC.SourceCodePath, '\$', 5) SSH.command('cd scripts', '\$', 5) - if re.match('OAI', EPC.GetType(), re.IGNORECASE): + if re.match('OAI', EPC.Type, re.IGNORECASE): logging.debug('Using the OAI EPC HSS: not implemented yet') HTML.CreateHtmlTestRow(self.ping_args, 'KO', pStatus) HTML.CreateHtmlTabFooter(False) @@ -1200,7 +1200,7 @@ class OaiCiTest(): for job in multi_jobs: job.join() if RAN.flexranCtrlInstalled and RAN.flexranCtrlStarted: - SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) + SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password) SSH.command('cd /opt/flexran_rtc', '\$', 5) SSH.command('curl http://localhost:9999/stats | jq \'.\' > log/check_status_' + self.testCase_id + '.log 2>&1', '\$', 5) SSH.command('cat log/check_status_' + self.testCase_id + '.log | jq \'.eNB_config[0].UE\' | grep -c rnti | sed -e "s#^#Nb Connected UE = #"', '\$', 5) @@ -1312,13 +1312,13 @@ class OaiCiTest(): # Launch ping on the EPC side (true for ltebox and old open-air-cn) # But for OAI-Rel14-CUPS, we launch from python executor launchFromEpc = True - if re.match('OAI-Rel14-CUPS', EPC.GetType(), re.IGNORECASE): + if re.match('OAI-Rel14-CUPS', EPC.Type, re.IGNORECASE): launchFromEpc = False ping_time = re.findall("-c (\d+)",str(self.ping_args)) if launchFromEpc: - SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) - SSH.command('cd ' + EPC.GetSourceCodePath(), '\$', 5) + SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password) + SSH.command('cd ' + EPC.SourceCodePath, '\$', 5) SSH.command('cd scripts', '\$', 5) ping_status = SSH.command('stdbuf -o0 ping ' + self.ping_args + ' ' + UE_IPAddress + ' 2>&1 | stdbuf -o0 tee ping_' + self.testCase_id + '_' + device_id + '.log', '\$', int(ping_time[0])*1.5) else: @@ -1327,9 +1327,9 @@ class OaiCiTest(): logging.debug(cmd) ret = subprocess.run(cmd, shell=True) ping_status = ret.returncode - SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'ping_' + self.testCase_id + '_' + device_id + '.log', EPC.GetSourceCodePath() + '/scripts') - SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) - SSH.command('cat ' + EPC.GetSourceCodePath() + '/scripts/ping_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) + SSH.copyout(EPC.IPAddress, EPC.UserName, EPC.Password, 'ping_' + self.testCase_id + '_' + device_id + '.log', EPC.SourceCodePath + '/scripts') + SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password) + SSH.command('cat ' + EPC.SourceCodePath + '/scripts/ping_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) # TIMEOUT CASE if ping_status < 0: message = 'Ping with UE (' + str(UE_IPAddress) + ') crashed due to TIMEOUT!' @@ -1487,7 +1487,7 @@ class OaiCiTest(): else: copyin_res = SSH.copyin(self.UEIPAddress, self.UEUserName, self.UEPassword, self.UESourceCodePath + '/cmake_targets/ping_' + self.testCase_id + '.log', '.') if (copyin_res == 0): - SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'ping_' + self.testCase_id + '.log', EPC.GetSourceCodePath() + '/scripts') + SSH.copyout(EPC.IPAddress, EPC.UserName, EPC.Password, 'ping_' + self.testCase_id + '.log', EPC.SourceCodePath + '/scripts') except: os.kill(os.getppid(),signal.SIGUSR1) @@ -1496,7 +1496,7 @@ class OaiCiTest(): if result is not None: self.PingNoS1() return - if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetSourceCodePath() == '': + if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.SourceCodePath == '': HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') check_eNB = True @@ -1840,7 +1840,7 @@ class OaiCiTest(): # Launch iperf server on EPC side (true for ltebox and old open-air-cn0 # But for OAI-Rel14-CUPS, we launch from python executor and we are using its IP address as iperf client address launchFromEpc = True - if re.match('OAI-Rel14-CUPS', EPC.GetType(), re.IGNORECASE): + if re.match('OAI-Rel14-CUPS', EPC.Type, re.IGNORECASE): launchFromEpc = False cmd = 'hostname -I' ret = subprocess.run(cmd, shell=True, stdout=subprocess.PIPE, encoding='utf-8') @@ -1848,13 +1848,13 @@ class OaiCiTest(): EPC_Iperf_UE_IPAddress = ret.stdout.strip() port = 5001 + idx if launchFromEpc: - SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) - SSH.command('cd ' + EPC.GetSourceCodePath() + '/scripts', '\$', 5) + SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password) + SSH.command('cd ' + EPC.SourceCodePath + '/scripts', '\$', 5) SSH.command('rm -f iperf_server_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) if udpIperf: - SSH.command('echo $USER; nohup iperf -u -s -i 1 -p ' + str(port) + ' > iperf_server_' + self.testCase_id + '_' + device_id + '.log &', EPC.GetUserName(), 5) + SSH.command('echo $USER; nohup iperf -u -s -i 1 -p ' + str(port) + ' > iperf_server_' + self.testCase_id + '_' + device_id + '.log &', EPC.UserName, 5) else: - SSH.command('echo $USER; nohup iperf -s -i 1 -p ' + str(port) + ' > iperf_server_' + self.testCase_id + '_' + device_id + '.log &', EPC.GetUserName(), 5) + SSH.command('echo $USER; nohup iperf -s -i 1 -p ' + str(port) + ' > iperf_server_' + self.testCase_id + '_' + device_id + '.log &', EPC.UserName, 5) SSH.close() else: if self.ueIperfVersion == self.dummyIperfVersion: @@ -1877,7 +1877,7 @@ class OaiCiTest(): SSH.command('cd ' + self.UESourceCodePath + '/cmake_targets', '\$', 5) else: SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) - SSH.command('cd ' + EPC.GetSourceCodePath() + '/scripts', '\$', 5) + SSH.command('cd ' + EPC.SourceCodePath+ '/scripts', '\$', 5) iperf_time = self.Iperf_ComputeTime() time.sleep(0.5) @@ -1911,27 +1911,27 @@ class OaiCiTest(): # Kill iperf server on EPC side if launchFromEpc: - SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) - SSH.command('killall --signal SIGKILL iperf', EPC.GetUserName(), 5) + SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password + SSH.command('killall --signal SIGKILL iperf', EPC.UserName, 5) SSH.close() else: cmd = 'killall --signal SIGKILL iperf' logging.debug(cmd) subprocess.run(cmd, shell=True) time.sleep(1) - SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'iperf_server_' + self.testCase_id + '_' + device_id + '.log', EPC.GetSourceCodePath() + '/scripts') + SSH.copyout(EPC.IPAddress, EPC.UserName, EPC.Password, 'iperf_server_' + self.testCase_id + '_' + device_id + '.log', EPC.SourceCodePath + '/scripts') # in case of failure, retrieve server log if (clientStatus == -1) or (clientStatus == -2): if launchFromEpc: time.sleep(1) if (os.path.isfile('iperf_server_' + self.testCase_id + '_' + device_id + '.log')): os.remove('iperf_server_' + self.testCase_id + '_' + device_id + '.log') - SSH.copyin(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), EPC.GetSourceCodePath() + '/scripts/iperf_server_' + self.testCase_id + '_' + device_id + '.log', '.') + SSH.copyin(EPC.IPAddress, EPC.UserName, EPC.Password, EPC.SourceCodePath+ '/scripts/iperf_server_' + self.testCase_id + '_' + device_id + '.log', '.') self.Iperf_analyzeV2Server(lock, UE_IPAddress, device_id, statusQueue, modified_options) # in case of OAI-UE if (device_id == 'OAI-UE'): SSH.copyin(self.UEIPAddress, self.UEUserName, self.UEPassword, self.UESourceCodePath + '/cmake_targets/iperf_' + self.testCase_id + '_' + device_id + '.log', '.') - SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'iperf_' + self.testCase_id + '_' + device_id + '.log', EPC.GetSourceCodePath() + '/scripts') + SSH.copyout(EPC.IPAddress, EPC.UserName, EPC.Password, 'iperf_' + self.testCase_id + '_' + device_id + '.log', EPC.SourceCodePath + '/scripts') def Iperf_common(self, lock, UE_IPAddress, device_id, idx, ue_num, statusQueue): try: @@ -1945,8 +1945,8 @@ class OaiCiTest(): if (device_id != 'OAI-UE'): SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) # if by chance ADB server and EPC are on the same remote host, at least log collection will take care of it - SSH.command('if [ ! -d ' + EPC.GetSourceCodePath() + '/scripts ]; then mkdir -p ' + EPC.GetSourceCodePath() + '/scripts ; fi', '\$', 5) - SSH.command('cd ' + EPC.GetSourceCodePath() + '/scripts', '\$', 5) + SSH.command('if [ ! -d ' + EPC.SourceCodePath + '/scripts ]; then mkdir -p ' + EPC.SourceCodePath + '/scripts ; fi', '\$', 5) + SSH.command('cd ' + EPC.SourceCodePath + '/scripts', '\$', 5) # Checking if iperf / iperf3 are installed if self.ADBCentralized: SSH.command('adb -s ' + device_id + ' shell "ls /data/local/tmp"', '\$', 5) @@ -2005,7 +2005,7 @@ class OaiCiTest(): SSH.command('echo $USER; nohup iperf -B ' + UE_IPAddress + ' -u -s -i 1 > iperf_server_' + self.testCase_id + '_' + device_id + '.log &', self.UEUserName, 5) else: SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) - SSH.command('cd ' + EPC.GetSourceCodePath() + '/scripts', '\$', 5) + SSH.command('cd ' + EPC.SourceCodePath + '/scripts', '\$', 5) if self.ADBCentralized: if (useIperf3): SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell /data/local/tmp/iperf3 -s &', '\$', 5) @@ -2027,11 +2027,11 @@ class OaiCiTest(): # Launch the IPERF client on the EPC side for DL (true for ltebox and old open-air-cn # But for OAI-Rel14-CUPS, we launch from python executor launchFromEpc = True - if re.match('OAI-Rel14-CUPS', EPC.GetType(), re.IGNORECASE): + if re.match('OAI-Rel14-CUPS', EPC.Type, re.IGNORECASE): launchFromEpc = False if launchFromEpc: - SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) - SSH.command('cd ' + EPC.GetSourceCodePath() + '/scripts', '\$', 5) + SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password) + SSH.command('cd ' + EPC.SourceCodePath + '/scripts', '\$', 5) iperf_time = self.Iperf_ComputeTime() time.sleep(0.5) @@ -2066,9 +2066,9 @@ class OaiCiTest(): logging.debug(cmd) ret = subprocess.run(cmd, shell=True) iperf_status = ret.returncode - SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'iperf_' + self.testCase_id + '_' + device_id + '.log', EPC.GetSourceCodePath() + '/scripts') - SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) - SSH.command('cat ' + EPC.GetSourceCodePath() + '/scripts/iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) + SSH.copyout(EPC.IPAddress, EPC.UserName, EPC.Password, 'iperf_' + self.testCase_id + '_' + device_id + '.log', EPC.SourceCodePath + '/scripts') + SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password) + SSH.command('cat ' + EPC.SourceCodePath + '/scripts/iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) if iperf_status < 0: if launchFromEpc: SSH.close() @@ -2105,7 +2105,7 @@ class OaiCiTest(): if (device_id == 'OAI-UE'): SSH.copyin(self.UEIPAddress, self.UEUserName, self.UEPassword, self.UESourceCodePath + '/cmake_targets/iperf_server_' + self.testCase_id + '_' + device_id + '.log', '.') else: - SSH.copyin(self.ADBIPAddress, self.ADBUserName, self.ADBPassword, EPC.GetSourceCodePath() + '/scripts/iperf_server_' + self.testCase_id + '_' + device_id + '.log', '.') + SSH.copyin(self.ADBIPAddress, self.ADBUserName, self.ADBPassword, EPC.SourceCodePath + '/scripts/iperf_server_' + self.testCase_id + '_' + device_id + '.log', '.') # fromdos has to be called on the python executor not on ADB server cmd = 'fromdos -o iperf_server_' + self.testCase_id + '_' + device_id + '.log' subprocess.run(cmd, shell=True) @@ -2115,10 +2115,10 @@ class OaiCiTest(): if (device_id == 'OAI-UE'): if (os.path.isfile('iperf_server_' + self.testCase_id + '_' + device_id + '.log')): if not launchFromEpc: - SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'iperf_server_' + self.testCase_id + '_' + device_id + '.log', EPC.GetSourceCodePath() + '/scripts') + SSH.copyout(EPC.IPAddress, EPC.UserName, EPC.Password, 'iperf_server_' + self.testCase_id + '_' + device_id + '.log', EPC.SourceCodePath + '/scripts') else: SSH.copyin(self.UEIPAddress, self.UEUserName, self.UEPassword, self.UESourceCodePath + '/cmake_targets/iperf_server_' + self.testCase_id + '_' + device_id + '.log', '.') - SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'iperf_server_' + self.testCase_id + '_' + device_id + '.log', EPC.GetSourceCodePath() + '/scripts') + SSH.copyout(EPC.IPAddress, EPC.UserName, EPC.Password, 'iperf_server_' + self.testCase_id + '_' + device_id + '.log', EPC.SourceCodePath + '/scripts') except: os.kill(os.getppid(),signal.SIGUSR1) @@ -2202,10 +2202,10 @@ class OaiCiTest(): if (clientStatus == -1): copyin_res = SSH.copyin(iServerIPAddr, iServerUser, iServerPasswd, '/tmp/tmp_iperf_server_' + self.testCase_id + '.log', 'iperf_server_' + self.testCase_id + '_OAI-UE.log') if (copyin_res == 0): - SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'iperf_server_' + self.testCase_id + '_OAI-UE.log', EPC.GetSourceCodePath() + '/scripts') + SSH.copyout(EPC.IPAddress, EPC.UserName, EPC.Password, 'iperf_server_' + self.testCase_id + '_OAI-UE.log', EPC.SourceCodePath + '/scripts') copyin_res = SSH.copyin(iClientIPAddr, iClientUser, iClientPasswd, '/tmp/tmp_iperf_' + self.testCase_id + '.log', 'iperf_' + self.testCase_id + '_OAI-UE.log') if (copyin_res == 0): - SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'iperf_' + self.testCase_id + '_OAI-UE.log', EPC.GetSourceCodePath() + '/scripts') + SSH.copyout(EPC.IPAddress, EPC.UserName, EPC.Password, 'iperf_' + self.testCase_id + '_OAI-UE.log', EPC.SourceCodePath + '/scripts') iperf_noperf = False if status_queue.empty(): iperf_status = False @@ -2236,7 +2236,7 @@ class OaiCiTest(): if result is not None: self.IperfNoS1() return - if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetSourceCodePath() == '' or self.ADBIPAddress == '' or self.ADBUserName == '' or self.ADBPassword == '': + if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.SourceCodePath == '' or self.ADBIPAddress == '' or self.ADBUserName == '' or self.ADBPassword == '': HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') check_eNB = True @@ -2432,7 +2432,7 @@ class OaiCiTest(): nrFoundDCI = 0 nrCRCOK = 0 mbms_messages = 0 - HTML.SethtmlUEFailureMsg('') + HTML.htmlUEFailureMsg='' global_status = CONST.ALL_PROCESSES_OK for line in ue_log_file.readlines(): result = re.search('nr_synchro_time', str(line)) @@ -2502,22 +2502,22 @@ class OaiCiTest(): if result is not None and (not mib_found): try: mibMsg = "MIB Information: " + result.group(1) + ', ' + result.group(2) - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg + '\n') + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + mibMsg + '\n' logging.debug('\033[94m' + mibMsg + '\033[0m') mibMsg = " nidcell = " + result.group('nidcell') - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg) + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + mibMsg logging.debug('\033[94m' + mibMsg + '\033[0m') mibMsg = " n_rb_dl = " + result.group('n_rb_dl') - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg + '\n') + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + mibMsg + '\n' logging.debug('\033[94m' + mibMsg + '\033[0m') mibMsg = " phich_duration = " + result.group('phich_duration') - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg) + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + mibMsg logging.debug('\033[94m' + mibMsg + '\033[0m') mibMsg = " phich_resource = " + result.group('phich_resource') - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg + '\n') + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + mibMsg + '\n' logging.debug('\033[94m' + mibMsg + '\033[0m') mibMsg = " tx_ant = " + result.group('tx_ant') - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg + '\n') + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + mibMsg + '\n' logging.debug('\033[94m' + mibMsg + '\033[0m') mib_found = True except Exception as e: @@ -2526,7 +2526,7 @@ class OaiCiTest(): if result is not None and (not frequency_found): try: mibMsg = "Measured Carrier Frequency = " + result.group('measured_carrier_frequency') + ' Hz' - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg + '\n') + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + mibMsg + '\n' logging.debug('\033[94m' + mibMsg + '\033[0m') frequency_found = True except Exception as e: @@ -2535,7 +2535,7 @@ class OaiCiTest(): if result is not None and (not plmn_found): try: mibMsg = 'PLMN MCC = ' + result.group('mcc') + ' MNC = ' + result.group('mnc') - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg + '\n') + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + mibMsg + '\n' logging.debug('\033[94m' + mibMsg + '\033[0m') plmn_found = True except Exception as e: @@ -2544,7 +2544,7 @@ class OaiCiTest(): if result is not None: try: mibMsg = "The operator is: " + result.group('operator') - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg + '\n') + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + mibMsg + '\n' logging.debug('\033[94m' + mibMsg + '\033[0m') except Exception as e: logging.error('\033[91m' + "Operator name not found" + '\033[0m') @@ -2552,7 +2552,7 @@ class OaiCiTest(): if result is not None: try: mibMsg = "SIB5 InterFreqCarrierFreq element " + result.group(1) + '/' + result.group(2) - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg + ' -> ') + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + mibMsg + ' -> ' logging.debug('\033[94m' + mibMsg + '\033[0m') except Exception as e: logging.error('\033[91m' + "SIB5 InterFreqCarrierFreq element not found" + '\033[0m') @@ -2570,7 +2570,7 @@ class OaiCiTest(): if result is not None: try: prb = result.group('allowed_bandwidth') - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + ' -- PRB: ' + prb + '\n') + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + ' -- PRB: ' + prb + '\n' logging.debug('\033[94m' + " AllowedMeasBandwidth: " + prb + '\033[0m') except Exception as e: logging.error('\033[91m' + " AllowedMeasBandwidth not found" + '\033[0m') @@ -2578,48 +2578,48 @@ class OaiCiTest(): if rrcConnectionRecfgComplete > 0: statMsg = 'UE connected to eNB (' + str(rrcConnectionRecfgComplete) + ' RRCConnectionReconfigurationComplete message(s) generated)' logging.debug('\033[94m' + statMsg + '\033[0m') - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n') + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + statMsg + '\n' if nrUEFlag: if nrDecodeMib > 0: statMsg = 'UE showed ' + str(nrDecodeMib) + ' MIB decode message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n') + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + statMsg + '\n' if nrFoundDCI > 0: statMsg = 'UE showed ' + str(nrFoundDCI) + ' DCI found message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n') + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + statMsg + '\n' if nrCRCOK > 0: statMsg = 'UE showed ' + str(nrCRCOK) + ' PDSCH decoding message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n') + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + statMsg + '\n' if not frequency_found: statMsg = 'NR-UE could NOT synch!' logging.error('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n') + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + statMsg + '\n' if uciStatMsgCount > 0: statMsg = 'UE showed ' + str(uciStatMsgCount) + ' "uci->stat" message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n') + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + statMsg + '\n' if pdcpDataReqFailedCount > 0: statMsg = 'UE showed ' + str(pdcpDataReqFailedCount) + ' "PDCP data request failed" message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n') + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + statMsg + '\n' if badDciCount > 0: statMsg = 'UE showed ' + str(badDciCount) + ' "bad DCI 1(A)" message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n') + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + statMsg + '\n' if f1aRetransmissionCount > 0: statMsg = 'UE showed ' + str(f1aRetransmissionCount) + ' "Format1A Retransmission but TBS are different" message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n') + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + statMsg + '\n' if fatalErrorCount > 0: statMsg = 'UE showed ' + str(fatalErrorCount) + ' "FATAL ERROR:" message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n') + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + statMsg + '\n' if macBsrTimerExpiredCount > 0: statMsg = 'UE showed ' + str(fatalErrorCount) + ' "MAC BSR Triggered ReTxBSR Timer expiry" message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n') + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + statMsg + '\n' if RAN.eNBmbmsEnables[0]: if mbms_messages > 0: statMsg = 'UE showed ' + str(mbms_messages) + ' "TRIED TO PUSH MBMS DATA" message(s)' @@ -2628,7 +2628,7 @@ class OaiCiTest(): statMsg = 'UE did NOT SHOW "TRIED TO PUSH MBMS DATA" message(s)' logging.debug('\u001B[1;30;41m ' + statMsg + ' \u001B[0m') global_status = OAI_UE_PROCESS_NO_MBMS_MSGS - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n') + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + statMsg + '\n' if foundSegFault: logging.debug('\u001B[1;37;41m UE ended with a Segmentation Fault! \u001B[0m') if not nrUEFlag: @@ -2638,7 +2638,7 @@ class OaiCiTest(): global_status = CONST.OAI_UE_PROCESS_SEG_FAULT if foundAssertion: logging.debug('\u001B[1;30;43m UE showed an assertion! \u001B[0m') - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + 'UE showed an assertion!\n') + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + 'UE showed an assertion!\n' if not nrUEFlag: if not mib_found or not frequency_found: global_status = CONST.OAI_UE_PROCESS_ASSERTION @@ -2647,14 +2647,14 @@ class OaiCiTest(): global_status = CONST.OAI_UE_PROCESS_ASSERTION if foundRealTimeIssue: logging.debug('\u001B[1;37;41m UE faced real time issues! \u001B[0m') - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + 'UE faced real time issues!\n') + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + 'UE faced real time issues!\n' if nrUEFlag: if not frequency_found: global_status = CONST.OAI_UE_PROCESS_COULD_NOT_SYNC else: if no_cell_sync_found and not mib_found: logging.debug('\u001B[1;37;41m UE could not synchronize ! \u001B[0m') - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + 'UE could not synchronize!\n') + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + 'UE could not synchronize!\n' global_status = CONST.OAI_UE_PROCESS_COULD_NOT_SYNC return global_status @@ -2662,13 +2662,13 @@ class OaiCiTest(): def TerminateFlexranCtrl(self): if RAN.flexranCtrlInstalled == False or RAN.flexranCtrlStarted == False: return - if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '': + if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '': HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) - SSH.command('echo ' + EPC.GetPassword() + ' | sudo -S daemon --name=flexran_rtc_daemon --stop', '\$', 5) + SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password) + SSH.command('echo ' + EPC.Password + ' | sudo -S daemon --name=flexran_rtc_daemon --stop', '\$', 5) time.sleep(1) - SSH.command('echo ' + EPC.GetPassword() + ' | sudo -S killall --signal SIGKILL rt_controller', '\$', 5) + SSH.command('echo ' + EPC.Password + ' | sudo -S killall --signal SIGKILL rt_controller', '\$', 5) time.sleep(1) SSH.close() RAN.flexranCtrlStarted=False @@ -2737,7 +2737,7 @@ class OaiCiTest(): copyin_res = SSH.copyin(self.UEIPAddress, self.UEUserName, self.UEPassword, self.UESourceCodePath + '/cmake_targets/' + self.UELogFile, '.') if (copyin_res == -1): logging.debug('\u001B[1;37;41m Could not copy UE logfile to analyze it! \u001B[0m') - HTML.SethtmlUEFailureMsg('Could not copy UE logfile to analyze it!') + HTML.htmlUEFailureMsg='Could not copy UE logfile to analyze it!' HTML.CreateHtmlTestRow('N/A', 'KO', CONST.OAI_UE_PROCESS_NOLOGFILE_TO_ANALYZE, 'UE') self.UELogFile = '' return @@ -2750,7 +2750,7 @@ class OaiCiTest(): ueAction = 'Connection' if (logStatus < 0): logging.debug('\u001B[1m' + ueAction + ' Failed \u001B[0m') - HTML.SethtmlUEFailureMsg('' + ueAction + ' Failed\n' + HTML.GethtmlUEFailureMsg()) + HTML.htmlUEFailureMsg='' + ueAction + ' Failed\n' + HTML.htmlUEFailureMsg HTML.CreateHtmlTestRow('N/A', 'KO', logStatus, 'UE') if RAN.air_interface == 'lte': # In case of sniffing on commercial eNBs we have random results @@ -2764,7 +2764,7 @@ class OaiCiTest(): self.AutoTerminateUEandeNB() else: logging.debug('\u001B[1m' + ueAction + ' Completed \u001B[0m') - HTML.SethtmlUEFailureMsg('' + ueAction + ' Completed\n' + HTML.GethtmlUEFailureMsg()) + HTML.htmlUEFailureMsg='' + ueAction + ' Completed\n' + HTML.htmlUEFailureMsg HTML.CreateHtmlTestRow('N/A', 'OK', CONST.ALL_PROCESSES_OK) self.UELogFile = '' else: @@ -2773,31 +2773,31 @@ class OaiCiTest(): def AutoTerminateUEandeNB(self): if (self.ADBIPAddress != 'none'): self.testCase_id = 'AUTO-KILL-UE' - HTML.SettestCase_id(self.testCase_id) + HTML.testCase_id=self.testCase_id self.desc = 'Automatic Termination of UE' - HTML.Setdesc('Automatic Termination of UE') + HTML.desc='Automatic Termination of UE' self.ShowTestID() self.TerminateUE() if (self.Initialize_OAI_UE_args != ''): self.testCase_id = 'AUTO-KILL-OAI-UE' - HTML.SettestCase_id(self.testCase_id) + HTML.testCase_id=self.testCase_id self.desc = 'Automatic Termination of OAI-UE' - HTML.Setdesc('Automatic Termination of OAI-UE') + HTML.desc='Automatic Termination of OAI-UE' self.ShowTestID() self.TerminateOAIUE() if (RAN.Initialize_eNB_args != ''): self.testCase_id = 'AUTO-KILL-eNB' - HTML.SettestCase_id(self.testCase_id) + HTML.testCase_id=self.testCase_id self.desc = 'Automatic Termination of eNB' - HTML.Setdesc('Automatic Termination of eNB') + HTML.desc='Automatic Termination of eNB' self.ShowTestID() RAN.eNB_instance='0' RAN.TerminateeNB() if RAN.flexranCtrlInstalled and RAN.flexranCtrlStarted: self.testCase_id = 'AUTO-KILL-flexran-ctl' - HTML.SettestCase_id(self.testCase_id) + HTML.testCase_id=self.testCase_id self.desc = 'Automatic Termination of FlexRan CTL' - HTML.Setdesc('Automatic Termination of FlexRan CTL') + HTML.desc='Automatic Termination of FlexRan CTL' self.ShowTestID() self.TerminateFlexranCtrl() RAN.prematureExit=True @@ -2807,7 +2807,7 @@ class OaiCiTest(): HTML.CreateHtmlTestRow(str(self.idle_sleep_time) + ' sec', 'OK', CONST.ALL_PROCESSES_OK) def X2_Status(self, idx, fileName): - cmd = "curl --silent http://" + EPC.GetIPAddress() + ":9999/stats | jq '.' > " + fileName + cmd = "curl --silent http://" + EPC.IPAddress + ":9999/stats | jq '.' > " + fileName message = cmd + '\n' logging.debug(cmd) subprocess.run(cmd, shell=True) @@ -2871,7 +2871,7 @@ class OaiCiTest(): eNB_cnt = self.x2NbENBs cnt = 0 while cnt < eNB_cnt: - cmd = "curl -XPOST http://" + EPC.GetIPAddress() + ":9999/rrc/x2_ho_net_control/enb/" + str(self.x2ENBBsIds[0][cnt]) + "/1" + cmd = "curl -XPOST http://" + EPC.IPAddress + ":9999/rrc/x2_ho_net_control/enb/" + str(self.x2ENBBsIds[0][cnt]) + "/1" logging.debug(cmd) fullMessage += cmd + '\n' subprocess.run(cmd, shell=True) @@ -2885,7 +2885,7 @@ class OaiCiTest(): while cnt < eNB_cnt: ueIdx = 0 while ueIdx < len(self.x2ENBConnectedUEs[0][cnt]): - cmd = "curl -XPOST http://" + EPC.GetIPAddress() + ":9999/rrc/ho/senb/" + str(self.x2ENBBsIds[0][cnt]) + "/ue/" + str(self.x2ENBConnectedUEs[0][cnt][ueIdx]) + "/tenb/" + str(self.x2ENBBsIds[0][eNB_cnt - cnt - 1]) + cmd = "curl -XPOST http://" + EPC.IPAddress() + ":9999/rrc/ho/senb/" + str(self.x2ENBBsIds[0][cnt]) + "/ue/" + str(self.x2ENBConnectedUEs[0][cnt][ueIdx]) + "/tenb/" + str(self.x2ENBBsIds[0][eNB_cnt - cnt - 1]) logging.debug(cmd) fullMessage += cmd + '\n' subprocess.run(cmd, shell=True) @@ -2936,8 +2936,8 @@ class OaiCiTest(): SSH.command('zip build.log.zip build_log_*/*', '\$', 60) SSH.close() def LogCollectPing(self): - SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) - SSH.command('cd ' + EPC.GetSourceCodePath(), '\$', 5) + SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password) + SSH.command('cd ' + EPC.SourceCodePath, '\$', 5) SSH.command('cd scripts', '\$', 5) SSH.command('rm -f ping.log.zip', '\$', 5) SSH.command('zip ping.log.zip ping*.log', '\$', 60) @@ -2945,8 +2945,8 @@ class OaiCiTest(): SSH.close() def LogCollectIperf(self): - SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword()) - SSH.command('cd ' + EPC.GetSourceCodePath(), '\$', 5) + SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password) + SSH.command('cd ' + EPC.SourceCodePath, '\$', 5) SSH.command('cd scripts', '\$', 5) SSH.command('rm -f iperf.log.zip', '\$', 5) SSH.command('zip iperf.log.zip iperf*.log', '\$', 60) @@ -2964,13 +2964,13 @@ class OaiCiTest(): def RetrieveSystemVersion(self, machine): if RAN.eNBIPAddress == 'none' or self.UEIPAddress == 'none': - HTML.SetOsVersion('Ubuntu 16.04.5 LTS', 0) - HTML.SetKernelVersion('4.15.0-45-generic', 0) - HTML.SetUhdVersion('3.13.0.1-0', 0) - HTML.SetUsrpBoard('B210', 0) - HTML.SetCpuNb('4', 0) - HTML.SetCpuModel('Intel(R) Core(TM) i5-6200U', 0) - HTML.SetCpuMHz('2399.996 MHz', 0) + HTML.OsVersion[0]='Ubuntu 16.04.5 LTS' + HTML.KernelVersion[0]='4.15.0-45-generic' + HTML.UhdVersion[0]='3.13.0.1-0' + HTML.UsrpBoard[0]='B210' + HTML.CpuNb[0]='4' + HTML.CpuModel[0]='Intel(R) Core(TM) i5-6200U' + HTML.CpuMHz[0]='2399.996 MHz' return 0 if machine == 'eNB': if RAN.eNBIPAddress != '' and RAN.eNBUserName != '' and RAN.eNBPassword != '': @@ -2995,7 +2995,7 @@ class OaiCiTest(): if result is not None: OsVersion = result.group('os_type') logging.debug('OS is: ' + OsVersion) - HTML.SetOsVersion(OsVersion, idx) + HTML.OsVersion[idx]=OsVersion else: SSH.command('hostnamectl', '\$', 5) result = re.search('Operating System: (?P[a-zA-Z0-9\-\_\.\ ]+)', SSH.getBefore()) @@ -3007,26 +3007,26 @@ class OaiCiTest(): if result is not None: OsVersion = OsVersion.replace('7 ', result.group('os_version')) logging.debug('OS is: ' + OsVersion) - HTML.SetOsVersion(OsVersion, idx) + HTML.OsVersion[idx]=OsVersion SSH.command('uname -r', '\$', 5) result = re.search('uname -r\\\\r\\\\n(?P[a-zA-Z0-9\-\_\.]+)', SSH.getBefore()) if result is not None: KernelVersion = result.group('kernel_version') logging.debug('Kernel Version is: ' + KernelVersion) - HTML.SetKernelVersion(KernelVersion, idx) + HTML.KernelVersion[idx]=KernelVersion SSH.command('dpkg --list | egrep --color=never libuhd003', '\$', 5) result = re.search('libuhd003:amd64 *(?P[0-9\.]+)', SSH.getBefore()) if result is not None: UhdVersion = result.group('uhd_version') logging.debug('UHD Version is: ' + UhdVersion) - HTML.SetUhdVersion(UhdVersion, idx) + HTML.UhdVersion[idx]=UhdVersion else: SSH.command('uhd_config_info --version', '\$', 5) result = re.search('UHD (?P[a-zA-Z0-9\.\-]+)', SSH.getBefore()) if result is not None: UhdVersion = result.group('uhd_version') logging.debug('UHD Version is: ' + UhdVersion) - HTML.SetUhdVersion(UhdVersion, idx) + HTML.UhdVersion[idx]=UhdVersion SSH.command('echo ' + Password + ' | sudo -S uhd_find_devices', '\$', 60) usrp_boards = re.findall('product: ([0-9A-Za-z]+)\\\\r\\\\n', SSH.getBefore()) count = 0 @@ -3038,19 +3038,19 @@ class OaiCiTest(): count += 1 if count > 0: logging.debug('USRP Board(s) : ' + UsrpBoard) - HTML.SetUsrpBoard(UsrpBoard, idx) + HTML.UsrpBoard[idx]=UsrpBoard SSH.command('lscpu', '\$', 5) result = re.search('CPU\(s\): *(?P[0-9]+).*Model name: *(?P[a-zA-Z0-9\-\_\.\ \(\)]+).*CPU MHz: *(?P[0-9\.]+)', SSH.getBefore()) if result is not None: CpuNb = result.group('nb_cpus') logging.debug('nb_cpus: ' + CpuNb) - HTML.SetCpuNb(CpuNb, idx) + HTML.CpuNb[idx]=CpuNb CpuModel = result.group('model') logging.debug('model: ' + CpuModel) - HTML.SetCpuModel(CpuModel, idx) + HTML.CpuModel[idx]=CpuModel CpuMHz = result.group('cpu_mhz') + ' MHz' logging.debug('cpu_mhz: ' + CpuMHz) - HTML.SetCpuMHz(CpuMHz, idx) + HTML.CpuMHz[idx]=CpuMHz SSH.close() #----------------------------------------------------------- @@ -3267,7 +3267,7 @@ EPC = epc.EPCManagement() RAN = ran.RANManagement() HTML = html.HTMLManagement() -EPC.SetHtmlObj(HTML) +EPC.HtmlObj=HTML RAN.HtmlObj=HTML RAN.EpcObj=EPC @@ -3294,7 +3294,7 @@ while len(argvs) > 1: matchReg = re.match('^\-\-ranRepository=(.+)$', myArgv, re.IGNORECASE) CiTestObj.ranRepository = matchReg.group(1) RAN.ranRepository=matchReg.group(1) - HTML.SetranRepository(matchReg.group(1)) + HTML.ranRepository=matchReg.group(1) ldpc.ranRepository=matchReg.group(1) elif re.match('^\-\-eNB_AllowMerge=(.+)$|^\-\-ranAllowMerge=(.+)$', myArgv, re.IGNORECASE): if re.match('^\-\-eNB_AllowMerge=(.+)$', myArgv, re.IGNORECASE): @@ -3306,7 +3306,7 @@ while len(argvs) > 1: if ((doMerge == 'true') or (doMerge == 'True')): CiTestObj.ranAllowMerge = True RAN.ranAllowMerge=True - HTML.SetranAllowMerge(True) + HTML.ranAllowMerge=True elif re.match('^\-\-eNBBranch=(.+)$|^\-\-ranBranch=(.+)$', myArgv, re.IGNORECASE): if re.match('^\-\-eNBBranch=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-eNBBranch=(.+)$', myArgv, re.IGNORECASE) @@ -3314,7 +3314,7 @@ while len(argvs) > 1: matchReg = re.match('^\-\-ranBranch=(.+)$', myArgv, re.IGNORECASE) CiTestObj.ranBranch = matchReg.group(1) RAN.ranBranch=matchReg.group(1) - HTML.SetranBranch(matchReg.group(1)) + HTML.ranBranch=matchReg.group(1) ldpc.ranBranch=matchReg.group(1) elif re.match('^\-\-eNBCommitID=(.*)$|^\-\-ranCommitID=(.*)$', myArgv, re.IGNORECASE): if re.match('^\-\-eNBCommitID=(.*)$', myArgv, re.IGNORECASE): @@ -3323,7 +3323,7 @@ while len(argvs) > 1: matchReg = re.match('^\-\-ranCommitID=(.*)$', myArgv, re.IGNORECASE) CiTestObj.ranCommitID = matchReg.group(1) RAN.ranCommitID=matchReg.group(1) - HTML.SetranCommitID(matchReg.group(1)) + HTML.ranCommitID=matchReg.group(1) ldpc.ranCommitID=matchReg.group(1) elif re.match('^\-\-eNBTargetBranch=(.*)$|^\-\-ranTargetBranch=(.*)$', myArgv, re.IGNORECASE): if re.match('^\-\-eNBTargetBranch=(.*)$', myArgv, re.IGNORECASE): @@ -3332,7 +3332,7 @@ while len(argvs) > 1: matchReg = re.match('^\-\-ranTargetBranch=(.*)$', myArgv, re.IGNORECASE) CiTestObj.ranTargetBranch = matchReg.group(1) RAN.ranTargetBranch=matchReg.group(1) - HTML.SetranTargetBranch(matchReg.group(1)) + HTML.ranTargetBranch=matchReg.group(1) ldpc.ranTargetBranch=matchReg.group(1) elif re.match('^\-\-eNBIPAddress=(.+)$|^\-\-eNB[1-2]IPAddress=(.+)$', myArgv, re.IGNORECASE): if re.match('^\-\-eNBIPAddress=(.+)$', myArgv, re.IGNORECASE): @@ -3380,25 +3380,25 @@ while len(argvs) > 1: RAN.eNB2SourceCodePath=matchReg.group(1) elif re.match('^\-\-EPCIPAddress=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-EPCIPAddress=(.+)$', myArgv, re.IGNORECASE) - EPC.SetIPAddress(matchReg.group(1)) + EPC.IPAddress=matchReg.group(1) elif re.match('^\-\-EPCUserName=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-EPCUserName=(.+)$', myArgv, re.IGNORECASE) - EPC.SetUserName(matchReg.group(1)) + EPC.UserName=matchReg.group(1) elif re.match('^\-\-EPCPassword=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-EPCPassword=(.+)$', myArgv, re.IGNORECASE) - EPC.SetPassword(matchReg.group(1)) + EPC.Password=matchReg.group(1) elif re.match('^\-\-EPCSourceCodePath=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-EPCSourceCodePath=(.+)$', myArgv, re.IGNORECASE) - EPC.SetSourceCodePath(matchReg.group(1)) + EPC.SourceCodePath=matchReg.group(1) elif re.match('^\-\-EPCType=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-EPCType=(.+)$', myArgv, re.IGNORECASE) if re.match('OAI', matchReg.group(1), re.IGNORECASE) or re.match('ltebox', matchReg.group(1), re.IGNORECASE) or re.match('OAI-Rel14-CUPS', matchReg.group(1), re.IGNORECASE) or re.match('OAI-Rel14-Docker', matchReg.group(1), re.IGNORECASE): - EPC.SetType(matchReg.group(1)) + EPC.Type=matchReg.group(1) else: sys.exit('Invalid EPC Type: ' + matchReg.group(1) + ' -- (should be OAI or ltebox or OAI-Rel14-CUPS or OAI-Rel14-Docker)') elif re.match('^\-\-EPCContainerPrefix=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-EPCContainerPrefix=(.+)$', myArgv, re.IGNORECASE) - EPC.SetContainerPrefix(matchReg.group(1)) + EPC.ContainerPrefix=matchReg.group(1) elif re.match('^\-\-ADBIPAddress=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-ADBIPAddress=(.+)$', myArgv, re.IGNORECASE) CiTestObj.ADBIPAddress = matchReg.group(1) @@ -3420,8 +3420,8 @@ while len(argvs) > 1: elif re.match('^\-\-XMLTestFile=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-XMLTestFile=(.+)$', myArgv, re.IGNORECASE) CiTestObj.testXMLfiles.append(matchReg.group(1)) - HTML.SettestXMLfiles(matchReg.group(1)) - HTML.SetnbTestXMLfiles(HTML.GetnbTestXMLfiles()+1) + HTML.testXMLfiles=matchReg.group(1) + HTML.nbTestXMLfiles=HTML.nbTestXMLfiles+1 elif re.match('^\-\-UEIPAddress=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-UEIPAddress=(.+)$', myArgv, re.IGNORECASE) CiTestObj.UEIPAddress = matchReg.group(1) @@ -3464,17 +3464,17 @@ elif re.match('^TerminateOAIUE$', mode, re.IGNORECASE): signal.signal(signal.SIGUSR1, receive_signal) CiTestObj.TerminateOAIUE() elif re.match('^TerminateHSS$', mode, re.IGNORECASE): - if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetType() == '' or EPC.GetSourceCodePath() == '': + if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.Type == '' or EPC.SourceCodePath == '': HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') EPC.TerminateHSS() elif re.match('^TerminateMME$', mode, re.IGNORECASE): - if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetType() == '' or EPC.GetSourceCodePath() == '': + if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.Type == '' or EPC.SourceCodePath == '': HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') EPC.TerminateMME() elif re.match('^TerminateSPGW$', mode, re.IGNORECASE): - if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetType() == '' or EPC.GetSourceCodePath() == '': + if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.Type == '' or EPC.SourceCodePath== '': HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') EPC.TerminateSPGW() @@ -3489,27 +3489,27 @@ elif re.match('^LogCollecteNB$', mode, re.IGNORECASE): sys.exit('Insufficient Parameter') RAN.LogCollecteNB() elif re.match('^LogCollectHSS$', mode, re.IGNORECASE): - if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetType() == '' or EPC.GetSourceCodePath() == '': + if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.Type == '' or EPC.SourceCodePath == '': HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') EPC.LogCollectHSS() elif re.match('^LogCollectMME$', mode, re.IGNORECASE): - if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetType() == '' or EPC.GetSourceCodePath() == '': + if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.Type == '' or EPC.SourceCodePath == '': HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') EPC.LogCollectMME() elif re.match('^LogCollectSPGW$', mode, re.IGNORECASE): - if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetType() == '' or EPC.GetSourceCodePath() == '': + if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.Type == '' or EPC.SourceCodePath == '': HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') EPC.LogCollectSPGW() elif re.match('^LogCollectPing$', mode, re.IGNORECASE): - if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetSourceCodePath() == '': + if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.SourceCodePath == '': HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') CiTestObj.LogCollectPing() elif re.match('^LogCollectIperf$', mode, re.IGNORECASE): - if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetSourceCodePath() == '': + if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.SourceCodePath == '': HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') CiTestObj.LogCollectIperf() @@ -3533,21 +3533,21 @@ elif re.match('^InitiateHtml$', mode, re.IGNORECASE): except: print("Error while parsing file: " + xml_test_file) xmlRoot = xmlTree.getroot() - HTML.SethtmlTabRefs(xmlRoot.findtext('htmlTabRef',default='test-tab-' + str(count))) - HTML.SethtmlTabNames(xmlRoot.findtext('htmlTabName',default='test-tab-' + str(count))) - HTML.SethtmlTabIcons(xmlRoot.findtext('htmlTabIcon',default='info-sign')) + HTML.htmlTabRefs.append(xmlRoot.findtext('htmlTabRef',default='test-tab-' + str(count))) + HTML.htmlTabNames.append(xmlRoot.findtext('htmlTabName',default='test-tab-' + str(count))) + HTML.htmlTabIcons.append(xmlRoot.findtext('htmlTabIcon',default='info-sign')) foundCount += 1 count += 1 - if foundCount != HTML.GetnbTestXMLfiles(): - HTML.SetnbTestXMLfiles(foundCount) + if foundCount != HTML.nbTestXMLfiles: + HTML.nbTestXMLfiles=foundCount if (CiTestObj.ADBIPAddress != 'none'): terminate_ue_flag = False CiTestObj.GetAllUEDevices(terminate_ue_flag) CiTestObj.GetAllCatMDevices(terminate_ue_flag) HTML.SethtmlUEConnected(len(CiTestObj.UEDevices) + len(CiTestObj.CatMDevices)) - HTML.SethtmlNb_Smartphones(len(CiTestObj.UEDevices)) - HTML.SethtmlNb_CATM_Modules(len(CiTestObj.CatMDevices)) + HTML.htmlNb_Smartphones=len(CiTestObj.UEDevices) + HTML.htmlNb_CATM_Modules=len(CiTestObj.CatMDevices) HTML.CreateHtmlHeader(CiTestObj.ADBIPAddress) elif re.match('^FinalizeHtml$', mode, re.IGNORECASE): logging.debug('\u001B[1m----------------------------------------\u001B[0m') @@ -3561,17 +3561,17 @@ elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re if re.match('^TesteNB$', mode, re.IGNORECASE): if RAN.eNBIPAddress == '' or RAN.ranRepository == '' or RAN.ranBranch == '' or RAN.eNBUserName == '' or RAN.eNBPassword == '' or RAN.eNBSourceCodePath == '' or EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.Type == '' or EPC.SourceCodePath == '' or CiTestObj.ADBIPAddress == '' or CiTestObj.ADBUserName == '' or CiTestObj.ADBPassword == '': HELP.GenericHelp(CONST.Version) - if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetSourceCodePath() == '' or EPC.GetType() == '': - HELP.EPCSrvHelp(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), EPC.GetSourceCodePath(), EPC.GetType()) + if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.SourceCodePath == '' or EPC.Type == '': + HELP.EPCSrvHelp(EPC.IPAddress, EPC.UserName, EPC.Password, EPC.SourceCodePath, EPC.Type) if RAN.ranRepository == '': HELP.GitSrvHelp(RAN.ranRepository, RAN.ranBranch, RAN.ranCommitID, RAN.ranAllowMerge, RAN.ranTargetBranch) if RAN.eNBIPAddress == '' or RAN.eNBUserName == '' or RAN.eNBPassword == '' or RAN.eNBSourceCodePath == '': HELP.eNBSrvHelp(RAN.eNBIPAddress, RAN.eNBUserName, RAN.eNBPassword, RAN.eNBSourceCodePath) sys.exit('Insufficient Parameter') - if (EPC.GetIPAddress() != '') and (EPC.GetIPAddress() != 'none'): - SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), cwd + "/tcp_iperf_stats.awk", "/tmp") - SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), cwd + "/active_net_interfaces.awk", "/tmp") + if (EPC.IPAddress!= '') and (EPC.IPAddress != 'none'): + SSH.copyout(EPC.IPAddress, EPC.UserName, EPC.Password, cwd + "/tcp_iperf_stats.awk", "/tmp") + SSH.copyout(EPC.IPAddress, EPC.UserName, EPC.Password, cwd + "/active_net_interfaces.awk", "/tmp") else: if CiTestObj.UEIPAddress == '' or CiTestObj.ranRepository == '' or CiTestObj.ranBranch == '' or CiTestObj.UEUserName == '' or CiTestObj.UEPassword == '' or CiTestObj.UESourceCodePath == '': HELP.GenericHelp(CONST.Version) @@ -3579,7 +3579,7 @@ elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re #read test_case_list.xml file # if no parameters for XML file, use default value - if (HTML.GetnbTestXMLfiles() != 1): + if (HTML.nbTestXMLfiles != 1): xml_test_file = cwd + "/test_case_list.xml" else: xml_test_file = cwd + "/" + CiTestObj.testXMLfiles[0] @@ -3589,9 +3589,9 @@ elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re exclusion_tests=xmlRoot.findtext('TestCaseExclusionList',default='') requested_tests=xmlRoot.findtext('TestCaseRequestedList',default='') - if (HTML.GetnbTestXMLfiles() == 1): - HTML.SethtmlTabRefs(xmlRoot.findtext('htmlTabRef',default='test-tab-0')) - HTML.SethtmlTabNames(xmlRoot.findtext('htmlTabName',default='Test-0')) + if (HTML.nbTestXMLfiles == 1): + HTML.htmlTabRefs.append(xmlRoot.findtext('htmlTabRef',default='test-tab-0')) + HTML.htmlTabNames.append(xmlRoot.findtext('htmlTabName',default='Test-0')) repeatCount = xmlRoot.findtext('repeatCount',default='1') CiTestObj.repeatCounts.append(int(repeatCount)) all_tests=xmlRoot.findall('testCase') @@ -3619,7 +3619,7 @@ elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re else: logging.debug('ERROR: requested test is invalidly formatted: ' + test) sys.exit(1) - if (EPC.GetIPAddress() != '') and (EPC.GetIPAddress() != 'none'): + if (EPC.IPAddress != '') and (EPC.IPAddress != 'none'): CiTestObj.CheckFlexranCtrlInstallation() EPC.SetMmeIPAddress() @@ -3645,7 +3645,7 @@ elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re CiTestObj.FailReportCnt = 0 RAN.prematureExit=True - HTML.SetstartTime(int(round(time.time() * 1000))) + HTML.startTime=int(round(time.time() * 1000)) while CiTestObj.FailReportCnt < CiTestObj.repeatCounts[0] and RAN.prematureExit: RAN.prematureExit=False # At every iteratin of the retry loop, a separator will be added @@ -3661,10 +3661,10 @@ elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re if test_case_id != id: continue CiTestObj.testCase_id = id - HTML.SettestCase_id(CiTestObj.testCase_id) - EPC.SetTestCase_id(CiTestObj.testCase_id) + HTML.testCase_id=CiTestObj.testCase_id + EPC.testCase_id=CiTestObj.testCase_id CiTestObj.desc = test.findtext('desc') - HTML.Setdesc(CiTestObj.desc) + HTML.desc=CiTestObj.desc action = test.findtext('class') if (CheckClassValidity(action, id) == False): continue diff --git a/ci-scripts/ran.py b/ci-scripts/ran.py index 32f21fe2f7..5673b4c082 100644 --- a/ci-scripts/ran.py +++ b/ci-scripts/ran.py @@ -92,143 +92,143 @@ class RANManagement(): self.epcObj = None -""" + #----------------------------------------------------------- # Setters and Getters on Public members #----------------------------------------------------------- - def SetHtmlObj(self, obj): - self.htmlObj = obj - def SetEpcObj(self, obj): - self.epcObj = obj +# def SetHtmlObj(self, obj): +# self.htmlObj = obj +# def SetEpcObj(self, obj): +# self.epcObj = obj +# +# def SetflexranCtrlInstalled(self,fxrctin): +# self.flexranCtrlInstalled = fxrctin +# def GetflexranCtrlInstalled(self): +# return self.flexranCtrlInstalled +# def SetflexranCtrlStarted(self,fxrctst): +# self.flexranCtrlStarted = fxrctst +# def GetflexranCtrlStarted(self): +# return self.flexranCtrlStarted +# def SetpStatus(self, pSt): +# self.pStatus = pSt +# def SetranRepository(self, repository): +# self.ranRepository = repository +# def GetranRepository(self): +# return self.ranRepository +# def SetranBranch(self, branch): +# self.ranBranch = branch +# def GetranBranch(self): +# return self.ranBranch +# def SetranCommitID(self, commitid): +# self.ranCommitID = commitid +# def GetranCommitID(self): +# return self.ranCommitID +# def SeteNB_serverId(self, enbsrvid): +# self.eNB_serverId = enbsrvid +# def GeteNB_serverId(self): +# return self.eNB_serverId +# def SeteNBIPAddress(self, enbip): +# self.eNBIPAddress = enbip +# def GeteNBIPAddress(self): +# return self.eNBIPAddress +# def SeteNBUserName(self, enbusr): +# self.eNBUserName = enbusr +# def GeteNBUserName(self): +# return self.eNBUserName +# def SeteNBPassword(self, enbpw): +# self.eNBPassword = enbpw +# def GeteNBPassword(self): +# return self.eNBPassword +# def SeteNBSourceCodePath(self, enbcodepath): +# self.eNBSourceCodePath = enbcodepath +# def GeteNBSourceCodePath(self): +# return self.eNBSourceCodePath +# def SetranAllowMerge(self, merge): +# self.ranAllowMerge = merge +# def GetranAllowMerge(self): +# return self.ranAllowMerge +# def SetranTargetBranch(self, tbranch): +# self.ranTargetBranch = tbranch +# def GetranTargetBranch(self): +# return self.ranTargetBranch +# def SetBuild_eNB_args(self, enbbuildarg): +# self.Build_eNB_args = enbbuildarg +# def GetBuild_eNB_args(self): +# return self.Build_eNB_args +# def SetInitialize_eNB_args(self, initenbarg): +# self.Initialize_eNB_args = initenbarg +# def GetInitialize_eNB_args(self): +# return self.Initialize_eNB_args +# def SetbackgroundBuild(self, bkbuild): +# self.backgroundBuild = bkbuild +# def GetbackgroundBuild(self): +# return self.backgroundBuild +# def SetbackgroundBuildTestId(self, bkbuildid): +# self.backgroundBuildTestId = bkbuildid +# def GetbackgroundBuildTestId(self): +# return self.backgroundBuildTestId +# def SetBuild_eNB_forced_workspace_cleanup(self, fcdwspclean): +# self.Build_eNB_forced_workspace_cleanup = fcdwspclean +# def GetBuild_eNB_forced_workspace_cleanup(self): +# return self.Build_eNB_forced_workspace_cleanup +# def Setair_interface(self, airif): +# self.air_interface = airif +# def Getair_interface(self): +# return self.air_interface +# def SeteNB_instance(self, enbinst): +# self.eNB_instance = enbinst +# def GeteNB_instance(self): +# return self.eNB_instance +# +# def SeteNBLogFile(self, enblog, idx): +# self.eNBLogFiles[idx] = enblog +# def GeteNBLogFile(self, idx): +# return self.eNBLogFiles[idx] +# +# def GeteNBmbmsEnable(self, idx): +# return self.eNBmbmsEnables[idx] +# +# def SeteNB1IPAddress(self,enb1ip): +# self.eNB1IPAddress = enb1ip +# def GeteNB1IPAddress(self): +# return self.eNB1IPAddress +# def SeteNB1UserName(self, enb1usr): +# self.eNB1UserName = enb1usr +# def GeteNB1UserName(self): +# return self.eNB1UserName +# def SeteNB1Password(self, enb1pw): +# self.eNB1Password = enb1pw +# def GeteNB1Password(self): +# return self.eNB1Password +# def SeteNB1SourceCodePath(self, enb1codepath): +# self.eNB1SourceCodePath = enb1codepath +# def GeteNB1SourceCodePath(self): +# return self.eNB1SourceCodePath +# +# def SeteNB2IPAddress(self, enb2ip): +# self.eNB2IPAddress = enb2ip +# def GeteNB2IPAddress(self): +# return self.eNB2IPAddress +# def SeteNB2UserName(self, enb2usr): +# self.eNB2UserName = enb2usr +# def GeteNB2UserName(self): +# return self.eNB2UserName +# def SeteNB2Password(self, enb2pw): +# self.eNB2Password = enb2pw +# def GeteNB2Password(self): +# return self.eNB2Password +# def SeteNB2SourceCodePath(self, enb2codepath): +# self.eNB2SourceCodePath = enb2codepath +# def GeteNB2SourceCodePath(self): +# return self.eNB2SourceCodePath +# +# def SetprematureExit(self, premex): +# self.prematureExit = premex +# def GetprematureExit(self): +# return self.prematureExit - def SetflexranCtrlInstalled(self,fxrctin): - self.flexranCtrlInstalled = fxrctin - def GetflexranCtrlInstalled(self): - return self.flexranCtrlInstalled - def SetflexranCtrlStarted(self,fxrctst): - self.flexranCtrlStarted = fxrctst - def GetflexranCtrlStarted(self): - return self.flexranCtrlStarted - def SetpStatus(self, pSt): - self.pStatus = pSt - def SetranRepository(self, repository): - self.ranRepository = repository - def GetranRepository(self): - return self.ranRepository - def SetranBranch(self, branch): - self.ranBranch = branch - def GetranBranch(self): - return self.ranBranch - def SetranCommitID(self, commitid): - self.ranCommitID = commitid - def GetranCommitID(self): - return self.ranCommitID - def SeteNB_serverId(self, enbsrvid): - self.eNB_serverId = enbsrvid - def GeteNB_serverId(self): - return self.eNB_serverId - def SeteNBIPAddress(self, enbip): - self.eNBIPAddress = enbip - def GeteNBIPAddress(self): - return self.eNBIPAddress - def SeteNBUserName(self, enbusr): - self.eNBUserName = enbusr - def GeteNBUserName(self): - return self.eNBUserName - def SeteNBPassword(self, enbpw): - self.eNBPassword = enbpw - def GeteNBPassword(self): - return self.eNBPassword - def SeteNBSourceCodePath(self, enbcodepath): - self.eNBSourceCodePath = enbcodepath - def GeteNBSourceCodePath(self): - return self.eNBSourceCodePath - def SetranAllowMerge(self, merge): - self.ranAllowMerge = merge - def GetranAllowMerge(self): - return self.ranAllowMerge - def SetranTargetBranch(self, tbranch): - self.ranTargetBranch = tbranch - def GetranTargetBranch(self): - return self.ranTargetBranch - def SetBuild_eNB_args(self, enbbuildarg): - self.Build_eNB_args = enbbuildarg - def GetBuild_eNB_args(self): - return self.Build_eNB_args - def SetInitialize_eNB_args(self, initenbarg): - self.Initialize_eNB_args = initenbarg - def GetInitialize_eNB_args(self): - return self.Initialize_eNB_args - def SetbackgroundBuild(self, bkbuild): - self.backgroundBuild = bkbuild - def GetbackgroundBuild(self): - return self.backgroundBuild - def SetbackgroundBuildTestId(self, bkbuildid): - self.backgroundBuildTestId = bkbuildid - def GetbackgroundBuildTestId(self): - return self.backgroundBuildTestId - def SetBuild_eNB_forced_workspace_cleanup(self, fcdwspclean): - self.Build_eNB_forced_workspace_cleanup = fcdwspclean - def GetBuild_eNB_forced_workspace_cleanup(self): - return self.Build_eNB_forced_workspace_cleanup - def Setair_interface(self, airif): - self.air_interface = airif - def Getair_interface(self): - return self.air_interface - def SeteNB_instance(self, enbinst): - self.eNB_instance = enbinst - def GeteNB_instance(self): - return self.eNB_instance - def SeteNBLogFile(self, enblog, idx): - self.eNBLogFiles[idx] = enblog - def GeteNBLogFile(self, idx): - return self.eNBLogFiles[idx] - - def GeteNBmbmsEnable(self, idx): - return self.eNBmbmsEnables[idx] - - def SeteNB1IPAddress(self,enb1ip): - self.eNB1IPAddress = enb1ip - def GeteNB1IPAddress(self): - return self.eNB1IPAddress - def SeteNB1UserName(self, enb1usr): - self.eNB1UserName = enb1usr - def GeteNB1UserName(self): - return self.eNB1UserName - def SeteNB1Password(self, enb1pw): - self.eNB1Password = enb1pw - def GeteNB1Password(self): - return self.eNB1Password - def SeteNB1SourceCodePath(self, enb1codepath): - self.eNB1SourceCodePath = enb1codepath - def GeteNB1SourceCodePath(self): - return self.eNB1SourceCodePath - - def SeteNB2IPAddress(self, enb2ip): - self.eNB2IPAddress = enb2ip - def GeteNB2IPAddress(self): - return self.eNB2IPAddress - def SeteNB2UserName(self, enb2usr): - self.eNB2UserName = enb2usr - def GeteNB2UserName(self): - return self.eNB2UserName - def SeteNB2Password(self, enb2pw): - self.eNB2Password = enb2pw - def GeteNB2Password(self): - return self.eNB2Password - def SeteNB2SourceCodePath(self, enb2codepath): - self.eNB2SourceCodePath = enb2codepath - def GeteNB2SourceCodePath(self): - return self.eNB2SourceCodePath - - def SetprematureExit(self, premex): - self.prematureExit = premex - def GetprematureExit(self): - return self.prematureExit - -""" #----------------------------------------------------------- # RAN management functions From bbca88ad78906d732fb067875f0a2787752488b4 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Sat, 11 Apr 2020 15:42:13 +0200 Subject: [PATCH 476/553] Bugfix FlexRAN: if a UE is in RRC but not S1AP, treat as no bug --- openair2/ENB_APP/flexran_agent_ran_api.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair2/ENB_APP/flexran_agent_ran_api.c b/openair2/ENB_APP/flexran_agent_ran_api.c index 32cb8c74e1..abade20846 100644 --- a/openair2/ENB_APP/flexran_agent_ran_api.c +++ b/openair2/ENB_APP/flexran_agent_ran_api.c @@ -3644,7 +3644,7 @@ int flexran_get_s1ap_ue(mid_t mod_id, rnti_t rnti, Protocol__FlexS1apUe * ue_con RB_FOREACH(ue, s1ap_ue_map, &s1ap->s1ap_ue_head){ if (ue->eNB_ue_s1ap_id == enb_ue_s1ap_id) break; } - if (ue == NULL) return -1; + if (!ue) return 0; // UE does not exist: it might be connected but CN did not answer if (ue->mme_ref->mme_s1_ip.ipv4) ue_conf->mme_s1_ip = (char*) &ue->mme_ref->mme_s1_ip.ipv4_address[0]; From 40fdd53adcaf2dc61c2cc34991bea7074c7a114d Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Wed, 15 Apr 2020 21:25:42 +0200 Subject: [PATCH 477/553] Correctly decode IMSI also when not integrity protected --- openair2/RRC/LTE/rrc_eNB_S1AP.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/openair2/RRC/LTE/rrc_eNB_S1AP.c b/openair2/RRC/LTE/rrc_eNB_S1AP.c index 27a442ed05..9f92be366b 100644 --- a/openair2/RRC/LTE/rrc_eNB_S1AP.c +++ b/openair2/RRC/LTE/rrc_eNB_S1AP.c @@ -96,36 +96,34 @@ void extract_imsi(uint8_t *pdu_buf, uint32_t pdu_len, rrc_eNB_ue_context_t *ue_c && pdu_len > NAS_MESSAGE_SECURITY_HEADER_SIZE)) return; + /* Decode plain NAS message */ + EMM_msg *e_msg = &nas_msg.plain.emm; + emm_msg_header_t *emm_header = &e_msg->header; + if (header->security_header_type != SECURITY_HEADER_TYPE_NOT_PROTECTED) { /* Decode the message authentication code */ DECODE_U32((char *) pdu_buf+size, header->message_authentication_code, size); /* Decode the sequence number */ DECODE_U8((char *) pdu_buf+size, header->sequence_number, size); - } + /* Decode the security header type and the protocol discriminator */ + DECODE_U8(pdu_buf + size, *(uint8_t *)(emm_header), size); - /* Note: the value of the pointer (i.e. the address) is given by value, so we - * can modify it as we want. The callee retains the original address! */ + /* Check that this is the right message */ + if (emm_header->protocol_discriminator != EPS_MOBILITY_MANAGEMENT_MESSAGE) + return; + } pdu_buf += size; pdu_len -= size; - /* Decode plain NAS message */ - EMM_msg *e_msg = &nas_msg.plain.emm; - emm_msg_header_t *emm_header = &e_msg->header; - /* First decode the EMM message header */ - int e_head_size = 0; /* Check that buffer contains more than only the header */ if (pdu_len <= sizeof(emm_msg_header_t)) return; - /* Decode the security header type and the protocol discriminator */ - DECODE_U8(pdu_buf + e_head_size, *(uint8_t *)(emm_header), e_head_size); + /* First decode the EMM message header */ + int e_head_size = 0; /* Decode the message type */ DECODE_U8(pdu_buf + e_head_size, emm_header->message_type, e_head_size); - /* Check that this is the right message */ - if (emm_header->protocol_discriminator != EPS_MOBILITY_MANAGEMENT_MESSAGE) - return; - pdu_buf += e_head_size; pdu_len -= e_head_size; From 64f0b7e0e53094279ef87f20941fa11513fbf9eb Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Sat, 11 Apr 2020 00:20:24 +0200 Subject: [PATCH 478/553] Do not check for register_enb_pending The test seemingly ensures that this code block is hit only once. However, if we enable later activation of MMEs, it will be hit a second (and third, ...) time. The only thing in guards against, though, is an INIT message to the L1L2 thread, when register_enb_pending == 0, which should only be sent once. Therefore, functionality won't be changed if register_enb_pending becomes negative, and the assert can be removed. --- openair2/ENB_APP/enb_app.c | 1 - 1 file changed, 1 deletion(-) diff --git a/openair2/ENB_APP/enb_app.c b/openair2/ENB_APP/enb_app.c index 0e1c7e64bc..7c91e57813 100644 --- a/openair2/ENB_APP/enb_app.c +++ b/openair2/ENB_APP/enb_app.c @@ -273,7 +273,6 @@ void *eNB_app_task(void *args_p) { if (EPC_MODE_ENABLED) { LOG_I(ENB_APP, "[eNB %d] Received %s: associated MME %d\n", instance, ITTI_MSG_NAME (msg_p), S1AP_REGISTER_ENB_CNF(msg_p).nb_mme); - DevAssert(register_enb_pending > 0); register_enb_pending--; /* Check if at least eNB is registered with one MME */ From d47c539ddae4cd28d0a3254f67651b62565e7039 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Sat, 11 Apr 2020 00:23:40 +0200 Subject: [PATCH 479/553] S1AP: Only register MME if we do not know it yet --- openair3/S1AP/s1ap_eNB.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/openair3/S1AP/s1ap_eNB.c b/openair3/S1AP/s1ap_eNB.c index c228034245..c703501847 100644 --- a/openair3/S1AP/s1ap_eNB.c +++ b/openair3/S1AP/s1ap_eNB.c @@ -220,8 +220,21 @@ void s1ap_eNB_handle_register_eNB(instance_t instance, s1ap_register_enb_req_t * /* Trying to connect to provided list of MME ip address */ for (index = 0; index < s1ap_register_eNB->nb_mme; index++) { + net_ip_address_t *mme_ip = &s1ap_register_eNB->mme_ip_address[index]; + struct s1ap_eNB_mme_data_s *mme = NULL; + RB_FOREACH(mme, s1ap_mme_map, &new_instance->s1ap_mme_head) { + /* Compare whether IPv4 and IPv6 information is already present, in which + * wase we do not register again */ + if (mme->mme_s1_ip.ipv4 == mme_ip->ipv4 && (!mme_ip->ipv4 + || strncmp(mme->mme_s1_ip.ipv4_address, mme_ip->ipv4_address, 16) == 0) + && mme->mme_s1_ip.ipv6 == mme_ip->ipv6 && (!mme_ip->ipv6 + || strncmp(mme->mme_s1_ip.ipv6_address, mme_ip->ipv6_address, 46) == 0)) + break; + } + if (mme) + continue; s1ap_eNB_register_mme(new_instance, - &s1ap_register_eNB->mme_ip_address[index], + mme_ip, &s1ap_register_eNB->enb_ip_address, s1ap_register_eNB->sctp_in_streams, s1ap_register_eNB->sctp_out_streams, From e4eea33de6928ce5ad0c8fe40dba1f403f61f38d Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Fri, 10 Apr 2020 23:17:36 +0200 Subject: [PATCH 480/553] FlexRAN: Enable MME adding/removing --- .../CONTROL_MODULES/S1AP/flexran_agent_s1ap.c | 33 +++++++ .../CONTROL_MODULES/S1AP/flexran_agent_s1ap.h | 5 + openair2/ENB_APP/flexran_agent_common.c | 47 +++++----- openair2/ENB_APP/flexran_agent_ran_api.c | 91 +++++++++++++++++++ openair2/ENB_APP/flexran_agent_ran_api.h | 6 ++ 5 files changed, 160 insertions(+), 22 deletions(-) diff --git a/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.c b/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.c index 04a47406e1..d5fc5627a0 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.c +++ b/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.c @@ -125,6 +125,39 @@ void flexran_agent_s1ap_destroy_stats_reply(Protocol__FlexStatsReply *reply) { } } +void flexran_agent_handle_mme_update(mid_t mod_id, + size_t n_mme, + Protocol__FlexS1apMme **mme) { + if (n_mme == 0 || n_mme > 1) { + LOG_E(FLEXRAN_AGENT, "cannot handle %lu MMEs yet\n", n_mme); + return; + } + + if (!mme[0]->s1_ip) { + LOG_E(FLEXRAN_AGENT, "no S1 IP present, cannot handle request\n"); + return; + } + + if (mme[0]->has_state + && mme[0]->state == PROTOCOL__FLEX_MME_STATE__FLMMES_DISCONNECTED) { + int rc = flexran_remove_s1ap_mme(mod_id, 1, &mme[0]->s1_ip); + if (rc == 0) + LOG_I(FLEXRAN_AGENT, "remove MME at IP %s\n", mme[0]->s1_ip); + else + LOG_W(FLEXRAN_AGENT, + "could not remove MME: flexran_remove_s1ap_mme() returned %d\n", + rc); + } else { + int rc = flexran_add_s1ap_mme(mod_id, 1, &mme[0]->s1_ip); + if (rc == 0) + LOG_I(FLEXRAN_AGENT, "add MME at IP %s\n", mme[0]->s1_ip); + else + LOG_W(FLEXRAN_AGENT, + "could not add MME: flexran_add_s1ap_mme() returned %d\n", + rc); + } +} + int flexran_agent_register_s1ap_xface(mid_t mod_id) { if (agent_s1ap_xface[mod_id]) { LOG_E(FLEXRAN_AGENT, "S1AP agent CM for eNB %d is already registered\n", mod_id); diff --git a/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.h b/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.h index 1cca6ac9c1..54ea2926a8 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.h +++ b/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.h @@ -60,6 +60,11 @@ int flexran_agent_s1ap_stats_reply(mid_t mod_id, /* Free allocated S1AP stats message */ void flexran_agent_s1ap_destroy_stats_reply(Protocol__FlexStatsReply *reply); +/* Add or remove MME updates */ +void flexran_agent_handle_mme_update(mid_t mod_id, + size_t n_mme, + Protocol__FlexS1apMme **mme); + /* Register technology specific interface callbacks */ int flexran_agent_register_s1ap_xface(mid_t mod_id); diff --git a/openair2/ENB_APP/flexran_agent_common.c b/openair2/ENB_APP/flexran_agent_common.c index dc320ef974..ec0b780a3a 100644 --- a/openair2/ENB_APP/flexran_agent_common.c +++ b/openair2/ENB_APP/flexran_agent_common.c @@ -893,31 +893,34 @@ int flexran_agent_handle_enb_config_reply(mid_t mod_id, const void *params, Prot Protocol__FlexranMessage *input = (Protocol__FlexranMessage *)params; Protocol__FlexEnbConfigReply *enb_config = input->enb_config_reply_msg; - if (enb_config->n_cell_config == 0) { - LOG_W(FLEXRAN_AGENT, - "received enb_config_reply message does not contain a cell_config\n"); - *msg = NULL; - return 0; - } - if (enb_config->n_cell_config > 1) LOG_W(FLEXRAN_AGENT, "ignoring slice configs for other cell except cell 0\n"); - if (flexran_agent_get_mac_xface(mod_id) && enb_config->cell_config[0]->slice_config) { - prepare_update_slice_config(mod_id, enb_config->cell_config[0]->slice_config); - } else if (enb_config->cell_config[0]->has_eutra_band - && enb_config->cell_config[0]->has_dl_freq - && enb_config->cell_config[0]->has_ul_freq - && enb_config->cell_config[0]->has_dl_bandwidth) { - initiate_soft_restart(mod_id, enb_config->cell_config[0]); - } else if (flexran_agent_get_rrc_xface(mod_id) - && enb_config->cell_config[0]->has_x2_ho_net_control) { - LOG_I(FLEXRAN_AGENT, - "setting X2 HO NetControl to %d\n", - enb_config->cell_config[0]->x2_ho_net_control); - const int rc = flexran_set_x2_ho_net_control(mod_id, enb_config->cell_config[0]->x2_ho_net_control); - if (rc < 0) - LOG_E(FLEXRAN_AGENT, "Error in configuring X2 handover controlled by network"); + if (enb_config->n_cell_config > 0) { + if (flexran_agent_get_mac_xface(mod_id) && enb_config->cell_config[0]->slice_config) { + prepare_update_slice_config(mod_id, enb_config->cell_config[0]->slice_config); + } + if (enb_config->cell_config[0]->has_eutra_band + && enb_config->cell_config[0]->has_dl_freq + && enb_config->cell_config[0]->has_ul_freq + && enb_config->cell_config[0]->has_dl_bandwidth) { + initiate_soft_restart(mod_id, enb_config->cell_config[0]); + } + if (flexran_agent_get_rrc_xface(mod_id) + && enb_config->cell_config[0]->has_x2_ho_net_control) { + LOG_I(FLEXRAN_AGENT, + "setting X2 HO NetControl to %d\n", + enb_config->cell_config[0]->x2_ho_net_control); + const int rc = flexran_set_x2_ho_net_control(mod_id, enb_config->cell_config[0]->x2_ho_net_control); + if (rc < 0) + LOG_E(FLEXRAN_AGENT, "Error in configuring X2 handover controlled by network"); + } + } + + if (flexran_agent_get_s1ap_xface(mod_id) && enb_config->s1ap) { + flexran_agent_handle_mme_update(mod_id, + enb_config->s1ap->n_mme, + enb_config->s1ap->mme); } *msg = NULL; diff --git a/openair2/ENB_APP/flexran_agent_ran_api.c b/openair2/ENB_APP/flexran_agent_ran_api.c index abade20846..3306dfe61b 100644 --- a/openair2/ENB_APP/flexran_agent_ran_api.c +++ b/openair2/ENB_APP/flexran_agent_ran_api.c @@ -3634,6 +3634,97 @@ int flexran_get_s1ap_mme_conf(mid_t mod_id, mid_t mme_index, Protocol__FlexS1apM return 0; } +int flexran_add_s1ap_mme(mid_t mod_id, size_t n_mme, char **mme_ipv4) { + s1ap_eNB_instance_t *s1ap = s1ap_eNB_get_instance(mod_id); + if (!s1ap) return -1; + if (!rrc_is_present(mod_id)) return -2; + + /* Reconstruct S1AP_REGISTER_ENB_REQ */ + MessageDef *m = itti_alloc_new_message(TASK_FLEXRAN_AGENT, S1AP_REGISTER_ENB_REQ); + RCconfig_S1(m, mod_id); + + const int CC_id = 0; + eNB_RRC_INST *rrc = RC.rrc[CC_id]; + RrcConfigurationReq *conf = &rrc->configuration; + S1AP_REGISTER_ENB_REQ(m).num_plmn = conf->num_plmn; + for (int i = 0; i < conf->num_plmn; ++i) { + S1AP_REGISTER_ENB_REQ(m).mcc[i] = conf->mcc[i]; + S1AP_REGISTER_ENB_REQ(m).mnc[i] = conf->mnc[i]; + S1AP_REGISTER_ENB_REQ(m).mnc_digit_length[i] = conf->mnc_digit_length[i]; + } + + /* reconstruct MME list, it might have been updated since initial + * configuration */ + S1AP_REGISTER_ENB_REQ(m).nb_mme = 0; + struct s1ap_eNB_mme_data_s *mme = NULL; + RB_FOREACH(mme, s1ap_mme_map, &s1ap->s1ap_mme_head) { + const int n = S1AP_REGISTER_ENB_REQ(m).nb_mme; + S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv4 = mme->mme_s1_ip.ipv4; + strcpy(S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv4_address, mme->mme_s1_ip.ipv4_address); + S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv6 = mme->mme_s1_ip.ipv6; + strcpy(S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv6_address, mme->mme_s1_ip.ipv6_address); + S1AP_REGISTER_ENB_REQ(m).broadcast_plmn_num[n] = mme->broadcast_plmn_num; + for (int i = 0; i < mme->broadcast_plmn_num; ++i) + S1AP_REGISTER_ENB_REQ(m).broadcast_plmn_index[n][i] = mme->broadcast_plmn_index[i]; + S1AP_REGISTER_ENB_REQ(m).nb_mme += 1; + } + + if (S1AP_REGISTER_ENB_REQ(m).nb_mme + n_mme > S1AP_MAX_NB_MME_IP_ADDRESS) + return -1; + + for (int i = 0; i < n_mme; ++i) { + const int n = S1AP_REGISTER_ENB_REQ(m).nb_mme; + strcpy(S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv4_address, mme_ipv4[0]); + S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv4 = 1; + S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv6 = 0; + S1AP_REGISTER_ENB_REQ(m).broadcast_plmn_num[n] = S1AP_REGISTER_ENB_REQ(m).num_plmn; + for (int i = 0; i < S1AP_REGISTER_ENB_REQ(m).num_plmn; ++i) + S1AP_REGISTER_ENB_REQ(m).broadcast_plmn_index[n][i] = i; + S1AP_REGISTER_ENB_REQ(m).nb_mme += 1; + } + + itti_send_msg_to_task (TASK_S1AP, ENB_MODULE_ID_TO_INSTANCE(mod_id), m); + + return 0; +} + +int flexran_remove_s1ap_mme(mid_t mod_id, size_t n_mme, char **mme_ipv4) { + s1ap_eNB_instance_t *s1ap = s1ap_eNB_get_instance(mod_id); + if (!s1ap) return -1; + struct s1ap_eNB_mme_data_s *mme = NULL; + RB_FOREACH(mme, s1ap_mme_map, &s1ap->s1ap_mme_head) { + if (mme->mme_s1_ip.ipv4 + && strncmp(mme->mme_s1_ip.ipv4_address, mme_ipv4[0], 16) == 0) + break; + } + if (!mme) + return -2; + + MessageDef *m = itti_alloc_new_message(TASK_FLEXRAN_AGENT, SCTP_CLOSE_ASSOCIATION); + SCTP_CLOSE_ASSOCIATION(m).assoc_id = mme->assoc_id; + itti_send_msg_to_task (TASK_SCTP, ENB_MODULE_ID_TO_INSTANCE(mod_id), m); + + switch (mme->state) { + case S1AP_ENB_STATE_WAITING: + s1ap->s1ap_mme_nb -= 1; + if (s1ap->s1ap_mme_pending_nb > 0) + s1ap->s1ap_mme_pending_nb -= 1; + break; + case S1AP_ENB_STATE_CONNECTED: + case S1AP_ENB_OVERLOAD: /* I am not sure the decrements are right here */ + s1ap->s1ap_mme_nb -= 1; + s1ap->s1ap_mme_associated_nb -= 1; + break; + case S1AP_ENB_STATE_DISCONNECTED: + default: + break; + } + RB_REMOVE(s1ap_mme_map, &s1ap->s1ap_mme_head, mme); + + return 0; +} + + int flexran_get_s1ap_ue(mid_t mod_id, rnti_t rnti, Protocol__FlexS1apUe * ue_conf){ if (!rrc_is_present(mod_id)) return -1; s1ap_eNB_instance_t *s1ap = s1ap_eNB_get_instance(mod_id); diff --git a/openair2/ENB_APP/flexran_agent_ran_api.h b/openair2/ENB_APP/flexran_agent_ran_api.h index ce32883852..3c2803d663 100644 --- a/openair2/ENB_APP/flexran_agent_ran_api.h +++ b/openair2/ENB_APP/flexran_agent_ran_api.h @@ -832,6 +832,12 @@ int flexran_get_s1ap_mme_conf(mid_t mod_id, mid_t mme_index, Protocol__FlexS1apM /* Get the S1AP UE conf */ int flexran_get_s1ap_ue(mid_t mod_id, rnti_t rnti, Protocol__FlexS1apUe * ue_conf); +/* Add MMEs and re-issue S1AP Registration Request */ +int flexran_add_s1ap_mme(mid_t mod_id, size_t n_mme, char **mme_ipv4); + +/* Remove MMEs and and cut SCTP to MME */ +int flexran_remove_s1ap_mme(mid_t mod_id, size_t n_mme, char **mme_ipv4); + /********************* general information *****************/ /* get an ID for this BS (or part of a BS) */ uint64_t flexran_get_bs_id(mid_t mod_id); From a1f77198f74701c07340f3f51e06cc830c834e60 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Sat, 11 Apr 2020 13:40:50 +0200 Subject: [PATCH 481/553] FlexRAN: Manage PLMNs --- .../CONTROL_MODULES/S1AP/flexran_agent_s1ap.c | 24 +++++++ .../CONTROL_MODULES/S1AP/flexran_agent_s1ap.h | 6 ++ openair2/ENB_APP/flexran_agent_common.c | 6 ++ openair2/ENB_APP/flexran_agent_ran_api.c | 71 +++++++++++++++++++ openair2/ENB_APP/flexran_agent_ran_api.h | 3 + 5 files changed, 110 insertions(+) diff --git a/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.c b/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.c index d5fc5627a0..c2d7cb9e55 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.c +++ b/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.c @@ -158,6 +158,30 @@ void flexran_agent_handle_mme_update(mid_t mod_id, } } +void flexran_agent_handle_plmn_update(mid_t mod_id, + int CC_id, + size_t n_plmn, + Protocol__FlexPlmn **plmn_id) { + if (n_plmn < 1 || n_plmn > 6) { + LOG_E(FLEXRAN_AGENT, "cannot handle %lu PLMNs\n", n_plmn); + return; + } + + /* We assume the controller has checked all the parameters within each + * plmn_id */ + int rc = flexran_set_new_plmn_id(mod_id, CC_id, n_plmn, plmn_id); + if (rc == 0) { + LOG_I(FLEXRAN_AGENT, "set %lu new PLMNs:\n", n_plmn); + for (int i = 0; i < (int)n_plmn; ++i) + LOG_I(FLEXRAN_AGENT, " MCC %d MNC %d MNC length %d\n", + plmn_id[i]->mcc, plmn_id[i]->mnc, plmn_id[0]->mnc_length); + } else { + LOG_W(FLEXRAN_AGENT, + "could not set new PLMN configuration: flexran_set_new_plmn_id() returned %d\n", + rc); + } +} + int flexran_agent_register_s1ap_xface(mid_t mod_id) { if (agent_s1ap_xface[mod_id]) { LOG_E(FLEXRAN_AGENT, "S1AP agent CM for eNB %d is already registered\n", mod_id); diff --git a/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.h b/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.h index 54ea2926a8..006eaa1d3c 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.h +++ b/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.h @@ -65,6 +65,12 @@ void flexran_agent_handle_mme_update(mid_t mod_id, size_t n_mme, Protocol__FlexS1apMme **mme); +/* Set a new PLMN configuration */ +void flexran_agent_handle_plmn_update(mid_t mod_id, + int CC_id, + size_t n_plmn, + Protocol__FlexPlmn **plmn_id); + /* Register technology specific interface callbacks */ int flexran_agent_register_s1ap_xface(mid_t mod_id); diff --git a/openair2/ENB_APP/flexran_agent_common.c b/openair2/ENB_APP/flexran_agent_common.c index ec0b780a3a..e77b2fb386 100644 --- a/openair2/ENB_APP/flexran_agent_common.c +++ b/openair2/ENB_APP/flexran_agent_common.c @@ -915,6 +915,12 @@ int flexran_agent_handle_enb_config_reply(mid_t mod_id, const void *params, Prot if (rc < 0) LOG_E(FLEXRAN_AGENT, "Error in configuring X2 handover controlled by network"); } + if (flexran_agent_get_rrc_xface(mod_id) && enb_config->cell_config[0]->n_plmn_id > 0) { + flexran_agent_handle_plmn_update(mod_id, + 0, + enb_config->cell_config[0]->n_plmn_id, + enb_config->cell_config[0]->plmn_id); + } } if (flexran_agent_get_s1ap_xface(mod_id) && enb_config->s1ap) { diff --git a/openair2/ENB_APP/flexran_agent_ran_api.c b/openair2/ENB_APP/flexran_agent_ran_api.c index 3306dfe61b..0fcc51782e 100644 --- a/openair2/ENB_APP/flexran_agent_ran_api.c +++ b/openair2/ENB_APP/flexran_agent_ran_api.c @@ -3724,6 +3724,77 @@ int flexran_remove_s1ap_mme(mid_t mod_id, size_t n_mme, char **mme_ipv4) { return 0; } +int flexran_set_new_plmn_id(mid_t mod_id, int CC_id, size_t n_plmn, Protocol__FlexPlmn **plmn_id) { + if (!rrc_is_present(mod_id)) + return -1; + s1ap_eNB_instance_t *s1ap = s1ap_eNB_get_instance(mod_id); + if (!s1ap) + return -2; + + eNB_RRC_INST *rrc = RC.rrc[CC_id]; + RrcConfigurationReq *conf = &rrc->configuration; + + uint8_t num_plmn_old = conf->num_plmn; + uint16_t mcc[PLMN_LIST_MAX_SIZE]; + uint16_t mnc[PLMN_LIST_MAX_SIZE]; + uint8_t mnc_digit_length[PLMN_LIST_MAX_SIZE]; + for (int i = 0; i < num_plmn_old; ++i) { + mcc[i] = conf->mcc[i]; + mnc[i] = conf->mnc[i]; + mnc_digit_length[i] = conf->mnc_digit_length[i]; + } + + conf->num_plmn = (uint8_t) n_plmn; + for (int i = 0; i < conf->num_plmn; ++i) { + conf->mcc[i] = plmn_id[i]->mcc; + conf->mnc[i] = plmn_id[i]->mnc; + conf->mnc_digit_length[i] = plmn_id[i]->mnc_length; + } + + rrc_eNB_carrier_data_t *carrier = &rrc->carrier[CC_id]; + extern uint8_t do_SIB1(rrc_eNB_carrier_data_t *carrier, + int Mod_id, + int CC_id, + BOOLEAN_t brOption, + RrcConfigurationReq *configuration); + carrier->sizeof_SIB1 = do_SIB1(carrier, mod_id, CC_id, FALSE, conf); + if (carrier->sizeof_SIB1 < 0) + return -1337; /* SIB1 encoding failed, hell will probably break loose */ + + s1ap->num_plmn = (uint8_t) n_plmn; + for (int i = 0; i < conf->num_plmn; ++i) { + s1ap->mcc[i] = plmn_id[i]->mcc; + s1ap->mnc[i] = plmn_id[i]->mnc; + s1ap->mnc_digit_length[i] = plmn_id[i]->mnc_length; + } + + int bpn_failed = 0; + struct s1ap_eNB_mme_data_s *mme = NULL; + RB_FOREACH(mme, s1ap_mme_map, &s1ap->s1ap_mme_head) { + for (int i = 0; i < mme->broadcast_plmn_num; ++i) { + /* search the new index and update. If we don't find, we count this using + * bpn_failed to now how many broadcast_plmns could not be updated */ + int idx = mme->broadcast_plmn_index[i]; + int omcc = mcc[idx]; + int omnc = mnc[idx]; + int omncl = mnc_digit_length[idx]; + int j = 0; + for (j = 0; j < s1ap->num_plmn; ++j) { + if (s1ap->mcc[j] == omcc + && s1ap->mnc[j] == omnc + && s1ap->mnc_digit_length[j] == omncl) { + mme->broadcast_plmn_index[i] = j; + break; + } + } + if (j == s1ap->num_plmn) /* could not find the old PLMN in the new ones */ + bpn_failed++; + } + } + if (bpn_failed > 0) + return -10000 - bpn_failed; + return 0; +} int flexran_get_s1ap_ue(mid_t mod_id, rnti_t rnti, Protocol__FlexS1apUe * ue_conf){ if (!rrc_is_present(mod_id)) return -1; diff --git a/openair2/ENB_APP/flexran_agent_ran_api.h b/openair2/ENB_APP/flexran_agent_ran_api.h index 3c2803d663..9d1bfb9d3e 100644 --- a/openair2/ENB_APP/flexran_agent_ran_api.h +++ b/openair2/ENB_APP/flexran_agent_ran_api.h @@ -838,6 +838,9 @@ int flexran_add_s1ap_mme(mid_t mod_id, size_t n_mme, char **mme_ipv4); /* Remove MMEs and and cut SCTP to MME */ int flexran_remove_s1ap_mme(mid_t mod_id, size_t n_mme, char **mme_ipv4); +/* Set a new PLMN configuration */ +int flexran_set_new_plmn_id(mid_t mod_id, int CC_id, size_t n_plmn, Protocol__FlexPlmn **plmn_id); + /********************* general information *****************/ /* get an ID for this BS (or part of a BS) */ uint64_t flexran_get_bs_id(mid_t mod_id); From 332dec605ace8cfec771d3c578b335588563ac9e Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Tue, 14 Apr 2020 14:47:27 +0200 Subject: [PATCH 482/553] UE: Print all SIB1 decoded PLMNs --- openair2/RRC/LTE/rrc_UE.c | 65 +++++++++++++++++++-------------------- 1 file changed, 32 insertions(+), 33 deletions(-) diff --git a/openair2/RRC/LTE/rrc_UE.c b/openair2/RRC/LTE/rrc_UE.c index 4116f5367e..53348f5621 100644 --- a/openair2/RRC/LTE/rrc_UE.c +++ b/openair2/RRC/LTE/rrc_UE.c @@ -2794,44 +2794,43 @@ int decode_SIB1( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB_index, LTE_SystemInformationBlockType1_t *sib1 = UE_rrc_inst[ctxt_pP->module_id].sib1[eNB_index]; VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_RRC_UE_DECODE_SIB1, VCD_FUNCTION_IN ); LOG_I( RRC, "[UE %d] : Dumping SIB 1\n", ctxt_pP->module_id ); - LTE_PLMN_Identity_t *PLMN_identity = &sib1->cellAccessRelatedInfo.plmn_IdentityList.list.array[0]->plmn_Identity; - int mccdigits = PLMN_identity->mcc->list.count; - int mncdigits = PLMN_identity->mnc.list.count; - int mcc; + const int n = sib1->cellAccessRelatedInfo.plmn_IdentityList.list.count; + for (int i = 0; i < n; ++i) { + LTE_PLMN_Identity_t *PLMN_identity = &sib1->cellAccessRelatedInfo.plmn_IdentityList.list.array[i]->plmn_Identity; + int mccdigits = PLMN_identity->mcc->list.count; + int mncdigits = PLMN_identity->mnc.list.count; - if (mccdigits == 2) { - mcc = *PLMN_identity->mcc->list.array[0]*10 + *PLMN_identity->mcc->list.array[1]; - } else { - mcc = *PLMN_identity->mcc->list.array[0]*100 + *PLMN_identity->mcc->list.array[1]*10 + *PLMN_identity->mcc->list.array[2]; + int mcc; + if (mccdigits == 2) { + mcc = *PLMN_identity->mcc->list.array[0]*10 + *PLMN_identity->mcc->list.array[1]; + } else { + mcc = *PLMN_identity->mcc->list.array[0]*100 + *PLMN_identity->mcc->list.array[1]*10 + *PLMN_identity->mcc->list.array[2]; + } + + int mnc; + if (mncdigits == 2) { + mnc = *PLMN_identity->mnc.list.array[0]*10 + *PLMN_identity->mnc.list.array[1]; + } else { + mnc = *PLMN_identity->mnc.list.array[0]*100 + *PLMN_identity->mnc.list.array[1]*10 + *PLMN_identity->mnc.list.array[2]; + } + + LOG_I( RRC, "PLMN %d MCC %0*d, MNC %0*d\n", i + 1, mccdigits, mcc, mncdigits, mnc); + // search internal table for provider name + int plmn_ind = 0; + + while (plmn_data[plmn_ind].mcc > 0) { + if ((plmn_data[plmn_ind].mcc == mcc) && (plmn_data[plmn_ind].mnc == mnc)) { + LOG_I( RRC, "Found %s (name from internal table)\n", plmn_data[plmn_ind].oper_short ); + break; + } + + plmn_ind++; + } } - - int mnc; - - if (mncdigits == 2) { - mnc = *PLMN_identity->mnc.list.array[0]*10 + *PLMN_identity->mnc.list.array[1]; - } else { - mnc = *PLMN_identity->mnc.list.array[0]*100 + *PLMN_identity->mnc.list.array[1]*10 + *PLMN_identity->mnc.list.array[2]; - } - - LOG_I( RRC, "PLMN MCC %0*d, MNC %0*d, TAC 0x%04x\n", mccdigits, mcc, mncdigits, mnc, + LOG_I( RRC, "TAC 0x%04x\n", ((sib1->cellAccessRelatedInfo.trackingAreaCode.size == 2)?((sib1->cellAccessRelatedInfo.trackingAreaCode.buf[0]<<8) + sib1->cellAccessRelatedInfo.trackingAreaCode.buf[1]):0)); LOG_I( RRC, "cellReservedForOperatorUse : raw:%ld decoded:%s\n", sib1->cellAccessRelatedInfo.plmn_IdentityList.list.array[0]->cellReservedForOperatorUse, SIBreserved(sib1->cellAccessRelatedInfo.plmn_IdentityList.list.array[0]->cellReservedForOperatorUse) ); - // search internal table for provider name - int plmn_ind = 0; - - while (plmn_data[plmn_ind].mcc > 0) { - if ((plmn_data[plmn_ind].mcc == mcc) && (plmn_data[plmn_ind].mnc == mnc)) { - LOG_I( RRC, "Found %s (name from internal table)\n", plmn_data[plmn_ind].oper_short ); - break; - } - - plmn_ind++; - } - - if (plmn_data[plmn_ind].mcc < 0) { - LOG_I( RRC, "Found Unknown operator (no entry in internal table)\n" ); - } LOG_I( RRC, "cellAccessRelatedInfo.cellIdentity : raw:%"PRIu32" decoded:%02x.%02x.%02x.%02x\n", BIT_STRING_to_uint32( &sib1->cellAccessRelatedInfo.cellIdentity ), From 19c2856bbe0bf3400262085c1e8ef5dc05fbd1b7 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Tue, 14 Apr 2020 14:47:59 +0200 Subject: [PATCH 483/553] UE: Set correct selected PLMN Identity --- openair2/RRC/LTE/MESSAGES/asn1_msg.c | 4 ++-- openair2/RRC/LTE/MESSAGES/asn1_msg.h | 6 +++++- openair2/RRC/LTE/rrc_UE.c | 26 +++++++++++++++++++++----- openair2/RRC/LTE/rrc_defs.h | 1 + 4 files changed, 29 insertions(+), 8 deletions(-) diff --git a/openair2/RRC/LTE/MESSAGES/asn1_msg.c b/openair2/RRC/LTE/MESSAGES/asn1_msg.c index 583e10da94..9ede543003 100644 --- a/openair2/RRC/LTE/MESSAGES/asn1_msg.c +++ b/openair2/RRC/LTE/MESSAGES/asn1_msg.c @@ -2310,7 +2310,7 @@ uint8_t do_SidelinkUEInformation(uint8_t Mod_id, uint8_t *buffer, LTE_SL_Destin return((enc_rval.encoded+7)/8); } -uint8_t do_RRCConnectionSetupComplete(uint8_t Mod_id, uint8_t *buffer, const uint8_t Transaction_id, const int dedicatedInfoNASLength, const char *dedicatedInfoNAS) { +uint8_t do_RRCConnectionSetupComplete(uint8_t Mod_id, uint8_t *buffer, const uint8_t Transaction_id, uint8_t sel_plmn_id, const int dedicatedInfoNASLength, const char *dedicatedInfoNAS) { asn_enc_rval_t enc_rval; LTE_UL_DCCH_Message_t ul_dcch_msg; LTE_RRCConnectionSetupComplete_t *rrcConnectionSetupComplete; @@ -2323,7 +2323,7 @@ uint8_t do_RRCConnectionSetupComplete(uint8_t Mod_id, uint8_t *buffer, const uin rrcConnectionSetupComplete->criticalExtensions.choice.c1.present = LTE_RRCConnectionSetupComplete__criticalExtensions__c1_PR_rrcConnectionSetupComplete_r8; rrcConnectionSetupComplete->criticalExtensions.choice.c1.choice.rrcConnectionSetupComplete_r8.nonCriticalExtension=CALLOC(1, sizeof(*rrcConnectionSetupComplete->criticalExtensions.choice.c1.choice.rrcConnectionSetupComplete_r8.nonCriticalExtension)); - rrcConnectionSetupComplete->criticalExtensions.choice.c1.choice.rrcConnectionSetupComplete_r8.selectedPLMN_Identity= 1; + rrcConnectionSetupComplete->criticalExtensions.choice.c1.choice.rrcConnectionSetupComplete_r8.selectedPLMN_Identity= sel_plmn_id; rrcConnectionSetupComplete->criticalExtensions.choice.c1.choice.rrcConnectionSetupComplete_r8.registeredMME = NULL;//calloc(1,sizeof(*rrcConnectionSetupComplete->criticalExtensions.choice.c1.choice.rrcConnectionSetupComplete_r8.registeredMME)); /* diff --git a/openair2/RRC/LTE/MESSAGES/asn1_msg.h b/openair2/RRC/LTE/MESSAGES/asn1_msg.h index dda2340610..640d18a61f 100644 --- a/openair2/RRC/LTE/MESSAGES/asn1_msg.h +++ b/openair2/RRC/LTE/MESSAGES/asn1_msg.h @@ -142,7 +142,11 @@ uint8_t do_SidelinkUEInformation(uint8_t Mod_id, uint8_t *buffer, LTE_SL_Destina /** \brief Generate an RRCConnectionSetupComplete UL-DCCH-Message (UE) @param buffer Pointer to PER-encoded ASN.1 description of UL-DCCH-Message PDU @returns Size of encoded bit stream in bytes*/ -uint8_t do_RRCConnectionSetupComplete(uint8_t Mod_id, uint8_t *buffer, const uint8_t Transaction_id, const int dedicatedInfoNASLength, +uint8_t do_RRCConnectionSetupComplete(uint8_t Mod_id, + uint8_t *buffer, + const uint8_t Transaction_id, + uint8_t sel_plmn_id, + const int dedicatedInfoNASLength, const char *dedicatedInfoNAS); /** \brief Generate an RRCConnectionReconfigurationComplete UL-DCCH-Message (UE) diff --git a/openair2/RRC/LTE/rrc_UE.c b/openair2/RRC/LTE/rrc_UE.c index 53348f5621..bdf992c76a 100644 --- a/openair2/RRC/LTE/rrc_UE.c +++ b/openair2/RRC/LTE/rrc_UE.c @@ -128,8 +128,13 @@ static int decode_SIB1_MBMS( const protocol_ctxt_t *const ctxt_pP, const uint8_t * \param ctxt_pP Running context * \param eNB_index Index of corresponding eNB/CH * \param Transaction_id Transaction identifier + * \param sel_plmn_id selected PLMN Identity */ -static void rrc_ue_generate_RRCConnectionSetupComplete( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB_index, const uint8_t Transaction_id ); +static void rrc_ue_generate_RRCConnectionSetupComplete( + const protocol_ctxt_t *const ctxt_pP, + const uint8_t eNB_index, + const uint8_t Transaction_id, + uint8_t sel_plmn_id); /** \brief Generates/Encodes RRCConnectionReconfigurationComplete message at UE * \param ctxt_pP Running context @@ -367,6 +372,7 @@ char openair_rrc_ue_init( const module_id_t ue_mod_idP, const unsigned char eNB_ rrc_set_state (ue_mod_idP, RRC_STATE_INACTIVE); rrc_set_sub_state (ue_mod_idP, RRC_SUB_STATE_INACTIVE); LOG_I(RRC,"[UE %d] INIT State = RRC_IDLE (eNB %d)\n",ctxt.module_id,eNB_index); + UE_rrc_inst[ctxt.module_id].selected_plmn_identity = 1; UE_rrc_inst[ctxt.module_id].Info[eNB_index].State=RRC_IDLE; UE_rrc_inst[ctxt.module_id].Info[eNB_index].T300_active = 0; UE_rrc_inst[ctxt.module_id].Info[eNB_index].T304_active = 0; @@ -490,7 +496,11 @@ rrc_t310_expiration( } //----------------------------------------------------------------------------- -static void rrc_ue_generate_RRCConnectionSetupComplete( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB_index, const uint8_t Transaction_id ) { +static void rrc_ue_generate_RRCConnectionSetupComplete( + const protocol_ctxt_t *const ctxt_pP, + const uint8_t eNB_index, + const uint8_t Transaction_id, + uint8_t sel_plmn_id) { uint8_t buffer[100]; uint8_t size; const char *nas_msg; @@ -504,7 +514,7 @@ static void rrc_ue_generate_RRCConnectionSetupComplete( const protocol_ctxt_t *c nas_msg_length = sizeof(nas_attach_req_imsi); } - size = do_RRCConnectionSetupComplete(ctxt_pP->module_id, buffer, Transaction_id, nas_msg_length, nas_msg); + size = do_RRCConnectionSetupComplete(ctxt_pP->module_id, buffer, Transaction_id, sel_plmn_id, nas_msg_length, nas_msg); LOG_I(RRC,"[UE %d][RAPROC] Frame %d : Logical Channel UL-DCCH (SRB1), Generating RRCConnectionSetupComplete (bytes%d, eNB %d)\n", ctxt_pP->module_id,ctxt_pP->frame, size, eNB_index); LOG_D(RLC, @@ -624,7 +634,8 @@ int rrc_ue_decode_ccch( const protocol_ctxt_t *const ctxt_pP, const SRB_INFO *co rrc_ue_generate_RRCConnectionSetupComplete( ctxt_pP, eNB_index, - dl_ccch_msg->message.choice.c1.choice.rrcConnectionSetup.rrc_TransactionIdentifier); + dl_ccch_msg->message.choice.c1.choice.rrcConnectionSetup.rrc_TransactionIdentifier, + UE_rrc_inst[ctxt_pP->module_id].selected_plmn_identity); rval = 0; break; @@ -2969,6 +2980,7 @@ int decode_SIB1( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB_index, NAS_CELL_SELECTION_CNF (msg_p).rsrp = rsrp; itti_send_msg_to_task(TASK_NAS_UE, ctxt_pP->instance, msg_p); cell_valid = 1; + UE_rrc_inst[ctxt_pP->module_id].selected_plmn_identity = plmn + 1; break; } } @@ -2979,7 +2991,11 @@ int decode_SIB1( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB_index, MessageDef *msg_p; msg_p = itti_alloc_new_message(TASK_RRC_UE, PHY_FIND_NEXT_CELL_REQ); itti_send_msg_to_task(TASK_PHY_UE, ctxt_pP->instance, msg_p); - LOG_E(RRC, "Synched with a cell, but PLMN doesn't match our SIM, the message PHY_FIND_NEXT_CELL_REQ is sent but lost in current UE implementation! \n"); + LOG_E(RRC, + "Synched with a cell, but PLMN doesn't match our SIM " + "(selected_plmn_identity %d), the message PHY_FIND_NEXT_CELL_REQ " + "is sent but lost in current UE implementation!\n", + UE_rrc_inst[ctxt_pP->module_id].selected_plmn_identity); } } diff --git a/openair2/RRC/LTE/rrc_defs.h b/openair2/RRC/LTE/rrc_defs.h index e366061674..3c02c45bc1 100644 --- a/openair2/RRC/LTE/rrc_defs.h +++ b/openair2/RRC/LTE/rrc_defs.h @@ -809,6 +809,7 @@ typedef struct UE_RRC_INST_s { Rrc_Sub_State_t RrcSubState; plmn_t plmnID; Byte_t rat; + uint8_t selected_plmn_identity; as_nas_info_t initialNasMsg; OAI_UECapability_t *UECap; uint8_t *UECapability; From a96c3761cc24101c1708b7bec465afa6dd553fed Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Thu, 21 May 2020 21:18:26 +0200 Subject: [PATCH 484/553] Log TBS in every window --- openair2/LAYER2/MAC/eNB_scheduler_dlsch.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c index 7621994ab2..2382af3636 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c @@ -588,6 +588,7 @@ schedule_ue_spec(module_id_t module_idP, UE_sched_ctrl_t *ue_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; UE_TEMPLATE *ue_template = &UE_info->UE_template[CC_id][UE_id]; eNB_UE_STATS *eNB_UE_stats = &UE_info->eNB_UE_stats[CC_id][UE_id]; + eNB_UE_stats->TBS = 0; const rnti_t rnti = ue_template->rnti; // If TDD @@ -799,6 +800,7 @@ schedule_ue_spec(module_id_t module_idP, eNB_UE_stats->rbs_used_retx = nb_rb; eNB_UE_stats->total_rbs_used_retx += nb_rb; eNB_UE_stats->dlsch_mcs2 = eNB_UE_stats->dlsch_mcs1; + eNB_UE_stats->TBS = TBS; } else { // Now check RLC information to compute number of required RBs // get maximum TBS size for RLC request From d0baab6ed3ca0e618283620059faf28ae97ba832 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Fri, 12 Jun 2020 19:25:44 +0200 Subject: [PATCH 485/553] DLSCH: limit LC bytes according to preprocessor --- openair2/LAYER2/MAC/eNB_scheduler_dlsch.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c index 2382af3636..c35af34a7f 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c @@ -844,13 +844,18 @@ schedule_ue_spec(module_id_t module_idP, if (ue_sched_ctrl->dl_lc_bytes[i] == 0) // no data in this LC! continue; - LOG_D(MAC, "[eNB %d] SFN/SF %d.%d, LC%d->DLSCH CC_id %d, Requesting %d bytes from RLC (RRC message)\n", + const uint32_t data = + min(ue_sched_ctrl->dl_lc_bytes[i], + TBS - ta_len - header_length_total - sdu_length_total - 3); + LOG_D(MAC, + "[eNB %d] SFN/SF %d.%d, LC%d->DLSCH CC_id %d, Requesting %d " + "bytes from RLC (RRC message)\n", module_idP, frameP, subframeP, lcid, CC_id, - TBS - ta_len - header_length_total - sdu_length_total - 3); + data); sdu_lengths[num_sdus] = mac_rlc_data_req(module_idP, rnti, @@ -859,7 +864,7 @@ schedule_ue_spec(module_id_t module_idP, ENB_FLAG_YES, MBMS_FLAG_NO, lcid, - TBS - ta_len - header_length_total - sdu_length_total - 3, + data, (char *)&dlsch_buffer[sdu_length_total], 0, 0 From 82194319cfca0ef23c5a838f8d517faf424ed147 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Wed, 24 Jun 2020 14:24:02 +0200 Subject: [PATCH 486/553] Bugfix DLSCH: only warn when retx with less RB The preprocessor pre-allocates a CCE. Thus, when arriving at the check for the number of RBs for retransmission, it is too late to skip the UE. Therefore, only print a warning. The default schedulers allocate a correct amount of RBs for retransmissions, therefore it is ok. --- openair2/LAYER2/MAC/eNB_scheduler_dlsch.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c index c35af34a7f..783d4e8b1a 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c @@ -680,15 +680,15 @@ schedule_ue_spec(module_id_t module_idP, const uint32_t rbc = allocate_prbs_sub( nb_rb, N_RB_DL, N_RBG, ue_sched_ctrl->rballoc_sub_UE[CC_id]); - if (nb_rb > ue_sched_ctrl->pre_nb_available_rbs[CC_id]) { - LOG_D(MAC, - "[eNB %d] Frame %d CC_id %d : don't schedule UE %d, its retransmission takes more resources than we have\n", + if (nb_rb > ue_sched_ctrl->pre_nb_available_rbs[CC_id]) + LOG_W(MAC, + "[eNB %d] %d.%d CC_id %d : should not schedule UE %d, its " + "retransmission takes more resources than we have\n", module_idP, frameP, + subframeP, CC_id, UE_id); - continue; - } /* CDRX */ ue_sched_ctrl->harq_rtt_timer[CC_id][harq_pid] = 1; // restart HARQ RTT timer From 864fa84ba80c99e831a7d9be5f88968a728a8efc Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Wed, 20 May 2020 12:45:35 +0200 Subject: [PATCH 487/553] Default SCHED RR algo: optimize algo and defer RB calc. - Loop only to next UE instead of jumping multiple - mark used RBGs in rbg_mask - Only calculate number of RBs based on CQI when UE is selected, instead of calculating for all UEs which might be unnecessary. - When looping the list of UEs for RB allocation, remove UEs that have no data anymore instead of skipping them. --- openair2/LAYER2/MAC/pre_processor.c | 72 ++++++++++------------------- 1 file changed, 25 insertions(+), 47 deletions(-) diff --git a/openair2/LAYER2/MAC/pre_processor.c b/openair2/LAYER2/MAC/pre_processor.c index 4f3baf1783..62b9e1c2cc 100644 --- a/openair2/LAYER2/MAC/pre_processor.c +++ b/openair2/LAYER2/MAC/pre_processor.c @@ -86,9 +86,6 @@ int round_robin_dl(module_id_t Mod_id, int num_ue_req = 0; UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; - int rb_required[MAX_MOBILES_PER_ENB]; // how much UEs request - memset(rb_required, 0, sizeof(rb_required)); - int rbg = 0; for (; !rbgalloc_mask[rbg]; rbg++) ; /* fast-forward to first allowed RBG */ @@ -133,6 +130,7 @@ int round_robin_dl(module_id_t Mod_id, if (!rbgalloc_mask[rbg]) continue; ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1; + rbgalloc_mask[rbg] = 0; nb_rbg--; } LOG_D(MAC, @@ -150,22 +148,8 @@ int round_robin_dl(module_id_t Mod_id, return n_rbg_sched; for (; !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ; } else { - const int dlsch_mcs1 = cqi_to_mcs[UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id]]; - UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1 = dlsch_mcs1; - rb_required[UE_id] = - find_nb_rb_DL(dlsch_mcs1, - UE_info->UE_template[CC_id][UE_id].dl_buffer_total, - n_rbg_sched * RBGsize, - RBGsize); - if (rb_required[UE_id] > 0) + if (UE_info->UE_template[CC_id][UE_id].dl_buffer_total > 0) num_ue_req++; - LOG_D(MAC, - "%d/%d UE_id %d rb_required %d n_rbg_sched %d\n", - frame, - subframe, - UE_id, - rb_required[UE_id], - n_rbg_sched); } } @@ -178,12 +162,13 @@ int round_robin_dl(module_id_t Mod_id, g_start_ue_dl = UE_list->head; int UE_id = g_start_ue_dl; UE_list_t UE_sched; - int rb_required_total = 0; + int *cur_UE = &UE_sched.head; + int num_ue_sched = 0; max_num_ue = min(min(max_num_ue, num_ue_req), n_rbg_sched); - int *cur_UE = &UE_sched.head; + int rb_required[MAX_MOBILES_PER_ENB]; // how much UEs request while (num_ue_sched < max_num_ue) { - while (rb_required[UE_id] == 0) + while (UE_info->UE_template[CC_id][UE_id].dl_buffer_total <= 0) UE_id = next_ue_list_looped(UE_list, UE_id); const uint8_t cqi = UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id]; const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi); @@ -195,42 +180,42 @@ int round_robin_dl(module_id_t Mod_id, continue; } UE_info->UE_sched_ctrl[UE_id].pre_dci_dl_pdu_idx = idx; + const int mcs = cqi_to_mcs[cqi]; + UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1 = mcs; + const uint32_t B = UE_info->UE_template[CC_id][UE_id].dl_buffer_total; + rb_required[UE_id] = find_nb_rb_DL(mcs, B, n_rbg_sched * RBGsize, RBGsize); *cur_UE = UE_id; cur_UE = &UE_sched.next[UE_id]; - rb_required_total += rb_required[UE_id]; num_ue_sched++; UE_id = next_ue_list_looped(UE_list, UE_id); // next candidate } *cur_UE = -1; /* for one UE after the next: allocate resources */ - for (int UE_id = UE_sched.head; UE_id >= 0; - UE_id = next_ue_list_looped(&UE_sched, UE_id)) { - if (rb_required[UE_id] <= 0) - continue; + cur_UE = &UE_sched.head; + while (*cur_UE >= 0) { + const int UE_id = *cur_UE; UE_sched_ctrl_t *ue_ctrl = &UE_info->UE_sched_ctrl[UE_id]; ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1; + rbgalloc_mask[rbg] = 0; const int sRBG = rbg == N_RBG - 1 ? RBGlastsize : RBGsize; ue_ctrl->pre_nb_available_rbs[CC_id] += sRBG; rb_required[UE_id] -= sRBG; - rb_required_total -= sRBG; - if (rb_required_total <= 0) - break; + if (rb_required[UE_id] <= 0) { + *cur_UE = UE_sched.next[*cur_UE]; + if (*cur_UE < 0) + cur_UE = &UE_sched.head; + } else { + cur_UE = UE_sched.next[*cur_UE] < 0 ? &UE_sched.head : &UE_sched.next[*cur_UE]; + } n_rbg_sched--; if (n_rbg_sched <= 0) break; for (rbg++; !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ; } - /* if not all UEs could be allocated in this round */ - if (num_ue_req > max_num_ue) { - /* go to the first one we missed */ - for (int i = 0; i < max_num_ue; ++i) - g_start_ue_dl = next_ue_list_looped(UE_list, g_start_ue_dl); - } else { - /* else, just start with the next UE next time */ - g_start_ue_dl = next_ue_list_looped(UE_list, g_start_ue_dl); - } + /* just start with the next UE next time */ + g_start_ue_dl = next_ue_list_looped(UE_list, g_start_ue_dl); return n_rbg_sched; } @@ -742,15 +727,8 @@ int round_robin_ul(module_id_t Mod_id, } } - /* if not all UEs could be allocated in this round */ - if (num_ue_req > max_num_ue) { - /* go to the first one we missed */ - for (int i = 0; i < max_num_ue; ++i) - g_start_ue_ul = next_ue_list_looped(UE_list, g_start_ue_ul); - } else { - /* else, just start with the next UE next time */ - g_start_ue_ul = next_ue_list_looped(UE_list, g_start_ue_ul); - } + /* just start with the next UE next time */ + g_start_ue_ul = next_ue_list_looped(UE_list, g_start_ue_ul); return rbs[0].length + (num_contig_rb > 1 ? rbs[1].length : 0); } From 8c7d94133f2400c836725484ec70820b9a10b1f0 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Wed, 24 Jun 2020 14:20:27 +0200 Subject: [PATCH 488/553] Bugfix RR DL: a retx UE might not be allocated again --- openair2/LAYER2/MAC/pre_processor.c | 68 ++++++++++++++--------------- 1 file changed, 33 insertions(+), 35 deletions(-) diff --git a/openair2/LAYER2/MAC/pre_processor.c b/openair2/LAYER2/MAC/pre_processor.c index 62b9e1c2cc..8324969a9c 100644 --- a/openair2/LAYER2/MAC/pre_processor.c +++ b/openair2/LAYER2/MAC/pre_processor.c @@ -83,15 +83,22 @@ int round_robin_dl(module_id_t Mod_id, const int N_RBG = to_rbg(RC.mac[Mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth); const int RBGsize = get_min_rb_unit(Mod_id, CC_id); const int RBGlastsize = get_rbg_size_last(Mod_id, CC_id); - int num_ue_req = 0; UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; int rbg = 0; for (; !rbgalloc_mask[rbg]; rbg++) ; /* fast-forward to first allowed RBG */ - // Calculate the amount of RBs every UE wants to send. - for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { + /* just start with the UE after the one we had last time. If it does not + * exist, this will start at the head */ + int g_start_ue_dl = data; + g_start_ue_dl = next_ue_list_looped(UE_list, g_start_ue_dl); + + int UE_id = g_start_ue_dl; + UE_list_t UE_sched; + int *cur_UE = &UE_sched.head; + // Allocate retransmissions, and mark UEs with new transmissions + do { // check whether there are HARQ retransmissions const COMMON_channels_t *cc = &RC.mac[Mod_id]->common_channels[CC_id]; const uint8_t harq_pid = frame_subframe2_dl_harq_pid(cc->tdd_Config, frame, subframe); @@ -100,14 +107,14 @@ int round_robin_dl(module_id_t Mod_id, if (round != 8) { // retransmission: allocate const int nb_rb = UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid]; if (nb_rb == 0) - continue; + goto skip_ue; int nb_rbg = (nb_rb + (nb_rb % RBGsize)) / RBGsize; // needs more RBGs than we can allocate if (nb_rbg > n_rbg_sched) { LOG_D(MAC, "retransmission of UE %d needs more RBGs (%d) than we have (%d)\n", UE_id, nb_rbg, n_rbg_sched); - continue; + goto skip_ue; } // ensure that the number of RBs can be contained by the RBGs (!), i.e. // if we allocate the last RBG this one should have the full RBGsize @@ -116,12 +123,12 @@ int round_robin_dl(module_id_t Mod_id, LOG_D(MAC, "retransmission of UE %d needs %d RBs, but the last RBG %d is too small (%d, normal %d)\n", UE_id, nb_rb, N_RBG - 1, RBGlastsize, RBGsize); - continue; + goto skip_ue; } const uint8_t cqi = ue_ctrl->dl_cqi[CC_id]; const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi); if (idx < 0) - continue; // cannot allocate CCE + goto skip_ue; // cannot allocate CCE ue_ctrl->pre_dci_dl_pdu_idx = idx; // retransmissions: directly allocate n_rbg_sched -= nb_rbg; @@ -148,35 +155,32 @@ int round_robin_dl(module_id_t Mod_id, return n_rbg_sched; for (; !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ; } else { - if (UE_info->UE_template[CC_id][UE_id].dl_buffer_total > 0) - num_ue_req++; + if (UE_info->UE_template[CC_id][UE_id].dl_buffer_total > 0) { + *cur_UE = UE_id; + cur_UE = &UE_sched.next[UE_id]; + } } - } - if (num_ue_req == 0) +skip_ue: + UE_id = next_ue_list_looped(UE_list, UE_id); + } while (UE_id != g_start_ue_dl); + *cur_UE = -1; // mark end + + if (UE_sched.head < 0) return n_rbg_sched; // no UE has a transmission - // after allocating retransmissions: build list of UE to allocate. - // if start_UE does not exist anymore (detach etc), start at first UE - if (g_start_ue_dl == -1) - g_start_ue_dl = UE_list->head; - int UE_id = g_start_ue_dl; - UE_list_t UE_sched; - int *cur_UE = &UE_sched.head; - - int num_ue_sched = 0; - max_num_ue = min(min(max_num_ue, num_ue_req), n_rbg_sched); + // after allocating retransmissions: pre-allocate CCE, compute number of + // requested RBGs + max_num_ue = min(max_num_ue, n_rbg_sched); int rb_required[MAX_MOBILES_PER_ENB]; // how much UEs request - while (num_ue_sched < max_num_ue) { - while (UE_info->UE_template[CC_id][UE_id].dl_buffer_total <= 0) - UE_id = next_ue_list_looped(UE_list, UE_id); + cur_UE = &UE_sched.head; + while (*cur_UE >= 0 && max_num_ue > 0) { + const int UE_id = *cur_UE; + cur_UE = &UE_sched.next[UE_id]; // go to next const uint8_t cqi = UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id]; const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi); if (idx < 0) { LOG_D(MAC, "cannot allocate CCE for UE %d, skipping\n", UE_id); - num_ue_req--; - max_num_ue = min(min(max_num_ue, num_ue_req), n_rbg_sched); - UE_id = next_ue_list_looped(UE_list, UE_id); // next candidate continue; } UE_info->UE_sched_ctrl[UE_id].pre_dci_dl_pdu_idx = idx; @@ -184,12 +188,9 @@ int round_robin_dl(module_id_t Mod_id, UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1 = mcs; const uint32_t B = UE_info->UE_template[CC_id][UE_id].dl_buffer_total; rb_required[UE_id] = find_nb_rb_DL(mcs, B, n_rbg_sched * RBGsize, RBGsize); - *cur_UE = UE_id; - cur_UE = &UE_sched.next[UE_id]; - num_ue_sched++; - UE_id = next_ue_list_looped(UE_list, UE_id); // next candidate + max_num_ue--; } - *cur_UE = -1; + *cur_UE = -1; // not all UEs might be allocated, mark end /* for one UE after the next: allocate resources */ cur_UE = &UE_sched.head; @@ -214,9 +215,6 @@ int round_robin_dl(module_id_t Mod_id, for (rbg++; !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ; } - /* just start with the next UE next time */ - g_start_ue_dl = next_ue_list_looped(UE_list, g_start_ue_dl); - return n_rbg_sched; } From 18a6961fcdc609b6f19017c9b9e8bb391aff522a Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Wed, 17 Jun 2020 11:05:35 +0200 Subject: [PATCH 489/553] Format to dynamically handle default DL SCHED algo --- openair2/LAYER2/MAC/mac.h | 15 +++++++ openair2/LAYER2/MAC/main.c | 6 ++- openair2/LAYER2/MAC/pre_processor.c | 69 +++++++++++++++++++---------- 3 files changed, 65 insertions(+), 25 deletions(-) diff --git a/openair2/LAYER2/MAC/mac.h b/openair2/LAYER2/MAC/mac.h index 329e262c82..0264951683 100644 --- a/openair2/LAYER2/MAC/mac.h +++ b/openair2/LAYER2/MAC/mac.h @@ -1274,6 +1274,19 @@ typedef struct { int length; } contig_rbs_t; +/** + * definition of a scheduling algorithm implementation used in the + * default scheduler + */ +typedef struct { + char *name; + void *(*setup)(void); + void (*unset)(void **); + int (*run)( + module_id_t, int, int, int, UE_list_t *, int, int, uint8_t *, void *); + void *data; +} default_sched_dl_algo_t; + /*! \brief eNB common channels */ typedef struct { int physCellId; @@ -1432,6 +1445,8 @@ typedef struct eNB_MAC_INST_s { UE_free_list_t UE_free_list; /// for scheduling selection SCHEDULER_MODES scheduler_mode; + /// scheduling algorithm used in default scheduler + default_sched_dl_algo_t dl_algo; int32_t puSch10xSnr; int32_t puCch10xSnr; diff --git a/openair2/LAYER2/MAC/main.c b/openair2/LAYER2/MAC/main.c index 1a88623a1f..39e342cba0 100644 --- a/openair2/LAYER2/MAC/main.c +++ b/openair2/LAYER2/MAC/main.c @@ -128,7 +128,11 @@ void mac_top_init_eNB(void) } mac[i]->if_inst = IF_Module_init(i); - + char *s = "round_robin_dl"; + void *d = dlsym(NULL, s); + AssertFatal(d, "%s(): no scheduler algo '%s' found\n", __func__, s); + mac[i]->dl_algo = *(default_sched_dl_algo_t *) d; + mac[i]->dl_algo.data = mac[i]->dl_algo.setup(); init_UE_info(&mac[i]->UE_info); init_slice_info(&mac[i]->slice_info); } diff --git a/openair2/LAYER2/MAC/pre_processor.c b/openair2/LAYER2/MAC/pre_processor.c index 8324969a9c..596e45ce2a 100644 --- a/openair2/LAYER2/MAC/pre_processor.c +++ b/openair2/LAYER2/MAC/pre_processor.c @@ -69,15 +69,26 @@ int get_rbg_size_last(module_id_t Mod_id, int CC_id) { return RBGsize; } -int g_start_ue_dl = -1; -int round_robin_dl(module_id_t Mod_id, - int CC_id, - int frame, - int subframe, - UE_list_t *UE_list, - int max_num_ue, - int n_rbg_sched, - uint8_t *rbgalloc_mask) { +void *rr_dl_setup(void) { + void *data = malloc(sizeof(int)); + *(int *) data = 0; + AssertFatal(data, "could not allocate data in %s()\n", __func__); + return data; +} +void rr_dl_unset(void **data) { + if (*data) + free(*data); + *data = NULL; +} +int rr_dl_run(module_id_t Mod_id, + int CC_id, + int frame, + int subframe, + UE_list_t *UE_list, + int max_num_ue, + int n_rbg_sched, + uint8_t *rbgalloc_mask, + void *data) { DevAssert(UE_list->head >= 0); DevAssert(n_rbg_sched > 0); const int N_RBG = to_rbg(RC.mac[Mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth); @@ -91,10 +102,10 @@ int round_robin_dl(module_id_t Mod_id, /* just start with the UE after the one we had last time. If it does not * exist, this will start at the head */ - int g_start_ue_dl = data; - g_start_ue_dl = next_ue_list_looped(UE_list, g_start_ue_dl); + int *start_ue = data; + *start_ue = next_ue_list_looped(UE_list, *start_ue); - int UE_id = g_start_ue_dl; + int UE_id = *start_ue; UE_list_t UE_sched; int *cur_UE = &UE_sched.head; // Allocate retransmissions, and mark UEs with new transmissions @@ -163,7 +174,7 @@ int round_robin_dl(module_id_t Mod_id, skip_ue: UE_id = next_ue_list_looped(UE_list, UE_id); - } while (UE_id != g_start_ue_dl); + } while (UE_id != *start_ue); *cur_UE = -1; // mark end if (UE_sched.head < 0) @@ -217,6 +228,14 @@ skip_ue: return n_rbg_sched; } +default_sched_dl_algo_t round_robin_dl = { + .name = "round_robin_dl", + .setup = rr_dl_setup, + .unset = rr_dl_unset, + .run = rr_dl_run, + .data = NULL +}; + // This function stores the downlink buffer for all the logical channels void @@ -306,8 +325,9 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id, int CC_id, frame_t frameP, sub_frame_t subframeP) { - UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; - const int N_RBG = to_rbg(RC.mac[Mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth); + eNB_MAC_INST *mac = RC.mac[Mod_id]; + UE_info_t *UE_info = &mac->UE_info; + const int N_RBG = to_rbg(mac->common_channels[CC_id].mib->message.dl_Bandwidth); const int RBGsize = get_min_rb_unit(Mod_id, CC_id); store_dlsch_buffer(Mod_id, CC_id, frameP, subframeP); @@ -364,7 +384,7 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id, if (UE_to_sched.head < 0) return; - uint8_t *vrb_map = RC.mac[Mod_id]->common_channels[CC_id].vrb_map; + uint8_t *vrb_map = mac->common_channels[CC_id].vrb_map; uint8_t rbgalloc_mask[N_RBG_MAX]; int n_rbg_sched = 0; for (int i = 0; i < N_RBG; i++) { @@ -376,14 +396,15 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id, n_rbg_sched += rbgalloc_mask[i]; } - round_robin_dl(Mod_id, - CC_id, - frameP, - subframeP, - &UE_to_sched, - 4, // max_num_ue - n_rbg_sched, - rbgalloc_mask); + mac->dl_algo.run(Mod_id, + CC_id, + frameP, + subframeP, + &UE_to_sched, + 4, // max_num_ue + n_rbg_sched, + rbgalloc_mask, + mac->dl_algo.data); // the following block is meant for validation of the pre-processor to check // whether all UE allocations are non-overlapping and is not necessary for From 2de57fbc3658223daa0cd0aa21472a728b52a39b Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Thu, 28 May 2020 16:17:52 +0200 Subject: [PATCH 490/553] Add Proportional Fair scheduler, wbCqi Selects UE with highest coefficient. Allocates until there are no more RBGs to allocate, or UE has no more data. In the latter case, continues with the next UE (second-highest coefficient). --- openair2/LAYER2/MAC/pre_processor.c | 164 ++++++++++++++++++++++++++++ 1 file changed, 164 insertions(+) diff --git a/openair2/LAYER2/MAC/pre_processor.c b/openair2/LAYER2/MAC/pre_processor.c index 596e45ce2a..dba6f3750f 100644 --- a/openair2/LAYER2/MAC/pre_processor.c +++ b/openair2/LAYER2/MAC/pre_processor.c @@ -237,6 +237,170 @@ default_sched_dl_algo_t round_robin_dl = { }; +void *pf_dl_setup(void) { + void *data = calloc(MAX_MOBILES_PER_ENB, sizeof(float)); + for (int i = 0; i < MAX_MOBILES_PER_ENB; i++) + *(float *) data = 0.0f; + AssertFatal(data, "could not allocate data in %s()\n", __func__); + return data; +} +void pf_dl_unset(void **data) { + if (*data) + free(*data); + *data = NULL; +} +int pf_wbcqi_dl_run(module_id_t Mod_id, + int CC_id, + int frame, + int subframe, + UE_list_t *UE_list, + int max_num_ue, + int n_rbg_sched, + uint8_t *rbgalloc_mask, + void *data) { + DevAssert(UE_list->head >= 0); + DevAssert(n_rbg_sched > 0); + const int N_RBG = to_rbg(RC.mac[Mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth); + const int RBGsize = get_min_rb_unit(Mod_id, CC_id); + const int RBGlastsize = get_rbg_size_last(Mod_id, CC_id); + UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; + + int rbg = 0; + for (; !rbgalloc_mask[rbg]; rbg++) + ; /* fast-forward to first allowed RBG */ + + UE_list_t UE_sched; // UEs that could be scheduled + int *uep = &UE_sched.head; + float *thr_ue = data; + float coeff_ue[MAX_MOBILES_PER_ENB]; + + for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { + const float a = 0.0005f; // corresponds to 200ms window + const uint32_t b = UE_info->eNB_UE_stats[CC_id][UE_id].TBS; + thr_ue[UE_id] = (1 - a) * thr_ue[UE_id] + a * b; + + // check whether there are HARQ retransmissions + const COMMON_channels_t *cc = &RC.mac[Mod_id]->common_channels[CC_id]; + const uint8_t harq_pid = frame_subframe2_dl_harq_pid(cc->tdd_Config, frame, subframe); + UE_sched_ctrl_t *ue_ctrl = &UE_info->UE_sched_ctrl[UE_id]; + const uint8_t round = ue_ctrl->round[CC_id][harq_pid]; + if (round != 8) { // retransmission: allocate + const int nb_rb = UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid]; + if (nb_rb == 0) + continue; + int nb_rbg = (nb_rb + (nb_rb % RBGsize)) / RBGsize; + // needs more RBGs than we can allocate + if (nb_rbg > n_rbg_sched) { + LOG_D(MAC, + "retransmission of UE %d needs more RBGs (%d) than we have (%d)\n", + UE_id, nb_rbg, n_rbg_sched); + continue; + } + // ensure that the number of RBs can be contained by the RBGs (!), i.e. + // if we allocate the last RBG this one should have the full RBGsize + if ((nb_rb % RBGsize) == 0 && nb_rbg == n_rbg_sched + && rbgalloc_mask[N_RBG - 1] && RBGlastsize != RBGsize) { + LOG_D(MAC, + "retransmission of UE %d needs %d RBs, but the last RBG %d is too small (%d, normal %d)\n", + UE_id, nb_rb, N_RBG - 1, RBGlastsize, RBGsize); + continue; + } + const uint8_t cqi = ue_ctrl->dl_cqi[CC_id]; + const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi); + if (idx < 0) + continue; // cannot allocate CCE + ue_ctrl->pre_dci_dl_pdu_idx = idx; + // retransmissions: directly allocate + n_rbg_sched -= nb_rbg; + ue_ctrl->pre_nb_available_rbs[CC_id] += nb_rb; + for (; nb_rbg > 0; rbg++) { + if (!rbgalloc_mask[rbg]) + continue; + ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1; + rbgalloc_mask[rbg] = 0; + nb_rbg--; + } + LOG_D(MAC, + "%4d.%d n_rbg_sched %d after retransmission reservation for UE %d " + "round %d retx nb_rb %d pre_nb_available_rbs %d\n", + frame, subframe, n_rbg_sched, UE_id, round, + UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid], + ue_ctrl->pre_nb_available_rbs[CC_id]); + /* if there are no more RBG to give, return */ + if (n_rbg_sched <= 0) + return 0; + max_num_ue--; + /* if there are no UEs that can be allocated anymore, return */ + if (max_num_ue == 0) + return n_rbg_sched; + for (; !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ; + } else { + if (UE_info->UE_template[CC_id][UE_id].dl_buffer_total == 0) + continue; + + const int mcs = cqi_to_mcs[UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id]]; + const uint32_t tbs = get_TBS_DL(mcs, RBGsize); + coeff_ue[UE_id] = (float) tbs / thr_ue[UE_id]; + //LOG_I(MAC, " pf UE %d: old TBS %d thr %f MCS %d TBS %d coeff %f\n", + // UE_id, b, thr_ue[UE_id], mcs, tbs, coeff_ue[UE_id]); + *uep = UE_id; + uep = &UE_sched.next[UE_id]; + } + } + *uep = -1; + + while (max_num_ue > 0 && n_rbg_sched > 0 && UE_sched.head >= 0) { + int *max = &UE_sched.head; /* assume head is max */ + int *p = &UE_sched.next[*max]; + while (*p >= 0) { + /* if the current one has larger coeff, save for later */ + if (coeff_ue[*p] > coeff_ue[*max]) + max = p; + p = &UE_sched.next[*p]; + } + /* remove the max one */ + const int UE_id = *max; + p = &UE_sched.next[*max]; + *max = UE_sched.next[*max]; + *p = -1; + + const uint8_t cqi = UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id]; + const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi); + if (idx < 0) + continue; + UE_info->UE_sched_ctrl[UE_id].pre_dci_dl_pdu_idx = idx; + + max_num_ue--; + + /* allocate as much as possible */ + const int mcs = cqi_to_mcs[cqi]; + UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1 = mcs; + int req = find_nb_rb_DL(mcs, + UE_info->UE_template[CC_id][UE_id].dl_buffer_total, + n_rbg_sched * RBGsize, + RBGsize); + UE_sched_ctrl_t *ue_ctrl = &UE_info->UE_sched_ctrl[UE_id]; + while (req > 0 && n_rbg_sched > 0) { + ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1; + rbgalloc_mask[rbg] = 0; + const int sRBG = rbg == N_RBG - 1 ? RBGlastsize : RBGsize; + ue_ctrl->pre_nb_available_rbs[CC_id] += sRBG; + req -= sRBG; + n_rbg_sched--; + for (rbg++; n_rbg_sched > 0 && !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ; + } + } + + return n_rbg_sched; +} +default_sched_dl_algo_t proportional_fair_wbcqi_dl = { + .name = "proportional_fair_wbcqi_dl", + .setup = pf_dl_setup, + .unset = pf_dl_unset, + .run = pf_wbcqi_dl_run, + .data = NULL +}; + // This function stores the downlink buffer for all the logical channels void store_dlsch_buffer(module_id_t Mod_id, From fe7236d9c4bfd7f00508123075b367d18a210072 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Fri, 22 May 2020 16:43:24 +0200 Subject: [PATCH 491/553] Add Maximum Throughput scheduler, wbCqi Selects the UE with the highest CQI. If two UEs have the same CQI, choses the one with highest number of bytes in RLC queue. Allocates as many RBGs as possible, and potentially continues with the next UE. --- openair2/LAYER2/MAC/pre_processor.c | 150 ++++++++++++++++++++++++++++ 1 file changed, 150 insertions(+) diff --git a/openair2/LAYER2/MAC/pre_processor.c b/openair2/LAYER2/MAC/pre_processor.c index dba6f3750f..436ec2435e 100644 --- a/openair2/LAYER2/MAC/pre_processor.c +++ b/openair2/LAYER2/MAC/pre_processor.c @@ -401,6 +401,156 @@ default_sched_dl_algo_t proportional_fair_wbcqi_dl = { .data = NULL }; +void *mt_dl_setup(void) { + return NULL; +} +void mt_dl_unset(void **data) { + *data = NULL; +} +int mt_wbcqi_dl_run(module_id_t Mod_id, + int CC_id, + int frame, + int subframe, + UE_list_t *UE_list, + int max_num_ue, + int n_rbg_sched, + uint8_t *rbgalloc_mask, + void *data) { + DevAssert(UE_list->head >= 0); + DevAssert(n_rbg_sched > 0); + const int N_RBG = to_rbg(RC.mac[Mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth); + const int RBGsize = get_min_rb_unit(Mod_id, CC_id); + const int RBGlastsize = get_rbg_size_last(Mod_id, CC_id); + UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; + + int rbg = 0; + for (; !rbgalloc_mask[rbg]; rbg++) + ; /* fast-forward to first allowed RBG */ + + UE_list_t UE_sched; // UEs that could be scheduled + int *uep = &UE_sched.head; + + for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { + // check whether there are HARQ retransmissions + const COMMON_channels_t *cc = &RC.mac[Mod_id]->common_channels[CC_id]; + const uint8_t harq_pid = frame_subframe2_dl_harq_pid(cc->tdd_Config, frame, subframe); + UE_sched_ctrl_t *ue_ctrl = &UE_info->UE_sched_ctrl[UE_id]; + const uint8_t round = ue_ctrl->round[CC_id][harq_pid]; + if (round != 8) { // retransmission: allocate + const int nb_rb = UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid]; + if (nb_rb == 0) + continue; + int nb_rbg = (nb_rb + (nb_rb % RBGsize)) / RBGsize; + // needs more RBGs than we can allocate + if (nb_rbg > n_rbg_sched) { + LOG_D(MAC, + "retransmission of UE %d needs more RBGs (%d) than we have (%d)\n", + UE_id, nb_rbg, n_rbg_sched); + continue; + } + // ensure that the number of RBs can be contained by the RBGs (!), i.e. + // if we allocate the last RBG this one should have the full RBGsize + if ((nb_rb % RBGsize) == 0 && nb_rbg == n_rbg_sched + && rbgalloc_mask[N_RBG - 1] && RBGlastsize != RBGsize) { + LOG_D(MAC, + "retransmission of UE %d needs %d RBs, but the last RBG %d is too small (%d, normal %d)\n", + UE_id, nb_rb, N_RBG - 1, RBGlastsize, RBGsize); + continue; + } + const uint8_t cqi = ue_ctrl->dl_cqi[CC_id]; + const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi); + if (idx < 0) + continue; // cannot allocate CCE + ue_ctrl->pre_dci_dl_pdu_idx = idx; + // retransmissions: directly allocate + n_rbg_sched -= nb_rbg; + ue_ctrl->pre_nb_available_rbs[CC_id] += nb_rb; + for (; nb_rbg > 0; rbg++) { + if (!rbgalloc_mask[rbg]) + continue; + ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1; + rbgalloc_mask[rbg] = 0; + nb_rbg--; + } + LOG_D(MAC, + "%4d.%d n_rbg_sched %d after retransmission reservation for UE %d " + "round %d retx nb_rb %d pre_nb_available_rbs %d\n", + frame, subframe, n_rbg_sched, UE_id, round, + UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid], + ue_ctrl->pre_nb_available_rbs[CC_id]); + /* if there are no more RBG to give, return */ + if (n_rbg_sched <= 0) + return 0; + max_num_ue--; + /* if there are no UEs that can be allocated anymore, return */ + if (max_num_ue == 0) + return n_rbg_sched; + for (; !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ; + } else { + if (UE_info->UE_template[CC_id][UE_id].dl_buffer_total == 0) + continue; + *uep = UE_id; + uep = &UE_sched.next[UE_id]; + } + } + *uep = -1; + + while (max_num_ue > 0 && n_rbg_sched > 0 && UE_sched.head >= 0) { + int *max = &UE_sched.head; /* assume head is max */ + int *p = &UE_sched.next[*max]; + while (*p >= 0) { + /* if the current one has better CQI, or the same and more data */ + const uint8_t maxCqi = UE_info->UE_sched_ctrl[*max].dl_cqi[CC_id]; + const uint32_t maxB = UE_info->UE_template[CC_id][*max].dl_buffer_total; + const uint8_t pCqi = UE_info->UE_sched_ctrl[*p].dl_cqi[CC_id]; + const uint32_t pB = UE_info->UE_template[CC_id][*p].dl_buffer_total; + if (pCqi > maxCqi || (pCqi == maxCqi && pB > maxB)) + max = p; + p = &UE_sched.next[*p]; + } + /* remove the max one */ + const int UE_id = *max; + p = &UE_sched.next[*max]; + *max = UE_sched.next[*max]; + *p = -1; + + const uint8_t cqi = UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id]; + const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi); + if (idx < 0) + continue; + UE_info->UE_sched_ctrl[UE_id].pre_dci_dl_pdu_idx = idx; + + max_num_ue--; + + /* allocate as much as possible */ + const int mcs = cqi_to_mcs[cqi]; + UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1 = mcs; + int req = find_nb_rb_DL(mcs, + UE_info->UE_template[CC_id][UE_id].dl_buffer_total, + n_rbg_sched * RBGsize, + RBGsize); + UE_sched_ctrl_t *ue_ctrl = &UE_info->UE_sched_ctrl[UE_id]; + while (req > 0 && n_rbg_sched > 0) { + ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1; + rbgalloc_mask[rbg] = 0; + const int sRBG = rbg == N_RBG - 1 ? RBGlastsize : RBGsize; + ue_ctrl->pre_nb_available_rbs[CC_id] += sRBG; + req -= sRBG; + n_rbg_sched--; + for (rbg++; n_rbg_sched > 0 && !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ; + } + } + + return n_rbg_sched; +} +default_sched_dl_algo_t maximum_throughput_wbcqi_dl = { + .name = "maximum_throughput_wbcqi_dl", + .setup = mt_dl_setup, + .unset = mt_dl_unset, + .run = mt_wbcqi_dl_run, + .data = NULL +}; + // This function stores the downlink buffer for all the logical channels void store_dlsch_buffer(module_id_t Mod_id, From af89a6b780ce65ccb42f6b01b0a85d16450f0e58 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Wed, 17 Jun 2020 18:40:48 +0200 Subject: [PATCH 492/553] Configurable Default Scheduler DL Algo --- openair2/ENB_APP/MACRLC_paramdef.h | 3 +++ openair2/ENB_APP/enb_config.c | 10 ++++++++++ 2 files changed, 13 insertions(+) diff --git a/openair2/ENB_APP/MACRLC_paramdef.h b/openair2/ENB_APP/MACRLC_paramdef.h index 55ce9d5059..fcee6142f0 100644 --- a/openair2/ENB_APP/MACRLC_paramdef.h +++ b/openair2/ENB_APP/MACRLC_paramdef.h @@ -58,6 +58,7 @@ #define CONFIG_STRING_MACRLC_SCHED_MODE "scheduler_mode" #define CONFIG_MACRLC_PUSCH10xSNR "puSch10xSnr" #define CONFIG_MACRLC_PUCCH10xSNR "puCch10xSnr" +#define CONFIG_STRING_MACRLC_DEFAULT_SCHED_DL_ALGO "default_sched_dl_algo" /*-------------------------------------------------------------------------------------------------------------------------------------------------------*/ /* MacRLC configuration parameters */ @@ -84,6 +85,7 @@ {CONFIG_STRING_MACRLC_SCHED_MODE, NULL, 0, strptr:NULL, defstrval:"default", TYPE_STRING, 0}, \ {CONFIG_MACRLC_PUSCH10xSNR, NULL, 0, iptr:NULL, defintval:200, TYPE_INT, 0}, \ {CONFIG_MACRLC_PUCCH10xSNR, NULL, 0, iptr:NULL, defintval:200, TYPE_INT, 0}, \ +{CONFIG_STRING_MACRLC_DEFAULT_SCHED_DL_ALGO, NULL, 0, strptr:NULL, defstrval:"round_robin_dl", TYPE_STRING, 0}, \ } #define MACRLC_CC_IDX 0 #define MACRLC_TRANSPORT_N_PREFERENCE_IDX 1 @@ -105,6 +107,7 @@ #define MACRLC_SCHED_MODE_IDX 17 #define MACRLC_PUSCH10xSNR_IDX 18 #define MACRLC_PUCCH10xSNR_IDX 19 +#define MACRLC_DEFAULT_SCHED_DL_ALGO_IDX 20 /*---------------------------------------------------------------------------------------------------------------------------------------------------------*/ #endif diff --git a/openair2/ENB_APP/enb_config.c b/openair2/ENB_APP/enb_config.c index 2200c8f013..0308c2fd79 100644 --- a/openair2/ENB_APP/enb_config.c +++ b/openair2/ENB_APP/enb_config.c @@ -29,6 +29,7 @@ #include #include +#include #include "common/utils/LOG/log.h" #include "assertions.h" @@ -260,6 +261,15 @@ void RCconfig_macrlc(int macrlc_has_f1[MAX_MAC_INST]) { global_scheduler_mode=SCHED_MODE_DEFAULT; printf("sched mode = default %d [%s]\n",global_scheduler_mode,*(MacRLC_ParamList.paramarray[j][MACRLC_SCHED_MODE_IDX].strptr)); } + + char *s = *MacRLC_ParamList.paramarray[j][MACRLC_DEFAULT_SCHED_DL_ALGO_IDX].strptr; + void *d = dlsym(NULL, s); + AssertFatal(d, "%s(): no default scheduler DL algo '%s' found\n", __func__, s); + // release default, add new + RC.mac[j]->dl_algo.unset(&RC.mac[j]->dl_algo.data); + RC.mac[j]->dl_algo = *(default_sched_dl_algo_t *) d; + RC.mac[j]->dl_algo.data = RC.mac[j]->dl_algo.setup(); + LOG_I(ENB_APP, "using default scheduler DL algo '%s'\n", RC.mac[j]->dl_algo.name); }// j=0..num_inst } /*else {// MacRLC_ParamList.numelt > 0 // ignore it From 6fcc4f59709708fc4f6862b9eb87264d1015a7fe Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Thu, 18 Jun 2020 17:32:01 +0200 Subject: [PATCH 493/553] Format to dynamically handle UL SCHED --- openair2/LAYER2/MAC/mac.h | 16 +++++- openair2/LAYER2/MAC/main.c | 5 ++ openair2/LAYER2/MAC/pre_processor.c | 79 ++++++++++++++++++----------- 3 files changed, 70 insertions(+), 30 deletions(-) diff --git a/openair2/LAYER2/MAC/mac.h b/openair2/LAYER2/MAC/mac.h index 0264951683..09585fae55 100644 --- a/openair2/LAYER2/MAC/mac.h +++ b/openair2/LAYER2/MAC/mac.h @@ -1276,7 +1276,7 @@ typedef struct { /** * definition of a scheduling algorithm implementation used in the - * default scheduler + * default DL scheduler */ typedef struct { char *name; @@ -1287,6 +1287,19 @@ typedef struct { void *data; } default_sched_dl_algo_t; +/** + * definition of a scheduling algorithm implementation used in the + * default UL scheduler + */ +typedef struct { + char *name; + void *(*setup)(void); + void (*unset)(void **); + int (*run)( + module_id_t, int, int, int, int, int, UE_list_t *, int, int, contig_rbs_t *, void *); + void *data; +} default_sched_ul_algo_t; + /*! \brief eNB common channels */ typedef struct { int physCellId; @@ -1447,6 +1460,7 @@ typedef struct eNB_MAC_INST_s { SCHEDULER_MODES scheduler_mode; /// scheduling algorithm used in default scheduler default_sched_dl_algo_t dl_algo; + default_sched_ul_algo_t ul_algo; int32_t puSch10xSnr; int32_t puCch10xSnr; diff --git a/openair2/LAYER2/MAC/main.c b/openair2/LAYER2/MAC/main.c index 39e342cba0..294eb12159 100644 --- a/openair2/LAYER2/MAC/main.c +++ b/openair2/LAYER2/MAC/main.c @@ -133,6 +133,11 @@ void mac_top_init_eNB(void) AssertFatal(d, "%s(): no scheduler algo '%s' found\n", __func__, s); mac[i]->dl_algo = *(default_sched_dl_algo_t *) d; mac[i]->dl_algo.data = mac[i]->dl_algo.setup(); + s = "round_robin_ul"; + d = dlsym(NULL, s); + AssertFatal(d, "%s(): no scheduler algo '%s' found\n", __func__, s); + mac[i]->ul_algo = *(default_sched_ul_algo_t *) d; + mac[i]->ul_algo.data = mac[i]->ul_algo.setup(); init_UE_info(&mac[i]->UE_info); init_slice_info(&mac[i]->slice_info); } diff --git a/openair2/LAYER2/MAC/pre_processor.c b/openair2/LAYER2/MAC/pre_processor.c index 436ec2435e..07bbed22c3 100644 --- a/openair2/LAYER2/MAC/pre_processor.c +++ b/openair2/LAYER2/MAC/pre_processor.c @@ -830,17 +830,28 @@ int pp_find_rb_table_index(int approximate) { return p + 1; } -int g_start_ue_ul = -1; -int round_robin_ul(module_id_t Mod_id, - int CC_id, - int frame, - int subframe, - int sched_frame, - int sched_subframe, - UE_list_t *UE_list, - int max_num_ue, - int num_contig_rb, - contig_rbs_t *rbs) { +void *rr_ul_setup(void) { + void *data = malloc(sizeof(int)); + *(int *) data = 0; + AssertFatal(data, "could not allocate data in %s()\n", __func__); + return data; +} +void rr_ul_unset(void **data) { + if (*data) + free(*data); + *data = NULL; +} +int rr_ul_run(module_id_t Mod_id, + int CC_id, + int frame, + int subframe, + int sched_frame, + int sched_subframe, + UE_list_t *UE_list, + int max_num_ue, + int num_contig_rb, + contig_rbs_t *rbs, + void *data) { AssertFatal(num_contig_rb <= 2, "cannot handle more than two contiguous RB regions\n"); UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; const int max_rb = num_contig_rb > 1 ? MAX(rbs[0].length, rbs[1].length) : rbs[0].length; @@ -980,9 +991,10 @@ int round_robin_ul(module_id_t Mod_id, end = la > lb ? 2 : -1; } - if (g_start_ue_ul == -1) - g_start_ue_ul = UE_list->head; - int sUE_id = g_start_ue_ul; + int *start_ue = data; + if (*start_ue == -1) + *start_ue = UE_list->head; + int sUE_id = *start_ue; int rb_idx_given[MAX_MOBILES_PER_ENB]; memset(rb_idx_given, 0, sizeof(rb_idx_given)); @@ -1061,10 +1073,17 @@ int round_robin_ul(module_id_t Mod_id, } /* just start with the next UE next time */ - g_start_ue_ul = next_ue_list_looped(UE_list, g_start_ue_ul); + *start_ue = next_ue_list_looped(UE_list, *start_ue); return rbs[0].length + (num_contig_rb > 1 ? rbs[1].length : 0); } +default_sched_ul_algo_t round_robin_ul = { + .name = "round_robin_ul", + .setup = rr_ul_setup, + .unset = rr_ul_unset, + .run = rr_ul_run, + .data = NULL +}; void ulsch_scheduler_pre_processor(module_id_t Mod_id, int CC_id, @@ -1072,9 +1091,10 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id, sub_frame_t subframeP, int sched_frameP, unsigned char sched_subframeP) { - UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; - const int N_RB_UL = to_prb(RC.mac[Mod_id]->common_channels[CC_id].ul_Bandwidth); - COMMON_channels_t *cc = &RC.mac[Mod_id]->common_channels[CC_id]; + eNB_MAC_INST *mac = RC.mac[Mod_id]; + UE_info_t *UE_info = &mac->UE_info; + const int N_RB_UL = to_prb(mac->common_channels[CC_id].ul_Bandwidth); + COMMON_channels_t *cc = &mac->common_channels[CC_id]; UE_list_t UE_to_sched; UE_to_sched.head = -1; @@ -1131,16 +1151,17 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id, } } - round_robin_ul(Mod_id, - CC_id, - frameP, - subframeP, - sched_frameP, - sched_subframeP, - &UE_to_sched, - 4, // max_num_ue - n_contig, - rbs); + mac->ul_algo.run(Mod_id, + CC_id, + frameP, + subframeP, + sched_frameP, + sched_subframeP, + &UE_to_sched, + 4, // max_num_ue + n_contig, + rbs, + mac->ul_algo.data); // the following block is meant for validation of the pre-processor to check // whether all UE allocations are non-overlapping and is not necessary for @@ -1159,7 +1180,7 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id, continue; print = 1; - uint8_t harq_pid = subframe2harqpid(&RC.mac[Mod_id]->common_channels[CC_id], + uint8_t harq_pid = subframe2harqpid(&mac->common_channels[CC_id], sched_frameP, sched_subframeP); LOG_D(MAC, "%4d.%d UE%d %d RBs (index %d) at start %d, pre MCS %d %s\n", frameP, From da09d63acdc1a4630ef683d2f7eabbb1952e0833 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Tue, 23 Jun 2020 10:27:45 +0200 Subject: [PATCH 494/553] Default pre-processor: efficiently build UE list --- openair2/LAYER2/MAC/pre_processor.c | 27 ++++++++------------------- 1 file changed, 8 insertions(+), 19 deletions(-) diff --git a/openair2/LAYER2/MAC/pre_processor.c b/openair2/LAYER2/MAC/pre_processor.c index 07bbed22c3..d7dfc7816a 100644 --- a/openair2/LAYER2/MAC/pre_processor.c +++ b/openair2/LAYER2/MAC/pre_processor.c @@ -647,12 +647,10 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id, store_dlsch_buffer(Mod_id, CC_id, frameP, subframeP); UE_list_t UE_to_sched; - UE_to_sched.head = -1; for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) UE_to_sched.next[i] = -1; + int *cur = &UE_to_sched.head; - int first = 1; - int last_UE_id = -1; for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { UE_sched_ctrl_t *ue_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; const UE_TEMPLATE *ue_template = &UE_info->UE_template[CC_id][UE_id]; @@ -685,15 +683,10 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id, } /* define UEs to schedule */ - if (first) { - first = 0; - UE_to_sched.head = UE_id; - } else { - UE_to_sched.next[last_UE_id] = UE_id; - } - UE_to_sched.next[UE_id] = -1; - last_UE_id = UE_id; + *cur = UE_id; + cur = &UE_to_sched.next[UE_id]; } + *cur = -1; if (UE_to_sched.head < 0) return; @@ -1097,11 +1090,10 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id, COMMON_channels_t *cc = &mac->common_channels[CC_id]; UE_list_t UE_to_sched; - UE_to_sched.head = -1; for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) UE_to_sched.next[i] = -1; + int *cur = &UE_to_sched.head; - int last_UE_id = -1; for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { UE_TEMPLATE *UE_template = &UE_info->UE_template[CC_id][UE_id]; UE_sched_ctrl_t *ue_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; @@ -1124,13 +1116,10 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id, continue; /* define UEs to schedule */ - if (UE_to_sched.head < 0) - UE_to_sched.head = UE_id; - else - UE_to_sched.next[last_UE_id] = UE_id; - UE_to_sched.next[UE_id] = -1; - last_UE_id = UE_id; + *cur = UE_id; + cur = &UE_to_sched.next[UE_id]; } + *cur = -1; if (UE_to_sched.head < 0) return; From 714a2df097f9792dc356d7033ed31374b09a289f Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Sun, 12 Apr 2020 12:00:43 +0200 Subject: [PATCH 495/553] Remove any slice-related information from OAI --- .../CONTROL_MODULES/MAC/flexran_agent_mac.c | 13 - .../MAC/flexran_agent_mac_internal.c | 28 +- .../flexran_agent_mac_slice_verification.c | 4 +- openair2/ENB_APP/flexran_agent_ran_api.c | 314 ++---------------- openair2/LAYER2/MAC/mac.h | 104 ------ openair2/LAYER2/MAC/mac_proto.h | 2 - openair2/LAYER2/MAC/main.c | 27 -- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 2 - 8 files changed, 39 insertions(+), 455 deletions(-) diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c index 603ff25198..669eb33ea3 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c @@ -49,19 +49,6 @@ struct lfds700_misc_prng_state ps[NUM_MAX_ENB]; struct lfds700_ringbuffer_element *dl_mac_config_array[NUM_MAX_ENB]; struct lfds700_ringbuffer_state ringbuffer_state[NUM_MAX_ENB]; -/* the slice config as kept in the underlying system */ -Protocol__FlexSliceConfig *slice_config[MAX_NUM_SLICES]; -/* a structure that keeps updates which will be reflected in slice_config later */ -Protocol__FlexSliceConfig *sc_update[MAX_NUM_SLICES]; -/* indicates whether sc_update contains new data */ -int perform_slice_config_update_count = 1; -/* queue of incoming new UE<>slice association commands */ -Protocol__FlexUeConfig *ue_slice_assoc_update[MAX_NUM_SLICES]; -int n_ue_slice_assoc_updates = 0; -/* mutex for sc_update: do not receive new config and write it at the same time */ -pthread_mutex_t sc_update_mtx = PTHREAD_MUTEX_INITIALIZER; - - int flexran_agent_mac_stats_reply_ue(mid_t mod_id, Protocol__FlexUeStatsReport **ue_report, int n_ue, diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c index a85cbac543..84a28683b7 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c @@ -33,14 +33,6 @@ #include "flexran_agent_mac_internal.h" #include "flexran_agent_mac_slice_verification.h" -/* from flexran_agent_mac.c */ -extern Protocol__FlexSliceConfig *slice_config[MAX_NUM_SLICES]; -extern Protocol__FlexSliceConfig *sc_update[MAX_NUM_SLICES]; -extern int perform_slice_config_update_count; -extern Protocol__FlexUeConfig *ue_slice_assoc_update[MAX_NUM_SLICES]; -extern int n_ue_slice_assoc_updates; -extern pthread_mutex_t sc_update_mtx; - Protocol__FlexranMessage * flexran_agent_generate_diff_mac_stats_report(Protocol__FlexranMessage *new_message, Protocol__FlexranMessage *old_message) { @@ -1040,12 +1032,12 @@ Protocol__FlexSliceConfig *flexran_agent_create_slice_config(int n_dl, int m_ul) if (!fsc) return NULL; protocol__flex_slice_config__init(fsc); - /* say there are n_dl slices but reserve memory for up to MAX_NUM_SLICES so + /* say there are n_dl slices but reserve memory for up to 10 so * we don't need to reserve again later */ fsc->n_dl = n_dl; - fsc->dl = calloc(MAX_NUM_SLICES, sizeof(Protocol__FlexDlSlice *)); + fsc->dl = calloc(10, sizeof(Protocol__FlexDlSlice *)); if (!fsc->dl) fsc->n_dl = 0; - for (i = 0; i < MAX_NUM_SLICES; i++) { + for (i = 0; i < 10; i++) { fsc->dl[i] = malloc(sizeof(Protocol__FlexDlSlice)); if (!fsc->dl[i]) continue; protocol__flex_dl_slice__init(fsc->dl[i]); @@ -1053,9 +1045,9 @@ Protocol__FlexSliceConfig *flexran_agent_create_slice_config(int n_dl, int m_ul) /* as above */ fsc->n_ul = m_ul; - fsc->ul = calloc(MAX_NUM_SLICES, sizeof(Protocol__FlexUlSlice *)); + fsc->ul = calloc(10, sizeof(Protocol__FlexUlSlice *)); if (!fsc->ul) fsc->n_ul = 0; - for (i = 0; i < MAX_NUM_SLICES; i++) { + for (i = 0; i < 10; i++) { fsc->ul[i] = malloc(sizeof(Protocol__FlexUlSlice)); if (!fsc->ul[i]) continue; protocol__flex_ul_slice__init(fsc->ul[i]); @@ -1401,8 +1393,8 @@ Protocol__FlexDlSlice *create_new_dl_slice(mid_t mod_id, int id) mod_id, id); Protocol__FlexDlSlice *to = sc_update[mod_id]->dl[sc_update[mod_id]->n_dl]; sc_update[mod_id]->n_dl++; - AssertFatal(sc_update[mod_id]->n_dl <= MAX_NUM_SLICES, - "cannot create more than MAX_NUM_SLICES\n"); + AssertFatal(sc_update[mod_id]->n_dl <= 10, + "cannot create more than 10\n"); to->id = id; return to; } @@ -1468,8 +1460,8 @@ Protocol__FlexUlSlice *create_new_ul_slice(mid_t mod_id, int id) mod_id, id); Protocol__FlexUlSlice *to = sc_update[mod_id]->ul[sc_update[mod_id]->n_ul]; sc_update[mod_id]->n_ul++; - AssertFatal(sc_update[mod_id]->n_ul <= MAX_NUM_SLICES, - "cannot create more than MAX_NUM_SLICES\n"); + AssertFatal(sc_update[mod_id]->n_ul <= 10, + "cannot create more than 10\n"); to->id = id; return to; } @@ -1698,7 +1690,7 @@ int apply_new_slice_ul_config(mid_t mod_id, Protocol__FlexUlSlice *oldc, Protoco void prepare_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig *ue_config) { - if (n_ue_slice_assoc_updates == MAX_NUM_SLICES) { + if (n_ue_slice_assoc_updates == 10) { LOG_E(FLEXRAN_AGENT, "[%d] can not handle flex_ue_config message, buffer is full; try again later\n", mod_id); diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.c index 67329e91be..f7f60541f5 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.c +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.c @@ -132,7 +132,7 @@ int flexran_verify_group_dl_slices(mid_t mod_id, Protocol__FlexDlSlice **existin /* else "only" an update */ } - if (n < 1 || n > MAX_NUM_SLICES) { + if (n < 1 || n > 10) { LOG_E(FLEXRAN_AGENT, "[%d] Illegal number of resulting DL slices (%d -> %d)\n", mod_id, n_ex, n); return 0; @@ -253,7 +253,7 @@ int flexran_verify_group_ul_slices(mid_t mod_id, Protocol__FlexUlSlice **existin /* else "only" an update */ } - if (n < 1 || n > MAX_NUM_SLICES) { + if (n < 1 || n > 10) { LOG_E(FLEXRAN_AGENT, "[%d] Illegal number of resulting UL slices (%d -> %d)\n", mod_id, n_ex, n); return 0; diff --git a/openair2/ENB_APP/flexran_agent_ran_api.c b/openair2/ENB_APP/flexran_agent_ran_api.c index 0fcc51782e..291c4dc7d8 100644 --- a/openair2/ENB_APP/flexran_agent_ran_api.c +++ b/openair2/ENB_APP/flexran_agent_ran_api.c @@ -3015,469 +3015,209 @@ uint32_t flexran_get_rrc_enb_ue_s1ap_id(mid_t mod_id, rnti_t rnti) /**************************** SLICING ****************************/ int flexran_get_ue_dl_slice_id(mid_t mod_id, mid_t ue_id) { if (!mac_is_present(mod_id)) return -1; - - int slice_idx = 0; //RC.mac[mod_id]->UE_info.assoc_dl_slice_idx[ue_id]; - - if (slice_idx >= 0 && slice_idx < RC.mac[mod_id]->slice_info.n_dl) - return RC.mac[mod_id]->slice_info.dl[slice_idx].id; - return 0; } void flexran_set_ue_dl_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx) { if (!mac_is_present(mod_id)) return; - - if (flexran_get_mac_ue_crnti(mod_id, ue_id) == NOT_A_RNTI) return; - - if (!flexran_dl_slice_exists(mod_id, slice_idx)) return; - - //RC.mac[mod_id]->UE_info.assoc_dl_slice_idx[ue_id] = slice_idx; } int flexran_get_ue_ul_slice_id(mid_t mod_id, mid_t ue_id) { if (!mac_is_present(mod_id)) return -1; - - int slice_idx = 0; //RC.mac[mod_id]->UE_info.assoc_ul_slice_idx[ue_id]; - - if (slice_idx >= 0 && slice_idx < RC.mac[mod_id]->slice_info.n_ul) - return RC.mac[mod_id]->slice_info.ul[slice_idx].id; - return 0; } void flexran_set_ue_ul_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx) { if (!mac_is_present(mod_id)) return; - - if (flexran_get_mac_ue_crnti(mod_id, ue_id) == NOT_A_RNTI) return; - - if (!flexran_ul_slice_exists(mod_id, slice_idx)) return; - - //RC.mac[mod_id]->UE_info.assoc_ul_slice_idx[ue_id] = slice_idx; } int flexran_dl_slice_exists(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - return slice_idx >= 0 && slice_idx < RC.mac[mod_id]->slice_info.n_dl; + return 0; } int flexran_create_dl_slice(mid_t mod_id, slice_id_t slice_id) { if (!mac_is_present(mod_id)) return -1; - - int newidx = RC.mac[mod_id]->slice_info.n_dl; - - if (newidx >= MAX_NUM_SLICES) return -1; - - ++RC.mac[mod_id]->slice_info.n_dl; - flexran_set_dl_slice_id(mod_id, newidx, slice_id); - return newidx; + return -1; } int flexran_find_dl_slice(mid_t mod_id, slice_id_t slice_id) { if (!mac_is_present(mod_id)) return -1; - - slice_info_t *sli = &RC.mac[mod_id]->slice_info; - int n = sli->n_dl; - - for (int i = 0; i < n; i++) { - if (sli->dl[i].id == slice_id) return i; - } - return -1; } int flexran_remove_dl_slice(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - slice_info_t *sli = &RC.mac[mod_id]->slice_info; - - if (sli->n_dl <= 1) return -1; - - if (sli->dl[slice_idx].sched_name) free(sli->dl[slice_idx].sched_name); - - --sli->n_dl; - - /* move last element to the position of the removed one */ - if (slice_idx != sli->n_dl) - memcpy(&sli->dl[slice_idx], &sli->dl[sli->n_dl], sizeof(sli->dl[sli->n_dl])); - - memset(&sli->dl[sli->n_dl], 0, sizeof(sli->dl[sli->n_dl])); - /* all UEs that have been in the old slice are put into slice index 0 */ - //int *assoc_list = RC.mac[mod_id]->UE_info.assoc_dl_slice_idx; - - //for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) { - // if (assoc_list[i] == slice_idx) - // assoc_list[i] = 0; - //} - - return 1; + return -1; } int flexran_get_num_dl_slices(mid_t mod_id) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.n_dl; + return 0; } int flexran_get_intraslice_sharing_active(mid_t mod_id) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.intraslice_share_active; + return -1; } void flexran_set_intraslice_sharing_active(mid_t mod_id, int intraslice_active) { if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.intraslice_share_active = intraslice_active; } int flexran_get_interslice_sharing_active(mid_t mod_id) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.interslice_share_active; + return -1; } void flexran_set_interslice_sharing_active(mid_t mod_id, int interslice_active) { if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.interslice_share_active = interslice_active; } slice_id_t flexran_get_dl_slice_id(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.dl[slice_idx].id; + return -1; } void flexran_set_dl_slice_id(mid_t mod_id, int slice_idx, slice_id_t slice_id) { if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.dl[slice_idx].id = slice_id; } int flexran_get_dl_slice_percentage(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.dl[slice_idx].pct * 100.0f; + return -1; } void flexran_set_dl_slice_percentage(mid_t mod_id, int slice_idx, int percentage) { if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.dl[slice_idx].pct = percentage / 100.0f; } int flexran_get_dl_slice_isolation(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.dl[slice_idx].isol; + return -1; } void flexran_set_dl_slice_isolation(mid_t mod_id, int slice_idx, int is_isolated) { if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.dl[slice_idx].isol = is_isolated; } int flexran_get_dl_slice_priority(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.dl[slice_idx].prio; + return -1; } void flexran_set_dl_slice_priority(mid_t mod_id, int slice_idx, int priority) { if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.dl[slice_idx].prio = priority; } int flexran_get_dl_slice_position_low(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.dl[slice_idx].pos_low; + return -1; } void flexran_set_dl_slice_position_low(mid_t mod_id, int slice_idx, int poslow) { if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.dl[slice_idx].pos_low = poslow; } int flexran_get_dl_slice_position_high(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.dl[slice_idx].pos_high; + return -1; } void flexran_set_dl_slice_position_high(mid_t mod_id, int slice_idx, int poshigh) { if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.dl[slice_idx].pos_high = poshigh; } int flexran_get_dl_slice_maxmcs(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.dl[slice_idx].maxmcs; + return -1; } void flexran_set_dl_slice_maxmcs(mid_t mod_id, int slice_idx, int maxmcs) { if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.dl[slice_idx].maxmcs = maxmcs; } int flexran_get_dl_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexDlSorting **sorting_list) { if (!mac_is_present(mod_id)) return -1; - - if (!(*sorting_list)) { - *sorting_list = calloc(CR_NUM, sizeof(Protocol__FlexDlSorting)); - - if (!(*sorting_list)) return -1; - } - - uint32_t policy = RC.mac[mod_id]->slice_info.dl[slice_idx].sorting; - - for (int i = 0; i < CR_NUM; i++) { - switch (policy >> 4 * (CR_NUM - 1 - i) & 0xF) { - case CR_ROUND: - (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_ROUND; - break; - - case CR_SRB12: - (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_SRB12; - break; - - case CR_HOL: - (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_HOL; - break; - - case CR_LC: - (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_LC; - break; - - case CR_CQI: - (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_CQI; - break; - - case CR_LCP: - (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_LCP; - break; - - default: - /* this should not happen, but a "default" */ - (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_ROUND; - break; - } - } - - return CR_NUM; + return -1; } void flexran_set_dl_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexDlSorting *sorting_list, int n) { if (!mac_is_present(mod_id)) return; - - uint32_t policy = 0; - - for (int i = 0; i < n && i < CR_NUM; i++) { - switch (sorting_list[i]) { - case PROTOCOL__FLEX_DL_SORTING__CR_ROUND: - policy = policy << 4 | CR_ROUND; - break; - - case PROTOCOL__FLEX_DL_SORTING__CR_SRB12: - policy = policy << 4 | CR_SRB12; - break; - - case PROTOCOL__FLEX_DL_SORTING__CR_HOL: - policy = policy << 4 | CR_HOL; - break; - - case PROTOCOL__FLEX_DL_SORTING__CR_LC: - policy = policy << 4 | CR_LC; - break; - - case PROTOCOL__FLEX_DL_SORTING__CR_CQI: - policy = policy << 4 | CR_CQI; - break; - - case PROTOCOL__FLEX_DL_SORTING__CR_LCP: - policy = policy << 4 | CR_LCP; - break; - - default: /* suppresses warnings */ - policy = policy << 4 | CR_ROUND; - break; - } - } - - /* fill up with 0 == CR_ROUND */ - if (CR_NUM > n) policy = policy << 4 * (CR_NUM - n); - - RC.mac[mod_id]->slice_info.dl[slice_idx].sorting = policy; } Protocol__FlexDlAccountingPolicy flexran_get_dl_slice_accounting_policy(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_FAIR; - - switch (RC.mac[mod_id]->slice_info.dl[slice_idx].accounting) { - case POL_FAIR: - return PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_FAIR; - - case POL_GREEDY: - return PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_GREEDY; - - default: - return PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_FAIR; - } + return PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_FAIR; } void flexran_set_dl_slice_accounting_policy(mid_t mod_id, int slice_idx, Protocol__FlexDlAccountingPolicy accounting) { if (!mac_is_present(mod_id)) return; - - switch (accounting) { - case PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_FAIR: - RC.mac[mod_id]->slice_info.dl[slice_idx].accounting = POL_FAIR; - return; - - case PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_GREEDY: - RC.mac[mod_id]->slice_info.dl[slice_idx].accounting = POL_GREEDY; - return; - - default: - RC.mac[mod_id]->slice_info.dl[slice_idx].accounting = POL_FAIR; - return; - } } char *flexran_get_dl_slice_scheduler(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return NULL; - - return RC.mac[mod_id]->slice_info.dl[slice_idx].sched_name; + return NULL; } int flexran_set_dl_slice_scheduler(mid_t mod_id, int slice_idx, char *name) { if (!mac_is_present(mod_id)) return 0; - - if (RC.mac[mod_id]->slice_info.dl[slice_idx].sched_name) - free(RC.mac[mod_id]->slice_info.dl[slice_idx].sched_name); - - RC.mac[mod_id]->slice_info.dl[slice_idx].sched_name = strdup(name); - RC.mac[mod_id]->slice_info.dl[slice_idx].sched_cb = dlsym(NULL, name); - return RC.mac[mod_id]->slice_info.dl[slice_idx].sched_cb != NULL; + return 0; } int flexran_create_ul_slice(mid_t mod_id, slice_id_t slice_id) { if (!mac_is_present(mod_id)) return -1; - - int newidx = RC.mac[mod_id]->slice_info.n_ul; - - if (newidx >= MAX_NUM_SLICES) return -1; - - ++RC.mac[mod_id]->slice_info.n_ul; - flexran_set_ul_slice_id(mod_id, newidx, slice_id); - return newidx; + return -1; } int flexran_find_ul_slice(mid_t mod_id, slice_id_t slice_id) { if (!mac_is_present(mod_id)) return -1; - - slice_info_t *sli = &RC.mac[mod_id]->slice_info; - int n = sli->n_ul; - - for (int i = 0; i < n; i++) { - if (sli->ul[i].id == slice_id) return i; - } - return -1; } int flexran_remove_ul_slice(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - slice_info_t *sli = &RC.mac[mod_id]->slice_info; - - if (sli->n_ul <= 1) return -1; - - if (sli->ul[slice_idx].sched_name) free(sli->ul[slice_idx].sched_name); - - --sli->n_ul; - - /* move last element to the position of the removed one */ - if (slice_idx != sli->n_ul) - memcpy(&sli->ul[slice_idx], &sli->ul[sli->n_ul], sizeof(sli->ul[sli->n_ul])); - - memset(&sli->ul[sli->n_ul], 0, sizeof(sli->ul[sli->n_ul])); - /* all UEs that have been in the old slice are put into slice index 0 */ - //int *assoc_list = RC.mac[mod_id]->UE_info.assoc_ul_slice_idx; - - //for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) { - // if (assoc_list[i] == slice_idx) - // assoc_list[i] = 0; - //} - - return sli->n_ul; + return -1; } int flexran_get_num_ul_slices(mid_t mod_id) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.n_ul; + return 0; } int flexran_ul_slice_exists(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - return slice_idx >= 0 && slice_idx < RC.mac[mod_id]->slice_info.n_ul; + return 0; } slice_id_t flexran_get_ul_slice_id(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.ul[slice_idx].id; + return -1; } void flexran_set_ul_slice_id(mid_t mod_id, int slice_idx, slice_id_t slice_id) { if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.ul[slice_idx].id = slice_id; } int flexran_get_ul_slice_percentage(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.ul[slice_idx].pct * 100.0f; + return -1; } void flexran_set_ul_slice_percentage(mid_t mod_id, int slice_idx, int percentage) { if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.ul[slice_idx].pct = percentage / 100.0f; } int flexran_get_ul_slice_first_rb(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.ul[slice_idx].first_rb; + return -1; } void flexran_set_ul_slice_first_rb(mid_t mod_id, int slice_idx, int first_rb) { if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.ul[slice_idx].first_rb = first_rb; } int flexran_get_ul_slice_maxmcs(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; - - return RC.mac[mod_id]->slice_info.ul[slice_idx].maxmcs; + return -1; } void flexran_set_ul_slice_maxmcs(mid_t mod_id, int slice_idx, int maxmcs) { if (!mac_is_present(mod_id)) return; - - RC.mac[mod_id]->slice_info.ul[slice_idx].maxmcs = maxmcs; } char *flexran_get_ul_slice_scheduler(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return NULL; - - return RC.mac[mod_id]->slice_info.ul[slice_idx].sched_name; + return ""; } int flexran_set_ul_slice_scheduler(mid_t mod_id, int slice_idx, char *name) { if (!mac_is_present(mod_id)) return 0; - - if (RC.mac[mod_id]->slice_info.ul[slice_idx].sched_name) - free(RC.mac[mod_id]->slice_info.ul[slice_idx].sched_name); - - RC.mac[mod_id]->slice_info.ul[slice_idx].sched_name = strdup(name); - RC.mac[mod_id]->slice_info.ul[slice_idx].sched_cb = dlsym(NULL, name); - return RC.mac[mod_id]->slice_info.ul[slice_idx].sched_cb != NULL; + return 0; } /************************** S1AP **************************/ diff --git a/openair2/LAYER2/MAC/mac.h b/openair2/LAYER2/MAC/mac.h index 09585fae55..8349d84d48 100644 --- a/openair2/LAYER2/MAC/mac.h +++ b/openair2/LAYER2/MAC/mac.h @@ -155,9 +155,6 @@ /*!\brief minimum MAC data needed for transmitting 1 min RLC PDU size + 1 byte MAC subHeader */ #define MIN_MAC_HDR_RLC_SIZE (1 + MIN_RLC_PDU_SIZE) -/*!\brief maximum number of slices / groups */ -#define MAX_NUM_SLICES 10 - #define U_PLANE_INACTIVITY_VALUE 0 /* defined 10ms order (zero means infinity) */ @@ -1150,9 +1147,6 @@ typedef struct { UE_list_t list; int num_UEs; boolean_t active[MAX_MOBILES_PER_ENB]; - - /// Sorting criteria for the UE list in the MAC preprocessor - uint16_t sorting_criteria[MAX_NUM_SLICES][CR_NUM]; } UE_info_t; /*! \brief deleting control information*/ @@ -1171,101 +1165,6 @@ typedef struct { int tail_freelist; ///the tail position of the delete list } UE_free_list_t; -/** - * slice specific scheduler for the DL - */ -typedef void (*slice_scheduler_dl)(module_id_t mod_id, - int slice_idx, - frame_t frame, - sub_frame_t subframe, - int *mbsfn_flag); - -typedef struct { - slice_id_t id; - - /// RB share for each slice - float pct; - - /// whether this slice is isolated from the others - int isol; - - int prio; - - /// Frequency ranges for slice positioning - int pos_low; - int pos_high; - - // max mcs for each slice - int maxmcs; - - /// criteria for sorting policies of the slices - uint32_t sorting; - - /// Accounting policy (just greedy(1) or fair(0) setting for now) - int accounting; - - /// name of available scheduler - char *sched_name; - - /// pointer to the slice specific scheduler in DL - slice_scheduler_dl sched_cb; - -} slice_sched_conf_dl_t; - -typedef void (*slice_scheduler_ul)(module_id_t mod_id, - int slice_idx, - frame_t frame, - sub_frame_t subframe, - unsigned char sched_subframe, - uint16_t *first_rb); - -typedef struct { - slice_id_t id; - - /// RB share for each slice - float pct; - - // MAX MCS for each slice - int maxmcs; - - /// criteria for sorting policies of the slices - uint32_t sorting; - - /// starting RB (RB offset) of UL scheduling - int first_rb; - - /// name of available scheduler - char *sched_name; - - /// pointer to the slice specific scheduler in UL - slice_scheduler_ul sched_cb; - -} slice_sched_conf_ul_t; - - -typedef struct { - /// counter used to indicate when all slices have pre-allocated UEs - //int slice_counter; - - /// indicates whether remaining RBs after first intra-slice allocation will - /// be allocated to UEs of the same slice - int intraslice_share_active; - /// indicates whether remaining RBs after slice allocation will be - /// allocated to UEs of another slice. Isolated slices will be ignored - int interslice_share_active; - - /// number of active DL slices - int n_dl; - slice_sched_conf_dl_t dl[MAX_NUM_SLICES]; - - /// number of active UL slices - int n_ul; - slice_sched_conf_ul_t ul[MAX_NUM_SLICES]; - - /// common rb allocation list between slices - uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX]; -} slice_info_t; - /** * describes contiguous RBs */ @@ -1421,9 +1320,6 @@ typedef struct eNB_MAC_INST_s { uint32_t ul_handle; UE_info_t UE_info; - /// slice-related configuration - slice_info_t slice_info; - ///subband bitmap configuration SBMAP_CONF sbmap_conf; /// CCE table used to build DCI scheduling information diff --git a/openair2/LAYER2/MAC/mac_proto.h b/openair2/LAYER2/MAC/mac_proto.h index 2cb86c25af..61251ef088 100644 --- a/openair2/LAYER2/MAC/mac_proto.h +++ b/openair2/LAYER2/MAC/mac_proto.h @@ -187,8 +187,6 @@ void add_msg3(module_id_t module_idP, int CC_id, RA_t *ra, frame_t frameP, void init_UE_info(UE_info_t *UE_info); -void init_slice_info(slice_info_t *sli); - int mac_top_init(int eMBMS_active, char *uecap_xer, uint8_t cba_group_active, uint8_t HO_active); diff --git a/openair2/LAYER2/MAC/main.c b/openair2/LAYER2/MAC/main.c index 294eb12159..35b5136889 100644 --- a/openair2/LAYER2/MAC/main.c +++ b/openair2/LAYER2/MAC/main.c @@ -57,32 +57,6 @@ void init_UE_info(UE_info_t *UE_info) memset(UE_info->active, 0, sizeof(UE_info->active)); } -void init_slice_info(slice_info_t *sli) -{ - sli->intraslice_share_active = 1; - sli->interslice_share_active = 1; - - sli->n_dl = 1; - memset(sli->dl, 0, sizeof(slice_sched_conf_dl_t) * MAX_NUM_SLICES); - sli->dl[0].pct = 1.0; - sli->dl[0].prio = 10; - sli->dl[0].pos_high = N_RBG_MAX; - sli->dl[0].maxmcs = 28; - sli->dl[0].sorting = 0x012345; - sli->dl[0].sched_name = "schedule_ue_spec"; - sli->dl[0].sched_cb = dlsym(NULL, sli->dl[0].sched_name); - AssertFatal(sli->dl[0].sched_cb, "DLSCH scheduler callback is NULL\n"); - - sli->n_ul = 1; - memset(sli->ul, 0, sizeof(slice_sched_conf_ul_t) * MAX_NUM_SLICES); - sli->ul[0].pct = 1.0; - sli->ul[0].maxmcs = 20; - sli->ul[0].sorting = 0x0123; - sli->ul[0].sched_name = "schedule_ulsch_rnti"; - sli->ul[0].sched_cb = dlsym(NULL, sli->ul[0].sched_name); - AssertFatal(sli->ul[0].sched_cb, "ULSCH scheduler callback is NULL\n"); -} - void mac_top_init_eNB(void) { module_id_t i, j; @@ -139,7 +113,6 @@ void mac_top_init_eNB(void) mac[i]->ul_algo = *(default_sched_ul_algo_t *) d; mac[i]->ul_algo.data = mac[i]->ul_algo.setup(); init_UE_info(&mac[i]->UE_info); - init_slice_info(&mac[i]->slice_info); } RC.mac = mac; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index fc2a2e18cf..b73b074c37 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -68,8 +68,6 @@ extern RAN_CONTEXT_t RC; -extern int n_active_slices; - // Note the 2 scs values in the table names represent resp. scs_common and pdcch_scs /// LUT for the number of symbols in the coreset indexed by coreset index (4 MSB rmsi_pdcch_config) uint8_t nr_coreset_nsymb_pdcch_type_0_scs_15_15[15] = {2,2,2,3,3,3,1,1,2,2,3,3,1,2,3}; From a74f4c1238b03a31fafba5d1552f0b08ac184a3d Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Tue, 14 Apr 2020 16:17:56 +0200 Subject: [PATCH 496/553] Delete old protobuf slice types flex_slice_{dl,ul} --- .../CONTROL_MODULES/MAC/flexran_agent_mac.c | 206 +----- .../MAC/flexran_agent_mac_internal.c | 666 +----------------- .../MAC/flexran_agent_mac_internal.h | 20 - .../flexran_agent_mac_slice_verification.c | 343 --------- .../flexran_agent_mac_slice_verification.h | 6 - .../ENB_APP/MESSAGES/V2/config_common.proto | 77 -- .../ENB_APP/MESSAGES/V2/config_messages.proto | 8 - openair2/ENB_APP/flexran_agent_common.c | 20 +- openair2/ENB_APP/flexran_agent_ran_api.c | 178 +---- openair2/ENB_APP/flexran_agent_ran_api.h | 149 +--- 10 files changed, 47 insertions(+), 1626 deletions(-) diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c index 669eb33ea3..4800fccea9 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c @@ -1468,10 +1468,12 @@ void flexran_agent_fill_mac_ue_config(mid_t mod_id, mid_t ue_id, ue_conf->rnti = flexran_get_mac_ue_crnti(mod_id, ue_id); ue_conf->has_rnti = 1; - ue_conf->dl_slice_id = flexran_get_ue_dl_slice_id(mod_id, ue_id); - ue_conf->has_dl_slice_id = 1; - ue_conf->ul_slice_id = flexran_get_ue_ul_slice_id(mod_id, ue_id); - ue_conf->has_ul_slice_id = 1; + int dl_id = flexran_get_ue_dl_slice_id(mod_id, ue_id); + ue_conf->dl_slice_id = dl_id; + ue_conf->has_dl_slice_id = dl_id >= 0; + int ul_id = flexran_get_ue_ul_slice_id(mod_id, ue_id); + ue_conf->ul_slice_id = ul_id; + ue_conf->has_ul_slice_id = ul_id >= 0; ue_conf->ue_aggregated_max_bitrate_ul = flexran_get_ue_aggregated_max_bitrate_ul(mod_id, ue_id); ue_conf->has_ue_aggregated_max_bitrate_ul = 1; @@ -1576,149 +1578,24 @@ void flexran_create_config_structures(mid_t mod_id) sc_update[mod_id] = flexran_agent_create_slice_config(n_dl, m_ul); if (!slice_config[mod_id] || !sc_update[mod_id]) return; - flexran_agent_read_slice_config(mod_id, slice_config[mod_id]); - flexran_agent_read_slice_config(mod_id, sc_update[mod_id]); + //flexran_agent_read_slice_config(mod_id, slice_config[mod_id]); + //flexran_agent_read_slice_config(mod_id, sc_update[mod_id]); for (i = 0; i < n_dl; i++) { - flexran_agent_read_slice_dl_config(mod_id, i, slice_config[mod_id]->dl[i]); - flexran_agent_read_slice_dl_config(mod_id, i, sc_update[mod_id]->dl[i]); + //flexran_agent_read_slice_dl_config(mod_id, i, slice_config[mod_id]->dl[i]); + //flexran_agent_read_slice_dl_config(mod_id, i, sc_update[mod_id]->dl[i]); } for (i = 0; i < m_ul; i++) { - flexran_agent_read_slice_ul_config(mod_id, i, slice_config[mod_id]->ul[i]); - flexran_agent_read_slice_ul_config(mod_id, i, sc_update[mod_id]->ul[i]); + //flexran_agent_read_slice_ul_config(mod_id, i, slice_config[mod_id]->ul[i]); + //flexran_agent_read_slice_ul_config(mod_id, i, sc_update[mod_id]->ul[i]); } } void flexran_check_and_remove_slices(mid_t mod_id) { - Protocol__FlexDlSlice **dl = sc_update[mod_id]->dl; - Protocol__FlexDlSlice **dlreal = slice_config[mod_id]->dl; - int i = 0; - while (i < sc_update[mod_id]->n_dl) { - /* remove slices whose percentage is zero */ - if (dl[i]->percentage > 0) { - ++i; - continue; - } - if (flexran_remove_dl_slice(mod_id, i) < 1) { - LOG_W(FLEXRAN_AGENT, "[%d] can not remove slice index %d ID %d\n", - mod_id, i, dl[i]->id); - ++i; - continue; - } - LOG_I(FLEXRAN_AGENT, "[%d] removed slice index %d ID %d\n", - mod_id, i, dl[i]->id); - if (dl[i]->n_sorting > 0) free(dl[i]->sorting); - free(dl[i]->scheduler_name); - if (dlreal[i]->n_sorting > 0) { - dlreal[i]->n_sorting = 0; - free(dlreal[i]->sorting); - } - free(dlreal[i]->scheduler_name); - --sc_update[mod_id]->n_dl; - --slice_config[mod_id]->n_dl; - const size_t last = sc_update[mod_id]->n_dl; - /* we need to memcpy the higher slice to the position we just deleted */ - memcpy(dl[i], dl[last], sizeof(*dl[last])); - memset(dl[last], 0, sizeof(*dl[last])); - memcpy(dlreal[i], dlreal[last], sizeof(*dlreal[last])); - memset(dlreal[last], 0, sizeof(*dlreal[last])); - /* dont increase i but recheck the slice which has been copied to here */ - } - Protocol__FlexUlSlice **ul = sc_update[mod_id]->ul; - Protocol__FlexUlSlice **ulreal = slice_config[mod_id]->ul; - i = 0; - while (i < sc_update[mod_id]->n_ul) { - if (ul[i]->percentage > 0) { - ++i; - continue; - } - if (flexran_remove_ul_slice(mod_id, i) < 1) { - LOG_W(FLEXRAN_AGENT, "[%d] can not remove slice index %d ID %d\n", - mod_id, i, ul[i]->id); - ++i; - continue; - } - LOG_I(FLEXRAN_AGENT, "[%d] removed slice index %d ID %d\n", - mod_id, i, ul[i]->id); - free(ul[i]->scheduler_name); - free(ulreal[i]->scheduler_name); - --sc_update[mod_id]->n_ul; - --slice_config[mod_id]->n_ul; - const size_t last = sc_update[mod_id]->n_ul; - /* see DL remarks */ - memcpy(ul[i], ul[last], sizeof(*ul[last])); - memset(ul[last], 0, sizeof(*ul[last])); - memcpy(ulreal[i], ulreal[last], sizeof(*ulreal[last])); - memset(ulreal[last], 0, sizeof(*ulreal[last])); - /* dont increase i but recheck the slice which has been copied to here */ - } } void flexran_agent_slice_update(mid_t mod_id) { - int i; - int changes = 0; - - if (perform_slice_config_update_count <= 0) return; - perform_slice_config_update_count--; - - pthread_mutex_lock(&sc_update_mtx); - - if (!slice_config[mod_id]) { - /* if the configuration does not exist for agent, create from eNB structure - * and exit */ - flexran_create_config_structures(mod_id); - pthread_mutex_unlock(&sc_update_mtx); - return; - } - - /********* read existing config *********/ - /* simply update slice_config all the time and write new config - * (apply_new_slice_dl_config() only updates if changes are necessary) */ - slice_config[mod_id]->n_dl = flexran_get_num_dl_slices(mod_id); - slice_config[mod_id]->n_ul = flexran_get_num_ul_slices(mod_id); - for (i = 0; i < slice_config[mod_id]->n_dl; i++) { - flexran_agent_read_slice_dl_config(mod_id, i, slice_config[mod_id]->dl[i]); - } - for (i = 0; i < slice_config[mod_id]->n_ul; i++) { - flexran_agent_read_slice_ul_config(mod_id, i, slice_config[mod_id]->ul[i]); - } - - /********* write new config *********/ - /* check for removal (sc_update[X]->dl[Y].percentage == 0) - * and update sc_update & slice_config accordingly */ - flexran_check_and_remove_slices(mod_id); - - /* create new DL and UL slices if necessary */ - for (i = slice_config[mod_id]->n_dl; i < sc_update[mod_id]->n_dl; i++) { - flexran_create_dl_slice(mod_id, sc_update[mod_id]->dl[i]->id); - } - for (i = slice_config[mod_id]->n_ul; i < sc_update[mod_id]->n_ul; i++) { - flexran_create_ul_slice(mod_id, sc_update[mod_id]->ul[i]->id); - } - slice_config[mod_id]->n_dl = flexran_get_num_dl_slices(mod_id); - slice_config[mod_id]->n_ul = flexran_get_num_ul_slices(mod_id); - changes += apply_new_slice_config(mod_id, slice_config[mod_id], sc_update[mod_id]); - for (i = 0; i < slice_config[mod_id]->n_dl; i++) { - changes += apply_new_slice_dl_config(mod_id, - slice_config[mod_id]->dl[i], - sc_update[mod_id]->dl[i]); - flexran_agent_read_slice_dl_config(mod_id, i, slice_config[mod_id]->dl[i]); - } - for (i = 0; i < slice_config[mod_id]->n_ul; i++) { - changes += apply_new_slice_ul_config(mod_id, - slice_config[mod_id]->ul[i], - sc_update[mod_id]->ul[i]); - flexran_agent_read_slice_ul_config(mod_id, i, slice_config[mod_id]->ul[i]); - } - flexran_agent_read_slice_config(mod_id, slice_config[mod_id]); - if (n_ue_slice_assoc_updates > 0) { - changes += apply_ue_slice_assoc_update(mod_id); - } - if (changes > 0) - LOG_I(FLEXRAN_AGENT, "[%d] slice configuration: applied %d changes\n", mod_id, changes); - - pthread_mutex_unlock(&sc_update_mtx); } Protocol__FlexSliceConfig *flexran_agent_get_slice_config(mid_t mod_id) @@ -1727,69 +1604,10 @@ Protocol__FlexSliceConfig *flexran_agent_get_slice_config(mid_t mod_id) Protocol__FlexSliceConfig *config = NULL; pthread_mutex_lock(&sc_update_mtx); - config = flexran_agent_create_slice_config(slice_config[mod_id]->n_dl, - slice_config[mod_id]->n_ul); if (!config) { pthread_mutex_unlock(&sc_update_mtx); return NULL; } - config->has_intraslice_share_active = 1; - config->intraslice_share_active = slice_config[mod_id]->intraslice_share_active; - config->has_interslice_share_active = 1; - config->interslice_share_active = slice_config[mod_id]->interslice_share_active; - for (int i = 0; i < slice_config[mod_id]->n_dl; ++i) { - if (!config->dl[i]) continue; - config->dl[i]->has_id = 1; - config->dl[i]->id = slice_config[mod_id]->dl[i]->id; - config->dl[i]->has_label = 1; - config->dl[i]->label = slice_config[mod_id]->dl[i]->label; - config->dl[i]->has_percentage = 1; - config->dl[i]->percentage = slice_config[mod_id]->dl[i]->percentage; - config->dl[i]->has_isolation = 1; - config->dl[i]->isolation = slice_config[mod_id]->dl[i]->isolation; - config->dl[i]->has_priority = 1; - config->dl[i]->priority = slice_config[mod_id]->dl[i]->priority; - config->dl[i]->has_position_low = 1; - config->dl[i]->position_low = slice_config[mod_id]->dl[i]->position_low; - config->dl[i]->has_position_high = 1; - config->dl[i]->position_high = slice_config[mod_id]->dl[i]->position_high; - config->dl[i]->has_maxmcs = 1; - config->dl[i]->maxmcs = slice_config[mod_id]->dl[i]->maxmcs; - config->dl[i]->n_sorting = slice_config[mod_id]->dl[i]->n_sorting; - config->dl[i]->sorting = calloc(config->dl[i]->n_sorting, sizeof(Protocol__FlexDlSorting)); - if (!config->dl[i]->sorting) config->dl[i]->n_sorting = 0; - for (int j = 0; j < config->dl[i]->n_sorting; ++j) - config->dl[i]->sorting[j] = slice_config[mod_id]->dl[i]->sorting[j]; - config->dl[i]->has_accounting = 1; - config->dl[i]->accounting = slice_config[mod_id]->dl[i]->accounting; - config->dl[i]->scheduler_name = strdup(slice_config[mod_id]->dl[i]->scheduler_name); - } - for (int i = 0; i < slice_config[mod_id]->n_ul; ++i) { - if (!config->ul[i]) continue; - config->ul[i]->has_id = 1; - config->ul[i]->id = slice_config[mod_id]->ul[i]->id; - config->ul[i]->has_label = 1; - config->ul[i]->label = slice_config[mod_id]->ul[i]->label; - config->ul[i]->has_percentage = 1; - config->ul[i]->percentage = slice_config[mod_id]->ul[i]->percentage; - config->ul[i]->has_isolation = 1; - config->ul[i]->isolation = slice_config[mod_id]->ul[i]->isolation; - config->ul[i]->has_priority = 1; - config->ul[i]->priority = slice_config[mod_id]->ul[i]->priority; - config->ul[i]->has_first_rb = 1; - config->ul[i]->first_rb = slice_config[mod_id]->ul[i]->first_rb; - config->ul[i]->has_maxmcs = 1; - config->ul[i]->maxmcs = slice_config[mod_id]->ul[i]->maxmcs; - config->ul[i]->n_sorting = slice_config[mod_id]->ul[i]->n_sorting; - config->ul[i]->sorting = calloc(config->ul[i]->n_sorting, sizeof(Protocol__FlexUlSorting)); - if (!config->ul[i]->sorting) config->ul[i]->n_sorting = 0; - for (int j = 0; j < config->ul[i]->n_sorting; ++j) - config->ul[i]->sorting[j] = slice_config[mod_id]->ul[i]->sorting[j]; - config->ul[i]->has_accounting = 1; - config->ul[i]->accounting = slice_config[mod_id]->ul[i]->accounting; - config->ul[i]->scheduler_name = strdup(slice_config[mod_id]->ul[i]->scheduler_name); - } - pthread_mutex_unlock(&sc_update_mtx); return config; } diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c index 84a28683b7..4c80c561ee 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c @@ -1027,666 +1027,18 @@ int load_dl_scheduler_function(mid_t mod_id, const char *function_name) { Protocol__FlexSliceConfig *flexran_agent_create_slice_config(int n_dl, int m_ul) { - int i; Protocol__FlexSliceConfig *fsc = malloc(sizeof(Protocol__FlexSliceConfig)); if (!fsc) return NULL; protocol__flex_slice_config__init(fsc); - /* say there are n_dl slices but reserve memory for up to 10 so - * we don't need to reserve again later */ - fsc->n_dl = n_dl; - fsc->dl = calloc(10, sizeof(Protocol__FlexDlSlice *)); - if (!fsc->dl) fsc->n_dl = 0; - for (i = 0; i < 10; i++) { - fsc->dl[i] = malloc(sizeof(Protocol__FlexDlSlice)); - if (!fsc->dl[i]) continue; - protocol__flex_dl_slice__init(fsc->dl[i]); - } - - /* as above */ - fsc->n_ul = m_ul; - fsc->ul = calloc(10, sizeof(Protocol__FlexUlSlice *)); - if (!fsc->ul) fsc->n_ul = 0; - for (i = 0; i < 10; i++) { - fsc->ul[i] = malloc(sizeof(Protocol__FlexUlSlice)); - if (!fsc->ul[i]) continue; - protocol__flex_ul_slice__init(fsc->ul[i]); - } + /* TODO */ return fsc; } -void flexran_agent_read_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *s) -{ - s->intraslice_share_active = flexran_get_intraslice_sharing_active(mod_id); - s->has_intraslice_share_active = 1; - s->interslice_share_active = flexran_get_interslice_sharing_active(mod_id); - s->has_interslice_share_active = 1; -} - -void flexran_agent_read_slice_dl_config(mid_t mod_id, int slice_idx, Protocol__FlexDlSlice *dl_slice) -{ - dl_slice->id = flexran_get_dl_slice_id(mod_id, slice_idx); - dl_slice->has_id = 1; - /* read label from corresponding sc_update entry or give default */ - dl_slice->label = PROTOCOL__FLEX_SLICE_LABEL__xMBB; - dl_slice->has_label = 1; - for (int i = 0; i < sc_update[mod_id]->n_dl; i++) { - if (sc_update[mod_id]->dl[i]->id == dl_slice->id - && sc_update[mod_id]->dl[i]->has_label) { - dl_slice->label = sc_update[mod_id]->dl[i]->label; - break; - } - } - dl_slice->percentage = flexran_get_dl_slice_percentage(mod_id, slice_idx); - dl_slice->has_percentage = 1; - dl_slice->isolation = flexran_get_dl_slice_isolation(mod_id, slice_idx); - dl_slice->has_isolation = 1; - dl_slice->priority = flexran_get_dl_slice_priority(mod_id, slice_idx); - dl_slice->has_priority = 1; - dl_slice->position_low = flexran_get_dl_slice_position_low(mod_id, slice_idx); - dl_slice->has_position_low = 1; - dl_slice->position_high = flexran_get_dl_slice_position_high(mod_id, slice_idx); - dl_slice->has_position_high = 1; - dl_slice->maxmcs = flexran_get_dl_slice_maxmcs(mod_id, slice_idx); - dl_slice->has_maxmcs = 1; - dl_slice->n_sorting = flexran_get_dl_slice_sorting(mod_id, slice_idx, &dl_slice->sorting); - if (dl_slice->n_sorting < 1) dl_slice->sorting = NULL; - dl_slice->accounting = flexran_get_dl_slice_accounting_policy(mod_id, slice_idx); - dl_slice->has_accounting = 1; - const char *s_name = flexran_get_dl_slice_scheduler(mod_id, slice_idx); - if (!dl_slice->scheduler_name - || strcmp(dl_slice->scheduler_name, s_name) != 0) { - dl_slice->scheduler_name = realloc(dl_slice->scheduler_name, strlen(s_name) + 1); - strcpy(dl_slice->scheduler_name, s_name); - } -} - -void flexran_agent_read_slice_ul_config(mid_t mod_id, int slice_idx, Protocol__FlexUlSlice *ul_slice) -{ - ul_slice->id = flexran_get_ul_slice_id(mod_id, slice_idx); - ul_slice->has_id = 1; - /* read label from corresponding sc_update entry or give default */ - ul_slice->label = PROTOCOL__FLEX_SLICE_LABEL__xMBB; - ul_slice->has_label = 1; - for (int i = 0; i < sc_update[mod_id]->n_ul; i++) { - if (sc_update[mod_id]->ul[i]->id == ul_slice->id - && sc_update[mod_id]->ul[i]->has_label) { - ul_slice->label = sc_update[mod_id]->ul[i]->label; - break; - } - } - ul_slice->percentage = flexran_get_ul_slice_percentage(mod_id, slice_idx); - ul_slice->has_percentage = 1; - /*ul_slice->isolation = flexran_get_ul_slice_isolation(mod_id, slice_idx);*/ - ul_slice->has_isolation = 0; - /*ul_slice->priority = flexran_get_ul_slice_priority(mod_id, slice_idx);*/ - ul_slice->has_priority = 0; - ul_slice->first_rb = flexran_get_ul_slice_first_rb(mod_id, slice_idx); - ul_slice->has_first_rb = 1; - /*ul_slice-> = flexran_get_ul_slice_length_rb(mod_id, slice_idx); - ul_slice->has_length_rb = 0;*/ - ul_slice->maxmcs = flexran_get_ul_slice_maxmcs(mod_id, slice_idx); - ul_slice->has_maxmcs = 1; - ul_slice->n_sorting = 0; - /*if (ul_slice->sorting) { - free(ul_slice->sorting); - ul_slice->sorting = NULL; - } - ul_slice->n_sorting = flexran_get_ul_slice_sorting(mod_id, slice_idx, &ul_slice->sorting); - if (ul_slice->n_sorting < 1) ul_slice->sorting = NULL;*/ - /*ul_slice->accounting = flexran_get_ul_slice_accounting_policy(mod_id, slice_idx);*/ - ul_slice->has_accounting = 0; - const char *s_name = flexran_get_ul_slice_scheduler(mod_id, slice_idx); - if (!ul_slice->scheduler_name - || strcmp(ul_slice->scheduler_name, s_name) != 0) { - ul_slice->scheduler_name = realloc(ul_slice->scheduler_name, strlen(s_name) + 1); - strcpy(ul_slice->scheduler_name, s_name); - } -} - -int check_dl_sorting_update(Protocol__FlexDlSlice *old, Protocol__FlexDlSlice *new) -{ - /* sorting_update => true when old->n_sorting == 0 or different numbers of - * elements; otherwise will check * element-wise */ - int sorting_update = old->n_sorting == 0 || (old->n_sorting != new->n_sorting); - for (int i = 0; i < old->n_sorting && !sorting_update; ++i) { - sorting_update = sorting_update || (new->sorting[i] != old->sorting[i]); - } - return sorting_update; -} - -int check_ul_sorting_update(Protocol__FlexUlSlice *old, Protocol__FlexUlSlice *new) -{ - /* sorting_update => true when old->n_sorting == 0 or different numbers of - * elements; otherwise will check * element-wise */ - int sorting_update = old->n_sorting == 0 || (old->n_sorting != new->n_sorting); - for (int i = 0; i < old->n_sorting && !sorting_update; ++i) { - sorting_update = sorting_update || (new->sorting[i] != old->sorting[i]); - } - return sorting_update; -} - -void overwrite_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *exist, Protocol__FlexSliceConfig *update) -{ - if (update->has_intraslice_share_active - && exist->intraslice_share_active != update->intraslice_share_active) { - LOG_I(FLEXRAN_AGENT, "[%d] update intraslice_share_active: %d -> %d\n", - mod_id, exist->intraslice_share_active, update->intraslice_share_active); - exist->intraslice_share_active = update->intraslice_share_active; - exist->has_intraslice_share_active = 1; - } - if (update->has_interslice_share_active - && exist->interslice_share_active != update->interslice_share_active) { - LOG_I(FLEXRAN_AGENT, "[%d] update interslice_share_active: %d -> %d\n", - mod_id, exist->interslice_share_active, update->interslice_share_active); - exist->interslice_share_active = update->interslice_share_active; - exist->has_interslice_share_active = 1; - } -} - -void overwrite_slice_config_dl(mid_t mod_id, Protocol__FlexDlSlice *exist, Protocol__FlexDlSlice *update) -{ - if (update->label != exist->label) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update label: %d -> %d\n", - mod_id, update->id, exist->label, update->label); - exist->label = update->label; - exist->has_label = 1; - } - if (update->percentage != exist->percentage) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update percentage: %d -> %d\n", - mod_id, update->id, exist->percentage, update->percentage); - exist->percentage = update->percentage; - exist->has_percentage = 1; - } - if (update->isolation != exist->isolation) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update isolation: %d -> %d\n", - mod_id, update->id, exist->isolation, update->isolation); - exist->isolation = update->isolation; - exist->has_isolation = 1; - } - if (update->priority != exist->priority) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update priority: %d -> %d\n", - mod_id, update->id, exist->priority, update->priority); - exist->priority = update->priority; - exist->has_priority = 1; - } - if (update->position_low != exist->position_low) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update position_low: %d -> %d\n", - mod_id, update->id, exist->position_low, update->position_low); - exist->position_low = update->position_low; - exist->has_position_low = 1; - } - if (update->position_high != exist->position_high) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update position_high: %d -> %d\n", - mod_id, update->id, exist->position_high, update->position_high); - exist->position_high = update->position_high; - exist->has_position_high = 1; - } - if (update->maxmcs != exist->maxmcs) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update maxmcs: %d -> %d\n", - mod_id, update->id, exist->maxmcs, update->maxmcs); - exist->maxmcs = update->maxmcs; - exist->has_maxmcs = 1; - } - if (check_dl_sorting_update(exist, update)) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update sorting array\n", mod_id, update->id); - if (exist->n_sorting != update->n_sorting) { - exist->n_sorting = update->n_sorting; - exist->sorting = realloc(exist->sorting, exist->n_sorting * sizeof(Protocol__FlexDlSorting)); - if (!exist->sorting) exist->n_sorting = 0; - } - for (int i = 0; i < exist->n_sorting; i++) - exist->sorting[i] = update->sorting[i]; - } - if (update->accounting != exist->accounting) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update accounting: %d -> %d\n", - mod_id, update->id, exist->accounting, update->accounting); - exist->accounting = update->accounting; - exist->has_accounting = 1; - } - if (!exist->scheduler_name - || strcmp(update->scheduler_name, exist->scheduler_name) != 0) { - LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update scheduler: %s -> %s\n", - mod_id, update->id, exist->scheduler_name, update->scheduler_name); - if (exist->scheduler_name) free(exist->scheduler_name); - exist->scheduler_name = strdup(update->scheduler_name); - } -} - -void overwrite_slice_config_ul(mid_t mod_id, Protocol__FlexUlSlice *exist, Protocol__FlexUlSlice *update) -{ - if (update->label != exist->label) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update label: %d -> %d\n", - mod_id, update->id, exist->label, update->label); - exist->label = update->label; - exist->has_label = 1; - } - if (update->percentage != exist->percentage) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update percentage: %d -> %d\n", - mod_id, update->id, exist->percentage, update->percentage); - exist->percentage = update->percentage; - exist->has_percentage = 1; - } - if (update->isolation != exist->isolation) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update isolation: %d -> %d\n", - mod_id, update->id, exist->isolation, update->isolation); - exist->isolation = update->isolation; - exist->has_isolation = 1; - } - if (update->priority != exist->priority) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update priority: %d -> %d\n", - mod_id, update->id, exist->priority, update->priority); - exist->priority = update->priority; - exist->has_priority = 1; - } - if (update->first_rb != exist->first_rb) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update first_rb: %d -> %d\n", - mod_id, update->id, exist->first_rb, update->first_rb); - exist->first_rb = update ->first_rb; - exist->has_first_rb = 1; - } - /*if (update->lenght_rb != exist->lenght_rb) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update lenght_rb: %d -> %d\n", - mod_id, update->id, exist->lenght_rb, update->lenght_rb); - exist->lenght_rb = update->lenght_rb; - }*/ - if (update->maxmcs != exist->maxmcs) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update maxmcs: %d -> %d\n", - mod_id, update->id, exist->maxmcs, update->maxmcs); - exist->maxmcs = update->maxmcs; - exist->has_maxmcs = 1; - } - /* TODO - int sorting_update = 0; - int n = min(exist->n_sorting, update->n_sorting); - int i = 0; - while (i < n && !sorting_update) { - sorting_update = sorting_update || (update->sorting[i] != exist->sorting[i]); - i++; - } - if (sorting_update) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update sorting array\n", update->id, mod_id); - if (exist->n_sorting != update->n_sorting) - LOG_W(FLEXRAN_AGENT, "[%d][UL slice %d] only writing %d elements\n", - mod_id, update->id, n); - for (i = 0; i < n; i++) - exist->sorting[i] = update->sorting[i]; - } - */ - if (update->accounting != exist->accounting) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update accounting: %d -> %d\n", - mod_id, update->id, exist->accounting, update->accounting); - exist->accounting = update->accounting; - exist->has_accounting = 1; - } - if (!exist->scheduler_name - || strcmp(update->scheduler_name, exist->scheduler_name) != 0) { - LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update scheduler: %s -> %s\n", - mod_id, update->id, exist->scheduler_name, update->scheduler_name); - if (exist->scheduler_name) free(exist->scheduler_name); - exist->scheduler_name = strdup(update->scheduler_name); - } -} - -void fill_dl_slice(mid_t mod_id, Protocol__FlexDlSlice *s, Protocol__FlexDlSlice *from) -{ - /* function fills slice with information from another slice or with default - * values (currently slice 0) if from is NULL */ - /* TODO fill the slice depending on the chosen label */ - if (!s->has_label) { - s->has_label = 1; - s->label = from ? from->label : sc_update[mod_id]->dl[0]->label; - } - if (!s->has_percentage) { - s->has_percentage = 1; - s->percentage = from ? from->percentage : sc_update[mod_id]->dl[0]->percentage; - } - if (!s->has_isolation) { - s->has_isolation = 1; - s->isolation = from ? from->isolation : sc_update[mod_id]->dl[0]->isolation; - } - if (!s->has_priority) { - s->has_priority = 1; - s->priority = from ? from->priority : sc_update[mod_id]->dl[0]->priority; - } - if (!s->has_position_low) { - s->has_position_low = 1; - s->position_low = from ? from->position_low : sc_update[mod_id]->dl[0]->position_low; - } - if (!s->has_position_high) { - s->has_position_high = 1; - s->position_high = from ? from->position_high : sc_update[mod_id]->dl[0]->position_high; - } - if (!s->has_maxmcs) { - s->has_maxmcs = 1; - s->maxmcs = from ? from->maxmcs : sc_update[mod_id]->dl[0]->maxmcs; - } - if (s->n_sorting == 0) { - s->n_sorting = from ? from->n_sorting : sc_update[mod_id]->dl[0]->n_sorting; - s->sorting = calloc(s->n_sorting, sizeof(Protocol__FlexDlSorting)); - if (!s->sorting) s->n_sorting = 0; - for (int i = 0; i < s->n_sorting; ++i) - s->sorting[i] = from ? from->sorting[i] : sc_update[0]->dl[0]->sorting[i]; - } - if (!s->has_accounting) { - s->accounting = from ? from->accounting : sc_update[mod_id]->dl[0]->accounting; - } - if (!s->scheduler_name) { - s->scheduler_name = strdup(from ? from->scheduler_name : sc_update[mod_id]->dl[0]->scheduler_name); - } -} - -Protocol__FlexDlSlice *get_existing_dl_slice(mid_t mod_id, int id) -{ - for (int i = 0; i < sc_update[mod_id]->n_dl; ++i) { - if (id == sc_update[mod_id]->dl[i]->id) { - return sc_update[mod_id]->dl[i]; - } - } - return NULL; -} - -Protocol__FlexDlSlice *create_new_dl_slice(mid_t mod_id, int id) -{ - LOG_I(FLEXRAN_AGENT, - "[%d] Creating DL slice with ID %d, taking default values from DL slice 0\n", - mod_id, id); - Protocol__FlexDlSlice *to = sc_update[mod_id]->dl[sc_update[mod_id]->n_dl]; - sc_update[mod_id]->n_dl++; - AssertFatal(sc_update[mod_id]->n_dl <= 10, - "cannot create more than 10\n"); - to->id = id; - return to; -} - -void fill_ul_slice(mid_t mod_id, Protocol__FlexUlSlice *s, Protocol__FlexUlSlice *from) -{ - /* function fills slice with information from another slice or with default - * values (currently slice 0) if from is NULL */ - /* TODO fill the slice depending on the chosen label */ - if (!s->has_label) { - s->has_label = 1; - s->label = from ? from->label : sc_update[mod_id]->ul[0]->label; - } - if (!s->has_percentage) { - s->has_percentage = 1; - s->percentage = from ? from->percentage : sc_update[mod_id]->ul[0]->percentage; - } - if (!s->has_isolation) { - s->has_isolation = 1; - s->isolation = from ? from->isolation : sc_update[mod_id]->ul[0]->isolation; - } - if (!s->has_priority) { - s->has_priority = 1; - s->priority = from ? from->priority : sc_update[mod_id]->ul[0]->priority; - } - if (!s->has_first_rb) { - s->has_first_rb = 1; - s->first_rb = from ? from->first_rb : sc_update[mod_id]->ul[0]->first_rb; - } - if (!s->has_maxmcs) { - s->has_maxmcs = 1; - s->maxmcs = from ? from->maxmcs : sc_update[mod_id]->ul[0]->maxmcs; - } - if (s->n_sorting == 0) { - s->n_sorting = from ? from->n_sorting : sc_update[0]->ul[0]->n_sorting; - s->sorting = calloc(s->n_sorting, sizeof(Protocol__FlexUlSorting)); - if (!s->sorting) s->n_sorting = 0; - for (int i = 0; i < s->n_sorting; ++i) - s->sorting[i] = from ? from->sorting[i] : sc_update[0]->ul[0]->sorting[i]; - } - if (!s->has_accounting) { - s->accounting = from ? from->accounting : sc_update[0]->ul[0]->accounting; - } - if (!s->scheduler_name) { - s->scheduler_name = strdup(from ? from->scheduler_name : sc_update[mod_id]->ul[0]->scheduler_name); - } -} - -Protocol__FlexUlSlice *get_existing_ul_slice(mid_t mod_id, int id) -{ - for (int i = 0; i < sc_update[mod_id]->n_ul; ++i) { - if (id == sc_update[mod_id]->ul[i]->id) { - return sc_update[mod_id]->ul[i]; - } - } - return NULL; -} - -Protocol__FlexUlSlice *create_new_ul_slice(mid_t mod_id, int id) -{ - LOG_I(FLEXRAN_AGENT, - "[%d] Creating UL slice with ID %d, taking default values from UL slice 0\n", - mod_id, id); - Protocol__FlexUlSlice *to = sc_update[mod_id]->ul[sc_update[mod_id]->n_ul]; - sc_update[mod_id]->n_ul++; - AssertFatal(sc_update[mod_id]->n_ul <= 10, - "cannot create more than 10\n"); - to->id = id; - return to; -} - void prepare_update_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *sup) { - int verified = 1; - if (!sc_update[mod_id]) { - LOG_E(FLEXRAN_AGENT, "Can not update slice policy (no existing slice profile)\n"); - return; - } - - pthread_mutex_lock(&sc_update_mtx); - /* no need for tests in the current state as there are only two protobuf - * bools for intra-/interslice sharing. The function applies new values if - * applicable */ - overwrite_slice_config(mod_id, sc_update[mod_id], sup); - - if (sup->n_dl == 0) { - LOG_I(FLEXRAN_AGENT, "[%d] no DL slice configuration in flex_slice_config message\n", mod_id); - } else { - /* verify slice parameters */ - for (int i = 0; i < sup->n_dl; i++) { - if (!sup->dl[i]->has_id) { - verified = 0; - break; - } - Protocol__FlexDlSlice *dls = get_existing_dl_slice(mod_id, sup->dl[i]->id); - /* fill up so that the slice is complete. This way, we don't need to - * worry about it later */ - fill_dl_slice(mod_id, sup->dl[i], dls); - verified = verified && flexran_verify_dl_slice(mod_id, sup->dl[i]); - if (!verified) break; - } - - /* verify group-based parameters (e.g. sum percentage should not exceed - * 100%). Can be used to perform admission control */ - verified = verified && flexran_verify_group_dl_slices(mod_id, - sc_update[mod_id]->dl, sc_update[mod_id]->n_dl, sup->dl, sup->n_dl); - - if (verified) { - for (int i = 0; i < sup->n_dl; i++) { - /* if all verifications were successful, get existing slice for ID or - * create new one and overwrite with the update */ - Protocol__FlexDlSlice *dls = get_existing_dl_slice(mod_id, sup->dl[i]->id); - if (!dls) dls = create_new_dl_slice(mod_id, sup->dl[i]->id); - overwrite_slice_config_dl(mod_id, dls, sup->dl[i]); - } - } else { - LOG_E(FLEXRAN_AGENT, "[%d] DL slice verification failed, refusing application\n", mod_id); - } - } - - verified = 1; - if (sup->n_ul == 0) { - LOG_I(FLEXRAN_AGENT, "[%d] no UL slice configuration in flex_slice_config message\n", mod_id); - } else { - /* verify slice parameters */ - for (int i = 0; i < sup->n_ul; i++) { - if (!sup->ul[i]->has_id) { - verified = 0; - break; - } - Protocol__FlexUlSlice *uls = get_existing_ul_slice(mod_id, sup->ul[i]->id); - /* fill up so that the slice is complete. This way, we don't need to - * worry about it later */ - fill_ul_slice(mod_id, sup->ul[i], uls); - verified = verified && flexran_verify_ul_slice(mod_id, sup->ul[i]); - if (!verified) break; - } - - /* verify group-based parameters (e.g. sum percentage should not exceed - * 100%). Can be used to perform admission control */ - verified = verified && flexran_verify_group_ul_slices(mod_id, - sc_update[mod_id]->ul, sc_update[mod_id]->n_ul, sup->ul, sup->n_ul); - - if (verified) { - for (int i = 0; i < sup->n_ul; i++) { - /* if all verifications were successful, get existing slice for ID or - * create new one and overwrite with the update */ - Protocol__FlexUlSlice *uls = get_existing_ul_slice(mod_id, sup->ul[i]->id); - if (!uls) uls = create_new_ul_slice(mod_id, sup->ul[i]->id); - overwrite_slice_config_ul(mod_id, uls, sup->ul[i]); - } - } else { - LOG_E(FLEXRAN_AGENT, "[%d] UL slice verification failed, refusing application\n", mod_id); - } - } - pthread_mutex_unlock(&sc_update_mtx); - - perform_slice_config_update_count = 1; } -int apply_new_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *olds, Protocol__FlexSliceConfig *news) -{ - /* not setting the old configuration is intentional, as it will be picked up - * later when reading the configuration. There is thus a direct feedback - * whether it has been set. */ - int changes = 0; - if (olds->intraslice_share_active != news->intraslice_share_active) { - flexran_set_intraslice_sharing_active(mod_id, news->intraslice_share_active); - changes++; - } - if (olds->interslice_share_active != news->interslice_share_active) { - flexran_set_interslice_sharing_active(mod_id, news->interslice_share_active); - changes++; - } - return changes; -} - -int apply_new_slice_dl_config(mid_t mod_id, Protocol__FlexDlSlice *oldc, Protocol__FlexDlSlice *newc) -{ - /* not setting the old configuration is intentional, as it will be picked up - * later when reading the configuration. There is thus a direct feedback - * whether it has been set. */ - int changes = 0; - int slice_idx = flexran_find_dl_slice(mod_id, newc->id); - if (slice_idx < 0) { - LOG_W(FLEXRAN_AGENT, "[%d] cannot find index for slice ID %d\n", mod_id, newc->id); - return 0; - } - if (oldc->percentage != newc->percentage) { - flexran_set_dl_slice_percentage(mod_id, slice_idx, newc->percentage); - changes++; - } - if (oldc->isolation != newc->isolation) { - flexran_set_dl_slice_isolation(mod_id, slice_idx, newc->isolation); - changes++; - } - if (oldc->priority != newc->priority) { - flexran_set_dl_slice_priority(mod_id, slice_idx, newc->priority); - changes++; - } - if (oldc->position_low != newc->position_low) { - flexran_set_dl_slice_position_low(mod_id, slice_idx, newc->position_low); - changes++; - } - if (oldc->position_high != newc->position_high) { - flexran_set_dl_slice_position_high(mod_id, slice_idx, newc->position_high); - changes++; - } - if (oldc->maxmcs != newc->maxmcs) { - flexran_set_dl_slice_maxmcs(mod_id, slice_idx, newc->maxmcs); - changes++; - } - if (check_dl_sorting_update(oldc, newc)) { - flexran_set_dl_slice_sorting(mod_id, slice_idx, newc->sorting, newc->n_sorting); - changes++; - } - if (oldc->accounting != newc->accounting) { - flexran_set_dl_slice_accounting_policy(mod_id, slice_idx, newc->accounting); - changes++; - } - if (!oldc->scheduler_name - || strcmp(oldc->scheduler_name, newc->scheduler_name) != 0) { - int ret = flexran_set_dl_slice_scheduler(mod_id, slice_idx, newc->scheduler_name); - AssertFatal(ret, "could not set DL slice scheduler for slice %d idx %d\n", - newc->id, slice_idx); - changes++; - } - return changes; -} - -int apply_new_slice_ul_config(mid_t mod_id, Protocol__FlexUlSlice *oldc, Protocol__FlexUlSlice *newc) -{ - /* not setting the old configuration is intentional, as it will be picked up - * later when reading the configuration. There is thus a direct feedback - * whether it has been set. */ - int changes = 0; - int slice_idx = flexran_find_ul_slice(mod_id, newc->id); - if (slice_idx < 0) { - LOG_W(FLEXRAN_AGENT, "[%d] cannot find index for slice ID %d\n", mod_id, newc->id); - return 0; - } - if (oldc->percentage != newc->percentage) { - flexran_set_ul_slice_percentage(mod_id, slice_idx, newc->percentage); - changes++; - } - if (oldc->isolation != newc->isolation) { - /*flexran_set_ul_slice_isolation(mod_id, slice_idx, newc->isolation); - *changes++;*/ - LOG_W(FLEXRAN_AGENT, "[%d][UL slice %d] setting isolation is not supported\n", - mod_id, newc->id); - } - if (oldc->priority != newc->priority) { - /*flexran_set_ul_slice_priority(mod_id, slice_idx, newc->priority); - *changes++;*/ - LOG_W(FLEXRAN_AGENT, "[%d][UL slice %d] setting the priority is not supported\n", - mod_id, newc->id); - } - if (oldc->first_rb != newc->first_rb) { - flexran_set_ul_slice_first_rb(mod_id, slice_idx, newc->first_rb); - changes++; - } - /*if (oldc->length_rb != newc->length_rb) { - flexran_set_ul_slice_length_rb(mod_id, slice_idx, newc->length_rb); - changes++; - LOG_W(FLEXRAN_AGENT, "[%d][UL slice %d] setting length_rb is not supported\n", - mod_id, newc->id); - }*/ - if (oldc->maxmcs != newc->maxmcs) { - flexran_set_ul_slice_maxmcs(mod_id, slice_idx, newc->maxmcs); - changes++; - } - /*if (check_ul_sorting_update(oldc, newc)) { - flexran_set_ul_slice_sorting(mod_id, slice_idx, newc->sorting, n); - changes++; - LOG_W(FLEXRAN_AGENT, "[%d][UL slice %d] setting the sorting is not supported\n", - mod_id, newc->id); - }*/ - if (oldc->accounting != newc->accounting) { - /*flexran_set_ul_slice_accounting_policy(mod_id, slice_idx, newc->accounting); - *changes++;*/ - LOG_W(FLEXRAN_AGENT, "[%d][UL slice %d] setting the accounting is not supported\n", - mod_id, newc->id); - } - if (!oldc->scheduler_name - || strcmp(oldc->scheduler_name, newc->scheduler_name) != 0) { - int ret = flexran_set_ul_slice_scheduler(mod_id, slice_idx, newc->scheduler_name); - AssertFatal(ret, "could not set DL slice scheduler for slice %d idx %d\n", - newc->id, slice_idx); - changes++; - } - return changes; -} void prepare_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig *ue_config) { @@ -1723,24 +1075,8 @@ int apply_ue_slice_assoc_update(mid_t mod_id) continue; } if (ue_slice_assoc_update[i]->has_dl_slice_id) { - int slice_idx = flexran_find_dl_slice(mod_id, ue_slice_assoc_update[i]->dl_slice_id); - if (flexran_dl_slice_exists(mod_id, slice_idx)) { - flexran_set_ue_dl_slice_idx(mod_id, ue_id, slice_idx); - changes++; - } else { - LOG_W(FLEXRAN_AGENT, "[%d] DL slice %d does not exist, refusing change\n", - mod_id, ue_slice_assoc_update[i]->dl_slice_id); - } } if (ue_slice_assoc_update[i]->has_ul_slice_id) { - int slice_idx = flexran_find_ul_slice(mod_id, ue_slice_assoc_update[i]->ul_slice_id); - if (flexran_ul_slice_exists(mod_id, slice_idx)) { - flexran_set_ue_ul_slice_idx(mod_id, ue_id, slice_idx); - changes++; - } else { - LOG_W(FLEXRAN_AGENT, "[%d] UL slice %d does not exist, refusing change\n", - mod_id, ue_slice_assoc_update[i]->ul_slice_id); - } } } n_ue_slice_assoc_updates = 0; diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.h b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.h index 957fe6065e..ef2a7e40a9 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.h +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.h @@ -111,30 +111,10 @@ Protocol__FlexSliceConfig *flexran_agent_create_slice_config(int n_dl, int m_ul) * Protocol__FlexSliceConfig struct */ void flexran_agent_read_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *s); -/* read the DL slice config via the RAN into a given Protocol__FlexDlSlice - * struct */ -void flexran_agent_read_slice_dl_config(mid_t mod_id, int slice_idx, Protocol__FlexDlSlice *dl_slice); - -/* read the UL slice config via the RAN into a given Protocol__FlexUlSlice - * struct */ -void flexran_agent_read_slice_ul_config(mid_t mod_id, int slice_idx, Protocol__FlexUlSlice *ul_slice); - /* reads content of slice over the sc_update structure, so that it can be * applied later by performing a diff between slice_config and sc_update */ void prepare_update_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *slice); -/* apply generic slice parameters (e.g. intra-/interslice sharing activated or - * not) if there are changes. Returns the number of changed parameters. */ -int apply_new_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *olds, Protocol__FlexSliceConfig *news); - -/* apply new configuration of slice in DL if there are changes between the - * parameters. Returns the number of changed parameters. */ -int apply_new_slice_dl_config(mid_t mod_id, Protocol__FlexDlSlice *oldc, Protocol__FlexDlSlice *newc); - -/* apply new configuration of slice in UL if there are changes between the - * parameters. Returns the number of changed parameters. */ -int apply_new_slice_ul_config(mid_t mod_id, Protocol__FlexUlSlice *oldc, Protocol__FlexUlSlice *newc); - /* inserts a new ue_config into the structure keeping ue to slice association * updates and marks so it can be applied */ void prepare_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig *ue_config); diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.c index f7f60541f5..6e54e155c2 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.c +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.c @@ -28,346 +28,3 @@ #include "flexran_agent_mac_slice_verification.h" - -/* overlap check for UL slices, helper type */ -struct sregion_s { - int start; - int length; -}; - -/* forward declaration of locally-used verification functions */ -int flexran_dl_slice_verify_pct(int pct); -int flexran_dl_slice_verify_priority(int prio); -int flexran_dl_slice_verify_position(int pos_low, int pos_high); -int flexran_dl_slice_verify_maxmcs(int maxmcs); -int flexran_ul_slice_verify_pct(int pct); -int flexran_ul_slice_verify_priority(int prio); -int flexran_ul_slice_verify_first_rb(int first_rb); -int flexran_ul_slice_verify_maxmcs(int maxmcs); -int check_ul_slice_overlap(mid_t mod_id, struct sregion_s *sr, int n); - -int flexran_verify_dl_slice(mid_t mod_id, Protocol__FlexDlSlice *dls) -{ - /* check mandatory parameters */ - if (!dls->has_id) { - LOG_E(FLEXRAN_AGENT, "[%d] Incoming DL slice configuration has no ID\n", mod_id); - return 0; - } - - /* verify parameters individualy */ - /* label is enum */ - if (!flexran_dl_slice_verify_pct(dls->percentage)) { - LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] illegal DL slice percentage (%d)\n", - mod_id, dls->id, dls->percentage); - return 0; - } - /* isolation is a protobuf bool */ - if (!flexran_dl_slice_verify_priority(dls->priority)) { - LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] illegal DL slice priority (%d)\n", - mod_id, dls->id, dls->priority); - return 0; - } - if (!flexran_dl_slice_verify_position(dls->position_low, dls->position_high)) { - LOG_E(FLEXRAN_AGENT, - "[%d][DL slice %d] illegal DL slice position low (%d) and/or high (%d)\n", - mod_id, dls->id, dls->position_low, dls->position_high); - return 0; - } - if (!flexran_dl_slice_verify_maxmcs(dls->maxmcs)) { - LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] illegal DL slice max mcs %d\n", - mod_id, dls->id, dls->maxmcs); - return 0; - } - if (dls->n_sorting == 0) { - LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] no sorting in DL slice\n", - mod_id, dls->id); - return 0; - } - if (!dls->sorting) { - LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] no sorting found in DL slice\n", - mod_id, dls->id); - return 0; - } - /* sorting is an enum */ - /* accounting is an enum */ - if (!dls->scheduler_name) { - LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] no scheduler name found\n", - mod_id, dls->id); - return 0; - } - if (strcmp(dls->scheduler_name, "schedule_ue_spec") != 0) { - LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] setting the scheduler to something " - "different than schedule_ue_spec is currently not allowed\n", - mod_id, dls->id); - return 0; - } - - return 1; -} - -int flexran_verify_group_dl_slices(mid_t mod_id, Protocol__FlexDlSlice **existing, - int n_ex, Protocol__FlexDlSlice **update, int n_up) -{ - int i, j, n; - int pct, pct_orig; - /* for every update, array points to existing slice, or NULL if update - * creates new slice */ - Protocol__FlexDlSlice *s[n_up]; - for (i = 0; i < n_up; i++) { - s[i] = NULL; - for (j = 0; j < n_ex; j++) { - if (existing[j]->id == update[i]->id) - s[i] = existing[j]; - } - } - - /* check that number of created and number of added slices in total matches - * [1,10] */ - n = n_ex; - for (i = 0; i < n_up; i++) { - /* new slice */ - if (!s[i]) n += 1; - /* slice will be deleted */ - else if (s[i]->percentage == 0) n -= 1; - /* else "only" an update */ - } - - if (n < 1 || n > 10) { - LOG_E(FLEXRAN_AGENT, "[%d] Illegal number of resulting DL slices (%d -> %d)\n", - mod_id, n_ex, n); - return 0; - } - - /* check that the sum of all slices percentages (including removed/added - * slices) matches [1,100] */ - pct = 0; - for (i = 0; i < n_ex; i++) { - pct += existing[i]->percentage; - } - pct_orig = pct; - for (i = 0; i < n_up; i++) { - /* if there is an existing slice, subtract its percentage and add the - * update's percentage */ - if (s[i]) - pct -= s[i]->percentage; - pct += update[i]->percentage; - } - if (pct < 1 || pct > 100) { - LOG_E(FLEXRAN_AGENT, - "[%d] invalid total RB share for DL slices (%d%% -> %d%%)\n", - mod_id, pct_orig, pct); - return 0; - } - - return 1; -} - -int flexran_verify_ul_slice(mid_t mod_id, Protocol__FlexUlSlice *uls) -{ - /* check mandatory parameters */ - if (!uls->has_id) { - LOG_E(FLEXRAN_AGENT, "[%d] Incoming UL slice configuration has no ID\n", mod_id); - return 0; - } - - /* verify parameters individually */ - /* label is enum */ - if (!flexran_ul_slice_verify_pct(uls->percentage)) { - LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] illegal UL slice percentage (%d)\n", - mod_id, uls->id, uls->percentage); - return 0; - } - /* isolation is a protobuf bool */ - if (!flexran_ul_slice_verify_priority(uls->priority)) { - LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] illegal UL slice percentage (%d)\n", - mod_id, uls->id, uls->priority); - return 0; - } - if (!flexran_ul_slice_verify_first_rb(uls->first_rb)) { - LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] illegal UL slice first RB (%d)\n", - mod_id, uls->id, uls->first_rb); - return 0; - } - if (!flexran_ul_slice_verify_maxmcs(uls->maxmcs)) { - LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] illegal UL slice max mcs (%d)\n", - mod_id, uls->id, uls->maxmcs); - return 0; - } - /* TODO - if (uls->n_sorting == 0) { - LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] no sorting in UL slice\n", - mod_id, uls->id); - return 0; - } - if (!uls->sorting) { - LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] no sorting found in UL slice\n", - mod_id, uls->id); - return 0; - } - */ - /* sorting is an enum */ - /* accounting is an enum */ - if (!uls->scheduler_name) { - LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] no scheduler name found\n", - mod_id, uls->id); - return 0; - } - if (strcmp(uls->scheduler_name, "schedule_ulsch_rnti") != 0) { - LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] setting the scheduler to something " - "different than schedule_ulsch_rnti is currently not allowed\n", - mod_id, uls->id); - return 0; - } - - return 1; -} - -int flexran_verify_group_ul_slices(mid_t mod_id, Protocol__FlexUlSlice **existing, - int n_ex, Protocol__FlexUlSlice **update, int n_up) -{ - int i, j, n; - int pct, pct_orig; - /* for every update, array "s" points to existing slice, or NULL if update - * creates new slice; array "offs" gives the offset of this slice */ - Protocol__FlexUlSlice *s[n_up]; - int offs[n_up]; - for (i = 0; i < n_up; i++) { - s[i] = NULL; - offs[i] = 0; - for (j = 0; j < n_ex; j++) { - if (existing[j]->id == update[i]->id) { - s[i] = existing[j]; - offs[i] = j; - } - } - } - - /* check that number of created and number of added slices in total matches - * [1,10] */ - n = n_ex; - for (i = 0; i < n_up; i++) { - /* new slice */ - if (!s[i]) n += 1; - /* slice will be deleted */ - else if (s[i]->percentage == 0) n -= 1; - /* else "only" an update */ - } - - if (n < 1 || n > 10) { - LOG_E(FLEXRAN_AGENT, "[%d] Illegal number of resulting UL slices (%d -> %d)\n", - mod_id, n_ex, n); - return 0; - } - - /* check that the sum of all slices percentages (including removed/added - * slices) matches [1,100] */ - pct = 0; - for (i = 0; i < n_ex; i++) { - pct += existing[i]->percentage; - } - pct_orig = pct; - for (i = 0; i < n_up; i++) { - /* if there is an existing slice, subtract its percentage and add the - * update's percentage */ - if (s[i]) - pct -= s[i]->percentage; - pct += update[i]->percentage; - } - if (pct < 1 || pct > 100) { - LOG_E(FLEXRAN_AGENT, "[%d] invalid total RB share (%d%% -> %d%%)\n", - mod_id, pct_orig, pct); - return 0; - } - - /* check that there is no overlap in slices resulting as the combination of - * first_rb and percentage */ - struct sregion_s sregion[n]; - const int N_RB = flexran_get_N_RB_UL(mod_id, 0); /* assume PCC */ - int k = n_ex; - for (i = 0; i < n_ex; i++) { - sregion[i].start = existing[i]->first_rb; - sregion[i].length = existing[i]->percentage * N_RB / 100; - } - for (i = 0; i < n_up; i++) { - ptrdiff_t d = s[i] ? offs[i] : k++; - AssertFatal(d >= 0 && d < k, "illegal pointer offset (%ld, k=%d)\n", d, k); - sregion[d].start = update[i]->first_rb; - sregion[d].length = update[i]->percentage * N_RB / 100; - } - AssertFatal(k == n, "illegal number of slices while calculating overlap\n"); - if (!check_ul_slice_overlap(mod_id, sregion, k)) { - LOG_E(FLEXRAN_AGENT, "[%d] UL slices are overlapping\n", mod_id); - return 0; - } - - return 1; -} - -int flexran_dl_slice_verify_pct(int pct) -{ - return pct >= 0 && pct <= 100; -} - -int flexran_dl_slice_verify_priority(int prio) -{ - return prio >= 0; -} - -int flexran_dl_slice_verify_position(int pos_low, int pos_high) -{ - return pos_low < pos_high && pos_low >= 0 && pos_high <= N_RBG_MAX; -} - -int flexran_dl_slice_verify_maxmcs(int maxmcs) -{ - return maxmcs >= 0 && maxmcs <= 28; -} - -int flexran_ul_slice_verify_pct(int pct) -{ - return pct >= 0 && pct <= 100; -} - -int flexran_ul_slice_verify_priority(int prio) -{ - return prio >= 0; -} - -int flexran_ul_slice_verify_first_rb(int first_rb) -{ - return first_rb >= 0 && first_rb < 100; -} - -int flexran_ul_slice_verify_maxmcs(int maxmcs) -{ - return maxmcs >= 0 && maxmcs <= 20; -} - -int sregion_compare(const void *_a, const void *_b) -{ - const struct sregion_s *a = (const struct sregion_s *)_a; - const struct sregion_s *b = (const struct sregion_s *)_b; - const int res = a->start - b->start; - if (res < 0) return -1; - else if (res == 0) return 0; - else return 1; -} - -int check_ul_slice_overlap(mid_t mod_id, struct sregion_s *sr, int n) -{ - int i; - int overlap, op, u; - const int N_RB = flexran_get_N_RB_UL(mod_id, 0); /* assume PCC */ - qsort(sr, n, sizeof(sr[0]), sregion_compare); - for (i = 0; i < n; i++) { - u = i == n-1 ? N_RB : sr[i+1].start; - AssertFatal(sr[i].start <= u, "unsorted slice list\n"); - overlap = sr[i].start + sr[i].length - u; - if (overlap <= 0) continue; - op = overlap * 100 / sr[i].length; - LOG_W(FLEXRAN_AGENT, "[%d] slice overlap of %d%% detected\n", mod_id, op); - if (op >= 10) /* more than 10% overlap -> refuse */ - return 0; - } - return 1; -} diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.h b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.h index a8f4030d36..c9e66b6f88 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.h +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.h @@ -29,9 +29,3 @@ #include "flexran_agent_common_internal.h" #include "flexran_agent_mac_internal.h" -int flexran_verify_dl_slice(mid_t mod_id, Protocol__FlexDlSlice *dls); -int flexran_verify_group_dl_slices(mid_t mod_id, Protocol__FlexDlSlice **existing, - int n_ex, Protocol__FlexDlSlice **update, int n_up); -int flexran_verify_ul_slice(mid_t mod_id, Protocol__FlexUlSlice *uls); -int flexran_verify_group_ul_slices(mid_t mod_id, Protocol__FlexUlSlice **existing, - int n_ex, Protocol__FlexUlSlice **update, int n_up); diff --git a/openair2/ENB_APP/MESSAGES/V2/config_common.proto b/openair2/ENB_APP/MESSAGES/V2/config_common.proto index 733d883c92..e5d01ebdc0 100644 --- a/openair2/ENB_APP/MESSAGES/V2/config_common.proto +++ b/openair2/ENB_APP/MESSAGES/V2/config_common.proto @@ -61,83 +61,6 @@ enum flex_qam { // // Slice config related structures and enums // -enum flex_dl_sorting { - - CR_ROUND = 0; // Highest HARQ first - CR_SRB12 = 1; // Highest SRB1+2 first - CR_HOL = 2; // Highest HOL first - CR_LC = 3; // Greatest RLC buffer first - CR_CQI = 4; // Highest CQI first - CR_LCP = 5; // Highest LC priority first -} - -enum flex_ul_sorting { - CRU_ROUND = 0; // Highest HARQ first - CRU_BUF = 1; // Highest BSR first - CRU_BTS = 2; // More bytes to schedule first - CRU_MCS = 3; // Highest MCS first - CRU_LCP = 4; // Highest LC priority first - CRU_HOL = 5; // Highest HOL first -} - -enum flex_dl_accounting_policy { - POL_FAIR = 0; - POL_GREEDY = 1; - POL_NUM = 2; -} - -enum flex_ul_accounting_policy { - POLU_FAIR = 0; - POLU_GREEDY = 1; - POLU_NUM = 2; -} - -enum flex_slice_label { - xMBB = 0; - URLLC = 1; - mMTC = 2; - xMTC = 3; - Other = 4; -} - -message flex_dl_slice { - optional uint32 id = 1; - optional flex_slice_label label = 2; - // should be between 0 and 100 - optional uint32 percentage = 3; - // whether this slice should be exempted form interslice sharing - optional bool isolation = 4; - // increasing value means increasing prio - optional uint32 priority = 5; - // min and max RB to use (in frequency) in the range [0, N_RBG_MAX] - optional uint32 position_low = 6; - optional uint32 position_high = 7; - // maximum MCS to be allowed in this slice - optional uint32 maxmcs = 8; - repeated flex_dl_sorting sorting = 9; - optional flex_dl_accounting_policy accounting = 10; - optional string scheduler_name = 11; -} - -message flex_ul_slice { - optional uint32 id = 1; - optional flex_slice_label label = 2; - // should be between 0 and 100 - optional uint32 percentage = 3; - // whether this slice should be exempted form interslice sharing - optional bool isolation = 4; - // increasing value means increasing prio - optional uint32 priority = 5; - // RB start to use (in frequency) in the range [0, N_RB_MAX] - optional uint32 first_rb = 6; - // TODO RB number - //optional uint32 length_rb = 7; - // maximum MCS to be allowed in this slice - optional uint32 maxmcs = 8; - repeated flex_ul_sorting sorting = 9; - optional flex_ul_accounting_policy accounting = 10; - optional string scheduler_name = 11; -} // // UE config related structures and enums diff --git a/openair2/ENB_APP/MESSAGES/V2/config_messages.proto b/openair2/ENB_APP/MESSAGES/V2/config_messages.proto index 324153613d..1a66a4f20f 100644 --- a/openair2/ENB_APP/MESSAGES/V2/config_messages.proto +++ b/openair2/ENB_APP/MESSAGES/V2/config_messages.proto @@ -49,14 +49,6 @@ message flex_cell_config { } message flex_slice_config { - // whether remaining RBs after first intra-slice allocation will - // be allocated to UEs of the same slice - optional bool intraslice_share_active = 3; - // whether remaining RBs after slice allocation will be allocated - // to UEs of another slice. Isolated slices will be ignored. - optional bool interslice_share_active = 4; - repeated flex_dl_slice dl = 1; - repeated flex_ul_slice ul = 2; } message flex_ue_config { diff --git a/openair2/ENB_APP/flexran_agent_common.c b/openair2/ENB_APP/flexran_agent_common.c index e77b2fb386..3dd9f5b957 100644 --- a/openair2/ENB_APP/flexran_agent_common.c +++ b/openair2/ENB_APP/flexran_agent_common.c @@ -316,25 +316,7 @@ int flexran_agent_destroy_enb_config_reply(Protocol__FlexranMessage *msg) { } if (reply->cell_config[i]->slice_config) { - for (int j = 0; j < reply->cell_config[i]->slice_config->n_dl; ++j) { - if (reply->cell_config[i]->slice_config->dl[j]->n_sorting > 0) - free(reply->cell_config[i]->slice_config->dl[j]->sorting); - - free(reply->cell_config[i]->slice_config->dl[j]->scheduler_name); - free(reply->cell_config[i]->slice_config->dl[j]); - } - - free(reply->cell_config[i]->slice_config->dl); - - for (int j = 0; j < reply->cell_config[i]->slice_config->n_ul; ++j) { - if (reply->cell_config[i]->slice_config->ul[j]->n_sorting > 0) - free(reply->cell_config[i]->slice_config->ul[j]->sorting); - - free(reply->cell_config[i]->slice_config->ul[j]->scheduler_name); - free(reply->cell_config[i]->slice_config->ul[j]); - } - - free(reply->cell_config[i]->slice_config->ul); + /* TODO */ free(reply->cell_config[i]->slice_config); } diff --git a/openair2/ENB_APP/flexran_agent_ran_api.c b/openair2/ENB_APP/flexran_agent_ran_api.c index 291c4dc7d8..cd8b0b8f67 100644 --- a/openair2/ENB_APP/flexran_agent_ran_api.c +++ b/openair2/ENB_APP/flexran_agent_ran_api.c @@ -3018,142 +3018,44 @@ int flexran_get_ue_dl_slice_id(mid_t mod_id, mid_t ue_id) { return 0; } -void flexran_set_ue_dl_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx) { - if (!mac_is_present(mod_id)) return; -} - int flexran_get_ue_ul_slice_id(mid_t mod_id, mid_t ue_id) { if (!mac_is_present(mod_id)) return -1; return 0; } -void flexran_set_ue_ul_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx) { - if (!mac_is_present(mod_id)) return; -} - -int flexran_dl_slice_exists(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return 0; -} - +/* TODO */ int flexran_create_dl_slice(mid_t mod_id, slice_id_t slice_id) { if (!mac_is_present(mod_id)) return -1; return -1; } +/* TODO */ +int flexran_remove_dl_slice(mid_t mod_id, int slice_idx) { + if (!mac_is_present(mod_id)) return -1; + return -1; +} + int flexran_find_dl_slice(mid_t mod_id, slice_id_t slice_id) { if (!mac_is_present(mod_id)) return -1; return -1; } -int flexran_remove_dl_slice(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} +//int flexran_get_dl_slice(mid_t mod_id, int slice_idx, Protocol__FlexSlice *s) { +//} int flexran_get_num_dl_slices(mid_t mod_id) { if (!mac_is_present(mod_id)) return -1; return 0; } -int flexran_get_intraslice_sharing_active(mid_t mod_id) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} -void flexran_set_intraslice_sharing_active(mid_t mod_id, int intraslice_active) { +/* TODO */ +void flexran_create_ul_slice(mid_t mod_id, slice_id_t slice_id) { if (!mac_is_present(mod_id)) return; + return; } -int flexran_get_interslice_sharing_active(mid_t mod_id) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} -void flexran_set_interslice_sharing_active(mid_t mod_id, int interslice_active) { - if (!mac_is_present(mod_id)) return; -} - -slice_id_t flexran_get_dl_slice_id(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} -void flexran_set_dl_slice_id(mid_t mod_id, int slice_idx, slice_id_t slice_id) { - if (!mac_is_present(mod_id)) return; -} - -int flexran_get_dl_slice_percentage(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} -void flexran_set_dl_slice_percentage(mid_t mod_id, int slice_idx, int percentage) { - if (!mac_is_present(mod_id)) return; -} - -int flexran_get_dl_slice_isolation(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} -void flexran_set_dl_slice_isolation(mid_t mod_id, int slice_idx, int is_isolated) { - if (!mac_is_present(mod_id)) return; -} - -int flexran_get_dl_slice_priority(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} -void flexran_set_dl_slice_priority(mid_t mod_id, int slice_idx, int priority) { - if (!mac_is_present(mod_id)) return; -} - -int flexran_get_dl_slice_position_low(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} -void flexran_set_dl_slice_position_low(mid_t mod_id, int slice_idx, int poslow) { - if (!mac_is_present(mod_id)) return; -} - -int flexran_get_dl_slice_position_high(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} -void flexran_set_dl_slice_position_high(mid_t mod_id, int slice_idx, int poshigh) { - if (!mac_is_present(mod_id)) return; -} - -int flexran_get_dl_slice_maxmcs(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} -void flexran_set_dl_slice_maxmcs(mid_t mod_id, int slice_idx, int maxmcs) { - if (!mac_is_present(mod_id)) return; -} - -int flexran_get_dl_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexDlSorting **sorting_list) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} -void flexran_set_dl_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexDlSorting *sorting_list, int n) { - if (!mac_is_present(mod_id)) return; -} - -Protocol__FlexDlAccountingPolicy flexran_get_dl_slice_accounting_policy(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_FAIR; - return PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_FAIR; -} -void flexran_set_dl_slice_accounting_policy(mid_t mod_id, int slice_idx, Protocol__FlexDlAccountingPolicy accounting) { - if (!mac_is_present(mod_id)) return; -} - -char *flexran_get_dl_slice_scheduler(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return NULL; - return NULL; -} -int flexran_set_dl_slice_scheduler(mid_t mod_id, int slice_idx, char *name) { - if (!mac_is_present(mod_id)) return 0; - return 0; -} - -int flexran_create_ul_slice(mid_t mod_id, slice_id_t slice_id) { +/* TODO */ +int flexran_remove_ul_slice(mid_t mod_id, int slice_idx) { if (!mac_is_present(mod_id)) return -1; return -1; } @@ -3163,62 +3065,14 @@ int flexran_find_ul_slice(mid_t mod_id, slice_id_t slice_id) { return -1; } -int flexran_remove_ul_slice(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} +//int flexran_get_ul_slice(mid_t mod_id, int slice_idx, Protocol__FlexSlice *s) { +//} int flexran_get_num_ul_slices(mid_t mod_id) { if (!mac_is_present(mod_id)) return -1; return 0; } -int flexran_ul_slice_exists(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return 0; -} - -slice_id_t flexran_get_ul_slice_id(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} -void flexran_set_ul_slice_id(mid_t mod_id, int slice_idx, slice_id_t slice_id) { - if (!mac_is_present(mod_id)) return; -} - -int flexran_get_ul_slice_percentage(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} -void flexran_set_ul_slice_percentage(mid_t mod_id, int slice_idx, int percentage) { - if (!mac_is_present(mod_id)) return; -} - -int flexran_get_ul_slice_first_rb(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} - -void flexran_set_ul_slice_first_rb(mid_t mod_id, int slice_idx, int first_rb) { - if (!mac_is_present(mod_id)) return; -} - -int flexran_get_ul_slice_maxmcs(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; -} -void flexran_set_ul_slice_maxmcs(mid_t mod_id, int slice_idx, int maxmcs) { - if (!mac_is_present(mod_id)) return; -} - -char *flexran_get_ul_slice_scheduler(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return NULL; - return ""; -} -int flexran_set_ul_slice_scheduler(mid_t mod_id, int slice_idx, char *name) { - if (!mac_is_present(mod_id)) return 0; - return 0; -} /************************** S1AP **************************/ int flexran_get_s1ap_mme_pending(mid_t mod_id){ diff --git a/openair2/ENB_APP/flexran_agent_ran_api.h b/openair2/ENB_APP/flexran_agent_ran_api.h index 9d1bfb9d3e..c29ba53c11 100644 --- a/openair2/ENB_APP/flexran_agent_ran_api.h +++ b/openair2/ENB_APP/flexran_agent_ran_api.h @@ -659,153 +659,38 @@ uint32_t flexran_get_rrc_enb_ue_s1ap_id(mid_t mod_id, rnti_t rnti); /* Get the DL slice ID for a UE */ int flexran_get_ue_dl_slice_id(mid_t mod_id, mid_t ue_id); - /* Set the DL slice index(!) for a UE */ -void flexran_set_ue_dl_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx); +//void flexran_set_ue_dl_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx); /* Get the UL slice ID for a UE */ int flexran_get_ue_ul_slice_id(mid_t mod_id, mid_t ue_id); - /* Set the UL slice index(!) for a UE */ -void flexran_set_ue_ul_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx); +//void flexran_set_ue_ul_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx); -/* Whether intraslice sharing is active, return boolean */ -int flexran_get_intraslice_sharing_active(mid_t mod_id); -/* Set whether intraslice sharing is active */ -void flexran_set_intraslice_sharing_active(mid_t mod_id, int intraslice_active); - -/* Whether intraslice sharing is active, return boolean */ -int flexran_get_interslice_sharing_active(mid_t mod_id); -/* Set whether intraslice sharing is active */ -void flexran_set_interslice_sharing_active(mid_t mod_id, int interslice_active); +/* Create slice in DL, returns the new slice index */ +//int flexran_create_dl_slice(mid_t mod_id, slice_id_t slice_id); +/* Remove slice in DL, returns new number of slices or -1 on error */ +//int flexran_remove_dl_slice(mid_t mod_id, int slice_idx); +/* Finds slice in DL with given slice_id and returns slice index */ +int flexran_find_dl_slice(mid_t mod_id, slice_id_t slice_id); +/* Return the parameters of slice at index slice_idx */ +//void flexran_get_dl_slice(mid_t mod_id, int slice_idx, Protocol__FlexSlice *s); /* Get the number of slices in DL */ int flexran_get_num_dl_slices(mid_t mod_id); -/* Query slice existence in DL. Return is boolean value */ -int flexran_dl_slice_exists(mid_t mod_id, int slice_idx); +/* Create slice in UL, returns the new slice index */ +//int flexran_create_ul_slice(mid_t mod_id, slice_id_t slice_id); +/* Remove slice in UL */ +//int flexran_remove_ul_slice(mid_t mod_id, int slice_idx); -/* Create slice in DL, returns the new slice index */ -int flexran_create_dl_slice(mid_t mod_id, slice_id_t slice_id); /* Finds slice in DL with given slice_id and returns slice index */ -int flexran_find_dl_slice(mid_t mod_id, slice_id_t slice_id); -/* Remove slice in DL, returns new number of slices or -1 on error */ -int flexran_remove_dl_slice(mid_t mod_id, int slice_idx); - -/* Get the ID of a slice in DL */ -slice_id_t flexran_get_dl_slice_id(mid_t mod_id, int slice_idx); -/* Set the ID of a slice in DL */ -void flexran_set_dl_slice_id(mid_t mod_id, int slice_idx, slice_id_t slice_id); - -/* Get the RB share a slice in DL, value 0-100 */ -int flexran_get_dl_slice_percentage(mid_t mod_id, int slice_idx); -/* Set the RB share a slice in DL, value 0-100 */ -void flexran_set_dl_slice_percentage(mid_t mod_id, int slice_idx, int percentage); - -/* Whether a slice in DL is isolated */ -int flexran_get_dl_slice_isolation(mid_t mod_id, int slice_idx); -/* Set whether a slice in DL is isolated */ -void flexran_set_dl_slice_isolation(mid_t mod_id, int slice_idx, int is_isolated); - -/* Get the priority of a slice in DL */ -int flexran_get_dl_slice_priority(mid_t mod_id, int slice_idx); -/* Get the priority of a slice in DL */ -void flexran_set_dl_slice_priority(mid_t mod_id, int slice_idx, int priority); - -/* Get the lower end of the frequency range for the slice positioning in DL */ -int flexran_get_dl_slice_position_low(mid_t mod_id, int slice_idx); -/* Set the lower end of the frequency range for the slice positioning in DL */ -void flexran_set_dl_slice_position_low(mid_t mod_id, int slice_idx, int poslow); - -/* Get the higher end of the frequency range for the slice positioning in DL */ -int flexran_get_dl_slice_position_high(mid_t mod_id, int slice_idx); -/* Set the higher end of the frequency range for the slice positioning in DL */ -void flexran_set_dl_slice_position_high(mid_t mod_id, int slice_idx, int poshigh); - -/* Get the maximum MCS for slice in DL */ -int flexran_get_dl_slice_maxmcs(mid_t mod_id, int slice_idx); -/* Set the maximum MCS for slice in DL */ -void flexran_set_dl_slice_maxmcs(mid_t mod_id, int slice_idx, int maxmcs); - -/* Get the sorting order of a slice in DL, return value is number of elements - * in sorting_list */ -int flexran_get_dl_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexDlSorting **sorting_list); -/* Set the sorting order of a slice in DL */ -void flexran_set_dl_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexDlSorting *sorting_list, int n); - -/* Get the accounting policy for a slice in DL */ -Protocol__FlexDlAccountingPolicy flexran_get_dl_slice_accounting_policy(mid_t mod_id, int slice_idx); -/* Set the accounting policy for a slice in DL */ -void flexran_set_dl_slice_accounting_policy(mid_t mod_id, int slice_idx, Protocol__FlexDlAccountingPolicy accounting); - -/* Get the scheduler name for a slice in DL */ -char *flexran_get_dl_slice_scheduler(mid_t mod_id, int slice_idx); -/* Set the scheduler name for a slice in DL */ -int flexran_set_dl_slice_scheduler(mid_t mod_id, int slice_idx, char *name); - +int flexran_find_ul_slice(mid_t mod_id, slice_id_t slice_id); +/* Return the parameters of slice at index slice_idx */ +//void flexran_get_ul_slice(mid_t mod_id, int slice_idx, Protocol__FlexSlice *s); /* Get the number of slices in UL */ int flexran_get_num_ul_slices(mid_t mod_id); -/* Query slice existence in UL. Return is boolean value */ -int flexran_ul_slice_exists(mid_t mod_id, int slice_idx); - -/* Create slice in UL, returns the new slice index */ -int flexran_create_ul_slice(mid_t mod_id, slice_id_t slice_id); -/* Finds slice in UL with given slice_id and returns slice index */ -int flexran_find_ul_slice(mid_t mod_id, slice_id_t slice_id); -/* Remove slice in UL */ -int flexran_remove_ul_slice(mid_t mod_id, int slice_idx); - -/* Get the ID of a slice in UL */ -slice_id_t flexran_get_ul_slice_id(mid_t mod_id, int slice_idx); -/* Set the ID of a slice in UL */ -void flexran_set_ul_slice_id(mid_t mod_id, int slice_idx, slice_id_t slice_id); - -/* Get the RB share a slice in UL, value 0-100 */ -int flexran_get_ul_slice_percentage(mid_t mod_id, int slice_idx); -/* Set the RB share a slice in UL, value 0-100 */ -void flexran_set_ul_slice_percentage(mid_t mod_id, int slice_idx, int percentage); - -/* TODO Whether a slice in UL is isolated */ -/*int flexran_get_ul_slice_isolation(mid_t mod_id, int slice_idx);*/ -/* TODO Set whether a slice in UL is isolated */ -/*void flexran_set_ul_slice_isolation(mid_t mod_id, int slice_idx, int is_isolated);*/ - -/* TODO Get the priority of a slice in UL */ -/*int flexran_get_ul_slice_priority(mid_t mod_id, int slice_idx);*/ -/* TODO Set the priority of a slice in UL */ -/*void flexran_set_ul_slice_priority(mid_t mod_id, int slice_idx, int priority);*/ - -/* Get the first RB for allocation in a slice in UL */ -int flexran_get_ul_slice_first_rb(mid_t mod_id, int slice_idx); -/* Set the first RB for allocation in a slice in UL */ -void flexran_set_ul_slice_first_rb(mid_t mod_id, int slice_idx, int first_rb); - -/* TODO Get the number of RB for the allocation in a slice in UL */ -/*int flexran_get_ul_slice_length_rb(mid_t mod_id, int slice_idx);*/ -/* TODO Set the of number of RB for the allocation in a slice in UL */ -/*void flexran_set_ul_slice_length_rb(mid_t mod_id, int slice_idx, int poshigh);*/ - -/* Get the maximum MCS for slice in UL */ -int flexran_get_ul_slice_maxmcs(mid_t mod_id, int slice_idx); -/* Set the maximum MCS for slice in UL */ -void flexran_set_ul_slice_maxmcs(mid_t mod_id, int slice_idx, int maxmcs); - -/* TODO Get the sorting order of a slice in UL, return value is number of elements - * in sorting_list */ -/*int flexran_get_ul_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexUlSorting **sorting_list);*/ -/* TODO Set the sorting order of a slice in UL */ -/*void flexran_set_ul_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexUlSorting *sorting_list, int n);*/ - -/* TODO Get the accounting policy for a slice in UL */ -/*Protocol__UlAccountingPolicy flexran_get_ul_slice_accounting_policy(mid_t mod_id, int slice_idx);*/ -/* TODO Set the accounting policy for a slice in UL */ -/*void flexran_get_ul_slice_accounting_policy(mid_t mod_id, int slice_idx, Protocol__UlAccountingPolicy accountin);*/ - -/* Get the scheduler name for a slice in UL */ -char *flexran_get_ul_slice_scheduler(mid_t mod_id, int slice_idx); -/* Set the scheduler name for a slice in UL */ -int flexran_set_ul_slice_scheduler(mid_t mod_id, int slice_idx, char *name); /************************** S1AP **************************/ /* Get the number of MMEs to be connected */ From 2b4e52906879d1001380679aac92306121946793 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Sun, 12 Apr 2020 15:16:21 +0200 Subject: [PATCH 497/553] Simplify add_ue_list(), remove_ue_list(); add init_ue_list() --- .../LAYER2/MAC/eNB_scheduler_primitives.c | 43 ++++++++++--------- openair2/LAYER2/MAC/mac_proto.h | 1 + openair2/LAYER2/MAC/main.c | 5 +-- 3 files changed, 25 insertions(+), 24 deletions(-) diff --git a/openair2/LAYER2/MAC/eNB_scheduler_primitives.c b/openair2/LAYER2/MAC/eNB_scheduler_primitives.c index 78d6f6a3d7..b75ab774c6 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_primitives.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_primitives.c @@ -2131,33 +2131,36 @@ dump_ue_list(UE_list_t *listP) { * Add a UE to UE_list listP */ inline void add_ue_list(UE_list_t *listP, int UE_id) { - if (listP->head == -1) { - listP->head = UE_id; - listP->next[UE_id] = -1; - } else { - int i = listP->head; - while (listP->next[i] >= 0) - i = listP->next[i]; - listP->next[i] = UE_id; - listP->next[UE_id] = -1; - } + int *cur = &listP->head; + while (*cur >= 0) + cur = &listP->next[*cur]; + *cur = UE_id; } //------------------------------------------------------------------------------ /* - * Remove a UE from the UE_list listP, return the previous element + * Remove a UE from the UE_list listP */ inline int remove_ue_list(UE_list_t *listP, int UE_id) { - listP->next[UE_id] = -1; - if (listP->head == UE_id) { - listP->head = listP->next[UE_id]; - return -1; - } + int *cur = &listP->head; + while (*cur != -1 && *cur != UE_id) + cur = &listP->next[*cur]; + if (*cur == -1) + return 0; + int *next = &listP->next[*cur]; + *cur = listP->next[*cur]; + *next = -1; + return 1; +} - int previous = prev(listP, UE_id); - if (previous != -1) - listP->next[previous] = listP->next[UE_id]; - return previous; +//------------------------------------------------------------------------------ +/* + * Initialize the UE_list listP + */ +inline void init_ue_list(UE_list_t *listP) { + listP->head = -1; + for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) + listP->next[i] = -1; } //------------------------------------------------------------------------------ diff --git a/openair2/LAYER2/MAC/mac_proto.h b/openair2/LAYER2/MAC/mac_proto.h index 61251ef088..818eb834fb 100644 --- a/openair2/LAYER2/MAC/mac_proto.h +++ b/openair2/LAYER2/MAC/mac_proto.h @@ -659,6 +659,7 @@ int prev(UE_list_t *listP, int nodeP); void add_ue_list(UE_list_t *listP, int UE_id); int remove_ue_list(UE_list_t *listP, int UE_id); void dump_ue_list(UE_list_t *listP); +void init_ue_list(UE_list_t *listP); int UE_num_active_CC(UE_info_t *listP, int ue_idP); int UE_PCCID(module_id_t mod_idP, int ue_idP); rnti_t UE_RNTI(module_id_t mod_idP, int ue_idP); diff --git a/openair2/LAYER2/MAC/main.c b/openair2/LAYER2/MAC/main.c index 35b5136889..659c7250e8 100644 --- a/openair2/LAYER2/MAC/main.c +++ b/openair2/LAYER2/MAC/main.c @@ -45,11 +45,8 @@ extern RAN_CONTEXT_t RC; void init_UE_info(UE_info_t *UE_info) { - int list_el; UE_info->num_UEs = 0; - UE_info->list.head = -1; - for (list_el = 0; list_el < MAX_MOBILES_PER_ENB; list_el++) - UE_info->list.next[list_el] = -1; + init_ue_list(&UE_info->list); memset(UE_info->DLSCH_pdu, 0, sizeof(UE_info->DLSCH_pdu)); memset(UE_info->UE_template, 0, sizeof(UE_info->UE_template)); memset(UE_info->eNB_UE_stats, 0, sizeof(UE_info->eNB_UE_stats)); From 9956b96049a32ec9ccb3aa9e78ff6aa0008044f8 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Sun, 12 Apr 2020 14:38:05 +0200 Subject: [PATCH 498/553] Use fptr for preproc and align UL PP definition --- openair2/ENB_APP/enb_config.c | 9 +-- openair2/LAYER2/MAC/eNB_scheduler_dlsch.c | 5 +- .../LAYER2/MAC/eNB_scheduler_primitives.c | 12 ++++ openair2/LAYER2/MAC/eNB_scheduler_ulsch.c | 4 +- openair2/LAYER2/MAC/mac.h | 59 +++++++++++++++++-- openair2/LAYER2/MAC/mac_proto.h | 6 +- openair2/LAYER2/MAC/main.c | 13 ++-- openair2/LAYER2/MAC/pre_processor.c | 46 +++++++-------- 8 files changed, 110 insertions(+), 44 deletions(-) diff --git a/openair2/ENB_APP/enb_config.c b/openair2/ENB_APP/enb_config.c index 0308c2fd79..1d189832b4 100644 --- a/openair2/ENB_APP/enb_config.c +++ b/openair2/ENB_APP/enb_config.c @@ -266,10 +266,11 @@ void RCconfig_macrlc(int macrlc_has_f1[MAX_MAC_INST]) { void *d = dlsym(NULL, s); AssertFatal(d, "%s(): no default scheduler DL algo '%s' found\n", __func__, s); // release default, add new - RC.mac[j]->dl_algo.unset(&RC.mac[j]->dl_algo.data); - RC.mac[j]->dl_algo = *(default_sched_dl_algo_t *) d; - RC.mac[j]->dl_algo.data = RC.mac[j]->dl_algo.setup(); - LOG_I(ENB_APP, "using default scheduler DL algo '%s'\n", RC.mac[j]->dl_algo.name); + pp_impl_param_t *dl_pp = &RC.mac[j]->pre_processor_dl; + dl_pp->dl_algo.unset(&dl_pp->dl_algo.data); + dl_pp->dl_algo = *(default_sched_dl_algo_t *) d; + dl_pp->dl_algo.data = dl_pp->dl_algo.setup(); + LOG_I(ENB_APP, "using default scheduler DL algo '%s'\n", dl_pp->dl_algo.name); }// j=0..num_inst } /*else {// MacRLC_ParamList.numelt > 0 // ignore it diff --git a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c index 783d4e8b1a..1f99f50ece 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c @@ -573,10 +573,7 @@ schedule_ue_spec(module_id_t module_idP, VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DLSCH_PREPROCESSOR, VCD_FUNCTION_IN); start_meas(&eNB->schedule_dlsch_preprocessor); - dlsch_scheduler_pre_processor(module_idP, - CC_id, - frameP, - subframeP); + eNB->pre_processor_dl.dl(module_idP, CC_id, frameP, subframeP); stop_meas(&eNB->schedule_dlsch_preprocessor); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DLSCH_PREPROCESSOR, VCD_FUNCTION_OUT); diff --git a/openair2/LAYER2/MAC/eNB_scheduler_primitives.c b/openair2/LAYER2/MAC/eNB_scheduler_primitives.c index b75ab774c6..89c2ecc83d 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_primitives.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_primitives.c @@ -2199,6 +2199,12 @@ add_new_ue(module_id_t mod_idP, UE_info->active[UE_id] = TRUE; add_ue_list(&UE_info->list, UE_id); dump_ue_list(&UE_info->list); + pp_impl_param_t* dl = &RC.mac[mod_idP]->pre_processor_dl; + if (dl->slices) // inform slice implementation about new UE + dl->add_UE(dl->slices, UE_id); + pp_impl_param_t* ul = &RC.mac[mod_idP]->pre_processor_ul; + if (ul->slices) // inform slice implementation about new UE + ul->add_UE(ul->slices, UE_id); if (IS_SOFTMODEM_IQPLAYER)// not specific to record/playback ? UE_info->UE_template[cc_idP][UE_id].pre_assigned_mcs_ul = 0; UE_info->UE_template[cc_idP][UE_id].rach_resource_type = rach_resource_type; @@ -2262,6 +2268,12 @@ rrc_mac_remove_ue(module_id_t mod_idP, UE_info->num_UEs--; remove_ue_list(&UE_info->list, UE_id); + pp_impl_param_t* dl = &RC.mac[mod_idP]->pre_processor_dl; + if (dl->slices) // inform slice implementation about new UE + dl->remove_UE(dl->slices, UE_id); + pp_impl_param_t* ul = &RC.mac[mod_idP]->pre_processor_ul; + if (ul->slices) // inform slice implementation about new UE + ul->remove_UE(ul->slices, UE_id); /* Clear all remaining pending transmissions */ memset(&UE_info->UE_template[pCC_id][UE_id], 0, sizeof(UE_TEMPLATE)); diff --git a/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c b/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c index 3062e5c964..2de45db856 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c @@ -1301,11 +1301,11 @@ schedule_ulsch_rnti(module_id_t module_idP, /* * ULSCH preprocessor: set UE_template-> - * pre_allocated_nb_rb_ul[slice_idx] + * pre_allocated_nb_rb_ul * pre_assigned_mcs_ul * pre_allocated_rb_table_index_ul */ - ulsch_scheduler_pre_processor(module_idP, CC_id, frameP, subframeP, sched_frame, sched_subframeP); + mac->pre_processor_ul.ul(module_idP, CC_id, frameP, subframeP, sched_frame, sched_subframeP); for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { if (UE_info->UE_template[CC_id][UE_id].rach_resource_type > 0) diff --git a/openair2/LAYER2/MAC/mac.h b/openair2/LAYER2/MAC/mac.h index 8349d84d48..faefc481f6 100644 --- a/openair2/LAYER2/MAC/mac.h +++ b/openair2/LAYER2/MAC/mac.h @@ -540,7 +540,6 @@ typedef enum { SCHED_MODE_FAIR_RR /// fair raund robin } SCHEDULER_MODES; - /*! \brief temporary struct for ULSCH sched */ typedef struct { rnti_t rnti; @@ -1199,6 +1198,56 @@ typedef struct { void *data; } default_sched_ul_algo_t; +typedef void (*pp_impl_dl)(module_id_t mod_id, + int CC_id, + frame_t frame, + sub_frame_t subframe); +typedef void (*pp_impl_ul)(module_id_t mod_id, + int CC_id, + frame_t frame, + sub_frame_t subframe, + frame_t sched_frame, + sub_frame_t sched_subframe); + +struct slice_info_s; +typedef struct { + int algorithm; + + /// inform the slice algorithm about a new UE + void (*add_UE)(struct slice_info_s *s, int UE_id); + /// inform the slice algorithm about a UE that disconnected + void (*remove_UE)(struct slice_info_s *s, int UE_id); + /// move a UE to a slice in DL/UL, -1 means don't move (no-op). + void (*move_UE)(struct slice_info_s *s, int UE_id, int idx); + + /// Adds a new slice through admission control. slice_params are + /// algorithm-specific parameters. sched is either a default_sched_ul_algo_t + /// or default_sched_dl_algo_t, depending on whether this implementation + /// handles UL/DL. If slice at index exists, updates existing + /// slice. Returns index of new slice or -1 on failure. + int (*addmod_slice)(struct slice_info_s *s, + int id, + char *label, + void *sched, + void *slice_params); + /// Returns slice through slice_idx. 1 if successful, 0 if not. + int (*remove_slice)(struct slice_info_s *s, uint8_t slice_idx); + + union { + pp_impl_dl dl; + pp_impl_ul ul; + }; + + union { + default_sched_ul_algo_t ul_algo; + default_sched_dl_algo_t dl_algo; + }; + + void (*destroy)(struct slice_info_s **s); + + struct slice_info_s *slices; +} pp_impl_param_t; + /*! \brief eNB common channels */ typedef struct { int physCellId; @@ -1354,9 +1403,11 @@ typedef struct eNB_MAC_INST_s { UE_free_list_t UE_free_list; /// for scheduling selection SCHEDULER_MODES scheduler_mode; - /// scheduling algorithm used in default scheduler - default_sched_dl_algo_t dl_algo; - default_sched_ul_algo_t ul_algo; + /// Default scheduler: Pre-processor implementation. Algorithms for UL/DL + /// are called by ULSCH/DLSCH, respectively. Pro-processor implementation can + /// encapsulate slicing. + pp_impl_param_t pre_processor_dl; + pp_impl_param_t pre_processor_ul; int32_t puSch10xSnr; int32_t puCch10xSnr; diff --git a/openair2/LAYER2/MAC/mac_proto.h b/openair2/LAYER2/MAC/mac_proto.h index 818eb834fb..9d49fdffd5 100644 --- a/openair2/LAYER2/MAC/mac_proto.h +++ b/openair2/LAYER2/MAC/mac_proto.h @@ -674,10 +674,10 @@ void set_ul_DAI(int module_idP, void ulsch_scheduler_pre_processor(module_id_t module_idP, int CC_id, - int frameP, + frame_t frameP, sub_frame_t subframeP, - int sched_frameP, - unsigned char sched_subframeP); + frame_t sched_frameP, + sub_frame_t sched_subframeP); int phy_stats_exist(module_id_t Mod_id, int rnti); diff --git a/openair2/LAYER2/MAC/main.c b/openair2/LAYER2/MAC/main.c index 659c7250e8..24038e60d5 100644 --- a/openair2/LAYER2/MAC/main.c +++ b/openair2/LAYER2/MAC/main.c @@ -99,16 +99,21 @@ void mac_top_init_eNB(void) } mac[i]->if_inst = IF_Module_init(i); + + mac[i]->pre_processor_dl.dl = dlsch_scheduler_pre_processor; char *s = "round_robin_dl"; void *d = dlsym(NULL, s); AssertFatal(d, "%s(): no scheduler algo '%s' found\n", __func__, s); - mac[i]->dl_algo = *(default_sched_dl_algo_t *) d; - mac[i]->dl_algo.data = mac[i]->dl_algo.setup(); + mac[i]->pre_processor_dl.dl_algo = *(default_sched_dl_algo_t *) d; + mac[i]->pre_processor_dl.dl_algo.data = mac[i]->pre_processor_dl.dl_algo.setup(); + + mac[i]->pre_processor_ul.ul = ulsch_scheduler_pre_processor; s = "round_robin_ul"; d = dlsym(NULL, s); AssertFatal(d, "%s(): no scheduler algo '%s' found\n", __func__, s); - mac[i]->ul_algo = *(default_sched_ul_algo_t *) d; - mac[i]->ul_algo.data = mac[i]->ul_algo.setup(); + mac[i]->pre_processor_ul.ul_algo = *(default_sched_ul_algo_t *) d; + mac[i]->pre_processor_ul.ul_algo.data = mac[i]->pre_processor_ul.ul_algo.setup(); + init_UE_info(&mac[i]->UE_info); } diff --git a/openair2/LAYER2/MAC/pre_processor.c b/openair2/LAYER2/MAC/pre_processor.c index d7dfc7816a..6477d60021 100644 --- a/openair2/LAYER2/MAC/pre_processor.c +++ b/openair2/LAYER2/MAC/pre_processor.c @@ -703,15 +703,15 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id, n_rbg_sched += rbgalloc_mask[i]; } - mac->dl_algo.run(Mod_id, - CC_id, - frameP, - subframeP, - &UE_to_sched, - 4, // max_num_ue - n_rbg_sched, - rbgalloc_mask, - mac->dl_algo.data); + mac->pre_processor_dl.dl_algo.run(Mod_id, + CC_id, + frameP, + subframeP, + &UE_to_sched, + 4, // max_num_ue + n_rbg_sched, + rbgalloc_mask, + mac->pre_processor_dl.dl_algo.data); // the following block is meant for validation of the pre-processor to check // whether all UE allocations are non-overlapping and is not necessary for @@ -1080,10 +1080,10 @@ default_sched_ul_algo_t round_robin_ul = { void ulsch_scheduler_pre_processor(module_id_t Mod_id, int CC_id, - int frameP, + frame_t frameP, sub_frame_t subframeP, - int sched_frameP, - unsigned char sched_subframeP) { + frame_t sched_frameP, + sub_frame_t sched_subframeP) { eNB_MAC_INST *mac = RC.mac[Mod_id]; UE_info_t *UE_info = &mac->UE_info; const int N_RB_UL = to_prb(mac->common_channels[CC_id].ul_Bandwidth); @@ -1140,17 +1140,17 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id, } } - mac->ul_algo.run(Mod_id, - CC_id, - frameP, - subframeP, - sched_frameP, - sched_subframeP, - &UE_to_sched, - 4, // max_num_ue - n_contig, - rbs, - mac->ul_algo.data); + mac->pre_processor_ul.ul_algo.run(Mod_id, + CC_id, + frameP, + subframeP, + sched_frameP, + sched_subframeP, + &UE_to_sched, + 4, // max_num_ue + n_contig, + rbs, + mac->pre_processor_ul.ul_algo.data); // the following block is meant for validation of the pre-processor to check // whether all UE allocations are non-overlapping and is not necessary for From 872cfc03fe2323f708acbc7008f3d4294f3df2de Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Sun, 12 Apr 2020 18:33:55 +0200 Subject: [PATCH 499/553] Implement Static Slicing --- cmake_targets/CMakeLists.txt | 1 + openair2/LAYER2/MAC/slicing/slicing.c | 586 ++++++++++++++++++ openair2/LAYER2/MAC/slicing/slicing.h | 74 +++ .../LAYER2/MAC/slicing/slicing_internal.h | 46 ++ 4 files changed, 707 insertions(+) create mode 100644 openair2/LAYER2/MAC/slicing/slicing.c create mode 100644 openair2/LAYER2/MAC/slicing/slicing.h create mode 100644 openair2/LAYER2/MAC/slicing/slicing_internal.h diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index 7e59f38e8d..0b60172747 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -1830,6 +1830,7 @@ set (MAC_SRC ${MAC_DIR}/eNB_scheduler_fairRR.c ${MAC_DIR}/eNB_scheduler_phytest.c ${MAC_DIR}/pre_processor.c + ${MAC_DIR}/slicing/slicing.c ${MAC_DIR}/config.c ${MAC_DIR}/config_ue.c ) diff --git a/openair2/LAYER2/MAC/slicing/slicing.c b/openair2/LAYER2/MAC/slicing/slicing.c new file mode 100644 index 0000000000..a1de326df0 --- /dev/null +++ b/openair2/LAYER2/MAC/slicing/slicing.c @@ -0,0 +1,586 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! + * \file slicing.c + * \brief Generic slicing helper functions and Static Slicing Implementation + * \author Robert Schmidt + * \date 2020 + * \email robert.schmidt@eurecom.fr + */ + +#define _GNU_SOURCE +#include +#include + +#include "assertions.h" +#include "common/utils/LOG/log.h" + +#include "slicing.h" +#include "slicing_internal.h" + +#include "common/ran_context.h" +extern RAN_CONTEXT_t RC; + +#define RET_FAIL(ret, x...) do { LOG_E(MAC, x); return ret; } while (0) + +int slicing_get_UE_slice_idx(slice_info_t *si, int UE_id) { + return si->UE_assoc_slice[UE_id]; +} + +void slicing_add_UE(slice_info_t *si, int UE_id) { + add_ue_list(&si->s[0]->UEs, UE_id); + si->UE_assoc_slice[UE_id] = 0; +} + +void _remove_UE(slice_t **s, uint8_t *assoc, int UE_id) { + const uint8_t i = assoc[UE_id]; + DevAssert(remove_ue_list(&s[i]->UEs, UE_id)); + assoc[UE_id] = -1; +} + +void slicing_remove_UE(slice_info_t *si, int UE_id) { + _remove_UE(si->s, si->UE_assoc_slice, UE_id); +} + +void _move_UE(slice_t **s, uint8_t *assoc, int UE_id, int to) { + const uint8_t i = assoc[UE_id]; + const int ri = remove_ue_list(&s[i]->UEs, UE_id); + if (!ri) + LOG_W(MAC, "did not find UE %d in DL slice index %d\n", UE_id, i); + add_ue_list(&s[to]->UEs, UE_id); + assoc[UE_id] = to; +} + +void slicing_move_UE(slice_info_t *si, int UE_id, int idx) { + DevAssert(idx >= -1 && idx < si->num); + if (idx >= 0) + _move_UE(si->s, si->UE_assoc_slice, UE_id, idx); +} + +int _exists_slice(uint8_t n, slice_t **s, int id) { + for (int i = 0; i < n; ++i) + if (s[i]->id == id) + return i; + return -1; +} + +slice_t *_add_slice(uint8_t *n, slice_t **s) { + s[*n] = calloc(1, sizeof(slice_t)); + if (!s[*n]) + return NULL; + init_ue_list(&s[*n]->UEs); + *n += 1; + return s[*n - 1]; +} + +slice_t *_remove_slice(uint8_t *n, slice_t **s, uint8_t *assoc, int idx) { + if (idx >= *n) + return NULL; + + slice_t *sr = s[idx]; + while (sr->UEs.head >= 0) + _move_UE(s, assoc, sr->UEs.head, 0); + + for (int i = idx + 1; i < *n; ++i) + s[i - 1] = s[i]; + *n -= 1; + s[*n] = NULL; + + for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) + if (assoc[i] > idx) + assoc[i] -= 1; + + if (sr->label) + free(sr->label); + + return sr; +} + +/************************ Static Slicing Implementation ************************/ + +int addmod_static_slice_dl(slice_info_t *si, + int id, + char *label, + void *algo, + void *slice_params_dl) { + static_slice_param_t *dl = slice_params_dl; + if (dl && dl->posLow > dl->posHigh) + RET_FAIL(-1, "%s(): slice id %d posLow > posHigh\n", __func__, id); + + uint8_t rbgMap[25] = { 0 }; + int index = _exists_slice(si->num, si->s, id); + if (index >= 0) { + for (int s = 0; s < si->num; ++s) { + static_slice_param_t *sd = dl && si->s[s]->id == id ? dl : si->s[s]->algo_data; + for (int i = sd->posLow; i <= sd->posHigh; ++i) { + if (rbgMap[i]) + RET_FAIL(-33, "%s(): overlap of slices detected at RBG %d\n", __func__, i); + rbgMap[i] = 1; + } + } + /* no problem, can allocate */ + slice_t *s = si->s[index]; + if (label) { + if (s->label) free(s->label); + s->label = label; + } + if (algo) { + s->dl_algo.unset(&s->dl_algo.data); + s->dl_algo = *(default_sched_dl_algo_t *) algo; + if (!s->dl_algo.data) + s->dl_algo.data = s->dl_algo.setup(); + } + if (dl) { + free(s->algo_data); + s->algo_data = dl; + } + return index; + } + + if (!dl) + RET_FAIL(-100, "%s(): no parameters for new slice %d, aborting\n", __func__, id); + + if (si->num >= MAX_STATIC_SLICES) + RET_FAIL(-2, "%s(): cannot have more than %d slices\n", __func__, MAX_STATIC_SLICES); + for (int s = 0; s < si->num; ++s) { + static_slice_param_t *sd = si->s[s]->algo_data; + for (int i = sd->posLow; i <= sd->posHigh; ++i) + rbgMap[i] = 1; + } + + for (int i = dl->posLow; i <= dl->posHigh; ++i) + if (rbgMap[i]) + RET_FAIL(-3, "%s(): overlap of slices detected at RBG %d\n", __func__, i); + + if (!algo) + RET_FAIL(-14, "%s(): no scheduler algorithm provided\n", __func__); + + slice_t *ns = _add_slice(&si->num, si->s); + if (!ns) + RET_FAIL(-4, "%s(): could not create new slice\n", __func__); + ns->id = id; + ns->label = label; + ns->dl_algo = *(default_sched_dl_algo_t *) algo; + if (!ns->dl_algo.data) + ns->dl_algo.data = ns->dl_algo.setup(); + ns->algo_data = dl; + + return si->num - 1; +} + +int addmod_static_slice_ul(slice_info_t *si, + int id, + char *label, + void *algo, + void *slice_params_ul) { + static_slice_param_t *ul = slice_params_ul; + /* Minimum 3RBs, because LTE stack requires this */ + if (ul && ul->posLow + 2 > ul->posHigh) + RET_FAIL(-1, "%s(): slice id %d posLow + 2 > posHigh\n", __func__, id); + + uint8_t rbMap[110] = { 0 }; + int index = _exists_slice(si->num, si->s, id); + if (index >= 0) { + for (int s = 0; s < si->num; ++s) { + static_slice_param_t *su = ul && si->s[s]->id == id && ul ? ul : si->s[s]->algo_data; + for (int i = su->posLow; i <= su->posHigh; ++i) { + if (rbMap[i]) + RET_FAIL(-33, "%s(): overlap of slices detected at RBG %d\n", __func__, i); + rbMap[i] = 1; + } + } + /* no problem, can allocate */ + slice_t *s = si->s[index]; + if (algo) { + s->ul_algo.unset(&s->ul_algo.data); + s->ul_algo = *(default_sched_ul_algo_t *) algo; + if (!s->ul_algo.data) + s->ul_algo.data = s->ul_algo.setup(); + } + if (label) { + if (s->label) free(s->label); + s->label = label; + } + if (ul) { + free(s->algo_data); + s->algo_data = ul; + } + return index; + } + + if (!ul) + RET_FAIL(-100, "%s(): no parameters for new slice %d, aborting\n", __func__, id); + + if (si->num >= MAX_STATIC_SLICES) + RET_FAIL(-2, "%s(): cannot have more than %d slices\n", __func__, MAX_STATIC_SLICES); + for (int s = 0; s < si->num; ++s) { + static_slice_param_t *sd = si->s[s]->algo_data; + for (int i = sd->posLow; i <= sd->posHigh; ++i) + rbMap[i] = 1; + } + + for (int i = ul->posLow; i <= ul->posHigh; ++i) + if (rbMap[i]) + RET_FAIL(-3, "%s(): overlap of slices detected at RBG %d\n", __func__, i); + + if (!algo) + RET_FAIL(-14, "%s(): no scheduler algorithm provided\n", __func__); + + slice_t *ns = _add_slice(&si->num, si->s); + if (!ns) + RET_FAIL(-4, "%s(): could not create new slice\n", __func__); + ns->id = id; + ns->label = label; + ns->ul_algo = *(default_sched_ul_algo_t *) algo; + if (!ns->ul_algo.data) + ns->ul_algo.data = ns->ul_algo.setup(); + ns->algo_data = ul; + + return si->num - 1; +} + +int remove_static_slice(slice_info_t *si, uint8_t slice_idx) { + if (slice_idx == 0) + return 0; + slice_t *sr = _remove_slice(&si->num, si->s, si->UE_assoc_slice, slice_idx); + if (!sr) + return 0; + free(sr->algo_data); + free(sr); + return 1; +} + +void static_dl(module_id_t mod_id, + int CC_id, + frame_t frame, + sub_frame_t subframe) { + UE_info_t *UE_info = &RC.mac[mod_id]->UE_info; + + store_dlsch_buffer(mod_id, CC_id, frame, subframe); + + for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { + UE_sched_ctrl_t *ue_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; + + /* initialize per-UE scheduling information */ + ue_sched_ctrl->pre_nb_available_rbs[CC_id] = 0; + ue_sched_ctrl->dl_pow_off[CC_id] = 2; + memset(ue_sched_ctrl->rballoc_sub_UE[CC_id], 0, sizeof(ue_sched_ctrl->rballoc_sub_UE[CC_id])); + ue_sched_ctrl->pre_dci_dl_pdu_idx = -1; + } + + const int N_RBG = to_rbg(RC.mac[mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth); + const int RBGsize = get_min_rb_unit(mod_id, CC_id); + uint8_t *vrb_map = RC.mac[mod_id]->common_channels[CC_id].vrb_map; + uint8_t rbgalloc_mask[N_RBG_MAX]; + for (int i = 0; i < N_RBG; i++) { + // calculate mask: init to one + "AND" with vrb_map: + // if any RB in vrb_map is blocked (1), the current RBG will be 0 + rbgalloc_mask[i] = 1; + for (int j = 0; j < RBGsize; j++) + rbgalloc_mask[i] &= !vrb_map[RBGsize * i + j]; + } + + slice_info_t *s = RC.mac[mod_id]->pre_processor_dl.slices; + int max_num_ue; + switch (s->num) { + case 1: + max_num_ue = 4; + break; + case 2: + max_num_ue = 2; + break; + default: + max_num_ue = 1; + break; + } + for (int i = 0; i < s->num; ++i) { + if (s->s[i]->UEs.head < 0) + continue; + uint8_t rbgalloc_slice_mask[N_RBG_MAX]; + memset(rbgalloc_slice_mask, 0, sizeof(rbgalloc_slice_mask)); + static_slice_param_t *p = s->s[i]->algo_data; + int n_rbg_sched = 0; + for (int rbg = p->posLow; rbg <= p->posHigh && rbg <= N_RBG; ++rbg) { + rbgalloc_slice_mask[rbg] = rbgalloc_mask[rbg]; + n_rbg_sched += rbgalloc_mask[rbg]; + } + + s->s[i]->dl_algo.run(mod_id, + CC_id, + frame, + subframe, + &s->s[i]->UEs, + max_num_ue, // max_num_ue + n_rbg_sched, + rbgalloc_slice_mask, + s->s[i]->dl_algo.data); + } + + // the following block is meant for validation of the pre-processor to check + // whether all UE allocations are non-overlapping and is not necessary for + // scheduling functionality + char t[26] = "_________________________"; + t[N_RBG] = 0; + for (int i = 0; i < N_RBG; i++) + for (int j = 0; j < RBGsize; j++) + if (vrb_map[RBGsize*i+j] != 0) + t[i] = 'x'; + int print = 0; + for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { + const UE_sched_ctrl_t *ue_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; + + if (ue_sched_ctrl->pre_nb_available_rbs[CC_id] == 0) + continue; + + LOG_D(MAC, + "%4d.%d UE%d %d RBs allocated, pre MCS %d\n", + frame, + subframe, + UE_id, + ue_sched_ctrl->pre_nb_available_rbs[CC_id], + UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1); + + print = 1; + + for (int i = 0; i < N_RBG; i++) { + if (!ue_sched_ctrl->rballoc_sub_UE[CC_id][i]) + continue; + for (int j = 0; j < RBGsize; j++) { + if (vrb_map[RBGsize*i+j] != 0) { + LOG_I(MAC, "%4d.%d DL scheduler allocation list: %s\n", frame, subframe, t); + LOG_E(MAC, "%4d.%d: UE %d allocated at locked RB %d/RBG %d\n", frame, + subframe, UE_id, RBGsize * i + j, i); + } + vrb_map[RBGsize*i+j] = 1; + } + t[i] = '0' + UE_id; + } + } + if (print) + LOG_D(MAC, "%4d.%d DL scheduler allocation list: %s\n", frame, subframe, t); +} + +void static_ul(module_id_t mod_id, + int CC_id, + frame_t frame, + sub_frame_t subframe, + frame_t sched_frame, + sub_frame_t sched_subframe) { + UE_info_t *UE_info = &RC.mac[mod_id]->UE_info; + const int N_RB_UL = to_prb(RC.mac[mod_id]->common_channels[CC_id].ul_Bandwidth); + COMMON_channels_t *cc = &RC.mac[mod_id]->common_channels[CC_id]; + + for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { + UE_TEMPLATE *UE_template = &UE_info->UE_template[CC_id][UE_id]; + UE_template->pre_assigned_mcs_ul = 0; + UE_template->pre_allocated_nb_rb_ul = 0; + UE_template->pre_allocated_rb_table_index_ul = -1; + UE_template->pre_first_nb_rb_ul = 0; + UE_template->pre_dci_ul_pdu_idx = -1; + } + + slice_info_t *s = RC.mac[mod_id]->pre_processor_ul.slices; + int max_num_ue; + switch (s->num) { + case 1: + max_num_ue = 4; + break; + case 2: + max_num_ue = 2; + break; + default: + max_num_ue = 1; + break; + } + for (int i = 0; i < s->num; ++i) { + if (s->s[i]->UEs.head < 0) + continue; + int last_rb_blocked = 1; + int n_contig = 0; + contig_rbs_t rbs[2]; // up to two contig RBs for PRACH in between + static_slice_param_t *p = s->s[i]->algo_data; + for (int rb = p->posLow; rb <= p->posHigh && rb < N_RB_UL; ++rb) { + if (cc->vrb_map_UL[rb] == 0 && last_rb_blocked) { + last_rb_blocked = 0; + n_contig++; + AssertFatal(n_contig <= 2, "cannot handle more than two contiguous RB regions\n"); + rbs[n_contig - 1].start = rb; + } + if (cc->vrb_map_UL[rb] == 1 && !last_rb_blocked) { + last_rb_blocked = 1; + rbs[n_contig - 1].length = rb - rbs[n_contig - 1].start; + } + } + if (!last_rb_blocked) + rbs[n_contig - 1].length = p->posHigh - rbs[n_contig - 1].start + 1; + + s->s[i]->ul_algo.run(mod_id, + CC_id, + frame, + subframe, + sched_frame, + sched_subframe, + &s->s[i]->UEs, + max_num_ue, // max_num_ue + n_contig, + rbs, + s->s[i]->ul_algo.data); + } + + // the following block is meant for validation of the pre-processor to check + // whether all UE allocations are non-overlapping and is not necessary for + // scheduling functionality + char t[101] = "__________________________________________________" + "__________________________________________________"; + t[N_RB_UL] = 0; + for (int j = 0; j < N_RB_UL; j++) + if (cc->vrb_map_UL[j] != 0) + t[j] = 'x'; + int print = 0; + for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) { + UE_TEMPLATE *UE_template = &UE_info->UE_template[CC_id][UE_id]; + if (UE_template->pre_allocated_nb_rb_ul == 0) + continue; + + print = 1; + uint8_t harq_pid = subframe2harqpid(&RC.mac[mod_id]->common_channels[CC_id], + sched_frame, sched_subframe); + LOG_D(MAC, "%4d.%d UE%d %d RBs (index %d) at start %d, pre MCS %d %s\n", + frame, + subframe, + UE_id, + UE_template->pre_allocated_nb_rb_ul, + UE_template->pre_allocated_rb_table_index_ul, + UE_template->pre_first_nb_rb_ul, + UE_template->pre_assigned_mcs_ul, + UE_info->UE_sched_ctrl[UE_id].round_UL[CC_id][harq_pid] > 0 ? "(retx)" : ""); + + for (int i = 0; i < UE_template->pre_allocated_nb_rb_ul; ++i) { + /* only check if this is not a retransmission */ + if (UE_info->UE_sched_ctrl[UE_id].round_UL[CC_id][harq_pid] == 0 + && cc->vrb_map_UL[UE_template->pre_first_nb_rb_ul + i] == 1) { + + LOG_I(MAC, "%4d.%d UL scheduler allocation list: %s\n", frame, subframe, t); + LOG_E(MAC, + "%4d.%d: UE %d allocated at locked RB %d (is: allocated start " + "%d/length %d)\n", + frame, subframe, UE_id, UE_template->pre_first_nb_rb_ul + i, + UE_template->pre_first_nb_rb_ul, + UE_template->pre_allocated_nb_rb_ul); + } + cc->vrb_map_UL[UE_template->pre_first_nb_rb_ul + i] = 1; + t[UE_template->pre_first_nb_rb_ul + i] = UE_id + '0'; + } + } + if (print) + LOG_D(MAC, + "%4d.%d UL scheduler allocation list: %s\n", + sched_frame, + sched_subframe, + t); +} + +void static_destroy(slice_info_t **si) { + const int n = (*si)->num; + (*si)->num = 0; + for (int i = 0; i < n; ++i) { + slice_t *s = (*si)->s[i]; + if (s->label) + free(s->label); + free(s->algo_data); + free(s); + } + free((*si)->s); + free(*si); +} + +pp_impl_param_t static_dl_init(module_id_t mod_id, int CC_id) { + slice_info_t *si = calloc(1, sizeof(slice_info_t)); + DevAssert(si); + + si->num = 0; + si->s = calloc(MAX_STATIC_SLICES, sizeof(slice_t)); + DevAssert(si->s); + for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) + si->UE_assoc_slice[i] = -1; + + /* insert default slice, all resources */ + static_slice_param_t *dlp = malloc(sizeof(static_slice_param_t)); + dlp->posLow = 0; + dlp->posHigh = to_rbg(RC.mac[mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth) - 1; + default_sched_dl_algo_t *algo = &RC.mac[mod_id]->pre_processor_dl.dl_algo; + DevAssert(0 == addmod_static_slice_dl(si, 0, strdup("default"), algo, dlp)); + const UE_list_t *UE_list = &RC.mac[mod_id]->UE_info.list; + for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) + slicing_add_UE(si, UE_id); + + pp_impl_param_t sttc; + sttc.algorithm = STATIC_SLICING; + sttc.add_UE = slicing_add_UE; + sttc.remove_UE = slicing_remove_UE; + sttc.move_UE = slicing_move_UE; + sttc.addmod_slice = addmod_static_slice_dl; + sttc.remove_slice = remove_static_slice; + sttc.dl = static_dl; + // current DL algo becomes default scheduler + sttc.dl_algo = *algo; + sttc.destroy = static_destroy; + sttc.slices = si; + + return sttc; +} + +pp_impl_param_t static_ul_init(module_id_t mod_id, int CC_id) { + slice_info_t *si = calloc(1, sizeof(slice_info_t)); + DevAssert(si); + + si->num = 0; + si->s = calloc(MAX_STATIC_SLICES, sizeof(slice_t)); + DevAssert(si->s); + for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) + si->UE_assoc_slice[i] = -1; + + /* insert default slice, all resources */ + static_slice_param_t *ulp = malloc(sizeof(static_slice_param_t)); + ulp->posLow = 0; + ulp->posHigh = to_prb(RC.mac[mod_id]->common_channels[CC_id].ul_Bandwidth) - 1; + default_sched_ul_algo_t *algo = &RC.mac[mod_id]->pre_processor_ul.ul_algo; + DevAssert(0 == addmod_static_slice_ul(si, 0, strdup("default"), algo, ulp)); + const UE_list_t *UE_list = &RC.mac[mod_id]->UE_info.list; + for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) + slicing_add_UE(si, UE_id); + + pp_impl_param_t sttc; + sttc.algorithm = STATIC_SLICING; + sttc.add_UE = slicing_add_UE; + sttc.remove_UE = slicing_remove_UE; + sttc.move_UE = slicing_move_UE; + sttc.addmod_slice = addmod_static_slice_ul; + sttc.remove_slice = remove_static_slice; + sttc.ul = static_ul; + // current DL algo becomes default scheduler + sttc.ul_algo = *algo; + sttc.destroy = static_destroy; + sttc.slices = si; + + return sttc; +} diff --git a/openair2/LAYER2/MAC/slicing/slicing.h b/openair2/LAYER2/MAC/slicing/slicing.h new file mode 100644 index 0000000000..1099b50ea0 --- /dev/null +++ b/openair2/LAYER2/MAC/slicing/slicing.h @@ -0,0 +1,74 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! + * \file slicing.h + * \brief General slice definition and helper parameters + * \author Robert Schmidt + * \date 2020 + * \email robert.schmidt@eurecom.fr + */ + +#ifndef __SLICING_H__ +#define __SLICING_H__ + +#include "openair2/LAYER2/MAC/mac.h" + +typedef struct slice_s { + /// Arbitrary ID + slice_id_t id; + /// Arbitrary label + char *label; + + union { + default_sched_dl_algo_t dl_algo; + default_sched_ul_algo_t ul_algo; + }; + + /// A specific algorithm's implementation parameters + void *algo_data; + /// Internal data that might be kept alongside a slice's params + void *int_data; + + // list of users in this slice + UE_list_t UEs; +} slice_t; + +typedef struct slice_info_s { + uint8_t num; + slice_t **s; + uint8_t UE_assoc_slice[MAX_MOBILES_PER_ENB]; +} slice_info_t; + +int slicing_get_UE_slice_idx(slice_info_t *si, int UE_id); + +#define STATIC_SLICING 10 +/* only four static slices for UL, DL resp. (not enough DCIs) */ +#define MAX_STATIC_SLICES 4 +typedef struct { + uint16_t posLow; + uint16_t posHigh; +} static_slice_param_t; +pp_impl_param_t static_dl_init(module_id_t mod_id, int CC_id); +pp_impl_param_t static_ul_init(module_id_t mod_id, int CC_id); + + +#endif /* __SLICING_H__ */ diff --git a/openair2/LAYER2/MAC/slicing/slicing_internal.h b/openair2/LAYER2/MAC/slicing/slicing_internal.h new file mode 100644 index 0000000000..744f8924d9 --- /dev/null +++ b/openair2/LAYER2/MAC/slicing/slicing_internal.h @@ -0,0 +1,46 @@ +/* + * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The OpenAirInterface Software Alliance licenses this file to You under + * the OAI Public License, Version 1.1 (the "License"); you may not use this file + * except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.openairinterface.org/?page_id=698 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *------------------------------------------------------------------------------- + * For more information about the OpenAirInterface (OAI) Software Alliance: + * contact@openairinterface.org + */ + +/*! + * \file slicing_internal.h + * \brief Internal slice helper functions + * \author Robert Schmidt + * \date 2020 + * \email robert.schmidt@eurecom.fr + */ + +#ifndef __SLICING_INTERNAL_H__ +#define __SLICING_INTERNAL_H__ + +#include "slicing.h" + +void slicing_add_UE(slice_info_t *si, int UE_id); + +void _remove_UE(slice_t **s, uint8_t *assoc, int UE_id); +void slicing_remove_UE(slice_info_t *si, int UE_id); + +void _move_UE(slice_t **s, uint8_t *assoc, int UE_id, int to); +void slicing_move_UE(slice_info_t *si, int UE_id, int idx); + +slice_t *_add_slice(uint8_t *n, slice_t **s); +slice_t *_remove_slice(uint8_t *n, slice_t **s, uint8_t *assoc, int idx); + +#endif /* __SLICING_INTERNAL_H__ */ From 4901daf75901901d66df158bc10a10db471f53f3 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Thu, 18 Jun 2020 19:12:15 +0200 Subject: [PATCH 500/553] FlexRAN: New protobuf slice structure + Static Slice handling --- .../CONTROL_MODULES/MAC/flexran_agent_mac.c | 139 ++++++--- .../CONTROL_MODULES/MAC/flexran_agent_mac.h | 13 +- .../MAC/flexran_agent_mac_internal.c | 202 ++++++++++--- .../MAC/flexran_agent_mac_internal.h | 20 +- .../ENB_APP/MESSAGES/V2/config_common.proto | 25 ++ .../ENB_APP/MESSAGES/V2/config_messages.proto | 2 + openair2/ENB_APP/flexran_agent_common.c | 12 +- openair2/ENB_APP/flexran_agent_ran_api.c | 277 ++++++++++++++++-- openair2/ENB_APP/flexran_agent_ran_api.h | 45 ++- openair2/LAYER2/MAC/main.c | 2 + openair2/LAYER2/MAC/slicing/slicing.c | 21 +- 11 files changed, 614 insertions(+), 144 deletions(-) diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c index 4800fccea9..e5d1c94c95 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c @@ -1452,9 +1452,74 @@ void flexran_agent_fill_mac_cell_config(mid_t mod_id, uint8_t cc_id, conf->si_config->has_sfn = 1; } - /* get a pointer to the config which is maintained in the agent throughout - * its lifetime */ - conf->slice_config = flexran_agent_get_slice_config(mod_id); + conf->slice_config = malloc(sizeof(Protocol__FlexSliceConfig)); + if (conf->slice_config) { + protocol__flex_slice_config__init(conf->slice_config); + Protocol__FlexSliceConfig *sc = conf->slice_config; + + sc->dl = malloc(sizeof(Protocol__FlexSliceDlUlConfig)); + DevAssert(sc->dl); + protocol__flex_slice_dl_ul_config__init(sc->dl); + sc->dl->algorithm = flexran_get_dl_slice_algo(mod_id); + sc->dl->has_algorithm = 1; + sc->dl->n_slices = flexran_get_num_dl_slices(mod_id); + if (sc->dl->n_slices > 0) { + sc->dl->slices = calloc(sc->dl->n_slices, sizeof(Protocol__FlexSlice *)); + DevAssert(sc->dl->slices); + for (int i = 0; i < sc->dl->n_slices; ++i) { + sc->dl->slices[i] = malloc(sizeof(Protocol__FlexSlice)); + DevAssert(sc->dl->slices[i]); + protocol__flex_slice__init(sc->dl->slices[i]); + flexran_get_dl_slice(mod_id, i, sc->dl->slices[i], sc->dl->algorithm); + } + } else { + sc->dl->scheduler = flexran_get_dl_scheduler_name(mod_id); + } + + sc->ul = malloc(sizeof(Protocol__FlexSliceDlUlConfig)); + DevAssert(sc->ul); + protocol__flex_slice_dl_ul_config__init(sc->ul); + sc->ul->algorithm = flexran_get_ul_slice_algo(mod_id); + sc->ul->has_algorithm = 1; + sc->ul->n_slices = flexran_get_num_ul_slices(mod_id); + if (sc->ul->n_slices > 0) { + sc->ul->slices = calloc(sc->ul->n_slices, sizeof(Protocol__FlexSlice *)); + DevAssert(sc->ul->slices); + for (int i = 0; i < sc->ul->n_slices; ++i) { + sc->ul->slices[i] = malloc(sizeof(Protocol__FlexSlice)); + DevAssert(sc->ul->slices[i]); + protocol__flex_slice__init(sc->ul->slices[i]); + flexran_get_ul_slice(mod_id, i, sc->ul->slices[i], sc->ul->algorithm); + } + } else { + sc->ul->scheduler = flexran_get_ul_scheduler_name(mod_id); + } + } +} + +void flexran_agent_destroy_mac_slice_config(Protocol__FlexCellConfig *conf) { + Protocol__FlexSliceConfig *sc = conf->slice_config; + for (int i = 0; i < sc->dl->n_slices; ++i) { + free(sc->dl->slices[i]); + sc->dl->slices[i] = NULL; + /* scheduler names are not freed: we assume we read them directly from the + * underlying memory and do not dispose it */ + } + free(sc->dl->slices); + /* scheduler name is not freed */ + free(sc->dl); + sc->dl = NULL; + for (int i = 0; i < sc->ul->n_slices; ++i) { + free(sc->ul->slices[i]); + sc->ul->slices[i] = NULL; + /* scheduler names are not freed */ + } + free(sc->ul->slices); + /* scheduler name is not freed */ + free(sc->ul); + sc->ul = NULL; + free(conf->slice_config); + conf->slice_config = NULL; } void flexran_agent_fill_mac_ue_config(mid_t mod_id, mid_t ue_id, @@ -1568,46 +1633,46 @@ int flexran_agent_unregister_mac_xface(mid_t mod_id) return 0; } - -void flexran_create_config_structures(mid_t mod_id) -{ - int i; - int n_dl = flexran_get_num_dl_slices(mod_id); - int m_ul = flexran_get_num_ul_slices(mod_id); - slice_config[mod_id] = flexran_agent_create_slice_config(n_dl, m_ul); - sc_update[mod_id] = flexran_agent_create_slice_config(n_dl, m_ul); - if (!slice_config[mod_id] || !sc_update[mod_id]) return; - - //flexran_agent_read_slice_config(mod_id, slice_config[mod_id]); - //flexran_agent_read_slice_config(mod_id, sc_update[mod_id]); - for (i = 0; i < n_dl; i++) { - //flexran_agent_read_slice_dl_config(mod_id, i, slice_config[mod_id]->dl[i]); - //flexran_agent_read_slice_dl_config(mod_id, i, sc_update[mod_id]->dl[i]); +void helper_destroy_mac_slice_config(Protocol__FlexSliceConfig *slice_config) { + if (slice_config->dl) { + if (slice_config->dl->scheduler) + free(slice_config->dl->scheduler); + for (int i = 0; i < slice_config->dl->n_slices; i++) + if (slice_config->dl->slices[i]->scheduler) + free(slice_config->dl->slices[i]->scheduler); } - for (i = 0; i < m_ul; i++) { - //flexran_agent_read_slice_ul_config(mod_id, i, slice_config[mod_id]->ul[i]); - //flexran_agent_read_slice_ul_config(mod_id, i, sc_update[mod_id]->ul[i]); + if (slice_config->ul) { + if (slice_config->ul->scheduler) + free(slice_config->ul->scheduler); + for (int i = 0; i < slice_config->ul->n_slices; i++) + if (slice_config->ul->slices[i]->scheduler) + free(slice_config->ul->slices[i]->scheduler); } + + Protocol__FlexCellConfig helper; + helper.slice_config = slice_config; + flexran_agent_destroy_mac_slice_config(&helper); } -void flexran_check_and_remove_slices(mid_t mod_id) -{ +void prepare_update_slice_config(mid_t mod_id, Protocol__FlexSliceConfig **slice_config) { + if (!*slice_config) return; + Protocol__FlexSliceConfig *sc = *slice_config; + *slice_config = NULL; + + /* TODO handle using lock-free queue */ + apply_update_dl_slice_config(mod_id, sc->dl); + apply_update_ul_slice_config(mod_id, sc->ul); + + helper_destroy_mac_slice_config(*slice_config); } -void flexran_agent_slice_update(mid_t mod_id) -{ +void prepare_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig **ue_config) { + /* TODO handle using lock-free queue */ + apply_ue_slice_assoc_update(mod_id, *ue_config); + + free(*ue_config); + *ue_config = NULL; } -Protocol__FlexSliceConfig *flexran_agent_get_slice_config(mid_t mod_id) -{ - if (!slice_config[mod_id]) return NULL; - Protocol__FlexSliceConfig *config = NULL; - - pthread_mutex_lock(&sc_update_mtx); - if (!config) { - pthread_mutex_unlock(&sc_update_mtx); - return NULL; - } - pthread_mutex_unlock(&sc_update_mtx); - return config; +void flexran_agent_slice_update(mid_t mod_id) { } diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.h b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.h index 2f9f99c740..5a8d4f31aa 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.h +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.h @@ -115,7 +115,16 @@ int flexran_agent_unregister_mac_xface(mid_t mod_id); /* Inform controller about possibility to update slice configuration */ void flexran_agent_slice_update(mid_t mod_id); -/* return a pointer to the current config */ -Protocol__FlexSliceConfig *flexran_agent_get_slice_config(mid_t mod_id); +/* marks slice_config so that it can be applied later. Takes ownership of the + * FlexSliceConfig message */ +void prepare_update_slice_config(mid_t mod_id, Protocol__FlexSliceConfig **slice); + +/* inserts a new ue_config into the structure keeping ue to slice association + * updates and marks so it can be applied. Takes ownership of the FlexUeConfig message */ +void prepare_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig **ue_config); + +/* free slice_config part of flexCellConfig, filled in + * flexran_agent_fill_mac_cell_config() */ +void flexran_agent_destroy_mac_slice_config(Protocol__FlexCellConfig *conf); #endif diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c index 4c80c561ee..93de0b11ec 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c @@ -1025,60 +1025,166 @@ int load_dl_scheduler_function(mid_t mod_id, const char *function_name) { } -Protocol__FlexSliceConfig *flexran_agent_create_slice_config(int n_dl, int m_ul) -{ - Protocol__FlexSliceConfig *fsc = malloc(sizeof(Protocol__FlexSliceConfig)); - if (!fsc) return NULL; - protocol__flex_slice_config__init(fsc); - - /* TODO */ - return fsc; -} - -void prepare_update_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *sup) -{ -} - - -void prepare_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig *ue_config) -{ - if (n_ue_slice_assoc_updates == 10) { - LOG_E(FLEXRAN_AGENT, - "[%d] can not handle flex_ue_config message, buffer is full; try again later\n", - mod_id); - return; +void update_or_remove_dl(mid_t mod_id, Protocol__FlexSlice *s) { + if (s->params_case == PROTOCOL__FLEX_SLICE__PARAMS__NOT_SET + && !s->label && !s->scheduler) { + LOG_I(FLEXRAN_AGENT, "remove DL slice ID %d\n", s->id); + const int rc = flexran_remove_dl_slice(mod_id, s); + if (!rc) + LOG_W(FLEXRAN_AGENT, "error while removing slice ID %d\n", s->id); + } else { + LOG_I(FLEXRAN_AGENT, "updating DL slice ID %d\n", s->id); + const int rc = flexran_create_dl_slice(mod_id, s); + if (rc < 0) + LOG_W(FLEXRAN_AGENT, + "error while update slice ID %d: flexran_create_dl_slice() -> %d\n", + s->id, rc); } +} + +void update_or_remove_ul(mid_t mod_id, Protocol__FlexSlice *s) { + if (s->params_case == PROTOCOL__FLEX_SLICE__PARAMS__NOT_SET + && !s->label && !s->scheduler) { + LOG_I(FLEXRAN_AGENT, "remove UL slice ID %d\n", s->id); + const int rc = flexran_remove_ul_slice(mod_id, s); + if (!rc) + LOG_W(FLEXRAN_AGENT, "error while removing slice ID %d\n", s->id); + } else { + LOG_I(FLEXRAN_AGENT, "updating UL slice ID %d\n", s->id); + const int rc = flexran_create_ul_slice(mod_id, s); + if (rc < 0) + LOG_W(FLEXRAN_AGENT, + "error while updating slice ID %d: flexran_create_ul_slice() -> %d)\n", + s->id, rc); + } +} + +void apply_update_dl_slice_config(mid_t mod_id, Protocol__FlexSliceDlUlConfig *dl) { + if (!dl) + return; + + Protocol__FlexSliceAlgorithm dl_algo = flexran_get_dl_slice_algo(mod_id); + if (dl->has_algorithm && dl_algo != dl->algorithm) { + LOG_I(FLEXRAN_AGENT, "loading new DL slice algorithm %d\n", dl->algorithm); + dl_algo = dl->algorithm; + flexran_set_dl_slice_algo(mod_id, dl_algo); + } + + /* first update existing slices, then create new. Thus, we go through the + * list twice. First round, if a slice exists, handle and mark as such. Then, + * apply all others in the second round */ + if (dl->n_slices > 0) { + if (dl_algo == PROTOCOL__FLEX_SLICE_ALGORITHM__None) { + LOG_E(FLEXRAN_AGENT, "cannot update slices: no algorithm loaded\n"); + return; + } + int handled_dl[dl->n_slices]; + for (int i = 0; i < dl->n_slices; ++i) { + if (flexran_find_dl_slice(mod_id, dl->slices[i]->id) < 0) { + handled_dl[i] = 0; + continue; + } + update_or_remove_dl(mod_id, dl->slices[i]); + handled_dl[i] = 1; + } + for (int i = 0; i < dl->n_slices; ++i) { + if (handled_dl[i]) + continue; + update_or_remove_dl(mod_id, dl->slices[i]); + } + } + + if (dl->scheduler) { + if (dl_algo != PROTOCOL__FLEX_SLICE_ALGORITHM__None) { + LOG_E(FLEXRAN_AGENT, "cannot update scheduling algorithm: slice algorithm loaded\n"); + return; + } + LOG_I(FLEXRAN_AGENT, "loading DL new scheduling algorithm '%s'\n", dl->scheduler); + const int rc = flexran_set_dl_scheduler(mod_id, dl->scheduler); + if (rc < 0) { + LOG_E(FLEXRAN_AGENT, + "error while updating scheduling algorithm: " + "flexran_update_dl_sched_algo() -> %d)\n", + rc); + return; + } + } +} + +void apply_update_ul_slice_config(mid_t mod_id, Protocol__FlexSliceDlUlConfig *ul) { + if (!ul) + return; + + Protocol__FlexSliceAlgorithm ul_algo = flexran_get_ul_slice_algo(mod_id); + if (ul->has_algorithm && ul_algo != ul->algorithm) { + LOG_I(FLEXRAN_AGENT, "loading new UL slice algorithm %d\n", ul->algorithm); + ul_algo = ul->algorithm; + flexran_set_ul_slice_algo(mod_id, ul_algo); + } + if (ul->n_slices > 0) { + if (ul_algo == PROTOCOL__FLEX_SLICE_ALGORITHM__None) { + LOG_E(FLEXRAN_AGENT, "cannot update slices: no algorithm loaded\n"); + return; + } + int handled_ul[ul->n_slices]; + for (int i = 0; i < ul->n_slices; ++i) { + if (flexran_find_ul_slice(mod_id, ul->slices[i]->id) < 0) { + handled_ul[i] = 0; + continue; + } + update_or_remove_ul(mod_id, ul->slices[i]); + handled_ul[i] = 1; + } + for (int i = 0; i < ul->n_slices; ++i) { + if (handled_ul[i]) + continue; + update_or_remove_ul(mod_id, ul->slices[i]); + } + } + + if (ul->scheduler) { + if (ul_algo != PROTOCOL__FLEX_SLICE_ALGORITHM__None) { + LOG_E(FLEXRAN_AGENT, "cannot update scheduling algorithm: slice algorithm loaded\n"); + return; + } + LOG_I(FLEXRAN_AGENT, "loading new UL scheduling algorithm '%s'\n", ul->scheduler); + const int rc = flexran_set_ul_scheduler(mod_id, ul->scheduler); + if (rc < 0) { + LOG_E(FLEXRAN_AGENT, + "error while updating scheduling algorithm: " + "flexran_update_dl_sched_algo() -> %d)\n", + rc); + return; + } + } +} + +int apply_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig *ue_config) +{ if (!ue_config->has_rnti) { LOG_E(FLEXRAN_AGENT, "[%d] cannot update UE to slice association, no RNTI in flex_ue_config message\n", mod_id); - return; + return 0; } - if (ue_config->has_dl_slice_id) - LOG_I(FLEXRAN_AGENT, "[%d] associating UE RNTI %#x to DL slice ID %d\n", - mod_id, ue_config->rnti, ue_config->dl_slice_id); - if (ue_config->has_ul_slice_id) - LOG_I(FLEXRAN_AGENT, "[%d] associating UE RNTI %#x to UL slice ID %d\n", - mod_id, ue_config->rnti, ue_config->ul_slice_id); - ue_slice_assoc_update[n_ue_slice_assoc_updates++] = ue_config; - perform_slice_config_update_count = 2; -} - -int apply_ue_slice_assoc_update(mid_t mod_id) -{ - int i; - int changes = 0; - for (i = 0; i < n_ue_slice_assoc_updates; i++) { - int ue_id = find_UE_id(mod_id, ue_slice_assoc_update[i]->rnti); - if (ue_id < 0 || ue_id > MAX_MOBILES_PER_ENB){ - LOG_E(FLEXRAN_AGENT,"UE_id %d is wrong!!\n",ue_id); - continue; - } - if (ue_slice_assoc_update[i]->has_dl_slice_id) { - } - if (ue_slice_assoc_update[i]->has_ul_slice_id) { + int UE_id = flexran_get_mac_ue_id_rnti(mod_id, ue_config->rnti); + if (ue_config->has_dl_slice_id) { + if (flexran_get_dl_slice_algo(mod_id) == PROTOCOL__FLEX_SLICE_ALGORITHM__None) { + LOG_E(FLEXRAN_AGENT, "no DL slice algorithm loaded\n"); + } else { + LOG_I(FLEXRAN_AGENT, "[%d] associating UE RNTI %04x - %d/UE %d to DL slice ID %d\n", + mod_id, ue_config->rnti, ue_config->rnti, UE_id, ue_config->dl_slice_id); + flexran_set_ue_dl_slice_id(mod_id, UE_id, ue_config->dl_slice_id); } } - n_ue_slice_assoc_updates = 0; - return changes; + if (ue_config->has_ul_slice_id) { + if (flexran_get_ul_slice_algo(mod_id) == PROTOCOL__FLEX_SLICE_ALGORITHM__None) { + LOG_E(FLEXRAN_AGENT, "no UL slice algorithm loaded\n"); + } else { + LOG_I(FLEXRAN_AGENT, "[%d] associating UE RNTI %04x - %d/UE %d to UL slice ID %d\n", + mod_id, ue_config->rnti, ue_config->rnti, UE_id, ue_config->ul_slice_id); + flexran_set_ue_ul_slice_id(mod_id, UE_id, ue_config->ul_slice_id); + } + } + return 0; } diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.h b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.h index ef2a7e40a9..9db5d61a11 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.h +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.h @@ -103,23 +103,11 @@ int load_dl_scheduler_function(mid_t mod_id, const char *function_name); /*** Functions for handling a slice config ***/ -/* allocate memory for a Protocol__FlexSliceConfig structure with n_dl DL slice - * configs and m_ul UL slice configs */ -Protocol__FlexSliceConfig *flexran_agent_create_slice_config(int n_dl, int m_ul); - -/* read the general slice parameters via RAN into the given - * Protocol__FlexSliceConfig struct */ -void flexran_agent_read_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *s); - -/* reads content of slice over the sc_update structure, so that it can be - * applied later by performing a diff between slice_config and sc_update */ -void prepare_update_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *slice); - -/* inserts a new ue_config into the structure keeping ue to slice association - * updates and marks so it can be applied */ -void prepare_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig *ue_config); +/* Prepare the application of a slicing config */ +void apply_update_dl_slice_config(mid_t mod_id, Protocol__FlexSliceDlUlConfig *slice); +void apply_update_ul_slice_config(mid_t mod_id, Protocol__FlexSliceDlUlConfig *slice); /* apply a new association between a UE and a slice (both DL and UL) */ -int apply_ue_slice_assoc_update(mid_t mod_id); +int apply_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig *ue_config); #endif /*FLEXRAN_AGENT_MAC_INTERNAL_H_*/ diff --git a/openair2/ENB_APP/MESSAGES/V2/config_common.proto b/openair2/ENB_APP/MESSAGES/V2/config_common.proto index e5d01ebdc0..2f2267b628 100644 --- a/openair2/ENB_APP/MESSAGES/V2/config_common.proto +++ b/openair2/ENB_APP/MESSAGES/V2/config_common.proto @@ -61,6 +61,31 @@ enum flex_qam { // // Slice config related structures and enums // +enum flex_slice_algorithm { + None = 0; + Static = 1; + NVS = 2; +} + +message flex_slice_static { + optional uint32 posLow = 1; + optional uint32 posHigh = 2; +} + +message flex_slice { + optional uint32 id = 1; + optional string label = 2; + optional string scheduler = 3; + oneof params { + flex_slice_static static = 10; + } +} + +message flex_slice_dl_ul_config { + optional flex_slice_algorithm algorithm = 1; + repeated flex_slice slices = 2; + optional string scheduler = 3; // if no slicing +} // // UE config related structures and enums diff --git a/openair2/ENB_APP/MESSAGES/V2/config_messages.proto b/openair2/ENB_APP/MESSAGES/V2/config_messages.proto index 1a66a4f20f..1a69deec71 100644 --- a/openair2/ENB_APP/MESSAGES/V2/config_messages.proto +++ b/openair2/ENB_APP/MESSAGES/V2/config_messages.proto @@ -49,6 +49,8 @@ message flex_cell_config { } message flex_slice_config { + optional flex_slice_dl_ul_config dl = 6; + optional flex_slice_dl_ul_config ul = 7; } message flex_ue_config { diff --git a/openair2/ENB_APP/flexran_agent_common.c b/openair2/ENB_APP/flexran_agent_common.c index 3dd9f5b957..7569ca1ac1 100644 --- a/openair2/ENB_APP/flexran_agent_common.c +++ b/openair2/ENB_APP/flexran_agent_common.c @@ -306,6 +306,7 @@ int flexran_agent_destroy_enb_config_reply(Protocol__FlexranMessage *msg) { if (reply->cell_config[i]->mbsfn_subframe_config_sfalloc) free(reply->cell_config[i]->mbsfn_subframe_config_sfalloc); + /* si_config is shared between MAC and RRC, free here */ if (reply->cell_config[i]->si_config) { for(int j = 0; j < reply->cell_config[i]->si_config->n_si_message; j++) { free(reply->cell_config[i]->si_config->si_message[j]); @@ -316,8 +317,7 @@ int flexran_agent_destroy_enb_config_reply(Protocol__FlexranMessage *msg) { } if (reply->cell_config[i]->slice_config) { - /* TODO */ - free(reply->cell_config[i]->slice_config); + flexran_agent_destroy_mac_slice_config(reply->cell_config[i]); } free(reply->cell_config[i]); @@ -880,7 +880,7 @@ int flexran_agent_handle_enb_config_reply(mid_t mod_id, const void *params, Prot if (enb_config->n_cell_config > 0) { if (flexran_agent_get_mac_xface(mod_id) && enb_config->cell_config[0]->slice_config) { - prepare_update_slice_config(mod_id, enb_config->cell_config[0]->slice_config); + prepare_update_slice_config(mod_id, &enb_config->cell_config[0]->slice_config); } if (enb_config->cell_config[0]->has_eutra_band && enb_config->cell_config[0]->has_dl_freq @@ -921,7 +921,11 @@ int flexran_agent_handle_ue_config_reply(mid_t mod_id, const void *params, Proto Protocol__FlexUeConfigReply *ue_config_reply = input->ue_config_reply_msg; for (i = 0; flexran_agent_get_mac_xface(mod_id) && i < ue_config_reply->n_ue_config; i++) - prepare_ue_slice_assoc_update(mod_id, ue_config_reply->ue_config[i]); + prepare_ue_slice_assoc_update(mod_id, &ue_config_reply->ue_config[i]); + /* prepare_ue_slice_assoc_update takes ownership of the individual + * FlexUeConfig messages. Therefore, mark zero messages to not accidentally + * free them twice */ + ue_config_reply->n_ue_config = 0; *msg = NULL; return 0; diff --git a/openair2/ENB_APP/flexran_agent_ran_api.c b/openair2/ENB_APP/flexran_agent_ran_api.c index cd8b0b8f67..79c992a4d7 100644 --- a/openair2/ENB_APP/flexran_agent_ran_api.c +++ b/openair2/ENB_APP/flexran_agent_ran_api.c @@ -30,6 +30,7 @@ #include "flexran_agent_ran_api.h" #include "s1ap_eNB_ue_context.h" #include "s1ap_eNB_management_procedures.h" +#include "openair2/LAYER2/MAC/slicing/slicing.h" static inline int phy_is_present(mid_t mod_id, uint8_t cc_id) { return RC.eNB && RC.eNB[mod_id] && RC.eNB[mod_id][cc_id]; @@ -3013,66 +3014,294 @@ uint32_t flexran_get_rrc_enb_ue_s1ap_id(mid_t mod_id, rnti_t rnti) } /**************************** SLICING ****************************/ +Protocol__FlexSliceAlgorithm flexran_get_dl_slice_algo(mid_t mod_id) { + if (!mac_is_present(mod_id)) return PROTOCOL__FLEX_SLICE_ALGORITHM__None; + + switch (RC.mac[mod_id]->pre_processor_dl.algorithm) { + case STATIC_SLICING: + return PROTOCOL__FLEX_SLICE_ALGORITHM__Static; + default: + return PROTOCOL__FLEX_SLICE_ALGORITHM__None; + } +} + +int flexran_set_dl_slice_algo(mid_t mod_id, Protocol__FlexSliceAlgorithm algo) { + if (!mac_is_present(mod_id)) return 0; + eNB_MAC_INST *mac = RC.mac[mod_id]; + const int cc_id = 0; + + pp_impl_param_t dl = mac->pre_processor_dl; + switch (algo) { + case PROTOCOL__FLEX_SLICE_ALGORITHM__Static: + mac->pre_processor_dl = static_dl_init(mod_id, cc_id); + break; + default: + mac->pre_processor_dl.algorithm = 0; + mac->pre_processor_dl.dl = dlsch_scheduler_pre_processor; + mac->pre_processor_dl.dl_algo.data = mac->pre_processor_dl.dl_algo.setup(); + mac->pre_processor_dl.slices = NULL; + break; + } + if (dl.slices) + dl.destroy(&dl.slices); + if (dl.dl_algo.data) + dl.dl_algo.unset(&dl.dl_algo.data); + return 1; +} + +Protocol__FlexSliceAlgorithm flexran_get_ul_slice_algo(mid_t mod_id) { + if (!mac_is_present(mod_id)) return PROTOCOL__FLEX_SLICE_ALGORITHM__None; + + switch (RC.mac[mod_id]->pre_processor_ul.algorithm) { + case STATIC_SLICING: + return PROTOCOL__FLEX_SLICE_ALGORITHM__Static; + default: + return PROTOCOL__FLEX_SLICE_ALGORITHM__None; + } +} + +int flexran_set_ul_slice_algo(mid_t mod_id, Protocol__FlexSliceAlgorithm algo) { + if (!mac_is_present(mod_id)) return 0; + eNB_MAC_INST *mac = RC.mac[mod_id]; + const int cc_id = 0; + + pp_impl_param_t ul = mac->pre_processor_ul; + switch (algo) { + case PROTOCOL__FLEX_SLICE_ALGORITHM__Static: + mac->pre_processor_ul = static_ul_init(mod_id, cc_id); + break; + default: + mac->pre_processor_ul.algorithm = 0; + mac->pre_processor_ul.ul = ulsch_scheduler_pre_processor; + mac->pre_processor_ul.ul_algo.data = mac->pre_processor_ul.ul_algo.setup(); + mac->pre_processor_ul.slices = NULL; + break; + } + if (ul.slices) + ul.destroy(&ul.slices); + if (ul.ul_algo.data) + ul.ul_algo.unset(&ul.ul_algo.data); + return 1; +} + int flexran_get_ue_dl_slice_id(mid_t mod_id, mid_t ue_id) { if (!mac_is_present(mod_id)) return -1; - return 0; + slice_info_t *slices = RC.mac[mod_id]->pre_processor_dl.slices; + if (!slices) return -1; + const int idx = slices->UE_assoc_slice[ue_id]; + return slices->s[idx]->id; +} + +void flexran_set_ue_dl_slice_id(mid_t mod_id, mid_t ue_id, slice_id_t slice_id) { + if (!mac_is_present(mod_id)) return; + int idx = flexran_find_dl_slice(mod_id, slice_id); + if (idx < 0) return; + pp_impl_param_t *dl = &RC.mac[mod_id]->pre_processor_dl; + dl->move_UE(dl->slices, ue_id, idx); } int flexran_get_ue_ul_slice_id(mid_t mod_id, mid_t ue_id) { if (!mac_is_present(mod_id)) return -1; - return 0; + slice_info_t *slices = RC.mac[mod_id]->pre_processor_ul.slices; + if (!slices) return -1; + const int idx = slices->UE_assoc_slice[ue_id]; + return slices->s[idx]->id; } -/* TODO */ -int flexran_create_dl_slice(mid_t mod_id, slice_id_t slice_id) { - if (!mac_is_present(mod_id)) return -1; - return -1; +void flexran_set_ue_ul_slice_id(mid_t mod_id, mid_t ue_id, slice_id_t slice_id) { + if (!mac_is_present(mod_id)) return; + int idx = flexran_find_ul_slice(mod_id, slice_id); + if (idx < 0) return; + pp_impl_param_t *ul = &RC.mac[mod_id]->pre_processor_ul; + ul->move_UE(ul->slices, ue_id, idx); } -/* TODO */ -int flexran_remove_dl_slice(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; +int flexran_create_dl_slice(mid_t mod_id, const Protocol__FlexSlice *s) { + if (!mac_is_present(mod_id)) return 0; + void *params = NULL; + switch (s->params_case) { + case PROTOCOL__FLEX_SLICE__PARAMS_STATIC: + params = malloc(sizeof(static_slice_param_t)); + if (!params) return 0; + ((static_slice_param_t *)params)->posLow = s->static_->poslow; + ((static_slice_param_t *)params)->posHigh = s->static_->poshigh; + break; + default: + break; + } + pp_impl_param_t *dl = &RC.mac[mod_id]->pre_processor_dl; + char *l = s->label ? strdup(s->label) : NULL; + void *algo = &dl->dl_algo; // default scheduler + if (s->scheduler) { + algo = dlsym(NULL, s->scheduler); + if (!algo) { + free(params); + LOG_E(FLEXRAN_AGENT, "cannot locate scheduler '%s'\n", s->scheduler); + return -15; + } + } + return dl->addmod_slice(dl->slices, s->id, l, algo, params); +} + +int flexran_remove_dl_slice(mid_t mod_id, const Protocol__FlexSlice *s) { + if (!mac_is_present(mod_id)) return 0; + const int idx = flexran_find_dl_slice(mod_id, s->id); + if (idx < 0) return 0; + pp_impl_param_t *dl = &RC.mac[mod_id]->pre_processor_dl; + return dl->remove_slice(dl->slices, idx); } int flexran_find_dl_slice(mid_t mod_id, slice_id_t slice_id) { if (!mac_is_present(mod_id)) return -1; + slice_info_t *si = RC.mac[mod_id]->pre_processor_dl.slices; + for (int i = 0; i < si->num; ++i) + if (si->s[i]->id == slice_id) + return i; return -1; } -//int flexran_get_dl_slice(mid_t mod_id, int slice_idx, Protocol__FlexSlice *s) { -//} +void flexran_get_dl_slice(mid_t mod_id, + int slice_idx, + Protocol__FlexSlice *slice, + Protocol__FlexSliceAlgorithm algo) { + if (!mac_is_present(mod_id)) return; + slice_t *s_ = RC.mac[mod_id]->pre_processor_dl.slices->s[slice_idx]; + slice->has_id = 1; + slice->id = s_->id; + slice->label = s_->label; + slice->scheduler = s_->dl_algo.name; + slice->params_case = PROTOCOL__FLEX_SLICE__PARAMS__NOT_SET; + switch (algo) { + case PROTOCOL__FLEX_SLICE_ALGORITHM__Static: + slice->static_ = malloc(sizeof(Protocol__FlexSliceStatic)); + if (!slice->static_) return; + protocol__flex_slice_static__init(slice->static_); + slice->static_->has_poslow = 1; + slice->static_->poslow = ((static_slice_param_t *)s_->algo_data)->posLow; + slice->static_->has_poshigh = 1; + slice->static_->poshigh = ((static_slice_param_t *)s_->algo_data)->posHigh; + slice->params_case = PROTOCOL__FLEX_SLICE__PARAMS_STATIC; + break; + default: + break; + } +} int flexran_get_num_dl_slices(mid_t mod_id) { - if (!mac_is_present(mod_id)) return -1; - return 0; + if (!mac_is_present(mod_id)) return 0; + if (!RC.mac[mod_id]->pre_processor_dl.slices) return 0; + return RC.mac[mod_id]->pre_processor_dl.slices->num; } -/* TODO */ -void flexran_create_ul_slice(mid_t mod_id, slice_id_t slice_id) { - if (!mac_is_present(mod_id)) return; - return; +int flexran_create_ul_slice(mid_t mod_id, const Protocol__FlexSlice *s) { + if (!mac_is_present(mod_id)) return -1; + void *params = NULL; + switch (s->params_case) { + case PROTOCOL__FLEX_SLICE__PARAMS_STATIC: + params = malloc(sizeof(static_slice_param_t)); + if (!params) return 0; + ((static_slice_param_t *)params)->posLow = s->static_->poslow; + ((static_slice_param_t *)params)->posHigh = s->static_->poshigh; + break; + default: + break; + } + pp_impl_param_t *ul = &RC.mac[mod_id]->pre_processor_ul; + char *l = s->label ? strdup(s->label) : NULL; + void *algo = &ul->ul_algo; // default scheduler + if (s->scheduler) { + algo = dlsym(NULL, s->scheduler); + if (!algo) { + free(params); + LOG_E(FLEXRAN_AGENT, "cannot locate scheduler '%s'\n", s->scheduler); + return -15; + } + } + return ul->addmod_slice(ul->slices, s->id, l, algo, params); } -/* TODO */ -int flexran_remove_ul_slice(mid_t mod_id, int slice_idx) { - if (!mac_is_present(mod_id)) return -1; - return -1; +int flexran_remove_ul_slice(mid_t mod_id, const Protocol__FlexSlice *s) { + if (!mac_is_present(mod_id)) return 0; + const int idx = flexran_find_ul_slice(mod_id, s->id); + if (idx < 0) return 0; + pp_impl_param_t *ul = &RC.mac[mod_id]->pre_processor_ul; + return ul->remove_slice(ul->slices, idx); } int flexran_find_ul_slice(mid_t mod_id, slice_id_t slice_id) { if (!mac_is_present(mod_id)) return -1; + slice_info_t *si = RC.mac[mod_id]->pre_processor_ul.slices; + for (int i = 0; i < si->num; ++i) + if (si->s[i]->id == slice_id) + return i; return -1; } -//int flexran_get_ul_slice(mid_t mod_id, int slice_idx, Protocol__FlexSlice *s) { -//} +void flexran_get_ul_slice(mid_t mod_id, + int slice_idx, + Protocol__FlexSlice *slice, + Protocol__FlexSliceAlgorithm algo) { + if (!mac_is_present(mod_id)) return; + slice_t *s_ = RC.mac[mod_id]->pre_processor_ul.slices->s[slice_idx]; + slice->has_id = 1; + slice->id = s_->id; + slice->label = s_->label; + slice->scheduler = s_->ul_algo.name; + slice->params_case = PROTOCOL__FLEX_SLICE__PARAMS__NOT_SET; + switch (algo) { + case PROTOCOL__FLEX_SLICE_ALGORITHM__Static: + slice->static_ = malloc(sizeof(Protocol__FlexSliceStatic)); + if (!slice->static_) return; + protocol__flex_slice_static__init(slice->static_); + slice->static_->has_poslow = 1; + slice->static_->poslow = ((static_slice_param_t *)s_->algo_data)->posLow; + slice->static_->has_poshigh = 1; + slice->static_->poshigh = ((static_slice_param_t *)s_->algo_data)->posHigh; + slice->params_case = PROTOCOL__FLEX_SLICE__PARAMS_STATIC; + break; + default: + break; + } + +} int flexran_get_num_ul_slices(mid_t mod_id) { + if (!mac_is_present(mod_id)) return 0; + if (!RC.mac[mod_id]->pre_processor_ul.slices) return 0; + return RC.mac[mod_id]->pre_processor_ul.slices->num; +} + +char *flexran_get_dl_scheduler_name(mid_t mod_id) { + if (!mac_is_present(mod_id)) return NULL; + return RC.mac[mod_id]->pre_processor_dl.dl_algo.name; +} + +int flexran_set_dl_scheduler(mid_t mod_id, char *sched) { if (!mac_is_present(mod_id)) return -1; + void *d = dlsym(NULL, sched); + if (!d) return -2; + pp_impl_param_t *dl_pp = &RC.mac[mod_id]->pre_processor_dl; + dl_pp->dl_algo.unset(&dl_pp->dl_algo.data); + dl_pp->dl_algo = *(default_sched_dl_algo_t *) d; + dl_pp->dl_algo.data = dl_pp->dl_algo.setup(); return 0; } +char *flexran_get_ul_scheduler_name(mid_t mod_id) { + if (!mac_is_present(mod_id)) return NULL; + return RC.mac[mod_id]->pre_processor_ul.ul_algo.name; +} + +int flexran_set_ul_scheduler(mid_t mod_id, char *sched) { + if (!mac_is_present(mod_id)) return -1; + void *d = dlsym(NULL, sched); + if (!d) return -2; + pp_impl_param_t *ul_pp = &RC.mac[mod_id]->pre_processor_ul; + ul_pp->ul_algo.unset(&ul_pp->ul_algo.data); + ul_pp->ul_algo = *(default_sched_ul_algo_t *) d; + ul_pp->ul_algo.data = ul_pp->ul_algo.setup(); + return 0; +} /************************** S1AP **************************/ int flexran_get_s1ap_mme_pending(mid_t mod_id){ diff --git a/openair2/ENB_APP/flexran_agent_ran_api.h b/openair2/ENB_APP/flexran_agent_ran_api.h index c29ba53c11..2d8a86f7d0 100644 --- a/openair2/ENB_APP/flexran_agent_ran_api.h +++ b/openair2/ENB_APP/flexran_agent_ran_api.h @@ -656,41 +656,66 @@ int flexran_agent_rrc_gtp_get_teid_sgw(mid_t mod_id, rnti_t rnti, int index); uint32_t flexran_get_rrc_enb_ue_s1ap_id(mid_t mod_id, rnti_t rnti); /************************** Slice configuration **************************/ +/* Get the currently active DL slicing algorithm */ +Protocol__FlexSliceAlgorithm flexran_get_dl_slice_algo(mid_t mod_id); +/* Set the active DL slicing algorithm */ +int flexran_set_dl_slice_algo(mid_t mod_id, Protocol__FlexSliceAlgorithm algo); + +/* Get the currently active UL slicing algorithm */ +Protocol__FlexSliceAlgorithm flexran_get_ul_slice_algo(mid_t mod_id); +/* Set the active UL slicing algorithm */ +int flexran_set_ul_slice_algo(mid_t mod_id, Protocol__FlexSliceAlgorithm algo); /* Get the DL slice ID for a UE */ int flexran_get_ue_dl_slice_id(mid_t mod_id, mid_t ue_id); -/* Set the DL slice index(!) for a UE */ -//void flexran_set_ue_dl_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx); +/* Set the DL slice for a UE */ +void flexran_set_ue_dl_slice_id(mid_t mod_id, mid_t ue_id, slice_id_t slice_id); /* Get the UL slice ID for a UE */ int flexran_get_ue_ul_slice_id(mid_t mod_id, mid_t ue_id); -/* Set the UL slice index(!) for a UE */ -//void flexran_set_ue_ul_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx); +/* Set the UL slice for a UE */ +void flexran_set_ue_ul_slice_id(mid_t mod_id, mid_t ue_id, slice_id_t slice_id); /* Create slice in DL, returns the new slice index */ -//int flexran_create_dl_slice(mid_t mod_id, slice_id_t slice_id); +int flexran_create_dl_slice(mid_t mod_id, const Protocol__FlexSlice *s); /* Remove slice in DL, returns new number of slices or -1 on error */ -//int flexran_remove_dl_slice(mid_t mod_id, int slice_idx); +int flexran_remove_dl_slice(mid_t mod_id, const Protocol__FlexSlice *s); /* Finds slice in DL with given slice_id and returns slice index */ int flexran_find_dl_slice(mid_t mod_id, slice_id_t slice_id); /* Return the parameters of slice at index slice_idx */ -//void flexran_get_dl_slice(mid_t mod_id, int slice_idx, Protocol__FlexSlice *s); +void flexran_get_dl_slice(mid_t mod_id, + int slice_idx, + Protocol__FlexSlice *slice, + Protocol__FlexSliceAlgorithm algo); /* Get the number of slices in DL */ int flexran_get_num_dl_slices(mid_t mod_id); /* Create slice in UL, returns the new slice index */ -//int flexran_create_ul_slice(mid_t mod_id, slice_id_t slice_id); +int flexran_create_ul_slice(mid_t mod_id, const Protocol__FlexSlice *s); /* Remove slice in UL */ -//int flexran_remove_ul_slice(mid_t mod_id, int slice_idx); +int flexran_remove_ul_slice(mid_t mod_id, const Protocol__FlexSlice *s); /* Finds slice in DL with given slice_id and returns slice index */ int flexran_find_ul_slice(mid_t mod_id, slice_id_t slice_id); /* Return the parameters of slice at index slice_idx */ -//void flexran_get_ul_slice(mid_t mod_id, int slice_idx, Protocol__FlexSlice *s); +void flexran_get_ul_slice(mid_t mod_id, + int slice_idx, + Protocol__FlexSlice *slice, + Protocol__FlexSliceAlgorithm algo); /* Get the number of slices in UL */ int flexran_get_num_ul_slices(mid_t mod_id); +/* Get the name of/Set the DL scheduling algorithm. If slicing is active, this + * corresponds to the default algorithm for slices, otherwise the currently + * used one. */ +char *flexran_get_dl_scheduler_name(mid_t mod_id); +int flexran_set_dl_scheduler(mid_t mod_id, char *sched); + +/* Get the name of/Set the UL scheduler algorithm. Same applies as for the DL + * case */ +char *flexran_get_ul_scheduler_name(mid_t mod_id); +int flexran_set_ul_scheduler(mid_t mod_id, char *sched); /************************** S1AP **************************/ /* Get the number of MMEs to be connected */ diff --git a/openair2/LAYER2/MAC/main.c b/openair2/LAYER2/MAC/main.c index 24038e60d5..af6d1a7ac3 100644 --- a/openair2/LAYER2/MAC/main.c +++ b/openair2/LAYER2/MAC/main.c @@ -100,6 +100,7 @@ void mac_top_init_eNB(void) mac[i]->if_inst = IF_Module_init(i); + mac[i]->pre_processor_dl.algorithm = 0; mac[i]->pre_processor_dl.dl = dlsch_scheduler_pre_processor; char *s = "round_robin_dl"; void *d = dlsym(NULL, s); @@ -107,6 +108,7 @@ void mac_top_init_eNB(void) mac[i]->pre_processor_dl.dl_algo = *(default_sched_dl_algo_t *) d; mac[i]->pre_processor_dl.dl_algo.data = mac[i]->pre_processor_dl.dl_algo.setup(); + mac[i]->pre_processor_ul.algorithm = 0; mac[i]->pre_processor_ul.ul = ulsch_scheduler_pre_processor; s = "round_robin_ul"; d = dlsym(NULL, s); diff --git a/openair2/LAYER2/MAC/slicing/slicing.c b/openair2/LAYER2/MAC/slicing/slicing.c index a1de326df0..9c88f6cffb 100644 --- a/openair2/LAYER2/MAC/slicing/slicing.c +++ b/openair2/LAYER2/MAC/slicing/slicing.c @@ -258,13 +258,26 @@ int addmod_static_slice_ul(slice_info_t *si, return si->num - 1; } -int remove_static_slice(slice_info_t *si, uint8_t slice_idx) { +int remove_static_slice_dl(slice_info_t *si, uint8_t slice_idx) { if (slice_idx == 0) return 0; slice_t *sr = _remove_slice(&si->num, si->s, si->UE_assoc_slice, slice_idx); if (!sr) return 0; free(sr->algo_data); + sr->dl_algo.unset(&sr->dl_algo.data); + free(sr); + return 1; +} + +int remove_static_slice_ul(slice_info_t *si, uint8_t slice_idx) { + if (slice_idx == 0) + return 0; + slice_t *sr = _remove_slice(&si->num, si->s, si->UE_assoc_slice, slice_idx); + if (!sr) + return 0; + free(sr->algo_data); + sr->ul_algo.unset(&sr->ul_algo.data); free(sr); return 1; } @@ -528,6 +541,7 @@ pp_impl_param_t static_dl_init(module_id_t mod_id, int CC_id) { dlp->posLow = 0; dlp->posHigh = to_rbg(RC.mac[mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth) - 1; default_sched_dl_algo_t *algo = &RC.mac[mod_id]->pre_processor_dl.dl_algo; + algo->data = NULL; DevAssert(0 == addmod_static_slice_dl(si, 0, strdup("default"), algo, dlp)); const UE_list_t *UE_list = &RC.mac[mod_id]->UE_info.list; for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) @@ -539,7 +553,7 @@ pp_impl_param_t static_dl_init(module_id_t mod_id, int CC_id) { sttc.remove_UE = slicing_remove_UE; sttc.move_UE = slicing_move_UE; sttc.addmod_slice = addmod_static_slice_dl; - sttc.remove_slice = remove_static_slice; + sttc.remove_slice = remove_static_slice_dl; sttc.dl = static_dl; // current DL algo becomes default scheduler sttc.dl_algo = *algo; @@ -564,6 +578,7 @@ pp_impl_param_t static_ul_init(module_id_t mod_id, int CC_id) { ulp->posLow = 0; ulp->posHigh = to_prb(RC.mac[mod_id]->common_channels[CC_id].ul_Bandwidth) - 1; default_sched_ul_algo_t *algo = &RC.mac[mod_id]->pre_processor_ul.ul_algo; + algo->data = NULL; DevAssert(0 == addmod_static_slice_ul(si, 0, strdup("default"), algo, ulp)); const UE_list_t *UE_list = &RC.mac[mod_id]->UE_info.list; for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) @@ -575,7 +590,7 @@ pp_impl_param_t static_ul_init(module_id_t mod_id, int CC_id) { sttc.remove_UE = slicing_remove_UE; sttc.move_UE = slicing_move_UE; sttc.addmod_slice = addmod_static_slice_ul; - sttc.remove_slice = remove_static_slice; + sttc.remove_slice = remove_static_slice_ul; sttc.ul = static_ul; // current DL algo becomes default scheduler sttc.ul_algo = *algo; From 07313fd96d2b598ca5deb7574b2b7124fe9a0019 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Tue, 23 Jun 2020 13:25:28 +0200 Subject: [PATCH 501/553] FlexRAN Bugfix: Free Ringbuffer on exit --- openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c index e5d1c94c95..4c5f3e5609 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c @@ -1619,6 +1619,11 @@ int flexran_agent_unregister_mac_xface(mid_t mod_id) LOG_E(FLEXRAN_AGENT, "MAC agent CM for eNB %d is not registered\n", mod_id); return -1; } + + lfds700_ringbuffer_cleanup(&ringbuffer_state[mod_id], NULL ); + free(dl_mac_config_array[mod_id]); + lfds700_misc_library_cleanup(); + AGENT_MAC_xface *xface = agent_mac_xface[mod_id]; xface->flexran_agent_send_sr_info = NULL; xface->flexran_agent_send_sf_trigger = NULL; From 33b860f1b4a5eab264548281596cae53d03da414 Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Tue, 23 Jun 2020 13:50:59 +0200 Subject: [PATCH 502/553] FlexRAN: use lock-free ringbuffers for slice conf Use LFDS 7.0.0 Ringbuffer implementation to handle * Slice Configuration * UE slice association which is then uploaded through MAC scheduling thread --- .../CONTROL_MODULES/MAC/flexran_agent_mac.c | 100 ++++++++++++++++-- 1 file changed, 92 insertions(+), 8 deletions(-) diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c index 4c5f3e5609..f1daacbb65 100644 --- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c +++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c @@ -49,6 +49,14 @@ struct lfds700_misc_prng_state ps[NUM_MAX_ENB]; struct lfds700_ringbuffer_element *dl_mac_config_array[NUM_MAX_ENB]; struct lfds700_ringbuffer_state ringbuffer_state[NUM_MAX_ENB]; +/* Ringbuffer-related to slice configuration */ +struct lfds700_ringbuffer_element *slice_config_array[NUM_MAX_ENB]; +struct lfds700_ringbuffer_state slice_config_ringbuffer_state[NUM_MAX_ENB]; + +/* Ringbuffer-related to slice configuration */ +struct lfds700_ringbuffer_element *ue_assoc_array[NUM_MAX_ENB]; +struct lfds700_ringbuffer_state ue_assoc_ringbuffer_state[NUM_MAX_ENB]; + int flexran_agent_mac_stats_reply_ue(mid_t mod_id, Protocol__FlexUeStatsReport **ue_report, int n_ue, @@ -1341,6 +1349,33 @@ void flexran_agent_init_mac_agent(mid_t mod_id) { AssertFatal(i == 0, "posix_memalign(): could not allocate aligned memory for lfds library\n"); lfds700_ringbuffer_init_valid_on_current_logical_core(&ringbuffer_state[mod_id], dl_mac_config_array[mod_id], num_elements, &ps[mod_id], NULL); + + struct lfds700_misc_prng_state scrng; + i = posix_memalign((void **) &slice_config_array[mod_id], + LFDS700_PAL_ATOMIC_ISOLATION_IN_BYTES, + sizeof(struct lfds700_ringbuffer_element) * num_elements); + AssertFatal(i == 0, + "posix_memalign(): could not allocate aligned memory\n"); + lfds700_ringbuffer_init_valid_on_current_logical_core( + &slice_config_ringbuffer_state[mod_id], + slice_config_array[mod_id], + num_elements, + &scrng, + NULL); + + struct lfds700_misc_prng_state uarng; + i = posix_memalign((void **) &ue_assoc_array[mod_id], + LFDS700_PAL_ATOMIC_ISOLATION_IN_BYTES, + sizeof(struct lfds700_ringbuffer_element) * num_elements); + AssertFatal(i == 0, + "posix_memalign(): could not allocate aligned memory\n"); + lfds700_ringbuffer_init_valid_on_current_logical_core( + &ue_assoc_ringbuffer_state[mod_id], + ue_assoc_array[mod_id], + num_elements, + &uarng, + NULL); + for (i = 0; i < MAX_MOBILES_PER_ENB; i++) { for (j = 0; j < 8; j++) { if (RC.mac && RC.mac[mod_id]) @@ -1622,6 +1657,10 @@ int flexran_agent_unregister_mac_xface(mid_t mod_id) lfds700_ringbuffer_cleanup(&ringbuffer_state[mod_id], NULL ); free(dl_mac_config_array[mod_id]); + lfds700_ringbuffer_cleanup(&slice_config_ringbuffer_state[mod_id], NULL ); + free(slice_config_array[mod_id]); + lfds700_ringbuffer_cleanup(&ue_assoc_ringbuffer_state[mod_id], NULL ); + free(ue_assoc_array[mod_id]); lfds700_misc_library_cleanup(); AGENT_MAC_xface *xface = agent_mac_xface[mod_id]; @@ -1661,23 +1700,68 @@ void helper_destroy_mac_slice_config(Protocol__FlexSliceConfig *slice_config) { void prepare_update_slice_config(mid_t mod_id, Protocol__FlexSliceConfig **slice_config) { if (!*slice_config) return; + /* just use the memory and set to NULL in original */ Protocol__FlexSliceConfig *sc = *slice_config; *slice_config = NULL; - /* TODO handle using lock-free queue */ - apply_update_dl_slice_config(mod_id, sc->dl); - apply_update_ul_slice_config(mod_id, sc->ul); + struct lfds700_misc_prng_state ls; + LFDS700_MISC_MAKE_VALID_ON_CURRENT_LOGICAL_CORE_INITS_COMPLETED_BEFORE_NOW_ON_ANY_OTHER_LOGICAL_CORE; + lfds700_misc_prng_init(&ls); + enum lfds700_misc_flag overwrite_occurred_flag; - helper_destroy_mac_slice_config(*slice_config); + Protocol__FlexSliceConfig *overwritten_sc; + lfds700_ringbuffer_write(&slice_config_ringbuffer_state[mod_id], + NULL, + (void *)sc, + &overwrite_occurred_flag, + NULL, + (void **)&overwritten_sc, + &ls); + + if (overwrite_occurred_flag == LFDS700_MISC_FLAG_RAISED) { + helper_destroy_mac_slice_config(overwritten_sc); + LOG_E(FLEXRAN_AGENT, "lost slice config: too many reconfigurations at once\n"); + } } void prepare_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig **ue_config) { - /* TODO handle using lock-free queue */ - apply_ue_slice_assoc_update(mod_id, *ue_config); + struct lfds700_misc_prng_state ls; + LFDS700_MISC_MAKE_VALID_ON_CURRENT_LOGICAL_CORE_INITS_COMPLETED_BEFORE_NOW_ON_ANY_OTHER_LOGICAL_CORE; + lfds700_misc_prng_init(&ls); + enum lfds700_misc_flag overwrite_occurred_flag; - free(*ue_config); - *ue_config = NULL; + Protocol__FlexUeConfig *overwritten_ue_config; + lfds700_ringbuffer_write(&ue_assoc_ringbuffer_state[mod_id], + NULL, + (void *) *ue_config, + &overwrite_occurred_flag, + NULL, + (void **)&overwritten_ue_config, + &ls); + + if (overwrite_occurred_flag == LFDS700_MISC_FLAG_RAISED) { + free(overwritten_ue_config); + LOG_E(FLEXRAN_AGENT, "lost UE-slice association: too many UE-slice associations at once\n"); + } } void flexran_agent_slice_update(mid_t mod_id) { + struct lfds700_misc_prng_state ls; + LFDS700_MISC_MAKE_VALID_ON_CURRENT_LOGICAL_CORE_INITS_COMPLETED_BEFORE_NOW_ON_ANY_OTHER_LOGICAL_CORE; + lfds700_misc_prng_init(&ls); + + Protocol__FlexSliceConfig *sc = NULL; + struct lfds700_ringbuffer_state *state = &slice_config_ringbuffer_state[mod_id]; + if (lfds700_ringbuffer_read(state, NULL, (void **) &sc, &ls) != 0) { + apply_update_dl_slice_config(mod_id, sc->dl); + apply_update_ul_slice_config(mod_id, sc->ul); + helper_destroy_mac_slice_config(sc); + } + + Protocol__FlexUeConfig *ue_config = NULL; + state = &ue_assoc_ringbuffer_state[mod_id]; + if (lfds700_ringbuffer_read(state, NULL, (void **) &ue_config, &ls) != 0) { + apply_ue_slice_assoc_update(mod_id, ue_config); + free(ue_config); + } } From 6eb00a0895e2c6a9e9da94161c46cf8a060041ed Mon Sep 17 00:00:00 2001 From: Robert Schmidt Date: Mon, 20 Jul 2020 09:33:35 +0200 Subject: [PATCH 503/553] Enable multi-module support in pdcp_fifo_flush_sdus() --- openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c b/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c index 6c23332687..6c6bd30070 100644 --- a/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c +++ b/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c @@ -114,7 +114,9 @@ int pdcp_fifo_flush_sdus(const protocol_ctxt_t *const ctxt_pP) { int ret=0; while ((sdu_p = pollNotifiedFIFO(&pdcp_sdu_list)) != NULL ) { pdcp_data_ind_header_t * pdcpHead=(pdcp_data_ind_header_t *)NotifiedFifoData(sdu_p); - AssertFatal(pdcpHead->inst==ctxt_pP->module_id, "To implement correctly multi module id\n"); + + /* Note: we ignore the instance ID in the context and use the one in the + * PDCP packet to pick the right socket below */ int rb_id = pdcpHead->rb_id; int sizeToWrite= sizeof (pdcp_data_ind_header_t) + @@ -130,19 +132,19 @@ int pdcp_fifo_flush_sdus(const protocol_ctxt_t *const ctxt_pP) { sizeof(sidelink_pc5s_element), 0, (struct sockaddr *)&prose_pdcp_addr,sizeof(prose_pdcp_addr) ); } else if (UE_NAS_USE_TUN) { - //ret = write(nas_sock_fd[ctxt_pP->module_id], &(sdu_p->data[sizeof(pdcp_data_ind_header_t)]),sizeToWrite ); + //ret = write(nas_sock_fd[pdcpHead->inst], &(sdu_p->data[sizeof(pdcp_data_ind_header_t)]),sizeToWrite ); if(rb_id == mbms_rab_id){ ret = write(nas_sock_mbms_fd, pdcpData,sizeToWrite ); LOG_I(PDCP,"[PDCP_FIFOS] ret %d TRIED TO PUSH MBMS DATA TO rb_id %d handle %d sizeToWrite %d\n", - ret,rb_id,nas_sock_fd[ctxt_pP->module_id],sizeToWrite); + ret,rb_id,nas_sock_fd[pdcpHead->inst],sizeToWrite); } else { if( LOG_DEBUGFLAG(DEBUG_PDCP) ) log_dump(PDCP, pdcpData, sizeToWrite, LOG_DUMP_CHAR,"PDCP output to be sent to TUN interface: \n"); - ret = write(nas_sock_fd[ctxt_pP->module_id], pdcpData,sizeToWrite ); + ret = write(nas_sock_fd[pdcpHead->inst], pdcpData,sizeToWrite ); LOG_T(PDCP,"[UE PDCP_FIFOS] ret %d TRIED TO PUSH DATA TO rb_id %d handle %d sizeToWrite %d\n", - ret,rb_id,nas_sock_fd[ctxt_pP->module_id],sizeToWrite); + ret,rb_id,nas_sock_fd[pdcpHead->inst],sizeToWrite); } } else if (ENB_NAS_USE_TUN) { if( LOG_DEBUGFLAG(DEBUG_PDCP) ) From 331c74af2af9e0449441d716e24cec590accca39 Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Mon, 20 Jul 2020 14:21:11 +0200 Subject: [PATCH 504/553] fixing execution issues following recent changes --- ci-scripts/main.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ci-scripts/main.py b/ci-scripts/main.py index 7bfe331fc2..65a0b0d836 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -1911,7 +1911,7 @@ class OaiCiTest(): # Kill iperf server on EPC side if launchFromEpc: - SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password + SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password) SSH.command('killall --signal SIGKILL iperf', EPC.UserName, 5) SSH.close() else: @@ -3524,7 +3524,7 @@ elif re.match('^InitiateHtml$', mode, re.IGNORECASE): sys.exit('Insufficient Parameter') count = 0 foundCount = 0 - while (count < HTML.GetnbTestXMLfiles()): + while (count < HTML.nbTestXMLfiles): #xml_test_file = cwd + "/" + CiTestObj.testXMLfiles[count] xml_test_file = sys.path[0] + "/" + CiTestObj.testXMLfiles[count] if (os.path.isfile(xml_test_file)): From 0f0ede038d0148bd7f1aa35d6b49834feb21f965 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Mon, 20 Jul 2020 16:25:04 +0200 Subject: [PATCH 505/553] removing a printf in pusch scheduling --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 11a2f8d2a5..3a003ab1c6 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -918,8 +918,8 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, pusch_pdu->pusch_identity = *scc->physCellId; } pusch_dmrs_AdditionalPosition_t additional_pos; - if (NR_DMRS_UplinkConfig->dmrs_AdditionalPosition == NULL){printf("%d\n",2); - additional_pos = 2;} + if (NR_DMRS_UplinkConfig->dmrs_AdditionalPosition == NULL) + additional_pos = 2; else { if (*NR_DMRS_UplinkConfig->dmrs_AdditionalPosition == NR_DMRS_UplinkConfig__dmrs_AdditionalPosition_pos3) additional_pos = 3; From 87dccea43fdfd0a7871e6a8db1f7cc2135219119 Mon Sep 17 00:00:00 2001 From: hardy Date: Mon, 20 Jul 2020 16:44:51 +0200 Subject: [PATCH 506/553] integrating cots ue control into CI --- ci-scripts/cls_cots_ue.py | 89 +++++++++++++++++++++ ci-scripts/main.py | 7 ++ ci-scripts/xml_files/fr1_toggle_cots_ue.xml | 39 +++++++++ 3 files changed, 135 insertions(+) create mode 100644 ci-scripts/cls_cots_ue.py create mode 100644 ci-scripts/xml_files/fr1_toggle_cots_ue.xml diff --git a/ci-scripts/cls_cots_ue.py b/ci-scripts/cls_cots_ue.py new file mode 100644 index 0000000000..821d39fb6f --- /dev/null +++ b/ci-scripts/cls_cots_ue.py @@ -0,0 +1,89 @@ +# * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more +# * contributor license agreements. See the NOTICE file distributed with +# * this work for additional information regarding copyright ownership. +# * The OpenAirInterface Software Alliance licenses this file to You under +# * the OAI Public License, Version 1.1 (the "License"); you may not use this file +# * except in compliance with the License. +# * You may obtain a copy of the License at +# * +# * http://www.openairinterface.org/?page_id=698 +# * +# * Unless required by applicable law or agreed to in writing, software +# * distributed under the License is distributed on an "AS IS" BASIS, +# * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# * See the License for the specific language governing permissions and +# * limitations under the License. +# *------------------------------------------------------------------------------- +# * For more information about the OpenAirInterface (OAI) Software Alliance: +# * contact@openairinterface.org +# */ +#--------------------------------------------------------------------- +# Python for CI of OAI-eNB + COTS-UE +# +# Required Python Version +# Python 3.x +# +# Required Python Package +# pexpect +#--------------------------------------------------------------------- + +#to use logging.info() +import logging +#to create a SSH object locally in the methods +import sshconnection + + +class CotsUe: + def __init__(self,model,UEIPAddr,UEUserName,UEPassWord): + self.model = model + self.UEIPAddr = UEIPAddr + self.UEUserName = UEUserName + self.UEPassWord = UEPassWord + self.runargs = '' #on of off to toggle airplane mode on/off + self.__SetAirplaneRetry = 3 + +#-----------------$ +#PUBLIC Methods$ +#-----------------$ + + def Check_Airplane(self): + mySSH = sshconnection.SSHConnection() + mySSH.open(self.UEIPAddr, self.UEUserName, self.UEPassWord) + + mySSH.command('cd /home/oaici/remi/android-sdk-linux/platform-tools', '\$', 5) + status=mySSH.cde_check_value('sudo ./adb shell settings get global airplane_mode_on ', ['0','1'],5) + mySSH.close() + return status + + + def Set_Airplane(self,target_state_str): + print("toggling state to : "+target_state_str) + current_state = self.Check_Airplane() + if target_state_str.lower()=="on": + target_state=1 + else: + target_state=0 + if current_state != target_state: + #toggle state + mySSH = sshconnection.SSHConnection() + mySSH.open(self.UEIPAddr, self.UEUserName, self.UEPassWord) + retry = 0 + while (current_state!=target_state) and (retry < self.__SetAirplaneRetry): + mySSH.command('cd /home/oaici/remi/android-sdk-linux/platform-tools', '\$', 5) + mySSH.command('sudo ./adb shell am start -a android.settings.AIRPLANE_MODE_SETTINGS', '\$', 5) + mySSH.command('sudo ./adb shell input keyevent 20', '\$', 5) + mySSH.command('sudo ./adb shell input tap 968 324', '\$', 5) + time.sleep(1) + current_state = self.Check_Airplane() + retry+=1 + if current_state != target_state: + print("ATTENTION : Could not toggle to : "+target_state_str) + print("Current state is : "+ str(current_state)) + mySSH.close() + else: + print("Airplane mode is already "+ target_state_str) + + + + + diff --git a/ci-scripts/main.py b/ci-scripts/main.py index 65a0b0d836..d1103be3f2 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -3236,6 +3236,10 @@ def GetParametersFromXML(action): if action == 'Run_PhySim': ldpc.runargs = test.findtext('physim_run_args') + + if action == 'COTS_UE_Airplane': + COTS_UE=CotsUe('oppo', self.UEIPAddress, self.UEUserName,UEPassword) + COTS_UE.runargs = test.findtext('cots_ue_airplane_args') #check if given test is in list #it is in list if one of the strings in 'list' is at the beginning of 'test' @@ -3274,6 +3278,9 @@ RAN.EpcObj=EPC import cls_physim #class PhySim for physical simulators build and test ldpc=cls_physim.PhySim() #create an instance for LDPC test using GPU or CPU build +import cls_cots_ue #class CotsUe + + argvs = sys.argv argc = len(argvs) cwd = os.getcwd() diff --git a/ci-scripts/xml_files/fr1_toggle_cots_ue.xml b/ci-scripts/xml_files/fr1_toggle_cots_ue.xml new file mode 100644 index 0000000000..8271d333e2 --- /dev/null +++ b/ci-scripts/xml_files/fr1_toggle_cots_ue.xml @@ -0,0 +1,39 @@ + + + test-toggle-airplane-mode + Airplane + tasks + + 010101 + + + + + COTS_UE_Airplane + toggle on + ON + + + + From dfe6278ee175e650cca7cbb676219681ebc5370c Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Mon, 20 Jul 2020 18:06:02 +0200 Subject: [PATCH 507/553] fixing issues for CI integration --- ci-scripts/cls_cots_ue.py | 19 ++++++++++--------- ci-scripts/main.py | 13 ++++++++++--- ci-scripts/xml_files/fr1_toggle_cots_ue.xml | 2 +- 3 files changed, 21 insertions(+), 13 deletions(-) diff --git a/ci-scripts/cls_cots_ue.py b/ci-scripts/cls_cots_ue.py index 821d39fb6f..3e4c8179a8 100644 --- a/ci-scripts/cls_cots_ue.py +++ b/ci-scripts/cls_cots_ue.py @@ -31,7 +31,8 @@ import logging #to create a SSH object locally in the methods import sshconnection - +#time.sleep +import time class CotsUe: def __init__(self,model,UEIPAddr,UEUserName,UEPassWord): @@ -47,9 +48,8 @@ class CotsUe: #-----------------$ def Check_Airplane(self): - mySSH = sshconnection.SSHConnection() + mySSH = sshconnection.SSHConnection() mySSH.open(self.UEIPAddr, self.UEUserName, self.UEPassWord) - mySSH.command('cd /home/oaici/remi/android-sdk-linux/platform-tools', '\$', 5) status=mySSH.cde_check_value('sudo ./adb shell settings get global airplane_mode_on ', ['0','1'],5) mySSH.close() @@ -57,7 +57,11 @@ class CotsUe: def Set_Airplane(self,target_state_str): - print("toggling state to : "+target_state_str) + mySSH = sshconnection.SSHConnection() + mySSH.open(self.UEIPAddr, self.UEUserName, self.UEPassWord) + mySSH.command('cd /home/oaici/remi/android-sdk-linux/platform-tools', '\$', 5) + mySSH.command('sudo ./adb start-server','$',5) + logging.info("Toggling COTS UE Airplane mode to : "+target_state_str) current_state = self.Check_Airplane() if target_state_str.lower()=="on": target_state=1 @@ -65,11 +69,8 @@ class CotsUe: target_state=0 if current_state != target_state: #toggle state - mySSH = sshconnection.SSHConnection() - mySSH.open(self.UEIPAddr, self.UEUserName, self.UEPassWord) retry = 0 while (current_state!=target_state) and (retry < self.__SetAirplaneRetry): - mySSH.command('cd /home/oaici/remi/android-sdk-linux/platform-tools', '\$', 5) mySSH.command('sudo ./adb shell am start -a android.settings.AIRPLANE_MODE_SETTINGS', '\$', 5) mySSH.command('sudo ./adb shell input keyevent 20', '\$', 5) mySSH.command('sudo ./adb shell input tap 968 324', '\$', 5) @@ -79,10 +80,10 @@ class CotsUe: if current_state != target_state: print("ATTENTION : Could not toggle to : "+target_state_str) print("Current state is : "+ str(current_state)) - mySSH.close() else: print("Airplane mode is already "+ target_state_str) - + mySSH.command('sudo ./adb kill-server','$',5) + mySSH.close() diff --git a/ci-scripts/main.py b/ci-scripts/main.py index d1103be3f2..521cd3aa51 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -50,6 +50,7 @@ logging.basicConfig( format="[%(asctime)s] %(name)s:%(levelname)s: %(message)s" ) +import cls_cots_ue #----------------------------------------------------------- # Class Declaration @@ -3063,7 +3064,7 @@ class OaiCiTest(): logging.debug('\u001B[1m----------------------------------------\u001B[0m') def CheckClassValidity(action,id): - if action!='Build_PhySim' and action!='Run_PhySim' and action != 'Build_eNB' and action != 'WaitEndBuild_eNB' and action != 'Initialize_eNB' and action != 'Terminate_eNB' and action != 'Initialize_UE' and action != 'Terminate_UE' and action != 'Attach_UE' and action != 'Detach_UE' and action != 'Build_OAI_UE' and action != 'Initialize_OAI_UE' and action != 'Terminate_OAI_UE' and action != 'DataDisable_UE' and action != 'DataEnable_UE' and action != 'CheckStatusUE' and action != 'Ping' and action != 'Iperf' and action != 'Reboot_UE' and action != 'Initialize_FlexranCtrl' and action != 'Terminate_FlexranCtrl' and action != 'Initialize_HSS' and action != 'Terminate_HSS' and action != 'Initialize_MME' and action != 'Terminate_MME' and action != 'Initialize_SPGW' and action != 'Terminate_SPGW' and action != 'Initialize_CatM_module' and action != 'Terminate_CatM_module' and action != 'Attach_CatM_module' and action != 'Detach_CatM_module' and action != 'Ping_CatM_module' and action != 'IdleSleep' and action != 'Perform_X2_Handover': + if action!='COTS_UE_Airplane' and action!='Build_PhySim' and action!='Run_PhySim' and action != 'Build_eNB' and action != 'WaitEndBuild_eNB' and action != 'Initialize_eNB' and action != 'Terminate_eNB' and action != 'Initialize_UE' and action != 'Terminate_UE' and action != 'Attach_UE' and action != 'Detach_UE' and action != 'Build_OAI_UE' and action != 'Initialize_OAI_UE' and action != 'Terminate_OAI_UE' and action != 'DataDisable_UE' and action != 'DataEnable_UE' and action != 'CheckStatusUE' and action != 'Ping' and action != 'Iperf' and action != 'Reboot_UE' and action != 'Initialize_FlexranCtrl' and action != 'Terminate_FlexranCtrl' and action != 'Initialize_HSS' and action != 'Terminate_HSS' and action != 'Initialize_MME' and action != 'Terminate_MME' and action != 'Initialize_SPGW' and action != 'Terminate_SPGW' and action != 'Initialize_CatM_module' and action != 'Terminate_CatM_module' and action != 'Attach_CatM_module' and action != 'Detach_CatM_module' and action != 'Ping_CatM_module' and action != 'IdleSleep' and action != 'Perform_X2_Handover': logging.debug('ERROR: test-case ' + id + ' has wrong class ' + action) return False return True @@ -3238,7 +3239,6 @@ def GetParametersFromXML(action): ldpc.runargs = test.findtext('physim_run_args') if action == 'COTS_UE_Airplane': - COTS_UE=CotsUe('oppo', self.UEIPAddress, self.UEUserName,UEPassword) COTS_UE.runargs = test.findtext('cots_ue_airplane_args') #check if given test is in list @@ -3278,7 +3278,6 @@ RAN.EpcObj=EPC import cls_physim #class PhySim for physical simulators build and test ldpc=cls_physim.PhySim() #create an instance for LDPC test using GPU or CPU build -import cls_cots_ue #class CotsUe argvs = sys.argv @@ -3450,6 +3449,12 @@ while len(argvs) > 1: HELP.GenericHelp(CONST.Version) sys.exit('Invalid Parameter: ' + myArgv) + +COTS_UE=cls_cots_ue.CotsUe('oppo', CiTestObj.UEIPAddress, CiTestObj.UEUserName,CiTestObj.UEPassword) + + + + if re.match('^TerminateeNB$', mode, re.IGNORECASE): if RAN.eNBIPAddress == '' or RAN.eNBUserName == '' or RAN.eNBPassword == '': HELP.GenericHelp(CONST.Version) @@ -3754,6 +3759,8 @@ elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re if ldpc.exitStatus==1:sys.exit() elif action == 'Run_PhySim': HTML=ldpc.Run_PhySim(HTML,CONST,id) + elif action == 'COTS_UE_Airplane': + COTS_UE.Set_Airplane(COTS_UE.runargs) else: sys.exit('Invalid action') CiTestObj.FailReportCnt += 1 diff --git a/ci-scripts/xml_files/fr1_toggle_cots_ue.xml b/ci-scripts/xml_files/fr1_toggle_cots_ue.xml index 8271d333e2..371063c791 100644 --- a/ci-scripts/xml_files/fr1_toggle_cots_ue.xml +++ b/ci-scripts/xml_files/fr1_toggle_cots_ue.xml @@ -31,7 +31,7 @@ COTS_UE_Airplane - toggle on + Toggle COTS Airplane mode ON ON From d244ea4b994bd7cd7ec7877a3a2603949299fd89 Mon Sep 17 00:00:00 2001 From: hardy Date: Mon, 20 Jul 2020 22:45:24 +0200 Subject: [PATCH 508/553] slight reformatiing of main.py ; introducing yaml for xml class definition --- ci-scripts/main.py | 97 +++++++++++++++++++++++++---------- ci-scripts/xml_class_list.yml | 35 +++++++++++++ 2 files changed, 106 insertions(+), 26 deletions(-) create mode 100755 ci-scripts/xml_class_list.yml diff --git a/ci-scripts/main.py b/ci-scripts/main.py index 521cd3aa51..21d1104546 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -28,15 +28,30 @@ # pexpect #--------------------------------------------------------------------- -import constants as CONST #----------------------------------------------------------- -# Import +# Import Components +#----------------------------------------------------------- + +import helpreadme as HELP +import constants as CONST + +import cls_physim #class PhySim for physical simulators build and test +import cls_cots_ue #class CotsUe for Airplane mode control + +import sshconnection +import epc +import ran +import html + + +#----------------------------------------------------------- +# Import Libs #----------------------------------------------------------- import sys # arg import re # reg -import pexpect # pexpect +import pexpect # pexpect import time # sleep import os import subprocess @@ -50,10 +65,10 @@ logging.basicConfig( format="[%(asctime)s] %(name)s:%(levelname)s: %(message)s" ) -import cls_cots_ue + #----------------------------------------------------------- -# Class Declaration +# OaiCiTest Class Definition #----------------------------------------------------------- class OaiCiTest(): @@ -3054,20 +3069,33 @@ class OaiCiTest(): HTML.CpuMHz[idx]=CpuMHz SSH.close() -#----------------------------------------------------------- -# ShowTestID() -#----------------------------------------------------------- def ShowTestID(self): logging.debug('\u001B[1m----------------------------------------\u001B[0m') logging.debug('\u001B[1mTest ID:' + self.testCase_id + '\u001B[0m') logging.debug('\u001B[1m' + self.desc + '\u001B[0m') logging.debug('\u001B[1m----------------------------------------\u001B[0m') + + +#----------------------------------------------------------- +# General Functions +#----------------------------------------------------------- + + + def CheckClassValidity(action,id): - if action!='COTS_UE_Airplane' and action!='Build_PhySim' and action!='Run_PhySim' and action != 'Build_eNB' and action != 'WaitEndBuild_eNB' and action != 'Initialize_eNB' and action != 'Terminate_eNB' and action != 'Initialize_UE' and action != 'Terminate_UE' and action != 'Attach_UE' and action != 'Detach_UE' and action != 'Build_OAI_UE' and action != 'Initialize_OAI_UE' and action != 'Terminate_OAI_UE' and action != 'DataDisable_UE' and action != 'DataEnable_UE' and action != 'CheckStatusUE' and action != 'Ping' and action != 'Iperf' and action != 'Reboot_UE' and action != 'Initialize_FlexranCtrl' and action != 'Terminate_FlexranCtrl' and action != 'Initialize_HSS' and action != 'Terminate_HSS' and action != 'Initialize_MME' and action != 'Terminate_MME' and action != 'Initialize_SPGW' and action != 'Terminate_SPGW' and action != 'Initialize_CatM_module' and action != 'Terminate_CatM_module' and action != 'Attach_CatM_module' and action != 'Detach_CatM_module' and action != 'Ping_CatM_module' and action != 'IdleSleep' and action != 'Perform_X2_Handover': - logging.debug('ERROR: test-case ' + id + ' has wrong class ' + action) - return False - return True +# if action !='COTS_UE_Airplane' and action!='Build_PhySim' and action!='Run_PhySim' and action != 'Build_eNB' and action != 'WaitEndBuild_eNB' and action != 'Initialize_eNB' and action != 'Terminate_eNB' and +# action != 'Initialize_UE' and action != 'Terminate_UE' and action != 'Attach_UE' and action != 'Detach_UE' and action != 'Build_OAI_UE' and action != 'Initialize_OAI_UE' and action != 'Terminate_OAI_UE' and +# action != 'DataDisable_UE' and action != 'DataEnable_UE' and action != 'CheckStatusUE' and action != 'Ping' and action != 'Iperf' and action != 'Reboot_UE' and action != 'Initialize_FlexranCtrl' and +# action != 'Terminate_FlexranCtrl' and action != 'Initialize_HSS' and action != 'Terminate_HSS' and action != 'Initialize_MME' and action != 'Terminate_MME' and action != 'Initialize_SPGW' and +# action != 'Terminate_SPGW' and action != 'Initialize_CatM_module' and action != 'Terminate_CatM_module' and action != 'Attach_CatM_module' and action != 'Detach_CatM_module' and +# action != 'Ping_CatM_module' and action != 'IdleSleep' and action != 'Perform_X2_Handover': + if action not in xml_class_list: + logging.debug('ERROR: test-case ' + id + ' has unlisted class ' + action + ' ##CHECK xml_class_list.yml') + resp=False + else: + resp=True + return resp def GetParametersFromXML(action): if action == 'Build_eNB': @@ -3253,18 +3281,25 @@ def test_in_list(test, list): def receive_signal(signum, frame): sys.exit(1) -#----------------------------------------------------------- -# Parameter Check -#----------------------------------------------------------- -mode = '' -CiTestObj = OaiCiTest() -import sshconnection -import epc -import helpreadme as HELP -import ran -import html -import constants + + + + +#----------------------------------------------------------- +# MAIN PART +#----------------------------------------------------------- + +#loading xml action list from yaml +import yaml +with open('xml_class_list.yml','r') as file: + # The FullLoader parameter handles the conversion from YAML + # scalar values to Python the dictionary format + xml_class_list = yaml.load(file,Loader=yaml.FullLoader) + +mode = '' + +CiTestObj = OaiCiTest() SSH = sshconnection.SSHConnection() EPC = epc.EPCManagement() @@ -3275,11 +3310,15 @@ EPC.HtmlObj=HTML RAN.HtmlObj=HTML RAN.EpcObj=EPC -import cls_physim #class PhySim for physical simulators build and test + ldpc=cls_physim.PhySim() #create an instance for LDPC test using GPU or CPU build +#----------------------------------------------------------- +# Parameter Check +#----------------------------------------------------------- + argvs = sys.argv argc = len(argvs) cwd = os.getcwd() @@ -3450,10 +3489,16 @@ while len(argvs) > 1: sys.exit('Invalid Parameter: ' + myArgv) +#----------------------------------------------------------- +# COTS UE instanciation +#----------------------------------------------------------- +#COTS_UE instanciation can only be done here for the moment, due to code architecture COTS_UE=cls_cots_ue.CotsUe('oppo', CiTestObj.UEIPAddress, CiTestObj.UEUserName,CiTestObj.UEPassword) - +#----------------------------------------------------------- +# XML class (action) analysis +#----------------------------------------------------------- if re.match('^TerminateeNB$', mode, re.IGNORECASE): if RAN.eNBIPAddress == '' or RAN.eNBUserName == '' or RAN.eNBPassword == '': @@ -3762,7 +3807,7 @@ elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re elif action == 'COTS_UE_Airplane': COTS_UE.Set_Airplane(COTS_UE.runargs) else: - sys.exit('Invalid action') + sys.exit('Invalid class (action) from xml') CiTestObj.FailReportCnt += 1 if CiTestObj.FailReportCnt == CiTestObj.repeatCounts[0] and RAN.prematureExit: logging.debug('Testsuite failed ' + str(CiTestObj.FailReportCnt) + ' time(s)') diff --git a/ci-scripts/xml_class_list.yml b/ci-scripts/xml_class_list.yml new file mode 100755 index 0000000000..56890c1fc6 --- /dev/null +++ b/ci-scripts/xml_class_list.yml @@ -0,0 +1,35 @@ + - COTS_UE_Airplane + - Build_PhySim + - Run_PhySim + - Build_eNB + - WaitEndBuild_eNB + - Initialize_eNB + - Terminate_eNB + - Initialize_UE + - Terminate_UE + - Attach_UE + - Detach_UE + - Build_OAI_UE + - Initialize_OAI_UE + - Terminate_OAI_UE + - DataDisable_UE + - DataEnable_ + - CheckStatusUE + - Ping + - Iperf + - Reboot_UE + - Initialize_FlexranCtrl + - Terminate_FlexranCtrl + - Initialize_HSS + - Terminate_HSS + - Initialize_MME + - Terminate_MME + - Initialize_SPGW + - Terminate_SPGW + - Initialize_CatM_module + - Terminate_CatM_module + - Attach_CatM_module + - Detach_CatM_module + - Ping_CatM_module + - IdleSleep + - Perform_X2_Handover From 3d365b0d8ef46905b8fedf05a1485f3b65bf54f9 Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Tue, 21 Jul 2020 17:04:23 +0200 Subject: [PATCH 509/553] WIP fr1 set up --- ci-scripts/cls_cots_ue.py | 4 ++-- ci-scripts/ran.py | 3 ++- ci-scripts/xml_files/fr1_multi_node_build.xml | 20 ++++++++----------- ci-scripts/xml_files/fr1_toggle_cots_ue.xml | 4 ++-- 4 files changed, 14 insertions(+), 17 deletions(-) diff --git a/ci-scripts/cls_cots_ue.py b/ci-scripts/cls_cots_ue.py index 3e4c8179a8..23feba982b 100644 --- a/ci-scripts/cls_cots_ue.py +++ b/ci-scripts/cls_cots_ue.py @@ -78,8 +78,8 @@ class CotsUe: current_state = self.Check_Airplane() retry+=1 if current_state != target_state: - print("ATTENTION : Could not toggle to : "+target_state_str) - print("Current state is : "+ str(current_state)) + logging.error("ATTENTION : Could not toggle to : "+target_state_str) + logging.error("Current state is : "+ str(current_state)) else: print("Airplane mode is already "+ target_state_str) mySSH.command('sudo ./adb kill-server','$',5) diff --git a/ci-scripts/ran.py b/ci-scripts/ran.py index 5673b4c082..6ebecec843 100644 --- a/ci-scripts/ran.py +++ b/ci-scripts/ran.py @@ -431,7 +431,8 @@ class RANManagement(): os.remove('./tmp_build' + testcaseId + '.zip') mySSH.open(self.eNBIPAddress, self.eNBUserName, self.eNBPassword) mySSH.command('cd ' + self.eNBSourceCodePath + '/cmake_targets', '\$', 5) - mySSH.command('unzip -qq -DD tmp_build' + testcaseId + '.zip', '\$', 5) + #-qq quiet / -u update orcreate files + mySSH.command('unzip -u -qq -DD tmp_build' + testcaseId + '.zip', '\$', 5) mySSH.command('rm -f tmp_build' + testcaseId + '.zip', '\$', 5) mySSH.close() else: diff --git a/ci-scripts/xml_files/fr1_multi_node_build.xml b/ci-scripts/xml_files/fr1_multi_node_build.xml index b2c0daa74e..579eef27a8 100644 --- a/ci-scripts/xml_files/fr1_multi_node_build.xml +++ b/ci-scripts/xml_files/fr1_multi_node_build.xml @@ -25,41 +25,37 @@ Build wrench - 010101 010102 - 000101 000102 + 000001 000002 + 000003 000004 - + Build_eNB Build eNB - -w USRP -c --eNB --ninja + -w USRP -c --eNB 0 0 - True - + WaitEndBuild_eNB Wait for end of Build eNB - -w USRP -c --eNB --ninja 0 0 - + Build_eNB Build gNB - -w USRP -c --gNB --ninja + -w USRP -c --gNB 1 1 - True - + WaitEndBuild_eNB Wait for end of Build gNB - -w USRP -c --gNB --ninja 1 1 diff --git a/ci-scripts/xml_files/fr1_toggle_cots_ue.xml b/ci-scripts/xml_files/fr1_toggle_cots_ue.xml index 371063c791..ee4d36f00a 100644 --- a/ci-scripts/xml_files/fr1_toggle_cots_ue.xml +++ b/ci-scripts/xml_files/fr1_toggle_cots_ue.xml @@ -25,11 +25,11 @@ Airplane tasks - 010101 + 010000 - + COTS_UE_Airplane Toggle COTS Airplane mode ON ON From 4b48e457ba86b951c98fb10b5e61960f233cf686 Mon Sep 17 00:00:00 2001 From: hardy Date: Tue, 21 Jul 2020 23:55:20 +0200 Subject: [PATCH 510/553] WIP : yaml config files for multiple eNB or gNB nodes --- ci-scripts/main.py | 39 ++++++++++++++++++++++++++-- ci-scripts/py_params.yaml | 54 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 91 insertions(+), 2 deletions(-) create mode 100644 ci-scripts/py_params.yaml diff --git a/ci-scripts/main.py b/ci-scripts/main.py index 21d1104546..2865f5984b 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -3083,7 +3083,7 @@ class OaiCiTest(): -def CheckClassValidity(action,id): +def CheckClassValidity(xml_class_list,action,id): # if action !='COTS_UE_Airplane' and action!='Build_PhySim' and action!='Run_PhySim' and action != 'Build_eNB' and action != 'WaitEndBuild_eNB' and action != 'Initialize_eNB' and action != 'Terminate_eNB' and # action != 'Initialize_UE' and action != 'Terminate_UE' and action != 'Attach_UE' and action != 'Detach_UE' and action != 'Build_OAI_UE' and action != 'Initialize_OAI_UE' and action != 'Terminate_OAI_UE' and # action != 'DataDisable_UE' and action != 'DataEnable_UE' and action != 'CheckStatusUE' and action != 'Ping' and action != 'Iperf' and action != 'Reboot_UE' and action != 'Initialize_FlexranCtrl' and @@ -3097,6 +3097,20 @@ def CheckClassValidity(action,id): resp=True return resp + +#assigning parameters to object instance attributes (even if the attributes do not exist !!) +def AssignParams(params_dict): + #-- + mode=params_dict['mode'] + #-- + for key,value in params_dict.items(): + setattr(CITestObj, key, value) + setattr(RAN, key, value) + setattr(HTML, key, value) + setattr(ldpc, key, value) + + + def GetParametersFromXML(action): if action == 'Build_eNB': RAN.Build_eNB_args=test.findtext('Build_eNB_args') @@ -3326,9 +3340,23 @@ cwd = os.getcwd() while len(argvs) > 1: myArgv = argvs.pop(1) # 0th is this file's name + #--help if re.match('^\-\-help$', myArgv, re.IGNORECASE): HELP.GenericHelp(CONST.Version) sys.exit(0) + + #--apply= as parameters file, to replace inline parameters + elif re.match('^\-\-apply=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-apply=(.+)$', myArgv, re.IGNORECASE) + py_params_file = matchReg.group(1) + with open(py_params_file,'r') as file: + # The FullLoader parameter handles the conversion from YAML + # scalar values to Python dictionary format + py_params = yaml.load(file,Loader=yaml.FullLoader) + py_param_file_present = True #to be removed once validated + #AssignParams(py_params) #to be uncommented once validated + + #consider inline parameters elif re.match('^\-\-mode=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-mode=(.+)$', myArgv, re.IGNORECASE) mode = matchReg.group(1) @@ -3489,6 +3517,13 @@ while len(argvs) > 1: sys.exit('Invalid Parameter: ' + myArgv) +#----------------------------------------------------------- +# TEMPORARY params management +#----------------------------------------------------------- +#temporary solution for testing: +if py_param_file_present == True: + AssignParams(py_params) + #----------------------------------------------------------- # COTS UE instanciation #----------------------------------------------------------- @@ -3723,7 +3758,7 @@ elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re CiTestObj.desc = test.findtext('desc') HTML.desc=CiTestObj.desc action = test.findtext('class') - if (CheckClassValidity(action, id) == False): + if (CheckClassValidity(xml_class_list, action, id) == False): continue CiTestObj.ShowTestID() GetParametersFromXML(action) diff --git a/ci-scripts/py_params.yaml b/ci-scripts/py_params.yaml new file mode 100644 index 0000000000..68471763f7 --- /dev/null +++ b/ci-scripts/py_params.yaml @@ -0,0 +1,54 @@ +mode : a +eNBRepository : b +ranRepository : c +eNB_AllowMerge : +ranAllowMerge : +eNBBranch : f +ranBranch : g +eNBCommitID : +ranCommitID : i +eNBTargetBranch : j +ranTargetBranch : k + +nodes : + - type : eNB + IPAddress : 001.1.1 + UserName : toto + Password : qwe + SourceCodePath : l + - type : gNB + IPAddress : 002.2.2 + UserName : tata + Password : asd + SourceCodePath : m + - type : eNB + IPAddress : 003.3.3 + UserName : titi + Password : zxc + SourceCodePath : n + - type : gNB + IPAddress : 004.4.4 + UserName : caca + Password : pepe + SourceCodePath : o + +EPCIPAddress : p +EPCUserName : q +EPCPassword : r +EPCSourceCodePath : s +EPCType : t +EPCContainerPrefix : u + +ADBIPAddress : v +ADBUserName : w +ADBType : x +ADBPassword : y + +XMLTestFile : z + +UEIPAddress : qqq +UEUserName : www +UEPassword : eee +UESourceCodePath : yyy + +finalStatus : bbb \ No newline at end of file From 5331189c8b78568a035f91f3000ab37cad5d4c57 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Wed, 22 Jul 2020 15:07:04 +0200 Subject: [PATCH 511/553] bugfixes --- openair1/SCHED_NR/fapi_nr_l1.c | 1 + openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/openair1/SCHED_NR/fapi_nr_l1.c b/openair1/SCHED_NR/fapi_nr_l1.c index ddebcc3e06..2870f1d42e 100644 --- a/openair1/SCHED_NR/fapi_nr_l1.c +++ b/openair1/SCHED_NR/fapi_nr_l1.c @@ -160,6 +160,7 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){ gNB->dlsch[i][0]->harq_mask=0; } gNB->pdcch_pdu = NULL; + gNB->ul_dci_pdu = NULL; gNB->pbch_configured=0; for (int i=0;irv = pusch_pdu->pusch_data.rv_index; dci_pdu_rel15->harq_pid = pusch_pdu->pusch_data.harq_process_id; dci_pdu_rel15->frequency_hopping_flag.val = pusch_pdu->frequency_hopping; - //dci_pdu_rel15->dai[0].val = ???; //TODO + dci_pdu_rel15->dai[0].val = 0; //TODO // bwp indicator if (n_ubwp < 4) dci_pdu_rel15->bwp_indicator.val = bwp_id; From 39b22f17b330332621a0572c7e2717c94cd821ab Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Wed, 22 Jul 2020 15:11:17 +0200 Subject: [PATCH 512/553] calloc for dci_pdu --- openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c | 1 - openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 7 ++++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index 10d4e9ab3c..f40d822b6b 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -2010,7 +2010,6 @@ uint16_t nr_dci_size(NR_ServingCellConfigCommon_t *scc, } // Precoding info and number of layers long transformPrecoder; - dci_pdu->precoding_information.nbits = 0; if (pusch_Config->transformPrecoder == NULL){ // if transform precoder is null, apply the values from msg3 if(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder == NULL) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index c1565bd408..89de2da0e5 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -1052,9 +1052,10 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, return; } else { - dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET]; - config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types,n_ubwp,bwp_id); - fill_dci_pdu_rel15(scc,secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types,pusch_pdu->bwp_size,bwp_id); + dci_pdu_rel15_t *dci_pdu_rel15 = calloc(MAX_DCI_CORESET,sizeof(dci_pdu_rel15_t)); + config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types,time_domain_assignment,n_ubwp,bwp_id); + fill_dci_pdu_rel15(scc,secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types,pusch_pdu->bwp_size,bwp_id); + free(dci_pdu_rel15); } } From 390c648a81ee2b209b73dbdb5b5dce7a7d51a4e4 Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Wed, 22 Jul 2020 09:13:04 +0200 Subject: [PATCH 513/553] bugfix in time domain assigment --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 5 +++-- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 89de2da0e5..8841083796 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -474,6 +474,7 @@ void config_uldci(NR_BWP_Uplink_t *ubwp, nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types, + int time_domain_assignment, int n_ubwp, int bwp_id) { switch(dci_formats[(pdcch_pdu_rel15->numDlDci)-1]) { @@ -482,7 +483,7 @@ void config_uldci(NR_BWP_Uplink_t *ubwp, pusch_pdu->rb_start, NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275)); - dci_pdu_rel15->time_domain_assignment.val = 2; // row index used here instead of SLIV; + dci_pdu_rel15->time_domain_assignment.val = time_domain_assignment; dci_pdu_rel15->frequency_hopping_flag.val = pusch_pdu->frequency_hopping; dci_pdu_rel15->mcs = 9; @@ -511,7 +512,7 @@ void config_uldci(NR_BWP_Uplink_t *ubwp, else AssertFatal(1==0,"Only frequency resource allocation type 1 is currently supported\n"); // time domain assignment - dci_pdu_rel15->time_domain_assignment.val = 2; + dci_pdu_rel15->time_domain_assignment.val = time_domain_assignment; // mcs dci_pdu_rel15->mcs = pusch_pdu->mcs_index; // tpc command for pusch diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index 8b38c357c6..74c6841a3a 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -137,6 +137,7 @@ void config_uldci(NR_BWP_Uplink_t *ubwp, nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types, + int time_domain_assignment, int n_ubwp, int bwp_id); void configure_fapi_dl_Tx(module_id_t Mod_idP, From 220445f15798ee7daec0970d930fcb23af3a5dc4 Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Wed, 22 Jul 2020 17:53:28 +0200 Subject: [PATCH 514/553] wip : fr1 set up automation / fixing issues from recent changes --- ci-scripts/main.py | 10 +++++----- ci-scripts/ran.py | 11 ++++++----- ci-scripts/xml_files/fr1_multi_node_build.xml | 1 + ci-scripts/xml_files/fr1_toggle_cots_ue.xml | 4 ++-- 4 files changed, 14 insertions(+), 12 deletions(-) diff --git a/ci-scripts/main.py b/ci-scripts/main.py index 2865f5984b..82a1da0390 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -3320,9 +3320,9 @@ EPC = epc.EPCManagement() RAN = ran.RANManagement() HTML = html.HTMLManagement() -EPC.HtmlObj=HTML -RAN.HtmlObj=HTML -RAN.EpcObj=EPC +EPC.htmlObj=HTML +RAN.htmlObj=HTML +RAN.epcObj=EPC ldpc=cls_physim.PhySim() #create an instance for LDPC test using GPU or CPU build @@ -3336,7 +3336,7 @@ ldpc=cls_physim.PhySim() #create an instance for LDPC test using GPU or CPU b argvs = sys.argv argc = len(argvs) cwd = os.getcwd() - +py_param_file_present = False while len(argvs) > 1: myArgv = argvs.pop(1) # 0th is this file's name @@ -3352,7 +3352,7 @@ while len(argvs) > 1: with open(py_params_file,'r') as file: # The FullLoader parameter handles the conversion from YAML # scalar values to Python dictionary format - py_params = yaml.load(file,Loader=yaml.FullLoader) + py_params = yaml.load(file,Loader=yaml.FullLoader) py_param_file_present = True #to be removed once validated #AssignParams(py_params) #to be uncommented once validated diff --git a/ci-scripts/ran.py b/ci-scripts/ran.py index 6ebecec843..23a004e4ce 100644 --- a/ci-scripts/ran.py +++ b/ci-scripts/ran.py @@ -274,7 +274,7 @@ class RANManagement(): if self.Build_eNB_forced_workspace_cleanup: mySSH.command('echo ' + lPassWord + ' | sudo -S rm -Rf ' + lSourcePath, '\$', 15) if self.htmlObj is not None: - self.testCase_id = self.htmlObj.GettestCase_id() + self.testCase_id = self.htmlObj.testCase_id else: self.testCase_id = '000000' # on RedHat/CentOS .git extension is mandatory @@ -388,7 +388,7 @@ class RANManagement(): def checkBuildeNB(self, lIpAddr, lUserName, lPassWord, lSourcePath, testcaseId): if self.htmlObj is not None: - self.htmlObj.SettestCase_id(testcaseId) + self.htmlObj.testCase_id=testcaseId mySSH = SSH.SSHConnection() mySSH.open(lIpAddr, lUserName, lPassWord) @@ -397,6 +397,7 @@ class RANManagement(): mySSH.command('ls ran_build/build', '\$', 3) #check if we have the build corresponding to the air interface keywords (nr-softmode, lte-softmodem, ocp-enb) + logging.info('CHECK Build with IP='+lIpAddr+' SourcePath='+lSourcePath) result = re.search(self.air_interface, mySSH.getBefore()) if result is None: buildStatus = False #if not, build failed @@ -471,7 +472,7 @@ class RANManagement(): sys.exit('Insufficient Parameter') if self.htmlObj is not None: - self.testCase_id = self.htmlObj.GettestCase_id() + self.testCase_id = self.htmlObj.testCase_id else: self.testCase_id = '000000' mySSH = SSH.SSHConnection() @@ -762,7 +763,7 @@ class RANManagement(): if (copyin_res == -1): logging.debug('\u001B[1;37;41m Could not copy ' + nodeB_prefix + 'NB logfile to analyze it! \u001B[0m') if self.htmlObj is not None: - self.htmlObj.SetHmleNBFailureMsg('Could not copy ' + nodeB_prefix + 'NB logfile to analyze it!') + self.htmlObj.HmleNBFailureMsg='Could not copy ' + nodeB_prefix + 'NB logfile to analyze it!' self.htmlObj.CreateHtmlTestRow('N/A', 'KO', CONST.ENB_PROCESS_NOLOGFILE_TO_ANALYZE) self.eNBmbmsEnables[int(self.eNB_instance)] = False return @@ -1065,5 +1066,5 @@ class RANManagement(): htmleNBFailureMsg += rlcMsg + '\n' global_status = CONST.ENB_PROCESS_REALTIME_ISSUE if self.htmlObj is not None: - self.htmlObj.SetHmleNBFailureMsg(htmleNBFailureMsg) + self.htmlObj.HmleNBFailureMsg=htmleNBFailureMsg return global_status diff --git a/ci-scripts/xml_files/fr1_multi_node_build.xml b/ci-scripts/xml_files/fr1_multi_node_build.xml index 579eef27a8..0b7dce29d8 100644 --- a/ci-scripts/xml_files/fr1_multi_node_build.xml +++ b/ci-scripts/xml_files/fr1_multi_node_build.xml @@ -60,4 +60,5 @@ 1 + diff --git a/ci-scripts/xml_files/fr1_toggle_cots_ue.xml b/ci-scripts/xml_files/fr1_toggle_cots_ue.xml index ee4d36f00a..b2267efc77 100644 --- a/ci-scripts/xml_files/fr1_toggle_cots_ue.xml +++ b/ci-scripts/xml_files/fr1_toggle_cots_ue.xml @@ -21,8 +21,8 @@ --> - test-toggle-airplane-mode - Airplane + test-airplane-mode + AirplaneToggle tasks 010000 From 3d8e5e11ef14508fc767ae0fb7bb1c63dec1153e Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Wed, 22 Jul 2020 17:56:51 +0200 Subject: [PATCH 515/553] fixes for buffer overrun when L1 information is cleared upon UE removal in RRC. This is a temporary fix to solve a stability issue for Benetel pending more significant changes along the same lines in several places. --- openair2/RRC/LTE/rrc_eNB.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index 1d44751dca..35a45714c4 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -994,11 +994,14 @@ void put_UE_in_freelist(module_id_t mod_id, rnti_t rnti, boolean_t removeFlag) { pthread_mutex_unlock(&lock_ue_freelist); } +extern int16_t find_dlsch(uint16_t rnti, PHY_VARS_eNB *eNB,find_type_t type); +extern int16_t find_ulsch(uint16_t rnti, PHY_VARS_eNB *eNB,find_type_t type); +extern void clean_eNb_ulsch(LTE_eNB_ULSCH_t *ulsch); +extern void clean_eNb_dlsch(LTE_eNB_DLSCH_t *dlsch); + void release_UE_in_freeList(module_id_t mod_id) { int i, j, CC_id, pdu_number; protocol_ctxt_t ctxt; - LTE_eNB_ULSCH_t *ulsch = NULL; - LTE_eNB_DLSCH_t *dlsch = NULL; nfapi_ul_config_request_body_t *ul_req_tmp = NULL; PHY_VARS_eNB *eNB_PHY = NULL; struct rrc_eNB_ue_context_s *ue_context_pP = NULL; @@ -1032,6 +1035,25 @@ void release_UE_in_freeList(module_id_t mod_id) { for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { eNB_PHY = RC.eNB[mod_id][CC_id]; + int id; + + // clean ULSCH entries for rnti + id = find_ulsch(rnti,eNB_PHY,SEARCH_EXIST); + if (id>0) clean_eNb_ulsch(eNB_PHY->ulsch[id]); + + // clean DLSCH entries for rnti + id = find_dlsch(rnti,eNB_PHY,SEARCH_EXIST); + if (id>0) clean_eNb_dlsch(eNB_PHY->dlsch[id][0]); + + // clean UCI entries for rnti + for (i=0; iuci_vars[i].rnti == rnti) { + LOG_I(MAC, "clean eNb uci_vars[%d] UE %x \n",i, rnti); + memset(&eNB_PHY->uci_vars[i],0,sizeof(LTE_eNB_UCI)); + } + } + + /* for (i=0; iulsch[i]; @@ -1064,6 +1086,7 @@ void release_UE_in_freeList(module_id_t mod_id) { memset(&eNB_PHY->uci_vars[i],0,sizeof(LTE_eNB_UCI)); } } + */ if (flexran_agent_get_rrc_xface(mod_id)) { flexran_agent_get_rrc_xface(mod_id)->flexran_agent_notify_ue_state_change( From 1f74524d0dc72e357872c25a4431d46f926a17dc Mon Sep 17 00:00:00 2001 From: Francesco Mani Date: Thu, 23 Jul 2020 10:10:19 +0200 Subject: [PATCH 516/553] fix for prepare dci 0_1 --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index a22d4988df..876f1b5396 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -820,7 +820,7 @@ void fill_dci_pdu_rel15(NR_ServingCellConfigCommon_t *scc, pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d] = dci_size; AssertFatal(pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d]<=64, "DCI sizes above 64 bits not yet supported"); - if(dci_formats[d]==NR_DL_DCI_FORMAT_1_1) + if(dci_formats[d]==NR_DL_DCI_FORMAT_1_1 || dci_formats[d]==NR_UL_DCI_FORMAT_0_1) prepare_dci(secondaryCellGroup,&dci_pdu_rel15[d],dci_formats[d],bwp_id); /// Payload generation From d8bbfdbddaf719142a3d073bb907f285a800aaa5 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Thu, 23 Jul 2020 22:24:55 +0200 Subject: [PATCH 517/553] bugfix in eNB_scheduler.c. Code still to be moved to L1. --- openair2/LAYER2/MAC/eNB_scheduler.c | 19 ++++++++++++++++++- openair2/RRC/LTE/rrc_eNB.c | 4 ++-- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/openair2/LAYER2/MAC/eNB_scheduler.c b/openair2/LAYER2/MAC/eNB_scheduler.c index c46005ee2d..d184c7e439 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler.c +++ b/openair2/LAYER2/MAC/eNB_scheduler.c @@ -547,7 +547,7 @@ copy_ulreq(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP) { ul_req_tmp->ul_config_request_body.number_of_pdus = 0; if (ul_req->ul_config_request_body.number_of_pdus>0) { - LOG_D(PHY, "%s() active NOW (frameP:%d subframeP:%d) pdus:%d\n", __FUNCTION__, frameP, subframeP, ul_req->ul_config_request_body.number_of_pdus); + LOG_D(MAC, "%s() active NOW (frameP:%d subframeP:%d) pdus:%d\n", __FUNCTION__, frameP, subframeP, ul_req->ul_config_request_body.number_of_pdus); } memcpy((void *)ul_req->ul_config_request_body.ul_config_pdu_list, @@ -556,6 +556,11 @@ copy_ulreq(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP) { } } +extern int16_t find_dlsch(uint16_t rnti, PHY_VARS_eNB *eNB,find_type_t type); +extern int16_t find_ulsch(uint16_t rnti, PHY_VARS_eNB *eNB,find_type_t type); +extern void clean_eNb_ulsch(LTE_eNB_ULSCH_t *ulsch); +extern void clean_eNb_dlsch(LTE_eNB_DLSCH_t *dlsch); + void eNB_dlsch_ulsch_scheduler(module_id_t module_idP, frame_t frameP, @@ -843,6 +848,7 @@ eNB_dlsch_ulsch_scheduler(module_id_t module_idP, } /* Note: This should not be done in the MAC! */ + /* for (int ii=0; iiulsch[ii]; @@ -862,6 +868,17 @@ eNB_dlsch_ulsch_scheduler(module_id_t module_idP, clean_eNb_dlsch(dlsch); } } + */ + + int id; + + // clean ULSCH entries for rnti + id = find_ulsch(rnti,RC.eNB[module_idP][CC_id],SEARCH_EXIST); + if (id>=0) clean_eNb_ulsch(RC.eNB[module_idP][CC_id]->ulsch[id]); + + // clean DLSCH entries for rnti + id = find_dlsch(rnti,RC.eNB[module_idP][CC_id],SEARCH_EXIST); + if (id>=0) clean_eNb_dlsch(RC.eNB[module_idP][CC_id]->dlsch[id][0]); for (int j = 0; j < 10; j++) { nfapi_ul_config_request_body_t *ul_req_tmp = NULL; diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c index 35a45714c4..16d5065d37 100644 --- a/openair2/RRC/LTE/rrc_eNB.c +++ b/openair2/RRC/LTE/rrc_eNB.c @@ -1039,11 +1039,11 @@ void release_UE_in_freeList(module_id_t mod_id) { // clean ULSCH entries for rnti id = find_ulsch(rnti,eNB_PHY,SEARCH_EXIST); - if (id>0) clean_eNb_ulsch(eNB_PHY->ulsch[id]); + if (id>=0) clean_eNb_ulsch(eNB_PHY->ulsch[id]); // clean DLSCH entries for rnti id = find_dlsch(rnti,eNB_PHY,SEARCH_EXIST); - if (id>0) clean_eNb_dlsch(eNB_PHY->dlsch[id][0]); + if (id>=0) clean_eNb_dlsch(eNB_PHY->dlsch[id][0]); // clean UCI entries for rnti for (i=0; i Date: Fri, 24 Jul 2020 18:03:22 +0200 Subject: [PATCH 518/553] brought cde line arg parsing out of main.py, into a separated module --- ci-scripts/args_parse.py | 229 +++++++++++++++++ ci-scripts/main.py | 385 +++++++++++++++-------------- ci-scripts/py_params.yaml | 1 - ci-scripts/py_params_template.yaml | 97 ++++++++ 4 files changed, 524 insertions(+), 188 deletions(-) create mode 100644 ci-scripts/args_parse.py create mode 100644 ci-scripts/py_params_template.yaml diff --git a/ci-scripts/args_parse.py b/ci-scripts/args_parse.py new file mode 100644 index 0000000000..a36f619ee2 --- /dev/null +++ b/ci-scripts/args_parse.py @@ -0,0 +1,229 @@ + +# * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more +# * contributor license agreements. See the NOTICE file distributed with +# * this work for additional information regarding copyright ownership. +# * The OpenAirInterface Software Alliance licenses this file to You under +# * the OAI Public License, Version 1.1 (the "License"); you may not use this file +# * except in compliance with the License. +# * You may obtain a copy of the License at +# * +# * http://www.openairinterface.org/?page_id=698 +# * +# * Unless required by applicable law or agreed to in writing, software +# * distributed under the License is distributed on an "AS IS" BASIS, +# * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# * See the License for the specific language governing permissions and +# * limitations under the License. +# *------------------------------------------------------------------------------- +# * For more information about the OpenAirInterface (OAI) Software Alliance: +# * contact@openairinterface.org +# */ +#--------------------------------------------------------------------- +# Python for CI of OAI-eNB + COTS-UE +# +# Required Python Version +# Python 3.x +# +# Required Python Package +# pexpect +#--------------------------------------------------------------------- + +#----------------------------------------------------------- +# Import Libs +#----------------------------------------------------------- +import sys # arg +import re # reg +import yaml + + +#----------------------------------------------------------- +# Parsing Command Line Arguements +#----------------------------------------------------------- + + +def ArgsParse(argvs,CiTestObj,RAN,HTML,ldpc,HELP): + + + py_param_file_present = False + py_params={} + + while len(argvs) > 1: + myArgv = argvs.pop(1) # 0th is this file's name + + #--help + if re.match('^\-\-help$', myArgv, re.IGNORECASE): + HELP.GenericHelp(CONST.Version) + sys.exit(0) + + #--apply= as parameters file, to replace inline parameters + elif re.match('^\-\-Apply=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-Apply=(.+)$', myArgv, re.IGNORECASE) + py_params_file = matchReg.group(1) + with open(py_params_file,'r') as file: + # The FullLoader parameter handles the conversion from YAML + # scalar values to Python dictionary format + py_params = yaml.load(file,Loader=yaml.FullLoader) + py_param_file_present = True #to be removed once validated + #AssignParams(py_params) #to be uncommented once validated + + #consider inline parameters + elif re.match('^\-\-mode=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-mode=(.+)$', myArgv, re.IGNORECASE) + mode = matchReg.group(1) + elif re.match('^\-\-eNBRepository=(.+)$|^\-\-ranRepository(.+)$', myArgv, re.IGNORECASE): + if re.match('^\-\-eNBRepository=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-eNBRepository=(.+)$', myArgv, re.IGNORECASE) + else: + matchReg = re.match('^\-\-ranRepository=(.+)$', myArgv, re.IGNORECASE) + CiTestObj.ranRepository = matchReg.group(1) + RAN.ranRepository=matchReg.group(1) + HTML.ranRepository=matchReg.group(1) + ldpc.ranRepository=matchReg.group(1) + elif re.match('^\-\-eNB_AllowMerge=(.+)$|^\-\-ranAllowMerge=(.+)$', myArgv, re.IGNORECASE): + if re.match('^\-\-eNB_AllowMerge=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-eNB_AllowMerge=(.+)$', myArgv, re.IGNORECASE) + else: + matchReg = re.match('^\-\-ranAllowMerge=(.+)$', myArgv, re.IGNORECASE) + doMerge = matchReg.group(1) + ldpc.ranAllowMerge=matchReg.group(1) + if ((doMerge == 'true') or (doMerge == 'True')): + CiTestObj.ranAllowMerge = True + RAN.ranAllowMerge=True + HTML.ranAllowMerge=True + elif re.match('^\-\-eNBBranch=(.+)$|^\-\-ranBranch=(.+)$', myArgv, re.IGNORECASE): + if re.match('^\-\-eNBBranch=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-eNBBranch=(.+)$', myArgv, re.IGNORECASE) + else: + matchReg = re.match('^\-\-ranBranch=(.+)$', myArgv, re.IGNORECASE) + CiTestObj.ranBranch = matchReg.group(1) + RAN.ranBranch=matchReg.group(1) + HTML.ranBranch=matchReg.group(1) + ldpc.ranBranch=matchReg.group(1) + elif re.match('^\-\-eNBCommitID=(.*)$|^\-\-ranCommitID=(.*)$', myArgv, re.IGNORECASE): + if re.match('^\-\-eNBCommitID=(.*)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-eNBCommitID=(.*)$', myArgv, re.IGNORECASE) + else: + matchReg = re.match('^\-\-ranCommitID=(.*)$', myArgv, re.IGNORECASE) + CiTestObj.ranCommitID = matchReg.group(1) + RAN.ranCommitID=matchReg.group(1) + HTML.ranCommitID=matchReg.group(1) + ldpc.ranCommitID=matchReg.group(1) + elif re.match('^\-\-eNBTargetBranch=(.*)$|^\-\-ranTargetBranch=(.*)$', myArgv, re.IGNORECASE): + if re.match('^\-\-eNBTargetBranch=(.*)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-eNBTargetBranch=(.*)$', myArgv, re.IGNORECASE) + else: + matchReg = re.match('^\-\-ranTargetBranch=(.*)$', myArgv, re.IGNORECASE) + CiTestObj.ranTargetBranch = matchReg.group(1) + RAN.ranTargetBranch=matchReg.group(1) + HTML.ranTargetBranch=matchReg.group(1) + ldpc.ranTargetBranch=matchReg.group(1) + elif re.match('^\-\-eNBIPAddress=(.+)$|^\-\-eNB[1-2]IPAddress=(.+)$', myArgv, re.IGNORECASE): + if re.match('^\-\-eNBIPAddress=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-eNBIPAddress=(.+)$', myArgv, re.IGNORECASE) + RAN.eNBIPAddress=matchReg.group(1) + ldpc.eNBIpAddr=matchReg.group(1) + elif re.match('^\-\-eNB1IPAddress=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-eNB1IPAddress=(.+)$', myArgv, re.IGNORECASE) + RAN.eNB1IPAddress=matchReg.group(1) + elif re.match('^\-\-eNB2IPAddress=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-eNB2IPAddress=(.+)$', myArgv, re.IGNORECASE) + RAN.eNB2IPAddress=matchReg.group(1) + elif re.match('^\-\-eNBUserName=(.+)$|^\-\-eNB[1-2]UserName=(.+)$', myArgv, re.IGNORECASE): + if re.match('^\-\-eNBUserName=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-eNBUserName=(.+)$', myArgv, re.IGNORECASE) + RAN.eNBUserName=matchReg.group(1) + ldpc.eNBUserName=matchReg.group(1) + elif re.match('^\-\-eNB1UserName=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-eNB1UserName=(.+)$', myArgv, re.IGNORECASE) + RAN.eNB1UserName=matchReg.group(1) + elif re.match('^\-\-eNB2UserName=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-eNB2UserName=(.+)$', myArgv, re.IGNORECASE) + RAN.eNB2UserName=matchReg.group(1) + elif re.match('^\-\-eNBPassword=(.+)$|^\-\-eNB[1-2]Password=(.+)$', myArgv, re.IGNORECASE): + if re.match('^\-\-eNBPassword=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-eNBPassword=(.+)$', myArgv, re.IGNORECASE) + RAN.eNBPassword=matchReg.group(1) + ldpc.eNBPassWord=matchReg.group(1) + elif re.match('^\-\-eNB1Password=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-eNB1Password=(.+)$', myArgv, re.IGNORECASE) + RAN.eNB1Password=matchReg.group(1) + elif re.match('^\-\-eNB2Password=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-eNB2Password=(.+)$', myArgv, re.IGNORECASE) + RAN.eNB2Password=matchReg.group(1) + elif re.match('^\-\-eNBSourceCodePath=(.+)$|^\-\-eNB[1-2]SourceCodePath=(.+)$', myArgv, re.IGNORECASE): + if re.match('^\-\-eNBSourceCodePath=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-eNBSourceCodePath=(.+)$', myArgv, re.IGNORECASE) + RAN.eNBSourceCodePath=matchReg.group(1) + ldpc.eNBSourceCodePath=matchReg.group(1) + elif re.match('^\-\-eNB1SourceCodePath=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-eNB1SourceCodePath=(.+)$', myArgv, re.IGNORECASE) + RAN.eNB1SourceCodePath=matchReg.group(1) + elif re.match('^\-\-eNB2SourceCodePath=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-eNB2SourceCodePath=(.+)$', myArgv, re.IGNORECASE) + RAN.eNB2SourceCodePath=matchReg.group(1) + elif re.match('^\-\-EPCIPAddress=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-EPCIPAddress=(.+)$', myArgv, re.IGNORECASE) + EPC.IPAddress=matchReg.group(1) + elif re.match('^\-\-EPCUserName=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-EPCUserName=(.+)$', myArgv, re.IGNORECASE) + EPC.UserName=matchReg.group(1) + elif re.match('^\-\-EPCPassword=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-EPCPassword=(.+)$', myArgv, re.IGNORECASE) + EPC.Password=matchReg.group(1) + elif re.match('^\-\-EPCSourceCodePath=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-EPCSourceCodePath=(.+)$', myArgv, re.IGNORECASE) + EPC.SourceCodePath=matchReg.group(1) + elif re.match('^\-\-EPCType=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-EPCType=(.+)$', myArgv, re.IGNORECASE) + if re.match('OAI', matchReg.group(1), re.IGNORECASE) or re.match('ltebox', matchReg.group(1), re.IGNORECASE) or re.match('OAI-Rel14-CUPS', matchReg.group(1), re.IGNORECASE) or re.match('OAI-Rel14-Docker', matchReg.group(1), re.IGNORECASE): + EPC.Type=matchReg.group(1) + else: + sys.exit('Invalid EPC Type: ' + matchReg.group(1) + ' -- (should be OAI or ltebox or OAI-Rel14-CUPS or OAI-Rel14-Docker)') + elif re.match('^\-\-EPCContainerPrefix=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-EPCContainerPrefix=(.+)$', myArgv, re.IGNORECASE) + EPC.ContainerPrefix=matchReg.group(1) + elif re.match('^\-\-ADBIPAddress=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-ADBIPAddress=(.+)$', myArgv, re.IGNORECASE) + CiTestObj.ADBIPAddress = matchReg.group(1) + elif re.match('^\-\-ADBUserName=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-ADBUserName=(.+)$', myArgv, re.IGNORECASE) + CiTestObj.ADBUserName = matchReg.group(1) + elif re.match('^\-\-ADBType=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-ADBType=(.+)$', myArgv, re.IGNORECASE) + if re.match('centralized', matchReg.group(1), re.IGNORECASE) or re.match('distributed', matchReg.group(1), re.IGNORECASE): + if re.match('distributed', matchReg.group(1), re.IGNORECASE): + CiTestObj.ADBCentralized = False + else: + CiTestObj.ADBCentralized = True + else: + sys.exit('Invalid ADB Type: ' + matchReg.group(1) + ' -- (should be centralized or distributed)') + elif re.match('^\-\-ADBPassword=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-ADBPassword=(.+)$', myArgv, re.IGNORECASE) + CiTestObj.ADBPassword = matchReg.group(1) + elif re.match('^\-\-XMLTestFile=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-XMLTestFile=(.+)$', myArgv, re.IGNORECASE) + CiTestObj.testXMLfiles.append(matchReg.group(1)) + HTML.testXMLfiles=matchReg.group(1) + HTML.nbTestXMLfiles=HTML.nbTestXMLfiles+1 + elif re.match('^\-\-UEIPAddress=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-UEIPAddress=(.+)$', myArgv, re.IGNORECASE) + CiTestObj.UEIPAddress = matchReg.group(1) + elif re.match('^\-\-UEUserName=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-UEUserName=(.+)$', myArgv, re.IGNORECASE) + CiTestObj.UEUserName = matchReg.group(1) + elif re.match('^\-\-UEPassword=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-UEPassword=(.+)$', myArgv, re.IGNORECASE) + CiTestObj.UEPassword = matchReg.group(1) + elif re.match('^\-\-UESourceCodePath=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-UESourceCodePath=(.+)$', myArgv, re.IGNORECASE) + CiTestObj.UESourceCodePath = matchReg.group(1) + elif re.match('^\-\-finalStatus=(.+)$', myArgv, re.IGNORECASE): + matchReg = re.match('^\-\-finalStatus=(.+)$', myArgv, re.IGNORECASE) + finalStatus = matchReg.group(1) + if ((finalStatus == 'true') or (finalStatus == 'True')): + CiTestObj.finalStatus = True + else: + HELP.GenericHelp(CONST.Version) + sys.exit('Invalid Parameter: ' + myArgv) + + return py_param_file_present, py_params, mode \ No newline at end of file diff --git a/ci-scripts/main.py b/ci-scripts/main.py index 82a1da0390..9fc7b19d58 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -3100,11 +3100,9 @@ def CheckClassValidity(xml_class_list,action,id): #assigning parameters to object instance attributes (even if the attributes do not exist !!) def AssignParams(params_dict): - #-- - mode=params_dict['mode'] - #-- + for key,value in params_dict.items(): - setattr(CITestObj, key, value) + setattr(CiTestObj, key, value) setattr(RAN, key, value) setattr(HTML, key, value) setattr(ldpc, key, value) @@ -3330,191 +3328,193 @@ ldpc=cls_physim.PhySim() #create an instance for LDPC test using GPU or CPU b #----------------------------------------------------------- -# Parameter Check +# Parsing Command Line Arguments #----------------------------------------------------------- -argvs = sys.argv -argc = len(argvs) -cwd = os.getcwd() -py_param_file_present = False -while len(argvs) > 1: - myArgv = argvs.pop(1) # 0th is this file's name +import args_parse +py_param_file_present, py_params, mode = args_parse.ArgsParse(sys.argv,CiTestObj,RAN,HTML,ldpc,HELP) - #--help - if re.match('^\-\-help$', myArgv, re.IGNORECASE): - HELP.GenericHelp(CONST.Version) - sys.exit(0) - - #--apply= as parameters file, to replace inline parameters - elif re.match('^\-\-apply=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-apply=(.+)$', myArgv, re.IGNORECASE) - py_params_file = matchReg.group(1) - with open(py_params_file,'r') as file: - # The FullLoader parameter handles the conversion from YAML - # scalar values to Python dictionary format - py_params = yaml.load(file,Loader=yaml.FullLoader) - py_param_file_present = True #to be removed once validated - #AssignParams(py_params) #to be uncommented once validated - - #consider inline parameters - elif re.match('^\-\-mode=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-mode=(.+)$', myArgv, re.IGNORECASE) - mode = matchReg.group(1) - elif re.match('^\-\-eNBRepository=(.+)$|^\-\-ranRepository(.+)$', myArgv, re.IGNORECASE): - if re.match('^\-\-eNBRepository=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-eNBRepository=(.+)$', myArgv, re.IGNORECASE) - else: - matchReg = re.match('^\-\-ranRepository=(.+)$', myArgv, re.IGNORECASE) - CiTestObj.ranRepository = matchReg.group(1) - RAN.ranRepository=matchReg.group(1) - HTML.ranRepository=matchReg.group(1) - ldpc.ranRepository=matchReg.group(1) - elif re.match('^\-\-eNB_AllowMerge=(.+)$|^\-\-ranAllowMerge=(.+)$', myArgv, re.IGNORECASE): - if re.match('^\-\-eNB_AllowMerge=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-eNB_AllowMerge=(.+)$', myArgv, re.IGNORECASE) - else: - matchReg = re.match('^\-\-ranAllowMerge=(.+)$', myArgv, re.IGNORECASE) - doMerge = matchReg.group(1) - ldpc.ranAllowMerge=matchReg.group(1) - if ((doMerge == 'true') or (doMerge == 'True')): - CiTestObj.ranAllowMerge = True - RAN.ranAllowMerge=True - HTML.ranAllowMerge=True - elif re.match('^\-\-eNBBranch=(.+)$|^\-\-ranBranch=(.+)$', myArgv, re.IGNORECASE): - if re.match('^\-\-eNBBranch=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-eNBBranch=(.+)$', myArgv, re.IGNORECASE) - else: - matchReg = re.match('^\-\-ranBranch=(.+)$', myArgv, re.IGNORECASE) - CiTestObj.ranBranch = matchReg.group(1) - RAN.ranBranch=matchReg.group(1) - HTML.ranBranch=matchReg.group(1) - ldpc.ranBranch=matchReg.group(1) - elif re.match('^\-\-eNBCommitID=(.*)$|^\-\-ranCommitID=(.*)$', myArgv, re.IGNORECASE): - if re.match('^\-\-eNBCommitID=(.*)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-eNBCommitID=(.*)$', myArgv, re.IGNORECASE) - else: - matchReg = re.match('^\-\-ranCommitID=(.*)$', myArgv, re.IGNORECASE) - CiTestObj.ranCommitID = matchReg.group(1) - RAN.ranCommitID=matchReg.group(1) - HTML.ranCommitID=matchReg.group(1) - ldpc.ranCommitID=matchReg.group(1) - elif re.match('^\-\-eNBTargetBranch=(.*)$|^\-\-ranTargetBranch=(.*)$', myArgv, re.IGNORECASE): - if re.match('^\-\-eNBTargetBranch=(.*)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-eNBTargetBranch=(.*)$', myArgv, re.IGNORECASE) - else: - matchReg = re.match('^\-\-ranTargetBranch=(.*)$', myArgv, re.IGNORECASE) - CiTestObj.ranTargetBranch = matchReg.group(1) - RAN.ranTargetBranch=matchReg.group(1) - HTML.ranTargetBranch=matchReg.group(1) - ldpc.ranTargetBranch=matchReg.group(1) - elif re.match('^\-\-eNBIPAddress=(.+)$|^\-\-eNB[1-2]IPAddress=(.+)$', myArgv, re.IGNORECASE): - if re.match('^\-\-eNBIPAddress=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-eNBIPAddress=(.+)$', myArgv, re.IGNORECASE) - RAN.eNBIPAddress=matchReg.group(1) - ldpc.eNBIpAddr=matchReg.group(1) - elif re.match('^\-\-eNB1IPAddress=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-eNB1IPAddress=(.+)$', myArgv, re.IGNORECASE) - RAN.eNB1IPAddress=matchReg.group(1) - elif re.match('^\-\-eNB2IPAddress=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-eNB2IPAddress=(.+)$', myArgv, re.IGNORECASE) - RAN.eNB2IPAddress=matchReg.group(1) - elif re.match('^\-\-eNBUserName=(.+)$|^\-\-eNB[1-2]UserName=(.+)$', myArgv, re.IGNORECASE): - if re.match('^\-\-eNBUserName=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-eNBUserName=(.+)$', myArgv, re.IGNORECASE) - RAN.eNBUserName=matchReg.group(1) - ldpc.eNBUserName=matchReg.group(1) - elif re.match('^\-\-eNB1UserName=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-eNB1UserName=(.+)$', myArgv, re.IGNORECASE) - RAN.eNB1UserName=matchReg.group(1) - elif re.match('^\-\-eNB2UserName=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-eNB2UserName=(.+)$', myArgv, re.IGNORECASE) - RAN.eNB2UserName=matchReg.group(1) - elif re.match('^\-\-eNBPassword=(.+)$|^\-\-eNB[1-2]Password=(.+)$', myArgv, re.IGNORECASE): - if re.match('^\-\-eNBPassword=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-eNBPassword=(.+)$', myArgv, re.IGNORECASE) - RAN.eNBPassword=matchReg.group(1) - ldpc.eNBPassWord=matchReg.group(1) - elif re.match('^\-\-eNB1Password=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-eNB1Password=(.+)$', myArgv, re.IGNORECASE) - RAN.eNB1Password=matchReg.group(1) - elif re.match('^\-\-eNB2Password=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-eNB2Password=(.+)$', myArgv, re.IGNORECASE) - RAN.eNB2Password=matchReg.group(1) - elif re.match('^\-\-eNBSourceCodePath=(.+)$|^\-\-eNB[1-2]SourceCodePath=(.+)$', myArgv, re.IGNORECASE): - if re.match('^\-\-eNBSourceCodePath=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-eNBSourceCodePath=(.+)$', myArgv, re.IGNORECASE) - RAN.eNBSourceCodePath=matchReg.group(1) - ldpc.eNBSourceCodePath=matchReg.group(1) - elif re.match('^\-\-eNB1SourceCodePath=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-eNB1SourceCodePath=(.+)$', myArgv, re.IGNORECASE) - RAN.eNB1SourceCodePath=matchReg.group(1) - elif re.match('^\-\-eNB2SourceCodePath=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-eNB2SourceCodePath=(.+)$', myArgv, re.IGNORECASE) - RAN.eNB2SourceCodePath=matchReg.group(1) - elif re.match('^\-\-EPCIPAddress=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-EPCIPAddress=(.+)$', myArgv, re.IGNORECASE) - EPC.IPAddress=matchReg.group(1) - elif re.match('^\-\-EPCUserName=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-EPCUserName=(.+)$', myArgv, re.IGNORECASE) - EPC.UserName=matchReg.group(1) - elif re.match('^\-\-EPCPassword=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-EPCPassword=(.+)$', myArgv, re.IGNORECASE) - EPC.Password=matchReg.group(1) - elif re.match('^\-\-EPCSourceCodePath=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-EPCSourceCodePath=(.+)$', myArgv, re.IGNORECASE) - EPC.SourceCodePath=matchReg.group(1) - elif re.match('^\-\-EPCType=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-EPCType=(.+)$', myArgv, re.IGNORECASE) - if re.match('OAI', matchReg.group(1), re.IGNORECASE) or re.match('ltebox', matchReg.group(1), re.IGNORECASE) or re.match('OAI-Rel14-CUPS', matchReg.group(1), re.IGNORECASE) or re.match('OAI-Rel14-Docker', matchReg.group(1), re.IGNORECASE): - EPC.Type=matchReg.group(1) - else: - sys.exit('Invalid EPC Type: ' + matchReg.group(1) + ' -- (should be OAI or ltebox or OAI-Rel14-CUPS or OAI-Rel14-Docker)') - elif re.match('^\-\-EPCContainerPrefix=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-EPCContainerPrefix=(.+)$', myArgv, re.IGNORECASE) - EPC.ContainerPrefix=matchReg.group(1) - elif re.match('^\-\-ADBIPAddress=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-ADBIPAddress=(.+)$', myArgv, re.IGNORECASE) - CiTestObj.ADBIPAddress = matchReg.group(1) - elif re.match('^\-\-ADBUserName=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-ADBUserName=(.+)$', myArgv, re.IGNORECASE) - CiTestObj.ADBUserName = matchReg.group(1) - elif re.match('^\-\-ADBType=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-ADBType=(.+)$', myArgv, re.IGNORECASE) - if re.match('centralized', matchReg.group(1), re.IGNORECASE) or re.match('distributed', matchReg.group(1), re.IGNORECASE): - if re.match('distributed', matchReg.group(1), re.IGNORECASE): - CiTestObj.ADBCentralized = False - else: - CiTestObj.ADBCentralized = True - else: - sys.exit('Invalid ADB Type: ' + matchReg.group(1) + ' -- (should be centralized or distributed)') - elif re.match('^\-\-ADBPassword=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-ADBPassword=(.+)$', myArgv, re.IGNORECASE) - CiTestObj.ADBPassword = matchReg.group(1) - elif re.match('^\-\-XMLTestFile=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-XMLTestFile=(.+)$', myArgv, re.IGNORECASE) - CiTestObj.testXMLfiles.append(matchReg.group(1)) - HTML.testXMLfiles=matchReg.group(1) - HTML.nbTestXMLfiles=HTML.nbTestXMLfiles+1 - elif re.match('^\-\-UEIPAddress=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-UEIPAddress=(.+)$', myArgv, re.IGNORECASE) - CiTestObj.UEIPAddress = matchReg.group(1) - elif re.match('^\-\-UEUserName=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-UEUserName=(.+)$', myArgv, re.IGNORECASE) - CiTestObj.UEUserName = matchReg.group(1) - elif re.match('^\-\-UEPassword=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-UEPassword=(.+)$', myArgv, re.IGNORECASE) - CiTestObj.UEPassword = matchReg.group(1) - elif re.match('^\-\-UESourceCodePath=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-UESourceCodePath=(.+)$', myArgv, re.IGNORECASE) - CiTestObj.UESourceCodePath = matchReg.group(1) - elif re.match('^\-\-finalStatus=(.+)$', myArgv, re.IGNORECASE): - matchReg = re.match('^\-\-finalStatus=(.+)$', myArgv, re.IGNORECASE) - finalStatus = matchReg.group(1) - if ((finalStatus == 'true') or (finalStatus == 'True')): - CiTestObj.finalStatus = True - else: - HELP.GenericHelp(CONST.Version) - sys.exit('Invalid Parameter: ' + myArgv) +#argvs = sys.argv +#py_param_file_present = False +# +#while len(argvs) > 1: +# myArgv = argvs.pop(1) # 0th is this file's name +# +# #--help +# if re.match('^\-\-help$', myArgv, re.IGNORECASE): +# HELP.GenericHelp(CONST.Version) +# sys.exit(0) +# +# #--apply= as parameters file, to replace inline parameters +# elif re.match('^\-\-Apply=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-Apply=(.+)$', myArgv, re.IGNORECASE) +# py_params_file = matchReg.group(1) +# with open(py_params_file,'r') as file: +# # The FullLoader parameter handles the conversion from YAML +# # scalar values to Python dictionary format +# py_params = yaml.load(file,Loader=yaml.FullLoader) +# py_param_file_present = True #to be removed once validated +# #AssignParams(py_params) #to be uncommented once validated +# +# #consider inline parameters +# elif re.match('^\-\-mode=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-mode=(.+)$', myArgv, re.IGNORECASE) +# mode = matchReg.group(1) +# elif re.match('^\-\-eNBRepository=(.+)$|^\-\-ranRepository(.+)$', myArgv, re.IGNORECASE): +# if re.match('^\-\-eNBRepository=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-eNBRepository=(.+)$', myArgv, re.IGNORECASE) +# else: +# matchReg = re.match('^\-\-ranRepository=(.+)$', myArgv, re.IGNORECASE) +# CiTestObj.ranRepository = matchReg.group(1) +# RAN.ranRepository=matchReg.group(1) +# HTML.ranRepository=matchReg.group(1) +# ldpc.ranRepository=matchReg.group(1) +# elif re.match('^\-\-eNB_AllowMerge=(.+)$|^\-\-ranAllowMerge=(.+)$', myArgv, re.IGNORECASE): +# if re.match('^\-\-eNB_AllowMerge=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-eNB_AllowMerge=(.+)$', myArgv, re.IGNORECASE) +# else: +# matchReg = re.match('^\-\-ranAllowMerge=(.+)$', myArgv, re.IGNORECASE) +# doMerge = matchReg.group(1) +# ldpc.ranAllowMerge=matchReg.group(1) +# if ((doMerge == 'true') or (doMerge == 'True')): +# CiTestObj.ranAllowMerge = True +# RAN.ranAllowMerge=True +# HTML.ranAllowMerge=True +# elif re.match('^\-\-eNBBranch=(.+)$|^\-\-ranBranch=(.+)$', myArgv, re.IGNORECASE): +# if re.match('^\-\-eNBBranch=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-eNBBranch=(.+)$', myArgv, re.IGNORECASE) +# else: +# matchReg = re.match('^\-\-ranBranch=(.+)$', myArgv, re.IGNORECASE) +# CiTestObj.ranBranch = matchReg.group(1) +# RAN.ranBranch=matchReg.group(1) +# HTML.ranBranch=matchReg.group(1) +# ldpc.ranBranch=matchReg.group(1) +# elif re.match('^\-\-eNBCommitID=(.*)$|^\-\-ranCommitID=(.*)$', myArgv, re.IGNORECASE): +# if re.match('^\-\-eNBCommitID=(.*)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-eNBCommitID=(.*)$', myArgv, re.IGNORECASE) +# else: +# matchReg = re.match('^\-\-ranCommitID=(.*)$', myArgv, re.IGNORECASE) +# CiTestObj.ranCommitID = matchReg.group(1) +# RAN.ranCommitID=matchReg.group(1) +# HTML.ranCommitID=matchReg.group(1) +# ldpc.ranCommitID=matchReg.group(1) +# elif re.match('^\-\-eNBTargetBranch=(.*)$|^\-\-ranTargetBranch=(.*)$', myArgv, re.IGNORECASE): +# if re.match('^\-\-eNBTargetBranch=(.*)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-eNBTargetBranch=(.*)$', myArgv, re.IGNORECASE) +# else: +# matchReg = re.match('^\-\-ranTargetBranch=(.*)$', myArgv, re.IGNORECASE) +# CiTestObj.ranTargetBranch = matchReg.group(1) +# RAN.ranTargetBranch=matchReg.group(1) +# HTML.ranTargetBranch=matchReg.group(1) +# ldpc.ranTargetBranch=matchReg.group(1) +# elif re.match('^\-\-eNBIPAddress=(.+)$|^\-\-eNB[1-2]IPAddress=(.+)$', myArgv, re.IGNORECASE): +# if re.match('^\-\-eNBIPAddress=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-eNBIPAddress=(.+)$', myArgv, re.IGNORECASE) +# RAN.eNBIPAddress=matchReg.group(1) +# ldpc.eNBIpAddr=matchReg.group(1) +# elif re.match('^\-\-eNB1IPAddress=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-eNB1IPAddress=(.+)$', myArgv, re.IGNORECASE) +# RAN.eNB1IPAddress=matchReg.group(1) +# elif re.match('^\-\-eNB2IPAddress=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-eNB2IPAddress=(.+)$', myArgv, re.IGNORECASE) +# RAN.eNB2IPAddress=matchReg.group(1) +# elif re.match('^\-\-eNBUserName=(.+)$|^\-\-eNB[1-2]UserName=(.+)$', myArgv, re.IGNORECASE): +# if re.match('^\-\-eNBUserName=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-eNBUserName=(.+)$', myArgv, re.IGNORECASE) +# RAN.eNBUserName=matchReg.group(1) +# ldpc.eNBUserName=matchReg.group(1) +# elif re.match('^\-\-eNB1UserName=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-eNB1UserName=(.+)$', myArgv, re.IGNORECASE) +# RAN.eNB1UserName=matchReg.group(1) +# elif re.match('^\-\-eNB2UserName=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-eNB2UserName=(.+)$', myArgv, re.IGNORECASE) +# RAN.eNB2UserName=matchReg.group(1) +# elif re.match('^\-\-eNBPassword=(.+)$|^\-\-eNB[1-2]Password=(.+)$', myArgv, re.IGNORECASE): +# if re.match('^\-\-eNBPassword=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-eNBPassword=(.+)$', myArgv, re.IGNORECASE) +# RAN.eNBPassword=matchReg.group(1) +# ldpc.eNBPassWord=matchReg.group(1) +# elif re.match('^\-\-eNB1Password=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-eNB1Password=(.+)$', myArgv, re.IGNORECASE) +# RAN.eNB1Password=matchReg.group(1) +# elif re.match('^\-\-eNB2Password=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-eNB2Password=(.+)$', myArgv, re.IGNORECASE) +# RAN.eNB2Password=matchReg.group(1) +# elif re.match('^\-\-eNBSourceCodePath=(.+)$|^\-\-eNB[1-2]SourceCodePath=(.+)$', myArgv, re.IGNORECASE): +# if re.match('^\-\-eNBSourceCodePath=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-eNBSourceCodePath=(.+)$', myArgv, re.IGNORECASE) +# RAN.eNBSourceCodePath=matchReg.group(1) +# ldpc.eNBSourceCodePath=matchReg.group(1) +# elif re.match('^\-\-eNB1SourceCodePath=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-eNB1SourceCodePath=(.+)$', myArgv, re.IGNORECASE) +# RAN.eNB1SourceCodePath=matchReg.group(1) +# elif re.match('^\-\-eNB2SourceCodePath=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-eNB2SourceCodePath=(.+)$', myArgv, re.IGNORECASE) +# RAN.eNB2SourceCodePath=matchReg.group(1) +# elif re.match('^\-\-EPCIPAddress=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-EPCIPAddress=(.+)$', myArgv, re.IGNORECASE) +# EPC.IPAddress=matchReg.group(1) +# elif re.match('^\-\-EPCUserName=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-EPCUserName=(.+)$', myArgv, re.IGNORECASE) +# EPC.UserName=matchReg.group(1) +# elif re.match('^\-\-EPCPassword=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-EPCPassword=(.+)$', myArgv, re.IGNORECASE) +# EPC.Password=matchReg.group(1) +# elif re.match('^\-\-EPCSourceCodePath=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-EPCSourceCodePath=(.+)$', myArgv, re.IGNORECASE) +# EPC.SourceCodePath=matchReg.group(1) +# elif re.match('^\-\-EPCType=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-EPCType=(.+)$', myArgv, re.IGNORECASE) +# if re.match('OAI', matchReg.group(1), re.IGNORECASE) or re.match('ltebox', matchReg.group(1), re.IGNORECASE) or re.match('OAI-Rel14-CUPS', matchReg.group(1), re.IGNORECASE) or re.match('OAI-Rel14-Docker', matchReg.group(1), re.IGNORECASE): +# EPC.Type=matchReg.group(1) +# else: +# sys.exit('Invalid EPC Type: ' + matchReg.group(1) + ' -- (should be OAI or ltebox or OAI-Rel14-CUPS or OAI-Rel14-Docker)') +# elif re.match('^\-\-EPCContainerPrefix=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-EPCContainerPrefix=(.+)$', myArgv, re.IGNORECASE) +# EPC.ContainerPrefix=matchReg.group(1) +# elif re.match('^\-\-ADBIPAddress=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-ADBIPAddress=(.+)$', myArgv, re.IGNORECASE) +# CiTestObj.ADBIPAddress = matchReg.group(1) +# elif re.match('^\-\-ADBUserName=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-ADBUserName=(.+)$', myArgv, re.IGNORECASE) +# CiTestObj.ADBUserName = matchReg.group(1) +# elif re.match('^\-\-ADBType=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-ADBType=(.+)$', myArgv, re.IGNORECASE) +# if re.match('centralized', matchReg.group(1), re.IGNORECASE) or re.match('distributed', matchReg.group(1), re.IGNORECASE): +# if re.match('distributed', matchReg.group(1), re.IGNORECASE): +# CiTestObj.ADBCentralized = False +# else: +# CiTestObj.ADBCentralized = True +# else: +# sys.exit('Invalid ADB Type: ' + matchReg.group(1) + ' -- (should be centralized or distributed)') +# elif re.match('^\-\-ADBPassword=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-ADBPassword=(.+)$', myArgv, re.IGNORECASE) +# CiTestObj.ADBPassword = matchReg.group(1) +# elif re.match('^\-\-XMLTestFile=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-XMLTestFile=(.+)$', myArgv, re.IGNORECASE) +# CiTestObj.testXMLfiles.append(matchReg.group(1)) +# HTML.testXMLfiles=matchReg.group(1) +# HTML.nbTestXMLfiles=HTML.nbTestXMLfiles+1 +# elif re.match('^\-\-UEIPAddress=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-UEIPAddress=(.+)$', myArgv, re.IGNORECASE) +# CiTestObj.UEIPAddress = matchReg.group(1) +# elif re.match('^\-\-UEUserName=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-UEUserName=(.+)$', myArgv, re.IGNORECASE) +# CiTestObj.UEUserName = matchReg.group(1) +# elif re.match('^\-\-UEPassword=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-UEPassword=(.+)$', myArgv, re.IGNORECASE) +# CiTestObj.UEPassword = matchReg.group(1) +# elif re.match('^\-\-UESourceCodePath=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-UESourceCodePath=(.+)$', myArgv, re.IGNORECASE) +# CiTestObj.UESourceCodePath = matchReg.group(1) +# elif re.match('^\-\-finalStatus=(.+)$', myArgv, re.IGNORECASE): +# matchReg = re.match('^\-\-finalStatus=(.+)$', myArgv, re.IGNORECASE) +# finalStatus = matchReg.group(1) +# if ((finalStatus == 'true') or (finalStatus == 'True')): +# CiTestObj.finalStatus = True +# else: +# HELP.GenericHelp(CONST.Version) +# sys.exit('Invalid Parameter: ' + myArgv) #----------------------------------------------------------- @@ -3522,7 +3522,15 @@ while len(argvs) > 1: #----------------------------------------------------------- #temporary solution for testing: if py_param_file_present == True: - AssignParams(py_params) + AssignParams(py_params) + +#for debug +print(RAN.__dict__) +print(CiTestObj.__dict__) +print(HTML.__dict__) +print(ldpc.__dict__) +#for debug + #----------------------------------------------------------- # COTS UE instanciation @@ -3534,6 +3542,7 @@ COTS_UE=cls_cots_ue.CotsUe('oppo', CiTestObj.UEIPAddress, CiTestObj.UEUserName,C #----------------------------------------------------------- # XML class (action) analysis #----------------------------------------------------------- +cwd = os.getcwd() if re.match('^TerminateeNB$', mode, re.IGNORECASE): if RAN.eNBIPAddress == '' or RAN.eNBUserName == '' or RAN.eNBPassword == '': @@ -3851,6 +3860,8 @@ elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re else: logging.info('Testsuite passed after ' + str(CiTestObj.FailReportCnt) + ' time(s)') HTML.CreateHtmlTabFooter(True) +elif re.match('^LoadParams$', mode, re.IGNORECASE): + pass else: HELP.GenericHelp(CONST.Version) sys.exit('Invalid mode') diff --git a/ci-scripts/py_params.yaml b/ci-scripts/py_params.yaml index 68471763f7..303d5d1006 100644 --- a/ci-scripts/py_params.yaml +++ b/ci-scripts/py_params.yaml @@ -1,4 +1,3 @@ -mode : a eNBRepository : b ranRepository : c eNB_AllowMerge : diff --git a/ci-scripts/py_params_template.yaml b/ci-scripts/py_params_template.yaml new file mode 100644 index 0000000000..aaf31c1576 --- /dev/null +++ b/ci-scripts/py_params_template.yaml @@ -0,0 +1,97 @@ +eNBRepository : b +ranRepository : c +eNB_AllowMerge : +ranAllowMerge : +eNBBranch : f +ranBranch : g +eNBCommitID : +ranCommitID : i +eNBTargetBranch : j +ranTargetBranch : k + + +RAN: + RAN_inst_0: + name : RAN_1 + nodes : + - type : eNB + IPAddress : 001.1.1 + UserName : toto + Password : qwe + SourceCodePath : l + - type : gNB + IPAddress : 002.2.2 + UserName : tata + Password : asd + SourceCodePath : m + - type : eNB + IPAddress : 003.3.3 + UserName : titi + Password : zxc + SourceCodePath : n + - type : gNB + IPAddress : 004.4.4 + UserName : caca + Password : pepe + SourceCodePath : o + RAN_inst_1: + name : RAN_2 + nodes : + - type : eNB + IPAddress : 101.1.1 + UserName : toto + Password : qwe + SourceCodePath : l + - type : gNB + IPAddress : 102.2.2 + UserName : zaza + Password : asd + SourceCodePath : m + - type : eNB + IPAddress : 103.3.3 + UserName : zizi + Password : zxc + SourceCodePath : n + - type : gNB + IPAddress : 104.4.4 + UserName : aaaa + Password : pepe + SourceCodePath : o + + + +EPC: + EPC_inst_0: + EPCIPAddress : p + EPCUserName : q + EPCPassword : r + EPCSourceCodePath : s + EPCType : t + EPCContainerPrefix : u + +ADB: + ADBIPAddress : v + ADBUserName : w + ADBType : x + ADBPassword : y + + +UE: + UE_inst_0: + name : UE_1 + type : + UEIPAddress : qqq + UEUserName : www + UEPassword : eee + UESourceCodePath : yyy + UE_inst_1: + name : UE_2 + type : + UEIPAddress : bloblob + UEUserName : gwou + UEPassword : zebu + UESourceCodePath : pop + + +XMLTestFile : z +finalStatus : bbb \ No newline at end of file From d81f8b91205c6c2aa2840f4ff195428f0358ba29 Mon Sep 17 00:00:00 2001 From: hardy Date: Mon, 27 Jul 2020 14:08:21 +0200 Subject: [PATCH 519/553] fixed CONST. missing in front of constant, leading to execution error --- ci-scripts/main.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ci-scripts/main.py b/ci-scripts/main.py index 9fc7b19d58..4ea2884c3b 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -2643,7 +2643,7 @@ class OaiCiTest(): else: statMsg = 'UE did NOT SHOW "TRIED TO PUSH MBMS DATA" message(s)' logging.debug('\u001B[1;30;41m ' + statMsg + ' \u001B[0m') - global_status = OAI_UE_PROCESS_NO_MBMS_MSGS + global_status = CONST.OAI_UE_PROCESS_NO_MBMS_MSGS HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + statMsg + '\n' if foundSegFault: logging.debug('\u001B[1;37;41m UE ended with a Segmentation Fault! \u001B[0m') From 427b223136ce00cd933f86628729acf81c231c83 Mon Sep 17 00:00:00 2001 From: Laurent Date: Mon, 27 Jul 2020 16:08:31 +0200 Subject: [PATCH 520/553] small fiwes --- cmake_targets/build_oai | 1 + common/utils/ocp_itti/intertask_interface.cpp | 2 +- common/utils/threadPool/thread-pool.c | 5 +++-- executables/nr-uesoftmodem.c | 7 ++----- openair1/PHY/LTE_UE_TRANSPORT/prach_ue.c | 2 +- openair1/PHY/NR_TRANSPORT/nr_prach.c | 2 +- openair1/PHY/TOOLS/readme.md | 12 ++++++++++++ openair1/PHY/phy_vars.h | 8 ++++---- openair1/PHY/phy_vars_nr_ue.h | 2 +- openair1/SCHED_NR/phy_procedures_nr_gNB.c | 2 +- openair2/ENB_APP/flexran_agent_extern.h | 2 -- openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c | 2 +- targets/ARCH/ETHERNET/USERSPACE/LIB/ethernet_lib.c | 4 ++-- targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp | 1 - targets/ARCH/rfsimulator/simulator.c | 12 ++++++++++-- 15 files changed, 40 insertions(+), 24 deletions(-) create mode 100644 openair1/PHY/TOOLS/readme.md diff --git a/cmake_targets/build_oai b/cmake_targets/build_oai index 88b8811575..e0093c909c 100755 --- a/cmake_targets/build_oai +++ b/cmake_targets/build_oai @@ -580,6 +580,7 @@ function main() { cmake_file=$DIR/$build_dir/CMakeLists.txt echo "cmake_minimum_required(VERSION 2.8)" > $cmake_file + echo "project (OpenAirInterface)" >> $cmake_file echo "set ( CMAKE_BUILD_TYPE $CMAKE_BUILD_TYPE )" >> $cmake_file echo "set ( CFLAGS_PROCESSOR_USER \"$CFLAGS_PROCESSOR_USER\" )" >> $cmake_file echo "set ( UE_EXPANSION $UE_EXPANSION )" >> $cmake_file diff --git a/common/utils/ocp_itti/intertask_interface.cpp b/common/utils/ocp_itti/intertask_interface.cpp index 22933fdd5b..1680410ebb 100644 --- a/common/utils/ocp_itti/intertask_interface.cpp +++ b/common/utils/ocp_itti/intertask_interface.cpp @@ -80,7 +80,7 @@ task_list_t tasks[TASK_MAX]; void *itti_malloc(task_id_t origin_task_id, task_id_t destination_task_id, ssize_t size) { void *ptr = NULL; - AssertFatal ((ptr=malloc (size)) != NULL, "Memory allocation of %zu bytes failed (%d -> %d)!\n", + AssertFatal ((ptr=calloc (size, 1)) != NULL, "Memory allocation of %zu bytes failed (%d -> %d)!\n", size, origin_task_id, destination_task_id); return ptr; } diff --git a/common/utils/threadPool/thread-pool.c b/common/utils/threadPool/thread-pool.c index cbb2dbe3d9..e1446f15d7 100644 --- a/common/utils/threadPool/thread-pool.c +++ b/common/utils/threadPool/thread-pool.c @@ -111,9 +111,10 @@ void initTpool(char *params,tpool_t *pool, bool performanceMeas) { pool->activated=true; initNotifiedFIFO(&pool->incomingFifo); char *saveptr, * curptr; + char *parms_cpy=strdup(params); pool->nbThreads=0; pool->restrictRNTI=false; - curptr=strtok_r(params,",",&saveptr); + curptr=strtok_r(parms_cpy,",",&saveptr); struct one_thread * ptr; while ( curptr!=NULL ) { int c=toupper(curptr[0]); @@ -145,7 +146,7 @@ void initTpool(char *params,tpool_t *pool, bool performanceMeas) { curptr=strtok_r(NULL,",",&saveptr); } - + free(parms_cpy); if (pool->activated && pool->nbThreads==0) { printf("No servers created in the thread pool, exit\n"); exit(1); diff --git a/executables/nr-uesoftmodem.c b/executables/nr-uesoftmodem.c index 6d3bbc9038..e4c6d7b439 100644 --- a/executables/nr-uesoftmodem.c +++ b/executables/nr-uesoftmodem.c @@ -76,12 +76,9 @@ unsigned short config_frames[4] = {2,9,11,13}; #include #include -//#include "stats.h" -// current status is that every UE has a DL scope for a SINGLE eNB (eNB_id=0) -#include "PHY/TOOLS/nr_phy_scope.h" -// at eNB 0, an UL scope for every UE -//FD_lte_phy_scope_enb *form_enb[MAX_NUM_CCs][NUMBER_OF_UE_MAX]; +/* Callbacks, globals and object handlers */ +#include "PHY/TOOLS/nr_phy_scope.h" #include #include "executables/softmodem-common.h" #include "executables/thread-common.h" diff --git a/openair1/PHY/LTE_UE_TRANSPORT/prach_ue.c b/openair1/PHY/LTE_UE_TRANSPORT/prach_ue.c index e4083863f0..ab7c2b9091 100644 --- a/openair1/PHY/LTE_UE_TRANSPORT/prach_ue.c +++ b/openair1/PHY/LTE_UE_TRANSPORT/prach_ue.c @@ -55,7 +55,7 @@ int32_t generate_prach( PHY_VARS_UE *ue, uint8_t eNB_id, uint8_t subframe, uint1 uint8_t preamble_index = ue->prach_resources[eNB_id]->ra_PreambleIndex; uint8_t tdd_mapindex = ue->prach_resources[eNB_id]->ra_TDD_map_index; int16_t *prachF = ue->prach_vars[eNB_id]->prachF; - static int16_t prach_tmp[45600*2] __attribute__((aligned(32))); + static int16_t prach_tmp[45600*4] __attribute__((aligned(32))); int16_t *prach = prach_tmp; int16_t *prach2; int16_t amp = ue->prach_vars[eNB_id]->amp; diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c index 2640a86240..d36dd6772b 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_prach.c +++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c @@ -540,7 +540,7 @@ void rx_nr_prach(PHY_VARS_gNB *gNB, uint16_t rootSequenceIndex; int numrootSequenceIndex; uint8_t restricted_set; - uint8_t n_ra_prb; + uint8_t n_ra_prb=0xFF; int16_t *prachF=NULL; int nb_rx; diff --git a/openair1/PHY/TOOLS/readme.md b/openair1/PHY/TOOLS/readme.md new file mode 100644 index 0000000000..f6671acc6d --- /dev/null +++ b/openair1/PHY/TOOLS/readme.md @@ -0,0 +1,12 @@ + +To use the scope, run the xNB or the UE with option "-d" + +Usage in gdb +In gdb, when you break, you can refresh immediatly the scope view by calling the display function. +The first paramter is the graph context, nevertheless we keep the last value for a dirty call in gdb (so you can use '0') + +Example with no variable known +phy_scope_nrUE(0, PHY_vars_UE_g[0][0], 0, 0, 0) + +or +phy_scope_gNB(0, phy_vars_gnb, phy_vars_ru, UE_id) diff --git a/openair1/PHY/phy_vars.h b/openair1/PHY/phy_vars.h index a74d148479..5e2be8bd8f 100644 --- a/openair1/PHY/phy_vars.h +++ b/openair1/PHY/phy_vars.h @@ -59,10 +59,10 @@ const short conjugate2[8]__attribute__((aligned(16))) = {1,-1,1,-1,1,-1,1,-1}; unsigned char NB_RU=0; #ifndef OPENAIR2 -unsigned char NB_eNB_INST=0; -uint16_t NB_UE_INST=0; -unsigned char NB_RN_INST=0; -unsigned char NB_INST=0; +//unsigned char NB_eNB_INST=0; +//uint16_t NB_UE_INST=0; +//unsigned char NB_RN_INST=0; +//unsigned char NB_INST=0; #endif int number_of_cards; diff --git a/openair1/PHY/phy_vars_nr_ue.h b/openair1/PHY/phy_vars_nr_ue.h index 1843d8d5bc..baa64561f0 100644 --- a/openair1/PHY/phy_vars_nr_ue.h +++ b/openair1/PHY/phy_vars_nr_ue.h @@ -138,4 +138,4 @@ uint8_t scrambling_lut[65536*16] __attribute__((aligned(32))); uint8_t max_ldpc_iterations=4; uint8_t max_turbo_iterations=4; -#endif /*__PHY_VARS_H__ */ +#endif diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index 992c908c5d..94e356951a 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -424,7 +424,7 @@ void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) for (int ULSCH_id=0;ULSCH_idulsch[ULSCH_id][0]; int harq_pid; - int no_sig; + //int no_sig; NR_UL_gNB_HARQ_t *ulsch_harq; if ((ulsch) && diff --git a/openair2/ENB_APP/flexran_agent_extern.h b/openair2/ENB_APP/flexran_agent_extern.h index 5f17cf4841..2a5930e1a8 100644 --- a/openair2/ENB_APP/flexran_agent_extern.h +++ b/openair2/ENB_APP/flexran_agent_extern.h @@ -44,8 +44,6 @@ AGENT_PHY_xface *flexran_agent_get_phy_xface(mid_t mod_id); extern AGENT_MAC_xface *agent_mac_xface[NUM_MAX_ENB]; #define flexran_agent_get_mac_xface(mod_id) (agent_mac_xface[mod_id]) -/* Control module interface for the communication of the RRC Control Module with the agent */ - /* Control module interface for the communication of the RRC Control Module with the agent */ // AGENT_RRC_xface *flexran_agent_get_rrc_xface(mid_t mod_id); extern AGENT_RRC_xface *agent_rrc_xface[NUM_MAX_ENB]; diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c index 56ae14f98b..840aafa943 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c @@ -360,7 +360,7 @@ uint8_t nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources, uint8_t sdu_lcids[NB_RB_MAX] = {0}; uint16_t sdu_lengths[NB_RB_MAX] = {0}; - int TBS_bytes = 848, header_length_total, num_sdus, offset, preambleTransMax, mac_ce_len; + int TBS_bytes = 848, header_length_total=0, num_sdus, offset, preambleTransMax, mac_ce_len; AssertFatal(CC_id == 0,"Transmission on secondary CCs is not supported yet\n"); diff --git a/targets/ARCH/ETHERNET/USERSPACE/LIB/ethernet_lib.c b/targets/ARCH/ETHERNET/USERSPACE/LIB/ethernet_lib.c index c72e7d4130..1d3c280f0e 100644 --- a/targets/ARCH/ETHERNET/USERSPACE/LIB/ethernet_lib.c +++ b/targets/ARCH/ETHERNET/USERSPACE/LIB/ethernet_lib.c @@ -288,7 +288,7 @@ int ethernet_tune(openair0_device *device, /******************* interface level options *************************/ case MTU_SIZE: /* change MTU of the eth interface */ ifr.ifr_addr.sa_family = AF_INET; - strncpy(ifr.ifr_name,eth->if_name, sizeof(ifr.ifr_name)); + strncpy(ifr.ifr_name,eth->if_name, sizeof(ifr.ifr_name)-1); ifr.ifr_mtu =value; if (ioctl(eth->sockfdd,SIOCSIFMTU,(caddr_t)&ifr) < 0 ) perror ("[ETHERNET] Can't set the MTU"); @@ -298,7 +298,7 @@ int ethernet_tune(openair0_device *device, case TX_Q_LEN: /* change TX queue length of eth interface */ ifr.ifr_addr.sa_family = AF_INET; - strncpy(ifr.ifr_name,eth->if_name, sizeof(ifr.ifr_name)); + strncpy(ifr.ifr_name,eth->if_name, sizeof(ifr.ifr_name)-1); ifr.ifr_qlen =value; if (ioctl(eth->sockfdd,SIOCSIFTXQLEN,(caddr_t)&ifr) < 0 ) perror ("[ETHERNET] Can't set the txqueuelen"); diff --git a/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp b/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp index 1377086e8f..6e94717a6f 100644 --- a/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp +++ b/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp @@ -976,7 +976,6 @@ extern "C" { double usrp_master_clock; if (device_adds[0].get("type") == "b200") { - printf("Found USRP b200\n"); device->type = USRP_B200_DEV; usrp_master_clock = 30.72e6; args += boost::str(boost::format(",master_clock_rate=%f") % usrp_master_clock); diff --git a/targets/ARCH/rfsimulator/simulator.c b/targets/ARCH/rfsimulator/simulator.c index b7b435f2d9..9f9e316da8 100644 --- a/targets/ARCH/rfsimulator/simulator.c +++ b/targets/ARCH/rfsimulator/simulator.c @@ -148,15 +148,18 @@ void allocCirBuf(rfsimulator_state_t *bridge, int sock) { // Legacy changes directlty the variable channel_model->path_loss_dB place to place // while calling new_channel_desc_scm() with path losses = 0 static bool init_done=false; + if (!init_done) { uint64_t rand; FILE *h=fopen("/dev/random","r"); - fread(&rand,sizeof(rand),1,h); + if ( 1 != fread(&rand,sizeof(rand),1,h) ) + LOG_W(HW, "Simulator can't read /dev/random\n"); fclose(h); randominit(rand); tableNor(rand); init_done=true; } + ptr->channel_model=new_channel_desc_scm(bridge->tx_num_channels,bridge->rx_num_channels, bridge->channelmod, bridge->sample_rate, @@ -379,6 +382,7 @@ static int rfsimulator_write_internal(rfsimulator_state_t *t, openair0_timestamp if (t->lastWroteTS > timestamp+nsamps) LOG_E(HW,"Not supported to send Tx out of order (same in USRP) %lu, %lu\n", t->lastWroteTS, timestamp); + t->lastWroteTS=timestamp+nsamps; if (!alreadyLocked) @@ -480,6 +484,7 @@ static bool flushInput(rfsimulator_state_t *t, int timeout, int nsamps_for_initi b->trashingPacket=true; } else if ( b->lastReceivedTS < b->th.timestamp) { int nbAnt= b->th.nbAnt; + if ( b->th.timestamp-b->lastReceivedTS < CirSize ) { for (uint64_t index=b->lastReceivedTS; index < b->th.timestamp; index++ ) { for (int a=0; a < nbAnt; a++) { @@ -490,8 +495,10 @@ static bool flushInput(rfsimulator_state_t *t, int timeout, int nsamps_for_initi } else { memset(b->circularBuf, 0, sampleToByte(CirSize,1)); } + if (b->lastReceivedTS != 0 && b->th.timestamp-b->lastReceivedTS > 50 ) LOG_W(HW,"UEsock: %d gap of: %ld in reception\n", fd, b->th.timestamp-b->lastReceivedTS ); + b->lastReceivedTS=b->th.timestamp; } else if ( b->lastReceivedTS > b->th.timestamp && b->th.size == 1 ) { @@ -510,7 +517,7 @@ static bool flushInput(rfsimulator_state_t *t, int timeout, int nsamps_for_initi LOG_E(HW,"UEsock: %d Tx/Rx shift too large Tx:%lu, Rx:%lu\n", fd, t->lastWroteTS, b->lastReceivedTS); pthread_mutex_unlock(&Sockmutex); - b->transferPtr=(char *)&b->circularBuf[b->lastReceivedTS%CirSize]; + b->transferPtr=(char *)&b->circularBuf[(b->lastReceivedTS*b->th.nbAnt)%CirSize]; b->remainToTransfer=sampleToByte(b->th.size, b->th.nbAnt); } @@ -653,6 +660,7 @@ int rfsimulator_read(openair0_device *device, openair0_timestamp *ptimestamp, vo else { // no channel modeling sample_t *out=(sample_t *)samplesVoid[a]; const int64_t base=t->nextTimestamp*nbAnt+a; + for ( int i=0; i < nsamps; i++ ) { const int idx=(i*nbAnt+base)%CirSize; out[i].r+=ptr->circularBuf[idx].r; From 7eb2ab66c56cdec882c07ee194b001959b6e265d Mon Sep 17 00:00:00 2001 From: frtabu Date: Tue, 28 Jul 2020 01:33:16 +0200 Subject: [PATCH 521/553] add telnet commands to show and modify channel simulation parameters --- cmake_targets/CMakeLists.txt | 4 +- cmake_targets/build_oai | 2 +- executables/nr-softmodem.c | 2 +- executables/nr-uesoftmodem.c | 5 +- openair1/PHY/TOOLS/nr_phy_scope.c | 16 ++- openair1/SIMULATION/TOOLS/random_channel.c | 123 +++++++++++++++++++-- openair1/SIMULATION/TOOLS/sim.h | 9 +- targets/ARCH/rfsimulator/simulator.c | 12 +- 8 files changed, 148 insertions(+), 25 deletions(-) diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index d5b90d3454..92b6b64f0f 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -2473,8 +2473,8 @@ add_library(uescope MODULE ${XFORMS_SOURCE} ${XFORMS_SOURCE_SOFTMODEM} ${XFORMS_ target_link_libraries(enbscope ${XFORMS_LIBRARIES}) target_link_libraries(uescope ${XFORMS_LIBRARIES}) -add_library(gnbscope MODULE ${XFORMS_SOURCE_NR}) -target_link_libraries(gnbscope ${XFORMS_LIBRARIES}) +add_library(nrscope MODULE ${XFORMS_SOURCE_NR}) +target_link_libraries(nrscope ${XFORMS_LIBRARIES}) add_library(rfsimulator MODULE diff --git a/cmake_targets/build_oai b/cmake_targets/build_oai index 88b8811575..e2753d9248 100755 --- a/cmake_targets/build_oai +++ b/cmake_targets/build_oai @@ -67,7 +67,7 @@ UE_TIMING_TRACE="False" USRP_REC_PLAY="False" BUILD_ECLIPSE=0 NR="False" -OPTIONAL_LIBRARIES="telnetsrv enbscope uescope msc" +OPTIONAL_LIBRARIES="telnetsrv enbscope uescope nrscope msc" trap handle_ctrl_c INT function print_help() { diff --git a/executables/nr-softmodem.c b/executables/nr-softmodem.c index 8f68485d29..95d57a535a 100644 --- a/executables/nr-softmodem.c +++ b/executables/nr-softmodem.c @@ -968,7 +968,7 @@ if(!IS_SOFTMODEM_NOS1) p.argv=argv; p.gNB=RC.gNB[0]; p.ru=RC.ru[0]; - load_softscope("gnb",&p); + load_softscope("nr",&p); } if (nfapi_mode != 1 && nfapi_mode != 2) { diff --git a/executables/nr-uesoftmodem.c b/executables/nr-uesoftmodem.c index b36a041a70..64cbb9495c 100644 --- a/executables/nr-uesoftmodem.c +++ b/executables/nr-uesoftmodem.c @@ -152,9 +152,6 @@ char ref[128] = "internal"; char channels[128] = "0"; -static char *parallel_config = NULL; -static char *worker_config = NULL; - int rx_input_level_dBm; //static int online_log_messages=0; @@ -764,7 +761,7 @@ int main( int argc, char **argv ) { mlockall(MCL_CURRENT | MCL_FUTURE); if(IS_SOFTMODEM_DOFORMS) { - load_softscope("gnb",PHY_vars_UE_g[0][0]); + load_softscope("nr",PHY_vars_UE_g[0][0]); } number_of_cards = 1; diff --git a/openair1/PHY/TOOLS/nr_phy_scope.c b/openair1/PHY/TOOLS/nr_phy_scope.c index fa86f690b2..5aff1ac48a 100644 --- a/openair1/PHY/TOOLS/nr_phy_scope.c +++ b/openair1/PHY/TOOLS/nr_phy_scope.c @@ -26,6 +26,7 @@ #include #include "nr_phy_scope.h" #include "executables/nr-softmodem-common.h" +#include "executables/softmodem-common.h" #include #define TPUT_WINDOW_LENGTH 100 @@ -416,7 +417,7 @@ static void *scope_thread_gNB(void *arg) { return NULL; } -void gnbscope_autoinit(scopeParms_t *p) { +void gNBinitScope(scopeParms_t *p) { static scopeParms_t parms; memcpy(&parms,p,sizeof(parms)); pthread_t forms_thread; @@ -763,11 +764,20 @@ static void *nrUEscopeThread(void *arg) { pthread_exit((void *)arg); } -void nruescope_autoinit(PHY_VARS_NR_UE *ue) { +void nrUEinitScope(PHY_VARS_NR_UE *ue) { pthread_t forms_thread; threadCreate(&forms_thread, nrUEscopeThread, ue, "scope", -1, OAI_PRIORITY_RT_LOW); } + +void nrscope_autoinit(void *dataptr) { + AssertFatal( (IS_SOFTMODEM_GNB_BIT||IS_SOFTMODEM_5GUE_BIT),"Scope cannot find NRUE or GNB context"); + + if (IS_SOFTMODEM_GNB_BIT) + gNBinitScope(dataptr); + else + nrUEinitScope(dataptr); +} // Kept to put back the functionality soon #if 0 //FD_stats_form *form_stats=NULL,*form_stats_l2=NULL; @@ -795,6 +805,8 @@ static void reset_stats_gNB(FL_OBJECT *button, } } + + static FD_stats_form *create_form_stats_form(int ID) { FL_OBJECT *obj; FD_stats_form *fdui = calloc(( sizeof *fdui ),1); diff --git a/openair1/SIMULATION/TOOLS/random_channel.c b/openair1/SIMULATION/TOOLS/random_channel.c index 41d8551e75..0cc0ba5501 100644 --- a/openair1/SIMULATION/TOOLS/random_channel.c +++ b/openair1/SIMULATION/TOOLS/random_channel.c @@ -45,8 +45,10 @@ static mapping channelmod_names[] = { }; static int channelmod_show_cmd(char *buff, int debug, telnet_printfunc_t prnt); +static int channelmod_modify_cmd(char *buff, int debug, telnet_printfunc_t prnt); static telnetshell_cmddef_t channelmod_cmdarray[] = { - {"show","",channelmod_show_cmd}, + {"show","",channelmod_show_cmd}, + {"modify"," ",channelmod_modify_cmd}, {"","",NULL}, }; @@ -56,7 +58,8 @@ static telnetshell_vardef_t channelmod_vardef[] = { static double snr_dB=25; static double sinr_dB=0; - +static unsigned int max_chan; +static channel_desc_t** defined_channels; void fill_channel_desc(channel_desc_t *chan_desc, uint8_t nb_tx, uint8_t nb_rx, @@ -281,10 +284,22 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx, int32_t channel_offset, double path_loss_dB) { channel_desc_t *chan_desc = (channel_desc_t *)malloc(sizeof(channel_desc_t)); + for(int i=0; ichan_idx=i; + break; + } + else { + AssertFatal(i<(max_chan-1), + "No more channel descriptors available, increase channelmod.max_chan parameter above %u\n",max_chan); + } + } uint16_t i,j; double sum_amps; double aoa,ricean_factor,Td,maxDoppler; int channel_length,nb_taps; + chan_desc->modelid = channel_model; chan_desc->nb_tx = nb_tx; chan_desc->nb_rx = nb_rx; chan_desc->sampling_rate = sampling_rate; @@ -1295,6 +1310,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx, void free_channel_desc_scm(channel_desc_t *ch) { // Must be made cleanly, a lot of leaks... + defined_channels[ch->chan_idx]=NULL; free(ch); } @@ -1408,11 +1424,11 @@ int random_channel(channel_desc_t *desc, uint8_t abstraction_flag) { desc->ch[aarx+(aatx*desc->nb_rx)][k].y = 0.0; for (l=0; lnb_taps; l++) { - if ((k - (desc->delays[l]*desc->sampling_rate) - NB_SAMPLES_CHANNEL_OFFSET) == 0) + if ((k - (desc->delays[l]*desc->sampling_rate) - desc->channel_offset) == 0) s = 1.0; else - s = sin(M_PI*(k - (desc->delays[l]*desc->sampling_rate) - NB_SAMPLES_CHANNEL_OFFSET))/ - (M_PI*(k - (desc->delays[l]*desc->sampling_rate) - NB_SAMPLES_CHANNEL_OFFSET)); + s = sin(M_PI*(k - (desc->delays[l]*desc->sampling_rate) - desc->channel_offset))/ + (M_PI*(k - (desc->delays[l]*desc->sampling_rate) - desc->channel_offset)); desc->ch[aarx+(aatx*desc->nb_rx)][k].x += s*desc->a[l][aarx+(aatx*desc->nb_rx)].x; desc->ch[aarx+(aatx*desc->nb_rx)][k].y += s*desc->a[l][aarx+(aatx*desc->nb_rx)].y; @@ -1491,13 +1507,99 @@ double N_RB2channel_bandwidth(uint16_t N_RB) { return(channel_bandwidth); } +static void display_channelmodel_help( telnet_printfunc_t prnt) { + +} + + +static void display_channelmodel(channel_desc_t *cd,int debug, telnet_printfunc_t prnt) { + prnt("nb_tx: %i nb_rx: %i taps: %i bandwidth: %lf sampling: %lf\n",cd->nb_tx, cd->nb_rx, cd->nb_taps, cd->channel_bandwidth, cd->sampling_rate); + prnt("channel length: %i Max path delay: %lf ricean fact.: %lf angle of arrival: %lf (randomized:%s)\n", + cd->channel_length, cd->Td, cd->ricean_factor, cd->aoa, (cd->random_aoa?"Yes":"No")); + prnt("max Doppler: %lf path loss: %lf rchannel offset: %i forget factor; %lf\n", + cd->max_Doppler, cd->path_loss_dB, cd->channel_offset, cd->forgetting_factor); + prnt("Initial phase: %lf nb_path: %i \n", + cd->ip, cd->nb_paths); + for (int i=0; inb_taps ; i++) { + prnt("taps: %i lin. ampli. : %lf delay: %lf \n",i,cd->amps[i], cd->delays[i]); + } +} + static int channelmod_show_cmd(char *buff, int debug, telnet_printfunc_t prnt) { - for(int i=0; channelmod_names[i].name != NULL ; i++) { - prnt(" %i %s\n", i, map_int_to_str(channelmod_names,i )); - } + char *subcmd=NULL; + int s = sscanf(buff,"%ms\n",&subcmd); - return 0; + if (s>0) { + if ( strcmp(subcmd,"predef") == 0) { + for (int i=0; channelmod_names[i].name != NULL ; i++) { + prnt(" %i %s\n", i, map_int_to_str(channelmod_names,i )); + } + } else if ( strcmp(subcmd,"current") == 0) { + for (int i=0; i < max_chan ; i++) { + if (defined_channels[i] != NULL) { + prnt("model %i %s: \n----------------\n", i, map_int_to_str(channelmod_names,defined_channels[i]->modelid)); + display_channelmodel(defined_channels[i],debug,prnt); + } + } + } else { + display_channelmodel_help(prnt); + } + free(subcmd); + } + return CMDSTATUS_FOUND; +} + + + +static int channelmod_modify_cmd(char *buff, int debug, telnet_printfunc_t prnt) { + char *param=NULL, *value=NULL; + int cd_id= -1; + int s = sscanf(buff,"%i %ms %ms \n",&cd_id,¶m, &value); + if (cd_id<0 || cd_id >= max_chan) { + prnt("ERROR, %i: Channel model id outof range (0-%i)\n",cd_id,max_chan-1); + return CMDSTATUS_FOUND; + } + if (defined_channels[cd_id]==NULL) { + prnt("ERROR, %i: Channel model has not been set\n",cd_id); + return CMDSTATUS_FOUND; + } + + if (s==3) { + if ( strcmp(param,"riceanf") == 0) { + double dbl = atof(value); + if (dbl <0 || dbl > 1) + prnt("ricean factor range: 0 to 1, %lf is outof range\n",dbl); + else + defined_channels[cd_id]->ricean_factor=dbl; + } else if ( strcmp(param,"aoa") == 0) { + double dbl = atof(value); + if (dbl <0 || dbl >6.28) + prnt("angle of arrival range: 0 to 2*Pi, %lf is outof range\n",dbl); + else + defined_channels[cd_id]->aoa=dbl; + } else if ( strcmp(param,"ploss") == 0) { + double dbl = atof(value); + defined_channels[cd_id]->path_loss_dB=dbl; + } else if ( strcmp(param,"offset") == 0) { + int i = atoi(value); + defined_channels[cd_id]->channel_offset=i; + } else if ( strcmp(param,"forgetf") == 0) { + double dbl = atof(value); + if (dbl <0 || dbl > 1) + prnt("forgetting factor range: 0 to 1 (disable variation), %lf is outof range\n",dbl); + else + defined_channels[cd_id]->forgetting_factor=dbl; + } else { + + } + display_channelmodel(defined_channels[cd_id],debug,prnt); + free(param); + free(value); + + } + + return CMDSTATUS_FOUND; } int modelid_fromname(char *modelname) { @@ -1519,6 +1621,9 @@ void init_channelmod(void) { paramdef_t channelmod_params[] = CHANNELMOD_PARAMS_DESC; int ret = config_get( channelmod_params,sizeof(channelmod_params)/sizeof(paramdef_t),CHANNELMOD_SECTION); AssertFatal(ret >= 0, "configuration couldn't be performed"); + defined_channels=calloc(max_chan,sizeof( channel_desc_t*)); + AssertFatal(defined_channels!=NULL, "couldn't allocate %u channel descriptors\n",max_chan); + /* look for telnet server, if it is loaded, add the channel modeling commands to it */ add_telnetcmd_func_t addcmd = (add_telnetcmd_func_t)get_shlibmodule_fptr("telnetsrv", TELNET_ADDCMD_FNAME); diff --git a/openair1/SIMULATION/TOOLS/sim.h b/openair1/SIMULATION/TOOLS/sim.h index 6071e1e743..2e067e4ae8 100644 --- a/openair1/SIMULATION/TOOLS/sim.h +++ b/openair1/SIMULATION/TOOLS/sim.h @@ -92,6 +92,10 @@ typedef struct { time_stats_t interp_time; time_stats_t interp_freq; time_stats_t convolution; + /// index in the channel descriptors array + unsigned int chan_idx; + /// id of the channel modeling algorithm + int modelid; } channel_desc_t; typedef struct { @@ -214,8 +218,9 @@ typedef enum { #define CONFIG_HLP_SNR "Set average SNR in dB (for --siml1 option)\n" #define CHANNELMOD_SECTION "channelmod" #define CHANNELMOD_PARAMS_DESC { \ - {"s" , CONFIG_HLP_SNR, PARAMFLAG_CMDLINE_NOPREFIXENABLED, dblptr:&snr_dB , defdblval:25, TYPE_DOUBLE, 0},\ - {"sinr_dB", NULL , 0 , dblptr:&sinr_dB, defdblval:0 , TYPE_DOUBLE, 0},\ + {"s" , CONFIG_HLP_SNR, PARAMFLAG_CMDLINE_NOPREFIXENABLED, dblptr:&snr_dB, defdblval:25, TYPE_DOUBLE, 0},\ + {"sinr_dB", NULL, 0 , dblptr:&sinr_dB, defdblval:0 , TYPE_DOUBLE, 0},\ + {"max_chan, CONFIG_HLP_MAX_CHAN", 0, uptr:&max_chan, defintval:10, TYPE_UINT, 0},\ } #include "platform_constants.h" diff --git a/targets/ARCH/rfsimulator/simulator.c b/targets/ARCH/rfsimulator/simulator.c index b7b435f2d9..ff53ca8c46 100644 --- a/targets/ARCH/rfsimulator/simulator.c +++ b/targets/ARCH/rfsimulator/simulator.c @@ -78,9 +78,11 @@ extern RAN_CONTEXT_t RC; #define RFSIMULATOR_PARAMS_DESC {\ {"serveraddr", "\n", 0, strptr:&(rfsimulator->ip), defstrval:"127.0.0.1", TYPE_STRING, 0 },\ {"serverport", "\n", 0, u16ptr:&(rfsimulator->port), defuintval:PORT, TYPE_UINT16, 0 },\ - {RFSIMU_OPTIONS_PARAMNAME, RFSIM_CONFIG_HELP_OPTIONS, 0, strlistptr:NULL, defstrlistval:NULL, TYPE_STRINGLIST,0},\ + {RFSIMU_OPTIONS_PARAMNAME, RFSIM_CONFIG_HELP_OPTIONS, 0, strlistptr:NULL, defstrlistval:NULL, TYPE_STRINGLIST,0 },\ {"IQfile", "\n", 0, strptr:&(saveF), defstrval:"/tmp/rfsimulator.iqs",TYPE_STRING, 0 },\ - {"modelname", "\n", 0, strptr:&(modelname), defstrval:"AWGN", TYPE_STRING, 0 }\ + {"modelname", "\n", 0, strptr:&(modelname), defstrval:"AWGN", TYPE_STRING, 0 },\ + {"ploss", "\n", 0, dblptr:&(rfsimulator->chan_pathloss), defdblval:0, TYPE_DOUBLE, 0 },\ + {"forgetfact", "\n", 0, dblptr:&(rfsimulator->chan_forgetfact), defdblval:0, TYPE_DOUBLE, 0 }\ }; pthread_mutex_t Sockmutex; @@ -114,6 +116,8 @@ typedef struct { double sample_rate; double tx_bw; int channelmod; + double chan_pathloss; + double chan_forgetfact; } rfsimulator_state_t; @@ -161,9 +165,9 @@ void allocCirBuf(rfsimulator_state_t *bridge, int sock) { bridge->channelmod, bridge->sample_rate, bridge->tx_bw, - 0.0, // forgetting_factor + bridge->chan_forgetfact, // forgetting_factor 0, // maybe used for TA - 0); // path_loss in dB + bridge->chan_pathloss); // path_loss in dB random_channel(ptr->channel_model,false); } } From 828bab2fd6bfb619c169bae7cb68fd3e16968f3f Mon Sep 17 00:00:00 2001 From: "dong.zhanyi" Date: Tue, 28 Jul 2020 07:34:05 +0800 Subject: [PATCH 522/553] fixed the bug no supporting CellId more than 256 --- nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h index fea64e3f3e..c8624e9e91 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h @@ -364,7 +364,7 @@ typedef struct //table 3-22 typedef struct { - nfapi_uint8_tlv_t phy_cell_id;//Physical Cell ID, 𝑁_{𝐼𝐷}^{𝑐𝑒𝑙𝑙} [38.211, sec 7.4.2.1] Value: 0 ->1007 + nfapi_uint16_tlv_t phy_cell_id;//Physical Cell ID, 𝑁_{𝐼𝐷}^{𝑐𝑒𝑙𝑙} [38.211, sec 7.4.2.1] Value: 0 ->1007 nfapi_uint8_tlv_t frame_duplex_type;//Frame duplex type Value: 0 = FDD 1 = TDD } nfapi_nr_cell_config_t; From eceb1ed21f26567582cc14730ebc5d0434228571 Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Tue, 28 Jul 2020 10:40:15 +0200 Subject: [PATCH 523/553] fixed air_interface variable for ocp-enb option --- ci-scripts/main.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/ci-scripts/main.py b/ci-scripts/main.py index 4ea2884c3b..bb4a87099d 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -3160,7 +3160,7 @@ def GetParametersFromXML(action): elif (air_interface.lower() in ['nr','lte']): CiTestObj.air_interface = air_interface.lower() +'-softmodem' else : - CiTestObj.air_interface = air_interface.lower() +'ocp-enb' + CiTestObj.air_interface = 'ocp-enb' RAN.air_interface(CiTestObj.air_interface) if action == 'Terminate_eNB': @@ -3178,7 +3178,7 @@ def GetParametersFromXML(action): elif (air_interface.lower() in ['nr','lte']): CiTestObj.air_interface = air_interface.lower() +'-softmodem' else : - CiTestObj.air_interface = air_interface.lower() +'ocp-enb' + CiTestObj.air_interface = 'ocp-enb' RAN.air_interface=CiTestObj.air_interface if action == 'Attach_UE': @@ -3216,7 +3216,7 @@ def GetParametersFromXML(action): elif (air_interface.lower() in ['nr','lte']): CiTestObj.air_interface = air_interface.lower() +'-softmodem' else : - CiTestObj.air_interface = air_interface.lower() +'ocp-enb' + CiTestObj.air_interface = 'ocp-enb' RAN.air_interface=CiTestObj.air_interface if action == 'Terminate_OAI_UE': From 8c9501b6a691d458f8a57ae335e528af814d2276 Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Tue, 28 Jul 2020 14:17:27 +0200 Subject: [PATCH 524/553] fixing args_parse function arguments list --- ci-scripts/args_parse.py | 4 ++-- ci-scripts/main.py | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/ci-scripts/args_parse.py b/ci-scripts/args_parse.py index a36f619ee2..b51fbc500d 100644 --- a/ci-scripts/args_parse.py +++ b/ci-scripts/args_parse.py @@ -41,7 +41,7 @@ import yaml #----------------------------------------------------------- -def ArgsParse(argvs,CiTestObj,RAN,HTML,ldpc,HELP): +def ArgsParse(argvs,CiTestObj,RAN,HTML,EPC,ldpc,HELP): py_param_file_present = False @@ -226,4 +226,4 @@ def ArgsParse(argvs,CiTestObj,RAN,HTML,ldpc,HELP): HELP.GenericHelp(CONST.Version) sys.exit('Invalid Parameter: ' + myArgv) - return py_param_file_present, py_params, mode \ No newline at end of file + return py_param_file_present, py_params, mode diff --git a/ci-scripts/main.py b/ci-scripts/main.py index bb4a87099d..693406efff 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -3332,7 +3332,7 @@ ldpc=cls_physim.PhySim() #create an instance for LDPC test using GPU or CPU b #----------------------------------------------------------- import args_parse -py_param_file_present, py_params, mode = args_parse.ArgsParse(sys.argv,CiTestObj,RAN,HTML,ldpc,HELP) +py_param_file_present, py_params, mode = args_parse.ArgsParse(sys.argv,CiTestObj,RAN,HTML,EPC,ldpc,HELP) #argvs = sys.argv #py_param_file_present = False From d3b415d6ed14d60d3dad6d266d8f90179d964e2a Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Tue, 28 Jul 2020 14:22:46 +0200 Subject: [PATCH 525/553] commented out printing of object attributes (debug) --- ci-scripts/main.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/ci-scripts/main.py b/ci-scripts/main.py index 693406efff..5b1b31fafd 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -3525,10 +3525,10 @@ if py_param_file_present == True: AssignParams(py_params) #for debug -print(RAN.__dict__) -print(CiTestObj.__dict__) -print(HTML.__dict__) -print(ldpc.__dict__) +#print(RAN.__dict__) +#print(CiTestObj.__dict__) +#print(HTML.__dict__) +#print(ldpc.__dict__) #for debug From 31a0d28ad9bc3ef2d7024b7c16bed49b20b96623 Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Tue, 28 Jul 2020 15:22:46 +0200 Subject: [PATCH 526/553] CI: fix a few typos Signed-off-by: Raphael Defosseux --- ci-scripts/main.py | 13 +++++++++---- ci-scripts/ran.py | 2 +- cmake_targets/build_oai | 2 +- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/ci-scripts/main.py b/ci-scripts/main.py index 5b1b31fafd..21676719a0 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -1,4 +1,4 @@ - +#/* # * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more # * contributor license agreements. See the NOTICE file distributed with # * this work for additional information regarding copyright ownership. @@ -1598,7 +1598,7 @@ class OaiCiTest(): return result def Iperf_analyzeV2TCPOutput(self, lock, UE_IPAddress, device_id, statusQueue, iperf_real_options): - SSH.command('awk -f /tmp/tcp_iperf_stats.awk /tmp/CI-eNB/scripts/iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) + SSH.command('awk -f /tmp/tcp_iperf_stats.awk ' + EPC.SourceCodePath + '/scripts/iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', 5) result = re.search('Avg Bitrate : (?P[0-9\.]+ Mbits\/sec) Max Bitrate : (?P[0-9\.]+ Mbits\/sec) Min Bitrate : (?P[0-9\.]+ Mbits\/sec)', SSH.getBefore()) if result is not None: avgbitrate = result.group('average') @@ -3161,7 +3161,7 @@ def GetParametersFromXML(action): CiTestObj.air_interface = air_interface.lower() +'-softmodem' else : CiTestObj.air_interface = 'ocp-enb' - RAN.air_interface(CiTestObj.air_interface) + RAN.air_interface=CiTestObj.air_interface if action == 'Terminate_eNB': RAN.eNB_instance=test.findtext('eNB_instance') @@ -3304,7 +3304,12 @@ def receive_signal(signum, frame): #loading xml action list from yaml import yaml -with open('xml_class_list.yml','r') as file: +xml_class_list_file='' +if (os.path.isfile('xml_class_list.yml')): + xml_class_list_file='xml_class_list.yml' +if (os.path.isfile('ci-scripts/xml_class_list.yml')): + xml_class_list_file='ci-scripts/xml_class_list.yml' +with open(xml_class_list_file,'r') as file: # The FullLoader parameter handles the conversion from YAML # scalar values to Python the dictionary format xml_class_list = yaml.load(file,Loader=yaml.FullLoader) diff --git a/ci-scripts/ran.py b/ci-scripts/ran.py index 23a004e4ce..b1d26b8af3 100644 --- a/ci-scripts/ran.py +++ b/ci-scripts/ran.py @@ -536,7 +536,7 @@ class RANManagement(): # Make a copy and adapt to EPC / eNB IP addresses mySSH.command('cp ' + full_config_file + ' ' + ci_full_config_file, '\$', 5) if self.epcObj is not None: - localMmeIpAddr = self.epcObj.GetMmeIPAddress() + localMmeIpAddr = self.epcObj.MmeIPAddress mySSH.command('sed -i -e \'s/CI_MME_IP_ADDR/' + localMmeIpAddr + '/\' ' + ci_full_config_file, '\$', 2); mySSH.command('sed -i -e \'s/CI_ENB_IP_ADDR/' + lIpAddr + '/\' ' + ci_full_config_file, '\$', 2); mySSH.command('sed -i -e \'s/CI_RCC_IP_ADDR/' + self.eNBIPAddress + '/\' ' + ci_full_config_file, '\$', 2); diff --git a/cmake_targets/build_oai b/cmake_targets/build_oai index 469c840b4d..4c8399f4a9 100755 --- a/cmake_targets/build_oai +++ b/cmake_targets/build_oai @@ -830,7 +830,7 @@ function main() { #################################################### # Build RF device and transport protocol libraries # #################################################### - if [ "$eNB" = "1" -o "$UE" = "1" -o "$gNB" = "1" -o "$nrUE" = "1" -o "$HWLAT" = "1" ] ; then + if [ "$eNB" = "1" -o "$eNBocp" = "1" -o "$UE" = "1" -o "$gNB" = "1" -o "$nrUE" = "1" -o "$HWLAT" = "1" ] ; then # build RF device libraries if [ "$HW" != "None" ] ; then From 5dd3e3353d028b2ff54fd3d2f61a734dd2be7511 Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Tue, 28 Jul 2020 15:25:00 +0200 Subject: [PATCH 527/553] CI: using ninja for OCP build Signed-off-by: Raphael Defosseux --- ci-scripts/xml_files/enb_ocp_usrp210_build.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ci-scripts/xml_files/enb_ocp_usrp210_build.xml b/ci-scripts/xml_files/enb_ocp_usrp210_build.xml index 8110c7f1b6..33a0fc205e 100644 --- a/ci-scripts/xml_files/enb_ocp_usrp210_build.xml +++ b/ci-scripts/xml_files/enb_ocp_usrp210_build.xml @@ -32,7 +32,7 @@ Build_eNB Build eNB OCP (USRP) - -w USRP -c --eNBocp + -w USRP -c --eNBocp --ninja From b8edd71244886c4293d90615ea73bd3ea2b96c84 Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Tue, 28 Jul 2020 16:03:28 +0200 Subject: [PATCH 528/553] CI: adding retries on OCP test Signed-off-by: Raphael Defosseux --- ci-scripts/xml_files/enb_ocp_usrp210_band7_test_05mhz_tm1.xml | 1 + 1 file changed, 1 insertion(+) diff --git a/ci-scripts/xml_files/enb_ocp_usrp210_band7_test_05mhz_tm1.xml b/ci-scripts/xml_files/enb_ocp_usrp210_band7_test_05mhz_tm1.xml index 5326973cc2..854fb8cb19 100644 --- a/ci-scripts/xml_files/enb_ocp_usrp210_band7_test_05mhz_tm1.xml +++ b/ci-scripts/xml_files/enb_ocp_usrp210_band7_test_05mhz_tm1.xml @@ -24,6 +24,7 @@ test-05-tm1 Test-05MHz-TM1 tasks + 4 030201 040101 From 5c2df00101cb0bdf83b3d04f373fb93588bd77e9 Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Tue, 28 Jul 2020 16:28:36 +0200 Subject: [PATCH 529/553] CI: fix terminate Signed-off-by: Raphael Defosseux --- ci-scripts/ran.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ci-scripts/ran.py b/ci-scripts/ran.py index b1d26b8af3..833e2784d1 100644 --- a/ci-scripts/ran.py +++ b/ci-scripts/ran.py @@ -710,12 +710,12 @@ class RANManagement(): result = re.search('(-softmodem|ocp)', mySSH.getBefore()) if result is not None: mySSH.command('echo ' + lPassWord + ' | sudo -S daemon --name=enb' + str(self.eNB_instance) + '_daemon --stop', '\$', 5) - mySSH.command('echo ' + lPassWord + ' | sudo -S killall --signal SIGINT -r .*-softmodem .ocp-enb || true', '\$', 5) + mySSH.command('echo ' + lPassWord + ' | sudo -S killall --signal SIGINT -r .*-softmodem ocp-enb || true', '\$', 5) time.sleep(10) mySSH.command('stdbuf -o0 ps -aux | grep --color=never -e softmodem -e ocp-enb | grep -v grep', '\$', 5) result = re.search('(-softmodem|ocp)', mySSH.getBefore()) if result is not None: - mySSH.command('echo ' + lPassWord + ' | sudo -S killall --signal SIGKILL -r .*-softmodem .ocp-enb || true', '\$', 5) + mySSH.command('echo ' + lPassWord + ' | sudo -S killall --signal SIGKILL -r .*-softmodem ocp-enb || true', '\$', 5) time.sleep(5) mySSH.command('rm -f my-lte-softmodem-run' + str(self.eNB_instance) + '.sh', '\$', 5) mySSH.close() From ca21ad8b365fc6bcaf0606fa86a859ae160cd2a4 Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Tue, 28 Jul 2020 17:02:28 +0200 Subject: [PATCH 530/553] cleaned-removed commented-out legacy code --- ci-scripts/epc.py | 32 -------- ci-scripts/html.py | 55 ------------- ci-scripts/main.py | 187 --------------------------------------------- ci-scripts/ran.py | 137 --------------------------------- 4 files changed, 411 deletions(-) diff --git a/ci-scripts/epc.py b/ci-scripts/epc.py index 14bbcd0540..25bbbba091 100644 --- a/ci-scripts/epc.py +++ b/ci-scripts/epc.py @@ -66,38 +66,6 @@ class EPCManagement(): self.MmeIPAddress = '' self.containerPrefix = 'prod' -#----------------------------------------------------------- -# Setter and Getters on Public Members -#----------------------------------------------------------- - -# def SetIPAddress(self, ipaddress): -# self.IPAddress = ipaddress -# def GetIPAddress(self): -# return self.IPAddress -# def SetUserName(self, username): -# self.UserName = username -# def GetUserName(self): -# return self.UserName -# def SetPassword(self, password): -# self.Password = password -# def GetPassword(self): -# return self.Password -# def SetSourceCodePath(self, sourcecodepath): -# self.SourceCodePath = sourcecodepath -# def GetSourceCodePath(self): -# return self.SourceCodePath -# def SetType(self, kind): -# self.Type = kind -# def GetType(self): -# return self.Type -# def SetHtmlObj(self, obj): -# self.htmlObj = obj -# def SetTestCase_id(self, idx): -# self.testCase_id = idx -# def GetMmeIPAddress(self): -# return self.MmeIPAddress -# def SetContainerPrefix(self, prefix): -# self.containerPrefix = prefix #----------------------------------------------------------- # EPC management functions diff --git a/ci-scripts/html.py b/ci-scripts/html.py index b7b3c31fad..8f2d38cced 100644 --- a/ci-scripts/html.py +++ b/ci-scripts/html.py @@ -90,61 +90,6 @@ class HTMLManagement(): self.htmlUEConnected = 1 -# def SethtmlUEFailureMsg(self,huefa): -# self.htmlUEFailureMsg = huefa -# def GethtmlUEFailureMsg(self): -# return self.htmlUEFailureMsg -# def SetHmleNBFailureMsg(self, msg): -# self.htmleNBFailureMsg = msg -# def Setdesc(self, dsc): -# self.desc = dsc -# def SetstartTime(self, sttime): -# self.startTime = sttime -# def SettestCase_id(self, tcid): -# self.testCase_id = tcid -# def GettestCase_id(self): -# return self.testCase_id -# def SetranRepository(self, repository): -# self.ranRepository = repository -# def SetranAllowMerge(self, merge): -# self.ranAllowMerge = merge -# def SetranBranch(self, branch): -# self.ranBranch = branch -# def SetranCommitID(self, commitid): -# self.ranCommitID = commitid -# def SetranTargetBranch(self, tbranch): -# self.ranTargetBranch = tbranch -# def SethtmlNb_Smartphones(self, nbUEs): -# self.htmlNb_Smartphones = nbUEs -# def SethtmlNb_CATM_Modules(self, nbUEs): -# self.htmlNb_CATM_Modules = nbUEs -# def SetnbTestXMLfiles(self, nb): -# self.nbTestXMLfiles = nb -# def GetnbTestXMLfiles(self): -# return self.nbTestXMLfiles -# def SettestXMLfiles(self, xmlFile): -# self.testXMLfiles.append(xmlFile) -# def SethtmlTabRefs(self, tabRef): -# self.htmlTabRefs.append(tabRef) -# def SethtmlTabNames(self, tabName): -# self.htmlTabNames.append(tabName) -# def SethtmlTabIcons(self, tabIcon): -# self.htmlTabIcons.append(tabIcon) -# def SetOsVersion(self, version, idx): -# self.OsVersion[idx] = version -# def SetKernelVersion(self, version, idx): -# self.KernelVersion[idx] = version -# def SetUhdVersion(self, version, idx): -# self.UhdVersion[idx] = version -# def SetUsrpBoard(self, version, idx): -# self.UsrpBoard[idx] = version -# def SetCpuNb(self, nb, idx): -# self.CpuNb[idx] = nb -# def SetCpuModel(self, model, idx): -# self.CpuModel[idx] = model -# def SetCpuMHz(self, freq, idx): -# self.CpuMHz[idx] = freq - #----------------------------------------------------------- # HTML structure creation functions diff --git a/ci-scripts/main.py b/ci-scripts/main.py index 21676719a0..5b9b98988b 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -3084,12 +3084,6 @@ class OaiCiTest(): def CheckClassValidity(xml_class_list,action,id): -# if action !='COTS_UE_Airplane' and action!='Build_PhySim' and action!='Run_PhySim' and action != 'Build_eNB' and action != 'WaitEndBuild_eNB' and action != 'Initialize_eNB' and action != 'Terminate_eNB' and -# action != 'Initialize_UE' and action != 'Terminate_UE' and action != 'Attach_UE' and action != 'Detach_UE' and action != 'Build_OAI_UE' and action != 'Initialize_OAI_UE' and action != 'Terminate_OAI_UE' and -# action != 'DataDisable_UE' and action != 'DataEnable_UE' and action != 'CheckStatusUE' and action != 'Ping' and action != 'Iperf' and action != 'Reboot_UE' and action != 'Initialize_FlexranCtrl' and -# action != 'Terminate_FlexranCtrl' and action != 'Initialize_HSS' and action != 'Terminate_HSS' and action != 'Initialize_MME' and action != 'Terminate_MME' and action != 'Initialize_SPGW' and -# action != 'Terminate_SPGW' and action != 'Initialize_CatM_module' and action != 'Terminate_CatM_module' and action != 'Attach_CatM_module' and action != 'Detach_CatM_module' and -# action != 'Ping_CatM_module' and action != 'IdleSleep' and action != 'Perform_X2_Handover': if action not in xml_class_list: logging.debug('ERROR: test-case ' + id + ' has unlisted class ' + action + ' ##CHECK xml_class_list.yml') resp=False @@ -3339,187 +3333,6 @@ ldpc=cls_physim.PhySim() #create an instance for LDPC test using GPU or CPU b import args_parse py_param_file_present, py_params, mode = args_parse.ArgsParse(sys.argv,CiTestObj,RAN,HTML,EPC,ldpc,HELP) -#argvs = sys.argv -#py_param_file_present = False -# -#while len(argvs) > 1: -# myArgv = argvs.pop(1) # 0th is this file's name -# -# #--help -# if re.match('^\-\-help$', myArgv, re.IGNORECASE): -# HELP.GenericHelp(CONST.Version) -# sys.exit(0) -# -# #--apply= as parameters file, to replace inline parameters -# elif re.match('^\-\-Apply=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-Apply=(.+)$', myArgv, re.IGNORECASE) -# py_params_file = matchReg.group(1) -# with open(py_params_file,'r') as file: -# # The FullLoader parameter handles the conversion from YAML -# # scalar values to Python dictionary format -# py_params = yaml.load(file,Loader=yaml.FullLoader) -# py_param_file_present = True #to be removed once validated -# #AssignParams(py_params) #to be uncommented once validated -# -# #consider inline parameters -# elif re.match('^\-\-mode=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-mode=(.+)$', myArgv, re.IGNORECASE) -# mode = matchReg.group(1) -# elif re.match('^\-\-eNBRepository=(.+)$|^\-\-ranRepository(.+)$', myArgv, re.IGNORECASE): -# if re.match('^\-\-eNBRepository=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-eNBRepository=(.+)$', myArgv, re.IGNORECASE) -# else: -# matchReg = re.match('^\-\-ranRepository=(.+)$', myArgv, re.IGNORECASE) -# CiTestObj.ranRepository = matchReg.group(1) -# RAN.ranRepository=matchReg.group(1) -# HTML.ranRepository=matchReg.group(1) -# ldpc.ranRepository=matchReg.group(1) -# elif re.match('^\-\-eNB_AllowMerge=(.+)$|^\-\-ranAllowMerge=(.+)$', myArgv, re.IGNORECASE): -# if re.match('^\-\-eNB_AllowMerge=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-eNB_AllowMerge=(.+)$', myArgv, re.IGNORECASE) -# else: -# matchReg = re.match('^\-\-ranAllowMerge=(.+)$', myArgv, re.IGNORECASE) -# doMerge = matchReg.group(1) -# ldpc.ranAllowMerge=matchReg.group(1) -# if ((doMerge == 'true') or (doMerge == 'True')): -# CiTestObj.ranAllowMerge = True -# RAN.ranAllowMerge=True -# HTML.ranAllowMerge=True -# elif re.match('^\-\-eNBBranch=(.+)$|^\-\-ranBranch=(.+)$', myArgv, re.IGNORECASE): -# if re.match('^\-\-eNBBranch=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-eNBBranch=(.+)$', myArgv, re.IGNORECASE) -# else: -# matchReg = re.match('^\-\-ranBranch=(.+)$', myArgv, re.IGNORECASE) -# CiTestObj.ranBranch = matchReg.group(1) -# RAN.ranBranch=matchReg.group(1) -# HTML.ranBranch=matchReg.group(1) -# ldpc.ranBranch=matchReg.group(1) -# elif re.match('^\-\-eNBCommitID=(.*)$|^\-\-ranCommitID=(.*)$', myArgv, re.IGNORECASE): -# if re.match('^\-\-eNBCommitID=(.*)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-eNBCommitID=(.*)$', myArgv, re.IGNORECASE) -# else: -# matchReg = re.match('^\-\-ranCommitID=(.*)$', myArgv, re.IGNORECASE) -# CiTestObj.ranCommitID = matchReg.group(1) -# RAN.ranCommitID=matchReg.group(1) -# HTML.ranCommitID=matchReg.group(1) -# ldpc.ranCommitID=matchReg.group(1) -# elif re.match('^\-\-eNBTargetBranch=(.*)$|^\-\-ranTargetBranch=(.*)$', myArgv, re.IGNORECASE): -# if re.match('^\-\-eNBTargetBranch=(.*)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-eNBTargetBranch=(.*)$', myArgv, re.IGNORECASE) -# else: -# matchReg = re.match('^\-\-ranTargetBranch=(.*)$', myArgv, re.IGNORECASE) -# CiTestObj.ranTargetBranch = matchReg.group(1) -# RAN.ranTargetBranch=matchReg.group(1) -# HTML.ranTargetBranch=matchReg.group(1) -# ldpc.ranTargetBranch=matchReg.group(1) -# elif re.match('^\-\-eNBIPAddress=(.+)$|^\-\-eNB[1-2]IPAddress=(.+)$', myArgv, re.IGNORECASE): -# if re.match('^\-\-eNBIPAddress=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-eNBIPAddress=(.+)$', myArgv, re.IGNORECASE) -# RAN.eNBIPAddress=matchReg.group(1) -# ldpc.eNBIpAddr=matchReg.group(1) -# elif re.match('^\-\-eNB1IPAddress=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-eNB1IPAddress=(.+)$', myArgv, re.IGNORECASE) -# RAN.eNB1IPAddress=matchReg.group(1) -# elif re.match('^\-\-eNB2IPAddress=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-eNB2IPAddress=(.+)$', myArgv, re.IGNORECASE) -# RAN.eNB2IPAddress=matchReg.group(1) -# elif re.match('^\-\-eNBUserName=(.+)$|^\-\-eNB[1-2]UserName=(.+)$', myArgv, re.IGNORECASE): -# if re.match('^\-\-eNBUserName=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-eNBUserName=(.+)$', myArgv, re.IGNORECASE) -# RAN.eNBUserName=matchReg.group(1) -# ldpc.eNBUserName=matchReg.group(1) -# elif re.match('^\-\-eNB1UserName=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-eNB1UserName=(.+)$', myArgv, re.IGNORECASE) -# RAN.eNB1UserName=matchReg.group(1) -# elif re.match('^\-\-eNB2UserName=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-eNB2UserName=(.+)$', myArgv, re.IGNORECASE) -# RAN.eNB2UserName=matchReg.group(1) -# elif re.match('^\-\-eNBPassword=(.+)$|^\-\-eNB[1-2]Password=(.+)$', myArgv, re.IGNORECASE): -# if re.match('^\-\-eNBPassword=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-eNBPassword=(.+)$', myArgv, re.IGNORECASE) -# RAN.eNBPassword=matchReg.group(1) -# ldpc.eNBPassWord=matchReg.group(1) -# elif re.match('^\-\-eNB1Password=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-eNB1Password=(.+)$', myArgv, re.IGNORECASE) -# RAN.eNB1Password=matchReg.group(1) -# elif re.match('^\-\-eNB2Password=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-eNB2Password=(.+)$', myArgv, re.IGNORECASE) -# RAN.eNB2Password=matchReg.group(1) -# elif re.match('^\-\-eNBSourceCodePath=(.+)$|^\-\-eNB[1-2]SourceCodePath=(.+)$', myArgv, re.IGNORECASE): -# if re.match('^\-\-eNBSourceCodePath=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-eNBSourceCodePath=(.+)$', myArgv, re.IGNORECASE) -# RAN.eNBSourceCodePath=matchReg.group(1) -# ldpc.eNBSourceCodePath=matchReg.group(1) -# elif re.match('^\-\-eNB1SourceCodePath=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-eNB1SourceCodePath=(.+)$', myArgv, re.IGNORECASE) -# RAN.eNB1SourceCodePath=matchReg.group(1) -# elif re.match('^\-\-eNB2SourceCodePath=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-eNB2SourceCodePath=(.+)$', myArgv, re.IGNORECASE) -# RAN.eNB2SourceCodePath=matchReg.group(1) -# elif re.match('^\-\-EPCIPAddress=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-EPCIPAddress=(.+)$', myArgv, re.IGNORECASE) -# EPC.IPAddress=matchReg.group(1) -# elif re.match('^\-\-EPCUserName=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-EPCUserName=(.+)$', myArgv, re.IGNORECASE) -# EPC.UserName=matchReg.group(1) -# elif re.match('^\-\-EPCPassword=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-EPCPassword=(.+)$', myArgv, re.IGNORECASE) -# EPC.Password=matchReg.group(1) -# elif re.match('^\-\-EPCSourceCodePath=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-EPCSourceCodePath=(.+)$', myArgv, re.IGNORECASE) -# EPC.SourceCodePath=matchReg.group(1) -# elif re.match('^\-\-EPCType=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-EPCType=(.+)$', myArgv, re.IGNORECASE) -# if re.match('OAI', matchReg.group(1), re.IGNORECASE) or re.match('ltebox', matchReg.group(1), re.IGNORECASE) or re.match('OAI-Rel14-CUPS', matchReg.group(1), re.IGNORECASE) or re.match('OAI-Rel14-Docker', matchReg.group(1), re.IGNORECASE): -# EPC.Type=matchReg.group(1) -# else: -# sys.exit('Invalid EPC Type: ' + matchReg.group(1) + ' -- (should be OAI or ltebox or OAI-Rel14-CUPS or OAI-Rel14-Docker)') -# elif re.match('^\-\-EPCContainerPrefix=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-EPCContainerPrefix=(.+)$', myArgv, re.IGNORECASE) -# EPC.ContainerPrefix=matchReg.group(1) -# elif re.match('^\-\-ADBIPAddress=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-ADBIPAddress=(.+)$', myArgv, re.IGNORECASE) -# CiTestObj.ADBIPAddress = matchReg.group(1) -# elif re.match('^\-\-ADBUserName=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-ADBUserName=(.+)$', myArgv, re.IGNORECASE) -# CiTestObj.ADBUserName = matchReg.group(1) -# elif re.match('^\-\-ADBType=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-ADBType=(.+)$', myArgv, re.IGNORECASE) -# if re.match('centralized', matchReg.group(1), re.IGNORECASE) or re.match('distributed', matchReg.group(1), re.IGNORECASE): -# if re.match('distributed', matchReg.group(1), re.IGNORECASE): -# CiTestObj.ADBCentralized = False -# else: -# CiTestObj.ADBCentralized = True -# else: -# sys.exit('Invalid ADB Type: ' + matchReg.group(1) + ' -- (should be centralized or distributed)') -# elif re.match('^\-\-ADBPassword=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-ADBPassword=(.+)$', myArgv, re.IGNORECASE) -# CiTestObj.ADBPassword = matchReg.group(1) -# elif re.match('^\-\-XMLTestFile=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-XMLTestFile=(.+)$', myArgv, re.IGNORECASE) -# CiTestObj.testXMLfiles.append(matchReg.group(1)) -# HTML.testXMLfiles=matchReg.group(1) -# HTML.nbTestXMLfiles=HTML.nbTestXMLfiles+1 -# elif re.match('^\-\-UEIPAddress=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-UEIPAddress=(.+)$', myArgv, re.IGNORECASE) -# CiTestObj.UEIPAddress = matchReg.group(1) -# elif re.match('^\-\-UEUserName=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-UEUserName=(.+)$', myArgv, re.IGNORECASE) -# CiTestObj.UEUserName = matchReg.group(1) -# elif re.match('^\-\-UEPassword=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-UEPassword=(.+)$', myArgv, re.IGNORECASE) -# CiTestObj.UEPassword = matchReg.group(1) -# elif re.match('^\-\-UESourceCodePath=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-UESourceCodePath=(.+)$', myArgv, re.IGNORECASE) -# CiTestObj.UESourceCodePath = matchReg.group(1) -# elif re.match('^\-\-finalStatus=(.+)$', myArgv, re.IGNORECASE): -# matchReg = re.match('^\-\-finalStatus=(.+)$', myArgv, re.IGNORECASE) -# finalStatus = matchReg.group(1) -# if ((finalStatus == 'true') or (finalStatus == 'True')): -# CiTestObj.finalStatus = True -# else: -# HELP.GenericHelp(CONST.Version) -# sys.exit('Invalid Parameter: ' + myArgv) #----------------------------------------------------------- diff --git a/ci-scripts/ran.py b/ci-scripts/ran.py index 833e2784d1..39ecb00979 100644 --- a/ci-scripts/ran.py +++ b/ci-scripts/ran.py @@ -93,143 +93,6 @@ class RANManagement(): -#----------------------------------------------------------- -# Setters and Getters on Public members -#----------------------------------------------------------- - -# def SetHtmlObj(self, obj): -# self.htmlObj = obj -# def SetEpcObj(self, obj): -# self.epcObj = obj -# -# def SetflexranCtrlInstalled(self,fxrctin): -# self.flexranCtrlInstalled = fxrctin -# def GetflexranCtrlInstalled(self): -# return self.flexranCtrlInstalled -# def SetflexranCtrlStarted(self,fxrctst): -# self.flexranCtrlStarted = fxrctst -# def GetflexranCtrlStarted(self): -# return self.flexranCtrlStarted -# def SetpStatus(self, pSt): -# self.pStatus = pSt -# def SetranRepository(self, repository): -# self.ranRepository = repository -# def GetranRepository(self): -# return self.ranRepository -# def SetranBranch(self, branch): -# self.ranBranch = branch -# def GetranBranch(self): -# return self.ranBranch -# def SetranCommitID(self, commitid): -# self.ranCommitID = commitid -# def GetranCommitID(self): -# return self.ranCommitID -# def SeteNB_serverId(self, enbsrvid): -# self.eNB_serverId = enbsrvid -# def GeteNB_serverId(self): -# return self.eNB_serverId -# def SeteNBIPAddress(self, enbip): -# self.eNBIPAddress = enbip -# def GeteNBIPAddress(self): -# return self.eNBIPAddress -# def SeteNBUserName(self, enbusr): -# self.eNBUserName = enbusr -# def GeteNBUserName(self): -# return self.eNBUserName -# def SeteNBPassword(self, enbpw): -# self.eNBPassword = enbpw -# def GeteNBPassword(self): -# return self.eNBPassword -# def SeteNBSourceCodePath(self, enbcodepath): -# self.eNBSourceCodePath = enbcodepath -# def GeteNBSourceCodePath(self): -# return self.eNBSourceCodePath -# def SetranAllowMerge(self, merge): -# self.ranAllowMerge = merge -# def GetranAllowMerge(self): -# return self.ranAllowMerge -# def SetranTargetBranch(self, tbranch): -# self.ranTargetBranch = tbranch -# def GetranTargetBranch(self): -# return self.ranTargetBranch -# def SetBuild_eNB_args(self, enbbuildarg): -# self.Build_eNB_args = enbbuildarg -# def GetBuild_eNB_args(self): -# return self.Build_eNB_args -# def SetInitialize_eNB_args(self, initenbarg): -# self.Initialize_eNB_args = initenbarg -# def GetInitialize_eNB_args(self): -# return self.Initialize_eNB_args -# def SetbackgroundBuild(self, bkbuild): -# self.backgroundBuild = bkbuild -# def GetbackgroundBuild(self): -# return self.backgroundBuild -# def SetbackgroundBuildTestId(self, bkbuildid): -# self.backgroundBuildTestId = bkbuildid -# def GetbackgroundBuildTestId(self): -# return self.backgroundBuildTestId -# def SetBuild_eNB_forced_workspace_cleanup(self, fcdwspclean): -# self.Build_eNB_forced_workspace_cleanup = fcdwspclean -# def GetBuild_eNB_forced_workspace_cleanup(self): -# return self.Build_eNB_forced_workspace_cleanup -# def Setair_interface(self, airif): -# self.air_interface = airif -# def Getair_interface(self): -# return self.air_interface -# def SeteNB_instance(self, enbinst): -# self.eNB_instance = enbinst -# def GeteNB_instance(self): -# return self.eNB_instance -# -# def SeteNBLogFile(self, enblog, idx): -# self.eNBLogFiles[idx] = enblog -# def GeteNBLogFile(self, idx): -# return self.eNBLogFiles[idx] -# -# def GeteNBmbmsEnable(self, idx): -# return self.eNBmbmsEnables[idx] -# -# def SeteNB1IPAddress(self,enb1ip): -# self.eNB1IPAddress = enb1ip -# def GeteNB1IPAddress(self): -# return self.eNB1IPAddress -# def SeteNB1UserName(self, enb1usr): -# self.eNB1UserName = enb1usr -# def GeteNB1UserName(self): -# return self.eNB1UserName -# def SeteNB1Password(self, enb1pw): -# self.eNB1Password = enb1pw -# def GeteNB1Password(self): -# return self.eNB1Password -# def SeteNB1SourceCodePath(self, enb1codepath): -# self.eNB1SourceCodePath = enb1codepath -# def GeteNB1SourceCodePath(self): -# return self.eNB1SourceCodePath -# -# def SeteNB2IPAddress(self, enb2ip): -# self.eNB2IPAddress = enb2ip -# def GeteNB2IPAddress(self): -# return self.eNB2IPAddress -# def SeteNB2UserName(self, enb2usr): -# self.eNB2UserName = enb2usr -# def GeteNB2UserName(self): -# return self.eNB2UserName -# def SeteNB2Password(self, enb2pw): -# self.eNB2Password = enb2pw -# def GeteNB2Password(self): -# return self.eNB2Password -# def SeteNB2SourceCodePath(self, enb2codepath): -# self.eNB2SourceCodePath = enb2codepath -# def GeteNB2SourceCodePath(self): -# return self.eNB2SourceCodePath -# -# def SetprematureExit(self, premex): -# self.prematureExit = premex -# def GetprematureExit(self): -# return self.prematureExit - - - #----------------------------------------------------------- # RAN management functions #----------------------------------------------------------- From 71c66ec58320a9124b5ac01f6a71f1aca88defd1 Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Tue, 28 Jul 2020 17:08:09 +0200 Subject: [PATCH 531/553] CI: fix HTML tab name Signed-off-by: Raphael Defosseux --- ci-scripts/args_parse.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ci-scripts/args_parse.py b/ci-scripts/args_parse.py index b51fbc500d..1249f52172 100644 --- a/ci-scripts/args_parse.py +++ b/ci-scripts/args_parse.py @@ -203,7 +203,7 @@ def ArgsParse(argvs,CiTestObj,RAN,HTML,EPC,ldpc,HELP): elif re.match('^\-\-XMLTestFile=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-XMLTestFile=(.+)$', myArgv, re.IGNORECASE) CiTestObj.testXMLfiles.append(matchReg.group(1)) - HTML.testXMLfiles=matchReg.group(1) + HTML.testXMLfiles.append(matchReg.group(1)) HTML.nbTestXMLfiles=HTML.nbTestXMLfiles+1 elif re.match('^\-\-UEIPAddress=(.+)$', myArgv, re.IGNORECASE): matchReg = re.match('^\-\-UEIPAddress=(.+)$', myArgv, re.IGNORECASE) From f61f9520dba252eae01b7aab690fcf8fe797c28f Mon Sep 17 00:00:00 2001 From: frtabu Date: Tue, 28 Jul 2020 20:08:48 +0200 Subject: [PATCH 532/553] implement queued commands in telnet server --- common/utils/telnetsrv/telnetsrv.c | 21 ++++++++- common/utils/telnetsrv/telnetsrv.h | 16 +++++-- openair1/SIMULATION/TOOLS/random_channel.c | 55 ++++++++++++++-------- targets/ARCH/rfsimulator/simulator.c | 6 ++- 4 files changed, 72 insertions(+), 26 deletions(-) diff --git a/common/utils/telnetsrv/telnetsrv.c b/common/utils/telnetsrv/telnetsrv.c index 06a5d350c7..831d6032c8 100644 --- a/common/utils/telnetsrv/telnetsrv.c +++ b/common/utils/telnetsrv/telnetsrv.c @@ -53,6 +53,7 @@ #include #include "common/utils/load_module_shlib.h" #include "common/config/config_userapi.h" +#include "common/utils/threadPool/thread-pool.h" #include "executables/softmodem-common.h" #include @@ -512,7 +513,17 @@ int process_command(char *buf) { } else { for (k=0 ; telnetparams.CmdParsers[i].cmd[k].cmdfunc != NULL ; k++) { if (strncasecmp(cmd, telnetparams.CmdParsers[i].cmd[k].cmdname,sizeof(telnetparams.CmdParsers[i].cmd[k].cmdname)) == 0) { - telnetparams.CmdParsers[i].cmd[k].cmdfunc(cmdb, telnetparams.telnetdbg, client_printf); + if (telnetparams.CmdParsers[i].cmd[k].qptr != NULL) { + notifiedFIFO_elt_t *msg =newNotifiedFIFO_elt(sizeof(telnetsrv_qmsg_t),0,NULL,NULL); + telnetsrv_qmsg_t *cmddata=NotifiedFifoData(msg); + cmddata->cmdfunc=telnetparams.CmdParsers[i].cmd[k].cmdfunc; + cmddata->prnt=client_printf; + cmddata->debug=telnetparams.telnetdbg; + cmddata->cmdbuff=strdup(cmdb); + pushNotifiedFIFO(telnetparams.CmdParsers[i].cmd[k].qptr, msg); + } else { + telnetparams.CmdParsers[i].cmd[k].cmdfunc(cmdb, telnetparams.telnetdbg, client_printf); + } rt= CMDSTATUS_FOUND; } } /* for k */ @@ -758,6 +769,7 @@ int telnetsrv_autoinit(void) { */ int add_telnetcmd(char *modulename, telnetshell_vardef_t *var, telnetshell_cmddef_t *cmd) { int i; + notifiedFIFO_t *afifo=NULL; if( modulename == NULL || var == NULL || cmd == NULL) { fprintf(stderr,"[TELNETSRV] Telnet server, add_telnetcmd: invalid parameters\n"); @@ -769,6 +781,13 @@ int add_telnetcmd(char *modulename, telnetshell_vardef_t *var, telnetshell_cmdde strncpy(telnetparams.CmdParsers[i].module,modulename,sizeof(telnetparams.CmdParsers[i].module)-1); telnetparams.CmdParsers[i].cmd = cmd; telnetparams.CmdParsers[i].var = var; + if (cmd->cmdflags & TELNETSRV_CMDFLAG_PUSHINTPOOLQ) { + if (afifo == NULL) { + afifo = malloc(sizeof(notifiedFIFO_t)); + initNotifiedFIFO(afifo); + } + cmd->qptr = afifo; + } printf("[TELNETSRV] Telnet server: module %i = %s added to shell\n", i,telnetparams.CmdParsers[i].module); break; diff --git a/common/utils/telnetsrv/telnetsrv.h b/common/utils/telnetsrv/telnetsrv.h index debb9f02ec..32ec2b9666 100644 --- a/common/utils/telnetsrv/telnetsrv.h +++ b/common/utils/telnetsrv/telnetsrv.h @@ -54,12 +54,24 @@ typedef void(*telnet_printfunc_t)(const char* format, ...); typedef int(*cmdfunc_t)(char*, int, telnet_printfunc_t prnt); +#define TELNETSRV_CMDFLAG_PUSHINTPOOLQ (1<<0) // ask the telnet server to push the command in a thread pool queue typedef struct cmddef { char cmdname[TELNET_CMD_MAXSIZE]; char helpstr[TELNET_HELPSTR_SIZE]; cmdfunc_t cmdfunc; + unsigned int cmdflags; + void *qptr; } telnetshell_cmddef_t; +/*----------------------------------------------------------------------------*/ +/* structure used to send a command via a message queue to enable */ +/* executing a command in a thread different from the telnet server thread */ +typedef struct telnetsrv_qmsg { + cmdfunc_t cmdfunc; + telnet_printfunc_t prnt; + int debug; + char *cmdbuff; +} telnetsrv_qmsg_t; /*----------------------------------------------------------------------------*/ /*structure to be used when adding a module to the telnet server */ /* This is the first parameter of the add_telnetcmd function, which can be used */ @@ -111,9 +123,6 @@ typedef struct { } telnetsrv_params_t; - -typedef int(*addcmdfunc_t)(char*, telnetshell_vardef_t*, telnetshell_cmddef_t*); - typedef void(*settelnetmodule_t)(char *name, void *ptr); /*-------------------------------------------------------------------------------------------*/ @@ -133,6 +142,7 @@ VT escape sequence definition, for smarter display.... /*---------------------------------------------------------------------------------------------*/ #define TELNET_ADDCMD_FNAME "add_telnetcmd" +#define TELNET_ADDQUEUEDCMD_FNAME "add_telnetqueuedcmd" typedef int(*add_telnetcmd_func_t)(char *, telnetshell_vardef_t *, telnetshell_cmddef_t *); #ifdef TELNETSERVERCODE int add_telnetcmd(char *modulename, telnetshell_vardef_t *var, telnetshell_cmddef_t *cmd); diff --git a/openair1/SIMULATION/TOOLS/random_channel.c b/openair1/SIMULATION/TOOLS/random_channel.c index 0cc0ba5501..af266a6600 100644 --- a/openair1/SIMULATION/TOOLS/random_channel.c +++ b/openair1/SIMULATION/TOOLS/random_channel.c @@ -46,7 +46,9 @@ static mapping channelmod_names[] = { static int channelmod_show_cmd(char *buff, int debug, telnet_printfunc_t prnt); static int channelmod_modify_cmd(char *buff, int debug, telnet_printfunc_t prnt); +static int channelmod_print_help(char *buff, int debug, telnet_printfunc_t prnt); static telnetshell_cmddef_t channelmod_cmdarray[] = { + {"help","",channelmod_print_help}, {"show","",channelmod_show_cmd}, {"modify"," ",channelmod_modify_cmd}, {"","",NULL}, @@ -286,7 +288,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx, channel_desc_t *chan_desc = (channel_desc_t *)malloc(sizeof(channel_desc_t)); for(int i=0; ichan_idx=i; break; } @@ -438,7 +440,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx, } break; - + case EPA: chan_desc->nb_taps = 7; chan_desc->Td = .410; @@ -1504,11 +1506,18 @@ double N_RB2channel_bandwidth(uint16_t N_RB) { LOG_E(PHY,"Unknown N_PRB\n"); return(-1); } - return(channel_bandwidth); -} -static void display_channelmodel_help( telnet_printfunc_t prnt) { +} + +static int channelmod_print_help(char *buff, int debug, telnet_printfunc_t prnt ) { + prnt("channelmod commands can be used to display or modify channel models parameters\n"); + prnt("channelmod show predef: display predefined model algorithms available in oai\n"); + prnt("channelmod show current: display the currently used models in the running executable\n"); + prnt("channelmod modify : set the specified parameters in a current model to the given value\n"); + prnt(" specifies the model, the show current model command can be used to list the current models indexes\n"); + prnt(" can be one of \"riceanf\", \"aoa\", \"randaoa\", \"ploss\", \"offset\", \"forgetf\"\n"); + return CMDSTATUS_FOUND; } @@ -1522,10 +1531,10 @@ static void display_channelmodel(channel_desc_t *cd,int debug, telnet_printfunc_ cd->ip, cd->nb_paths); for (int i=0; inb_taps ; i++) { prnt("taps: %i lin. ampli. : %lf delay: %lf \n",i,cd->amps[i], cd->delays[i]); - } + } } - - + + static int channelmod_show_cmd(char *buff, int debug, telnet_printfunc_t prnt) { char *subcmd=NULL; int s = sscanf(buff,"%ms\n",&subcmd); @@ -1543,14 +1552,14 @@ static int channelmod_show_cmd(char *buff, int debug, telnet_printfunc_t prnt) { } } } else { - display_channelmodel_help(prnt); + channelmod_print_help(buff, debug, prnt); } free(subcmd); } return CMDSTATUS_FOUND; } - + static int channelmod_modify_cmd(char *buff, int debug, telnet_printfunc_t prnt) { char *param=NULL, *value=NULL; @@ -1569,15 +1578,21 @@ static int channelmod_modify_cmd(char *buff, int debug, telnet_printfunc_t prnt) if ( strcmp(param,"riceanf") == 0) { double dbl = atof(value); if (dbl <0 || dbl > 1) - prnt("ricean factor range: 0 to 1, %lf is outof range\n",dbl); + prnt("ERROR: ricean factor range: 0 to 1, %lf is outof range\n",dbl); else defined_channels[cd_id]->ricean_factor=dbl; } else if ( strcmp(param,"aoa") == 0) { double dbl = atof(value); if (dbl <0 || dbl >6.28) - prnt("angle of arrival range: 0 to 2*Pi, %lf is outof range\n",dbl); + prnt("ERROR: angle of arrival range: 0 to 2*Pi, %lf is outof range\n",dbl); else defined_channels[cd_id]->aoa=dbl; + } else if ( strcmp(param,"randaoa") == 0) { + int i = atoi(value); + if (i!=0 && i!=1) + prnt("ERROR: randaoa is a boolean, must be 0 or 1\n"); + else + defined_channels[cd_id]->random_aoa=i; } else if ( strcmp(param,"ploss") == 0) { double dbl = atof(value); defined_channels[cd_id]->path_loss_dB=dbl; @@ -1587,21 +1602,21 @@ static int channelmod_modify_cmd(char *buff, int debug, telnet_printfunc_t prnt) } else if ( strcmp(param,"forgetf") == 0) { double dbl = atof(value); if (dbl <0 || dbl > 1) - prnt("forgetting factor range: 0 to 1 (disable variation), %lf is outof range\n",dbl); + prnt("ERROR: forgetting factor range: 0 to 1 (disable variation), %lf is outof range\n",dbl); else defined_channels[cd_id]->forgetting_factor=dbl; } else { - + prnt("ERROR: %s, unknown channel parameter\n",param); + return CMDSTATUS_FOUND; } - display_channelmodel(defined_channels[cd_id],debug,prnt); - free(param); + display_channelmodel(defined_channels[cd_id],debug,prnt); + free(param); free(value); - + random_channel(defined_channels[cd_id],false); } - - return CMDSTATUS_FOUND; + return CMDSTATUS_FOUND; } - + int modelid_fromname(char *modelname) { int modelid=map_str_to_int(channelmod_names,modelname); AssertFatal(modelid>0, diff --git a/targets/ARCH/rfsimulator/simulator.c b/targets/ARCH/rfsimulator/simulator.c index ff53ca8c46..4b0c0a35e4 100644 --- a/targets/ARCH/rfsimulator/simulator.c +++ b/targets/ARCH/rfsimulator/simulator.c @@ -82,7 +82,8 @@ extern RAN_CONTEXT_t RC; {"IQfile", "\n", 0, strptr:&(saveF), defstrval:"/tmp/rfsimulator.iqs",TYPE_STRING, 0 },\ {"modelname", "\n", 0, strptr:&(modelname), defstrval:"AWGN", TYPE_STRING, 0 },\ {"ploss", "\n", 0, dblptr:&(rfsimulator->chan_pathloss), defdblval:0, TYPE_DOUBLE, 0 },\ - {"forgetfact", "\n", 0, dblptr:&(rfsimulator->chan_forgetfact), defdblval:0, TYPE_DOUBLE, 0 }\ + {"forgetfact", "\n", 0, dblptr:&(rfsimulator->chan_forgetfact), defdblval:0, TYPE_DOUBLE, 0 },\ + {"offset", "\n", 0, iptr:&(rfsimulator->chan_offset), defintval:0, TYPE_INT, 0 }\ }; pthread_mutex_t Sockmutex; @@ -118,6 +119,7 @@ typedef struct { int channelmod; double chan_pathloss; double chan_forgetfact; + int chan_offset; } rfsimulator_state_t; @@ -166,7 +168,7 @@ void allocCirBuf(rfsimulator_state_t *bridge, int sock) { bridge->sample_rate, bridge->tx_bw, bridge->chan_forgetfact, // forgetting_factor - 0, // maybe used for TA + bridge->chan_offset, // maybe used for TA bridge->chan_pathloss); // path_loss in dB random_channel(ptr->channel_model,false); } From f5d1dbb731f4f260a1a8dcdc0ca8d4051c054cab Mon Sep 17 00:00:00 2001 From: frtabu Date: Wed, 29 Jul 2020 01:34:52 +0200 Subject: [PATCH 533/553] add telnet command to rfsimulator --- common/utils/telnetsrv/telnetsrv.c | 10 ++++++ common/utils/telnetsrv/telnetsrv.h | 3 +- targets/ARCH/rfsimulator/simulator.c | 54 ++++++++++++++++++++++++++-- 3 files changed, 64 insertions(+), 3 deletions(-) diff --git a/common/utils/telnetsrv/telnetsrv.c b/common/utils/telnetsrv/telnetsrv.c index 831d6032c8..1a96a50b21 100644 --- a/common/utils/telnetsrv/telnetsrv.c +++ b/common/utils/telnetsrv/telnetsrv.c @@ -684,6 +684,16 @@ void run_telnetsrv(void) { return; } +void poll_telnetcmdq(void *qid) { + notifiedFIFO_elt_t *msg = pollNotifiedFIFO((notifiedFIFO_t *)qid); + + if (msg != NULL) { + telnetsrv_qmsg_t *msgdata=NotifiedFifoData(msg); + msgdata->cmdfunc(msgdata->cmdbuff,msgdata->debug,msgdata->prnt); + free(msgdata->cmdbuff); + delNotifiedFIFO_elt(msg); + } +} /*------------------------------------------------------------------------------------------------*/ /* load the commands delivered with the telnet server * diff --git a/common/utils/telnetsrv/telnetsrv.h b/common/utils/telnetsrv/telnetsrv.h index 32ec2b9666..4aceb64079 100644 --- a/common/utils/telnetsrv/telnetsrv.h +++ b/common/utils/telnetsrv/telnetsrv.h @@ -142,8 +142,9 @@ VT escape sequence definition, for smarter display.... /*---------------------------------------------------------------------------------------------*/ #define TELNET_ADDCMD_FNAME "add_telnetcmd" -#define TELNET_ADDQUEUEDCMD_FNAME "add_telnetqueuedcmd" +#define TELNET_POLLCMDQ_FNAME "poll_telnetcmdq" typedef int(*add_telnetcmd_func_t)(char *, telnetshell_vardef_t *, telnetshell_cmddef_t *); +typedef void(*poll_telnetcmdq_func_t)(void *qid); #ifdef TELNETSERVERCODE int add_telnetcmd(char *modulename, telnetshell_vardef_t *var, telnetshell_cmddef_t *cmd); void set_sched(pthread_t tid, int pid,int priority); diff --git a/targets/ARCH/rfsimulator/simulator.c b/targets/ARCH/rfsimulator/simulator.c index 4b0c0a35e4..9ad05f3a88 100644 --- a/targets/ARCH/rfsimulator/simulator.c +++ b/targets/ARCH/rfsimulator/simulator.c @@ -44,6 +44,7 @@ #include #include #include +#include #include #include "common_lib.h" #include @@ -86,6 +87,17 @@ extern RAN_CONTEXT_t RC; {"offset", "\n", 0, iptr:&(rfsimulator->chan_offset), defintval:0, TYPE_INT, 0 }\ }; + + +static int rfsimu_setchanmod_cmd(char *buff, int debug, telnet_printfunc_t prnt); +static telnetshell_cmddef_t rfsimu_cmdarray[] = { + {"setmodel","",rfsimu_setchanmod_cmd,TELNETSRV_CMDFLAG_PUSHINTPOOLQ}, + {"","",NULL}, +}; + +static telnetshell_vardef_t rfsimu_vardef[] = { + {"",0,NULL} +}; pthread_mutex_t Sockmutex; typedef struct complex16 sample_t; // 2*16 bits complex number @@ -120,6 +132,8 @@ typedef struct { double chan_pathloss; double chan_forgetfact; int chan_offset; + void *telnetcmd_qid; + poll_telnetcmdq_func_t poll_telnetcmdq; } rfsimulator_state_t; @@ -157,7 +171,8 @@ void allocCirBuf(rfsimulator_state_t *bridge, int sock) { if (!init_done) { uint64_t rand; FILE *h=fopen("/dev/random","r"); - fread(&rand,sizeof(rand),1,h); + int st=fread(&rand,sizeof(rand),1,h); + AssertFatal(st != -1, "Error reading random int %s\n",strerror(errno)); fclose(h); randominit(rand); tableNor(rand); @@ -296,6 +311,28 @@ void rfsimulator_readconfig(rfsimulator_state_t *rfsimulator) { rfsimulator->typeStamp = UE_MAGICDL_FDD; } +static int rfsimu_setchanmod_cmd(char *buff, int debug, telnet_printfunc_t prnt) { + char *modelname=NULL; + int s = sscanf(buff,"%ms\n",&modelname); + int channelmod=modelid_fromname(modelname); + for (int i=0; ibuf[i].conn_sock > 0) { + channel_desc_t *cm = rfsimulator->buf[i].channel_model; + + rfsimulator->buf[i].channel_model=new_channel_desc_scm(cm->nb_tx,cm->nb_rx, + channelmod, + cm->sampling_rate, + cm->channel_bandwidth, + cm->forgetting_factor, // forgetting_factor + cm->channel_offset, // maybe used for TA + cm-> path_loss_dB); // path_loss in dB + free_channel_desc_scm(cm); + random_channel(ptr->channel_model,false); + } */ + } + return CMDSTATUS_FOUND; +} + int server_start(openair0_device *device) { rfsimulator_state_t *t = (rfsimulator_state_t *) device->priv; t->typeStamp=ENB_MAGICDL_FDD; @@ -646,7 +683,7 @@ int rfsimulator_read(openair0_device *device, openair0_timestamp *ptimestamp, vo // it seems legacy behavior is: never in UL, each frame in DL if (reGenerateChannel) random_channel(ptr->channel_model,0); - + t->poll_telnetcmdq(t->telnetcmd_qid); for (int a=0; achannel_model != NULL ) // apply a channel model rxAddInput( ptr->circularBuf, (struct complex16 *) samplesVoid[a], @@ -740,5 +777,18 @@ int device_init(openair0_device *device, openair0_config_t *openair0_cfg) { rfsimulator->tx_bw=openair0_cfg->tx_bw; //randominit(0); set_taus_seed(0); + /* look for telnet server, if it is loaded, add the channel modeling commands to it */ + add_telnetcmd_func_t addcmd = (add_telnetcmd_func_t)get_shlibmodule_fptr("telnetsrv", TELNET_ADDCMD_FNAME); + + if (addcmd != NULL) { + rfsimulator->poll_telnetcmdq = (poll_telnetcmdq_func_t)get_shlibmodule_fptr("telnetsrv", TELNET_POLLCMDQ_FNAME); + addcmd("rfsimu",rfsimu_vardef,rfsimu_cmdarray); + for(int i=0; rfsimu_cmdarray[i].cmdfunc != NULL; i++) { + if ( rfsimu_cmdarray[i].qptr != NULL) { + rfsimulator->telnetcmd_qid = rfsimu_cmdarray[i].qptr; + break; + } + } + } return 0; } From 9c2696e5e2883788159e6c32de07d7a50622192b Mon Sep 17 00:00:00 2001 From: Cedric Roux Date: Tue, 28 Jul 2020 16:39:46 +0200 Subject: [PATCH 534/553] fix to have the sony 5g connect in NSA mode c_SRS was 61, which does not fit for 106 PRBs as it seems. Value 0 works. Maybe not the right thing to do though (see 38.211 6.4.1.4.3, table 6.4.1.4.3-1). Also it seems necessary to pass desired LTE/NR bands when requesting LTE UE capabilities. Today this is hardcoded, to be done better at some point. We should get the bands from the eNB configuration and the eNB/gNB X2 exchanges. --- openair2/RRC/LTE/MESSAGES/asn1_msg.c | 46 +++++++++++++++++++++++++--- openair2/RRC/NR/rrc_gNB_reconfig.c | 2 +- 2 files changed, 42 insertions(+), 6 deletions(-) diff --git a/openair2/RRC/LTE/MESSAGES/asn1_msg.c b/openair2/RRC/LTE/MESSAGES/asn1_msg.c index 9ede543003..c537c536b2 100644 --- a/openair2/RRC/LTE/MESSAGES/asn1_msg.c +++ b/openair2/RRC/LTE/MESSAGES/asn1_msg.c @@ -3198,6 +3198,42 @@ uint8_t do_UECapabilityEnquiry( const protocol_ctxt_t *const ctxt_pP, ASN_SEQUENCE_ADD(&dl_dcch_msg.message.choice.c1.choice.ueCapabilityEnquiry.criticalExtensions.choice.c1.choice.ueCapabilityEnquiry_r8.ue_CapabilityRequest.list, &rat); + /* request NR configuration */ + LTE_UECapabilityEnquiry_r8_IEs_t *r8 = &dl_dcch_msg.message.choice.c1.choice.ueCapabilityEnquiry.criticalExtensions.choice.c1.choice.ueCapabilityEnquiry_r8; + LTE_UECapabilityEnquiry_v8a0_IEs_t r8_a0; + LTE_UECapabilityEnquiry_v1180_IEs_t r11_80; + LTE_UECapabilityEnquiry_v1310_IEs_t r13_10; + LTE_UECapabilityEnquiry_v1430_IEs_t r14_30; + LTE_UECapabilityEnquiry_v1510_IEs_t r15_10; + + memset(&r8_a0, 0, sizeof(r8_a0)); + memset(&r11_80, 0, sizeof(r11_80)); + memset(&r13_10, 0, sizeof(r13_10)); + memset(&r14_30, 0, sizeof(r14_30)); + memset(&r15_10, 0, sizeof(r15_10)); + + r8->nonCriticalExtension = &r8_a0; + r8_a0.nonCriticalExtension = &r11_80; + r11_80.nonCriticalExtension = &r13_10; + r13_10.nonCriticalExtension = &r14_30; + r14_30.nonCriticalExtension = &r15_10; + + /* TODO: no hardcoded values here */ + + OCTET_STRING_t req_freq; + unsigned char req_freq_buf[5] = { 0x00, 0x20, 0x1a, 0x02, 0x68 }; // bands 7 & nr78 + //unsigned char req_freq_buf[5] = { 0x00, 0x20, 0x1a, 0x08, 0x18 }; // bands 7 & nr260 + + //unsigned char req_freq_buf[13] = { 0x00, 0xc0, 0x18, 0x01, 0x01, 0x30, 0x4b, 0x04, 0x0e, 0x08, 0x24, 0x04, 0xd0 }; +// unsigned char req_freq_buf[21] = { +//0x01, 0x60, 0x18, 0x05, 0x80, 0xc0, 0x04, 0x04, 0xc1, 0x2c, 0x10, 0x08, 0x20, 0x30, 0x40, 0xe0, 0x82, 0x40, 0x28, 0x80, 0x9a +// }; + + req_freq.buf = req_freq_buf; + req_freq.size = 5; +// req_freq.size = 21; + + r15_10.requestedFreqBandsNR_MRDC_r15 = &req_freq; if ( LOG_DEBUGFLAG(DEBUG_ASN1) ) { xer_fprint(stdout, &asn_DEF_LTE_DL_DCCH_Message, (void *)&dl_dcch_msg); } @@ -3276,17 +3312,17 @@ uint8_t do_NR_UECapabilityEnquiry( const protocol_ctxt_t *const ctxt_pP, /* TODO: no hardcoded values here */ OCTET_STRING_t req_freq; - //unsigned char req_freq_buf[5] = { 0x00, 0x20, 0x1a, 0x02, 0x68 }; // bands 7 & nr78 + unsigned char req_freq_buf[5] = { 0x00, 0x20, 0x1a, 0x02, 0x68 }; // bands 7 & nr78 //unsigned char req_freq_buf[5] = { 0x00, 0x20, 0x1a, 0x08, 0x18 }; // bands 7 & nr260 //unsigned char req_freq_buf[13] = { 0x00, 0xc0, 0x18, 0x01, 0x01, 0x30, 0x4b, 0x04, 0x0e, 0x08, 0x24, 0x04, 0xd0 }; - unsigned char req_freq_buf[21] = { -0x01, 0x60, 0x18, 0x05, 0x80, 0xc0, 0x04, 0x04, 0xc1, 0x2c, 0x10, 0x08, 0x20, 0x30, 0x40, 0xe0, 0x82, 0x40, 0x28, 0x80, 0x9a - }; +// unsigned char req_freq_buf[21] = { +//0x01, 0x60, 0x18, 0x05, 0x80, 0xc0, 0x04, 0x04, 0xc1, 0x2c, 0x10, 0x08, 0x20, 0x30, 0x40, 0xe0, 0x82, 0x40, 0x28, 0x80, 0x9a +// }; req_freq.buf = req_freq_buf; req_freq.size = 5; - req_freq.size = 21; +// req_freq.size = 21; r15_10.requestedFreqBandsNR_MRDC_r15 = &req_freq; diff --git a/openair2/RRC/NR/rrc_gNB_reconfig.c b/openair2/RRC/NR/rrc_gNB_reconfig.c index a7aa38dfe3..6ea6f3b3b3 100644 --- a/openair2/RRC/NR/rrc_gNB_reconfig.c +++ b/openair2/RRC/NR/rrc_gNB_reconfig.c @@ -917,7 +917,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco srs_res0->resourceMapping.repetitionFactor=NR_SRS_Resource__resourceMapping__repetitionFactor_n1; srs_res0->freqDomainPosition=0; srs_res0->freqDomainShift=0; - srs_res0->freqHopping.c_SRS = 61; + srs_res0->freqHopping.c_SRS = 0; srs_res0->freqHopping.b_SRS=0; srs_res0->freqHopping.b_hop=0; srs_res0->groupOrSequenceHopping=NR_SRS_Resource__groupOrSequenceHopping_neither; From d4bd2cdc63e9a6c28c29f9a1b7f1cb0c6eeab4be Mon Sep 17 00:00:00 2001 From: frtabu Date: Wed, 29 Jul 2020 20:27:04 +0200 Subject: [PATCH 535/553] implement modifying channel model algo while running, complete function freeing a model --- common/utils/telnetsrv/telnetsrv.c | 14 ++-- common/utils/telnetsrv/telnetsrv.h | 5 +- openair1/SIMULATION/TOOLS/random_channel.c | 98 ++++++++++++++-------- openair1/SIMULATION/TOOLS/sim.h | 27 +++++- targets/ARCH/rfsimulator/simulator.c | 53 +++++++----- 5 files changed, 135 insertions(+), 62 deletions(-) diff --git a/common/utils/telnetsrv/telnetsrv.c b/common/utils/telnetsrv/telnetsrv.c index 1a96a50b21..03f7af99bc 100644 --- a/common/utils/telnetsrv/telnetsrv.c +++ b/common/utils/telnetsrv/telnetsrv.c @@ -508,7 +508,7 @@ int process_command(char *buf) { } rt= CMDSTATUS_FOUND; - } else if (strncasecmp(cmd,"get",3) == 0 || strncasecmp(cmd,"set",3) == 0) { + } else if (strcasecmp(cmd,"get") == 0 || strcasecmp(cmd,"set") == 0) { rt= setgetvar(i,cmd[0],cmdb); } else { for (k=0 ; telnetparams.CmdParsers[i].cmd[k].cmdfunc != NULL ; k++) { @@ -516,7 +516,7 @@ int process_command(char *buf) { if (telnetparams.CmdParsers[i].cmd[k].qptr != NULL) { notifiedFIFO_elt_t *msg =newNotifiedFIFO_elt(sizeof(telnetsrv_qmsg_t),0,NULL,NULL); telnetsrv_qmsg_t *cmddata=NotifiedFifoData(msg); - cmddata->cmdfunc=telnetparams.CmdParsers[i].cmd[k].cmdfunc; + cmddata->cmdfunc=(qcmdfunc_t)telnetparams.CmdParsers[i].cmd[k].cmdfunc; cmddata->prnt=client_printf; cmddata->debug=telnetparams.telnetdbg; cmddata->cmdbuff=strdup(cmdb); @@ -684,12 +684,12 @@ void run_telnetsrv(void) { return; } -void poll_telnetcmdq(void *qid) { +void poll_telnetcmdq(void *qid, void *arg) { notifiedFIFO_elt_t *msg = pollNotifiedFIFO((notifiedFIFO_t *)qid); if (msg != NULL) { telnetsrv_qmsg_t *msgdata=NotifiedFifoData(msg); - msgdata->cmdfunc(msgdata->cmdbuff,msgdata->debug,msgdata->prnt); + msgdata->cmdfunc(msgdata->cmdbuff,msgdata->debug,msgdata->prnt,arg); free(msgdata->cmdbuff); delNotifiedFIFO_elt(msg); } @@ -826,8 +826,10 @@ int telnetsrv_checkbuildver(char *mainexec_buildversion, char **shlib_buildvers } int telnetsrv_getfarray(loader_shlibfunc_t **farray) { - *farray=malloc(sizeof(loader_shlibfunc_t)); + *farray=malloc(sizeof(loader_shlibfunc_t)*2); (*farray)[0].fname=TELNET_ADDCMD_FNAME; (*farray)[0].fptr=(int (*)(void) )add_telnetcmd; - return 1; + (*farray)[1].fname=TELNET_POLLCMDQ_FNAME; + (*farray)[1].fptr=(int (*)(void) )poll_telnetcmdq; + return ( 2); } diff --git a/common/utils/telnetsrv/telnetsrv.h b/common/utils/telnetsrv/telnetsrv.h index 4aceb64079..b66641d5c8 100644 --- a/common/utils/telnetsrv/telnetsrv.h +++ b/common/utils/telnetsrv/telnetsrv.h @@ -53,6 +53,7 @@ /* to add a set of new command to the telnet server shell */ typedef void(*telnet_printfunc_t)(const char* format, ...); typedef int(*cmdfunc_t)(char*, int, telnet_printfunc_t prnt); +typedef int(*qcmdfunc_t)(char*, int, telnet_printfunc_t prnt,void *arg); #define TELNETSRV_CMDFLAG_PUSHINTPOOLQ (1<<0) // ask the telnet server to push the command in a thread pool queue typedef struct cmddef { @@ -67,7 +68,7 @@ typedef struct cmddef { /* structure used to send a command via a message queue to enable */ /* executing a command in a thread different from the telnet server thread */ typedef struct telnetsrv_qmsg { - cmdfunc_t cmdfunc; + qcmdfunc_t cmdfunc; telnet_printfunc_t prnt; int debug; char *cmdbuff; @@ -144,7 +145,7 @@ VT escape sequence definition, for smarter display.... #define TELNET_ADDCMD_FNAME "add_telnetcmd" #define TELNET_POLLCMDQ_FNAME "poll_telnetcmdq" typedef int(*add_telnetcmd_func_t)(char *, telnetshell_vardef_t *, telnetshell_cmddef_t *); -typedef void(*poll_telnetcmdq_func_t)(void *qid); +typedef void(*poll_telnetcmdq_func_t)(void *qid,void *arg); #ifdef TELNETSERVERCODE int add_telnetcmd(char *modulename, telnetshell_vardef_t *var, telnetshell_cmddef_t *cmd); void set_sched(pthread_t tid, int pid,int priority); diff --git a/openair1/SIMULATION/TOOLS/random_channel.c b/openair1/SIMULATION/TOOLS/random_channel.c index af266a6600..f97b9dfb78 100644 --- a/openair1/SIMULATION/TOOLS/random_channel.c +++ b/openair1/SIMULATION/TOOLS/random_channel.c @@ -68,7 +68,7 @@ void fill_channel_desc(channel_desc_t *chan_desc, uint8_t nb_taps, uint8_t channel_length, double *amps, - double *delays, + double *delays, struct complex **R_sqrt, double Td, double sampling_rate, @@ -93,6 +93,7 @@ void fill_channel_desc(channel_desc_t *chan_desc, if (delays==NULL) { chan_desc->delays = (double *) malloc(nb_taps*sizeof(double)); + chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_DELAY ; delta_tau = Td/nb_taps; for (i=0; iR_sqrt = (struct complex **) calloc(nb_taps,sizeof(struct complex *)); - + chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_RSQRT_NTAPS ; for (i = 0; iR_sqrt[i] = (struct complex *) calloc(nb_tx*nb_rx*nb_tx*nb_rx,sizeof(struct complex)); - + chan_desc->R_sqrt[i] = (struct complex *) calloc(nb_tx*nb_rx*nb_tx*nb_rx,sizeof(struct complex)); for (j = 0; jR_sqrt[i][j].x = 1.0; chan_desc->R_sqrt[i][j].y = 0.0; @@ -145,7 +145,7 @@ void fill_channel_desc(channel_desc_t *chan_desc, } } else { chan_desc->R_sqrt = (struct complex **) calloc(nb_taps,sizeof(struct complex *)); - + for (i = 0; iR_sqrt[i] = (struct complex*) calloc(nb_tx*nb_rx*nb_tx*nb_rx,sizeof(struct complex)); //chan_desc->R_sqrt = (struct complex*)&R_sqrt[i][0]; @@ -175,7 +175,7 @@ void fill_channel_desc(channel_desc_t *chan_desc, double mbsfn_delays[] = {0,.03,.15,.31,.37,1.09,12.490,12.52,12.64,12.80,12.86,13.58,27.49,27.52,27.64,27.80,27.86,28.58}; double mbsfn_amps_dB[] = {0,-1.5,-1.4,-3.6,-0.6,-7.0,-10,-11.5,-11.4,-13.6,-10.6,-17.0,-20,-21.5,-21.4,-23.6,-20.6,-27}; -double scm_c_delays[] = {0, 0.0125, 0.0250, 0.3625, 0.3750, 0.3875, 0.2500, 0.2625, 0.2750, 1.0375, 1.0500, 1.0625, 2.7250, 2.7375, 2.7500, 4.6000, 4.6125, 4.6250}; +double scm_c_delays[] = {0, 0.0125, 0.0250, 0.3625, 0.3750, 0.3875, 0.2500, 0.2625, 0.2750, 1.0375, 1.0500, 1.0625, 2.7250, 2.7375, 2.7500, 4.6000, 4.6125, 4.6250}; double scm_c_amps_dB[] = {0.00, -2.22, -3.98, -1.86, -4.08, -5.84, -1.08, -3.30, -5.06, -9.08, -11.30, -13.06, -15.14, -17.36, -19.12, -20.64, -22.85, -24.62}; double epa_delays[] = { 0,.03,.07,.09,.11,.19,.41}; @@ -282,10 +282,10 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx, SCM_t channel_model, double sampling_rate, double channel_bandwidth, - double forgetting_factor, + double forgetting_factor, int32_t channel_offset, double path_loss_dB) { - channel_desc_t *chan_desc = (channel_desc_t *)malloc(sizeof(channel_desc_t)); + channel_desc_t *chan_desc = (channel_desc_t *)calloc(1,sizeof(channel_desc_t)); for(int i=0; ichannel_length = (int) (2*chan_desc->sampling_rate*chan_desc->Td + 1 + 2/(M_PI*M_PI)*log(4*M_PI*chan_desc->sampling_rate*chan_desc->Td)); sum_amps = 0; chan_desc->amps = (double *) malloc(chan_desc->nb_taps*sizeof(double)); - + chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_AMPS ; for (i = 0; inb_taps; i++) { chan_desc->amps[i] = pow(10,.1*scm_c_amps_dB[i]); sum_amps += chan_desc->amps[i]; @@ -368,9 +368,10 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx, for (i = 0; i<6; i++) chan_desc->R_sqrt[i] = (struct complex *) &R12_sqrt[i][0]; } else { + chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_RSQRT_6 ; for (i = 0; i<6; i++) { chan_desc->R_sqrt[i] = (struct complex *) malloc(nb_tx*nb_rx*nb_tx*nb_rx * sizeof(struct complex)); - + for (j = 0; jR_sqrt[i][j].x = 1.0; chan_desc->R_sqrt[i][j].y = 0.0; @@ -389,7 +390,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx, chan_desc->channel_length = (int) (2*chan_desc->sampling_rate*chan_desc->Td + 1 + 2/(M_PI*M_PI)*log(4*M_PI*chan_desc->sampling_rate*chan_desc->Td)); sum_amps = 0; chan_desc->amps = (double *) malloc(chan_desc->nb_taps*sizeof(double)); - + chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_AMPS ; for (i = 0; inb_taps; i++) { chan_desc->amps[i] = pow(10,.1*scm_c_amps_dB[i]); sum_amps += chan_desc->amps[i]; @@ -427,6 +428,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx, for (i = 0; i<6; i++) chan_desc->R_sqrt[i] = (struct complex *) &R12_sqrt[i][0]; } else { + chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_RSQRT_6 ; for (i = 0; i<6; i++) { chan_desc->R_sqrt[i] = (struct complex *) malloc(nb_tx*nb_rx*nb_tx*nb_rx * sizeof(struct complex)); @@ -447,7 +449,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx, chan_desc->channel_length = (int) (2*chan_desc->sampling_rate*chan_desc->Td + 1 + 2/(M_PI*M_PI)*log(4*M_PI*chan_desc->sampling_rate*chan_desc->Td)); sum_amps = 0; chan_desc->amps = (double *) malloc(chan_desc->nb_taps*sizeof(double)); - + chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_AMPS ; for (i = 0; inb_taps; i++) { chan_desc->amps[i] = pow(10,.1*epa_amps_dB[i]); sum_amps += chan_desc->amps[i]; @@ -466,7 +468,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx, for (i = 0; ich[i] = (struct complex *) malloc(chan_desc->channel_length * sizeof(struct complex)); - + for (i = 0; ichF[i] = (struct complex *) malloc(1200 * sizeof(struct complex)); @@ -480,7 +482,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx, chan_desc->R_sqrt[i] = (struct complex *) &R22_sqrt[i][0]; } else { chan_desc->R_sqrt = (struct complex **) malloc(6*sizeof(struct complex **)); - + chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_RSQRT_6 ; for (i = 0; i<6; i++) { chan_desc->R_sqrt[i] = (struct complex *) malloc(nb_tx*nb_rx*nb_tx*nb_rx * sizeof(struct complex)); @@ -501,7 +503,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx, chan_desc->channel_length = (int) (2*chan_desc->sampling_rate*chan_desc->Td + 1 + 2/(M_PI*M_PI)*log(4*M_PI*chan_desc->sampling_rate*chan_desc->Td)); sum_amps = 0; chan_desc->amps = (double *) malloc(chan_desc->nb_taps*sizeof(double)); - + chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_AMPS ; for (i = 0; inb_taps; i++) { chan_desc->amps[i] = pow(10,.1*epa_amps_dB[i]); sum_amps += chan_desc->amps[i]; @@ -547,7 +549,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx, LOG_W(OCM,"correlation matrix only implemented for nb_tx==2 and nb_rx==2, using identity\n"); } }*/ - break; + break; case EPA_high: chan_desc->nb_taps = 7; @@ -555,7 +557,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx, chan_desc->channel_length = (int) (2*chan_desc->sampling_rate*chan_desc->Td + 1 + 2/(M_PI*M_PI)*log(4*M_PI*chan_desc->sampling_rate*chan_desc->Td)); sum_amps = 0; chan_desc->amps = (double *) malloc(chan_desc->nb_taps*sizeof(double)); - + chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_AMPS ; for (i = 0; inb_taps; i++) { chan_desc->amps[i] = pow(10,.1*epa_amps_dB[i]); sum_amps += chan_desc->amps[i]; @@ -609,7 +611,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx, chan_desc->channel_length = (int) (2*chan_desc->sampling_rate*chan_desc->Td + 1 + 2/(M_PI*M_PI)*log(4*M_PI*chan_desc->sampling_rate*chan_desc->Td)); sum_amps = 0; chan_desc->amps = (double *) malloc(chan_desc->nb_taps*sizeof(double)); - + chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_AMPS ; for (i = 0; inb_taps; i++) { chan_desc->amps[i] = pow(10,.1*epa_amps_dB[i]); sum_amps += chan_desc->amps[i]; @@ -663,7 +665,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx, chan_desc->channel_length = (int) (2*chan_desc->sampling_rate*chan_desc->Td + 1 + 2/(M_PI*M_PI)*log(4*M_PI*chan_desc->sampling_rate*chan_desc->Td)); sum_amps = 0; chan_desc->amps = (double *) malloc(chan_desc->nb_taps*sizeof(double)); - + chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_AMPS ; for (i = 0; inb_taps; i++) { chan_desc->amps[i] = pow(10,.1*eva_amps_dB[i]); sum_amps += chan_desc->amps[i]; @@ -696,8 +698,8 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx, chan_desc->R_sqrt[i] = (struct complex *) &R22_sqrt[i][0]; } else { chan_desc->R_sqrt = (struct complex **) malloc(6*sizeof(struct complex **)); - - for (i = 0; i<6; i++) { + chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_RSQRT_6 ; + for (i = 0; i<6; i++) { chan_desc->R_sqrt[i] = (struct complex *) malloc(nb_tx*nb_rx*nb_tx*nb_rx * sizeof(struct complex)); for (j = 0; jchannel_length = (int) (2*chan_desc->sampling_rate*chan_desc->Td + 1 + 2/(M_PI*M_PI)*log(4*M_PI*chan_desc->sampling_rate*chan_desc->Td)); sum_amps = 0; chan_desc->amps = (double *) malloc(chan_desc->nb_taps*sizeof(double)); - + chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_AMPS ; for (i = 0; inb_taps; i++) { chan_desc->amps[i] = pow(10,.1*etu_amps_dB[i]); sum_amps += chan_desc->amps[i]; @@ -750,7 +752,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx, chan_desc->R_sqrt[i] = (struct complex *) &R22_sqrt[i][0]; } else { chan_desc->R_sqrt = (struct complex **) malloc(6*sizeof(struct complex **)); - + chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_RSQRT_6 ; for (i = 0; i<6; i++) { chan_desc->R_sqrt[i] = (struct complex *) malloc(nb_tx*nb_rx*nb_tx*nb_rx * sizeof(struct complex)); @@ -771,7 +773,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx, chan_desc->channel_length = (int) (2*chan_desc->sampling_rate*chan_desc->Td + 1 + 2/(M_PI*M_PI)*log(4*M_PI*chan_desc->sampling_rate*chan_desc->Td)); sum_amps = 0; chan_desc->amps = (double *) malloc(chan_desc->nb_taps*sizeof(double)); - + chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_AMPS ; for (i = 0; inb_taps; i++) { chan_desc->amps[i] = pow(10,.1*mbsfn_amps_dB[i]); sum_amps += chan_desc->amps[i]; @@ -798,7 +800,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx, chan_desc->a[i] = (struct complex *) malloc(nb_tx*nb_rx * sizeof(struct complex)); chan_desc->R_sqrt = (struct complex **) malloc(6*sizeof(struct complex *)); - + chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_RSQRT_6; for (i = 0; i<6; i++) { chan_desc->R_sqrt[i] = (struct complex *) malloc(nb_tx*nb_rx*nb_tx*nb_rx * sizeof(struct complex)); @@ -1309,11 +1311,37 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx, chan_desc->nb_paths = 10; return(chan_desc); } - + void free_channel_desc_scm(channel_desc_t *ch) { // Must be made cleanly, a lot of leaks... - defined_channels[ch->chan_idx]=NULL; - free(ch); + defined_channels[ch->chan_idx]=NULL; + if(ch->free_flags&CHANMODEL_FREE_AMPS) + free(ch->amps); + for (int i = 0; inb_tx*ch->nb_rx; i++) { + free(ch->ch[i]); + free(ch->chF[i]); + } + + for (int i = 0; inb_taps; i++) { + free(ch->a[i]); + } + if(ch->free_flags&CHANMODEL_FREE_DELAY) + free(ch->delays); + if(ch->free_flags&CHANMODEL_FREE_RSQRT_6) + for (int i = 0; i<6; i++) + free(ch->R_sqrt[i]); + if(ch->free_flags&CHANMODEL_FREE_RSQRT_NTAPS) + for (int i = 0; inb_taps;i++) + free(ch->R_sqrt[i]); + free(ch->R_sqrt); + free(ch->ch); + free(ch->chF); + free(ch->a); + free(ch); +} + +void set_channeldesc_owner(channel_desc_t *cdesc, uint32_t module_id) { + cdesc->module_id=module_id; } int random_channel(channel_desc_t *desc, uint8_t abstraction_flag) { @@ -1454,7 +1482,7 @@ int random_channel(channel_desc_t *desc, uint8_t abstraction_flag) { return (0); } - + double N_RB2sampling_rate(uint16_t N_RB) { double sampling_rate; @@ -1522,6 +1550,10 @@ static int channelmod_print_help(char *buff, int debug, telnet_printfunc_t prnt static void display_channelmodel(channel_desc_t *cd,int debug, telnet_printfunc_t prnt) { + char *module_id_str[]=MODULEID_STR_INIT; + if (cd->module_id != 0) { + prnt("model owner: %s\n",module_id_str[cd->module_id]); + } prnt("nb_tx: %i nb_rx: %i taps: %i bandwidth: %lf sampling: %lf\n",cd->nb_tx, cd->nb_rx, cd->nb_taps, cd->channel_bandwidth, cd->sampling_rate); prnt("channel length: %i Max path delay: %lf ricean fact.: %lf angle of arrival: %lf (randomized:%s)\n", cd->channel_length, cd->Td, cd->ricean_factor, cd->aoa, (cd->random_aoa?"Yes":"No")); @@ -1617,10 +1649,10 @@ static int channelmod_modify_cmd(char *buff, int debug, telnet_printfunc_t prnt) return CMDSTATUS_FOUND; } -int modelid_fromname(char *modelname) { - int modelid=map_str_to_int(channelmod_names,modelname); - AssertFatal(modelid>0, - "random_channel.c: Error channel model %s unknown\n",modelname); +int modelid_fromname(char *modelname) { + int modelid=map_str_to_int(channelmod_names,modelname); + if (modelid < 0) + LOG_E(OCM,"random_channel.c: Error channel model %s unknown\n",modelname); return modelid; } diff --git a/openair1/SIMULATION/TOOLS/sim.h b/openair1/SIMULATION/TOOLS/sim.h index 2e067e4ae8..cc06e2f85c 100644 --- a/openair1/SIMULATION/TOOLS/sim.h +++ b/openair1/SIMULATION/TOOLS/sim.h @@ -40,6 +40,16 @@ The present clause specifies several numerical functions for testing of digital #define NB_SAMPLES_CHANNEL_OFFSET 4 +typedef enum { + UNSPECIFIED_MODID=0, + RFSIMU_MODULEID=1 +} channelmod_moduleid_t; +#define MODULEID_STR_INIT {"","rfsimulator"} + +#define CHANMODEL_FREE_DELAY 1<<0 +#define CHANMODEL_FREE_RSQRT_6 1<<1 +#define CHANMODEL_FREE_RSQRT_NTAPS 1<<2 +#define CHANMODEL_FREE_AMPS 1<<3 typedef struct { ///Number of tx antennas uint8_t nb_tx; @@ -96,6 +106,10 @@ typedef struct { unsigned int chan_idx; /// id of the channel modeling algorithm int modelid; + /// identifies channel descriptor owner (the module which created this descriptor) + channelmod_moduleid_t module_id; + /// flags to properly trigger memory free + unsigned int free_flags; } channel_desc_t; typedef struct { @@ -278,9 +292,18 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx, double forgetting_factor, int32_t channel_offset, double path_loss_dB); +/** +\brief free memory allocated for a model descriptor +\param ch points to the model, which cannot be used after calling this fuction +*/ +void free_channel_desc_scm(channel_desc_t *ch); - - +/** +\brief This set the ownerid of a model descriptor, can be later used to check what module created a channel model +\param cdesc points to the model descriptor +\param module_id identifies the channel model. should be define as a macro in simu.h +*/ +void set_channeldesc_owner(channel_desc_t *cdesc, channelmod_moduleid_t module_id); /** \fn void random_channel(channel_desc_t *desc) \brief This routine generates a random channel response (time domain) according to a tapped delay line model. \param desc Pointer to the channel descriptor diff --git a/targets/ARCH/rfsimulator/simulator.c b/targets/ARCH/rfsimulator/simulator.c index 9ad05f3a88..36c90304b7 100644 --- a/targets/ARCH/rfsimulator/simulator.c +++ b/targets/ARCH/rfsimulator/simulator.c @@ -89,9 +89,9 @@ extern RAN_CONTEXT_t RC; -static int rfsimu_setchanmod_cmd(char *buff, int debug, telnet_printfunc_t prnt); +static int rfsimu_setchanmod_cmd(char *buff, int debug, telnet_printfunc_t prnt, void *arg); static telnetshell_cmddef_t rfsimu_cmdarray[] = { - {"setmodel","",rfsimu_setchanmod_cmd,TELNETSRV_CMDFLAG_PUSHINTPOOLQ}, + {"setmodel","",(cmdfunc_t)rfsimu_setchanmod_cmd,TELNETSRV_CMDFLAG_PUSHINTPOOLQ}, {"","",NULL}, }; @@ -185,6 +185,7 @@ void allocCirBuf(rfsimulator_state_t *bridge, int sock) { bridge->chan_forgetfact, // forgetting_factor bridge->chan_offset, // maybe used for TA bridge->chan_pathloss); // path_loss in dB + set_channeldesc_owner(ptr->channel_model, RFSIMU_MODULEID); random_channel(ptr->channel_model,false); } } @@ -311,25 +312,38 @@ void rfsimulator_readconfig(rfsimulator_state_t *rfsimulator) { rfsimulator->typeStamp = UE_MAGICDL_FDD; } -static int rfsimu_setchanmod_cmd(char *buff, int debug, telnet_printfunc_t prnt) { +static int rfsimu_setchanmod_cmd(char *buff, int debug, telnet_printfunc_t prnt, void *arg) { char *modelname=NULL; int s = sscanf(buff,"%ms\n",&modelname); - int channelmod=modelid_fromname(modelname); - for (int i=0; ibuf[i].conn_sock > 0) { - channel_desc_t *cm = rfsimulator->buf[i].channel_model; - - rfsimulator->buf[i].channel_model=new_channel_desc_scm(cm->nb_tx,cm->nb_rx, - channelmod, - cm->sampling_rate, - cm->channel_bandwidth, - cm->forgetting_factor, // forgetting_factor - cm->channel_offset, // maybe used for TA - cm-> path_loss_dB); // path_loss in dB - free_channel_desc_scm(cm); - random_channel(ptr->channel_model,false); - } */ + if (s == 1) { + int channelmod=modelid_fromname(modelname); + if (channelmod<0) + prnt("ERROR: model %s unknown\n",modelname); + else { + rfsimulator_state_t *t = (rfsimulator_state_t *)arg; + for (int i=0; ibuf[i]; + if (b->conn_sock >= 0 ) { + channel_desc_t *newmodel=new_channel_desc_scm(t->tx_num_channels,t->rx_num_channels, + channelmod, + t->sample_rate, + t->tx_bw, + t->chan_forgetfact, // forgetting_factor + t->chan_offset, // maybe used for TA + t->chan_pathloss); // path_loss in dB + set_channeldesc_owner(newmodel, RFSIMU_MODULEID); + random_channel(newmodel,false); + channel_desc_t *oldmodel=b->channel_model; + b->channel_model=newmodel; + free_channel_desc_scm(oldmodel); + prnt("New model %s applied to channel connected to sock %d\n",modelname,i); + } + } + } + } else { + prnt("ERROR: no model specified\n"); } + free(modelname); return CMDSTATUS_FOUND; } @@ -683,7 +697,8 @@ int rfsimulator_read(openair0_device *device, openair0_timestamp *ptimestamp, vo // it seems legacy behavior is: never in UL, each frame in DL if (reGenerateChannel) random_channel(ptr->channel_model,0); - t->poll_telnetcmdq(t->telnetcmd_qid); + if (t->poll_telnetcmdq) + t->poll_telnetcmdq(t->telnetcmd_qid,t); for (int a=0; achannel_model != NULL ) // apply a channel model rxAddInput( ptr->circularBuf, (struct complex16 *) samplesVoid[a], From 2612f2639dd40841b5b69d6a5e4d6ba7ebbb2319 Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Thu, 30 Jul 2020 10:38:36 +0200 Subject: [PATCH 536/553] CI: fix a few remaining getters Signed-off-by: Raphael Defosseux --- ci-scripts/ran.py | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/ci-scripts/ran.py b/ci-scripts/ran.py index 94d4f857b7..8f254975eb 100644 --- a/ci-scripts/ran.py +++ b/ci-scripts/ran.py @@ -348,9 +348,9 @@ class RANManagement(): # If tracer options is on, running tshark on EPC side and capture traffic b/ EPC and eNB result = re.search('T_stdout', str(self.Initialize_eNB_args)) if (result is not None) and (self.epcObj is not None): - localEpcIpAddr = self.epcObj.GetIPAddress() - localEpcUserName = self.epcObj.GetUserName() - localEpcPassword = self.epcObj.GetPassword() + localEpcIpAddr = self.epcObj.IPAddress + localEpcUserName = self.epcObj.UserName + localEpcPassword = self.epcObj.Password mySSH.open(localEpcIpAddr, localEpcUserName, localEpcPassword) mySSH.command('ip addr show | awk -f /tmp/active_net_interfaces.awk | egrep -v "lo|tun"', '\$', 5) result = re.search('interfaceToUse=(?P[a-zA-Z0-9\-\_]+)done', mySSH.getBefore()) @@ -457,9 +457,9 @@ class RANManagement(): # In case of T tracer recording, we need to kill tshark on EPC side result = re.search('T_stdout', str(self.Initialize_eNB_args)) if (result is not None) and (self.epcObj is not None): - localEpcIpAddr = self.epcObj.GetIPAddress() - localEpcUserName = self.epcObj.GetUserName() - localEpcPassword = self.epcObj.GetPassword() + localEpcIpAddr = self.epcObj.IPAddress + localEpcUserName = self.epcObj.UserName + localEpcPassword = self.epcObj.Password mySSH.open(localEpcIpAddr, localEpcUserName, localEpcPassword) logging.debug('\u001B[1m Stopping tshark \u001B[0m') mySSH.command('echo ' + localEpcPassword + ' | sudo -S killall --signal SIGKILL tshark', '\$', 5) @@ -588,9 +588,9 @@ class RANManagement(): # If tracer options is on, stopping tshark on EPC side result = re.search('T_stdout', str(self.Initialize_eNB_args)) if (result is not None) and (self.epcObj is not None): - localEpcIpAddr = self.epcObj.GetIPAddress() - localEpcUserName = self.epcObj.GetUserName() - localEpcPassword = self.epcObj.GetPassword() + localEpcIpAddr = self.epcObj.IPAddress + localEpcUserName = self.epcObj.UserName + localEpcPassword = self.epcObj.Password mySSH.open(localEpcIpAddr, localEpcUserName, localEpcPassword) logging.debug('\u001B[1m Stopping tshark \u001B[0m') mySSH.command('echo ' + localEpcPassword + ' | sudo -S killall --signal SIGKILL tshark', '\$', 5) From 5e62d39c9d57e55450febd588289b22d0e64f84f Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Thu, 30 Jul 2020 14:06:31 +0200 Subject: [PATCH 537/553] CI: fix the air_interface support on RAN and OAI-UE sides -- separate member now. Signed-off-by: Raphael Defosseux --- ci-scripts/main.py | 102 +++++++++++------- ci-scripts/ran.py | 33 +++--- ci-scripts/xml_files/fr1_multi_node_build.xml | 12 ++- ci-scripts/xml_files/gnb_usrp_build.xml | 2 +- ci-scripts/xml_files/nr_ue_usrp_build.xml | 2 +- 5 files changed, 88 insertions(+), 63 deletions(-) diff --git a/ci-scripts/main.py b/ci-scripts/main.py index aaceac600e..660f068c2c 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -119,6 +119,7 @@ class OaiCiTest(): self.Build_OAI_UE_args = '' self.Initialize_OAI_UE_args = '' self.clean_repository = True + self.air_interface='' self.expectedNbOfConnectedUEs = 0 def BuildOAIUE(self): @@ -128,10 +129,10 @@ class OaiCiTest(): SSH.open(self.UEIPAddress, self.UEUserName, self.UEPassword) result = re.search('--nrUE', self.Build_OAI_UE_args) if result is not None: - RAN.air_interface='nr' + self.air_interface='nr-uesoftmodem' ue_prefix = 'NR ' else: - RAN.air_interface='lte' + self.air_interface='lte-uesoftmodem' ue_prefix = '' result = re.search('([a-zA-Z0-9\:\-\.\/])+\.git', self.ranRepository) if result is not None: @@ -171,7 +172,7 @@ class OaiCiTest(): mismatch = True if not mismatch: SSH.close() - HTML.CreateHtmlTestRow(RAN.Build_eNB_args, 'OK', CONST.ALL_PROCESSES_OK) + HTML.CreateHtmlTestRow(self.Build_OAI_UE_args, 'OK', CONST.ALL_PROCESSES_OK) return SSH.command('echo ' + self.UEPassword + ' | sudo -S git clean -x -d -ff', '\$', 30) @@ -197,7 +198,7 @@ class OaiCiTest(): SSH.command('ls ran_build/build', '\$', 3) SSH.command('ls ran_build/build', '\$', 3) buildStatus = True - result = re.search(RAN.air_interface + '-uesoftmodem', SSH.getBefore()) + result = re.search(self.air_interface, SSH.getBefore()) if result is None: buildStatus = False SSH.command('mkdir -p build_log_' + self.testCase_id, '\$', 5) @@ -322,7 +323,7 @@ class OaiCiTest(): if self.UEIPAddress == '' or self.UEUserName == '' or self.UEPassword == '' or self.UESourceCodePath == '': HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') - if RAN.air_interface == 'lte': + if self.air_interface == 'lte-uesoftmodem': result = re.search('--no-L2-connect', str(self.Initialize_OAI_UE_args)) if result is None: check_eNB = True @@ -351,7 +352,7 @@ class OaiCiTest(): # Initialize_OAI_UE_args usually start with -C and followed by the location in repository SSH.command('source oaienv', '\$', 5) SSH.command('cd cmake_targets/ran_build/build', '\$', 5) - if RAN.air_interface == 'lte': + if self.air_interface == 'lte-uesoftmodem': result = re.search('--no-L2-connect', str(self.Initialize_OAI_UE_args)) # We may have to regenerate the .u* files if result is None: @@ -373,7 +374,7 @@ class OaiCiTest(): copyin_res = SSH.copyin(RAN.eNBIPAddress, RAN.eNBUserName, RAN.eNBPassword, RAN.eNBSourceCodePath + '/cmake_targets/reconfig.raw', '.') if (copyin_res == 0): SSH.copyout(self.UEIPAddress, self.UEUserName, self.UEPassword, './reconfig.raw', self.UESourceCodePath + '/cmake_targets/ran_build/build') - SSH.command('echo "ulimit -c unlimited && ./'+ RAN.air_interface +'-uesoftmodem ' + self.Initialize_OAI_UE_args + '" > ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5) + SSH.command('echo "ulimit -c unlimited && ./'+ self.air_interface +' ' + self.Initialize_OAI_UE_args + '" > ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5) SSH.command('chmod 775 ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5) SSH.command('echo ' + self.UEPassword + ' | sudo -S rm -Rf ' + self.UESourceCodePath + '/cmake_targets/ue_' + self.testCase_id + '.log', '\$', 5) self.UELogFile = 'ue_' + self.testCase_id + '.log' @@ -404,7 +405,7 @@ class OaiCiTest(): doLoop = False continue SSH.command('stdbuf -o0 cat ue_' + self.testCase_id + '.log | egrep --text --color=never -i "wait|sync"', '\$', 4) - if RAN.air_interface == 'nr': + if self.air_interface == 'nr-uesoftmodem': result = re.search('Starting sync detection', SSH.getBefore()) else: result = re.search('got sync', SSH.getBefore()) @@ -429,7 +430,7 @@ class OaiCiTest(): # That is the case for LTE # In NR case, it's a positive message that will show if synchronization occurs doLoop = True - if RAN.air_interface == 'nr': + if self.air_interface == 'nr-uesoftmodem': loopCounter = 10 else: # We are now checking if sync w/ eNB DOES NOT OCCUR @@ -438,7 +439,7 @@ class OaiCiTest(): while (doLoop): loopCounter = loopCounter - 1 if (loopCounter == 0): - if RAN.air_interface == 'nr': + if self.air_interface == 'nr-uesoftmodem': # Here we do have great chances that UE did NOT cell-sync w/ gNB doLoop = False fullSyncStatus = False @@ -457,7 +458,7 @@ class OaiCiTest(): fullSyncStatus = True continue SSH.command('stdbuf -o0 cat ue_' + self.testCase_id + '.log | egrep --text --color=never -i "wait|sync|Frequency"', '\$', 4) - if RAN.air_interface == 'nr': + if self.air_interface == 'nr-uesoftmodem': # Positive messaging --> result = re.search('Measured Carrier Frequency', SSH.getBefore()) if result is not None: @@ -486,12 +487,12 @@ class OaiCiTest(): if fullSyncStatus and gotSyncStatus: doInterfaceCheck = False - if RAN.air_interface == 'lte': + if self.air_interface == 'lte-uesoftmodem': result = re.search('--no-L2-connect', str(self.Initialize_OAI_UE_args)) if result is None: doInterfaceCheck = True # For the moment, only in explicit noS1 without kernel module (ie w/ tunnel interface) - if RAN.air_interface == 'nr': + if self.air_interface == 'nr-uesoftmodem': result = re.search('--noS1 --nokrnmod 1', str(self.Initialize_OAI_UE_args)) if result is not None: doInterfaceCheck = True @@ -531,7 +532,7 @@ class OaiCiTest(): self.UEDevicesStatus = [] self.UEDevicesStatus.append(CONST.UE_STATUS_DETACHED) else: - if RAN.air_interface == 'lte': + if self.air_interface == 'lte-uesoftmodem': if RAN.eNBmbmsEnables[0]: HTML.htmlUEFailureMsg='oaitun_ue1/oaitun_uem1 interfaces are either NOT mounted or NOT configured' else: @@ -1086,7 +1087,10 @@ class OaiCiTest(): sys.exit('Insufficient Parameter') SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) if self.ADBCentralized: - SSH.command('adb devices', '\$', 15) + if self.ADBIPAddress == '192.168.18.196': + SSH.command('/home/oaici/remi/android-sdk-linux/platform-tools/adb devices', '\$', 15) + else: + SSH.command('adb devices', '\$', 15) #self.UEDevices = re.findall("\\\\r\\\\n([A-Za-z0-9]+)\\\\tdevice",SSH.getBefore()) self.UEDevices = re.findall("\\\\r\\\\n([A-Za-z0-9]+)\\\\tdevice",SSH.getBefore()) SSH.close() @@ -2414,8 +2418,8 @@ class OaiCiTest(): def CheckOAIUEProcess(self, status_queue): try: SSH.open(self.UEIPAddress, self.UEUserName, self.UEPassword) - SSH.command('stdbuf -o0 ps -aux | grep --color=never ' + RAN.air_interface + '-uesoftmodem | grep -v grep', '\$', 5) - result = re.search(RAN.air_interface + '-uesoftmodem', SSH.getBefore()) + SSH.command('stdbuf -o0 ps -aux | grep --color=never ' + self.air_interface + ' | grep -v grep', '\$', 5) + result = re.search(self.air_interface, SSH.getBefore()) if result is None: logging.debug('\u001B[1;37;41m OAI UE Process Not Found! \u001B[0m') status_queue.put(CONST.OAI_UE_PROCESS_FAILED) @@ -2772,7 +2776,7 @@ class OaiCiTest(): logging.debug('\u001B[1m' + ueAction + ' Failed \u001B[0m') HTML.htmlUEFailureMsg='' + ueAction + ' Failed\n' + HTML.htmlUEFailureMsg HTML.CreateHtmlTestRow('N/A', 'KO', logStatus, 'UE') - if RAN.air_interface == 'lte': + if self.air_interface == 'lte-uesoftmodem': # In case of sniffing on commercial eNBs we have random results # Not an error then if (logStatus != CONST.OAI_UE_PROCESS_COULD_NOT_SYNC) or (ueAction != 'Sniffing'): @@ -2811,7 +2815,7 @@ class OaiCiTest(): self.desc = 'Automatic Termination of eNB' HTML.desc='Automatic Termination of eNB' self.ShowTestID() - RAN.eNB_instance='0' + RAN.eNB_instance=0 RAN.TerminateeNB() if RAN.flexranCtrlInstalled and RAN.flexranCtrlStarted: self.testCase_id = 'AUTO-KILL-flexran-ctl' @@ -3118,9 +3122,11 @@ def GetParametersFromXML(action): RAN.Build_eNB_forced_workspace_cleanup=True else: RAN.Build_eNB_forced_workspace_cleanup=False - RAN.eNB_instance=test.findtext('eNB_instance') - if (RAN.eNB_instance is None): - RAN.eNB_instance='0' + eNB_instance=test.findtext('eNB_instance') + if (eNB_instance is None): + RAN.eNB_instance=0 + else: + RAN.eNB_instance=int(eNB_instance) RAN.eNB_serverId=test.findtext('eNB_serverId') if (RAN.eNB_serverId is None): RAN.eNB_serverId='0' @@ -3135,18 +3141,22 @@ def GetParametersFromXML(action): if action == 'WaitEndBuild_eNB': RAN.Build_eNB_args=test.findtext('Build_eNB_args') - RAN.eNB_instance=test.findtext('eNB_instance') - if (RAN.eNB_instance is None): + eNB_instance=test.findtext('eNB_instance') + if (eNB_instance is None): RAN.eNB_instance='0' + else: + RAN.eNB_instance=int(eNB_instance) RAN.eNB_serverId=test.findtext('eNB_serverId') if (RAN.eNB_serverId is None): RAN.eNB_serverId='0' if action == 'Initialize_eNB': RAN.Initialize_eNB_args=test.findtext('Initialize_eNB_args') - RAN.eNB_instance=test.findtext('eNB_instance') - if (RAN.eNB_instance is None): - RAN.eNB_instance='0' + eNB_instance=test.findtext('eNB_instance') + if (eNB_instance is None): + RAN.eNB_instance=0 + else: + RAN.eNB_instance=int(eNB_instance) RAN.eNB_serverId=test.findtext('eNB_serverId') if (RAN.eNB_serverId is None): RAN.eNB_serverId='0' @@ -3154,17 +3164,18 @@ def GetParametersFromXML(action): #local variable air_interface air_interface = test.findtext('air_interface') if (air_interface is None) or (air_interface.lower() not in ['nr','lte','ocp']): - CiTestObj.air_interface = 'lte-softmodem' + RAN.air_interface[RAN.eNB_instance] = 'lte-softmodem' elif (air_interface.lower() in ['nr','lte']): - CiTestObj.air_interface = air_interface.lower() +'-softmodem' + RAN.air_interface[RAN.eNB_instance] = air_interface.lower() +'-softmodem' else : - CiTestObj.air_interface = 'ocp-enb' - RAN.air_interface=CiTestObj.air_interface + RAN.air_interface[RAN.eNB_instance] = 'ocp-enb' if action == 'Terminate_eNB': - RAN.eNB_instance=test.findtext('eNB_instance') + eNB_instance=test.findtext('eNB_instance') if (RAN.eNB_instance is None): - RAN.eNB_instance='0' + RAN.eNB_instance=0 + else: + RAN.eNB_instance=int(eNB_instance) RAN.eNB_serverId=test.findtext('eNB_serverId') if (RAN.eNB_serverId is None): RAN.eNB_serverId='0' @@ -3172,12 +3183,11 @@ def GetParametersFromXML(action): #local variable air_interface air_interface = test.findtext('air_interface') if (air_interface is None) or (air_interface.lower() not in ['nr','lte','ocp']): - CiTestObj.air_interface = 'lte-softmodem' + RAN.air_interface[RAN.eNB_instance] = 'lte-softmodem' elif (air_interface.lower() in ['nr','lte']): - CiTestObj.air_interface = air_interface.lower() +'-softmodem' + RAN.air_interface[RAN.eNB_instance] = air_interface.lower() +'-softmodem' else : - CiTestObj.air_interface = 'ocp-enb' - RAN.air_interface=CiTestObj.air_interface + RAN.air_interface[RAN.eNB_instance] = 'ocp-enb' if action == 'Attach_UE': nbMaxUEtoAttach = test.findtext('nbMaxUEtoAttach') @@ -3210,17 +3220,27 @@ def GetParametersFromXML(action): #local variable air_interface air_interface = test.findtext('air_interface') if (air_interface is None) or (air_interface.lower() not in ['nr','lte','ocp']): - CiTestObj.air_interface = 'lte-softmodem' + CiTestObj.air_interface = 'lte-uesoftmodem' elif (air_interface.lower() in ['nr','lte']): - CiTestObj.air_interface = air_interface.lower() +'-softmodem' + CiTestObj.air_interface = air_interface.lower() +'-uesoftmodem' else : - CiTestObj.air_interface = 'ocp-enb' - RAN.air_interface=CiTestObj.air_interface + #CiTestObj.air_interface = 'ocp-enb' + logging.error('OCP UE -- NOT SUPPORTED') if action == 'Terminate_OAI_UE': RAN.eNB_instance=test.findtext('UE_instance') if (CiTestObj.UE_instance is None): CiTestObj.UE_instance = '0' + + #local variable air_interface + air_interface = test.findtext('air_interface') + if (air_interface is None) or (air_interface.lower() not in ['nr','lte','ocp']): + CiTestObj.air_interface = 'lte-uesoftmodem' + elif (air_interface.lower() in ['nr','lte']): + CiTestObj.air_interface = air_interface.lower() +'-uesoftmodem' + else : + #CiTestObj.air_interface = 'ocp-enb' + logging.error('OCP UE -- NOT SUPPORTED') if action == 'Ping' or action == 'Ping_CatM_module': CiTestObj.ping_args = test.findtext('ping_args') diff --git a/ci-scripts/ran.py b/ci-scripts/ran.py index 8f254975eb..054b92a181 100644 --- a/ci-scripts/ran.py +++ b/ci-scripts/ran.py @@ -77,8 +77,8 @@ class RANManagement(): self.backgroundBuildTestId = ['', '', ''] self.Build_eNB_forced_workspace_cleanup = False self.Initialize_eNB_args = '' - self.air_interface = '' #changed from 'lte' to '' may lead to side effects in main - self.eNB_instance = '' + self.air_interface = ['', '', ''] #changed from 'lte' to '' may lead to side effects in main + self.eNB_instance = 0 self.eNB_serverId = '' self.eNBLogFiles = ['', '', ''] self.eNBOptions = ['', '', ''] @@ -125,13 +125,13 @@ class RANManagement(): # Check if we build an 5G-NR gNB or an LTE eNB or an OCP eNB result = re.search('--eNBocp', self.Build_eNB_args) if result is not None: - self.air_interface='ocp-enb' + self.air_interface[self.eNB_instance] = 'ocp-enb' else: result = re.search('--gNB', self.Build_eNB_args) if result is not None: - self.air_interface = 'nr-softmodem' + self.air_interface[self.eNB_instance] = 'nr-softmodem' else: - self.air_interface = 'lte-softmodem' + self.air_interface[self.eNB_instance] = 'lte-softmodem' # Worakround for some servers, we need to erase completely the workspace if self.Build_eNB_forced_workspace_cleanup: @@ -205,7 +205,9 @@ class RANManagement(): if self.backgroundBuild: mySSH.command('echo "./build_oai ' + self.Build_eNB_args + '" > ./my-lte-softmodem-build.sh', '\$', 5) mySSH.command('chmod 775 ./my-lte-softmodem-build.sh', '\$', 5) - mySSH.command('echo ' + lPassWord + ' | sudo -S -E daemon --inherit --unsafe --name=build_enb_daemon --chdir=' + lSourcePath + '/cmake_targets -o ' + lSourcePath + '/cmake_targets/compile_oai_enb.log ./my-lte-softmodem-build.sh', '\$', 5) + #mySSH.command('echo ' + lPassWord + ' | sudo -S -E daemon --inherit --unsafe --name=build_enb_daemon --chdir=' + lSourcePath + '/cmake_targets -o ' + lSourcePath + '/cmake_targets/compile_oai_enb.log ./my-lte-softmodem-build.sh', '\$', 5) + mySSH.command('echo ' + lPassWord + ' | sudo -S ls', '\$', 5) + mySSH.command('echo $USER; nohup sudo ./my-lte-softmodem-build.sh' + ' > ' + lSourcePath + '/cmake_targets/compile_oai_enb.log ' + ' 2>&1 &', lUserName, 5) mySSH.close() if self.htmlObj is not None: self.htmlObj.CreateHtmlTestRow(self.Build_eNB_args, 'OK', CONST.ALL_PROCESSES_OK) @@ -261,7 +263,7 @@ class RANManagement(): #check if we have the build corresponding to the air interface keywords (nr-softmode, lte-softmodem, ocp-enb) logging.info('CHECK Build with IP='+lIpAddr+' SourcePath='+lSourcePath) - result = re.search(self.air_interface, mySSH.getBefore()) + result = re.search(self.air_interface[self.eNB_instance], mySSH.getBefore()) if result is None: buildStatus = False #if not, build failed else: @@ -304,11 +306,11 @@ class RANManagement(): #generate logging info depending on buildStatus and air interface if buildStatus: - logging.info('\u001B[1m Building OAI ' + self.air_interface + ' Pass\u001B[0m') + logging.info('\u001B[1m Building OAI ' + self.air_interface[self.eNB_instance] + ' Pass\u001B[0m') if self.htmlObj is not None: self.htmlObj.CreateHtmlTestRow(self.Build_eNB_args, 'OK', CONST.ALL_PROCESSES_OK) else: - logging.error('\u001B[1m Building OAI ' + self.air_interface + ' Failed\u001B[0m') + logging.error('\u001B[1m Building OAI ' + self.air_interface[self.eNB_instance] + ' Failed\u001B[0m') if self.htmlObj is not None: self.htmlObj.CreateHtmlTestRow(self.Build_eNB_args, 'KO', CONST.ALL_PROCESSES_OK) self.htmlObj.CreateHtmlTabFooter(False) @@ -426,7 +428,8 @@ class RANManagement(): if self.air_interface == 'nr': mySSH.command('if [ -e rbconfig.raw ]; then echo ' + lPassWord + ' | sudo -S rm rbconfig.raw; fi', '\$', 5) mySSH.command('if [ -e reconfig.raw ]; then echo ' + lPassWord + ' | sudo -S rm reconfig.raw; fi', '\$', 5) - mySSH.command('echo "ulimit -c unlimited && ./ran_build/build/' + self.air_interface + '-softmodem -O ' + lSourcePath + '/' + ci_full_config_file + extra_options + '" > ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh', '\$', 5) + # NOTE: WE SHALL do a check if the executable is present (in case build went wrong) + mySSH.command('echo "ulimit -c unlimited && ./ran_build/build/' + self.air_interface[self.eNB_instance] + ' -O ' + lSourcePath + '/' + ci_full_config_file + extra_options + '" > ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh', '\$', 5) mySSH.command('chmod 775 ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh', '\$', 5) mySSH.command('echo ' + lPassWord + ' | sudo -S rm -Rf enb_' + self.testCase_id + '.log', '\$', 5) mySSH.command('hostnamectl','\$', 5) @@ -535,8 +538,8 @@ class RANManagement(): lPassWord = self.eNBPassword mySSH = SSH.SSHConnection() mySSH.open(lIpAddr, lUserName, lPassWord) - mySSH.command('stdbuf -o0 ps -aux | grep --color=never ' + self.air_interface + ' | grep -v grep', '\$', 5) - result = re.search(self.air_interface, mySSH.getBefore()) + mySSH.command('stdbuf -o0 ps -aux | grep --color=never ' + self.air_interface[self.eNB_instance] + ' | grep -v grep', '\$', 5) + result = re.search(self.air_interface[self.eNB_instance], mySSH.getBefore()) if result is None: logging.debug('\u001B[1;37;41m eNB Process Not Found! \u001B[0m') status_queue.put(CONST.ENB_PROCESS_FAILED) @@ -568,7 +571,7 @@ class RANManagement(): mySSH = SSH.SSHConnection() mySSH.open(lIpAddr, lUserName, lPassWord) mySSH.command('cd ' + lSourcePath + '/cmake_targets', '\$', 5) - if (self.air_interface == 'lte-softmodem') or (self.air_interface == 'ocp-enb'): + if (self.air_interface[self.eNB_instance] == 'lte-softmodem') or (self.air_interface[self.eNB_instance] == 'ocp-enb'): nodeB_prefix = 'e' else: nodeB_prefix = 'g' @@ -831,11 +834,11 @@ class RANManagement(): mbmsRequestMsg += 1 enb_log_file.close() logging.debug(' File analysis completed') - if (self.air_interface == 'lte-softmodem') or (self.air_interface == 'ocp-enb'): + if (self.air_interface[self.eNB_instance] == 'lte-softmodem') or (self.air_interface[self.eNB_instance] == 'ocp-enb'): nodeB_prefix = 'e' else: nodeB_prefix = 'g' - if self.air_interface == 'nr-softmodem': + if self.air_interface[self.eNB_instance] == 'nr-softmodem': if ulschReceiveOK > 0: statMsg = nodeB_prefix + 'NB showed ' + str(ulschReceiveOK) + ' "ULSCH received ok" message(s)' logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m') diff --git a/ci-scripts/xml_files/fr1_multi_node_build.xml b/ci-scripts/xml_files/fr1_multi_node_build.xml index 0b7dce29d8..7b4eacef3a 100644 --- a/ci-scripts/xml_files/fr1_multi_node_build.xml +++ b/ci-scripts/xml_files/fr1_multi_node_build.xml @@ -33,27 +33,29 @@ Build_eNB Build eNB - -w USRP -c --eNB + -w USRP -c --eNB --ninja 0 0 + True - + WaitEndBuild_eNB Wait for end of Build eNB 0 0 - + Build_eNB Build gNB - -w USRP -c --gNB + -w USRP -c --gNB --ninja 1 1 + True - + WaitEndBuild_eNB Wait for end of Build gNB 1 diff --git a/ci-scripts/xml_files/gnb_usrp_build.xml b/ci-scripts/xml_files/gnb_usrp_build.xml index 97d6ef06f6..e2662180c5 100644 --- a/ci-scripts/xml_files/gnb_usrp_build.xml +++ b/ci-scripts/xml_files/gnb_usrp_build.xml @@ -34,7 +34,7 @@ TesteNB Build_eNB Build gNB (USRP) - --gNB -w USRP + --gNB -w USRP --ninja True diff --git a/ci-scripts/xml_files/nr_ue_usrp_build.xml b/ci-scripts/xml_files/nr_ue_usrp_build.xml index c3c842b85a..bc04efdb4b 100644 --- a/ci-scripts/xml_files/nr_ue_usrp_build.xml +++ b/ci-scripts/xml_files/nr_ue_usrp_build.xml @@ -34,7 +34,7 @@ TestUE Build_OAI_UE Build NR UE (USRP) - --nrUE -w USRP + --nrUE -w USRP --ninja false From e55f2aea0c629a52ed5551d36d1b8e53a466c35c Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Thu, 30 Jul 2020 16:21:51 +0200 Subject: [PATCH 538/553] CI: adding support for FR1 run of both eNB and gNB Signed-off-by: Raphael Defosseux --- .../enb.band7.tm1.fr1.25PRB.usrpb210.conf | 283 +++++++++++++++++ .../gnb.band78.tm1.fr1.106PRB.usrpb210.conf | 291 ++++++++++++++++++ ci-scripts/main.py | 18 +- ci-scripts/ran.py | 2 + ci-scripts/xml_files/fr1_multi_node_test.xml | 77 +++++ 5 files changed, 664 insertions(+), 7 deletions(-) create mode 100755 ci-scripts/conf_files/enb.band7.tm1.fr1.25PRB.usrpb210.conf create mode 100755 ci-scripts/conf_files/gnb.band78.tm1.fr1.106PRB.usrpb210.conf create mode 100644 ci-scripts/xml_files/fr1_multi_node_test.xml diff --git a/ci-scripts/conf_files/enb.band7.tm1.fr1.25PRB.usrpb210.conf b/ci-scripts/conf_files/enb.band7.tm1.fr1.25PRB.usrpb210.conf new file mode 100755 index 0000000000..085c5d0ab3 --- /dev/null +++ b/ci-scripts/conf_files/enb.band7.tm1.fr1.25PRB.usrpb210.conf @@ -0,0 +1,283 @@ +Active_eNBs = ( "eNB-Eurecom-LTEBox"); +# Asn1_verbosity, choice in: none, info, annoying +Asn1_verbosity = "none"; + +eNBs = +( + { + # real_time choice in {hard, rt-preempt, no} + real_time = "no"; + ////////// Identification parameters: + eNB_ID = 0xe01; + cell_type = "CELL_MACRO_ENB"; + eNB_name = "eNB-Eurecom-LTEBox"; + + // Tracking area code, 0x0000 and 0xfffe are reserved values + tracking_area_code = 1; + plmn_list = ( + { mcc = 222; mnc = 01; mnc_length = 2; } + ); + + tr_s_preference = "local_mac" + + ////////// Physical parameters: + + component_carriers = ( + { + node_function = "eNodeB_3GPP"; + node_timing = "synch_to_ext_device"; + node_synch_ref = 0; + nb_antenna_portsi = 1; + ue_TransmissionMode = 1; + frame_type = "FDD"; + tdd_config = 3; + tdd_config_s = 0; + prefix_type = "NORMAL"; + eutra_band = 7; + downlink_frequency = 2680000000L; + uplink_frequency_offset = -120000000; + + Nid_cell = 0; + N_RB_DL = 25; + Nid_cell_mbsfn = 0; + nb_antennas_tx = 1; + nb_antennas_rx = 1; + prach_root = 0; + tx_gain = 90; + rx_gain = 115; + pbch_repetition = "FALSE"; + + prach_config_index = 0; + prach_high_speed = "DISABLE"; + prach_zero_correlation = 1; + prach_freq_offset = 2; + + pucch_delta_shift = 1; + pucch_nRB_CQI = 0; + pucch_nCS_AN = 0; + pucch_n1_AN = 0; + pdsch_referenceSignalPower = -29; + pdsch_p_b = 0; + pusch_n_SB = 1; + pusch_enable64QAM = "DISABLE"; + pusch_hoppingMode = "interSubFrame"; + pusch_hoppingOffset = 0; + pusch_groupHoppingEnabled = "ENABLE"; + pusch_groupAssignment = 0; + pusch_sequenceHoppingEnabled = "DISABLE"; + pusch_nDMRS1 = 1; + phich_duration = "NORMAL"; + phich_resource = "ONESIXTH"; + srs_enable = "DISABLE"; +/* + srs_BandwidthConfig =; + srs_SubframeConfig =; + srs_ackNackST =; + srs_MaxUpPts =; +*/ + + pusch_p0_Nominal = -96; + pusch_alpha = "AL1"; + pucch_p0_Nominal = -96; + msg3_delta_Preamble = 6; + pucch_deltaF_Format1 = "deltaF2"; + pucch_deltaF_Format1b = "deltaF3"; + pucch_deltaF_Format2 = "deltaF0"; + pucch_deltaF_Format2a = "deltaF0"; + pucch_deltaF_Format2b = "deltaF0"; + + rach_numberOfRA_Preambles = 64; + rach_preamblesGroupAConfig = "DISABLE"; +/* + rach_sizeOfRA_PreamblesGroupA = ; + rach_messageSizeGroupA = ; + rach_messagePowerOffsetGroupB = ; +*/ + rach_powerRampingStep = 4; + rach_preambleInitialReceivedTargetPower = -108; + rach_preambleTransMax = 10; + rach_raResponseWindowSize = 10; + rach_macContentionResolutionTimer = 48; + rach_maxHARQ_Msg3Tx = 4; + + pcch_default_PagingCycle = 128; + pcch_nB = "oneT"; + bcch_modificationPeriodCoeff = 2; + ue_TimersAndConstants_t300 = 1000; + ue_TimersAndConstants_t301 = 1000; + ue_TimersAndConstants_t310 = 1000; + ue_TimersAndConstants_t311 = 10000; + ue_TimersAndConstants_n310 = 20; + ue_TimersAndConstants_n311 = 1; + + //Parameters for SIB18 + rxPool_sc_CP_Len = "normal"; + rxPool_sc_Period = "sf40"; + rxPool_data_CP_Len = "normal"; + rxPool_ResourceConfig_prb_Num = 20; + rxPool_ResourceConfig_prb_Start = 5; + rxPool_ResourceConfig_prb_End = 44; + rxPool_ResourceConfig_offsetIndicator_present = "prSmall"; + rxPool_ResourceConfig_offsetIndicator_choice = 0; + rxPool_ResourceConfig_subframeBitmap_present = "prBs40"; + rxPool_ResourceConfig_subframeBitmap_choice_bs_buf = "00000000000000000000"; + rxPool_ResourceConfig_subframeBitmap_choice_bs_size = 5; + rxPool_ResourceConfig_subframeBitmap_choice_bs_bits_unused = 0; +/* + rxPool_dataHoppingConfig_hoppingParameter = 0; + rxPool_dataHoppingConfig_numSubbands = "ns1"; + rxPool_dataHoppingConfig_rbOffset = 0; + rxPool_commTxResourceUC-ReqAllowed = "TRUE"; +*/ + // Parameters for SIB19 + discRxPool_cp_Len = "normal" + discRxPool_discPeriod = "rf32" + discRxPool_numRetx = 1; + discRxPool_numRepetition = 2; + discRxPool_ResourceConfig_prb_Num = 5; + discRxPool_ResourceConfig_prb_Start = 3; + discRxPool_ResourceConfig_prb_End = 21; + discRxPool_ResourceConfig_offsetIndicator_present = "prSmall"; + discRxPool_ResourceConfig_offsetIndicator_choice = 0; + discRxPool_ResourceConfig_subframeBitmap_present = "prBs40"; + discRxPool_ResourceConfig_subframeBitmap_choice_bs_buf = "f0ffffffff"; + discRxPool_ResourceConfig_subframeBitmap_choice_bs_size = 5; + discRxPool_ResourceConfig_subframeBitmap_choice_bs_bits_unused = 0; + + } + ); + + srb1_parameters : + { + # timer_poll_retransmit = (ms) [5, 10, 15, 20,... 250, 300, 350, ... 500] + timer_poll_retransmit = 80; + + # timer_reordering = (ms) [0,5, ... 100, 110, 120, ... ,200] + timer_reordering = 35; + + # timer_reordering = (ms) [0,5, ... 250, 300, 350, ... ,500] + timer_status_prohibit = 0; + + # poll_pdu = [4, 8, 16, 32 , 64, 128, 256, infinity(>10000)] + poll_pdu = 4; + + # poll_byte = (kB) [25,50,75,100,125,250,375,500,750,1000,1250,1500,2000,3000,infinity(>10000)] + poll_byte = 99999; + + # max_retx_threshold = [1, 2, 3, 4 , 6, 8, 16, 32] + max_retx_threshold = 4; + } + + # ------- SCTP definitions + SCTP : + { + # Number of streams to use in input/output + SCTP_INSTREAMS = 2; + SCTP_OUTSTREAMS = 2; + }; + + enable_measurement_reports = "yes"; + + ////////// MME parameters: + mme_ip_address = ( { ipv4 = "CI_MME_IP_ADDR"; + ipv6 = "192:168:30::17"; + active = "yes"; + preference = "ipv4"; + } + ); + + ///X2 + enable_x2 = "yes"; + t_reloc_prep = 1000; /* unit: millisecond */ + tx2_reloc_overall = 2000; /* unit: millisecond */ + + NETWORK_INTERFACES : + { + ENB_INTERFACE_NAME_FOR_S1_MME = "eth1"; + ENB_IPV4_ADDRESS_FOR_S1_MME = "CI_ENB_IP_ADDR"; + + ENB_INTERFACE_NAME_FOR_S1U = "eth1"; + ENB_IPV4_ADDRESS_FOR_S1U = "CI_ENB_IP_ADDR"; + ENB_PORT_FOR_S1U = 2152; # Spec 2152 + + ENB_IPV4_ADDRESS_FOR_X2C = "CI_ENB_IP_ADDR"; + ENB_PORT_FOR_X2C = 36422; # Spec 36422 + }; + + log_config : + { + global_log_level ="info"; + global_log_verbosity ="high"; + hw_log_level ="info"; + hw_log_verbosity ="medium"; + phy_log_level ="info"; + phy_log_verbosity ="medium"; + mac_log_level ="info"; + mac_log_verbosity ="high"; + rlc_log_level ="debug"; + rlc_log_verbosity ="high"; + pdcp_log_level ="info"; + pdcp_log_verbosity ="high"; + rrc_log_level ="info"; + rrc_log_verbosity ="medium"; + }; + + } +); + +MACRLCs = ( + { + num_cc = 1; + tr_s_preference = "local_L1"; + tr_n_preference = "local_RRC"; + phy_test_mode = 0; + puSch10xSnr = 160; + puCch10xSnr = 160; + } +); + +THREAD_STRUCT = ( + { + parallel_config = "PARALLEL_RU_L1_TRX_SPLIT"; + worker_config = "ENABLE"; + } +); + +L1s = ( + { + num_cc = 1; + tr_n_preference = "local_mac"; + } +); + +RUs = ( + { + local_rf = "yes" + nb_tx = 1 + nb_rx = 1 + att_tx = 0 + att_rx = 0; + bands = [7]; + max_pdschReferenceSignalPower = -27; + max_rxgain = 118; + eNB_instances = [0]; + } +); + +log_config : + { + global_log_level ="info"; + global_log_verbosity ="high"; + hw_log_level ="info"; + hw_log_verbosity ="medium"; + phy_log_level ="info"; + phy_log_verbosity ="medium"; + mac_log_level ="info"; + mac_log_verbosity ="high"; + rlc_log_level ="info"; + rlc_log_verbosity ="high"; + pdcp_log_level ="info"; + pdcp_log_verbosity ="high"; + rrc_log_level ="info"; + rrc_log_verbosity ="medium"; + }; diff --git a/ci-scripts/conf_files/gnb.band78.tm1.fr1.106PRB.usrpb210.conf b/ci-scripts/conf_files/gnb.band78.tm1.fr1.106PRB.usrpb210.conf new file mode 100755 index 0000000000..af72787752 --- /dev/null +++ b/ci-scripts/conf_files/gnb.band78.tm1.fr1.106PRB.usrpb210.conf @@ -0,0 +1,291 @@ +Active_gNBs = ( "gNB-Eurecom-5GNRBox"); +# Asn1_verbosity, choice in: none, info, annoying +Asn1_verbosity = "none"; + +gNBs = +( + { + ////////// Identification parameters: + gNB_ID = 0xe00; + + cell_type = "CELL_MACRO_GNB"; + gNB_name = "gNB-Eurecom-5GNRBox"; + + // Tracking area code, 0x0000 and 0xfffe are reserved values + tracking_area_code = 1; + plmn_list = ({mcc = 222; mnc = 01; mnc_length = 2;}); + + tr_s_preference = "local_mac" + + ////////// Physical parameters: + + ssb_SubcarrierOffset = 31; //0; + pdsch_AntennaPorts = 1; + + servingCellConfigCommon = ( + { + #spCellConfigCommon + + physCellId = 0; + +# downlinkConfigCommon + #frequencyInfoDL + # this is 3600 MHz + 84 PRBs@30kHz SCS (same as initial BWP) + absoluteFrequencySSB = 641272; //641032; #641968; 641968=start of ssb at 3600MHz + 82 RBs 641032=center of SSB at center of cell + dl_frequencyBand = 78; + # this is 3600 MHz + dl_absoluteFrequencyPointA = 640000; + #scs-SpecificCarrierList + dl_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + dl_subcarrierSpacing = 1; + dl_carrierBandwidth = 106; + #initialDownlinkBWP + #genericParameters + # this is RBstart=84,L=13 (275*(L-1))+RBstart + initialDLBWPlocationAndBandwidth = 6366; //28875; //6366; #6407; #3384; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialDLBWPsubcarrierSpacing = 1; + #pdcch-ConfigCommon + initialDLBWPcontrolResourceSetZero = 0; + initialDLBWPsearchSpaceZero = 0; + #pdsch-ConfigCommon + #pdschTimeDomainAllocationList (up to 16 entries) + initialDLBWPk0_0 = 0; + #initialULBWPmappingType + #0=typeA,1=typeB + initialDLBWPmappingType_0 = 0; + #this is SS=1,L=13 + initialDLBWPstartSymbolAndLength_0 = 40; + + initialDLBWPk0_1 = 0; + initialDLBWPmappingType_1 = 0; + #this is SS=2,L=12 + initialDLBWPstartSymbolAndLength_1 = 53; + + initialDLBWPk0_2 = 0; + initialDLBWPmappingType_2 = 0; + #this is SS=1,L=12 + initialDLBWPstartSymbolAndLength_2 = 54; + + initialDLBWPk0_3 = 0; + initialDLBWPmappingType_3 = 0; + #this is SS=1,L=4 //5 (4 is for 43, 5 is for 57) + initialDLBWPstartSymbolAndLength_3 = 57; //43; //57; + #uplinkConfigCommon + #frequencyInfoUL + ul_frequencyBand = 78; + #scs-SpecificCarrierList + ul_offstToCarrier = 0; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + ul_subcarrierSpacing = 1; + ul_carrierBandwidth = 106; + pMax = 20; + #initialUplinkBWP + #genericParameters + initialULBWPlocationAndBandwidth = 6366; //28875; //6366; #6407; #3384; +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + initialULBWPsubcarrierSpacing = 1; + #rach-ConfigCommon + #rach-ConfigGeneric + prach_ConfigurationIndex = 98; +#prach_msg1_FDM +#0 = one, 1=two, 2=four, 3=eight + prach_msg1_FDM = 0; + prach_msg1_FrequencyStart = 0; + zeroCorrelationZoneConfig = 13; + preambleReceivedTargetPower = -118; +#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200) + preambleTransMax = 6; +#powerRampingStep +# 0=dB0,1=dB2,2=dB4,3=dB6 + powerRampingStep = 1; +#ra_ReponseWindow +#1,2,4,8,10,20,40,80 + ra_ResponseWindow = 5; +#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR +#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen + ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4; +#oneHalf (0..15) 4,8,12,16,...60,64 + ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 14; //15; +#ra_ContentionResolutionTimer +#(0..7) 8,16,24,32,40,48,56,64 + ra_ContentionResolutionTimer = 7; + rsrp_ThresholdSSB = 19; +#prach-RootSequenceIndex_PR +#1 = 839, 2 = 139 + prach_RootSequenceIndex_PR = 2; + prach_RootSequenceIndex = 1; + # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex + # + msg1_SubcarrierSpacing = 1, + +# restrictedSetConfig +# 0=unrestricted, 1=restricted type A, 2=restricted type B + restrictedSetConfig = 0, + # pusch-ConfigCommon (up to 16 elements) + initialULBWPk2_0 = 2; + initialULBWPmappingType_0 = 1 + # this is SS=0 L=11 + initialULBWPstartSymbolAndLength_0 = 55; + + initialULBWPk2_1 = 2; + initialULBWPmappingType_1 = 1; + # this is SS=0 L=12 + initialULBWPstartSymbolAndLength_1 = 69; + + initialULBWPk2_2 = 7; + initialULBWPmappingType_2 = 1; + # this is SS=10 L=4 + initialULBWPstartSymbolAndLength_2 = 52; + + msg3_DeltaPreamble = 1; + p0_NominalWithGrant =-90; + +# pucch-ConfigCommon setup : +# pucchGroupHopping +# 0 = neither, 1= group hopping, 2=sequence hopping + pucchGroupHopping = 0; + hoppingId = 40; + p0_nominal = -90; +# ssb_PositionsInBurs_BitmapPR +# 1=short, 2=medium, 3=long + ssb_PositionsInBurst_PR = 2; + ssb_PositionsInBurst_Bitmap = 1; #0x80; + +# ssb_periodicityServingCell +# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1 + ssb_periodicityServingCell = 2; + +# dmrs_TypeA_position +# 0 = pos2, 1 = pos3 + dmrs_TypeA_Position = 0; + +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + subcarrierSpacing = 1; + + + #tdd-UL-DL-ConfigurationCommon +# subcarrierSpacing +# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120 + referenceSubcarrierSpacing = 1; + # pattern1 + # dl_UL_TransmissionPeriodicity + # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10 + dl_UL_TransmissionPeriodicity = 6; + nrofDownlinkSlots = 7; //8; //7; + nrofDownlinkSymbols = 6; //0; //6; + nrofUplinkSlots = 2; + nrofUplinkSymbols = 4; //0; //4; + + ssPBCH_BlockPower = 10; + } + + ); + + + # ------- SCTP definitions + SCTP : + { + # Number of streams to use in input/output + SCTP_INSTREAMS = 2; + SCTP_OUTSTREAMS = 2; + }; + + + ////////// MME parameters: + mme_ip_address = ( { ipv4 = "CI_MME_IP_ADDR"; + ipv6 = "192:168:30::17"; + active = "yes"; + preference = "ipv4"; + } + ); + + ///X2 + enable_x2 = "yes"; + t_reloc_prep = 1000; /* unit: millisecond */ + tx2_reloc_overall = 2000; /* unit: millisecond */ + target_enb_x2_ip_address = ( + { ipv4 = "CI_FR1_CTL_ENB_IP_ADDR"; + ipv6 = "192:168:30::17"; + preference = "ipv4"; + } + ); + + NETWORK_INTERFACES : + { + + GNB_INTERFACE_NAME_FOR_S1_MME = "eth0"; + GNB_IPV4_ADDRESS_FOR_S1_MME = "CI_GNB_IP_ADDR"; + GNB_INTERFACE_NAME_FOR_S1U = "eth0"; + GNB_IPV4_ADDRESS_FOR_S1U = "CI_GNB_IP_ADDR"; + GNB_PORT_FOR_S1U = 2152; # Spec 2152 + GNB_IPV4_ADDRESS_FOR_X2C = "CI_GNB_IP_ADDR"; + GNB_PORT_FOR_X2C = 36422; # Spec 36422 + }; + } +); + +MACRLCs = ( + { + num_cc = 1; + tr_s_preference = "local_L1"; + tr_n_preference = "local_RRC"; + } +); + +L1s = ( + { + num_cc = 1; + tr_n_preference = "local_mac"; + } +); + +RUs = ( + { + local_rf = "yes" + nb_tx = 1 + nb_rx = 1 + att_tx = 0 + att_rx = 0; + bands = [7]; + max_pdschReferenceSignalPower = -27; + max_rxgain = 114; + eNB_instances = [0]; + clock_src = "internal"; + } +); + +THREAD_STRUCT = ( + { + #three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT" + //parallel_config = "PARALLEL_RU_L1_TRX_SPLIT"; + parallel_config = "PARALLEL_SINGLE_THREAD"; + #two option for worker "WORKER_DISABLE" or "WORKER_ENABLE" + worker_config = "WORKER_ENABLE"; + } +); + + log_config : + { + global_log_level ="info"; + global_log_verbosity ="medium"; + hw_log_level ="info"; + hw_log_verbosity ="medium"; + phy_log_level ="info"; + phy_log_verbosity ="medium"; + mac_log_level ="info"; + mac_log_verbosity ="high"; + rlc_log_level ="info"; + rlc_log_verbosity ="medium"; + pdcp_log_level ="info"; + pdcp_log_verbosity ="medium"; + rrc_log_level ="info"; + rrc_log_verbosity ="medium"; + }; + diff --git a/ci-scripts/main.py b/ci-scripts/main.py index 660f068c2c..bec0489dd0 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -113,7 +113,7 @@ class OaiCiTest(): self.UEIPAddress = '' self.UEUserName = '' self.UEPassword = '' - self.UE_instance = '' + self.UE_instance = 0 self.UESourceCodePath = '' self.UELogFile = '' self.Build_OAI_UE_args = '' @@ -3172,7 +3172,7 @@ def GetParametersFromXML(action): if action == 'Terminate_eNB': eNB_instance=test.findtext('eNB_instance') - if (RAN.eNB_instance is None): + if (eNB_instance is None): RAN.eNB_instance=0 else: RAN.eNB_instance=int(eNB_instance) @@ -3213,9 +3213,11 @@ def GetParametersFromXML(action): if action == 'Initialize_OAI_UE': CiTestObj.Initialize_OAI_UE_args = test.findtext('Initialize_OAI_UE_args') - CiTestObj.UE_instance = test.findtext('UE_instance') - if (CiTestObj.UE_instance is None): - CiTestObj.UE_instance = '0' + UE_instance = test.findtext('UE_instance') + if (UE_instance is None): + CiTestObj.UE_instance = 0 + else: + CiTestObj.UE_instance = UE_instance #local variable air_interface air_interface = test.findtext('air_interface') @@ -3228,9 +3230,11 @@ def GetParametersFromXML(action): logging.error('OCP UE -- NOT SUPPORTED') if action == 'Terminate_OAI_UE': - RAN.eNB_instance=test.findtext('UE_instance') - if (CiTestObj.UE_instance is None): + UE_instance=test.findtext('UE_instance') + if (UE_instance is None): CiTestObj.UE_instance = '0' + else: + CiTestObj.UE_instance = int(UE_instance) #local variable air_interface air_interface = test.findtext('air_interface') diff --git a/ci-scripts/ran.py b/ci-scripts/ran.py index 054b92a181..ab72739bd2 100644 --- a/ci-scripts/ran.py +++ b/ci-scripts/ran.py @@ -404,9 +404,11 @@ class RANManagement(): localMmeIpAddr = self.epcObj.MmeIPAddress mySSH.command('sed -i -e \'s/CI_MME_IP_ADDR/' + localMmeIpAddr + '/\' ' + ci_full_config_file, '\$', 2); mySSH.command('sed -i -e \'s/CI_ENB_IP_ADDR/' + lIpAddr + '/\' ' + ci_full_config_file, '\$', 2); + mySSH.command('sed -i -e \'s/CI_GNB_IP_ADDR/' + lIpAddr + '/\' ' + ci_full_config_file, '\$', 2); mySSH.command('sed -i -e \'s/CI_RCC_IP_ADDR/' + self.eNBIPAddress + '/\' ' + ci_full_config_file, '\$', 2); mySSH.command('sed -i -e \'s/CI_RRU1_IP_ADDR/' + self.eNB1IPAddress + '/\' ' + ci_full_config_file, '\$', 2); mySSH.command('sed -i -e \'s/CI_RRU2_IP_ADDR/' + self.eNB2IPAddress + '/\' ' + ci_full_config_file, '\$', 2); + mySSH.command('sed -i -e \'s/CI_FR1_CTL_ENB_IP_ADDR/' + self.eNBIPAddress + '/\' ' + ci_full_config_file, '\$', 2); if self.flexranCtrlInstalled and self.flexranCtrlStarted: mySSH.command('sed -i -e \'s/FLEXRAN_ENABLED.*;/FLEXRAN_ENABLED = "yes";/\' ' + ci_full_config_file, '\$', 2); else: diff --git a/ci-scripts/xml_files/fr1_multi_node_test.xml b/ci-scripts/xml_files/fr1_multi_node_test.xml new file mode 100644 index 0000000000..31a703793f --- /dev/null +++ b/ci-scripts/xml_files/fr1_multi_node_test.xml @@ -0,0 +1,77 @@ + + + test-fr1-tm1 + Test-FR1-TM1 + tasks + 1 + + 030000 + 040000 + 000001 + 070000 + 070001 + + + + + + Initialize_eNB + Initialize eNB + -O ci-scripts/conf_files/enb.band7.tm1.fr1.25PRB.usrpb210.conf + 0 + 0 + lte + + + + Initialize_eNB + Initialize gNB + -O ci-scripts/conf_files/gnb.band78.tm1.fr1.106PRB.usrpb210.conf + 1 + 1 + nr + + + + IdleSleep + Sleep + 30 + + + + Terminate_eNB + Terminate eNB + 0 + 0 + + + + Terminate_eNB + Terminate eNB + 1 + 1 + + + + From 765ba2eba3311e70ea42b89d88c79fe34861e6ff Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Fri, 31 Jul 2020 09:51:01 +0200 Subject: [PATCH 539/553] CI: last typo Signed-off-by: Raphael Defosseux --- ci-scripts/main.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ci-scripts/main.py b/ci-scripts/main.py index bec0489dd0..7499b53ce0 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -3143,7 +3143,7 @@ def GetParametersFromXML(action): RAN.Build_eNB_args=test.findtext('Build_eNB_args') eNB_instance=test.findtext('eNB_instance') if (eNB_instance is None): - RAN.eNB_instance='0' + RAN.eNB_instance=0 else: RAN.eNB_instance=int(eNB_instance) RAN.eNB_serverId=test.findtext('eNB_serverId') @@ -3395,7 +3395,7 @@ if re.match('^TerminateeNB$', mode, re.IGNORECASE): HELP.GenericHelp(CONST.Version) sys.exit('Insufficient Parameter') RAN.eNB_serverId='0' - RAN.eNB_instance='0' + RAN.eNB_instance=0 RAN.eNBSourceCodePath='/tmp/' RAN.TerminateeNB() elif re.match('^TerminateUE$', mode, re.IGNORECASE): From f00ddc79726439a68a3b79a92c2b0761b905a25d Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Fri, 31 Jul 2020 10:20:38 +0200 Subject: [PATCH 540/553] CI: add OCP pipeline trigger to master pipeline Signed-off-by: Raphael Defosseux --- ci-scripts/Jenkinsfile-gitlab | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/ci-scripts/Jenkinsfile-gitlab b/ci-scripts/Jenkinsfile-gitlab index 8dfa5c4ec4..c3b997a4e8 100644 --- a/ci-scripts/Jenkinsfile-gitlab +++ b/ci-scripts/Jenkinsfile-gitlab @@ -66,7 +66,8 @@ pipeline { "Test-IF4p5-TDD-Band38-Multi-RRU", "Test-eNB-OAI-UE-FDD-Band7", "Test-Mono-FDD-Band13-X2-HO", - "Test-TDD-Band78-gNB-NR-UE" + "Test-TDD-Band78-gNB-NR-UE", + "Test-OCP-FDD-Band7" ]) ansiColor('xterm') } @@ -683,6 +684,25 @@ pipeline { } } } + stage ("Test OAI OCP-eNB - FDD - Band 7 - B210") { + steps { + script { + triggerSlaveJob ('OCPeNB-FDD-Band7-B210', 'Test-OCP-FDD-Band7') + } + } + post { + always { + script { + finalizeSlaveJob('OCPeNB-FDD-Band7-B210') + } + } + failure { + script { + currentBuild.result = 'FAILURE' + } + } + } + } } post { always { From a6cd5b2d34a198e1f261e7042c0389b8d75d8d1c Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Fri, 31 Jul 2020 11:54:29 +0200 Subject: [PATCH 541/553] CI: no more usage of 'daemon' for launch soft-modem executables Signed-off-by: Raphael Defosseux --- ci-scripts/main.py | 4 +--- ci-scripts/ran.py | 11 ++--------- doc/TESTING_GNB_W_COTS_UE.md | 6 +++--- 3 files changed, 6 insertions(+), 15 deletions(-) diff --git a/ci-scripts/main.py b/ci-scripts/main.py index 7499b53ce0..32742f3e88 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -387,9 +387,7 @@ class OaiCiTest(): while (doOutterLoop): SSH.command('cd ' + self.UESourceCodePath + '/cmake_targets/ran_build/build', '\$', 5) SSH.command('echo ' + self.UEPassword + ' | sudo -S rm -Rf ' + self.UESourceCodePath + '/cmake_targets/ue_' + self.testCase_id + '.log', '\$', 5) - #use nohup instead of daemon - #SSH.command('echo ' + self.UEPassword + ' | sudo -S -E daemon --inherit --unsafe --name=ue' + str(self.UE_instance) + '_daemon --chdir=' + self.UESourceCodePath + '/cmake_targets/ran_build/build -o ' + self.UESourceCodePath + '/cmake_targets/ue_' + self.testCase_id + '.log ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5) - SSH.command('echo $USER; nohup sudo ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh' + ' > ' + self.UESourceCodePath + '/cmake_targets/ue_' + self.testCase_id + '.log ' + ' 2>&1 &', self.UEUserName, 5) + SSH.command('echo $USER; nohup sudo -E ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh' + ' > ' + self.UESourceCodePath + '/cmake_targets/ue_' + self.testCase_id + '.log ' + ' 2>&1 &', self.UEUserName, 5) time.sleep(6) SSH.command('cd ../..', '\$', 5) doLoop = True diff --git a/ci-scripts/ran.py b/ci-scripts/ran.py index ab72739bd2..936eeb3227 100644 --- a/ci-scripts/ran.py +++ b/ci-scripts/ran.py @@ -205,9 +205,8 @@ class RANManagement(): if self.backgroundBuild: mySSH.command('echo "./build_oai ' + self.Build_eNB_args + '" > ./my-lte-softmodem-build.sh', '\$', 5) mySSH.command('chmod 775 ./my-lte-softmodem-build.sh', '\$', 5) - #mySSH.command('echo ' + lPassWord + ' | sudo -S -E daemon --inherit --unsafe --name=build_enb_daemon --chdir=' + lSourcePath + '/cmake_targets -o ' + lSourcePath + '/cmake_targets/compile_oai_enb.log ./my-lte-softmodem-build.sh', '\$', 5) mySSH.command('echo ' + lPassWord + ' | sudo -S ls', '\$', 5) - mySSH.command('echo $USER; nohup sudo ./my-lte-softmodem-build.sh' + ' > ' + lSourcePath + '/cmake_targets/compile_oai_enb.log ' + ' 2>&1 &', lUserName, 5) + mySSH.command('echo $USER; nohup sudo -E ./my-lte-softmodem-build.sh' + ' > ' + lSourcePath + '/cmake_targets/compile_oai_enb.log ' + ' 2>&1 &', lUserName, 5) mySSH.close() if self.htmlObj is not None: self.htmlObj.CreateHtmlTestRow(self.Build_eNB_args, 'OK', CONST.ALL_PROCESSES_OK) @@ -434,12 +433,7 @@ class RANManagement(): mySSH.command('echo "ulimit -c unlimited && ./ran_build/build/' + self.air_interface[self.eNB_instance] + ' -O ' + lSourcePath + '/' + ci_full_config_file + extra_options + '" > ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh', '\$', 5) mySSH.command('chmod 775 ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh', '\$', 5) mySSH.command('echo ' + lPassWord + ' | sudo -S rm -Rf enb_' + self.testCase_id + '.log', '\$', 5) - mySSH.command('hostnamectl','\$', 5) - result = re.search('CentOS Linux 7', mySSH.getBefore()) - if result is not None: - mySSH.command('echo $USER; nohup sudo ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh > ' + lSourcePath + '/cmake_targets/enb_' + self.testCase_id + '.log 2>&1 &', lUserName, 10) - else: - mySSH.command('echo ' + lPassWord + ' | sudo -S -E daemon --inherit --unsafe --name=enb' + str(self.eNB_instance) + '_daemon --chdir=' + lSourcePath + '/cmake_targets -o ' + lSourcePath + '/cmake_targets/enb_' + self.testCase_id + '.log ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh', '\$', 5) + mySSH.command('echo $USER; nohup sudo -E ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh > ' + lSourcePath + '/cmake_targets/enb_' + self.testCase_id + '.log 2>&1 &', lUserName, 10) self.eNBLogFiles[int(self.eNB_instance)] = 'enb_' + self.testCase_id + '.log' if extra_options != '': self.eNBOptions[int(self.eNB_instance)] = extra_options @@ -580,7 +574,6 @@ class RANManagement(): mySSH.command('stdbuf -o0 ps -aux | grep --color=never -e softmodem -e ocp-enb | grep -v grep', '\$', 5) result = re.search('(-softmodem|ocp)', mySSH.getBefore()) if result is not None: - mySSH.command('echo ' + lPassWord + ' | sudo -S daemon --name=enb' + str(self.eNB_instance) + '_daemon --stop', '\$', 5) mySSH.command('echo ' + lPassWord + ' | sudo -S killall --signal SIGINT -r .*-softmodem ocp-enb || true', '\$', 5) time.sleep(10) mySSH.command('stdbuf -o0 ps -aux | grep --color=never -e softmodem -e ocp-enb | grep -v grep', '\$', 5) diff --git a/doc/TESTING_GNB_W_COTS_UE.md b/doc/TESTING_GNB_W_COTS_UE.md index e507050239..51fdf25f77 100644 --- a/doc/TESTING_GNB_W_COTS_UE.md +++ b/doc/TESTING_GNB_W_COTS_UE.md @@ -146,11 +146,11 @@ These files have to be updated manually to set the IP addresses and frequency. { GNB_INTERFACE_NAME_FOR_S1_MME = "eth0"; - GNB_IPV4_ADDRESS_FOR_S1_MME = "**YOUR_ENB_IP_ADDR**"; + GNB_IPV4_ADDRESS_FOR_S1_MME = "**YOUR_GNB_IP_ADDR**"; GNB_INTERFACE_NAME_FOR_S1U = "eth0"; - GNB_IPV4_ADDRESS_FOR_S1U = "**YOUR_ENB_IP_ADDR**"; + GNB_IPV4_ADDRESS_FOR_S1U = "**YOUR_GNB_IP_ADDR**"; GNB_PORT_FOR_S1U = 2152; # Spec 2152 - GNB_IPV4_ADDRESS_FOR_X2C = "**YOUR_ENB_IP_ADDR**"; + GNB_IPV4_ADDRESS_FOR_X2C = "**YOUR_GNB_IP_ADDR**"; GNB_PORT_FOR_X2C = 36422; # Spec 36422 }; From 3ec2a46fd37c33bfba0509036e3719a47dccc761 Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Fri, 31 Jul 2020 14:40:52 +0200 Subject: [PATCH 542/553] CI: fix clock management in FR1 conf files Signed-off-by: Raphael Defosseux --- .../conf_files/enb.band7.tm1.fr1.25PRB.usrpb210.conf | 3 ++- .../conf_files/gnb.band78.tm1.fr1.106PRB.usrpb210.conf | 10 +++++----- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/ci-scripts/conf_files/enb.band7.tm1.fr1.25PRB.usrpb210.conf b/ci-scripts/conf_files/enb.band7.tm1.fr1.25PRB.usrpb210.conf index 085c5d0ab3..5b2c90a714 100755 --- a/ci-scripts/conf_files/enb.band7.tm1.fr1.25PRB.usrpb210.conf +++ b/ci-scripts/conf_files/enb.band7.tm1.fr1.25PRB.usrpb210.conf @@ -27,7 +27,7 @@ eNBs = node_function = "eNodeB_3GPP"; node_timing = "synch_to_ext_device"; node_synch_ref = 0; - nb_antenna_portsi = 1; + nb_antenna_ports = 1; ue_TransmissionMode = 1; frame_type = "FDD"; tdd_config = 3; @@ -261,6 +261,7 @@ RUs = ( max_pdschReferenceSignalPower = -27; max_rxgain = 118; eNB_instances = [0]; + clock_src = "external"; } ); diff --git a/ci-scripts/conf_files/gnb.band78.tm1.fr1.106PRB.usrpb210.conf b/ci-scripts/conf_files/gnb.band78.tm1.fr1.106PRB.usrpb210.conf index af72787752..92af74c300 100755 --- a/ci-scripts/conf_files/gnb.band78.tm1.fr1.106PRB.usrpb210.conf +++ b/ci-scripts/conf_files/gnb.band78.tm1.fr1.106PRB.usrpb210.conf @@ -98,7 +98,7 @@ gNBs = prach_msg1_FDM = 0; prach_msg1_FrequencyStart = 0; zeroCorrelationZoneConfig = 13; - preambleReceivedTargetPower = -118; + preambleReceivedTargetPower = -100; #preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200) preambleTransMax = 6; #powerRampingStep @@ -183,7 +183,7 @@ gNBs = nrofUplinkSlots = 2; nrofUplinkSymbols = 4; //0; //4; - ssPBCH_BlockPower = 10; + ssPBCH_BlockPower = -25; } ); @@ -257,15 +257,15 @@ RUs = ( max_pdschReferenceSignalPower = -27; max_rxgain = 114; eNB_instances = [0]; - clock_src = "internal"; + clock_src = "external"; } ); THREAD_STRUCT = ( { #three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT" - //parallel_config = "PARALLEL_RU_L1_TRX_SPLIT"; - parallel_config = "PARALLEL_SINGLE_THREAD"; + parallel_config = "PARALLEL_RU_L1_TRX_SPLIT"; + //parallel_config = "PARALLEL_SINGLE_THREAD"; #two option for worker "WORKER_DISABLE" or "WORKER_ENABLE" worker_config = "WORKER_ENABLE"; } From a12266b94f69c2b8158f37d269b1826cb1f630b1 Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Fri, 31 Jul 2020 14:43:05 +0200 Subject: [PATCH 543/553] DOC: point now to CI-used conf files Signed-off-by: Raphael Defosseux --- doc/TESTING_GNB_W_COTS_UE.md | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/doc/TESTING_GNB_W_COTS_UE.md b/doc/TESTING_GNB_W_COTS_UE.md index 51fdf25f77..d4381a1ca5 100644 --- a/doc/TESTING_GNB_W_COTS_UE.md +++ b/doc/TESTING_GNB_W_COTS_UE.md @@ -82,10 +82,8 @@ Some config examples can be found in the following folder: https://gitlab.eurecom.fr/oai/openairinterface5g/-/tree/develop/targets/PROJECTS/GENERIC-LTE-EPC/CONF Also base config files can be found here: -[enb conf file](https://gitlab.eurecom.fr/oai/openairinterface5g/-/blob/rh_doc_update_3/doc/testing_gnb_w_cots_ue_resources/enb.conf) -[gnb conf file](https://gitlab.eurecom.fr/oai/openairinterface5g/-/blob/rh_doc_update_3/doc/testing_gnb_w_cots_ue_resources/gnb.conf) - -TO DO : attach base confif files +[enb conf file](../ci-scripts/conf_files/enb.band7.tm1.fr1.25PRB.usrpb210.conf) +[gnb conf file](../ci-scripts/conf_files/gnb.band78.tm1.fr1.106PRB.usrpb210.conf) These files have to be updated manually to set the IP addresses and frequency. From def42f92d8ccb38b889fdc149957b6a54b75046d Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Fri, 31 Jul 2020 15:07:26 +0200 Subject: [PATCH 544/553] Update TESTING_GNB_W_COTS_UE.md --- doc/TESTING_GNB_W_COTS_UE.md | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/doc/TESTING_GNB_W_COTS_UE.md b/doc/TESTING_GNB_W_COTS_UE.md index d4381a1ca5..d2f167164a 100644 --- a/doc/TESTING_GNB_W_COTS_UE.md +++ b/doc/TESTING_GNB_W_COTS_UE.md @@ -1,4 +1,5 @@ -STATUS 2020/06/26 : information is up to date, but under continuous improvement +STATUS 2020/07/30 : under continuous improvement ; updated the configuration files links with CI approved reference files + ## Table of Contents ## @@ -78,15 +79,17 @@ https://github.com/OPENAIRINTERFACE/openair-epc-fed/blob/master-documentation/do Each component (EPC, eNB, gNB) has its own configuration file. These config files are passed as arguments of the run command line, using the option -O \ -Some config examples can be found in the following folder: -https://gitlab.eurecom.fr/oai/openairinterface5g/-/tree/develop/targets/PROJECTS/GENERIC-LTE-EPC/CONF - -Also base config files can be found here: +The **REFERENCE** files for eNB and gNB, **used by the CI**, can be found here: [enb conf file](../ci-scripts/conf_files/enb.band7.tm1.fr1.25PRB.usrpb210.conf) [gnb conf file](../ci-scripts/conf_files/gnb.band78.tm1.fr1.106PRB.usrpb210.conf) These files have to be updated manually to set the IP addresses and frequency. + +**ATTENTION** : an **EXTERNAL** clock is used to sync the eNB and gNB, +whether the clock is internal or external is defined in the configuration files (!! details needed !!) + + 1- In the **eNB configuration file** : - look for MME IP address, and update the **ipv4 field** with the IP address of the **EPC** server ``` @@ -126,7 +129,7 @@ These files have to be updated manually to set the IP addresses and frequency. } ); ``` -- look for X2 IP address, and update the **4 fields** with the IP address of the **eNB** server (notice : even if -in principle- S1 MME is not required for gNB setting) +- look for X2 IP address, and update the **4 fields** with the IP address of the **eNB** server / **gNB** server as below (notice : even if -in principle- S1 MME is not required for gNB setting) ``` ///X2 From b829d3c9f759d46feef72a16c4bfa6849e5e0e84 Mon Sep 17 00:00:00 2001 From: laurent Date: Fri, 31 Jul 2020 16:04:24 +0200 Subject: [PATCH 545/553] add exit trace and fix a gcc warning --- executables/main-fs6.c | 2 +- executables/main-ocp.c | 2 ++ executables/split_headers.h | 2 ++ 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/executables/main-fs6.c b/executables/main-fs6.c index ffa44bd978..d2d64d0959 100644 --- a/executables/main-fs6.c +++ b/executables/main-fs6.c @@ -401,7 +401,7 @@ void sendFs6Ul(PHY_VARS_eNB *eNB, int UE_id, int harq_pid, int segmentID, int16_ hULUE(newUDPheader)->O_ACK=eNB->ulsch[UE_id]->harq_processes[harq_pid]->O_ACK; memcpy(hULUE(newUDPheader)->o_ACK, eNB->ulsch[UE_id]->harq_processes[harq_pid]->o_ACK, sizeof(eNB->ulsch[UE_id]->harq_processes[harq_pid]->o_ACK)); - hULUE(newUDPheader)->ta=lte_est_timing_advance_pusch(eNB, UE_id); + hULUE(newUDPheader)->ta=lte_est_timing_advance_pusch(&eNB->frame_parms, eNB->pusch_vars[UE_id]->drs_ch_estimates_time); hULUE(newUDPheader)->segment=segmentID; memcpy(hULUE(newUDPheader)->o, eNB->ulsch[UE_id]->harq_processes[harq_pid]->o, sizeof(eNB->ulsch[UE_id]->harq_processes[harq_pid]->o)); diff --git a/executables/main-ocp.c b/executables/main-ocp.c index e4e42b4f23..204067b229 100644 --- a/executables/main-ocp.c +++ b/executables/main-ocp.c @@ -97,6 +97,7 @@ void exit_function(const char *file, const char *function, const int line, const if (s != NULL) { printf("%s:%d %s() Exiting OAI softmodem: %s\n",file,line, function, s); } + softmodem_printresources(0,(telnet_printfunc_t)printf); close_log_mem(); oai_exit = 1; @@ -1167,6 +1168,7 @@ int main ( int argc, char **argv ) { T_Config_Init(); #endif configure_linux(); + set_softmodem_sighandler(); cpuf=get_cpu_freq_GHz(); set_taus_seed (0); diff --git a/executables/split_headers.h b/executables/split_headers.h index 4e328f74c4..985b1b7dae 100644 --- a/executables/split_headers.h +++ b/executables/split_headers.h @@ -28,6 +28,7 @@ #include #include #include +#include #define CU_PORT "7878" #define DU_PORT "8787" @@ -325,5 +326,6 @@ void fep_full(RU_t *ru, int subframe); void feptx_prec(RU_t *ru,int frame,int subframe); void feptx_ofdm(RU_t *ru, int frame, int subframe); void oai_subframe_ind(uint16_t sfn, uint16_t sf); +void softmodem_printresources(int sig, telnet_printfunc_t pf); extern uint16_t sf_ahead; #endif From de64484fe5bc6132fd13ff6c343cbe682adbe9f6 Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Fri, 31 Jul 2020 16:11:13 +0200 Subject: [PATCH 546/553] Update TESTING_GNB_W_COTS_UE.md --- doc/TESTING_GNB_W_COTS_UE.md | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/doc/TESTING_GNB_W_COTS_UE.md b/doc/TESTING_GNB_W_COTS_UE.md index d2f167164a..a16b4dbe13 100644 --- a/doc/TESTING_GNB_W_COTS_UE.md +++ b/doc/TESTING_GNB_W_COTS_UE.md @@ -216,26 +216,20 @@ Execute: ``` -For example: -``` -~/openairinterface5g/cmake_targets/ran_build/build$ sudo ./lte-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.band7.tm1.50PRB.usrpb210.conf | tee mylogfile.log -``` - - - **gNB** (on the gNB host) Execute: ``` -~/openairinterface5g/cmake_targets/ran_build/build$ sudo ./nr-softmodem -O **YOUR_GNB_CONF_FILE** | tee **YOUR_LOG_FILE** +~/openairinterface5g/cmake_targets/ran_build/build$ sudo ./nr-softmodem -O **YOUR_GNB_CONF_FILE** -E | tee **YOUR_LOG_FILE** ``` -For example: -``` -~/openairinterface5g/cmake_targets/ran_build/build$ sudo ./nr-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf | tee mylogfile.log -``` +**ATTENTION** : for the gNB execution, +The -E option is required to enable the tri-quarter sampling rate when using a B2xx serie USRP +The -E opton is not needed when using a a N300 USRP + ## Test Case From 0e0627736045e29276fdeb030e8f24c41db06aaa Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Fri, 31 Jul 2020 16:14:34 +0200 Subject: [PATCH 547/553] CI: enabling 3/4 sampling rate when running gNB on B210 Signed-off-by: Raphael Defosseux --- ci-scripts/xml_files/fr1_multi_node_test.xml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ci-scripts/xml_files/fr1_multi_node_test.xml b/ci-scripts/xml_files/fr1_multi_node_test.xml index 31a703793f..d35dd74c2b 100644 --- a/ci-scripts/xml_files/fr1_multi_node_test.xml +++ b/ci-scripts/xml_files/fr1_multi_node_test.xml @@ -46,8 +46,8 @@ Initialize_eNB - Initialize gNB - -O ci-scripts/conf_files/gnb.band78.tm1.fr1.106PRB.usrpb210.conf + Initialize gNB (3/4 sampling rate) + -O ci-scripts/conf_files/gnb.band78.tm1.fr1.106PRB.usrpb210.conf -E 1 1 nr From 381fa7234abb56f93f916dbba6608f23199613d1 Mon Sep 17 00:00:00 2001 From: laurent Date: Mon, 3 Aug 2020 09:20:25 +0200 Subject: [PATCH 548/553] remove need to set /data/opencells-ran/../oaiCloneFapi before calling cmake --- cmake_targets/CMakeLists.txt | 6 +++++- executables/main-ocp.c | 1 - 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index 0b60172747..5db0b1f021 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -27,6 +27,10 @@ cmake_minimum_required (VERSION 3.0) # Base directories, compatible with legacy OAI building # ######################################################### set (OPENAIR_DIR $ENV{OPENAIR_DIR}) +if("${OPENAIR_DIR}" STREQUAL "") + string(REGEX REPLACE "/cmake_targets.*$" "" OPENAIR_DIR ${CMAKE_CURRENT_BINARY_DIR}) +endif() + set (NFAPI_DIR ${OPENAIR_DIR}/nfapi/open-nFAPI) set (NFAPI_USER_DIR ${OPENAIR_DIR}/nfapi/oai_integration) set (OPENAIR1_DIR ${OPENAIR_DIR}/openair1) @@ -2624,7 +2628,7 @@ add_executable(ocp-enb ${CONFIG_SOURCES} ${SHLIB_LOADER_SOURCES} ) -add_dependencies(ocp-enb rrc_flag s1ap_flag x2_flag oai_iqplayer) +add_dependencies(ocp-enb rrc_flag s1ap_flag x2_flag oai_iqplayer coding params_libconfig rfsimulator) target_link_libraries (ocp-enb -Wl,--start-group diff --git a/executables/main-ocp.c b/executables/main-ocp.c index 204067b229..2d96d40c75 100644 --- a/executables/main-ocp.c +++ b/executables/main-ocp.c @@ -97,7 +97,6 @@ void exit_function(const char *file, const char *function, const int line, const if (s != NULL) { printf("%s:%d %s() Exiting OAI softmodem: %s\n",file,line, function, s); } - softmodem_printresources(0,(telnet_printfunc_t)printf); close_log_mem(); oai_exit = 1; From 613d603278d770e4ae70c5dc406a57d76626377c Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Mon, 3 Aug 2020 11:15:06 +0200 Subject: [PATCH 549/553] CI: few fixes and improvements Signed-off-by: Raphael Defosseux --- ci-scripts/cls_cots_ue.py | 14 ++++++-------- ci-scripts/main.py | 16 ++++++---------- ci-scripts/ran.py | 10 +++++----- .../enb_ocp_usrp210_band7_test_05mhz_tm1.xml | 4 ++-- 4 files changed, 19 insertions(+), 25 deletions(-) diff --git a/ci-scripts/cls_cots_ue.py b/ci-scripts/cls_cots_ue.py index 23feba982b..6954aa3927 100644 --- a/ci-scripts/cls_cots_ue.py +++ b/ci-scripts/cls_cots_ue.py @@ -50,8 +50,7 @@ class CotsUe: def Check_Airplane(self): mySSH = sshconnection.SSHConnection() mySSH.open(self.UEIPAddr, self.UEUserName, self.UEPassWord) - mySSH.command('cd /home/oaici/remi/android-sdk-linux/platform-tools', '\$', 5) - status=mySSH.cde_check_value('sudo ./adb shell settings get global airplane_mode_on ', ['0','1'],5) + status=mySSH.cde_check_value('sudo adb shell settings get global airplane_mode_on ', ['0','1'],5) mySSH.close() return status @@ -59,8 +58,7 @@ class CotsUe: def Set_Airplane(self,target_state_str): mySSH = sshconnection.SSHConnection() mySSH.open(self.UEIPAddr, self.UEUserName, self.UEPassWord) - mySSH.command('cd /home/oaici/remi/android-sdk-linux/platform-tools', '\$', 5) - mySSH.command('sudo ./adb start-server','$',5) + mySSH.command('sudo adb start-server','$',5) logging.info("Toggling COTS UE Airplane mode to : "+target_state_str) current_state = self.Check_Airplane() if target_state_str.lower()=="on": @@ -71,9 +69,9 @@ class CotsUe: #toggle state retry = 0 while (current_state!=target_state) and (retry < self.__SetAirplaneRetry): - mySSH.command('sudo ./adb shell am start -a android.settings.AIRPLANE_MODE_SETTINGS', '\$', 5) - mySSH.command('sudo ./adb shell input keyevent 20', '\$', 5) - mySSH.command('sudo ./adb shell input tap 968 324', '\$', 5) + mySSH.command('sudo adb shell am start -a android.settings.AIRPLANE_MODE_SETTINGS', '\$', 5) + mySSH.command('sudo adb shell input keyevent 20', '\$', 5) + mySSH.command('sudo adb shell input tap 968 324', '\$', 5) time.sleep(1) current_state = self.Check_Airplane() retry+=1 @@ -82,7 +80,7 @@ class CotsUe: logging.error("Current state is : "+ str(current_state)) else: print("Airplane mode is already "+ target_state_str) - mySSH.command('sudo ./adb kill-server','$',5) + mySSH.command('sudo adb kill-server','$',5) mySSH.close() diff --git a/ci-scripts/main.py b/ci-scripts/main.py index 32742f3e88..d37f205f4e 100644 --- a/ci-scripts/main.py +++ b/ci-scripts/main.py @@ -330,7 +330,7 @@ class OaiCiTest(): check_OAI_UE = False pStatus = self.CheckProcessExist(check_eNB, check_OAI_UE) if (pStatus < 0): - HTML.CreateHtmlTestRow(self.Initialize_OAI_UE_args, 'KO', pStatus) + HTML.CreateHtmlTestRow(self.air_interface + ' ' + self.Initialize_OAI_UE_args, 'KO', pStatus) HTML.CreateHtmlTabFooter(False) sys.exit(1) UE_prefix = '' @@ -522,7 +522,7 @@ class OaiCiTest(): SSH.close() if fullSyncStatus and gotSyncStatus and tunnelInterfaceStatus: - HTML.CreateHtmlTestRow(self.Initialize_OAI_UE_args, 'OK', CONST.ALL_PROCESSES_OK, 'OAI UE') + HTML.CreateHtmlTestRow(self.air_interface + ' ' + self.Initialize_OAI_UE_args, 'OK', CONST.ALL_PROCESSES_OK, 'OAI UE') logging.debug('\u001B[1m Initialize OAI UE Completed\u001B[0m') if (self.ADBIPAddress != 'none'): self.UEDevices = [] @@ -535,10 +535,10 @@ class OaiCiTest(): HTML.htmlUEFailureMsg='oaitun_ue1/oaitun_uem1 interfaces are either NOT mounted or NOT configured' else: HTML.htmlUEFailureMsg='oaitun_ue1 interface is either NOT mounted or NOT configured' - HTML.CreateHtmlTestRow(self.Initialize_OAI_UE_args, 'KO', CONST.OAI_UE_PROCESS_NO_TUNNEL_INTERFACE, 'OAI UE') + HTML.CreateHtmlTestRow(self.air_interface + ' ' + self.Initialize_OAI_UE_args, 'KO', CONST.OAI_UE_PROCESS_NO_TUNNEL_INTERFACE, 'OAI UE') else: HTML.htmlUEFailureMsg='nr-uesoftmodem did NOT synced' - HTML.CreateHtmlTestRow(self.Initialize_OAI_UE_args, 'KO', CONST.OAI_UE_PROCESS_COULD_NOT_SYNC, 'OAI UE') + HTML.CreateHtmlTestRow(self.air_interface + ' ' + self.Initialize_OAI_UE_args, 'KO', CONST.OAI_UE_PROCESS_COULD_NOT_SYNC, 'OAI UE') logging.error('\033[91mInitialize OAI UE Failed! \033[0m') self.AutoTerminateUEandeNB() @@ -1085,11 +1085,7 @@ class OaiCiTest(): sys.exit('Insufficient Parameter') SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword) if self.ADBCentralized: - if self.ADBIPAddress == '192.168.18.196': - SSH.command('/home/oaici/remi/android-sdk-linux/platform-tools/adb devices', '\$', 15) - else: - SSH.command('adb devices', '\$', 15) - #self.UEDevices = re.findall("\\\\r\\\\n([A-Za-z0-9]+)\\\\tdevice",SSH.getBefore()) + SSH.command('adb devices', '\$', 15) self.UEDevices = re.findall("\\\\r\\\\n([A-Za-z0-9]+)\\\\tdevice",SSH.getBefore()) SSH.close() else: @@ -2584,7 +2580,7 @@ class OaiCiTest(): freq = result.group('carrier_frequency') new_freq = re.sub('/[0-9]+','',freq) float_freq = float(new_freq) / 1000000 - HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + 'DL Freq: ' + ('%.1f' % float_freq) + ' MHz') + HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + 'DL Freq: ' + ('%.1f' % float_freq) + ' MHz' logging.debug('\033[94m' + " DL Carrier Frequency is: " + str(freq) + '\033[0m') except Exception as e: logging.error('\033[91m' + " DL Carrier Frequency not found" + '\033[0m') diff --git a/ci-scripts/ran.py b/ci-scripts/ran.py index 936eeb3227..35513493dc 100644 --- a/ci-scripts/ran.py +++ b/ci-scripts/ran.py @@ -343,7 +343,7 @@ class RANManagement(): if (self.pStatus < 0): if self.htmlObj is not None: - self.htmlObj.CreateHtmlTestRow(self.Initialize_eNB_args, 'KO', self.pStatus) + self.htmlObj.CreateHtmlTestRow(self.air_interface[self.eNB_instance] + ' ' + self.Initialize_eNB_args, 'KO', self.pStatus) self.htmlObj.CreateHtmlTabFooter(False) sys.exit(1) # If tracer options is on, running tshark on EPC side and capture traffic b/ EPC and eNB @@ -450,9 +450,9 @@ class RANManagement(): mySSH.command('killall --signal SIGKILL record', '\$', 5) mySSH.close() doLoop = False - logging.error('\u001B[1;37;41m eNB logging system did not show got sync! \u001B[0m') + logging.error('\u001B[1;37;41m eNB/gNB/ocp-eNB logging system did not show got sync! \u001B[0m') if self.htmlObj is not None: - self.htmlObj.CreateHtmlTestRow('-O ' + config_file + extra_options, 'KO', CONST.ALL_PROCESSES_OK) + self.htmlObj.CreateHtmlTestRow(self.air_interface[self.eNB_instance] + ' -O ' + config_file + extra_options, 'KO', CONST.ALL_PROCESSES_OK) # In case of T tracer recording, we need to kill tshark on EPC side result = re.search('T_stdout', str(self.Initialize_eNB_args)) if (result is not None) and (self.epcObj is not None): @@ -510,8 +510,8 @@ class RANManagement(): mySSH.close() if self.htmlObj is not None: - self.htmlObj.CreateHtmlTestRow('-O ' + config_file + extra_options, 'OK', CONST.ALL_PROCESSES_OK) - logging.debug('\u001B[1m Initialize eNB Completed\u001B[0m') + self.htmlObj.CreateHtmlTestRow(self.air_interface[self.eNB_instance] + ' -O ' + config_file + extra_options, 'OK', CONST.ALL_PROCESSES_OK) + logging.debug('\u001B[1m Initialize eNB/gNB/ocp-eNB Completed\u001B[0m') def CheckeNBProcess(self, status_queue): try: diff --git a/ci-scripts/xml_files/enb_ocp_usrp210_band7_test_05mhz_tm1.xml b/ci-scripts/xml_files/enb_ocp_usrp210_band7_test_05mhz_tm1.xml index 854fb8cb19..a4caa77075 100644 --- a/ci-scripts/xml_files/enb_ocp_usrp210_band7_test_05mhz_tm1.xml +++ b/ci-scripts/xml_files/enb_ocp_usrp210_band7_test_05mhz_tm1.xml @@ -34,14 +34,14 @@ Initialize_eNB - Initialize eNB (FDD/Band7/5MHz) + Initialize OCP-eNB (FDD/Band7/5MHz) -O ci-scripts/conf_files/enb.band7.tm1.25PRB.usrpb210.conf ocp Terminate_eNB - Terminate eNB + Terminate OCP-eNB ocp From 7daa4a2a104bf973995f96e5713e9e4eb2732db0 Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Mon, 3 Aug 2020 14:02:12 +0200 Subject: [PATCH 550/553] CI: update on FR1 scenarios Signed-off-by: Raphael Defosseux --- .../xml_files/fr1_multi_node_terminate.xml | 50 +++++++++++++++++++ ci-scripts/xml_files/fr1_multi_node_test.xml | 4 +- 2 files changed, 52 insertions(+), 2 deletions(-) create mode 100644 ci-scripts/xml_files/fr1_multi_node_terminate.xml diff --git a/ci-scripts/xml_files/fr1_multi_node_terminate.xml b/ci-scripts/xml_files/fr1_multi_node_terminate.xml new file mode 100644 index 0000000000..cbaaf8ba99 --- /dev/null +++ b/ci-scripts/xml_files/fr1_multi_node_terminate.xml @@ -0,0 +1,50 @@ + + + test-fr1-tm1 + Test-FR1-TM1 + tasks + 1 + + 070001 + 070000 + + + + + + Terminate_eNB + Terminate eNB + 0 + 0 + + + + Terminate_eNB + Terminate gNB + 1 + 1 + + + + diff --git a/ci-scripts/xml_files/fr1_multi_node_test.xml b/ci-scripts/xml_files/fr1_multi_node_test.xml index d35dd74c2b..8c56f0bcec 100644 --- a/ci-scripts/xml_files/fr1_multi_node_test.xml +++ b/ci-scripts/xml_files/fr1_multi_node_test.xml @@ -29,8 +29,8 @@ 030000 040000 000001 - 070000 070001 + 070000 @@ -68,7 +68,7 @@ Terminate_eNB - Terminate eNB + Terminate gNB 1 1 From a385ad5244c0e7062772dcda711c0f159ab87968 Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Mon, 3 Aug 2020 14:03:20 +0200 Subject: [PATCH 551/553] Putting back SIGINT detection for lte-softmodem and initial skeleton to retrieve runtime stats from eNB/gNB Signed-off-by: Raphael Defosseux --- ci-scripts/ran.py | 30 ++++++++++++++++++++++++++++++ openair2/X2AP/x2ap_eNB.c | 4 +++- targets/RT/USER/lte-softmodem.c | 2 ++ 3 files changed, 35 insertions(+), 1 deletion(-) diff --git a/ci-scripts/ran.py b/ci-scripts/ran.py index 35513493dc..71cdca1019 100644 --- a/ci-scripts/ran.py +++ b/ci-scripts/ran.py @@ -698,7 +698,30 @@ class RANManagement(): X2HO_inNbProcedures = 0 X2HO_outNbProcedures = 0 global_status = CONST.ALL_PROCESSES_OK + # Runtime statistics + runTime = '' + userTime = '' + systemTime = '' + maxPhyMemUsage = '' + nbContextSwitches = '' for line in enb_log_file.readlines(): + # Runtime statistics + result = re.search('Run time:' ,str(line)) + if result is not None: + runTime = str(line).strip() + if runTime != '': + result = re.search('Time executing user inst', str(line)) + if result is not None: + userTime = 'to be decoded - 1' + result = re.search('Time executing system inst', str(line)) + if result is not None: + systemTime = 'to be decoded - 2' + result = re.search('Max. Phy. memory usage:', str(line)) + if result is not None: + maxPhyMemUsage = 'to be decoded - 3' + result = re.search('Number of context switch.*process origin', str(line)) + if result is not None: + nbContextSwitches = 'to be decoded - 4' if X2HO_state == CONST.X2_HO_REQ_STATE__IDLE: result = re.search('target eNB Receives X2 HO Req X2AP_HANDOVER_REQ', str(line)) if result is not None: @@ -955,4 +978,11 @@ class RANManagement(): global_status = CONST.ENB_PROCESS_REALTIME_ISSUE if self.htmlObj is not None: self.htmlObj.HmleNBFailureMsg=htmleNBFailureMsg + # Runtime statistics + if runTime != '': + logging.debug(runTime) + logging.debug('Time executing user inst : ' + userTime) + logging.debug('Time executing system inst : ' + systemTime) + logging.debug('Max Physical Memory Usage : ' + maxPhyMemUsage) + logging.debug('Nb Context Switches : ' + nbContextSwitches) return global_status diff --git a/openair2/X2AP/x2ap_eNB.c b/openair2/X2AP/x2ap_eNB.c index 6a037b8ee3..bd77272747 100644 --- a/openair2/X2AP/x2ap_eNB.c +++ b/openair2/X2AP/x2ap_eNB.c @@ -116,7 +116,9 @@ void x2ap_eNB_handle_sctp_association_resp(instance_t instance, sctp_new_associa /* some sanity check - to be refined at some point */ if (sctp_new_association_resp->sctp_state != SCTP_STATE_ESTABLISHED) { X2AP_ERROR("x2ap_enb_data_p not NULL and sctp state not SCTP_STATE_ESTABLISHED, what to do?\n"); - abort(); + // Allow for a gracious exit when we kill first the gNB, then the eNB + //abort(); + return; } x2ap_enb_data_p->in_streams = sctp_new_association_resp->in_streams; diff --git a/targets/RT/USER/lte-softmodem.c b/targets/RT/USER/lte-softmodem.c index 4715a4e995..26f84e66c0 100644 --- a/targets/RT/USER/lte-softmodem.c +++ b/targets/RT/USER/lte-softmodem.c @@ -556,6 +556,8 @@ int main ( int argc, char **argv ) MSC_INIT(MSC_E_UTRAN, THREAD_MAX+TASK_MAX); init_opt(); + // to make a graceful exit when ctrl-c is pressed + set_softmodem_sighandler(); check_clock(); #ifndef PACKAGE_VERSION # define PACKAGE_VERSION "UNKNOWN-EXPERIMENTAL" From cf23c586816b89c6a825c69173e14478d8bf9650 Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Wed, 5 Aug 2020 18:04:16 +0200 Subject: [PATCH 552/553] CI: fix typo for RAN HTML reporting Signed-off-by: Raphael Defosseux --- ci-scripts/ran.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ci-scripts/ran.py b/ci-scripts/ran.py index 71cdca1019..96f28e21fe 100644 --- a/ci-scripts/ran.py +++ b/ci-scripts/ran.py @@ -627,7 +627,7 @@ class RANManagement(): if (copyin_res == -1): logging.debug('\u001B[1;37;41m Could not copy ' + nodeB_prefix + 'NB logfile to analyze it! \u001B[0m') if self.htmlObj is not None: - self.htmlObj.HmleNBFailureMsg='Could not copy ' + nodeB_prefix + 'NB logfile to analyze it!' + self.htmlObj.htmleNBFailureMsg='Could not copy ' + nodeB_prefix + 'NB logfile to analyze it!' self.htmlObj.CreateHtmlTestRow('N/A', 'KO', CONST.ENB_PROCESS_NOLOGFILE_TO_ANALYZE) self.eNBmbmsEnables[int(self.eNB_instance)] = False return @@ -977,7 +977,7 @@ class RANManagement(): htmleNBFailureMsg += rlcMsg + '\n' global_status = CONST.ENB_PROCESS_REALTIME_ISSUE if self.htmlObj is not None: - self.htmlObj.HmleNBFailureMsg=htmleNBFailureMsg + self.htmlObj.htmleNBFailureMsg=htmleNBFailureMsg # Runtime statistics if runTime != '': logging.debug(runTime) From f445bdd3244a3cd09d90b640b46166d7b0c95b18 Mon Sep 17 00:00:00 2001 From: Raphael Defosseux Date: Tue, 11 Aug 2020 11:29:05 +0200 Subject: [PATCH 553/553] CI: fixed typo in the list of allowed methods Signed-off-by: Raphael Defosseux --- ci-scripts/xml_class_list.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ci-scripts/xml_class_list.yml b/ci-scripts/xml_class_list.yml index 56890c1fc6..e80063a120 100755 --- a/ci-scripts/xml_class_list.yml +++ b/ci-scripts/xml_class_list.yml @@ -13,7 +13,7 @@ - Initialize_OAI_UE - Terminate_OAI_UE - DataDisable_UE - - DataEnable_ + - DataEnable_UE - CheckStatusUE - Ping - Iperf

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z_>bmnHhxez+E1yXioMC|0$hW&Rhzl?sQ3J*18`Bv^#1@jqKeC*L6Zvg+mq?}(8Y?W zJe&s4PxHkTQ;7phtdIALaC62EJt-9gjkl>o%Krd`6jLmWDyYh@%aiY%bsw!GsEIT8 zcnl6t89(GvMIw5OwR5?CWhb85KTpb$)uNksA9pyw>Hh%M#S~UG4XMR9saNbx{{TIk S{`mg@>(NCOpDC}iiT~MoB_g;0 literal 0 HcmV?d00001 From ff111e0797fcf0600cc653f877c45fe1b25bb188 Mon Sep 17 00:00:00 2001 From: Remi Hardy Date: Thu, 25 Jun 2020 12:13:51 +0200 Subject: [PATCH 375/553] Update TESTING_GNB_W_COTS_UE.md --- doc/TESTING_GNB_W_COTS_UE.md | 1 + 1 file changed, 1 insertion(+) diff --git a/doc/TESTING_GNB_W_COTS_UE.md b/doc/TESTING_GNB_W_COTS_UE.md index cd2da4eda5..a6a45c0a97 100644 --- a/doc/TESTING_GNB_W_COTS_UE.md +++ b/doc/TESTING_GNB_W_COTS_UE.md @@ -23,6 +23,7 @@ The scheme below depicts our typical setup: ![image info](./testing_gnb_w_cots_ue_resources/oai_fr1_setup.jpg) +![image info](./testing_gnb_w_cots_ue_resources/oai_fr1_lab.jpg) ## Build / Install From 8048f6b8383d6755d311a9089186ef12063316dc Mon Sep 17 00:00:00 2001 From: hardy Date: Thu, 25 Jun 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