Adding one UL empty slot before actual UL slot
- total num of symbols is 12 instead of 14 in PUSCH - actual UL slot is 3 instead of 2
This commit is contained in:
committed by
Thomas Schlichter
parent
f7d546f2d9
commit
2dd941a22d
+14
-2
@@ -382,7 +382,7 @@ void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) {
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n_rnti = 0x1234;
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n_rnti = 0x1234;
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nb_rb = 50;
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nb_rb = 50;
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start_rb = 0;
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start_rb = 0;
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nb_symb_sch = 14;
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nb_symb_sch = 12;
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start_symbol = 0;
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start_symbol = 0;
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precod_nbr_layers = 1;
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precod_nbr_layers = 1;
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mcs = 9;
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mcs = 9;
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@@ -736,6 +736,18 @@ void *UE_thread(void *arg) {
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readBlockSize,
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readBlockSize,
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UE->frame_parms.nb_antennas_rx),"");
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UE->frame_parms.nb_antennas_rx),"");
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if (slot_nr == (20+NR_UPLINK_SLOT-DURATION_RX_TO_TX - 1)%20)
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AssertFatal( writeBlockSize ==
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UE->rfdevice.trx_write_func(&UE->rfdevice,
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timestamp+
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(DURATION_RX_TO_TX*UE->frame_parms.samples_per_slot) -
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UE->frame_parms.ofdm_symbol_size-UE->frame_parms.nb_prefix_samples0 -
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openair0_cfg[0].tx_sample_advance,
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txp,
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writeBlockSize,
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UE->frame_parms.nb_antennas_tx,
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2),"");
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if (slot_nr == (20+NR_UPLINK_SLOT-DURATION_RX_TO_TX)%20)
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if (slot_nr == (20+NR_UPLINK_SLOT-DURATION_RX_TO_TX)%20)
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AssertFatal( writeBlockSize ==
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AssertFatal( writeBlockSize ==
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UE->rfdevice.trx_write_func(&UE->rfdevice,
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UE->rfdevice.trx_write_func(&UE->rfdevice,
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@@ -746,7 +758,7 @@ if (slot_nr == (20+NR_UPLINK_SLOT-DURATION_RX_TO_TX)%20)
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txp,
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txp,
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writeBlockSize,
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writeBlockSize,
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UE->frame_parms.nb_antennas_tx,
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UE->frame_parms.nb_antennas_tx,
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4),"");
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3),"");
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if( slot_nr==(nb_slot_frame-1)) {
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if( slot_nr==(nb_slot_frame-1)) {
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// read in first symbol of next frame and adjust for timing drift
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// read in first symbol of next frame and adjust for timing drift
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@@ -119,7 +119,7 @@ SystemInformationBlockType1_nr_t;
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#define NR_TDD_SET_ALL_SYMBOLS (0x3FFF)
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#define NR_TDD_SET_ALL_SYMBOLS (0x3FFF)
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#define NR_DOWNLINK_SLOT (0x01)
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#define NR_DOWNLINK_SLOT (0x01)
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#define NR_UPLINK_SLOT (0x02)
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#define NR_UPLINK_SLOT (0x03)
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#define FRAME_DURATION_MICRO_SEC (10000) /* frame duration in microsecond */
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#define FRAME_DURATION_MICRO_SEC (10000) /* frame duration in microsecond */
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@@ -375,11 +375,11 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
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// Phytest scheduling
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// Phytest scheduling
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if (slot_rxP==2){
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if (slot_rxP==NR_UPLINK_SLOT){
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nr_schedule_uss_ulsch_phytest(&RC.nrmac[module_idP]->UL_tti_req[0], frame_rxP, slot_rxP);
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nr_schedule_uss_ulsch_phytest(&RC.nrmac[module_idP]->UL_tti_req[0], frame_rxP, slot_rxP);
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}
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}
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if (slot_txP==1){
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if (slot_txP==NR_DOWNLINK_SLOT){
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nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP,NULL);
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nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP,NULL);
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}
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}
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@@ -527,7 +527,7 @@ void nr_schedule_uss_ulsch_phytest(nfapi_nr_ul_tti_request_t *UL_tti_req,
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pusch_pdu->uplink_frequency_shift_7p5khz = 0;
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pusch_pdu->uplink_frequency_shift_7p5khz = 0;
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//Resource Allocation in time domain
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//Resource Allocation in time domain
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pusch_pdu->start_symbol_index = 0;
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pusch_pdu->start_symbol_index = 0;
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pusch_pdu->nr_of_symbols = 14;
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pusch_pdu->nr_of_symbols = 12;
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//Optional Data only included if indicated in pduBitmap
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//Optional Data only included if indicated in pduBitmap
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pusch_pdu->pusch_data.rv_index = 0;
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pusch_pdu->pusch_data.rv_index = 0;
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pusch_pdu->pusch_data.harq_process_id = 0;
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pusch_pdu->pusch_data.harq_process_id = 0;
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