Rename NR_sched_pusch_t and use for Freq Alloc + MCS
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@@ -1724,17 +1724,13 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){
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UE_info->UE_sched_ctrl[UE_id].sched_pucch = (NR_sched_pucch **)malloc(num_slots_ul*sizeof(NR_sched_pucch *));
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UE_info->UE_sched_ctrl[UE_id].sched_pucch = (NR_sched_pucch **)malloc(num_slots_ul*sizeof(NR_sched_pucch *));
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for (int s=0; s<num_slots_ul;s++)
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for (int s=0; s<num_slots_ul;s++)
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UE_info->UE_sched_ctrl[UE_id].sched_pucch[s] = (NR_sched_pucch *)malloc(2*sizeof(NR_sched_pucch));
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UE_info->UE_sched_ctrl[UE_id].sched_pucch[s] = (NR_sched_pucch *)malloc(2*sizeof(NR_sched_pucch));
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UE_info->UE_sched_ctrl[UE_id].sched_pusch = (NR_sched_pusch *)malloc(num_slots_ul*sizeof(NR_sched_pusch));
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UE_info->UE_sched_ctrl[UE_id].sched_pusch = calloc(num_slots_ul, sizeof(NR_sched_pusch_t));
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for (int k=0; k<num_slots_ul; k++) {
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for (int k=0; k<num_slots_ul; k++) {
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for (int l=0; l<2; l++)
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for (int l=0; l<2; l++)
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memset((void *) &UE_info->UE_sched_ctrl[UE_id].sched_pucch[k][l],
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memset((void *) &UE_info->UE_sched_ctrl[UE_id].sched_pucch[k][l],
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0,
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0,
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sizeof(NR_sched_pucch));
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sizeof(NR_sched_pucch));
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memset((void *) &UE_info->UE_sched_ctrl[UE_id].sched_pusch[k],
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0,
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sizeof(NR_sched_pusch));
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}
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}
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LOG_I(MAC, "gNB %d] Add NR UE_id %d : rnti %x\n",
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LOG_I(MAC, "gNB %d] Add NR UE_id %d : rnti %x\n",
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mod_idP,
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mod_idP,
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@@ -501,6 +501,11 @@ void nr_simple_ulsch_preprocessor(module_id_t module_id,
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return;
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return;
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}
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}
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UE_info->num_pdcch_cand[UE_id][cid]++;
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UE_info->num_pdcch_cand[UE_id][cid]++;
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sched_ctrl->sched_pusch->mcs = 9;
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sched_ctrl->sched_pusch->rbStart = 0;
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sched_ctrl->sched_pusch->rbSize = get_softmodem_params()->phy_test ?
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50 : NRRIV2BW(sched_ctrl->active_ubwp->bwp_Common->genericParameters.locationAndBandwidth,275);
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}
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}
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void nr_schedule_ulsch(module_id_t module_id,
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void nr_schedule_ulsch(module_id_t module_id,
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@@ -539,11 +544,6 @@ void nr_schedule_ulsch(module_id_t module_id,
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if (is_xlsch_in_slot(ulsch_in_slot_bitmap, sched_slot)
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if (is_xlsch_in_slot(ulsch_in_slot_bitmap, sched_slot)
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&& (!get_softmodem_params()->phy_test || sched_slot == 8)) {
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&& (!get_softmodem_params()->phy_test || sched_slot == 8)) {
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const uint8_t mcs = 9;
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const uint16_t rbStart = 0;
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const uint16_t rbSize = get_softmodem_params()->phy_test ?
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50 : NRRIV2BW(sched_ctrl->active_ubwp->bwp_Common->genericParameters.locationAndBandwidth,275);
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nfapi_nr_ul_dci_request_t *UL_dci_req = &RC.nrmac[module_id]->UL_dci_req[0];
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nfapi_nr_ul_dci_request_t *UL_dci_req = &RC.nrmac[module_id]->UL_dci_req[0];
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UL_dci_req->SFN = frame;
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UL_dci_req->SFN = frame;
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UL_dci_req->Slot = slot;
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UL_dci_req->Slot = slot;
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@@ -607,7 +607,7 @@ void nr_schedule_ulsch(module_id_t module_id,
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else
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else
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pusch_pdu->data_scrambling_id = *scc->physCellId;
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pusch_pdu->data_scrambling_id = *scc->physCellId;
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pusch_pdu->mcs_index = mcs;
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pusch_pdu->mcs_index = sched_ctrl->sched_pusch->mcs;
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const int target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific;
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const int target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific;
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if (pusch_pdu->transform_precoding)
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if (pusch_pdu->transform_precoding)
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pusch_pdu->mcs_table = get_pusch_mcs_table(pusch_Config->mcs_Table,
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pusch_pdu->mcs_table = get_pusch_mcs_table(pusch_Config->mcs_Table,
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@@ -640,8 +640,8 @@ void nr_schedule_ulsch(module_id_t module_id,
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AssertFatal(pusch_Config->resourceAllocation == NR_PUSCH_Config__resourceAllocation_resourceAllocationType1,
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AssertFatal(pusch_Config->resourceAllocation == NR_PUSCH_Config__resourceAllocation_resourceAllocationType1,
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"Only frequency resource allocation type 1 is currently supported\n");
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"Only frequency resource allocation type 1 is currently supported\n");
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pusch_pdu->resource_alloc = 1; //type 1
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pusch_pdu->resource_alloc = 1; //type 1
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pusch_pdu->rb_start = rbStart;
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pusch_pdu->rb_start = sched_ctrl->sched_pusch->rbStart;
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pusch_pdu->rb_size = rbSize;
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pusch_pdu->rb_size = sched_ctrl->sched_pusch->rbSize;
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pusch_pdu->vrb_to_prb_mapping = 0;
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pusch_pdu->vrb_to_prb_mapping = 0;
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if (pusch_Config->frequencyHopping==NULL)
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if (pusch_Config->frequencyHopping==NULL)
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@@ -786,5 +786,8 @@ void nr_schedule_ulsch(module_id_t module_id,
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const int n_ubwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.count;
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const int n_ubwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.count;
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config_uldci(sched_ctrl->active_ubwp,pusch_pdu,pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types,tda,UE_info->UE_sched_ctrl[UE_id].tpc0,n_ubwp,sched_ctrl->active_bwp->bwp_Id);
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config_uldci(sched_ctrl->active_ubwp,pusch_pdu,pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types,tda,UE_info->UE_sched_ctrl[UE_id].tpc0,n_ubwp,sched_ctrl->active_bwp->bwp_Id);
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fill_dci_pdu_rel15(scc,secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types,pusch_pdu->bwp_size,sched_ctrl->active_bwp->bwp_Id);
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fill_dci_pdu_rel15(scc,secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types,pusch_pdu->bwp_size,sched_ctrl->active_bwp->bwp_Id);
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sched_ctrl->sched_pusch->rbSize = 0;
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}
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}
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}
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}
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@@ -290,7 +290,14 @@ typedef struct NR_sched_pusch {
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int slot;
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int slot;
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bool active;
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bool active;
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nfapi_nr_pusch_pdu_t pusch_pdu;
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nfapi_nr_pusch_pdu_t pusch_pdu;
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} NR_sched_pusch;
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/// RB allocation within active uBWP
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uint16_t rbSize;
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uint16_t rbStart;
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/// MCS
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uint8_t mcs;
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} NR_sched_pusch_t;
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typedef struct NR_UE_harq {
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typedef struct NR_UE_harq {
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uint8_t is_waiting;
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uint8_t is_waiting;
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@@ -355,7 +362,7 @@ typedef struct {
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/// selected PUCCH index, if scheduled
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/// selected PUCCH index, if scheduled
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int pucch_sched_idx;
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int pucch_sched_idx;
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int pucch_occ_idx;
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int pucch_occ_idx;
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NR_sched_pusch *sched_pusch;
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NR_sched_pusch_t *sched_pusch;
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/// CCE index and aggregation, should be coherent with cce_list
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/// CCE index and aggregation, should be coherent with cce_list
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NR_SearchSpace_t *search_space;
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NR_SearchSpace_t *search_space;
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