* Compile Rel10 with component carrier
* Add VCD timing for PDCP, RLC, and MAC * Update MAC-PHY interface * update eNB MAC DLSCH scheduler and preprocessor with component carrier * Add test case for dlsim performance git-svn-id: http://svn.eurecom.fr/openair4G/trunk@5708 818b1a75-f10b-46b9-bf7c-635c3b92a50f
This commit is contained in:
Navid Nikaein
+237
-392
@@ -36,7 +36,7 @@
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*/
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#include "assertions.h"
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#include "PHY/defs.h"
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#include "PHY/extern.h"
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@@ -70,7 +70,6 @@
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extern inline unsigned int taus(void);
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// This function stores the downlink buffer for all the logical channels
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void store_dlsch_buffer (module_id_t Mod_id,
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frame_t frameP,
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@@ -104,10 +103,12 @@ void store_dlsch_buffer (module_id_t Mod_id,
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UE_template->dl_buffer_info[i] = rlc_status.bytes_in_buffer; //storing the dlsch buffer for each logical channel
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UE_template->dl_pdus_in_buffer[i] = rlc_status.pdus_in_buffer;
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UE_template->dl_buffer_head_sdu_creation_time[i] = rlc_status.head_sdu_creation_time ;
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UE_template->dl_buffer_head_sdu_creation_time_max = cmax(UE_template->dl_buffer_head_sdu_creation_time_max,
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rlc_status.head_sdu_creation_time );
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UE_template->dl_buffer_head_sdu_remaining_size_to_send[i] = rlc_status.head_sdu_remaining_size_to_send;
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UE_template->dl_buffer_head_sdu_is_segmented[i] = rlc_status.head_sdu_is_segmented;
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UE_template->dl_buffer_total = UE_template->dl_buffer_total + UE_template->dl_buffer_info[i];//storing the total dlsch buffer
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UE_template->dl_pdus_total += UE_template->dl_pdus_in_buffer[i];
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UE_template->dl_buffer_total += UE_template->dl_buffer_info[i];//storing the total dlsch buffer
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UE_template->dl_pdus_total += UE_template->dl_pdus_in_buffer[i];
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#ifdef DEBUG_eNB_SCHEDULER
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/* note for dl_buffer_head_sdu_remaining_size_to_send[i] :
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@@ -124,18 +125,18 @@ void store_dlsch_buffer (module_id_t Mod_id,
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#endif
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}
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#ifdef DEBUG_eNB_SCHEDULER
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//#ifdef DEBUG_eNB_SCHEDULER
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if ( UE_template->dl_buffer_total>0)
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LOG_D(MAC,"[eNB %d] Frame %d Subframe %d : RLC status for UE %d : total DL buffer size %d and total number of pdu %d \n",
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Mod_id, frameP, subframeP, UE_id,
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UE_template->dl_buffer_total,
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UE_template->dl_pdus_total
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);
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#endif
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//#endif
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}
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}
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// This function returns the estimated number of RBs required by each UE for downlink scheduling
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void assign_rbs_required (module_id_t Mod_id,
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frame_t frameP,
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@@ -149,76 +150,25 @@ void assign_rbs_required (module_id_t Mod_id,
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LTE_eNB_UE_stats *eNB_UE_stats[MAX_NUM_CCs];
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int UE_id,n,i,j,CC_id,pCCid,tmp;
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UE_list_t *UE_list = &eNB_mac_inst[Mod_id].UE_list;
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UE_TEMPLATE *UE_template;
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LTE_DL_FRAME_PARMS *frame_parms[MAX_NUM_CCs];
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// clear rb allocations across all CC_ids
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for (UE_id=UE_list->head;UE_id>=0;UE_id=UE_list->next[UE_id]){
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pCCid = UE_PCCID(Mod_id,UE_id);
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//update CQI information across component carriers
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for (n=0;n<UE_list->numactiveCCs[UE_id];n++) {
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CC_id = UE_list->ordered_CCids[n][UE_id];
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frame_parms[CC_id] = mac_xface->get_lte_frame_parms(Mod_id,CC_id);
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eNB_UE_stats[CC_id] = mac_xface->get_eNB_UE_stats(Mod_id,CC_id,rnti);
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switch(eNB_UE_stats[CC_id]->DL_cqi[0]) {
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case 0:
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eNB_UE_stats[CC_id]->dlsch_mcs1 = 0;
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break;
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case 1:
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eNB_UE_stats[CC_id]->dlsch_mcs1 = 0;
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break;
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case 2:
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eNB_UE_stats[CC_id]->dlsch_mcs1 = 0;
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break;
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case 3:
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eNB_UE_stats[CC_id]->dlsch_mcs1 = 2;
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break;
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case 4:
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eNB_UE_stats[CC_id]->dlsch_mcs1 = 4;
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break;
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case 5:
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eNB_UE_stats[CC_id]->dlsch_mcs1 = 6;
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break;
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case 6:
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eNB_UE_stats[CC_id]->dlsch_mcs1 = 8;
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break;
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case 7:
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eNB_UE_stats[CC_id]->dlsch_mcs1 = 11;
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break;
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case 8:
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eNB_UE_stats[CC_id]->dlsch_mcs1 = 13;
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break;
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case 9:
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eNB_UE_stats[CC_id]->dlsch_mcs1 = 16;
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break;
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case 10:
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eNB_UE_stats[CC_id]->dlsch_mcs1 = 18;
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break;
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case 11:
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eNB_UE_stats[CC_id]->dlsch_mcs1 = 20;
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break;
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case 12:
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eNB_UE_stats[CC_id]->dlsch_mcs1 = 22;
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break;
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case 13:
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eNB_UE_stats[CC_id]->dlsch_mcs1 = 25;
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break;
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case 14:
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eNB_UE_stats[CC_id]->dlsch_mcs1 = 27;
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break;
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case 15:
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eNB_UE_stats[CC_id]->dlsch_mcs1 = 28;
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break;
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default:
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LOG_E(MAC,"preprocessor.c assign_rbs_required(): Invalid CQI %d, should not happen",eNB_UE_stats[CC_id]->DL_cqi[0]);
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exit(-1);
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}
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/*
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DevCheck(((eNB_UE_stats[CC_id]->DL_cqi[0] < MIN_CQI_VALUE) || (eNB_UE_stats[CC_id]->DL_cqi[0] > MAX_CQI_VALUE)),
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eNB_UE_stats[CC_id]->DL_cqi[0], MIN_CQI_VALUE, MAX_CQI_VALUE);
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*/
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eNB_UE_stats[CC_id]->dlsch_mcs1=cqi_to_mcs[eNB_UE_stats[CC_id]->DL_cqi[0]];
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}
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// provide the list of CCs sorted according to MCS
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for (i=0;i<UE_list->numactiveCCs[UE_id];i++) {
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for (j=i+1;j<UE_list->numactiveCCs[UE_id];j++) {
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@@ -230,39 +180,43 @@ void assign_rbs_required (module_id_t Mod_id,
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}
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}
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}
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/*
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if ((mac_get_rrc_status(Mod_id,1,UE_id) < RRC_RECONFIGURED)){ // If we still don't have a default radio bearer
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nb_rbs_required[pCCid][UE_id] = PHY_vars_eNB_g[Mod_id][pCCid]->lte_frame_parms.N_RB_DL;
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continue;
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}
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if (UE_list->UE_template[UE_id]->dl_buffer_total> 0) {
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*/
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/* NN --> RK
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* check the index of UE_template"
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*/
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// if (UE_list->UE_template[UE_id]->dl_buffer_total> 0) {
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if (UE_list->UE_template[pCCid][UE_id].dl_buffer_total> 0) {
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LOG_D(MAC,"[preprocessor] assign RB for UE %d\n",UE_id);
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for (i=0;i<UE_list->numactiveCCs[UE_id];i++) {
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CC_id = UE_list->ordered_CCids[i][UE_id];
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LOG_D(MAC,"[preprocessor] assign RB for UE %d\n",UE_id);
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if (eNB_UE_stats[CC_id]->dlsch_mcs1==0) nb_rbs_required[CC_id][UE_id] = 4; // don't let the TBS get too small
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else nb_rbs_required[CC_id][UE_id] = min_rb_unit[CC_id];
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TBS = mac_xface->get_TBS_DL(eNB_UE_stats[CC_id]->dlsch_mcs1,nb_rbs_required[CC_id][UE_id]);
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/* calculating required number of RBs for each UE */
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while (TBS < UE_list->UE_template[UE_id]->dl_buffer_total) {
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nb_rbs_required[CC_id][UE_id] += min_rb_unit[CC_id];
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if (nb_rbs_required[CC_id][UE_id]>PHY_vars_eNB_g[Mod_id][CC_id]->lte_frame_parms.N_RB_DL) {
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TBS = mac_xface->get_TBS_DL(eNB_UE_stats[CC_id]->dlsch_mcs1,PHY_vars_eNB_g[Mod_id][CC_id]->lte_frame_parms.N_RB_DL);
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nb_rbs_required[CC_id][UE_id] = PHY_vars_eNB_g[Mod_id][CC_id]->lte_frame_parms.N_RB_DL;// calculating required number of RBs for each UE
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if (nb_rbs_required[CC_id][UE_id] > frame_parms[CC_id]->N_RB_DL) {
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TBS = mac_xface->get_TBS_DL(eNB_UE_stats[CC_id]->dlsch_mcs1,frame_parms[CC_id]->N_RB_DL);
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nb_rbs_required[CC_id][UE_id] = frame_parms[CC_id]->N_RB_DL;
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break;
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}
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TBS = mac_xface->get_TBS_DL(eNB_UE_stats[CC_id]->dlsch_mcs1,nb_rbs_required[CC_id][UE_id]);
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}
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} // end of while
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LOG_D(MAC,"[eNB %d] Frame %d: UE %d on CC %d nb_required RB %d (TBS %d, mcs %d)\n",
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Mod_id, frameP,UE_id, CC_id, nb_rbs_required[CC_id][UE_id], TBS, eNB_UE_stats[CC_id]->dlsch_mcs1);
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}
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}
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}
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}
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// This function scans all CC_ids for a particular UE to find the maximum round index of its HARQ processes
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int maxround(module_id_t Mod_id,uint16_t rnti,sub_frame_t subframe) {
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@@ -341,33 +295,24 @@ void sort_UEs (module_id_t Mod_id,
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// for(j=0;j<MAX_NUM_LCID;j++){
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// if (eNB_mac_inst[Mod_id][pCC_id1].UE_template[UE_id1].dl_buffer_info[j] <
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// eNB_mac_inst[Mod_id][pCC_id2].UE_template[UE_id2].dl_buffer_info[j]){
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if (UE_list->UE_template[pCC_id1][UE_id1].dl_buffer_total <
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UE_list->UE_template[pCC_id2][UE_id2].dl_buffer_total){
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swap_UEs(UE_list,UE_id1,UE_id2);
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// break;
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}
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else if (cqi1 < cqi2){
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swap_UEs(UE_list,UE_id1,UE_id2);
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}
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// if((j == MAX_NUM_LCID-1))
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// {
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// first check the buffer status for SRB1 and SRB2
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/* The goal is to sort by priority.
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* We use the priority of DTCH logical
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* channel.
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*/
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/*if(eNB_mac_inst[Mod_id][CC_id].UE_sched_ctrl[UE_id1].priority[3]<eNB_mac_inst[Mod_id][CC_id].UE_sched_ctrl[UE_id2].priority[3])
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{
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UE_id_sorted[i] = UE_id2;
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UE_id_sorted[ii] = UE_id1;
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} //if the priority is the same then sort by CQI
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else if(eNB_mac_inst[Mod_id][CC_id].UE_sched_ctrl[UE_id1].priority[3]==eNB_mac_inst[Mod_id][CC_id].UE_sched_ctrl[UE_id2].priority[3]){*/
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//}
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// }
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if ( (UE_list->UE_template[pCC_id1][UE_id1].dl_buffer_info[1] + UE_list->UE_template[pCC_id1][UE_id1].dl_buffer_info[2]) <
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(UE_list->UE_template[pCC_id2][UE_id2].dl_buffer_info[1] + UE_list->UE_template[pCC_id2][UE_id2].dl_buffer_info[2]) ){
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swap_UEs(UE_list,UE_id1,UE_id2);
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}
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else if (UE_list->UE_template[pCC_id1][UE_id1].dl_buffer_head_sdu_creation_time_max <
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UE_list->UE_template[pCC_id2][UE_id2].dl_buffer_head_sdu_creation_time_max ){
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swap_UEs(UE_list,UE_id1,UE_id2);
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}
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else if (UE_list->UE_template[pCC_id1][UE_id1].dl_buffer_total <
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UE_list->UE_template[pCC_id2][UE_id2].dl_buffer_total ){
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swap_UEs(UE_list,UE_id1,UE_id2);
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}
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else if (cqi1 < cqi2){
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swap_UEs(UE_list,UE_id1,UE_id2);
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}
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}
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}
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}
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@@ -382,11 +327,11 @@ void dlsch_scheduler_pre_processor (module_id_t Mod_id,
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sub_frame_t subframeP,
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uint8_t dl_pow_off[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
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uint16_t pre_nb_available_rbs[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
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int N_RBGS[MAX_NUM_CCs],
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unsigned char rballoc_sub_UE[MAX_NUM_CCs][NUMBER_OF_UE_MAX][N_RBGS_MAX],
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int *mbsfn_flag){
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int N_RBG[MAX_NUM_CCs],
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unsigned char rballoc_sub_UE[MAX_NUM_CCs][NUMBER_OF_UE_MAX][N_RBG_MAX],
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int *mbsfn_flag){
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unsigned char rballoc_sub[MAX_NUM_CCs][13],harq_pid=0,harq_pid1=0,harq_pid2=0,round=0,round1=0,round2=0,total_ue_count[MAX_NUM_CCs];
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unsigned char rballoc_sub[MAX_NUM_CCs][13],harq_pid=0,harq_pid1=0,harq_pid2=0,round=0,round1=0,round2=0,total_ue_count;
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unsigned char MIMO_mode_indicator[MAX_NUM_CCs][13];
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int UE_id, UE_id2, i;
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uint16_t ii,j;
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@@ -400,50 +345,37 @@ void dlsch_scheduler_pre_processor (module_id_t Mod_id,
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LTE_eNB_UE_stats *eNB_UE_stats2 = NULL;
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int min_rb_unit[MAX_NUM_CCs];
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int CC_id;
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uint8_t CC_id;
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UE_list_t *UE_list = &eNB_mac_inst[Mod_id].UE_list;
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LTE_DL_FRAME_PARMS *frame_parms[MAX_NUM_CCs];
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int rrc_status = RRC_IDLE;
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int transmission_mode = 0;
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for (CC_id=0;CC_id<MAX_NUM_CCs;CC_id++) {
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if (mbsfn_flag[CC_id]>0) // If this CC is allocated for MBSFN skip it here
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continue;
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switch (PHY_vars_eNB_g[Mod_id][CC_id]->lte_frame_parms.N_RB_DL) {
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case 6:
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min_rb_unit[CC_id]=1;
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break;
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case 25:
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min_rb_unit[CC_id]=2;
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break;
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case 50:
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min_rb_unit[CC_id]=3;
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break;
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case 100:
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min_rb_unit[CC_id]=4;
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break;
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default:
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min_rb_unit[CC_id]=2;
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break;
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}
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// Initialize scheduling information for all active UEs
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frame_parms[CC_id] = mac_xface->get_lte_frame_parms(Mod_id,CC_id);
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min_rb_unit[CC_id]=get_min_rb_unit(Mod_id,CC_id);
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for (i=UE_list->head;i>=0;i=UE_list->next[i]) {
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UE_id = i;
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nb_rbs_required[CC_id][UE_id] = 0;
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dl_pow_off[CC_id][UE_id] =2;
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pre_nb_available_rbs[CC_id][UE_id] = 0;
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nb_rbs_required_remaining[CC_id][UE_id] = 0;
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for(j=0;j<N_RBGS[CC_id];j++)
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{
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MIMO_mode_indicator[CC_id][j] = 2;
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rballoc_sub[CC_id][j] = 0;
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rballoc_sub_UE[CC_id][UE_id][j] = 0;
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}
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// Initialize scheduling information for all active UEs
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dlsch_scheduler_pre_processor_reset(UE_id,
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CC_id,
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N_RBG[CC_id],
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dl_pow_off,
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nb_rbs_required,
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pre_nb_available_rbs,
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nb_rbs_required_remaining,
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rballoc_sub_UE,
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rballoc_sub,
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MIMO_mode_indicator);
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}
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}
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// Store the DLSCH buffer for each logical channel
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store_dlsch_buffer (Mod_id,frameP,subframeP);
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@@ -453,7 +385,7 @@ void dlsch_scheduler_pre_processor (module_id_t Mod_id,
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// Sorts the user on the basis of dlsch logical channel buffer and CQI
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sort_UEs (Mod_id,subframeP);
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total_ue_count =0;
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// loop over all active UEs
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for (i=UE_list->head;i>=0;i=UE_list->next[i]) {
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@@ -467,7 +399,6 @@ void dlsch_scheduler_pre_processor (module_id_t Mod_id,
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for (ii=0;ii<UE_num_active_CC(UE_list,UE_id);ii++) {
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CC_id = UE_list->ordered_CCids[ii][UE_id];
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total_ue_count[CC_id]=0;
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average_rbs_per_user[CC_id]=0;
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@@ -476,9 +407,10 @@ void dlsch_scheduler_pre_processor (module_id_t Mod_id,
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nb_rbs_required[CC_id][UE_id] = UE_list->UE_template[CC_id][UE_id].nb_rb[harq_pid];
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//nb_rbs_required_remaining[UE_id] = nb_rbs_required[UE_id];
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if (nb_rbs_required[CC_id][UE_id] > 0) {
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total_ue_count[CC_id] = total_ue_count[CC_id] + 1;
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total_ue_count = total_ue_count + 1;
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}
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||||
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||||
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||||
// hypotetical assignement
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/*
|
||||
* If schedule is enabled and if the priority of the UEs is modified
|
||||
@@ -489,14 +421,17 @@ void dlsch_scheduler_pre_processor (module_id_t Mod_id,
|
||||
* per user by a coefficient which represents the degree of priority.
|
||||
*/
|
||||
|
||||
|
||||
if((total_ue_count[CC_id] > 0) && ( min_rb_unit[CC_id] * total_ue_count[CC_id] <= PHY_vars_eNB_g[Mod_id][CC_id]->lte_frame_parms.N_RB_DL ) )
|
||||
average_rbs_per_user[CC_id] = (uint16_t) ceil(PHY_vars_eNB_g[Mod_id][CC_id]->lte_frame_parms.N_RB_DL/total_ue_count[CC_id]);
|
||||
if (total_ue_count == 0)
|
||||
average_rbs_per_user[CC_id] = 0;
|
||||
else if( (min_rb_unit[CC_id] * total_ue_count) <= (frame_parms[CC_id]->N_RB_DL) )
|
||||
average_rbs_per_user[CC_id] = (uint16_t) ceil(frame_parms[CC_id]->N_RB_DL/total_ue_count);
|
||||
else
|
||||
average_rbs_per_user[CC_id] = min_rb_unit[CC_id];
|
||||
}
|
||||
}
|
||||
|
||||
// note: nb_rbs_required is assigned according to total_buffer_dl
|
||||
// extend nb_rbs_required to capture per LCID RB required
|
||||
for(i=UE_list->head;i>=0;i=UE_list->next[i]){
|
||||
for (ii=0;ii<UE_num_active_CC(UE_list,UE_id);ii++) {
|
||||
CC_id = UE_list->ordered_CCids[ii][UE_id];
|
||||
@@ -508,7 +443,6 @@ void dlsch_scheduler_pre_processor (module_id_t Mod_id,
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
//Allocation to UEs is done in 2 rounds,
|
||||
// 1st round: average number of RBs allocated to each UE
|
||||
// 2nd round: remaining RBs are allocated to high priority UEs
|
||||
@@ -517,165 +451,69 @@ void dlsch_scheduler_pre_processor (module_id_t Mod_id,
|
||||
for(i=UE_list->head; i>=0;i=UE_list->next[i]) {
|
||||
for (ii=0;ii<UE_num_active_CC(UE_list,UE_id);ii++) {
|
||||
CC_id = UE_list->ordered_CCids[ii][UE_id];
|
||||
|
||||
|
||||
if(r1 == 0)
|
||||
nb_rbs_required_remaining[CC_id][i] = nb_rbs_required_remaining_1[CC_id][i];
|
||||
else // rb required based only on the buffer - rb allloctaed in the 1st round + extra reaming rb form the 1st round
|
||||
nb_rbs_required_remaining[CC_id][i] = nb_rbs_required[CC_id][i]-nb_rbs_required_remaining_1[CC_id][i]+nb_rbs_required_remaining[CC_id][i];
|
||||
|
||||
LOG_D(MAC,"round %d : nb_rbs_required_remaining[%d][%d]= %d (remaining_1 %d, required %d, pre_nb_available_rbs %d, N_RBG %d, rb_unit %d)\n",
|
||||
r1, CC_id, i,
|
||||
nb_rbs_required_remaining[CC_id][i],
|
||||
nb_rbs_required_remaining_1[CC_id][i],
|
||||
nb_rbs_required[CC_id][i],
|
||||
pre_nb_available_rbs[CC_id][i],
|
||||
N_RBG[CC_id],
|
||||
min_rb_unit[CC_id]);
|
||||
|
||||
}
|
||||
}
|
||||
// retransmission in control channels
|
||||
for(i=UE_list->head; i>=0;i=UE_list->next[i]) {
|
||||
UE_id = i;
|
||||
for (ii=0;ii<UE_num_active_CC(UE_list,UE_id);ii++) {
|
||||
CC_id = UE_list->ordered_CCids[ii][UE_id];
|
||||
|
||||
if (total_ue_count > 0 ) {
|
||||
for(i=UE_list->head; i>=0;i=UE_list->next[i]) {
|
||||
UE_id = i;
|
||||
for (ii=0;ii<UE_num_active_CC(UE_list,UE_id);ii++) {
|
||||
CC_id = UE_list->ordered_CCids[ii][UE_id];
|
||||
|
||||
|
||||
rnti = UE_RNTI(Mod_id,UE_id);
|
||||
if(rnti == 0)
|
||||
continue;
|
||||
mac_xface->get_ue_active_harq_pid(Mod_id,CC_id,rnti,subframeP,&harq_pid,&round,0);
|
||||
|
||||
if ((mac_get_rrc_status(Mod_id,1,UE_id) < RRC_RECONFIGURED) && (round >0)) {
|
||||
for(j=0;j<N_RBGS[CC_id];j++){
|
||||
rnti = UE_RNTI(Mod_id,UE_id);
|
||||
// LOG_D(MAC,"UE %d rnti 0x\n", UE_id, rnti );
|
||||
if(rnti == 0)
|
||||
continue;
|
||||
transmission_mode = mac_xface->get_transmission_mode(Mod_id,CC_id,rnti);
|
||||
mac_xface->get_ue_active_harq_pid(Mod_id,CC_id,rnti,subframeP,&harq_pid,&round,0);
|
||||
rrc_status = mac_get_rrc_status(Mod_id,1,UE_id);
|
||||
/* 1st allocate for the retx */
|
||||
|
||||
// retransmission in data channels
|
||||
// control channel in the 1st transmission
|
||||
// data channel for all TM
|
||||
LOG_D(MAC,"calling dlsch_scheduler_pre_processor_allocate .. \n ");
|
||||
dlsch_scheduler_pre_processor_allocate (Mod_id,
|
||||
UE_id,
|
||||
CC_id,
|
||||
N_RBG[CC_id],
|
||||
transmission_mode,
|
||||
min_rb_unit[CC_id],
|
||||
frame_parms[CC_id]->N_RB_DL,
|
||||
dl_pow_off,
|
||||
nb_rbs_required,
|
||||
pre_nb_available_rbs,
|
||||
nb_rbs_required_remaining,
|
||||
rballoc_sub_UE,
|
||||
rballoc_sub,
|
||||
MIMO_mode_indicator);
|
||||
|
||||
#ifdef TM5
|
||||
// data chanel TM5: to be revisted
|
||||
if ((round == 0 ) &&
|
||||
(transmission_mode == 5) &&
|
||||
(dl_pow_off[CC_id][UE_id] != 1)){
|
||||
|
||||
for(j=0;j<N_RBG[CC_id];j+=2) {
|
||||
|
||||
if((rballoc_sub[CC_id][j] == 0) && (rballoc_sub_UE[CC_id][UE_id][j] == 0) && (nb_rbs_required_remaining[UE_id]>0)){
|
||||
|
||||
rballoc_sub[CC_id][j] = 1;
|
||||
rballoc_sub_UE[CC_id][UE_id][j] = 1;
|
||||
|
||||
MIMO_mode_indicator[CC_id][j] = 1;
|
||||
|
||||
if(mac_xface->get_transmission_mode(Mod_id,CC_id,rnti)==5)
|
||||
dl_pow_off[CC_id][UE_id] = 1;
|
||||
// if the total rb is odd
|
||||
if ((j == N_RBGS[CC_id]-1) &&
|
||||
((PHY_vars_eNB_g[Mod_id][CC_id]->lte_frame_parms.N_RB_DL == 25)||
|
||||
(PHY_vars_eNB_g[Mod_id][CC_id]->lte_frame_parms.N_RB_DL == 50))) {
|
||||
nb_rbs_required_remaining[CC_id][UE_id] = nb_rbs_required_remaining[CC_id][UE_id] - min_rb_unit[CC_id]+1;
|
||||
pre_nb_available_rbs[CC_id][UE_id] = pre_nb_available_rbs[CC_id][UE_id] + min_rb_unit[CC_id] - 1;
|
||||
}
|
||||
else {
|
||||
nb_rbs_required_remaining[CC_id][UE_id] = nb_rbs_required_remaining[CC_id][UE_id] - min_rb_unit[CC_id];
|
||||
pre_nb_available_rbs[CC_id][UE_id] = pre_nb_available_rbs[CC_id][UE_id] + min_rb_unit[CC_id];
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// retransmission in data channels
|
||||
|
||||
for(i=UE_list->head; i>=0;i=UE_list->next[i]) {
|
||||
UE_id = i;
|
||||
for (ii=0;ii<UE_num_active_CC(UE_list,UE_id);ii++) {
|
||||
CC_id = UE_list->ordered_CCids[ii][UE_id];
|
||||
|
||||
rnti = UE_RNTI(Mod_id,UE_id);
|
||||
if(rnti == 0)
|
||||
continue;
|
||||
mac_xface->get_ue_active_harq_pid(Mod_id,CC_id,rnti,subframeP,&harq_pid,&round,0);
|
||||
|
||||
if ((mac_get_rrc_status(Mod_id,1,UE_id) >= RRC_RECONFIGURED) && (round > 0)) {
|
||||
|
||||
for(j=0;j<N_RBGS[CC_id];j++){
|
||||
|
||||
if((rballoc_sub[CC_id][j] == 0) && (rballoc_sub_UE[CC_id][UE_id][j] == 0) && (nb_rbs_required_remaining[UE_id]>0)){
|
||||
|
||||
rballoc_sub[CC_id][j] = 1;
|
||||
rballoc_sub_UE[CC_id][UE_id][j] = 1;
|
||||
|
||||
MIMO_mode_indicator[CC_id][j] = 1;
|
||||
|
||||
if(mac_xface->get_transmission_mode(Mod_id,CC_id,rnti)==5)
|
||||
dl_pow_off[CC_id][UE_id] = 1;
|
||||
|
||||
if((j == N_RBGS[CC_id]-1) &&
|
||||
((PHY_vars_eNB_g[Mod_id][CC_id]->lte_frame_parms.N_RB_DL == 25)||
|
||||
(PHY_vars_eNB_g[Mod_id][CC_id]->lte_frame_parms.N_RB_DL == 50))){
|
||||
nb_rbs_required_remaining[CC_id][UE_id] = nb_rbs_required_remaining[CC_id][UE_id] - min_rb_unit[CC_id] + 1;
|
||||
pre_nb_available_rbs[CC_id][UE_id] = pre_nb_available_rbs[CC_id][UE_id] + min_rb_unit[CC_id] - 1;
|
||||
}
|
||||
else {
|
||||
nb_rbs_required_remaining[CC_id][UE_id] = nb_rbs_required_remaining[CC_id][UE_id] - min_rb_unit[CC_id];
|
||||
pre_nb_available_rbs[CC_id][UE_id] = pre_nb_available_rbs[CC_id][UE_id] + min_rb_unit[CC_id];
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// control channel in the 1st transmission
|
||||
|
||||
for(i=UE_list->head; i>=0;i=UE_list->next[i]) {
|
||||
UE_id = i;
|
||||
for (ii=0;ii<UE_num_active_CC(UE_list,UE_id);ii++) {
|
||||
CC_id = UE_list->ordered_CCids[ii][UE_id];
|
||||
|
||||
|
||||
rnti = UE_RNTI(Mod_id,UE_id);
|
||||
if(rnti == 0)
|
||||
continue;
|
||||
mac_xface->get_ue_active_harq_pid(Mod_id,CC_id,rnti,subframeP,&harq_pid,&round,0);
|
||||
|
||||
if ((mac_get_rrc_status(Mod_id,1,UE_id) < RRC_RECONFIGURED) && (round == 0)) {
|
||||
|
||||
|
||||
|
||||
|
||||
for(j=0;j<N_RBGS[CC_id];j++){
|
||||
|
||||
if((rballoc_sub[CC_id][j] == 0) && (rballoc_sub_UE[CC_id][UE_id][j] == 0) && (nb_rbs_required_remaining[CC_id][UE_id]>0)){
|
||||
|
||||
rballoc_sub[CC_id][j] = 1;
|
||||
rballoc_sub_UE[CC_id][UE_id][j] = 1;
|
||||
|
||||
MIMO_mode_indicator[CC_id][j] = 1;
|
||||
|
||||
if(mac_xface->get_transmission_mode(Mod_id,CC_id,rnti)==5)
|
||||
dl_pow_off[CC_id][UE_id] = 1;
|
||||
|
||||
if((j == N_RBGS[CC_id]-1) &&
|
||||
((PHY_vars_eNB_g[Mod_id][CC_id]->lte_frame_parms.N_RB_DL == 25)||
|
||||
(PHY_vars_eNB_g[Mod_id][CC_id]->lte_frame_parms.N_RB_DL == 50))){
|
||||
nb_rbs_required_remaining[CC_id][UE_id] = nb_rbs_required_remaining[CC_id][UE_id] - min_rb_unit[CC_id] + 1;
|
||||
pre_nb_available_rbs[CC_id][UE_id] = pre_nb_available_rbs[CC_id][UE_id] + min_rb_unit[CC_id] - 1;
|
||||
}
|
||||
else {
|
||||
nb_rbs_required_remaining[CC_id][UE_id] = nb_rbs_required_remaining[CC_id][UE_id] - min_rb_unit[CC_id];
|
||||
pre_nb_available_rbs[CC_id][UE_id] = pre_nb_available_rbs[CC_id][UE_id] + min_rb_unit[CC_id];
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// data chanel TM5
|
||||
for(i=UE_list->head; i>=0;i=UE_list->next[i]) {
|
||||
UE_id = i;
|
||||
for (ii=0;ii<UE_num_active_CC(UE_list,UE_id);ii++) {
|
||||
CC_id = UE_list->ordered_CCids[ii][UE_id];
|
||||
|
||||
|
||||
rnti1 = UE_RNTI(Mod_id,UE_id);
|
||||
if(rnti1 == 0)
|
||||
continue;
|
||||
|
||||
eNB_UE_stats1 = mac_xface->get_eNB_UE_stats(Mod_id,CC_id,rnti1);
|
||||
|
||||
mac_xface->get_ue_active_harq_pid(Mod_id,CC_id,rnti1,subframeP,&harq_pid1,&round1,0);
|
||||
|
||||
if ((mac_get_rrc_status(Mod_id,1,UE_id) >= RRC_RECONFIGURED) && (round1==0) && (mac_xface->get_transmission_mode(Mod_id,CC_id,rnti1)==5) && (dl_pow_off[CC_id][UE_id] != 1)) {
|
||||
|
||||
|
||||
for(j=0;j<N_RBGS[CC_id];j+=2){
|
||||
|
||||
if((((j == (N_RBGS[CC_id]-1))&& (rballoc_sub[CC_id][j] == 0) && (rballoc_sub_UE[CC_id][UE_id][j] == 0)) || ((j < (N_RBGS[CC_id]-1)) && (rballoc_sub[CC_id][j+1] == 0) && (rballoc_sub_UE[CC_id][UE_id][j+1] == 0))) && (nb_rbs_required_remaining[CC_id][UE_id]>0)){
|
||||
if( (((j == (N_RBG[CC_id]-1))&& (rballoc_sub[CC_id][j] == 0) && (rballoc_sub_UE[CC_id][UE_id][j] == 0)) ||
|
||||
((j < (N_RBG[CC_id]-1)) && (rballoc_sub[CC_id][j+1] == 0) && (rballoc_sub_UE[CC_id][UE_id][j+1] == 0)) ) &&
|
||||
(nb_rbs_required_remaining[CC_id][UE_id]>0)){
|
||||
|
||||
for (ii = UE_list->next[i+1];ii >=0;ii=UE_list->next[ii]) {
|
||||
|
||||
@@ -687,9 +525,14 @@ void dlsch_scheduler_pre_processor (module_id_t Mod_id,
|
||||
eNB_UE_stats2 = mac_xface->get_eNB_UE_stats(Mod_id,CC_id,rnti2);
|
||||
mac_xface->get_ue_active_harq_pid(Mod_id,CC_id,rnti2,subframeP,&harq_pid2,&round2,0);
|
||||
|
||||
if ((mac_get_rrc_status(Mod_id,1,UE_id2) >= RRC_RECONFIGURED) && (round2==0) && (mac_xface->get_transmission_mode(Mod_id,CC_id,rnti2)==5) && (dl_pow_off[CC_id][UE_id2] != 1)) {
|
||||
if ((mac_get_rrc_status(Mod_id,1,UE_id2) >= RRC_RECONFIGURED) &&
|
||||
(round2==0) &&
|
||||
(mac_xface->get_transmission_mode(Mod_id,CC_id,rnti2)==5) &&
|
||||
(dl_pow_off[CC_id][UE_id2] != 1)) {
|
||||
|
||||
if((((j == (N_RBGS[CC_id]-1)) && (rballoc_sub_UE[CC_id][UE_id2][j] == 0)) || ((j < (N_RBGS[CC_id]-1)) && (rballoc_sub_UE[CC_id][UE_id2][j+1] == 0))) && (nb_rbs_required_remaining[CC_id][UE_id2]>0)){
|
||||
if( (((j == (N_RBG[CC_id]-1)) && (rballoc_sub_UE[CC_id][UE_id2][j] == 0)) ||
|
||||
((j < (N_RBG[CC_id]-1)) && (rballoc_sub_UE[CC_id][UE_id2][j+1] == 0)) ) &&
|
||||
(nb_rbs_required_remaining[CC_id][UE_id2]>0)){
|
||||
|
||||
if((((eNB_UE_stats2->DL_pmi_single^eNB_UE_stats1->DL_pmi_single)<<(14-j))&0xc000)== 0x4000){ //MU-MIMO only for 25 RBs configuration
|
||||
|
||||
@@ -698,7 +541,7 @@ void dlsch_scheduler_pre_processor (module_id_t Mod_id,
|
||||
rballoc_sub_UE[CC_id][UE_id2][j] = 1;
|
||||
MIMO_mode_indicator[CC_id][j] = 0;
|
||||
|
||||
if (j< N_RBGS[CC_id]-1) {
|
||||
if (j< N_RBG[CC_id]-1) {
|
||||
rballoc_sub[CC_id][j+1] = 1;
|
||||
rballoc_sub_UE[CC_id][UE_id][j+1] = 1;
|
||||
rballoc_sub_UE[CC_id][UE_id2][j+1] = 1;
|
||||
@@ -709,9 +552,7 @@ void dlsch_scheduler_pre_processor (module_id_t Mod_id,
|
||||
dl_pow_off[CC_id][UE_id2] = 0;
|
||||
|
||||
|
||||
|
||||
|
||||
if ((j == N_RBGS[CC_id]-1) &&
|
||||
if ((j == N_RBG[CC_id]-1) &&
|
||||
((PHY_vars_eNB_g[Mod_id][CC_id]->lte_frame_parms.N_RB_DL == 25) ||
|
||||
(PHY_vars_eNB_g[Mod_id][CC_id]->lte_frame_parms.N_RB_DL == 50))){
|
||||
nb_rbs_required_remaining[CC_id][UE_id] = nb_rbs_required_remaining[CC_id][UE_id] - min_rb_unit[CC_id]+1;
|
||||
@@ -730,93 +571,21 @@ void dlsch_scheduler_pre_processor (module_id_t Mod_id,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
// data channel for all TM
|
||||
|
||||
for(i=UE_list->head; i>=0;i=UE_list->next[i]) {
|
||||
for (ii=0;ii<UE_num_active_CC(UE_list,UE_id);ii++) {
|
||||
CC_id = UE_list->ordered_CCids[ii][UE_id];
|
||||
UE_id = i;
|
||||
|
||||
rnti = UE_RNTI(Mod_id,UE_id);
|
||||
if (rnti == 0)
|
||||
continue;
|
||||
|
||||
mac_xface->get_ue_active_harq_pid(Mod_id,CC_id,rnti,subframeP,&harq_pid,&round,0);
|
||||
|
||||
if ((mac_get_rrc_status(Mod_id,1,UE_id) >= RRC_RECONFIGURED) && (round==0)) {
|
||||
|
||||
|
||||
for(j=0;j<N_RBGS[CC_id];j++){
|
||||
|
||||
if((rballoc_sub[CC_id][j] == 0) && (rballoc_sub_UE[CC_id][UE_id][j] == 0) && (nb_rbs_required_remaining[CC_id][UE_id]>0)){
|
||||
|
||||
|
||||
switch (mac_xface->get_transmission_mode(Mod_id,CC_id,rnti)) {
|
||||
case 1:
|
||||
case 2:
|
||||
case 4:
|
||||
case 6:
|
||||
rballoc_sub[CC_id][j] = 1;
|
||||
rballoc_sub_UE[CC_id][UE_id][j] = 1;
|
||||
|
||||
MIMO_mode_indicator[CC_id][j] = 1;
|
||||
|
||||
if((j == N_RBGS[CC_id]-1) &&
|
||||
((PHY_vars_eNB_g[Mod_id][CC_id]->lte_frame_parms.N_RB_DL == 25)||
|
||||
(PHY_vars_eNB_g[Mod_id][CC_id]->lte_frame_parms.N_RB_DL == 50))){
|
||||
nb_rbs_required_remaining[CC_id][UE_id] = nb_rbs_required_remaining[CC_id][UE_id] - min_rb_unit[CC_id]+1;
|
||||
pre_nb_available_rbs[CC_id][UE_id] = pre_nb_available_rbs[CC_id][UE_id] +min_rb_unit[CC_id]-1;
|
||||
}
|
||||
else {
|
||||
nb_rbs_required_remaining[CC_id][UE_id] = nb_rbs_required_remaining[CC_id][UE_id] - min_rb_unit[CC_id];
|
||||
pre_nb_available_rbs[CC_id][UE_id] = pre_nb_available_rbs[CC_id][UE_id] + min_rb_unit[CC_id];
|
||||
}
|
||||
|
||||
break;
|
||||
case 5:
|
||||
if (dl_pow_off[CC_id][UE_id] != 0){
|
||||
|
||||
dl_pow_off[CC_id][UE_id] = 1;
|
||||
|
||||
rballoc_sub[CC_id][j] = 1;
|
||||
rballoc_sub_UE[CC_id][UE_id][j] = 1;
|
||||
|
||||
MIMO_mode_indicator[CC_id][j] = 1;
|
||||
|
||||
if((j == N_RBGS[CC_id]-1) &&
|
||||
((PHY_vars_eNB_g[Mod_id][CC_id]->lte_frame_parms.N_RB_DL == 25)||
|
||||
(PHY_vars_eNB_g[Mod_id][CC_id]->lte_frame_parms.N_RB_DL == 50))){
|
||||
nb_rbs_required_remaining[CC_id][UE_id] = nb_rbs_required_remaining[CC_id][UE_id] - min_rb_unit[CC_id]+1;
|
||||
pre_nb_available_rbs[CC_id][UE_id] = pre_nb_available_rbs[CC_id][UE_id] + min_rb_unit[CC_id]-1;
|
||||
}
|
||||
else {
|
||||
nb_rbs_required_remaining[CC_id][UE_id] = nb_rbs_required_remaining[CC_id][UE_id] - min_rb_unit[CC_id];
|
||||
pre_nb_available_rbs[CC_id][UE_id] = pre_nb_available_rbs[CC_id][UE_id] + min_rb_unit[CC_id];
|
||||
}
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
} // total_ue_count
|
||||
} // end of for for r1 and r2
|
||||
#ifdef TM5
|
||||
// This has to be revisited!!!!
|
||||
for (CC_id=0;CC_id<MAX_NUM_CCs;CC_id++) {
|
||||
i1=0;
|
||||
i2=0;
|
||||
i3=0;
|
||||
for (j=0;j<N_RBGS[CC_id];j++){
|
||||
for (j=0;j<N_RBG[CC_id];j++){
|
||||
if(MIMO_mode_indicator[CC_id][j] == 2)
|
||||
i1 = i1+1;
|
||||
else if(MIMO_mode_indicator[CC_id][j] == 1)
|
||||
@@ -824,21 +593,20 @@ void dlsch_scheduler_pre_processor (module_id_t Mod_id,
|
||||
else if(MIMO_mode_indicator[CC_id][j] == 0)
|
||||
i3 = i3+1;
|
||||
}
|
||||
|
||||
|
||||
if((i1 < N_RBGS[CC_id]) && (i2>0) && (i3==0))
|
||||
if((i1 < N_RBG[CC_id]) && (i2>0) && (i3==0))
|
||||
PHY_vars_eNB_g[Mod_id][CC_id]->check_for_SUMIMO_transmissions = PHY_vars_eNB_g[Mod_id][CC_id]->check_for_SUMIMO_transmissions + 1;
|
||||
|
||||
if(i3 == N_RBGS[CC_id] && i1==0 && i2==0)
|
||||
if(i3 == N_RBG[CC_id] && i1==0 && i2==0)
|
||||
PHY_vars_eNB_g[Mod_id][CC_id]->FULL_MUMIMO_transmissions = PHY_vars_eNB_g[Mod_id][CC_id]->FULL_MUMIMO_transmissions + 1;
|
||||
|
||||
if((i1 < N_RBGS[CC_id]) && (i3 > 0))
|
||||
if((i1 < N_RBG[CC_id]) && (i3 > 0))
|
||||
PHY_vars_eNB_g[Mod_id][CC_id]->check_for_MUMIMO_transmissions = PHY_vars_eNB_g[Mod_id][CC_id]->check_for_MUMIMO_transmissions + 1;
|
||||
|
||||
PHY_vars_eNB_g[Mod_id][CC_id]->check_for_total_transmissions = PHY_vars_eNB_g[Mod_id][CC_id]->check_for_total_transmissions + 1;
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
for(i=UE_list->head; i>=0;i=UE_list->next[i]) {
|
||||
for (ii=0;ii<UE_num_active_CC(UE_list,UE_id);ii++) {
|
||||
@@ -848,7 +616,7 @@ void dlsch_scheduler_pre_processor (module_id_t Mod_id,
|
||||
LOG_D(MAC,"******************Scheduling Information for UE%d ************************\n",UE_id);
|
||||
LOG_D(MAC,"dl power offset UE%d = %d \n",UE_id,dl_pow_off[CC_id][UE_id]);
|
||||
LOG_D(MAC,"***********RB Alloc for every subband for UE%d ***********\n",UE_id);
|
||||
for(j=0;j<N_RBGS[CC_id];j++){
|
||||
for(j=0;j<N_RBG[CC_id];j++){
|
||||
//PHY_vars_eNB_g[Mod_id]->mu_mimo_mode[UE_id].rballoc_sub[i] = rballoc_sub_UE[CC_id][UE_id][i];
|
||||
LOG_D(MAC,"RB Alloc for UE%d and Subband%d = %d\n",UE_id,j,rballoc_sub_UE[CC_id][UE_id][j]);
|
||||
}
|
||||
@@ -858,3 +626,80 @@ void dlsch_scheduler_pre_processor (module_id_t Mod_id,
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dlsch_scheduler_pre_processor_reset (int UE_id,
|
||||
uint8_t CC_id,
|
||||
int N_RBG,
|
||||
uint8_t dl_pow_off[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
|
||||
uint16_t nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
|
||||
uint16_t pre_nb_available_rbs[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
|
||||
uint16_t nb_rbs_required_remaining[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
|
||||
unsigned char rballoc_sub_UE[MAX_NUM_CCs][NUMBER_OF_UE_MAX][N_RBG_MAX],
|
||||
unsigned char rballoc_sub[MAX_NUM_CCs][13],
|
||||
unsigned char MIMO_mode_indicator[MAX_NUM_CCs][13]){
|
||||
int i;
|
||||
nb_rbs_required[CC_id][UE_id]=0;
|
||||
pre_nb_available_rbs[CC_id][UE_id] = 0;
|
||||
dl_pow_off[CC_id][UE_id] = 2;
|
||||
nb_rbs_required_remaining[CC_id][UE_id] = 0;
|
||||
for (i=0;i<N_RBG;i++){
|
||||
rballoc_sub_UE[CC_id][UE_id][i] = 0;
|
||||
rballoc_sub[CC_id][i] = 0;
|
||||
MIMO_mode_indicator[CC_id][i] = 2;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dlsch_scheduler_pre_processor_allocate (module_id_t Mod_id,
|
||||
int UE_id,
|
||||
uint8_t CC_id,
|
||||
int N_RBG,
|
||||
int transmission_mode,
|
||||
int min_rb_unit,
|
||||
uint8_t N_RB_DL,
|
||||
uint8_t dl_pow_off[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
|
||||
uint16_t nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
|
||||
uint16_t pre_nb_available_rbs[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
|
||||
uint16_t nb_rbs_required_remaining[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
|
||||
unsigned char rballoc_sub_UE[MAX_NUM_CCs][NUMBER_OF_UE_MAX][N_RBG_MAX],
|
||||
unsigned char rballoc_sub[MAX_NUM_CCs][13],
|
||||
unsigned char MIMO_mode_indicator[MAX_NUM_CCs][13]){
|
||||
|
||||
int i;
|
||||
|
||||
for(i=0;i<N_RBG;i++){
|
||||
|
||||
if((rballoc_sub[CC_id][i] == 0) &&
|
||||
(rballoc_sub_UE[CC_id][UE_id][i] == 0) &&
|
||||
(nb_rbs_required_remaining[UE_id]>0) &&
|
||||
(pre_nb_available_rbs[CC_id][UE_id] < nb_rbs_required[CC_id][UE_id])){
|
||||
|
||||
// if this UE is not scheduled for TM5
|
||||
if (dl_pow_off[CC_id][UE_id] != 0 ) {
|
||||
|
||||
rballoc_sub[CC_id][i] = 1;
|
||||
rballoc_sub_UE[CC_id][UE_id][i] = 1;
|
||||
MIMO_mode_indicator[CC_id][i] = 1;
|
||||
|
||||
if (transmission_mode == 5 )
|
||||
dl_pow_off[CC_id][UE_id] = 1;
|
||||
|
||||
if ((i == N_RBG-1) && ((N_RB_DL == 25) || (N_RB_DL == 50))) {
|
||||
nb_rbs_required_remaining[CC_id][UE_id] = nb_rbs_required_remaining[CC_id][UE_id] - min_rb_unit+1;
|
||||
pre_nb_available_rbs[CC_id][UE_id] = pre_nb_available_rbs[CC_id][UE_id] + min_rb_unit - 1;
|
||||
}
|
||||
else {
|
||||
nb_rbs_required_remaining[CC_id][UE_id] = nb_rbs_required_remaining[CC_id][UE_id] - min_rb_unit;
|
||||
pre_nb_available_rbs[CC_id][UE_id] = pre_nb_available_rbs[CC_id][UE_id] + min_rb_unit;
|
||||
}
|
||||
} // dl_pow_off[CC_id][UE_id] ! = 0
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user