From 2fe218e91a59d154343a3c07634a460a92ebce1b Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Wed, 18 Nov 2015 14:18:58 -0800 Subject: [PATCH] Moved CCE allocations from PHY to MAC and updated MAC interfaces for BCCH/RA/UE-SPEC scheduling. --- openair1/PHY/CODING/lte_rate_matching.c | 9 +- openair1/PHY/LTE_TRANSPORT/dci.c | 18 +- openair1/PHY/LTE_TRANSPORT/defs.h | 6 +- openair1/PHY/LTE_TRANSPORT/dlsch_coding.c | 5 +- openair1/PHY/LTE_TRANSPORT/dlsch_decoding.c | 5 +- openair1/PHY/LTE_TRANSPORT/proto.h | 19 +- openair1/SCHED/defs.h | 1 - openair1/SCHED/phy_procedures_lte_eNb.c | 225 ++----- openair1/SIMULATION/LTE_PHY/dlsim.c | 32 +- openair2/LAYER2/MAC/defs.h | 13 +- openair2/LAYER2/MAC/eNB_scheduler.c | 188 +++--- openair2/LAYER2/MAC/eNB_scheduler_RA.c | 560 +++++++++++---- openair2/LAYER2/MAC/eNB_scheduler_bch.c | 150 ++++- openair2/LAYER2/MAC/eNB_scheduler_dlsch.c | 635 +----------------- .../LAYER2/MAC/eNB_scheduler_primitives.c | 205 ++++++ openair2/LAYER2/MAC/eNB_scheduler_ulsch.c | 55 +- openair2/LAYER2/MAC/main.c | 2 +- openair2/LAYER2/MAC/pre_processor.c | 13 +- openair2/LAYER2/MAC/proto.h | 48 +- openair2/PHY_INTERFACE/defs.h | 3 +- targets/SIMU/USER/init_lte.c | 20 +- 21 files changed, 1083 insertions(+), 1129 deletions(-) diff --git a/openair1/PHY/CODING/lte_rate_matching.c b/openair1/PHY/CODING/lte_rate_matching.c index 69697fc2e0..96663bd8a6 100644 --- a/openair1/PHY/CODING/lte_rate_matching.c +++ b/openair1/PHY/CODING/lte_rate_matching.c @@ -36,6 +36,7 @@ #include #endif #include "PHY/defs.h" +#include "assertions.h" //#define cmin(a,b) ((a)<(b) ? (a) : (b)) @@ -515,16 +516,14 @@ uint32_t lte_rate_matching_turbo(uint32_t RTC, // if (rvidx==3) // for (cnt=0;cnt=(3*RTC<<5),"Exiting, RM condition (Ncb %d, Nir/C %d, Nsoft %d, Kw %d\n",Ncb,Nir/C,Nsoft,3*(RTC<<5)); + Gp = G/Nl/Qm; GpmodC = Gp%C; #ifdef RM_DEBUG - printf("lte_rate_matching_turbo: Kw %d, rvidx %d, G %d, Qm %d, Nl%d, r %d\n",3*(RTC<<5),rvidx, G, Qm,Nl,r); + printf("lte_rate_matching_turbo: Ncb %d, Kw %d, Nir/C %d, rvidx %d, G %d, Qm %d, Nl%d, r %d\n",Ncb,3*(RTC<<5),Nir/C,rvidx, G, Qm,Nl,r); #endif if (r < (C-(GpmodC))) diff --git a/openair1/PHY/LTE_TRANSPORT/dci.c b/openair1/PHY/LTE_TRANSPORT/dci.c index 2fd89c8f64..f126d0e2ea 100644 --- a/openair1/PHY/LTE_TRANSPORT/dci.c +++ b/openair1/PHY/LTE_TRANSPORT/dci.c @@ -2108,14 +2108,14 @@ uint8_t generate_dci_top(uint8_t num_ue_spec_dci, if (dci_alloc[i].L == (uint8_t)L) { #ifdef DEBUG_DCI_ENCODING - LOG_I(PHY,"Generating common DCI %d/%d (nCCE %d) of length %d, aggregation %d (%x)\n",i,num_common_dci,dci_alloc[i].nCCE,dci_alloc[i].dci_length,1<=0) { + if (dci_alloc[i].firstCCE>=0) { e_ptr = generate_dci0(dci_alloc[i].dci_pdu, - e+(72*dci_alloc[i].nCCE), + e+(72*dci_alloc[i].firstCCE), dci_alloc[i].dci_length, dci_alloc[i].L, dci_alloc[i].rnti); @@ -2133,9 +2133,9 @@ uint8_t generate_dci_top(uint8_t num_ue_spec_dci, dump_dci(frame_parms,&dci_alloc[i]); #endif - if (dci_alloc[i].nCCE >= 0) { + if (dci_alloc[i].firstCCE >= 0) { e_ptr = generate_dci0(dci_alloc[i].dci_pdu, - e+(72*dci_alloc[i].nCCE), + e+(72*dci_alloc[i].firstCCE), dci_alloc[i].dci_length, dci_alloc[i].L, dci_alloc[i].rnti); @@ -2537,11 +2537,13 @@ uint16_t get_nquad(uint8_t num_pdcch_symbols,LTE_DL_FRAME_PARMS *frame_parms,uin return(Nreg - 4 - (3*Ngroup_PHICH)); } -uint16_t get_nCCE_max(uint8_t Mod_id,uint8_t CC_id) +uint16_t get_nCCE_mac(uint8_t Mod_id,uint8_t CC_id,int num_pdcch_symbols,int subframe) { // check for eNB only ! - return(get_nCCE(3,&PHY_vars_eNB_g[Mod_id][CC_id]->lte_frame_parms,1)); // 5, 15,21 + return(get_nCCE(num_pdcch_symbols, + &PHY_vars_eNB_g[Mod_id][CC_id]->lte_frame_parms, + get_mi(&PHY_vars_eNB_g[Mod_id][CC_id]->lte_frame_parms,subframe))); } void dci_decoding_procedure0(LTE_UE_PDCCH **lte_ue_pdcch_vars, @@ -2691,7 +2693,7 @@ void dci_decoding_procedure0(LTE_UE_PDCCH **lte_ue_pdcch_vars, dci_alloc[*dci_cnt].dci_length = sizeof_bits; dci_alloc[*dci_cnt].rnti = crc; dci_alloc[*dci_cnt].L = L; - dci_alloc[*dci_cnt].nCCE = CCEind; + dci_alloc[*dci_cnt].firstCCE = CCEind; if (sizeof_bytes<=4) { dci_alloc[*dci_cnt].dci_pdu[3] = dci_decoded_output[0]; diff --git a/openair1/PHY/LTE_TRANSPORT/defs.h b/openair1/PHY/LTE_TRANSPORT/defs.h index 8b23c51079..f25e199e9d 100644 --- a/openair1/PHY/LTE_TRANSPORT/defs.h +++ b/openair1/PHY/LTE_TRANSPORT/defs.h @@ -266,6 +266,8 @@ typedef struct { uint8_t Mdlharq; /// MIMO transmission mode indicator for this sub-frame (for definition see 36-212 V8.6 2009-03, p.17) uint8_t Kmimo; + /// Nsoft parameter related to UE Category + uint32_t Nsoft; /// amplitude of PDSCH (compared to RS) in symbols without pilots int16_t sqrt_rho_a; /// amplitude of PDSCH (compared to RS) in symbols containing pilots @@ -693,6 +695,8 @@ typedef struct { uint8_t Mdlharq; /// MIMO transmission mode indicator for this sub-frame (for definition see 36-212 V8.6 2009-03, p.17) uint8_t Kmimo; + /// Nsoft parameter related to UE Category + uint32_t Nsoft; /// Maximum number of Turbo iterations uint8_t max_turbo_iterations; /// accumulated tx power adjustment for PUCCH @@ -737,7 +741,7 @@ typedef struct { /// Aggregation level uint8_t L; /// Position of first CCE of the dci - int nCCE; + int firstCCE; /// flag to indicate that this is a RA response boolean_t ra_flag; /// rnti diff --git a/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c b/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c index 83066480b4..a2f33f0fb2 100644 --- a/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c +++ b/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c @@ -117,7 +117,7 @@ void free_eNB_dlsch(LTE_eNB_DLSCH_t *dlsch) } -LTE_eNB_DLSCH_t *new_eNB_dlsch(unsigned char Kmimo,unsigned char Mdlharq,unsigned char N_RB_DL, uint8_t abstraction_flag) +LTE_eNB_DLSCH_t *new_eNB_dlsch(unsigned char Kmimo,unsigned char Mdlharq,uint32_t Nsoft,unsigned char N_RB_DL, uint8_t abstraction_flag) { LTE_eNB_DLSCH_t *dlsch; @@ -148,6 +148,7 @@ LTE_eNB_DLSCH_t *new_eNB_dlsch(unsigned char Kmimo,unsigned char Mdlharq,unsigne bzero(dlsch,sizeof(LTE_eNB_DLSCH_t)); dlsch->Kmimo = Kmimo; dlsch->Mdlharq = Mdlharq; + dlsch->Nsoft = Nsoft; for (i=0; i<10; i++) dlsch->harq_ids[i] = Mdlharq; @@ -395,7 +396,7 @@ int dlsch_encoding(unsigned char *a, dlsch->harq_processes[harq_pid]->w[r], dlsch->harq_processes[harq_pid]->e+r_offset, dlsch->harq_processes[harq_pid]->C, // C - NSOFT, // Nsoft, + dlsch->Nsoft, // Nsoft, dlsch->Mdlharq, dlsch->Kmimo, dlsch->harq_processes[harq_pid]->rvidx, diff --git a/openair1/PHY/LTE_TRANSPORT/dlsch_decoding.c b/openair1/PHY/LTE_TRANSPORT/dlsch_decoding.c index 6ab784aa18..efcd868338 100644 --- a/openair1/PHY/LTE_TRANSPORT/dlsch_decoding.c +++ b/openair1/PHY/LTE_TRANSPORT/dlsch_decoding.c @@ -81,7 +81,7 @@ void free_ue_dlsch(LTE_UE_DLSCH_t *dlsch) } } -LTE_UE_DLSCH_t *new_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint8_t max_turbo_iterations,uint8_t N_RB_DL, uint8_t abstraction_flag) +LTE_UE_DLSCH_t *new_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint8_t max_turbo_iterations,uint8_t N_RB_DL, uint8_t abstraction_flag) { LTE_UE_DLSCH_t *dlsch; @@ -113,6 +113,7 @@ LTE_UE_DLSCH_t *new_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint8_t max_turbo_ite memset(dlsch,0,sizeof(LTE_UE_DLSCH_t)); dlsch->Kmimo = Kmimo; dlsch->Mdlharq = Mdlharq; + dlsch->Nsoft = Nsoft; dlsch->max_turbo_iterations = max_turbo_iterations; for (i=0; iC, - NSOFT, + dlsch->Nsoft, dlsch->Mdlharq, dlsch->Kmimo, harq_process->rvidx, diff --git a/openair1/PHY/LTE_TRANSPORT/proto.h b/openair1/PHY/LTE_TRANSPORT/proto.h index e472e30676..8506891e6d 100644 --- a/openair1/PHY/LTE_TRANSPORT/proto.h +++ b/openair1/PHY/LTE_TRANSPORT/proto.h @@ -56,15 +56,16 @@ void free_eNB_dlsch(LTE_eNB_DLSCH_t *dlsch); void clean_eNb_dlsch(LTE_eNB_DLSCH_t *dlsch, uint8_t abstraction_flag); -/** \fn new_eNB_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint8_t abstraction_flag) +/** \fn new_eNB_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint8_t abstraction_flag) \brief This function allocates structures for a particular DLSCH at eNB @returns Pointer to DLSCH to be removed @param Kmimo Kmimo factor from 36-212/36-213 @param Mdlharq Maximum number of HARQ rounds (36-212/36-213) + @param Nsoft Soft-LLR buffer size from UE-Category @params N_RB_DL total number of resource blocks (determine the operating BW) @param abstraction_flag Flag to indicate abstracted interface */ -LTE_eNB_DLSCH_t *new_eNB_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint8_t N_RB_DL, uint8_t abstraction_flag); +LTE_eNB_DLSCH_t *new_eNB_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint8_t N_RB_DL, uint8_t abstraction_flag); /** \fn free_ue_dlsch(LTE_UE_DLSCH_t *dlsch) \brief This function frees memory allocated for a particular DLSCH at UE @@ -72,8 +73,16 @@ LTE_eNB_DLSCH_t *new_eNB_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint8_t N_RB_DL, ui */ void free_ue_dlsch(LTE_UE_DLSCH_t *dlsch); -LTE_UE_DLSCH_t *new_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint8_t max_turbo_iterations,uint8_t N_RB_DL, uint8_t abstraction_flag); - +/** \fn new_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint8_t abstraction_flag) + \brief This function allocates structures for a particular DLSCH at eNB + @returns Pointer to DLSCH to be removed + @param Kmimo Kmimo factor from 36-212/36-213 + @param Mdlharq Maximum number of HARQ rounds (36-212/36-213) + @param Nsoft Soft-LLR buffer size from UE-Category + @params N_RB_DL total number of resource blocks (determine the operating BW) + @param abstraction_flag Flag to indicate abstracted interface +*/ +LTE_UE_DLSCH_t *new_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint8_t max_turbo_iterations,uint8_t N_RB_DL, uint8_t abstraction_flag); void clean_eNb_ulsch(LTE_eNB_ULSCH_t *ulsch, uint8_t abstraction_flag); @@ -1581,7 +1590,7 @@ uint16_t get_nquad(uint8_t num_pdcch_symbols,LTE_DL_FRAME_PARMS *frame_parms,uin uint8_t get_mi(LTE_DL_FRAME_PARMS *frame,uint8_t subframe); -uint16_t get_nCCE_max(uint8_t Mod_id,uint8_t CC_id); +uint16_t get_nCCE_mac(uint8_t Mod_id,uint8_t CC_id,int num_pdcch_symbols,int subframe); uint8_t get_num_pdcch_symbols(uint8_t num_dci,DCI_ALLOC_t *dci_alloc,LTE_DL_FRAME_PARMS *frame_parms,uint8_t subframe); diff --git a/openair1/SCHED/defs.h b/openair1/SCHED/defs.h index bebe476dcd..bcf2c213c2 100644 --- a/openair1/SCHED/defs.h +++ b/openair1/SCHED/defs.h @@ -399,7 +399,6 @@ uint32_t pdcch_alloc2ul_frame(LTE_DL_FRAME_PARMS *frame_parms,uint32_t frame, ui uint16_t get_Np(uint8_t N_RB_DL,uint8_t nCCE,uint8_t plus1); -int get_nCCE_offset(unsigned char L, int nCCE, int common_dci, unsigned short rnti, unsigned char subframe); int8_t find_ue(uint16_t rnti, PHY_VARS_eNB *phy_vars_eNB); diff --git a/openair1/SCHED/phy_procedures_lte_eNb.c b/openair1/SCHED/phy_procedures_lte_eNb.c index b9cb618ea0..cb78f429b5 100755 --- a/openair1/SCHED/phy_procedures_lte_eNb.c +++ b/openair1/SCHED/phy_procedures_lte_eNb.c @@ -296,100 +296,6 @@ int get_ue_active_harq_pid(const uint8_t Mod_id,const uint8_t CC_id,const uint16 } -int CCE_table[800]; - -void init_nCCE_table(void) -{ - memset(CCE_table,0,800*sizeof(int)); -} - - -int get_nCCE_offset(const unsigned char L, const int nCCE, const int common_dci, const unsigned short rnti, const unsigned char subframe) -{ - - int search_space_free,m,nb_candidates = 0,l,i; - unsigned int Yk; - - /* - printf("CCE Allocation: "); - for (i=0;i=0 ; m--) { - search_space_free = 1; - for (l=0; lPHY_measurements_eNB[0].n0_power_tot_dBm; @@ -1811,15 +1717,18 @@ void phy_procedures_eNB_TX(unsigned char sched_subframe,PHY_VARS_eNB *phy_vars_e phy_vars_eNB->dlsch_eNB[i][0]->subframe_tx[subframe] = 0; } - init_nCCE_table(); + // init_nCCE_table(); - num_pdcch_symbols = get_num_pdcch_symbols(DCI_pdu->Num_common_dci + DCI_pdu->Num_ue_spec_dci, - DCI_pdu->dci_alloc, - &phy_vars_eNB->lte_frame_parms, - subframe); + num_pdcch_symbols = DCI_pdu->num_pdcch_symbols; + /*get_num_pdcch_symbols(DCI_pdu->Num_common_dci + DCI_pdu->Num_ue_spec_dci, + DCI_pdu->dci_alloc, + &phy_vars_eNB->lte_frame_parms, + subframe);*/ + /* DCI_pdu->nCCE = get_nCCE(num_pdcch_symbols, &phy_vars_eNB->lte_frame_parms, - get_mi(&phy_vars_eNB->lte_frame_parms,subframe)); + get_mi(&phy_vars_eNB->lte_frame_parms,subframe));*/ + LOG_D(PHY,"num_pdcch_symbols %"PRIu8", nCCE %u (dci commond %"PRIu8", dci uespec %"PRIu8"\n",num_pdcch_symbols,DCI_pdu->nCCE, DCI_pdu->Num_common_dci,DCI_pdu->Num_ue_spec_dci); @@ -1835,6 +1744,7 @@ void phy_procedures_eNB_TX(unsigned char sched_subframe,PHY_VARS_eNB *phy_vars_e #endif for (i=0; iNum_common_dci + DCI_pdu->Num_ue_spec_dci ; i++) { + LOG_D(PHY,"[eNB] Subframe %d: DCI %d/%d : rnti %x, CCEind %d\n",subframe,i,DCI_pdu->Num_common_dci+DCI_pdu->Num_ue_spec_dci,DCI_pdu->dci_alloc[i].rnti,DCI_pdu->dci_alloc[i].firstCCE); #ifdef DEBUG_PHY_PROC if (DCI_pdu->dci_alloc[i].rnti != SI_RNTI) { @@ -1862,28 +1772,21 @@ void phy_procedures_eNB_TX(unsigned char sched_subframe,PHY_VARS_eNB *phy_vars_e phy_vars_eNB->eNB_UE_stats[0].DL_pmi_single); - int result = get_nCCE_offset(1<dci_alloc[i].L, DCI_pdu->nCCE, 1, SI_RNTI, subframe); - phy_vars_eNB->dlsch_eNB_SI->nCCE[subframe] = result; - - if (result == -1) { - // FIXME what happens to phy_vars_eNB->dlsch_eNB_SI->nCCE[subframe]? - LOG_E(PHY,"[eNB %"PRIu8"] Frame %d subframe %d : No available CCE resources for common DCI (SI)!!!\n",phy_vars_eNB->Mod_id,phy_vars_eNB->proc[sched_subframe].frame_tx,subframe); - } else { - LOG_T(PHY,"[eNB %"PRIu8"] Frame %d subframe %d : CCE resource for common DCI (SI) => %"PRIu8"/%u\n",phy_vars_eNB->Mod_id,phy_vars_eNB->proc[sched_subframe].frame_tx,subframe, - phy_vars_eNB->dlsch_eNB_SI->nCCE[subframe],DCI_pdu->nCCE); + phy_vars_eNB->dlsch_eNB_SI->nCCE[subframe] = DCI_pdu->dci_alloc[i].firstCCE; + LOG_T(PHY,"[eNB %"PRIu8"] Frame %d subframe %d : CCE resource for common DCI (SI) => %"PRIu8"/%u\n",phy_vars_eNB->Mod_id,phy_vars_eNB->proc[sched_subframe].frame_tx,subframe, + phy_vars_eNB->dlsch_eNB_SI->nCCE[subframe],DCI_pdu->nCCE); + #if defined(SMBV) && !defined(EXMIMO) - // configure SI DCI - if (smbv_is_config_frame(phy_vars_eNB->proc[sched_subframe].frame_tx) && (smbv_frame_cnt < 4)) { - msg("[SMBV] Frame %3d, SI in SF %d DCI %"PRIu32"\n",phy_vars_eNB->proc[sched_subframe].frame_tx,subframe,i); - smbv_configure_common_dci(smbv_fname,(smbv_frame_cnt*10) + (subframe), "SI", &DCI_pdu->dci_alloc[i], i); - } - -#endif + // configure SI DCI + if (smbv_is_config_frame(phy_vars_eNB->proc[sched_subframe].frame_tx) && (smbv_frame_cnt < 4)) { + msg("[SMBV] Frame %3d, SI in SF %d DCI %"PRIu32"\n",phy_vars_eNB->proc[sched_subframe].frame_tx,subframe,i); + smbv_configure_common_dci(smbv_fname,(smbv_frame_cnt*10) + (subframe), "SI", &DCI_pdu->dci_alloc[i], i); } - - DCI_pdu->dci_alloc[i].nCCE = phy_vars_eNB->dlsch_eNB_SI->nCCE[subframe]; + +#endif + } else if (DCI_pdu->dci_alloc[i].ra_flag == 1) { #ifdef DEBUG_PHY_PROC @@ -1904,28 +1807,20 @@ void phy_procedures_eNB_TX(unsigned char sched_subframe,PHY_VARS_eNB *phy_vars_e // mac_xface->macphy_exit("Transmitted RAR, exiting\n"); - int result = get_nCCE_offset(1<dci_alloc[i].L, DCI_pdu->nCCE, 1, DCI_pdu->dci_alloc[i].rnti, subframe); - phy_vars_eNB->dlsch_eNB_ra->nCCE[subframe] = result; - if (result == -1) { - // FIXME what happens to phy_vars_eNB->dlsch_eNB_ra->nCCE[subframe]? - LOG_E(PHY,"[eNB %"PRIu8"] Frame %d subframe %d : No available CCE resources for common DCI (RA) !!!\n",phy_vars_eNB->Mod_id,phy_vars_eNB->proc[sched_subframe].frame_tx,subframe); - } else { - LOG_D(PHY,"[eNB %"PRIu8"] Frame %d subframe %d : CCE resource for common DCI (RA) => %"PRIu8"/%u\n",phy_vars_eNB->Mod_id,phy_vars_eNB->proc[sched_subframe].frame_tx,subframe, - phy_vars_eNB->dlsch_eNB_ra->nCCE[subframe],DCI_pdu->nCCE); + phy_vars_eNB->dlsch_eNB_ra->nCCE[subframe] = DCI_pdu->dci_alloc[i].firstCCE; + + LOG_D(PHY,"[eNB %"PRIu8"] Frame %d subframe %d : CCE resource for common DCI (RA) => %"PRIu8"/%u\n",phy_vars_eNB->Mod_id,phy_vars_eNB->proc[sched_subframe].frame_tx,subframe, + phy_vars_eNB->dlsch_eNB_ra->nCCE[subframe],DCI_pdu->nCCE); #if defined(SMBV) && !defined(EXMIMO) - // configure RA DCI - if (smbv_is_config_frame(phy_vars_eNB->proc[sched_subframe].frame_tx) && (smbv_frame_cnt < 4)) { - msg("[SMBV] Frame %3d, RA in SF %d DCI %"PRIu32"\n",phy_vars_eNB->proc[sched_subframe].frame_tx,subframe,i); - smbv_configure_common_dci(smbv_fname,(smbv_frame_cnt*10) + (subframe), "RA", &DCI_pdu->dci_alloc[i], i); - } - -#endif - + // configure RA DCI + if (smbv_is_config_frame(phy_vars_eNB->proc[sched_subframe].frame_tx) && (smbv_frame_cnt < 4)) { + msg("[SMBV] Frame %3d, RA in SF %d DCI %"PRIu32"\n",phy_vars_eNB->proc[sched_subframe].frame_tx,subframe,i); + smbv_configure_common_dci(smbv_fname,(smbv_frame_cnt*10) + (subframe), "RA", &DCI_pdu->dci_alloc[i], i); } - DCI_pdu->dci_alloc[i].nCCE = phy_vars_eNB->dlsch_eNB_ra->nCCE[subframe]; +#endif } @@ -1966,30 +1861,22 @@ void phy_procedures_eNB_TX(unsigned char sched_subframe,PHY_VARS_eNB *phy_vars_e LOG_D(PHY,"[eNB %"PRIu8"][PDSCH %"PRIx16"/%"PRIu8"] Frame %d subframe %d: Generated dlsch params\n", phy_vars_eNB->Mod_id,DCI_pdu->dci_alloc[i].rnti,phy_vars_eNB->dlsch_eNB[(uint8_t)UE_id][0]->current_harq_pid,phy_vars_eNB->proc[sched_subframe].frame_tx,subframe); - int result = get_nCCE_offset(1<dci_alloc[i].L, DCI_pdu->nCCE, 0, DCI_pdu->dci_alloc[i].rnti, subframe); - phy_vars_eNB->dlsch_eNB[(uint8_t)UE_id][0]->nCCE[subframe] = result; - if (result == -1) { - // FIXME what happens to phy_vars_eNB->dlsch_eNB[(uint8_t)UE_id][0]->nCCE[subframe]? - LOG_E(PHY,"[eNB %"PRIu8"] Frame %d subframe %d : No available CCE resources for UE spec DCI (PDSCH %"PRIx16") !!!\n", - phy_vars_eNB->Mod_id,phy_vars_eNB->proc[sched_subframe].frame_tx,subframe,DCI_pdu->dci_alloc[i].rnti); - } else { - LOG_D(PHY,"[eNB %"PRIu8"] Frame %d subframe %d : CCE resource for ue DCI (PDSCH %"PRIx16") => %"PRIu8"/%u\n",phy_vars_eNB->Mod_id,phy_vars_eNB->proc[sched_subframe].frame_tx,subframe, - DCI_pdu->dci_alloc[i].rnti,phy_vars_eNB->dlsch_eNB[(uint8_t)UE_id][0]->nCCE[subframe],DCI_pdu->nCCE); + phy_vars_eNB->dlsch_eNB[(uint8_t)UE_id][0]->nCCE[subframe] = DCI_pdu->dci_alloc[i].firstCCE; + + LOG_D(PHY,"[eNB %"PRIu8"] Frame %d subframe %d : CCE resource for ue DCI (PDSCH %"PRIx16") => %"PRIu8"/%u\n",phy_vars_eNB->Mod_id,phy_vars_eNB->proc[sched_subframe].frame_tx,subframe, + DCI_pdu->dci_alloc[i].rnti,phy_vars_eNB->dlsch_eNB[(uint8_t)UE_id][0]->nCCE[subframe],DCI_pdu->nCCE); #if defined(SMBV) && !defined(EXMIMO) - DCI_pdu->dci_alloc[i].nCCE = phy_vars_eNB->dlsch_eNB[(uint8_t)UE_id][0]->nCCE[subframe]; - - // configure UE-spec DCI - if (smbv_is_config_frame(phy_vars_eNB->proc[sched_subframe].frame_tx) && (smbv_frame_cnt < 4)) { - msg("[SMBV] Frame %3d, PDSCH in SF %d DCI %"PRIu32"\n",phy_vars_eNB->proc[sched_subframe].frame_tx,subframe,i); - smbv_configure_ue_spec_dci(smbv_fname,(smbv_frame_cnt*10) + (subframe), UE_id+1, &DCI_pdu->dci_alloc[i], i); - } + + // configure UE-spec DCI + if (smbv_is_config_frame(phy_vars_eNB->proc[sched_subframe].frame_tx) && (smbv_frame_cnt < 4)) { + msg("[SMBV] Frame %3d, PDSCH in SF %d DCI %"PRIu32"\n",phy_vars_eNB->proc[sched_subframe].frame_tx,subframe,i); + smbv_configure_ue_spec_dci(smbv_fname,(smbv_frame_cnt*10) + (subframe), UE_id+1, &DCI_pdu->dci_alloc[i], i); + } #endif - } - DCI_pdu->dci_alloc[i].nCCE = phy_vars_eNB->dlsch_eNB[(uint8_t)UE_id][0]->nCCE[subframe]; #ifdef DEBUG_PHY_PROC //if (phy_vars_eNB->proc[sched_subframe].frame_tx%100 == 0) LOG_D(PHY,"[eNB %"PRIu8"][DCI][PDSCH %"PRIx16"] Frame %d subframe %d UE_id %"PRId8" Generated DCI format %d, aggregation %d\n", @@ -2067,29 +1954,21 @@ void phy_procedures_eNB_TX(unsigned char sched_subframe,PHY_VARS_eNB *phy_vars_e CBA_RNTI, 0); // do_srs - if ((DCI_pdu->dci_alloc[i].nCCE=get_nCCE_offset(1<dci_alloc[i].L, - DCI_pdu->nCCE, - 0, - DCI_pdu->dci_alloc[i].rnti, - subframe)) == -1) { - LOG_E(PHY,"[eNB %"PRIu8"] Frame %d subframe %d : No available CCE resources (%u) for UE spec DCI (PUSCH %"PRIx16") !!!\n", - phy_vars_eNB->Mod_id,phy_vars_eNB->proc[sched_subframe].frame_tx,subframe,DCI_pdu->nCCE,DCI_pdu->dci_alloc[i].rnti); - } else { - LOG_T(PHY,"[eNB %"PRIu8"] Frame %d subframe %d : CCE resources for UE spec DCI (PUSCH %"PRIx16") => %d/%u\n", - phy_vars_eNB->Mod_id,phy_vars_eNB->proc[sched_subframe].frame_tx,subframe,DCI_pdu->dci_alloc[i].rnti, - DCI_pdu->dci_alloc[i].nCCE,DCI_pdu->nCCE); - + LOG_T(PHY,"[eNB %"PRIu8"] Frame %d subframe %d : CCE resources for UE spec DCI (PUSCH %"PRIx16") => %d/%u\n", + phy_vars_eNB->Mod_id,phy_vars_eNB->proc[sched_subframe].frame_tx,subframe,DCI_pdu->dci_alloc[i].rnti, + DCI_pdu->dci_alloc[i].firstCCE,DCI_pdu->nCCE); + #if defined(SMBV) && !defined(EXMIMO) // configure UE-spec DCI for UL Grant - if (smbv_is_config_frame(phy_vars_eNB->proc[sched_subframe].frame_tx) && (smbv_frame_cnt < 4)) { - msg("[SMBV] Frame %3d, SF %d UL DCI %"PRIu32"\n",phy_vars_eNB->proc[sched_subframe].frame_tx,subframe,i); - smbv_configure_ue_spec_dci(smbv_fname,(smbv_frame_cnt*10) + (subframe), UE_id+1, &DCI_pdu->dci_alloc[i], i); - } - + if (smbv_is_config_frame(phy_vars_eNB->proc[sched_subframe].frame_tx) && (smbv_frame_cnt < 4)) { + msg("[SMBV] Frame %3d, SF %d UL DCI %"PRIu32"\n",phy_vars_eNB->proc[sched_subframe].frame_tx,subframe,i); + smbv_configure_ue_spec_dci(smbv_fname,(smbv_frame_cnt*10) + (subframe), UE_id+1, &DCI_pdu->dci_alloc[i], i); + } + #endif - } + #ifdef DEBUG_PHY_PROC LOG_D(PHY,"[eNB %"PRIu8"][PUSCH %"PRIu8"] frame %d subframe %d Setting subframe_scheduling_flag for UE %"PRIu32" harq_pid %"PRIu8" (ul subframe %"PRIu8")\n", @@ -2120,13 +1999,13 @@ void phy_procedures_eNB_TX(unsigned char sched_subframe,PHY_VARS_eNB *phy_vars_e } if (abstraction_flag == 0) { -#ifdef DEBUG_PHY_PROC + //#ifdef DEBUG_PHY_PROC if (DCI_pdu->Num_ue_spec_dci+DCI_pdu->Num_common_dci > 0) LOG_D(PHY,"[eNB %"PRIu8"] Frame %d, subframe %d: Calling generate_dci_top (pdcch) (common %"PRIu8",ue_spec %"PRIu8")\n",phy_vars_eNB->Mod_id,phy_vars_eNB->proc[sched_subframe].frame_tx, subframe, DCI_pdu->Num_common_dci,DCI_pdu->Num_ue_spec_dci); -#endif + //#endif // for (sect_id=0;sect_idNum_ue_spec_dci, diff --git a/openair1/SIMULATION/LTE_PHY/dlsim.c b/openair1/SIMULATION/LTE_PHY/dlsim.c index 28e7bc8216..8f5c3aeb31 100644 --- a/openair1/SIMULATION/LTE_PHY/dlsim.c +++ b/openair1/SIMULATION/LTE_PHY/dlsim.c @@ -347,6 +347,8 @@ int main(int argc, char **argv) LTE_DL_UE_HARQ_t *dlsch0_ue_harq; LTE_DL_eNB_HARQ_t *dlsch0_eNB_harq; uint8_t Kmimo; + uint8_t ue_category=4; + uint32_t Nsoft; FILE *proc_fd = NULL; char buf[64]; @@ -378,7 +380,7 @@ int main(int argc, char **argv) num_layers = 1; perfect_ce = 0; - while ((c = getopt (argc, argv, "ahdpZDe:m:n:o:s:f:t:c:g:r:F:x:y:z:AM:N:I:i:O:R:S:C:T:b:u:v:w:B:PLl:Y")) != -1) { + while ((c = getopt (argc, argv, "ahdpZDe:m:n:o:s:f:t:c:g:r:F:x:y:z:AM:N:I:i:O:R:S:C:T:b:u:U:v:w:B:PLl:Y")) != -1) { switch (c) { case 'a': awgn_flag = 1; @@ -522,7 +524,6 @@ int main(int argc, char **argv) case 'N': channel_model=AWGN; break; - default: msg("Unsupported channel model!\n"); exit(-1); @@ -530,6 +531,10 @@ int main(int argc, char **argv) break; + case 'U': + ue_category = atoi(optarg); + break; + case 'x': transmission_mode=atoi(optarg); @@ -981,10 +986,27 @@ int main(int argc, char **argv) else Kmimo=1; + switch (ue_category) { + case 1: + Nsoft = 250368; + break; + case 2: + case 3: + Nsoft = 1237248; + break; + case 4: + Nsoft = 1827072; + break; + default: + printf("Unsupported UE category %d\n",ue_category); + exit(-1); + break; + } + for (k=0; kdlsch_eNB[k][i] = new_eNB_dlsch(Kmimo,8,N_RB_DL,0); + PHY_vars_eNB->dlsch_eNB[k][i] = new_eNB_dlsch(Kmimo,8,Nsoft,N_RB_DL,0); if (!PHY_vars_eNB->dlsch_eNB[k][i]) { printf("Can't get eNB dlsch structures\n"); @@ -996,7 +1018,7 @@ int main(int argc, char **argv) } for (i=0; i<2; i++) { - PHY_vars_UE->dlsch_ue[0][i] = new_ue_dlsch(Kmimo,8,MAX_TURBO_ITERATIONS,N_RB_DL,0); + PHY_vars_UE->dlsch_ue[0][i] = new_ue_dlsch(Kmimo,8,Nsoft,MAX_TURBO_ITERATIONS,N_RB_DL,0); if (!PHY_vars_UE->dlsch_ue[0][i]) { printf("Can't get ue dlsch structures\n"); @@ -1007,7 +1029,7 @@ int main(int argc, char **argv) } // structure for SIC at UE - PHY_vars_UE->dlsch_eNB[0] = new_eNB_dlsch(Kmimo,8,N_RB_DL,0); + PHY_vars_UE->dlsch_eNB[0] = new_eNB_dlsch(Kmimo,8,Nsoft,N_RB_DL,0); if (DLSCH_alloc_pdu2_1E[0].tpmi == 5) { diff --git a/openair2/LAYER2/MAC/defs.h b/openair2/LAYER2/MAC/defs.h index a0a43b6d79..d92a143348 100644 --- a/openair2/LAYER2/MAC/defs.h +++ b/openair2/LAYER2/MAC/defs.h @@ -251,7 +251,8 @@ typedef struct { typedef struct { uint8_t Num_ue_spec_dci ; uint8_t Num_common_dci ; - unsigned int nCCE; + uint32_t nCCE; + uint32_t num_pdcch_symbols; DCI_ALLOC_t dci_alloc[NUM_DCI_MAX] ; } DCI_PDU; /*! \brief CCCH payload */ @@ -765,8 +766,6 @@ typedef struct { uint8_t Msg3_subframe; /// Flag to indicate the eNB should generate Msg4 upon reception of SDU from RRC. This is triggered by first ULSCH reception at eNB for new user. uint8_t generate_Msg4; - /// Flag to indicate the eNB should generate the DCI for Msg4, after getting the SDU from RRC. - uint8_t generate_Msg4_dci; /// Flag to indicate that eNB is waiting for ACK that UE has received Msg3. uint8_t wait_ack_Msg4; /// UE RNTI allocated during RAR @@ -835,8 +834,8 @@ typedef struct { /// Outgoing CCCH pdu for PHY CCCH_PDU CCCH_pdu; RA_TEMPLATE RA_template[NB_RA_PROC_MAX]; - /// BCCH active flag - uint8_t bcch_active; + /// VRB map for common channels + uint8_t vrb_map[100]; /// MBSFN SubframeConfig struct MBSFN_SubframeConfig *mbsfn_SubframeConfig[8]; /// number of subframe allocation pattern available for MBSFN sync area @@ -883,9 +882,11 @@ typedef struct { /// Common cell resources COMMON_channels_t common_channels[MAX_NUM_CCs]; UE_list_t UE_list; + ///subband bitmap configuration SBMAP_CONF sbmap_conf; - + /// CCE table used to build DCI scheduling information + int CCE_table[MAX_NUM_CCs][800]; /// active flag for Other lcid // uint8_t lcid_active[NB_RB_MAX]; /// eNB stats diff --git a/openair2/LAYER2/MAC/eNB_scheduler.c b/openair2/LAYER2/MAC/eNB_scheduler.c index 329c40be05..01e32ec307 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler.c +++ b/openair2/LAYER2/MAC/eNB_scheduler.c @@ -77,11 +77,13 @@ + + + void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag, frame_t frameP, sub_frame_t subframeP) //, int calibration_flag) { { unsigned int nprb[MAX_NUM_CCs]; - unsigned int nCCE[MAX_NUM_CCs]; int mbsfn_status[MAX_NUM_CCs]; uint32_t RBalloc[MAX_NUM_CCs]; protocol_ctxt_t ctxt; @@ -106,10 +108,13 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag, for (CC_id=0; CC_idnCCE=0; + DCI_pdu[CC_id]->num_pdcch_symbols=1; nprb[CC_id]=0; RBalloc[CC_id]=0; mbsfn_status[CC_id]=0; + // clear vrb_map + memset(eNB_mac_inst[module_idP].common_channels[CC_id].vrb_map,0,100); } // refresh UE list based on UEs dropped by PHY in previous subframe @@ -186,7 +191,7 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag, for (CC_id=0; CC_idNum_common_dci = 0; DCI_pdu[CC_id]->Num_ue_spec_dci = 0; - eNB_mac_inst[module_idP].common_channels[CC_id].bcch_active = 0; + #ifdef Rel10 eNB_mac_inst[module_idP].common_channels[CC_id].mcch_active =0; @@ -194,6 +199,8 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag, eNB_mac_inst[module_idP].frame = frameP; eNB_mac_inst[module_idP].subframe = subframeP; + + } //if (subframeP%5 == 0) @@ -238,19 +245,19 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag, // Schedule ULSCH for FDD or subframeP 4 (TDD config 0,3,6) // Schedule Normal DLSCH - schedule_RA(module_idP,frameP,subframeP,2,nprb,nCCE); + schedule_RA(module_idP,frameP,subframeP,2,nprb); if (mac_xface->lte_frame_parms->frame_type == FDD) { //FDD - schedule_ulsch(module_idP,frameP,cooperation_flag,0,4,nCCE);//,calibration_flag); + schedule_ulsch(module_idP,frameP,cooperation_flag,0,4);//,calibration_flag); } else if ((mac_xface->lte_frame_parms->tdd_config == TDD) || //TDD (mac_xface->lte_frame_parms->tdd_config == 3) || (mac_xface->lte_frame_parms->tdd_config == 6)) { - //schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,4,nCCE);//,calibration_flag); + //schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,4);//,calibration_flag); } - // schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status); + // schedule_ue_spec(module_idP,frameP,subframeP,nprb,mbsfn_status); - fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,1,mbsfn_status); + fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,mbsfn_status); break; @@ -262,22 +269,22 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag, switch (mac_xface->lte_frame_parms->tdd_config) { case 0: case 1: - schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,7,nCCE); - fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status); + schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,7); + fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,mbsfn_status); break; case 6: - schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,8,nCCE); - fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status); + schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,8); + fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,mbsfn_status); break; default: break; } } else { //FDD - schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status); - fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status); - schedule_ulsch(module_idP,frameP,cooperation_flag,1,5,nCCE); + schedule_ue_spec(module_idP,frameP,subframeP,nprb,mbsfn_status); + fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,mbsfn_status); + schedule_ulsch(module_idP,frameP,cooperation_flag,1,5); } break; @@ -287,9 +294,9 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag, // TDD, nothing // FDD, normal UL/DLSCH if (mac_xface->lte_frame_parms->frame_type == FDD) { //FDD - schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status); - fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status); - schedule_ulsch(module_idP,frameP,cooperation_flag,2,6,nCCE); + schedule_ue_spec(module_idP,frameP,subframeP,nprb,mbsfn_status); + fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,mbsfn_status); + schedule_ulsch(module_idP,frameP,cooperation_flag,2,6); } break; @@ -302,21 +309,21 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag, if (mac_xface->lte_frame_parms->frame_type == TDD) { switch (mac_xface->lte_frame_parms->tdd_config) { case 2: - schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,7,nCCE); + schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,7); // no break here! case 5: - schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status); - fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status); + schedule_ue_spec(module_idP,frameP,subframeP,nprb,mbsfn_status); + fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,mbsfn_status); break; default: break; } } else { //FDD - schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status); - fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status); - schedule_ulsch(module_idP,frameP,cooperation_flag,3,7,nCCE); + schedule_ue_spec(module_idP,frameP,subframeP,nprb,mbsfn_status); + fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,mbsfn_status); + schedule_ulsch(module_idP,frameP,cooperation_flag,3,7); } @@ -330,8 +337,8 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag, if (mac_xface->lte_frame_parms->frame_type == 1) { // TDD switch (mac_xface->lte_frame_parms->tdd_config) { case 1: - // schedule_RA(module_idP,frameP,subframeP,nprb,nCCE); - schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,8,nCCE); + // schedule_RA(module_idP,frameP,subframeP,nprb); + schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,8); // no break here! case 2: @@ -341,8 +348,8 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag, // no break here! case 5: - schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status); - fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,1,mbsfn_status); + schedule_ue_spec(module_idP,frameP,subframeP,nprb,mbsfn_status); + fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,mbsfn_status); break; default: @@ -350,10 +357,10 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag, } } else { if (mac_xface->lte_frame_parms->frame_type == FDD) { //FDD - // schedule_RA(module_idP,frameP, subframeP, 0, nprb, nCCE); - // schedule_ulsch(module_idP, frameP, cooperation_flag, 4, 8, nCCE); - schedule_ue_spec(module_idP, frameP, subframeP, nprb, nCCE, mbsfn_status); - fill_DLSCH_dci(module_idP, frameP, subframeP, RBalloc, 1, mbsfn_status); + // schedule_RA(module_idP,frameP, subframeP, 0, nprb); + // schedule_ulsch(module_idP, frameP, cooperation_flag, 4, 8); + schedule_ue_spec(module_idP, frameP, subframeP, nprb, mbsfn_status); + fill_DLSCH_dci(module_idP, frameP, subframeP, RBalloc, mbsfn_status); } } @@ -365,21 +372,21 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag, // TDD Config 0,6 ULSCH for subframes 9,3 resp. // TDD normal DLSCH // FDD normal UL/DLSCH - schedule_SI(module_idP,frameP,nprb,nCCE); + schedule_SI(module_idP,frameP,subframeP,nprb); - //schedule_RA(module_idP,frameP,subframeP,5,nprb,nCCE); + //schedule_RA(module_idP,frameP,subframeP,5,nprb); if (mac_xface->lte_frame_parms->frame_type == FDD) { - schedule_RA(module_idP,frameP,subframeP,1,nprb,nCCE); - // schedule_ulsch(module_idP,frameP,cooperation_flag,5,9,nCCE); - fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,1,mbsfn_status); + schedule_RA(module_idP,frameP,subframeP,1,nprb); + // schedule_ulsch(module_idP,frameP,cooperation_flag,5,9); + fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,mbsfn_status); } else if ((mac_xface->lte_frame_parms->tdd_config == 0) || // TDD Config 0 (mac_xface->lte_frame_parms->tdd_config == 6)) { // TDD Config 6 - //schedule_ulsch(module_idP,cooperation_flag,subframeP,nCCE); - fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status); + //schedule_ulsch(module_idP,cooperation_flag,subframeP); + fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,mbsfn_status); } else { - //schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status); - fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status); + //schedule_ue_spec(module_idP,frameP,subframeP,nprb,mbsfn_status); + fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,mbsfn_status); } break; @@ -395,36 +402,36 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag, break; case 1: - schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,2,nCCE); - // schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status); - fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status); + schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,2); + // schedule_ue_spec(module_idP,frameP,subframeP,nprb,mbsfn_status); + fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,mbsfn_status); break; case 6: - schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,3,nCCE); - // schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status); - fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status); + schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,3); + // schedule_ue_spec(module_idP,frameP,subframeP,nprb,mbsfn_status); + fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,mbsfn_status); break; case 5: - schedule_RA(module_idP,frameP,subframeP,2,nprb,nCCE); - schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status); - fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,1,mbsfn_status); + schedule_RA(module_idP,frameP,subframeP,2,nprb); + schedule_ue_spec(module_idP,frameP,subframeP,nprb,mbsfn_status); + fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,mbsfn_status); break; case 3: case 4: - schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status); - fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status); + schedule_ue_spec(module_idP,frameP,subframeP,nprb,mbsfn_status); + fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,mbsfn_status); break; default: break; } } else { //FDD - // schedule_ulsch(module_idP,frameP,cooperation_flag,6,0,nCCE); - schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status); - fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status); + // schedule_ulsch(module_idP,frameP,cooperation_flag,6,0); + schedule_ue_spec(module_idP,frameP,subframeP,nprb,mbsfn_status); + fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,mbsfn_status); } break; @@ -437,23 +444,23 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag, switch (mac_xface->lte_frame_parms->tdd_config) { case 3: case 4: - schedule_RA(module_idP,frameP,subframeP,3,nprb,nCCE); // 3 = Msg3 subframeP, not - schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status); - fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,1,mbsfn_status); + schedule_RA(module_idP,frameP,subframeP,3,nprb); // 3 = Msg3 subframeP, not + schedule_ue_spec(module_idP,frameP,subframeP,nprb,mbsfn_status); + fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,mbsfn_status); break; case 5: - schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status); - fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status); + schedule_ue_spec(module_idP,frameP,subframeP,nprb,mbsfn_status); + fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,mbsfn_status); break; default: break; } } else { //FDD - //schedule_ulsch(module_idP,frameP,cooperation_flag,7,1,nCCE); - schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status); - fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status); + //schedule_ulsch(module_idP,frameP,cooperation_flag,7,1); + schedule_ue_spec(module_idP,frameP,subframeP,nprb,mbsfn_status); + fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,mbsfn_status); } break; @@ -470,19 +477,19 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag, case 4: case 5: - // schedule_RA(module_idP,subframeP,nprb,nCCE); - schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,2,nCCE); - schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status); - fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status); + // schedule_RA(module_idP,subframeP,nprb); + schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,2); + schedule_ue_spec(module_idP,frameP,subframeP,nprb,mbsfn_status); + fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,mbsfn_status); break; default: break; } } else { //FDD - //schedule_ulsch(module_idP,frameP,cooperation_flag,8,2,nCCE); - schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status); - fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status); + //schedule_ulsch(module_idP,frameP,cooperation_flag,8,2); + schedule_ue_spec(module_idP,frameP,subframeP,nprb,mbsfn_status); + fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,mbsfn_status); } break; @@ -493,51 +500,50 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag, if (mac_xface->lte_frame_parms->frame_type == TDD) { switch (mac_xface->lte_frame_parms->tdd_config) { case 1: - schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,3,nCCE); - schedule_RA(module_idP,frameP,subframeP,7,nprb,nCCE); // 7 = Msg3 subframeP, not - schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status); - fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,1,mbsfn_status); + schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,3); + schedule_RA(module_idP,frameP,subframeP,7,nprb); // 7 = Msg3 subframeP, not + schedule_ue_spec(module_idP,frameP,subframeP,nprb,mbsfn_status); + fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,mbsfn_status); break; case 3: case 4: - schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,3,nCCE); - schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status); - fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status); + schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,3); + schedule_ue_spec(module_idP,frameP,subframeP,nprb,mbsfn_status); + fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,mbsfn_status); break; case 6: - schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,4,nCCE); - //schedule_RA(module_idP,frameP,subframeP,nprb,nCCE); - schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status); - fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status); + schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,4); + //schedule_RA(module_idP,frameP,subframeP,nprb); + schedule_ue_spec(module_idP,frameP,subframeP,nprb,mbsfn_status); + fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,mbsfn_status); break; case 2: case 5: - //schedule_RA(module_idP,frameP,subframeP,nprb,nCCE); - schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status); - fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status); + //schedule_RA(module_idP,frameP,subframeP,nprb); + schedule_ue_spec(module_idP,frameP,subframeP,nprb,mbsfn_status); + fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,mbsfn_status); break; default: break; } } else { //FDD - // schedule_ulsch(module_idP,frameP,cooperation_flag,9,3,nCCE); - schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status); - fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status); + // schedule_ulsch(module_idP,frameP,cooperation_flag,9,3); + schedule_ue_spec(module_idP,frameP,subframeP,nprb,mbsfn_status); + fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,mbsfn_status); } break; } - for (CC_id=0; CC_idnCCE = nCCE[CC_id]; - } + for (CC_id=0;CC_idschedule_ra); for (CC_id=0; CC_idcommon_channels[CC_id].RA_template[0]; + + vrb_map = eNB->common_channels[CC_id].vrb_map; + DCI_pdu = &eNB->common_channels[CC_id].DCI_pdu; for (i=0; icommon_channels[CC_id].RA_template[i]; + + if (RA_template->RA_active == TRUE) { LOG_D(MAC,"[eNB %d][RAPROC] CC_id %d RA %d is active (generate RAR %d, generate_Msg4 %d, wait_ack_Msg4 %d, rnti %x)\n", - module_idP,CC_id,i,RA_template[i].generate_rar,RA_template[i].generate_Msg4,RA_template[i].wait_ack_Msg4, RA_template[i].rnti); + module_idP,CC_id,i,RA_template->generate_rar,RA_template->generate_Msg4,RA_template->wait_ack_Msg4, RA_template->rnti); - if (RA_template[i].generate_rar == 1) { - nprb[CC_id]= nprb[CC_id] + 3; - nCCE[CC_id] = nCCE[CC_id] + 4; - RA_template[i].Msg3_subframe=Msg3_subframe; - } else if (RA_template[i].generate_Msg4 == 1) { + if (RA_template->generate_rar == 1) { + + LOG_D(MAC,"[eNB %d] CC_id %d Frame %d, subframeP %d: Generating RAR DCI (proc %d), RA_active %d format 1A (%d,%d))\n", + module_idP, CC_id, frameP, subframeP,i, + RA_template->RA_active, + RA_template->RA_dci_fmt1, + RA_template->RA_dci_size_bits1); + + + + if (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.frame_type == TDD) { + switch(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL) { + case 6: + ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->type=1; + ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type=0; + ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->ndi=1; + ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rv=0; + ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->mcs=0; + ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0; + ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1; + ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->padding=0; + ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); + rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type, + ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc); + break; + + case 25: + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->type=1; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type=0; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->ndi=1; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rv=0; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->mcs=0; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->padding=0; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); + rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type, + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc); + break; + + case 50: + ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->type=1; + ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type=0; + ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->ndi=1; + ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rv=0; + ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->mcs=0; + ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0; + ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1; + ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->padding=0; + ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); + rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type, + ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc); + break; + + case 100: + ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->type=1; + ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type=0; + ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->ndi=1; + ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rv=0; + ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->mcs=0; + ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0; + ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1; + ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->padding=0; + ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); + rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type, + ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc); + break; + + default: + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->type=1; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type=0; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->ndi=1; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rv=0; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->mcs=0; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->padding=0; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); + rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type, + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc); + break; + } + } else { + switch(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL) { + case 6: + ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->type=1; + ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type=0; + ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->ndi=1; + ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rv=0; + ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->mcs=0; + ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0; + ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1; + ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->padding=0; + ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); + rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type, + ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc); + break; + + case 25: + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->type=1; + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type=0; + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->ndi=1; + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rv=0; + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->mcs=0; + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0; + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1; + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->padding=0; + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_UL,first_rb,4); + rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type, + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc); + break; + + case 50: + ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->type=1; + ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type=0; + ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->ndi=1; + ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rv=0; + ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->mcs=0; + ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0; + ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1; + ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->padding=0; + ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); + rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type, + ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc); + break; + + case 100: + ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->type=1; + ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type=0; + ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->ndi=1; + ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rv=0; + ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->mcs=0; + ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0; + ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1; + ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->padding=0; + ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); + rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type, + ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc); + break; + + default: + break; + } + } + + if (!CCE_allocation_infeasible(module_idP,CC_id,1,subframeP,2,RA_template->RA_rnti)) { + add_common_dci(DCI_pdu, + (void*)&RA_template->RA_alloc_pdu1[0], + RA_template->RA_rnti, + RA_template->RA_dci_size_bytes1, + 2, + RA_template->RA_dci_size_bits1, + RA_template->RA_dci_fmt1, + 1); + + nprb[CC_id]= nprb[CC_id] + 3; + RA_template->Msg3_subframe=Msg3_subframe; + } + } else if (RA_template->generate_Msg4 == 1) { // check for Msg4 Message - UE_id = find_UE_id(module_idP,RA_template[i].rnti); + UE_id = find_UE_id(module_idP,RA_template->rnti); if (Is_rrc_registered == 1) { @@ -131,7 +293,7 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un if (rrc_sdu_length>0) { LOG_I(MAC,"[eNB %d][RAPROC] CC_id %d Frame %d, subframeP %d: Generating Msg4 with RRC Piggyback (RA proc %d, RNTI %x)\n", - module_idP, CC_id, frameP, subframeP,i,RA_template[i].rnti); + module_idP, CC_id, frameP, subframeP,i,RA_template->rnti); //msg("[MAC][eNB %d][RAPROC] Frame %d, subframeP %d: Received %d bytes for Msg4: \n",module_idP,frameP,subframeP,rrc_sdu_length); // for (j=0;jlte_frame_parms.N_RB_DL-4)); + + if ((vrb_map[first_rb] != 1) && (vrb_map[first_rb+3] != 1)) + break; + } + + vrb_map[first_rb] = 1; + vrb_map[first_rb+1] = 1; + vrb_map[first_rb+2] = 1; + vrb_map[first_rb+3] = 1; // Compute MCS for 3 PRB @@ -149,273 +323,405 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un switch (mac_xface->lte_frame_parms->N_RB_DL) { case 6: - ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->ndi=1; + ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->ndi=1; if ((rrc_sdu_length+msg4_header) <= 22) { - ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=4; + ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->mcs=4; TBsize = 22; } else if ((rrc_sdu_length+msg4_header) <= 28) { - ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=5; + ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->mcs=5; TBsize = 28; } else if ((rrc_sdu_length+msg4_header) <= 32) { - ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=6; + ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->mcs=6; TBsize = 32; } else if ((rrc_sdu_length+msg4_header) <= 41) { - ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=7; + ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->mcs=7; TBsize = 41; } else if ((rrc_sdu_length+msg4_header) <= 49) { - ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=8; + ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->mcs=8; TBsize = 49; } else if ((rrc_sdu_length+msg4_header) <= 57) { - ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=9; + ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->mcs=9; TBsize = 57; } - + ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->type=1; + ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type=0; + ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rv=0; + ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->harq_pid=0; + ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->TPC=1; + ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->padding=0; + ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); + rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type, + ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc); + break; case 25: - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->ndi=1; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->ndi=1; if ((rrc_sdu_length+msg4_header) <= 22) { - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=4; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->mcs=4; TBsize = 22; } else if ((rrc_sdu_length+msg4_header) <= 28) { - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=5; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->mcs=5; TBsize = 28; } else if ((rrc_sdu_length+msg4_header) <= 32) { - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=6; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->mcs=6; TBsize = 32; } else if ((rrc_sdu_length+msg4_header) <= 41) { - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=7; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->mcs=7; TBsize = 41; } else if ((rrc_sdu_length+msg4_header) <= 49) { - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=8; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->mcs=8; TBsize = 49; } else if ((rrc_sdu_length+msg4_header) <= 57) { - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=9; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->mcs=9; TBsize = 57; } - + + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->type=1; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type=0; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rv=0; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->harq_pid=0; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->TPC=1; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->padding=0; + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); + rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type, + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc); break; case 50: - ((DCI1A_10MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->ndi=1; + ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->ndi=1; if ((rrc_sdu_length+msg4_header) <= 22) { - ((DCI1A_10MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=4; + ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->mcs=4; TBsize = 22; } else if ((rrc_sdu_length+msg4_header) <= 28) { - ((DCI1A_10MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=5; + ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->mcs=5; TBsize = 28; } else if ((rrc_sdu_length+msg4_header) <= 32) { - ((DCI1A_10MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=6; + ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->mcs=6; TBsize = 32; } else if ((rrc_sdu_length+msg4_header) <= 41) { - ((DCI1A_10MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=7; + ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->mcs=7; TBsize = 41; } else if ((rrc_sdu_length+msg4_header) <= 49) { - ((DCI1A_10MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=8; + ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->mcs=8; TBsize = 49; } else if ((rrc_sdu_length+msg4_header) <= 57) { - ((DCI1A_10MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=9; + ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->mcs=9; TBsize = 57; } + ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->type=1; + ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type=0; + ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rv=0; + ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->harq_pid=0; + ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->TPC=1; + ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->padding=0; + ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); + rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type, + ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc); break; case 100: - ((DCI1A_20MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->ndi=1; + ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->ndi=1; if ((rrc_sdu_length+msg4_header) <= 22) { - ((DCI1A_20MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=4; + ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->mcs=4; TBsize = 22; } else if ((rrc_sdu_length+msg4_header) <= 28) { - ((DCI1A_20MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=5; + ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->mcs=5; TBsize = 28; } else if ((rrc_sdu_length+msg4_header) <= 32) { - ((DCI1A_20MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=6; + ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->mcs=6; TBsize = 32; } else if ((rrc_sdu_length+msg4_header) <= 41) { - ((DCI1A_20MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=7; + ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->mcs=7; TBsize = 41; } else if ((rrc_sdu_length+msg4_header) <= 49) { - ((DCI1A_20MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=8; + ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->mcs=8; TBsize = 49; } else if ((rrc_sdu_length+msg4_header) <= 57) { - ((DCI1A_20MHz_TDD_1_6_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=9; + ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->mcs=9; TBsize = 57; } + ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->type=1; + ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type=0; + ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rv=0; + ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->harq_pid=0; + ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->TPC=1; + ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); + rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type, + ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc); break; } } else { // FDD DCI switch (mac_xface->lte_frame_parms->N_RB_DL) { case 6: - ((DCI1A_1_5MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->ndi=1; + ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->ndi=1; if ((rrc_sdu_length+msg4_header) <= 22) { - ((DCI1A_1_5MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=4; + ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->mcs=4; TBsize = 22; } else if ((rrc_sdu_length+msg4_header) <= 28) { - ((DCI1A_1_5MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=5; + ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->mcs=5; TBsize = 28; } else if ((rrc_sdu_length+msg4_header) <= 32) { - ((DCI1A_1_5MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=6; + ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->mcs=6; TBsize = 32; } else if ((rrc_sdu_length+msg4_header) <= 41) { - ((DCI1A_1_5MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=7; + ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->mcs=7; TBsize = 41; } else if ((rrc_sdu_length+msg4_header) <= 49) { - ((DCI1A_1_5MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=8; + ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->mcs=8; TBsize = 49; } else if ((rrc_sdu_length+msg4_header) <= 57) { - ((DCI1A_1_5MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=9; + ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->mcs=9; TBsize = 57; } + ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->type=1; + ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type=0; + ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rv=0; + ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->harq_pid=0; + ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->TPC=1; + ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->padding=0; + ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); + rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type, + ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc); break; case 25: - ((DCI1A_5MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->ndi=1; + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->ndi=1; if ((rrc_sdu_length+msg4_header) <= 22) { - ((DCI1A_5MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=4; + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->mcs=4; TBsize = 22; } else if ((rrc_sdu_length+msg4_header) <= 28) { - ((DCI1A_5MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=5; + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->mcs=5; TBsize = 28; } else if ((rrc_sdu_length+msg4_header) <= 32) { - ((DCI1A_5MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=6; + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->mcs=6; TBsize = 32; } else if ((rrc_sdu_length+msg4_header) <= 41) { - ((DCI1A_5MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=7; + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->mcs=7; TBsize = 41; } else if ((rrc_sdu_length+msg4_header) <= 49) { - ((DCI1A_5MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=8; + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->mcs=8; TBsize = 49; } else if ((rrc_sdu_length+msg4_header) <= 57) { - ((DCI1A_5MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=9; + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->mcs=9; TBsize = 57; } + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->type=1; + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type=0; + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rv=0; + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->harq_pid=0; + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->TPC=1; + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->padding=0; + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); + rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type, + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc); break; case 50: - ((DCI1A_10MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->ndi=1; + ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->ndi=1; if ((rrc_sdu_length+msg4_header) <= 22) { - ((DCI1A_10MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=4; + ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->mcs=4; TBsize = 22; } else if ((rrc_sdu_length+msg4_header) <= 28) { - ((DCI1A_10MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=5; + ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->mcs=5; TBsize = 28; } else if ((rrc_sdu_length+msg4_header) <= 32) { - ((DCI1A_10MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=6; + ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->mcs=6; TBsize = 32; } else if ((rrc_sdu_length+msg4_header) <= 41) { - ((DCI1A_10MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=7; + ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->mcs=7; TBsize = 41; } else if ((rrc_sdu_length+msg4_header) <= 49) { - ((DCI1A_10MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=8; + ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->mcs=8; TBsize = 49; } else if ((rrc_sdu_length+msg4_header) <= 57) { - ((DCI1A_10MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=9; + ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->mcs=9; TBsize = 57; } + ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->type=1; + ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type=0; + ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rv=0; + ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->harq_pid=0; + ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->TPC=1; + ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->padding=0; + ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); + rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type, + ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc); break; case 100: - ((DCI1A_20MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->ndi=1; + ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->ndi=1; if ((rrc_sdu_length+msg4_header) <= 22) { - ((DCI1A_20MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=4; + ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->mcs=4; TBsize = 22; } else if ((rrc_sdu_length+msg4_header) <= 28) { - ((DCI1A_20MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=5; + ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->mcs=5; TBsize = 28; } else if ((rrc_sdu_length+msg4_header) <= 32) { - ((DCI1A_20MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=6; + ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->mcs=6; TBsize = 32; } else if ((rrc_sdu_length+msg4_header) <= 41) { - ((DCI1A_20MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=7; + ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->mcs=7; TBsize = 41; } else if ((rrc_sdu_length+msg4_header) <= 49) { - ((DCI1A_20MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=8; + ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->mcs=8; TBsize = 49; } else if ((rrc_sdu_length+msg4_header) <= 57) { - ((DCI1A_20MHz_FDD_t*)&RA_template[i].RA_alloc_pdu2[0])->mcs=9; + ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->mcs=9; TBsize = 57; } - + ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->type=1; + ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type=0; + ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rv=0; + ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->harq_pid=0; + ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->TPC=1; + ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->padding=0; + ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); + rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type, + ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc); break; } } - RA_template[i].generate_Msg4=0; - RA_template[i].generate_Msg4_dci=1; - RA_template[i].wait_ack_Msg4=1; - RA_template[i].RA_active = FALSE; - lcid=0; - - if ((TBsize - rrc_sdu_length - msg4_header) <= 2) { - msg4_padding = TBsize - rrc_sdu_length - msg4_header; - msg4_post_padding = 0; - } else { - msg4_padding = 0; - msg4_post_padding = TBsize - rrc_sdu_length - msg4_header -1; - } - - LOG_I(MAC,"[eNB %d][RAPROC] CC_id %d Frame %d subframeP %d Msg4 : TBS %d, sdu_len %d, msg4_header %d, msg4_padding %d, msg4_post_padding %d\n", - module_idP,CC_id,frameP,subframeP,TBsize,rrc_sdu_length,msg4_header,msg4_padding,msg4_post_padding); - DevAssert( UE_id != UE_INDEX_INVALID ); // FIXME not sure how to gracefully return - offset = generate_dlsch_header((unsigned char*)eNB->UE_list.DLSCH_pdu[CC_id][0][(unsigned char)UE_id].payload[0], - 1, //num_sdus - (unsigned short*)&rrc_sdu_length, // - &lcid, // sdu_lcid - 255, // no drx - 0, // no timing advance - RA_template[i].cont_res_id, // contention res id - msg4_padding, // no padding - msg4_post_padding); - - memcpy((void*)&eNB->UE_list.DLSCH_pdu[CC_id][0][(unsigned char)UE_id].payload[0][(unsigned char)offset], - &eNB->common_channels[CC_id].CCCH_pdu.payload[0], - rrc_sdu_length); - - if (opt_enabled==1) { - trace_pdu(1, (uint8_t *)eNB->UE_list.DLSCH_pdu[CC_id][0][(unsigned char)UE_id].payload[0], - rrc_sdu_length, UE_id, 3, UE_RNTI(module_idP, UE_id), - eNB->subframe,0,0); - LOG_D(OPT,"[eNB %d][DLSCH] CC_id %d Frame %d trace pdu for rnti %x with size %d\n", - module_idP, CC_id, frameP, UE_RNTI(module_idP,UE_id), rrc_sdu_length); - } - - nprb[CC_id]= nprb[CC_id] + 3; - nCCE[CC_id] = nCCE[CC_id] + 4; - } + if (!CCE_allocation_infeasible(module_idP,CC_id,0,subframeP,2,RA_template->rnti)) { + add_ue_spec_dci(DCI_pdu, + (void*)&RA_template->RA_alloc_pdu2[0], + RA_template->rnti, + RA_template->RA_dci_size_bytes2, + 1, + RA_template->RA_dci_size_bits2, + RA_template->RA_dci_fmt2, + 0); + + RA_template->generate_Msg4=0; + RA_template->wait_ack_Msg4=1; + RA_template->RA_active = FALSE; + lcid=0; + + if ((TBsize - rrc_sdu_length - msg4_header) <= 2) { + msg4_padding = TBsize - rrc_sdu_length - msg4_header; + msg4_post_padding = 0; + } else { + msg4_padding = 0; + msg4_post_padding = TBsize - rrc_sdu_length - msg4_header -1; + } + + LOG_I(MAC,"[eNB %d][RAPROC] CC_id %d Frame %d subframeP %d Msg4 : TBS %d, sdu_len %d, msg4_header %d, msg4_padding %d, msg4_post_padding %d\n", + module_idP,CC_id,frameP,subframeP,TBsize,rrc_sdu_length,msg4_header,msg4_padding,msg4_post_padding); + DevAssert( UE_id != UE_INDEX_INVALID ); // FIXME not sure how to gracefully return + offset = generate_dlsch_header((unsigned char*)eNB->UE_list.DLSCH_pdu[CC_id][0][(unsigned char)UE_id].payload[0], + 1, //num_sdus + (unsigned short*)&rrc_sdu_length, // + &lcid, // sdu_lcid + 255, // no drx + 0, // no timing advance + RA_template->cont_res_id, // contention res id + msg4_padding, // no padding + msg4_post_padding); + + memcpy((void*)&eNB->UE_list.DLSCH_pdu[CC_id][0][(unsigned char)UE_id].payload[0][(unsigned char)offset], + &eNB->common_channels[CC_id].CCCH_pdu.payload[0], + rrc_sdu_length); + + if (opt_enabled==1) { + trace_pdu(1, (uint8_t *)eNB->UE_list.DLSCH_pdu[CC_id][0][(unsigned char)UE_id].payload[0], + rrc_sdu_length, UE_id, 3, UE_RNTI(module_idP, UE_id), + eNB->subframe,0,0); + LOG_D(OPT,"[eNB %d][DLSCH] CC_id %d Frame %d trace pdu for rnti %x with size %d\n", + module_idP, CC_id, frameP, UE_RNTI(module_idP,UE_id), rrc_sdu_length); + } + + nprb[CC_id]= nprb[CC_id] + 3; + } + } //try here } - /* - else if (eNB_mac_inst[module_idP][CC_id].RA_template[i].wait_ack_Msg4==1) { - // check HARQ status and retransmit if necessary - LOG_I(MAC,"[eNB %d][RAPROC] Frame %d, subframeP %d: Checking if Msg4 was acknowledged :\n",module_idP,frameP,subframeP); - // Get candidate harq_pid from PHY - mac_xface->get_ue_active_harq_pid(module_idP,eNB_mac_inst[module_idP][CC_id].RA_template[i].rnti,subframeP,&harq_pid,&round,0); - if (round>0) { - *nprb= (*nprb) + 3; - *nCCE = (*nCCE) + 4; - } - } - */ + } else if (RA_template->wait_ack_Msg4==1) { + // check HARQ status and retransmit if necessary + LOG_I(MAC,"[eNB %d][RAPROC] CC_id %d Frame %d, subframeP %d: Checking if Msg4 was acknowledged: \n", + module_idP,CC_id,frameP,subframeP); + // Get candidate harq_pid from PHY + mac_xface->get_ue_active_harq_pid(module_idP,CC_id,RA_template->rnti,frameP,subframeP,&harq_pid,&round,0); + + if (round>0) { + //RA_template->wait_ack_Msg4++; + // we have to schedule a retransmission + if (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.frame_type == TDD) { + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->ndi=1; + } else { + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->ndi=1; + } + + // randomize frequency allocation for RA + while (1) { + first_rb = (unsigned char)(taus()%(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL-4)); + + if ((vrb_map[first_rb] != 1) && (vrb_map[first_rb+3] != 1)) + break; + } + + vrb_map[first_rb] = 1; + vrb_map[first_rb+1] = 1; + vrb_map[first_rb+2] = 1; + vrb_map[first_rb+3] = 1; + + if (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.frame_type == TDD) { + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_UL,first_rb,4); + rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type, + ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc); + } else { + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_UL,first_rb,4); + rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type, + ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc); + } + + if (!CCE_allocation_infeasible(module_idP,CC_id,0,subframeP,2,RA_template->rnti)) { + add_ue_spec_dci(DCI_pdu, + (void*)&RA_template->RA_alloc_pdu2[0], + RA_template->rnti, + RA_template->RA_dci_size_bytes2, + 2, + RA_template->RA_dci_size_bits2, + RA_template->RA_dci_fmt2, + 0); + } + LOG_W(MAC,"[eNB %d][RAPROC] CC_id %d Frame %d, subframeP %d: Msg4 not acknowledged, adding ue specific dci (rnti %x) for RA (Msg4 Retransmission)\n", + module_idP,CC_id,frameP,subframeP,RA_template->rnti); + } else { + /* msg4 not received + if ((round == 0) && (RA_template->wait_ack_Msg4>1){ + remove UE instance across all the layers: mac_xface->cancel_RA(); + } + */ + LOG_I(MAC,"[eNB %d][RAPROC] CC_id %d Frame %d, subframeP %d : Msg4 acknowledged\n",module_idP,CC_id,frameP,subframeP); + RA_template->wait_ack_Msg4=0; + RA_template->RA_active=FALSE; + UE_id = find_UE_id(module_idP,RA_template->rnti); + DevAssert( UE_id != -1 ); + eNB_mac_inst[module_idP].UE_list.UE_template[UE_PCCID(module_idP,UE_id)][UE_id].configured=TRUE; + + } } - } - } + } // for i=0 .. N_RA_PROC-1 + } // CC_id stop_meas(&eNB->schedule_ra); } diff --git a/openair2/LAYER2/MAC/eNB_scheduler_bch.c b/openair2/LAYER2/MAC/eNB_scheduler_bch.c index dd0890783e..a109e6fb5f 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_bch.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_bch.c @@ -72,9 +72,9 @@ void schedule_SI( module_id_t module_idP, frame_t frameP, - unsigned int* nprbP, - unsigned int* nCCEP -) + sub_frame_t subframeP, + unsigned int* nprbP) + //------------------------------------------------------------------------------ { @@ -85,12 +85,19 @@ schedule_SI( void *BCCH_alloc_pdu; int CC_id; eNB_MAC_INST *eNB = &eNB_mac_inst[module_idP]; + uint8_t *vrb_map; + int first_rb; + int rballoc[MAX_NUM_CCs]; + int sizeof1A_bytes,sizeof1A_bits; + DCI_PDU *DCI_pdu; start_meas(&eNB->schedule_si); for (CC_id=0; CC_idcommon_channels[CC_id].BCCH_alloc_pdu; + + BCCH_alloc_pdu = (void*)&eNB->common_channels[CC_id].BCCH_alloc_pdu; + DCI_pdu = (void*)&eNB->common_channels[CC_id].DCI_pdu; + vrb_map = (void*)&eNB->common_channels[CC_id].vrb_map; bcch_sdu_length = mac_rrc_data_req(module_idP, CC_id, @@ -104,7 +111,21 @@ schedule_SI( if (bcch_sdu_length > 0) { LOG_D(MAC,"[eNB %d] Frame %d : BCCH->DLSCH CC_id %d, Received %d bytes \n",module_idP,frameP,CC_id,bcch_sdu_length); + // Allocate 4 PRBs in a random location + while (1) { + first_rb = (unsigned char)(taus()%(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL-4)); + if ((vrb_map[first_rb] != 1) && + (vrb_map[first_rb+1] != 1) && + (vrb_map[first_rb+2] != 1) && + (vrb_map[first_rb+3] != 1)) + break; + } + vrb_map[first_rb] = 1; + vrb_map[first_rb+1] = 1; + vrb_map[first_rb+2] = 1; + vrb_map[first_rb+3] = 1; + // Get MCS for length of SI if (bcch_sdu_length <= (mac_xface->get_TBS_DL(0,3))) { mcs=0; } else if (bcch_sdu_length <= (mac_xface->get_TBS_DL(1,3))) { @@ -125,46 +146,153 @@ schedule_SI( mcs=8; } + + if (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.frame_type == TDD) { switch (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL) { case 6: ((DCI1A_1_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->mcs = mcs; + ((DCI1A_1_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); + ((DCI1A_1_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->type = 1; + ((DCI1A_1_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->vrb_type = 0; + ((DCI1A_1_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->ndi = 1; + ((DCI1A_1_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rv = 1; + ((DCI1A_1_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->harq_pid = 0; + ((DCI1A_1_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->TPC = 1; + ((DCI1A_1_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->padding = 0; + rballoc[CC_id] |= mac_xface->get_rballoc(0,((DCI1A_1_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rballoc); + sizeof1A_bytes = sizeof(DCI1A_1_5MHz_TDD_1_6_t); + sizeof1A_bits = sizeof_DCI1A_1_5MHz_TDD_1_6_t; break; case 25: ((DCI1A_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->mcs = mcs; - break; + ((DCI1A_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); + ((DCI1A_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->type = 1; + ((DCI1A_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->vrb_type = 0; + ((DCI1A_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->ndi = 1; + ((DCI1A_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rv = 1; + ((DCI1A_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->harq_pid = 0; + ((DCI1A_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->TPC = 1; + ((DCI1A_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->padding = 0; + rballoc[CC_id] |= mac_xface->get_rballoc(0,((DCI1A_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rballoc); + sizeof1A_bytes = sizeof(DCI1A_5MHz_TDD_1_6_t); + sizeof1A_bits = sizeof_DCI1A_5MHz_TDD_1_6_t; + break; case 50: ((DCI1A_10MHz_TDD_1_6_t*)BCCH_alloc_pdu)->mcs = mcs; + ((DCI1A_10MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); + ((DCI1A_10MHz_TDD_1_6_t*)BCCH_alloc_pdu)->type = 1; + ((DCI1A_10MHz_TDD_1_6_t*)BCCH_alloc_pdu)->vrb_type = 0; + ((DCI1A_10MHz_TDD_1_6_t*)BCCH_alloc_pdu)->ndi = 1; + ((DCI1A_10MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rv = 1; + ((DCI1A_10MHz_TDD_1_6_t*)BCCH_alloc_pdu)->harq_pid = 0; + ((DCI1A_10MHz_TDD_1_6_t*)BCCH_alloc_pdu)->TPC = 1; + ((DCI1A_10MHz_TDD_1_6_t*)BCCH_alloc_pdu)->padding = 0; + rballoc[CC_id] |= mac_xface->get_rballoc(0,((DCI1A_10MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rballoc); + sizeof1A_bytes = sizeof(DCI1A_10MHz_TDD_1_6_t); + sizeof1A_bits = sizeof_DCI1A_10MHz_TDD_1_6_t; break; case 100: ((DCI1A_20MHz_TDD_1_6_t*)BCCH_alloc_pdu)->mcs = mcs; - break; + ((DCI1A_20MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); + ((DCI1A_20MHz_TDD_1_6_t*)BCCH_alloc_pdu)->type = 1; + ((DCI1A_20MHz_TDD_1_6_t*)BCCH_alloc_pdu)->vrb_type = 0; + ((DCI1A_20MHz_TDD_1_6_t*)BCCH_alloc_pdu)->ndi = 1; + ((DCI1A_20MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rv = 1; + ((DCI1A_20MHz_TDD_1_6_t*)BCCH_alloc_pdu)->harq_pid = 0; + ((DCI1A_20MHz_TDD_1_6_t*)BCCH_alloc_pdu)->TPC = 1; + ((DCI1A_20MHz_TDD_1_6_t*)BCCH_alloc_pdu)->padding = 0; + rballoc[CC_id] |= mac_xface->get_rballoc(0,((DCI1A_20MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rballoc); + sizeof1A_bytes = sizeof(DCI1A_20MHz_TDD_1_6_t); + sizeof1A_bits = sizeof_DCI1A_20MHz_TDD_1_6_t; + break; } } else { switch (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL) { case 6: ((DCI1A_1_5MHz_FDD_t*)BCCH_alloc_pdu)->mcs = mcs; + ((DCI1A_1_5MHz_FDD_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); + ((DCI1A_1_5MHz_FDD_t*)BCCH_alloc_pdu)->type = 1; + ((DCI1A_1_5MHz_FDD_t*)BCCH_alloc_pdu)->vrb_type = 0; + ((DCI1A_1_5MHz_FDD_t*)BCCH_alloc_pdu)->ndi = 1; + ((DCI1A_1_5MHz_FDD_t*)BCCH_alloc_pdu)->rv = 1; + ((DCI1A_1_5MHz_FDD_t*)BCCH_alloc_pdu)->harq_pid = 0; + ((DCI1A_1_5MHz_FDD_t*)BCCH_alloc_pdu)->TPC = 1; + ((DCI1A_1_5MHz_FDD_t*)BCCH_alloc_pdu)->padding = 0; + + rballoc[CC_id] |= mac_xface->get_rballoc(0,((DCI1A_1_5MHz_FDD_t*)BCCH_alloc_pdu)->rballoc); + sizeof1A_bytes = sizeof(DCI1A_1_5MHz_FDD_t); + sizeof1A_bits = sizeof_DCI1A_1_5MHz_FDD_t; break; case 25: ((DCI1A_5MHz_FDD_t*)BCCH_alloc_pdu)->mcs = mcs; + ((DCI1A_5MHz_FDD_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); + ((DCI1A_5MHz_FDD_t*)BCCH_alloc_pdu)->type = 1; + ((DCI1A_5MHz_FDD_t*)BCCH_alloc_pdu)->vrb_type = 0; + ((DCI1A_5MHz_FDD_t*)BCCH_alloc_pdu)->ndi = 1; + ((DCI1A_5MHz_FDD_t*)BCCH_alloc_pdu)->rv = 1; + ((DCI1A_5MHz_FDD_t*)BCCH_alloc_pdu)->harq_pid = 0; + ((DCI1A_5MHz_FDD_t*)BCCH_alloc_pdu)->TPC = 1; + ((DCI1A_5MHz_FDD_t*)BCCH_alloc_pdu)->padding = 0; + + rballoc[CC_id] |= mac_xface->get_rballoc(0,((DCI1A_5MHz_FDD_t*)BCCH_alloc_pdu)->rballoc); + sizeof1A_bytes = sizeof(DCI1A_5MHz_FDD_t); + sizeof1A_bits = sizeof_DCI1A_5MHz_FDD_t; break; case 50: ((DCI1A_10MHz_FDD_t*)BCCH_alloc_pdu)->mcs = mcs; + ((DCI1A_10MHz_FDD_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); + ((DCI1A_10MHz_FDD_t*)BCCH_alloc_pdu)->type = 1; + ((DCI1A_10MHz_FDD_t*)BCCH_alloc_pdu)->vrb_type = 0; + ((DCI1A_10MHz_FDD_t*)BCCH_alloc_pdu)->ndi = 1; + ((DCI1A_10MHz_FDD_t*)BCCH_alloc_pdu)->rv = 1; + ((DCI1A_10MHz_FDD_t*)BCCH_alloc_pdu)->harq_pid = 0; + ((DCI1A_10MHz_FDD_t*)BCCH_alloc_pdu)->TPC = 1; + ((DCI1A_10MHz_FDD_t*)BCCH_alloc_pdu)->padding = 0; + + rballoc[CC_id] |= mac_xface->get_rballoc(0,((DCI1A_10MHz_FDD_t*)BCCH_alloc_pdu)->rballoc); + sizeof1A_bytes = sizeof(DCI1A_10MHz_FDD_t); + sizeof1A_bits = sizeof_DCI1A_10MHz_FDD_t; break; case 100: ((DCI1A_20MHz_FDD_t*)BCCH_alloc_pdu)->mcs = mcs; - break; + ((DCI1A_20MHz_FDD_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); + ((DCI1A_20MHz_FDD_t*)BCCH_alloc_pdu)->type = 1; + ((DCI1A_20MHz_FDD_t*)BCCH_alloc_pdu)->vrb_type = 0; + ((DCI1A_20MHz_FDD_t*)BCCH_alloc_pdu)->ndi = 1; + ((DCI1A_20MHz_FDD_t*)BCCH_alloc_pdu)->rv = 1; + ((DCI1A_20MHz_FDD_t*)BCCH_alloc_pdu)->harq_pid = 0; + ((DCI1A_20MHz_FDD_t*)BCCH_alloc_pdu)->TPC = 1; + ((DCI1A_20MHz_FDD_t*)BCCH_alloc_pdu)->padding = 0; + + rballoc[CC_id] |= mac_xface->get_rballoc(0,((DCI1A_20MHz_FDD_t*)BCCH_alloc_pdu)->rballoc); + sizeof1A_bytes = sizeof(DCI1A_20MHz_FDD_t); + sizeof1A_bits = sizeof_DCI1A_20MHz_FDD_t; + break; } } + if (!CCE_allocation_infeasible(module_idP,CC_id,1,subframeP,2,SI_RNTI)) { + add_common_dci(DCI_pdu, + BCCH_alloc_pdu, + SI_RNTI, + sizeof1A_bytes, + 2, + sizeof1A_bits, + format1A,0); + } + else { + LOG_E(MAC,"[eNB %d] CCid %d Frame %d, subframe %d : Cannot add DCI 1A for SI\n",module_idP, CC_id,frameP,subframeP); + } + if (opt_enabled == 1) { trace_pdu(1, &eNB->common_channels[CC_id].BCCH_pdu.payload[0], @@ -194,17 +322,15 @@ schedule_SI( mac_xface->get_TBS_DL(mcs,3)); } - eNB->common_channels[CC_id].bcch_active=1; + nprbP[CC_id]=3; - nCCEP[CC_id]=4; eNB->eNB_stats[CC_id].total_num_bcch_pdu+=1; eNB->eNB_stats[CC_id].bcch_buffer=bcch_sdu_length; eNB->eNB_stats[CC_id].total_bcch_buffer+=bcch_sdu_length; eNB->eNB_stats[CC_id].bcch_mcs=mcs; } else { - eNB->common_channels[CC_id].bcch_active=0; + nprbP[CC_id]=0; - nCCEP[CC_id]=0; //LOG_D(MAC,"[eNB %d] Frame %d : BCCH not active \n",Mod_id,frame); } } diff --git a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c index 3dea35f053..e3b1a96a55 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c @@ -423,7 +423,6 @@ schedule_ue_spec( frame_t frameP, sub_frame_t subframeP, unsigned int *nb_rb_used0, - unsigned int *nCCE_used, int* mbsfn_flag ) //------------------------------------------------------------------------------ @@ -431,7 +430,6 @@ schedule_ue_spec( uint8_t CC_id; int UE_id; - uint16_t nCCE[MAX_NUM_CCs]; int N_RBG[MAX_NUM_CCs]; unsigned char aggregation; mac_rlc_status_resp_t rlc_status; @@ -474,14 +472,12 @@ schedule_ue_spec( min_rb_unit[CC_id]=get_min_rb_unit(module_idP,CC_id); frame_parms[CC_id] = mac_xface->get_lte_frame_parms(module_idP,CC_id); total_nb_available_rb[CC_id] = frame_parms[CC_id]->N_RB_DL - nb_rb_used0[CC_id]; - nCCE[CC_id] = mac_xface->get_nCCE_max(module_idP,CC_id) - nCCE_used[CC_id]; N_RBG[CC_id] = frame_parms[CC_id]->N_RBG; // store the global enb stats: eNB->eNB_stats[CC_id].num_dlactive_UEs = UE_list->num_UEs; eNB->eNB_stats[CC_id].available_prbs = total_nb_available_rb[CC_id]; eNB->eNB_stats[CC_id].total_available_prbs += total_nb_available_rb[CC_id]; - eNB->eNB_stats[CC_id].available_ncces = nCCE[CC_id]; eNB->eNB_stats[CC_id].dlsch_bytes_tx=0; eNB->eNB_stats[CC_id].dlsch_pdus_tx=0; } @@ -523,9 +519,11 @@ schedule_ue_spec( continue_flag=1; } - if ((ue_sched_ctl->pre_nb_available_rbs[CC_id] == 0) || (nCCE[CC_id] < (1<pre_nb_available_rbs[CC_id] == 0) || // no RBs allocated + CCE_allocation_infeasible(module_idP,CC_id,0,subframeP,aggregation,rnti) + ) { LOG_D(MAC,"[eNB %d] Frame %d : no RB allocated for UE %d on CC_id %d: continue \n", - module_idP, frameP, UE_id, CC_id, nb_rb_used0[CC_id], ue_sched_ctl->pre_nb_available_rbs[CC_id], nCCE[CC_id], aggregation); + module_idP, frameP, UE_id, CC_id); //if(mac_xface->get_transmission_mode(module_idP,rnti)==5) continue_flag=1; //to next user (there might be rbs availiable for other UEs in TM5 // else @@ -587,11 +585,10 @@ schedule_ue_spec( UE_list->UE_template[CC_id][UE_id].rballoc_subband[harq_pid][j] = 0; } - LOG_D(MAC,"[eNB %d] Frame %d: Scheduling UE %d on CC_id %d (rnti %x, harq_pid %d, round %d, rb %d, cqi %d, mcs %d, ncc %d, rrc %d)\n", + LOG_D(MAC,"[eNB %d] Frame %d: Scheduling UE %d on CC_id %d (rnti %x, harq_pid %d, round %d, rb %d, cqi %d, mcs %d, rrc %d)\n", module_idP, frameP, UE_id,CC_id,rnti,harq_pid, round,nb_available_rb, eNB_UE_stats->DL_cqi[0], eNB_UE_stats->dlsch_mcs1, - nCCE[CC_id], - UE_list->eNB_UE_stats[CC_id][UE_id].rrc_status); + UE_list->eNB_UE_stats[CC_id][UE_id].rrc_status); // Note this code is for a specific DCI format @@ -641,8 +638,6 @@ schedule_ue_spec( nb_available_rb -= nb_rb; aggregation = process_ue_cqi(module_idP,UE_id); - nCCE[CC_id]-=(1<mu_mimo_mode[UE_id].pre_nb_available_rbs = nb_rb; @@ -789,7 +784,6 @@ schedule_ue_spec( UE_list->eNB_UE_stats[CC_id][UE_id].num_retransmission+=1; UE_list->eNB_UE_stats[CC_id][UE_id].rbs_used_retx=nb_rb; UE_list->eNB_UE_stats[CC_id][UE_id].total_rbs_used_retx+=nb_rb; - UE_list->eNB_UE_stats[CC_id][UE_id].ncce_used_retx=nCCE[CC_id]; UE_list->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1=eNB_UE_stats->dlsch_mcs1; UE_list->eNB_UE_stats[CC_id][UE_id].dlsch_mcs2=eNB_UE_stats->dlsch_mcs1; } else { @@ -1130,8 +1124,6 @@ schedule_ue_spec( } aggregation = process_ue_cqi(module_idP,UE_id); - nCCE[CC_id]-=(1<UE_template[CC_id][UE_id].nb_rb[harq_pid] = nb_rb; add_ue_dlsch_info(module_idP, @@ -1145,7 +1137,6 @@ schedule_ue_spec( UE_list->eNB_UE_stats[CC_id][UE_id].rbs_used = nb_rb; UE_list->eNB_UE_stats[CC_id][UE_id].total_rbs_used += nb_rb; - UE_list->eNB_UE_stats[CC_id][UE_id].ncce_used = nCCE[CC_id]; UE_list->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1=eNB_UE_stats->dlsch_mcs1; UE_list->eNB_UE_stats[CC_id][UE_id].dlsch_mcs2=mcs; UE_list->eNB_UE_stats[CC_id][UE_id].TBS = TBS; @@ -1498,10 +1489,9 @@ schedule_ue_spec( if (frame_parms[CC_id]->frame_type == TDD) { set_ul_DAI(module_idP,UE_id,CC_id,frameP,subframeP,frame_parms); } - } - } - //printf("MAC nCCE : %d\n",*nCCE_used); + } // UE_id loop + } // CC_id loop stop_meas(&eNB->schedule_dlsch); @@ -1512,13 +1502,12 @@ schedule_ue_spec( //------------------------------------------------------------------------------ void fill_DLSCH_dci( - module_id_t module_idP, - frame_t frameP, - sub_frame_t subframeP, - uint32_t* RBallocP, - uint8_t RA_scheduledP, - int* mbsfn_flagP -) + module_id_t module_idP, + frame_t frameP, + sub_frame_t subframeP, + uint32_t* RBallocP, + int* mbsfn_flagP + ) //------------------------------------------------------------------------------ { @@ -1526,7 +1515,7 @@ fill_DLSCH_dci( int UE_id = -1; uint8_t first_rb,nb_rb=3; rnti_t rnti; - unsigned char vrb_map[100]; + unsigned char *vrb_map; uint8_t rballoc_sub[25]; //uint8_t number_of_subbands=13; uint32_t *rballoc=RBallocP; @@ -1552,598 +1541,8 @@ fill_DLSCH_dci( if (mbsfn_flagP[CC_id]>0) continue; - DCI_pdu = &eNB->common_channels[CC_id].DCI_pdu; - BCCH_alloc_pdu=(void*)&eNB->common_channels[CC_id].BCCH_alloc_pdu; - // clear vrb_map - memset(vrb_map,0,100); - - - // SI DLSCH - // printf("BCCH check\n"); - if (eNB->common_channels[CC_id].bcch_active == 1) { - eNB->common_channels[CC_id].bcch_active = 0; - LOG_D(MAC,"[eNB %d] CC_id %d Frame %d subframeP %d: BCCH active\n", module_idP, CC_id, frameP, subframeP); - // randomize frequency allocation for SI - first_rb = 0;//10;//(unsigned char)(taus()%(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL-4)); - - /* Where is this from, should be removed!!!! - - if (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.frame_type == TDD) { - - } - else { - BCCH_alloc_pdu_fdd.rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - rballoc[CC_id] |= mac_xface->get_rballoc(BCCH_alloc_pdu_fdd.vrb_type,BCCH_alloc_pdu_fdd.rballoc); - } - */ - - - vrb_map[first_rb] = 1; - vrb_map[first_rb+1] = 1; - vrb_map[first_rb+2] = 1; - vrb_map[first_rb+3] = 1; - - if (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.frame_type == TDD) { - switch (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL) { - case 6: - ((DCI1A_1_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - ((DCI1A_1_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->type = 1; - ((DCI1A_1_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->vrb_type = 0; - ((DCI1A_1_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->ndi = 1; - ((DCI1A_1_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rv = 1; - ((DCI1A_1_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->harq_pid = 0; - ((DCI1A_1_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->TPC = 1; - ((DCI1A_1_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->padding = 0; - rballoc[CC_id] |= mac_xface->get_rballoc(0,((DCI1A_1_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rballoc); - add_common_dci(DCI_pdu, - BCCH_alloc_pdu, - SI_RNTI, - sizeof(DCI1A_1_5MHz_TDD_1_6_t), - 2, - sizeof_DCI1A_1_5MHz_TDD_1_6_t, - format1A,0); - break; - - case 25: - ((DCI1A_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - ((DCI1A_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->type = 1; - ((DCI1A_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->vrb_type = 0; - ((DCI1A_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->ndi = 1; - ((DCI1A_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rv = 1; - ((DCI1A_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->harq_pid = 0; - ((DCI1A_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->TPC = 1; - ((DCI1A_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->padding = 0; - rballoc[CC_id] |= mac_xface->get_rballoc(0,((DCI1A_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rballoc); - add_common_dci(DCI_pdu, - BCCH_alloc_pdu, - SI_RNTI, - sizeof(DCI1A_5MHz_TDD_1_6_t), - 2, - sizeof_DCI1A_5MHz_TDD_1_6_t, - format1A,0); - break; - - case 50: - ((DCI1A_10MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - ((DCI1A_10MHz_TDD_1_6_t*)BCCH_alloc_pdu)->type = 1; - ((DCI1A_10MHz_TDD_1_6_t*)BCCH_alloc_pdu)->vrb_type = 0; - ((DCI1A_10MHz_TDD_1_6_t*)BCCH_alloc_pdu)->ndi = 1; - ((DCI1A_10MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rv = 1; - ((DCI1A_10MHz_TDD_1_6_t*)BCCH_alloc_pdu)->harq_pid = 0; - ((DCI1A_10MHz_TDD_1_6_t*)BCCH_alloc_pdu)->TPC = 1; - ((DCI1A_10MHz_TDD_1_6_t*)BCCH_alloc_pdu)->padding = 0; - rballoc[CC_id] |= mac_xface->get_rballoc(0,((DCI1A_10MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rballoc); - add_common_dci(DCI_pdu, - BCCH_alloc_pdu, - SI_RNTI, - sizeof(DCI1A_10MHz_TDD_1_6_t), - 2, - sizeof_DCI1A_10MHz_TDD_1_6_t, - format1A,0); - break; - - case 100: - ((DCI1A_20MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - ((DCI1A_20MHz_TDD_1_6_t*)BCCH_alloc_pdu)->type = 1; - ((DCI1A_20MHz_TDD_1_6_t*)BCCH_alloc_pdu)->vrb_type = 0; - ((DCI1A_20MHz_TDD_1_6_t*)BCCH_alloc_pdu)->ndi = 1; - ((DCI1A_20MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rv = 1; - ((DCI1A_20MHz_TDD_1_6_t*)BCCH_alloc_pdu)->harq_pid = 0; - ((DCI1A_20MHz_TDD_1_6_t*)BCCH_alloc_pdu)->TPC = 1; - ((DCI1A_20MHz_TDD_1_6_t*)BCCH_alloc_pdu)->padding = 0; - rballoc[CC_id] |= mac_xface->get_rballoc(0,((DCI1A_20MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rballoc); - add_common_dci(DCI_pdu, - BCCH_alloc_pdu, - SI_RNTI, - sizeof(DCI1A_20MHz_TDD_1_6_t), - 2, - sizeof_DCI1A_20MHz_TDD_1_6_t, - format1A,0); - break; - } - } else { - switch (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL) { - case 6: - ((DCI1A_1_5MHz_FDD_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - ((DCI1A_1_5MHz_FDD_t*)BCCH_alloc_pdu)->type = 1; - ((DCI1A_1_5MHz_FDD_t*)BCCH_alloc_pdu)->vrb_type = 0; - ((DCI1A_1_5MHz_FDD_t*)BCCH_alloc_pdu)->ndi = 1; - ((DCI1A_1_5MHz_FDD_t*)BCCH_alloc_pdu)->rv = 1; - ((DCI1A_1_5MHz_FDD_t*)BCCH_alloc_pdu)->harq_pid = 0; - ((DCI1A_1_5MHz_FDD_t*)BCCH_alloc_pdu)->TPC = 1; - ((DCI1A_1_5MHz_FDD_t*)BCCH_alloc_pdu)->padding = 0; - - rballoc[CC_id] |= mac_xface->get_rballoc(0,((DCI1A_1_5MHz_FDD_t*)BCCH_alloc_pdu)->rballoc); - add_common_dci(DCI_pdu, - BCCH_alloc_pdu, - SI_RNTI, - sizeof(DCI1A_1_5MHz_FDD_t), - 2, - sizeof_DCI1A_1_5MHz_FDD_t, - format1A,0); - break; - - case 25: - ((DCI1A_5MHz_FDD_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - ((DCI1A_5MHz_FDD_t*)BCCH_alloc_pdu)->type = 1; - ((DCI1A_5MHz_FDD_t*)BCCH_alloc_pdu)->vrb_type = 0; - ((DCI1A_5MHz_FDD_t*)BCCH_alloc_pdu)->ndi = 1; - ((DCI1A_5MHz_FDD_t*)BCCH_alloc_pdu)->rv = 1; - ((DCI1A_5MHz_FDD_t*)BCCH_alloc_pdu)->harq_pid = 0; - ((DCI1A_5MHz_FDD_t*)BCCH_alloc_pdu)->TPC = 1; - ((DCI1A_5MHz_FDD_t*)BCCH_alloc_pdu)->padding = 0; - - rballoc[CC_id] |= mac_xface->get_rballoc(0,((DCI1A_5MHz_FDD_t*)BCCH_alloc_pdu)->rballoc); - add_common_dci(DCI_pdu, - BCCH_alloc_pdu, - SI_RNTI, - sizeof(DCI1A_5MHz_FDD_t), - 2, - sizeof_DCI1A_5MHz_FDD_t, - format1A,0); - break; - - case 50: - ((DCI1A_10MHz_FDD_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - ((DCI1A_10MHz_FDD_t*)BCCH_alloc_pdu)->type = 1; - ((DCI1A_10MHz_FDD_t*)BCCH_alloc_pdu)->vrb_type = 0; - ((DCI1A_10MHz_FDD_t*)BCCH_alloc_pdu)->ndi = 1; - ((DCI1A_10MHz_FDD_t*)BCCH_alloc_pdu)->rv = 1; - ((DCI1A_10MHz_FDD_t*)BCCH_alloc_pdu)->harq_pid = 0; - ((DCI1A_10MHz_FDD_t*)BCCH_alloc_pdu)->TPC = 1; - ((DCI1A_10MHz_FDD_t*)BCCH_alloc_pdu)->padding = 0; - - rballoc[CC_id] |= mac_xface->get_rballoc(0,((DCI1A_10MHz_FDD_t*)BCCH_alloc_pdu)->rballoc); - add_common_dci(DCI_pdu, - BCCH_alloc_pdu, - SI_RNTI, - sizeof(DCI1A_10MHz_FDD_t), - 2, - sizeof_DCI1A_10MHz_FDD_t, - format1A,0); - break; - - case 100: - ((DCI1A_20MHz_FDD_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - ((DCI1A_20MHz_FDD_t*)BCCH_alloc_pdu)->type = 1; - ((DCI1A_20MHz_FDD_t*)BCCH_alloc_pdu)->vrb_type = 0; - ((DCI1A_20MHz_FDD_t*)BCCH_alloc_pdu)->ndi = 1; - ((DCI1A_20MHz_FDD_t*)BCCH_alloc_pdu)->rv = 1; - ((DCI1A_20MHz_FDD_t*)BCCH_alloc_pdu)->harq_pid = 0; - ((DCI1A_20MHz_FDD_t*)BCCH_alloc_pdu)->TPC = 1; - ((DCI1A_20MHz_FDD_t*)BCCH_alloc_pdu)->padding = 0; - - rballoc[CC_id] |= mac_xface->get_rballoc(0,((DCI1A_20MHz_FDD_t*)BCCH_alloc_pdu)->rballoc); - add_common_dci(DCI_pdu, - BCCH_alloc_pdu, - SI_RNTI, - sizeof(DCI1A_20MHz_FDD_t), - 2, - sizeof_DCI1A_20MHz_FDD_t, - format1A,0); - break; - } - } - } - - if (RA_scheduledP == 1) { - for (i=0; icommon_channels[CC_id].RA_template[i]; - - if (RA_template->generate_rar == 1) { - - //FK: postponed to fill_rar - //RA_template->generate_rar = 0; - - LOG_D(MAC,"[eNB %d] CC_id %d Frame %d, subframeP %d: Generating RAR DCI (proc %d), RA_active %d format 1A (%d,%d))\n", - module_idP, CC_id, frameP, subframeP,i, - RA_template->RA_active, - RA_template->RA_dci_fmt1, - RA_template->RA_dci_size_bits1); - - // randomize frequency allocation for RA - while (1) { - first_rb = (unsigned char)(taus()%(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL-4)); - - if ((vrb_map[first_rb] != 1) && (vrb_map[first_rb+3] != 1)) - break; - } - - vrb_map[first_rb] = 1; - vrb_map[first_rb+1] = 1; - vrb_map[first_rb+2] = 1; - vrb_map[first_rb+3] = 1; - - if (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.frame_type == TDD) { - switch(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL) { - case 6: - ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->type=1; - ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type=0; - ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->ndi=1; - ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rv=0; - ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->mcs=0; - ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0; - ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1; - ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->padding=0; - ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type, - ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc); - break; - - case 25: - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->type=1; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type=0; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->ndi=1; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rv=0; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->mcs=0; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->padding=0; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type, - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc); - break; - - case 50: - ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->type=1; - ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type=0; - ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->ndi=1; - ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rv=0; - ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->mcs=0; - ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0; - ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1; - ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->padding=0; - ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type, - ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc); - break; - - case 100: - ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->type=1; - ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type=0; - ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->ndi=1; - ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rv=0; - ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->mcs=0; - ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0; - ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1; - ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->padding=0; - ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type, - ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc); - break; - - default: - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->type=1; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type=0; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->ndi=1; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rv=0; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->mcs=0; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->padding=0; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type, - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc); - break; - } - } else { - switch(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL) { - case 6: - ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->type=1; - ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type=0; - ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->ndi=1; - ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rv=0; - ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->mcs=0; - ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0; - ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1; - ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->padding=0; - ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type, - ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc); - break; - - case 25: - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->type=1; - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type=0; - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->ndi=1; - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rv=0; - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->mcs=0; - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0; - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1; - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->padding=0; - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_UL,first_rb,4); - rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type, - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc); - break; - - case 50: - ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->type=1; - ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type=0; - ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->ndi=1; - ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rv=0; - ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->mcs=0; - ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0; - ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1; - ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->padding=0; - ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type, - ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc); - break; - - case 100: - ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->type=1; - ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type=0; - ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->ndi=1; - ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rv=0; - ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->mcs=0; - ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0; - ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1; - ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->padding=0; - ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type, - ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc); - break; - - default: - break; - } - } - - add_common_dci(DCI_pdu, - (void*)&RA_template->RA_alloc_pdu1[0], - RA_template->RA_rnti, - RA_template->RA_dci_size_bytes1, - 2, - RA_template->RA_dci_size_bits1, - RA_template->RA_dci_fmt1, - 1); - - - - LOG_D(MAC,"[eNB %d] CC_id %d Frame %d: Adding common dci for RA%d (RAR) RA_active %d\n", - module_idP,CC_id,frameP,i, RA_template->RA_active); - } - - if (RA_template->generate_Msg4_dci == 1) { - - // randomize frequency allocation for RA - while (1) { - first_rb = (unsigned char)(taus()%(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL-4)); - - if ((vrb_map[first_rb] != 1) && (vrb_map[first_rb+3] != 1)) - break; - } - - vrb_map[first_rb] = 1; - vrb_map[first_rb+1] = 1; - vrb_map[first_rb+2] = 1; - vrb_map[first_rb+3] = 1; - - if (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.frame_type == TDD) { - switch (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL) { - case 6: - ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->type=1; - ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type=0; - ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rv=0; - ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->harq_pid=0; - ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->TPC=1; - ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->padding=0; - ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type, - ((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc); - break; - - case 25: - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->type=1; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type=0; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rv=0; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->harq_pid=0; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->TPC=1; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->padding=0; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type, - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc); - break; - - case 50: - ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->type=1; - ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type=0; - ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rv=0; - ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->harq_pid=0; - ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->TPC=1; - ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->padding=0; - ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type, - ((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc); - break; - - case 100: - ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->type=1; - ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type=0; - ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rv=0; - ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->harq_pid=0; - ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->TPC=1; - ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type, - ((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc); - break; - - default: - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->type=1; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type=0; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rv=0; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->harq_pid=0; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->TPC=1; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->padding=0; - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type, - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc); - break; - } - } else { - switch (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL) { - - case 6: - ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->type=1; - ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type=0; - ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rv=0; - ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->harq_pid=0; - ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->TPC=1; - ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->padding=0; - ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type, - ((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc); - break; - - case 25: - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->type=1; - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type=0; - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rv=0; - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->harq_pid=0; - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->TPC=1; - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->padding=0; - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type, - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc); - break; - - case 50: - ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->type=1; - ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type=0; - ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rv=0; - ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->harq_pid=0; - ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->TPC=1; - ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->padding=0; - ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type, - ((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc); - break; - - case 100: - ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->type=1; - ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type=0; - ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rv=0; - ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->harq_pid=0; - ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->TPC=1; - ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->padding=0; - ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type, - ((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc); - break; - - default: - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->type=1; - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type=0; - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rv=0; - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->harq_pid=0; - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->TPC=1; - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4); - rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type, - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc); - break; - } - } - - add_ue_spec_dci(DCI_pdu, - (void*)&RA_template->RA_alloc_pdu2[0], - RA_template->rnti, - RA_template->RA_dci_size_bytes2, - 1, - RA_template->RA_dci_size_bits2, - RA_template->RA_dci_fmt2, - 0); - LOG_D(MAC,"[eNB %d][RAPROC] CC_id %d Frame %d, subframeP %d: Adding ue specific dci (rnti %x) for Msg4\n", - module_idP,CC_id,frameP,subframeP,RA_template->rnti); - RA_template->generate_Msg4_dci=0; - - } else if (RA_template->wait_ack_Msg4==1) { - // check HARQ status and retransmit if necessary - LOG_I(MAC,"[eNB %d][RAPROC] CC_id %d Frame %d, subframeP %d: Checking if Msg4 was acknowledged: \n", - module_idP,CC_id,frameP,subframeP); - // Get candidate harq_pid from PHY - mac_xface->get_ue_active_harq_pid(module_idP,CC_id,RA_template->rnti,frameP,subframeP,&harq_pid,&round,0); - - if (round>0) { - //RA_template->wait_ack_Msg4++; - // we have to schedule a retransmission - if (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.frame_type == TDD) { - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->ndi=1; - } else { - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->ndi=1; - } - - // randomize frequency allocation for RA - while (1) { - first_rb = (unsigned char)(taus()%(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL-4)); - - if ((vrb_map[first_rb] != 1) && (vrb_map[first_rb+3] != 1)) - break; - } - - vrb_map[first_rb] = 1; - vrb_map[first_rb+1] = 1; - vrb_map[first_rb+2] = 1; - vrb_map[first_rb+3] = 1; - - if (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.frame_type == TDD) { - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_UL,first_rb,4); - rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type, - ((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc); - } else { - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_UL,first_rb,4); - rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type, - ((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc); - } - - add_ue_spec_dci(DCI_pdu, - (void*)&RA_template->RA_alloc_pdu2[0], - RA_template->rnti, - RA_template->RA_dci_size_bytes2, - 2, - RA_template->RA_dci_size_bits2, - RA_template->RA_dci_fmt2, - 0); - LOG_W(MAC,"[eNB %d][RAPROC] CC_id %d Frame %d, subframeP %d: Msg4 not acknowledged, adding ue specific dci (rnti %x) for RA (Msg4 Retransmission)\n", - module_idP,CC_id,frameP,subframeP,RA_template->rnti); - } else { - /* msg4 not received - if ((round == 0) && (RA_template->wait_ack_Msg4>1){ - remove UE instance across all the layers: mac_xface->cancel_RA(); - } - */ - LOG_I(MAC,"[eNB %d][RAPROC] CC_id %d Frame %d, subframeP %d : Msg4 acknowledged\n",module_idP,CC_id,frameP,subframeP); - RA_template->wait_ack_Msg4=0; - RA_template->RA_active=FALSE; - UE_id = find_UE_id(module_idP,RA_template->rnti); - DevAssert( UE_id != -1 ); - eNB_mac_inst[module_idP].UE_list.UE_template[UE_PCCID(module_idP,UE_id)][UE_id].configured=TRUE; - - } - } - } - } // RA is scheduled in this subframeP - + DCI_pdu = &eNB->common_channels[CC_id].DCI_pdu; + // UE specific DCIs for (UE_id=UE_list->head; UE_id>=0; UE_id=UE_list->next[UE_id]) { diff --git a/openair2/LAYER2/MAC/eNB_scheduler_primitives.c b/openair2/LAYER2/MAC/eNB_scheduler_primitives.c index 34169d902e..da2e5f311e 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_primitives.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_primitives.c @@ -879,3 +879,208 @@ int get_nb_subband(void) return nb_sb; } + +void init_CCE_table(int module_idP,int CC_idP) +{ + memset(eNB_mac_inst[module_idP].CCE_table[CC_idP],0,800*sizeof(int)); +} + + +int get_nCCE_offset(int *CCE_table, + const unsigned char L, + const int nCCE, + const int common_dci, + const unsigned short rnti, + const unsigned char subframe) +{ + + int search_space_free,m,nb_candidates = 0,l,i; + unsigned int Yk; + /* + printf("CCE Allocation: "); + for (i=0;i=0 ; m--) { + + search_space_free = 1; + for (l=0; lget_nCCE_max(module_idP,CC_idP,DCI_pdu->num_pdcch_symbols,subframeP); + int fCCE; + int i; + int allocation_is_feasible = 1; + DCI_ALLOC_t *dci_alloc; + + LOG_I(MAC,"Allocate CCEs subframe %d, test %d\n",subframeP,test_onlyP); + init_CCE_table(module_idP,CC_idP); + DCI_pdu->nCCE=0; + + while (allocation_is_feasible == 1) { + + for (i=0;iNum_common_dci + DCI_pdu->Num_ue_spec_dci;i++) { + dci_alloc = &DCI_pdu->dci_alloc[i]; + LOG_I(MAC,"Trying to allocate DCI %d/%d (%d,%d) : rnti %x, aggreg %d nCCE %d / %d (num_pdcch_symbols %d)\n", + i,DCI_pdu->Num_common_dci+DCI_pdu->Num_ue_spec_dci, + DCI_pdu->Num_common_dci,DCI_pdu->Num_ue_spec_dci, + dci_alloc->rnti,1<L, + DCI_pdu->nCCE,nCCE_max,DCI_pdu->num_pdcch_symbols); + + if (DCI_pdu->nCCE + (1<L) > nCCE_max) { + if (DCI_pdu->num_pdcch_symbols == 3) + allocation_is_feasible = 0; + else { + DCI_pdu->num_pdcch_symbols++; + nCCE_max = mac_xface->get_nCCE_max(module_idP,CC_idP,DCI_pdu->num_pdcch_symbols,subframeP); + } + break; + } + else { // number of CCEs left can potentially hold this allocation + if ((fCCE = get_nCCE_offset(CCE_table, + 1<<(dci_alloc->L), + nCCE_max, + (iNum_common_dci) ? 1 : 0, + dci_alloc->rnti, + subframeP))>=0) {// the allocation is feasible, rnti rule passes + LOG_I(MAC,"Allocating at nCCE %d\n",fCCE); + if (test_onlyP == 0) { + DCI_pdu->nCCE += (1<L); + dci_alloc->firstCCE=fCCE; + LOG_I(MAC,"Allocate CCEs subframe %d, test %d\n",subframeP,test_onlyP); + } + } // fCCE>=0 + else { + if (DCI_pdu->num_pdcch_symbols == 3) + allocation_is_feasible = 0; + else { + DCI_pdu->num_pdcch_symbols++; + nCCE_max = mac_xface->get_nCCE_max(module_idP,CC_idP,DCI_pdu->num_pdcch_symbols,subframeP); + } + break; + } // fCCE==-1 + } // nCCE <= nCCE_max + } // for i = 0 ... num_dcis + if (allocation_is_feasible==1) + return (0); + } // allocation_is_feasible == 1 + + return(-1); + + +} + +boolean_t CCE_allocation_infeasible(int module_idP, + int CC_idP, + int common_flag, + int subframe, + int aggregation, + int rnti) { + + + DCI_PDU *DCI_pdu = &eNB_mac_inst[module_idP].common_channels[CC_idP].DCI_pdu; + DCI_ALLOC_t *dci_alloc; + int ret; + boolean_t res=FALSE; + + if (common_flag==1) { + DCI_pdu->dci_alloc[DCI_pdu->Num_common_dci + DCI_pdu->Num_ue_spec_dci].rnti = rnti; + DCI_pdu->dci_alloc[DCI_pdu->Num_common_dci + DCI_pdu->Num_ue_spec_dci].L = aggregation; + DCI_pdu->Num_common_dci++; + ret = allocate_CCEs(module_idP,CC_idP,subframe,1); + if (ret==-1) + res = TRUE; + DCI_pdu->Num_common_dci--; + } + else { + DCI_pdu->dci_alloc[DCI_pdu->Num_common_dci + DCI_pdu->Num_ue_spec_dci].rnti = rnti; + DCI_pdu->dci_alloc[DCI_pdu->Num_common_dci + DCI_pdu->Num_ue_spec_dci].L = aggregation; + DCI_pdu->Num_ue_spec_dci++; + ret = allocate_CCEs(module_idP,CC_idP,subframe,1); + if (ret==-1) + res = FALSE; + DCI_pdu->Num_ue_spec_dci--; + } +} + diff --git a/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c b/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c index 10c728f2a7..82aca12b34 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c @@ -596,12 +596,14 @@ unsigned char *parse_ulsch_header(unsigned char *mac_header, } -void schedule_ulsch(module_id_t module_idP, frame_t frameP,unsigned char cooperation_flag,sub_frame_t subframeP, unsigned char sched_subframe, - unsigned int *nCCE) //,int calibration_flag) { -{ +void schedule_ulsch(module_id_t module_idP, + frame_t frameP, + unsigned char cooperation_flag, + sub_frame_t subframeP, + unsigned char sched_subframe) { + - unsigned int nCCE_available[MAX_NUM_CCs]; uint16_t first_rb[MAX_NUM_CCs],i; int CC_id; eNB_MAC_INST *eNB=&eNB_mac_inst[module_idP]; @@ -612,7 +614,6 @@ void schedule_ulsch(module_id_t module_idP, frame_t frameP,unsigned char coopera for (CC_id=0; CC_idget_nCCE_max(module_idP,CC_id) - nCCE[CC_id]; // UE data info; // check which UE has data to transmit @@ -644,10 +645,10 @@ void schedule_ulsch(module_id_t module_idP, frame_t frameP,unsigned char coopera } - schedule_ulsch_rnti(module_idP, cooperation_flag, frameP, subframeP, sched_subframe, nCCE, nCCE_available, first_rb); + schedule_ulsch_rnti(module_idP, cooperation_flag, frameP, subframeP, sched_subframe,first_rb); #ifdef CBA - schedule_ulsch_cba_rnti(module_idP, cooperation_flag, frameP, subframeP, sched_subframe, nCCE, nCCE_available, first_rb); + schedule_ulsch_cba_rnti(module_idP, cooperation_flag, frameP, subframeP, sched_subframe, first_rb); #endif @@ -662,8 +663,6 @@ void schedule_ulsch_rnti(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP, unsigned char sched_subframe, - unsigned int *nCCE, - unsigned int *nCCE_available, uint16_t *first_rb) { @@ -697,8 +696,7 @@ void schedule_ulsch_rnti(module_id_t module_idP, frameP, subframeP, first_rb, - aggregation, - nCCE); + aggregation); // LOG_I(MAC,"exiting ulsch preprocesor\n"); @@ -729,8 +727,8 @@ void schedule_ulsch_rnti(module_id_t module_idP, continue; // mac_xface->macphy_exit("[MAC][eNB] Cannot find eNB_UE_stats\n"); } - if (nCCE_available[CC_id] < (1<mode]); + LOG_T(MAC,"[eNB %d] Frame %d, subframeP %d, UE %d CC %d : got harq pid %d round %d (rnti %x,mode %s)\n", + module_idP,frameP,subframeP,UE_id,CC_id, harq_pid, round,rnti,mode_string[eNB_UE_stats->mode]); #undef EXMIMO_IOT #ifndef EXMIMO_IOT @@ -1089,9 +1087,6 @@ void schedule_ulsch_rnti(module_id_t module_idP, subframeP, S_UL_SCHEDULED); - nCCE[CC_id] = nCCE[CC_id] + (1<get_nCCE_max(module_idP,CC_id) - nCCE[CC_id]; - LOG_D(MAC,"[eNB %d] CC_id %d Frame %d, subframeP %d: Generated ULSCH DCI for next UE_id %d, format 0\n", module_idP,CC_id,frameP,subframeP,UE_id); #ifdef DEBUG dump_dci(frame_parms, &DCI_pdu->dci_alloc[DCI_pdu->Num_common_dci+DCI_pdu->Num_ue_spec_dci-1]); @@ -1104,8 +1099,7 @@ void schedule_ulsch_rnti(module_id_t module_idP, } #ifdef CBA -void schedule_ulsch_cba_rnti(module_id_t module_idP, unsigned char cooperation_flag, frame_t frameP, sub_frame_t subframeP, unsigned char sched_subframe, unsigned int *nCCE, - unsigned int *nCCE_available, uint16_t *first_rb) +void schedule_ulsch_cba_rnti(module_id_t module_idP, unsigned char cooperation_flag, frame_t frameP, sub_frame_t subframeP, unsigned char sched_subframe, uint16_t *first_rb) { eNB_MAC_INST *eNB = &eNB_mac_inst[module_idP]; @@ -1164,11 +1158,11 @@ void schedule_ulsch_cba_rnti(module_id_t module_idP, unsigned char cooperation_f // cba group template uses the exisitng UE template, and thus if a UE // is scheduled, the correspodning group can't be used for CBA // this can be fixed later - if ((total_groups > 0) && (nCCE[CC_id] == 0)) { + if (total_groups > 0) { DCI_pdu = &eNB_mac_inst[module_idP].common_channels[CC_id].DCI_pdu; for (cba_group=0; - (cba_group (1< (1<= nCCE_available[CC_id]) { - num_cba_resources[cba_group%total_groups]--; - total_cba_resources--; - // LOG_N(MAC,"reducing num cba resources to %d for group %d \n", num_cba_resources[cba_group%total_groups], cba_group%total_groups ); - cba_group++; - } - if (total_cba_resources <= 0) { return; } @@ -1280,11 +1267,11 @@ void schedule_ulsch_cba_rnti(module_id_t module_idP, unsigned char cooperation_f for (cba_group=0; cba_groupN_RB_UL) { case 6: @@ -1426,8 +1413,6 @@ void schedule_ulsch_cba_rnti(module_id_t module_idP, unsigned char cooperation_f break; } - nCCE[CC_id] = nCCE[CC_id] + (1<get_nCCE_max(module_idP,CC_id) - nCCE[CC_id]; // break;// for the moment only schedule one } } diff --git a/openair2/LAYER2/MAC/main.c b/openair2/LAYER2/MAC/main.c index 5db78a30c2..a55301d80d 100644 --- a/openair2/LAYER2/MAC/main.c +++ b/openair2/LAYER2/MAC/main.c @@ -507,7 +507,7 @@ int l2_init(LTE_DL_FRAME_PARMS *frame_parms,int eMBMS_active, char *uecap_xer,ui mac_xface->computeRIV = computeRIV; mac_xface->get_TBS_DL = get_TBS_DL; mac_xface->get_TBS_UL = get_TBS_UL; - mac_xface->get_nCCE_max = get_nCCE_max; + mac_xface->get_nCCE_max = get_nCCE_mac; mac_xface->get_nCCE_offset = get_nCCE_offset; mac_xface->get_ue_mode = get_ue_mode; mac_xface->phy_config_sib1_eNB = phy_config_sib1_eNB; diff --git a/openair2/LAYER2/MAC/pre_processor.c b/openair2/LAYER2/MAC/pre_processor.c index 5a4caf82c4..316c79c524 100644 --- a/openair2/LAYER2/MAC/pre_processor.c +++ b/openair2/LAYER2/MAC/pre_processor.c @@ -828,8 +828,7 @@ void ulsch_scheduler_pre_processor(module_id_t module_idP, int frameP, sub_frame_t subframeP, uint16_t *first_rb, - uint8_t aggregation, - uint32_t *nCCE) + uint8_t aggregation) { int16_t i; @@ -839,7 +838,6 @@ void ulsch_scheduler_pre_processor(module_id_t module_idP, int16_t total_remaining_rbs[MAX_NUM_CCs]; uint16_t max_num_ue_to_be_scheduled=0,total_ue_count=0; rnti_t rnti= -1; - uint32_t nCCE_to_be_used[MAX_NUM_CCs]; UE_list_t *UE_list = &eNB_mac_inst[module_idP].UE_list; UE_TEMPLATE *UE_template = 0; LTE_DL_FRAME_PARMS *frame_parms = 0; @@ -860,7 +858,6 @@ void ulsch_scheduler_pre_processor(module_id_t module_idP, // we need to distribute RBs among UEs // step1: reset the vars for (CC_id=0; CC_idpre_allocated_nb_rb_ul > 0) { total_ue_count+=1; } - - if((mac_xface->get_nCCE_max(module_idP,CC_id) - nCCE_to_be_used[CC_id]) > (1<get_nCCE_max(module_idP,CC_id,3,subframeP) - nCCE_to_be_used[CC_id]) > (1<dlsch_eNB[i][j] = new_eNB_dlsch(1,NUMBER_OF_HARQ_PID_MAX,frame_parms->N_RB_DL,abstraction_flag); + PHY_vars_eNB->dlsch_eNB[i][j] = new_eNB_dlsch(1,NUMBER_OF_HARQ_PID_MAX,NSOFT,frame_parms->N_RB_DL,abstraction_flag); if (!PHY_vars_eNB->dlsch_eNB[i][j]) { LOG_E(PHY,"Can't get eNB dlsch structures for UE %d \n", i); @@ -128,11 +128,11 @@ PHY_VARS_eNB* init_lte_eNB(LTE_DL_FRAME_PARMS *frame_parms, exit(-1); } - PHY_vars_eNB->dlsch_eNB_SI = new_eNB_dlsch(1,1,frame_parms->N_RB_DL, abstraction_flag); + PHY_vars_eNB->dlsch_eNB_SI = new_eNB_dlsch(1,1,NSOFT,frame_parms->N_RB_DL, abstraction_flag); LOG_D(PHY,"eNB %d : SI %p\n",eNB_id,PHY_vars_eNB->dlsch_eNB_SI); - PHY_vars_eNB->dlsch_eNB_ra = new_eNB_dlsch(1,1,frame_parms->N_RB_DL, abstraction_flag); + PHY_vars_eNB->dlsch_eNB_ra = new_eNB_dlsch(1,1,NSOFT,frame_parms->N_RB_DL, abstraction_flag); LOG_D(PHY,"eNB %d : RA %p\n",eNB_id,PHY_vars_eNB->dlsch_eNB_ra); - PHY_vars_eNB->dlsch_eNB_MCH = new_eNB_dlsch(1,NUMBER_OF_HARQ_PID_MAX,frame_parms->N_RB_DL, 0); + PHY_vars_eNB->dlsch_eNB_MCH = new_eNB_dlsch(1,NUMBER_OF_HARQ_PID_MAX,NSOFT,frame_parms->N_RB_DL, 0); LOG_D(PHY,"eNB %d : MCH %p\n",eNB_id,PHY_vars_eNB->dlsch_eNB_MCH); @@ -169,7 +169,7 @@ PHY_VARS_UE* init_lte_UE(LTE_DL_FRAME_PARMS *frame_parms, for (i=0; idlsch_ue[i][j] = new_ue_dlsch(1,NUMBER_OF_HARQ_PID_MAX,MAX_TURBO_ITERATIONS,frame_parms->N_RB_DL, abstraction_flag); + PHY_vars_UE->dlsch_ue[i][j] = new_ue_dlsch(1,NUMBER_OF_HARQ_PID_MAX,NSOFT,MAX_TURBO_ITERATIONS,frame_parms->N_RB_DL, abstraction_flag); if (!PHY_vars_UE->dlsch_ue[i][j]) { LOG_E(PHY,"Can't get ue dlsch structures\n"); @@ -187,15 +187,15 @@ PHY_VARS_UE* init_lte_UE(LTE_DL_FRAME_PARMS *frame_parms, exit(-1); } - PHY_vars_UE->dlsch_ue_SI[i] = new_ue_dlsch(1,1,MAX_TURBO_ITERATIONS,frame_parms->N_RB_DL, abstraction_flag); - PHY_vars_UE->dlsch_ue_ra[i] = new_ue_dlsch(1,1,MAX_TURBO_ITERATIONS,frame_parms->N_RB_DL, abstraction_flag); + PHY_vars_UE->dlsch_ue_SI[i] = new_ue_dlsch(1,1,NSOFT,MAX_TURBO_ITERATIONS,frame_parms->N_RB_DL, abstraction_flag); + PHY_vars_UE->dlsch_ue_ra[i] = new_ue_dlsch(1,1,NSOFT,MAX_TURBO_ITERATIONS,frame_parms->N_RB_DL, abstraction_flag); PHY_vars_UE->transmission_mode[i] = transmission_mode; } PHY_vars_UE->lte_frame_parms.pucch_config_common.deltaPUCCH_Shift = 1; - PHY_vars_UE->dlsch_ue_MCH[0] = new_ue_dlsch(1,NUMBER_OF_HARQ_PID_MAX,MAX_TURBO_ITERATIONS_MBSFN,frame_parms->N_RB_DL,0); + PHY_vars_UE->dlsch_ue_MCH[0] = new_ue_dlsch(1,NUMBER_OF_HARQ_PID_MAX,NSOFT,MAX_TURBO_ITERATIONS_MBSFN,frame_parms->N_RB_DL,0); return (PHY_vars_UE); } @@ -211,11 +211,11 @@ PHY_VARS_RN* init_lte_RN(LTE_DL_FRAME_PARMS *frame_parms, if (eMBMS_active_state == multicast_relay) { for (i=0; i < 10 ; i++) { // num SF in a frame - PHY_vars_RN->dlsch_rn_MCH[i] = new_ue_dlsch(1,1,MAX_TURBO_ITERATIONS_MBSFN,frame_parms->N_RB_DL, 0); + PHY_vars_RN->dlsch_rn_MCH[i] = new_ue_dlsch(1,1,MAX_TURBO_ITERATIONS_MBSFN,NSOFT,frame_parms->N_RB_DL, 0); LOG_D(PHY,"eNB %d : MCH[%d] %p\n",RN_id,i,PHY_vars_RN->dlsch_rn_MCH[i]); } } else { - PHY_vars_RN->dlsch_rn_MCH[0] = new_ue_dlsch(1,1,MAX_TURBO_ITERATIONS,frame_parms->N_RB_DL, 0); + PHY_vars_RN->dlsch_rn_MCH[0] = new_ue_dlsch(1,1,MAX_TURBO_ITERATIONS,NSOFT,frame_parms->N_RB_DL, 0); LOG_D(PHY,"eNB %d : MCH[0] %p\n",RN_id,PHY_vars_RN->dlsch_rn_MCH[0]); }