All contiguous RB update
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@@ -34,7 +34,7 @@
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//#define DEBUG_PDCCH_DMRS
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//#define DEBUG_DCI
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//#define DEBUG_POLAR_PARAMS
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//#define DEBUG_CHANNEL_CODING
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#define PDCCH_TEST_POLAR_TEMP_FIX
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extern short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT];
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@@ -220,7 +220,7 @@ uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars,
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#endif
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polar_encoder_dci(dci_alloc.dci_pdu, encoder_output, currentPtr, n_RNTI);
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#ifdef DEBUG_POLAR_PARAMS
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#ifdef DEBUG_CHANNEL_CODING
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printf("DCI PDU: [0]->0x%08x \t [1]->0x%08x \t [2]->0x%08x \t [3]->0x%08x\n",
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dci_alloc.dci_pdu[0], dci_alloc.dci_pdu[1], dci_alloc.dci_pdu[2], dci_alloc.dci_pdu[3]);
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printf("Encoded Payload: [0]->0x%08x \t [1]->0x%08x \t [2]->0x%08x \t [3]->0x%08x\n",
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@@ -231,7 +231,7 @@ uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars,
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// QPSK modulation
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int16_t mod_dci[NR_MAX_DCI_SIZE>>1];
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for (int i=0; i<encoded_length>>1; i++) {
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idx = (((scrambled_output[i<<1]>>(i<<1))&1)<<1) ^ ((scrambled_output[(i<<1)+1]>>((i<<1)+1))&1);
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idx = ((((scrambled_output[(i<<1)>>5])>>((i<<1)&0x1f))&1)<<1) ^ (((scrambled_output[((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1);
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mod_dci[i<<1] = nr_mod_table[(NR_MOD_TABLE_QPSK_OFFSET + idx)<<1];
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mod_dci[(i<<1)+1] = nr_mod_table[((NR_MOD_TABLE_QPSK_OFFSET + idx)<<1) + 1];
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#ifdef DEBUG_DCI
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@@ -248,57 +248,70 @@ uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars,
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if (cset_start_sc >= frame_parms.ofdm_symbol_size)
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cset_start_sc -= frame_parms.ofdm_symbol_size;
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if (pdcch_params.precoder_granularity == NFAPI_NR_CSET_SAME_AS_REG_BUNDLE) {
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/*Reorder REG list for a freq first mapping*/
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uint8_t symb_idx[NR_MAX_CSET_DURATION] = {0,0,0};
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uint8_t nb_regs = dci_alloc.L*NR_NB_REG_PER_CCE;
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uint8_t regs_per_symb = nb_regs/cset_nsymb;
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for (int cce_idx=0; cce_idx<dci_alloc.L; cce_idx++){
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cce = dci_alloc.cce_list[cce_idx];
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for (int reg_idx=0; reg_idx<NR_NB_REG_PER_CCE; reg_idx++) {
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reg = cce.reg_list[reg_idx];
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reg_mapping_list[reg.symb_idx*regs_per_symb + symb_idx[reg.symb_idx]++] = reg;
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}
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/*Reorder REG list for a freq first mapping*/
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uint8_t symb_idx[NR_MAX_CSET_DURATION] = {0,0,0};
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uint8_t nb_regs = dci_alloc.L*NR_NB_REG_PER_CCE;
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uint8_t regs_per_symb = nb_regs/cset_nsymb;
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for (int cce_idx=0; cce_idx<dci_alloc.L; cce_idx++){
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cce = dci_alloc.cce_list[cce_idx];
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for (int reg_idx=0; reg_idx<NR_NB_REG_PER_CCE; reg_idx++) {
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reg = cce.reg_list[reg_idx];
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reg_mapping_list[reg.symb_idx*regs_per_symb + symb_idx[reg.symb_idx]++] = reg;
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}
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}
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#ifdef DEBUG_DCI
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printf("\n Ordered REG list:\n");
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for (int i=0; i<nb_regs; i++)
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printf("%d\t",reg_mapping_list[i].reg_idx );
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printf("\n");
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printf("\n Ordered REG list:\n");
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for (int i=0; i<nb_regs; i++)
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printf("%d\t",reg_mapping_list[i].reg_idx );
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printf("\n");
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#endif
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/*Now mapping based on newly constructed list*/
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for (int reg_idx=0; reg_idx<nb_regs; reg_idx++) {
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reg = reg_mapping_list[reg_idx];
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k = cset_start_sc + reg.start_sc_idx;
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if (k >= frame_parms.ofdm_symbol_size)
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if (pdcch_params.precoder_granularity == NFAPI_NR_CSET_ALL_CONTIGUOUS_RBS) {
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/*in this case the DMRS are mapped on all the coreset*/
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for (l=cset_start_symb; l<cset_start_symb+ cset_nsymb; l++) {
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dmrs_idx = 0;
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k = cset_start_sc + 1;
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while (dmrs_idx<3*pdcch_params.n_rb) {
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((int16_t*)txdataF[aa])[(l*frame_parms.ofdm_symbol_size + k)<<1] = (a * mod_dmrs[l][dmrs_idx<<1]) >> 15;
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((int16_t*)txdataF[aa])[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (a * mod_dmrs[l][(dmrs_idx<<1) + 1]) >> 15;
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k+=4;
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if (k >= frame_parms.ofdm_symbol_size)
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k -= frame_parms.ofdm_symbol_size;
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l = cset_start_symb + reg.symb_idx;
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dmrs_idx = (reg.reg_idx/cset_nsymb)*3;
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k_prime = 0;
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for (int m=0; m<NR_NB_SC_PER_RB; m++) {
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if ( m == (k_prime<<2)+1) { // DMRS
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dmrs_idx++;
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}
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}
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}
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/*Now mapping the encoded DCI based on newly constructed REG list
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* and the DMRS for the precoder granularity same as REG bundle*/
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for (int reg_idx=0; reg_idx<nb_regs; reg_idx++) {
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reg = reg_mapping_list[reg_idx];
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k = cset_start_sc + reg.start_sc_idx;
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if (k >= frame_parms.ofdm_symbol_size)
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k -= frame_parms.ofdm_symbol_size;
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l = cset_start_symb + reg.symb_idx;
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dmrs_idx = (reg.reg_idx/cset_nsymb)*3;
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k_prime = 0;
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for (int m=0; m<NR_NB_SC_PER_RB; m++) {
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if ( m == (k_prime<<2)+1) { // DMRS if not already mapped
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if (pdcch_params.precoder_granularity == NFAPI_NR_CSET_SAME_AS_REG_BUNDLE) {
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((int16_t*)txdataF[aa])[(l*frame_parms.ofdm_symbol_size + k)<<1] = (a * mod_dmrs[l][dmrs_idx<<1]) >> 15;
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((int16_t*)txdataF[aa])[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (a * mod_dmrs[l][(dmrs_idx<<1) + 1]) >> 15;
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k_prime++;
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dmrs_idx++;
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}
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else { // DCI payload
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((int16_t*)txdataF[aa])[(l*frame_parms.ofdm_symbol_size + k)<<1] = (a * mod_dci[dci_idx<<1]) >> 15;
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((int16_t*)txdataF[aa])[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (a * mod_dci[(dci_idx<<1) + 1]) >> 15;
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dci_idx++;
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}
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k++;
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if (k >= frame_parms.ofdm_symbol_size)
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k -= frame_parms.ofdm_symbol_size;
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}
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else { // DCI payload
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((int16_t*)txdataF[aa])[(l*frame_parms.ofdm_symbol_size + k)<<1] = (a * mod_dci[dci_idx<<1]) >> 15;
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((int16_t*)txdataF[aa])[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (a * mod_dci[(dci_idx<<1) + 1]) >> 15;
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dci_idx++;
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}
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k++;
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if (k >= frame_parms.ofdm_symbol_size)
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k -= frame_parms.ofdm_symbol_size;
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}
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}
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else { //NFAPI_NR_CSET_ALL_CONTIGUOUS_RBS
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}
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}
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#ifdef DEBUG_DCI
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