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Perform UL slot check in pre-processor

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This commit is contained in:
Robert Schmidt
2020-12-02 18:08:50 +01:00
parent 2e53fdea9c
commit 327e3e706d
2 changed files with 269 additions and 261 deletions
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openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
+266 -261
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@@ -463,8 +463,14 @@ int8_t select_ul_harq_pid(NR_UE_sched_ctrl_t *sched_ctrl) {
void nr_simple_ulsch_preprocessor(module_id_t module_id,
frame_t frame,
sub_frame_t slot) {
NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info;
sub_frame_t slot,
int num_slots_per_tdd,
uint64_t ulsch_in_slot_bitmap) {
gNB_MAC_INST *nr_mac = RC.nrmac[module_id];
NR_COMMON_channels_t *cc = nr_mac->common_channels;
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
const int mu = scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.subcarrierSpacing;
NR_UE_info_t *UE_info = &nr_mac->UE_info;
AssertFatal(UE_info->num_UEs <= 1,
"%s() cannot handle more than one UE, but found %d\n",
@@ -478,6 +484,30 @@ void nr_simple_ulsch_preprocessor(module_id_t module_id,
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
const int tda = 1;
const struct NR_PUSCH_TimeDomainResourceAllocationList *tdaList =
sched_ctrl->active_ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList;
AssertFatal(tda < tdaList->list.count,
"time domain assignment %d >= %d\n",
tda,
tdaList->list.count);
int K2 = get_K2(sched_ctrl->active_ubwp, tda, mu);
const int sched_frame = frame + (slot + K2 >= num_slots_per_tdd);
const int sched_slot = (slot + K2) % num_slots_per_tdd;
/* check if slot is UL, and for phy test verify that it is in first TDD
* period, slot 8 (for K2=6, this is at slot 2 in the gNB; because of UE
* limitations). Note that if K2 or the TDD configuration is changed, below
* conditions might exclude each other and never be true */
const bool transmit =
is_xlsch_in_slot(ulsch_in_slot_bitmap, sched_slot)
&& (!get_softmodem_params()->phy_test || sched_slot == 8);
if (!transmit)
return;
sched_ctrl->sched_pusch->time_domain_allocation = tda;
sched_ctrl->sched_pusch->slot = sched_slot;
sched_ctrl->sched_pusch->frame = sched_frame;
const int target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific;
sched_ctrl->search_space = get_searchspace(sched_ctrl->active_bwp, target_ss);
uint8_t nr_of_candidates;
@@ -514,280 +544,255 @@ void nr_schedule_ulsch(module_id_t module_id,
int num_slots_per_tdd,
int ul_slots,
uint64_t ulsch_in_slot_bitmap) {
gNB_MAC_INST *nr_mac = RC.nrmac[module_id];
NR_COMMON_channels_t *cc = nr_mac->common_channels;
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
const int mu = scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.subcarrierSpacing;
const int UE_id = 0;
NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info;
AssertFatal(UE_info->active[UE_id],"Cannot find UE_id %d is not active\n",UE_id);
nr_simple_ulsch_preprocessor(
module_id, frame, slot, num_slots_per_tdd, ulsch_in_slot_bitmap);
NR_CellGroupConfig_t *secondaryCellGroup = UE_info->secondaryCellGroup[UE_id];
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
if (sched_ctrl->sched_pusch->rbSize <= 0)
return;
const int tda = 1; // hardcoded for the moment
uint16_t rnti = UE_info->rnti[UE_id];
/* PUSCH in a later slot, but corresponding DCI now! */
nfapi_nr_ul_tti_request_t *future_ul_tti_req = &RC.nrmac[module_id]->UL_tti_req_ahead[0][sched_ctrl->sched_pusch->slot];
AssertFatal(future_ul_tti_req->SFN == sched_ctrl->sched_pusch->frame
&& future_ul_tti_req->Slot == sched_ctrl->sched_pusch->slot,
"%d.%d future UL_tti_req's frame.slot %d.%d does not match PUSCH %d.%d\n",
frame, slot,
future_ul_tti_req->SFN,
future_ul_tti_req->Slot,
sched_ctrl->sched_pusch->frame,
sched_ctrl->sched_pusch->slot);
future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE;
future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].pdu_size = sizeof(nfapi_nr_pusch_pdu_t);
nfapi_nr_pusch_pdu_t *pusch_pdu = &future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].pusch_pdu;
memset(pusch_pdu, 0, sizeof(nfapi_nr_pusch_pdu_t));
future_ul_tti_req->n_pdus += 1;
LOG_D(MAC, "%4d.%2d Scheduling UE specific PUSCH\n", frame, slot);
int dci_formats[2];
if (sched_ctrl->search_space->searchSpaceType->choice.ue_Specific->dci_Formats)
dci_formats[0] = NR_UL_DCI_FORMAT_0_1;
else
dci_formats[0] = NR_UL_DCI_FORMAT_0_0;
int rnti_types[2] = { NR_RNTI_C, 0 };
//Resource Allocation in time domain
const int tda = sched_ctrl->sched_pusch->time_domain_allocation;
const struct NR_PUSCH_TimeDomainResourceAllocationList *tdaList =
sched_ctrl->active_ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList;
AssertFatal(tda < tdaList->list.count,
"time domain assignment %d >= %d\n",
tda,
tdaList->list.count);
const int startSymbolAndLength = tdaList->list.array[tda]->startSymbolAndLength;
int StartSymbolIndex, NrOfSymbols;
SLIV2SL(startSymbolAndLength,&StartSymbolIndex,&NrOfSymbols);
pusch_pdu->start_symbol_index = StartSymbolIndex;
pusch_pdu->nr_of_symbols = NrOfSymbols;
int K2 = get_K2(sched_ctrl->active_ubwp, tda, mu);
/* check if slot is UL, and for phy test verify that it is in first TDD
* period, slot 8 (for K2=2, this is at slot 6 in the gNB; because of UE
* limitations). Note that if K2 or the TDD configuration is changed, below
* conditions might exclude each other and never be true */
const int sched_frame = frame + (slot + K2 >= num_slots_per_tdd);
const int sched_slot = (slot + K2) % num_slots_per_tdd;
if (is_xlsch_in_slot(ulsch_in_slot_bitmap, sched_slot)
&& (!get_softmodem_params()->phy_test || sched_slot == 8)) {
pusch_pdu->pdu_bit_map = PUSCH_PDU_BITMAP_PUSCH_DATA;
pusch_pdu->rnti = rnti;
pusch_pdu->handle = 0; //not yet used
nfapi_nr_ul_dci_request_t *UL_dci_req = &RC.nrmac[module_id]->UL_dci_req[0];
UL_dci_req->SFN = frame;
UL_dci_req->Slot = slot;
nfapi_nr_ul_dci_request_pdus_t *ul_dci_request_pdu;
pusch_pdu->bwp_size = NRRIV2BW(sched_ctrl->active_ubwp->bwp_Common->genericParameters.locationAndBandwidth,275);
pusch_pdu->bwp_start = NRRIV2PRBOFFSET(sched_ctrl->active_ubwp->bwp_Common->genericParameters.locationAndBandwidth,275);
pusch_pdu->subcarrier_spacing = sched_ctrl->active_ubwp->bwp_Common->genericParameters.subcarrierSpacing;
pusch_pdu->cyclic_prefix = 0;
uint16_t rnti = UE_info->rnti[UE_id];
NR_PUSCH_Config_t *pusch_Config = sched_ctrl->active_ubwp->bwp_Dedicated->pusch_Config->choice.setup;
NR_ServingCellConfigCommon_t *scc = RC.nrmac[0]->common_channels->ServingCellConfigCommon;
if (!pusch_Config->transformPrecoder)
pusch_pdu->transform_precoding = !scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder;
else
pusch_pdu->transform_precoding = *pusch_Config->transformPrecoder;
/* PUSCH in a later slot, but corresponding DCI now! */
nfapi_nr_ul_tti_request_t *future_ul_tti_req = &RC.nrmac[module_id]->UL_tti_req_ahead[0][sched_slot];
AssertFatal(future_ul_tti_req->SFN == sched_frame
&& future_ul_tti_req->Slot == sched_slot,
"%d.%d future UL_tti_req's frame.slot %d.%d does not match PUSCH %d.%d\n",
frame, slot,
future_ul_tti_req->SFN,
future_ul_tti_req->Slot,
sched_frame,
sched_slot);
nfapi_nr_ul_dci_request_t *ul_dci_req = &RC.nrmac[module_id]->UL_dci_req[0];
ul_dci_req->SFN = frame;
ul_dci_req->Slot = slot;
future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE;
future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].pdu_size = sizeof(nfapi_nr_pusch_pdu_t);
nfapi_nr_pusch_pdu_t *pusch_pdu = &future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].pusch_pdu;
memset(pusch_pdu, 0, sizeof(nfapi_nr_pusch_pdu_t));
future_ul_tti_req->n_pdus += 1;
if (pusch_Config->dataScramblingIdentityPUSCH)
pusch_pdu->data_scrambling_id = *pusch_Config->dataScramblingIdentityPUSCH;
else
pusch_pdu->data_scrambling_id = *scc->physCellId;
LOG_D(MAC, "%4d.%2d Scheduling UE specific PUSCH\n", frame, slot);
pusch_pdu->mcs_index = sched_ctrl->sched_pusch->mcs;
const int target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific;
if (pusch_pdu->transform_precoding)
pusch_pdu->mcs_table = get_pusch_mcs_table(pusch_Config->mcs_Table,
0,
dci_formats[0],
rnti_types[0],
target_ss,
false);
else
pusch_pdu->mcs_table =
get_pusch_mcs_table(pusch_Config->mcs_TableTransformPrecoder,
1,
dci_formats[0],
rnti_types[0],
target_ss,
false);
int dci_formats[2];
if (sched_ctrl->search_space->searchSpaceType->choice.ue_Specific->dci_Formats)
dci_formats[0] = NR_UL_DCI_FORMAT_0_1;
else
dci_formats[0] = NR_UL_DCI_FORMAT_0_0;
int rnti_types[2] = { NR_RNTI_C, 0 };
//Resource Allocation in time domain
const int startSymbolAndLength = tdaList->list.array[tda]->startSymbolAndLength;
int StartSymbolIndex, NrOfSymbols;
SLIV2SL(startSymbolAndLength,&StartSymbolIndex,&NrOfSymbols);
pusch_pdu->start_symbol_index = StartSymbolIndex;
pusch_pdu->nr_of_symbols = NrOfSymbols;
pusch_pdu->pdu_bit_map = PUSCH_PDU_BITMAP_PUSCH_DATA;
pusch_pdu->rnti = rnti;
pusch_pdu->handle = 0; //not yet used
pusch_pdu->bwp_size = NRRIV2BW(sched_ctrl->active_ubwp->bwp_Common->genericParameters.locationAndBandwidth,275);
pusch_pdu->bwp_start = NRRIV2PRBOFFSET(sched_ctrl->active_ubwp->bwp_Common->genericParameters.locationAndBandwidth,275);
pusch_pdu->subcarrier_spacing = sched_ctrl->active_ubwp->bwp_Common->genericParameters.subcarrierSpacing;
pusch_pdu->cyclic_prefix = 0;
NR_PUSCH_Config_t *pusch_Config = sched_ctrl->active_ubwp->bwp_Dedicated->pusch_Config->choice.setup;
if (!pusch_Config->transformPrecoder)
pusch_pdu->transform_precoding = !scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder;
else
pusch_pdu->transform_precoding = *pusch_Config->transformPrecoder;
if (pusch_Config->dataScramblingIdentityPUSCH)
pusch_pdu->data_scrambling_id = *pusch_Config->dataScramblingIdentityPUSCH;
else
pusch_pdu->data_scrambling_id = *scc->physCellId;
pusch_pdu->mcs_index = sched_ctrl->sched_pusch->mcs;
const int target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific;
if (pusch_pdu->transform_precoding)
pusch_pdu->mcs_table = get_pusch_mcs_table(pusch_Config->mcs_Table,
0,
dci_formats[0],
rnti_types[0],
target_ss,
false);
else
pusch_pdu->mcs_table =
get_pusch_mcs_table(pusch_Config->mcs_TableTransformPrecoder,
1,
dci_formats[0],
rnti_types[0],
target_ss,
false);
pusch_pdu->target_code_rate = nr_get_code_rate_ul(pusch_pdu->mcs_index,pusch_pdu->mcs_table);
pusch_pdu->qam_mod_order = nr_get_Qm_ul(pusch_pdu->mcs_index,pusch_pdu->mcs_table);
if (pusch_Config->tp_pi2BPSK) {
if (((pusch_pdu->mcs_table == 3) && (pusch_pdu->mcs_index < 2))
|| ((pusch_pdu->mcs_table == 4) && (pusch_pdu->mcs_index < 6))) {
pusch_pdu->target_code_rate = pusch_pdu->target_code_rate>>1;
pusch_pdu->qam_mod_order = pusch_pdu->qam_mod_order<<1;
}
pusch_pdu->target_code_rate = nr_get_code_rate_ul(pusch_pdu->mcs_index,pusch_pdu->mcs_table);
pusch_pdu->qam_mod_order = nr_get_Qm_ul(pusch_pdu->mcs_index,pusch_pdu->mcs_table);
if (pusch_Config->tp_pi2BPSK) {
if (((pusch_pdu->mcs_table == 3) && (pusch_pdu->mcs_index < 2))
|| ((pusch_pdu->mcs_table == 4) && (pusch_pdu->mcs_index < 6))) {
pusch_pdu->target_code_rate = pusch_pdu->target_code_rate>>1;
pusch_pdu->qam_mod_order = pusch_pdu->qam_mod_order<<1;
}
pusch_pdu->nrOfLayers = 1;
//Pusch Allocation in frequency domain [TS38.214, sec 6.1.2.2]
AssertFatal(pusch_Config->resourceAllocation == NR_PUSCH_Config__resourceAllocation_resourceAllocationType1,
"Only frequency resource allocation type 1 is currently supported\n");
pusch_pdu->resource_alloc = 1; //type 1
pusch_pdu->rb_start = sched_ctrl->sched_pusch->rbStart;
pusch_pdu->rb_size = sched_ctrl->sched_pusch->rbSize;
pusch_pdu->vrb_to_prb_mapping = 0;
if (pusch_Config->frequencyHopping==NULL)
pusch_pdu->frequency_hopping = 0;
else
pusch_pdu->frequency_hopping = 1;
// --------------------
// ------- DMRS -------
// --------------------
const int mapping_type = tdaList->list.array[tda]->mappingType;
NR_DMRS_UplinkConfig_t *NR_DMRS_UplinkConfig;
if (mapping_type == NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeA)
NR_DMRS_UplinkConfig = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA->choice.setup;
else
NR_DMRS_UplinkConfig = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup;
if (NR_DMRS_UplinkConfig->dmrs_Type == NULL)
pusch_pdu->dmrs_config_type = 0;
else
pusch_pdu->dmrs_config_type = 1;
pusch_pdu->scid = 0; // DMRS sequence initialization [TS38.211, sec 6.4.1.1.1]
if (pusch_pdu->transform_precoding) { // transform precoding disabled
long *scramblingid;
if (pusch_pdu->scid == 0)
scramblingid = NR_DMRS_UplinkConfig->transformPrecodingDisabled->scramblingID0;
else
scramblingid = NR_DMRS_UplinkConfig->transformPrecodingDisabled->scramblingID1;
if (scramblingid == NULL)
pusch_pdu->ul_dmrs_scrambling_id = *scc->physCellId;
else
pusch_pdu->ul_dmrs_scrambling_id = *scramblingid;
}
else {
pusch_pdu->ul_dmrs_scrambling_id = *scc->physCellId;
if (NR_DMRS_UplinkConfig->transformPrecodingEnabled->nPUSCH_Identity != NULL)
pusch_pdu->pusch_identity = *NR_DMRS_UplinkConfig->transformPrecodingEnabled->nPUSCH_Identity;
else
pusch_pdu->pusch_identity = *scc->physCellId;
}
pusch_dmrs_AdditionalPosition_t additional_pos;
if (NR_DMRS_UplinkConfig->dmrs_AdditionalPosition == NULL)
additional_pos = 2;
else {
if (*NR_DMRS_UplinkConfig->dmrs_AdditionalPosition == NR_DMRS_UplinkConfig__dmrs_AdditionalPosition_pos3)
additional_pos = 3;
else
additional_pos = *NR_DMRS_UplinkConfig->dmrs_AdditionalPosition;
}
pusch_maxLength_t pusch_maxLength;
if (NR_DMRS_UplinkConfig->maxLength == NULL)
pusch_maxLength = 1;
else
pusch_maxLength = 2;
uint16_t l_prime_mask = get_l_prime(pusch_pdu->nr_of_symbols, mapping_type, additional_pos, pusch_maxLength);
pusch_pdu->ul_dmrs_symb_pos = l_prime_mask << pusch_pdu->start_symbol_index;
pusch_pdu->num_dmrs_cdm_grps_no_data = 1;
pusch_pdu->dmrs_ports = 1;
// --------------------
// ------- PTRS -------
// --------------------
if (NR_DMRS_UplinkConfig->phaseTrackingRS != NULL) {
// TODO to be fixed from RRC config
uint8_t ptrs_mcs1 = 2; // higher layer parameter in PTRS-UplinkConfig
uint8_t ptrs_mcs2 = 4; // higher layer parameter in PTRS-UplinkConfig
uint8_t ptrs_mcs3 = 10; // higher layer parameter in PTRS-UplinkConfig
uint16_t n_rb0 = 25; // higher layer parameter in PTRS-UplinkConfig
uint16_t n_rb1 = 75; // higher layer parameter in PTRS-UplinkConfig
pusch_pdu->pusch_ptrs.ptrs_time_density = get_L_ptrs(ptrs_mcs1, ptrs_mcs2, ptrs_mcs3, pusch_pdu->mcs_index, pusch_pdu->mcs_table);
pusch_pdu->pusch_ptrs.ptrs_freq_density = get_K_ptrs(n_rb0, n_rb1, pusch_pdu->rb_size);
pusch_pdu->pusch_ptrs.ptrs_ports_list = (nfapi_nr_ptrs_ports_t *) malloc(2*sizeof(nfapi_nr_ptrs_ports_t));
pusch_pdu->pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset = 0;
pusch_pdu->pdu_bit_map |= PUSCH_PDU_BITMAP_PUSCH_PTRS; // enable PUSCH PTRS
}
else{
pusch_pdu->pdu_bit_map &= ~PUSCH_PDU_BITMAP_PUSCH_PTRS; // disable PUSCH PTRS
}
// --------------------------------------------------------------------------------------------------------------------------------------------
//Pusch Allocation in frequency domain [TS38.214, sec 6.1.2.2]
//Optional Data only included if indicated in pduBitmap
int8_t harq_id = select_ul_harq_pid(&UE_info->UE_sched_ctrl[UE_id]);
if (harq_id < 0) return;
NR_UE_ul_harq_t *cur_harq = &UE_info->UE_sched_ctrl[UE_id].ul_harq_processes[harq_id];
pusch_pdu->pusch_data.harq_process_id = harq_id;
pusch_pdu->pusch_data.new_data_indicator = cur_harq->ndi;
pusch_pdu->pusch_data.rv_index = nr_rv_round_map[cur_harq->round];
cur_harq->state = ACTIVE_SCHED;
cur_harq->last_tx_slot = sched_slot;
uint8_t num_dmrs_symb = 0;
for(int i = pusch_pdu->start_symbol_index; i < pusch_pdu->start_symbol_index + pusch_pdu->nr_of_symbols; i++)
num_dmrs_symb += (pusch_pdu->ul_dmrs_symb_pos >> i) & 1;
uint8_t N_PRB_DMRS;
if (pusch_pdu->dmrs_config_type == 0)
N_PRB_DMRS = pusch_pdu->num_dmrs_cdm_grps_no_data*6;
else
N_PRB_DMRS = pusch_pdu->num_dmrs_cdm_grps_no_data*4;
pusch_pdu->pusch_data.tb_size = nr_compute_tbs(pusch_pdu->qam_mod_order,
pusch_pdu->target_code_rate,
pusch_pdu->rb_size,
pusch_pdu->nr_of_symbols,
N_PRB_DMRS * num_dmrs_symb,
0, //nb_rb_oh
0,
pusch_pdu->nrOfLayers)>>3;
UE_info->mac_stats[UE_id].ulsch_rounds[cur_harq->round]++;
if (cur_harq->round == 0)
UE_info->mac_stats[UE_id].ulsch_total_bytes_scheduled += pusch_pdu->pusch_data.tb_size;
pusch_pdu->pusch_data.num_cb = 0; //CBG not supported
ul_dci_request_pdu = &UL_dci_req->ul_dci_pdu_list[UL_dci_req->numPdus];
memset((void*)ul_dci_request_pdu,0,sizeof(nfapi_nr_ul_dci_request_pdus_t));
ul_dci_request_pdu->PDUType = NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE;
ul_dci_request_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdcch_pdu));
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &ul_dci_request_pdu->pdcch_pdu.pdcch_pdu_rel15;
UL_dci_req->numPdus+=1;
LOG_D(MAC,"Configuring ULDCI/PDCCH in %d.%d\n", frame,slot);
nr_configure_pdcch(nr_mac,
pdcch_pdu_rel15,
rnti,
sched_ctrl->search_space,
sched_ctrl->coreset,
scc,
sched_ctrl->active_bwp,
sched_ctrl->aggregation_level,
sched_ctrl->cce_index);
dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET];
memset(dci_pdu_rel15, 0, sizeof(dci_pdu_rel15));
const int n_ubwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.count;
config_uldci(sched_ctrl->active_ubwp,pusch_pdu,pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types,tda,UE_info->UE_sched_ctrl[UE_id].tpc0,n_ubwp,sched_ctrl->active_bwp->bwp_Id);
fill_dci_pdu_rel15(scc,secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types,pusch_pdu->bwp_size,sched_ctrl->active_bwp->bwp_Id);
sched_ctrl->sched_pusch->rbSize = 0;
}
pusch_pdu->nrOfLayers = 1;
//Pusch Allocation in frequency domain [TS38.214, sec 6.1.2.2]
AssertFatal(pusch_Config->resourceAllocation == NR_PUSCH_Config__resourceAllocation_resourceAllocationType1,
"Only frequency resource allocation type 1 is currently supported\n");
pusch_pdu->resource_alloc = 1; //type 1
pusch_pdu->rb_start = sched_ctrl->sched_pusch->rbStart;
pusch_pdu->rb_size = sched_ctrl->sched_pusch->rbSize;
pusch_pdu->vrb_to_prb_mapping = 0;
if (pusch_Config->frequencyHopping==NULL)
pusch_pdu->frequency_hopping = 0;
else
pusch_pdu->frequency_hopping = 1;
// --------------------
// ------- DMRS -------
// --------------------
const int mapping_type = tdaList->list.array[tda]->mappingType;
NR_DMRS_UplinkConfig_t *NR_DMRS_UplinkConfig;
if (mapping_type == NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeA)
NR_DMRS_UplinkConfig = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA->choice.setup;
else
NR_DMRS_UplinkConfig = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup;
if (NR_DMRS_UplinkConfig->dmrs_Type == NULL)
pusch_pdu->dmrs_config_type = 0;
else
pusch_pdu->dmrs_config_type = 1;
pusch_pdu->scid = 0; // DMRS sequence initialization [TS38.211, sec 6.4.1.1.1]
if (pusch_pdu->transform_precoding) { // transform precoding disabled
long *scramblingid;
if (pusch_pdu->scid == 0)
scramblingid = NR_DMRS_UplinkConfig->transformPrecodingDisabled->scramblingID0;
else
scramblingid = NR_DMRS_UplinkConfig->transformPrecodingDisabled->scramblingID1;
if (scramblingid == NULL)
pusch_pdu->ul_dmrs_scrambling_id = *scc->physCellId;
else
pusch_pdu->ul_dmrs_scrambling_id = *scramblingid;
}
else {
pusch_pdu->ul_dmrs_scrambling_id = *scc->physCellId;
if (NR_DMRS_UplinkConfig->transformPrecodingEnabled->nPUSCH_Identity != NULL)
pusch_pdu->pusch_identity = *NR_DMRS_UplinkConfig->transformPrecodingEnabled->nPUSCH_Identity;
else
pusch_pdu->pusch_identity = *scc->physCellId;
}
pusch_dmrs_AdditionalPosition_t additional_pos;
if (NR_DMRS_UplinkConfig->dmrs_AdditionalPosition == NULL)
additional_pos = 2;
else {
if (*NR_DMRS_UplinkConfig->dmrs_AdditionalPosition == NR_DMRS_UplinkConfig__dmrs_AdditionalPosition_pos3)
additional_pos = 3;
else
additional_pos = *NR_DMRS_UplinkConfig->dmrs_AdditionalPosition;
}
pusch_maxLength_t pusch_maxLength;
if (NR_DMRS_UplinkConfig->maxLength == NULL)
pusch_maxLength = 1;
else
pusch_maxLength = 2;
uint16_t l_prime_mask = get_l_prime(pusch_pdu->nr_of_symbols, mapping_type, additional_pos, pusch_maxLength);
pusch_pdu->ul_dmrs_symb_pos = l_prime_mask << pusch_pdu->start_symbol_index;
pusch_pdu->num_dmrs_cdm_grps_no_data = 1;
pusch_pdu->dmrs_ports = 1;
// --------------------
// ------- PTRS -------
// --------------------
if (NR_DMRS_UplinkConfig->phaseTrackingRS != NULL) {
// TODO to be fixed from RRC config
uint8_t ptrs_mcs1 = 2; // higher layer parameter in PTRS-UplinkConfig
uint8_t ptrs_mcs2 = 4; // higher layer parameter in PTRS-UplinkConfig
uint8_t ptrs_mcs3 = 10; // higher layer parameter in PTRS-UplinkConfig
uint16_t n_rb0 = 25; // higher layer parameter in PTRS-UplinkConfig
uint16_t n_rb1 = 75; // higher layer parameter in PTRS-UplinkConfig
pusch_pdu->pusch_ptrs.ptrs_time_density = get_L_ptrs(ptrs_mcs1, ptrs_mcs2, ptrs_mcs3, pusch_pdu->mcs_index, pusch_pdu->mcs_table);
pusch_pdu->pusch_ptrs.ptrs_freq_density = get_K_ptrs(n_rb0, n_rb1, pusch_pdu->rb_size);
pusch_pdu->pusch_ptrs.ptrs_ports_list = (nfapi_nr_ptrs_ports_t *) malloc(2*sizeof(nfapi_nr_ptrs_ports_t));
pusch_pdu->pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset = 0;
pusch_pdu->pdu_bit_map |= PUSCH_PDU_BITMAP_PUSCH_PTRS; // enable PUSCH PTRS
}
else{
pusch_pdu->pdu_bit_map &= ~PUSCH_PDU_BITMAP_PUSCH_PTRS; // disable PUSCH PTRS
}
int8_t harq_id = select_ul_harq_pid(&UE_info->UE_sched_ctrl[UE_id]);
if (harq_id < 0) return;
NR_UE_ul_harq_t *cur_harq = &UE_info->UE_sched_ctrl[UE_id].ul_harq_processes[harq_id];
pusch_pdu->pusch_data.harq_process_id = harq_id;
pusch_pdu->pusch_data.new_data_indicator = cur_harq->ndi;
pusch_pdu->pusch_data.rv_index = nr_rv_round_map[cur_harq->round];
cur_harq->state = ACTIVE_SCHED;
cur_harq->last_tx_slot = sched_ctrl->sched_pusch->slot;
uint8_t num_dmrs_symb = 0;
for(int i = pusch_pdu->start_symbol_index; i < pusch_pdu->start_symbol_index + pusch_pdu->nr_of_symbols; i++)
num_dmrs_symb += (pusch_pdu->ul_dmrs_symb_pos >> i) & 1;
uint8_t N_PRB_DMRS;
if (pusch_pdu->dmrs_config_type == 0)
N_PRB_DMRS = pusch_pdu->num_dmrs_cdm_grps_no_data*6;
else
N_PRB_DMRS = pusch_pdu->num_dmrs_cdm_grps_no_data*4;
pusch_pdu->pusch_data.tb_size = nr_compute_tbs(pusch_pdu->qam_mod_order,
pusch_pdu->target_code_rate,
pusch_pdu->rb_size,
pusch_pdu->nr_of_symbols,
N_PRB_DMRS * num_dmrs_symb,
0, //nb_rb_oh
0,
pusch_pdu->nrOfLayers)>>3;
UE_info->mac_stats[UE_id].ulsch_rounds[cur_harq->round]++;
if (cur_harq->round == 0)
UE_info->mac_stats[UE_id].ulsch_total_bytes_scheduled += pusch_pdu->pusch_data.tb_size;
pusch_pdu->pusch_data.num_cb = 0; //CBG not supported
nfapi_nr_ul_dci_request_t *ul_dci_req = &RC.nrmac[module_id]->UL_dci_req[0];
ul_dci_req->SFN = frame;
ul_dci_req->Slot = slot;
nfapi_nr_ul_dci_request_pdus_t *ul_dci_request_pdu = &ul_dci_req->ul_dci_pdu_list[ul_dci_req->numPdus];
memset(ul_dci_request_pdu, 0, sizeof(nfapi_nr_ul_dci_request_pdus_t));
ul_dci_request_pdu->PDUType = NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE;
ul_dci_request_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdcch_pdu));
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &ul_dci_request_pdu->pdcch_pdu.pdcch_pdu_rel15;
ul_dci_req->numPdus += 1;
LOG_D(MAC,"Configuring ULDCI/PDCCH in %d.%d\n", frame,slot);
nr_configure_pdcch(RC.nrmac[0],
pdcch_pdu_rel15,
rnti,
sched_ctrl->search_space,
sched_ctrl->coreset,
scc,
sched_ctrl->active_bwp,
sched_ctrl->aggregation_level,
sched_ctrl->cce_index);
dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET];
memset(dci_pdu_rel15, 0, sizeof(dci_pdu_rel15));
const int n_ubwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.count;
config_uldci(sched_ctrl->active_ubwp,pusch_pdu,pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types,tda,UE_info->UE_sched_ctrl[UE_id].tpc0,n_ubwp,sched_ctrl->active_bwp->bwp_Id);
fill_dci_pdu_rel15(scc,secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types,pusch_pdu->bwp_size,sched_ctrl->active_bwp->bwp_Id);
sched_ctrl->sched_pusch->rbSize = 0;
}
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
+3
View File
@@ -295,6 +295,9 @@ typedef struct NR_sched_pusch {
uint16_t rbSize;
uint16_t rbStart;
// time-domain allocation for scheduled RBs
int time_domain_allocation;
/// MCS
uint8_t mcs;
} NR_sched_pusch_t;