diff --git a/common/utils/nr/nr_common.c b/common/utils/nr/nr_common.c index af31c83d6e..6add03c324 100644 --- a/common/utils/nr/nr_common.c +++ b/common/utils/nr/nr_common.c @@ -191,6 +191,19 @@ int PRBalloc_to_locationandbandwidth(int NPRB,int RBstart) { return(PRBalloc_to_locationandbandwidth0(NPRB,RBstart,275)); } +int cce_to_reg_interleaving(const int R, int k, int n_shift, const int C, int L, const int N_regs) { + + int f; // interleaving function + if(R==0) + f = k; + else { + int c = k/R; + int r = k%R; + f = (r*C + c + n_shift)%(N_regs/L); + } + return f; +} + void get_coreset_rballoc(uint8_t *FreqDomainResource,int *n_rb,int *rb_offset) { uint8_t count=0, start=0, start_set=0; diff --git a/common/utils/nr/nr_common.h b/common/utils/nr/nr_common.h index 5258ce8809..5f7f670ce9 100644 --- a/common/utils/nr/nr_common.h +++ b/common/utils/nr/nr_common.h @@ -57,7 +57,7 @@ static inline int get_num_dmrs(uint16_t dmrs_mask ) { return(num_dmrs); } - +int cce_to_reg_interleaving(const int R, int k, int n_shift, const int C, int L, const int N_regs); int get_SLIV(uint8_t S, uint8_t L); void get_coreset_rballoc(uint8_t *FreqDomainResource,int *n_rb,int *rb_offset); uint16_t config_bandwidth(int mu, int nb_rb, int nr_band); diff --git a/openair1/PHY/INIT/nr_init_ru.c b/openair1/PHY/INIT/nr_init_ru.c index b1a01fb3dc..c96aeab432 100644 --- a/openair1/PHY/INIT/nr_init_ru.c +++ b/openair1/PHY/INIT/nr_init_ru.c @@ -60,7 +60,7 @@ int nr_phy_init_RU(RU_t *ru) { for (i=0; inb_tx; i++) { // Allocate 10 subframes of I/Q TX signal data (time) if not - ru->common.txdata[i] = (int32_t*)malloc16_clear( ru->sf_extension + (fp->samples_per_frame*sizeof(int32_t) )); + ru->common.txdata[i] = (int32_t*)malloc16_clear((ru->sf_extension +fp->samples_per_frame) *sizeof(int32_t)); LOG_I(PHY,"[INIT] common.txdata[%d] = %p (%lu bytes,sf_extension %d)\n",i,ru->common.txdata[i], (ru->sf_extension + fp->samples_per_frame)*sizeof(int32_t),ru->sf_extension); ru->common.txdata[i] = &ru->common.txdata[i][ru->sf_extension]; diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.c b/openair1/PHY/NR_TRANSPORT/nr_dci.c index ffbe850fdd..d70d991e7b 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.c @@ -73,7 +73,6 @@ void nr_generate_dci(PHY_VARS_gNB *gNB, NR_DL_FRAME_PARMS *frame_parms, int slot) { - int16_t mod_dmrs[NR_MAX_CSET_DURATION][NR_MAX_PDCCH_DMRS_LENGTH>>1] __attribute__((aligned(16))); // 3 for the max coreset duration uint16_t cset_start_sc; uint8_t cset_start_symb, cset_nsymb; int k,l,k_prime,dci_idx, dmrs_idx; @@ -82,13 +81,14 @@ void nr_generate_dci(PHY_VARS_gNB *gNB, int rb_offset; int n_rb; - // compute rb_offset and n_prb based on frequency allocation nr_cce_t cce_list[MAX_DCI_CORESET][NR_MAX_PDCCH_AGG_LEVEL]; - nr_fill_cce_list(cce_list,0,pdcch_pdu_rel15); + nr_fill_cce_list(cce_list, pdcch_pdu_rel15); get_coreset_rballoc(pdcch_pdu_rel15->FreqDomainResource,&n_rb,&rb_offset); cset_start_sc = frame_parms->first_carrier_offset + (pdcch_pdu_rel15->BWPStart + rb_offset) * NR_NB_SC_PER_RB; + int16_t mod_dmrs[pdcch_pdu_rel15->StartSymbolIndex+pdcch_pdu_rel15->DurationSymbols][(n_rb+rb_offset)*6] __attribute__((aligned(16))); // 3 for the max coreset duration + for (int d=0;dnumDlDci;d++) { /*The coreset is initialised * in frequency: the first subcarrier is obtained by adding the first CRB overlapping the SSB and the rb_offset for coreset 0 @@ -118,7 +118,7 @@ void nr_generate_dci(PHY_VARS_gNB *gNB, /// DMRS QPSK modulation for (int symb=cset_start_symb; symbDurationSymbols; symb++) { - + nr_modulation(gold_pdcch_dmrs[symb], dmrs_length, DMRS_MOD_ORDER, mod_dmrs[symb]); //Qm = 2 as DMRS is QPSK modulated #ifdef DEBUG_PDCCH_DMRS @@ -178,8 +178,10 @@ void nr_generate_dci(PHY_VARS_gNB *gNB, // Get cce_list indices by reg_idx in ascending order int reg_list_index = 0; + int N_regs = n_rb*pdcch_pdu_rel15->DurationSymbols; // nb of REGs per coreset + int N_cces = N_regs / NR_NB_REG_PER_CCE; // nb of cces in coreset int reg_list_order[NR_MAX_PDCCH_AGG_LEVEL] = {}; - for (int p = 0; p < NR_MAX_PDCCH_AGG_LEVEL; p++) { + for (int p = 0; p < N_cces; p++) { for(int p2 = 0; p2 < dci_pdu->AggregationLevel; p2++) { if(cce_list[d][p2].reg_list[0].reg_idx == p * NR_NB_REG_PER_CCE) { reg_list_order[reg_list_index] = p2; @@ -191,24 +193,25 @@ void nr_generate_dci(PHY_VARS_gNB *gNB, /*Mapping the encoded DCI along with the DMRS */ for(int symbol_idx = 0; symbol_idx < pdcch_pdu_rel15->DurationSymbols; symbol_idx++) { - for (int cce_count = 0; cce_count < dci_pdu->AggregationLevel; cce_count+=pdcch_pdu_rel15->DurationSymbols) { + for (int cce_count = 0; cce_count < dci_pdu->AggregationLevel; cce_count++) { int8_t cce_idx = reg_list_order[cce_count]; - for (int reg_in_cce_idx = 0; reg_in_cce_idx < NR_NB_REG_PER_CCE; reg_in_cce_idx++) { + for (int reg_in_cce_idx = 0; reg_in_cce_idx < NR_NB_REG_PER_CCE; reg_in_cce_idx+=pdcch_pdu_rel15->DurationSymbols) { k = cset_start_sc + cce_list[d][cce_idx].reg_list[reg_in_cce_idx].start_sc_idx; - + LOG_D(PHY,"CCE %d REG %d k %d\n",cce_idx,reg_in_cce_idx+symbol_idx,k); if (k >= frame_parms->ofdm_symbol_size) k -= frame_parms->ofdm_symbol_size; l = cset_start_symb + symbol_idx; // dmrs index depends on reference point for k according to 38.211 7.4.1.3.2 + int eff_reg_idx = cce_list[d][cce_idx].reg_list[reg_in_cce_idx].reg_idx/pdcch_pdu_rel15->DurationSymbols; if (pdcch_pdu_rel15->CoreSetType == NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG) - dmrs_idx = (cce_list[d][cce_idx].reg_list[reg_in_cce_idx].reg_idx) * 3; + dmrs_idx = eff_reg_idx * 3; else - dmrs_idx = (cce_list[d][cce_idx].reg_list[reg_in_cce_idx].reg_idx + rb_offset) * 3; + dmrs_idx = (eff_reg_idx + rb_offset) * 3; k_prime = 0; diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.h b/openair1/PHY/NR_TRANSPORT/nr_dci.h index 490a8b5286..0bf6932bb5 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.h +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.h @@ -55,6 +55,6 @@ void nr_fill_ul_dci(PHY_VARS_gNB *gNB, int slot, nfapi_nr_ul_dci_request_pdus_t *pdcch_pdu); -void nr_fill_cce_list(nr_cce_t cce_list[MAX_DCI_CORESET][NR_MAX_PDCCH_AGG_LEVEL], uint8_t m,nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15); +void nr_fill_cce_list(nr_cce_t cce_list[MAX_DCI_CORESET][NR_MAX_PDCCH_AGG_LEVEL], nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15); #endif //__PHY_NR_TRANSPORT_DCI__H diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c index 8d5eb4a660..e9d3010ce7 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c @@ -37,89 +37,8 @@ #include "nr_dlsch.h" -/* - Original version to keep code for Y that needs to be moved to MAC -void nr_fill_cce_list(PHY_VARS_gNB *gNB, uint16_t n_shift, uint8_t m) { - - nr_cce_t* cce; - nr_reg_t* reg; - nfapi_nr_dl_config_pdcch_pdu_rel15_t* pdcch_pdu = gNB->pdcch_pdu.pdcch; - - uint8_t L = dci_alloc->L; - uint8_t bsize = pdcch_params->reg_bundle_size; - uint8_t R = pdcch_params->interleaver_size; - uint16_t N_reg = pdcch_params->n_rb * pdcch_params->n_symb; - uint16_t Y, N_cce, M_s_max, n_CI=0, tmp, C=0; - uint16_t n_RNTI = (pdcch_params->search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC)? pdcch_params->rnti:0; - uint32_t A[3]={39827,39829,39839}; - - if (pdcch_params->config_type == NFAPI_NR_CSET_CONFIG_MIB_SIB1) - AssertFatal(L>=4, "Invalid aggregation level for SIB1 configured PDCCH %d\n", L); - - N_cce = N_reg / NR_NB_REG_PER_CCE; - //Max number of candidates per aggregation level -- SIB1 configured search space only - M_s_max = (L==4)?4:(L==8)?2:1; - - if (pdcch_params->search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_COMMON) - Y = 0; - else { //NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC - Y = (A[0]*n_RNTI)%65537; // Candidate 0, antenna port 0 - } - - if (pdcch_params->cr_mapping_type == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) { - uint16_t assertFatalCond = (N_reg%(bsize*R)); - AssertFatal(assertFatalCond == 0,"CCE to REG interleaving: Invalid configuration leading to non integer C (N_reg %us, bsize %d R %d)\n",N_reg, bsize, R); - C = N_reg/(bsize*R); - } - - tmp = L * (( Y + (m*N_cce)/(L*M_s_max) + n_CI ) % CEILIDIV(N_cce,L)); - - LOG_D(PHY, "CCE list generation for candidate %d: bundle size %d ilv size %d tmp %d\n", m, bsize, R, tmp); - for (uint8_t cce_idx=0; cce_idxcce_list[cce_idx]; - cce->cce_idx = tmp + cce_idx; - LOG_D(PHY, "cce_idx %d\n", cce->cce_idx); - - if (pdcch_params->cr_mapping_type == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) { - LOG_D(PHY, "Interleaved CCE to REG mapping\n"); - uint8_t j = cce->cce_idx, j_prime; - uint8_t r,c,idx; - - for (uint8_t bundle_idx=0; bundle_idxreg_list[reg_idx]; - reg->reg_idx = bsize*idx + reg_idx; - reg->start_sc_idx = (reg->reg_idx/pdcch_params->n_symb) * NR_NB_SC_PER_RB; - reg->symb_idx = reg->reg_idx % pdcch_params->n_symb; - LOG_D(PHY, "reg %d symbol %d start subcarrier %d\n", reg->reg_idx, reg->symb_idx, reg->start_sc_idx); - } - } - } - else { // NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED - LOG_D(PHY, "Non interleaved CCE to REG mapping\n"); - for (uint8_t reg_idx=0; reg_idxreg_list[reg_idx]; - reg->reg_idx = cce->cce_idx*NR_NB_REG_PER_CCE + reg_idx; - reg->start_sc_idx = (reg->reg_idx/pdcch_params->n_symb) * NR_NB_SC_PER_RB; - reg->symb_idx = reg->reg_idx % pdcch_params->n_symb; - LOG_D(PHY, "reg %d symbol %d start subcarrier %d\n", reg->reg_idx, reg->symb_idx, reg->start_sc_idx); - } - - } - - } -} - -*/ - -void nr_fill_cce_list(nr_cce_t cce_list[MAX_DCI_CORESET][NR_MAX_PDCCH_AGG_LEVEL], uint8_t m, nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15) { +void nr_fill_cce_list(nr_cce_t cce_list[MAX_DCI_CORESET][NR_MAX_PDCCH_AGG_LEVEL], nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15) { nr_cce_t* cce; nr_reg_t* reg; @@ -128,71 +47,51 @@ void nr_fill_cce_list(nr_cce_t cce_list[MAX_DCI_CORESET][NR_MAX_PDCCH_AGG_LEVEL] int R = pdcch_pdu_rel15->InterleaverSize; int n_shift = pdcch_pdu_rel15->ShiftIndex; - //Max number of candidates per aggregation level -- SIB1 configured search space only - int n_rb,rb_offset; get_coreset_rballoc(pdcch_pdu_rel15->FreqDomainResource,&n_rb,&rb_offset); - - int N_reg = n_rb; - int C=-1; - - AssertFatal(N_reg > 0,"N_reg cannot be 0\n"); - for (int d=0;dnumDlDci;d++) { + int L = pdcch_pdu_rel15->dci_pdu[d].AggregationLevel; + int dur = pdcch_pdu_rel15->DurationSymbols; + int N_regs = n_rb*dur; // nb of REGs per coreset + AssertFatal(N_regs > 0,"N_reg cannot be 0\n"); if (pdcch_pdu_rel15->CoreSetType == NFAPI_NR_CSET_CONFIG_MIB_SIB1) AssertFatal(L>=4, "Invalid aggregation level for SIB1 configured PDCCH %d\n", L); - + + int C = 0; + if (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) { - uint16_t assertFatalCond = (N_reg%(bsize*R)); - AssertFatal(assertFatalCond == 0,"CCE to REG interleaving: Invalid configuration leading to non integer C (N_reg %us, bsize %d R %d)\n",N_reg, bsize, R); - C = N_reg/(bsize*R); + uint16_t assertFatalCond = (N_regs%(bsize*R)); + AssertFatal(assertFatalCond == 0,"CCE to REG interleaving: Invalid configuration leading to non integer C (N_reg %us, bsize %d R %d)\n",N_regs, bsize, R); + C = N_regs/(bsize*R); } - - if (pdcch_pdu_rel15->dci_pdu[d].RNTI != 0xFFFF) LOG_D(PHY, "CCE list generation for candidate %d: bundle size %d ilv size %d CceIndex %d\n", m, bsize, R, pdcch_pdu_rel15->dci_pdu[d].CceIndex); + + if (pdcch_pdu_rel15->dci_pdu[d].RNTI != 0xFFFF) + LOG_D(PHY, "CCE list generation for candidate %d: bundle size %d ilv size %d CceIndex %d\n", d, bsize, R, pdcch_pdu_rel15->dci_pdu[d].CceIndex); + for (uint8_t cce_idx=0; cce_idxcce_idx = pdcch_pdu_rel15->dci_pdu[d].CceIndex + cce_idx; LOG_D(PHY, "cce_idx %d\n", cce->cce_idx); - - if (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) { - LOG_D(PHY, "Interleaved CCE to REG mapping\n"); - uint8_t j = cce->cce_idx, j_prime; - uint8_t r,c,idx; - - for (uint8_t bundle_idx=0; bundle_idxreg_list[reg_idx]; - reg->reg_idx = bsize*idx + reg_idx; - reg->start_sc_idx = reg->reg_idx * NR_NB_SC_PER_RB; - reg->symb_idx = 0; - LOG_D(PHY, "reg %d symbol %d start subcarrier %d\n", reg->reg_idx, reg->symb_idx, reg->start_sc_idx); - } - } - } - else { // NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED - LOG_D(PHY, "Non interleaved CCE to REG mapping\n"); - for (uint8_t reg_idx=0; reg_idxcce_idx; + for (int k=6*j/bsize; k<(6*j/bsize+6/bsize); k++) { // loop over REG bundles + + int f = cce_to_reg_interleaving(R, k, n_shift, C, bsize, N_regs); + + for (uint8_t reg_idx=0; reg_idxreg_list[reg_idx]; - reg->reg_idx = cce->cce_idx*NR_NB_REG_PER_CCE + reg_idx; - reg->start_sc_idx = reg->reg_idx * NR_NB_SC_PER_RB; - reg->symb_idx = 0; + reg->reg_idx = bsize*f + reg_idx; + reg->start_sc_idx = (reg->reg_idx/dur) * NR_NB_SC_PER_RB; + reg->symb_idx = reg_idx%dur; LOG_D(PHY, "reg %d symbol %d start subcarrier %d\n", reg->reg_idx, reg->symb_idx, reg->start_sc_idx); } - } - } } } diff --git a/openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c b/openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c index 037851be0c..1141ef8140 100644 --- a/openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c +++ b/openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c @@ -683,7 +683,7 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue, int ch_offset,symbol_offset; uint8_t nushift; - int **dl_ch_estimates =ue->pdsch_vars[proc->thread_id][gNB_id]->dl_ch_estimates; + int **dl_ch_estimates = ue->pdsch_vars[proc->thread_id][gNB_id]->dl_ch_estimates; int **rxdataF=ue->common_vars.common_vars_rx_data_per_thread[proc->thread_id].rxdataF; ch_offset = ue->frame_parms.ofdm_symbol_size*symbol; diff --git a/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c b/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c index 336d388d40..792f0424b1 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c +++ b/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c @@ -142,7 +142,8 @@ static void nr_pdcch_demapping_deinterleaving(uint32_t *llr, int B_rb = reg_bundle_size_L/coreset_time_dur; // nb of RBs occupied by each REG bundle int num_bundles_per_cce = 6/reg_bundle_size_L; - int max_bundles = NR_MAX_PDCCH_AGG_LEVEL*num_bundles_per_cce; + int n_cce = N_regs/6; + int max_bundles = n_cce*num_bundles_per_cce; int f_bundle_j_list[max_bundles]; // for each bundle @@ -359,10 +360,7 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF, * According to this equations, DM-RS PDCCH are mapped on k where k%12==1 || k%12==5 || k%12==9 * */ - // the bitmap coreset_frq_domain contains 45 bits -#define CORESET_FREQ_DOMAIN_BITMAP_SIZE 45 - // each bit is associated to 6 RBs -#define BIT_TO_NBR_RB_CORESET_FREQ_DOMAIN 6 + #define NBR_RE_PER_RB_WITH_DMRS 12 // after removing the 3 DMRS RE, the RB contains 9 RE with PDCCH #define NBR_RE_PER_RB_WITHOUT_DMRS 9 diff --git a/openair1/SIMULATION/NR_PHY/dlsim.c b/openair1/SIMULATION/NR_PHY/dlsim.c index 99236c9a43..51499c0f36 100644 --- a/openair1/SIMULATION/NR_PHY/dlsim.c +++ b/openair1/SIMULATION/NR_PHY/dlsim.c @@ -263,26 +263,35 @@ void update_ptrs_config(NR_CellGroupConfig_t *secondaryCellGroup, uint16_t *rbSi void update_dmrs_config(NR_CellGroupConfig_t *scg, int8_t* dmrs_arg); extern void fix_scd(NR_ServingCellConfig_t *scd);// forward declaration -/* specific dlsim DL preprocessor: uses rbStart/rbSize/mcs/nrOfLayers from command line of - dlsim, does not search for CCE/PUCCH occasion but simply sets to 0 */ +/* specific dlsim DL preprocessor: uses rbStart/rbSize/mcs/nrOfLayers from command line of dlsim */ int g_mcsIndex = -1, g_mcsTableIdx = 0, g_rbStart = -1, g_rbSize = -1, g_nrOfLayers = 1; void nr_dlsim_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t slot) { + NR_UE_info_t *UE_info = RC.nrmac[module_id]->UE_info.list[0]; AssertFatal(RC.nrmac[module_id]->UE_info.list[1]==NULL, "can have only a single UE\n"); NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl; NR_ServingCellConfigCommon_t *scc = RC.nrmac[0]->common_channels[0].ServingCellConfigCommon; - /* manually set free CCE to 0 */ const int target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific; sched_ctrl->search_space = get_searchspace(NULL, scc, sched_ctrl->active_bwp ? sched_ctrl->active_bwp->bwp_Dedicated : NULL, target_ss); uint8_t nr_of_candidates; find_aggregation_candidates(&sched_ctrl->aggregation_level, &nr_of_candidates, sched_ctrl->search_space,4); + sched_ctrl->coreset = get_coreset(RC.nrmac[module_id], scc, sched_ctrl->active_bwp->bwp_Dedicated, sched_ctrl->search_space, target_ss); - sched_ctrl->cce_index = 0; + uint32_t Y = get_Y(sched_ctrl->search_space, slot, UE_info->rnti); + int CCEIndex = find_pdcch_candidate(RC.nrmac[module_id], + /* CC_id = */ 0, + sched_ctrl->aggregation_level, + nr_of_candidates, + &sched_ctrl->sched_pdcch, + sched_ctrl->coreset, + Y); + AssertFatal(CCEIndex>=0, "%4d.%2d could not find CCE for DL DCI UE %d/RNTI %04x\n", frame, slot, 0, UE_info->rnti); + sched_ctrl->cce_index = CCEIndex; NR_pdsch_semi_static_t *ps = &sched_ctrl->pdsch_semi_static; @@ -1103,14 +1112,9 @@ int main(int argc, char **argv) while ((roundack==0)) { clear_nr_nfapi_information(RC.nrmac[0], 0, frame, slot); - UE_info->UE_sched_ctrl.harq_processes[harq_pid].ndi = !(trial&1); - - UE_info->UE_sched_ctrl.harq_processes[harq_pid].round = round; - for (int i=0; ipdcch_cand[i] = 0; - + if (css_flag == 0) { nr_schedule_ue_spec(0, frame, slot); } else { diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c index bb80ff2a3c..5d6f9a2f2e 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c @@ -3498,6 +3498,22 @@ void csi_period_offset(NR_CSI_ReportConfig_t *csirep, } } +uint32_t get_Y(NR_SearchSpace_t *ss, int slot, rnti_t rnti) { + + if(ss->searchSpaceType->present == NR_SearchSpace__searchSpaceType_PR_common) + return 0; + + const int cid = *ss->controlResourceSetId%3; + const uint32_t A[3] = {39827, 39829, 39839}; + const uint32_t D = 65537; + uint32_t Y; + + Y = (A[cid] * rnti) % D; + for (int s = 0; s < slot; s++) + Y = (A[cid] * Y) % D; + + return Y; +} void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config, frame_t frameP, diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h index a658c990bc..6caddcff78 100644 --- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h +++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h @@ -37,6 +37,8 @@ #include "nr_mac.h" #include "openair1/PHY/impl_defs_nr.h" +uint32_t get_Y(NR_SearchSpace_t *ss, int slot, rnti_t rnti); + uint64_t from_nrarfcn(int nr_bandP, uint8_t scs_index, uint32_t dl_nrarfcn); uint32_t to_nrarfcn(int nr_bandP, uint64_t dl_CarrierFreq, uint8_t scs_index, uint32_t bw); diff --git a/openair2/LAYER2/NR_MAC_UE/mac_defs.h b/openair2/LAYER2/NR_MAC_UE/mac_defs.h index 335f3be907..800e042464 100644 --- a/openair2/LAYER2/NR_MAC_UE/mac_defs.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_defs.h @@ -558,7 +558,6 @@ typedef struct ssb_list_info { } ssb_list_info_t; void config_dci_pdu(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15, fapi_nr_dl_config_request_t *dl_config, int rnti_type, int ss_id); -void fill_dci_search_candidates(NR_SearchSpace_t *ss,fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15); /*@}*/ #endif /*__LAYER2_MAC_DEFS_H__ */ diff --git a/openair2/LAYER2/NR_MAC_UE/mac_proto.h b/openair2/LAYER2/NR_MAC_UE/mac_proto.h index 8ee0a087ec..caa4af4144 100644 --- a/openair2/LAYER2/NR_MAC_UE/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_UE/mac_proto.h @@ -243,10 +243,7 @@ int nr_write_ce_ulsch_pdu(uint8_t *mac_ce, uint16_t *crnti, NR_BSR_SHORT *truncated_bsr, NR_BSR_SHORT *short_bsr, - NR_BSR_LONG *long_bsr - ); - -void fill_dci_search_candidates(NR_SearchSpace_t *ss,fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15); + NR_BSR_LONG *long_bsr); void config_dci_pdu(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15, fapi_nr_dl_config_request_t *dl_config, int rnti_type, int ss_id); @@ -448,7 +445,7 @@ int8_t nr_ue_process_dci_freq_dom_resource_assignment(nfapi_nr_ue_pusch_pdu_t *p uint16_t riv); void config_dci_pdu(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15, fapi_nr_dl_config_request_t *dl_config, int rnti_type, int ss_id); -void fill_dci_search_candidates(NR_SearchSpace_t *ss,fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15); +void fill_dci_search_candidates(NR_SearchSpace_t *ss,fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15, int slot, int rnti); void build_ssb_to_ro_map(NR_UE_MAC_INST_t *mac); diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c index 0dfbbf2be3..9b618cdbfb 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c @@ -49,7 +49,9 @@ //#define DEBUG_DCI -void fill_dci_search_candidates(NR_SearchSpace_t *ss,fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15) { +void fill_dci_search_candidates(NR_SearchSpace_t *ss, + fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15, + int slot, int rnti) { LOG_D(NR_MAC,"Filling search candidates for DCI\n"); @@ -57,6 +59,9 @@ void fill_dci_search_candidates(NR_SearchSpace_t *ss,fapi_nr_dl_config_dci_dl_pd uint8_t number_of_candidates=0; rel15->number_of_candidates=0; int i=0; + uint32_t Y = 0; + if (slot >= 0) + Y = get_Y(ss, slot, rnti); for (int maxL=16;maxL>0;maxL>>=1) { find_aggregation_candidates(&aggregation, &number_of_candidates, @@ -65,8 +70,17 @@ void fill_dci_search_candidates(NR_SearchSpace_t *ss,fapi_nr_dl_config_dci_dl_pd if (number_of_candidates>0) { LOG_D(NR_MAC,"L %d, number of candidates %d, aggregation %d\n",maxL,number_of_candidates,aggregation); rel15->number_of_candidates += number_of_candidates; + int N_cce_sym = 0; // nb of rbs of coreset per symbol + for (int i=0;i<6;i++) { + for (int t=0;t<8;t++) { + N_cce_sym+=((rel15->coreset.frequency_domain_resource[i]>>t)&1); + } + } + int N_cces = N_cce_sym*rel15->coreset.duration; for (int j=0; jCCE[i] = j*aggregation; + int first_cce = aggregation * (( Y + CEILIDIV((j*N_cces),(aggregation*number_of_candidates)) + 0 ) % CEILIDIV(N_cces,aggregation)); + LOG_D(NR_MAC,"Candidate %d of %d first_cce %d (L %d N_cces %d Y %d)\n", j, number_of_candidates, first_cce, aggregation, N_cces, Y); + rel15->CCE[i] = first_cce; rel15->L[i] = aggregation; } } @@ -305,14 +319,14 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl } else { config_dci_pdu(mac, rel15, dl_config, NR_RNTI_RA, ss_id); } - fill_dci_search_candidates(ss, rel15); + fill_dci_search_candidates(ss, rel15, -1, -1); break; case WAIT_CONTENTION_RESOLUTION: LOG_D(NR_MAC, "[DCI_CONFIG] Configure monitoring of PDCCH candidates in Type1-PDCCH common random access search space (RA-Msg4)\n"); rel15->num_dci_options = 1; rel15->dci_format_options[0] = NR_DL_DCI_FORMAT_1_0; config_dci_pdu(mac, rel15, dl_config, NR_RNTI_TC, -1); - fill_dci_search_candidates(ss, rel15); + fill_dci_search_candidates(ss, rel15, -1, -1); break; default: break; @@ -384,7 +398,7 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl rel15->dci_format_options[0] = NR_DL_DCI_FORMAT_1_1; rel15->dci_format_options[1] = NR_UL_DCI_FORMAT_0_1; config_dci_pdu(mac, rel15, dl_config, NR_RNTI_C, ss_id); - fill_dci_search_candidates(ss, rel15); + fill_dci_search_candidates(ss, rel15, slot, mac->crnti); //#ifdef DEBUG_DCI LOG_D(NR_MAC, "[DCI_CONFIG] ss %d ue_Specific %p searchSpaceType->present %d dci_Formats %d\n", @@ -420,19 +434,4 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl AssertFatal(1==0,"Handle DCI searching when CellGroup without dedicated BWP\n"); } - // Search space 0, CORESET ID 0 - if (!get_softmodem_params()->nsa) { - NR_SearchSpace_t *ss0 = mac->search_space_zero; - if(ss0) { - fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15 = &dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15; - rel15->num_dci_options = 1; - rel15->dci_format_options[0] = NR_DL_DCI_FORMAT_1_0; - config_dci_pdu(mac, - rel15, - dl_config, - ((frame%2==mac->type0_PDCCH_CSS_config.sfn_c)&&(slot==mac->type0_PDCCH_CSS_config.n_0)) ? NR_RNTI_SI : NR_RNTI_C, - -1); - fill_dci_search_candidates(ss0, rel15); - } - } } diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_scheduler.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_scheduler.c index e7e41a5a75..140fde407f 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_scheduler.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_scheduler.c @@ -1099,7 +1099,7 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in if (mac->ra.ra_state == WAIT_CONTENTION_RESOLUTION) rel15->dci_format_options[1] = NR_UL_DCI_FORMAT_0_0; // msg3 retransmission config_dci_pdu(mac, rel15, dl_config, mac->ra.ra_state == WAIT_RAR ? NR_RNTI_RA : NR_RNTI_TC , mac->ra.ss->searchSpaceId); - fill_dci_search_candidates(mac->ra.ss, rel15); + fill_dci_search_candidates(mac->ra.ss, rel15, -1 , -1); dl_config->number_pdus = 1; LOG_D(MAC,"mac->cg %p: Calling fill_scheduled_response rnti %x, type0_pdcch, num_pdus %d\n",mac->cg,rel15->rnti,dl_config->number_pdus); fill_scheduled_response(&scheduled_response, dl_config, NULL, NULL, mod_id, cc_id, rx_frame, rx_slot, dl_info->thread_id, dl_info->phy_data); @@ -2789,7 +2789,7 @@ void nr_ue_sib1_scheduler(module_id_t module_idP, rel15->num_dci_options = 1; rel15->dci_format_options[0] = NR_DL_DCI_FORMAT_1_0; config_dci_pdu(mac, rel15, dl_config, NR_RNTI_SI, -1); - fill_dci_search_candidates(mac->search_space_zero, rel15); + fill_dci_search_candidates(mac->search_space_zero, rel15, -1, -1); if(mac->type0_PDCCH_CSS_config.type0_pdcch_ss_mux_pattern == 1){ // same frame as ssb diff --git a/openair2/LAYER2/NR_MAC_gNB/config.c b/openair2/LAYER2/NR_MAC_gNB/config.c index 19845c708b..f775938868 100644 --- a/openair2/LAYER2/NR_MAC_gNB/config.c +++ b/openair2/LAYER2/NR_MAC_gNB/config.c @@ -646,13 +646,11 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP, ra->msg3_dcch_dtch = false; LOG_I(NR_MAC,"Added new RA process for UE RNTI %04x with initial CellGroup\n", rnti); } else { // CellGroup has been updated - NR_ServingCellConfigCommon_t *scc = RC.nrmac[Mod_idP]->common_channels[0].ServingCellConfigCommon; NR_UE_info_t * UE = find_nr_UE(&RC.nrmac[Mod_idP]->UE_info,rnti); if (!UE) { LOG_E(NR_MAC, "Can't find UE %04x\n", rnti); return -1; } - int target_ss; UE->CellGroup = CellGroup; LOG_I(NR_MAC,"Modified rnti %04x with CellGroup\n",rnti); @@ -664,30 +662,7 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP, // add all available DL HARQ processes for this UE in SA create_dl_harq_list(sched_ctrl, pdsch); } - // update coreset/searchspace - void *bwpd = NULL; - NR_BWP_t *genericParameters = NULL; - target_ss = NR_SearchSpace__searchSpaceType_PR_common; - if ((sched_ctrl->active_bwp)) { - target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific; - bwpd = (void*)sched_ctrl->active_bwp->bwp_Dedicated; - genericParameters = &sched_ctrl->active_bwp->bwp_Common->genericParameters; - } - else if (CellGroup->spCellConfig && - CellGroup->spCellConfig->spCellConfigDedicated && - (CellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP)) { - target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific; - bwpd = (void*)CellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP; - genericParameters = &scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters; - } - sched_ctrl->search_space = get_searchspace(sib1 ? sib1->message.choice.c1->choice.systemInformationBlockType1 : NULL, scc, bwpd, target_ss); - sched_ctrl->coreset = get_coreset(RC.nrmac[Mod_idP], scc, bwpd, sched_ctrl->search_space, target_ss); - sched_ctrl->sched_pdcch = set_pdcch_structure(RC.nrmac[Mod_idP], - sched_ctrl->search_space, - sched_ctrl->coreset, - scc, - genericParameters, - RC.nrmac[Mod_idP]->type0_PDCCH_CSS_config); + sched_ctrl->maxL = 2; if (CellGroup->spCellConfig && diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index d56fc0ae2a..385cf5af16 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -144,8 +144,6 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, nr_rrc_trigger(&ctxt, 0 /*CC_id*/, frame, slot >> *scc->ssbSubcarrierSpacing); } - for (int i=0; ipdcch_cand[i] = 0; for (int CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { //mbsfn_status[CC_id] = 0; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c index 4b71b40662..3b5c9ffad4 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c @@ -489,8 +489,8 @@ bool allocate_dl_retransmission(module_id_t module_id, } /* Find a free CCE */ - const int cid = sched_ctrl->coreset->controlResourceSetId; - const uint16_t Y = get_Y(cid%3, slot, UE->rnti); + + const uint32_t Y = get_Y(sched_ctrl->search_space, slot, UE->rnti); uint8_t nr_of_candidates; for (int i=0; i<5; i++) { @@ -528,7 +528,6 @@ bool allocate_dl_retransmission(module_id_t module_id, UE->rnti, frame, slot); - RC.nrmac[module_id]->pdcch_cand[cid]--; return false; } @@ -692,8 +691,7 @@ void pf_dl(module_id_t module_id, } /* Find a free CCE */ - const int cid = sched_ctrl->coreset->controlResourceSetId; - const uint16_t Y = get_Y(cid%3, slot, iterator->UE->rnti); + const uint32_t Y = get_Y(sched_ctrl->search_space, slot, iterator->UE->rnti); uint8_t nr_of_candidates; for (int i=0; i<5; i++) { @@ -732,7 +730,6 @@ void pf_dl(module_id_t module_id, rnti, frame, slot); - mac->pdcch_cand[cid]--; iterator++; continue; } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 9d32a44220..808fc613f1 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -263,8 +263,7 @@ void nr_preprocessor_phytest(module_id_t module_id, } AssertFatal(nr_of_candidates>0,"nr_of_candidates is 0\n"); - const int cid = sched_ctrl->coreset->controlResourceSetId; - const uint16_t Y = get_Y(cid%3, slot, UE->rnti); + const uint32_t Y = get_Y(sched_ctrl->search_space, slot, UE->rnti); int CCEIndex = find_pdcch_candidate(RC.nrmac[module_id], CC_id, @@ -288,7 +287,6 @@ void nr_preprocessor_phytest(module_id_t module_id, rnti, frame, slot); - RC.nrmac[module_id]->pdcch_cand[cid]--; return; } @@ -440,8 +438,7 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_ } AssertFatal(nr_of_candidates>0,"nr_of_candidates is 0\n"); - const int cid = sched_ctrl->coreset->controlResourceSetId; - const uint16_t Y = get_Y(cid%3, slot, UE->rnti); + const uint32_t Y = get_Y(sched_ctrl->search_space, slot, UE->rnti); int CCEIndex = find_pdcch_candidate(nr_mac, CC_id, @@ -453,7 +450,6 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_ if (CCEIndex < 0) { LOG_E(MAC, "%s(): CCE list not empty, couldn't schedule PUSCH\n", __func__); - nr_mac->pdcch_cand[cid]--; return false; } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index c035f1b821..e6797bbab8 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -440,36 +440,17 @@ NR_sched_pdcch_t set_pdcch_structure(gNB_MAC_INST *gNB_mac, } -int cce_to_reg_interleaving(const int R, int k, int n_shift, const int C, int L, const int N_regs) { - - int f; // interleaving function - if(R==0) - f = k; - else { - int c = k/R; - int r = k%R; - f = (r*C + c + n_shift)%(N_regs/L); - } - return f; -} - int find_pdcch_candidate(gNB_MAC_INST *mac, int cc_id, int aggregation, int nr_of_candidates, NR_sched_pdcch_t *pdcch, NR_ControlResourceSet_t *coreset, - uint16_t Y){ + uint32_t Y){ uint16_t *vrb_map = mac->common_channels[cc_id].vrb_map; - const int next_cand = mac->pdcch_cand[coreset->controlResourceSetId]; const int N_ci = 0; - if(next_cand>=nr_of_candidates) { - LOG_D(NR_MAC,"No more available candidates for this coreset\n"); - return -1; - } - const int N_rb = pdcch->n_rb; // nb of rbs of coreset per symbol const int N_symb = coreset->duration; // nb of coreset symbols const int N_regs = N_rb*N_symb; // nb of REGs per coreset @@ -481,9 +462,10 @@ int find_pdcch_candidate(gNB_MAC_INST *mac, // loop over all the available candidates // this implements TS 38.211 Sec. 7.3.2.2 - for(int m=next_cand; mShiftIndex, C, L, N_regs); @@ -495,10 +477,8 @@ int find_pdcch_candidate(gNB_MAC_INST *mac, } } } - if(!taken){ - mac->pdcch_cand[coreset->controlResourceSetId] = m++; // using candidate m, next available is m+1 + if(!taken) return first_cce; - } } return -1; } @@ -1133,7 +1113,7 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu, for (int i=0;i<6;i++) pdcch_pdu->FreqDomainResource[i] = coreset->frequencyDomainResources.buf[i]; - LOG_D(MAC,"Coreset : BWPstart %d, BWPsize %d, SCS %d, freq %x, , duration %d, \n", + LOG_D(MAC,"Coreset : BWPstart %d, BWPsize %d, SCS %d, freq %x, , duration %d\n", pdcch_pdu->BWPStart,pdcch_pdu->BWPSize,(int)pdcch_pdu->SubcarrierSpacing,(int)coreset->frequencyDomainResources.buf[0],(int)coreset->duration); pdcch_pdu->CceRegMappingType = pdcch->CceRegMappingType; @@ -2277,20 +2257,6 @@ NR_UE_info_t *find_nr_UE(NR_UEs_t *UEs, rnti_t rntiP) return NULL; } -uint16_t get_Y(int cid, int slot, rnti_t rnti) { - - const int A[3] = {39827, 39829, 39839}; - const int D = 65537; - int Y; - - Y = (A[cid] * rnti) % D; - - for (int s = 0; s < slot; s++) - Y = (A[cid] * Y) % D; - - return Y; -} - int find_nr_RA_id(module_id_t mod_idP, int CC_idP, rnti_t rntiP) { //------------------------------------------------------------------------------ int RA_id; @@ -2938,6 +2904,30 @@ void nr_mac_update_timers(module_id_t module_id, cg->spCellConfig->spCellConfigDedicated ? cg->spCellConfig->spCellConfigDedicated->initialDownlinkBWP : NULL; + // update coreset/searchspace + int target_ss = NR_SearchSpace__searchSpaceType_PR_common; + NR_BWP_t *genericParameters = NULL; + if (sched_ctrl->active_bwp) { + target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific; + bwpd = (void*)sched_ctrl->active_bwp->bwp_Dedicated; + genericParameters = &sched_ctrl->active_bwp->bwp_Common->genericParameters; + } + else if (cg->spCellConfig && + cg->spCellConfig->spCellConfigDedicated && + (cg->spCellConfig->spCellConfigDedicated->initialDownlinkBWP)) { + target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific; + genericParameters = &scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters; + } + NR_BCCH_DL_SCH_Message_t *SIB1 = RC.nrmac[module_id]->common_channels[0].sib1; + sched_ctrl->search_space = get_searchspace(SIB1 ? SIB1->message.choice.c1->choice.systemInformationBlockType1 : NULL, scc, bwpd, target_ss); + sched_ctrl->coreset = get_coreset(RC.nrmac[module_id], scc, bwpd, sched_ctrl->search_space, target_ss); + sched_ctrl->sched_pdcch = set_pdcch_structure(RC.nrmac[module_id], + sched_ctrl->search_space, + sched_ctrl->coreset, + scc, + genericParameters, + RC.nrmac[module_id]->type0_PDCCH_CSS_config); + NR_pdsch_semi_static_t *ps = &sched_ctrl->pdsch_semi_static; const uint8_t layers = set_dl_nrOfLayers(sched_ctrl); diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_uci.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_uci.c index 3e36611c66..d64b9c43db 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_uci.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_uci.c @@ -941,7 +941,7 @@ void tci_handling(NR_UE_info_t *UE, frame_t frame, slot_t slot) { uint8_t idx = 0; NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl; - const int bwp_id = sched_ctrl->active_bwp ? 1 : 0; + const int bwp_id = sched_ctrl->active_bwp ? sched_ctrl->active_bwp->bwp_Id : 0; NR_CellGroupConfig_t *CellGroup = UE->CellGroup; //bwp indicator diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c index f7f05fd57b..495ca765e6 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c @@ -933,8 +933,7 @@ static bool allocate_ul_retransmission(gNB_MAC_INST *nrmac, } /* Find a free CCE */ - const int cid = sched_ctrl->coreset->controlResourceSetId; - const uint16_t Y = get_Y(cid%3, slot, UE->rnti); + const uint32_t Y = get_Y(sched_ctrl->search_space, slot, UE->rnti); uint8_t nr_of_candidates; for (int i=0; i<5; i++) { // for now taking the lowest value among the available aggregation levels @@ -1101,8 +1100,7 @@ void pf_ul(module_id_t module_id, if (B == 0 && do_sched) { /* if no data, pre-allocate 5RB */ /* Find a free CCE */ - const int cid = sched_ctrl->coreset->controlResourceSetId; - const uint16_t Y = get_Y(cid%3, slot, UE->rnti); + const uint32_t Y = get_Y(sched_ctrl->search_space, slot, UE->rnti); uint8_t nr_of_candidates; for (int i=0; i<5; i++) { // for now taking the lowest value among the available aggregation levels @@ -1216,8 +1214,7 @@ void pf_ul(module_id_t module_id, NR_UE_sched_ctrl_t *sched_ctrl = &iterator->UE->UE_sched_ctrl; - const int cid = sched_ctrl->coreset->controlResourceSetId; - const uint16_t Y = get_Y(cid%3, slot, iterator->UE->rnti); + const uint32_t Y = get_Y(sched_ctrl->search_space, slot, iterator->UE->rnti); uint8_t nr_of_candidates; for (int i=0; i<5; i++) { // for now taking the lowest value among the available aggregation levels diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index e42acb3061..b6774756c9 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -290,7 +290,7 @@ int find_pdcch_candidate(gNB_MAC_INST *mac, int nr_of_candidates, NR_sched_pdcch_t *pdcch, NR_ControlResourceSet_t *coreset, - uint16_t Y); + uint32_t Y); void fill_pdcch_vrb_map(gNB_MAC_INST *mac, int CC_id, @@ -373,8 +373,6 @@ void nr_set_pusch_semi_static(const NR_SIB1_t *sib1, uint8_t nrOfLayers, NR_pusch_semi_static_t *ps); -uint16_t get_Y(int cid, int slot, rnti_t rnti); - uint8_t nr_get_tpc(int target, uint8_t cqi, int incr); int get_spf(nfapi_nr_config_request_scf_t *cfg); @@ -412,14 +410,6 @@ void mac_remove_nr_ue(gNB_MAC_INST *nr_mac, rnti_t rnti); void nr_mac_remove_ra_rnti(module_id_t mod_id, rnti_t rnti); -int allocate_nr_CCEs(gNB_MAC_INST *nr_mac, - NR_BWP_Downlink_t *bwp, - NR_ControlResourceSet_t *coreset, - int aggregation, - uint16_t Y, - int m, - int nr_of_candidates); - int nr_get_default_pucch_res(int pucch_ResourceCommon); void compute_csi_bitlen(NR_CSI_MeasConfig_t *csi_MeasConfig, NR_UE_info_t *UE); diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index 974d6dff4a..03a982ab7b 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -789,7 +789,7 @@ typedef struct gNB_MAC_INST_s { nfapi_nr_ul_dci_request_t UL_dci_req[NFAPI_CC_MAX]; /// NFAPI DL PDU structure nfapi_nr_tx_data_request_t TX_req[NFAPI_CC_MAX]; - int pdcch_cand[MAX_NUM_CORESET]; + NR_UEs_t UE_info; /// UL handle diff --git a/openair2/RRC/NR/MESSAGES/asn1_msg.c b/openair2/RRC/NR/MESSAGES/asn1_msg.c index 189ade4796..d38a8ff13d 100755 --- a/openair2/RRC/NR/MESSAGES/asn1_msg.c +++ b/openair2/RRC/NR/MESSAGES/asn1_msg.c @@ -1041,61 +1041,8 @@ void fill_default_downlinkBWP(NR_BWP_Downlink_t *bwp, int curr_bwp = NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,MAX_BWP_SIZE); NR_ControlResourceSet_t *coreset = calloc(1,sizeof(*coreset)); - coreset->controlResourceSetId=(bwp->bwp_Id<<1); // To uniquely identify each Coreset lets derive it from the BWPId - // frequency domain resources depends on BWP size - // options are 24, 48 or 96 - coreset->frequencyDomainResources.buf = calloc(1,6); - if (0) { - if (curr_bwp < 48) - coreset->frequencyDomainResources.buf[0] = 0xf0; - else - coreset->frequencyDomainResources.buf[0] = 0xff; - if (curr_bwp < 96) - coreset->frequencyDomainResources.buf[1] = 0; - else - coreset->frequencyDomainResources.buf[1] = 0xff; - } else { - coreset->frequencyDomainResources.buf[0] = 0xf0; - coreset->frequencyDomainResources.buf[1] = 0; - } - coreset->frequencyDomainResources.buf[2] = 0; - coreset->frequencyDomainResources.buf[3] = 0; - coreset->frequencyDomainResources.buf[4] = 0; - coreset->frequencyDomainResources.buf[5] = 0; - coreset->frequencyDomainResources.size = 6; - coreset->frequencyDomainResources.bits_unused = 3; - coreset->duration=1; - coreset->cce_REG_MappingType.present = NR_ControlResourceSet__cce_REG_MappingType_PR_nonInterleaved; - coreset->precoderGranularity = NR_ControlResourceSet__precoderGranularity_sameAsREG_bundle; - - coreset->tci_StatesPDCCH_ToAddList=calloc(1,sizeof(*coreset->tci_StatesPDCCH_ToAddList)); - uint64_t bitmap=0; - switch (scc->ssb_PositionsInBurst->present) { - case 1 : - bitmap = ((uint64_t) scc->ssb_PositionsInBurst->choice.shortBitmap.buf[0])<<56; - break; - case 2 : - bitmap = ((uint64_t) scc->ssb_PositionsInBurst->choice.mediumBitmap.buf[0])<<56; - break; - case 3 : - for (int i=0; i<8; i++) { - bitmap |= (((uint64_t) scc->ssb_PositionsInBurst->choice.longBitmap.buf[i])<<((7-i)*8)); - } - break; - default: - AssertFatal(1==0,"SSB bitmap size value %d undefined (allowed values 1,2,3) \n", scc->ssb_PositionsInBurst->present); - } - NR_TCI_StateId_t *tci[64]; - for (int i=0;i<64;i++) { - if ((bitmap>>(63-i))&0x01){ - tci[i]=calloc(1,sizeof(*tci[i])); - *tci[i] = i; - ASN_SEQUENCE_ADD(&coreset->tci_StatesPDCCH_ToAddList->list,tci[i]); - } - } - coreset->tci_StatesPDCCH_ToReleaseList = NULL; - coreset->tci_PresentInDCI = NULL; - coreset->pdcch_DMRS_ScramblingID = NULL; + uint64_t bitmap = get_ssb_bitmap(scc); + rrc_coreset_config(coreset, bwp->bwp_Id, curr_bwp, bitmap); bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet = coreset; bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->searchSpaceZero=NULL; @@ -1153,36 +1100,7 @@ void fill_default_downlinkBWP(NR_BWP_Downlink_t *bwp, bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList)); NR_ControlResourceSet_t *coreset2 = calloc(1,sizeof(*coreset2)); - coreset2->controlResourceSetId=(bwp->bwp_Id<<1)+1; // To uniquely identify each Coreset lets derive it from the BWPId - // frequency domain resources depends on BWP size - // options are 24, 48 or 96 - coreset2->frequencyDomainResources.buf = calloc(1,6); - if (0) { - if (curr_bwp < 48) - coreset2->frequencyDomainResources.buf[0] = 0xf0; - else - coreset2->frequencyDomainResources.buf[0] = 0xff; - if (curr_bwp < 96) - coreset2->frequencyDomainResources.buf[1] = 0; - else - coreset2->frequencyDomainResources.buf[1] = 0xff; - } else { - coreset2->frequencyDomainResources.buf[0] = 0xf0; - coreset2->frequencyDomainResources.buf[1] = 0; - } - coreset2->frequencyDomainResources.buf[2] = 0; - coreset2->frequencyDomainResources.buf[3] = 0; - coreset2->frequencyDomainResources.buf[4] = 0; - coreset2->frequencyDomainResources.buf[5] = 0; - coreset2->frequencyDomainResources.size = 6; - coreset2->frequencyDomainResources.bits_unused = 3; - coreset2->duration=1; - coreset2->cce_REG_MappingType.present = NR_ControlResourceSet__cce_REG_MappingType_PR_nonInterleaved; - coreset2->precoderGranularity = NR_ControlResourceSet__precoderGranularity_sameAsREG_bundle; - coreset2->tci_StatesPDCCH_ToAddList=NULL; - coreset2->tci_StatesPDCCH_ToReleaseList = NULL; - coreset2->tci_PresentInDCI = NULL; - coreset2->pdcch_DMRS_ScramblingID = NULL; + rrc_coreset_config(coreset2, bwp->bwp_Id, curr_bwp, bitmap); ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list, coreset2); bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList)); @@ -1832,38 +1750,9 @@ void fill_initial_SpCellConfig(int uid, bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList = calloc(1,sizeof(*bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList)); NR_ControlResourceSet_t *coreset = calloc(1,sizeof(*coreset)); - coreset->controlResourceSetId=1; - // frequency domain resources depends on BWP size - // options are 24, 48 or 96 - coreset->frequencyDomainResources.buf = calloc(1,6); - if (0) { - int curr_bwp = scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth; - if (curr_bwp < 48) - coreset->frequencyDomainResources.buf[0] = 0xf0; - else - coreset->frequencyDomainResources.buf[0] = 0xff; - if (curr_bwp < 96) - coreset->frequencyDomainResources.buf[1] = 0; - else - coreset->frequencyDomainResources.buf[1] = 0xff; - } else { - coreset->frequencyDomainResources.buf[0] = 0xf0; - coreset->frequencyDomainResources.buf[1] = 0; - } - coreset->frequencyDomainResources.buf[2] = 0; - coreset->frequencyDomainResources.buf[3] = 0; - coreset->frequencyDomainResources.buf[4] = 0; - coreset->frequencyDomainResources.buf[5] = 0; - coreset->frequencyDomainResources.size = 6; - coreset->frequencyDomainResources.bits_unused = 3; - coreset->duration=1; - coreset->cce_REG_MappingType.present = NR_ControlResourceSet__cce_REG_MappingType_PR_nonInterleaved; - coreset->precoderGranularity = NR_ControlResourceSet__precoderGranularity_sameAsREG_bundle; - coreset->tci_StatesPDCCH_ToAddList=NULL; - coreset->tci_StatesPDCCH_ToReleaseList = NULL; - coreset->tci_PresentInDCI = NULL; - coreset->pdcch_DMRS_ScramblingID = NULL; + uint64_t bitmap = get_ssb_bitmap(scc); + rrc_coreset_config(coreset, 0, curr_bwp, bitmap); ASN_SEQUENCE_ADD(&bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list, coreset); @@ -1874,7 +1763,7 @@ void fill_initial_SpCellConfig(int uid, ss2->searchSpaceId=2; ss2->controlResourceSetId=calloc(1,sizeof(*ss2->controlResourceSetId)); - *ss2->controlResourceSetId=1; + *ss2->controlResourceSetId=coreset->controlResourceSetId; ss2->monitoringSlotPeriodicityAndOffset=calloc(1,sizeof(*ss2->monitoringSlotPeriodicityAndOffset)); ss2->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1; ss2->monitoringSlotPeriodicityAndOffset->choice.sl1=(NULL_t)0; diff --git a/openair2/RRC/NR/nr_rrc_config.c b/openair2/RRC/NR/nr_rrc_config.c index d339ab0780..3517cf76a0 100644 --- a/openair2/RRC/NR/nr_rrc_config.c +++ b/openair2/RRC/NR/nr_rrc_config.c @@ -34,6 +34,63 @@ const uint8_t slotsperframe[5] = {10, 20, 40, 80, 160}; +void rrc_coreset_config(NR_ControlResourceSet_t *coreset, + int bwp_id, + int curr_bwp, + uint64_t ssb_bitmap) { + + + // frequency domain resources depending on BWP size + coreset->frequencyDomainResources.buf = calloc(1,6); + coreset->frequencyDomainResources.buf[0] = (curr_bwp < 48) ? 0xf0 : 0xff; + coreset->frequencyDomainResources.buf[1] = (curr_bwp < 96) ? 0x00 : 0xff; + coreset->frequencyDomainResources.buf[2] = (curr_bwp < 144) ? 0x00 : 0xff; + coreset->frequencyDomainResources.buf[3] = (curr_bwp < 192) ? 0x00 : 0xff; + coreset->frequencyDomainResources.buf[4] = (curr_bwp < 240) ? 0x00 : 0xff; + coreset->frequencyDomainResources.buf[5] = 0x00; + coreset->frequencyDomainResources.size = 6; + coreset->frequencyDomainResources.bits_unused = 3; + coreset->duration = (curr_bwp < 48) ? 2 : 1; + coreset->cce_REG_MappingType.present = NR_ControlResourceSet__cce_REG_MappingType_PR_nonInterleaved; + coreset->precoderGranularity = NR_ControlResourceSet__precoderGranularity_sameAsREG_bundle; + + // The ID space is used across the BWPs of a Serving Cell as per 38.331 + coreset->controlResourceSetId = bwp_id + 1; + + coreset->tci_StatesPDCCH_ToAddList=calloc(1,sizeof(*coreset->tci_StatesPDCCH_ToAddList)); + NR_TCI_StateId_t *tci[64]; + for (int i=0;i<64;i++) { + if ((ssb_bitmap>>(63-i))&0x01){ + tci[i]=calloc(1,sizeof(*tci[i])); + *tci[i] = i; + ASN_SEQUENCE_ADD(&coreset->tci_StatesPDCCH_ToAddList->list,tci[i]); + } + } + coreset->tci_StatesPDCCH_ToReleaseList = NULL; + coreset->tci_PresentInDCI = NULL; + coreset->pdcch_DMRS_ScramblingID = NULL; +} + +uint64_t get_ssb_bitmap(NR_ServingCellConfigCommon_t *scc) { + uint64_t bitmap=0; + switch (scc->ssb_PositionsInBurst->present) { + case 1 : + bitmap = ((uint64_t) scc->ssb_PositionsInBurst->choice.shortBitmap.buf[0])<<56; + break; + case 2 : + bitmap = ((uint64_t) scc->ssb_PositionsInBurst->choice.mediumBitmap.buf[0])<<56; + break; + case 3 : + for (int i=0; i<8; i++) { + bitmap |= (((uint64_t) scc->ssb_PositionsInBurst->choice.longBitmap.buf[i])<<((7-i)*8)); + } + break; + default: + AssertFatal(1==0,"SSB bitmap size value %d undefined (allowed values 1,2,3) \n", scc->ssb_PositionsInBurst->present); + } + return bitmap; +} + void set_csirs_periodicity(NR_NZP_CSI_RS_Resource_t *nzpcsi0, int uid, int nb_slots_per_period) { nzpcsi0->periodicityAndOffset = calloc(1,sizeof(*nzpcsi0->periodicityAndOffset)); diff --git a/openair2/RRC/NR/nr_rrc_config.h b/openair2/RRC/NR/nr_rrc_config.h index ca6e20512e..8b28e2d584 100644 --- a/openair2/RRC/NR/nr_rrc_config.h +++ b/openair2/RRC/NR/nr_rrc_config.h @@ -111,6 +111,11 @@ typedef struct physicalcellgroup_s{ long RNTI_Value[MAX_NUM_CCs]; }physicalcellgroup_t; +uint64_t get_ssb_bitmap(NR_ServingCellConfigCommon_t *scc); +void rrc_coreset_config(NR_ControlResourceSet_t *coreset, + int bwp_id, + int curr_bwp, + uint64_t ssb_bitmap); void nr_rrc_config_dl_tda(NR_ServingCellConfigCommon_t *scc, NR_PDSCH_TimeDomainResourceAllocationList_t *pdsch_TimeDomainAllocationList, int curr_bwp); diff --git a/openair2/RRC/NR/rrc_gNB_reconfig.c b/openair2/RRC/NR/rrc_gNB_reconfig.c index de62035b48..0118778582 100644 --- a/openair2/RRC/NR/rrc_gNB_reconfig.c +++ b/openair2/RRC/NR/rrc_gNB_reconfig.c @@ -119,39 +119,7 @@ void fill_default_nsa_downlinkBWP(NR_BWP_Downlink_t *bwp, int curr_bwp = NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275); NR_ControlResourceSet_t *coreset = calloc(1,sizeof(*coreset)); - coreset->controlResourceSetId=bwp->bwp_Id+1; // To uniquely identify each Coreset lets derive it from the BWPId - // frequency domain resources depends on BWP size - // options are 24, 48 or 96 - coreset->frequencyDomainResources.buf = calloc(1,6); - if (curr_bwp < 48) - coreset->frequencyDomainResources.buf[0] = 0xf0; - else - coreset->frequencyDomainResources.buf[0] = 0xff; - if (curr_bwp < 96) - coreset->frequencyDomainResources.buf[1] = 0; - else - coreset->frequencyDomainResources.buf[1] = 0xff; - coreset->frequencyDomainResources.buf[2] = 0; - coreset->frequencyDomainResources.buf[3] = 0; - coreset->frequencyDomainResources.buf[4] = 0; - coreset->frequencyDomainResources.buf[5] = 0; - coreset->frequencyDomainResources.size = 6; - coreset->frequencyDomainResources.bits_unused = 3; - coreset->duration=1; - coreset->cce_REG_MappingType.present = NR_ControlResourceSet__cce_REG_MappingType_PR_nonInterleaved; - coreset->precoderGranularity = NR_ControlResourceSet__precoderGranularity_sameAsREG_bundle; - coreset->tci_StatesPDCCH_ToAddList=calloc(1,sizeof(*coreset->tci_StatesPDCCH_ToAddList)); - NR_TCI_StateId_t *tci[64]; - for (int i=0;i<64;i++) { - if ((bitmap>>(63-i))&0x01){ - tci[i]=calloc(1,sizeof(*tci[i])); - *tci[i] = i; - ASN_SEQUENCE_ADD(&coreset->tci_StatesPDCCH_ToAddList->list,tci[i]); - } - } - coreset->tci_StatesPDCCH_ToReleaseList = NULL; - coreset->tci_PresentInDCI = NULL; - coreset->pdcch_DMRS_ScramblingID = NULL; + rrc_coreset_config(coreset, bwp->bwp_Id, curr_bwp, bitmap); bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet = coreset; bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->searchSpaceZero=NULL; @@ -663,25 +631,9 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco // where the startPosition = 2 or 3 and sl160 = 17, 17, 27 ... 157 only give us 30 different allocations. AssertFatal(uid>=0 && uid<30, "gNB cannot allocate the SRS resources\n"); + uint64_t bitmap = get_ssb_bitmap(servingcellconfigcommon); fix_servingcellconfigdedicated(servingcellconfigdedicated); - uint64_t bitmap=0; - switch (servingcellconfigcommon->ssb_PositionsInBurst->present) { - case 1 : - bitmap = ((uint64_t) servingcellconfigcommon->ssb_PositionsInBurst->choice.shortBitmap.buf[0])<<56; - break; - case 2 : - bitmap = ((uint64_t) servingcellconfigcommon->ssb_PositionsInBurst->choice.mediumBitmap.buf[0])<<56; - break; - case 3 : - for (int i=0; i<8; i++) { - bitmap |= (((uint64_t) servingcellconfigcommon->ssb_PositionsInBurst->choice.longBitmap.buf[i])<<((7-i)*8)); - } - break; - default: - AssertFatal(1==0,"SSB bitmap size value %d undefined (allowed values 1,2,3) \n", servingcellconfigcommon->ssb_PositionsInBurst->present); - } - memset(secondaryCellGroup,0,sizeof(NR_CellGroupConfig_t)); secondaryCellGroup->cellGroupId = scg_id; NR_RLC_BearerConfig_t *RLC_BearerConfig = calloc(1,sizeof(*RLC_BearerConfig));