diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.c b/openair1/PHY/NR_TRANSPORT/nr_dci.c index 213fa6571d..c830278b44 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.c @@ -205,7 +205,7 @@ uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars, nr_byte2bit(encoderOutput,currentPtr->encoderLength,encoded_payload);*/ // scrambling - uint32_t scrambled_payload[4]; + uint32_t scrambled_payload[NR_MAX_DCI_SIZE_DWORD]; uint32_t Nid = (pdcch_params.search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC)? pdcch_params.scrambling_id : config.sch_config.physical_cell_id.value; uint32_t n_RNTI = (pdcch_params.search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC)? pdcch_params.rnti : 0; nr_pdcch_scrambling(dci_alloc.dci_pdu, dci_alloc.size, Nid, n_RNTI, scrambled_payload); diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c index 2f0b713a00..fb75415bf3 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c @@ -56,7 +56,8 @@ void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m else { //NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC } - AssertFatal((N_reg%(bsize*R))==0, "CCE to REG interleaving: Invalid configuration leading to non integer C\n"); + uint8_t cond = N_reg%(bsize*R); + AssertFatal(cond==0, "CCE to REG interleaving: Invalid configuration leading to non integer C\n"); C = N_reg/(bsize*R); tmp = L * (( Y + (uint16_t)(floor((m*N_cce)/(L*M_s_max))) + n_CI ) % ((uint16_t)floor(N_cce/L))); @@ -65,10 +66,10 @@ void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m for (uint8_t cce_idx=0; cce_idxcce_list[cce_idx]; cce->cce_idx = tmp + cce_idx; - LOG_I(PHY, "cce_idx %d\n", cce->cce_idx); + LOG_D(PHY, "cce_idx %d\n", cce->cce_idx); if (pdcch_params->cr_mapping_type == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) { - LOG_I(PHY, "Interleaved CCE to REG mapping\n"); + LOG_D(PHY, "Interleaved CCE to REG mapping\n"); uint8_t j = cce->cce_idx, j_prime; uint8_t r,c,idx; @@ -77,14 +78,14 @@ void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m r = j_prime%R; c = (j_prime-r)/R; idx = (r*C + c + n_shift)%(N_reg/bsize); - LOG_I(PHY, "bundle idx = %d \n j = %d \t j_prime = %d \t r = %d \t c = %d\n", idx, j , j_prime, r, c); + LOG_D(PHY, "bundle idx = %d \n j = %d \t j_prime = %d \t r = %d \t c = %d\n", idx, j , j_prime, r, c); for (uint8_t reg_idx=0; reg_idxreg_list[reg_idx]; reg->reg_idx = bsize*idx + reg_idx; reg->start_sc_idx = (reg->reg_idx/pdcch_params->n_symb) * NR_NB_SC_PER_RB; reg->symb_idx = reg->reg_idx % pdcch_params->n_symb; - LOG_I(PHY, "reg %d symbol %d start subcarrier %d\n", reg->reg_idx, reg->symb_idx, reg->start_sc_idx); + LOG_D(PHY, "reg %d symbol %d start subcarrier %d\n", reg->reg_idx, reg->symb_idx, reg->start_sc_idx); } } } @@ -130,22 +131,18 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB, // Freq domain assignment fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<frequency_domain_assignment>>(fsize-i-1))&1)<time_domain_assignment>>(3-i))&1)<<(pos+i); - pos += 4; + *dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<vrb_to_prb_mapping&1)<vrb_to_prb_mapping&1)<mcs>>(4-i))&1)<<(pos+i); - pos += 5; + *dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<tb_scaling>>(1-i))&1)<<(pos+i); + *dci_pdu |= ((pdu_rel15->tb_scaling>>(1-i))&1)<