Schedule ULSCH in flexible slots in InitialBWP
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@@ -1360,18 +1360,6 @@ bool nr_fr1_ulsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t
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if (!is_xlsch_in_slot(nr_mac->ulsch_slot_bitmap[sched_slot / 64], sched_slot))
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if (!is_xlsch_in_slot(nr_mac->ulsch_slot_bitmap[sched_slot / 64], sched_slot))
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return false;
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return false;
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bool is_mixed_slot = false;
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const NR_TDD_UL_DL_Pattern_t *tdd =
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scc->tdd_UL_DL_ConfigurationCommon ? &scc->tdd_UL_DL_ConfigurationCommon->pattern1 : NULL;
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if (tdd)
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is_mixed_slot = is_xlsch_in_slot(nr_mac->dlsch_slot_bitmap[sched_slot / 64], sched_slot) &&
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is_xlsch_in_slot(nr_mac->ulsch_slot_bitmap[sched_slot / 64], sched_slot);
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// FIXME: Avoid mixed slots for initialUplinkBWP
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if (current_BWP->bwp_id==0 && is_mixed_slot)
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return false;
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// Avoid slots with the SRS
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// Avoid slots with the SRS
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UE_iterator(nr_mac->UE_info.list, UE) {
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UE_iterator(nr_mac->UE_info.list, UE) {
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NR_sched_srs_t sched_srs = UE->UE_sched_ctrl.sched_srs;
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NR_sched_srs_t sched_srs = UE->UE_sched_ctrl.sched_srs;
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