separate DL and UL timers at UE
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+4
-1
@@ -519,7 +519,7 @@ void processSlotTX(void *arg)
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bool sl_tx_action = false;
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if (UE->if_inst)
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UE->if_inst->slot_indication(UE->Mod_id);
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UE->if_inst->slot_indication(UE->Mod_id, true);
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if (proc->tx_slot_type == NR_UPLINK_SLOT || proc->tx_slot_type == NR_MIXED_SLOT) {
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if (UE->sl_mode == 2 && proc->tx_slot_type == NR_SIDELINK_SLOT) {
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@@ -650,6 +650,9 @@ static int UE_dl_preprocessing(PHY_VARS_NR_UE *UE,
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}
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}
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if (UE->if_inst)
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UE->if_inst->slot_indication(UE->Mod_id, false);
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bool dl_slot = false;
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if (proc->rx_slot_type == NR_DOWNLINK_SLOT || proc->rx_slot_type == NR_MIXED_SLOT) {
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dl_slot = true;
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