maki/openairinterface5g
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fixed CCE allocation bug.

Browse Source
This commit is contained in:
Raymond Knopp
2016-05-10 19:34:36 +02:00
parent 8df63bdfe8
commit 4070a3affa
7 changed files with 47 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files
openair1/SCHED/phy_mac_stub.c
+4 -3
View File
@@ -571,12 +571,13 @@ void fill_dci(DCI_PDU *DCI_pdu, uint8_t sched_subframe, PHY_VARS_eNB *phy_vars_e
break;*/ break;*/
} }
/*
DCI_pdu->nCCE = 0; DCI_pdu->nCCE = 0;
for (i=0; i<DCI_pdu->Num_common_dci+DCI_pdu->Num_ue_spec_dci; i++) { for (i=0; i<DCI_pdu->Num_common_dci+DCI_pdu->Num_ue_spec_dci; i++) {
DCI_pdu->nCCE += (1<<(DCI_pdu->dci_alloc[i].L)); DCI_pdu->nCCE += (1<<(DCI_pdu->dci_alloc[i].L));
} }
*/
} }
void fill_dci_emos(DCI_PDU *DCI_pdu, uint8_t subframe, PHY_VARS_eNB *phy_vars_eNB) void fill_dci_emos(DCI_PDU *DCI_pdu, uint8_t subframe, PHY_VARS_eNB *phy_vars_eNB)
@@ -744,11 +745,11 @@ void fill_dci_emos(DCI_PDU *DCI_pdu, uint8_t subframe, PHY_VARS_eNB *phy_vars_eN
default: default:
break; break;
} }
/*
DCI_pdu->nCCE = 0; DCI_pdu->nCCE = 0;
for (i=0; i<DCI_pdu->Num_common_dci+DCI_pdu->Num_ue_spec_dci; i++) { for (i=0; i<DCI_pdu->Num_common_dci+DCI_pdu->Num_ue_spec_dci; i++) {
DCI_pdu->nCCE += (1<<(DCI_pdu->dci_alloc[i].L)); DCI_pdu->nCCE += (1<<(DCI_pdu->dci_alloc[i].L));
} }
*/
} }
openair1/SCHED/phy_procedures_lte_eNb.c
+7 -7
View File
@@ -1,3 +1,4 @@
/******************************************************************************* /*******************************************************************************
OpenAirInterface OpenAirInterface
Copyright(c) 1999 - 2014 Eurecom Copyright(c) 1999 - 2014 Eurecom
@@ -965,7 +966,7 @@ void phy_procedures_eNB_TX(unsigned char sched_subframe,PHY_VARS_eNB *phy_vars_e
num_pdcch_symbols = DCI_pdu->num_pdcch_symbols; num_pdcch_symbols = DCI_pdu->num_pdcch_symbols;
LOG_D(PHY,"num_pdcch_symbols %"PRIu8", nCCE %u (dci commond %"PRIu8", dci uespec %"PRIu8"\n",num_pdcch_symbols,DCI_pdu->nCCE, LOG_D(PHY,"num_pdcch_symbols %"PRIu8",(dci common %"PRIu8", dci uespec %"PRIu8"\n",num_pdcch_symbols,
DCI_pdu->Num_common_dci,DCI_pdu->Num_ue_spec_dci); DCI_pdu->Num_common_dci,DCI_pdu->Num_ue_spec_dci);
#if defined(SMBV) && !defined(EXMIMO) #if defined(SMBV) && !defined(EXMIMO)
@@ -1008,7 +1009,7 @@ void phy_procedures_eNB_TX(unsigned char sched_subframe,PHY_VARS_eNB *phy_vars_e
phy_vars_eNB->dlsch_eNB_SI->nCCE[subframe] = DCI_pdu->dci_alloc[i].firstCCE; phy_vars_eNB->dlsch_eNB_SI->nCCE[subframe] = DCI_pdu->dci_alloc[i].firstCCE;
LOG_T(PHY,"[eNB %"PRIu8"] Frame %d subframe %d : CCE resource for common DCI (SI) => %"PRIu8"/%u\n",phy_vars_eNB->Mod_id,phy_vars_eNB->proc[sched_subframe].frame_tx,subframe, LOG_T(PHY,"[eNB %"PRIu8"] Frame %d subframe %d : CCE resource for common DCI (SI) => %"PRIu8"/%u\n",phy_vars_eNB->Mod_id,phy_vars_eNB->proc[sched_subframe].frame_tx,subframe,
phy_vars_eNB->dlsch_eNB_SI->nCCE[subframe],DCI_pdu->nCCE); phy_vars_eNB->dlsch_eNB_SI->nCCE[subframe],DCI_pdu->dci_alloc[i].firstCCE);
#if defined(SMBV) && !defined(EXMIMO) #if defined(SMBV) && !defined(EXMIMO)
@@ -1039,8 +1040,8 @@ void phy_procedures_eNB_TX(unsigned char sched_subframe,PHY_VARS_eNB *phy_vars_e
phy_vars_eNB->dlsch_eNB_ra->nCCE[subframe] = DCI_pdu->dci_alloc[i].firstCCE; phy_vars_eNB->dlsch_eNB_ra->nCCE[subframe] = DCI_pdu->dci_alloc[i].firstCCE;
LOG_D(PHY,"[eNB %"PRIu8"] Frame %d subframe %d : CCE resource for common DCI (RA) => %"PRIu8"/%u\n",phy_vars_eNB->Mod_id,phy_vars_eNB->proc[sched_subframe].frame_tx,subframe, LOG_D(PHY,"[eNB %"PRIu8"] Frame %d subframe %d : CCE resource for common DCI (RA) => %"PRIu8"/%u (num_pdcch_symbols %d)\n",phy_vars_eNB->Mod_id,phy_vars_eNB->proc[sched_subframe].frame_tx,subframe,
phy_vars_eNB->dlsch_eNB_ra->nCCE[subframe],DCI_pdu->nCCE); phy_vars_eNB->dlsch_eNB_ra->nCCE[subframe],get_nCCE_mac(phy_vars_eNB->Mod_id,phy_vars_eNB->CC_id,num_pdcch_symbols,subframe),num_pdcch_symbols);
#if defined(SMBV) && !defined(EXMIMO) #if defined(SMBV) && !defined(EXMIMO)
// configure RA DCI // configure RA DCI
@@ -1094,7 +1095,7 @@ void phy_procedures_eNB_TX(unsigned char sched_subframe,PHY_VARS_eNB *phy_vars_e
phy_vars_eNB->dlsch_eNB[(uint8_t)UE_id][0]->nCCE[subframe] = DCI_pdu->dci_alloc[i].firstCCE; phy_vars_eNB->dlsch_eNB[(uint8_t)UE_id][0]->nCCE[subframe] = DCI_pdu->dci_alloc[i].firstCCE;
LOG_D(PHY,"[eNB %"PRIu8"] Frame %d subframe %d : CCE resource for ue DCI (PDSCH %"PRIx16") => %"PRIu8"/%u\n",phy_vars_eNB->Mod_id,phy_vars_eNB->proc[sched_subframe].frame_tx,subframe, LOG_D(PHY,"[eNB %"PRIu8"] Frame %d subframe %d : CCE resource for ue DCI (PDSCH %"PRIx16") => %"PRIu8"/%u\n",phy_vars_eNB->Mod_id,phy_vars_eNB->proc[sched_subframe].frame_tx,subframe,
DCI_pdu->dci_alloc[i].rnti,phy_vars_eNB->dlsch_eNB[(uint8_t)UE_id][0]->nCCE[subframe],DCI_pdu->nCCE); DCI_pdu->dci_alloc[i].rnti,phy_vars_eNB->dlsch_eNB[(uint8_t)UE_id][0]->nCCE[subframe],DCI_pdu->dci_alloc[i].firstCCE);
#if defined(SMBV) && !defined(EXMIMO) #if defined(SMBV) && !defined(EXMIMO)
@@ -1177,7 +1178,7 @@ void phy_procedures_eNB_TX(unsigned char sched_subframe,PHY_VARS_eNB *phy_vars_e
LOG_T(PHY,"[eNB %"PRIu8"] Frame %d subframe %d : CCE resources for UE spec DCI (PUSCH %"PRIx16") => %d/%u\n", LOG_T(PHY,"[eNB %"PRIu8"] Frame %d subframe %d : CCE resources for UE spec DCI (PUSCH %"PRIx16") => %d/%u\n",
phy_vars_eNB->Mod_id,phy_vars_eNB->proc[sched_subframe].frame_tx,subframe,DCI_pdu->dci_alloc[i].rnti, phy_vars_eNB->Mod_id,phy_vars_eNB->proc[sched_subframe].frame_tx,subframe,DCI_pdu->dci_alloc[i].rnti,
DCI_pdu->dci_alloc[i].firstCCE,DCI_pdu->nCCE); DCI_pdu->dci_alloc[i].firstCCE,DCI_pdu->dci_alloc[i].firstCCE);
#if defined(SMBV) && !defined(EXMIMO) #if defined(SMBV) && !defined(EXMIMO)
@@ -1218,7 +1219,6 @@ void phy_procedures_eNB_TX(unsigned char sched_subframe,PHY_VARS_eNB *phy_vars_e
LOG_D(PHY,"[eNB %"PRIu8"] Frame %d, subframe %d: Calling generate_dci_top (pdcch) (common %"PRIu8",ue_spec %"PRIu8")\n",phy_vars_eNB->Mod_id,phy_vars_eNB->proc[sched_subframe].frame_tx, subframe, LOG_D(PHY,"[eNB %"PRIu8"] Frame %d, subframe %d: Calling generate_dci_top (pdcch) (common %"PRIu8",ue_spec %"PRIu8")\n",phy_vars_eNB->Mod_id,phy_vars_eNB->proc[sched_subframe].frame_tx, subframe,
DCI_pdu->Num_common_dci,DCI_pdu->Num_ue_spec_dci); DCI_pdu->Num_common_dci,DCI_pdu->Num_ue_spec_dci);
num_pdcch_symbols = generate_dci_top(DCI_pdu->Num_ue_spec_dci, num_pdcch_symbols = generate_dci_top(DCI_pdu->Num_ue_spec_dci,
DCI_pdu->Num_common_dci, DCI_pdu->Num_common_dci,
DCI_pdu->dci_alloc, DCI_pdu->dci_alloc,
openair2/LAYER2/MAC/defs.h
+1 -1
View File
@@ -251,7 +251,7 @@ typedef struct {
typedef struct { typedef struct {
uint8_t Num_ue_spec_dci ; uint8_t Num_ue_spec_dci ;
uint8_t Num_common_dci ; uint8_t Num_common_dci ;
uint32_t nCCE; // uint32_t nCCE;
uint32_t num_pdcch_symbols; uint32_t num_pdcch_symbols;
DCI_ALLOC_t dci_alloc[NUM_DCI_MAX] ; DCI_ALLOC_t dci_alloc[NUM_DCI_MAX] ;
} DCI_PDU; } DCI_PDU;
openair2/LAYER2/MAC/eNB_scheduler.c
+21 -2
View File
@@ -108,8 +108,6 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
for (CC_id=0; CC_id<MAX_NUM_CCs; CC_id++) { for (CC_id=0; CC_id<MAX_NUM_CCs; CC_id++) {
DCI_pdu[CC_id] = &eNB_mac_inst[module_idP].common_channels[CC_id].DCI_pdu; DCI_pdu[CC_id] = &eNB_mac_inst[module_idP].common_channels[CC_id].DCI_pdu;
DCI_pdu[CC_id]->nCCE=0;
DCI_pdu[CC_id]->num_pdcch_symbols=1;
mbsfn_status[CC_id]=0; mbsfn_status[CC_id]=0;
// clear vrb_map // clear vrb_map
memset(eNB_mac_inst[module_idP].common_channels[CC_id].vrb_map,0,100); memset(eNB_mac_inst[module_idP].common_channels[CC_id].vrb_map,0,100);
@@ -661,7 +659,28 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
for (CC_id=0;CC_id<MAX_NUM_CCs;CC_id++) for (CC_id=0;CC_id<MAX_NUM_CCs;CC_id++)
allocate_CCEs(module_idP,CC_id,subframeP,0); allocate_CCEs(module_idP,CC_id,subframeP,0);
/*
int dummy=0;
for (i=0;
i<DCI_pdu[CC_id]->Num_common_dci+DCI_pdu[CC_id]->Num_ue_spec_dci;
i++)
if (DCI_pdu[CC_id]->dci_alloc[i].rnti==2)
dummy=1;
if (dummy==1)
for (i=0;
i<DCI_pdu[CC_id]->Num_common_dci+DCI_pdu[CC_id]->Num_ue_spec_dci;
i++)
LOG_I(MAC,"Frame %d, subframe %d: DCI %d/%d, format %d, rnti %x, NCCE %d(num_pdcch_symb %d)\n",
frameP,subframeP,i,DCI_pdu[CC_id]->Num_common_dci+DCI_pdu[CC_id]->Num_ue_spec_dci,
DCI_pdu[CC_id]->dci_alloc[i].format,
DCI_pdu[CC_id]->dci_alloc[i].rnti,
DCI_pdu[CC_id]->dci_alloc[i].firstCCE,
DCI_pdu[CC_id]->num_pdcch_symbols);
LOG_D(MAC,"frameP %d, subframeP %d\n",frameP,subframeP); LOG_D(MAC,"frameP %d, subframeP %d\n",frameP,subframeP);
*/
stop_meas(&eNB_mac_inst[module_idP].eNB_scheduler); stop_meas(&eNB_mac_inst[module_idP].eNB_scheduler);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ULSCH_SCHEDULER,VCD_FUNCTION_OUT); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ULSCH_SCHEDULER,VCD_FUNCTION_OUT);
openair2/LAYER2/MAC/eNB_scheduler_RA.c
+2
View File
@@ -251,6 +251,8 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
} }
if (!CCE_allocation_infeasible(module_idP,CC_id,1,subframeP,2,RA_template->RA_rnti)) { if (!CCE_allocation_infeasible(module_idP,CC_id,1,subframeP,2,RA_template->RA_rnti)) {
LOG_D(MAC,"Frame %d: Subframe %d : Adding common DCI for RA_RNTI %x\n",
frameP,subframeP,RA_template->RA_rnti);
add_common_dci(DCI_pdu, add_common_dci(DCI_pdu,
(void*)&RA_template->RA_alloc_pdu1[0], (void*)&RA_template->RA_alloc_pdu1[0],
RA_template->RA_rnti, RA_template->RA_rnti,
openair2/LAYER2/MAC/eNB_scheduler_primitives.c
+8 -6
View File
@@ -993,17 +993,19 @@ int allocate_CCEs(int module_idP,
int *CCE_table = eNB_mac_inst[module_idP].CCE_table[CC_idP]; int *CCE_table = eNB_mac_inst[module_idP].CCE_table[CC_idP];
DCI_PDU *DCI_pdu = &eNB_mac_inst[module_idP].common_channels[CC_idP].DCI_pdu; DCI_PDU *DCI_pdu = &eNB_mac_inst[module_idP].common_channels[CC_idP].DCI_pdu;
int nCCE_max = mac_xface->get_nCCE_max(module_idP,CC_idP,DCI_pdu->num_pdcch_symbols,subframeP); int nCCE_max = mac_xface->get_nCCE_max(module_idP,CC_idP,1,subframeP);
int fCCE; int fCCE;
int i,j; int i,j;
int allocation_is_feasible = 1; int allocation_is_feasible = 1;
DCI_ALLOC_t *dci_alloc; DCI_ALLOC_t *dci_alloc;
int nCCE=0;
LOG_D(MAC,"Allocate CCEs subframe %d, test %d : (common %d,uspec %d)\n",subframeP,test_onlyP,DCI_pdu->Num_common_dci,DCI_pdu->Num_ue_spec_dci); LOG_D(MAC,"Allocate CCEs subframe %d, test %d : (common %d,uspec %d)\n",subframeP,test_onlyP,DCI_pdu->Num_common_dci,DCI_pdu->Num_ue_spec_dci);
DCI_pdu->num_pdcch_symbols=1;
while (allocation_is_feasible == 1) { while (allocation_is_feasible == 1) {
init_CCE_table(module_idP,CC_idP); init_CCE_table(module_idP,CC_idP);
DCI_pdu->nCCE=0; nCCE=0;
for (i=0;i<DCI_pdu->Num_common_dci + DCI_pdu->Num_ue_spec_dci;i++) { for (i=0;i<DCI_pdu->Num_common_dci + DCI_pdu->Num_ue_spec_dci;i++) {
dci_alloc = &DCI_pdu->dci_alloc[i]; dci_alloc = &DCI_pdu->dci_alloc[i];
@@ -1011,9 +1013,9 @@ int allocate_CCEs(int module_idP,
i,DCI_pdu->Num_common_dci+DCI_pdu->Num_ue_spec_dci, i,DCI_pdu->Num_common_dci+DCI_pdu->Num_ue_spec_dci,
DCI_pdu->Num_common_dci,DCI_pdu->Num_ue_spec_dci, DCI_pdu->Num_common_dci,DCI_pdu->Num_ue_spec_dci,
dci_alloc->rnti,1<<dci_alloc->L, dci_alloc->rnti,1<<dci_alloc->L,
DCI_pdu->nCCE,nCCE_max,DCI_pdu->num_pdcch_symbols); nCCE,nCCE_max,DCI_pdu->num_pdcch_symbols);
if (DCI_pdu->nCCE + (1<<dci_alloc->L) > nCCE_max) { if (nCCE + (1<<dci_alloc->L) > nCCE_max) {
if (DCI_pdu->num_pdcch_symbols == 3) if (DCI_pdu->num_pdcch_symbols == 3)
allocation_is_feasible = 0; allocation_is_feasible = 0;
else { else {
@@ -1032,7 +1034,7 @@ int allocate_CCEs(int module_idP,
LOG_D(MAC,"Allocating at nCCE %d\n",fCCE); LOG_D(MAC,"Allocating at nCCE %d\n",fCCE);
if (test_onlyP == 0) { if (test_onlyP == 0) {
DCI_pdu->nCCE += (1<<dci_alloc->L); nCCE += (1<<dci_alloc->L);
dci_alloc->firstCCE=fCCE; dci_alloc->firstCCE=fCCE;
LOG_D(MAC,"Allocate CCEs subframe %d, test %d\n",subframeP,test_onlyP); LOG_D(MAC,"Allocate CCEs subframe %d, test %d\n",subframeP,test_onlyP);
} }
@@ -1049,7 +1051,7 @@ int allocate_CCEs(int module_idP,
DCI_pdu->Num_common_dci,DCI_pdu->Num_ue_spec_dci, DCI_pdu->Num_common_dci,DCI_pdu->Num_ue_spec_dci,
DCI_pdu->dci_alloc[j].rnti,DCI_pdu->dci_alloc[j].format, DCI_pdu->dci_alloc[j].rnti,DCI_pdu->dci_alloc[j].format,
1<<DCI_pdu->dci_alloc[j].L, 1<<DCI_pdu->dci_alloc[j].L,
DCI_pdu->nCCE,nCCE_max,DCI_pdu->num_pdcch_symbols); nCCE,nCCE_max,DCI_pdu->num_pdcch_symbols);
} }
} }
else { else {
targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.band7.tm1.50PRB.usrpb210.conf
+4 -4
View File
@@ -130,7 +130,7 @@ eNBs =
}; };
////////// MME parameters: ////////// MME parameters:
mme_ip_address = ( { ipv4 = "192.168.12.11"; mme_ip_address = ( { ipv4 = "127.0.0.3";
ipv6 = "192:168:30::17"; ipv6 = "192:168:30::17";
active = "yes"; active = "yes";
preference = "ipv4"; preference = "ipv4";
@@ -139,11 +139,11 @@ eNBs =
NETWORK_INTERFACES : NETWORK_INTERFACES :
{ {
ENB_INTERFACE_NAME_FOR_S1_MME = "eth0"; ENB_INTERFACE_NAME_FOR_S1_MME = "lo";
ENB_IPV4_ADDRESS_FOR_S1_MME = "192.168.12.213/24"; ENB_IPV4_ADDRESS_FOR_S1_MME = "127.0.0.2/24";
ENB_INTERFACE_NAME_FOR_S1U = "eth0"; ENB_INTERFACE_NAME_FOR_S1U = "eth0";
ENB_IPV4_ADDRESS_FOR_S1U = "192.168.12.213/24"; ENB_IPV4_ADDRESS_FOR_S1U = "127.0.0.4/24";
ENB_PORT_FOR_S1U = 2152; # Spec 2152 ENB_PORT_FOR_S1U = 2152; # Spec 2152
}; };