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ULSCH: remove CC loop, remove variables or limit scope

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This commit is contained in:
Robert Schmidt
2020-04-06 13:56:31 +02:00
parent 1670b4521e
commit 4250f8eaec
3 changed files with 532 additions and 534 deletions
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openair2/LAYER2/MAC/eNB_scheduler_ulsch.c
+522 -525
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File diff suppressed because it is too large Load Diff
openair2/LAYER2/MAC/mac_proto.h
+5 -3
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@@ -122,12 +122,12 @@ void schedule_ulsch(module_id_t module_idP, frame_t frameP,
/** \brief ULSCH Scheduling per RNTI /** \brief ULSCH Scheduling per RNTI
@param Mod_id Instance ID of eNB @param Mod_id Instance ID of eNB
@param slice_idx Slice instance index for this eNB @param CC_id The component carrier to schedule
@param frame Frame index @param frame Frame index
@param subframe Subframe number on which to act @param subframe Subframe number on which to act
@param sched_subframe Subframe number where PUSCH is transmitted (for DAI lookup) @param sched_subframe Subframe number where PUSCH is transmitted (for DAI lookup)
*/ */
void schedule_ulsch_rnti(module_id_t module_idP, int slice_idx, frame_t frameP, void schedule_ulsch_rnti(module_id_t module_idP, int CC_id, frame_t frameP,
sub_frame_t subframe, sub_frame_t subframe,
unsigned char sched_subframe, unsigned char sched_subframe,
uint16_t *first_rb); uint16_t *first_rb);
@@ -677,7 +677,9 @@ void set_ul_DAI(int module_idP,
int frameP, int frameP,
int subframeP); int subframeP);
void ulsch_scheduler_pre_processor(module_id_t module_idP, int slice_idx, int frameP, void ulsch_scheduler_pre_processor(module_id_t module_idP,
int CC_id,
int frameP,
sub_frame_t subframeP, sub_frame_t subframeP,
int sched_frameP, int sched_frameP,
unsigned char sched_subframeP, unsigned char sched_subframeP,
openair2/LAYER2/MAC/pre_processor.c
+5 -6
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@@ -419,7 +419,7 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id,
/// ULSCH PRE_PROCESSOR /// ULSCH PRE_PROCESSOR
void ulsch_scheduler_pre_processor(module_id_t module_idP, void ulsch_scheduler_pre_processor(module_id_t module_idP,
int slice_idx, int CC_id,
int frameP, int frameP,
sub_frame_t subframeP, sub_frame_t subframeP,
int sched_frameP, int sched_frameP,
@@ -427,7 +427,7 @@ void ulsch_scheduler_pre_processor(module_id_t module_idP,
uint16_t *first_rb) { uint16_t *first_rb) {
int UE_id; int UE_id;
uint16_t n; uint16_t n;
uint8_t CC_id, harq_pid; uint8_t harq_pid;
uint16_t nb_allocated_rbs[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB]; uint16_t nb_allocated_rbs[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB];
uint16_t total_allocated_rbs[NFAPI_CC_MAX]; uint16_t total_allocated_rbs[NFAPI_CC_MAX];
uint16_t average_rbs_per_user[NFAPI_CC_MAX]; uint16_t average_rbs_per_user[NFAPI_CC_MAX];
@@ -436,6 +436,7 @@ void ulsch_scheduler_pre_processor(module_id_t module_idP,
eNB_MAC_INST *eNB = RC.mac[module_idP]; eNB_MAC_INST *eNB = RC.mac[module_idP];
UE_info_t *UE_info = &eNB->UE_info; UE_info_t *UE_info = &eNB->UE_info;
slice_info_t *sli = &eNB->slice_info; slice_info_t *sli = &eNB->slice_info;
const int slice_idx = 0;
UE_TEMPLATE *UE_template = 0; UE_TEMPLATE *UE_template = 0;
UE_sched_ctrl_t *ue_sched_ctl; UE_sched_ctrl_t *ue_sched_ctl;
int N_RB_UL = 0; int N_RB_UL = 0;
@@ -498,8 +499,7 @@ void ulsch_scheduler_pre_processor(module_id_t module_idP,
ue_sched_ctl->max_rbs_allowed_slice_uplink[CC_id][slice_idx] = ue_sched_ctl->max_rbs_allowed_slice_uplink[CC_id][slice_idx] =
nb_rbs_allowed_slice(sli->ul[slice_idx].pct, N_RB_UL); nb_rbs_allowed_slice(sli->ul[slice_idx].pct, N_RB_UL);
first_rb_offset = UE_info->first_rb_offset[CC_id][slice_idx]; first_rb_offset = UE_info->first_rb_offset[CC_id][slice_idx];
available_rbs = available_rbs = N_RB_UL - 2 * first_rb[CC_id]; // factor 2: top&bottom
cmin(ue_sched_ctl->max_rbs_allowed_slice_uplink[CC_id][slice_idx], N_RB_UL - first_rb[CC_id] - first_rb_offset);
if (available_rbs < 0) if (available_rbs < 0)
available_rbs = 0; available_rbs = 0;
@@ -668,8 +668,7 @@ assign_max_mcs_min_rb(module_id_t module_idP,
} }
first_rb_offset = UE_info->first_rb_offset[CC_id][slice_idx]; first_rb_offset = UE_info->first_rb_offset[CC_id][slice_idx];
available_rbs = available_rbs = N_RB_UL - 2 * first_rb[CC_id];
cmin(ue_sched_ctl->max_rbs_allowed_slice_uplink[CC_id][slice_idx], N_RB_UL - first_rb[CC_id] - first_rb_offset);
while (tbs < bits_to_schedule && while (tbs < bits_to_schedule &&
rb_table[rb_table_index] < available_rbs && rb_table[rb_table_index] < available_rbs &&