From 0efa1185f3f7d5612e7cd4147d96bb9e5a2f988f Mon Sep 17 00:00:00 2001 From: naoi Date: Wed, 7 Feb 2018 20:40:06 +0900 Subject: [PATCH 01/18] fix: UE dosen't respond to pdcch order(contention based) --- openair1/PHY/LTE_TRANSPORT/dci_tools.c | 10 +++++++++- openair2/LAYER2/MAC/eNB_scheduler.c | 3 ++- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/openair1/PHY/LTE_TRANSPORT/dci_tools.c b/openair1/PHY/LTE_TRANSPORT/dci_tools.c index 3c6a5ded2c..ff31507979 100644 --- a/openair1/PHY/LTE_TRANSPORT/dci_tools.c +++ b/openair1/PHY/LTE_TRANSPORT/dci_tools.c @@ -907,6 +907,7 @@ void fill_pdcch_order(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_a ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->TPC = rel8->tpc; ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid = rel8->harq_process; ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->padding = 0; } else { dci_alloc->dci_length = sizeof_DCI1A_1_5MHz_FDD_t; ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->type = 1; @@ -917,6 +918,7 @@ void fill_pdcch_order(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_a ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->rv = rel8->redundancy_version_1; ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process; + ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->padding = 0; // printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } break; @@ -931,7 +933,8 @@ void fill_pdcch_order(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_a ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->rv = rel8->redundancy_version_1; ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->TPC = rel8->tpc; ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid = rel8->harq_process; - ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->padding = 0; // printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } else { dci_alloc->dci_length = sizeof_DCI1A_5MHz_FDD_t; @@ -943,6 +946,7 @@ void fill_pdcch_order(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_a ((DCI1A_5MHz_FDD_t *)dci_pdu)->rv = rel8->redundancy_version_1; ((DCI1A_5MHz_FDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI1A_5MHz_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process; + ((DCI1A_5MHz_FDD_t *)dci_pdu)->padding = 0; // printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } break; @@ -958,6 +962,7 @@ void fill_pdcch_order(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_a ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->TPC = rel8->tpc; ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->harq_pid = rel8->harq_process; ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->padding = 0; // printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } else { dci_alloc->dci_length = sizeof_DCI1A_10MHz_FDD_t; @@ -969,6 +974,7 @@ void fill_pdcch_order(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_a ((DCI1A_10MHz_FDD_t *)dci_pdu)->rv = rel8->redundancy_version_1; ((DCI1A_10MHz_FDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI1A_10MHz_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process; + ((DCI1A_10MHz_FDD_t *)dci_pdu)->padding = 0; // printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } break; @@ -984,6 +990,7 @@ void fill_pdcch_order(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_a ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->TPC = rel8->tpc; ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->harq_pid = rel8->harq_process; ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->padding = 0; // printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } else { dci_alloc->dci_length = sizeof_DCI1A_20MHz_FDD_t; @@ -995,6 +1002,7 @@ void fill_pdcch_order(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_a ((DCI1A_20MHz_FDD_t *)dci_pdu)->rv = rel8->redundancy_version_1; ((DCI1A_20MHz_FDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI1A_20MHz_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process; + ((DCI1A_20MHz_FDD_t *)dci_pdu)->padding = 0; // printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } break; diff --git a/openair2/LAYER2/MAC/eNB_scheduler.c b/openair2/LAYER2/MAC/eNB_scheduler.c index a69a721568..312c49094e 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler.c +++ b/openair2/LAYER2/MAC/eNB_scheduler.c @@ -550,7 +550,8 @@ check_ul_failure(module_id_t module_idP, int CC_id, int UE_id, UE_list->UE_sched_ctrl[UE_id].ul_failure_timer++; // check threshold - if (UE_list->UE_sched_ctrl[UE_id].ul_failure_timer > 20000) { + if (UE_list->UE_sched_ctrl[UE_id].ul_failure_timer > 4000) { + // note: probably ul_failure_timer is should be less than UE radio link failure time(see T310/N310/N311) // inform RRC of failure and clear timer LOG_I(MAC, "UE %d rnti %x: UL Failure after repeated PDCCH orders: Triggering RRC \n", From 0684f6dda1ee330bb39dcf3300d454a57b3e704e Mon Sep 17 00:00:00 2001 From: naoi Date: Fri, 9 Feb 2018 23:27:30 +0900 Subject: [PATCH 02/18] Fix: All UEs are detached when rf_tx_thread_busy occurs. --- targets/RT/USER/lte-ru.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/targets/RT/USER/lte-ru.c b/targets/RT/USER/lte-ru.c index 18d9cd42fc..ef641f6920 100644 --- a/targets/RT/USER/lte-ru.c +++ b/targets/RT/USER/lte-ru.c @@ -1524,8 +1524,10 @@ static void* ru_thread( void* param ) { // the thread can now be woken up AssertFatal(pthread_cond_signal(&ru->proc.cond_phy_tx) == 0, "ERROR pthread_cond_signal for phy_tx thread\n"); + }else{ + LOG_E(PHY,"phy tx thread busy, skipping\n"); + ++ru->proc.instance_cnt_phy_tx; } - else LOG_W(PHY,"phy tx thread busy, skipping\n"); pthread_mutex_unlock( &ru->proc.mutex_phy_tx ); } else { phy_tx_end = 1; @@ -1793,8 +1795,10 @@ static void* eNB_thread_phy_tx( void* param ) { // the thread can now be woken up AssertFatal(pthread_cond_signal(&ru->proc.cond_rf_tx) == 0, "ERROR pthread_cond_signal for rf_tx thread\n"); + }else{ + LOG_E(PHY,"rf tx thread busy, skipping\n"); + ru->proc.instance_cnt_rf_tx++; } - else LOG_W(PHY,"rf tx thread busy, skipping\n"); pthread_mutex_unlock( &ru->proc.mutex_rf_tx ); } if (release_thread(&proc->mutex_phy_tx,&proc->instance_cnt_phy_tx,"eNB_thread_phy_tx") < 0) break; From 5eac636b343cd27588543c51d185952c696bdad5 Mon Sep 17 00:00:00 2001 From: naoi Date: Tue, 13 Feb 2018 17:57:44 +0900 Subject: [PATCH 03/18] FIX: E-RAB is removed when UE's status is E_RAB_STATUS_DONE. --- openair2/RRC/LITE/rrc_eNB.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair2/RRC/LITE/rrc_eNB.c b/openair2/RRC/LITE/rrc_eNB.c index e57ed85b6f..94e4c71986 100644 --- a/openair2/RRC/LITE/rrc_eNB.c +++ b/openair2/RRC/LITE/rrc_eNB.c @@ -1448,7 +1448,7 @@ rrc_eNB_process_RRCConnectionReestablishmentComplete( memset(&create_tunnel_req, 0 , sizeof(create_tunnel_req)); for (j = 0, i = 0; i < NB_RB_MAX; i++) { - if (ue_context_pP->ue_context.e_rab[i].status == E_RAB_STATUS_ESTABLISHED) { + if (ue_context_pP->ue_context.e_rab[i].status == E_RAB_STATUS_ESTABLISHED || ue_context_pP->ue_context.e_rab[i].status == E_RAB_STATUS_DONE) { create_tunnel_req.eps_bearer_id[j] = ue_context_pP->ue_context.e_rab[i].param.e_rab_id; create_tunnel_req.sgw_S1u_teid[j] = ue_context_pP->ue_context.e_rab[i].param.gtp_teid; From 1ba01559448a04636caa71b9eece4b5c3e5ac056 Mon Sep 17 00:00:00 2001 From: naoi Date: Tue, 13 Feb 2018 18:22:38 +0900 Subject: [PATCH 04/18] clean: log modification. --- openair1/PHY/LTE_TRANSPORT/pucch.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair1/PHY/LTE_TRANSPORT/pucch.c b/openair1/PHY/LTE_TRANSPORT/pucch.c index c8da27bcb8..c8a4e7fd78 100644 --- a/openair1/PHY/LTE_TRANSPORT/pucch.c +++ b/openair1/PHY/LTE_TRANSPORT/pucch.c @@ -2457,7 +2457,7 @@ uint32_t rx_pucch(PHY_VARS_eNB *eNB, #if defined(USRP_REC_PLAY) LOG_I(PHY,"PUCCH 1a/b: NAK subframe %d : sigma2_dB %d, stat_max %d, pucch1_thres %d\n",subframe,sigma2_dB,dB_fixed(stat_max),pucch1_thres); #else - LOG_I(PHY,"PUCCH 1a/b: subframe %d : sigma2_dB %d, stat_max %d, pucch1_thres %d\n",subframe,sigma2_dB,dB_fixed(stat_max),pucch1_thres); + LOG_D(PHY,"PUCCH 1a/b: subframe %d : sigma2_dB %d, stat_max %d, pucch1_thres %d\n",subframe,sigma2_dB,dB_fixed(stat_max),pucch1_thres); #endif *payload = 4; // DTX ((int16_t*)&eNB->pucch1ab_stats[UE_id][(subframe<<10) + (eNB->pucch1ab_stats_cnt[UE_id][subframe])])[0] = (int16_t)(stat_re); From 4c0a8f88f99385d219ba818b3cac3f6d2ee93bdc Mon Sep 17 00:00:00 2001 From: Masayuki HARADA Date: Thu, 15 Feb 2018 10:58:47 +0900 Subject: [PATCH 05/18] Add fail safe when RF TX thread is busy. --- targets/RT/USER/lte-ru.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/targets/RT/USER/lte-ru.c b/targets/RT/USER/lte-ru.c index ef641f6920..a2b436ef23 100644 --- a/targets/RT/USER/lte-ru.c +++ b/targets/RT/USER/lte-ru.c @@ -1842,6 +1842,10 @@ static void* rf_tx( void* param ) { if (ru->fh_north_out) ru->fh_north_out(ru); } if (release_thread(&proc->mutex_rf_tx,&proc->instance_cnt_rf_tx,"rf_tx") < 0) break; + if(proc->instance_cnt_rf_tx >= 0){ + late_control=STATE_BURST_TERMINATE; + LOG_E(PHY,"detect rf tx busy change mode TX failsafe\n"); + } } LOG_I(PHY, "Exiting rf TX\n"); From 897d3c49df97af6501a3cae9ebf44a8d22f1f4e5 Mon Sep 17 00:00:00 2001 From: naoi Date: Thu, 15 Feb 2018 18:05:40 +0900 Subject: [PATCH 06/18] Fix: avoid conflict between pre-scd thread and ru thread. --- openair2/LAYER2/RLC/AM_v9.3.0/rlc_am.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/openair2/LAYER2/RLC/AM_v9.3.0/rlc_am.c b/openair2/LAYER2/RLC/AM_v9.3.0/rlc_am.c index 881c7b14cc..c8b8bce7aa 100644 --- a/openair2/LAYER2/RLC/AM_v9.3.0/rlc_am.c +++ b/openair2/LAYER2/RLC/AM_v9.3.0/rlc_am.c @@ -551,7 +551,9 @@ rlc_am_mac_status_indication ( rlc->last_absolute_subframe_status_indication = PROTOCOL_CTXT_TIME_MILLI_SECONDS(ctxt_pP); - rlc->nb_bytes_requested_by_mac = tb_sizeP; + if (tb_sizeP > 0) { + rlc->nb_bytes_requested_by_mac = tb_sizeP; + } status_resp.buffer_occupancy_in_bytes = rlc_am_get_buffer_occupancy_in_bytes(ctxt_pP, rlc); From d82ebce55b06adc6e5b8abfe01a0f204b8ad6870 Mon Sep 17 00:00:00 2001 From: Masayuki HARADA Date: Thu, 15 Feb 2018 20:10:08 +0900 Subject: [PATCH 07/18] If TB buffer's all regments recieved is NOT equal RLC's all regments recieved, discard that TB buffer. --- openair2/LAYER2/RLC/AM_v9.3.0/rlc_am_receiver.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/openair2/LAYER2/RLC/AM_v9.3.0/rlc_am_receiver.c b/openair2/LAYER2/RLC/AM_v9.3.0/rlc_am_receiver.c index b1facdfb02..42bdd56e77 100644 --- a/openair2/LAYER2/RLC/AM_v9.3.0/rlc_am_receiver.c +++ b/openair2/LAYER2/RLC/AM_v9.3.0/rlc_am_receiver.c @@ -396,14 +396,20 @@ rlc_am_receive_process_data_pdu ( } if (pdu_info_p->sn == rlc_pP->vr_r) { +mem_block_t* cursor_p = rlc_pP->receiver_buffer.head; +rlc_am_rx_pdu_management_t * pdu_cursor_mgnt_p = (rlc_am_rx_pdu_management_t *) (cursor_p->data); +if( (((rlc_am_rx_pdu_management_t*)(tb_pP->data))->all_segments_received) == (pdu_cursor_mgnt_p->all_segments_received)){ if (((rlc_am_rx_pdu_management_t*)(tb_pP->data))->all_segments_received) { rlc_am_rx_update_vr_r(ctxt_pP, rlc_pP, tb_pP); rlc_pP->vr_mr = (rlc_pP->vr_r + RLC_AM_WINDOW_SIZE) & RLC_AM_SN_MASK; } - reassemble = rlc_am_rx_check_vr_reassemble(ctxt_pP, rlc_pP); //TODO : optimization : check whether a reassembly is needed by looking at LI, FI, SO, etc... - +}else{ + LOG_E(RLC, "BAD all_segments_received!!! discard buffer!!!\n"); + /* Discard received block if out of window, duplicate or header error */ + free_mem_block (tb_pP, __func__); +} } //FNA: fix check VrX out of receiving window From de35844c424d8ea8f5222877986595394649ec2e Mon Sep 17 00:00:00 2001 From: Masayuki HARADA Date: Thu, 15 Feb 2018 20:23:54 +0900 Subject: [PATCH 08/18] Change priority of itti thread. --- common/utils/itti/intertask_interface.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/utils/itti/intertask_interface.c b/common/utils/itti/intertask_interface.c index 387d37d61d..a1bb6b072f 100644 --- a/common/utils/itti/intertask_interface.c +++ b/common/utils/itti/intertask_interface.c @@ -782,7 +782,7 @@ void itti_mark_task_ready(task_id_t task_id) /* Mark the thread as using LFDS queue */ lfds611_queue_use(itti_desc.tasks[task_id].message_queue); -#ifdef RTAI +#if defined(UE_EXPANSION) || defined(RTAI) /* Assign low priority to created threads */ { struct sched_param sched_param; From 497a3275c62d397e8659961b64bc34081c2806ed Mon Sep 17 00:00:00 2001 From: naoi Date: Thu, 22 Feb 2018 10:17:34 +0900 Subject: [PATCH 09/18] fix: drop reestablishment request after UL failure is detected in layer2. eNB should be keep UE context longer than T311 timer after UL failure is detected in layer2. Configuration file(GENERIC-LTE-EPC) sets T311 to 10s, so eNB keep UE context up to 20s. --- openair2/LAYER2/MAC/eNB_scheduler_ulsch.c | 2 +- openair2/RRC/LITE/rrc_common.c | 6 +++--- openair2/RRC/LITE/rrc_eNB.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c b/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c index 6612fb25b9..0e4bbb84f1 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c @@ -302,7 +302,7 @@ rx_sdu(const module_id_t enb_mod_idP, // prepare transmission of Msg4(RRCConnectionReconfiguration) ra->state = MSGCRNTI; LOG_I(MAC, - "[eNB %d] Frame %d, Subframe %d CC_id %d : (rnti %x UE_id %d) RRCConnectionReconfiguration(Msg4)", + "[eNB %d] Frame %d, Subframe %d CC_id %d : (rnti %x UE_id %d) RRCConnectionReconfiguration(Msg4)\n", enb_mod_idP, frameP, subframeP, CC_idP, old_rnti, old_UE_id); // UE_id = old_UE_id; diff --git a/openair2/RRC/LITE/rrc_common.c b/openair2/RRC/LITE/rrc_common.c index aad423418a..8bd3638f5a 100644 --- a/openair2/RRC/LITE/rrc_common.c +++ b/openair2/RRC/LITE/rrc_common.c @@ -350,7 +350,7 @@ rrc_rx_tx( } if (ue_context_p->ue_context.ul_failure_timer>0) { ue_context_p->ue_context.ul_failure_timer++; - if (ue_context_p->ue_context.ul_failure_timer >= 8) { + if (ue_context_p->ue_context.ul_failure_timer >= 20000) { // remove UE after 20 seconds after MAC has indicated UL failure LOG_I(RRC,"Removing UE %x instance\n",ue_context_p->ue_context.rnti); ue_to_be_removed = ue_context_p; @@ -515,14 +515,14 @@ rrc_rx_tx( } } if (ue_to_be_removed) { - if(ue_to_be_removed->ue_context.ul_failure_timer >= 8) { + if(ue_to_be_removed->ue_context.ul_failure_timer >= 20000) { ue_to_be_removed->ue_context.ue_release_timer_s1 = 1; ue_to_be_removed->ue_context.ue_release_timer_thres_s1 = 200; ue_to_be_removed->ue_context.ue_release_timer = 0; ue_to_be_removed->ue_context.ue_reestablishment_timer = 0; } rrc_eNB_free_UE(ctxt_pP->module_id,ue_to_be_removed); - if(ue_to_be_removed->ue_context.ul_failure_timer >= 8){ + if(ue_to_be_removed->ue_context.ul_failure_timer >= 20000){ ue_to_be_removed->ue_context.ul_failure_timer = 0; } } diff --git a/openair2/RRC/LITE/rrc_eNB.c b/openair2/RRC/LITE/rrc_eNB.c index 94e4c71986..0772e76b74 100644 --- a/openair2/RRC/LITE/rrc_eNB.c +++ b/openair2/RRC/LITE/rrc_eNB.c @@ -822,7 +822,7 @@ rrc_eNB_free_UE(const module_id_t enb_mod_idP,const struct rrc_eNB_ue_context_s* LOG_W(RRC, "[eNB %d] Removing UE RNTI %x\n", enb_mod_idP, rnti); #if defined(ENABLE_USE_MME) - if( ue_context_pP->ue_context.ul_failure_timer >= 8 ) { + if( ue_context_pP->ue_context.ul_failure_timer >= 20000 ) { LOG_I(RRC, "[eNB %d] S1AP_UE_CONTEXT_RELEASE_REQ RNTI %x\n", enb_mod_idP, rnti); rrc_eNB_send_S1AP_UE_CONTEXT_RELEASE_REQ(enb_mod_idP, ue_context_pP, S1AP_CAUSE_RADIO_NETWORK, 21); // send cause 21: connection with ue lost /* From 3GPP 36300v10 p129 : 19.2.2.2.2 S1 UE Context Release Request (eNB triggered) From 59623646cfb22e16c9c080931f7ae55d84661fdb Mon Sep 17 00:00:00 2001 From: Masayuki HARADA Date: Thu, 22 Feb 2018 11:11:15 +0900 Subject: [PATCH 10/18] Avoid NULL access in rrc_eNB_process_RRCConnectionReestablishmentComplete. --- openair2/RRC/LITE/rrc_eNB.c | 80 ++++++++++++++++++++++--------------- 1 file changed, 47 insertions(+), 33 deletions(-) diff --git a/openair2/RRC/LITE/rrc_eNB.c b/openair2/RRC/LITE/rrc_eNB.c index 94e4c71986..0c9f9e08ea 100644 --- a/openair2/RRC/LITE/rrc_eNB.c +++ b/openair2/RRC/LITE/rrc_eNB.c @@ -1371,8 +1371,10 @@ rrc_eNB_process_RRCConnectionReestablishmentComplete( SRB_configList2 = &ue_context_pP->ue_context.SRB_configList2[xid]; // get old configuration of SRB2 if (*SRB_configList2 != NULL) { - LOG_D(RRC, "SRB_configList2(%p) count is %d\n SRB_configList2->list.array[0] addr is %p", + if((*SRB_configList2)->list.count!=0){ + LOG_D(RRC, "SRB_configList2(%p) count is %d\n SRB_configList2->list.array[0] addr is %p", SRB_configList2, (*SRB_configList2)->list.count, (*SRB_configList2)->list.array[0]); + } for (i = 0; (i < (*SRB_configList2)->list.count) && (i < 3); i++) { if ((*SRB_configList2)->list.array[i]->srb_Identity == 2 ){ LOG_D(RRC, "get SRB2_config from (ue_context_pP->ue_context.SRB_configList2[%d])\n", xid); @@ -1384,9 +1386,13 @@ rrc_eNB_process_RRCConnectionReestablishmentComplete( SRB_configList2 = &ue_context_pP->ue_context.SRB_configList2[next_xid]; DRB_configList2 = &ue_context_pP->ue_context.DRB_configList2[next_xid]; - if (*SRB_configList2) { - free(*SRB_configList2); - LOG_D(RRC, "free(ue_context_pP->ue_context.SRB_configList2[%d])\n", next_xid); + if(SRB_configList2!=NULL){ + if (*SRB_configList2) { + free(*SRB_configList2); + LOG_D(RRC, "free(ue_context_pP->ue_context.SRB_configList2[%d])\n", next_xid); + } + }else{ + LOG_E(RRC, "SRB_configList2 is null\n"); } *SRB_configList2 = CALLOC(1, sizeof(**SRB_configList2)); if (SRB2_config != NULL) { @@ -1406,9 +1412,13 @@ rrc_eNB_process_RRCConnectionReestablishmentComplete( - if (*DRB_configList2) { - free(*DRB_configList2); - LOG_D(RRC, "free(ue_context_pP->ue_context.DRB_configList2[%d])\n", next_xid); + if(DRB_configList2!=NULL){ + if (*DRB_configList2) { + free(*DRB_configList2); + LOG_D(RRC, "free(ue_context_pP->ue_context.DRB_configList2[%d])\n", next_xid); + } + }else{ + LOG_E(RRC, "DRB_configList2 is null\n"); } *DRB_configList2 = CALLOC(1, sizeof(**DRB_configList2)); @@ -1863,35 +1873,39 @@ rrc_eNB_process_RRCConnectionReestablishmentComplete( } #endif + if(size==65535){ + LOG_E(RRC,"RRC decode err!!! do_RRCConnectionReconfiguration\n"); + put_UE_in_freelist(ctxt_pP->module_id, reestablish_rnti, 0); + return; + }else{ + LOG_I(RRC, + "[eNB %d] Frame %d, Logical Channel DL-DCCH, Generate RRCConnectionReconfiguration (bytes %d, UE id %x)\n", + ctxt_pP->module_id, ctxt_pP->frame, size, ue_context_pP->ue_context.rnti); - LOG_I(RRC, - "[eNB %d] Frame %d, Logical Channel DL-DCCH, Generate RRCConnectionReconfiguration (bytes %d, UE id %x)\n", - ctxt_pP->module_id, ctxt_pP->frame, size, ue_context_pP->ue_context.rnti); + LOG_D(RRC, + "[FRAME %05d][RRC_eNB][MOD %u][][--- PDCP_DATA_REQ/%d Bytes (rrcConnectionReconfiguration to UE %x MUI %d) --->][PDCP][MOD %u][RB %u]\n", + ctxt_pP->frame, ctxt_pP->module_id, size, ue_context_pP->ue_context.rnti, rrc_eNB_mui, ctxt_pP->module_id, DCCH); - LOG_D(RRC, - "[FRAME %05d][RRC_eNB][MOD %u][][--- PDCP_DATA_REQ/%d Bytes (rrcConnectionReconfiguration to UE %x MUI %d) --->][PDCP][MOD %u][RB %u]\n", - ctxt_pP->frame, ctxt_pP->module_id, size, ue_context_pP->ue_context.rnti, rrc_eNB_mui, ctxt_pP->module_id, DCCH); - - MSC_LOG_TX_MESSAGE( - MSC_RRC_ENB, - MSC_RRC_UE, - buffer, - size, - MSC_AS_TIME_FMT" rrcConnectionReconfiguration UE %x MUI %d size %u", - MSC_AS_TIME_ARGS(ctxt_pP), - ue_context_pP->ue_context.rnti, - rrc_eNB_mui, - size); - - rrc_data_req( - ctxt_pP, - DCCH, - rrc_eNB_mui++, - SDU_CONFIRM_NO, - size, - buffer, - PDCP_TRANSMISSION_MODE_CONTROL); + MSC_LOG_TX_MESSAGE( + MSC_RRC_ENB, + MSC_RRC_UE, + buffer, + size, + MSC_AS_TIME_FMT" rrcConnectionReconfiguration UE %x MUI %d size %u", + MSC_AS_TIME_ARGS(ctxt_pP), + ue_context_pP->ue_context.rnti, + rrc_eNB_mui, + size); + rrc_data_req( + ctxt_pP, + DCCH, + rrc_eNB_mui++, + SDU_CONFIRM_NO, + size, + buffer, + PDCP_TRANSMISSION_MODE_CONTROL); + } // delete UE data of prior RNTI. UE use current RNTI. // protocol_ctxt_t ctxt_prior = *ctxt_pP; // ctxt_prior.rnti = reestablish_rnti; From 2d975ca61b7143f24f452a95fa5a0c860d0f935d Mon Sep 17 00:00:00 2001 From: Masayuki HARADA Date: Thu, 22 Feb 2018 22:11:44 +0900 Subject: [PATCH 11/18] Change scheduling priority : UL-SCH == MAC-CE --- openair2/LAYER2/MAC/pre_processor.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/openair2/LAYER2/MAC/pre_processor.c b/openair2/LAYER2/MAC/pre_processor.c index f5980d60d3..b341c9ca3c 100644 --- a/openair2/LAYER2/MAC/pre_processor.c +++ b/openair2/LAYER2/MAC/pre_processor.c @@ -2511,7 +2511,15 @@ void ulsch_scheduler_pre_ue_select( ue_first_num[CC_id]++; continue; } - if ( (ulsch_ue_select[CC_id].ue_num+ul_inactivity_num[CC_id] ) < ulsch_ue_max_num[CC_id] ) { + UE_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; + if ( ((UE_sched_ctl->ul_inactivity_timer>20)&&(UE_sched_ctl->ul_scheduled==0)) || + ((UE_sched_ctl->ul_inactivity_timer>10)&&(UE_sched_ctl->ul_scheduled==0)&&(mac_eNB_get_rrc_status(module_idP,UE_RNTI(module_idP,UE_id)) < RRC_CONNECTED))) { + first_ue_id[CC_id][ue_first_num[CC_id]]= UE_id; + first_ue_total[CC_id] [ue_first_num[CC_id]] = 0; + ue_first_num[CC_id]++; + continue; + } + /*if ( (ulsch_ue_select[CC_id].ue_num+ul_inactivity_num[CC_id] ) < ulsch_ue_max_num[CC_id] ) { UE_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; if ( ((UE_sched_ctl->ul_inactivity_timer>20)&&(UE_sched_ctl->ul_scheduled==0)) || ((UE_sched_ctl->ul_inactivity_timer>10)&&(UE_sched_ctl->ul_scheduled==0)&&(mac_eNB_get_rrc_status(module_idP,UE_RNTI(module_idP,UE_id)) < RRC_CONNECTED))) { @@ -2519,7 +2527,7 @@ void ulsch_scheduler_pre_ue_select( ul_inactivity_num[CC_id] ++; continue; } - } + }*/ } } @@ -2594,7 +2602,10 @@ void ulsch_scheduler_pre_ue_select( HI_DCI0_req = &eNB->HI_DCI0_req[CC_id].hi_dci0_request_body; //SR BSR - if ( (UE_list->UE_template[CC_id][UE_id].ul_total_buffer > 0) || (UE_list->UE_template[CC_id][UE_id].ul_SR > 0) ) { + UE_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; + if ( (UE_list->UE_template[CC_id][UE_id].ul_total_buffer > 0) || (UE_list->UE_template[CC_id][UE_id].ul_SR > 0) || + ((UE_sched_ctl->ul_inactivity_timer>20)&&(UE_sched_ctl->ul_scheduled==0)) || + ((UE_sched_ctl->ul_inactivity_timer>10)&&(UE_sched_ctl->ul_scheduled==0)&&(mac_eNB_get_rrc_status(module_idP,UE_RNTI(module_idP,UE_id)) < RRC_CONNECTED)) ){ hi_dci0_pdu = &HI_DCI0_req->hi_dci0_pdu_list[HI_DCI0_req->number_of_dci+HI_DCI0_req->number_of_hi]; format_flag = 2; if (CCE_allocation_infeasible(module_idP,CC_id,format_flag,subframeP,aggregation,rnti) == 1) { @@ -2617,7 +2628,7 @@ void ulsch_scheduler_pre_ue_select( } } //inactivity UE - if ( (ulsch_ue_select[CC_id].ue_num+ul_inactivity_num[CC_id]) < ulsch_ue_max_num[CC_id] ) { +/* if ( (ulsch_ue_select[CC_id].ue_num+ul_inactivity_num[CC_id]) < ulsch_ue_max_num[CC_id] ) { UE_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; if ( ((UE_sched_ctl->ul_inactivity_timer>20)&&(UE_sched_ctl->ul_scheduled==0)) || ((UE_sched_ctl->ul_inactivity_timer>10)&&(UE_sched_ctl->ul_scheduled==0)&&(mac_eNB_get_rrc_status(module_idP,UE_RNTI(module_idP,UE_id)) < RRC_CONNECTED))) { @@ -2625,7 +2636,7 @@ void ulsch_scheduler_pre_ue_select( ul_inactivity_num[CC_id]++; continue; } - } + }*/ } for ( CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++ ) { From c9f89db89bf63cc624a4edf2cadda79efe379829 Mon Sep 17 00:00:00 2001 From: Cedric Roux Date: Wed, 3 Jan 2018 11:19:54 +0100 Subject: [PATCH 12/18] hotfix: clear DCI padding bits The problem is the following (as reported by an user): "one UE is attached to OAI system. UE is near the antenna. Try to detach the UE and attach again. Repeat this procedure for 5-6 times. OAI system does not work and any the UE can not attach to this system. I use TEMS software and I can see MIB signaling on this UE but UE can not decode SIB1 and SIB2." What happens is that the DCI for SIB1 and SIB2 is not cleared before use. That is the bits in the 'padding' field keep the values that were set before. If the structure has been used to transmit other DCIs (eg. for UEs) in the past, it may be reused with some of those bits set to 1. When receiving this DCI, the UE won't accept it because it gets some bits at 1 where it expects them to be 0. The short-term/quick solution is to clear the 'padding' field. A better solution would be to rewrite this part of the code, which is way too complicated for what it does. But this takes too much time. In dci.h the field 'dummy' of some structures was renamed to 'padding'. The fields 'padding32' and 'padding64' were also renamed to 'padding' for consistency. Some structures (DCI2B_1_5MHz_TDD, DCI2B_10MHz_FDD, DCI2D_1_5MHz_FDD, DCI2D_5MHz_FDD, DCI2D_10MHz_FDD) had a 'padding' field at the end, which was renamed to 'padding0'. I don't know if this field should be here at all. To me this field looks very suspicious. When we test DCIs 2B and 2D we should be careful. (cherry picked from commit c5ca2bd86227d958175f2a5569546c1d60179d07) --- openair1/PHY/LTE_TRANSPORT/dci.h | 140 ++++++++++++------------- openair1/PHY/LTE_TRANSPORT/dci_tools.c | 88 ++++++++++++---- 2 files changed, 135 insertions(+), 93 deletions(-) diff --git a/openair1/PHY/LTE_TRANSPORT/dci.h b/openair1/PHY/LTE_TRANSPORT/dci.h index 0e74324b2c..9381dd63fd 100644 --- a/openair1/PHY/LTE_TRANSPORT/dci.h +++ b/openair1/PHY/LTE_TRANSPORT/dci.h @@ -482,8 +482,8 @@ typedef struct DCI1A_20MHz_FDD DCI1A_20MHz_FDD_t; /// DCI Format Type 1 (1.5 MHz, TDD, 23 bits) struct DCI1_1_5MHz_TDD { - /// Dummy bits to align to 32-bits - uint32_t dummy:9; + /// padding bits to align to 32-bits + uint32_t padding:9; /// DAI (TDD) uint32_t dai:2; /// Power Control @@ -507,8 +507,8 @@ typedef struct DCI1_1_5MHz_TDD DCI1_1_5MHz_TDD_t; /// DCI Format Type 1 (5 MHz, TDD, 30 bits) struct DCI1_5MHz_TDD { - /// Dummy bits to align to 32-bits - uint32_t dummy:2; + /// padding bits to align to 32-bits + uint32_t padding:2; /// DAI (TDD) uint32_t dai:2; /// Power Control @@ -532,8 +532,8 @@ typedef struct DCI1_5MHz_TDD DCI1_5MHz_TDD_t; /// DCI Format Type 1 (10 MHz, TDD, 34 bits) struct DCI1_10MHz_TDD { - /// Dummy bits to align to 64-bits - uint64_t dummy:30; + /// padding bits to align to 64-bits + uint64_t padding:30; /// DAI (TDD) uint64_t dai:2; /// Power Control @@ -557,8 +557,8 @@ typedef struct DCI1_10MHz_TDD DCI1_10MHz_TDD_t; /// DCI Format Type 1 (20 MHz, TDD, 42 bits) struct DCI1_20MHz_TDD { - /// Dummy bits to align to 64-bits - uint64_t dummy:22; + /// padding bits to align to 64-bits + uint64_t padding:22; /// DAI (TDD) uint64_t dai:2; /// Power Control @@ -582,8 +582,8 @@ typedef struct DCI1_20MHz_TDD DCI1_20MHz_TDD_t; /// DCI Format Type 1 (1.5 MHz, FDD, 21 bits) struct DCI1_1_5MHz_FDD { - /// Dummy bits to align to 32-bits - uint32_t dummy:11; + /// padding bits to align to 32-bits + uint32_t padding:11; /// Power Control uint32_t TPC:2; /// Redundancy version @@ -605,8 +605,8 @@ typedef struct DCI1_1_5MHz_FDD DCI1_1_5MHz_FDD_t; /// DCI Format Type 1 (5 MHz, FDD, 27 bits) struct DCI1_5MHz_FDD { - /// dummy bits (not transmitted) - uint32_t dummy:5; + /// padding its (not transmitted) + uint32_t padding:5; /// Power Control uint32_t TPC:2; /// Redundancy version @@ -628,8 +628,8 @@ typedef struct DCI1_5MHz_FDD DCI1_5MHz_FDD_t; /// DCI Format Type 1 (10 MHz, FDD, 31 bits) struct DCI1_10MHz_FDD { - /// dummy bits (not transmitted) - uint32_t dummy:1; + /// padding bits (not transmitted) + uint32_t padding:1; /// Power Control uint32_t TPC:2; /// Redundancy version @@ -651,8 +651,8 @@ typedef struct DCI1_10MHz_FDD DCI1_10MHz_FDD_t; /// DCI Format Type 1 (20 MHz, FDD, 39 bits) struct DCI1_20MHz_FDD { - /// dummy bits (not transmitted) - uint64_t dummy:25; + /// padding bits (not transmitted) + uint64_t padding:25; /// Power Control uint64_t TPC:2; /// Redundancy version @@ -674,10 +674,8 @@ typedef struct DCI1_20MHz_FDD DCI1_20MHz_FDD_t; /// DCI Format Type 1A (5 MHz, TDD, frame 1-6, 27 bits) struct DCI1A_RA_5MHz_TDD_1_6 { - /// Dummy bits to align to 32-bits - uint32_t dummy:5; - /// Padding - uint32_t padding:6; + /// padding bits to align to 32-bits + uint32_t padding:11; /// PRACH mask index uint32_t prach_mask_index:4; /// Preamble Index @@ -822,7 +820,7 @@ typedef struct DCI1B_5MHz_4A_TDD DCI1B_5MHz_4A_TDD_t; struct DCI1C_1_5MHz { /// padding to 32bits - uint32_t padding32:24; + uint32_t padding:24; uint32_t mcs:5; uint32_t rballoc:3; // N_RB_step = 2, Ngap=Ngap1=3, NDLVRBGap = 6, ceil(log2((3*4)/2)) = 3 } __attribute__ ((__packed__)); @@ -836,7 +834,7 @@ typedef struct DCI1C_1_5MHz DCI1C_1_5MHz_t; struct DCI1C_5MHz { /// padding to 32bits - uint32_t padding32:20; + uint32_t padding:20; uint32_t mcs:5; uint32_t rballoc:7; // N_RB_step = 2, Ngap1=Ngap2=12, NDLVRBGap = 24, ceil(log2((12*13)/2)) = 7 } __attribute__ ((__packed__)); @@ -848,7 +846,7 @@ typedef struct DCI1C_5MHz DCI1C_5MHz_t; struct DCI1C_10MHz { /// padding to 32bits - uint32_t padding32:19; + uint32_t padding:19; uint32_t mcs:5; uint32_t rballoc:7; // N_RB_step = 4, Ngap1=27, NDLVRBGap = 46, ceil(log2(((11*12)/2)) = 7 uint32_t Ngap:1; @@ -861,7 +859,7 @@ typedef struct DCI1C_10MHz DCI1C_10MHz_t; struct DCI1C_15MHz { /// padding to 32bits - uint32_t padding32:18; + uint32_t padding:18; uint32_t mcs:5; uint32_t rballoc:8; // N_RB_step = 4, Ngap1=64, ceil(log2((16*17)/2)) = 8 uint32_t Ngap:1; @@ -874,7 +872,7 @@ typedef struct DCI1C_15MHz DCI1C_15MHz_t; struct DCI1C_20MHz { /// padding to 32bits - uint32_t padding32:17; + uint32_t padding:17; uint32_t mcs:5; uint32_t rballoc:9; // N_RB_step = 4, Ngap1=48, ceil(log2((24*25)/2)) = 9 uint32_t Ngap:1; @@ -1006,7 +1004,7 @@ typedef struct DCI1D_5MHz_4A_TDD DCI1D_5MHz_4A_TDD_t; /// DCI Format Type 1E (5 MHz, TDD, 2 Antenna Ports, more than 10 PRBs, 34 bits) struct DCI1E_5MHz_2A_M10PRB_TDD { /// padding to 64bits - uint64_t padding64:30; + uint64_t padding:30; /// Redundancy version 2 ///uint64_t rv2:2; /// New Data Indicator 2 @@ -1045,7 +1043,7 @@ typedef struct DCI1E_5MHz_2A_M10PRB_TDD DCI1E_5MHz_2A_M10PRB_TDD_t; /// DCI Format Type 2 (1.5 MHz, TDD, 2 Antenna Ports, 34 bits) struct DCI2_1_5MHz_2A_TDD { /// padding to 64bits - uint64_t padding64:30; + uint64_t padding:30; /// TPMI information for precoding uint64_t tpmi:3; /// Redundancy version 2 @@ -1078,7 +1076,7 @@ typedef struct DCI2_1_5MHz_2A_TDD DCI2_1_5MHz_2A_TDD_t; /// DCI Format Type 2 (1.5 MHz, TDD, 4 Antenna Ports, 37 bits) struct DCI2_1_5MHz_4A_TDD { /// padding for 64-bit - uint64_t padding64:27; + uint64_t padding:27; /// TPMI information for precoding uint64_t tpmi:6; /// Redundancy version 2 @@ -1111,7 +1109,7 @@ typedef struct DCI2_1_5MHz_4A_TDD DCI2_1_5MHz_4A_TDD_t; /// DCI Format Type 2 (5 MHz, TDD, 2 Antenna Ports, 42 bits) struct DCI2_5MHz_2A_TDD { /// padding to 64bits - uint64_t padding64:22; + uint64_t padding:22; /// TPMI information for precoding uint64_t tpmi:3; /// Redundancy version 2 @@ -1146,7 +1144,7 @@ typedef struct DCI2_5MHz_2A_TDD DCI2_5MHz_2A_TDD_t; /// DCI Format Type 2 (5 MHz, TDD, 4 Antenna Ports, 45 bits) struct DCI2_5MHz_4A_TDD { /// padding for 64-bit - uint64_t padding64:19; + uint64_t padding:19; /// TPMI information for precoding uint64_t tpmi:6; /// Redundancy version 2 @@ -1181,7 +1179,7 @@ typedef struct DCI2_5MHz_4A_TDD DCI2_5MHz_4A_TDD_t; /// DCI Format Type 2 (10 MHz, TDD, 2 Antenna Ports, 46 bits) struct DCI2_10MHz_2A_TDD { /// padding to 64bits - uint64_t padding64:18; + uint64_t padding:18; /// TPMI information for precoding uint64_t tpmi:3; /// Redundancy version 2 @@ -1216,7 +1214,7 @@ typedef struct DCI2_10MHz_2A_TDD DCI2_10MHz_2A_TDD_t; /// DCI Format Type 2 (10 MHz, TDD, 4 Antenna Ports, 49 bits) struct DCI2_10MHz_4A_TDD { /// padding for 64-bit - uint64_t padding64:15; + uint64_t padding:15; /// TPMI information for precoding uint64_t tpmi:6; /// Redundancy version 2 @@ -1251,7 +1249,7 @@ typedef struct DCI2_10MHz_4A_TDD DCI2_10MHz_4A_TDD_t; /// DCI Format Type 2 (20 MHz, TDD, 2 Antenna Ports, 54 bits) struct DCI2_20MHz_2A_TDD { /// padding to 64bits - uint64_t padding64:10; + uint64_t padding:10; /// TPMI information for precoding uint64_t tpmi:3; /// Redundancy version 2 @@ -1286,7 +1284,7 @@ typedef struct DCI2_20MHz_2A_TDD DCI2_20MHz_2A_TDD_t; /// DCI Format Type 2 (20 MHz, TDD, 4 Antenna Ports, 57 bits) struct DCI2_20MHz_4A_TDD { /// padding for 64-bit - uint64_t padding64:7; + uint64_t padding:7; /// TPMI information for precoding uint64_t tpmi:6; /// Redundancy version 2 @@ -1321,7 +1319,7 @@ typedef struct DCI2_20MHz_4A_TDD DCI2_20MHz_4A_TDD_t; /// DCI Format Type 2 (1.5 MHz, FDD, 2 Antenna Ports, 31 bits) struct DCI2_1_5MHz_2A_FDD { //padding for 32 bits - uint32_t padding32:1; + uint32_t padding:1; /// precoding bits uint32_t tpmi:3; /// Redundancy version 2 @@ -1352,7 +1350,7 @@ typedef struct DCI2_1_5MHz_2A_FDD DCI2_1_5MHz_2A_FDD_t; /// DCI Format Type 2 (1.5 MHz, FDD, 4 Antenna Ports, 34 bits) struct DCI2_1_5MHz_4A_FDD { /// padding for 32 bits - uint64_t padding64:30; + uint64_t padding:30; /// precoding bits uint64_t tpmi:6; /// Redundancy version 2 @@ -1383,7 +1381,7 @@ typedef struct DCI2_1_5MHz_4A_FDD DCI2_1_5MHz_4A_FDD_t; /// DCI Format Type 2 (5 MHz, FDD, 2 Antenna Ports, 39 bits) struct DCI2_5MHz_2A_FDD { /// padding for 64-bit - uint64_t padding64:25; + uint64_t padding:25; /// TPMI information for precoding uint64_t tpmi:3; /// Redundancy version 2 @@ -1416,7 +1414,7 @@ typedef struct DCI2_5MHz_2A_FDD DCI2_5MHz_2A_FDD_t; /// DCI Format Type 2 (5 MHz, TDD, 4 Antenna Ports, 42 bits) struct DCI2_5MHz_4A_FDD { /// padding for 64-bit - uint64_t padding64:21; + uint64_t padding:21; /// TPMI information for precoding uint64_t tpmi:6; /// Redundancy version 2 @@ -1448,7 +1446,7 @@ typedef struct DCI2_5MHz_4A_FDD DCI2_5MHz_4A_FDD_t; /// DCI Format Type 2 (10 MHz, FDD, 2 Antenna Ports, 43 bits) struct DCI2_10MHz_2A_FDD { /// padding for 64-bit - uint64_t padding64:21; + uint64_t padding:21; /// TPMI information for precoding uint64_t tpmi:3; /// Redundancy version 2 @@ -1481,7 +1479,7 @@ typedef struct DCI2_10MHz_2A_FDD DCI2_10MHz_2A_FDD_t; /// DCI Format Type 2 (5 MHz, TDD, 4 Antenna Ports, 46 bits) struct DCI2_10MHz_4A_FDD { /// padding for 64-bit - uint64_t padding64:18; + uint64_t padding:18; /// TPMI information for precoding uint64_t tpmi:6; /// Redundancy version 2 @@ -1513,7 +1511,7 @@ typedef struct DCI2_10MHz_4A_FDD DCI2_10MHz_4A_FDD_t; /// DCI Format Type 2 (20 MHz, FDD, 2 Antenna Ports, 51 bits) struct DCI2_20MHz_2A_FDD { /// padding for 64-bit - uint64_t padding64:13; + uint64_t padding:13; /// TPMI information for precoding uint64_t tpmi:3; /// Redundancy version 2 @@ -1546,7 +1544,7 @@ typedef struct DCI2_20MHz_2A_FDD DCI2_20MHz_2A_FDD_t; /// DCI Format Type 2 (20 MHz, FDD, 4 Antenna Ports, 54 bits) struct DCI2_20MHz_4A_FDD { /// padding for 64-bit - uint64_t padding64:10; + uint64_t padding:10; /// TPMI information for precoding uint64_t tpmi:6; /// Redundancy version 2 @@ -2083,7 +2081,7 @@ typedef struct DCI2A_20MHz_4A_FDD DCI2A_20MHz_4A_FDD_t; // ******************************************************************* /// DCI Format Type 2B (1.5 MHz, TDD, 33 bits) struct DCI2B_1_5MHz_TDD { - uint64_t padding64:31; + uint64_t padding:31; /// Redundancy version 2 uint64_t rv2:2; /// New Data Indicator 2 @@ -2109,7 +2107,7 @@ struct DCI2B_1_5MHz_TDD { /// RB Assignment (ceil(log2(N_RB_DL/P)) bits) uint64_t rballoc:6; /// Padding for ambiguity - uint64_t padding:1; + uint64_t padding0:1; } __attribute__ ((__packed__)); typedef struct DCI2B_1_5MHz_TDD DCI2B_1_5MHz_TDD_t; @@ -2118,7 +2116,7 @@ typedef struct DCI2B_1_5MHz_TDD DCI2B_1_5MHz_TDD_t; /// DCI Format Type 2B (5 MHz, TDD, 39 bits) struct DCI2B_5MHz_TDD { /// padding to 64bits - uint64_t padding64:25; + uint64_t padding:25; /// Redundancy version 2 uint64_t rv2:2; /// New Data Indicator 2 @@ -2153,7 +2151,7 @@ typedef struct DCI2B_5MHz_TDD DCI2B_5MHz_TDD_t; /// DCI Format Type 2B (10 MHz, TDD, 43 bits) struct DCI2B_10MHz_TDD { /// padding to 64bits - uint64_t padding64:21; + uint64_t padding:21; /// Redundancy version 2 uint64_t rv2:2; /// New Data Indicator 2 @@ -2188,7 +2186,7 @@ typedef struct DCI2B_10MHz_TDD DCI2B_10MHz_TDD_t; /// DCI Format Type 2B (20 MHz, TDD, 51 bits) struct DCI2B_20MHz_TDD { /// padding to 64bits - uint64_t padding64:13; + uint64_t padding:13; /// Redundancy version 2 uint64_t rv2:2; /// New Data Indicator 2 @@ -2223,7 +2221,7 @@ typedef struct DCI2B_20MHz_TDD DCI2B_20MHz_TDD_t; /// DCI Format Type 2B (1.5 MHz, FDD, 28 bits) struct DCI2B_1_5MHz_FDD { //padding for 32 bits - uint32_t padding32:4; + uint32_t padding:4; /// Redundancy version 2 uint32_t rv2:2; /// New Data Indicator 2 @@ -2252,7 +2250,7 @@ typedef struct DCI2B_1_5MHz_FDD DCI2B_1_5MHz_FDD_t; /// DCI Format Type 2B (5 MHz, FDD, 36 bits) struct DCI2B_5MHz_FDD { /// padding for 64-bit - uint64_t padding64:28; + uint64_t padding:28; /// Redundancy version 2 uint64_t rv2:2; /// New Data Indicator 2 @@ -2283,7 +2281,7 @@ typedef struct DCI2B_5MHz_FDD DCI2B_5MHz_FDD_t; /// DCI Format Type 2B (10 MHz, FDD, 41 bits) struct DCI2B_10MHz_FDD { /// padding for 64-bit - uint64_t padding64:23; + uint64_t padding:23; /// Redundancy version 2 uint64_t rv2:2; /// New Data Indicator 2 @@ -2307,7 +2305,7 @@ struct DCI2B_10MHz_FDD { /// Resource Allocation Header uint64_t rah:1; /// Padding for ambiguity - uint64_t padding:1; + uint64_t padding0:1; } __attribute__ ((__packed__)); #define sizeof_DCI2B_10MHz_FDD_t 41 @@ -2316,7 +2314,7 @@ typedef struct DCI2B_10MHz_FDD DCI2B_10MHz_FDD_t; /// DCI Format Type 2B (20 MHz, FDD, 48 bits) struct DCI2B_20MHz_FDD { /// padding for 64-bit - uint64_t padding64:16; + uint64_t padding:16; /// Redundancy version 2 uint64_t rv2:2; /// New Data Indicator 2 @@ -2350,7 +2348,7 @@ typedef struct DCI2B_20MHz_FDD DCI2B_20MHz_FDD_t; /// DCI Format Type 2C (1.5 MHz, TDD, 34 bits) struct DCI2C_1_5MHz_TDD { - uint64_t padding64:30; + uint64_t padding:30; /// Redundancy version 2 uint64_t rv2:2; /// New Data Indicator 2 @@ -2383,7 +2381,7 @@ typedef struct DCI2C_1_5MHz_TDD DCI2C_1_5MHz_TDD_t; /// DCI Format Type 2C (5 MHz, TDD, 41 bits) struct DCI2C_5MHz_TDD { /// padding to 64bits - uint64_t padding64:23; + uint64_t padding:23; /// Redundancy version 2 uint64_t rv2:2; /// New Data Indicator 2 @@ -2418,7 +2416,7 @@ typedef struct DCI2C_5MHz_TDD DCI2C_5MHz_TDD_t; /// DCI Format Type 2C (10 MHz, TDD, 45 bits) struct DCI2C_10MHz_TDD { /// padding to 64bits - uint64_t padding64:19; + uint64_t padding:19; /// Redundancy version 2 uint64_t rv2:2; /// New Data Indicator 2 @@ -2453,7 +2451,7 @@ typedef struct DCI2C_10MHz_TDD DCI2C_10MHz_TDD_t; /// DCI Format Type 2C (20 MHz, TDD, 53 bits) struct DCI2C_20MHz_TDD { /// padding to 64bits - uint64_t padding64:11; + uint64_t padding:11; /// Redundancy version 2 uint64_t rv2:2; /// New Data Indicator 2 @@ -2488,7 +2486,7 @@ typedef struct DCI2C_20MHz_TDD DCI2C_20MHz_TDD_t; /// DCI Format Type 2C (1.5 MHz, FDD, 30 bits) struct DCI2C_1_5MHz_FDD { //padding for 32 bits - uint32_t padding32:2; + uint32_t padding:2; /// Redundancy version 2 uint32_t rv2:2; /// New Data Indicator 2 @@ -2517,7 +2515,7 @@ typedef struct DCI2C_1_5MHz_FDD DCI2C_1_5MHz_FDD_t; /// DCI Format Type 2C (5 MHz, FDD, 38 bits) struct DCI2C_5MHz_FDD { /// padding for 64-bit - uint64_t padding64:26; + uint64_t padding:26; /// Redundancy version 2 uint64_t rv2:2; /// New Data Indicator 2 @@ -2548,7 +2546,7 @@ typedef struct DCI2C_5MHz_FDD DCI2C_5MHz_FDD_t; /// DCI Format Type 2C (10 MHz, FDD, 42 bits) struct DCI2C_10MHz_FDD { /// padding for 64-bit - uint64_t padding64:22; + uint64_t padding:22; /// Redundancy version 2 uint64_t rv2:2; /// New Data Indicator 2 @@ -2579,7 +2577,7 @@ typedef struct DCI2C_10MHz_FDD DCI2C_10MHz_FDD_t; /// DCI Format Type 2C (20 MHz, FDD, 50 bits) struct DCI2C_20MHz_FDD { /// padding for 64-bit - uint64_t padding64:14; + uint64_t padding:14; /// Redundancy version 2 uint64_t rv2:2; /// New Data Indicator 2 @@ -2613,7 +2611,7 @@ typedef struct DCI2C_20MHz_FDD DCI2C_20MHz_FDD_t; /// DCI Format Type 2D (1.5 MHz, TDD, 36 bits) struct DCI2D_1_5MHz_TDD { - uint64_t padding64:28; + uint64_t padding:28; /// PDSCH REsource Mapping and Quasi-Co-Location Indicator uint64_t REMQCL:2; /// Redundancy version 2 @@ -2648,7 +2646,7 @@ typedef struct DCI2D_1_5MHz_TDD DCI2D_1_5MHz_TDD_t; /// DCI Format Type 2D (5 MHz, TDD, 43 bits) struct DCI2D_5MHz_TDD { /// padding to 64bits - uint64_t padding64:21; + uint64_t padding:21; /// PDSCH REsource Mapping and Quasi-Co-Location Indicator uint64_t REMQCL:2; /// Redundancy version 2 @@ -2685,7 +2683,7 @@ typedef struct DCI2D_5MHz_TDD DCI2D_5MHz_TDD_t; /// DCI Format Type 2D (10 MHz, TDD, 47 bits) struct DCI2D_10MHz_TDD { /// padding to 64bits - uint64_t padding64:17; + uint64_t padding:17; /// PDSCH REsource Mapping and Quasi-Co-Location Indicator uint64_t REMQCL:2; /// Redundancy version 2 @@ -2722,7 +2720,7 @@ typedef struct DCI2D_10MHz_TDD DCI2D_10MHz_TDD_t; /// DCI Format Type 2D (20 MHz, TDD, 55 bits) struct DCI2D_20MHz_TDD { /// padding to 64bits - uint64_t padding64:9; + uint64_t padding:9; /// PDSCH REsource Mapping and Quasi-Co-Location Indicator uint64_t REMQCL:2; /// Redundancy version 2 @@ -2759,7 +2757,7 @@ typedef struct DCI2D_20MHz_TDD DCI2D_20MHz_TDD_t; /// DCI Format Type 2D (1.5 MHz, FDD, 33 bits) struct DCI2D_1_5MHz_FDD { //padding for 33 bits - uint64_t padding64:31; + uint64_t padding:31; /// PDSCH REsource Mapping and Quasi-Co-Location Indicator uint64_t REMQCL:2; /// Redundancy version 2 @@ -2783,7 +2781,7 @@ struct DCI2D_1_5MHz_FDD { /// RB Assignment (ceil(log2(N_RB_DL/P)) bits) uint64_t rballoc:6; /// padding for ambiguity - uint64_t padding; + uint64_t padding0; } __attribute__ ((__packed__)); typedef struct DCI2D_1_5MHz_FDD DCI2D_1_5MHz_FDD_t; @@ -2792,7 +2790,7 @@ typedef struct DCI2D_1_5MHz_FDD DCI2D_1_5MHz_FDD_t; /// DCI Format Type 2D (5 MHz, FDD, 41 bits) struct DCI2D_5MHz_FDD { /// padding for 64-bit - uint64_t padding64:23; + uint64_t padding:23; /// PDSCH REsource Mapping and Quasi-Co-Location Indicator uint64_t REMQCL:2; /// Redundancy version 2 @@ -2818,7 +2816,7 @@ struct DCI2D_5MHz_FDD { /// Resource Allocation Header uint64_t rah:1; /// padding for ambiguity - uint64_t padding:1; + uint64_t padding0:1; } __attribute__ ((__packed__)); #define sizeof_DCI2D_5MHz_FDD_t 41 @@ -2827,7 +2825,7 @@ typedef struct DCI2D_5MHz_FDD DCI2D_5MHz_FDD_t; /// DCI Format Type 2D (10 MHz, FDD, 45 bits) struct DCI2D_10MHz_FDD { /// padding for 64-bit - uint64_t padding64:19; + uint64_t padding:19; /// PDSCH REsource Mapping and Quasi-Co-Location Indicator uint64_t REMQCL:2; /// Redundancy version 2 @@ -2853,7 +2851,7 @@ struct DCI2D_10MHz_FDD { /// Resource Allocation Header uint64_t rah:1; /// padding for ambiguity - uint64_t padding:1; + uint64_t padding0:1; } __attribute__ ((__packed__)); #define sizeof_DCI2D_10MHz_FDD_t 45 @@ -2862,7 +2860,7 @@ typedef struct DCI2D_10MHz_FDD DCI2D_10MHz_FDD_t; /// DCI Format Type 2D (20 MHz, FDD, 52 bits) struct DCI2D_20MHz_FDD { /// padding for 64-bit - uint64_t padding64:12; + uint64_t padding:12; /// Redundancy version 2 uint64_t rv2:2; /// New Data Indicator 2 diff --git a/openair1/PHY/LTE_TRANSPORT/dci_tools.c b/openair1/PHY/LTE_TRANSPORT/dci_tools.c index ff31507979..d943b91d3a 100644 --- a/openair1/PHY/LTE_TRANSPORT/dci_tools.c +++ b/openair1/PHY/LTE_TRANSPORT/dci_tools.c @@ -1113,6 +1113,7 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->TPC = rel8->tpc; ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid = rel8->harq_process; ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->padding = 0; } else { dci_alloc->dci_length = sizeof_DCI1A_1_5MHz_FDD_t; @@ -1124,6 +1125,7 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->rv = rel8->redundancy_version_1; ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process; + ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->padding = 0; // printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } AssertFatal(rel8->virtual_resource_block_assignment_flag==LOCALIZED,"Distributed RB allocation not done yet\n"); @@ -1142,7 +1144,8 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->rv = rel8->redundancy_version_1; ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->TPC = rel8->tpc; ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid = rel8->harq_process; - ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->padding = 0; // printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } else { dci_alloc->dci_length = sizeof_DCI1A_5MHz_FDD_t; @@ -1154,6 +1157,7 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI1A_5MHz_FDD_t *)dci_pdu)->rv = rel8->redundancy_version_1; ((DCI1A_5MHz_FDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI1A_5MHz_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process; + ((DCI1A_5MHz_FDD_t *)dci_pdu)->padding = 0; // printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } AssertFatal(rel8->virtual_resource_block_assignment_flag==LOCALIZED,"Distributed RB allocation not done yet\n"); @@ -1172,7 +1176,8 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->rv = rel8->redundancy_version_1; ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->TPC = rel8->tpc; ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->harq_pid = rel8->harq_process; - ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->padding = 0; // printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } else { dci_alloc->dci_length = sizeof_DCI1A_10MHz_FDD_t; @@ -1184,6 +1189,7 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI1A_10MHz_FDD_t *)dci_pdu)->rv = rel8->redundancy_version_1; ((DCI1A_10MHz_FDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI1A_10MHz_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process; + ((DCI1A_10MHz_FDD_t *)dci_pdu)->padding = 0; // printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } AssertFatal(rel8->virtual_resource_block_assignment_flag==LOCALIZED,"Distributed RB allocation not done yet\n"); @@ -1203,7 +1209,8 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->rv = rel8->redundancy_version_1; ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->TPC = rel8->tpc; ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->harq_pid = rel8->harq_process; - ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->padding = 0; // printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } else { dci_alloc->dci_length = sizeof_DCI1A_20MHz_FDD_t; @@ -1215,6 +1222,7 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI1A_20MHz_FDD_t *)dci_pdu)->rv = rel8->redundancy_version_1; ((DCI1A_20MHz_FDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI1A_20MHz_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process; + ((DCI1A_20MHz_FDD_t *)dci_pdu)->padding = 0; // printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } AssertFatal(rel8->virtual_resource_block_assignment_flag==LOCALIZED,"Distributed RB allocation not done yet\n"); @@ -1286,7 +1294,8 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI1_1_5MHz_TDD_t *)dci_pdu)->rv = rel8->redundancy_version_1; ((DCI1_1_5MHz_TDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI1_1_5MHz_TDD_t *)dci_pdu)->harq_pid = rel8->harq_process; - ((DCI1_1_5MHz_TDD_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI1_1_5MHz_TDD_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI1_1_5MHz_TDD_t *)dci_pdu)->padding = 0; // printf("TDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } else { dci_alloc->dci_length = sizeof_DCI1_1_5MHz_FDD_t; @@ -1297,6 +1306,7 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI1_1_5MHz_FDD_t *)dci_pdu)->rv = rel8->redundancy_version_1; ((DCI1_1_5MHz_FDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI1_1_5MHz_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process; + ((DCI1_1_5MHz_FDD_t *)dci_pdu)->padding = 0; // printf("FDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } break; @@ -1310,7 +1320,8 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI1_5MHz_TDD_t *)dci_pdu)->rv = rel8->redundancy_version_1; ((DCI1_5MHz_TDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI1_5MHz_TDD_t *)dci_pdu)->harq_pid = rel8->harq_process; - ((DCI1_5MHz_TDD_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI1_5MHz_TDD_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI1_5MHz_TDD_t *)dci_pdu)->padding = 0; // printf("TDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } else { dci_alloc->dci_length = sizeof_DCI1_5MHz_FDD_t; @@ -1321,6 +1332,7 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI1_5MHz_FDD_t *)dci_pdu)->rv = rel8->redundancy_version_1; ((DCI1_5MHz_FDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI1_5MHz_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process; + ((DCI1_5MHz_FDD_t *)dci_pdu)->padding = 0; // printf("FDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } break; @@ -1334,7 +1346,8 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI1_10MHz_TDD_t *)dci_pdu)->rv = rel8->redundancy_version_1; ((DCI1_10MHz_TDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI1_10MHz_TDD_t *)dci_pdu)->harq_pid = rel8->harq_process; - ((DCI1_10MHz_TDD_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI1_10MHz_TDD_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI1_10MHz_TDD_t *)dci_pdu)->padding = 0; // printf("TDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } else { dci_alloc->dci_length = sizeof_DCI1_10MHz_FDD_t; @@ -1345,6 +1358,7 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI1_10MHz_FDD_t *)dci_pdu)->rv = rel8->redundancy_version_1; ((DCI1_10MHz_FDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI1_10MHz_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process; + ((DCI1_10MHz_FDD_t *)dci_pdu)->padding = 0; } break; case 100: @@ -1357,7 +1371,8 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI1_20MHz_TDD_t *)dci_pdu)->rv = rel8->redundancy_version_1; ((DCI1_20MHz_TDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI1_20MHz_TDD_t *)dci_pdu)->harq_pid = rel8->harq_process; - ((DCI1_20MHz_TDD_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI1_20MHz_TDD_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI1_20MHz_TDD_t *)dci_pdu)->padding = 0; // printf("TDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } else { dci_alloc->dci_length = sizeof_DCI1_20MHz_FDD_t; @@ -1368,6 +1383,7 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI1_20MHz_FDD_t *)dci_pdu)->rv = rel8->redundancy_version_1; ((DCI1_20MHz_FDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI1_20MHz_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process; + ((DCI1_20MHz_FDD_t *)dci_pdu)->padding = 0; } break; } @@ -1456,6 +1472,7 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->harq_pid = rel8->harq_process; ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->tb_swap = rel8->transport_block_to_codeword_swap_flag; ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + /* there is no padding in this structure, it is exactly 32 bits */ // printf("TDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } else { dci_alloc->dci_length = sizeof_DCI2A_1_5MHz_2A_FDD_t; @@ -1470,6 +1487,7 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process; ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->tb_swap = rel8->transport_block_to_codeword_swap_flag; + ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->padding = 0; // printf("FDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } break; @@ -1486,8 +1504,9 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->rv2 = rel8->redundancy_version_2; ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->harq_pid = rel8->harq_process; - ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->tb_swap = rel8->transport_block_to_codeword_swap_flag; - ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->tb_swap = rel8->transport_block_to_codeword_swap_flag; + ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->padding = 0; // printf("TDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } else { dci_alloc->dci_length = sizeof_DCI2A_5MHz_2A_FDD_t; @@ -1502,6 +1521,7 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process; ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->tb_swap = rel8->transport_block_to_codeword_swap_flag; + ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->padding = 0; // printf("FDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } break; @@ -1518,8 +1538,9 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->rv2 = rel8->redundancy_version_2; ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->harq_pid = rel8->harq_process; - ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->tb_swap = rel8->transport_block_to_codeword_swap_flag; - ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->tb_swap = rel8->transport_block_to_codeword_swap_flag; + ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->padding = 0; // printf("TDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } else { dci_alloc->dci_length = sizeof_DCI2A_10MHz_2A_FDD_t; @@ -1533,7 +1554,8 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->rv2 = rel8->redundancy_version_2; ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process; - ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->tb_swap = rel8->transport_block_to_codeword_swap_flag; + ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->tb_swap = rel8->transport_block_to_codeword_swap_flag; + ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->padding = 0; } break; case 100: @@ -1549,8 +1571,9 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->rv2 = rel8->redundancy_version_2; ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->harq_pid = rel8->harq_process; - ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->tb_swap = rel8->transport_block_to_codeword_swap_flag; - ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->tb_swap = rel8->transport_block_to_codeword_swap_flag; + ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->padding = 0; // printf("TDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } else { dci_alloc->dci_length = sizeof_DCI2A_20MHz_2A_FDD_t; @@ -1564,7 +1587,8 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->rv2 = rel8->redundancy_version_2; ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process; - ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->tb_swap = rel8->transport_block_to_codeword_swap_flag; + ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->tb_swap = rel8->transport_block_to_codeword_swap_flag; + ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->padding = 0; } break; @@ -1803,6 +1827,7 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->tb_swap = rel8->transport_block_to_codeword_swap_flag; ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->dai = rel8->downlink_assignment_index; ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->tpmi = rel8->precoding_information; + ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->padding = 0; // printf("TDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } else { dci_alloc->dci_length = sizeof_DCI2_1_5MHz_2A_FDD_t; @@ -1817,6 +1842,7 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process; ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->tb_swap = rel8->transport_block_to_codeword_swap_flag; ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->tpmi = rel8->precoding_information; + ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->padding = 0; // printf("FDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } break; @@ -1836,6 +1862,7 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->tb_swap = rel8->transport_block_to_codeword_swap_flag; ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->dai = rel8->downlink_assignment_index; ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->tpmi = rel8->precoding_information; + ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->padding = 0; // printf("TDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } else { dci_alloc->dci_length = sizeof_DCI2_5MHz_2A_FDD_t; @@ -1850,7 +1877,8 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process; ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->tb_swap = rel8->transport_block_to_codeword_swap_flag; - ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->tpmi = rel8->precoding_information; + ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->tpmi = rel8->precoding_information; + ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->padding = 0; // printf("FDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } break; @@ -1870,6 +1898,7 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->tb_swap = rel8->transport_block_to_codeword_swap_flag; ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->dai = rel8->downlink_assignment_index; ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->tpmi = rel8->precoding_information; + ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->padding = 0; // printf("TDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } else { dci_alloc->dci_length = sizeof_DCI2_10MHz_2A_FDD_t; @@ -1883,13 +1912,14 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->rv2 = rel8->redundancy_version_2; ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process; - ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->tb_swap = rel8->transport_block_to_codeword_swap_flag; + ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->tb_swap = rel8->transport_block_to_codeword_swap_flag; ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->tpmi = rel8->precoding_information; + ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->padding = 0; } break; case 100: if (fp->frame_type == TDD) { - dci_alloc->dci_length = sizeof_DCI2_20MHz_2A_TDD_t; + dci_alloc->dci_length = sizeof_DCI2_20MHz_2A_TDD_t; ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->rah = rel8->resource_allocation_type; ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->mcs1 = rel8->mcs_1; ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->mcs2 = rel8->mcs_2; @@ -1900,12 +1930,13 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->rv2 = rel8->redundancy_version_2; ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->harq_pid = rel8->harq_process; - ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->tb_swap = rel8->transport_block_to_codeword_swap_flag; - ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->dai = rel8->downlink_assignment_index; + ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->tb_swap = rel8->transport_block_to_codeword_swap_flag; + ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->dai = rel8->downlink_assignment_index; ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->tpmi = rel8->precoding_information; + ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->padding = 0; // printf("TDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB); } else { - dci_alloc->dci_length = sizeof_DCI2_20MHz_2A_FDD_t; + dci_alloc->dci_length = sizeof_DCI2_20MHz_2A_FDD_t; ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->rah = rel8->resource_allocation_type; ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->mcs1 = rel8->mcs_1; ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->mcs2 = rel8->mcs_2; @@ -1916,8 +1947,9 @@ LOG_D(PHY,"NFAPI: harq_pid %d harq_mask %x, round %d ndi (%d,%d) rnti type %d\n" ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->rv2 = rel8->redundancy_version_2; ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->TPC = rel8->tpc; ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process; - ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->tb_swap = rel8->transport_block_to_codeword_swap_flag; + ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->tb_swap = rel8->transport_block_to_codeword_swap_flag; ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->tpmi = rel8->precoding_information; + ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->padding = 0; } break; @@ -2300,6 +2332,7 @@ void fill_mdci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,mDCI_ALLOC_t *d ((DCI6_1A_5MHz_t *)dci_pdu)->srs_req = rel13->srs_request; ((DCI6_1A_5MHz_t *)dci_pdu)->harq_ack_off = rel13->harq_resource_offset; ((DCI6_1A_5MHz_t *)dci_pdu)->dci_rep = rel13->dci_subframe_repetition_number-1; + ((DCI6_1A_5MHz_t *)dci_pdu)->padding = 0; break; case 50: @@ -2316,6 +2349,7 @@ void fill_mdci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,mDCI_ALLOC_t *d ((DCI6_1A_10MHz_t *)dci_pdu)->srs_req = rel13->srs_request; ((DCI6_1A_10MHz_t *)dci_pdu)->harq_ack_off = rel13->harq_resource_offset; ((DCI6_1A_10MHz_t *)dci_pdu)->dci_rep = rel13->dci_subframe_repetition_number-1; + ((DCI6_1A_10MHz_t *)dci_pdu)->padding = 0; break; case 100: dci_alloc->dci_length = sizeof_DCI6_1A_20MHz_t; @@ -2331,6 +2365,7 @@ void fill_mdci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,mDCI_ALLOC_t *d ((DCI6_1A_20MHz_t *)dci_pdu)->srs_req = rel13->srs_request; ((DCI6_1A_20MHz_t *)dci_pdu)->harq_ack_off = rel13->harq_resource_offset; ((DCI6_1A_20MHz_t *)dci_pdu)->dci_rep = rel13->dci_subframe_repetition_number-1; + ((DCI6_1A_20MHz_t *)dci_pdu)->padding = 0; break; } break; @@ -2353,6 +2388,7 @@ void fill_mdci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,mDCI_ALLOC_t *d ((DCI6_1B_5MHz_t *)dci_pdu)->ndi = rel13->new_data_indicator; ((DCI6_1B_5MHz_t *)dci_pdu)->harq_ack_off = rel13->harq_resource_offset; ((DCI6_1B_5MHz_t *)dci_pdu)->dci_rep = rel13->dci_subframe_repetition_number-1; + ((DCI6_1B_5MHz_t *)dci_pdu)->padding = 0; break; case 50: @@ -2365,6 +2401,7 @@ void fill_mdci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,mDCI_ALLOC_t *d ((DCI6_1B_10MHz_t *)dci_pdu)->ndi = rel13->new_data_indicator; ((DCI6_1B_10MHz_t *)dci_pdu)->harq_ack_off = rel13->harq_resource_offset; ((DCI6_1B_10MHz_t *)dci_pdu)->dci_rep = rel13->dci_subframe_repetition_number-1; + ((DCI6_1B_10MHz_t *)dci_pdu)->padding = 0; break; case 100: dci_alloc->dci_length = sizeof_DCI6_1B_20MHz_t; @@ -2376,6 +2413,7 @@ void fill_mdci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,mDCI_ALLOC_t *d ((DCI6_1B_20MHz_t *)dci_pdu)->ndi = rel13->new_data_indicator; ((DCI6_1B_20MHz_t *)dci_pdu)->harq_ack_off = rel13->harq_resource_offset; ((DCI6_1B_20MHz_t *)dci_pdu)->dci_rep = rel13->dci_subframe_repetition_number-1; + ((DCI6_1B_20MHz_t *)dci_pdu)->padding = 0; break; } case 12: // Format 6-2 @@ -2391,6 +2429,7 @@ void fill_mdci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,mDCI_ALLOC_t *d if (rel13->paging_direct_indication_differentiation_flag==0) { ((DCI6_2_di_5MHz_t *)dci_pdu)->type = 0; ((DCI6_2_di_5MHz_t *)dci_pdu)->di_info = rel13->direct_indication; + ((DCI6_2_di_5MHz_t *)dci_pdu)->padding = 0; } else { ((DCI6_2_paging_5MHz_t *)dci_pdu)->type = 1; @@ -2398,6 +2437,7 @@ void fill_mdci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,mDCI_ALLOC_t *d ((DCI6_2_paging_5MHz_t *)dci_pdu)->mcs = rel13->mcs; ((DCI6_2_paging_5MHz_t *)dci_pdu)->rep = (rel13->pdsch_reptition_levels-1); ((DCI6_2_paging_5MHz_t *)dci_pdu)->dci_rep = rel13->dci_subframe_repetition_number-1; + ((DCI6_2_paging_5MHz_t *)dci_pdu)->padding = 0; } break; @@ -2406,6 +2446,7 @@ void fill_mdci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,mDCI_ALLOC_t *d if (rel13->paging_direct_indication_differentiation_flag==0) { ((DCI6_2_di_10MHz_t *)dci_pdu)->type = 0; ((DCI6_2_di_10MHz_t *)dci_pdu)->di_info = rel13->direct_indication; + ((DCI6_2_di_10MHz_t *)dci_pdu)->padding = 0; } else { ((DCI6_2_paging_10MHz_t *)dci_pdu)->type = 1; @@ -2413,6 +2454,7 @@ void fill_mdci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,mDCI_ALLOC_t *d ((DCI6_2_paging_10MHz_t *)dci_pdu)->mcs = rel13->mcs; ((DCI6_2_paging_10MHz_t *)dci_pdu)->rep = (rel13->pdsch_reptition_levels-1); ((DCI6_2_paging_10MHz_t *)dci_pdu)->dci_rep = rel13->dci_subframe_repetition_number-1; + ((DCI6_2_paging_10MHz_t *)dci_pdu)->padding = 0; } break; @@ -2421,6 +2463,7 @@ void fill_mdci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,mDCI_ALLOC_t *d if (rel13->paging_direct_indication_differentiation_flag==0) { ((DCI6_2_di_20MHz_t *)dci_pdu)->type = 0; ((DCI6_2_di_20MHz_t *)dci_pdu)->di_info = rel13->direct_indication; + ((DCI6_2_di_20MHz_t *)dci_pdu)->padding = 0; } else { ((DCI6_2_paging_20MHz_t *)dci_pdu)->type = 1; @@ -2428,6 +2471,7 @@ void fill_mdci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,mDCI_ALLOC_t *d ((DCI6_2_paging_20MHz_t *)dci_pdu)->mcs = rel13->mcs; ((DCI6_2_paging_20MHz_t *)dci_pdu)->rep = (rel13->pdsch_reptition_levels-1); ((DCI6_2_paging_20MHz_t *)dci_pdu)->dci_rep = rel13->dci_subframe_repetition_number-1; + ((DCI6_2_paging_20MHz_t *)dci_pdu)->padding = 0; } break; From af6ca150208454c377f520dedc23929712506a8b Mon Sep 17 00:00:00 2001 From: naoi Date: Wed, 28 Feb 2018 17:11:37 +0900 Subject: [PATCH 13/18] Fix: Random access information is not released when Msg3(response to PDCCH order) re-transmission fails. --- openair2/LAYER2/MAC/eNB_scheduler_RA.c | 1 + openair2/LAYER2/MAC/eNB_scheduler_ulsch.c | 22 ++++++++++------------ 2 files changed, 11 insertions(+), 12 deletions(-) diff --git a/openair2/LAYER2/MAC/eNB_scheduler_RA.c b/openair2/LAYER2/MAC/eNB_scheduler_RA.c index 83c184c0c2..bcd3984df9 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_RA.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_RA.c @@ -1683,6 +1683,7 @@ cancel_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP, ra[i].RRC_timer = 20; ra[i].rnti = 0; ra[i].msg3_round = 0; + LOG_I(MAC,"[eNB %d][RAPROC] CC_id %d Frame %d Canceled RA procedure for UE rnti %x\n", module_idP, CC_id, frameP, rnti); } } } diff --git a/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c b/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c index 0e4bbb84f1..f4ad9a6e9d 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c @@ -157,18 +157,16 @@ rx_sdu(const module_id_t enb_mod_idP, UE_list->UE_sched_ctrl[UE_id].round_UL[CC_idP][harq_pid], ul_cqi); - // AssertFatal(1==0,"ulsch in error\n"); - if (UE_list->UE_sched_ctrl[UE_id].round_UL[CC_idP][harq_pid] == - 3) { - UE_list->UE_sched_ctrl[UE_id].ul_scheduled &= - (~(1 << harq_pid)); - UE_list->UE_sched_ctrl[UE_id].round_UL[CC_idP][harq_pid] = - 0; - if (UE_list->UE_sched_ctrl[UE_id]. - ul_consecutive_errors++ == 10) - UE_list->UE_sched_ctrl[UE_id].ul_failure_timer = 1; - } else - UE_list->UE_sched_ctrl[UE_id].round_UL[CC_idP][harq_pid]++; + // AssertFatal(1==0,"ulsch in error\n"); + if (UE_list->UE_sched_ctrl[UE_id].round_UL[CC_idP][harq_pid] == 3) { + UE_list->UE_sched_ctrl[UE_id].ul_scheduled &= (~(1 << harq_pid)); + UE_list->UE_sched_ctrl[UE_id].round_UL[CC_idP][harq_pid] = 0; + if (UE_list->UE_sched_ctrl[UE_id].ul_consecutive_errors++ == 10) + UE_list->UE_sched_ctrl[UE_id].ul_failure_timer = 1; + if(find_RA_id(enb_mod_idP, CC_idP, current_rnti) != -1) + cancel_ra_proc(enb_mod_idP, CC_idP, frameP, current_rnti); + } else + UE_list->UE_sched_ctrl[UE_id].round_UL[CC_idP][harq_pid]++; return; } From 3d1b8a9cef0dfd4c827d8af0c0945156c518a312 Mon Sep 17 00:00:00 2001 From: naoi Date: Wed, 28 Feb 2018 17:50:10 +0900 Subject: [PATCH 14/18] Fix: S1-U Bearers is generated incorrectly when PDCCH order re-establishment succeeded. --- openair2/RRC/LITE/rrc_eNB.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/openair2/RRC/LITE/rrc_eNB.c b/openair2/RRC/LITE/rrc_eNB.c index 16e56b86f2..3da9a20aca 100644 --- a/openair2/RRC/LITE/rrc_eNB.c +++ b/openair2/RRC/LITE/rrc_eNB.c @@ -6274,7 +6274,7 @@ if (ue_context_p->ue_context.nb_of_modify_e_rabs > 0) { ue_context_p, ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.rrc_TransactionIdentifier); } - }else { + }else if(dedicated_DRB == 0){ if(ue_context_p->ue_context.reestablishment_cause == ReestablishmentCause_spare1){ rrc_eNB_send_S1AP_INITIAL_CONTEXT_SETUP_RESP(ctxt_pP, ue_context_p); @@ -6288,7 +6288,15 @@ if (ue_context_p->ue_context.nb_of_modify_e_rabs > 0) { } } } - } + }else if(dedicated_DRB == 2){ + for (uint8_t e_rab = 0; e_rab < ue_context_p->ue_context.nb_of_e_rabs; e_rab++) { + if (ue_context_p->ue_context.e_rab[e_rab].status == E_RAB_STATUS_DONE) { + ue_context_p->ue_context.e_rab[e_rab].status = E_RAB_STATUS_ESTABLISHED; + } else { + ue_context_p->ue_context.e_rab[e_rab].status = E_RAB_STATUS_FAILED; + } + } + } } #else // establish a dedicated bearer if (dedicated_DRB == 0 ) { From 95f677f735be1586376ef916575acb8cd0645da2 Mon Sep 17 00:00:00 2001 From: naoi Date: Wed, 28 Feb 2018 19:34:20 +0900 Subject: [PATCH 15/18] Fix: pucch procedures moves after UE removed. --- openair2/RRC/LITE/rrc_eNB.c | 60 ++++++++++++++++++++++++++----------- 1 file changed, 43 insertions(+), 17 deletions(-) diff --git a/openair2/RRC/LITE/rrc_eNB.c b/openair2/RRC/LITE/rrc_eNB.c index 3da9a20aca..7a7e1e3b08 100644 --- a/openair2/RRC/LITE/rrc_eNB.c +++ b/openair2/RRC/LITE/rrc_eNB.c @@ -851,8 +851,17 @@ rrc_eNB_free_UE(const module_id_t enb_mod_idP,const struct rrc_eNB_ue_context_s* LOG_I(RRC, "clean_eNb_ulsch UE %x \n", rnti); //clean_eNb_ulsch(ulsch); ulsch->rnti = 0; - break; } + if(eNB_PHY->uci_vars[i].rnti == rnti){ + LOG_I(MAC, "clean eNb uci_vars[%d] UE %x \n",i, rnti); + memset(&eNB_PHY->uci_vars[i],0,sizeof(LTE_eNB_UCI)); + } + } + ulsch = eNB_PHY->ulsch[i]; + if((ulsch != NULL) && (ulsch->rnti == rnti)){ + LOG_I(RRC, "clean_eNb_ulsch UE %x \n", rnti); + //clean_eNb_ulsch(ulsch); + ulsch->rnti = 0; } for(j = 0; j < 10; j++){ @@ -860,12 +869,16 @@ rrc_eNB_free_UE(const module_id_t enb_mod_idP,const struct rrc_eNB_ue_context_s* if(ul_req_tmp){ pdu_number = ul_req_tmp->number_of_pdus; for(int pdu_index = pdu_number-1; pdu_index >= 0; pdu_index--){ - if(ul_req_tmp->ul_config_pdu_list[pdu_index].ulsch_pdu.ulsch_pdu_rel8.rnti == rnti){ - LOG_I(RRC, "remove UE %x from ul_config_pdu_list %d/%d\n", rnti, pdu_index, pdu_number); - if(pdu_index < pdu_number -1){ - memcpy(&ul_req_tmp->ul_config_pdu_list[pdu_index], &ul_req_tmp->ul_config_pdu_list[pdu_index+1], (pdu_number-1-pdu_index) * sizeof(nfapi_ul_config_request_pdu_t)); - } - ul_req_tmp->number_of_pdus--; + if((ul_req_tmp->ul_config_pdu_list[pdu_index].ulsch_pdu.ulsch_pdu_rel8.rnti == rnti) || + (ul_req_tmp->ul_config_pdu_list[pdu_index].uci_harq_pdu.ue_information.ue_information_rel8.rnti == rnti) || + (ul_req_tmp->ul_config_pdu_list[pdu_index].uci_cqi_pdu.ue_information.ue_information_rel8.rnti == rnti) || + (ul_req_tmp->ul_config_pdu_list[pdu_index].uci_sr_pdu.ue_information.ue_information_rel8.rnti == rnti) || + (ul_req_tmp->ul_config_pdu_list[pdu_index].srs_pdu.srs_pdu_rel8.rnti == rnti)){ + LOG_I(RRC, "remove UE %x from ul_config_pdu_list %d/%d\n", rnti, pdu_index, pdu_number); + if(pdu_index < pdu_number -1){ + memcpy(&ul_req_tmp->ul_config_pdu_list[pdu_index], &ul_req_tmp->ul_config_pdu_list[pdu_index+1], (pdu_number-1-pdu_index) * sizeof(nfapi_ul_config_request_pdu_t)); + } + ul_req_tmp->number_of_pdus--; } } } @@ -945,12 +958,21 @@ void release_UE_in_freeList(module_id_t mod_id) PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, mod_id, ENB_FLAG_YES, rnti, 0, 0,mod_id); for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { eNB_PHY = RC.eNB[mod_id][CC_id]; - for (i=0; i<=NUMBER_OF_UE_MAX; i++) { + for (i=0; iulsch[i]; if((ulsch != NULL) && (ulsch->rnti == rnti)){ - LOG_I(RRC, "clean_eNb_ulsch ulsch[%d] UE %x\n", i, rnti); - clean_eNb_ulsch(ulsch); - } + LOG_I(RRC, "clean_eNb_ulsch ulsch[%d] UE %x\n", i, rnti); + clean_eNb_ulsch(ulsch); + } + if(eNB_PHY->uci_vars[i].rnti == rnti){ + LOG_I(MAC, "clean eNb uci_vars[%d] UE %x \n",i, rnti); + memset(&eNB_PHY->uci_vars[i],0,sizeof(LTE_eNB_UCI)); + } + } + ulsch = eNB_PHY->ulsch[i]; + if((ulsch != NULL) && (ulsch->rnti == rnti)){ + LOG_I(RRC, "clean_eNb_ulsch ulsch[%d] UE %x\n", i, rnti); + clean_eNb_ulsch(ulsch); } for(j = 0; j < 10; j++){ @@ -958,12 +980,16 @@ void release_UE_in_freeList(module_id_t mod_id) if(ul_req_tmp){ pdu_number = ul_req_tmp->number_of_pdus; for(int pdu_index = pdu_number-1; pdu_index >= 0; pdu_index--){ - if(ul_req_tmp->ul_config_pdu_list[pdu_index].ulsch_pdu.ulsch_pdu_rel8.rnti == rnti){ - LOG_I(RRC, "remove UE %x from ul_config_pdu_list %d/%d\n", rnti, pdu_index, pdu_number); - if(pdu_index < pdu_number -1){ - memcpy(&ul_req_tmp->ul_config_pdu_list[pdu_index], &ul_req_tmp->ul_config_pdu_list[pdu_index+1], (pdu_number-1-pdu_index) * sizeof(nfapi_ul_config_request_pdu_t)); - } - ul_req_tmp->number_of_pdus--; + if((ul_req_tmp->ul_config_pdu_list[pdu_index].ulsch_pdu.ulsch_pdu_rel8.rnti == rnti) || + (ul_req_tmp->ul_config_pdu_list[pdu_index].uci_harq_pdu.ue_information.ue_information_rel8.rnti == rnti) || + (ul_req_tmp->ul_config_pdu_list[pdu_index].uci_cqi_pdu.ue_information.ue_information_rel8.rnti == rnti) || + (ul_req_tmp->ul_config_pdu_list[pdu_index].uci_sr_pdu.ue_information.ue_information_rel8.rnti == rnti) || + (ul_req_tmp->ul_config_pdu_list[pdu_index].srs_pdu.srs_pdu_rel8.rnti == rnti)){ + LOG_I(RRC, "remove UE %x from ul_config_pdu_list %d/%d\n", rnti, pdu_index, pdu_number); + if(pdu_index < pdu_number -1){ + memcpy(&ul_req_tmp->ul_config_pdu_list[pdu_index], &ul_req_tmp->ul_config_pdu_list[pdu_index+1], (pdu_number-1-pdu_index) * sizeof(nfapi_ul_config_request_pdu_t)); + } + ul_req_tmp->number_of_pdus--; } } } From 4b02d818392a88a479628fc164c6f4c32bd8f685 Mon Sep 17 00:00:00 2001 From: naoi Date: Thu, 1 Mar 2018 16:21:32 +0900 Subject: [PATCH 16/18] Fix: Random access information may not release if msg3_round initial value is not zero. --- openair2/LAYER2/MAC/eNB_scheduler_RA.c | 25 +++++++++++++++++++ .../LAYER2/MAC/eNB_scheduler_primitives.c | 12 ++------- openair2/LAYER2/MAC/eNB_scheduler_ulsch.c | 2 +- openair2/LAYER2/MAC/proto.h | 3 +++ openair2/LAYER2/MAC/rar_tools.c | 1 + 5 files changed, 32 insertions(+), 11 deletions(-) diff --git a/openair2/LAYER2/MAC/eNB_scheduler_RA.c b/openair2/LAYER2/MAC/eNB_scheduler_RA.c index bcd3984df9..5dee9b7a2c 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_RA.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_RA.c @@ -1565,6 +1565,8 @@ initiate_ra_proc(module_id_t module_idP, struct PRACH_ConfigSIB_v1310 *ext4_prach = NULL; PRACH_ParametersListCE_r13_t *prach_ParametersListCE_r13 = NULL; + + static uint8_t failure_cnt = 0; if (cc->radioResourceConfigCommon_BR && cc->radioResourceConfigCommon_BR->ext4) { @@ -1649,6 +1651,7 @@ initiate_ra_proc(module_id_t module_idP, } ra[i].RA_rnti = ra_rnti; ra[i].preamble_index = preamble_index; + failure_cnt = 0; LOG_D(MAC, "[eNB %d][RAPROC] CC_id %d Frame %d Activating RAR generation in Frame %d, subframe %d for process %d, rnti %x, state %d\n", module_idP, CC_id, frameP, ra[i].Msg2_frame, @@ -1661,6 +1664,13 @@ initiate_ra_proc(module_id_t module_idP, LOG_E(MAC, "[eNB %d][RAPROC] FAILURE: CC_id %d Frame %d Initiating RA procedure for preamble index %d\n", module_idP, CC_id, frameP, preamble_index); + + failure_cnt++; + if(failure_cnt > 20) { + LOG_E(MAC,"[eNB %d][RAPROC] CC_id %d Frame %d Clear Random access information\n"); + clear_ra_proc(module_idP, CC_id, frameP); + } + } void @@ -1687,3 +1697,18 @@ cancel_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP, } } } + +void clear_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP) +{ + unsigned char i; + RA_t *ra = (RA_t *) & RC.mac[module_idP]->common_channels[CC_id].ra[0]; + + for (i = 0; i < NB_RA_PROC_MAX; i++) { + LOG_D(MAC,"[eNB %d][RAPROC] CC_id %d Frame %d Clear Random access information rnti %x\n", module_idP, CC_id, frameP, ra[i].rnti); + ra[i].state = IDLE; + ra[i].timing_offset = 0; + ra[i].RRC_timer = 20; + ra[i].rnti = 0; + ra[i].msg3_round = 0; + } +} diff --git a/openair2/LAYER2/MAC/eNB_scheduler_primitives.c b/openair2/LAYER2/MAC/eNB_scheduler_primitives.c index fa462561af..ef41f4e850 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_primitives.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_primitives.c @@ -2170,16 +2170,8 @@ int rrc_mac_remove_ue(module_id_t mod_idP, rnti_t rntiP) eNB_dlsch_info[mod_idP][pCC_id][UE_id].serving_num = 0; // check if this has an RA process active - RA_t *ra; - for (i = 0; i < NB_RA_PROC_MAX; i++) { - ra = (RA_t *) & RC.mac[mod_idP]->common_channels[pCC_id].ra[i]; - if (ra->rnti == rntiP) { - ra->state = IDLE; - ra->timing_offset = 0; - ra->RRC_timer = 20; - ra->rnti = 0; - //break; - } + if(find_RA_id(mod_idP, pCC_id, rntiP) != -1) { + cancel_ra_proc(mod_idP, pCC_id, 0, rntiP); } return 0; diff --git a/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c b/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c index f4ad9a6e9d..6b5bf9a3d0 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c @@ -194,7 +194,7 @@ rx_sdu(const module_id_t enb_mod_idP, (int) mac->common_channels[CC_idP]. radioResourceConfigCommon->rach_ConfigCommon. maxHARQ_Msg3Tx); - if (ra[RA_id].msg3_round == + if (ra[RA_id].msg3_round >= mac->common_channels[CC_idP].radioResourceConfigCommon-> rach_ConfigCommon.maxHARQ_Msg3Tx - 1) { cancel_ra_proc(enb_mod_idP, CC_idP, frameP, current_rnti); diff --git a/openair2/LAYER2/MAC/proto.h b/openair2/LAYER2/MAC/proto.h index d42c8f38dc..d2cf3e047b 100644 --- a/openair2/LAYER2/MAC/proto.h +++ b/openair2/LAYER2/MAC/proto.h @@ -299,6 +299,9 @@ void cancel_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP, @param Msg3_frame frame where scheduling takes place @param Msg3_subframe subframe where scheduling takes place */ + +void clear_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP); + void set_msg3_subframe(module_id_t Mod_id, int CC_id, int frame, diff --git a/openair2/LAYER2/MAC/rar_tools.c b/openair2/LAYER2/MAC/rar_tools.c index f48a53636f..6a9b4fa987 100644 --- a/openair2/LAYER2/MAC/rar_tools.c +++ b/openair2/LAYER2/MAC/rar_tools.c @@ -84,6 +84,7 @@ fill_rar(const module_id_t module_idP, ra->msg3_TPC = 3; ra->msg3_ULdelay = 0; ra->msg3_cqireq = 0; + ra->msg3_round = 0; rar[2] |= ((ra->msg3_mcs & 0x8) >> 3); // mcs 10 rar[3] = (((ra->msg3_mcs & 0x7) << 5)) | ((ra->msg3_TPC & 7) << 2) | From 1f9a6c13691aa38e2de39603e83da7eebeff8ae9 Mon Sep 17 00:00:00 2001 From: naoi Date: Thu, 1 Mar 2018 17:12:36 +0900 Subject: [PATCH 17/18] Fix: improve success rate of lower layer re-establishment. --- openair2/LAYER2/MAC/eNB_scheduler.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openair2/LAYER2/MAC/eNB_scheduler.c b/openair2/LAYER2/MAC/eNB_scheduler.c index 312c49094e..2b8dfbea80 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler.c +++ b/openair2/LAYER2/MAC/eNB_scheduler.c @@ -544,8 +544,8 @@ check_ul_failure(module_id_t module_idP, int CC_id, int UE_id, "UE %d rnti %x: sent PDCCH order for RAPROC waiting (failure timer %d) \n", UE_id, rnti, UE_list->UE_sched_ctrl[UE_id].ul_failure_timer); - if ((UE_list->UE_sched_ctrl[UE_id].ul_failure_timer % 40) == 0) - UE_list->UE_sched_ctrl[UE_id].ra_pdcch_order_sent = 0; // resend every 4 frames + if ((UE_list->UE_sched_ctrl[UE_id].ul_failure_timer % 80) == 0) + UE_list->UE_sched_ctrl[UE_id].ra_pdcch_order_sent = 0; // resend every 8 frames } UE_list->UE_sched_ctrl[UE_id].ul_failure_timer++; From 7f03a6e32ae330520dc0bb879ef3d0941511c3c5 Mon Sep 17 00:00:00 2001 From: naoi Date: Thu, 1 Mar 2018 19:21:21 +0900 Subject: [PATCH 18/18] Fix: log argument issue. --- openair2/LAYER2/MAC/eNB_scheduler_RA.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair2/LAYER2/MAC/eNB_scheduler_RA.c b/openair2/LAYER2/MAC/eNB_scheduler_RA.c index 5dee9b7a2c..6a4c93ac3a 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_RA.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_RA.c @@ -1667,7 +1667,7 @@ initiate_ra_proc(module_id_t module_idP, failure_cnt++; if(failure_cnt > 20) { - LOG_E(MAC,"[eNB %d][RAPROC] CC_id %d Frame %d Clear Random access information\n"); + LOG_E(MAC,"[eNB %d][RAPROC] CC_id %d Frame %d Clear Random access information\n", module_idP, CC_id, frameP); clear_ra_proc(module_idP, CC_id, frameP); }