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Merge remote-tracking branch 'origin/develop-nr' into ocp_nrsimulator

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This commit is contained in:
Florian Kaltenberger
2019-02-21 09:04:02 +01:00
parent 9021be8cd5 985418139c
commit 4c9c6f68fa
39 changed files with 1884 additions and 1019 deletions
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openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
+14 -2
View File
@@ -323,6 +323,16 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
nfapi_nr_config_request_t *cfg = &RC.nrmac[module_idP]->config[CC_id];
nfapi_nr_coreset_t coreset = RC.nrmac[module_idP]->coreset[CC_id][1];
nfapi_nr_search_space_t search_space = RC.nrmac[module_idP]->search_space[CC_id][1];
if (nr_is_dci_opportunity(search_space,
coreset,
frameP,
slotP,
*cfg))
nr_schedule_uss_dlsch_phytest(module_idP, frameP, slotP);
rnti = UE_RNTI(module_idP, i);
CC_id = UE_PCCID(module_idP, i);
int spf = get_spf(cfg);
@@ -425,9 +435,11 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
// Phytest scheduling/ option not activated because of pending bug
if (slotP==2)
nr_schedule_css_dlsch_phytest(module_idP, frameP, slotP);
/*if (slotP==2)
nr_schedule_css_dlsch_phytest(module_idP, frameP, slotP);*/
if (slotP==1)
nr_schedule_uss_dlsch_phytest(module_idP, frameP, slotP);
/*
// Allocate CCEs for good after scheduling is done
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
+144 -1
View File
@@ -92,7 +92,8 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
nr_configure_css_dci_initial(params_rel15,
scs, scs, nr_FR1, 0, 0,
scs, scs, nr_FR1, 0, 0, 0,
sfn_sf, slotP,
slots_per_frame,
dl_carrier_bandwidth);
@@ -179,3 +180,145 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
}
}
/*Scheduling of DLSCH with associated DCI in user specific search space
* current version has only a DCI for type 1 PDCCH for C_RNTI*/
void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
frame_t frameP,
sub_frame_t slotP)
{
uint8_t CC_id;
gNB_MAC_INST *nr_mac = RC.nrmac[module_idP];
//NR_COMMON_channels_t *cc = nr_mac->common_channels;
nfapi_nr_dl_config_request_body_t *dl_req;
nfapi_nr_dl_config_request_pdu_t *dl_config_dci_pdu;
nfapi_nr_dl_config_request_pdu_t *dl_config_dlsch_pdu;
nfapi_tx_request_pdu_t *TX_req;
nfapi_nr_config_request_t *cfg = &nr_mac->config[0];
uint16_t rnti = 0x1234;
uint16_t sfn_sf = frameP << 7 | slotP;
int dl_carrier_bandwidth = cfg->rf_config.dl_carrier_bandwidth.value;
// everything here is hard-coded to 30 kHz
int scs = get_dlscs(cfg);
int slots_per_frame = get_spf(cfg);
for (CC_id=0; CC_id<MAX_NUM_CCs; CC_id++) {
LOG_I(MAC, "Scheduling UE specific search space DCI type 1 for CC_id %d\n",CC_id);
nfapi_nr_coreset_t* coreset = &nr_mac->coreset[CC_id][1];
nfapi_nr_search_space_t* search_space = &nr_mac->search_space[CC_id][1];
dl_req = &nr_mac->DL_req[CC_id].dl_config_request_body;
dl_config_dci_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu];
memset((void*)dl_config_dci_pdu,0,sizeof(nfapi_nr_dl_config_request_pdu_t));
dl_config_dci_pdu->pdu_type = NFAPI_NR_DL_CONFIG_DCI_DL_PDU_TYPE;
dl_config_dci_pdu->pdu_size = (uint8_t)(2+sizeof(nfapi_nr_dl_config_dci_dl_pdu));
dl_config_dlsch_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu+1];
memset((void*)dl_config_dlsch_pdu,0,sizeof(nfapi_nr_dl_config_request_pdu_t));
dl_config_dlsch_pdu->pdu_type = NFAPI_NR_DL_CONFIG_DLSCH_PDU_TYPE;
dl_config_dlsch_pdu->pdu_size = (uint8_t)(2+sizeof(nfapi_nr_dl_config_dlsch_pdu));
nfapi_nr_dl_config_dci_dl_pdu_rel15_t *pdu_rel15 = &dl_config_dci_pdu->dci_dl_pdu.dci_dl_pdu_rel15;
nfapi_nr_dl_config_pdcch_parameters_rel15_t *params_rel15 = &dl_config_dci_pdu->dci_dl_pdu.pdcch_params_rel15;
nfapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_pdu_rel15 = &dl_config_dlsch_pdu->dlsch_pdu.dlsch_pdu_rel15;
dlsch_pdu_rel15->start_prb = 0;
dlsch_pdu_rel15->n_prb = 50;
dlsch_pdu_rel15->start_symbol = 2;
dlsch_pdu_rel15->nb_symbols = 8;
dlsch_pdu_rel15->rnti = rnti;
dlsch_pdu_rel15->nb_layers =1;
dlsch_pdu_rel15->nb_codewords = 1;
dlsch_pdu_rel15->mcs_idx = 9;
dlsch_pdu_rel15->ndi = 1;
dlsch_pdu_rel15->redundancy_version = 0;
nr_configure_dci_from_pdcch_config(params_rel15,
coreset,
search_space,
*cfg,
dl_carrier_bandwidth);
pdu_rel15->frequency_domain_assignment = get_RIV(dlsch_pdu_rel15->start_prb, dlsch_pdu_rel15->n_prb, cfg->rf_config.dl_carrier_bandwidth.value);
pdu_rel15->time_domain_assignment = get_SLIV(dlsch_pdu_rel15->start_symbol, dlsch_pdu_rel15->nb_symbols);
pdu_rel15->vrb_to_prb_mapping = 1;
pdu_rel15->mcs = 9;
pdu_rel15->tb_scaling = 1;
pdu_rel15->ra_preamble_index = 25;
pdu_rel15->format_indicator = 1;
pdu_rel15->ndi = 1;
pdu_rel15->rv = 0;
pdu_rel15->harq_pid = 0;
pdu_rel15->dai = 2;
pdu_rel15->tpc = 2;
pdu_rel15->pucch_resource_indicator = 7;
pdu_rel15->pdsch_to_harq_feedback_timing_indicator = 7;
LOG_I(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d, time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n",
pdu_rel15->frequency_domain_assignment,
pdu_rel15->time_domain_assignment,
pdu_rel15->vrb_to_prb_mapping,
pdu_rel15->mcs,
pdu_rel15->tb_scaling,
pdu_rel15->ndi,
pdu_rel15->rv);
params_rel15->rnti = rnti;
params_rel15->rnti_type = NFAPI_NR_RNTI_C;
params_rel15->dci_format = NFAPI_NR_DL_DCI_FORMAT_1_0;
//params_rel15->aggregation_level = 1;
LOG_I(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d, config type %d\n \
coreset params: mux_pattern %d, n_rb %d, n_symb %d, rb_offset %d \n \
ss params : first symb %d, ss type %d\n",
params_rel15->rnti,
params_rel15->rnti_type,
params_rel15->config_type,
params_rel15->dci_format,
params_rel15->mux_pattern,
params_rel15->n_rb,
params_rel15->n_symb,
params_rel15->rb_offset,
params_rel15->first_symbol,
params_rel15->search_space_type);
nr_get_tbs(&dl_config_dlsch_pdu->dlsch_pdu, dl_config_dci_pdu->dci_dl_pdu, *cfg);
LOG_I(MAC, "DLSCH PDU: start PRB %d n_PRB %d start symbol %d nb_symbols %d nb_layers %d nb_codewords %d mcs %d\n",
dlsch_pdu_rel15->start_prb,
dlsch_pdu_rel15->n_prb,
dlsch_pdu_rel15->start_symbol,
dlsch_pdu_rel15->nb_symbols,
dlsch_pdu_rel15->nb_layers,
dlsch_pdu_rel15->nb_codewords,
dlsch_pdu_rel15->mcs_idx);
dl_req->number_dci++;
dl_req->number_pdsch_rnti++;
dl_req->number_pdu+=2;
TX_req = &nr_mac->TX_req[CC_id].tx_request_body.tx_pdu_list[nr_mac->TX_req[CC_id].tx_request_body.number_of_pdus];
TX_req->pdu_length = 6;
TX_req->pdu_index = nr_mac->pdu_index[CC_id]++;
TX_req->num_segments = 1;
TX_req->segments[0].segment_length = 8;
nr_mac->TX_req[CC_id].tx_request_body.number_of_pdus++;
nr_mac->TX_req[CC_id].sfn_sf = sfn_sf;
nr_mac->TX_req[CC_id].tx_request_body.tl.tag = NFAPI_TX_REQUEST_BODY_TAG;
nr_mac->TX_req[CC_id].header.message_id = NFAPI_TX_REQUEST;
TX_req = &nr_mac->TX_req[CC_id].tx_request_body.tx_pdu_list[nr_mac->TX_req[CC_id].tx_request_body.number_of_pdus+1];
TX_req->pdu_length = dlsch_pdu_rel15->transport_block_size;
TX_req->pdu_index = nr_mac->pdu_index[CC_id]++;
TX_req->num_segments = 1;
TX_req->segments[0].segment_length = 8;
nr_mac->TX_req[CC_id].tx_request_body.number_of_pdus++;
nr_mac->TX_req[CC_id].sfn_sf = sfn_sf;
nr_mac->TX_req[CC_id].tx_request_body.tl.tag = NFAPI_TX_REQUEST_BODY_TAG;
nr_mac->TX_req[CC_id].header.message_id = NFAPI_TX_REQUEST;
}
}
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
+355 -39
View File
@@ -21,11 +21,11 @@
/*! \file gNB_scheduler_primitives.c
* \brief primitives used by gNB for BCH, RACH, ULSCH, DLSCH scheduling
* \author Navid Nikaein and Raymond Knopp, WEI-TAI CHEN
* \date 2010 - 2014, 2018
* \email: navid.nikaein@eurecom.fr, kroempa@gmail.com
* \author Raymond Knopp, Guy De Souza
* \date 2018, 2019
* \email: knopp@eurecom.fr, desouza@eurecom.fr
* \version 1.0
* \company Eurecom, NTUST
* \company Eurecom
* @ingroup _mac
*/
@@ -65,23 +65,64 @@ extern RAN_CONTEXT_t RC;
extern int n_active_slices;
// Note the 2 scs values in the table names represent resp. scs_common and pdcch_scs
/// LUT for the number of symbols in the coreset indexed by coreset index (4 MSB rmsi_pdcch_config)
uint8_t nr_coreset_nsymb_pdcch_type_0_b40Mhz[16] = {2,2,2,2,2,3,3,3,3,3,1,1,1,2,2,2}; // below 40Mhz bw
uint8_t nr_coreset_nsymb_pdcch_type_0_a40Mhz[10] = {2,2,3,3,1,1,2,2,3,3}; // above 40Mhz bw
uint8_t nr_coreset_nsymb_pdcch_type_0_scs_15_15[15] = {2,2,2,3,3,3,1,1,2,2,3,3,1,2,3};
uint8_t nr_coreset_nsymb_pdcch_type_0_scs_15_30[14] = {2,2,2,2,3,3,3,3,1,1,2,2,3,3};
uint8_t nr_coreset_nsymb_pdcch_type_0_scs_30_15_b40Mhz[9] = {1,1,2,2,3,3,1,2,3};
uint8_t nr_coreset_nsymb_pdcch_type_0_scs_30_15_a40Mhz[9] = {1,2,3,1,1,2,2,3,3};
uint8_t nr_coreset_nsymb_pdcch_type_0_scs_30_30_b40Mhz[16] = {2,2,2,2,2,3,3,3,3,3,1,1,1,2,2,2}; // below 40Mhz bw
uint8_t nr_coreset_nsymb_pdcch_type_0_scs_30_30_a40Mhz[10] = {2,2,3,3,1,1,2,2,3,3}; // above 40Mhz bw
uint8_t nr_coreset_nsymb_pdcch_type_0_scs_120_60[12] = {1,1,2,2,3,3,1,2,1,1,1,1};
/// LUT for the number of RBs in the coreset indexed by coreset index
uint8_t nr_coreset_rb_offset_pdcch_type_0_b40Mhz[16] = {0,1,2,3,4,0,1,2,3,4,12,14,16,12,14,16};
uint8_t nr_coreset_rb_offset_pdcch_type_0_a40Mhz[10] = {0,4,0,4,0,28,0,28,0,28};
uint8_t nr_coreset_rb_offset_pdcch_type_0_scs_15_15[15] = {0,2,4,0,2,4,12,16,12,16,12,16,38,38,38};
uint8_t nr_coreset_rb_offset_pdcch_type_0_scs_15_30[14] = {5,6,7,8,5,6,7,8,18,20,18,20,18,20};
uint8_t nr_coreset_rb_offset_pdcch_type_0_scs_30_15_b40Mhz[9] = {2,6,2,6,2,6,28,28,28};
uint8_t nr_coreset_rb_offset_pdcch_type_0_scs_30_15_a40Mhz[9] = {4,4,4,0,56,0,56,0,56};
uint8_t nr_coreset_rb_offset_pdcch_type_0_scs_30_30_b40Mhz[16] = {0,1,2,3,4,0,1,2,3,4,12,14,16,12,14,16};
uint8_t nr_coreset_rb_offset_pdcch_type_0_scs_30_30_a40Mhz[10] = {0,4,0,4,0,28,0,28,0,28};
int8_t nr_coreset_rb_offset_pdcch_type_0_scs_120_60[12] = {0,8,0,8,0,8,28,28,-1,49,-1,97};
int8_t nr_coreset_rb_offset_pdcch_type_0_scs_120_120[8] = {0,4,14,14,-1,24,-1,48};
int8_t nr_coreset_rb_offset_pdcch_type_0_scs_240_120[8] = {0,8,0,8,-1,25,-1,49};
/// LUT for monitoring occasions param O indexed by ss index (4 LSB rmsi_pdcch_config)
// Note: scaling is used to avoid decimal values for O and M, original values commented
uint8_t nr_ss_param_O_type_0_mux1_FR1[16] = {0,0,2,2,5,5,7,7,0,5,0,0,2,2,5,5};
uint8_t nr_ss_param_O_type_0_mux1_FR2[14] = {0,0,2.5,2.5,5,5,0,2.5,5,7.5,7.5,7.5,0,5};
uint8_t nr_ss_param_O_type_0_mux1_FR2[14] = {0,0,5,5,5,5,0,5,5,15,15,15,0,5}; //{0,0,2.5,2.5,5,5,0,2.5,5,7.5,7.5,7.5,0,5}
uint8_t nr_ss_scale_O_mux1_FR2[14] = {0,0,1,1,0,0,0,1,0,1,1,1,0,0};
/// LUT for number of SS sets per slot indexed by ss index
uint8_t nr_ss_sets_per_slot_type_0_FR1[16] = {1,2,1,2,1,2,1,2,1,1,1,1,1,1,1,1};
uint8_t nr_ss_sets_per_slot_type_0_FR2[14] = {1,2,1,2,1,2,2,2,2,1,2,2,1,1};
/// LUT for monitoring occasions param M indexed by ss index
uint8_t nr_ss_param_M_type_0_mux1_FR1[16] = {1,0.5,1,0.5,1,0.5,1,0.5,2,2,1,1,1,1,1,1};
uint8_t nr_ss_param_M_type_0_mux1_FR2[14] = {1,0.5,1,0.5,1,0.5,0.5,0.5,0.5,1,0.5,0.5,2,2};
uint8_t nr_ss_param_M_type_0_mux1_FR1[16] = {1,1,1,1,1,1,1,1,2,2,1,1,1,1,1,1}; //{1,0.5,1,0.5,1,0.5,1,0.5,2,2,1,1,1,1,1,1}
uint8_t nr_ss_scale_M_mux1_FR1[16] = {0,1,0,1,0,1,0,1,0,0,0,0,0,0,0,0};
uint8_t nr_ss_param_M_type_0_mux1_FR2[14] = {1,1,1,1,1,1,1,1,1,1,1,1,2,2}; //{1,0.5,1,0.5,1,0.5,0.5,0.5,0.5,1,0.5,0.5,2,2}
uint8_t nr_ss_scale_M_mux1_FR2[14] = {0,1,0,1,0,1,1,1,1,0,1,1,0,0};
/// LUT for SS first symbol index indexed by ss index
uint8_t nr_ss_first_symb_idx_type_0_mux1_FR1[8] = {0,0,1,2,1,2,1,2};
// Mux pattern type 2
uint8_t nr_ss_first_symb_idx_scs_120_60_mux2[4] = {0,1,6,7};
uint8_t nr_ss_first_symb_idx_scs_240_120_set1_mux2[6] = {0,1,2,3,0,1};
// Mux pattern type 3
uint8_t nr_ss_first_symb_idx_scs_120_120_mux3[4] = {4,8,2,6};
/// Search space max values indexed by scs
uint8_t nr_max_number_of_candidates_per_slot[4] = {44, 36, 22, 20};
uint8_t nr_max_number_of_cces_per_slot[4] = {56, 56, 48, 32};
static inline uint8_t get_max_candidates(uint8_t scs) {
AssertFatal(scs<4, "Invalid PDCCH subcarrier spacing %d\n", scs);
return (nr_max_number_of_candidates_per_slot[scs]);
}
static inline uint8_t get_max_cces(uint8_t scs) {
AssertFatal(scs<4, "Invalid PDCCH subcarrier spacing %d\n", scs);
return (nr_max_number_of_cces_per_slot[scs]);
}
int is_nr_UL_slot(NR_COMMON_channels_t * ccP, int slot){
@@ -94,69 +135,143 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p
nr_frequency_range_e freq_range,
uint8_t rmsi_pdcch_config,
uint8_t ssb_idx,
uint8_t k_ssb,
uint16_t sfn_ssb,
uint8_t n_ssb, /*slot index overlapping the corresponding SSB index*/
uint16_t nb_slots_per_frame,
uint16_t N_RB)
{
uint8_t O, M;
uint8_t ss_idx = rmsi_pdcch_config&0xf;
uint8_t cset_idx = (rmsi_pdcch_config>>4)&0xf;
uint8_t mu;
uint8_t mu = scs_common;
uint8_t O_scale=0, M_scale=0; // used to decide if the values of O and M need to be divided by 2
/// Coreset params
switch(scs_common) {
case kHz15:
mu = 0;
switch(pdcch_scs) {
case kHz15:
AssertFatal(cset_idx<15,"Coreset index %d reserved for scs kHz15/kHz15\n", cset_idx);
pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1;
pdcch_params->n_rb = (cset_idx < 6)? 24 : (cset_idx < 12)? 48 : 96;
pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_15_15[cset_idx];
pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_15_15[cset_idx];
break;
case kHz30:
AssertFatal(cset_idx<14,"Coreset index %d reserved for scs kHz15/kHz30\n", cset_idx);
pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1;
pdcch_params->n_rb = (cset_idx < 8)? 24 : 48;
pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_15_30[cset_idx];
pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_15_15[cset_idx];
break;
default:
AssertFatal(1==0,"Invalid scs_common/pdcch_scs combination %d/%d \n", scs_common, pdcch_scs);
}
break;
case kHz30:
mu = 1;
if (N_RB < 106) { // Minimum 40Mhz bandwidth not satisfied
switch(pdcch_scs) {
case kHz15:
AssertFatal(1==0,"kHz15 not supported yet\n");
break;
AssertFatal(cset_idx<9,"Coreset index %d reserved for scs kHz30/kHz15\n", cset_idx);
pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1;
pdcch_params->n_rb = (cset_idx < 10)? 48 : 96;
pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_30_15_b40Mhz[cset_idx];
pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_30_15_b40Mhz[cset_idx];
break;
case kHz30:
pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1;
pdcch_params->n_rb = (cset_idx < 10)? 24 : 48;
pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_b40Mhz[cset_idx];
pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_b40Mhz[cset_idx];
break;
pdcch_params->n_rb = (cset_idx < 6)? 24 : 48;
pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_30_30_b40Mhz[cset_idx];
pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_30_30_b40Mhz[cset_idx];
break;
default:
AssertFatal(1==0,"Invalid scs_common/pdcch_scs combination %d/%d \n", scs_common, pdcch_scs);
}
}
else {
AssertFatal(ss_idx<10 ,"Invalid scs_common/pdcch_scs combination %d/%d \n", scs_common, pdcch_scs);
else { // above 40Mhz
switch(pdcch_scs) {
case kHz15:
AssertFatal(1==0,"15 kHz SCS not supported yet\n");
break;
AssertFatal(cset_idx<9,"Coreset index %d reserved for scs kHz30/kHz15\n", cset_idx);
pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1;
pdcch_params->n_rb = (cset_idx < 3)? 48 : 96;
pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_30_15_a40Mhz[cset_idx];
pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_30_15_a40Mhz[cset_idx];
break;
case kHz30:
AssertFatal(cset_idx<10,"Coreset index %d reserved for scs kHz30/kHz30\n", cset_idx);
pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1;
pdcch_params->n_rb = (cset_idx < 4)? 24 : 48;
pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_b40Mhz[cset_idx];
pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_b40Mhz[cset_idx];
break;
pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_30_30_a40Mhz[cset_idx];
pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_30_30_a40Mhz[cset_idx];
break;
default:
AssertFatal(1==0,"Invalid scs_common/pdcch_scs combination %d/%d \n", scs_common, pdcch_scs);
}
}
case kHz60:
mu = 2;
break;
case kHz120:
mu = 3;
switch(pdcch_scs) {
case kHz60:
AssertFatal(cset_idx<12,"Coreset index %d reserved for scs kHz120/kHz60\n", cset_idx);
pdcch_params->mux_pattern = (cset_idx < 8)?NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1 : NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE2;
pdcch_params->n_rb = (cset_idx < 6)? 48 : (cset_idx < 8)? 96 : (cset_idx < 10)? 48 : 96;
pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_120_60[cset_idx];
pdcch_params->rb_offset = (nr_coreset_rb_offset_pdcch_type_0_scs_120_60[cset_idx]>0)?nr_coreset_rb_offset_pdcch_type_0_scs_120_60[cset_idx] :
(k_ssb == 0)? -41 : -42;
break;
case kHz120:
AssertFatal(cset_idx<8,"Coreset index %d reserved for scs kHz120/kHz120\n", cset_idx);
pdcch_params->mux_pattern = (cset_idx < 4)?NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1 : NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE3;
pdcch_params->n_rb = (cset_idx < 2)? 24 : (cset_idx < 4)? 48 : (cset_idx < 6)? 24 : 48;
pdcch_params->n_symb = (cset_idx == 2)? 1 : 2;
pdcch_params->rb_offset = (nr_coreset_rb_offset_pdcch_type_0_scs_120_120[cset_idx]>0)? nr_coreset_rb_offset_pdcch_type_0_scs_120_120[cset_idx] :
(k_ssb == 0)? -20 : -21;
break;
default:
AssertFatal(1==0,"Invalid scs_common/pdcch_scs combination %d/%d \n", scs_common, pdcch_scs);
}
break;
case kHz240:
switch(pdcch_scs) {
case kHz60:
AssertFatal(cset_idx<4,"Coreset index %d reserved for scs kHz240/kHz60\n", cset_idx);
pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1;
pdcch_params->n_rb = 96;
pdcch_params->n_symb = (cset_idx < 2)? 1 : 2;
pdcch_params->rb_offset = (cset_idx&1)? 16 : 0;
break;
case kHz120:
AssertFatal(cset_idx<8,"Coreset index %d reserved for scs kHz240/kHz120\n", cset_idx);
pdcch_params->mux_pattern = (cset_idx < 4)? NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1 : NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE2;
pdcch_params->n_rb = (cset_idx < 4)? 48 : (cset_idx < 6)? 24 : 48;
pdcch_params->n_symb = ((cset_idx==2)||(cset_idx==3))? 2 : 1;
pdcch_params->rb_offset = (nr_coreset_rb_offset_pdcch_type_0_scs_240_120[cset_idx]>0)? nr_coreset_rb_offset_pdcch_type_0_scs_240_120[cset_idx] :
(k_ssb == 0)? -41 : -42;
break;
default:
AssertFatal(1==0,"Invalid scs_common/pdcch_scs combination %d/%d \n", scs_common, pdcch_scs);
}
break;
default:
AssertFatal(1==0,"Invalid common subcarrier spacing %d\n", scs_common);
@@ -170,27 +285,50 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p
O = nr_ss_param_O_type_0_mux1_FR1[ss_idx];
pdcch_params->nb_ss_sets_per_slot = nr_ss_sets_per_slot_type_0_FR1[ss_idx];
M = nr_ss_param_M_type_0_mux1_FR1[ss_idx];
pdcch_params->first_symbol = (ss_idx < 8)? ( (ss_idx&1)? pdcch_params->n_symb : 0 ) : nr_ss_first_symb_idx_type_0_mux1_FR1[ss_idx - 8];
M_scale = nr_ss_scale_M_mux1_FR1[ss_idx];
pdcch_params->first_symbol = (ss_idx < 8)? ( (ssb_idx&1)? pdcch_params->n_symb : 0 ) : nr_ss_first_symb_idx_type_0_mux1_FR1[ss_idx - 8];
}
else {
AssertFatal(ss_idx<14 ,"Invalid search space index for multiplexing type 1 and FR2 %d\n", ss_idx);
O = nr_ss_param_O_type_0_mux1_FR2[ss_idx];
O_scale = nr_ss_scale_O_mux1_FR2[ss_idx];
pdcch_params->nb_ss_sets_per_slot = nr_ss_sets_per_slot_type_0_FR2[ss_idx];
M = nr_ss_param_M_type_0_mux1_FR2[ss_idx];
M_scale = nr_ss_scale_M_mux1_FR2[ss_idx];
pdcch_params->first_symbol = (ss_idx < 12)? ( (ss_idx&1)? 7 : 0 ) : 0;
}
pdcch_params->nb_slots = 2;
pdcch_params->sfn_mod2 = ((uint8_t)(floor( (O*pow(2, mu) + floor(ssb_idx*M)) / nb_slots_per_frame )) & 1)? 1 : 0;
pdcch_params->first_slot = (uint8_t)(O*pow(2, mu) + floor(ssb_idx*M)) % nb_slots_per_frame;
pdcch_params->sfn_mod2 = (CEILIDIV( (((O<<mu)>>O_scale) + ((ssb_idx*M)>>M_scale)), nb_slots_per_frame ) & 1)? 1 : 0;
pdcch_params->first_slot = (((O<<mu)>>O_scale) + ((ssb_idx*M)>>M_scale)) % nb_slots_per_frame;
break;
break;
case NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE2:
break;
AssertFatal( ((scs_common==kHz120)&&(pdcch_scs==kHz60)) || ((scs_common==kHz240)&&(pdcch_scs==kHz120)),
"Invalid scs_common/pdcch_scs combination %d/%d for Mux type 2\n", scs_common, pdcch_scs );
AssertFatal(ss_idx==0, "Search space index %d reserved for scs_common/pdcch_scs combination %d/%d", ss_idx, scs_common, pdcch_scs);
pdcch_params->nb_slots = 1;
if ((scs_common==kHz120)&&(pdcch_scs==kHz60)) {
pdcch_params->first_symbol = nr_ss_first_symb_idx_scs_120_60_mux2[ssb_idx&3];
// Missing in pdcch_params sfn_C and n_C here and in else case
}
else {
pdcch_params->first_symbol = ((ssb_idx&7)==4)?12 : ((ssb_idx&7)==4)?13 : nr_ss_first_symb_idx_scs_240_120_set1_mux2[ssb_idx&7]; //???
}
break;
case NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE3:
break;
AssertFatal( (scs_common==kHz120)&&(pdcch_scs==kHz120),
"Invalid scs_common/pdcch_scs combination %d/%d for Mux type 3\n", scs_common, pdcch_scs );
AssertFatal(ss_idx==0, "Search space index %d reserved for scs_common/pdcch_scs combination %d/%d", ss_idx, scs_common, pdcch_scs);
pdcch_params->first_symbol = nr_ss_first_symb_idx_scs_120_120_mux3[ssb_idx&3];
break;
default:
AssertFatal(1==0, "Invalid SSB and coreset multiplexing pattern %d\n", pdcch_params->mux_pattern);
@@ -206,11 +344,179 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p
}
void nr_configure_css_dci_from_pdcch_config(nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params,
void nr_configure_dci_from_pdcch_config(nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params,
nfapi_nr_coreset_t* coreset,
nfapi_nr_search_space_t* search_space) {
nfapi_nr_search_space_t* search_space,
nfapi_nr_config_request_t cfg,
uint16_t N_RB) {
/// coreset
//ControlResourceSetId
pdcch_params->config_type = NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG;
//frequencyDomainResources
uint8_t count=0, start=0, start_set=0;
uint64_t bitmap = coreset->frequency_domain_resources;
for (int i=0; i<45; i++)
if ((bitmap>>(44-i))&1) {
count++;
if (!start_set) {
start = i;
start_set = 1;
}
}
pdcch_params->rb_offset = 6*start;
pdcch_params->n_rb = 6*count;
//duration
pdcch_params->n_symb = coreset->duration;
//cce-REG-MappingType
pdcch_params->cr_mapping_type = coreset->cce_reg_mapping_type;
if (pdcch_params->cr_mapping_type == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) {
pdcch_params->reg_bundle_size = coreset->reg_bundle_size;
pdcch_params->interleaver_size = coreset->interleaver_size;
}
else {
pdcch_params->reg_bundle_size = 0;
pdcch_params->interleaver_size = 0;
}
//shift index
pdcch_params->shift_index = coreset->shift_index;
//precoderGranularity
pdcch_params->precoder_granularity = coreset->precoder_granularity;
//TCI states
// PDCCH params does not yet include information about TCI and QCL (needed for DCI 1.1 and 0.1)
//pdcch-DMRS-ScramblingID
pdcch_params->scrambling_id = coreset->dmrs_scrambling_id;
/// SearchSpace
// first symbol
//AssertFatal(pdcch_scs==kHz15, "PDCCH SCS above 15kHz not allowed if a symbol above 2 is monitored");
for (int i=0; i<get_symbolsperslot(&cfg); i++)
if ((search_space->monitoring_symbols_in_slot>>(15-i))&1) {
pdcch_params->first_symbol=i;
break;
}
//searchSpaceType
pdcch_params->search_space_type = search_space->search_space_type;
/*
//searchSpaceId
AssertFatal(search_space->search_space_id<40, "Search space index out of range %d\n", search_space->search_space_id);
//controlResourceSetId
//monitoringSlotPeriodicityAndOffset
//duration
pdcch_params->nb_ss_sets_per_slot = search_space->duration;
//monitoringSymbolsWithinSlot
pdcch_params->first_symbol = search_space->monitoring_symbols_in_slot;
//nrofCandidates
pdcch_params->aggregation_level = (uint8_t)number_of_candidates[NFAPI_NR_MAX_NB_CCE_AGGREGATION_LEVELS - 1];
//Common_CSS
if (pdcch_params->search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_COMMON){
switch(search_space->css_formats_0_0_and_1_0){
case NFAPI_NR_RNTI_C:
pdcch_params->rnti_type = NFAPI_NR_RNTI_C;
break;
case NFAPI_NR_RNTI_CS:
pdcch_params->rnti_type = NFAPI_NR_RNTI_CS;
break;
case NFAPI_NR_RNTI_SP_CSI:
pdcch_params->rnti_type = NFAPI_NR_RNTI_SP_CSI;
break;
case NFAPI_NR_RNTI_RA:
pdcch_params->rnti_type = NFAPI_NR_RNTI_RA;
break;
case NFAPI_NR_RNTI_TC:
pdcch_params->rnti_type = NFAPI_NR_RNTI_TC;
break;
case NFAPI_NR_RNTI_P:
pdcch_params->rnti_type = NFAPI_NR_RNTI_P;
break;
case NFAPI_NR_RNTI_SI:
pdcch_params->rnti_type = NFAPI_NR_RNTI_SI;
break;
}
switch (search_space->css_format_2_0){
case NFAPI_NR_RNTI_SFI:
pdcch_params->rnti_type = NFAPI_NR_RNTI_SFI;
break;
}
switch (search_space->css_format_2_1){
case NFAPI_NR_RNTI_INT:
pdcch_params->rnti_type = NFAPI_NR_RNTI_INT;
break;
}
switch (search_space->css_format_2_2){
case NFAPI_NR_RNTI_TPC_PUSCH:
pdcch_params->rnti_type = NFAPI_NR_RNTI_TPC_PUSCH;
break;
case NFAPI_NR_RNTI_TPC_PUCCH:
pdcch_params->rnti_type = NFAPI_NR_RNTI_TPC_PUCCH;
break;
}
switch (search_space->css_format_2_3){
case NFAPI_NR_RNTI_TPC_SRS:
pdcch_params->rnti_type = NFAPI_NR_RNTI_TPC_SRS;
break;
}
}
//Ue_Specific_USS
if (pdcch_params->search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC){
switch (search_space->uss_dci_formats){
case NFAPI_NR_RNTI_C:
pdcch_params->rnti_type = NFAPI_NR_RNTI_C;
break;
case NFAPI_NR_RNTI_CS:
pdcch_params->rnti_type = NFAPI_NR_RNTI_CS;
break;
case NFAPI_NR_RNTI_SP_CSI:
pdcch_params->rnti_type = NFAPI_NR_RNTI_SP_CSI;
break;
}
}
*/
pdcch_params->n_RB_BWP = N_RB;
}
int nr_is_dci_opportunity(nfapi_nr_search_space_t search_space,
nfapi_nr_coreset_t coreset,
uint16_t frame,
uint16_t slot,
nfapi_nr_config_request_t cfg) {
AssertFatal(search_space.coreset_id==coreset.coreset_id, "Invalid association of coreset(%d) and search space(%d)\n",
search_space.search_space_id, coreset.coreset_id);
uint8_t is_dci_opportunity=0;
uint16_t Ks=search_space.slot_monitoring_periodicity;
uint16_t Os=search_space.slot_monitoring_offset;
uint8_t Ts=search_space.duration;
if (((frame*get_spf(&cfg) + slot - Os)%Ks)<Ts)
is_dci_opportunity=1;
return is_dci_opportunity;
}
int get_dlscs(nfapi_nr_config_request_t *cfg) {
@@ -237,3 +543,13 @@ int to_absslot(nfapi_nr_config_request_t *cfg,int frame,int slot) {
return(get_spf(cfg)*frame) + slot;
}
int get_symbolsperslot(nfapi_nr_config_request_t *cfg) {
return ((cfg->subframe_config.dl_cyclic_prefix_type.value==NFAPI_CP_EXTENDED)?12:14);
}
int nr_schedule_dci() {
}
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
+14 -2
View File
@@ -72,13 +72,23 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p
nr_frequency_range_e freq_range,
uint8_t rmsi_pdcch_config,
uint8_t ssb_idx,
uint8_t k_ssb,
uint16_t sfn_ssb,
uint8_t n_ssb,
uint16_t nb_slots_per_frame,
uint16_t N_RB);
int nr_is_dci_opportunity(nfapi_nr_search_space_t search_space,
nfapi_nr_coreset_t coreset,
uint16_t frame,
uint16_t slot,
nfapi_nr_config_request_t cfg);
void nr_configure_css_dci_from_pdcch_config(nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params,
void nr_configure_dci_from_pdcch_config(nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params,
nfapi_nr_coreset_t* coreset,
nfapi_nr_search_space_t* search_space);
nfapi_nr_search_space_t* search_space,
nfapi_nr_config_request_t cfg,
uint16_t N_RB);
int get_dlscs(nfapi_nr_config_request_t *cfg);
@@ -88,4 +98,6 @@ int get_spf(nfapi_nr_config_request_t *cfg);
int to_absslot(nfapi_nr_config_request_t *cfg,int frame,int slot);
int get_symbolsperslot(nfapi_nr_config_request_t *cfg);
#endif /*__LAYER2_NR_MAC_PROTO_H__*/
openair2/LAYER2/NR_MAC_gNB/main.c
+38 -6
View File
@@ -44,6 +44,34 @@
extern RAN_CONTEXT_t RC;
void nr_init_coreset(nfapi_nr_coreset_t *coreset) {
coreset->coreset_id = 1;
coreset->frequency_domain_resources = 0x1E0000000000;//0x1FFFE0000000; // 96 RB starting from CRB0
coreset->duration = 2;
coreset->cce_reg_mapping_type = NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED;
coreset->reg_bundle_size = 6;
coreset->interleaver_size = 2;
coreset->precoder_granularity = NFAPI_NR_CSET_SAME_AS_REG_BUNDLE;
coreset->tci_present_in_dci = 0;
coreset->dmrs_scrambling_id = 0;
}
void nr_init_search_space(nfapi_nr_search_space_t *search_space) {
search_space->search_space_id = 1;
search_space->coreset_id = 1;
search_space->search_space_type = NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC;
search_space->duration = 5;
search_space->slot_monitoring_periodicity = NFAPI_NR_SS_PERIODICITY_SL10;
search_space->slot_monitoring_offset = 1;
search_space->monitoring_symbols_in_slot = 0xC0000000; // first 2 ofdm symbols
search_space->css_formats_0_0_and_1_0 = 1;
search_space->uss_dci_formats = 0; // enum to be defined-- formats 0.0 and 1.0
for (int i=0; i<NFAPI_NR_MAX_NB_CCE_AGGREGATION_LEVELS; i++)
search_space->number_of_candidates[i] = 4; // TODO
}
void mac_top_init_gNB(void)
{
module_id_t i,j;
@@ -56,24 +84,24 @@ void mac_top_init_gNB(void)
if (RC.nb_nr_macrlc_inst > 0) {
RC.nrmac = (gNB_MAC_INST **) malloc16(RC.nb_nr_macrlc_inst *sizeof(gNB_MAC_INST *));
AssertFatal(RC.nrmac != NULL,"can't ALLOCATE %zu Bytes for %d gNB_MAC_INST with size %zu \n",
RC.nb_nr_macrlc_inst * sizeof(gNB_MAC_INST *),
RC.nb_nr_macrlc_inst, sizeof(gNB_MAC_INST));
for (i = 0; i < RC.nb_nr_macrlc_inst; i++) {
RC.nrmac[i] = (gNB_MAC_INST *) malloc16(sizeof(gNB_MAC_INST));
AssertFatal(RC.nrmac != NULL,"can't ALLOCATE %zu Bytes for %d gNB_MAC_INST with size %zu \n",
RC.nb_nr_macrlc_inst * sizeof(gNB_MAC_INST *),
RC.nb_nr_macrlc_inst, sizeof(gNB_MAC_INST));
LOG_D(MAC,"[MAIN] ALLOCATE %zu Bytes for %d gNB_MAC_INST @ %p\n",sizeof(gNB_MAC_INST), RC.nb_nr_macrlc_inst, RC.mac);
bzero(RC.nrmac[i], sizeof(gNB_MAC_INST));
RC.nrmac[i]->Mod_id = i;
for (j = 0; j < MAX_NUM_CCs; j++) {
RC.nrmac[i]->DL_req[j].dl_config_request_body.dl_config_pdu_list = RC.nrmac[i]->dl_config_pdu_list[j];
@@ -84,7 +112,11 @@ void mac_top_init_gNB(void)
RC.nrmac[i]->HI_DCI0_req[j].hi_dci0_request_body.hi_dci0_pdu_list = RC.nrmac[i]->hi_dci0_pdu_list[j];
RC.nrmac[i]->TX_req[j].tx_request_body.tx_pdu_list = RC.nrmac[i]->tx_request_pdu[j];
RC.nrmac[i]->ul_handle = 0;
RC.nrmac[i]->ul_handle = 0;
// Init PDCCH structures
nr_init_coreset(&RC.nrmac[i]->coreset[j][1]);
nr_init_search_space(&RC.nrmac[i]->search_space[j][1]);
}
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
+4
View File
@@ -138,6 +138,10 @@ typedef struct gNB_MAC_INST_s {
nfapi_tx_request_pdu_t tx_request_pdu[NFAPI_CC_MAX][MAX_NUM_TX_REQUEST_PDU];
/// NFAPI DL PDU structure
nfapi_tx_request_t TX_req[NFAPI_CC_MAX];
/// NFAPI coreset structure
nfapi_nr_coreset_t coreset[NFAPI_CC_MAX][NFAPI_NR_MAX_NB_CORESETS];
/// NFAPI search space structure
nfapi_nr_search_space_t search_space[NFAPI_CC_MAX][NFAPI_NR_MAX_NB_SEARCH_SPACES];
UE_list_t UE_list;
openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c
+3 -3
View File
@@ -283,9 +283,9 @@ int nr_ue_dcireq(nr_dcireq_t *dcireq) {
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.rb_offset = rb_offset; // additional parameter other than coreset
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.duration = num_symbols;
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_mapping_type =CCE_REG_MAPPING_TYPE_INTERLEAVED;
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_interleaved_reg_bundle_size = 6; // L 38.211 7.3.2.2
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_interleaved_interleaver_size = 2; // R 38.211 7.3.2.2
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_mapping_type =CCE_REG_MAPPING_TYPE_NON_INTERLEAVED;
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_interleaved_reg_bundle_size = 0; // L 38.211 7.3.2.2
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_interleaved_interleaver_size = 0; // R 38.211 7.3.2.2
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_interleaved_shift_index = cell_id;
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.precoder_granularity = PRECODER_GRANULARITY_SAME_AS_REG_BUNDLE;
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.pdcch_dmrs_scrambling_id = cell_id;
openair2/RRC/NR_UE/rrc_UE.c
+18 -19
View File
@@ -322,25 +322,24 @@ int8_t nr_rrc_ue_decode_NR_BCCH_BCH_Message(
(const void *)bufferP,
buffer_len );
if(bcch_message->message.choice.mib->systemFrameNumber.buf != 0){
if ((dec_rval.code != RC_OK) || (dec_rval.consumed == 0)) {
printf("NR_CellGroupConfig decode error\n");
for (i=0; i<buffer_len; i++){
printf("%02x ",bufferP[i]);
}
printf("\n");
// free the memory
SEQUENCE_free( &asn_DEF_NR_BCCH_BCH_Message, (void *)bcch_message, 1 );
return -1;
}
// link to rrc instance
mib = bcch_message->message.choice.mib;
//memcpy( (void *)mib,
// (void *)&bcch_message->message.choice.mib,
// sizeof(NR_MIB_t) );
nr_rrc_mac_config_req_ue( 0, 0, 0, mib, NULL, NULL, NULL);
if ((dec_rval.code != RC_OK) || (dec_rval.consumed == 0)) {
printf("NR_BCCH_BCH decode error\n");
for (i=0; i<buffer_len; i++){
printf("%02x ",bufferP[i]);
}
printf("\n");
// free the memory
SEQUENCE_free( &asn_DEF_NR_BCCH_BCH_Message, (void *)bcch_message, 1 );
return -1;
}
else {
// link to rrc instance
mib = bcch_message->message.choice.mib;
//memcpy( (void *)mib,
// (void *)&bcch_message->message.choice.mib,
// sizeof(NR_MIB_t) );
nr_rrc_mac_config_req_ue( 0, 0, 0, mib, NULL, NULL, NULL);
}
return 0;