Added documentation. Minor source code format fixes.
This commit is contained in:
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@@ -295,6 +295,7 @@ The following features are valid for the gNB and the 5G-NR UE.
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- NR RRC (38.331) Rel 15 messages using new asn1c
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- NR RRC (38.331) Rel 15 messages using new asn1c
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- LTE RRC (36.331) also updated to Rel 15
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- LTE RRC (36.331) also updated to Rel 15
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- Generation of CellGroupConfig (for eNB) and MIB
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- Generation of CellGroupConfig (for eNB) and MIB
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- Generation of system information block 1 (SIB1)
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- Application to read configuration file and program gNB RRC
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- Application to read configuration file and program gNB RRC
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- RRC can configure PDCP, RLC, MAC
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- RRC can configure PDCP, RLC, MAC
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@@ -305,7 +306,8 @@ The following features are valid for the gNB and the 5G-NR UE.
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**gNB MAC**
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**gNB MAC**
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- MAC -> PHY configuration using NR FAPI P5 interface
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- MAC -> PHY configuration using NR FAPI P5 interface
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- MAC <-> PHY data interface using FAPI P7 interface for BCH PDU, DCI PDU, PDSCH PDU
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- MAC <-> PHY data interface using FAPI P7 interface for BCH PDU, DCI PDU, PDSCH PDU
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- Scheduler for RA procedreat gNB
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- Scheduler procedures for SIB1
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- Scheduler procedures for RA
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- MAC downlink scheduler (fixed allocations)
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- MAC downlink scheduler (fixed allocations)
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- MAC header generation (including timing advance)
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- MAC header generation (including timing advance)
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- ACK / NACK handling and HARQ procedures for downlink
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- ACK / NACK handling and HARQ procedures for downlink
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@@ -350,11 +352,13 @@ The following features are valid for the gNB and the 5G-NR UE.
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## UE Higher Layers ##
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## UE Higher Layers ##
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**gNB MAC**
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**UE MAC**
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- Initial sync and MIB detection
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* Minimum system information (MSI)
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- MAC -> PHY configuration of PHY via UE FAPI P5 interface
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- Initial sync and MIB detection
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- Basic MAC to control PHY via UE FAPI P7 interface
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- System information block 1 (SIB1) reception
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- Random access procedure
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* MAC -> PHY configuration of PHY via UE FAPI P5 interface
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* Basic MAC to control PHY via UE FAPI P7 interface
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* Random access procedure
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**RLC**
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**RLC**
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@@ -132,6 +132,32 @@ With the RF simulator (on the same machine):
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`sudo RFSIMULATOR=127.0.0.1 ./nr-uesoftmodem --do-ra --rfsim --parallel-config PARALLEL_SINGLE_THREAD`
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`sudo RFSIMULATOR=127.0.0.1 ./nr-uesoftmodem --do-ra --rfsim --parallel-config PARALLEL_SINGLE_THREAD`
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## sa setup with OAI
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The sa flag is used to run gNB in standalone mode. Currently OAI in NR standalone mode transmits and receives SIB1.
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In order to run gNB in standalone mode, the following flag is needed at gNB:
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`--sa`
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### Run OAI in sa mode
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From the `cmake_targets/ran_build/build` folder:
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gNB on machine 1:
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`sudo ./nr-softmodem -O ../../../targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band78.fr1.106PRB.usrpb210.conf --sa`
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UE on machine 2:
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`sudo ./nr-uesoftmodem --rrc_config_path . --phy-test`
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With the RF simulator (on the same machine):
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`sudo ./nr-softmodem -O ../../../targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band78.fr1.106PRB.usrpb210.conf --rfsim --sa`
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`sudo ./nr-uesoftmodem --rrc_config_path . --rfsim --phy-test`
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## IF setup with OAI
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## IF setup with OAI
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The -C and -CO flags can be used together at UE side to set custom downlink and uplink FR1 intermediate frequencies for the IF equipment.
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The -C and -CO flags can be used together at UE side to set custom downlink and uplink FR1 intermediate frequencies for the IF equipment.
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@@ -725,14 +725,12 @@ int nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB_
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if (!dlsch1) {
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if (!dlsch1) {
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int harq_pid = dlsch0->current_harq_pid;
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int harq_pid = dlsch0->current_harq_pid;
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uint16_t BWPStart = dlsch0->harq_processes[harq_pid]->BWPStart;
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// uint16_t BWPSize = dlsch0->harq_processes[harq_pid]->BWPSize;
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uint16_t pdsch_start_rb = dlsch0->harq_processes[harq_pid]->start_rb;
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uint16_t pdsch_nb_rb = dlsch0->harq_processes[harq_pid]->nb_rb;
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uint16_t s0 = dlsch0->harq_processes[harq_pid]->start_symbol;
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uint16_t s1 = dlsch0->harq_processes[harq_pid]->nb_symbols;
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NR_DL_UE_HARQ_t *dlsch0_harq = dlsch0->harq_processes[harq_pid];
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NR_DL_UE_HARQ_t *dlsch0_harq = dlsch0->harq_processes[harq_pid];
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uint16_t nb_rb = dlsch0_harq->nb_rb/ue->frame_parms.nb_antennas_rx;
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uint16_t BWPStart = dlsch0_harq->BWPStart;
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uint16_t pdsch_start_rb = dlsch0_harq->start_rb;
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uint16_t pdsch_nb_rb = dlsch0_harq->nb_rb;
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uint16_t s0 = dlsch0_harq->start_symbol;
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uint16_t s1 = dlsch0_harq->nb_symbols;
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LOG_D(PHY,"[UE %d] PDSCH type %d active in nr_slot_rx %d, harq_pid %d (%d), rb_start %d, nb_rb %d, symbol_start %d, nb_symbols %d, DMRS mask %x\n",ue->Mod_id,pdsch,nr_slot_rx,harq_pid,dlsch0->harq_processes[harq_pid]->status,pdsch_start_rb,pdsch_nb_rb,s0,s1,dlsch0->harq_processes[harq_pid]->dlDmrsSymbPos);
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LOG_D(PHY,"[UE %d] PDSCH type %d active in nr_slot_rx %d, harq_pid %d (%d), rb_start %d, nb_rb %d, symbol_start %d, nb_symbols %d, DMRS mask %x\n",ue->Mod_id,pdsch,nr_slot_rx,harq_pid,dlsch0->harq_processes[harq_pid]->status,pdsch_start_rb,pdsch_nb_rb,s0,s1,dlsch0->harq_processes[harq_pid]->dlDmrsSymbPos);
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@@ -766,10 +764,15 @@ int nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB_
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}
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}
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uint16_t first_symbol_with_data = s0;
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uint16_t first_symbol_with_data = s0;
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uint8_t pilots = ((1<<s0)&dlsch0_harq->dlDmrsSymbPos)>0 ? 1 : 0;
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uint32_t dmrs_data_re;
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uint32_t len = (pilots==1)? ((ue->dmrs_DownlinkConfig.pdsch_dmrs_type==pdsch_dmrs_type1)?nb_rb*(12-6*dlsch0_harq->n_dmrs_cdm_groups): nb_rb*(12-4*dlsch0_harq->n_dmrs_cdm_groups)):(nb_rb*12);
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if(len == 0) {
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if (ue->dmrs_DownlinkConfig.pdsch_dmrs_type == pdsch_dmrs_type1)
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first_symbol_with_data = first_symbol_with_data + 1; // TODO: Replace "1" by dmrs duration
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dmrs_data_re = 12 - 6 * dlsch0_harq->n_dmrs_cdm_groups;
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else
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dmrs_data_re = 12 - 4 * dlsch0_harq->n_dmrs_cdm_groups;
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while ((dmrs_data_re == 0) && (dlsch0_harq->dlDmrsSymbPos & (1 << first_symbol_with_data))) {
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first_symbol_with_data++;
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}
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}
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for (m = s0; m < (s1 + s0); m++) {
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for (m = s0; m < (s1 + s0); m++) {
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@@ -778,9 +781,10 @@ int nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB_
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eNB_id_i = eNB_id+1;
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eNB_id_i = eNB_id+1;
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i_mod = 0;
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i_mod = 0;
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if (( m==first_symbol_with_data ) && (m<4))
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if (( m==first_symbol_with_data ) && (m<4))
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first_symbol_flag = 1;
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first_symbol_flag = 1;
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else
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else
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first_symbol_flag = 0;
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first_symbol_flag = 0;
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#if UE_TIMING_TRACE
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#if UE_TIMING_TRACE
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uint8_t slot = 0;
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uint8_t slot = 0;
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if(m >= ue->frame_parms.symbols_per_slot>>1)
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if(m >= ue->frame_parms.symbols_per_slot>>1)
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@@ -805,8 +809,8 @@ int nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB_
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return -1;
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return -1;
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}
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}
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else { // This is to adjust the llr offset in the case of skipping over a dmrs symbol (i.e. in case of no PDSCH REs in DMRS)
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else { // This is to adjust the llr offset in the case of skipping over a dmrs symbol (i.e. in case of no PDSCH REs in DMRS)
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if (pdsch == RA_PDSCH) ue->pdsch_vars[proc->thread_id][eNB_id]->llr_offset[m]=ue->pdsch_vars[proc->thread_id][eNB_id]->llr_offset[m-1];
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if (pdsch == RA_PDSCH) ue->pdsch_vars[proc->thread_id][eNB_id]->llr_offset[m]=ue->pdsch_vars[proc->thread_id][eNB_id]->llr_offset[m-1];
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else if (pdsch == PDSCH || pdsch == SI_PDSCH) {
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else if (pdsch == PDSCH || pdsch == SI_PDSCH) {
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if (nr_rx_pdsch(ue,
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if (nr_rx_pdsch(ue,
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proc,
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proc,
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pdsch,
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pdsch,
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@@ -821,7 +825,7 @@ int nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB_
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dlsch0->current_harq_pid) < 0)
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dlsch0->current_harq_pid) < 0)
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return -1;
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return -1;
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}
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}
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else AssertFatal(1==0,"Not RA_PDSCH, SI_PDSCH or PDSCH\n");
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else AssertFatal(1==0,"Not RA_PDSCH, SI_PDSCH or PDSCH\n");
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}
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}
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if (pdsch == PDSCH) LOG_D(PHY,"Done processing symbol %d : llr_offset %d\n",m,ue->pdsch_vars[proc->thread_id][eNB_id]->llr_offset[m]);
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if (pdsch == PDSCH) LOG_D(PHY,"Done processing symbol %d : llr_offset %d\n",m,ue->pdsch_vars[proc->thread_id][eNB_id]->llr_offset[m]);
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#if UE_TIMING_TRACE
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#if UE_TIMING_TRACE
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@@ -274,7 +274,6 @@ RUs = (
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eNB_instances = [0];
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eNB_instances = [0];
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#beamforming 1x4 matrix:
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#beamforming 1x4 matrix:
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bf_weights = [0x00007fff, 0x0000, 0x0000, 0x0000];
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bf_weights = [0x00007fff, 0x0000, 0x0000, 0x0000];
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sdr_addrs = "addr=192.168.10.2,mgmt_addr=192.168.10.2,second_addr=192.168.20.2";
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clock_src = "internal";
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clock_src = "internal";
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}
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}
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);
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);
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