From 4fb78818d28e0949f93898ffcab0cec79ad1ea08 Mon Sep 17 00:00:00 2001 From: luis_pereira87 Date: Mon, 5 Sep 2022 13:24:23 +0100 Subject: [PATCH] Fix 16 bit memory alignment on mod_dmrs buffer --- openair1/PHY/NR_TRANSPORT/nr_dci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.c b/openair1/PHY/NR_TRANSPORT/nr_dci.c index beb22217d9..6714a98536 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.c @@ -87,7 +87,7 @@ void nr_generate_dci(PHY_VARS_gNB *gNB, get_coreset_rballoc(pdcch_pdu_rel15->FreqDomainResource,&n_rb,&rb_offset); cset_start_sc = frame_parms->first_carrier_offset + (pdcch_pdu_rel15->BWPStart + rb_offset) * NR_NB_SC_PER_RB; - int16_t mod_dmrs[pdcch_pdu_rel15->StartSymbolIndex+pdcch_pdu_rel15->DurationSymbols][(n_rb+rb_offset+pdcch_pdu_rel15->BWPStart)*6] __attribute__((aligned(16))); // 3 for the max coreset duration + int16_t mod_dmrs[pdcch_pdu_rel15->StartSymbolIndex+pdcch_pdu_rel15->DurationSymbols][(((n_rb+rb_offset+pdcch_pdu_rel15->BWPStart)*6+15)>>4)<<4] __attribute__((aligned(16))); // 3 for the max coreset duration for (int d=0;dnumDlDci;d++) { /*The coreset is initialised