From 69195457d70f600e71d7d872936063108087250e Mon Sep 17 00:00:00 2001 From: Jaroslava Fiedlerova Date: Thu, 19 Dec 2024 13:03:49 +0100 Subject: [PATCH 1/3] CI: Increase number of test trials in nr_ulsim/nr_dlsim timing test Increasing a number of test trials aims to reduce variations and improve reliability of the nr_ulsim and nr_dlsim test results. --- .../xml_files/t2_offload_dec_nr_ulsim.xml | 36 +++++++------- .../xml_files/t2_offload_enc_nr_dlsim.xml | 48 +++++++++---------- 2 files changed, 42 insertions(+), 42 deletions(-) diff --git a/ci-scripts/xml_files/t2_offload_dec_nr_ulsim.xml b/ci-scripts/xml_files/t2_offload_dec_nr_ulsim.xml index 808f7155b5..639cf5926b 100644 --- a/ci-scripts/xml_files/t2_offload_dec_nr_ulsim.xml +++ b/ci-scripts/xml_files/t2_offload_dec_nr_ulsim.xml @@ -36,7 +36,7 @@ true nr_ulsim 300 - -n100 -s30 -S30.2 -m5 -r106 -R106 -C10 -P + -n1000 -s30 -S30.2 -m5 -r106 -R106 -C10 -P @@ -45,7 +45,7 @@ true nr_ulsim 100 - -n100 -s30 -S30.2 -m5 -r106 -R106 -C10 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 + -n1000 -s30 -S30.2 -m5 -r106 -R106 -C10 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 @@ -54,7 +54,7 @@ true nr_ulsim 300 - -n100 -s30 -S30.2 -m15 -r106 -R106 -C10 -P + -n1000 -s30 -S30.2 -m15 -r106 -R106 -C10 -P @@ -63,7 +63,7 @@ true nr_ulsim 150 - -n100 -s30 -S30.2 -m15 -r106 -R106 -C10 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 + -n1000 -s30 -S30.2 -m15 -r106 -R106 -C10 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 @@ -72,7 +72,7 @@ true nr_ulsim 250 - -n100 -s30 -S30.2 -m25 -r106 -R106 -C10 -P + -n1000 -s30 -S30.2 -m25 -r106 -R106 -C10 -P @@ -81,7 +81,7 @@ true nr_ulsim 250 - -n100 -s30 -S30.2 -m25 -r106 -R106 -C10 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 + -n1000 -s30 -S30.2 -m25 -r106 -R106 -C10 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 @@ -90,7 +90,7 @@ true nr_ulsim 300 - -n100 -s30 -S30.2 -m5 -r273 -R273 -C10 -P + -n1000 -s30 -S30.2 -m5 -r273 -R273 -C10 -P @@ -99,7 +99,7 @@ true nr_ulsim 150 - -n100 -s30 -S30.2 -m5 -r273 -R273 -C10 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 + -n1000 -s30 -S30.2 -m5 -r273 -R273 -C10 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 @@ -108,7 +108,7 @@ true nr_ulsim 400 - -n100 -s30 -S30.2 -m15 -r273 -R273 -C10 -P + -n1000 -s30 -S30.2 -m15 -r273 -R273 -C10 -P @@ -117,7 +117,7 @@ true nr_ulsim 350 - -n100 -s30 -S30.2 -m15 -r273 -R273 -C10 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 + -n1000 -s30 -S30.2 -m15 -r273 -R273 -C10 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 @@ -126,7 +126,7 @@ true nr_ulsim 400 - -n100 -s30 -S30.2 -m25 -r273 -R273 -C10 -P + -n1000 -s30 -S30.2 -m25 -r273 -R273 -C10 -P @@ -135,7 +135,7 @@ true nr_ulsim 550 - -n100 -s30 -S30.2 -m25 -r273 -R273 -C10 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 + -n1000 -s30 -S30.2 -m25 -r273 -R273 -C10 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 @@ -144,7 +144,7 @@ true nr_ulsim 300 - -n100 -s30 -S30.2 -m5 -r273 -R273 -C10 -W2 -z2 -y2 -P + -n1000 -s30 -S30.2 -m5 -r273 -R273 -C10 -W2 -z2 -y2 -P @@ -153,7 +153,7 @@ true nr_ulsim 250 - -n100 -s30 -S30.2 -m5 -r273 -R273 -C10 -W2 -z2 -y2 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 + -n1000 -s30 -S30.2 -m5 -r273 -R273 -C10 -W2 -z2 -y2 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 @@ -162,7 +162,7 @@ true nr_ulsim 600 - -n100 -s30 -S30.2 -m15 -r273 -R273 -C10 -W2 -z2 -y2 -P + -n1000 -s30 -S30.2 -m15 -r273 -R273 -C10 -W2 -z2 -y2 -P @@ -171,7 +171,7 @@ true nr_ulsim 650 - -n100 -s30 -S30.2 -m15 -r273 -R273 -C10 -W2 -z2 -y2 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 + -n1000 -s30 -S30.2 -m15 -r273 -R273 -C10 -W2 -z2 -y2 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 @@ -180,7 +180,7 @@ true nr_ulsim 650 - -n100 -s30 -S30.2 -m25 -r273 -R273 -C10 -W2 -z2 -y2 -P + -n1000 -s30 -S30.2 -m25 -r273 -R273 -C10 -W2 -z2 -y2 -P @@ -189,7 +189,7 @@ true nr_ulsim 1100 - -n100 -s30 -S30.2 -m25 -r273 -R273 -C10 -W2 -z2 -y2 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 + -n1000 -s30 -S30.2 -m25 -r273 -R273 -C10 -W2 -z2 -y2 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 diff --git a/ci-scripts/xml_files/t2_offload_enc_nr_dlsim.xml b/ci-scripts/xml_files/t2_offload_enc_nr_dlsim.xml index f1217ae737..9434d93bb2 100644 --- a/ci-scripts/xml_files/t2_offload_enc_nr_dlsim.xml +++ b/ci-scripts/xml_files/t2_offload_enc_nr_dlsim.xml @@ -37,7 +37,7 @@ true nr_dlsim 230 - -n100 -s30 -S30.2 -e5 -b106 -R106 -X 8,9,10,11,12 -P + -n1000 -s30 -S30.2 -e5 -b106 -R106 -X 8,9,10,11,12 -P @@ -46,7 +46,7 @@ true nr_dlsim 100 - -n100 -s30 -S30.2 -e5 -b106 -R106 -X4,5,6,7,8,9 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 + -n1000 -s30 -S30.2 -e5 -b106 -R106 -X4,5,6,7,8,9 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 @@ -55,7 +55,7 @@ true nr_dlsim 300 - -n100 -s30 -S30.2 -e15 -b106 -R106 -X 8,9,10,11,12 -P + -n1000 -s30 -S30.2 -e15 -b106 -R106 -X 8,9,10,11,12 -P @@ -64,7 +64,7 @@ true nr_dlsim 100 - -n100 -s30 -S30.2 -e15 -b106 -R106 -X4,5,6,7,8,9 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 + -n1000 -s30 -S30.2 -e15 -b106 -R106 -X4,5,6,7,8,9 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 @@ -73,7 +73,7 @@ true nr_dlsim 350 - -n100 -s30 -S30.2 -e25 -b106 -R106 -X 8,9,10,11,12 -P + -n1000 -s30 -S30.2 -e25 -b106 -R106 -X 8,9,10,11,12 -P @@ -82,7 +82,7 @@ true nr_dlsim 200 - -n100 -s30 -S30.2 -e25 -b106 -R106 -X4,5,6,7,8,9 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 + -n1000 -s30 -S30.2 -e25 -b106 -R106 -X4,5,6,7,8,9 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 @@ -91,7 +91,7 @@ true nr_dlsim 300 - -n100 -s30 -S30.2 -e5 -b273 -R273 -X 8,9,10,11,12 -P + -n1000 -s30 -S30.2 -e5 -b273 -R273 -X 8,9,10,11,12 -P @@ -100,7 +100,7 @@ true nr_dlsim 150 - -n100 -s30 -S30.2 -e5 -b273 -R273 -X4,5,6,7,8,9 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 + -n1000 -s30 -S30.2 -e5 -b273 -R273 -X4,5,6,7,8,9 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 @@ -109,7 +109,7 @@ true nr_dlsim 350 - -n100 -s30 -S30.2 -e15 -b273 -R273 -X 8,9,10,11,12 -P + -n1000 -s30 -S30.2 -e15 -b273 -R273 -X 8,9,10,11,12 -P @@ -118,7 +118,7 @@ true nr_dlsim 250 - -n100 -s30 -S30.2 -e15 -b273 -R273 -X4,5,6,7,8,9 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 + -n1000 -s30 -S30.2 -e15 -b273 -R273 -X4,5,6,7,8,9 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 @@ -127,7 +127,7 @@ true nr_dlsim 400 - -n100 -s30 -S30.2 -e25 -b273 -R273 -X 8,9,10,11,12 -P + -n1000 -s30 -S30.2 -e25 -b273 -R273 -X 8,9,10,11,12 -P @@ -136,7 +136,7 @@ true nr_dlsim 400 - -n100 -s30 -S30.2 -e25 -b273 -R273 -X4,5,6,7,8,9 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 + -n1000 -s30 -S30.2 -e25 -b273 -R273 -X4,5,6,7,8,9 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 @@ -145,7 +145,7 @@ true nr_dlsim 400 - -n100 -s30 -S30.2 -e5 -b273 -R273 -X 8,9,10,11,12 -x2 -z2 -y2 -P + -n1000 -s30 -S30.2 -e5 -b273 -R273 -X 8,9,10,11,12 -x2 -z2 -y2 -P @@ -154,7 +154,7 @@ true nr_dlsim 200 - -n100 -s30 -S30.2 -e5 -b273 -R273 -X4,5,6,7,8,9 -x2 -z2 -y2 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 + -n1000 -s30 -S30.2 -e5 -b273 -R273 -X4,5,6,7,8,9 -x2 -z2 -y2 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 @@ -163,7 +163,7 @@ true nr_dlsim 450 - -n100 -s30 -S30.2 -e15 -b273 -R273 -X 8,9,10,11,12 -x2 -z2 -y2 -P + -n1000 -s30 -S30.2 -e15 -b273 -R273 -X 8,9,10,11,12 -x2 -z2 -y2 -P @@ -172,7 +172,7 @@ true nr_dlsim 500 - -n100 -s30 -S30.2 -e15 -b273 -R273 -X4,5,6,7,8,9 -x2 -z2 -y2 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 + -n1000 -s30 -S30.2 -e15 -b273 -R273 -X4,5,6,7,8,9 -x2 -z2 -y2 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 @@ -181,7 +181,7 @@ true nr_dlsim 500 - -n100 -s30 -S30.2 -e25 -b273 -R273 -X 8,9,10,11,12 -x2 -z2 -y2 -P + -n1000 -s30 -S30.2 -e25 -b273 -R273 -X 8,9,10,11,12 -x2 -z2 -y2 -P @@ -190,7 +190,7 @@ true nr_dlsim 500 - -n100 -s30 -S30.2 -e25 -b273 -R273 -X4,5,6,7,8,9 -x2 -z2 -y2 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 + -n1000 -s30 -S30.2 -e25 -b273 -R273 -X4,5,6,7,8,9 -x2 -z2 -y2 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 @@ -199,7 +199,7 @@ true nr_dlsim 400 - -n100 -s30 -S30.2 -e5 -b273 -R273 -X8,9,10,11,12 -x2 -z4 -y4 -P + -n1000 -s30 -S30.2 -e5 -b273 -R273 -X8,9,10,11,12 -x2 -z4 -y4 -P @@ -208,7 +208,7 @@ true nr_dlsim 200 - -n100 -s30 -S30.2 -e5 -b273 -R273 -X4,5,6,7,8,9 -x2 -z4 -y4 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 + -n1000 -s30 -S30.2 -e5 -b273 -R273 -X4,5,6,7,8,9 -x2 -z4 -y4 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 @@ -217,7 +217,7 @@ true nr_dlsim 400 - -n100 -s30 -S30.2 -e15 -b273 -R273 -X8,9,10,11,12 -x2 -z4 -y4 -P + -n1000 -s30 -S30.2 -e15 -b273 -R273 -X8,9,10,11,12 -x2 -z4 -y4 -P @@ -226,7 +226,7 @@ true nr_dlsim 300 - -n100 -s30 -S30.2 -e15 -b273 -R273 -X4,5,6,7,8,9 -x2 -z4 -y4 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 + -n1000 -s30 -S30.2 -e15 -b273 -R273 -X4,5,6,7,8,9 -x2 -z4 -y4 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 @@ -235,7 +235,7 @@ true nr_dlsim 450 - -n100 -s30 -S30.2 -e25 -b273 -R273 -X8,9,10,11,12 -x2 -z4 -y4 -P + -n1000 -s30 -S30.2 -e25 -b273 -R273 -X8,9,10,11,12 -x2 -z4 -y4 -P @@ -244,6 +244,6 @@ true nr_dlsim 450 - -n100 -s30 -S30.2 -e25 -b273 -R273 -X4,5,6,7,8,9 -x2 -z4 -y4 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 + -n1000 -s30 -S30.2 -e25 -b273 -R273 -X4,5,6,7,8,9 -x2 -z4 -y4 -P --loader.ldpc.shlibversion _t2 --nrLDPC_coding_t2.dpdk_dev d8:00.0 --nrLDPC_coding_t2.dpdk_core_list 11-12 From 9b6f1be163570a7e62b9c4c3dd12e8cfdf1fb1af Mon Sep 17 00:00:00 2001 From: Jaroslava Fiedlerova Date: Tue, 14 Jan 2025 12:14:03 +0100 Subject: [PATCH 2/3] CI: disable sleep states of CPU for running timing tests Enable sleep states once the test is done. --- .../xml_files/t2_offload_dec_nr_ulsim.xml | 17 +++++++++++++++++ .../xml_files/t2_offload_enc_nr_dlsim.xml | 17 +++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/ci-scripts/xml_files/t2_offload_dec_nr_ulsim.xml b/ci-scripts/xml_files/t2_offload_dec_nr_ulsim.xml index 639cf5926b..c959d99e1b 100644 --- a/ci-scripts/xml_files/t2_offload_dec_nr_ulsim.xml +++ b/ci-scripts/xml_files/t2_offload_dec_nr_ulsim.xml @@ -24,12 +24,29 @@ Test T2 Offload Decoder tasks + 010204 010111 010112 010121 010122 010131 010132 010211 010212 010221 010222 010231 010232 010311 010312 010321 010322 010331 010332 + 402010 + + Custom_Command + Disable Sleep States + caracal + sudo cpupower idle-set -D 0 + + + + Custom_Command + true + Enable Sleep States + caracal + sudo cpupower idle-set -E + + Run_Physim Run nr_ulsim with CPU: SNR = 30, MCS = 5, 106 PRBs, 1 layer diff --git a/ci-scripts/xml_files/t2_offload_enc_nr_dlsim.xml b/ci-scripts/xml_files/t2_offload_enc_nr_dlsim.xml index 9434d93bb2..400399d3a1 100644 --- a/ci-scripts/xml_files/t2_offload_enc_nr_dlsim.xml +++ b/ci-scripts/xml_files/t2_offload_enc_nr_dlsim.xml @@ -24,13 +24,30 @@ Test T2 Offload Encoder tasks + 102040 000111 000112 000121 000122 000131 000132 000211 000212 000221 000222 000231 000232 000311 000312 000321 000322 000331 000332 000411 000412 000421 000422 000431 000432 + 040201 + + Custom_Command + Disable Sleep States + caracal + sudo cpupower idle-set -D 0 + + + + Custom_Command + true + Enable Sleep States + caracal + sudo cpupower idle-set -E + + Run_Physim Run nr_dlsim with CPU: SNR = 30, MCS = 5, 106 PRBs, 1 layer From 85b163b6b995901aa226d1aa66966e701d3ceab2 Mon Sep 17 00:00:00 2001 From: Jaroslava Fiedlerova Date: Tue, 14 Jan 2025 12:26:57 +0100 Subject: [PATCH 3/3] CI: Adjust timing thresholds in timing-phytest pipeline CI test sometimes fails because measured value is lower than allowed threshold. --- ci-scripts/datalog_rt_stats.1x1.60.yaml | 2 +- ci-scripts/datalog_rt_stats.default.yaml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/ci-scripts/datalog_rt_stats.1x1.60.yaml b/ci-scripts/datalog_rt_stats.1x1.60.yaml index 140f3939d7..f2cd345737 100644 --- a/ci-scripts/datalog_rt_stats.1x1.60.yaml +++ b/ci-scripts/datalog_rt_stats.1x1.60.yaml @@ -10,7 +10,7 @@ Ref : feprx : 46.0 feptx_prec : 15.0 feptx_ofdm : 35.0 - feptx_total : 57.0 + feptx_total : 50.0 L1 Tx processing : 260.0 DLSCH encoding : 160.0 L1 Rx processing : 420.0 diff --git a/ci-scripts/datalog_rt_stats.default.yaml b/ci-scripts/datalog_rt_stats.default.yaml index 3e665f1f0b..1b83aed783 100644 --- a/ci-scripts/datalog_rt_stats.default.yaml +++ b/ci-scripts/datalog_rt_stats.default.yaml @@ -10,7 +10,7 @@ Ref : feprx : 43.0 feptx_prec : 13.0 feptx_ofdm : 33.0 - feptx_total : 55.0 + feptx_total : 50.0 L1 Tx processing : 200.0 DLSCH encoding : 100.0 L1 Rx processing : 330.0