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Add Sidelink (SL) carrier frequency

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1. Adding a "SL" frequency for Sidelink mode. The
   importance of this variable is to ensure that
   when we are in mode 1 (UE+UE+gNB), that the slot
   configuration and frequencies do not overlap. This
   SL frequency is important for rotation and allows
   us to utilize the OFDM modulation and demodulation
   functions that already exist in OAI.
2. Adding sl_mode to the command line for proper UE
   deployment when in SL mode. sl_mode can be set to 0,
   1, or 2. sl_mode 0 indicates no-Sidelink at all,
   mode 1 is gNB, UE, and UE (3GPP defines mode numbers).
   sl_mode 2 indicated UE to UE communications with no
   gNB at all.
3. New functions for calculating the carrier frequency
   for SL mode.
This commit is contained in:
Robert Schmidt
2023-06-16 11:11:44 +02:00
parent f8f9f8ac14
commit 555a54f85e
24 changed files with 159 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files
executables/nr-gnb.c
+2 -1
View File
@@ -236,7 +236,8 @@ void rx_func(void *param)
gNB->common_vars.rxdataF[aa],
slot_rx,
0,
gNB->frame_parms.Ncp==EXTENDED?12:14);
gNB->frame_parms.Ncp == EXTENDED ? 12 : 14,
link_type_ul);
}
}
phy_procedures_gNB_uespec_RX(gNB, frame_rx, slot_rx);
executables/nr-uesoftmodem.c
+8 -1
View File
@@ -128,6 +128,7 @@ int dumpframe = 0;
uint64_t downlink_frequency[MAX_NUM_CCs][4];
int32_t uplink_frequency_offset[MAX_NUM_CCs][4];
uint64_t sidelink_frequency[MAX_NUM_CCs][4];
int rx_input_level_dBm;
#if MAX_NUM_CCs == 1
@@ -317,7 +318,7 @@ void init_openair0(void) {
NR_DL_FRAME_PARMS *frame_parms = &PHY_vars_UE_g[0][0]->frame_parms;
for (card=0; card<MAX_CARDS; card++) {
uint64_t dl_carrier, ul_carrier;
uint64_t dl_carrier, ul_carrier, sl_carrier;
openair0_cfg[card].configFilename = NULL;
openair0_cfg[card].threequarter_fs = frame_parms->threequarter_fs;
openair0_cfg[card].sample_rate = frame_parms->samples_per_subframe * 1e3;
@@ -346,6 +347,12 @@ void init_openair0(void) {
nr_get_carrier_frequencies(PHY_vars_UE_g[0][0], &dl_carrier, &ul_carrier);
nr_rf_card_config_freq(&openair0_cfg[card], ul_carrier, dl_carrier, freq_off);
if (get_softmodem_params()->sl_mode == 2) {
nr_get_carrier_frequencies_sl(PHY_vars_UE_g[0][0], &sl_carrier);
nr_rf_card_config_freq(&openair0_cfg[card], sl_carrier, sl_carrier, freq_off);
}
nr_rf_card_config_gain(&openair0_cfg[card], rx_gain_off);
openair0_cfg[card].configFilename = get_softmodem_params()->rf_config_file;
executables/nr-uesoftmodem.h
+1
View File
@@ -60,6 +60,7 @@
{"chest-freq", CONFIG_HLP_CHESTFREQ, 0, .iptr=&(nrUE_params.chest_freq), .defintval=0, TYPE_INT, 0}, \
{"chest-time", CONFIG_HLP_CHESTTIME, 0, .iptr=&(nrUE_params.chest_time), .defintval=0, TYPE_INT, 0}, \
{"ue-timing-correction-disable", CONFIG_HLP_DISABLETIMECORR, PARAMFLAG_BOOL, .iptr=&(nrUE_params.no_timing_correction), .defintval=0, TYPE_INT, 0}, \
{"SLC", CONFIG_HLP_SLF, 0, .u64ptr=&(sidelink_frequency[0][0]), .defuintval=2600000000,TYPE_UINT64,0}, \
}
// clang-format on
executables/softmodem-common.h
+6
View File
@@ -58,6 +58,7 @@ extern "C"
#define CONFIG_HLP_PHYTST "test UE phy layer, mac disabled\n"
#define CONFIG_HLP_DORA "test gNB and UE with RA procedures\n"
#define CONFIG_HLP_SA "run gNB in standalone mode\n"
#define CONFIG_HLP_SL_MODE "sets the NR sidelink mode (0: not in sidelink mode, 1: in-coverage/gNB, 2: out-of-coverage/no gNB)"
#define CONFIG_HLP_EXTS "tells hardware to use an external timing reference\n"
#define CONFIG_HLP_DMRSSYNC "tells RU to insert DMRS in subframe 1 slot 0"
#define CONFIG_HLP_CLK "tells hardware to use a clock reference (0:internal, 1:external, 2:gpsdo)\n"
@@ -67,6 +68,7 @@ extern "C"
#define CONFIG_HLP_NOSNGLT "Disables single-thread mode in lte-softmodem\n"
#define CONFIG_HLP_DLF "Set the downlink frequency for all component carriers\n"
#define CONFIG_HLP_ULF "Set the uplink frequency offset for all component carriers\n"
#define CONFIG_HLP_SLF "Set the sidelink frequency for all component carriers\n"
#define CONFIG_HLP_CHOFF "Channel id offset\n"
#define CONFIG_HLP_SOFTS "Enable soft scope and L1 and L2 stats (Xforms)\n"
#define CONFIG_HLP_SOFTS_QT "Enable soft scope and L1 and L2 stats (QT)\n"
@@ -115,6 +117,7 @@ extern "C"
#define PHY_TEST softmodem_params.phy_test
#define DO_RA softmodem_params.do_ra
#define SA softmodem_params.sa
#define SL_MODE softmodem_params.sl_mode
#define WAIT_FOR_SYNC softmodem_params.wait_for_sync
#define SINGLE_THREAD_FLAG softmodem_params.single_thread_flag
#define CHAIN_OFFSET softmodem_params.chain_offset
@@ -146,6 +149,7 @@ extern int usrp_tx_thread;
{"phy-test", CONFIG_HLP_PHYTST, PARAMFLAG_BOOL, .iptr=&PHY_TEST, .defintval=0, TYPE_INT, 0}, \
{"do-ra", CONFIG_HLP_DORA, PARAMFLAG_BOOL, .iptr=&DO_RA, .defintval=0, TYPE_INT, 0}, \
{"sa", CONFIG_HLP_SA, PARAMFLAG_BOOL, .iptr=&SA, .defintval=0, TYPE_INT, 0}, \
{"sl-mode", CONFIG_HLP_SL_MODE, 0, .u8ptr=&SL_MODE, .defintval=0, TYPE_UINT8, 0}, \
{"usim-test", CONFIG_HLP_USIM, PARAMFLAG_BOOL, .u8ptr=&USIM_TEST, .defintval=0, TYPE_UINT8, 0}, \
{"clock-source", CONFIG_HLP_CLK, 0, .uptr=&CLOCK_SOURCE, .defintval=0, TYPE_UINT, 0}, \
{"time-source", CONFIG_HLP_TME, 0, .uptr=&TIMING_SOURCE, .defintval=0, TYPE_UINT, 0}, \
@@ -214,6 +218,7 @@ extern int usrp_tx_thread;
{ .s5 = { NULL } }, \
{ .s5 = { NULL } }, \
{ .s5 = { NULL } }, \
{ .s5 = { NULL } }, \
{ .s3a = { config_checkstr_assign_integer, \
{"MONOLITHIC", "PNF", "VNF","UE_STUB_PNF","UE_STUB_OFFNET","STANDALONE_PNF"}, \
{NFAPI_MONOLITHIC, NFAPI_MODE_PNF, NFAPI_MODE_VNF,NFAPI_UE_STUB_PNF,NFAPI_UE_STUB_OFFNET,NFAPI_MODE_STANDALONE_PNF}, \
@@ -308,6 +313,7 @@ typedef struct {
int phy_test;
int do_ra;
int sa;
uint8_t sl_mode;
uint8_t usim_test;
int emulate_rf;
int wait_for_sync; //eNodeB only