diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt index 76553ba1fd..77d50e4df9 100644 --- a/cmake_targets/CMakeLists.txt +++ b/cmake_targets/CMakeLists.txt @@ -1647,7 +1647,7 @@ set ( NR_LTE_UE_REUSE_SRC ${OPENAIR1_DIR}/PHY/CODING/viterbi.c ${OPENAIR1_DIR}/PHY/LTE_TRANSPORT/phich_common.c ${OPENAIR1_DIR}/PHY/LTE_UE_TRANSPORT/dlsch_llr_computation.c - ${OPENAIR1_DIR}/PHY/LTE_TRANSPORT/dci_tools_common.c +# ${OPENAIR1_DIR}/PHY/LTE_TRANSPORT/dci_tools_common.c ${OPENAIR1_DIR}/PHY/CODING/lte_rate_matching.c ${OPENAIR1_DIR}/PHY/CODING/ccoding_byte_lte.c ${OPENAIR1_DIR}/PHY/CODING/ccoding_byte.c diff --git a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h index a141e68436..9c2681e6b1 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h @@ -452,7 +452,7 @@ typedef struct { uint8_t rnti_type; uint8_t dci_format; /// Number of CRB in BWP that this DCI configures - uint8_t n_RB_BWP; + uint16_t n_RB_BWP; uint8_t config_type; uint8_t search_space_type; uint8_t aggregation_level; diff --git a/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoder.c b/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoder.c index d3796143d2..bd35fa195d 100644 --- a/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoder.c +++ b/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoder.c @@ -1079,11 +1079,13 @@ uint32_t polar_decoder_int16(int16_t *input, int16_t d_tilde[polarParams->N];// = malloc(sizeof(double) * polarParams->N); + for (int i=0;iencoderLength;i++) printf("polar_input_RMin[%d] %d\n",i,input[i]); nr_polar_rate_matching_int16(input, d_tilde, polarParams->rate_matching_pattern, polarParams->K, polarParams->N, polarParams->encoderLength); for (int i=0;iN;i++) { if (d_tilde[i]<-128) d_tilde[i]=-128; else if (d_tilde[i]>127) d_tilde[i]=128; } + for (int i=0;iencoderLength;i++) printf("polar_input_RMout[%d] %d\n",i,d_tilde[i]); memcpy((void*)&polarParams->tree.root->alpha[0],(void*)&d_tilde[0],sizeof(int16_t)*polarParams->N); generic_polar_decoder(polarParams,polarParams->tree.root); diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.c b/openair1/PHY/NR_TRANSPORT/nr_dci.c index 650a0b88b9..52caff4a6c 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.c @@ -42,11 +42,10 @@ extern short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT]; uint16_t nr_get_dci_size(nfapi_nr_dci_format_e format, nfapi_nr_rnti_type_e rnti_type, - NR_BWP_PARMS* bwp, + uint16_t N_RB, nfapi_nr_config_request_t* config) { uint16_t size = 0; - uint16_t N_RB = bwp->N_RB; switch(format) { /*Only sizes for 0_0 and 1_0 are correct at the moment*/ @@ -54,7 +53,7 @@ uint16_t nr_get_dci_size(nfapi_nr_dci_format_e format, /// fixed: Format identifier 1, Hop flag 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2 Time Domain assgnmt 4 --20 size += 20; size += (uint8_t)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); // Freq domain assignment -- hopping scenario to be updated - size += nr_get_dci_size(NFAPI_NR_DL_DCI_FORMAT_1_0, rnti_type, bwp, config) - size; // Padding to match 1_0 size + size += nr_get_dci_size(NFAPI_NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB, config) - size; // Padding to match 1_0 size // UL/SUL indicator assumed to be 0 break; diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.h b/openair1/PHY/NR_TRANSPORT/nr_dci.h index 8d79311f35..90287dedf7 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.h +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.h @@ -29,7 +29,7 @@ typedef unsigned __int128 uint128_t; uint16_t nr_get_dci_size(nfapi_nr_dci_format_e format, nfapi_nr_rnti_type_e rnti_type, - NR_BWP_PARMS* bwp, + uint16_t N_RB, nfapi_nr_config_request_t* config); uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars, diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c index 4d685b6b39..27d671df08 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c @@ -114,16 +114,31 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB, { NR_DL_FRAME_PARMS *fp = &gNB->frame_parms; uint8_t n_shift; + uint32_t *dci_pdu = dci_alloc->dci_pdu; memset((void*)dci_pdu,0,4*sizeof(uint32_t)); nfapi_nr_dl_config_dci_dl_pdu_rel15_t *pdu_rel15 = &pdu->dci_dl_pdu.dci_dl_pdu_rel15; nfapi_nr_dl_config_pdcch_parameters_rel15_t *params_rel15 = &pdu->dci_dl_pdu.pdcch_params_rel15; + nfapi_nr_config_request_t *cfg = &gNB->gNB_config; + uint16_t N_RB = params_rel15->n_RB_BWP; uint8_t fsize=0, pos=0, cand_idx=0; + dci_alloc->L = 8; + memcpy((void*)&dci_alloc->pdcch_params, (void*)params_rel15, sizeof(nfapi_nr_dl_config_pdcch_parameters_rel15_t)); + dci_alloc->size = nr_get_dci_size(dci_alloc->pdcch_params.dci_format, + dci_alloc->pdcch_params.rnti_type, + N_RB, + cfg); + printf("DCI size for n_RB_BWP %d => %d\n",N_RB,dci_alloc->size); + AssertFatal(dci_alloc->size<=64, "DCI sizes above 64 bits not yet supported"); + n_shift = (dci_alloc->pdcch_params.config_type == NFAPI_NR_CSET_CONFIG_MIB_SIB1)? + cfg->sch_config.physical_cell_id.value : dci_alloc->pdcch_params.shift_index; + nr_fill_cce_list(dci_alloc, n_shift, cand_idx); + /// Payload generation switch(params_rel15->dci_format) { @@ -133,39 +148,263 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB, // Freq domain assignment fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); // Time domain assignment for (int i=0; i<4; i++) - *dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); // VRB to PRB mapping - *dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&1)<vrb_to_prb_mapping&1)<<(dci_alloc->size-pos++); // MCS for (int i=0; i<5; i++) - *dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<mcs>>(4-i))&1)<<(dci_alloc->size-pos++); // TB scaling for (int i=0; i<2; i++) - *dci_pdu |= ((pdu_rel15->tb_scaling>>(1-i))&1)<tb_scaling>>(1-i))&1)<<(dci_alloc->size-pos++); break; - } + + case NFAPI_NR_RNTI_C: + // indicating a DL DCI format 1bit + *dci_pdu |= (pdu_rel15->format_indicator&1)<<(dci_alloc->size-pos++); + // Freq domain assignment (275rb >> fsize = 16) + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); + + if ((pdu_rel15->frequency_domain_assignment+1)&1 ==0) //fsize are all 1 38.212 p86 + { + // ra_preamble_index 6 bits + for (int i=0; i<6; i++) + *dci_pdu |= ((pdu_rel15->ra_preamble_index>>(5-i))&1)<<(dci_alloc->size-pos++); + + // UL/SUL indicator 1 bit + *dci_pdu |= (pdu_rel15->ul_sul_indicator&1)<<(dci_alloc->size-pos++); + + // SS/PBCH index 6 bits + for (int i=0; i<6; i++) + *dci_pdu |= ((pdu_rel15->ss_pbch_index>>(5-i))&1)<<(dci_alloc->size-pos++); + + // prach_mask_index 4 bits + for (int i=0; i<4; i++) + *dci_pdu |= ((pdu_rel15->prach_mask_index>>(3-i))&1)<<(dci_alloc->size-pos++); + + } //end if + + else { + + // Time domain assignment 4bit + for (int i=0; i<4; i++) + *dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); + + // VRB to PRB mapping 1bit + *dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos++); + + // MCS 5bit //bit over 32, so dci_pdu ++ + for (int i=0; i<5; i++) + *dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++); + + // New data indicator 1bit + *dci_pdu |= (pdu_rel15->ndi&1)<<(dci_alloc->size-pos++); + + // Redundancy version 2bit + for (int i=0; i<2; i++) + *dci_pdu |= ((pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++); + + // HARQ process number 4bit + for (int i=0; i<4; i++) + *dci_pdu |= ((pdu_rel15->harq_pid>>(3-i))&1)<<(dci_alloc->size-pos++); + + // Downlink assignment index 2bit + for (int i=0; i<2; i++) + *dci_pdu |= ((pdu_rel15->dai>>(1-i))&1)<<(dci_alloc->size-pos++); + + // TPC command for scheduled PUCCH 2bit + for (int i=0; i<2; i++) + *dci_pdu |= ((pdu_rel15->tpc>>(1-i))&1)<<(dci_alloc->size-pos++); + + // PUCCH resource indicator 3bit + for (int i=0; i<3; i++) + *dci_pdu |= ((pdu_rel15->pucch_resource_indicator>>(2-i))&1)<<(dci_alloc->size-pos++); + + // PDSCH-to-HARQ_feedback timing indicator 3bit + for (int i=0; i<3; i++) + *dci_pdu |= ((pdu_rel15->pdsch_to_harq_feedback_timing_indicator>>(2-i))&1)<<(dci_alloc->size-pos++); + + } //end else + break; + + case NFAPI_NR_RNTI_P: + + // Short Messages Indicator – 2 bits + for (int i=0; i<2; i++) + *dci_pdu |= ((pdu_rel15->short_messages_indicator>>(1-i))&1)<<(dci_alloc->size-pos++); + // Short Messages – 8 bits + for (int i=0; i<8; i++) + *dci_pdu |= ((pdu_rel15->short_messages>>(7-i))&1)<<(dci_alloc->size-pos++); + // Freq domain assignment 0-16 bit + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); + // Time domain assignment 4 bit + for (int i=0; i<4; i++) + *dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); + // VRB to PRB mapping 1 bit + *dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos++); + // MCS 5 bit + for (int i=0; i<5; i++) + *dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++); + + // TB scaling 2 bit + for (int i=0; i<2; i++) + *dci_pdu |= ((pdu_rel15->tb_scaling>>(1-i))&1)<<(dci_alloc->size-pos++); + break; + + case NFAPI_NR_RNTI_SI: + // Freq domain assignment 0-16 bit + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); + // Time domain assignment 4 bit + for (int i=0; i<4; i++) + *dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); + // VRB to PRB mapping 1 bit + *dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos++); + // MCS 5bit //bit over 32, so dci_pdu ++ + for (int i=0; i<5; i++) + *dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++); + // Redundancy version 2bit + for (int i=0; i<2; i++) + *dci_pdu |= ((pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++); + + break; + + case NFAPI_NR_RNTI_TC: + // indicating a DL DCI format 1bit + *dci_pdu |= (pdu_rel15->format_indicator&1)<<(dci_alloc->size-pos++); + // Freq domain assignment 0-16 bit + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); + // Time domain assignment 4 bit + for (int i=0; i<4; i++) + *dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); + // VRB to PRB mapping 1 bit + *dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos++); + // MCS 5bit //bit over 32, so dci_pdu ++ + for (int i=0; i<5; i++) + *dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++); + // New data indicator 1bit + *dci_pdu |= (pdu_rel15->ndi&1)<<(dci_alloc->size-pos++); + // Redundancy version 2bit + for (int i=0; i<2; i++) + *dci_pdu |= ((pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++); + // HARQ process number 4bit + for (int i=0; i<4; i++) + *dci_pdu |= ((pdu_rel15->harq_pid>>(3-i))&1)<<(dci_alloc->size-pos++); + + // Downlink assignment index – 2 bits + for (int i=0; i<2; i++) + *dci_pdu |= ((pdu_rel15->dai>>(1-i))&1)<<(dci_alloc->size-pos++); + + // TPC command for scheduled PUCCH – 2 bits + for (int i=0; i<2; i++) + *dci_pdu |= ((pdu_rel15->tpc>>(1-i))&1)<<(dci_alloc->size-pos++); + + // PUCCH resource indicator – 3 bits + for (int i=0; i<3; i++) + *dci_pdu |= ((pdu_rel15->pucch_resource_indicator>>(2-i))&1)<<(dci_alloc->size-pos++); + + // PDSCH-to-HARQ_feedback timing indicator – 3 bits + for (int i=0; i<3; i++) + *dci_pdu |= ((pdu_rel15->pdsch_to_harq_feedback_timing_indicator>>(2-i))&1)<<(dci_alloc->size-pos++); + + break; + } case NFAPI_NR_UL_DCI_FORMAT_0_0: + switch(params_rel15->rnti_type) + { + case NFAPI_NR_RNTI_C: + // indicating a DL DCI format 1bit + *dci_pdu |= (pdu_rel15->format_indicator&1)<<(dci_alloc->size-pos++); + // Freq domain assignment max 16 bit + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); + // Time domain assignment 4bit + for (int i=0; i<4; i++) + *dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); + // Frequency hopping flag – 1 bit + *dci_pdu |= (pdu_rel15->frequency_hopping_flag&1)<<(dci_alloc->size-pos++); + // MCS 5 bit + for (int i=0; i<5; i++) + *dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++); + // New data indicator 1bit + *dci_pdu |= (pdu_rel15->ndi&1)<<(dci_alloc->size-pos++); + // Redundancy version 2bit + for (int i=0; i<2; i++) + *dci_pdu |= ((pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++); + // HARQ process number 4bit + for (int i=0; i<4; i++) + *dci_pdu |= ((pdu_rel15->harq_pid>>(3-i))&1)<<(dci_alloc->size-pos++); + + // TPC command for scheduled PUSCH – 2 bits + for (int i=0; i<2; i++) + *dci_pdu |= ((pdu_rel15->tpc>>(1-i))&1)<<(dci_alloc->size-pos++); + + // Padding bits + for(int a = pos;a<32;a++) + *dci_pdu |= (pdu_rel15->padding&1)<<(dci_alloc->size-pos++); + + // UL/SUL indicator – 1 bit + if (cfg->pucch_config.pucch_GroupHopping.value) + *dci_pdu |= (pdu_rel15->ul_sul_indicator&1)<<(dci_alloc->size-pos++); + + break; + + case NFAPI_NR_RNTI_TC: + + // indicating a DL DCI format 1bit + *dci_pdu |= (pdu_rel15->format_indicator&1)<<(dci_alloc->size-pos++); + // Freq domain assignment max 16 bit + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); + // Time domain assignment 4bit + for (int i=0; i<4; i++) + *dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); + // Frequency hopping flag – 1 bit + *dci_pdu |= (pdu_rel15->frequency_hopping_flag&1)<<(dci_alloc->size-pos++); + // MCS 5 bit + for (int i=0; i<5; i++) + *dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++); + // New data indicator 1bit + *dci_pdu |= (pdu_rel15->ndi&1)<<(dci_alloc->size-pos++); + // Redundancy version 2bit + for (int i=0; i<2; i++) + *dci_pdu |= ((pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++); + // HARQ process number 4bit + for (int i=0; i<4; i++) + *dci_pdu |= ((pdu_rel15->harq_pid>>(3-i))&1)<<(dci_alloc->size-pos++); + + // TPC command for scheduled PUSCH – 2 bits + for (int i=0; i<2; i++) + *dci_pdu |= ((pdu_rel15->tpc>>(1-i))&1)<<(dci_alloc->size-pos++); + + // Padding bits + for(int a = pos;a<32;a++) + *dci_pdu |= (pdu_rel15->padding&1)<<(dci_alloc->size-pos++); + + // UL/SUL indicator – 1 bit + if (cfg->pucch_config.pucch_GroupHopping.value) + *dci_pdu |= (pdu_rel15->ul_sul_indicator&1)<<(dci_alloc->size-pos++); + + break; + } break; } - LOG_I(PHY, "DCI PDU: [0]->0x%08x \t [1]->0x%08x \t [2]->0x%08x \t [3]->0x%08x\n", - dci_pdu[0], dci_pdu[1], dci_pdu[2], dci_pdu[3]); - - /// rest of DCI alloc - dci_alloc->L = 8; - memcpy((void*)&dci_alloc->pdcch_params, (void*)params_rel15, sizeof(nfapi_nr_dl_config_pdcch_parameters_rel15_t)); - dci_alloc->size = nr_get_dci_size(dci_alloc->pdcch_params.dci_format, - dci_alloc->pdcch_params.rnti_type, - &fp->initial_bwp_dl, - cfg); - n_shift = (dci_alloc->pdcch_params.config_type == NFAPI_NR_CSET_CONFIG_MIB_SIB1)? - cfg->sch_config.physical_cell_id.value : dci_alloc->pdcch_params.shift_index; - nr_fill_cce_list(dci_alloc, n_shift, cand_idx); + LOG_I(PHY, "DCI PDU: [0]->0x%16x \t [1]->0x%16x \n",dci_pdu[0], dci_pdu[1]); LOG_I(PHY, "DCI type %d payload (size %d) generated on candidate %d\n", dci_alloc->pdcch_params.dci_format, dci_alloc->size, cand_idx); } diff --git a/openair1/PHY/NR_TRANSPORT/nr_pbch.c b/openair1/PHY/NR_TRANSPORT/nr_pbch.c index 93288af29b..213e23cc45 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_pbch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_pbch.c @@ -305,7 +305,7 @@ int nr_generate_pbch(NR_gNB_PBCH *pbch, #endif /// CRC, coding and rate matching - polar_encoder_fast ((int64_t*)&pbch->pbch_a_prime, (uint32_t*)pbch->pbch_e, 0, polar_params); + polar_encoder_fast ((uint64_t*)&pbch->pbch_a_prime, (uint32_t*)pbch->pbch_e, 0, polar_params); #ifdef DEBUG_PBCH_ENCODING printf("Channel coding:\n"); for (int i=0; i [reg=%d,bundle_j=%d] z[%d]=(%d,%d) <-> \t[f_reg=%d,fbundle_j=%d] llr[%d]=(%d,%d) \n", - reg,bundle_j,(index_z + i),*(char*) &z[index_z + i],*(1 + (char*) &z[index_z + i]), - f_reg,f_bundle_j,(index_llr + i),*(char*) &llr[index_llr + i], *(1 + (char*) &llr[index_llr + i])); + reg,bundle_j,(index_z + i),*(int16_t*) &z[index_z + i],*(1 + (int16_t*) &z[index_z + i]), + f_reg,f_bundle_j,(index_llr + i),*(int16_t*) &llr[index_llr + i], *(1 + (int16_t*) &llr[index_llr + i])); #endif } if ((reg%reg_bundle_size_L) == 0) r++; @@ -152,35 +155,35 @@ void nr_pdcch_demapping_deinterleaving(uint16_t *llr, #ifdef NR_PDCCH_DCI_RUN int32_t nr_pdcch_llr(NR_DL_FRAME_PARMS *frame_parms, int32_t **rxdataF_comp, - char *pdcch_llr, uint8_t symbol,uint32_t coreset_nbr_rb) { + int16_t *pdcch_llr, uint8_t symbol,uint32_t coreset_nbr_rb) { int16_t *rxF = (int16_t*) &rxdataF_comp[0][(symbol * coreset_nbr_rb * 12)]; int32_t i; - char *pdcch_llr8; + int16_t *pdcch_llrp; - pdcch_llr8 = &pdcch_llr[2 * symbol * coreset_nbr_rb * 9]; + pdcch_llrp = &pdcch_llr[2 * symbol * coreset_nbr_rb * 9]; - if (!pdcch_llr8) { + if (!pdcch_llrp) { printf("pdcch_qpsk_llr: llr is null, symbol %d\n", symbol); return (-1); } #ifndef NR_PDCCH_DCI_DEBUG - printf("\t\t<-NR_PDCCH_DCI_DEBUG (nr_pdcch_llr)-> llr logs: pdcch qpsk llr for symbol %d (pos %d), llr offset %d\n",symbol,(symbol*frame_parms->N_RB_DL*12),pdcch_llr8-pdcch_llr); + printf("\t\t<-NR_PDCCH_DCI_DEBUG (nr_pdcch_llr)-> llr logs: pdcch qpsk llr for symbol %d (pos %d), llr offset %d\n",symbol,(symbol*frame_parms->N_RB_DL*12),pdcch_llrp-pdcch_llr); #endif //for (i = 0; i < (frame_parms->N_RB_DL * ((symbol == 0) ? 16 : 24)); i++) { for (i = 0; i < (coreset_nbr_rb * ((symbol == 0) ? 18 : 18)); i++) { if (*rxF > 31) - *pdcch_llr8 = 31; + *pdcch_llrp = 31; else if (*rxF < -32) - *pdcch_llr8 = -32; + *pdcch_llrp = -32; else - *pdcch_llr8 = (char) (*rxF); + *pdcch_llrp = (*rxF); #ifndef NR_PDCCH_DCI_DEBUG printf("\t\t<-NR_PDCCH_DCI_DEBUG (nr_pdcch_llr)-> llr logs: rb=%d i=%d *rxF:%d => *pdcch_llr8:%d\n",i/18,i,*rxF,*pdcch_llr8); #endif rxF++; - pdcch_llr8++; + pdcch_llrp++; } return (0); @@ -1034,8 +1037,8 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue, printf("\t<-NR_PDCCH_DCI_DEBUG (nr_rx_pdcch)-> we enter nr_pdcch_demapping_deinterleaving()\n"); #endif - nr_pdcch_demapping_deinterleaving(pdcch_vars[eNB_id]->llr, - (uint16_t*) pdcch_vars[eNB_id]->e_rx, + nr_pdcch_demapping_deinterleaving((uint32_t*) pdcch_vars[eNB_id]->llr, + (uint32_t*) pdcch_vars[eNB_id]->e_rx, frame_parms, coreset_time_dur, coreset_nbr_rb, @@ -1095,7 +1098,7 @@ void pdcch_scrambling(NR_DL_FRAME_PARMS *frame_parms, #ifdef NR_PDCCH_DCI_RUN void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8_t nr_tti_rx, - uint16_t *z, uint32_t length, uint16_t pdcch_DMRS_scrambling_id, int do_common) { + int16_t *z, uint32_t length, uint16_t pdcch_DMRS_scrambling_id, int do_common) { int i; uint8_t reset; @@ -1128,7 +1131,8 @@ void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8 //printf("\t\t<-NR_PDCCH_DCI_DEBUG (nr_pdcch_unscrambling)-> lte_gold[%d]=%x\n",i,s); reset = 0; } - + + /* #ifdef NR_PDCCH_DCI_DEBUG if (i%2 == 0) printf("\t\t<-NR_PDCCH_DCI_DEBUG (nr_pdcch_unscrambling)-> unscrambling %d : scrambled_z=%d, => ", i,*(char*) &z[(int)floor(i/2)]); @@ -1145,7 +1149,15 @@ void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8 if (i%2 == 0) printf("unscrambled_z=%d\n",*(char*) &z[(int)floor(i/2)]); if (i%2 == 1) printf("unscrambled_z=%d\n",*(1 + (char*) &z[(int)floor(i/2)])); #endif - + */ +#ifdef NR_PDCCH_DCI_DEBUG + printf("\t\t<-NR_PDCCH_DCI_DEBUG (nr_pdcch_unscrambling)-> unscrambling %d : scrambled_z=%d, => ", + i,z[i]); +#endif + if (((s >> (i % 32)) & 1) == 1) z[i] = -z[i]; +#ifdef NR_PDCCH_DCI_DEBUG + printf("unscrambled_z=%d\n",z[i]); +#endif } } @@ -1383,7 +1395,7 @@ void nr_dci_decoding_procedure0(int s, pdcch_vars[eNB_id]->num_pdcch_symbols,m,L2,sizeof_bits,CCEind,nCCE,*CCEmap,CCEmap_mask); else LOG_I(PHY,"[DCI search nPdcch %d - ue spec] Attempting candidate %d Aggregation Level %d DCI length %d at CCE %d/%d (CCEmap %x,CCEmap_cand %x) format %d\n", - pdcch_vars[eNB_id]->num_pdcch_symbols,m,L2,sizeof_bits,CCEind,nCCE,*CCEmap,CCEmap_mask,format_c); + pdcch_vars[eNB_id]->num_pdcch_symbols,m,L2,sizeof_bits,CCEind,nCCE,*CCEmap,CCEmap_mask,format_uss); #endif #ifndef NR_PDCCH_DCI_DEBUG printf ("\t\t<-NR_PDCCH_DCI_DEBUG (nr_dci_decoding_procedure0)-> ... we enter function dci_decoding(sizeof_bits=%d L=%d) -----\n",sizeof_bits,L); @@ -1634,9 +1646,10 @@ void nr_dci_decoding_procedure0(int s, } #ifdef DEBUG_DCI_DECODING - LOG_I(PHY,"[DCI search] Found DCI %d rnti %x Aggregation %d length %d format %s in CCE %d (CCEmap %x) candidate %d / %d \n", - *dci_cnt,crc,1<config[CC_idP]; + int mu = 1; + // FDD cfg->subframe_config.duplex_mode.value = 1; cfg->subframe_config.duplex_mode.tl.tag = NFAPI_SUBFRAME_CONFIG_DUPLEX_MODE_TAG; @@ -179,11 +181,11 @@ void config_common(int Mod_idP, cfg->nfapi_config.rf_bands.tl.tag = NFAPI_PHY_RF_BANDS_TAG; cfg->num_tlv++; - cfg->nfapi_config.nrarfcn.value = to_nrarfcn(nr_bandP,dl_CarrierFreqP,dl_BandwidthP); + cfg->nfapi_config.nrarfcn.value = to_nrarfcn(nr_bandP,dl_CarrierFreqP,dl_BandwidthP*180000*(1+mu)); cfg->nfapi_config.nrarfcn.tl.tag = NFAPI_NR_NFAPI_NRARFCN_TAG; cfg->num_tlv++; - cfg->subframe_config.numerology_index_mu.value = 1; + cfg->subframe_config.numerology_index_mu.value = mu; //cfg->subframe_config.tl.tag = //cfg->num_tlv++; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index f1546a907f..1ac386c34e 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -37,7 +37,7 @@ extern RAN_CONTEXT_t RC; * current version has only a DCI for type 1 PDCCH for RA-RNTI*/ void nr_schedule_css_dlsch_phytest(module_id_t module_idP, frame_t frameP, - sub_frame_t subframeP) + sub_frame_t slotP) { uint8_t CC_id; @@ -48,7 +48,7 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP, nfapi_tx_request_pdu_t *TX_req; nfapi_nr_config_request_t *cfg = &nr_mac->config[0]; - uint16_t sfn_sf = frameP << 4 | subframeP; + uint16_t sfn_sf = frameP << 4 | slotP; int dl_carrier_bandwidth = cfg->rf_config.dl_carrier_bandwidth.value; // everything here is hard-coded to 30 kHz @@ -68,10 +68,12 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP, nfapi_nr_dl_config_dci_dl_pdu_rel15_t *pdu_rel15 = &dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel15; nfapi_nr_dl_config_pdcch_parameters_rel15_t *params_rel15 = &dl_config_pdu->dci_dl_pdu.pdcch_params_rel15; + nr_configure_css_dci_initial(params_rel15, scs, scs, nr_FR1, 0, 0, slots_per_frame, dl_carrier_bandwidth); + params_rel15->first_slot = 0; pdu_rel15->frequency_domain_assignment = 5; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index ec2b2b68d8..f7520bd5ae 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -252,6 +252,8 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p pdcch_params->interleaver_size = 2; // set initial banwidth part to full bandwidth pdcch_params->n_RB_BWP = N_RB; + + } void nr_configure_css_dci_from_pdcch_config(nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params,