Merge nr_initialsync
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@@ -47,7 +47,10 @@ extern RAN_CONTEXT_t RC;
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#include "fapi_stub.h"
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//#include "fapi_l1.h"
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#include "UTIL/LOG/log.h"
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#include "openair2/LAYER2/MAC/proto.h"
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#include "openair2/LAYER2/MAC/mac_proto.h"
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#include "PHY/INIT/phy_init.h"
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#include "PHY/LTE_TRANSPORT/transport_proto.h"
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#define NUM_P5_PHY 2
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@@ -37,7 +37,8 @@
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#include "vendor_ext.h"
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#include "nfapi_vnf.h"
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#include "PHY/defs_eNB.h"
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#include "PHY/LTE_TRANSPORT/transport_proto.h"
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#include "common/ran_context.h"
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extern RAN_CONTEXT_t RC;
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@@ -201,8 +202,8 @@ void oai_create_enb(void) {
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eNB->CC_id = bodge_counter;
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eNB->abstraction_flag = 0;
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eNB->single_thread_flag = 0;//single_thread_flag;
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eNB->td = ulsch_decoding_data;//(single_thread_flag==1) ? ulsch_decoding_data_2thread : ulsch_decoding_data;
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eNB->te = dlsch_encoding;//(single_thread_flag==1) ? dlsch_encoding_2threads : dlsch_encoding;
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eNB->td = ulsch_decoding_data_all;//(single_thread_flag==1) ? ulsch_decoding_data_2thread : ulsch_decoding_data;
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eNB->te = dlsch_encoding_all;//(single_thread_flag==1) ? dlsch_encoding_2threads : dlsch_encoding;
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RC.nb_CC[bodge_counter] = 1;
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@@ -75,6 +75,9 @@
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#define NFAPI_VERSION_3_0_11 0x000
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#define NFAPI_VERSION_3_0_12 0x001
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#define NFAPI_HALF_FRAME_INDEX_FIRST_HALF 0
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#define NFAPI_HALF_FRAME_INDEX_SECOND_HALF 1
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// The IANA agreed port definition of the P5 SCTP VNF enpoint
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// http://www.iana.org/assignments/service-names-port-numbers/service-names-port-numbers.xhtml?search=7701
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#define NFAPI_P5_SCTP_PORT 7701
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@@ -671,20 +674,17 @@ typedef struct {
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#define NFAPI_PHICH_CONFIG_PHICH_DURATION_TAG 0x0015
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#define NFAPI_PHICH_CONFIG_PHICH_POWER_OFFSET_TAG 0x0016
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typedef enum {
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NFAPI_HALF_FRAME_INDEX_FIRST_HALF = 0,
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NFAPI_HALF_FRAME_INDEX_SECOND_HALF = 1
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} nfapi_half_frame_index_e;
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typedef struct {
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nfapi_uint16_tlv_t primary_synchronization_signal_epre_eprers;
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nfapi_uint16_tlv_t secondary_synchronization_signal_epre_eprers;
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nfapi_uint16_tlv_t physical_cell_id;
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nfapi_half_frame_index_e half_frame_index;
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nfapi_uint16_tlv_t half_frame_index;
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nfapi_uint16_tlv_t ssb_subcarrier_offset;
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nfapi_uint16_tlv_t ssb_position_in_burst;
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nfapi_uint16_tlv_t ssb_periodicity;
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nfapi_uint16_tlv_t ss_pbch_block_power;
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nfapi_uint16_tlv_t n_ssb_crb;
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} nfapi_sch_config_t;
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#define NFAPI_SCH_CONFIG_PRIMARY_SYNCHRONIZATION_SIGNAL_EPRE_EPRERS_TAG 0x001E
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@@ -695,6 +695,7 @@ typedef struct {
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#define NFAPI_SCH_CONFIG_SSB_POSITION_IN_BURST 0x0023
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#define NFAPI_SCH_CONFIG_SSB_PERIODICITY 0x0024
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#define NFAPI_SCH_CONFIG_SS_PBCH_BLOCK_POWER 0x0025
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#define NFAPI_SCH_CONFIG_N_SSB_CRB 0x0025
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typedef struct {
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nfapi_uint16_tlv_t configuration_index;
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