docs: Standardize documentation headings (remove multiple # H1)
- Remove multiple single top-level (# H1) headings per file - Use (# H2 and ###### H6) sub-headings for consistency - Remove any trailing # in the headings - This ensures proper table of contents rendering in MkDocs. - Also removed RUN_NR_multiple_BWPs.md as it is moved to MAC usage
This commit is contained in:
Robert Schmidt
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Shubhika Garg
Shubhika Garg
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+26
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@@ -19,40 +19,40 @@
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This documentation describes the integration of LDPC coding for lookaside acceleration using O-RAN AAL/DPDK BBDEV in OAI, along with its usage.
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For details on the implementation, please consult the [developer notes](../openair1/PHY/CODING/nrLDPC_coding/nrLDPC_coding_aal/README.md).
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# Requirements
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## Requirements
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In principle, any lookaside LDPC accelerator supporting the O-RAN AAL/DPDK BBDEV should work.
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However, the current implementation has only been validated for the Xilinx T2, Intel ACC100, and Intel ACC200 (VRB1).
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Therefore, your mileage may vary when using other BBDEV devices as there may be some hardware-specific changes required -- contributions are welcome!
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## DPDK Version Requirements
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### DPDK Version Requirements
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The following DPDK versions are supported:
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- For the Xilinx T2 card, DPDK20.11+ is supported.
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- As for the Intel ACC100/ACC200, only DPDK22.11+ is supported.
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## Tested Devices/ DPDK versions
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### Tested Devices/ DPDK versions
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### Xilinx T2
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#### Xilinx T2
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- DPDK20.11.9*.
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- DPDK22.11.7*.
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> Note: FPGA bitstream image and the corresponding patch file (e.g., `ACCL_BBDEV_DPDK20.11.3_ldpc_3.1.918.patch` for DPDK20.11) from Accelercomm required.
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### Intel ACC100
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#### Intel ACC100
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- DPDK22.11.7*.
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- DPDK23.11.3*.
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- DPDK24.11.2.
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> Note: [Patch]((https://github.com/DPDK/dpdk/commit/fdde63a1dfc129d0a510a831aa98253b36a2a1cd)) required for pre-DPDK24.11 versions when using the Intel ACC100.
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### Intel ACC200 (also known as VRB1)
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#### Intel ACC200 (also known as VRB1)
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- DPDK22.11.7.
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- DPDK23.11.3.
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- DPDK24.11.2.
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# System Setup
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## DPDK installation
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## System Setup
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### DPDK installation
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> Important:
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> - If you are using the Xilinx T2 card, you will need to apply the vendor-supplied patches before compiling DPDK.
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@@ -89,9 +89,9 @@ sudo ldconfig
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```
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</details>
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## System configuration
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### System configuration
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### Setting up Hugepages
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#### Setting up Hugepages
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First, we must setup hugepages on the system.
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In our setup, we setup 16 of the 1G hugepages.
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@@ -101,7 +101,7 @@ Apart from 1G, 2MB hugepages works too, but make sure to allocate a sufficient n
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# sudo dpdk-hugepages.py -p 1G --setup 16G
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```
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### Locating the Accelerator
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#### Locating the Accelerator
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Next, we check whether our system can detect our accelerator using `dpdk-devbind.py`.
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You should see Baseband devices detected by DPDK, as follows:
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@@ -117,14 +117,14 @@ Baseband devices using DPDK-compatible driver
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As you can see here, our Intel ACC200 has the address of `0000:f7:00.0`.
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Depending on the accelerator you are using, the address may vary.
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### Loading VFIO-PCI and enabling SR-IOV
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#### Loading VFIO-PCI and enabling SR-IOV
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Following, make sure to load the `vfio-pci` kernel modules and ensure that SR-IOV is enabled.
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```
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# sudo modprobe vfio-pci enable_sriov=1 disable_idle_d3=1
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```
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### Binding the Accelerator with `vfio-pci`
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#### Binding the Accelerator with `vfio-pci`
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Lastly, we bind our accelerator with the `vfio-pci` driver.
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```
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@@ -134,7 +134,7 @@ Lastly, we bind our accelerator with the `vfio-pci` driver.
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> Note: For the Xilinx T2, we can use this device directly.
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If you use an Intel vRAN accelerator, read on.
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### Additional Steps for Intel vRAN Accelerators
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#### Additional Steps for Intel vRAN Accelerators
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> IMPORTANT NOTE:
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> - Currently, we only support using the Virtual Functions (VFs) of the Intel vRAN accelerators, but not the Physical Function (PF).
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@@ -142,7 +142,7 @@ If you use an Intel vRAN accelerator, read on.
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If you are using an Intel vRAN accelerator, you will need to use the [pf_bb_config](https://github.com/intel/pf-bb-config) tool to configure the accelerator beforehand.
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#### pf_bb_config
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##### pf_bb_config
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For more details, please consult the `pf_bb_config` README.
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```
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@@ -164,7 +164,7 @@ VRB1 PF [0000:f7:00.0] configuration complete!
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Log file = /var/log/pf_bb_cfg_0000:f7:00.0.log
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```
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#### Creating VFs
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##### Creating VFs
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Finally, we create the VF(s) for our accelerator.
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In this example, we only create one SR-IOV VF.
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@@ -190,7 +190,7 @@ Baseband devices using DPDK-compatible driver
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...
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```
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# Building OAI with ORAN-AAL
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## Building OAI with ORAN-AAL
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OTA deployment is precisely described in the following tutorial:
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- [NR_SA_Tutorial_COTS_UE](https://gitlab.eurecom.fr/oai/openairinterface5g/-/blob/develop/doc/NR_SA_Tutorial_COTS_UE.md)
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Instead of section *3.2 Build OAI gNB* from the tutorial, run the following commands:
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@@ -218,7 +218,7 @@ The selection of the library to compile is done using `--build-lib ldpc_aal`.
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> Note: The required DPDK poll mode driver has to be present on the host machine and required DPDK version has to be installed on the host, prior to building OAI.
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# O-RAN AAL DPDK EAL parameters
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## O-RAN AAL DPDK EAL parameters
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To configure O-RAN AAL/DPDK BBDEV, you can set the following parameters via the command line of PHY simulators or nr-softmodem:
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> Note: the group parameter name has been renamed from `nrLDPC_coding_t2` to
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@@ -254,14 +254,14 @@ loader : {
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};
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```
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# Running OAI with O-RAN AAL
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## Running OAI with O-RAN AAL
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In general, to offload of the channel coding to the LDPC accelerator, we use use the `--loader.ldpc.shlibversion _aal` option.
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Reminder, if you are using the Xilinx T2 card, make sure to set `--nrLDPC_coding_aal.is_t2 1`.
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## 5G PHY simulators
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### 5G PHY simulators
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### nr_ulsim
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#### nr_ulsim
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Example command:
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```bash
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@@ -270,7 +270,7 @@ source oaienv
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cd cmake_targets/ran_build/build
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sudo ./nr_ulsim -n100 -s20 -m20 -r273 -R273 --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev 0000:f7:00.1 --nrLDPC_coding_aal.dpdk_core_list 0-1 --nrLDPC_coding_aal.vfio_vf_token 00112233-4455-6677-8899-aabbccddeeff
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```
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### nr_dlsim
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#### nr_dlsim
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Example command:
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```bash
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@@ -280,9 +280,9 @@ cd cmake_targets/ran_build/build
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sudo ./nr_dlsim -n300 -s30 -R 106 -e 27 --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev 0000:f7:00.1 --nrLDPC_coding_aal.dpdk_core_list 0-1 --nrLDPC_coding_aal.vfio_vf_token 00112233-4455-6677-8899-aabbccddeeff
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```
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## OTA test
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### OTA test
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### Running OAI gNB with USRP B210/FHI72
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#### Running OAI gNB with USRP B210/FHI72
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When running the gNB **with FHI 7.2**, it is not necessary to provide the `--nrLDPC_coding_aal.dpdk_core_list` argument
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since the core list specified for FHI 7.2 will be used for DPDK.
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@@ -296,9 +296,9 @@ cd cmake_targets/ran_build/build
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sudo ./nr-softmodem -O ~/gnb.conf --loader.ldpc.shlibversion _aal --nrLDPC_coding_aal.dpdk_dev 0000:f7:00.1 --nrLDPC_coding_aal.dpdk_core_list 14-15 --nrLDPC_coding_aal.vfio_vf_token 00112233-4455-6677-8899-aabbccddeeff
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```
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# Known Issue(s)
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## Known Issue(s)
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## Potential Low Throughput
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### Potential Low Throughput
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The current implementation has been tested to work in an end-to-end setup and is functional.
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However, depending on the accelerator in use,
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