From 5e9af20419f10815d46c8165a3e76a615f9c634b Mon Sep 17 00:00:00 2001 From: Guy De Souza Date: Mon, 3 Dec 2018 18:40:57 +0100 Subject: [PATCH] more DCI changes --- openair1/PHY/NR_TRANSPORT/nr_dci.c | 5 +- openair1/PHY/NR_TRANSPORT/nr_dci.h | 2 +- openair1/PHY/NR_TRANSPORT/nr_dci_tools.c | 210 +++++++++++------------ openair1/PHY/NR_TRANSPORT/nr_pbch.c | 2 +- 4 files changed, 104 insertions(+), 115 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.c b/openair1/PHY/NR_TRANSPORT/nr_dci.c index ef8dbc8a47..93b2d5692e 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.c @@ -41,11 +41,10 @@ extern short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT]; uint16_t nr_get_dci_size(nfapi_nr_dci_format_e format, nfapi_nr_rnti_type_e rnti_type, - NR_BWP_PARMS* bwp, + uint16_t N_RB, nfapi_nr_config_request_t* config) { uint16_t size = 0; - uint16_t N_RB = bwp->N_RB; switch(format) { /*Only sizes for 0_0 and 1_0 are correct at the moment*/ @@ -53,7 +52,7 @@ uint16_t nr_get_dci_size(nfapi_nr_dci_format_e format, /// fixed: Format identifier 1, Hop flag 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2 Time Domain assgnmt 4 --20 size += 20; size += (uint8_t)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); // Freq domain assignment -- hopping scenario to be updated - size += nr_get_dci_size(NFAPI_NR_DL_DCI_FORMAT_1_0, rnti_type, bwp, config) - size; // Padding to match 1_0 size + size += nr_get_dci_size(NFAPI_NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB, config) - size; // Padding to match 1_0 size // UL/SUL indicator assumed to be 0 break; diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.h b/openair1/PHY/NR_TRANSPORT/nr_dci.h index 8d79311f35..90287dedf7 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.h +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.h @@ -29,7 +29,7 @@ typedef unsigned __int128 uint128_t; uint16_t nr_get_dci_size(nfapi_nr_dci_format_e format, nfapi_nr_rnti_type_e rnti_type, - NR_BWP_PARMS* bwp, + uint16_t N_RB, nfapi_nr_config_request_t* config); uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars, diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c index 43456058c3..822927a342 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c @@ -120,14 +120,14 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB, nfapi_nr_dl_config_pdcch_parameters_rel15_t *params_rel15 = &pdu->dci_dl_pdu.pdcch_params_rel15; nfapi_nr_config_request_t *cfg = &gNB->gNB_config; - uint16_t N_RB = fp->initial_bwp_dl.N_RB; + uint16_t N_RB = params_rel15->n_RB_BWP; uint8_t fsize=0, pos=0, cand_idx=0; dci_alloc->L = 8; memcpy((void*)&dci_alloc->pdcch_params, (void*)params_rel15, sizeof(nfapi_nr_dl_config_pdcch_parameters_rel15_t)); dci_alloc->size = nr_get_dci_size(dci_alloc->pdcch_params.dci_format, dci_alloc->pdcch_params.rnti_type, - &fp->initial_bwp_dl, + N_RB, cfg); Assert_Fatal(dci_alloc->size<=64, "DCI sizes above 64 bits not yet supported"); n_shift = (dci_alloc->pdcch_params.config_type == NFAPI_NR_CSET_CONFIG_MIB_SIB1)? @@ -156,126 +156,120 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB, for (int i=0; i<2; i++) *dci_pdu |= ((pdu_rel15->tb_scaling>>(1-i))&1)<<(63-pos++); break; - } - break; -case NFAPI_NR_RNTI_C: - // indicating a DL DCI format 1bit - *dci_pdu |= (pdu_rel15->format_indicator&1)<<(63-pos++); - // Freq domain assignment (275rb >> fsize = 16) - fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); - for (int i=0; iformat_indicator&1)<<(63-pos++); + // Freq domain assignment (275rb >> fsize = 16) + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(63-pos++); - if ((pdu_rel15->frequency_domain_assignment+1)&1 ==0) //fsize are all 1 38.212 p86 - { - printf("***************************\n"); - - // ra_preamble_index 6 bits - for (int i=0; i<6; i++) - *dci_pdu |= ((pdu_rel15->ra_preamble_index>>(5-i))&1)<<(63-pos++); + if ((pdu_rel15->frequency_domain_assignment+1)&1 ==0) //fsize are all 1 38.212 p86 + { + // ra_preamble_index 6 bits + for (int i=0; i<6; i++) + *dci_pdu |= ((pdu_rel15->ra_preamble_index>>(5-i))&1)<<(63-pos++); - // UL/SUL indicator 1 bit - *dci_pdu |= (pdu_rel15->ul_sul_indicator&1)<<(63-pos++); + // UL/SUL indicator 1 bit + *dci_pdu |= (pdu_rel15->ul_sul_indicator&1)<<(63-pos++); + + // SS/PBCH index 6 bits + for (int i=0; i<6; i++) + *dci_pdu |= ((pdu_rel15->ss_pbch_index>>(5-i))&1)<<(63-pos++); - // SS/PBCH index 6 bits - for (int i=0; i<6; i++) - *dci_pdu |= ((pdu_rel15->ss_pbch_index>>(5-i))&1)<<(63-pos++); - - // prach_mask_index 4 bits - for (int i=0; i<4; i++) - *dci_pdu |= ((pdu_rel15->prach_mask_index>>(3-i))&1)<<(63-pos++); - - } //end if - else - - { - // Time domain assignment 4bit + // prach_mask_index 4 bits + for (int i=0; i<4; i++) + *dci_pdu |= ((pdu_rel15->prach_mask_index>>(3-i))&1)<<(63-pos++); + + } //end if + + else { + + // Time domain assignment 4bit for (int i=0; i<4; i++) *dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<(63-pos++); - // VRB to PRB mapping 1bit - *dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&1)<<(63-pos++); + // VRB to PRB mapping 1bit + *dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&1)<<(63-pos++); - // MCS 5bit //bit over 32, so dci_pdu ++ + // MCS 5bit //bit over 32, so dci_pdu ++ for (int i=0; i<5; i++) *dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<(63-pos++); - // New data indicator 1bit - *dci_pdu |= (pdu_rel15->ndi&1)<<(63-pos++); + // New data indicator 1bit + *dci_pdu |= (pdu_rel15->ndi&1)<<(63-pos++); - // Redundancy version 2bit + // Redundancy version 2bit for (int i=0; i<2; i++) *dci_pdu |= ((pdu_rel15->rv>>(1-i))&1)<<(63-pos++); - // HARQ process number 4bit + // HARQ process number 4bit for (int i=0; i<4; i++) - *dci_pdu |= ((pdu_rel15->harq_pid>>(3-i))&1)<<(63-pos++); - + *dci_pdu |= ((pdu_rel15->harq_pid>>(3-i))&1)<<(63-pos++); - // Downlink assignment index 2bit - for (int i=0; i<2; i++) - *dci_pdu |= ((pdu_rel15->dai>>(1-i))&1)<<(63-pos++); + // Downlink assignment index 2bit + for (int i=0; i<2; i++) + *dci_pdu |= ((pdu_rel15->dai>>(1-i))&1)<<(63-pos++); - // TPC command for scheduled PUCCH 2bit - for (int i=0; i<2; i++) - *dci_pdu |= ((pdu_rel15->tpc>>(1-i))&1)<<(63-pos++); + // TPC command for scheduled PUCCH 2bit + for (int i=0; i<2; i++) + *dci_pdu |= ((pdu_rel15->tpc>>(1-i))&1)<<(63-pos++); - // PUCCH resource indicator 3bit - for (int i=0; i<3; i++) - *dci_pdu |= ((pdu_rel15->pucch_resource_indicator>>(2-i))&1)<<(63-pos++); + // PUCCH resource indicator 3bit + for (int i=0; i<3; i++) + *dci_pdu |= ((pdu_rel15->pucch_resource_indicator>>(2-i))&1)<<(63-pos++); - // PDSCH-to-HARQ_feedback timing indicator 3bit - for (int i=0; i<3; i++) - *dci_pdu |= ((pdu_rel15->pdsch_to_harq_feedback_timing_indicator>>(2-i))&1)<<(63-pos++); + // PDSCH-to-HARQ_feedback timing indicator 3bit + for (int i=0; i<3; i++) + *dci_pdu |= ((pdu_rel15->pdsch_to_harq_feedback_timing_indicator>>(2-i))&1)<<(63-pos++); - } //end else - - break; + } //end else + break; case NFAPI_NR_RNTI_P: - // Short Messages Indicator – 2 bits - for (int i=0; i<2; i++) - *dci_pdu |= ((pdu_rel15->short_messages_indicator>>(1-i))&1)<<(63-pos++); - // Short Messages – 8 bits - for (int i=0; i<8; i++) - *dci_pdu |= ((pdu_rel15->short_messages>>(7-i))&1)<<(63-pos++); - // Freq domain assignment 0-16 bit + // Short Messages Indicator – 2 bits + for (int i=0; i<2; i++) + *dci_pdu |= ((pdu_rel15->short_messages_indicator>>(1-i))&1)<<(63-pos++); + // Short Messages – 8 bits + for (int i=0; i<8; i++) + *dci_pdu |= ((pdu_rel15->short_messages>>(7-i))&1)<<(63-pos++); + // Freq domain assignment 0-16 bit fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(63-pos++); - // Time domain assignment 4 bit - for (int i=0; i<4; i++) - *dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<(63-pos++); - // VRB to PRB mapping 1 bit + // Time domain assignment 4 bit + for (int i=0; i<4; i++) + *dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<(63-pos++); + // VRB to PRB mapping 1 bit *dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&1)<<(63-pos++); - // MCS 5 bit - for (int i=0; i<5; i++) - *dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<(63-pos++); + // MCS 5 bit + for (int i=0; i<5; i++) + *dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<(63-pos++); - // TB scaling 2 bit + // TB scaling 2 bit for (int i=0; i<2; i++) *dci_pdu |= ((pdu_rel15->tb_scaling>>(1-i))&1)<<(63-pos++); break; case NFAPI_NR_RNTI_SI: - // Freq domain assignment 0-16 bit + // Freq domain assignment 0-16 bit fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); - for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(63-pos++); - // Time domain assignment 4 bit - for (int i=0; i<4; i++) - *dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<(63-pos++); + for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(63-pos++); + // Time domain assignment 4 bit + for (int i=0; i<4; i++) + *dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<(63-pos++); // VRB to PRB mapping 1 bit *dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&1)<<(63-pos++); - // MCS 5bit //bit over 32, so dci_pdu ++ - for (int i=0; i<5; i++) - *dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<(63-pos++); - // Redundancy version 2bit - for (int i=0; i<2; i++) - *dci_pdu |= ((pdu_rel15->rv>>(1-i))&1)<<(63-pos++); + // MCS 5bit //bit over 32, so dci_pdu ++ + for (int i=0; i<5; i++) + *dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<(63-pos++); + // Redundancy version 2bit + for (int i=0; i<2; i++) + *dci_pdu |= ((pdu_rel15->rv>>(1-i))&1)<<(63-pos++); break; @@ -283,55 +277,53 @@ case NFAPI_NR_RNTI_C: // indicating a DL DCI format 1bit *dci_pdu |= (pdu_rel15->format_indicator&1)<<(63-pos++); // Freq domain assignment 0-16 bit - fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); - for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(63-pos++); + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(63-pos++); // Time domain assignment 4 bit - for (int i=0; i<4; i++) - *dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<(63-pos++); + for (int i=0; i<4; i++) + *dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<(63-pos++); // VRB to PRB mapping 1 bit *dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&1)<<(63-pos++); // MCS 5bit //bit over 32, so dci_pdu ++ - for (int i=0; i<5; i++) - *dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<(63-pos++); + for (int i=0; i<5; i++) + *dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<(63-pos++); // New data indicator 1bit *dci_pdu |= (pdu_rel15->ndi&1)<<(63-pos++); // Redundancy version 2bit - for (int i=0; i<2; i++) - *dci_pdu |= ((pdu_rel15->rv>>(1-i))&1)<<(63-pos++); + for (int i=0; i<2; i++) + *dci_pdu |= ((pdu_rel15->rv>>(1-i))&1)<<(63-pos++); // HARQ process number 4bit - for (int i=0; i<4; i++) - *dci_pdu |= ((pdu_rel15->harq_pid>>(3-i))&1)<<(63-pos++); + for (int i=0; i<4; i++) + *dci_pdu |= ((pdu_rel15->harq_pid>>(3-i))&1)<<(63-pos++); // Downlink assignment index – 2 bits - for (int i=0; i<2; i++) - *dci_pdu |= ((pdu_rel15->dai>>(1-i))&1)<<(63-pos++); + for (int i=0; i<2; i++) + *dci_pdu |= ((pdu_rel15->dai>>(1-i))&1)<<(63-pos++); // TPC command for scheduled PUCCH – 2 bits - for (int i=0; i<2; i++) - *dci_pdu |= ((pdu_rel15->tpc>>(1-i))&1)<<(63-pos++); + for (int i=0; i<2; i++) + *dci_pdu |= ((pdu_rel15->tpc>>(1-i))&1)<<(63-pos++); // PUCCH resource indicator – 3 bits - for (int i=0; i<3; i++) - *dci_pdu |= ((pdu_rel15->pucch_resource_indicator>>(2-i))&1)<<(63-pos++); + for (int i=0; i<3; i++) + *dci_pdu |= ((pdu_rel15->pucch_resource_indicator>>(2-i))&1)<<(63-pos++); // PDSCH-to-HARQ_feedback timing indicator – 3 bits - for (int i=0; i<3; i++) - *dci_pdu |= ((pdu_rel15->pdsch_to_harq_feedback_timing_indicator>>(2-i))&1)<<(63-pos++); + for (int i=0; i<3; i++) + *dci_pdu |= ((pdu_rel15->pdsch_to_harq_feedback_timing_indicator>>(2-i))&1)<<(63-pos++); - ///-----------------------------------?????????????????????------------------------ break; } - break; case NFAPI_NR_UL_DCI_FORMAT_0_0: - switch(params_rel15->rnti_type) + switch(params_rel15->rnti_type) { case NFAPI_NR_RNTI_C: // indicating a DL DCI format 1bit *dci_pdu |= (pdu_rel15->format_indicator&1)<<(63-pos++); // Freq domain assignment max 16 bit - fsize = (int)ceil( log2( (N_RB_UL*(N_RB_UL+1))>>1 ) ); + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(63-pos++); // Time domain assignment 4bit @@ -370,7 +362,7 @@ case NFAPI_NR_RNTI_C: // indicating a DL DCI format 1bit *dci_pdu |= (pdu_rel15->format_indicator&1)<<(63-pos++); // Freq domain assignment max 16 bit - fsize = (int)ceil( log2( (N_RB_UL*(N_RB_UL+1))>>1 ) ); + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(63-pos++); // Time domain assignment 4bit @@ -406,10 +398,8 @@ case NFAPI_NR_RNTI_C: } break; } - } - LOG_I(PHY, "DCI PDU: [0]->0x%08x \t [1]->0x%08x \t [2]->0x%08x \t [3]->0x%08x\n", - dci_pdu[0], dci_pdu[1], dci_pdu[2], dci_pdu[3]); + LOG_I(PHY, "DCI PDU: [0]->0x%16x \t [1]->0x%16x \n",dci_pdu[0], dci_pdu[1]); LOG_I(PHY, "DCI type %d payload (size %d) generated on candidate %d\n", dci_alloc->pdcch_params.dci_format, dci_alloc->size, cand_idx); } diff --git a/openair1/PHY/NR_TRANSPORT/nr_pbch.c b/openair1/PHY/NR_TRANSPORT/nr_pbch.c index 93288af29b..213e23cc45 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_pbch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_pbch.c @@ -305,7 +305,7 @@ int nr_generate_pbch(NR_gNB_PBCH *pbch, #endif /// CRC, coding and rate matching - polar_encoder_fast ((int64_t*)&pbch->pbch_a_prime, (uint32_t*)pbch->pbch_e, 0, polar_params); + polar_encoder_fast ((uint64_t*)&pbch->pbch_a_prime, (uint32_t*)pbch->pbch_e, 0, polar_params); #ifdef DEBUG_PBCH_ENCODING printf("Channel coding:\n"); for (int i=0; i