From f22769a80f6fd6c71523c85bc3d4d5ea6773a5af Mon Sep 17 00:00:00 2001 From: Reem Bahsoun Date: Thu, 15 Jan 2026 11:42:19 +0100 Subject: [PATCH 1/7] Update the entrypoint script: - Remove unused line - Change L1 config file - Update directories --- .../yaml_files/sa_gnb_aerial/aerial_l1_entrypoint.sh | 10 ++++------ .../sa_gnb_aerial_ul/aerial_l1_entrypoint.sh | 10 ++++------ 2 files changed, 8 insertions(+), 12 deletions(-) diff --git a/ci-scripts/yaml_files/sa_gnb_aerial/aerial_l1_entrypoint.sh b/ci-scripts/yaml_files/sa_gnb_aerial/aerial_l1_entrypoint.sh index e0fea22190..c8bac9eb3e 100755 --- a/ci-scripts/yaml_files/sa_gnb_aerial/aerial_l1_entrypoint.sh +++ b/ci-scripts/yaml_files/sa_gnb_aerial/aerial_l1_entrypoint.sh @@ -4,8 +4,6 @@ cuBB_Path="${cuBB_SDK:-/opt/nvidia/cuBB}" cd "$cuBB_Path" || exit 1 -# Add gdrcopy to LD_LIBRARY_PATH -export LD_LIBRARY_PATH=/usr/local/nvidia/lib:/usr/local/nvidia/lib64:/opt/mellanox/dpdk/lib/x86_64-linux-gnu:/opt/mellanox/doca/lib/x86_64-linux-gnu:/opt/nvidia/cuBB/cuPHY-CP/external/gdrcopy/build/x86_64/ # Restart MPS # Export variables @@ -14,7 +12,7 @@ export CUDA_MPS_PIPE_DIRECTORY=/var export CUDA_MPS_LOG_DIRECTORY=/var # Stop existing MPS -sudo -E echo quit | sudo -E nvidia-cuda-mps-control +echo quit | sudo -E nvidia-cuda-mps-control # Start MPS sudo -E nvidia-cuda-mps-control -d @@ -24,11 +22,11 @@ sudo -E echo start_server -uid 0 | sudo -E nvidia-cuda-mps-control # Check if an argument is provided if [ $# -eq 0 ]; then # No argument provided, use default value - argument="P5G_FXN_GH" + argument="P5G_WNC_GH" else # Argument provided, use it argument="$1" fi -sudo -E "$cuBB_Path"/build/cuPHY-CP/cuphycontroller/examples/cuphycontroller_scf "$argument" -sudo -E ./build/cuPHY-CP/gt_common_libs/nvIPC/tests/pcap/pcap_collect +sudo -E "$cuBB_Path"/build.$(uname -m)/cuPHY-CP/cuphycontroller/examples/cuphycontroller_scf "$argument" +sudo -E ./build.$(uname -m)/cuPHY-CP/gt_common_libs/nvIPC/tests/pcap/pcap_collect diff --git a/ci-scripts/yaml_files/sa_gnb_aerial_ul/aerial_l1_entrypoint.sh b/ci-scripts/yaml_files/sa_gnb_aerial_ul/aerial_l1_entrypoint.sh index e0fea22190..c8bac9eb3e 100755 --- a/ci-scripts/yaml_files/sa_gnb_aerial_ul/aerial_l1_entrypoint.sh +++ b/ci-scripts/yaml_files/sa_gnb_aerial_ul/aerial_l1_entrypoint.sh @@ -4,8 +4,6 @@ cuBB_Path="${cuBB_SDK:-/opt/nvidia/cuBB}" cd "$cuBB_Path" || exit 1 -# Add gdrcopy to LD_LIBRARY_PATH -export LD_LIBRARY_PATH=/usr/local/nvidia/lib:/usr/local/nvidia/lib64:/opt/mellanox/dpdk/lib/x86_64-linux-gnu:/opt/mellanox/doca/lib/x86_64-linux-gnu:/opt/nvidia/cuBB/cuPHY-CP/external/gdrcopy/build/x86_64/ # Restart MPS # Export variables @@ -14,7 +12,7 @@ export CUDA_MPS_PIPE_DIRECTORY=/var export CUDA_MPS_LOG_DIRECTORY=/var # Stop existing MPS -sudo -E echo quit | sudo -E nvidia-cuda-mps-control +echo quit | sudo -E nvidia-cuda-mps-control # Start MPS sudo -E nvidia-cuda-mps-control -d @@ -24,11 +22,11 @@ sudo -E echo start_server -uid 0 | sudo -E nvidia-cuda-mps-control # Check if an argument is provided if [ $# -eq 0 ]; then # No argument provided, use default value - argument="P5G_FXN_GH" + argument="P5G_WNC_GH" else # Argument provided, use it argument="$1" fi -sudo -E "$cuBB_Path"/build/cuPHY-CP/cuphycontroller/examples/cuphycontroller_scf "$argument" -sudo -E ./build/cuPHY-CP/gt_common_libs/nvIPC/tests/pcap/pcap_collect +sudo -E "$cuBB_Path"/build.$(uname -m)/cuPHY-CP/cuphycontroller/examples/cuphycontroller_scf "$argument" +sudo -E ./build.$(uname -m)/cuPHY-CP/gt_common_libs/nvIPC/tests/pcap/pcap_collect From a5e8e10acfcca09f3949b01b036adcde91691812 Mon Sep 17 00:00:00 2001 From: Reem Bahsoun Date: Thu, 15 Jan 2026 11:45:08 +0100 Subject: [PATCH 2/7] Mount the L1 config file in the volumes of the cuBB container, update cuBB image name and change L2 log to UTC time --- ci-scripts/yaml_files/sa_gnb_aerial/docker-compose.yaml | 5 +++-- ci-scripts/yaml_files/sa_gnb_aerial_ul/docker-compose.yaml | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/ci-scripts/yaml_files/sa_gnb_aerial/docker-compose.yaml b/ci-scripts/yaml_files/sa_gnb_aerial/docker-compose.yaml index 4050fa5310..985fe9a6a3 100644 --- a/ci-scripts/yaml_files/sa_gnb_aerial/docker-compose.yaml +++ b/ci-scripts/yaml_files/sa_gnb_aerial/docker-compose.yaml @@ -18,12 +18,13 @@ services: - /lib/modules:/lib/modules - /dev/hugepages:/dev/hugepages - /usr/src:/usr/src + - ./cuphycontroller_P5G_WNC_GH.yaml:/opt/nvidia/cuBB/cuPHY-CP/cuphycontroller/config/cuphycontroller_P5G_WNC_GH.yaml - ./aerial_l1_entrypoint.sh:/opt/nvidia/cuBB/aerial_l1_entrypoint.sh - /var/log/aerial:/var/log/aerial - ../../../cmake_targets/share:/opt/cuBB/share userns_mode: host ipc: "shareable" - image: cubb-build:25-2.1 + image: cubb-build:25-3 environment: - cuBB_SDK=/opt/nvidia/cuBB command: bash -c "sudo rm -rf /tmp/phy.log && sudo chmod +x /opt/nvidia/cuBB/aerial_l1_entrypoint.sh && /opt/nvidia/cuBB/aerial_l1_entrypoint.sh" @@ -45,7 +46,7 @@ services: - IPC_LOCK ipc: "container:nv-cubb" environment: - USE_ADDITIONAL_OPTIONS: --log_config.global_log_options level,nocolor,time + USE_ADDITIONAL_OPTIONS: --log_config.global_log_options level,nocolor,utc_time deploy: resources: reservations: diff --git a/ci-scripts/yaml_files/sa_gnb_aerial_ul/docker-compose.yaml b/ci-scripts/yaml_files/sa_gnb_aerial_ul/docker-compose.yaml index c0b3e6f81d..7276cfdebd 100644 --- a/ci-scripts/yaml_files/sa_gnb_aerial_ul/docker-compose.yaml +++ b/ci-scripts/yaml_files/sa_gnb_aerial_ul/docker-compose.yaml @@ -18,12 +18,13 @@ services: - /lib/modules:/lib/modules - /dev/hugepages:/dev/hugepages - /usr/src:/usr/src + - ./cuphycontroller_P5G_WNC_GH_ul.yaml:/opt/nvidia/cuBB/cuPHY-CP/cuphycontroller/config/cuphycontroller_P5G_WNC_GH.yaml - ./aerial_l1_entrypoint.sh:/opt/nvidia/cuBB/aerial_l1_entrypoint.sh - /var/log/aerial:/var/log/aerial - ../../../cmake_targets/share:/opt/cuBB/share userns_mode: host ipc: "shareable" - image: cubb-build:25-2.1_srs-ul-heavy + image: cubb-build:25-3 environment: - cuBB_SDK=/opt/nvidia/cuBB command: bash -c "sudo rm -rf /tmp/phy.log && sudo chmod +x /opt/nvidia/cuBB/aerial_l1_entrypoint.sh && /opt/nvidia/cuBB/aerial_l1_entrypoint.sh" @@ -45,7 +46,7 @@ services: - IPC_LOCK ipc: "container:nv-cubb" environment: - USE_ADDITIONAL_OPTIONS: --log_config.global_log_options level,nocolor,time + USE_ADDITIONAL_OPTIONS: --log_config.global_log_options level,nocolor,utc_time deploy: resources: reservations: From bf78ef08e13b84e1b4289b9bff0f0267758d5829 Mon Sep 17 00:00:00 2001 From: Reem Bahsoun Date: Thu, 15 Jan 2026 12:01:05 +0100 Subject: [PATCH 3/7] Add Nvidia L1 configuration file in sa_gnb_aerial and sa_gnb_aerial_ul --- .../cuphycontroller_P5G_WNC_GH.yaml | 243 ++++++++++++++++++ .../cuphycontroller_P5G_WNC_GH_ul.yaml | 243 ++++++++++++++++++ 2 files changed, 486 insertions(+) create mode 100644 ci-scripts/yaml_files/sa_gnb_aerial/cuphycontroller_P5G_WNC_GH.yaml create mode 100644 ci-scripts/yaml_files/sa_gnb_aerial_ul/cuphycontroller_P5G_WNC_GH_ul.yaml diff --git a/ci-scripts/yaml_files/sa_gnb_aerial/cuphycontroller_P5G_WNC_GH.yaml b/ci-scripts/yaml_files/sa_gnb_aerial/cuphycontroller_P5G_WNC_GH.yaml new file mode 100644 index 0000000000..9fe8cc3d6c --- /dev/null +++ b/ci-scripts/yaml_files/sa_gnb_aerial/cuphycontroller_P5G_WNC_GH.yaml @@ -0,0 +1,243 @@ +# SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +aerial_sdk_version: 25-3-cubb +l2adapter_filename: l2_adapter_config_P5G_GH.yaml +aerial_metrics_backend_address: 127.0.0.1:8081 + +# CPU core shared by all low-priority threads +low_priority_core: 10 +enable_ptp_svc_monitoring: 0 +ptp_rms_threshold: 20 #ns +nic_tput_alert_threshold_mbps: 85000 + +cuphydriver_config: + standalone: 0 + validation: 0 + num_slots: 8 + log_level: DBG + profiler_sec: 0 + dpdk_thread: 10 + dpdk_verbose_logs: 0 + accu_tx_sched_res_ns: 500 + accu_tx_sched_disable: 0 #Flag applicable only for CX6-DX : BF3/CX7 HW and beyond support accurate send scheduling directly on timestamp, for CX6-DX this is implemented via software emulation + fh_stats_dump_cpu_core: -1 + pdump_client_thread: -1 + use_green_contexts: 0 + use_batched_memcpy: 0 # Experimental feature; requires >= CUDA 12.8 + mps_sm_pusch: 100 + mps_sm_pucch: 2 + mps_sm_prach: 2 + mps_sm_ul_order: 20 + mps_sm_pdsch: 102 + mps_sm_pdcch: 10 + mps_sm_pbch: 2 + mps_sm_gpu_comms: 16 + mps_sm_srs: 16 + pdsch_fallback: 0 + dpdk_file_prefix: cuphycontroller + nics: + - nic: '0000:01:00.0' + mtu: 9216 + cpu_mbufs: 196608 + uplane_tx_handles: 64 + txq_size: 8192 + rxq_size: 16384 + gpu: 0 + cus_port_failover: 0 + gpus: + - 0 + # Set GPUID to the GPU sharing the PCIe switch as NIC + # run nvidia-smi topo -m to find out which GPU + workers_ul: [4,5] + workers_dl: [6,7,8] + debug_worker: -1 + workers_sched_priority: 95 + prometheus_thread: -1 + start_section_id_srs: 3072 + start_section_id_prach: 2048 + enable_ul_cuphy_graphs: 1 + enable_dl_cuphy_graphs: 1 + ul_order_kernel_mode: 0 # 0: Ping-Pong, 1: dual CTA + ul_order_timeout_cpu_ns: 8000000 + ul_order_timeout_log_interval_ns: 1000000000 + ul_order_timeout_gpu_ns: 3000000 + ul_order_timeout_gpu_srs_ns: 5200000 + ul_srs_aggr3_task_launch_offset_ns: 500000 + ul_order_timeout_gpu_log_enable: 0 + ul_order_max_rx_pkts: 512 + ul_order_rx_pkts_timeout_ns: 100000 + cplane_disable: 0 + gpu_init_comms_dl: 1 + cell_group: 1 + cell_group_num: 1 + fix_beta_dl: 0 + bfw_beta_prescaler: 16384 + pusch_workCancelMode: 2 # set cuphyPuschStatPrms_t workCancelMode field to PUSCH_DEVICE_GRAPHS; this only sets the mode and does not cancel work; + # work cancellation (i.e., not launching some of the device graphs) can only occur after an explicit internal + # memory write is timely observed by a PUSCH graph. + pusch_sinr: 2 + pusch_rssi: 1 + pusch_tdi: 1 + pusch_cfo: 1 + pusch_dftsofdm: 0 + pusch_to: 1 + pusch_select_eqcoeffalgo: 3 + pusch_select_chestalgo: 1 + pusch_enable_perprgchest: 0 + pusch_tbsizecheck: 1 + pusch_deviceGraphLaunchEn: 1 + pusch_waitTimeOutPreEarlyHarqUs: 3000 + pusch_waitTimeOutPostEarlyHarqUs: 3000 + puxch_polarDcdrListSz: 8 + enable_cpu_task_tracing: 0 + enable_prepare_tracing: 0 + disable_empw: 0 #1=>Disables Multi packet WQE feature + cqe_tracer_config: + enable_dl_cqe_tracing: 0 + cqe_trace_cell_mask: 1 #[64 bit mask: Bit0->Cell0, Bit1->Cell1...] + cqe_trace_slot_mask: 196800 #[20 bit mask: Bit0->Slot0, Bit1->Slot1...] 196800=>All *6,*7 DL Slots + ul_rx_pkt_tracing_level: 0 + ul_rx_pkt_tracing_level_srs: 0 + pmu_metrics: 0 #Enable and select PMU metrics, 0=disabled, 1=General Counters (platform agnostic), 2=Topdown Metrics (Grace only), 3=Cache Metrics (Grace only) + enable_h2d_copy_thread: 1 + h2d_copy_thread_cpu_affinity : 11 + h2d_copy_thread_sched_priority : 95 #0->SCHED_OTHER, >0->Actual + split_ul_cuda_streams: 0 # 1=Put UL slot 4 and slot 5 on different streams for DDDSUUDDDD pattern + serialize_pucch_pusch: 0 # 1=Force serialization of PUSCH/PUCCH + # Note: for Early Harq (EH) order is PUSCH EH -> PUCCH -> PUSCH non EH + # for non-Early Harq order is PUCCH -> all PUSCH processing + aggr_obj_non_avail_th: 5 # Threshold for consecutive non-availability of Aggregated objects(UL/DL) or DL/UL buffers + dl_wait_th_ns: + - 500000 #H2D copy wait threshold + - 4000000 #cuPHY DL channel wait threshold + sendCPlane_timing_error_th_ns : 0 + sendCPlane_ulbfw_backoff_th_ns: 300000 # ULBFW must be completed by cplane send time - this is the backoff time + sendCPlane_dlbfw_backoff_th_ns: 300000 # DLBFW must be completed by cplane send time - this is the backoff time + pusch_forcedNumCsi2Bits: 0 + mMIMO_enable: 0 + enable_srs: 1 + ue_mode: 0 + mCh_segment_proc_enable: 0 + pusch_aggr_per_ctx: 3 + prach_aggr_per_ctx: 2 + pucch_aggr_per_ctx: 4 + srs_aggr_per_ctx: 3 + ul_input_buffer_per_cell: 10 + ul_input_buffer_per_cell_srs: 6 + max_harq_pools: 384 + max_harq_tx_count_bundled: 10 + max_harq_tx_count_non_bundled: 4 + ok_testbench_config: + enable_ok_tb: 0 + num_ok_tb_slot: 0 #Presently not used + max_ru_unhealthy_ul_slots: 100 + srs_chest_algo_type: 0 + srs_chest_tol2_normalization_algo_type: 1 + srs_chest_tol2_constant_scaler: 32768.0 + bfw_power_normalization_alg_selector: 1 + total_num_srs_chest_buffers: 6144 + send_static_bfw_wt_all_cplane: 1 + ul_pcap_capture_enable: 0 + ul_pcap_capture_thread_cpu_affinity: 10 + ul_pcap_capture_thread_sched_priority: 95 + pcap_logger_ul_cplane_enable: 0 + pcap_logger_dl_cplane_enable: 0 + pcap_logger_thread_cpu_affinity: 10 + pcap_logger_thread_sched_prio: 95 + pcap_logger_file_save_dir: ./ + dlc_bfw_enable_divide_per_cell: 0 # Enable/disable dividing DL BFW C-Plane transmission window among multiple cells in a slot + ulc_bfw_enable_divide_per_cell: 0 # Enable/disable dividing UL BFW C-Plane transmission window among multiple cells in a slot + dlc_alloc_cplane_bfw_txq: 0 # Allocates a second separate queue for BFW DL C-Plane transmission + ulc_alloc_cplane_bfw_txq: 1 # Allocates a second separate queue for BFW UL C-Plane transmission + #static beam id range + static_beam_id_start: 1 + static_beam_id_end: 16527 + #dynamic beam id range + dynamic_beam_id_start: 16528 #Dynamic beam ID start should be after static beam ID end + dynamic_beam_id_end: 32767 #15bit max value + bfw_c_plane_chaining_mode: 0 # 0: Default memcpy of BFW weights, 1: CPU mbuf chaining of BFW weights, 2: GPU mbuf chaining + enable_l1_param_sanity_check: 0 + pusch_nMaxLdpcHetConfigs: 32 + notify_ul_harq_buffer_release: 0 + + # data_config: + # datalake_core: 12 # This must be set for Data Lake and/or E3 Agent to be used + # datalake_db_write_enable: 1 # Enable/disable ClickHouse writes based on datalake_data_types + # datalake_samples: 1000000 + # datalake_address: localhost + # datalake_engine: "MergeTree() PRIMARY KEY (TsTaiNs)" + # # datalake_drop_tables: 0 # Set to 1 to drop Clickhouse tables at startup + # datalake_data_types: [fh, pusch, hest] # Data types to write to ClickHouse DB (all types always collected in memory for E3 Agent): + # fh = Fronthaul IQ samples,pusch = PUSCH/FAPI data, hest = channel estimates + # datalake_store_failed_pdu: 0 # Set to 1 to store PDU data even when CRC fails + # e3_agent_enable: 0 # Enable/disable E3 Agent and dApp capabilities + # num_rows_fh: 120 + # num_rows_pusch: 200 + # num_rows_hest: 140 + # e3_pub_port: 5555 # E3 publisher port for indication messages + # e3_rep_port: 5556 # E3 reply port for E3AP requests + # e3_sub_port: 5560 # E3 subscriber port for Manager messages + + cells: + - name: O-RU 0 + cell_id: 1 + ru_type: 1 + # set to 00:00:00:00:00:00 to use the MAC address of the NIC port to use + src_mac_addr: 00:00:00:00:00:00 + dst_mac_addr: e8:c7:cf:ad:12:0b #WNC n78 + nic: '0000:01:00.0' + vlan: 500 + pcp: 7 + txq_count_uplane: 1 + eAxC_id_ssb_pbch: [0, 1, 2, 3] + eAxC_id_pdcch: [0, 1, 2, 3] + eAxC_id_pdsch: [0, 1, 2, 3] + eAxC_id_csirs: [0, 1, 2, 3] + eAxC_id_pusch: [0, 1, 2, 3] + eAxC_id_pucch: [0, 1, 2, 3] + eAxC_id_srs: [8, 9, 10, 11] + eAxC_id_prach: [4, 5, 6, 7] + dl_iq_data_fmt: {comp_meth: 1, bit_width: 9} + ul_iq_data_fmt: {comp_meth: 1, bit_width: 9} + section_3_time_offset: 484 + fs_offset_dl: 7 + exponent_dl: 4 + ref_dl: 0 + fs_offset_ul: -5 + exponent_ul: 4 + max_amp_ul: 65504 + mu: 1 + T1a_max_up_ns: 280000 + T1a_max_cp_ul_ns: 405000 + Ta4_min_ns: 50000 + Ta4_max_ns: 331000 + Tcp_adv_dl_ns: 125000 + ul_u_plane_tx_offset_ns: 280000 + fh_len_range: 0 + pusch_prb_stride: 273 + prach_prb_stride: 12 + srs_prb_stride: 273 + pusch_ldpc_max_num_itr_algo_type: 1 + pusch_fixed_max_num_ldpc_itrs: 10 + pusch_ldpc_early_termination: 0 + pusch_ldpc_algo_index: 0 + pusch_ldpc_flags: 2 + pusch_ldpc_use_half: 1 + pusch_nMaxPrb: 273 + pusch_nMaxRx: 4 + ul_gain_calibration: 78.68 + lower_guard_bw: 845 + tv_pusch: cuPhyChEstCoeffs.h5 diff --git a/ci-scripts/yaml_files/sa_gnb_aerial_ul/cuphycontroller_P5G_WNC_GH_ul.yaml b/ci-scripts/yaml_files/sa_gnb_aerial_ul/cuphycontroller_P5G_WNC_GH_ul.yaml new file mode 100644 index 0000000000..4866ae1ce1 --- /dev/null +++ b/ci-scripts/yaml_files/sa_gnb_aerial_ul/cuphycontroller_P5G_WNC_GH_ul.yaml @@ -0,0 +1,243 @@ +# SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +aerial_sdk_version: 25-3-cubb +l2adapter_filename: l2_adapter_config_P5G_GH.yaml +aerial_metrics_backend_address: 127.0.0.1:8081 + +# CPU core shared by all low-priority threads +low_priority_core: 10 +enable_ptp_svc_monitoring: 0 +ptp_rms_threshold: 20 #ns +nic_tput_alert_threshold_mbps: 85000 + +cuphydriver_config: + standalone: 0 + validation: 0 + num_slots: 8 + log_level: DBG + profiler_sec: 0 + dpdk_thread: 10 + dpdk_verbose_logs: 0 + accu_tx_sched_res_ns: 500 + accu_tx_sched_disable: 0 #Flag applicable only for CX6-DX : BF3/CX7 HW and beyond support accurate send scheduling directly on timestamp, for CX6-DX this is implemented via software emulation + fh_stats_dump_cpu_core: -1 + pdump_client_thread: -1 + use_green_contexts: 0 + use_batched_memcpy: 0 # Experimental feature; requires >= CUDA 12.8 + mps_sm_pusch: 100 + mps_sm_pucch: 2 + mps_sm_prach: 2 + mps_sm_ul_order: 20 + mps_sm_pdsch: 102 + mps_sm_pdcch: 10 + mps_sm_pbch: 2 + mps_sm_gpu_comms: 16 + mps_sm_srs: 16 + pdsch_fallback: 0 + dpdk_file_prefix: cuphycontroller + nics: + - nic: '0000:01:00.0' + mtu: 9216 + cpu_mbufs: 196608 + uplane_tx_handles: 64 + txq_size: 8192 + rxq_size: 16384 + gpu: 0 + cus_port_failover: 0 + gpus: + - 0 + # Set GPUID to the GPU sharing the PCIe switch as NIC + # run nvidia-smi topo -m to find out which GPU + workers_ul: [4,5] + workers_dl: [6,7,8] + debug_worker: -1 + workers_sched_priority: 95 + prometheus_thread: -1 + start_section_id_srs: 3072 + start_section_id_prach: 2048 + enable_ul_cuphy_graphs: 1 + enable_dl_cuphy_graphs: 1 + ul_order_kernel_mode: 0 # 0: Ping-Pong, 1: dual CTA + ul_order_timeout_cpu_ns: 8000000 + ul_order_timeout_log_interval_ns: 1000000000 + ul_order_timeout_gpu_ns: 3000000 + ul_order_timeout_gpu_srs_ns: 5200000 + ul_srs_aggr3_task_launch_offset_ns: 500000 + ul_order_timeout_gpu_log_enable: 0 + ul_order_max_rx_pkts: 512 + ul_order_rx_pkts_timeout_ns: 100000 + cplane_disable: 0 + gpu_init_comms_dl: 1 + cell_group: 1 + cell_group_num: 1 + fix_beta_dl: 0 + bfw_beta_prescaler: 16384 + pusch_workCancelMode: 2 # set cuphyPuschStatPrms_t workCancelMode field to PUSCH_DEVICE_GRAPHS; this only sets the mode and does not cancel work; + # work cancellation (i.e., not launching some of the device graphs) can only occur after an explicit internal + # memory write is timely observed by a PUSCH graph. + pusch_sinr: 2 + pusch_rssi: 1 + pusch_tdi: 1 + pusch_cfo: 1 + pusch_dftsofdm: 0 + pusch_to: 1 + pusch_select_eqcoeffalgo: 3 + pusch_select_chestalgo: 1 + pusch_enable_perprgchest: 0 + pusch_tbsizecheck: 1 + pusch_deviceGraphLaunchEn: 1 + pusch_waitTimeOutPreEarlyHarqUs: 3000 + pusch_waitTimeOutPostEarlyHarqUs: 3000 + puxch_polarDcdrListSz: 8 + enable_cpu_task_tracing: 0 + enable_prepare_tracing: 0 + disable_empw: 0 #1=>Disables Multi packet WQE feature + cqe_tracer_config: + enable_dl_cqe_tracing: 0 + cqe_trace_cell_mask: 1 #[64 bit mask: Bit0->Cell0, Bit1->Cell1...] + cqe_trace_slot_mask: 196800 #[20 bit mask: Bit0->Slot0, Bit1->Slot1...] 196800=>All *6,*7 DL Slots + ul_rx_pkt_tracing_level: 0 + ul_rx_pkt_tracing_level_srs: 0 + pmu_metrics: 0 #Enable and select PMU metrics, 0=disabled, 1=General Counters (platform agnostic), 2=Topdown Metrics (Grace only), 3=Cache Metrics (Grace only) + enable_h2d_copy_thread: 1 + h2d_copy_thread_cpu_affinity : 11 + h2d_copy_thread_sched_priority : 95 #0->SCHED_OTHER, >0->Actual + split_ul_cuda_streams: 0 # 1=Put UL slot 4 and slot 5 on different streams for DDDSUUDDDD pattern + serialize_pucch_pusch: 0 # 1=Force serialization of PUSCH/PUCCH + # Note: for Early Harq (EH) order is PUSCH EH -> PUCCH -> PUSCH non EH + # for non-Early Harq order is PUCCH -> all PUSCH processing + aggr_obj_non_avail_th: 5 # Threshold for consecutive non-availability of Aggregated objects(UL/DL) or DL/UL buffers + dl_wait_th_ns: + - 500000 #H2D copy wait threshold + - 4000000 #cuPHY DL channel wait threshold + sendCPlane_timing_error_th_ns : 0 + sendCPlane_ulbfw_backoff_th_ns: 300000 # ULBFW must be completed by cplane send time - this is the backoff time + sendCPlane_dlbfw_backoff_th_ns: 300000 # DLBFW must be completed by cplane send time - this is the backoff time + pusch_forcedNumCsi2Bits: 0 + mMIMO_enable: 0 + enable_srs: 1 + ue_mode: 0 + mCh_segment_proc_enable: 0 + pusch_aggr_per_ctx: 9 #3 + prach_aggr_per_ctx: 2 + pucch_aggr_per_ctx: 4 + srs_aggr_per_ctx: 3 + ul_input_buffer_per_cell: 10 + ul_input_buffer_per_cell_srs: 6 + max_harq_pools: 384 + max_harq_tx_count_bundled: 10 + max_harq_tx_count_non_bundled: 4 + ok_testbench_config: + enable_ok_tb: 0 + num_ok_tb_slot: 0 #Presently not used + max_ru_unhealthy_ul_slots: 100 + srs_chest_algo_type: 0 + srs_chest_tol2_normalization_algo_type: 1 + srs_chest_tol2_constant_scaler: 32768.0 + bfw_power_normalization_alg_selector: 1 + total_num_srs_chest_buffers: 6144 + send_static_bfw_wt_all_cplane: 1 + ul_pcap_capture_enable: 0 + ul_pcap_capture_thread_cpu_affinity: 10 + ul_pcap_capture_thread_sched_priority: 95 + pcap_logger_ul_cplane_enable: 0 + pcap_logger_dl_cplane_enable: 0 + pcap_logger_thread_cpu_affinity: 10 + pcap_logger_thread_sched_prio: 95 + pcap_logger_file_save_dir: ./ + dlc_bfw_enable_divide_per_cell: 0 # Enable/disable dividing DL BFW C-Plane transmission window among multiple cells in a slot + ulc_bfw_enable_divide_per_cell: 0 # Enable/disable dividing UL BFW C-Plane transmission window among multiple cells in a slot + dlc_alloc_cplane_bfw_txq: 0 # Allocates a second separate queue for BFW DL C-Plane transmission + ulc_alloc_cplane_bfw_txq: 1 # Allocates a second separate queue for BFW UL C-Plane transmission + #static beam id range + static_beam_id_start: 1 + static_beam_id_end: 16527 + #dynamic beam id range + dynamic_beam_id_start: 16528 #Dynamic beam ID start should be after static beam ID end + dynamic_beam_id_end: 32767 #15bit max value + bfw_c_plane_chaining_mode: 0 # 0: Default memcpy of BFW weights, 1: CPU mbuf chaining of BFW weights, 2: GPU mbuf chaining + enable_l1_param_sanity_check: 0 + pusch_nMaxLdpcHetConfigs: 32 + notify_ul_harq_buffer_release: 0 + + # data_config: + # datalake_core: 12 # This must be set for Data Lake and/or E3 Agent to be used + # datalake_db_write_enable: 1 # Enable/disable ClickHouse writes based on datalake_data_types + # datalake_samples: 1000000 + # datalake_address: localhost + # datalake_engine: "MergeTree() PRIMARY KEY (TsTaiNs)" + # # datalake_drop_tables: 0 # Set to 1 to drop Clickhouse tables at startup + # datalake_data_types: [fh, pusch, hest] # Data types to write to ClickHouse DB (all types always collected in memory for E3 Agent): + # fh = Fronthaul IQ samples,pusch = PUSCH/FAPI data, hest = channel estimates + # datalake_store_failed_pdu: 0 # Set to 1 to store PDU data even when CRC fails + # e3_agent_enable: 0 # Enable/disable E3 Agent and dApp capabilities + # num_rows_fh: 120 + # num_rows_pusch: 200 + # num_rows_hest: 140 + # e3_pub_port: 5555 # E3 publisher port for indication messages + # e3_rep_port: 5556 # E3 reply port for E3AP requests + # e3_sub_port: 5560 # E3 subscriber port for Manager messages + + cells: + - name: O-RU 0 + cell_id: 1 + ru_type: 1 + # set to 00:00:00:00:00:00 to use the MAC address of the NIC port to use + src_mac_addr: 00:00:00:00:00:00 + dst_mac_addr: e8:c7:cf:ad:12:0b #WNC n78 + nic: '0000:01:00.0' + vlan: 500 + pcp: 7 + txq_count_uplane: 1 + eAxC_id_ssb_pbch: [0, 1, 2, 3] + eAxC_id_pdcch: [0, 1, 2, 3] + eAxC_id_pdsch: [0, 1, 2, 3] + eAxC_id_csirs: [0, 1, 2, 3] + eAxC_id_pusch: [0, 1, 2, 3] + eAxC_id_pucch: [0, 1, 2, 3] + eAxC_id_srs: [8, 9, 10, 11] + eAxC_id_prach: [4, 5, 6, 7] + dl_iq_data_fmt: {comp_meth: 1, bit_width: 9} + ul_iq_data_fmt: {comp_meth: 1, bit_width: 9} + section_3_time_offset: 484 + fs_offset_dl: 7 + exponent_dl: 4 + ref_dl: 0 + fs_offset_ul: -5 + exponent_ul: 4 + max_amp_ul: 65504 + mu: 1 + T1a_max_up_ns: 280000 + T1a_max_cp_ul_ns: 405000 + Ta4_min_ns: 50000 + Ta4_max_ns: 331000 + Tcp_adv_dl_ns: 125000 + ul_u_plane_tx_offset_ns: 280000 + fh_len_range: 0 + pusch_prb_stride: 273 + prach_prb_stride: 12 + srs_prb_stride: 273 + pusch_ldpc_max_num_itr_algo_type: 1 + pusch_fixed_max_num_ldpc_itrs: 10 + pusch_ldpc_early_termination: 0 + pusch_ldpc_algo_index: 0 + pusch_ldpc_flags: 2 + pusch_ldpc_use_half: 1 + pusch_nMaxPrb: 273 + pusch_nMaxRx: 4 + ul_gain_calibration: 78.68 + lower_guard_bw: 845 + tv_pusch: cuPhyChEstCoeffs.h5 From de0d100d678567efdfd90f8bc4bb32c68cef0843 Mon Sep 17 00:00:00 2001 From: Reem Bahsoun Date: Mon, 19 Jan 2026 13:03:46 +0100 Subject: [PATCH 4/7] Update nvIPC library to match the new cuBB image --- ci-scripts/cls_containerize.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ci-scripts/cls_containerize.py b/ci-scripts/cls_containerize.py index d20bac6f44..490428abf7 100644 --- a/ci-scripts/cls_containerize.py +++ b/ci-scripts/cls_containerize.py @@ -417,13 +417,13 @@ class Containerize(): elif image != 'ran-build': cmd.run(f'sed -i -e "s#ran-build:latest#ran-build:{imageTag}#" docker/Dockerfile.{pattern}{self.dockerfileprefix}') if image == 'oai-gnb-aerial': - cmd.run('cp -f /opt/nvidia-ipc/nvipc_src.2025.10.09.tar.gz .') + cmd.run('cp -f /opt/nvidia-ipc/nvipc_src.2026.01.07.tar.gz .') logfile = f'{lSourcePath}/cmake_targets/log/{name}.docker.log' ret = cmd.run(f'{self.cli} build {self.cliBuildOptions} --target {image} --tag {name}:{imageTag} --file docker/Dockerfile.{pattern}{self.dockerfileprefix} {option} . > {logfile} 2>&1', timeout=1200) t = (name, archiveArtifact(cmd, ctx, logfile)) log_files.append(t) if image == 'oai-gnb-aerial': - cmd.run('rm -f nvipc_src.2025.10.09.tar.gz') + cmd.run('rm -f nvipc_src.2026.01.07.tar.gz') # check the status of the build ret = cmd.run(f"{self.cli} image inspect --format=\'Size = {{{{.Size}}}} bytes\' {name}:{imageTag}") if ret.returncode != 0: From 283063f3da80bee0d419ae7b5746349f2b4a42dd Mon Sep 17 00:00:00 2001 From: Reem Bahsoun Date: Tue, 27 Jan 2026 14:13:26 +0100 Subject: [PATCH 5/7] Update tutorial to align with the new Aerial release (25-3) --- doc/Aerial_FAPI_Split_Tutorial.md | 294 +++++++++++++++++++----------- 1 file changed, 190 insertions(+), 104 deletions(-) diff --git a/doc/Aerial_FAPI_Split_Tutorial.md b/doc/Aerial_FAPI_Split_Tutorial.md index 58380ba611..24a085c8e4 100644 --- a/doc/Aerial_FAPI_Split_Tutorial.md +++ b/doc/Aerial_FAPI_Split_Tutorial.md @@ -1,4 +1,4 @@ -# OAI 7.2 Fronthaul Interface 5G SA Tutorial +# OAI - Aerial FAPI Split Tutorial **Table of Contents** @@ -14,9 +14,12 @@ The hardware on which we have tried this tutorial: | Dell PowerEdge R750 (Dual Intel Xeon Gold 6336Y CPU @ 2.4G, 24C/48T (185W), 512GB RDIMM, 3200MT/s) |Ubuntu 22.04.3 LTS (5.15.0-72-lowlatency)| NVIDIA Converged Accelerator A100X (24.39.2048) | | Supermicro Grace Hopper MGX ARS-111GL-NHR (Neoverse-V2, 3.4GHz, 72C/72T, 576GB LPDDR5) | Ubuntu 22.04.5 LTS (6.5.0-1019-nvidia-64k) |NVIDIA BlueField3 (32.41.1000)| -**NOTE**: -- These are not minimum hardware requirements. This is the configuration of our servers. The NIC card should support hardware PTP time stamping. -- Starting from tag [2025.w13](https://gitlab.eurecom.fr/oai/openairinterface5g/-/tree/2025.w13?ref_type=tags) of OAI, we are only testing with the Grace Hopper server. +**Note**: +- These are not minimum hardware requirements. This is the configuration of our + servers. The NIC card should support hardware PTP time stamping. +- Starting from tag + [2025.w13](https://gitlab.eurecom.fr/oai/openairinterface5g/-/tree/2025.w13?ref_type=tags) + of OAI, we are only testing with the Grace Hopper server. PTP enabled switches and grandmaster clock we have tested with: @@ -54,10 +57,10 @@ The UEs that have been tested and confirmed working with Aerial are the followin To set up the L1 and install the components manually refer to this [instructions page](https://docs.nvidia.com/aerial/cuda-accelerated-ran/index.html). **Note**: -- As of wk36, the L1 must be compiled with the following CMake flag: `-DSCF_FAPI_10_04_SRS=ON` , this is due to the usage -of the FAPI 10.04 version of the SRS PDU, and RX_Beamforming PDU. -- To configure the Gigabyte server please refer to these [instructions](https://gitlab.eurecom.fr/oai/openairinterface5g/-/blob/2025.w13/doc/Aerial_FAPI_Split_Tutorial.md) -- The last release to support the Gigabyte server is **Aerial CUDA-Accelerated RAN 24-1**. +- To configure the Gigabyte server please refer to these + [instructions](https://gitlab.eurecom.fr/oai/openairinterface5g/-/blob/2025.w13/doc/Aerial_FAPI_Split_Tutorial.md) +- The last release to support the Gigabyte server is **Aerial CUDA-Accelerated + RAN 24-1**. #### CPU allocation @@ -67,21 +70,43 @@ of the FAPI 10.04 version of the SRS PDU, and RX_Beamforming PDU. **Grace Hopper MGX ARS-111GL-NHR** -| Applicative Threads | Allocated CPUs | -|------------------------|----------------| -| PTP & PHC2SYS Services | 41 | -| OAI `nr-softmodem` | 13-16 | +| Applicative Threads | Allocated CPUs | +|--------------------------------------|--------------------------------| +| `workers_ul` | 4, 5 | +| `workers_dl` | 6, 7, 8 | +| `timer_thread_config` | 9 | +| `message_thread_config` | 9 | +| `pcap_shm_caching_cpu_core` | 10 | +| `pcap_file_saving_cpu_core` | 10 | +| `dpdk_thread` | 10 | +| `ul_pcap_capture_thread_cpu_affinity`| 10 | +| `pcap_logger_thread_cpu_affinity` | 10 | +| `h2d_copy_thread_cpu_affinity` | 11 | +| `fh_stats_dump_cpu_core` | -1 | +| `pdump_client_thread` | -1 | +| `debug_worker` | -1 | +| `prometheus_thread` | -1 | +| | | +| OAI `nr-softmodem` | 13,14,15,16 | -### PTP configuration +**Note**: +- `-1` indicates that no explicit CPU pinning is applied and the thread +is scheduled by the Linux kernel. +- core 10 is a `low_priority_core` and it is shared by all low-priority threads. -1. You need to install the `linuxptp` debian package. It will install both ptp4l and phc2sys. +#### PTP configuration + +1. Install the `linuxptp` debian package. It will install both + ptp4l and phc2sys. ```bash #Ubuntu sudo apt install linuxptp -y ``` -Once installed you can use this configuration file for ptp4l (`/etc/ptp4l.conf`). Here the clock domain is 24 so you can adjust it according to your PTP GM clock domain +Once installed you can use this configuration file for ptp4l +(`/etc/ptp4l.conf`). Here the clock domain is 24 so you can adjust it according +to your PTP GM clock domain ``` [global] @@ -94,25 +119,27 @@ tx_timestamp_timeout 30 network_transport L2 ``` +The service of ptp4l (`/lib/systemd/system/ptp4l.service`) should be configured +as below: -The service of ptp4l (`/lib/systemd/system/ptp4l.service`) should be configured as below: ``` -[Unit] -Description=Precision Time Protocol (PTP) service +[Unit] Description=Precision Time Protocol (PTP) service Documentation=man:ptp4l [Service] Restart=always RestartSec=5s Type=simple -ExecStart=taskset -c 41 /usr/sbin/ptp4l -f /etc/ptp.conf +ExecStart=/usr/sbin/ptp4l -f /etc/ptp.conf [Install] WantedBy=multi-user.target ``` -and service of phc2sys (`/lib/systemd/system/phc2sys.service`) should be configured as below: +and service of phc2sys (`/lib/systemd/system/phc2sys.service`) should be +configured as below: + ``` [Unit] Description=Synchronize system clock or PTP hardware clock (PHC) @@ -131,10 +158,25 @@ ExecStart=/usr/sbin/phc2sys -a -r -n 24 WantedBy=multi-user.target ``` +**Note**: As of release 25-3 there's no need to allocate a core for PTP. + +## Prepare the L1 + +- Follow these + [instructions](https://github.com/NVIDIA/aerial-cuda-accelerated-ran) to + clone the `aerial-cuda-accelerated-ran` repository, pull and build the cuBB + image. +- The CMake flags we use to compile the L1 are: + - `-DSCF_FAPI_10_04_SRS=ON` this flag must be used as of OAI tag `2025.w36` + and this is due to the usage of the FAPI 10.04 version of the SRS PDU, and + RX_Beamforming PDU. + - `-DENABLE_CONFORMANCE_TM_PDSCH_PDCCH=OFF` this option should only be + enabled when doing conformance testing with testmac. ## Build OAI gNB If it's not already cloned, the first step is to clone OAI repository + ```bash git clone https://gitlab.eurecom.fr/oai/openairinterface5g.git ~/openairinterface5g cd ~/openairinterface5g/ @@ -142,65 +184,42 @@ cd ~/openairinterface5g/ ### Get nvIPC sources from the L1 container -The library used for communication between L1 and L2 components is called nvIPC, and is developed by NVIDIA. It is not open-source and can't be freely distributed. -In order to achieve this communication, we need to obtain the nvIPC source files from the L1 container (cuBB) and place it in the gNB project directory `~/openairinterface5g`. -This allows us to build and install this library when building the L2 docker container. - -Check whether your L1 container is running: -```bash -~$ docker container ls -a -CONTAINER ID IMAGE COMMAND CREATED STATUS PORTS NAMES -a9681a0c4a10 14dca2002237 "/opt/nvidia/nvidia_…" 3 months ago Exited (137) 10 days ago cuBB - -``` -If it is not running, you may start it and logging into the container by running the following: -```bash -~$ docker start cuBB -cuBB -~$ docker exec -it cuBB bash -aerial@c_aerial_aerial:/opt/nvidia/cuBB# -``` - -After logging into the container, you need to pack the nvIPC sources and copy them to the host ( the command creates a `tar.gz` file with the following name format: `nvipc_src.YYYY.MM.DD.tar.gz`) -```bash -~$ docker exec -it cuBB bash -aerial@c_aerial_aerial:/opt/nvidia/cuBB# cd cuPHY-CP/gt_common_libs -aerial@c_aerial_aerial:/opt/nvidia/cuBB/cuPHY-CP/gt_common_libs#./pack_nvipc.sh -nvipc_src.YYYY.MM.DD/ -... ---------------------------------------------- -Pack nvipc source code finished: -/opt/nvidia/cuBB/cuPHY-CP/gt_common_libs/nvipc_src.YYYY.MM.DD.tar.gz -aerial@c_aerial_aerial:/opt/nvidia/cuBB/cuPHY-CP/gt_common_libs# sudo cp nvipc_src.yyyy.mm.dd.tar.gz /opt/cuBB/share/ -aerial@c_aerial_aerial:/opt/nvidia/cuBB/cuPHY-CP/gt_common_libs# exit -``` - -The file should now be present in the `~/openairinterface5g/ci-scripts/yaml_files/sa_gnb_aerial/` directory, from where it is moved into `~/openairinterface5g` -```bash -~$ mv ~/openairinterface5g/ci-scripts/yaml_files/sa_gnb_aerial/nvipc_src.YYYY.MM.DD.tar.gz ~/openairinterface5g/ -``` - -Alternatively, after running `./pack_nvipc.sh` , you can exit the container and copy `nvipc_src.YYYY.MM.DD.tar.gz` using `docker cp` +The library used for communication between L1 and L2 components is called +nvIPC, and is developed by NVIDIA. In order to achieve this communication, we +need to obtain the nvIPC source files from the L1 container (cuBB) and place it +in the gNB project directory `~/openairinterface5g`. This allows us to build +and install this library when building the L2 docker image. ```bash -~$ docker exec -it cuBB bash -aerial@c_aerial_aerial:/opt/nvidia/cuBB# cd cuPHY-CP/gt_common_libs -aerial@c_aerial_aerial:/opt/nvidia/cuBB/cuPHY-CP/gt_common_libs#./pack_nvipc.sh -nvipc_src.YYYY.MM.DD/ -... ---------------------------------------------- -Pack nvipc source code finished: -/opt/nvidia/cuBB/cuPHY-CP/gt_common_libs/nvipc_src.YYYY.MM.DD.tar.gz -aerial@c_aerial_aerial:/opt/nvidia/cuBB/cuPHY-CP/gt_common_libs# exit -~$ docker cp nv-cubb:/opt/nvidia/cuBB/cuPHY-CP/gt_common_libs/nvipc_src.YYYY.MM.DD.tar.gz ~/openairinterface5g +# Start interactive development container +./cuPHY-CP/container/run_aerial.sh + +# Pack the nvIPC sources and copy them to the host ( the command creates a `tar.gz` file with the following name format: `nvipc_src.YYYY.MM.DD.tar.gz`) +aerial@c_aerial_oaicicd:/opt/nvidia/cuBB# cd cuPHY-CP/gt_common_libs +aerial@c_aerial_oaicicd:/opt/nvidia/cuBB/cuPHY-CP/gt_common_libs#./pack_nvipc.sh +nvipc_src.YYYY.MM.DD/ ... --------------------------------------------- Pack +nvipc source code finished:/opt/nvidia/cuBB/cuPHY-CP/gt_common_libs/nvipc_src.YYYY.MM.DD.tar.gz ``` -*Important note:* For using docker cp, make sure to copy the entire name of the created nvipc_src tar.gz file. + +Keep the interactive development container open and in another terminal use +`docker cp` to copy the library + +```bash +docker cp c_aerial_oaicicd:/opt/nvidia/cuBB/cuPHY-CP/gt_common_libs/nvipc_src.YYYY.MM.DD.tar.gz ~/openairinterface/ +``` +*Important note:* For using docker cp, make sure to +copy the entire name of the created nvipc_src tar.gz file. + +You can now exit the interactive development container. + +With the nvIPC sources in the project directory, the L2 docker image can be built. -With the nvIPC sources in the project directory, the docker image can be built. ### Building OAI gNB docker image -In order to build the target image (`oai-gnb-aerial`), first you should build a common shared image (`ran-base`) +In order to build the target image (`oai-gnb-aerial`), first you should build a +common shared image (`ran-base`) + ```bash ~$ cd ~/openairinterface5g/ ~/openairinterface5g$ docker build . -f docker/Dockerfile.base.ubuntu --tag ran-base:latest @@ -210,52 +229,113 @@ In order to build the target image (`oai-gnb-aerial`), first you should build a ## Running the setup -In order to use Docker Compose to automatically start and stop the setup, we first need to create a pre-built image of L1 after compiling the L1 software and making the necessary adjustments to its configuration files. -The process of preparing L1 is covered in NVIDIA's documentation and falls outside the scope of this document. - -### Prepare the L1 image -After preparing the L1 software, the container needs to be committed to create an image where L1 is ready for execution, which can later be referenced by a `docker-compose.yaml` file. - -*Note:* The default L1 configuration file is `cuphycontroller_P5G_FXN_GH.yaml`, located in `/opt/nvidia/cuBB/cuPHY-CP/cuphycontroller/config/`. -In this file the RU MAC address needs to be specified before commiting the image. - -```bash -~$ docker commit nv-cubb cubb-build:25-2.1 -~$ docker image ls -.. -cubb-build 25-2.1 824156e0334c 2 weeks ago 23.9GB --.. -``` - ### Adapt the OAI-gNB configuration file to your system/workspace -Edit the sample OAI gNB configuration file and check following parameters: +Edit the [OAI gNB configuration file](https://gitlab.eurecom.fr/oai/openairinterface5g/-/blob/develop/ci-scripts/conf_files/gnb-vnf.sa.band78.273prb.aerial.conf?ref_type=heads) +and check the following parameters: * `gNBs` section * The PLMN section shall match the one defined in the AMF + * To calculate the `absoluteFrequencySSB` and `dl_absoluteFrequencyPointA`, + please follow these + [instructions](https://gitlab.eurecom.fr/oai/openairinterface5g/-/blob/develop/doc/gNB_frequency_setup.md) * `amf_ip_address` shall be the correct AMF IP address in your system * `GNB_IPV4_ADDRESS_FOR_NG_AMF` shall match your DU N2 interface IP address * `GNB_IPV4_ADDRESS_FOR_NGU` shall match your DU N3 interface IP address -The default amf_ip_address:ipv4 value is 192.168.70.132, when installing the CN5G following [this tutorial](https://gitlab.eurecom.fr/oai/openairinterface5g/-/blob/develop/doc/NR_SA_Tutorial_OAI_CN5G.md) -Both 'GNB_IPV4_ADDRESS_FOR_NG_AMF' and 'GNB_IPV4_ADDRESS_FOR_NGU' need to be set to the IP address of the NIC referenced previously. +The default amf_ip_address:ipv4 value is 192.168.70.132, when installing the +CN5G following [this +tutorial](https://gitlab.eurecom.fr/oai/openairinterface5g/-/blob/develop/doc/NR_SA_Tutorial_OAI_CN5G.md) +Both `GNB_IPV4_ADDRESS_FOR_NG_AMF` and `GNB_IPV4_ADDRESS_FOR_NGU` need to be +set to the IP address of the NIC referenced previously. +**Note**: If the Core Network is running on the same server, 3 cores should be +allocated to it. 2 for the UPF and 1 for the all the remaining services as shown +below. -### Running docker compose -#### Aerial L1 entrypoint script -The `aerial_l1_entrypoint` script is used by the L1 container to start the L1 software and is called in the Docker Compose file. -It begins by setting up environment variables, restarting NVIDIA MPS, and finally running `cuphycontroller_scf`. +```patch +diff --git a/docker-compose/docker-compose-basic-nrf.yaml b/docker-compose/docker-compose-basic-nrf.yaml +index 7fbefc9..d5ef964 100644 +--- a/docker-compose/docker-compose-basic-nrf.yaml ++++ b/docker-compose/docker-compose-basic-nrf.yaml +@@ -28,6 +28,7 @@ services: + - 8080/tcp + volumes: + - ./conf/basic_nrf_config.yaml:/openair-udr/etc/config.yaml ++ cpuset: "15" + environment: + - TZ=Europe/Paris + depends_on: +``` -The L1 software is executed with an argument that specifies which configuration file to use. If not modified, the default argument is set to `P5G_FXN_GH`. +### Aerial L1 entrypoint script -After building the gNB image, and preparing the configuration file, the setup can be run with the following command: +The `aerial_l1_entrypoint` script is used by the L1 container to start the L1 +software and is mounted in the Docker Compose file. It begins by setting up +environment variables, restarting NVIDIA MPS, and finally running +`cuphycontroller_scf`. + +The L1 software is executed with an argument that specifies which configuration +file to use. If not modified, the default argument is set to `P5G_WNC_GH`. + +### Aerial L1 configuration + +```bash +cd ~/aerial-cuda-accelerated-ran/cuPHY-CP/cuphycontroller/config/ +``` + +Choose the configuration file that matches your setup and make the necessary +changes. We currently use `cuphycontroller_P5G_WNC_GH.yaml`. + +Make sure that the following parameters are modified: + +``` +dst_mac_addr: +nic: +vlan: +``` + +### Docker compose + +We recommend the user to apply the patch below for `docker-compose.yaml`. +```patch +diff --git a/ci-scripts/yaml_files/sa_gnb_aerial/docker-compose.yaml b/ci-scripts/yaml_files/sa_gnb_aerial/docker-compose.yaml +index 985fe9a6a3..0774d826ac 100644 +--- a/ci-scripts/yaml_files/sa_gnb_aerial/docker-compose.yaml ++++ b/ci-scripts/yaml_files/sa_gnb_aerial/docker-compose.yaml +@@ -15,10 +15,10 @@ services: + stdin_open: true + tty: true + volumes: ++ - ~/aerial-cuda-accelerated-ran:/opt/nvidia/cuBB/ + - /lib/modules:/lib/modules + - /dev/hugepages:/dev/hugepages + - /usr/src:/usr/src +- - ./cuphycontroller_P5G_WNC_GH.yaml:/opt/nvidia/cuBB/cuPHY-CP/cuphycontroller/config/cuphycontroller_P5G_WNC_GH.yaml + - ./aerial_l1_entrypoint.sh:/opt/nvidia/cuBB/aerial_l1_entrypoint.sh + - /var/log/aerial:/var/log/aerial + - ../../../cmake_targets/share:/opt/cuBB/share +``` + +By applying this change, it would easier for the user to modify the L1 code or +configuration files directly from the `aerial-cuda-accelerated-ran` repository. + +`ci-scripts/yaml_files/sa_gnb_aerial/docker-compose.yaml` is tailored for our +CI. +We copy the `aerial-cuda-accelerated-ran` repository inside the cuBB +docker image using `docker cp` and commit the changes using `docker commit`. +We mount the `cuphycontroller_P5G_WNC_GH.yaml` in the `nv-cubb` volumes so +that it would override some parameters depending on the setup being run on CI. + +After building the gNB image, and preparing the configuration file, the setup +can be run with the following command: ```bash cd ci-scripts/yaml_files/sa_gnb_aerial/ docker compose up -d - ``` -This will start both containers, beginning with `nv-cubb`, and `oai-gnb-aerial` will start only after it is ready. +This will start both containers, beginning with `nv-cubb`, and +`oai-gnb-aerial` will start only after it is ready. The logs can be followed using these commands: @@ -263,8 +343,13 @@ The logs can be followed using these commands: docker logs -f oai-gnb-aerial docker logs -f nv-cubb ``` + #### Running with multiple L2s -One L1 instance can support multiple L2 instances. See also the [aerial documentation](https://developer.nvidia.com/docs/gputelecom/aerial-sdk/text/cubb_quickstart/running_cubb-end-to-end.html#run-multiple-l2-instances-with-single-l1-instance) for more details. + +One L1 instance can support multiple L2 instances. See also +the [aerial +documentation](https://docs.nvidia.com/aerial/cuda-accelerated-ran/latest/quickstart_guide/running_cubb-end-to-end.html#run-multiple-l2-instances-with-single-l1-instance) +for more details. In OAI the shared memory prefix must be configured in the configuration file. @@ -274,11 +359,12 @@ In OAI the shared memory prefix must be configured in the configuration file. ``` -### Stopping the setup +#### Stopping the setup + +Run the following command to stop and remove both containers, leaving the +system ready to be restarted later: -Run the following command to stop and remove both containers, leaving the system ready to be restarted later: ```bash cd ci-scripts/yaml_files/sa_gnb_aerial/ docker compose down - ``` From 37b1a0a9f3b8f16f091fc9696024b3b0f96b1f2c Mon Sep 17 00:00:00 2001 From: Reem Bahsoun Date: Tue, 27 Jan 2026 14:23:27 +0100 Subject: [PATCH 6/7] Align configuration file in targets/ with the configuration file in ci-scripts/ and fix spacing. --- .../gnb-vnf.sa.band78.273prb.aerial.conf | 55 ++++----- .../CONF/gnb-vnf.sa.band78.273prb.aerial.conf | 110 +++++++----------- 2 files changed, 67 insertions(+), 98 deletions(-) diff --git a/ci-scripts/conf_files/gnb-vnf.sa.band78.273prb.aerial.conf b/ci-scripts/conf_files/gnb-vnf.sa.band78.273prb.aerial.conf index 9e95918e6f..1d99a472c4 100644 --- a/ci-scripts/conf_files/gnb-vnf.sa.band78.273prb.aerial.conf +++ b/ci-scripts/conf_files/gnb-vnf.sa.band78.273prb.aerial.conf @@ -13,16 +13,7 @@ gNBs = // Tracking area code, 0x0000 and 0xfffe are reserved values tracking_area_code = 1; - plmn_list = ({ - mcc = 208; - mnc = 97; - mnc_length = 2; - snssaiList = ( - { - sst = 1; - } - ); - }); + plmn_list = ({ mcc = 208; mnc = 97; mnc_length = 2; snssaiList = ({ sst = 1; }) }); nr_cellid = 12345678L; @@ -186,19 +177,19 @@ gNBs = MACRLCs = ( { - num_cc = 1; - remote_s_address = "127.0.0.1"; // pnf addr [!] - local_s_address = "127.0.0.2"; // vnf addr - local_s_portc = 50001; // vnf p5 port - remote_s_portc = 50000; // pnf p5 port [!] - local_s_portd = 50011; // vnf p7 port [!] - remote_s_portd = 50010; // pnf p7 port [!] - tr_s_preference = "aerial"; - tr_n_preference = "local_RRC"; - pusch_TargetSNRx10 = 280; # 150; - pucch_TargetSNRx10 = 200; #200; - dl_max_mcs = 28; - ul_max_mcs = 28; + num_cc = 1; + remote_s_address = "127.0.0.1"; // pnf addr [!] + local_s_address = "127.0.0.2"; // vnf addr + local_s_portc = 50001; // vnf p5 port + remote_s_portc = 50000; // pnf p5 port [!] + local_s_portd = 50011; // vnf p7 port [!] + remote_s_portd = 50010; // pnf p7 port [!] + tr_s_preference = "aerial"; + tr_n_preference = "local_RRC"; + pusch_TargetSNRx10 = 280; # 150; + pucch_TargetSNRx10 = 200; #200; + dl_max_mcs = 28; + ul_max_mcs = 28; } ); @@ -222,13 +213,13 @@ security = { log_config : { - global_log_level ="info"; - hw_log_level ="info"; - phy_log_level ="info"; - mac_log_level ="info"; - rlc_log_level ="info"; - pdcp_log_level ="info"; - rrc_log_level ="info"; - ngap_log_level ="debug"; - f1ap_log_level ="debug"; + global_log_level ="info"; + hw_log_level ="info"; + phy_log_level ="info"; + mac_log_level ="info"; + rlc_log_level ="info"; + pdcp_log_level ="info"; + rrc_log_level ="info"; + ngap_log_level ="debug"; + f1ap_log_level ="debug"; }; diff --git a/targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb-vnf.sa.band78.273prb.aerial.conf b/targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb-vnf.sa.band78.273prb.aerial.conf index 7b88ad23c4..046db5a780 100644 --- a/targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb-vnf.sa.band78.273prb.aerial.conf +++ b/targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb-vnf.sa.band78.273prb.aerial.conf @@ -3,7 +3,6 @@ Active_gNBs = ( "gNB-OAI"); Asn1_verbosity = "none"; nfapi = "AERIAL"; -pdcp-drop = 1; gNBs = ( @@ -14,49 +13,33 @@ gNBs = // Tracking area code, 0x0000 and 0xfffe are reserved values tracking_area_code = 1; - plmn_list = ({ - mcc = 001; - mnc = 01; - mnc_length = 2; - snssaiList = ( - { - sst = 1; - } - ); - }); + plmn_list = ({ mcc = 208; mnc = 99; mnc_length = 2; snssaiList = ({ sst = 1; }) }); - nr_cellid = 51L; + nr_cellid = 12345678L; ////////// Physical parameters: pdsch_AntennaPorts_XP = 2; - #pdsch_AntennaPorts_N1 = 2; #Uncomment for 4 layers + pdsch_AntennaPorts_N1 = 2; pusch_AntennaPorts = 2; do_CSIRS = 1; - do_SRS = 0; - min_rxtxtime = 3; + do_SRS = 1; + min_rxtxtime = 2; servingCellConfigCommon = ( { #spCellConfigCommon - physCellId = 51; + physCellId = 0; # downlinkConfigCommon #frequencyInfoDL - # this is 3300.24 + 134*12*30e3 = 3348.48 MHz (5G NR GSCN: 7741) - absoluteFrequencySSB = 649920; - #652860; #should be 649920 -#647520; -#647540; -#649920; -#650208; -#647540; - dl_frequencyBand = 78; - # this is 3300.24 MHz - dl_absoluteFrequencyPointA = 646724; -#649104; -#646724; + # center frequency = 3350.01 MHz + # selected SSB frequency = 3349.92 MHz + absoluteFrequencySSB = 653376; + dl_frequencyBand = 77; + # frequency point A = 3300.87 MHz + dl_absoluteFrequencyPointA = 650056; #scs-SpecificCarrierList dl_offstToCarrier = 0; # subcarrierSpacing @@ -77,7 +60,7 @@ gNBs = #uplinkConfigCommon #frequencyInfoUL - ul_frequencyBand = 78; + ul_frequencyBand = 77; #scs-SpecificCarrierList ul_offstToCarrier = 0; # subcarrierSpacing @@ -157,13 +140,13 @@ gNBs = # pattern1 # dl_UL_TransmissionPeriodicity # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10 - dl_UL_TransmissionPeriodicity = 6; - nrofDownlinkSlots = 6; - nrofDownlinkSymbols = 10; - nrofUplinkSlots = 3; + dl_UL_TransmissionPeriodicity = 6; #5; + nrofDownlinkSlots = 6; #3; + nrofDownlinkSymbols = 10; #6; + nrofUplinkSlots = 3; #1; nrofUplinkSymbols = 0; - ssPBCH_BlockPower = -34; + ssPBCH_BlockPower = -15; } ); @@ -179,12 +162,13 @@ gNBs = ////////// AMF parameters: - amf_ip_address = ({ ipv4 = "192.168.70.132"; }); + amf_ip_address = ({ ipv4 = "172.21.6.5"; }); + NETWORK_INTERFACES : { - GNB_IPV4_ADDRESS_FOR_NG_AMF = "192.168.70.129/24"; - GNB_IPV4_ADDRESS_FOR_NGU = "192.168.70.129/24"; + GNB_IPV4_ADDRESS_FOR_NG_AMF = "172.21.8.120"; + GNB_IPV4_ADDRESS_FOR_NGU = "172.21.8.120"; GNB_PORT_FOR_S1U = 2152; # Spec 2152 }; @@ -193,25 +177,19 @@ gNBs = MACRLCs = ( { - num_cc = 1; - - tr_s_preference = "aerial"; - tr_s_shm_prefix = "nvipc"; - tr_s_poll_core = 10; - remote_s_address = "127.0.0.1"; // pnf addr [!] - local_s_address = "127.0.0.2"; // vnf addr - local_s_portc = 50001; // vnf p5 port - remote_s_portc = 50000; // pnf p5 port [!] - local_s_portd = 50011; // vnf p7 port [!] - remote_s_portd = 50010; // pnf p7 port [!] - - tr_n_preference = "local_RRC"; - pusch_FailureThres = 10; - pusch_TargetSNRx10 = 280; # 150; - pucch_TargetSNRx10 = 100; #200; - ulsch_max_frame_inactivity = 10; - dl_max_mcs = 25; - ul_max_mcs = 25; + num_cc = 1; + remote_s_address = "127.0.0.1"; // pnf addr [!] + local_s_address = "127.0.0.2"; // vnf addr + local_s_portc = 50001; // vnf p5 port + remote_s_portc = 50000; // pnf p5 port [!] + local_s_portd = 50011; // vnf p7 port [!] + remote_s_portd = 50010; // pnf p7 port [!] + tr_s_preference = "aerial"; + tr_n_preference = "local_RRC"; + pusch_TargetSNRx10 = 280; # 150; + pucch_TargetSNRx10 = 200; #200; + dl_max_mcs = 28; + ul_max_mcs = 28; } ); @@ -235,13 +213,13 @@ security = { log_config : { - global_log_level ="info"; - hw_log_level ="info"; - phy_log_level ="info"; - mac_log_level ="info"; - rlc_log_level ="info"; - pdcp_log_level ="info"; - rrc_log_level ="info"; - ngap_log_level ="debug"; - f1ap_log_level ="debug"; + global_log_level ="info"; + hw_log_level ="info"; + phy_log_level ="info"; + mac_log_level ="info"; + rlc_log_level ="info"; + pdcp_log_level ="info"; + rrc_log_level ="info"; + ngap_log_level ="debug"; + f1ap_log_level ="debug"; }; From 81eb336addcf142452902cce59a13aea261d29e9 Mon Sep 17 00:00:00 2001 From: Reem Bahsoun Date: Wed, 28 Jan 2026 09:08:31 +0100 Subject: [PATCH 7/7] Add `-l` option to DL throughput tests in the Aerial pipeline --- ci-scripts/xml_files/container_sa_aerial_quectel.xml | 4 ++-- ci-scripts/xml_files/container_sa_aerial_quectel_ul_heavy.xml | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/ci-scripts/xml_files/container_sa_aerial_quectel.xml b/ci-scripts/xml_files/container_sa_aerial_quectel.xml index b5a2e11e50..7282513bb8 100644 --- a/ci-scripts/xml_files/container_sa_aerial_quectel.xml +++ b/ci-scripts/xml_files/container_sa_aerial_quectel.xml @@ -80,7 +80,7 @@ Iperf iperf (DL/UDP/800M)(30 sec)(single-ue profile) - -u -b 800M -t 30 -R + -u -b 800M -t 30 -R -l 1428 oc-cn5g-20897-aerial up2-aerial 25 @@ -101,7 +101,7 @@ Iperf Optional iperf (DL/UDP/1000M)(30 sec)(single-ue profile) true - -u -b 1000M -t 30 -R + -u -b 1000M -t 30 -R -l 1428 oc-cn5g-20897-aerial up2-aerial 25 diff --git a/ci-scripts/xml_files/container_sa_aerial_quectel_ul_heavy.xml b/ci-scripts/xml_files/container_sa_aerial_quectel_ul_heavy.xml index c577236887..8367316e3a 100644 --- a/ci-scripts/xml_files/container_sa_aerial_quectel_ul_heavy.xml +++ b/ci-scripts/xml_files/container_sa_aerial_quectel_ul_heavy.xml @@ -101,7 +101,7 @@ Iperf iperf (DL/UDP/200M)(30 sec)(single-ue profile) - -u -b 200M -t 30 -R + -u -b 200M -t 30 -R -l 1428 oc-cn5g-20897-aerial up2-aerial 25