PBCH working
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@@ -291,18 +291,19 @@ int8_t nr_ue_decode_mib(module_id_t module_id,
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}
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}
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#ifdef DEBUG_MIB
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LOG_I(MAC,"system frame number(6 MSB bits): %d\n", mac->mib->systemFrameNumber.buf[0]);
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LOG_I(MAC,"system frame number(with LSB): %d\n", (int)frame);
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LOG_I(MAC,"subcarrier spacing (0=15or60, 1=30or120): %d\n", (int)mac->mib->subCarrierSpacingCommon);
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LOG_I(MAC,"ssb carrier offset(with MSB): %d\n", (int)ssb_subcarrier_offset);
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LOG_I(MAC,"dmrs type A position (0=pos2,1=pos3): %d\n", (int)mac->mib->dmrs_TypeA_Position);
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LOG_I(MAC,"pdcch config sib1: %d\n", (int)mac->mib->pdcch_ConfigSIB1);
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LOG_I(MAC,"cell barred (0=barred,1=notBarred): %d\n", (int)mac->mib->cellBarred);
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LOG_I(MAC,"intra frequency reselection (0=allowed,1=notAllowed): %d\n", (int)mac->mib->intraFreqReselection);
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LOG_I(MAC,"half frame bit(extra bits): %d\n", (int)half_frame_bit);
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LOG_I(MAC,"ssb index(extra bits): %d\n", (int)ssb_index);
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#endif
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//#ifdef DEBUG_MIB
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LOG_I(MAC,"system frame number(6 MSB bits): %d\n", frame);
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LOG_I(MAC,"Unused bits: %d\n", mac->mib->systemFrameNumber.bits_unused);
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// LOG_I(MAC,"system frame number(with LSB): %d\n", (int)frame);
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// LOG_I(MAC,"subcarrier spacing (0=15or60, 1=30or120): %d\n", (int)mac->mib->subCarrierSpacingCommon);
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// LOG_I(MAC,"ssb carrier offset(with MSB): %d\n", (int)ssb_subcarrier_offset);
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// LOG_I(MAC,"dmrs type A position (0=pos2,1=pos3): %d\n", (int)mac->mib->dmrs_TypeA_Position);
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// LOG_I(MAC,"pdcch config sib1: %d\n", (int)mac->mib->pdcch_ConfigSIB1);
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// LOG_I(MAC,"cell barred (0=barred,1=notBarred): %d\n", (int)mac->mib->cellBarred);
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// LOG_I(MAC,"intra frequency reselection (0=allowed,1=notAllowed): %d\n", (int)mac->mib->intraFreqReselection);
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// LOG_I(MAC,"half frame bit(extra bits): %d\n", (int)half_frame_bit);
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// LOG_I(MAC,"ssb index(extra bits): %d\n", (int)ssb_index);
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// //#endif
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subcarrier_spacing_t scs_ssb = scs_30kHz; // default for
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//const uint32_t scs_index = 0;
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@@ -449,7 +449,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
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// hardcoding dlsch to be in slot 1
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if (!(slot%num_slots_per_tdd)) {
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if(slot==0) {
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*dlsch_in_slot_bitmap = 0x02;
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*dlsch_in_slot_bitmap = 0x04;
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*ulsch_in_slot_bitmap = 0x100;
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}
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else {
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@@ -508,7 +508,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
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nr_schedule_reception_msg3(module_idP, 0, frame, slot);
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} else
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UE_list->fiveG_connected[UE_id] = true;
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//printf("UE connected %d \n",UE_list->fiveG_connected[UE_id]);
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if (get_softmodem_params()->phy_test) {
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// TbD once RACH is available, start ta_timer when UE is connected
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@@ -526,12 +526,12 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
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}
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}
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// This schedules the DCI for Uplink and subsequently PUSCH
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//This schedules the DCI for Uplink and subsequently PUSCH
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if (UE_list->fiveG_connected[UE_id]) {
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int tda = 1; // time domain assignment hardcoded for now
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schedule_fapi_ul_pdu(module_idP, frame, slot, num_slots_per_tdd, nr_ulmix_slots, tda);
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nr_schedule_pusch(module_idP, UE_id, num_slots_per_tdd, nr_ulmix_slots, frame, slot);
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}
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} //Testing DL only
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if (UE_list->fiveG_connected[UE_id] && (is_xlsch_in_slot(*dlsch_in_slot_bitmap,slot%num_slots_per_tdd))) {
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ue_sched_ctl->current_harq_pid = slot % num_slots_per_tdd;
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@@ -570,7 +570,7 @@ void nr_generate_Msg2(module_id_t module_idP,
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if ((ra->Msg2_frame == frameP) && (ra->Msg2_slot == slotP)) {
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nfapi_nr_dl_tti_request_body_t *dl_req = &nr_mac->DL_req[CC_id].dl_tti_request_body;
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nfapi_nr_dl_tti_request_t *dl_req = &nr_mac->DL_req[CC_id];
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nfapi_nr_pdu_t *tx_req = &nr_mac->TX_req[CC_id].pdu_list[nr_mac->TX_req[CC_id].Number_of_PDUs];
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nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
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@@ -251,7 +251,6 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
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int configure_fapi_dl_pdu(int Mod_idP,
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int *CCEIndex,
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nfapi_nr_dl_tti_request_t *dl_tti_req,
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NR_sched_pucch *pucch_sched,
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uint8_t *mcsIndex,
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@@ -592,12 +591,12 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
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NR_sched_pucch *pucch_sched,
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nfapi_nr_dl_tti_pdsch_pdu_rel15_t *dlsch_config){
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LOG_D(MAC, "In nr_schedule_uss_dlsch_phytest frame %d slot %d\n",frameP,slotP);
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int post_padding = 0, ta_len = 0, header_length_total = 0, sdu_length_total = 0, num_sdus = 0;
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int lcid, offset, i, header_length_last, TBS_bytes = 0;
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int UE_id = 0, CC_id = 0;
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int UE_id = 0,CC_id = 0;
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LOG_I(MAC, "In nr_schedule_uss_dlsch_phytest frame %d slot %d DL req sfn %d slot %d\n",frameP,slotP,RC.nrmac[module_idP]->DL_req[CC_id].SFN,RC.nrmac[module_idP]->DL_req[CC_id].Slot);
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gNB_MAC_INST *gNB_mac = RC.nrmac[module_idP];
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//NR_COMMON_channels_t *cc = nr_mac->common_channels;
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//NR_ServingCellConfigCommon_t *scc=cc->ServingCellConfigCommon;
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@@ -621,7 +620,6 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
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ta_len = gNB_mac->ta_len;
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TBS_bytes = configure_fapi_dl_pdu(module_idP,
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CCEIndices,
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dl_tti_req,
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pucch_sched,
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dlsch_config!=NULL ? dlsch_config->mcsIndex : NULL,
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@@ -690,7 +688,8 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
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// fill dlsch_buffer with random data
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for (i = 0; i < TBS_bytes; i++){
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mac_sdus[i] = (unsigned char) (lrand48()&0xff);
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//mac_sdus[i] = (unsigned char) (lrand48()&0xff);
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mac_sdus[i] = (unsigned char) (0x01);//for testing
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//((uint8_t *)gNB_mac->UE_list.DLSCH_pdu[0][0].payload[0])[i] = (unsigned char) (lrand48()&0xff);
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}
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//Sending SDUs with size 1
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@@ -127,7 +127,6 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
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sub_frame_t subframeP);
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int configure_fapi_dl_pdu(int Mod_id,
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int *CCEIndeces,
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nfapi_nr_dl_tti_request_t *dl_tti_req,
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NR_sched_pucch *pucch_sched,
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uint8_t *mcsIndex,
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@@ -1096,6 +1096,14 @@ void handle_nfapi_hi_dci0_hi_pdu(
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nfapi_hi_dci0_request_pdu_t *hi_dci0_config_pdu) {
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}
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void rrc_pdcp_config_req (
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const protocol_ctxt_t *const ctxt_pP,
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const srb_flag_t srb_flagP,
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const uint32_t actionP,
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const rb_id_t rb_idP,
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const uint8_t security_modeP){
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}
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void handle_nfapi_dci_dl_pdu(PHY_VARS_eNB *eNB,
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int frame,
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int subframe,
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@@ -78,10 +78,11 @@ int8_t mac_rrc_nr_data_req(const module_id_t Mod_idP,
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carrier->MIB,
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24);
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LOG_D(NR_RRC,"Encoded MIB for frame %d sfn_msb %d (%p), bits %lu\n",frameP,sfn_msb,carrier->MIB,enc_rval.encoded);
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buffer_pP[0]=carrier->MIB[0];
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buffer_pP[1]=carrier->MIB[1];
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buffer_pP[2]=carrier->MIB[2];
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LOG_D(NR_RRC,"MIB PDU buffer_pP[0]=%x , buffer_pP[1]=%x, buffer_pP[2]=%x\n",buffer_pP[0],buffer_pP[1],buffer_pP[2]);
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LOG_I(NR_RRC,"MIB PDU buffer_pP[0]=%x , buffer_pP[1]=%x, buffer_pP[2]=%x\n",buffer_pP[0],buffer_pP[1],buffer_pP[2]);
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AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %lu)!\n",
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enc_rval.failed_type->name, enc_rval.encoded);
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return(3);
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