Merge remote-tracking branch 'origin/bler_txoptim' into integration_2022_wk05_b
This commit is contained in:
@@ -395,7 +395,9 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
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nr_schedule_ulsch(module_idP, frame, slot);
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// This schedules the DCI for Downlink and PDSCH
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nr_schedule_ue_spec(module_idP, frame, slot);
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start_meas(&gNB->schedule_dlsch);
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nr_schedule_ue_spec(module_idP, frame, slot);
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stop_meas(&gNB->schedule_dlsch);
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nr_schedule_pucch(module_idP, frame, slot);
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@@ -409,7 +409,7 @@ int get_mcs_from_bler(module_id_t mod_id, int CC_id, frame_t frame, sub_frame_t
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/*const int dret3x = stats->dlsch_rounds[3] - bler_stats->dlsch_rounds[3];
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if (dret3x > 0) {
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if there is a third retransmission, decrease MCS for stabilization and
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restart averaging window to stabilize transmission
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restart averaging window to stabilize transmission
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bler_stats->last_frame_slot = now;
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bler_stats->mcs = max(9, bler_stats->mcs - 1);
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memcpy(bler_stats->dlsch_rounds, stats->dlsch_rounds, sizeof(stats->dlsch_rounds));
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@@ -431,7 +431,7 @@ int get_mcs_from_bler(module_id_t mod_id, int CC_id, frame_t frame, sub_frame_t
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int new_mcs = old_mcs;
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// TODO put back this condition when relevant
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/* first ensure that number of 2nd retx is below threshold. If this is the
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* case, use 1st retx to adjust faster
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* case, use 1st retx to adjust faster
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if (bler_stats->rd2_bler > nrmac->dl_rd2_bler_threshold && old_mcs > 6) {
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new_mcs -= 2;
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} else if (bler_stats->rd2_bler < nrmac->dl_rd2_bler_threshold) {*/
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@@ -486,7 +486,8 @@ void nr_store_dlsch_buffer(module_id_t module_id,
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DL_SCH_LCID_DCCH,
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0,
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0);
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if ((sched_ctrl->lcid_mask&(1<<4)) > 0)
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if ((sched_ctrl->lcid_mask&(1<<4)) > 0) {
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start_meas(&RC.nrmac[module_id]->rlc_status_ind);
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sched_ctrl->rlc_status[DL_SCH_LCID_DTCH] = mac_rlc_status_ind(module_id,
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rnti,
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module_id,
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@@ -497,16 +498,17 @@ void nr_store_dlsch_buffer(module_id_t module_id,
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DL_SCH_LCID_DTCH,
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0,
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0);
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if(sched_ctrl->rlc_status[DL_SCH_LCID_DCCH].bytes_in_buffer > 0){
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lcid = DL_SCH_LCID_DCCH;
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}
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else if (sched_ctrl->rlc_status[DL_SCH_LCID_DCCH1].bytes_in_buffer > 0)
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{
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lcid = DL_SCH_LCID_DCCH1;
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}else{
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lcid = DL_SCH_LCID_DTCH;
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}
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stop_meas(&RC.nrmac[module_id]->rlc_status_ind);
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}
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if(sched_ctrl->rlc_status[DL_SCH_LCID_DCCH].bytes_in_buffer > 0){
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lcid = DL_SCH_LCID_DCCH;
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}
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else if (sched_ctrl->rlc_status[DL_SCH_LCID_DCCH1].bytes_in_buffer > 0)
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{
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lcid = DL_SCH_LCID_DCCH1;
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}else{
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lcid = DL_SCH_LCID_DTCH;
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}
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sched_ctrl->num_total_bytes += sched_ctrl->rlc_status[lcid].bytes_in_buffer;
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//later multiplex here. Just select DCCH/SRB before DTCH/DRB
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@@ -1228,6 +1230,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
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// const int lcid = DL_SCH_LCID_DTCH;
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const int lcid = sched_ctrl->lcid_to_schedule;
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int dlsch_total_bytes = 0;
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start_meas(&gNB_mac->rlc_data_req);
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if (sched_ctrl->num_total_bytes > 0) {
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tbs_size_t len = 0;
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while (size > 3) {
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@@ -1241,6 +1244,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
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/* limit requested number of bytes to what preprocessor specified, or
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* such that TBS is full */
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const rlc_buffer_occupancy_t ndata = min(sched_ctrl->rlc_status[lcid].bytes_in_buffer, size);
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len = mac_rlc_data_req(module_id,
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rnti,
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module_id,
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@@ -1301,6 +1305,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
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buf += size;
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dlsch_total_bytes += size;
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}
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stop_meas(&gNB_mac->rlc_data_req);
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// Add padding header and zero rest out if there is space left
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if (size > 0) {
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@@ -1946,7 +1946,7 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP, NR_CellGroupConfig_t *CellG
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add_nr_list(&UE_info->list, UE_id);
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memset(&UE_info->mac_stats[UE_id], 0, sizeof(NR_mac_stats_t));
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set_Y(UE_info->Y[UE_id], rntiP);
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if (CellGroup && CellGroup->spCellConfig && CellGroup->spCellConfig && CellGroup->spCellConfig->spCellConfigDedicated)
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if (CellGroup && CellGroup->spCellConfig && CellGroup->spCellConfig->spCellConfigDedicated)
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compute_csi_bitlen (CellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup, UE_info, UE_id, mod_idP);
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NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
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memset(sched_ctrl, 0, sizeof(*sched_ctrl));
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@@ -1117,7 +1117,7 @@ void handle_nr_uci_pucch_0_1(module_id_t mod_id,
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// tpc (power control) only if we received AckNack or positive SR. For a
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// negative SR, the UE won't have sent anything, and the SNR is not valid
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if (((uci_01->pduBitmap >> 1) & 0x1) || sched_ctrl->SR) {
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if (((uci_01->pduBitmap >> 1) & 0x1) ) {
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if ((uci_01->harq) && (uci_01->harq->harq_confidence_level==0)) sched_ctrl->tpc1 = nr_get_tpc(RC.nrmac[mod_id]->pucch_target_snrx10, uci_01->ul_cqi, 30);
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else sched_ctrl->tpc1 = 3;
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sched_ctrl->pucch_snrx10 = uci_01->ul_cqi * 5 - 640;
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@@ -910,13 +910,22 @@ bool nr_UE_is_to_be_scheduled(module_id_t mod_id, int CC_id, int UE_id, frame_t
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const NR_UE_sched_ctrl_t *sched_ctrl = &nrmac->UE_info.UE_sched_ctrl[UE_id];
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const int last_ul_sched = sched_ctrl->last_ul_frame * n + sched_ctrl->last_ul_slot;
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const NR_TDD_UL_DL_Pattern_t *tdd =
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scc->tdd_UL_DL_ConfigurationCommon ? &scc->tdd_UL_DL_ConfigurationCommon->pattern1 : NULL;
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int num_slots_per_period;
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int tdd_period_len[8] = {500,625,1000,1250,2000,2500,5000,10000};
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if (tdd)
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num_slots_per_period = n*tdd_period_len[tdd->dl_UL_TransmissionPeriodicity]/10000;
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else
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num_slots_per_period = n;
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const int diff = (now - last_ul_sched + 1024 * n) % (1024 * n);
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/* UE is to be scheduled if
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* (1) we think the UE has more bytes awaiting than what we scheduled
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* (2) there is a scheduling request
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* (3) or we did not schedule it in more than 10 frames */
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const bool has_data = sched_ctrl->estimated_ul_buffer > sched_ctrl->sched_ul_bytes;
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const bool high_inactivity = diff >= nrmac->ulsch_max_frame_inactivity * n;
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const bool high_inactivity = diff >= (nrmac->ulsch_max_frame_inactivity>0 ? (nrmac->ulsch_max_frame_inactivity * n) : num_slots_per_period);
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LOG_D(NR_MAC,
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"%4d.%2d UL inactivity %d slots has_data %d SR %d\n",
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frame,
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@@ -128,7 +128,10 @@ void dump_mac_stats(gNB_MAC_INST *gNB, char *output, int strlen, bool reset_rsrp
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}
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}
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}
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print_meas_log(&gNB->eNB_scheduler, "DL & UL scheduling timing stats", NULL, NULL, output+stroff);
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print_meas(&gNB->eNB_scheduler, "DL & UL scheduling timing stats", NULL, NULL);
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print_meas(&gNB->schedule_dlsch,"dlsch scheduler",NULL,NULL);
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print_meas(&gNB->rlc_data_req, "rlc_data_req",NULL,NULL);
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print_meas(&gNB->rlc_status_ind,"rlc_status_ind",NULL,NULL);
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}
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@@ -738,6 +738,10 @@ typedef struct gNB_MAC_INST_s {
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time_stats_t schedule_dlsch_preprocessor;
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/// processing time of eNB DLSCH scheduler
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time_stats_t schedule_dlsch; // include rlc_data_req + MAC header + preprocessor
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/// processing time of rlc_data_req
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time_stats_t rlc_data_req;
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/// processing time of rlc_status_ind
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time_stats_t rlc_status_ind;
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/// processing time of eNB MCH scheduler
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time_stats_t schedule_mch;
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/// processing time of eNB ULSCH reception
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@@ -490,13 +490,11 @@ void NR_UL_indication(NR_UL_IND_t *UL_info) {
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dump_dl(sched_info);
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#endif
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if (ifi->NR_Schedule_response) {
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AssertFatal(ifi->NR_Schedule_response!=NULL,
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"nr_schedule_response is null (mod %d, cc %d)\n",
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module_id,
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CC_id);
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ifi->NR_Schedule_response(sched_info);
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}
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AssertFatal(ifi->NR_Schedule_response!=NULL,
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"nr_schedule_response is null (mod %d, cc %d)\n",
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module_id,
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CC_id);
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ifi->NR_Schedule_response(sched_info);
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LOG_D(NR_PHY,"NR_Schedule_response: SFN SLOT:%d %d dl_pdus:%d\n",
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sched_info->frame,
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@@ -709,7 +709,7 @@ rrc_gNB_generate_defaultRRCReconfiguration(
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DRB_config->pdcp_Config->moreThanOneRLC = NULL;
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DRB_config->pdcp_Config->t_Reordering = calloc(1, sizeof(*DRB_config->pdcp_Config->t_Reordering));
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*DRB_config->pdcp_Config->t_Reordering = NR_PDCP_Config__t_Reordering_ms0;
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*DRB_config->pdcp_Config->t_Reordering = NR_PDCP_Config__t_Reordering_ms100;
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DRB_config->pdcp_Config->ext1 = NULL;
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ASN_SEQUENCE_ADD(&(*DRB_configList)->list, DRB_config);
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@@ -408,7 +408,7 @@ static void SendFrameNR(guint8 radioType, guint8 direction, guint8 rntiType,
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guint8 isPredefinedData, guint8 retx, guint8 crcStatus,
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guint8 oob_event, guint8 oob_event_value,
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uint8_t *pdu_buffer, unsigned int pdu_buffer_size) {
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unsigned char frameBuffer[9000];
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unsigned char frameBuffer[12000];
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unsigned int frameOffset;
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ssize_t bytesSent;
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frameOffset = 0;
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