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Operation of all of the physical simulators are tested and verified + various warning removals

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This commit is contained in:
yilmazt
2019-06-20 21:46:35 +02:00
parent ffebd6b403
commit 680a0c97c7
31 changed files with 293 additions and 552 deletions
Download Patch File Download Diff File Expand all files Collapse all files
openair1/PHY/INIT/nr_init.c
+3 -2
View File
@@ -279,11 +279,12 @@ void phy_config_request(PHY_Config_t *phy_config) {
}*/
void phy_free_nr_gNB(PHY_VARS_gNB *gNB) {
void phy_free_nr_gNB(PHY_VARS_gNB *gNB)
{
//NR_DL_FRAME_PARMS* const fp = &gNB->frame_parms;
//nfapi_nr_config_request_t *cfg = &gNB->gNB_config;
NR_gNB_COMMON *const common_vars = &gNB->common_vars;
NR_gNB_PUSCH **const pusch_vars = gNB->pusch_vars;
//NR_gNB_PUSCH **const pusch_vars = gNB->pusch_vars;
/*LTE_eNB_SRS *const srs_vars = gNB->srs_vars;
LTE_eNB_PRACH *const prach_vars = &gNB->prach_vars;*/
uint32_t ***pdcch_dmrs = gNB->nr_gold_pdcch_dmrs;
openair1/PHY/INIT/nr_init_ue.c
+2 -2
View File
@@ -678,13 +678,13 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue,
int i,j,k,l,slot,symb,q,layer;
int i,j,k,l,slot,symb,q;
int eNB_id;
int th_id;
int n_ssb_crb=(fp->N_RB_DL-20);
int k_ssb=0;
uint32_t ****pusch_dmrs;
int N_n_scid[2] = {0,1}; // [HOTFIX] This is a temporary implementation of scramblingID0 and scramblingID1 which are given by DMRS-UplinkConfig
uint16_t N_n_scid[2] = {0,1}; // [HOTFIX] This is a temporary implementation of scramblingID0 and scramblingID1 which are given by DMRS-UplinkConfig
int n_scid;
abstraction_flag = 0;
fp->nb_antennas_tx = 1;
openair1/PHY/MODULATION/nr_modulation.c
+6 -7
View File
@@ -26,20 +26,19 @@ extern short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT];
void nr_modulation(uint32_t *in,
uint16_t length,
uint16_t mod_order,
int16_t *out) {
int16_t *out)
{
uint16_t offset;
uint16_t order;
int i,j;
uint8_t idx, b_idx;
offset = (mod_order==2)? NR_MOD_TABLE_QPSK_OFFSET : (mod_order==4)? NR_MOD_TABLE_QAM16_OFFSET : \
(mod_order==6)? NR_MOD_TABLE_QAM64_OFFSET: (mod_order==8)? NR_MOD_TABLE_QAM256_OFFSET : 0;
for (i=0; i<length/mod_order; i++) {
for (int i=0; i<length/mod_order; i++)
{
idx = 0;
for (j=0; j<mod_order; j++) {
for (int j=0; j<mod_order; j++)
{
b_idx = (i*mod_order+j)&0x1f;
if (i && (!b_idx))
in++;
openair1/PHY/NR_REFSIG/nr_gold_ue.c
+10 -7
View File
@@ -23,7 +23,6 @@
void nr_gold_pbch(PHY_VARS_NR_UE* ue)
{
unsigned int n, x1, x2;
unsigned int Nid, i_ssb, i_ssb2;
unsigned char Lmax, l, n_hf, N_hf;
@@ -63,9 +62,10 @@ void nr_gold_pbch(PHY_VARS_NR_UE* ue)
}
void nr_gold_pdcch(PHY_VARS_NR_UE* ue,unsigned short n_idDMRS, unsigned short length_dmrs)
void nr_gold_pdcch(PHY_VARS_NR_UE* ue,
unsigned short n_idDMRS,
unsigned short length_dmrs)
{
unsigned char ns,l;
unsigned int n,x1,x2,x2tmp0;
unsigned int nid;
@@ -106,9 +106,11 @@ void nr_gold_pdcch(PHY_VARS_NR_UE* ue,unsigned short n_idDMRS, unsigned short le
}
}
void nr_gold_pdsch(PHY_VARS_NR_UE* ue,unsigned short lbar,unsigned short *n_idDMRS, unsigned short length_dmrs)
void nr_gold_pdsch(PHY_VARS_NR_UE* ue,
unsigned short lbar,
unsigned short *n_idDMRS,
unsigned short length_dmrs)
{
unsigned char ns,l;
unsigned int n,x1,x2,x2tmp0;
int nscid;
@@ -161,9 +163,10 @@ void nr_gold_pdsch(PHY_VARS_NR_UE* ue,unsigned short lbar,unsigned short *n_idDM
}
}
void nr_init_pusch_dmrs(PHY_VARS_NR_UE* ue, uint16_t *N_n_scid, uint8_t n_scid)
void nr_init_pusch_dmrs(PHY_VARS_NR_UE* ue,
uint16_t *N_n_scid,
uint8_t n_scid)
{
uint32_t x1, x2, n;
uint8_t reset, slot, symb, q;
NR_DL_FRAME_PARMS *fp = &ue->frame_parms;
openair1/PHY/NR_REFSIG/refsig_defs_ue.h
+23 -19
View File
@@ -31,38 +31,42 @@
/*!\brief This function generates the NR Gold sequence (38-211, Sec 5.2.1) for the PBCH DMRS.
@param PHY_VARS_NR_UE* ue structure provides configuration, frame parameters and the pointers to the 32 bits sequence storage tables
*/
int nr_pbch_dmrs_rx(int dmrss,unsigned int *nr_gold_pbch, int32_t *output );
int nr_pbch_dmrs_rx(int dmrss,
unsigned int *nr_gold_pbch,
int32_t *output);
/*!\brief This function generates the NR Gold sequence (38-211, Sec 5.2.1) for the PDCCH DMRS.
@param PHY_VARS_NR_UE* ue structure provides configuration, frame parameters and the pointers to the 32 bits sequence storage tables
*/
int nr_pdcch_dmrs_rx(PHY_VARS_NR_UE *ue,
uint8_t eNB_offset,
unsigned int Ns,
unsigned int *nr_gold_pdcch,
int32_t *output,
unsigned short p,
unsigned short nb_rb_corset);
uint8_t eNB_offset,
unsigned int Ns,
unsigned int *nr_gold_pdcch,
int32_t *output,
unsigned short p,
unsigned short nb_rb_corset);
int nr_pdsch_dmrs_rx(PHY_VARS_NR_UE *ue,
unsigned int Ns,
unsigned int *nr_gold_pdsch,
int32_t *output,
unsigned short p,
unsigned char lp,
unsigned short nb_pdsch_rb);
unsigned int Ns,
unsigned int *nr_gold_pdsch,
int32_t *output,
unsigned short p,
unsigned char lp,
unsigned short nb_pdsch_rb);
void nr_gold_pbch(PHY_VARS_NR_UE* ue);
void nr_gold_pdcch(PHY_VARS_NR_UE* ue,
unsigned short n_idDMRS,
unsigned short length_dmrs);
unsigned short n_idDMRS,
unsigned short length_dmrs);
void nr_gold_pdsch(PHY_VARS_NR_UE* ue,
unsigned short lbar,
unsigned short *n_idDMRS,
unsigned short length_dmrs);
unsigned short lbar,
unsigned short *n_idDMRS,
unsigned short length_dmrs);
void nr_init_pusch_dmrs(PHY_VARS_NR_UE* ue, uint16_t *N_n_scid, uint8_t n_scid);
void nr_init_pusch_dmrs(PHY_VARS_NR_UE* ue,
uint16_t *N_n_scid,
uint8_t n_scid);
#endif
openair1/SCHED/ru_procedures.c
+3 -3
View File
@@ -218,11 +218,11 @@ void feptx_ofdm_2thread(RU_t *ru,int frame,int subframe) {
}
void feptx_ofdm(RU_t *ru,int frame,int subframe) {
void feptx_ofdm(RU_t *ru, int frame, int subframe)
{
LTE_DL_FRAME_PARMS *fp=ru->frame_parms;
unsigned int aa,slot_offset, slot_offset_F;
unsigned int aa, slot_offset, slot_offset_F;
int dummy_tx_b[7680*4] __attribute__((aligned(32)));
int i,j, tx_offset;
int slot_sizeF = (fp->ofdm_symbol_size)*
openair1/SCHED_NR/phy_procedures_nr_gNB.c
+28 -9
View File
@@ -206,31 +206,50 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB,
}
void nr_ulsch_procedures(PHY_VARS_gNB *gNB, gNB_L1_rxtx_proc_t *proc, int UE_id, uint8_t harq_pid) {
NR_DL_FRAME_PARMS *frame_parms = &gNB->frame_parms;
void nr_ulsch_procedures(PHY_VARS_gNB *gNB,
gNB_L1_rxtx_proc_t *proc,
int UE_id,
uint8_t harq_pid)
{
NR_DL_FRAME_PARMS *frame_parms = &gNB->frame_parms;
nfapi_nr_ul_config_ulsch_pdu *rel15_ul = &gNB->ulsch[UE_id+1][0]->harq_processes[harq_pid]->ulsch_pdu;
nfapi_nr_ul_config_ulsch_pdu_rel15_t *nfapi_ulsch_pdu_rel15 = &rel15_ul->ulsch_pdu_rel15;
uint8_t ret;
//uint8_t ret;
uint32_t G;
int Nid_cell = 0; // [hna] shouldn't be a local variable (should be signaled)
G = nr_get_G(nfapi_ulsch_pdu_rel15->number_rbs, nfapi_ulsch_pdu_rel15->number_symbols, nfapi_ulsch_pdu_rel15->nb_re_dmrs, nfapi_ulsch_pdu_rel15->length_dmrs, nfapi_ulsch_pdu_rel15->Qm, nfapi_ulsch_pdu_rel15->n_layers);
G = nr_get_G(nfapi_ulsch_pdu_rel15->number_rbs,
nfapi_ulsch_pdu_rel15->number_symbols,
nfapi_ulsch_pdu_rel15->nb_re_dmrs,
nfapi_ulsch_pdu_rel15->length_dmrs,
nfapi_ulsch_pdu_rel15->Qm,
nfapi_ulsch_pdu_rel15->n_layers);
//----------------------------------------------------------
//------------------- ULSCH unscrambling -------------------
//----------------------------------------------------------
nr_ulsch_unscrambling(gNB->pusch_vars[UE_id]->llr, G, 0, Nid_cell, rel15_ul->rnti);
nr_ulsch_unscrambling(gNB->pusch_vars[UE_id]->llr,
G,
0,
Nid_cell,
rel15_ul->rnti);
//----------------------------------------------------------
//--------------------- ULSCH decoding ---------------------
//----------------------------------------------------------
ret = nr_ulsch_decoding(gNB, UE_id, gNB->pusch_vars[UE_id]->llr, frame_parms, proc->frame_rx,
nfapi_ulsch_pdu_rel15->number_symbols, proc->slot_rx, harq_pid, 0);
//ret = nr_ulsch_decoding(gNB,
nr_ulsch_decoding(gNB,
UE_id,
gNB->pusch_vars[UE_id]->llr,
frame_parms,
proc->frame_rx,
nfapi_ulsch_pdu_rel15->number_symbols,
proc->slot_rx,
harq_pid,
0);
// if (ret > ulsch_gNB->max_ldpc_iterations)
// n_errors++;
openair1/SCHED_NR_UE/fapi_nr_ue_l1.c
+2 -3
View File
@@ -40,9 +40,8 @@
#include "PHY/impl_defs_nr.h"
extern PHY_VARS_NR_UE ***PHY_vars_UE_g;
int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){
int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response)
{
/// module id
module_id_t module_id = scheduled_response->module_id;
/// component carrier id
openair1/SCHED_NR_UE/phy_procedures_nr_ue.c
+5 -7
View File
@@ -2463,10 +2463,11 @@ void ue_pucch_procedures(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_
#endif
void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t gNB_id, uint8_t thread_id) {
NR_DL_FRAME_PARMS *frame_parms=&ue->frame_parms;
void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue,
UE_nr_rxtx_proc_t *proc,
uint8_t gNB_id,
uint8_t thread_id)
{
fapi_nr_dci_pdu_rel15_t *ul_dci_pdu;
NR_UE_ULSCH_t *ulsch_ue;
NR_UL_UE_HARQ_t *harq_process_ul_ue;
@@ -2487,7 +2488,6 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t g
harq_pid = 0; //temporary implementation
generate_ue_ulsch_params(ue,
0,
gNB_id,
@@ -2496,7 +2496,6 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t g
ulsch_ue = ue->ulsch[thread_id][gNB_id][0]; // cwd_index = 0
harq_process_ul_ue = ulsch_ue->harq_processes[harq_pid];
TBS = nr_compute_tbs(ul_dci_pdu->mcs, harq_process_ul_ue->nb_rb, ulsch_ue->Nsymb_pusch, ulsch_ue->nb_re_dmrs, ulsch_ue->length_dmrs, ul_dci_pdu->precod_nbr_layers);
//-----------------------------------------------------//
@@ -2524,7 +2523,6 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t g
*/
nr_ue_pusch_common_procedures(ue,
slot_tx,
ul_dci_pdu->precod_nbr_layers,
openair1/SIMULATION/LTE_PHY/dlsim.c
+42 -382
View File
@@ -67,10 +67,9 @@
#include "common/config/config_load_configmodule.h"
#include "PHY/INIT/phy_init.h"
#include "nfapi/oai_integration/vendor_ext.h"
#include "targets/RT/USER/lte-softmodem.h"
void feptx_ofdm(RU_t *ru,int frame,int subframe);
void feptx_prec(RU_t *ru,int frame,int subframe);
void feptx_ofdm(RU_t *ru, int frame, int subframe);
void feptx_prec(RU_t *ru, int frame, int subframe);
double cpuf;
#define inMicroS(a) (((double)(a))/(cpu_freq_GHz*1000.0))
@@ -86,7 +85,29 @@ double t_rx_min = 1000000000; /*!< \brief initial min process time for rx */
int n_tx_dropped = 0; /*!< \brief initial max process time for tx */
int n_rx_dropped = 0; /*!< \brief initial max process time for rx */
THREAD_STRUCT thread_struct;
//THREAD_STRUCT thread_struct;
static THREAD_STRUCT thread_struct;
void set_parallel_conf(char *parallel_conf) {
if(strcmp(parallel_conf,"PARALLEL_SINGLE_THREAD")==0) thread_struct.parallel_conf = PARALLEL_SINGLE_THREAD;
else if(strcmp(parallel_conf,"PARALLEL_RU_L1_SPLIT")==0) thread_struct.parallel_conf = PARALLEL_RU_L1_SPLIT;
else if(strcmp(parallel_conf,"PARALLEL_RU_L1_TRX_SPLIT")==0) thread_struct.parallel_conf = PARALLEL_RU_L1_TRX_SPLIT;
printf("[CONFIG] parallel conf is set to %d\n",thread_struct.parallel_conf);
}
void set_worker_conf(char *worker_conf) {
if(strcmp(worker_conf,"WORKER_DISABLE")==0) thread_struct.worker_conf = WORKER_DISABLE;
else if(strcmp(worker_conf,"WORKER_ENABLE")==0) thread_struct.worker_conf = WORKER_ENABLE;
printf("[CONFIG] worker conf is set to %d\n",thread_struct.worker_conf);
}
PARALLEL_CONF_t get_thread_parallel_conf(void) {
return thread_struct.parallel_conf;
}
WORKER_CONF_t get_thread_worker_conf(void) {
return thread_struct.worker_conf;
}
int emulate_rf = 0;
@@ -294,7 +315,7 @@ fill_dlsch_config(nfapi_dl_config_request_body_t *dl_req,
uint8_t transmission_scheme,
uint8_t number_of_layers,
uint8_t number_of_subbands,
//uint8_t codebook_index,
// uint8_t codebook_index,
uint8_t ue_category_capacity,
uint8_t pa,
uint8_t delta_power_offset_index,
@@ -629,7 +650,7 @@ int main(int argc, char **argv) {
snr0 = 0;
// num_layers = 1;
perfect_ce = 0;
/*static paramdef_t options[] = {
static paramdef_t options[] = {
{ "awgn", "Use AWGN channel and not multipath", PARAMFLAG_BOOL, strptr:NULL, defintval:0, TYPE_INT, 0, NULL, NULL },
{ "Abstx", "Turns on calibration mode for abstraction.", PARAMFLAG_BOOL, iptr:&abstx, defintval:0, TYPE_INT, 0 },
{ "bTDD", "Set the tdd configuration mode",0, iptr:&tdd_config, defintval:3, TYPE_INT, 0 },
@@ -892,371 +913,7 @@ int main(int argc, char **argv) {
exit(0);
if (thread_struct.parallel_conf != PARALLEL_SINGLE_THREAD)
set_worker_conf("WORKER_ENABLE");*/
int c;
while ((c = getopt (argc, argv, "ahdpZDe:Em:n:o:s:f:t:c:g:r:F:x:q:y:z:AM:N:I:i:O:R:S:C:T:b:u:v:w:B:Pl:WXYL:")) != -1) {
switch (c) {
case 'a':
awgn_flag = 1;
channel_model = AWGN;
break;
case 'A':
abstx = 1;
break;
case 'b':
tdd_config=atoi(optarg);
break;
case 'B':
N_RB_DL=atoi(optarg);
break;
case 'c':
num_pdcch_symbols=atoi(optarg);
break;
case 'C':
Nid_cell = atoi(optarg);
break;
case 'd':
dci_flag = 1;
break;
case 'D':
frame_type=TDD;
break;
case 'e':
num_rounds=1;
common_flag = 1;
TPC = atoi(optarg);
break;
case 'E':
threequarter_fs=1;
break;
case 'f':
input_snr_step= atof(optarg);
break;
case 'F':
forgetting_factor = atof(optarg);
break;
case 'i':
input_fd = fopen(optarg,"r");
input_file=1;
dci_flag = 1;
break;
case 'I':
input_trch_fd = fopen(optarg,"r");
input_trch_file=1;
break;
case 'W':
two_thread_flag = 1;
break;
case 'l':
offset_mumimo_llr_drange_fix=atoi(optarg);
break;
case 'm':
mcs1 = atoi(optarg);
break;
case 'M':
mcs2 = atoi(optarg);
break;
case 'O':
test_perf=atoi(optarg);
//print_perf =1;
break;
case 't':
mcs_i = atoi(optarg);
i_mod = get_Qm(mcs_i);
break;
case 'n':
n_frames = atoi(optarg);
break;
case 'o':
rx_sample_offset = atoi(optarg);
break;
case 'r':
DLSCH_RB_ALLOC = atoi(optarg);
rballocset = 1;
break;
case 's':
snr0 = atof(optarg);
break;
case 'w':
snr_int = atof(optarg);
break;
case 'N':
n_ch_rlz= atof(optarg);
break;
case 'p':
extended_prefix_flag=1;
break;
case 'g':
memcpy(channel_model_input,optarg,10);
switch((char)*optarg) {
case 'A':
channel_model=SCM_A;
break;
case 'B':
channel_model=SCM_B;
break;
case 'C':
channel_model=SCM_C;
break;
case 'D':
channel_model=SCM_D;
break;
case 'E':
channel_model=EPA;
break;
case 'F':
channel_model=EVA;
break;
case 'G':
channel_model=ETU;
break;
case 'H':
channel_model=Rayleigh8;
break;
case 'I':
channel_model=Rayleigh1;
break;
case 'J':
channel_model=Rayleigh1_corr;
break;
case 'K':
channel_model=Rayleigh1_anticorr;
break;
case 'L':
channel_model=Rice8;
break;
case 'M':
channel_model=Rice1;
break;
case 'N':
channel_model=AWGN;
break;
default:
printf("Unsupported channel model!\n");
exit(-1);
}
break;
case 'R':
num_rounds=atoi(optarg);
break;
case 'S':
subframe=atoi(optarg);
break;
case 'T':
n_rnti=atoi(optarg);
break;
case 'u':
dual_stream_UE=1;
UE->use_ia_receiver = 1;
if ((n_tx_port!=2) || (transmission_mode!=5)) {
printf("IA receiver only supported for TM5!");
exit(-1);
}
break;
case 'v':
i_mod = atoi(optarg);
if (i_mod!=2 && i_mod!=4 && i_mod!=6) {
printf("Wrong i_mod %d, should be 2,4 or 6\n",i_mod);
exit(-1);
}
break;
case 'P':
print_perf=1;
break;
case 'q':
n_tx_port=atoi(optarg);
if ((n_tx_port==0) || ((n_tx_port>2))) {
printf("Unsupported number of cell specific antennas ports %d\n",n_tx_port);
exit(-1);
}
break;
case 'x':
transmission_mode=atoi(optarg);
if ((transmission_mode!=1) &&
(transmission_mode!=2) &&
(transmission_mode!=3) &&
(transmission_mode!=4) &&
(transmission_mode!=5) &&
(transmission_mode!=6) &&
(transmission_mode!=7)) {
printf("Unsupported transmission mode %d\n",transmission_mode);
exit(-1);
}
if (transmission_mode>1 && transmission_mode<7) {
n_tx_port = 2;
}
break;
case 'y':
n_tx_phy=atoi(optarg);
if (n_tx_phy < n_tx_port) {
printf("n_tx_phy mush not be smaller than n_tx_port");
exit(-1);
}
if ((transmission_mode>1 && transmission_mode<7) && n_tx_port<2) {
printf("n_tx_port must be >1 for transmission_mode %d\n",transmission_mode);
exit(-1);
}
if (transmission_mode==7 && (n_tx_phy!=1 && n_tx_phy!=2 && n_tx_phy!=4 && n_tx_phy!=8 && n_tx_phy!=16 && n_tx_phy!=64 && n_tx_phy!=128)) {
printf("Physical number of antennas not supported for TM7.\n");
exit(-1);
}
break;
break;
case 'X':
xforms=1;
break;
case 'Y':
perfect_ce=1;
break;
case 'z':
n_rx=atoi(optarg);
if ((n_rx==0) || (n_rx>2)) {
printf("Unsupported number of rx antennas %d\n",n_rx);
exit(-1);
}
break;
case 'Z':
dump_table=1;
break;
case 'L':
loglvl = atoi(optarg);
break;
case 'h':
default:
printf("%s -h(elp) -a(wgn on) -d(ci decoding on) -p(extended prefix on) -m mcs1 -M mcs2 -n n_frames -s snr0 -x transmission mode (1,2,5,6,7) -y TXant -z RXant -I trch_file\n",argv[0]);
printf("-h This message\n");
printf("-a Use AWGN channel and not multipath\n");
printf("-c Number of PDCCH symbols\n");
printf("-m MCS1 for TB 1\n");
printf("-M MCS2 for TB 2\n");
printf("-d Transmit the DCI and compute its error statistics\n");
printf("-p Use extended prefix mode\n");
printf("-n Number of frames to simulate\n");
printf("-o Sample offset for receiver\n");
printf("-s Starting SNR, runs from SNR to SNR+%.1fdB in steps of %.1fdB. If n_frames is 1 then just SNR is simulated and MATLAB/OCTAVE output is generated\n", snr_int, snr_step);
printf("-f step size of SNR, default value is 1.\n");
printf("-C cell id\n");
printf("-S subframe\n");
printf("-D use TDD mode\n");
printf("-b TDD config\n");
printf("-B bandwidth configuration (in number of ressource blocks): 6, 25, 50, 100\n");
printf("-r ressource block allocation (see section 7.1.6.3 in 36.213\n");
printf("-g [A:M] Use 3GPP 25.814 SCM-A/B/C/D('A','B','C','D') or 36-101 EPA('E'), EVA ('F'),ETU('G') models (ignores delay spread and Ricean factor), Rayghleigh8 ('H'), Rayleigh1('I'), Rayleigh1_corr('J'), Rayleigh1_anticorr ('K'), Rice8('L'), Rice1('M')\n");
printf("-F forgetting factor (0 new channel every trial, 1 channel constant\n");
printf("-x Transmission mode (1,2,6,7 for the moment)\n");
printf("-q Number of TX antennas ports used in eNB\n");
printf("-y Number of TX antennas used in eNB\n");
printf("-z Number of RX antennas used in UE\n");
printf("-t MCS of interfering UE\n");
printf("-R Number of HARQ rounds (fixed)\n");
printf("-A Turns on calibration mode for abstraction.\n");
printf("-N Determines the number of Channel Realizations in Abstraction mode. Default value is 1. \n");
printf("-O Set the percenatge of effective rate to testbench the modem performance (typically 30 and 70, range 1-100) \n");
printf("-I Input filename for TrCH data (binary)\n");
printf("-u Enables the Interference Aware Receiver for TM5 (default is normal receiver)\n");
exit(1);
break;
}
}
set_parallel_conf("PARALLEL_RU_L1_TRX_SPLIT");
set_worker_conf("WORKER_ENABLE");
set_worker_conf("WORKER_ENABLE");
if (transmission_mode>1) pa=dBm3;
@@ -1272,6 +929,7 @@ int main(int argc, char **argv) {
// however itti will catch all signals, so ctrl-c won't work anymore
// alternatively you can disable ITTI completely in CMakeLists.txt
//itti_init(TASK_MAX, THREAD_MAX, MESSAGES_ID_MAX, tasks_info, messages_info, messages_definition_xml, NULL);
T_stdout = 1;
if (common_flag == 0) {
switch (N_RB_DL) {
@@ -1355,8 +1013,8 @@ int main(int argc, char **argv) {
if ((transmission_mode==1) || (transmission_mode==7)) {
for (aa=0; aa<ru->nb_tx; aa++)
for (re=0; re<ru->frame_parms->ofdm_symbol_size; re++)
ru->beam_weights[0][0][aa][re] = 0x00007fff/eNB->frame_parms.nb_antennas_tx;
for (re=0; re<ru->frame_parms->ofdm_symbol_size; re++)
ru->beam_weights[0][0][aa][re] = 0x00007fff/eNB->frame_parms.nb_antennas_tx;
}
if (transmission_mode<7)
@@ -1632,17 +1290,19 @@ int main(int argc, char **argv) {
UE->dlsch_eNB[0] = new_eNB_dlsch(Kmimo,8,Nsoft,N_RB_DL,0,&eNB->frame_parms);
if (DLSCH_alloc_pdu2_1E[0].tpmi == 5) {
eNB->UE_stats[0].DL_pmi_single = (unsigned short)(taus()&0xffff);
eNB->UE_stats[0].DL_pmi_single = (unsigned short)(taus()&0xffff);
if (n_users>1) eNB->UE_stats[1].DL_pmi_single = (eNB->UE_stats[0].DL_pmi_single ^ 0x1555); //opposite PMI
if (n_users>1)
eNB->UE_stats[1].DL_pmi_single = (eNB->UE_stats[0].DL_pmi_single ^ 0x1555); //opposite PMI
} else {
eNB->UE_stats[0].DL_pmi_single = 0;
eNB->UE_stats[0].DL_pmi_single = 0;
if (n_users>1) eNB->UE_stats[1].DL_pmi_single = 0;
if (n_users>1)
eNB->UE_stats[1].DL_pmi_single = 0;
}
L1_rxtx_proc_t *proc_eNB = &eNB->proc.L1_proc; //&eNB->proc.proc_rxtx[0]; //UE->current_thread_id[subframe]];
proc_eNB->frame_tx = 0;
L1_rxtx_proc_t *proc_eNB = &eNB->proc.L1_proc;
proc_eNB->frame_tx=0;
if (input_fd==NULL) {
DL_req.dl_config_request_body.number_pdcch_ofdm_symbols = num_pdcch_symbols;
@@ -1846,7 +1506,7 @@ int main(int argc, char **argv) {
start_meas(&eNB->ofdm_mod_stats);
ru->proc.tti_tx=subframe;
memcpy((void *)&ru->frame_parms,(void *)&eNB->frame_parms,sizeof(LTE_DL_FRAME_PARMS));
memcpy((void *)ru->frame_parms,(void *)&eNB->frame_parms,sizeof(LTE_DL_FRAME_PARMS));
feptx_prec(ru,proc_eNB->frame_tx,subframe);
feptx_ofdm(ru,proc_eNB->frame_tx,subframe);
stop_meas(&eNB->ofdm_mod_stats);
@@ -1859,8 +1519,8 @@ int main(int argc, char **argv) {
schedule_response(&sched_resp);
phy_procedures_eNB_TX(eNB,proc_eNB,0);
ru->proc.tti_tx=(subframe+1)%10;
feptx_prec(ru,proc_eNB->frame_tx,subframe+1);
feptx_ofdm(ru,proc_eNB->frame_tx,subframe+1);
feptx_prec(ru,proc_eNB->frame_tx,subframe+1);
feptx_ofdm(ru,proc_eNB->frame_tx,subframe+1);
proc_eNB->frame_tx++;
tx_lev = 0;
openair1/SIMULATION/NR_PHY/dlsim.c
+6 -6
View File
@@ -195,7 +195,7 @@ int main(int argc, char **argv)
cpuf = get_cpu_freq_GHz();
if ( load_configmodule(argc,argv,CONFIG_ENABLECMDLINEONLY) == 0 ) {
if ( load_configmodule(argc,argv,CONFIG_ENABLECMDLINEONLY) == 0) {
exit_fun("[SOFTMODEM] Error, configuration module init failed\n");
}
@@ -449,8 +449,8 @@ int main(int argc, char **argv)
gNB2UE = new_channel_desc_scm(n_tx,
n_rx,
channel_model,
fs,
bw,
fs,
bw,
0,
0,
0);
@@ -703,7 +703,7 @@ int main(int argc, char **argv)
for (i=0; i<frame_length_complex_samples; i++) {
for (aa=0; aa<frame_parms->nb_antennas_rx; aa++) {
((short*) UE->common_vars.rxdata[aa])[2*i] = (short) ((r_re[aa][i] + sqrt(sigma2/2)*gaussdouble(0.0,1.0)));
((short*) UE->common_vars.rxdata[aa])[2*i+1] = (short) ((r_im[aa][i] + sqrt(sigma2/2)*gaussdouble(0.0,1.0)));
}
@@ -726,7 +726,7 @@ int main(int argc, char **argv)
UE_proc.frame_rx = frame;
UE_proc.nr_tti_rx= slot;
UE_proc.subframe_rx = slot;
nr_ue_scheduled_response(&UE_mac->scheduled_response);
printf("Running phy procedures UE RX %d.%d\n",frame,slot);
@@ -743,7 +743,7 @@ int main(int argc, char **argv)
if (UE->frame_parms.nb_antennas_rx>1)
LOG_M("rxsigF1.m","rxsF1", UE->common_vars.common_vars_rx_data_per_thread[0].rxdataF[1],slot_length_complex_samples_no_prefix,1,1);
}
if (UE->dci_ind.number_of_dcis==0) n_errors++;
}
} //noise trials
openair1/SIMULATION/NR_PHY/pucchsim.c
+2 -2
View File
@@ -94,7 +94,7 @@ int main(int argc, char **argv)
// int sync_pos, sync_pos_slot;
// FILE *rx_frame_file;
FILE *output_fd = NULL;
uint8_t write_output_file=0;
//uint8_t write_output_file=0;
//int result;
//int freq_offset;
//int subframe_offset;
@@ -144,7 +144,7 @@ int main(int argc, char **argv)
while ((c = getopt (argc, argv, "f:hA:f:g:n:o:s:S:t:x:y:z:N:F:GR:P:IL:")) != -1) {
switch (c) {
case 'f':
write_output_file=1;
//write_output_file=1;
output_fd = fopen(optarg,"w");
if (output_fd==NULL) {
openair1/SIMULATION/NR_PHY/ulschsim.c
+5 -10
View File
@@ -104,7 +104,7 @@ int main(int argc, char **argv) {
char c;
int i,sf;
double SNR, SNR_lin, snr0 = -2.0, snr1 = 2.0;
double SNR, snr0 = -2.0, snr1 = 2.0; //, SNR_lin;
double snr_step = 0.1;
uint8_t snr1set = 0;
FILE *output_fd = NULL;
@@ -123,7 +123,7 @@ int main(int argc, char **argv) {
//unsigned char pbch_phase = 0;
int frame = 0, subframe = 0;
NR_DL_FRAME_PARMS *frame_parms;
double sigma;
//double sigma;
unsigned char qbits = 8;
int ret;
int loglvl = OAILOG_WARNING;
@@ -531,15 +531,10 @@ int main(int argc, char **argv) {
//if (i<16) printf("modulated_input[%d] = %d\n",i,modulated_input[i]);
SNR_lin = pow(10, SNR / 10.0);
sigma = 1.0 / sqrt(2 * SNR_lin);
#if 0
channel_output_fixed[i] = (short) quantize(sigma / 4.0 / 4.0,
modulated_input[i] + sigma * gaussdouble(0.0, 1.0),
qbits);
#else
//SNR_lin = pow(10, SNR / 10.0);
//sigma = 1.0 / sqrt(2 * SNR_lin);
channel_output_fixed[i] = (short) quantize(0.01, modulated_input[i], qbits);
#endif
//channel_output_fixed[i] = (short) quantize(sigma / 4.0 / 4.0, modulated_input[i] + sigma * gaussdouble(0.0, 1.0), qbits);
//channel_output_fixed[i] = (char)quantize8bit(sigma/4.0,(2.0*modulated_input[i]) - 1.0 + sigma*gaussdouble(0.0,1.0));
//printf("channel_output_fixed[%d]: %d\n",i,channel_output_fixed[i]);
openair1/SIMULATION/NR_PHY/ulsim.c
+1 -1
View File
@@ -453,7 +453,7 @@ int main(int argc, char **argv) {
unsigned char harq_pid = 0;
unsigned int TBS = 8424;
unsigned int available_bits;
uint8_t nb_re_dmrs = UE->dmrs_UplinkConfig.pusch_maxLength*(UE->dmrs_UplinkConfig.pusch_dmrs_type == pusch_dmrs_type1)?6:4;
uint8_t nb_re_dmrs = UE->dmrs_UplinkConfig.pusch_maxLength*(UE->dmrs_UplinkConfig.pusch_dmrs_type == pusch_dmrs_type1)?6:4;
uint8_t length_dmrs = 1;
unsigned char mod_order;