harmonization of coreset configuration
This commit is contained in:
@@ -1768,38 +1768,8 @@ void fill_initial_SpCellConfig(int uid,
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bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList = calloc(1,sizeof(*bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList));
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bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList = calloc(1,sizeof(*bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList));
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NR_ControlResourceSet_t *coreset = calloc(1,sizeof(*coreset));
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NR_ControlResourceSet_t *coreset = calloc(1,sizeof(*coreset));
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coreset->controlResourceSetId=1;
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uint64_t bitmap = get_ssb_bitmap(scc);
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// frequency domain resources depends on BWP size
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rrc_coreset_config(coreset, curr_bwp, bitmap);
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// options are 24, 48 or 96
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coreset->frequencyDomainResources.buf = calloc(1,6);
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if (0) {
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int curr_bwp = scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth;
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if (curr_bwp < 48)
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coreset->frequencyDomainResources.buf[0] = 0xf0;
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else
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coreset->frequencyDomainResources.buf[0] = 0xff;
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if (curr_bwp < 96)
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coreset->frequencyDomainResources.buf[1] = 0;
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else
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coreset->frequencyDomainResources.buf[1] = 0xff;
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} else {
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coreset->frequencyDomainResources.buf[0] = 0xf0;
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coreset->frequencyDomainResources.buf[1] = 0;
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}
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coreset->frequencyDomainResources.buf[2] = 0;
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coreset->frequencyDomainResources.buf[3] = 0;
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coreset->frequencyDomainResources.buf[4] = 0;
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coreset->frequencyDomainResources.buf[5] = 0;
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coreset->frequencyDomainResources.size = 6;
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coreset->frequencyDomainResources.bits_unused = 3;
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coreset->duration=1;
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coreset->cce_REG_MappingType.present = NR_ControlResourceSet__cce_REG_MappingType_PR_nonInterleaved;
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coreset->precoderGranularity = NR_ControlResourceSet__precoderGranularity_sameAsREG_bundle;
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coreset->tci_StatesPDCCH_ToAddList=NULL;
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coreset->tci_StatesPDCCH_ToReleaseList = NULL;
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coreset->tci_PresentInDCI = NULL;
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coreset->pdcch_DMRS_ScramblingID = NULL;
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ASN_SEQUENCE_ADD(&bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list,
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ASN_SEQUENCE_ADD(&bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list,
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coreset);
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coreset);
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@@ -1810,7 +1780,7 @@ void fill_initial_SpCellConfig(int uid,
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ss2->searchSpaceId=2;
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ss2->searchSpaceId=2;
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ss2->controlResourceSetId=calloc(1,sizeof(*ss2->controlResourceSetId));
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ss2->controlResourceSetId=calloc(1,sizeof(*ss2->controlResourceSetId));
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*ss2->controlResourceSetId=1;
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*ss2->controlResourceSetId=coreset->controlResourceSetId;
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ss2->monitoringSlotPeriodicityAndOffset=calloc(1,sizeof(*ss2->monitoringSlotPeriodicityAndOffset));
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ss2->monitoringSlotPeriodicityAndOffset=calloc(1,sizeof(*ss2->monitoringSlotPeriodicityAndOffset));
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ss2->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1;
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ss2->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1;
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ss2->monitoringSlotPeriodicityAndOffset->choice.sl1=(NULL_t)0;
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ss2->monitoringSlotPeriodicityAndOffset->choice.sl1=(NULL_t)0;
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@@ -34,6 +34,64 @@
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const uint8_t slotsperframe[5] = {10, 20, 40, 80, 160};
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const uint8_t slotsperframe[5] = {10, 20, 40, 80, 160};
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void rrc_coreset_config(NR_ControlResourceSet_t *coreset,
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int curr_bwp,
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uint64_t ssb_bitmap) {
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// frequency domain resources depends on BWP size
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coreset->frequencyDomainResources.buf = calloc(1,6);
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coreset->frequencyDomainResources.buf[0] = (curr_bwp < 48) ? 0xf0 : 0xff;
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coreset->frequencyDomainResources.buf[1] = (curr_bwp < 96) ? 0x00 : 0xff;
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coreset->frequencyDomainResources.buf[2] = (curr_bwp < 144) ? 0x00 : 0xff;
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coreset->frequencyDomainResources.buf[3] = (curr_bwp < 192) ? 0x00 : 0xff;
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coreset->frequencyDomainResources.buf[4] = 0;
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coreset->frequencyDomainResources.buf[5] = 0;
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coreset->frequencyDomainResources.size = 6;
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coreset->frequencyDomainResources.bits_unused = 3;
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coreset->duration = (curr_bwp < 48) ? 2 : 1;
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coreset->cce_REG_MappingType.present = NR_ControlResourceSet__cce_REG_MappingType_PR_nonInterleaved;
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coreset->precoderGranularity = NR_ControlResourceSet__precoderGranularity_sameAsREG_bundle;
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// The ID space is used across the BWPs of a Serving Cell as per 38.331
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coreset->controlResourceSetId = (coreset->frequencyDomainResources.buf[0] > 0) +
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(coreset->frequencyDomainResources.buf[1] > 0) +
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(coreset->frequencyDomainResources.buf[2] > 0) +
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(coreset->frequencyDomainResources.buf[3] > 0);
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coreset->tci_StatesPDCCH_ToAddList=calloc(1,sizeof(*coreset->tci_StatesPDCCH_ToAddList));
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NR_TCI_StateId_t *tci[64];
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for (int i=0;i<64;i++) {
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if ((ssb_bitmap>>(63-i))&0x01){
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tci[i]=calloc(1,sizeof(*tci[i]));
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*tci[i] = i;
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ASN_SEQUENCE_ADD(&coreset->tci_StatesPDCCH_ToAddList->list,tci[i]);
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}
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}
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coreset->tci_StatesPDCCH_ToReleaseList = NULL;
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coreset->tci_PresentInDCI = NULL;
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coreset->pdcch_DMRS_ScramblingID = NULL;
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}
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uint64_t get_ssb_bitmap(NR_ServingCellConfigCommon_t *scc) {
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uint64_t bitmap=0;
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switch (scc->ssb_PositionsInBurst->present) {
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case 1 :
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bitmap = ((uint64_t) scc->ssb_PositionsInBurst->choice.shortBitmap.buf[0])<<56;
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break;
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case 2 :
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bitmap = ((uint64_t) scc->ssb_PositionsInBurst->choice.mediumBitmap.buf[0])<<56;
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break;
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case 3 :
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for (int i=0; i<8; i++) {
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bitmap |= (((uint64_t) scc->ssb_PositionsInBurst->choice.longBitmap.buf[i])<<((7-i)*8));
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}
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break;
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default:
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AssertFatal(1==0,"SSB bitmap size value %d undefined (allowed values 1,2,3) \n", scc->ssb_PositionsInBurst->present);
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}
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return bitmap;
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}
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void set_csirs_periodicity(NR_NZP_CSI_RS_Resource_t *nzpcsi0, int uid, int nb_slots_per_period) {
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void set_csirs_periodicity(NR_NZP_CSI_RS_Resource_t *nzpcsi0, int uid, int nb_slots_per_period) {
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nzpcsi0->periodicityAndOffset = calloc(1,sizeof(*nzpcsi0->periodicityAndOffset));
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nzpcsi0->periodicityAndOffset = calloc(1,sizeof(*nzpcsi0->periodicityAndOffset));
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@@ -111,6 +111,10 @@ typedef struct physicalcellgroup_s{
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long RNTI_Value[MAX_NUM_CCs];
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long RNTI_Value[MAX_NUM_CCs];
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}physicalcellgroup_t;
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}physicalcellgroup_t;
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uint64_t get_ssb_bitmap(NR_ServingCellConfigCommon_t *scc);
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void rrc_coreset_config(NR_ControlResourceSet_t *coreset,
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int curr_bwp,
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uint64_t ssb_bitmap);
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void nr_rrc_config_dl_tda(struct NR_PDSCH_TimeDomainResourceAllocationList *pdsch_TimeDomainAllocationList,
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void nr_rrc_config_dl_tda(struct NR_PDSCH_TimeDomainResourceAllocationList *pdsch_TimeDomainAllocationList,
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lte_frame_type_t frame_type,
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lte_frame_type_t frame_type,
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NR_TDD_UL_DL_ConfigCommon_t *tdd_UL_DL_ConfigurationCommon,
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NR_TDD_UL_DL_ConfigCommon_t *tdd_UL_DL_ConfigurationCommon,
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@@ -664,22 +664,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
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fix_servingcellconfigdedicated(servingcellconfigdedicated);
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fix_servingcellconfigdedicated(servingcellconfigdedicated);
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uint64_t bitmap=0;
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uint64_t bitmap = get_ssb_bitmap(servingcellconfigcommon);
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switch (servingcellconfigcommon->ssb_PositionsInBurst->present) {
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case 1 :
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bitmap = ((uint64_t) servingcellconfigcommon->ssb_PositionsInBurst->choice.shortBitmap.buf[0])<<56;
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break;
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case 2 :
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bitmap = ((uint64_t) servingcellconfigcommon->ssb_PositionsInBurst->choice.mediumBitmap.buf[0])<<56;
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break;
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case 3 :
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for (int i=0; i<8; i++) {
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bitmap |= (((uint64_t) servingcellconfigcommon->ssb_PositionsInBurst->choice.longBitmap.buf[i])<<((7-i)*8));
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}
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break;
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default:
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AssertFatal(1==0,"SSB bitmap size value %d undefined (allowed values 1,2,3) \n", servingcellconfigcommon->ssb_PositionsInBurst->present);
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}
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memset(secondaryCellGroup,0,sizeof(NR_CellGroupConfig_t));
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memset(secondaryCellGroup,0,sizeof(NR_CellGroupConfig_t));
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secondaryCellGroup->cellGroupId = scg_id;
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secondaryCellGroup->cellGroupId = scg_id;
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