UE add RF board ZC706+AD9371

Conflicts:
	cmake_targets/build_oai
	openair1/PHY/LTE_TRANSPORT/prach.c
	openair1/SCHED/phy_procedures_lte_ue.c
	targets/ARCH/COMMON/common_lib.h
	targets/RT/USER/lte-softmodem.c

cmake_targets/CMakeLists.txt

@@ -484,7 +484,7 @@ include_directories ("${X2AP_DIR}")
 add_list1_option(NB_ANTENNAS_RX "2" "Number of antennas in reception" "1" "2" "4")
 add_list1_option(NB_ANTENNAS_TX "4" "Number of antennas in transmission" "1" "2" "4")
 
-add_list2_option(RF_BOARD "EXMIMO" "RF head type" "None" "EXMIMO" "OAI_USRP" "OAI_BLADERF" "CPRIGW" "OAI_LMSSDR")
+add_list2_option(RF_BOARD "EXMIMO" "RF head type" "None" "EXMIMO" "OAI_USRP" "OAI_BLADERF" "CPRIGW" "OAI_LMSSDR" "OAI_ADRV9371_ZC706")
 
 add_list2_option(TRANSP_PRO "None" "Transport protocol type" "None" "ETHERNET")
 #NOKIA config enhancement
@@ -507,6 +507,11 @@ set (SHLIB_LOADER_SOURCES
 )
 # include RF devices / transport protocols library modules
 ######################################################################
+if (HWLAT)
+  add_definitions(-DHWLAT )
+endif()
+
+
 
 include_directories("${OPENAIR_TARGETS}/ARCH/EXMIMO/USERSPACE/LIB/")
 include_directories ("${OPENAIR_TARGETS}/ARCH/EXMIMO/DEFS/")
@@ -761,6 +766,9 @@ include_directories("${OPENAIR3_DIR}/UDP")
 include_directories("${OPENAIR3_DIR}/GTPV1-U")
 include_directories("${OPENAIR_DIR}/targets/COMMON")
 include_directories("${OPENAIR_DIR}/targets/ARCH/COMMON")
+include_directories("${OPENAIR_DIR}/targets/ARCH/ADRV9371_ZC706/USERSPACE/LIB/")
+include_directories("${OPENAIR_DIR}/targets/ARCH/ADRV9371_ZC706/USERSPACE/libini/")
+include_directories("${OPENAIR_DIR}/targets/ARCH/ADRV9371_ZC706/DEFS/")
 include_directories("${OPENAIR_DIR}/targets/ARCH/EXMIMO/USERSPACE/LIB/")
 include_directories("${OPENAIR_DIR}/targets/ARCH/EXMIMO/DEFS")
 include_directories("${OPENAIR2_DIR}/ENB_APP")
@@ -2063,6 +2071,38 @@ target_link_libraries (lte-softmodem-nos1 pthread m ${CONFIG_LIBRARIES} rt crypt
 target_link_libraries (lte-softmodem-nos1  ${LIB_LMS_LIBRARIES})
 target_link_libraries (lte-softmodem-nos1 ${T_LIB})
 
+
+# lte-hwlat
+###################################################
+add_executable(lte-hwlat
+  ${HW_SOURCE}
+  ${OPENAIR_TARGETS}/RT/USER/lte-hwlat.c
+  ${OPENAIR_TARGETS}/ARCH/COMMON/common_lib.c
+  )
+target_link_libraries (lte-hwlat
+  -Wl,--start-group
+  -Wl,--end-group )
+
+target_link_libraries (lte-hwlat rt pthread m )
+target_link_libraries (lte-hwlat ${CMAKE_DL_LIBS}  )
+target_link_libraries (lte-hwlat ${OPENAIR_TARGETS}/ARCH/ADRV9371_ZC706/slib/libadrv9371_zc706.so )
+
+
+# lte-hwlat-test
+###################################################
+add_executable(lte-hwlat-test
+  ${HW_SOURCE}
+  ${OPENAIR1_DIR}/PHY/TOOLS/time_meas.c
+  ${OPENAIR_TARGETS}/RT/USER/lte-hwlat2.c
+  ${OPENAIR_TARGETS}/ARCH/COMMON/common_lib.c
+  )
+target_link_libraries (lte-hwlat-test
+  -Wl,--start-group
+  -Wl,--end-group )
+
+target_link_libraries (lte-hwlat-test rt pthread m )
+target_link_libraries (lte-hwlat-test ${CMAKE_DL_LIBS}  )
+
 # lte-uesoftmodem is  UE implementation
 #######################################
 
@@ -2379,10 +2419,10 @@ if (${T_TRACER})
         #all "add_executable" definitions (except tests, rb_tool, updatefw)
         lte-softmodem lte-softmodem-nos1 oaisim oaisim_nos1
         dlsim_tm4 dlsim dlsim_tm7 ulsim pbchsim scansim mbmssim
-        pdcchsim pucchsim prachsim syncsim
+        pdcchsim pucchsim prachsim syncsim lte-hwlat
         #all "add_library" definitions
         ITTI RRC_LIB S1AP_LIB S1AP_ENB X2AP_LIB
-        oai_exmimodevif oai_usrpdevif oai_bladerfdevif oai_lmssdrdevif
+        oai_adrv9371_zc706devif oai_exmimodevif oai_usrpdevif oai_bladerfdevif oai_lmssdrdevif
         oai_eth_transpro
         FLPT_MSG ASYNC_IF FLEXRAN_AGENT HASHTABLE MSC UTIL OMG_SUMO SECU_OSA
         SECU_CN SCHED_LIB PHY L2 default_sched remote_sched RAL CN_UTILS

cmake_targets/build_oai

@@ -51,6 +51,7 @@ REL="Rel14"
 HW="None"
 TP="None"
 NOS1=0
+HW_LATENCY=0
 EPC=0
 VERBOSE_COMPILE=0
 CFLAGS_PROCESSOR_USER=""
@@ -104,12 +105,14 @@ Options
    Specify conf_nvram_path (default \"$conf_nvram_path\")
 --UE-gen-nvram [output path]
    Specify gen_nvram_path (default \"$gen_nvram_path\")
+--HWLAT
+    Makes test program for haw latency tests
 -r | --3gpp-release
    default is Rel14,
    Rel8 limits the implementation to 3GPP Release 8 version
    Rel10 limits the implementation to 3GPP Release 10 version
 -w | --hardware
-   EXMIMO, USRP, BLADERF, ETHERNET, LMSSDR, None (Default)
+   EXMIMO, USRP, BLADERF, ETHERNET, LMSSDR, ADRV9371_ZC706, None (Default)
    Adds this RF board support (in external packages installation and in compilation)
 -t | --transport protocol
    ETHERNET , None
@@ -234,13 +237,16 @@ function main() {
             shift 2;;
        -w | --hardware)
             HW="$2" #"${i#*=}"
-            # Use OAI_USRP  as the key word USRP is used inside UHD driver           
+            # Use OAI_USRP  as the key word USRP is used inside UHD driver
-	    if [ "$HW" != "BLADERF" -a  "$HW" != "USRP" -a "$HW" != "LMSSDR" -a  "$HW" != "None" -a  "$HW" != "EXMIMO"  ] ; then 
+	    if [ "$HW" != "BLADERF" -a  "$HW" != "USRP" -a "$HW" != "LMSSDR" -a  "$HW" != "None" -a  "$HW" != "EXMIMO" -a  "$HW" != "ADRV9371_ZC706"  ] ; then 
 		echo_fatal "Unknown HW type $HW will exit..."		
 	    else
 		if [ "$HW" == "USRP" ] ; then 
 		    HW="OAI_USRP"
 		fi 
+		if [ "$HW" == "ADRV9371_ZC706" ] ; then 
+		    HW="OAI_ADRV9371_ZC706"
+		fi 
 		if [ "$HW" == "BLADERF" ] ; then 
 		    HW="OAI_BLADERF"
 		fi
@@ -297,6 +303,14 @@ function main() {
 	    NOS1=1
             echo_info "Will compile without S1 interface"
             shift;;
+       --HWLAT)
+            HWLAT=1
+            echo_info "Will compile hw latency test program"
+            shift;;
+       --HWLAT_TEST)
+            HWLAT_TEST=1
+            echo_info "Will compile hw latency test program"
+            shift;;
        --verbose-compile)
 	    VERBOSE_COMPILE=1
             echo_info "Will compile with verbose instructions"
@@ -397,6 +411,12 @@ function main() {
       fi
   fi
   
+  if [ "$HWLAT" = "1" ] ; then
+      if [ "$HW" = "None" ] ; then
+    echo_info "No radio head has been selected (HW set to $HW)" 
+      fi
+  fi
+
   echo_info "RF HW set to $HW" 
   #Now we set flags to enable deadline scheduler settings
   #By default: USRP: disable, 
@@ -409,6 +429,8 @@ function main() {
         DEADLINE_SCHEDULER_FLAG_USER="False"
      elif [ "$HW" = "OAI_USRP" ] ; then 
         DEADLINE_SCHEDULER_FLAG_USER="False"
+     elif [ "$HW" = "OAI_ADRV9371_ZC706" ] ; then 
+        DEADLINE_SCHEDULER_FLAG_USER="False"
      elif [ "$HW" = "OAI_BLADERF" ] ; then 
         DEADLINE_SCHEDULER_FLAG_USER="False"
      elif [ "$HW" = "OAI_LMSSDR" ] ; then 
@@ -474,6 +496,10 @@ function main() {
         install_usrp_uhd_driver $UHD_IMAGES_DIR
       fi
     fi 
+    if [ "$HW" == "OAI_ADRV9371_ZC706" ] ; then
+      echo_info "\nInstalling packages for ADRV9371_ZC706 support"
+      check_install_libiio_driver
+    fi 
     if [ "$HW" == "OAI_BLADERF" ] ; then
       echo_info "installing packages for BLADERF support"
       check_install_bladerf_driver
@@ -811,9 +837,65 @@ function main() {
                   libtelnetsrv.so $dbin/libtelnetsrv.so
 
   fi  
+  # HWLAT compilation
+  #####################
+  if [ "$HWLAT" = "1" ] ; then
+
+     hwlat_exec=lte-hwlat
+     hwlat_build_dir=lte-hwlat
+     
+     echo_info "Compiling $hwlat_exec ..."
+    
+     [ "$CLEAN" = "1" ] && rm -rf $DIR/lte-hwlat/build 
+     mkdir -p $DIR/$hwlat_build_dir/build
+     cmake_file=$DIR/$hwlat_build_dir/CMakeLists.txt
+     echo "cmake_minimum_required(VERSION 2.8)"   >   $cmake_file
+     echo "set ( CMAKE_BUILD_TYPE $CMAKE_BUILD_TYPE )" >> $cmake_file
+     echo "set ( RF_BOARD \"${HW}\")"               >>  $cmake_file
+     echo 'set ( PACKAGE_NAME "\"lte-hwlat\"")'        >>  $cmake_file
+     echo "set ( DEADLINE_SCHEDULER \"${DEADLINE_SCHEDULER_FLAG_USER}\" )"    >>$cmake_file
+     echo "set ( CPU_AFFINITY \"${CPU_AFFINITY_FLAG_USER}\" )"    >>$cmake_file
+     echo "set ( HWLAT \"${HWLAT}\" )"    >>$cmake_file
+     echo 'include(${CMAKE_CURRENT_SOURCE_DIR}/../CMakeLists.txt)' >> $cmake_file    
+     cd $DIR/$hwlat_build_dir/build
+     cmake ..
+     compilations \
+   lte-hwlat lte-hwlat \
+   lte-hwlat $dbin/lte-hwlat
+
+  fi  
+ 
+  # HWLAT_TEST compilation
+  #####################
+  if [ "$HWLAT_TEST" = "1" ] ; then
+
+     hwlat_test_exec=lte-hwlat-test
+     hwlat_test_build_dir=lte-hwlat-test
+     
+     echo_info "Compiling $hwlat_test_exec ..."
+    
+     [ "$CLEAN" = "1" ] && rm -rf $DIR/lte-hwlat-test/build 
+     mkdir -p $DIR/$hwlat_test_build_dir/build
+     cmake_file=$DIR/$hwlat_test_build_dir/CMakeLists.txt
+     echo "cmake_minimum_required(VERSION 2.8)"   >   $cmake_file
+     echo "set ( CMAKE_BUILD_TYPE $CMAKE_BUILD_TYPE )" >> $cmake_file
+     echo "set ( RF_BOARD \"${HW}\")"               >>  $cmake_file
+     echo 'set ( PACKAGE_NAME "\"lte-hwlat-test\"")'        >>  $cmake_file
+     echo "set ( DEADLINE_SCHEDULER \"${DEADLINE_SCHEDULER_FLAG_USER}\" )"    >>$cmake_file
+     echo "set ( CPU_AFFINITY \"${CPU_AFFINITY_FLAG_USER}\" )"    >>$cmake_file
+     echo "set ( HWLAT \"${HWLAT}\" )"    >>$cmake_file
+     echo 'include(${CMAKE_CURRENT_SOURCE_DIR}/../CMakeLists.txt)' >> $cmake_file    
+     cd $DIR/$hwlat_test_build_dir/build
+     cmake ..
+     compilations \
+   lte-hwlat-test lte-hwlat-test \
+   lte-hwlat-test $dbin/lte-hwlat-test
+
+  fi  
+ 
   # build RF device and transport protocol libraries
   #####################################
-  if [ "$eNB" = "1" -o "$UE" = "1" -o "$gNB" = "1" -o "$nrUE" = "1" ] ; then
+  if [ "$eNB" = "1" -o "$UE" = "1" -o "$gNB" = "1" -o "$nrUE" = "1" - o "$HWLAT" = "1" ] ; then
 
       build_dir=$build_dir
 
@@ -831,6 +913,11 @@ function main() {
 	      ln -sf liboai_exmimodevif.so liboai_device.so
 	      ln -sf $dbin/liboai_exmimodevif.so.$REL $dbin/liboai_device.so
 	      echo_info "liboai_device.so is linked to EXMIMO device library"       
+	  elif [ "$HW" == "OAI_ADRV9371_ZC706" ] ; then
+
+        ln -sf $OPENAIR_DIR/targets/ARCH/ADRV9371_ZC706/slib/libadrv9371_zc706.so liboai_device.so
+
+	      echo_info "liboai_device.so is linked to ADRV9371_ZC706 device library"        
 	  elif [ "$HW" == "OAI_USRP" ] ; then
               compilations \
                   $build_dir oai_usrpdevif \

cmake_targets/tools/build_helper

@@ -242,6 +242,36 @@ install_protobuf_c_from_source(){
     ) >& $protobuf_c_install_log
 }
 
+install_libiio_driver_from_source(){
+    libiio_install_log=$OPENAIR_DIR/cmake_targets/log/libiio_install_log.txt
+    echo_info "\nInstalling LibIIO driver from sources. The log file for LibIIO driver installation is here: $libiio_install_log "
+    (
+     cd /tmp
+     echo "Downloading LibIIO driver"
+     rm -rf /tmp/libiio
+     git clone https://github.com/analogdevicesinc/libiio.git
+     cd libiio
+     git checkout 2016_R2
+     cmake ./
+	 make all
+     $SUDO make install
+    ) >& $libiio_install_log
+}
+
+check_install_libiio_driver(){
+    if [[ "$OS_DISTRO" == "ubuntu" ]]; then
+   		$SUDO apt-get install -y --allow-unauthenticated libxml2
+   		$SUDO apt-get install -y --allow-unauthenticated libxml2-dev
+   		$SUDO apt-get install -y --allow-unauthenticated bison
+   		$SUDO apt-get install -y --allow-unauthenticated flex
+   		$SUDO apt-get install -y --allow-unauthenticated libcdk5-dev
+   		$SUDO apt-get install -y --allow-unauthenticated cmake 
+		$SUDO apt-get install -y --allow-unauthenticated libaio-dev
+		$SUDO apt-get install -y --allow-unauthenticated libavahi-client-dev
+		install_libiio_driver_from_source
+    fi
+}
+
 install_usrp_uhd_driver_from_source(){
     uhd_install_log=$OPENAIR_DIR/cmake_targets/log/uhd_install_log.txt
     echo_info "\nInstalling UHD driver from sources. The log file for UHD driver installation is here: $uhd_install_log "

oaienv

@@ -17,3 +17,6 @@ alias oait='cd $OPENAIR_TARGETS'
 alias oailte='cd $OPENAIR_TARGETS/RT/USER'
 alias oais='cd $OPENAIR_TARGETS/SIMU/USER'
 alias oaiex='cd $OPENAIR_TARGETS/SIMU/EXAMPLES'
+
+export IIOD_REMOTE=192.168.121.32
+

openair1/PHY/LTE_TRANSPORT/dci_tools.c

@@ -8118,6 +8118,9 @@ int generate_ue_ulsch_params_from_dci(void *dci_pdu,
 
   // ulsch->n_DMRS2 = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->cshift;
 
+//printf("Format 0 DCI : ulsch (ue): AbsSubframe  %d.%d nrb %d harq_pid %d round %d mcs %d\n",proc->frame_rx%1024,nr_tti_rx,ulsch->harq_processes[harq_pid]->nb_rb,
+ //       harq_pid,ulsch->harq_processes[harq_pid]->round,ulsch->harq_processes[harq_pid]->mcs);
+
 #ifdef UE_DEBUG_TRACE
 
     LOG_D(PHY,"Format 0 DCI : ulsch (ue): AbsSubframe %d.%d\n",proc->frame_rx%1024,subframe);

openair1/PHY/LTE_TRANSPORT/initial_sync.c

@@ -554,7 +554,7 @@ int initial_sync(PHY_VARS_UE *ue, runmode_t mode)
 	  ue->frame_parms.nb_antenna_ports_eNB);
 #endif
 
-#if defined(OAI_USRP) || defined(EXMIMO) || defined(OAI_BLADERF) || defined(OAI_LMSSDR)
+#if defined(OAI_USRP) || defined(EXMIMO) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
 #  if DISABLE_LOG_X
     printf("[UE %d] Frame %d Measured Carrier Frequency %.0f Hz (offset %d Hz)\n",
 	  ue->Mod_id,
@@ -618,9 +618,11 @@ int initial_sync(PHY_VARS_UE *ue, runmode_t mode)
 #ifndef OAI_USRP
 #ifndef OAI_BLADERF
 #ifndef OAI_LMSSDR
+#ifndef OAI_ADRV9371_ZC706
   phy_adjust_gain(ue,ue->measurements.rx_power_avg_dB[0],0);
 #endif
 #endif
+#endif
 #endif
 
   }
@@ -629,9 +631,11 @@ int initial_sync(PHY_VARS_UE *ue, runmode_t mode)
 #ifndef OAI_USRP
 #ifndef OAI_BLADERF
 #ifndef OAI_LMSSDR
+#ifndef OAI_ADRV9371_ZC706
   phy_adjust_gain(ue,dB_fixed(ue->measurements.rssi),0);
 #endif
 #endif
+#endif
 #endif
 
   }

openair1/PHY/LTE_TRANSPORT/prach.c

@@ -636,7 +636,7 @@ int32_t generate_prach( PHY_VARS_UE *ue, uint8_t eNB_id, uint8_t subframe, uint1
   int i, prach_len;
   uint16_t first_nonzero_root_idx=0;
 
-#if defined(EXMIMO) || defined(OAI_USRP)
+#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_ADRV9371_ZC706)
   prach_start =  (ue->rx_offset+subframe*ue->frame_parms.samples_per_tti-ue->hw_timing_advance-ue->N_TA_offset);
 #ifdef PRACH_DEBUG
     LOG_I(PHY,"[UE %d] prach_start %d, rx_offset %d, hw_timing_advance %d, N_TA_offset %d\n", ue->Mod_id,
@@ -1042,7 +1042,7 @@ int32_t generate_prach( PHY_VARS_UE *ue, uint8_t eNB_id, uint8_t subframe, uint1
 
   AssertFatal(prach_fmt<4,
 	      "prach_fmt4 not fully implemented" );
-#if defined(EXMIMO) || defined(OAI_USRP)
+#if defined(EXMIMO) || defined(OAI_USRP)  || defined(OAI_ADRV9371_ZC706)
   int j;
   int overflow = prach_start + prach_len - LTE_NUMBER_OF_SUBFRAMES_PER_FRAME*ue->frame_parms.samples_per_tti;
   LOG_I( PHY, "prach_start=%d, overflow=%d\n", prach_start, overflow );

openair1/PHY/LTE_TRANSPORT/print_stats.c

@@ -42,7 +42,7 @@
 #endif
 
 extern int mac_get_rrc_status(uint8_t Mod_id,uint8_t eNB_flag,uint8_t index);
-#if defined(OAI_USRP) || defined(EXMIMO) || defined(OAI_BLADERF) || defined(OAI_LMSSDR)
+#if defined(OAI_USRP) || defined(EXMIMO) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
 #include "common_lib.h"
 extern openair0_config_t openair0_cfg[];
 #endif
@@ -90,10 +90,10 @@ int dump_ue_stats(PHY_VARS_UE *ue, UE_rxtx_proc_t *proc,char* buffer, int length
 #ifdef EXMIMO
     len += sprintf(&buffer[len], "[UE PROC] RX Gain %d dB (LNA %d, vga %d dB)\n",ue->rx_total_gain_dB, openair0_cfg[0].rxg_mode[0],(int)openair0_cfg[0].rx_gain[0]);
 #endif
-#if defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR)
+#if defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
     len += sprintf(&buffer[len], "[UE PROC] RX Gain %d dB\n",ue->rx_total_gain_dB);
 #endif
-#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR)
+#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
     len += sprintf(&buffer[len], "[UE_PROC] Frequency offset %d Hz, estimated carrier frequency %f Hz\n",ue->common_vars.freq_offset,openair0_cfg[0].rx_freq[0]-ue->common_vars.freq_offset);
 #endif
     len += sprintf(&buffer[len], "[UE PROC] UE mode = %s (%d)\n",mode_string[ue->UE_mode[0]],ue->UE_mode[0]);

openair1/SCHED/phy_procedures_lte_ue.c

@@ -76,7 +76,7 @@ extern double cpuf;
 void Msg1_transmitted(module_id_t module_idP,uint8_t CC_id,frame_t frameP, uint8_t eNB_id);
 void Msg3_transmitted(module_id_t module_idP,uint8_t CC_id,frame_t frameP, uint8_t eNB_id);
 
-#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR)
+#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
 extern uint32_t downlink_frequency[MAX_NUM_CCs][4];
 #endif
 
@@ -158,7 +158,7 @@ void dump_dlsch_SI(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t s
   exit(-1);
 }
 
-#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR)
+#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
 //unsigned int gain_table[31] = {100,112,126,141,158,178,200,224,251,282,316,359,398,447,501,562,631,708,794,891,1000,1122,1258,1412,1585,1778,1995,2239,2512,2818,3162};
 /*
   unsigned int get_tx_amp_prach(int power_dBm, int power_max_dBm, int N_RB_UL)
@@ -1202,7 +1202,7 @@ void ulsch_common_procedures(PHY_VARS_UE *ue, UE_rxtx_proc_t *proc, uint8_t empt
   int frame_tx = proc->frame_tx;
   int ulsch_start;
   int overflow=0;
-#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR)
+#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
   int k,l;
   int dummy_tx_buffer[frame_parms->samples_per_tti] __attribute__((aligned(16)));
 #endif
@@ -1213,7 +1213,7 @@ void ulsch_common_procedures(PHY_VARS_UE *ue, UE_rxtx_proc_t *proc, uint8_t empt
 #endif
   nsymb = (frame_parms->Ncp == 0) ? 14 : 12;
 
-#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR)//this is the EXPRESS MIMO case
+#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR)  || defined(OAI_ADRV9371_ZC706)//this is the EXPRESS MIMO case
   ulsch_start = (ue->rx_offset+subframe_tx*frame_parms->samples_per_tti-
          ue->hw_timing_advance-
          ue->timing_advance-
@@ -1231,7 +1231,7 @@ void ulsch_common_procedures(PHY_VARS_UE *ue, UE_rxtx_proc_t *proc, uint8_t empt
   ulsch_start = (frame_parms->samples_per_tti*subframe_tx)-ue->N_TA_offset; //-ue->timing_advance;
 #endif //else EXMIMO
 
-//#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR)
+//#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
   if (empty_subframe)
   {
 //#if 1
@@ -1279,7 +1279,7 @@ void ulsch_common_procedures(PHY_VARS_UE *ue, UE_rxtx_proc_t *proc, uint8_t empt
   for (aa=0; aa<frame_parms->nb_antennas_tx; aa++) {
     if (frame_parms->Ncp == 1)
       PHY_ofdm_mod(&ue->common_vars.txdataF[aa][subframe_tx*nsymb*frame_parms->ofdm_symbol_size],
-#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR)
+#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
        dummy_tx_buffer,
 #else
        &ue->common_vars.txdata[aa][ulsch_start],
@@ -1290,7 +1290,7 @@ void ulsch_common_procedures(PHY_VARS_UE *ue, UE_rxtx_proc_t *proc, uint8_t empt
        CYCLIC_PREFIX);
     else {
       normal_prefix_mod(&ue->common_vars.txdataF[aa][subframe_tx*nsymb*frame_parms->ofdm_symbol_size],
-#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR)
+#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
 			dummy_tx_buffer,
 #else
 			&ue->common_vars.txdata[aa][ulsch_start],
@@ -1308,7 +1308,7 @@ void ulsch_common_procedures(PHY_VARS_UE *ue, UE_rxtx_proc_t *proc, uint8_t empt
 			&ue->frame_parms);
       }
 
-#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR)
+#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
     apply_7_5_kHz(ue,dummy_tx_buffer,0);
     apply_7_5_kHz(ue,dummy_tx_buffer,1);
 #else
@@ -1317,7 +1317,7 @@ void ulsch_common_procedures(PHY_VARS_UE *ue, UE_rxtx_proc_t *proc, uint8_t empt
 #endif
 
 
-#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR)
+#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
     overflow = ulsch_start - 9*frame_parms->samples_per_tti;
 
 
@@ -1822,7 +1822,7 @@ void ue_ulsch_uespec_procedures(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB
       }
       ue->tx_total_RE[subframe_tx] = nb_rb*12;
       
-#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR)
+#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR)  || defined(OAI_ADRV9371_ZC706)
       tx_amp = get_tx_amp(ue->tx_power_dBm[subframe_tx],
 			  ue->tx_power_max_dBm,
 			  ue->frame_parms.N_RB_UL,
@@ -1899,7 +1899,7 @@ void ue_srs_procedures(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uint8
       Po_SRS = ue->tx_power_max_dBm;
     }
 
-#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR)
+#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
     if (ue->mac_enabled==1)
     {
     tx_amp = get_tx_amp(Po_SRS,
@@ -2182,7 +2182,7 @@ void ue_pucch_procedures(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uin
       ue->tx_power_dBm[subframe_tx] = Po_PUCCH;
       ue->tx_total_RE[subframe_tx] = 12;
 
-#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR)
+#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
       tx_amp = get_tx_amp(Po_PUCCH,
               ue->tx_power_max_dBm,
               ue->frame_parms.N_RB_UL,
@@ -2277,7 +2277,7 @@ void ue_pucch_procedures(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uin
       ue->tx_power_dBm[subframe_tx] = Po_PUCCH;
       ue->tx_total_RE[subframe_tx] = 12;
 
-#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR)
+#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
       tx_amp =  get_tx_amp(Po_PUCCH,
               ue->tx_power_max_dBm,
               ue->frame_parms.N_RB_UL,
@@ -2538,9 +2538,11 @@ void ue_measurement_procedures(
 #ifndef OAI_USRP
 #ifndef OAI_BLADERF
 #ifndef OAI_LMSSDR
+#ifndef OAI_ADRV9371_ZC706
     phy_adjust_gain (ue,dB_fixed(ue->measurements.rssi),0);
 #endif
 #endif
+#endif
 #endif
 
     VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GAIN_CONTROL, VCD_FUNCTION_OUT);

openair2/RRC/LITE/rrc_UE.c

@@ -788,7 +788,7 @@ rrc_ue_establish_drb(
                     RADIO_ACCESS_BEARER,Rlc_info_um);
    */
 #ifdef PDCP_USE_NETLINK
-#   if !defined(OAI_NW_DRIVER_TYPE_ETHERNET) && !defined(EXMIMO) && !defined(OAI_USRP) && !defined(OAI_BLADERF) && !defined(ETHERNET) && !defined(LINK_ENB_PDCP_TO_GTPV1U)
+#   if !defined(OAI_NW_DRIVER_TYPE_ETHERNET) && !defined(EXMIMO) && !defined(OAI_USRP) && !defined(OAI_BLADERF) && !defined(ETHERNET) && !defined(LINK_ENB_PDCP_TO_GTPV1U) && !defined(OAI_ADRV9371_ZC706)
   ip_addr_offset3 = 0;
   ip_addr_offset4 = 1;
   LOG_I(OIP,"[UE %d] trying to bring up the OAI interface oai%d, IP 10.0.%d.%d\n", ue_mod_idP, ip_addr_offset3+ue_mod_idP,

openair2/RRC/LITE/rrc_eNB.c

@@ -5401,7 +5401,7 @@ rrc_eNB_process_RRCConnectionReconfigurationComplete(
                 ctxt_pP->module_id, ctxt_pP->frame, (int)DRB_configList->list.array[i]->drb_Identity);
 #if  defined(PDCP_USE_NETLINK) && !defined(LINK_ENB_PDCP_TO_GTPV1U)
           // can mean also IPV6 since ether -> ipv6 autoconf
-#   if !defined(OAI_NW_DRIVER_TYPE_ETHERNET) && !defined(EXMIMO) && !defined(OAI_USRP) && !defined(OAI_BLADERF) && !defined(ETHERNET)
+#   if !defined(OAI_NW_DRIVER_TYPE_ETHERNET) && !defined(EXMIMO) && !defined(OAI_USRP) && !defined(OAI_BLADERF) && !defined(ETHERNET) && !defined(OAI_ADRV9371_ZC706)
           LOG_I(OIP, "[eNB %d] trying to bring up the OAI interface oai%d\n",
                 ctxt_pP->module_id,
                 ctxt_pP->module_id);

targets/ARCH/ADRV9371_ZC706/Makefile

@@ -0,0 +1,63 @@
+#			Creates shared library
+
+CC=			gcc
+CFLAGS+=	-DADRV9371_ZC706 -DHWLAT -O0 -g3 -Wall -fmessage-length=0 -fPIC
+
+DROOT=		./USERSPACE
+DIR=		$(DROOT)/LIB
+
+IFLAGS+=	-I$(DIR)/								\
+			-I$(DROOT)/libini/						\
+			-I../COMMON/							\
+			-I/usr/include/
+
+LDFLAGS+=	-L/usr/lib/x86/64-linux-gnu/			\
+			-lm -liio -ldl -lriffa
+
+OUTDIR=		./slib
+TARGET=		libadrv9371_zc706.so
+
+SRC=		$(DIR)/adrv9371_dump.c					\
+			$(DIR)/adrv9371_helper.c				\
+			$(DIR)/adrv9371_self_test.c				\
+			$(DIR)/adrv9371_zc706_lib.c				\
+			$(DIR)/adrv9371_zc706_riffa_lib.c		\
+			$(DIR)/adrv9371_zc706_stats.c			\
+			$(DIR)/hw_init.c			\
+			$(DROOT)/libini/libini.c
+
+OBJ=		$(OUTDIR)/adrv9371_dump.o				\
+			$(OUTDIR)/adrv9371_helper.o				\
+			$(OUTDIR)/adrv9371_self_test.o			\
+			$(OUTDIR)/adrv9371_zc706_lib.o			\
+			$(OUTDIR)/adrv9371_zc706_riffa_lib.o	\
+			$(OUTDIR)/adrv9371_zc706_stats.o		\
+			$(OUTDIR)/hw_init.o		\
+			$(OUTDIR)/libini.o
+
+all:	lib
+
+dir:
+	mkdir -p $(OUTDIR)
+
+env:
+	set PATH=/usr/lib/:${PATH}
+
+obj:	dir env
+	$(CC) -c $(CFLAGS) $(IFLAGS) $(SRC) 
+	mv *.o $(OUTDIR)
+
+lib:	dir obj
+	$(CC) -shared $(OBJ) -o $(OUTDIR)/$(TARGET) $(LDFLAGS)
+
+# exec: 	env
+#	$(CC) $(CFLAGS) $(IFLAGS) main.c $(SRC) -o lib.exe $(LDFLAGS) -lpthread
+
+.PHONY:	clean
+
+clean:	
+	rm -f $(OUTDIR)/*.o $(OUTDIR)/*~
+
+rm:		clean
+	rm -f $(OUTDIR)/$(TARGET)
+	rmdir $(OUTDIR)

targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ADRV9371-W_test.ini

@@ -0,0 +1,337 @@
+[IIO Oscilloscope]
+plugin.DMM.detached=0
+plugin.Debug.detached=0
+plugin.AD9371 Advanced.detached=0
+plugin.AD9371.detached=0
+startup_version_check=0
+test=1
+
+[IIO Oscilloscope - Capture Window1]
+fru_connect = 1
+test.message = Please ensure:\n • 30.72 MHz -> REF_CLK_IN (0dBm)\n • Rx1 <-> Tx1\n • Rx2 <-> Tx2
+domain=fft
+sample_count=400
+fft_size=16384
+fft_avg=8
+fft_pwr_offset=0.000000
+graph_type=Lines
+show_grid=1
+enable_auto_scale=1
+x_axis_min=-67.583626
+x_axis_max=67.576126
+y_axis_min=-130
+y_axis_max=3
+show_capture_options = 1
+
+axi-ad9371-rx-obs-hpc.expanded=1
+axi-ad9371-rx-obs-hpc.active=0
+axi-ad9371-rx-obs-hpc.trigger_enabled=0
+axi-ad9371-rx-obs-hpc.voltage0_i.enabled=0
+axi-ad9371-rx-obs-hpc.voltage0_q.enabled=0
+
+axi-ad9371-rx-hpc.expanded=1
+axi-ad9371-rx-hpc.active=1
+axi-ad9371-rx-hpc.voltage0_i.enabled=1
+axi-ad9371-rx-hpc.voltage0_q.enabled=1
+axi-ad9371-rx-hpc.voltage1_i.enabled=0
+axi-ad9371-rx-hpc.voltage1_q.enabled=0
+
+marker_type = Single Tone Markers
+marker.0 = 9525
+marker.1 = 8192
+marker.2 = 10859
+marker.3 = 12193
+marker.4 = 13526
+marker.5 = 14859
+capture_started=0
+
+[DMM]
+device_list = ad7291 0
+device_list = ad9371-phy 0
+device_list = xadc 0
+running = No
+
+# temp between 20C and 55C (in 0.25C units)
+test.ad7291.in_temp0_raw.int = 80 220
+
+# See the production testing wiki docs [1] for how these values are calculated.
+# [1]: (https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/testing#voltage)
+
+# scale = 0.610351562
+# All nominal voltages +/- 2.5%
+
+# 0 INPUT_VOLTAGE 12V - V(Drop Diode) 56/10
+test.ad7291.in_voltage0_raw.int = 2710 2850
+
+# 1 VOUT2_1V3_DIG 1
+test.ad7291.in_voltage1_raw.int = 2077 2183
+
+# 2 VDD_IF 10/10
+test.ad7291.in_voltage2_raw.int = 1997 2099
+
+# 3 VOUT3_3V3 10/10
+test.ad7291.in_voltage3_raw.int = 2636 2770
+
+# 5 VOUT4_1V8  1
+test.ad7291.in_voltage5_raw.int = 2875 3023
+
+# 7 VOUT1_1V3_ANLG 1
+test.ad7291.in_voltage7_raw.int = 2077 2183
+
+
+# Test AD9528 lock status - Requires 30.720 MHz reference clock!
+test.ad9528-1.pll1_reference_clk_a_present.int = 1 1
+test.ad9528-1.pll1_locked.int = 1 1
+test.ad9528-1.pll2_locked.int = 1 1
+
+
+[AD9371]
+ad9371-phy.in_voltage2_rf_port_select = INTERNALCALS
+ad9371-phy.in_voltage2_temp_comp_gain = 0.00 dB
+ad9371-phy.out_altvoltage1_TX_LO_frequency = 2500000000
+ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = 2600000000
+ad9371-phy.out_voltage1_hardwaregain = -10.000000 dB
+ad9371-phy.out_voltage1_lo_leakage_tracking_en = 1
+ad9371-phy.out_voltage1_quadrature_tracking_en = 1
+ad9371-phy.in_voltage0_gain_control_mode = automatic
+ad9371-phy.in_voltage0_quadrature_tracking_en = 1
+ad9371-phy.in_voltage0_temp_comp_gain = 0.00 dB
+ad9371-phy.in_voltage1_quadrature_tracking_en = 1
+ad9371-phy.in_voltage1_temp_comp_gain = 0.00 dB
+ad9371-phy.in_voltage1_gain_control_mode = automatic
+ad9371-phy.out_altvoltage0_RX_LO_frequency = 2600000000
+ad9371-phy.out_voltage0_lo_leakage_tracking_en = 1
+ad9371-phy.out_voltage0_hardwaregain = -10.000000 dB
+ad9371-phy.out_voltage0_quadrature_tracking_en = 1
+ad9371-phy.ensm_mode = radio_on
+axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_phase = 90000
+axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_scale = 0.251160
+axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_frequency = 10001402
+axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_phase = 90000
+axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_scale = 0.000000
+axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_frequency = 1001265
+axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_frequency = 10001402
+axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_phase = 90000
+axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_scale = 0.251160
+axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_frequency = 10001402
+axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_phase = 0
+axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_scale = 0.251160
+axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_phase = 0
+axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_scale = 0.000000
+axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_frequency = 40001860
+axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_phase = 0
+axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_scale = 0.000000
+axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_frequency = 1001265
+axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_phase = 0
+axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_scale = 0.251160
+axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_frequency = 10001402
+axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_frequency = 40001860
+axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_phase = 90000
+axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_scale = 0.000000
+dds_mode_tx1 = 0
+dds_mode_tx2 = 0
+SYNC_RELOAD = 1
+
+# test receiver at 1GHz to 5 GHz
+# SEQ FIRST INCREMENT LAST
+<SEQ> i 1000000000 5000000000 5000000000
+
+[IIO Oscilloscope - Capture Window1]
+# wait for device to settle
+marker_type = Peak Markers
+capture_started = 0
+cycle = 1000
+axi-ad9371-rx-hpc.voltage0_i.enabled=1
+axi-ad9371-rx-hpc.voltage0_q.enabled=1
+axi-ad9371-rx-hpc.voltage1_i.enabled=0
+axi-ad9371-rx-hpc.voltage1_q.enabled=0
+cycle = 1000
+
+[AD9371]
+ad9371-phy.out_altvoltage1_TX_LO_frequency = <i>
+ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = {{<i>} + {100000000}}
+ad9371-phy.out_altvoltage0_RX_LO_frequency = {{<i>} + {100000000}}
+dds_mode_tx1 = 0
+dds_mode_tx2 = 0
+SYNC_RELOAD = 1
+
+[IIO Oscilloscope - Capture Window1]
+# wait for device to settle
+capture_started = 1
+cycle = 3000
+
+[AD9371]
+# channels should be off, so RSSI should be low
+test.ad9371-phy.in_voltage0_rssi.int = 44 45
+test.ad9371-phy.in_voltage1_rssi.int = 44 45
+
+# and gain is high
+test.ad9371-phy.in_voltage0_hardwaregain.double = 30.0 31.0
+test.ad9371-phy.in_voltage0_hardwaregain.double = 30.0 31.0
+
+# set Tx and Rx to be the same
+ad9371-phy.out_altvoltage0_RX_LO_frequency = <i>
+dds_mode_tx1 = 1
+dds_mode_tx2 = 1
+SYNC_RELOAD = 1
+
+[IIO Oscilloscope - Capture Window1]
+# wait for device to settle
+marker_type = Single Tone Markers
+cycle = 3000
+
+[AD9371]
+
+ad9371-phy.out_voltage0_hardwaregain = 0.000000 dB
+ad9371-phy.out_voltage1_hardwaregain = 0.000000 dB
+
+# channels should be on, so RSSI should be high
+test.ad9371-phy.in_voltage0_rssi.int = 3 12
+test.ad9371-phy.in_voltage1_rssi.int = 3 12
+
+# and gain is low
+test.ad9371-phy.in_voltage0_hardwaregain.double = 15.0 29.0
+test.ad9371-phy.in_voltage0_hardwaregain.double = 15.0 29.0
+
+
+
+[IIO Oscilloscope - Capture Window1]
+cycle = 1000
+capture_started = 1
+cycle = 3000
+save_png = ADRV9371_rx1_<i>.png
+save_markers = markers.log
+
+#look at the markers - Fundamental
+test.marker.0 = -12.0 -4.0
+# DC
+test.marker.1 = -100.0 -60.0
+# 2st Harmonic
+test.marker.2 = -110.0 -75.0
+# 3nd Harmonic
+test.marker.3 = -110.0 -75.0
+# 4th Harmonic
+test.marker.4 = -110.0 -75.0
+# 4th Harmonic
+test.marker.5 = -110.0 -65.0
+
+capture_started = 0
+cycle = 1000
+
+axi-ad9371-rx-hpc.voltage0_i.enabled=0
+axi-ad9371-rx-hpc.voltage0_q.enabled=0
+axi-ad9371-rx-hpc.voltage1_i.enabled=1
+axi-ad9371-rx-hpc.voltage1_q.enabled=1
+
+cycle = 1000
+capture_started = 1
+cycle = 3000
+save_png = ADRV9371_rx2_<i>.png
+save_markers = markers.log
+
+#look at the markers - Fundamental
+test.marker.0 = -12.0 -4.0
+# DC
+test.marker.1 = -100.0 -60.0
+# 2st Harmonic
+test.marker.2 = -110.0 -75.0
+# 3nd Harmonic
+test.marker.3 = -110.0 -75.0
+# 4th Harmonic
+test.marker.4 = -110.0 -75.0
+# 4th Harmonic
+test.marker.5 = -110.0 -65.0
+
+</SEQ>
+
+[IIO Oscilloscope - Capture Window1]
+capture_started = 0
+test.message = Please ensure:\n • ORX1 <-> Tx1\n • ORX22 <-> Tx2
+
+axi-ad9371-rx-hpc.expanded=1
+axi-ad9371-rx-hpc.active=0
+axi-ad9371-rx-hpc.voltage0_i.enabled=0
+axi-ad9371-rx-hpc.voltage0_q.enabled=0
+axi-ad9371-rx-hpc.voltage1_i.enabled=0
+axi-ad9371-rx-hpc.voltage1_q.enabled=0
+
+axi-ad9371-rx-obs-hpc.expanded=1
+axi-ad9371-rx-obs-hpc.active=1
+axi-ad9371-rx-obs-hpc.voltage0_i.enabled=1
+axi-ad9371-rx-obs-hpc.voltage0_q.enabled=1
+cycle = 1000
+
+# test observer path at 1GHz to 5 GHz
+# SEQ FIRST INCREMENT LAST
+<SEQ> i 1000000000 1000000000 5000000000
+
+[AD9371]
+# set Tx and Rx to be the same
+ad9371-phy.out_altvoltage1_TX_LO_frequency = <i>
+ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = {{<i>} + {1000000}}
+ad9371-phy.out_altvoltage0_RX_LO_frequency = <i>
+dds_mode_tx1 = 1
+dds_mode_tx2 = 1
+ad9371-phy.out_voltage0_hardwaregain = -10.000000 dB
+ad9371-phy.out_voltage1_hardwaregain = -10.000000 dB
+ad9371-phy.in_voltage2_rf_port_select = ORX1_TX_LO
+ad9371-phy.in_voltage2_gain_control_mode = manual
+ad9371-phy.in_voltage2_hardwaregain = 18.000000 dB
+
+[IIO Oscilloscope - Capture Window1]
+capture_started = 1
+cycle = 3000
+save_png = ADRV9371_ob1_<i>.png
+save_markers = markers.log
+
+#look at the markers - Fundamental
+test.marker.0 = -15.0 -5.0
+# DC
+test.marker.1 = -100.0 -75.0
+# 2st Harmonic
+test.marker.2 = -110.0 -75.0
+# 3nd Harmonic
+test.marker.3 = -110.0 -75.0
+# 4th Harmonic
+test.marker.4 = -110.0 -75.0
+# 4th Harmonic
+test.marker.5 = -110.0 -65.0
+
+[AD9371]
+
+ad9371-phy.in_voltage2_rf_port_select = ORX2_TX_LO
+
+
+[IIO Oscilloscope - Capture Window1]
+cycle = 1000
+capture_started = 1
+cycle = 3000
+save_png = ADRV9371_ob2_<i>.png
+save_markers = markers.log
+
+#look at the markers - Fundamental
+test.marker.0 = -15.0 -4.0
+# DC
+test.marker.1 = -100.0 -75.0
+# 2st Harmonic
+test.marker.2 = -110.0 -75.0
+# 3nd Harmonic
+test.marker.3 = -110.0 -75.0
+# 4th Harmonic
+test.marker.4 = -110.0 -75.0
+# 4th Harmonic
+test.marker.5 = -110.0 -65.0
+
+</SEQ>
+
+[IIO Oscilloscope - Capture Window1]
+test.message = All tests passed - Ship it
+quit = 1

targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile1-osc.ini

@@ -0,0 +1,85 @@
+[AD9371]
+ad9371-phy.in_voltage2_rf_port_select = OFF
+ad9371-phy.in_voltage2_hardwaregain = -156.000000 dB
+ad9371-phy.in_voltage2_temp_comp_gain = 0.00 dB
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.out_voltage0_lo_leakage_tracking_en = 0
+ad9371-phy.out_voltage0_hardwaregain = -10.000000 dB
+ad9371-phy.out_voltage0_quadrature_tracking_en = 1
+ad9371-phy.out_voltage1_hardwaregain = -10.000000 dB
+ad9371-phy.out_voltage1_lo_leakage_tracking_en = 0
+ad9371-phy.out_voltage1_quadrature_tracking_en = 1
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.out_altvoltage1_TX_LO_frequency = 2685000000
+ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = 2565000000
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.in_voltage0_gain_control_mode = automatic
+ad9371-phy.in_voltage0_quadrature_tracking_en = 1
+ad9371-phy.in_voltage0_hardwaregain = 30.000000 dB
+ad9371-phy.in_voltage0_temp_comp_gain = 0.00 dB
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.in_voltage1_quadrature_tracking_en = 1
+ad9371-phy.in_voltage1_hardwaregain = 30.000000 dB
+ad9371-phy.in_voltage1_temp_comp_gain = 0.00 dB
+ad9371-phy.in_voltage1_gain_control_mode = automatic
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.out_altvoltage0_RX_LO_frequency = 2565000000
+ad9371-phy.calibrate_rx_qec_en = 0
+ad9371-phy.calibrate_tx_lol_en = 0
+ad9371-phy.calibrate_vswr_en = 0
+ad9371-phy.calibrate_tx_qec_en = 0
+ad9371-phy.calibrate_clgc_en = 0
+ad9371-phy.ensm_mode = radio_on
+ad9371-phy.calibrate_tx_lol_ext_en = 0
+ad9371-phy.calibrate_dpd_en = 0
+axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_phase = 90000
+axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_scale = 0.501160
+axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_frequency = 1999718
+axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_phase = 90000
+axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_scale = 0.000000
+axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_frequency = 1000327
+axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_frequency = 7999809
+axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_phase = 90000
+axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_scale = 0.251160
+axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_frequency = 7999809
+axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_phase = 0
+axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_scale = 0.251160
+axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_phase = 0
+axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_scale = 0.000000
+axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_frequency = 19998117
+axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_phase = 0
+axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_scale = 0.000000
+axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_frequency = 1000327
+axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_phase = 0
+axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_scale = 0.501160
+axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_frequency = 1999718
+axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_frequency = 19998117
+axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_phase = 90000
+axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_scale = 0.000000
+load_myk_profile_file = /targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile_rx30_Tx60_syr.txt
+dds_mode_tx1 = 1
+dds_mode_tx2 = 1
+dac_buf_filename = /usr/local/lib/osc/waveforms/LTE20.mat
+tx_channel_0 = 1
+tx_channel_1 = 1
+tx_channel_2 = 0
+tx_channel_3 = 0
+global_settings_show = 1
+tx_show = 1
+rx_show = 1
+obs_show = 1
+fpga_show = 1
+
+[ADRV9371_ZC706]
+debug_mode = 0
+interpolation_decimation_factor = 2

targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile_rx30_Tx60_syr.txt

@@ -0,0 +1,285 @@
+<profile AD9371 version=0 name=Rx 20, IQrate 30.720>
+ <clocks>
+  <deviceClock_kHz=122880>
+  <clkPllVcoFreq_kHz=9830400>
+  <clkPllVcoDiv=2>
+  <clkPllHsDiv=4>
+ </clocks>
+
+ <rx>
+  <adcDiv=1>
+  <rxFirDecimation=4>
+  <rxDec5Decimation=5>
+  <enHighRejDec5=1>
+  <rhb1Decimation=2>
+  <iqRate_kHz=30720>
+  <rfBandwidth_Hz=20000000>
+  <rxBbf3dBCorner_kHz=20000>
+
+  <filter FIR gain=-6 num=72>
+  0
+  2
+  4
+  3
+  -4
+  -14
+  -21
+  -12
+  17
+  56
+  73
+  39
+  -53
+  -159
+  -198
+  -101
+  129
+  377
+  457
+  229
+  -274
+  -793
+  -951
+  -482
+  527
+  1564
+  1899
+  1011
+  -978
+  -3154
+  -4109
+  -2611
+  1669
+  7795
+  13807
+  17524
+  17524
+  13807
+  7795
+  1669
+  -2611
+  -4109
+  -3154
+  -978
+  1011
+  1899
+  1564
+  527
+  -482
+  -951
+  -793
+  -274
+  229
+  457
+  377
+  129
+  -101
+  -198
+  -159
+  -53
+  39
+  73
+  56
+  17
+  -12
+  -21
+  -14
+  -4
+  3
+  4
+  2
+  0
+  </filter>
+
+  <adc-profile num=16>
+  599
+  357
+  201
+  98
+  1280
+  112
+  1505
+  53
+  1331
+  21
+  820
+  40
+  48
+  40
+  23
+  191
+  </adc-profile>
+ </rx>
+
+ <obs>
+  <adcDiv=1>
+  <rxFirDecimation=2>
+  <rxDec5Decimation=5>
+  <enHighRejDec5=1>
+  <rhb1Decimation=2>
+  <iqRate_kHz=61440>
+  <rfBandwidth_Hz=50000000>
+  <rxBbf3dBCorner_kHz=25000>
+
+  <filter FIR gain=0 num=72>
+  0
+  -1
+  1
+  2
+  -2
+  -6
+  6
+  12
+  -13
+  -24
+  25
+  43
+  -45
+  -73
+  77
+  118
+  -124
+  -183
+  193
+  274
+  -289
+  -402
+  423
+  579
+  -607
+  -826
+  866
+  1187
+  -1244
+  -1759
+  1842
+  2818
+  -2970
+  -5815
+  4337
+  18436
+  18436
+  4337
+  -5815
+  -2970
+  2818
+  1842
+  -1759
+  -1244
+  1187
+  866
+  -826
+  -607
+  579
+  423
+  -402
+  -289
+  274
+  193
+  -183
+  -124
+  118
+  77
+  -73
+  -45
+  43
+  25
+  -24
+  -13
+  12
+  6
+  -6
+  -2
+  2
+  1
+  -1
+  0
+  </filter>
+
+  <adc-profile num=16>
+  596
+  358
+  201
+  98
+  1280
+  134
+  1509
+  64
+  1329
+  25
+  818
+  39
+  48
+  40
+  23
+  190
+  </adc-profile>
+
+  <lpbk-adc-profile num=16>
+  599
+  357
+  201
+  98
+  1280
+  112
+  1505
+  53
+  1331
+  21
+  820
+  40
+  48
+  40
+  23
+  191
+  </lpbk-adc-profile>
+ </obs>
+
+ <tx>
+  <dacDiv=2.5>
+  <txFirInterpolation=2>
+  <thb1Interpolation=2>
+  <thb2Interpolation=2>
+  <txInputHbInterpolation=1>
+  <iqRate_kHz=61440>
+  <primarySigBandwidth_Hz=20000000>
+  <rfBandwidth_Hz=50000000>
+  <txDac3dBCorner_kHz=92000>
+  <txBbf3dBCorner_kHz=25000>
+
+  <filter FIR gain=0 num=32>
+  -118
+  -122
+  242
+  240
+  -429
+  -499
+  730
+  900
+  -1154
+  -1615
+  1742
+  2957
+  -2322
+  -5354
+  3885
+  17211
+  17211
+  3885
+  -5354
+  -2322
+  2957
+  1742
+  -1615
+  -1154
+  900
+  730
+  -499
+  -429
+  240
+  242
+  -122
+  -118
+  </filter>
+ </tx>
+</profile>

targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.adrv9371-zc706.ini

@@ -0,0 +1,89 @@
+[AD9371]
+ad9371-phy.in_voltage2_rf_port_select = OFF
+ad9371-phy.in_voltage2_hardwaregain = -156.000000 dB
+ad9371-phy.in_voltage2_temp_comp_gain = 0.00 dB
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.out_voltage0_lo_leakage_tracking_en = 0
+ad9371-phy.out_voltage0_hardwaregain = 0.000000 dB
+ad9371-phy.out_voltage0_quadrature_tracking_en = 1
+ad9371-phy.out_voltage1_hardwaregain = 0.000000 dB
+ad9371-phy.out_voltage1_lo_leakage_tracking_en = 0
+ad9371-phy.out_voltage1_quadrature_tracking_en = 1
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.out_altvoltage1_TX_LO_frequency = 2560000000
+ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = 2680000000
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.in_voltage0_gain_control_mode = manual
+ad9371-phy.in_voltage0_quadrature_tracking_en = 1
+ad9371-phy.in_voltage0_hardwaregain = 25.000000 dB
+ad9371-phy.in_voltage0_temp_comp_gain = 0.00 dB
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.in_voltage1_quadrature_tracking_en = 1
+ad9371-phy.in_voltage1_hardwaregain = 25.000000 dB
+ad9371-phy.in_voltage1_temp_comp_gain = 0.00 dB
+ad9371-phy.in_voltage1_gain_control_mode = manual
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.out_altvoltage0_RX_LO_frequency = 2680000000
+ad9371-phy.calibrate_rx_qec_en = 0
+ad9371-phy.calibrate_tx_lol_en = 0
+ad9371-phy.calibrate_vswr_en = 0
+ad9371-phy.calibrate_tx_qec_en = 0
+ad9371-phy.calibrate_clgc_en = 0
+ad9371-phy.ensm_mode = radio_on
+ad9371-phy.calibrate_tx_lol_ext_en = 0
+ad9371-phy.calibrate_dpd_en = 0
+axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_phase = 90000
+axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_scale = 0.501160
+axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_frequency = 1999718
+axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_phase = 90000
+axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_scale = 0.000000
+axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_frequency = 1000327
+axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_frequency = 7999809
+axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_phase = 90000
+axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_scale = 0.251160
+axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_frequency = 7999809
+axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_phase = 0
+axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_scale = 0.251160
+axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_phase = 0
+axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_scale = 0.000000
+axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_frequency = 19998117
+axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_phase = 0
+axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_scale = 0.000000
+axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_frequency = 1000327
+axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_phase = 0
+axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_scale = 0.501160
+axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_frequency = 1999718
+axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_frequency = 19998117
+axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_phase = 90000
+axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_scale = 0.000000
+load_myk_profile_file = /targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile20MHz.txt
+dds_mode_tx1 = 1
+dds_mode_tx2 = 1
+dac_buf_filename = /usr/local/lib/osc/waveforms/LTE20.mat
+tx_channel_0 = 1
+tx_channel_1 = 1
+tx_channel_2 = 0
+tx_channel_3 = 0
+global_settings_show = 1
+tx_show = 1
+rx_show = 1
+obs_show = 1
+fpga_show = 1
+
+[ADRV9371_ZC706]
+# NO_DEBUG=0; DEBUG=1
+debug_mode = 0
+# 20MHz 40MHz 80MHz=1; 10MHz=2; 5MHz=4
+interpolation_decimation_factor = 1
+# is taken into account only if "ad9371-phy.in_voltage0_gain_control_mode = manual"
+rx_gain_offset = 69

targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.adrv9371-zc706_HWgain15dB.ini

@@ -0,0 +1,89 @@
+[AD9371]
+ad9371-phy.in_voltage2_rf_port_select = OFF
+ad9371-phy.in_voltage2_hardwaregain = -156.000000 dB
+ad9371-phy.in_voltage2_temp_comp_gain = 0.00 dB
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.out_voltage0_lo_leakage_tracking_en = 0
+ad9371-phy.out_voltage0_hardwaregain = 0.000000 dB
+ad9371-phy.out_voltage0_quadrature_tracking_en = 1
+ad9371-phy.out_voltage1_hardwaregain = 0.000000 dB
+ad9371-phy.out_voltage1_lo_leakage_tracking_en = 0
+ad9371-phy.out_voltage1_quadrature_tracking_en = 1
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.out_altvoltage1_TX_LO_frequency = 2560000000
+ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = 2680000000
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.in_voltage0_gain_control_mode = manual
+ad9371-phy.in_voltage0_quadrature_tracking_en = 1
+ad9371-phy.in_voltage0_hardwaregain = 15.000000 dB
+ad9371-phy.in_voltage0_temp_comp_gain = 0.00 dB
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.in_voltage1_quadrature_tracking_en = 1
+ad9371-phy.in_voltage1_hardwaregain = 15.000000 dB
+ad9371-phy.in_voltage1_temp_comp_gain = 0.00 dB
+ad9371-phy.in_voltage1_gain_control_mode = manual
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.out_altvoltage0_RX_LO_frequency = 2680000000
+ad9371-phy.calibrate_rx_qec_en = 0
+ad9371-phy.calibrate_tx_lol_en = 0
+ad9371-phy.calibrate_vswr_en = 0
+ad9371-phy.calibrate_tx_qec_en = 0
+ad9371-phy.calibrate_clgc_en = 0
+ad9371-phy.ensm_mode = radio_on
+ad9371-phy.calibrate_tx_lol_ext_en = 0
+ad9371-phy.calibrate_dpd_en = 0
+axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_phase = 90000
+axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_scale = 0.501160
+axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_frequency = 1999718
+axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_phase = 90000
+axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_scale = 0.000000
+axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_frequency = 1000327
+axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_frequency = 7999809
+axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_phase = 90000
+axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_scale = 0.251160
+axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_frequency = 7999809
+axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_phase = 0
+axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_scale = 0.251160
+axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_phase = 0
+axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_scale = 0.000000
+axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_frequency = 19998117
+axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_phase = 0
+axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_scale = 0.000000
+axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_frequency = 1000327
+axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_phase = 0
+axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_scale = 0.501160
+axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_frequency = 1999718
+axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_frequency = 19998117
+axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_phase = 90000
+axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_scale = 0.000000
+load_myk_profile_file = /targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile20MHz.txt
+dds_mode_tx1 = 1
+dds_mode_tx2 = 1
+dac_buf_filename = /usr/local/lib/osc/waveforms/LTE20.mat
+tx_channel_0 = 1
+tx_channel_1 = 1
+tx_channel_2 = 0
+tx_channel_3 = 0
+global_settings_show = 1
+tx_show = 1
+rx_show = 1
+obs_show = 1
+fpga_show = 1
+
+[ADRV9371_ZC706]
+# NO_DEBUG=0; DEBUG=1
+debug_mode = 0
+# 20MHz 40MHz 80MHz=1; 10MHz=2; 5MHz=4
+interpolation_decimation_factor = 1
+# is taken into account only if "ad9371-phy.in_voltage0_gain_control_mode = manual"
+rx_gain_offset = 30

targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB25.adrv9371-zc706.ini

@@ -0,0 +1,85 @@
+[AD9371]
+ad9371-phy.in_voltage2_rf_port_select = OFF
+ad9371-phy.in_voltage2_hardwaregain = -156.000000 dB
+ad9371-phy.in_voltage2_temp_comp_gain = 0.00 dB
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.out_voltage0_lo_leakage_tracking_en = 0
+ad9371-phy.out_voltage0_hardwaregain = -10.000000 dB
+ad9371-phy.out_voltage0_quadrature_tracking_en = 1
+ad9371-phy.out_voltage1_hardwaregain = -10.000000 dB
+ad9371-phy.out_voltage1_lo_leakage_tracking_en = 0
+ad9371-phy.out_voltage1_quadrature_tracking_en = 1
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.out_altvoltage1_TX_LO_frequency = 2535000000
+ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = 2655000000
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.in_voltage0_gain_control_mode = automatic
+ad9371-phy.in_voltage0_quadrature_tracking_en = 1
+ad9371-phy.in_voltage0_hardwaregain = 30.000000 dB
+ad9371-phy.in_voltage0_temp_comp_gain = 0.00 dB
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.in_voltage1_quadrature_tracking_en = 1
+ad9371-phy.in_voltage1_hardwaregain = 30.000000 dB
+ad9371-phy.in_voltage1_temp_comp_gain = 0.00 dB
+ad9371-phy.in_voltage1_gain_control_mode = automatic
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.out_altvoltage0_RX_LO_frequency = 2655000000
+ad9371-phy.calibrate_rx_qec_en = 0
+ad9371-phy.calibrate_tx_lol_en = 0
+ad9371-phy.calibrate_vswr_en = 0
+ad9371-phy.calibrate_tx_qec_en = 0
+ad9371-phy.calibrate_clgc_en = 0
+ad9371-phy.ensm_mode = radio_on
+ad9371-phy.calibrate_tx_lol_ext_en = 0
+ad9371-phy.calibrate_dpd_en = 0
+axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_phase = 90000
+axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_scale = 0.501160
+axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_frequency = 1999718
+axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_phase = 90000
+axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_scale = 0.000000
+axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_frequency = 1000327
+axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_frequency = 7999809
+axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_phase = 90000
+axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_scale = 0.251160
+axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_frequency = 7999809
+axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_phase = 0
+axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_scale = 0.251160
+axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_phase = 0
+axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_scale = 0.000000
+axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_frequency = 19998117
+axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_phase = 0
+axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_scale = 0.000000
+axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_frequency = 1000327
+axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_phase = 0
+axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_scale = 0.501160
+axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_frequency = 1999718
+axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_frequency = 19998117
+axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_phase = 90000
+axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_scale = 0.000000
+load_myk_profile_file = /targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile_rx30_Tx60_syr.txt
+dds_mode_tx1 = 1
+dds_mode_tx2 = 1
+dac_buf_filename = /usr/local/lib/osc/waveforms/LTE20.mat
+tx_channel_0 = 1
+tx_channel_1 = 1
+tx_channel_2 = 0
+tx_channel_3 = 0
+global_settings_show = 1
+tx_show = 1
+rx_show = 1
+obs_show = 1
+fpga_show = 1
+
+[ADRV9371_ZC706]
+debug_mode = 0
+interpolation_decimation_factor = 4

targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB50.adrv9371-zc706.ini

@@ -0,0 +1,85 @@
+[AD9371]
+ad9371-phy.in_voltage2_rf_port_select = OFF
+ad9371-phy.in_voltage2_hardwaregain = -156.000000 dB
+ad9371-phy.in_voltage2_temp_comp_gain = 0.00 dB
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.out_voltage0_lo_leakage_tracking_en = 0
+ad9371-phy.out_voltage0_hardwaregain = -10.000000 dB
+ad9371-phy.out_voltage0_quadrature_tracking_en = 1
+ad9371-phy.out_voltage1_hardwaregain = -10.000000 dB
+ad9371-phy.out_voltage1_lo_leakage_tracking_en = 0
+ad9371-phy.out_voltage1_quadrature_tracking_en = 1
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.out_altvoltage1_TX_LO_frequency = 2535000000
+ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = 2655000000
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.in_voltage0_gain_control_mode = automatic
+ad9371-phy.in_voltage0_quadrature_tracking_en = 1
+ad9371-phy.in_voltage0_hardwaregain = 30.000000 dB
+ad9371-phy.in_voltage0_temp_comp_gain = 0.00 dB
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.in_voltage1_quadrature_tracking_en = 1
+ad9371-phy.in_voltage1_hardwaregain = 30.000000 dB
+ad9371-phy.in_voltage1_temp_comp_gain = 0.00 dB
+ad9371-phy.in_voltage1_gain_control_mode = automatic
+ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
+ad9371-phy.out_altvoltage0_RX_LO_frequency = 2655000000
+ad9371-phy.calibrate_rx_qec_en = 0
+ad9371-phy.calibrate_tx_lol_en = 0
+ad9371-phy.calibrate_vswr_en = 0
+ad9371-phy.calibrate_tx_qec_en = 0
+ad9371-phy.calibrate_clgc_en = 0
+ad9371-phy.ensm_mode = radio_on
+ad9371-phy.calibrate_tx_lol_ext_en = 0
+ad9371-phy.calibrate_dpd_en = 0
+axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_phase = 90000
+axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_scale = 0.501160
+axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_frequency = 1999718
+axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_phase = 90000
+axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_scale = 0.000000
+axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_frequency = 1000327
+axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_frequency = 7999809
+axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_phase = 90000
+axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_scale = 0.251160
+axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_frequency = 7999809
+axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_phase = 0
+axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_scale = 0.251160
+axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_phase = 0
+axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_scale = 0.000000
+axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_frequency = 19998117
+axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_phase = 0
+axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_scale = 0.000000
+axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_frequency = 1000327
+axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_phase = 0
+axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_scale = 0.501160
+axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_frequency = 1999718
+axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_frequency = 19998117
+axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_raw = 1
+axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_phase = 90000
+axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_scale = 0.000000
+load_myk_profile_file = /targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile_rx30_Tx60_syr.txt
+dds_mode_tx1 = 1
+dds_mode_tx2 = 1
+dac_buf_filename = /usr/local/lib/osc/waveforms/LTE20.mat
+tx_channel_0 = 1
+tx_channel_1 = 1
+tx_channel_2 = 0
+tx_channel_3 = 0
+global_settings_show = 1
+tx_show = 1
+rx_show = 1
+obs_show = 1
+fpga_show = 1
+
+[ADRV9371_ZC706]
+debug_mode = 0
+interpolation_decimation_factor = 2

targets/ARCH/ADRV9371_ZC706/readme.txt

@@ -0,0 +1,17 @@
+Common command line:
+--------------------
+cd /openairinterface5g/
+source oaienv
+
+HWLAT application:
+------------------
+./cmake_targets/build_oai -c -C -w ADRV9371_ZC706 --HWLAT
+./cmake_targets/lte-hwlat/build/lte-hwlat
+
+LTE-SOFTMODEM application:
+--------------------------
+./cmake_targets/build_oai -c --eNB --UE --noS1 -w ADRV9371_ZC706
+sudo su
+source oaienv
+source ./targets/bin/init_nas_nos1 UE
+./cmake_targets/lte_noS1_build_oai/build/lte-softmodem-nos1 -U -C 2680000000 -r100 --ue-scan-carrier --ue-txgain 0 --ue-rxgain 5 -S -A 6 --ue-max-power -25 --phy-test -g 7 --rf-config-file ./targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.adrv9371-zc706_HWgain15dB.ini

targets/ARCH/COMMON/common_lib.c

@@ -60,6 +60,12 @@ case USRP_X300_DEV:
   case NONE_DEV:
     printf("[%s] has not loaded a HW device.\n",((device->host_type == RAU_HOST) ? "RAU": "RRU"));
     break;    
+  case ADRV9371_ZC706_DEV:
+    printf("[%s] has loaded ADRV9371_ZC706 device.\n",((device->host_type == RAU_HOST) ? "RAU": "RRU"));
+    break;
+  case UEDv2_DEV:
+    printf("[%s] has loaded UEDv2 device.\n",((device->host_type == RAU_HOST) ? "RAU": "RRU"));
+    break;
   default:
     printf("[%s] invalid HW device.\n",((device->host_type == RAU_HOST) ? "RAU": "RRU")); 
     return -1;

targets/ARCH/COMMON/common_lib.h

@@ -97,6 +97,10 @@ typedef enum {
   LMSSDR_DEV,
   /*!\brief device is NONE*/
   NONE_DEV,
+  /*!\brief device is ADRV9371_ZC706 */
+  ADRV9371_ZC706_DEV,
+  /*!\brief device is UEDv2 */
+  UEDv2_DEV,
   MAX_RF_DEV_TYPE
 
 } dev_type_t;
@@ -216,6 +220,14 @@ typedef struct {
   unsigned int   sf_write_delay;    // write delay in replay mode
   unsigned int   eth_mtu;           // ethernet MTU
 #endif  
+
+  //! number of samples per tti
+  unsigned int  samples_per_tti;
+  //! the sample rate for receive.
+  double rx_sample_rate;
+  //! the sample rate for transmit.
+  double tx_sample_rate;
+
 } openair0_config_t;
 
 /*! \brief RF mapping */ 

targets/COMMON/openairinterface5g_limits.h

@@ -1,7 +1,7 @@
 #ifndef OPENAIRINTERFACE5G_LIMITS_H_
 #define OPENAIRINTERFACE5G_LIMITS_H_
 
-#if defined(CBMIMO1) || defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_LMSSDR)
+#if defined(CBMIMO1) || defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
 #        define NUMBER_OF_eNB_MAX 1
 #        define NUMBER_OF_RU_MAX 2
 #        define NUMBER_OF_UE_MAX 16

targets/RT/USER/lte-hwlat.c

@@ -0,0 +1,944 @@
+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1  (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ *      contact@openairinterface.org
+ */
+
+#define _GNU_SOURCE
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <string.h>
+#include <sys/ioctl.h>
+#include <sys/types.h>
+#include <sys/mman.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <sched.h>
+#include <linux/sched.h>
+#include <signal.h>
+#include <execinfo.h>
+#include <getopt.h>
+#include <syscall.h>
+#include <sys/sysinfo.h>
+
+#include "assertions.h"
+#include "PHY/types.h"
+
+#include "PHY/defs.h"
+
+#include <sys/time.h>
+#define GET_TIME_INIT(num) struct timeval _timers[num]
+#define GET_TIME_VAL(num) gettimeofday(&_timers[num], NULL)
+#define TIME_VAL_TO_MS(num) (((double)_timers[num].tv_sec*1000.0) + ((double)_timers[num].tv_usec/1000.0))
+
+#undef MALLOC //there are two conflicting definitions, so we better make sure we don't use it at all
+//#undef FRAME_LENGTH_COMPLEX_SAMPLES //there are two conflicting definitions, so we better make sure we don't use it at all
+
+#include "../../ARCH/COMMON/common_lib.h"
+
+#include "PHY/extern.h"
+#include "SCHED/extern.h"
+#include "LAYER2/MAC/extern.h"
+#include "LAYER2/MAC/proto.h"
+
+#define 		RIFFA_CHANNEL_TESTER  0
+#define 		RIFFA_CHANNEL_TESTER2 0
+#define     RIFFA_CHANNEL_DATA1   1
+
+volatile int             oai_exit = 0;
+
+openair0_config_t openair0_cfg[MAX_CARDS];
+
+#if 0
+#define NB_ANTENNAS_RX 4
+
+#define DevAssert(cOND)                     _Assert_(cOND, _Assert_Exit_, "")
+#define malloc16(x) memalign(16,x)
+
+#ifdef 0
+static inline void* malloc16_clear( size_t size )
+{
+#ifdef __AVX2__
+  void* ptr = memalign(32, size);
+#else
+  void* ptr = memalign(16, size);
+#endif
+  if(ptr)
+    memset( ptr, 0, size );
+  return ptr;
+}
+#endif
+
+#endif
+
+typedef struct latency_stat {
+    uint64_t    counter;
+
+    uint64_t    stat250;
+    uint64_t    stat500;
+    uint64_t    stat600;
+    uint64_t    stat700;
+    uint64_t    stat800;
+
+    uint64_t    stat1300;
+    uint64_t    stat1500;
+    uint64_t    stat2000;
+    uint64_t    stat2500;
+    uint64_t    stat3000;
+
+    uint64_t    stat880;
+    uint64_t    stat960;
+    uint64_t    stat1040;
+    uint64_t    stat1120;
+    uint64_t    stat1200;
+} latency_stat_t;
+
+
+typedef struct	timing_stats {
+	char			*name;
+	double			min;
+	double			max;
+	double			total;
+	unsigned int	count;
+} timing_stats_t;
+
+
+//static struct timespec	get_timespec_diff(
+//							struct timespec *start,
+//							struct timespec *stop )
+//{
+//	struct timespec		result;
+//
+//	if ( ( stop->tv_nsec - start->tv_nsec ) < 0 ) {
+//		result.tv_sec = stop->tv_sec - start->tv_sec - 1;
+//		result.tv_nsec = stop->tv_nsec - start->tv_nsec + 1000000000;
+//	}
+//	else {
+//		result.tv_sec = stop->tv_sec - start->tv_sec;
+//		result.tv_nsec = stop->tv_nsec - start->tv_nsec;
+//	}
+//
+//	return result;
+//}
+
+
+//static void 			measure_time (
+//							openair0_device	*rf_device,
+//							struct timespec *start,
+//							struct timespec *stop,
+//							timing_stats_t *stats,
+//							boolean_t START,
+//							uint8_t PRINT_INTERVAL )
+//{
+//	if ( START ) {
+//		clock_gettime( CLOCK_MONOTONIC, start );
+//	}
+//	else {
+//		clock_gettime( CLOCK_MONOTONIC, stop );
+//
+//		struct timespec		diff;
+//		double				current		= 0;
+////		boolean_t			show_stats	= false;
+//
+//		diff 	= get_timespec_diff( start, stop );
+//		current = (double)diff.tv_sec * 1000000 + (double)diff.tv_nsec / 1000;
+//
+//		if ( current > stats->max ) {
+//			stats->max = current;
+////			show_stats = true;
+//		}
+//		if ( stats->min == 0 || current < stats->min ) {
+//			stats->min = current;
+////			show_stats = true;
+//		}
+//		stats->total += current;
+//
+////		if ( show_stats ) {
+////			rf_device.trx_get_stats_func( &rf_device );
+////		}
+//
+////		if ( stats->count % PRINT_INTERVAL == 0 ) {
+////			double			avg	= stats->total / ( stats->count + 1 );
+////			printf( "[%s][%d] Current : %.2lf µs, Min : %.2lf µs, Max : %.2lf µs, Avg : %.2lf µs\n",
+////					stats->count, stats->name, current, stats->min, stats->max, avg );
+////		}
+//
+//		stats->count++;
+//	}
+//}
+int32_t **rxdata;
+int32_t **txdata;
+
+int setup_ue_buffers(PHY_VARS_UE **phy_vars_ue, openair0_config_t *openair0_cfg);
+
+static inline void saif_meas(int frame_rx, int subframe_rx) {
+    static latency_stat_t __thread latency_stat;
+    static struct timespec __thread last= {0};
+    struct timespec now;
+    clock_gettime(CLOCK_MONOTONIC_RAW, &now);
+    if ( last.tv_sec )  {
+        uint64_t diffTime =  ((uint64_t)now.tv_sec *1000 *1000 *1000 + now.tv_nsec) -
+                             ((uint64_t)last.tv_sec *1000 *1000 *1000 + last.tv_nsec);
+        diffTime/=1000;
+        latency_stat.counter++;
+
+        if ( diffTime <= 800 ) {
+          if (diffTime  < 250 )
+            latency_stat.stat250++;
+          else if (diffTime  < 500 )
+            latency_stat.stat500++;
+          else if (diffTime  < 600 )
+            latency_stat.stat600++;
+          else if (diffTime  < 700 )
+            latency_stat.stat700++;
+          else
+            latency_stat.stat800++;
+        }
+        else if ( diffTime > 1200 ) {
+            if (diffTime  < 1500 )
+                latency_stat.stat1300++;
+            else if ( diffTime < 2000 )
+                latency_stat.stat1500++;
+            else if ( diffTime < 2500 )
+                latency_stat.stat2000++;
+            else if ( diffTime < 3000 )
+                latency_stat.stat2500++;
+            else
+                latency_stat.stat3000++;
+        }
+        else
+          if (diffTime  <= 880 )
+            latency_stat.stat880++;
+          else if (diffTime  <= 960 )
+            latency_stat.stat960++;
+          else if (diffTime  <= 1040 )
+            latency_stat.stat1040++;
+          else if (diffTime  < 1120 )
+            latency_stat.stat1120++;
+          else
+            latency_stat.stat1200++;
+
+
+        if ( (diffTime>=1500) || ( !(frame_rx%1024) && subframe_rx == 0 ) ) {
+            time_t current=time(NULL);
+            printf("\n");
+            printf("%.2f Period stats cnt=%7.7ld    0.. 250=%7.7ld  250.. 500=%7.7ld  500.. 600=%7.7ld  600.. 700=%7.7ld  700.. 800=%7.7ld - (frame_rx=%d) - %s",
+                  now.tv_sec+(double)now.tv_nsec/1e9,
+                  latency_stat.counter,
+                  latency_stat.stat250, latency_stat.stat500,
+                  latency_stat.stat600, latency_stat.stat700,
+                  latency_stat.stat800,
+                  frame_rx,
+                  ctime(&current));
+            printf("%.2f Period stats cnt=%7.7ld  800.. 880=%7.7ld  880.. 960=%7.7ld  960..1040=%7.7ld 1040..1120=%7.7ld 1120..1200=%7.7ld - (frame_rx=%d) - %s",
+                  now.tv_sec+(double)now.tv_nsec/1e9,
+                  latency_stat.counter,
+                  latency_stat.stat880, latency_stat.stat960,
+                  latency_stat.stat1040, latency_stat.stat1120,
+                  latency_stat.stat1200,
+                  frame_rx,
+                  ctime(&current));
+            printf("%.2f Period stats cnt=%7.7ld 1200..1300=%7.7ld 1300..1500=%7.7ld 1500..2000=%7.7ld 2000..2500=%7.7ld      >3000=%7.7ld - (frame_rx=%d) - %s",
+                  now.tv_sec+(double)now.tv_nsec/1e9,
+                  latency_stat.counter,
+                  latency_stat.stat1300, latency_stat.stat1500,
+                  latency_stat.stat2000, latency_stat.stat2500,
+                  latency_stat.stat3000,
+                  frame_rx,
+                  ctime(&current));
+            fflush(stdout);
+        }
+    }
+    last=now;
+}
+/* End of Changed by SYRTEM */
+
+void exit_fun(const char* s)
+{
+
+  if (s != NULL) {
+    printf("%s %s() Exiting OAI softmodem: %s\n",__FILE__, __FUNCTION__, s);
+  }
+
+  oai_exit = 1;
+ 
+}
+
+
+void init_thread(int sched_runtime, int sched_deadline, int sched_fifo, char * name) {
+
+#ifdef DEADLINE_SCHEDULER
+    if (sched_runtime!=0) {
+        struct sched_attr attr= {0};
+        attr.size = sizeof(attr);
+        // This creates a .5 ms fpga_recv_cnt reservation
+        attr.sched_policy = SCHED_DEADLINE;
+        attr.sched_runtime  = sched_runtime;
+        attr.sched_deadline = sched_deadline;
+        attr.sched_period   = 0;
+        AssertFatal(sched_setattr(0, &attr, 0) == 0,
+                    "[SCHED] main eNB thread: sched_setattr failed %s \n",perror(errno));
+        LOG_I(HW,"[SCHED][eNB] eNB main deadline thread %lu started on CPU %d\n",
+              (unsigned long)gettid(), sched_getcpu());
+    }
+
+#else
+#ifdef CPU_AFFINITY
+    if (get_nprocs() >2) {
+        for (j = 1; j < get_nprocs(); j++)
+            CPU_SET(j, &cpuset);
+    }
+    AssertFatal( 0 == pthread_setaffinity_np(pthread_self(), sizeof(cpu_set_t), &cpuset)==0,"");
+#endif
+    struct sched_param sp;
+    sp.sched_priority = sched_fifo;
+    AssertFatal(pthread_setschedparam(pthread_self(),SCHED_FIFO,&sp)==0,
+                "Can't set thread priority, Are you root?\n");
+#endif
+
+    // Lock memory from swapping. This is a process wide call (not constraint to this thread).
+    mlockall(MCL_CURRENT | MCL_FUTURE);
+    pthread_setname_np( pthread_self(), name );
+
+}
+
+
+int main(void)
+{
+	int                 ret;
+	uint64_t			i;
+	openair0_device     rf_device;
+	openair0_timestamp	timestamp       = 0;
+
+	int					sub_frame       = 0;
+	unsigned int        frame_rx        = 0;
+
+	unsigned int        nb_antennas_tx  = 1;
+	unsigned int        nb_antennas_rx  = 1;
+
+
+	openair0_cfg[0].mmapped_dma         = 0;
+	openair0_cfg[0].configFilename      = NULL;
+	openair0_cfg[0].duplex_mode         = duplex_mode_FDD;
+
+	uint32_t			**sendbuff		= NULL;
+	uint32_t			**recvbuff		= NULL;
+	uint32_t			expected_value	= 0;
+	uint32_t			received_value	= 0;
+	int					nsamp 			= 0; // 1 ms
+	int					antenna_id		= 1;
+	int 				c 				= 0;
+	int 				numIter			= 0;
+	int 				fpga_loop		= 0;
+#if RIFFA_CHANNEL_DATA1
+	uint64_t			first_ts		= 0;
+	uint8_t				is_first_ts		= 0;
+	uint64_t			trx_read_cnt	= 0;
+	uint32_t			j				= 0;
+	uint32_t			err_cnt			= 0;
+#else
+	int         		failure			= 0;
+#endif
+#if 0 // 5MHz BW
+  unsigned int 			nb_sample_per_tti	= 7680;
+  openair0_cfg[0].sample_rate				= 7.68e6;
+  openair0_cfg[0].samples_per_frame			= nb_sample_per_tti*10;
+  openair0_cfg[0].rx_bw						= 2.5e6;
+  openair0_cfg[0].tx_bw						= 2.5e6;
+  openair0_cfg[0].num_rb_dl					= 25;
+#endif
+
+#if 0 // 10MHz BW
+  unsigned int  nb_sample_per_tti   = 15360;
+  openair0_cfg[0].sample_rate       = 15.36e6;
+  openair0_cfg[0].samples_per_frame = nb_sample_per_tti*10;
+  openair0_cfg[0].rx_bw             = 5.0e6;
+  openair0_cfg[0].tx_bw             = 5.0e6;
+  openair0_cfg[0].num_rb_dl         = 50;
+#endif
+
+#if 1 // 20MHz BW
+  unsigned int  nb_sample_per_tti   = 30720;
+  openair0_cfg[0].sample_rate       = 30.72e6;
+  openair0_cfg[0].samples_per_frame = nb_sample_per_tti*10;
+  openair0_cfg[0].rx_bw             = 10.0e6;
+  openair0_cfg[0].tx_bw             = 10.0e6;
+  openair0_cfg[0].num_rb_dl         = 100;
+#endif
+
+  const char *openair_dir = getenv("OPENAIR_DIR");
+  const char *ini_file		= "/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.adrv9371-zc706_HWgain15dB.ini";
+
+  int   readBlockSize;
+  void* rxp[nb_antennas_rx];
+  void* txp[nb_antennas_tx];
+
+//  int32_t rxdata[1][nb_sample_per_tti*10+2048];
+#if 0
+  int32_t 				**rxdata;
+#endif
+//  init_thread(100000, 500000, sched_get_priority_max(SCHED_FIFO),"main UE");
+
+	printf("LTE HARDWARE Latency debug utility \n");
+  printf("INIT data buffers \n");
+
+#if 0
+  rxdata    = (int32_t**)memalign(32, nb_antennas_rx*sizeof(int32_t*) );
+  rxdata[0] = (int32_t*)memalign(32,(nb_sample_per_tti*10+2048)*sizeof(int32_t));
+#else
+  rxdata = (int32_t**)malloc16( nb_antennas_rx*sizeof(int32_t*) );
+  txdata = (int32_t**)malloc16( nb_antennas_tx*sizeof(int32_t*) );
+  rxdata[0] = (int32_t*)malloc16_clear( 307200*sizeof(int32_t) );
+  txdata[0] = (int32_t*)malloc16_clear( 307200*sizeof(int32_t) );
+#endif
+
+	printf("INIT done\n");
+
+	memset(&rf_device, 0, sizeof(openair0_device));
+
+	rf_device.host_type = BBU_HOST;
+	openair0_cfg[0].duplex_mode = duplex_mode_FDD;
+	openair0_cfg[0].rx_num_channels  = 1;
+	openair0_cfg[0].tx_num_channels  = 1;
+
+	// configure channel 0
+	for (i=0; i<openair0_cfg[0].rx_num_channels; i++)
+  {
+		printf("configure channel %d \n",i);
+		openair0_cfg[0].autocal[i] = 1;
+		openair0_cfg[0].rx_freq[i] = 2680000000;
+		openair0_cfg[0].tx_freq[i] = 2560000000;
+		openair0_cfg[0].rx_gain[i] = 61;
+		openair0_cfg[0].tx_gain[i] = 90;
+	}
+
+	if (openair_dir)
+	{
+		openair0_cfg[0].configFilename = malloc(strlen(openair_dir) + strlen(ini_file) + 2);
+		sprintf(openair0_cfg[0].configFilename, "%s/%s", openair_dir, ini_file);
+	}
+//	printf("openair0_cfg[0].configFilename:%s\n", openair0_cfg[0].configFilename);
+
+	ret = openair0_device_load( &rf_device, &openair0_cfg[0] );
+	if (ret != 0){
+		exit_fun("Error loading device library");
+    exit(-1);
+	}
+
+/*	Runtime test
+ *	30 720 000 samples (4 bytes) for 1 sec (30 720 for 1 ms)
+ */
+	puts( "* Starting the device" );
+
+//	TIMING
+//	struct timespec		start, stop; // tx_start, tx_stop;
+//	timing_stats_t		rx_stats, tx_stats;
+
+//	rx_stats.name		= strdup( "RX" );
+//	tx_stats.name		= strdup( "TX" );
+//	TIMING
+
+	nsamp		= 307200; // 1 ms
+	sendbuff	= memalign( 128, nb_antennas_rx * sizeof( uint32_t * ) );
+	sendbuff[0]	= memalign( 128, nsamp * sizeof( uint32_t ) );
+	recvbuff	= memalign( 128, nb_antennas_rx * sizeof( uint32_t * ) );
+	recvbuff[0]	= memalign( 128, nsamp * sizeof( uint32_t ) );
+
+//	Create dummy buffer
+	for ( c = 0; c < nsamp; c++ ) {
+//		sendbuff[0][c] = (c+1);
+		sendbuff[0][c] = (c+1)*16;
+//		sendbuff[0][c] = (nsamp-c);
+		recvbuff[0][c] = 0;
+	}
+
+	GET_TIME_INIT(3);
+
+	if ( rf_device.trx_start_func( &rf_device ) < 0 ) {
+		printf( "  device could not be started !\n" );
+		return -1;
+	}
+
+	// read 30720
+
+	// write 30720 ts+2*30720
+
+	// if tsread >= 2-307200 -> check expected value + status (RxoVer TxUnder)
+
+	rxp[0]			= (void*)&rxdata[0][0];
+	txp[0]			= (void*)&txdata[0][0];
+	timestamp		= 0;
+	nsamp			= 30720;	// 30720  => 1ms buffer
+	trx_read_cnt	= 100000;		// 1 loop => 1ms (10sec=10000; 15min = 900000)
+	antenna_id		= 1;
+	int	diff		= 0;
+	int compare_start	= 0;
+
+	uint32_t	looploop=0;
+	uint64_t	error_cnt = 0;
+	uint64_t	error_ts_start;
+
+	for (i = 0; i < trx_read_cnt; i++)
+	{
+
+//		printf("\n\n");
+
+
+//		ret = rf_device.trx_read_func( &rf_device, &timestamp, &(rxp[0][(i*30720)%307200]), nsamp, antenna_id );
+//		ret = rf_device.trx_read_func( &rf_device, &timestamp, recvbuff[0][(i*30720)%307200], nsamp, antenna_id );
+		rxp[0]			= (void*)&rxdata[0][(i*30720)%307200];
+		GET_TIME_VAL(0);
+		ret = rf_device.trx_read_func( &rf_device, &timestamp, rxp, nsamp, antenna_id );
+		GET_TIME_VAL(1);
+		
+		if (ret != nsamp)
+		{
+			printf("Error: nsamp received (%d) != nsamp required (%d)\n", ret, nsamp);
+			fflush(stdout);
+			return (-1);
+		}
+		if (!is_first_ts)
+		{
+			first_ts 	= timestamp;
+			is_first_ts	= 1;
+		}
+	
+//		printf("%d - trx_read_func ret=%d - ts = %d - @=0x%08lx\n", i, ret, timestamp, rxp[0]  );
+
+		txp[0]			= (void*)&(txdata[0][ ((i*30720)%307200+2*30720)%307200 ]);	
+//		printf("    i=%d @txp[0][0] = 0x%016lx\n", i, &(((uint32_t *)txp[0])[0]) );
+//		printf("    i=%d @txp[0][1] = 0x%016lx\n", i, &(((uint32_t *)txp[0])[1]) );
+
+		for ( c = 0; c < nsamp; c++ )
+		{
+			(((uint32_t *)txp[0])[c]) = ( (((timestamp+c+2*30720)<<4)&0x0000FFF0) + (((timestamp+c+2*30720)<<8)&0xFFF00000) );
+		}
+
+//		printf("    txp[0][%d] = 0x%x\n",0,((uint32_t *)(txp[0]))[0]);
+//		printf("    txp[0][%d] = 0x%x\n",1,((uint32_t *)(txp[0]))[1]);
+//		printf("    ...\n");
+//		printf("    txp[0][%d] = 0x%x\n",nsamp-2,((uint32_t *)(txp[0]))[nsamp-2]);
+//		printf("    txp[0][%d] = 0x%x\n",nsamp-1,((uint32_t *)(txp[0]))[nsamp-1]);
+
+
+		ret = rf_device.trx_write_func( &rf_device, (timestamp+2*30720), txp, nsamp, antenna_id, false );
+		if (ret != nsamp)
+		{
+			printf("Error: nsamp sent (%d) != nsamp required (%d)\n", ret, nsamp);
+			fflush(stdout);
+			return (-1);
+		}
+
+//		printf("%d - trx_write_func ret=%d - ts = %d - @=0x%08lx\n", i, ret, (timestamp+2*30720), txp[0]  );
+
+
+		if (timestamp >= (first_ts + 2 * 307200))
+		{			
+
+			// check Rx Overflow
+			
+			// check Tx Underflow
+
+			// check Expected Value
+			for ( c = 0; c < nsamp; c++ )
+			{
+
+// LOOPBACK
+#if 1
+				expected_value	= ((timestamp + c)&0xFFFFFF);
+				received_value	= ((uint32_t *)(rxp[0]))[c];
+				received_value	= ((received_value)&0xFFF) + ((received_value>>4)&0xFFF000);
+
+				if (compare_start == 0)
+				{
+					compare_start	= 1;
+					diff			= expected_value - received_value;
+				}
+				received_value = (received_value + diff)&0xFFFFFF;
+
+#if 1
+
+				if (expected_value != received_value)
+				{
+					if(!error_cnt)
+						error_ts_start = (timestamp + c);
+					else
+					{
+						if (looploop < 32)
+							printf("%d - %d != %d - ts %d - raw 0x%x - diff %d\n",
+								looploop, 
+								expected_value, received_value, 
+								(timestamp + c), ((uint32_t *)(rxp[0]))[c],
+								diff);
+						looploop++;
+					}
+
+					error_cnt++;
+
+					if(!(error_cnt%102400))
+						printf(" -> error detected     : cnt=%d - start=%ld - stop=... diff=%d\n",
+									error_cnt,
+									error_ts_start,
+									diff);
+
+				}
+				else
+				{
+					if(error_cnt)
+					{
+						printf(" -> error detected     : cnt=%d - start=%ld - stop=%ld\n\n",
+									error_cnt,
+									error_ts_start,
+									(timestamp + c) );
+						looploop=0;
+					}
+					error_cnt=0;
+				}
+#endif
+#endif
+
+// DEBUG mode 0
+#if 0
+				received_value	= ((uint32_t *)(rxp[0]))[c];
+				received_value	= ((received_value)&0xFFF) + ((received_value>>4)&0xFFF000);
+				received_value	= (received_value&0xFFFFFF);
+				if (compare_start == 0)
+				{
+					compare_start	= 1;
+					expected_value 	= received_value;
+				}
+				else
+				{
+					expected_value++;
+					expected_value	= (expected_value&0xFFFFFF);
+				}
+
+				if (expected_value != received_value)
+				{
+					if(!error_cnt)
+						error_ts_start = (timestamp + c);
+					error_cnt++;
+				}
+				else
+				{
+					if(error_cnt)
+					{
+						printf(" -> error detected     : cnt=%d - start=%ld - stop=%ld\n\n",
+									error_cnt,
+									error_ts_start,
+									(timestamp + c) );
+					}
+					error_cnt=0;
+				}
+
+
+
+//				if (expected_value != received_value)
+//				{
+//					printf("%d -> %d != %d (ts+c=%ld)(raw=0x%08x)\n", 
+//							looploop, 
+//							expected_value, received_value,
+//							(timestamp + c),
+//							((uint32_t *)(rxp[0]))[c] );
+//
+//					if (received_value)
+//						expected_value 	= received_value;
+//				}
+#endif
+
+			}
+		}
+	}
+
+	printf("HwLat Application returns !!!\n");
+	fflush(stdout);
+	sleep(1);
+
+
+	printf("\n");
+	rf_device.trx_end_func( &rf_device );
+
+	sleep(1);
+	free(sendbuff[0]);
+	free(sendbuff);
+	free(recvbuff[0]);
+	free(recvbuff);
+
+	exit(0);
+
+
+
+	return(0);
+
+
+
+//	puts( "* Frequency modification test" );
+//	rf_device.trx_set_freq_func( &rf_device, &openair0_cfg[0], 0 );
+
+//	puts( "* Gain modification test" );
+//	rf_device.trx_set_gains_func( &rf_device, &openair0_cfg[0] );	//	NOT working (cf. initialization)
+
+//#if LTE_UE
+//  sleep(1);
+	GET_TIME_VAL(0);
+	for (i = 0; i < trx_read_cnt; i++)
+	{
+    printf("\n");
+		ret = rf_device.trx_read_func( &rf_device, &timestamp, rxp, nsamp, antenna_id );
+    printf("* timestamp=%ld\n", timestamp);
+#if 1
+		for (j = 0; j < nsamp; j++)
+		{
+			if ( ((uint32_t *)rxp[0])[j] != ((expected_value + j + timestamp)%307200) )
+			{
+				err_cnt++;
+				printf("rxp[%06d]=0x%08x (expected 0x%08lx)\n", j, ((uint32_t *)rxp[0])[j], ((expected_value + j + timestamp)%307200) );
+			}
+			if (err_cnt >= 128)
+			{
+				printf("Error: more than 128 expected value failed !\n");
+				i = (trx_read_cnt - 1);
+				j = nsamp;
+				break;
+			}
+		}
+		//expected_value	= (expected_value + nsamp)%307200;
+    expected_value  = (expected_value)%307200;
+#endif
+	}
+	GET_TIME_VAL(1);
+//#endif
+
+/* ********** ********** */
+/*  RIFFA_CHANNEL_DATA1  */
+/* ********** ********** */
+#if RIFFA_CHANNEL_DATA1
+
+//  rf_device.trx_get_stats_func( &rf_device );
+
+  rf_device.trx_end_func( &rf_device );
+
+  printf("\n* rf_device.trx_read_func(%d) x %d: %.6lf s\n\n", nsamp, i, ((TIME_VAL_TO_MS(1) - TIME_VAL_TO_MS(0)))/1000.0 );
+
+//  rf_device.trx_get_stats_func( &rf_device );
+
+#if 0
+  for (i = 0; i < nsamp; i++)
+  {
+//    if ( ((uint32_t *)rxp[0])[i] != i)
+//    {
+      err_cnt++;
+      printf("rxp[%06d]=0x%08x (expected 0x%08x)\n", i, ((uint32_t *)rxp[0])[i], i);
+//    }
+//    if (err_cnt > 256)
+//    {
+//      i = 307200;
+//      break;
+//    }
+  }
+#endif
+//  for (i = 1024-32; i < 1024+32; i++)
+//  {
+////    if ( ((uint32_t *)rxp[0])[i] != i)
+////    {
+//      err_cnt++;
+//      printf("rxp[%06d]=0x%08x (expected 0x%08x)\n", i, ((uint32_t *)rxp[0])[i], i);
+////    }
+//    if (err_cnt > 256)
+//    {
+//      i = 307200;
+//      break;
+//    }
+//  }
+	printf("RIFFA CHANNEL DATA1 done !!!\n");
+  sleep(1);
+	return(0);
+#endif
+/* ********** ********** */
+/*  RIFFA_CHANNEL_DATA1  */
+/* ********** ********** */
+
+
+
+	timestamp	= 0;
+	ret = rf_device.trx_write_func( &rf_device, timestamp, (void**)sendbuff, nsamp, antenna_id, false );
+	printf("* rf_device.trx_write_func returns %d\n", ret);
+
+	sleep(1);
+
+	nsamp	= 30720;
+	numIter		= 100000;
+	for ( c = 0; c < numIter; c++ )
+	{
+		fpga_loop ++;
+		if ( !(fpga_loop % 1000) )
+		{
+			printf("\rtest loop %d / %d", fpga_loop, numIter);
+			fflush(stdout);
+		}
+
+//		printf("* TEST : %08d\n", (c+1));
+//		measure_time( &rf_device, &start, &stop, &tx_stats, true, 10 );
+//		ret = rf_device.trx_write_func( &rf_device, timestamp, (void**)sendbuff, nsamp, antenna_id, false );
+//    		printf("* rf_device.trx_write_func returns %d\n", ret);
+//		measure_time( &rf_device, &start, &stop, &tx_stats, false, 10 );
+
+//		sleep(1);
+
+//		measure_time( &rf_device, &start, &stop, &tx_stats, true, 10 );
+		ret = rf_device.trx_read_func( &rf_device, &timestamp, (void**)recvbuff, nsamp, antenna_id );
+//		measure_time( &rf_device, &start, &stop, &tx_stats, false, 10 );
+
+		// Check the data
+		if (ret > 0)
+		{
+/* ********** ********** */
+/*  RIFFA_CHANNEL_TESTER */
+/* ********** ********** */
+#if RIFFA_CHANNEL_TESTER
+      failure = 0;
+			for (i = 0; i < ret; i++)
+			{
+				if ( ((i%1024) == 0) || ((i%1024) == 1) || ((i%1024) == 2) || ((i%1024) == 3) )
+				{
+					if ( (recvbuff[0])[i] != (1020 + ((i%1024)+1)) )
+					{
+						printf("* ERROR (buff[0])[%d]: %d, expected %d\n", i, (uint32_t)(recvbuff[0])[i], ((i%1024)+1) );
+						failure = 1;
+					}
+				}
+				else if ( (recvbuff[0])[i] != ((i%1024)+1) )
+				{
+					printf("* ERROR (buff[0])[%d]: %d, expected %d\n", i, (uint32_t)(recvbuff[0])[i], ((i%1024)+1) );
+					failure = 1;
+				}
+				else
+				{
+					printf("* DONE  (buff[0])[%d]: %d, expected %d\n", i, (uint32_t)(recvbuff[0])[i], ((i%1024)+1) );
+				}
+				if(failure)
+					break;
+			}
+			if (failure)
+			 	printf("* ERROR recv %08d checked FAILURE ret=%d\n", (c+1), ret);
+			else
+      			{
+//			 	printf("* DONE  recv %08d checked SUCCESSFULLY ret=%d\n", (c+1), ret);
+      			}
+#endif
+/* ********** ********** */
+/*  RIFFA_CHANNEL_TESTER2*/
+/* ********** ********** */
+#if RIFFA_CHANNEL_TESTER2
+//			printf("* ret=%d timestamp=%ld (%ld)\n", ret, timestamp, (timestamp%307200));
+      failure = 0;
+			for (i = 0; i < ret; i++)
+			{
+//				printf("* (recvbuff[0])[%d]: %d\n", i, (uint32_t)(recvbuff[0])[i]);
+//				printf("* timestamp+(i/1024+1)*1024 - 3 + i%1024: %d\n", (timestamp-nsamp+(i/1024+1)*1024 - 3 + i%1024)%307200 );
+				expected_value	= ((((i%1024)+1)/*>>4*/)&0x00000FFF);
+				if ( ((i%1024) == 0) || ((i%1024) == 1) || ((i%1024) == 2) || ((i%1024) == 3) )
+				{
+					expected_value	= ((((timestamp-nsamp+(i/1024+1)*1024 - 3 + i%1024))%307200));
+					if ( (recvbuff[0])[i] !=  expected_value)
+					{
+						if ( (expected_value == 0) && ((recvbuff[0])[i] != 4915200) )
+						{
+							printf("* ERROR (buff[0])[%d]: %d, expected %d\n", i, (uint32_t)(recvbuff[0])[i], expected_value );
+							failure = 1;
+						}
+						if ( (expected_value == 0) && ((recvbuff[0])[i] == 4915200) )
+						{
+//							printf("* DONE loop in circular buffer\n");
+						}
+					}
+				}
+				else if ( (recvbuff[0])[i] != expected_value )
+				{
+					printf("* ERROR (buff[0])[%d]: %d, expected %d\n", i, (uint32_t)(recvbuff[0])[i], ((i%1024)+1) );
+					failure = 1;
+				}
+				else
+				{
+//					printf("* DONE  (buff[0])[%d]: %d, expected %d\n", i, (uint32_t)(recvbuff[0])[i], ((i%1024)+1) );
+				}
+//				if(failure)
+//					break;
+			}
+			if (failure)
+			 	printf("* ERROR recv %08d checked FAILURE ret=%d\n", (c+1), ret);
+			else
+      			{
+//			 	printf("* DONE  recv %08d checked SUCCESSFULLY ret=%d\n", (c+1), ret);
+      			}
+#endif
+#if LOOPBACK
+
+#endif
+		}
+		else
+		{
+			printf("* ERROR rf_device.trx_read_func returns %d\n", ret);
+		}
+
+	}
+	printf("\n");
+	rf_device.trx_end_func( &rf_device );
+
+	sleep(1);
+	free(sendbuff[0]);
+	free(sendbuff);
+	free(recvbuff[0]);
+	free(recvbuff);
+
+	exit(0);
+
+//	END IS HERE !
+
+	rf_device.trx_set_freq_func(&rf_device,&openair0_cfg[0],0);
+
+	if (rf_device.trx_start_func(&rf_device) != 0 ) {
+		printf("Could not start the device\n");
+		oai_exit=1;
+	}
+
+	while(!oai_exit){
+
+	rxp[0] = (void*)&rxdata[0][sub_frame*nb_sample_per_tti];
+
+	readBlockSize = rf_device.trx_read_func( &rf_device,
+											&timestamp,
+											rxp,
+											nb_sample_per_tti,
+											0);
+
+    if ( readBlockSize != nb_sample_per_tti )
+      oai_exit = 1;
+
+    sub_frame++;
+    sub_frame%=10;
+
+    if( sub_frame == 0)
+      frame_rx++;
+
+    saif_meas(frame_rx, sub_frame);
+  }
+
+  return(0);
+}

targets/SIMU/USER/oaisim_functions.c

@@ -1704,7 +1704,7 @@ void update_otg_eNB(module_id_t enb_module_idP, unsigned int ctime)
   }
 
 #else
-#if 0 //  defined(EXMIMO) || defined(OAI_USRP)
+#if 0 //  defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_ADRV9371_ZC706)
   if (otg_enabled==1) {
     ctime = frame * 100;
 

targets/build_oai.bash

@@ -344,6 +344,10 @@ build_enb(){
         SOFTMODEM_DIRECTIVES="$SOFTMODEM_DIRECTIVES USRP=1 "
     fi
     
+    if [ $HW = "ADRV9371_ZC706" ]; then 
+        SOFTMODEM_DIRECTIVES="$SOFTMODEM_DIRECTIVES ADRV9371_ZC706=1 "
+    fi
+    
     if [ $HW = "EXMIMO" ]; then 
         SOFTMODEM_DIRECTIVES="$SOFTMODEM_DIRECTIVES EXMIMO=1 "
     fi