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Merge remote-tracking branch 'origin/develop' into feature-131-new-license

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Conflicts:
	openair1/PHY/INIT/lte_init.c
	openair1/PHY/LTE_TRANSPORT/dci_tools.c
	openair1/PHY/LTE_TRANSPORT/ulsch_decoding.c
	openair1/SCHED/phy_procedures_lte_eNb.c
	openair1/SCHED/phy_procedures_lte_ue.c
	openair1/SIMULATION/LTE_PHY/dlsim.c
	openair1/SIMULATION/RF/adc.c
	openair2/LAYER2/MAC/lte_transport_init.c
	targets/RT/USER/lte-softmodem.c
	targets/RT/USER/sched_dlsch.c
	targets/RT/USER/sched_rx_pdsch.c
	targets/RT/USER/sched_ulsch.c
	targets/SIMU/USER/oaisim.c
This commit is contained in:
Cedric Roux
2016-09-27 15:05:00 +02:00
parent f06dd02fe8 e08e2577f5
commit 7a724e7d2e
200 changed files with 22970 additions and 19972 deletions
Download Patch File Download Diff File Expand all files Collapse all files
openair2/ENB_APP/enb_config.c
+71 -10
View File
@@ -30,6 +30,7 @@
#include "sctp_default_values.h"
#include "SystemInformationBlockType2.h"
#include "LAYER2/MAC/extern.h"
#include "PHY/extern.h"
/* those macros are here to help diagnose problems in configuration files
* if the lookup fails, a warning is printed
@@ -65,6 +66,10 @@
#define ENB_CONFIG_STRING_COMPONENT_CARRIERS "component_carriers"
#define ENB_CONFIG_STRING_CC_NODE_FUNCTION "node_function"
#define ENB_CONFIG_STRING_CC_NODE_TIMING "node_timing"
#define ENB_CONFIG_STRING_CC_NODE_SYNCH_REF "node_synch_ref"
#define ENB_CONFIG_STRING_FRAME_TYPE "frame_type"
#define ENB_CONFIG_STRING_TDD_CONFIG "tdd_config"
#define ENB_CONFIG_STRING_TDD_CONFIG_S "tdd_config_s"
@@ -292,24 +297,29 @@ void enb_config_display(void)
printf( "\ttx_scheduling_advance :\t%d:\n",enb_properties.properties[i]->rrh_gw_config[j].tx_scheduling_advance);
printf( "\ttx_sample_advance : \t%d:\n",enb_properties.properties[i]->rrh_gw_config[j].tx_sample_advance);
printf( "\tiq_txshift : \t%d:\n",enb_properties.properties[i]->rrh_gw_config[j].iq_txshift);
printf( "\ttransport : \t%s Ethernet:\n",(enb_properties.properties[i]->rrh_gw_config[j].raw == 1)? "RAW" : "UDP");
printf( "\ttransport : \t%s Ethernet:\n",(enb_properties.properties[i]->rrh_gw_config[j].raw == 1)? "RAW" : (enb_properties.properties[i]->rrh_gw_config[j].rawif4p5 == 1)? "RAW_IF4p5" : (enb_properties.properties[i]->rrh_gw_config[j].udpif4p5 == 1)? "UDP_IF4p5" : (enb_properties.properties[i]->rrh_gw_config[j].rawif5_mobipass == 1)? "RAW_IF5_MOBIPASS" : "UDP");
if (enb_properties.properties[i]->rrh_gw_config[j].exmimo == 1) {
printf( "\tRF target : \tEXMIMO:\n\n");
printf( "\tRF target : \tEXMIMO:\n");
} else if (enb_properties.properties[i]->rrh_gw_config[j].usrp_b200 == 1) {
printf( "\tRF target : \tUSRP_B200:\n\n");
printf( "\tRF target : \tUSRP_B200:\n");
} else if (enb_properties.properties[i]->rrh_gw_config[j].usrp_x300 == 1) {
printf( "\tRF target : \tUSRP_X300:\n\n");
printf( "\tRF target : \tUSRP_X300:\n");
} else if (enb_properties.properties[i]->rrh_gw_config[j].bladerf == 1) {
printf( "\tRF target : \tBLADERF:\n\n");
printf( "\tRF target : \tBLADERF:\n");
} else if (enb_properties.properties[i]->rrh_gw_config[j].lmssdr == 1) {
printf( "\tRF target : \tLMSSDR:\n\n");
printf( "\tRF target : \tLMSSDR:\n");
} else {
printf( "\tRF target : \tNONE:\n\n");
printf( "\tRF target : \tNONE:\n");
}
}
}
for (j=0; j< enb_properties.properties[i]->nb_cc; j++) {
// CC_ID node function/timing
printf( "\n\tnode_function for CC %d: \t%s:\n",j,eNB_functions[enb_properties.properties[i]->cc_node_function[j]]);
printf( "\tnode_timing for CC %d: \t%s:\n",j,eNB_timing[enb_properties.properties[i]->cc_node_timing[j]]);
printf( "\tnode_synch_ref for CC %d: \t%d:\n",j,enb_properties.properties[i]->cc_node_synch_ref[j]);
printf( "\teutra band for CC %d: \t%"PRId16":\n",j,enb_properties.properties[i]->eutra_band[j]);
printf( "\tdownlink freq for CC %d: \t%"PRIu64":\n",j,enb_properties.properties[i]->downlink_frequency[j]);
printf( "\tuplink freq offset for CC %d: \t%"PRId32":\n",j,enb_properties.properties[i]->uplink_frequency_offset[j]);
@@ -319,7 +329,7 @@ void enb_config_display(void)
printf( "\tnb_antenna_ports for CC %d:\t%d:\n",j,enb_properties.properties[i]->nb_antenna_ports[j]);
printf( "\tnb_antennas_tx for CC %d:\t%d:\n",j,enb_properties.properties[i]->nb_antennas_tx[j]);
printf( "\tnb_antennas_rx for CC %d:\t%d:\n",j,enb_properties.properties[i]->nb_antennas_rx[j]);
// RACH-Config
printf( "\trach_numberOfRA_Preambles for CC %d:\t%ld:\n",j,enb_properties.properties[i]->rach_numberOfRA_Preambles[j]);
printf( "\trach_preamblesGroupAConfig for CC %d:\t%d:\n",j,enb_properties.properties[i]->rach_preamblesGroupAConfig[j]);
@@ -497,6 +507,7 @@ const Enb_properties_array_t *enb_config_init(char* lib_config_file_name_pP)
config_setting_t *setting_enb = NULL;
config_setting_t *setting_otg = NULL;
config_setting_t *subsetting_otg = NULL;
int parse_errors = 0;
int num_enb_properties = 0;
int enb_properties_index = 0;
int num_enbs = 0;
@@ -507,6 +518,11 @@ const Enb_properties_array_t *enb_config_init(char* lib_config_file_name_pP)
int i = 0;
int j = 0;
libconfig_int enb_id = 0;
const char* cc_node_function = NULL;
const char* cc_node_timing = NULL;
int cc_node_synch_ref = 0;
const char* cell_type = NULL;
const char* tac = 0;
const char* enb_name = NULL;
@@ -783,7 +799,10 @@ const Enb_properties_array_t *enb_config_init(char* lib_config_file_name_pP)
component_carrier = config_setting_get_elem(setting_component_carriers, j);
//printf("Component carrier %d\n",component_carrier);
if (!(config_setting_lookup_string(component_carrier, ENB_CONFIG_STRING_FRAME_TYPE, &frame_type)
if (!(config_setting_lookup_string(component_carrier, ENB_CONFIG_STRING_CC_NODE_FUNCTION, &cc_node_function)
&& config_setting_lookup_string(component_carrier, ENB_CONFIG_STRING_CC_NODE_TIMING, &cc_node_timing)
&& config_setting_lookup_int(component_carrier, ENB_CONFIG_STRING_CC_NODE_SYNCH_REF, &cc_node_synch_ref)
&& config_setting_lookup_string(component_carrier, ENB_CONFIG_STRING_FRAME_TYPE, &frame_type)
&& config_setting_lookup_int(component_carrier, ENB_CONFIG_STRING_TDD_CONFIG, &tdd_config)
&& config_setting_lookup_int(component_carrier, ENB_CONFIG_STRING_TDD_CONFIG_S, &tdd_config_s)
&& config_setting_lookup_string(component_carrier, ENB_CONFIG_STRING_PREFIX_TYPE, &prefix_type)
@@ -863,6 +882,42 @@ const Enb_properties_array_t *enb_config_init(char* lib_config_file_name_pP)
enb_properties.properties[enb_properties_index]->nb_cc++;
if (strcmp(cc_node_function, "eNodeB_3GPP") == 0) {
enb_properties.properties[enb_properties_index]->cc_node_function[j] = eNodeB_3GPP;
} else if (strcmp(cc_node_function, "eNodeB_3GPP_BBU") == 0) {
enb_properties.properties[enb_properties_index]->cc_node_function[j] = eNodeB_3GPP_BBU;
} else if (strcmp(cc_node_function, "NGFI_RCC_IF4p5") == 0) {
enb_properties.properties[enb_properties_index]->cc_node_function[j] = NGFI_RCC_IF4p5;
} else if (strcmp(cc_node_function, "NGFI_RAU_IF4p5") == 0) {
enb_properties.properties[enb_properties_index]->cc_node_function[j] = NGFI_RAU_IF4p5;
} else if (strcmp(cc_node_function, "NGFI_RRU_IF4p5") == 0) {
enb_properties.properties[enb_properties_index]->cc_node_function[j] = NGFI_RRU_IF4p5;
} else if (strcmp(cc_node_function, "NGFI_RRU_IF5") == 0) {
enb_properties.properties[enb_properties_index]->cc_node_function[j] = NGFI_RRU_IF5;
} else {
AssertError (0, parse_errors ++,
"Failed to parse eNB configuration file %s, enb %d unknown value \"%s\" for node_function choice: eNodeB_3GPP or eNodeB_3GPP_BBU or NGFI_IF4_RCC or NGFI_IF4_RRU or NGFI_IF5_RRU !\n",
lib_config_file_name_pP, i, cc_node_function);
}
if (strcmp(cc_node_timing, "synch_to_ext_device") == 0) {
enb_properties.properties[enb_properties_index]->cc_node_timing[j] = synch_to_ext_device;
} else if (strcmp(cc_node_timing, "synch_to_other") == 0) {
enb_properties.properties[enb_properties_index]->cc_node_timing[j] = synch_to_other;
} else {
AssertError (0, parse_errors ++,
"Failed to parse eNB configuration file %s, enb %d unknown value \"%s\" for node_function choice: SYNCH_TO_DEVICE or SYNCH_TO_OTHER !\n",
lib_config_file_name_pP, i, cc_node_timing);
}
if ((cc_node_synch_ref >= -1) && (cc_node_synch_ref < num_component_carriers)) {
enb_properties.properties[enb_properties_index]->cc_node_synch_ref[j] = (int16_t) cc_node_synch_ref;
} else {
AssertError (0, parse_errors ++,
"Failed to parse eNB configuration file %s, enb %d unknown value \"%d\" for node_synch_ref choice: valid CC_id or -1 !\n",
lib_config_file_name_pP, i, cc_node_synch_ref);
}
enb_properties.properties[enb_properties_index]->tdd_config[j] = tdd_config;
AssertFatal (tdd_config <= TDD_Config__subframeAssignment_sa6,
"Failed to parse eNB configuration file %s, enb %d illegal tdd_config %d (should be 0-%d)!",
@@ -886,7 +941,7 @@ const Enb_properties_array_t *enb_config_init(char* lib_config_file_name_pP)
"Failed to parse eNB configuration file %s, enb %d unknown value \"%s\" for prefix_type choice: NORMAL or EXTENDED !\n",
lib_config_file_name_pP, i, prefix_type);
}
enb_properties.properties[enb_properties_index]->eutra_band[j] = eutra_band;
enb_properties.properties[enb_properties_index]->downlink_frequency[j] = (uint32_t) downlink_frequency;
enb_properties.properties[enb_properties_index]->uplink_frequency_offset[j] = (unsigned int) uplink_frequency_offset;
@@ -2277,6 +2332,12 @@ const Enb_properties_array_t *enb_config_init(char* lib_config_file_name_pP)
enb_properties.properties[enb_properties_index]->rrh_gw_config[j].udp = 1;
} else if (strcmp(tr_preference, "raw") == 0) {
enb_properties.properties[enb_properties_index]->rrh_gw_config[j].raw = 1;
} else if (strcmp(tr_preference, "udp_if4p5") == 0) {
enb_properties.properties[enb_properties_index]->rrh_gw_config[j].udpif4p5 = 1;
} else if (strcmp(tr_preference, "raw_if4p5") == 0) {
enb_properties.properties[enb_properties_index]->rrh_gw_config[j].rawif4p5 = 1;
} else if (strcmp(tr_preference, "raw_if5_mobipass") == 0) {
enb_properties.properties[enb_properties_index]->rrh_gw_config[j].rawif5_mobipass = 1;
} else {//if (strcmp(preference, "no") == 0)
enb_properties.properties[enb_properties_index]->rrh_gw_config[j].udp = 1;
enb_properties.properties[enb_properties_index]->rrh_gw_config[j].raw = 1;
openair2/ENB_APP/enb_config.h
+7
View File
@@ -16,6 +16,7 @@
#include "platform_types.h"
#include "platform_constants.h"
#include "PHY/impl_defs_lte.h"
#include "PHY/defs.h"
#include "s1ap_messages_types.h"
#ifdef CMAKER
#include "SystemInformationBlockType2.h"
@@ -57,6 +58,9 @@ typedef struct rrh_gw_config_s {
char *remote_address;
uint16_t local_port;
uint16_t remote_port;
uint8_t udpif4p5;
uint8_t rawif4p5;
uint8_t rawif5_mobipass;
int tx_scheduling_advance;
int tx_sample_advance;
int iq_txshift;
@@ -97,6 +101,9 @@ typedef struct Enb_properties_s {
/* Physical parameters */
int16_t nb_cc;
eNB_func_t cc_node_function[1+MAX_NUM_CCs];
eNB_timing_t cc_node_timing[1+MAX_NUM_CCs];
int16_t cc_node_synch_ref[1+MAX_NUM_CCs];
lte_frame_type_t frame_type[1+MAX_NUM_CCs];
uint8_t tdd_config[1+MAX_NUM_CCs];
uint8_t tdd_config_s[1+MAX_NUM_CCs];
openair2/LAYER2/MAC/defs.h
+9
View File
@@ -54,6 +54,7 @@
#define BCCH_PAYLOAD_SIZE_MAX 128
#define CCCH_PAYLOAD_SIZE_MAX 128
#define PCCH_PAYLOAD_SIZE_MAX 128
#define SCH_PAYLOAD_SIZE_MAX 4096
/// Logical channel ids from 36-311 (Note BCCH is not specified in 36-311, uses the same as first DRB)
@@ -235,6 +236,10 @@ typedef struct {
typedef struct {
uint8_t payload[BCCH_PAYLOAD_SIZE_MAX] ;
} __attribute__((__packed__))BCCH_PDU;
/*! \brief BCCH payload */
typedef struct {
uint8_t payload[PCCH_PAYLOAD_SIZE_MAX] ;
} __attribute__((__packed__))PCCH_PDU;
#ifdef Rel10
/*! \brief MCCH payload */
@@ -263,6 +268,8 @@ typedef struct {
#define CCCH_LCHANID 0
/*!\brief Values of BCCH logical channel */
#define BCCH 3 // SI
/*!\brief Values of PCCH logical channel */
#define PCCH 4 // Paging
/*!\brief Value of CCCH / SRB0 logical channel */
#define CCCH 0 // srb0
/*!\brief DCCH / SRB1 logical channel */
@@ -1076,6 +1083,8 @@ typedef struct {
time_stats_t rx_mch_sdu;
/// UE BCCH rx processing time including RLC interface (mac_rrc_data_ind)
time_stats_t rx_si;
/// UE PCCH rx processing time including RLC interface (mac_rrc_data_ind)
time_stats_t rx_p;
} UE_MAC_INST;
/*! \brief ID of the neighboring cells used for HO*/
typedef struct {
openair2/LAYER2/MAC/eNB_scheduler.c
+31 -29
View File
@@ -91,8 +91,10 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
while (i>=0) {
rnti = UE_RNTI(module_idP, i);
CC_id = UE_PCCID(module_idP, i);
LOG_D(MAC,"UE %d: rnti %x (%p)\n", i, rnti,
mac_xface->get_eNB_UE_stats(module_idP, CC_id, rnti));
if ((frameP==0)&&(subframeP==0))
LOG_I(MAC,"UE rnti %x : %s\n", rnti,
UE_list->UE_sched_ctrl[i].ul_out_of_sync==0 ? "in synch" : "out of sync");
next_i= UE_list->next[i];
PHY_vars_eNB_g[module_idP][CC_id]->pusch_stats_bsr[i][(frameP*10)+subframeP]=-63;
@@ -118,8 +120,8 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
LOG_D(MAC,"UE %d rnti %x: sending PDCCH order for RAPROC (failure timer %d) \n",i,rnti,UE_list->UE_sched_ctrl[i].ul_failure_timer);
DLSCH_dci = (void *)UE_list->UE_template[CC_id][i].DLSCH_DCI[0];
*(uint32_t*)DLSCH_dci = 0;
if (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.frame_type == TDD) {
switch (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL) {
if (PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.frame_type == TDD) {
switch (PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL) {
case 6:
((DCI1A_1_5MHz_TDD_1_6_t*)DLSCH_dci)->type = 1;
((DCI1A_1_5MHz_TDD_1_6_t*)DLSCH_dci)->rballoc = 31;
@@ -147,7 +149,7 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
}
}
else { // FDD
switch (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL) {
switch (PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL) {
case 6:
((DCI1A_1_5MHz_FDD_t*)DLSCH_dci)->type = 1;
((DCI1A_1_5MHz_FDD_t*)DLSCH_dci)->rballoc = 31;
@@ -289,7 +291,7 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
//if (subframeP%5 == 0)
//#ifdef EXMIMO
PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, module_idP, ENB_FLAG_YES, NOT_A_RNTI, frameP, 0,module_idP);
PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, module_idP, ENB_FLAG_YES, NOT_A_RNTI, frameP, subframeP,module_idP);
pdcp_run(&ctxt);
//#endif
@@ -333,11 +335,11 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
schedule_RA(module_idP,frameP,subframeP,2);
if (mac_xface->lte_frame_parms->frame_type == FDD) { //FDD
if (mac_xface->frame_parms->frame_type == FDD) { //FDD
schedule_ulsch(module_idP,frameP,cooperation_flag,0,4);//,calibration_flag);
} else if ((mac_xface->lte_frame_parms->tdd_config == TDD) || //TDD
(mac_xface->lte_frame_parms->tdd_config == 3) ||
(mac_xface->lte_frame_parms->tdd_config == 6)) {
} else if ((mac_xface->frame_parms->tdd_config == TDD) || //TDD
(mac_xface->frame_parms->tdd_config == 3) ||
(mac_xface->frame_parms->tdd_config == 6)) {
//schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,4);//,calibration_flag);
}
@@ -350,8 +352,8 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
// TDD, schedule UL for subframeP 7 (TDD config 0,1) / subframeP 8 (TDD Config 6)
// FDD, schedule normal UL/DLSCH
if (mac_xface->lte_frame_parms->frame_type == TDD) { // TDD
switch (mac_xface->lte_frame_parms->tdd_config) {
if (mac_xface->frame_parms->frame_type == TDD) { // TDD
switch (mac_xface->frame_parms->tdd_config) {
case 0:
case 1:
schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,7);
@@ -378,7 +380,7 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
// TDD, nothing
// FDD, normal UL/DLSCH
if (mac_xface->lte_frame_parms->frame_type == FDD) { //FDD
if (mac_xface->frame_parms->frame_type == FDD) { //FDD
schedule_ulsch(module_idP,frameP,cooperation_flag,2,6);
schedule_ue_spec(module_idP,frameP,subframeP,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,mbsfn_status);
@@ -391,8 +393,8 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
// TDD Config 2, ULSCH for subframeP 7
// TDD Config 2/5 normal DLSCH
// FDD, normal UL/DLSCH
if (mac_xface->lte_frame_parms->frame_type == TDD) {
switch (mac_xface->lte_frame_parms->tdd_config) {
if (mac_xface->frame_parms->frame_type == TDD) {
switch (mac_xface->frame_parms->tdd_config) {
case 2:
schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,7);
@@ -419,8 +421,8 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
// TDD Config 1, ULSCH for subframeP 8
// TDD Config 1/2/4/5 DLSCH
// FDD UL/DLSCH
if (mac_xface->lte_frame_parms->frame_type == 1) { // TDD
switch (mac_xface->lte_frame_parms->tdd_config) {
if (mac_xface->frame_parms->frame_type == 1) { // TDD
switch (mac_xface->frame_parms->tdd_config) {
case 1:
// schedule_RA(module_idP,frameP,subframeP);
schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,8);
@@ -442,7 +444,7 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
break;
}
} else {
if (mac_xface->lte_frame_parms->frame_type == FDD) { //FDD
if (mac_xface->frame_parms->frame_type == FDD) { //FDD
schedule_ulsch(module_idP, frameP, cooperation_flag, 4, 8);
schedule_ue_spec(module_idP, frameP, subframeP, mbsfn_status);
@@ -460,13 +462,13 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
schedule_SI(module_idP,frameP,subframeP);
//schedule_RA(module_idP,frameP,subframeP,5);
if (mac_xface->lte_frame_parms->frame_type == FDD) {
if (mac_xface->frame_parms->frame_type == FDD) {
schedule_RA(module_idP,frameP,subframeP,1);
schedule_ulsch(module_idP,frameP,cooperation_flag,5,9);
schedule_ue_spec(module_idP, frameP, subframeP, mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,mbsfn_status);
} else if ((mac_xface->lte_frame_parms->tdd_config == 0) || // TDD Config 0
(mac_xface->lte_frame_parms->tdd_config == 6)) { // TDD Config 6
} else if ((mac_xface->frame_parms->tdd_config == 0) || // TDD Config 0
(mac_xface->frame_parms->tdd_config == 6)) { // TDD Config 6
//schedule_ulsch(module_idP,cooperation_flag,subframeP);
fill_DLSCH_dci(module_idP,frameP,subframeP,mbsfn_status);
} else {
@@ -481,8 +483,8 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
// TDD Config 0,1,6 ULSCH for subframes 2,3
// TDD Config 3,4,5 Normal DLSCH
// FDD normal ULSCH/DLSCH
if (mac_xface->lte_frame_parms->frame_type == TDD) { // TDD
switch (mac_xface->lte_frame_parms->tdd_config) {
if (mac_xface->frame_parms->frame_type == TDD) { // TDD
switch (mac_xface->frame_parms->tdd_config) {
case 0:
break;
@@ -525,8 +527,8 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
// TDD Config 3,4,5 Normal DLSCH
// FDD Normal UL/DLSCH
if (mac_xface->lte_frame_parms->frame_type == TDD) { // TDD
switch (mac_xface->lte_frame_parms->tdd_config) {
if (mac_xface->frame_parms->frame_type == TDD) { // TDD
switch (mac_xface->frame_parms->tdd_config) {
case 3:
case 4:
schedule_RA(module_idP,frameP,subframeP,3); // 3 = Msg3 subframeP, not
@@ -555,8 +557,8 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
// TDD Config 2,3,4,5 ULSCH for subframeP 2
//
// FDD Normal UL/DLSCH
if (mac_xface->lte_frame_parms->frame_type == TDD) { // TDD
switch (mac_xface->lte_frame_parms->tdd_config) {
if (mac_xface->frame_parms->frame_type == TDD) { // TDD
switch (mac_xface->frame_parms->tdd_config) {
case 2:
case 3:
case 4:
@@ -582,8 +584,8 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
case 9:
// TDD Config 1,3,4,6 ULSCH for subframes 3,3,3,4
if (mac_xface->lte_frame_parms->frame_type == TDD) {
switch (mac_xface->lte_frame_parms->tdd_config) {
if (mac_xface->frame_parms->frame_type == TDD) {
switch (mac_xface->frame_parms->tdd_config) {
case 1:
schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,3);
schedule_RA(module_idP,frameP,subframeP,7); // 7 = Msg3 subframeP, not
openair2/LAYER2/MAC/eNB_scheduler_RA.c
+29 -29
View File
@@ -87,8 +87,8 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
if (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.frame_type == TDD) {
switch(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL) {
if (PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.frame_type == TDD) {
switch(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL) {
case 6:
((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->type=1;
((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type=0;
@@ -98,7 +98,7 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0;
((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1;
((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->padding=0;
((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4);
((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL,first_rb,4);
rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type,
((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc);
break;
@@ -112,7 +112,7 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0;
((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1;
((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->padding=0;
((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4);
((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL,first_rb,4);
rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type,
((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc);
break;
@@ -126,7 +126,7 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0;
((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1;
((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->padding=0;
((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4);
((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL,first_rb,4);
rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type,
((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc);
break;
@@ -140,7 +140,7 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0;
((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1;
((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->padding=0;
((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4);
((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL,first_rb,4);
rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type,
((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc);
break;
@@ -154,13 +154,13 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0;
((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1;
((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->padding=0;
((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4);
((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL,first_rb,4);
rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type,
((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu1[0])->rballoc);
break;
}
} else {
switch(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL) {
switch(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL) {
case 6:
((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->type=1;
((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type=0;
@@ -170,7 +170,7 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0;
((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1;
((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->padding=0;
((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4);
((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL,first_rb,4);
rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type,
((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc);
break;
@@ -184,7 +184,7 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0;
((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1;
((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->padding=0;
((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_UL,first_rb,4);
((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_UL,first_rb,4);
rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type,
((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc);
break;
@@ -198,7 +198,7 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0;
((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1;
((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->padding=0;
((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4);
((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL,first_rb,4);
rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type,
((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc);
break;
@@ -212,7 +212,7 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->harq_pid=0;
((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->TPC=1;
((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->padding=0;
((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4);
((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL,first_rb,4);
rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->vrb_type,
((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu1[0])->rballoc);
break;
@@ -279,7 +279,7 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
/*
// randomize frequency allocation for RA
while (1) {
first_rb = (unsigned char)(taus()%(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL-4));
first_rb = (unsigned char)(taus()%(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL-4));
if ((vrb_map[first_rb] != 1) && (vrb_map[first_rb+3] != 1))
break;
@@ -296,9 +296,9 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
// Compute MCS for 3 PRB
msg4_header = 1+6+1; // CR header, CR CE, SDU header
if (mac_xface->lte_frame_parms->frame_type == TDD) {
if (mac_xface->frame_parms->frame_type == TDD) {
switch (mac_xface->lte_frame_parms->N_RB_DL) {
switch (mac_xface->frame_parms->N_RB_DL) {
case 6:
((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->ndi=1;
@@ -327,7 +327,7 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->harq_pid=0;
((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->TPC=1;
((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->padding=0;
((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4);
((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL,first_rb,4);
rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type,
((DCI1A_1_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc);
@@ -363,7 +363,7 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->harq_pid=0;
((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->TPC=1;
((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->padding=0;
((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4);
((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL,first_rb,4);
rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type,
((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc);
break;
@@ -397,7 +397,7 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->harq_pid=0;
((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->TPC=1;
((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->padding=0;
((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4);
((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL,first_rb,4);
rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type,
((DCI1A_10MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc);
@@ -432,13 +432,13 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rv=0;
((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->harq_pid=0;
((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->TPC=1;
((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4);
((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL,first_rb,4);
rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type,
((DCI1A_20MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc);
break;
}
} else { // FDD DCI
switch (mac_xface->lte_frame_parms->N_RB_DL) {
switch (mac_xface->frame_parms->N_RB_DL) {
case 6:
((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->ndi=1;
@@ -468,7 +468,7 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->harq_pid=0;
((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->TPC=1;
((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->padding=0;
((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4);
((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL,first_rb,4);
rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type,
((DCI1A_1_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc);
break;
@@ -502,7 +502,7 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->harq_pid=0;
((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->TPC=1;
((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->padding=0;
((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4);
((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL,first_rb,4);
rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type,
((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc);
break;
@@ -536,7 +536,7 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->harq_pid=0;
((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->TPC=1;
((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->padding=0;
((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4);
((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL,first_rb,4);
rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type,
((DCI1A_10MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc);
break;
@@ -569,7 +569,7 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->harq_pid=0;
((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->TPC=1;
((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->padding=0;
((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4);
((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc= mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL,first_rb,4);
rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type,
((DCI1A_20MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc);
break;
@@ -643,7 +643,7 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
if (round>0) {
//RA_template->wait_ack_Msg4++;
// we have to schedule a retransmission
if (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.frame_type == TDD) {
if (PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.frame_type == TDD) {
((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->ndi=1;
} else {
((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->ndi=1;
@@ -652,7 +652,7 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
/*
// randomize frequency allocation for RA
while (1) {
first_rb = (unsigned char)(taus()%(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL-4));
first_rb = (unsigned char)(taus()%(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL-4));
if ((vrb_map[first_rb] != 1) && (vrb_map[first_rb+3] != 1))
break;
@@ -664,12 +664,12 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
vrb_map[first_rb+2] = 1;
vrb_map[first_rb+3] = 1;
if (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.frame_type == TDD) {
((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_UL,first_rb,4);
if (PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.frame_type == TDD) {
((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_UL,first_rb,4);
rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type,
((DCI1A_5MHz_TDD_1_6_t*)&RA_template->RA_alloc_pdu2[0])->rballoc);
} else {
((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_UL,first_rb,4);
((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_UL,first_rb,4);
rballoc[CC_id] |= mac_xface->get_rballoc(((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->vrb_type,
((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->rballoc);
}
openair2/LAYER2/MAC/eNB_scheduler_bch.c
+14 -14
View File
@@ -84,7 +84,7 @@ schedule_SI(
// Allocate 4 PRBs in a random location
/*
while (1) {
first_rb = (unsigned char)(taus()%(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL-4));
first_rb = (unsigned char)(taus()%(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL-4));
if ((vrb_map[first_rb] != 1) &&
(vrb_map[first_rb+1] != 1) &&
(vrb_map[first_rb+2] != 1) &&
@@ -92,7 +92,7 @@ schedule_SI(
break;
}
*/
switch (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL) {
switch (PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL) {
case 6:
first_rb = 0;
break;
@@ -138,11 +138,11 @@ schedule_SI(
if (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.frame_type == TDD) {
switch (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL) {
if (PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.frame_type == TDD) {
switch (PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL) {
case 6:
((DCI1A_1_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->mcs = mcs;
((DCI1A_1_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4);
((DCI1A_1_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL,first_rb,4);
((DCI1A_1_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->type = 1;
((DCI1A_1_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->vrb_type = 0;
((DCI1A_1_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->ndi = 1;
@@ -157,7 +157,7 @@ schedule_SI(
case 25:
((DCI1A_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->mcs = mcs;
((DCI1A_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4);
((DCI1A_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL,first_rb,4);
((DCI1A_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->type = 1;
((DCI1A_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->vrb_type = 0;
((DCI1A_5MHz_TDD_1_6_t*)BCCH_alloc_pdu)->ndi = 1;
@@ -172,7 +172,7 @@ schedule_SI(
case 50:
((DCI1A_10MHz_TDD_1_6_t*)BCCH_alloc_pdu)->mcs = mcs;
((DCI1A_10MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4);
((DCI1A_10MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL,first_rb,4);
((DCI1A_10MHz_TDD_1_6_t*)BCCH_alloc_pdu)->type = 1;
((DCI1A_10MHz_TDD_1_6_t*)BCCH_alloc_pdu)->vrb_type = 0;
((DCI1A_10MHz_TDD_1_6_t*)BCCH_alloc_pdu)->ndi = 1;
@@ -187,7 +187,7 @@ schedule_SI(
case 100:
((DCI1A_20MHz_TDD_1_6_t*)BCCH_alloc_pdu)->mcs = mcs;
((DCI1A_20MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4);
((DCI1A_20MHz_TDD_1_6_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL,first_rb,4);
((DCI1A_20MHz_TDD_1_6_t*)BCCH_alloc_pdu)->type = 1;
((DCI1A_20MHz_TDD_1_6_t*)BCCH_alloc_pdu)->vrb_type = 0;
((DCI1A_20MHz_TDD_1_6_t*)BCCH_alloc_pdu)->ndi = 1;
@@ -202,10 +202,10 @@ schedule_SI(
}
} else {
switch (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL) {
switch (PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL) {
case 6:
((DCI1A_1_5MHz_FDD_t*)BCCH_alloc_pdu)->mcs = mcs;
((DCI1A_1_5MHz_FDD_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4);
((DCI1A_1_5MHz_FDD_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL,first_rb,4);
((DCI1A_1_5MHz_FDD_t*)BCCH_alloc_pdu)->type = 1;
((DCI1A_1_5MHz_FDD_t*)BCCH_alloc_pdu)->vrb_type = 0;
((DCI1A_1_5MHz_FDD_t*)BCCH_alloc_pdu)->ndi = 1;
@@ -221,7 +221,7 @@ schedule_SI(
case 25:
((DCI1A_5MHz_FDD_t*)BCCH_alloc_pdu)->mcs = mcs;
((DCI1A_5MHz_FDD_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4);
((DCI1A_5MHz_FDD_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL,first_rb,4);
((DCI1A_5MHz_FDD_t*)BCCH_alloc_pdu)->type = 1;
((DCI1A_5MHz_FDD_t*)BCCH_alloc_pdu)->vrb_type = 0;
((DCI1A_5MHz_FDD_t*)BCCH_alloc_pdu)->ndi = 1;
@@ -237,7 +237,7 @@ schedule_SI(
case 50:
((DCI1A_10MHz_FDD_t*)BCCH_alloc_pdu)->mcs = mcs;
((DCI1A_10MHz_FDD_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4);
((DCI1A_10MHz_FDD_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL,first_rb,4);
((DCI1A_10MHz_FDD_t*)BCCH_alloc_pdu)->type = 1;
((DCI1A_10MHz_FDD_t*)BCCH_alloc_pdu)->vrb_type = 0;
((DCI1A_10MHz_FDD_t*)BCCH_alloc_pdu)->ndi = 1;
@@ -253,7 +253,7 @@ schedule_SI(
case 100:
((DCI1A_20MHz_FDD_t*)BCCH_alloc_pdu)->mcs = mcs;
((DCI1A_20MHz_FDD_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL,first_rb,4);
((DCI1A_20MHz_FDD_t*)BCCH_alloc_pdu)->rballoc = mac_xface->computeRIV(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL,first_rb,4);
((DCI1A_20MHz_FDD_t*)BCCH_alloc_pdu)->type = 1;
((DCI1A_20MHz_FDD_t*)BCCH_alloc_pdu)->vrb_type = 0;
((DCI1A_20MHz_FDD_t*)BCCH_alloc_pdu)->ndi = 1;
@@ -296,7 +296,7 @@ schedule_SI(
LOG_D(OPT,"[eNB %d][BCH] Frame %d trace pdu for CC_id %d rnti %x with size %d\n",
module_idP, frameP, CC_id, 0xffff, bcch_sdu_length);
}
if (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.frame_type == TDD) {
if (PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.frame_type == TDD) {
LOG_D(MAC,"[eNB] Frame %d : Scheduling BCCH->DLSCH (TDD) for CC_id %d SI %d bytes (mcs %d, rb 3, TBS %d)\n",
frameP,
CC_id,
openair2/LAYER2/MAC/eNB_scheduler_dlsch.c
+9 -17
View File
@@ -544,17 +544,9 @@ schedule_ue_spec(
eNB_UE_stats->DL_cqi[0], MIN_CQI_VALUE, MAX_CQI_VALUE);
*/
eNB_UE_stats->dlsch_mcs1 = cqi_to_mcs[eNB_UE_stats->DL_cqi[0]];
eNB_UE_stats->dlsch_mcs1 = cmin(eNB_UE_stats->dlsch_mcs1, openair_daq_vars.target_ue_dl_mcs);
eNB_UE_stats->dlsch_mcs1 = eNB_UE_stats->dlsch_mcs1;//cmin(eNB_UE_stats->dlsch_mcs1, openair_daq_vars.target_ue_dl_mcs);
#ifdef EXMIMO
if (mac_xface->get_transmission_mode(module_idP,CC_id, rnti)==5) {
eNB_UE_stats->dlsch_mcs1 = cmin(eNB_UE_stats->dlsch_mcs1,16);
}
#endif
// store stats
UE_list->eNB_UE_stats[CC_id][UE_id].dl_cqi= eNB_UE_stats->DL_cqi[0];
@@ -1537,7 +1529,7 @@ fill_DLSCH_dci(
/// Synchronizing rballoc with rballoc_sub
for(i=0; i<PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RBG; i++) {
for(i=0; i<PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RBG; i++) {
rballoc_sub[i] = UE_list->UE_template[CC_id][UE_id].rballoc_subband[harq_pid][i];
}
@@ -1549,8 +1541,8 @@ fill_DLSCH_dci(
case 2:
LOG_D(MAC,"[eNB %d] CC_id %d Adding UE %d spec DCI for %d PRBS \n",module_idP, CC_id, UE_id, nb_rb);
if (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.frame_type == TDD) {
switch (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL) {
if (PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.frame_type == TDD) {
switch (PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL) {
case 6:
((DCI1_1_5MHz_TDD_t*)DLSCH_dci)->rballoc = allocate_prbs_sub(nb_rb,rballoc_sub);
((DCI1_1_5MHz_TDD_t*)DLSCH_dci)->rah = 0;
@@ -1589,7 +1581,7 @@ fill_DLSCH_dci(
} else {
switch(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL) {
switch(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL) {
case 6:
((DCI1_1_5MHz_FDD_t*)DLSCH_dci)->rballoc = allocate_prbs_sub(nb_rb,rballoc_sub);
((DCI1_1_5MHz_FDD_t*)DLSCH_dci)->rah = 0;
@@ -1642,8 +1634,8 @@ fill_DLSCH_dci(
LOG_D(MAC,"[eNB %d] CC_id %d Adding Format 2A UE %d spec DCI for %d PRBS (rb alloc: %x) \n",
module_idP, CC_id, UE_id, nb_rb);
if (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.frame_type == TDD) {
switch (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL) {
if (PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.frame_type == TDD) {
switch (PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL) {
case 6:
((DCI2A_1_5MHz_2A_TDD_t*)DLSCH_dci)->rballoc = allocate_prbs_sub(nb_rb,rballoc_sub);
((DCI2A_1_5MHz_2A_TDD_t*)DLSCH_dci)->rah = 0;
@@ -1682,7 +1674,7 @@ fill_DLSCH_dci(
} else {
switch(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL) {
switch(PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL) {
case 6:
((DCI2A_1_5MHz_2A_FDD_t*)DLSCH_dci)->rballoc = allocate_prbs_sub(nb_rb,rballoc_sub);
((DCI2A_1_5MHz_2A_FDD_t*)DLSCH_dci)->rah = 0;
@@ -1844,7 +1836,7 @@ update_ul_dci(
int i;
DCI0_5MHz_TDD_1_6_t *ULSCH_dci = NULL;;
if (mac_xface->lte_frame_parms->frame_type == TDD) {
if (mac_xface->frame_parms->frame_type == TDD) {
for (i=0; i<DCI_pdu->Num_common_dci+DCI_pdu->Num_ue_spec_dci; i++) {
ULSCH_dci = (DCI0_5MHz_TDD_1_6_t *)DCI_pdu->dci_alloc[i].dci_pdu;
openair2/LAYER2/MAC/eNB_scheduler_mch.c
+12 -12
View File
@@ -130,7 +130,7 @@ int schedule_MBMS(module_id_t module_idP, uint8_t CC_id, frame_t frameP, sub_fra
// Check if the subframeP is for MSI, MCCH or MTCHs and Set the correspoding flag to 1
switch (subframeP) {
case 1:
if (mac_xface->lte_frame_parms->frame_type == FDD) {
if (mac_xface->frame_parms->frame_type == FDD) {
if ((eNB_mac_inst[module_idP].common_channels[CC_id].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF1) == MBSFN_FDD_SF1) {
if (msi_pos == 1) {
msi_flag = 1;
@@ -148,7 +148,7 @@ int schedule_MBMS(module_id_t module_idP, uint8_t CC_id, frame_t frameP, sub_fra
break;
case 2:
if (mac_xface->lte_frame_parms->frame_type == FDD) {
if (mac_xface->frame_parms->frame_type == FDD) {
if ((eNB_mac_inst[module_idP].common_channels[CC_id].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF2) == MBSFN_FDD_SF2) {
if (msi_pos == 2) {
msi_flag = 1;
@@ -166,7 +166,7 @@ int schedule_MBMS(module_id_t module_idP, uint8_t CC_id, frame_t frameP, sub_fra
break;
case 3:
if (mac_xface->lte_frame_parms->frame_type == TDD) { // TDD
if (mac_xface->frame_parms->frame_type == TDD) { // TDD
if ((eNB_mac_inst[module_idP].common_channels[CC_id].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_TDD_SF3) == MBSFN_TDD_SF3) {
if (msi_pos == 1) {
msi_flag = 1;
@@ -197,7 +197,7 @@ int schedule_MBMS(module_id_t module_idP, uint8_t CC_id, frame_t frameP, sub_fra
break;
case 4:
if (mac_xface->lte_frame_parms->frame_type == TDD) {
if (mac_xface->frame_parms->frame_type == TDD) {
if ((eNB_mac_inst[module_idP].common_channels[CC_id].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_TDD_SF4) == MBSFN_TDD_SF4) {
if (msi_pos == 2) {
msi_flag = 1;
@@ -215,7 +215,7 @@ int schedule_MBMS(module_id_t module_idP, uint8_t CC_id, frame_t frameP, sub_fra
break;
case 6:
if (mac_xface->lte_frame_parms->frame_type == FDD) {
if (mac_xface->frame_parms->frame_type == FDD) {
if ((eNB_mac_inst[module_idP].common_channels[CC_id].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF6) == MBSFN_FDD_SF6) {
if (msi_pos == 4) {
msi_flag = 1;
@@ -233,7 +233,7 @@ int schedule_MBMS(module_id_t module_idP, uint8_t CC_id, frame_t frameP, sub_fra
break;
case 7:
if (mac_xface->lte_frame_parms->frame_type == TDD) { // TDD
if (mac_xface->frame_parms->frame_type == TDD) { // TDD
if ((eNB_mac_inst[module_idP].common_channels[CC_id].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_TDD_SF7) == MBSFN_TDD_SF7) {
if (msi_pos == 3) {
msi_flag = 1;
@@ -264,7 +264,7 @@ int schedule_MBMS(module_id_t module_idP, uint8_t CC_id, frame_t frameP, sub_fra
break;
case 8:
if (mac_xface->lte_frame_parms->frame_type == TDD) { //TDD
if (mac_xface->frame_parms->frame_type == TDD) { //TDD
if ((eNB_mac_inst[module_idP].common_channels[CC_id].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_TDD_SF8) == MBSFN_TDD_SF8) {
if (msi_pos == 4) {
msi_flag = 1;
@@ -295,7 +295,7 @@ int schedule_MBMS(module_id_t module_idP, uint8_t CC_id, frame_t frameP, sub_fra
break;
case 9:
if (mac_xface->lte_frame_parms->frame_type == TDD) {
if (mac_xface->frame_parms->frame_type == TDD) {
if ((eNB_mac_inst[module_idP].common_channels[CC_id].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_TDD_SF9) == MBSFN_TDD_SF9) {
if (msi_pos == 5) {
msi_flag = 1;
@@ -412,7 +412,7 @@ int schedule_MBMS(module_id_t module_idP, uint8_t CC_id, frame_t frameP, sub_fra
header_len_mcch = 2;
if (mac_xface->lte_frame_parms->frame_type == TDD) {
if (mac_xface->frame_parms->frame_type == TDD) {
LOG_D(MAC,"[eNB %d] CC_id %d Frame %d subframeP %d: Scheduling MCCH->MCH (TDD) for MCCH message %d bytes (mcs %d )\n",
module_idP, CC_id,
frameP,subframeP,
@@ -444,7 +444,7 @@ int schedule_MBMS(module_id_t module_idP, uint8_t CC_id, frame_t frameP, sub_fra
}
}
TBS = mac_xface->get_TBS_DL(eNB_mac_inst[module_idP].common_channels[CC_id].MCH_pdu.mcs, mac_xface->lte_frame_parms->N_RB_DL);
TBS = mac_xface->get_TBS_DL(eNB_mac_inst[module_idP].common_channels[CC_id].MCH_pdu.mcs, mac_xface->frame_parms->N_RB_DL);
#ifdef Rel10
// do not let mcch and mtch multiplexing when relaying is active
// for sync area 1, so not transmit data
@@ -455,10 +455,10 @@ int schedule_MBMS(module_id_t module_idP, uint8_t CC_id, frame_t frameP, sub_fra
if (mtch_flag == 1) {
// Calculate TBS
/* if ((msi_flag==1) || (mcch_flag==1)) {
TBS = mac_xface->get_TBS(mcch_mcs, mac_xface->lte_frame_parms->N_RB_DL);
TBS = mac_xface->get_TBS(mcch_mcs, mac_xface->frame_parms->N_RB_DL);
}
else { // only MTCH in this subframeP
TBS = mac_xface->get_TBS(eNB_mac_inst[module_idP].pmch_Config[0]->dataMCS_r9, mac_xface->lte_frame_parms->N_RB_DL);
TBS = mac_xface->get_TBS(eNB_mac_inst[module_idP].pmch_Config[0]->dataMCS_r9, mac_xface->frame_parms->N_RB_DL);
}
// get MTCH data from RLC (like for DTCH)
openair2/LAYER2/MAC/eNB_scheduler_primitives.c
+71 -13
View File
@@ -338,6 +338,22 @@ int rrc_mac_remove_ue(module_id_t mod_idP,rnti_t rntiP)
mac_phy_remove_ue(mod_idP,rntiP);
// check if this has an RA process active
RA_TEMPLATE *RA_template;
for (i=0;i<NB_RA_PROC_MAX;i++) {
RA_template = (RA_TEMPLATE *)&eNB_mac_inst[mod_idP].common_channels[pCC_id].RA_template[i];
if ((RA_template->RA_active == TRUE) &&
(RA_template->rnti == rntiP)){
RA_template->RA_active=FALSE;
RA_template->generate_rar=0;
RA_template->generate_Msg4=0;
RA_template->wait_ack_Msg4=0;
RA_template->timing_offset=0;
RA_template->RRC_timer=20;
RA_template->rnti = 0;
break;
}
}
if (ret == 0) {
return (0);
}
@@ -707,7 +723,7 @@ uint32_t allocate_prbs(int UE_id,unsigned char nb_rb, uint32_t *rballoc)
uint32_t rballoc_dci=0;
unsigned char nb_rb_alloc=0;
for (i=0; i<(mac_xface->lte_frame_parms->N_RB_DL-2); i+=2) {
for (i=0; i<(mac_xface->frame_parms->N_RB_DL-2); i+=2) {
if (((*rballoc>>i)&3)==0) {
*rballoc |= (3<<i);
rballoc_dci |= (1<<((12-i)>>1));
@@ -719,10 +735,10 @@ uint32_t allocate_prbs(int UE_id,unsigned char nb_rb, uint32_t *rballoc)
}
}
if ((mac_xface->lte_frame_parms->N_RB_DL&1)==1) {
if ((*rballoc>>(mac_xface->lte_frame_parms->N_RB_DL-1)&1)==0) {
*rballoc |= (1<<(mac_xface->lte_frame_parms->N_RB_DL-1));
rballoc_dci |= 1;//(1<<(mac_xface->lte_frame_parms->N_RB_DL>>1));
if ((mac_xface->frame_parms->N_RB_DL&1)==1) {
if ((*rballoc>>(mac_xface->frame_parms->N_RB_DL-1)&1)==0) {
*rballoc |= (1<<(mac_xface->frame_parms->N_RB_DL-1));
rballoc_dci |= 1;//(1<<(mac_xface->frame_parms->N_RB_DL>>1));
}
}
@@ -769,20 +785,20 @@ uint32_t allocate_prbs_sub(int nb_rb, uint8_t *rballoc)
//uint8_t number_of_subbands=13;
LOG_T(MAC,"*****Check1RBALLOC****: %d%d%d%d (nb_rb %d,N_RBG %d)\n",
rballoc[3],rballoc[2],rballoc[1],rballoc[0],nb_rb,mac_xface->lte_frame_parms->N_RBG);
rballoc[3],rballoc[2],rballoc[1],rballoc[0],nb_rb,mac_xface->frame_parms->N_RBG);
while((nb_rb >0) && (check < mac_xface->lte_frame_parms->N_RBG)) {
while((nb_rb >0) && (check < mac_xface->frame_parms->N_RBG)) {
//printf("rballoc[%d] %d\n",check,rballoc[check]);
if(rballoc[check] == 1) {
rballoc_dci |= (1<<((mac_xface->lte_frame_parms->N_RBG-1)-check));
rballoc_dci |= (1<<((mac_xface->frame_parms->N_RBG-1)-check));
switch (mac_xface->lte_frame_parms->N_RB_DL) {
switch (mac_xface->frame_parms->N_RB_DL) {
case 6:
nb_rb--;
break;
case 25:
if ((check == mac_xface->lte_frame_parms->N_RBG-1)) {
if ((check == mac_xface->frame_parms->N_RBG-1)) {
nb_rb--;
} else {
nb_rb-=2;
@@ -791,7 +807,7 @@ uint32_t allocate_prbs_sub(int nb_rb, uint8_t *rballoc)
break;
case 50:
if ((check == mac_xface->lte_frame_parms->N_RBG-1)) {
if ((check == mac_xface->frame_parms->N_RBG-1)) {
nb_rb-=2;
} else {
nb_rb-=3;
@@ -822,7 +838,7 @@ int get_nb_subband(void)
int nb_sb=0;
switch (mac_xface->lte_frame_parms->N_RB_DL) {
switch (mac_xface->frame_parms->N_RB_DL) {
case 6:
nb_sb=0;
break;
@@ -960,6 +976,46 @@ int get_nCCE_offset(int *CCE_table,
}
}
void dump_CCE_table(int *CCE_table,const int nCCE,const unsigned short rnti,const int subframe,int L) {
int nb_candidates = 0,i;
unsigned int Yk;
for (i=0;i<nCCE;i++) {
printf("%1d.",CCE_table[i]);
if ((i&7) == 0)
printf("\n");
}
Yk = (unsigned int)rnti;
for (i=0; i<=subframe; i++)
Yk = (Yk*39827)%65537;
Yk = Yk % (nCCE/L);
switch (L) {
case 1:
case 2:
nb_candidates = 6;
break;
case 4:
case 8:
nb_candidates = 2;
break;
default:
DevParam(L, nCCE, rnti);
break;
}
printf("rnti %x, Yk*L = %d, nCCE %d (nCCE/L %d),nb_cand*L %d\n",rnti,Yk*L,nCCE,nCCE/L,nb_candidates*L);
}
// Allocate the CCEs
int allocate_CCEs(int module_idP,
int CC_idP,
@@ -1011,12 +1067,14 @@ try_again:
subframeP,dci_alloc->rnti);
for (j=0;j<=i;j++){
LOG_I(MAC,"DCI %d/%d (%d,%d) : rnti %x dci format %d, aggreg %d nCCE %d / %d (num_pdcch_symbols %d)\n",
i,DCI_pdu->Num_common_dci+DCI_pdu->Num_ue_spec_dci,
j,DCI_pdu->Num_common_dci+DCI_pdu->Num_ue_spec_dci,
DCI_pdu->Num_common_dci,DCI_pdu->Num_ue_spec_dci,
DCI_pdu->dci_alloc[j].rnti,DCI_pdu->dci_alloc[j].format,
1<<DCI_pdu->dci_alloc[j].L,
nCCE,nCCE_max,DCI_pdu->num_pdcch_symbols);
}
dump_CCE_table(CCE_table,nCCE_max,subframeP,dci_alloc->rnti,dci_alloc->L);
goto failed;
}
DCI_pdu->num_pdcch_symbols++;
openair2/LAYER2/MAC/eNB_scheduler_ulsch.c
+4 -4
View File
@@ -808,14 +808,14 @@ void schedule_ulsch_rnti(module_id_t module_idP,
UE_list->eNB_UE_stats[CC_id][UE_id].normalized_rx_power=normalized_rx_power;
UE_list->eNB_UE_stats[CC_id][UE_id].target_rx_power=target_rx_power;
UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_mcs1=UE_template->pre_assigned_mcs_ul;
mcs = cmin (UE_template->pre_assigned_mcs_ul, openair_daq_vars.target_ue_ul_mcs); // adjust, based on user-defined MCS
mcs = UE_template->pre_assigned_mcs_ul;//cmin (UE_template->pre_assigned_mcs_ul, openair_daq_vars.target_ue_ul_mcs); // adjust, based on user-defined MCS
if ((cqi_req==1) && (mcs>19)) {
mcs=19;
}
if (UE_template->pre_allocated_rb_table_index_ul >=0) {
rb_table_index=UE_template->pre_allocated_rb_table_index_ul;
} else {
mcs=cmin (10, openair_daq_vars.target_ue_ul_mcs);
mcs=10;//cmin (10, openair_daq_vars.target_ue_ul_mcs);
rb_table_index=5; // for PHR
}
@@ -1162,7 +1162,7 @@ void schedule_ulsch_cba_rnti(module_id_t module_idP, unsigned char cooperation_f
required_rbs[cba_group] = 0;
num_cba_resources[cba_group]=0;
active_UEs[cba_group]=0;
mcs[cba_group]=openair_daq_vars.target_ue_ul_mcs;
mcs[cba_group]=10;//openair_daq_vars.target_ue_ul_mcs;
}
//LOG_D(MAC, "[eNB ] CBA granted ues are %d\n",granted_UEs );
@@ -1210,7 +1210,7 @@ void schedule_ulsch_cba_rnti(module_id_t module_idP, unsigned char cooperation_f
}
}
mcs[cba_group]= cmin(mcs[cba_group],openair_daq_vars.target_ue_ul_mcs);
mcs[cba_group]= mcs[cba_group];//cmin(mcs[cba_group],openair_daq_vars.target_ue_ul_mcs);
if (available_rbs < min_rb_unit )
break;
openair2/LAYER2/MAC/lte_transport_init.c
+3 -3
View File
@@ -1,6 +1,6 @@
#define UL_RB_ALLOC mac_xface->computeRIV(mac_xface->lte_frame_parms->N_RB_UL,0,24)
#define BCCH_RB_ALLOC mac_xface->computeRIV(mac_xface->lte_frame_parms->N_RB_UL,0,4)
#define RA_RB_ALLOC mac_xface->computeRIV(mac_xface->lte_frame_parms->N_RB_UL,0,4)
#define UL_RB_ALLOC mac_xface->computeRIV(mac_xface->frame_parms->N_RB_UL,0,24)
#define BCCH_RB_ALLOC mac_xface->computeRIV(mac_xface->frame_parms->N_RB_UL,0,4)
#define RA_RB_ALLOC mac_xface->computeRIV(mac_xface->frame_parms->N_RB_UL,0,4)
#define DLSCH_RB_ALLOC 0x1fff
#include "extern.h"
openair2/LAYER2/MAC/main.c
+7 -6
View File
@@ -196,8 +196,8 @@ int mac_top_init(int eMBMS_active, char *uecap_xer, uint8_t cba_group_active, ui
RA_template = (RA_TEMPLATE *)&eNB_mac_inst[i].common_channels[CC_id].RA_template[0];
for (j=0; j<NB_RA_PROC_MAX; j++) {
if (mac_xface->lte_frame_parms->frame_type == TDD) {
switch (mac_xface->lte_frame_parms->N_RB_DL) {
if (mac_xface->frame_parms->frame_type == TDD) {
switch (mac_xface->frame_parms->N_RB_DL) {
case 6:
size_bytes1 = sizeof(DCI1A_1_5MHz_TDD_1_6_t);
size_bytes2 = sizeof(DCI1A_1_5MHz_TDD_1_6_t);
@@ -235,7 +235,7 @@ int mac_top_init(int eMBMS_active, char *uecap_xer, uint8_t cba_group_active, ui
}
} else {
switch (mac_xface->lte_frame_parms->N_RB_DL) {
switch (mac_xface->frame_parms->N_RB_DL) {
case 6:
size_bytes1 = sizeof(DCI1A_1_5MHz_FDD_t);
size_bytes2 = sizeof(DCI1A_1_5MHz_FDD_t);
@@ -298,7 +298,7 @@ int mac_top_init(int eMBMS_active, char *uecap_xer, uint8_t cba_group_active, ui
//ICIC init param
#ifdef ICIC
uint8_t SB_size;
SB_size=mac_xface->get_SB_size(mac_xface->lte_frame_parms->N_RB_DL);
SB_size=mac_xface->get_SB_size(mac_xface->frame_parms->N_RB_DL);
srand (time(NULL));
@@ -437,7 +437,7 @@ int l2_init(LTE_DL_FRAME_PARMS *frame_parms,int eMBMS_active, char *uecap_xer,ui
mac_xface->UL_failure_indication = UL_failure_indication;
mac_xface->rx_sdu = rx_sdu;
mac_xface->get_dlsch_sdu = get_dlsch_sdu;
mac_xface->get_eNB_UE_stats = get_eNB_UE_stats;
mac_xface->get_eNB_UE_stats = get_UE_stats;
mac_xface->get_transmission_mode = get_transmission_mode;
mac_xface->get_rballoc = get_rballoc;
mac_xface->get_nb_rb = conv_nprb;
@@ -452,6 +452,7 @@ int l2_init(LTE_DL_FRAME_PARMS *frame_parms,int eMBMS_active, char *uecap_xer,ui
LOG_I(MAC,"[MAIN] init UE MAC functions \n");
mac_xface->ue_decode_si = ue_decode_si;
mac_xface->ue_decode_p = ue_decode_p;
mac_xface->ue_send_sdu = ue_send_sdu;
#ifdef Rel10
mac_xface->ue_send_mch_sdu = ue_send_mch_sdu;
@@ -466,7 +467,7 @@ int l2_init(LTE_DL_FRAME_PARMS *frame_parms,int eMBMS_active, char *uecap_xer,ui
LOG_I(MAC,"[MAIN] PHY Frame configuration \n");
mac_xface->lte_frame_parms = frame_parms;
mac_xface->frame_parms = frame_parms;
mac_xface->get_ue_active_harq_pid = get_ue_active_harq_pid;
mac_xface->get_PL = get_PL;
openair2/LAYER2/MAC/pre_processor.c
+6 -6
View File
@@ -150,7 +150,7 @@ void assign_rbs_required (module_id_t Mod_id,
*/
eNB_UE_stats[CC_id]->dlsch_mcs1=cqi_to_mcs[eNB_UE_stats[CC_id]->DL_cqi[0]];
eNB_UE_stats[CC_id]->dlsch_mcs1 = cmin(eNB_UE_stats[CC_id]->dlsch_mcs1,openair_daq_vars.target_ue_dl_mcs);
eNB_UE_stats[CC_id]->dlsch_mcs1 = eNB_UE_stats[CC_id]->dlsch_mcs1;//cmin(eNB_UE_stats[CC_id]->dlsch_mcs1,openair_daq_vars.target_ue_dl_mcs);
}
@@ -170,7 +170,7 @@ void assign_rbs_required (module_id_t Mod_id,
/*
if ((mac_get_rrc_status(Mod_id,1,UE_id) < RRC_RECONFIGURED)){ // If we still don't have a default radio bearer
nb_rbs_required[pCCid][UE_id] = PHY_vars_eNB_g[Mod_id][pCCid]->lte_frame_parms.N_RB_DL;
nb_rbs_required[pCCid][UE_id] = PHY_vars_eNB_g[Mod_id][pCCid]->frame_parms.N_RB_DL;
continue;
}
*/
@@ -621,8 +621,8 @@ void dlsch_scheduler_pre_processor (module_id_t Mod_id,
if ((j == N_RBG[CC_id]-1) &&
((PHY_vars_eNB_g[Mod_id][CC_id]->lte_frame_parms.N_RB_DL == 25) ||
(PHY_vars_eNB_g[Mod_id][CC_id]->lte_frame_parms.N_RB_DL == 50))) {
((PHY_vars_eNB_g[Mod_id][CC_id]->frame_parms.N_RB_DL == 25) ||
(PHY_vars_eNB_g[Mod_id][CC_id]->frame_parms.N_RB_DL == 50))) {
nb_rbs_required_remaining[CC_id][UE_id] = nb_rbs_required_remaining[CC_id][UE_id] - min_rb_unit[CC_id]+1;
ue_sched_ctl->pre_nb_available_rbs[CC_id] = ue_sched_ctl->pre_nb_available_rbs[CC_id] + min_rb_unit[CC_id]-1;
@@ -731,7 +731,7 @@ void dlsch_scheduler_pre_processor_reset (int module_idP,
UE_sched_ctrl *ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
rnti_t rnti = UE_RNTI(module_idP,UE_id);
uint8_t *vrb_map = eNB_mac_inst[module_idP].common_channels[CC_id].vrb_map;
int RBGsize = PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL/N_RBG;
int RBGsize = PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL/N_RBG;
#ifdef SF05_LIMIT
//int subframe05_limit=0;
int sf05_upper=-1,sf05_lower=-1;
@@ -748,7 +748,7 @@ void dlsch_scheduler_pre_processor_reset (int module_idP,
// WE SHOULD PROTECT the eNB_UE_stats with a mutex here ...
ue_sched_ctl->ta_timer = 20; // wait 20 subframes before taking TA measurement from PHY
switch (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL) {
switch (PHY_vars_eNB_g[module_idP][CC_id]->frame_parms.N_RB_DL) {
case 6:
ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update;
break;
openair2/LAYER2/MAC/proto.h
+3 -1
View File
@@ -357,6 +357,8 @@ void mac_out_of_sync_ind(module_id_t module_idP, frame_t frameP, uint16_t CH_ind
void ue_decode_si(module_id_t module_idP, int CC_id,frame_t frame, uint8_t CH_index, void *pdu, uint16_t len);
void ue_decode_p(module_id_t module_idP, int CC_id,frame_t frame, uint8_t CH_index, void *pdu, uint16_t len);
void ue_send_sdu(module_id_t module_idP, uint8_t CC_id,frame_t frame, uint8_t *sdu,uint16_t sdu_len,uint8_t CH_index);
@@ -758,7 +760,7 @@ rrc_get_estimated_ue_distance(
const int CC_idP,
const uint8_t loc_typeP);
void fill_dci(DCI_PDU *DCI_pdu, uint8_t sched_subframe, PHY_VARS_eNB *phy_vars_eNB);
void fill_dci(DCI_PDU *DCI_pdu, PHY_VARS_eNB *phy_vars_eNB,eNB_rxtx_proc_t *proc);
#endif
/** @}*/
openair2/LAYER2/MAC/ra_procedures.c
+2 -2
View File
@@ -223,13 +223,13 @@ void get_prach_resources(module_id_t module_idP,
// choose random PRACH resource in TDD
if (UE_mac_inst[module_idP].tdd_Config) {
num_prach = mac_xface->get_num_prach_tdd(mac_xface->lte_frame_parms);
num_prach = mac_xface->get_num_prach_tdd(mac_xface->frame_parms);
if ((num_prach>0) && (num_prach<6)) {
UE_mac_inst[module_idP].RA_prach_resources.ra_TDD_map_index = (taus()%num_prach);
}
f_id = mac_xface->get_fid_prach_tdd(mac_xface->lte_frame_parms,
f_id = mac_xface->get_fid_prach_tdd(mac_xface->frame_parms,
UE_mac_inst[module_idP].RA_prach_resources.ra_TDD_map_index);
}
openair2/LAYER2/MAC/ue_procedures.c
+43 -8
View File
@@ -478,6 +478,41 @@ void ue_decode_si(module_id_t module_idP,int CC_id,frame_t frameP, uint8_t eNB_i
}
}
void ue_decode_p(module_id_t module_idP,int CC_id,frame_t frameP, uint8_t eNB_index, void *pdu,uint16_t len)
{
start_meas(&UE_mac_inst[module_idP].rx_p);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_DECODE_PCCH, VCD_FUNCTION_IN);
LOG_D(MAC,"[UE %d] Frame %d Sending Paging message to RRC (LCID Id %d,len %d)\n",module_idP,frameP,PCCH,len);
mac_rrc_data_ind(module_idP,
CC_id,
frameP,0, // unknown subframe
P_RNTI,
PCCH,
(uint8_t *)pdu,
len,
ENB_FLAG_NO,
eNB_index,
0);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_DECODE_PCCH, VCD_FUNCTION_OUT);
stop_meas(&UE_mac_inst[module_idP].rx_p);
if (opt_enabled == 1) {
trace_pdu(0,
(uint8_t *)pdu,
len,
module_idP,
4,
P_RNTI,
UE_mac_inst[module_idP].subframe,
0,
0);
LOG_D(OPT,"[UE %d][BCH] Frame %d trace pdu for CC_id %d rnti %x with size %d\n",
module_idP, frameP, CC_id, P_RNTI, len);
}
}
#ifdef Rel10
unsigned char *parse_mch_header(unsigned char *mac_header,
unsigned char *num_sdu,
@@ -681,7 +716,7 @@ int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_
// Check if the subframe is for MSI, MCCH or MTCHs and Set the correspoding flag to 1
switch (subframe) {
case 1:
if (mac_xface->lte_frame_parms->frame_type == FDD) {
if (mac_xface->frame_parms->frame_type == FDD) {
if ((UE_mac_inst[module_idP].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF1) == MBSFN_FDD_SF1) {
if (msi_pos == 1) {
msi_flag = 1;
@@ -699,7 +734,7 @@ int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_
break;
case 2:
if (mac_xface->lte_frame_parms->frame_type == FDD) {
if (mac_xface->frame_parms->frame_type == FDD) {
if ((UE_mac_inst[module_idP].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF2) == MBSFN_FDD_SF2) {
if (msi_pos == 2) {
msi_flag = 1;
@@ -717,7 +752,7 @@ int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_
break;
case 3:
if (mac_xface->lte_frame_parms->frame_type == TDD) { // TDD
if (mac_xface->frame_parms->frame_type == TDD) { // TDD
if ((UE_mac_inst[module_idP].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_TDD_SF3) == MBSFN_TDD_SF3) {
if (msi_pos == 1) {
msi_flag = 1;
@@ -748,7 +783,7 @@ int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_
break;
case 4:
if (mac_xface->lte_frame_parms->frame_type == TDD) {
if (mac_xface->frame_parms->frame_type == TDD) {
if ((UE_mac_inst[module_idP].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_TDD_SF4) == MBSFN_TDD_SF4) {
if (msi_pos == 2) {
msi_flag = 1;
@@ -766,7 +801,7 @@ int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_
break;
case 6:
if (mac_xface->lte_frame_parms->frame_type == FDD) {
if (mac_xface->frame_parms->frame_type == FDD) {
if ((UE_mac_inst[module_idP].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF6) == MBSFN_FDD_SF6) {
if (msi_pos == 4) {
msi_flag = 1;
@@ -784,7 +819,7 @@ int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_
break;
case 7:
if (mac_xface->lte_frame_parms->frame_type == TDD) { // TDD
if (mac_xface->frame_parms->frame_type == TDD) { // TDD
if ((UE_mac_inst[module_idP].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_TDD_SF7) == MBSFN_TDD_SF7) {
if (msi_pos == 3) {
msi_flag = 1;
@@ -815,7 +850,7 @@ int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_
break;
case 8:
if (mac_xface->lte_frame_parms->frame_type == TDD) { //TDD
if (mac_xface->frame_parms->frame_type == TDD) { //TDD
if ((UE_mac_inst[module_idP].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_TDD_SF8) == MBSFN_TDD_SF8) {
if (msi_pos == 4) {
msi_flag = 1;
@@ -846,7 +881,7 @@ int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_
break;
case 9:
if (mac_xface->lte_frame_parms->frame_type == TDD) {
if (mac_xface->frame_parms->frame_type == TDD) {
if ((UE_mac_inst[module_idP].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_TDD_SF9) == MBSFN_TDD_SF9) {
if (msi_pos == 5) {
msi_flag = 1;
openair2/PHY_INTERFACE/defs.h
+4 -1
View File
@@ -117,6 +117,9 @@ typedef struct {
/// Send a received SI sdu
void (*ue_decode_si)(module_id_t Mod_id,int CC_id,frame_t frameP, uint8_t CH_index, void *pdu, uint16_t len);
/// Send a received Paging sdu
void (*ue_decode_p)(module_id_t Mod_id,int CC_id,frame_t frameP, uint8_t CH_index, void *pdu, uint16_t len);
/// Send a received DLSCH sdu to MAC
void (*ue_send_sdu)(module_id_t Mod_id,uint8_t CC_id,frame_t frameP,uint8_t *sdu,uint16_t sdu_len,uint8_t CH_index);
@@ -303,7 +306,7 @@ typedef struct {
unsigned char cluster_head_index;
/// PHY Frame Configuration
LTE_DL_FRAME_PARMS *lte_frame_parms;
LTE_DL_FRAME_PARMS *frame_parms;
uint8_t (*get_prach_prb_offset)(LTE_DL_FRAME_PARMS *frame_parms, uint8_t tdd_mapindex, uint16_t Nf);
openair2/RRC/LITE/L2_interface.c
+14 -9
View File
@@ -262,10 +262,10 @@ mac_rrc_data_req(
#endif //Rel10
} else { //This is an UE
#ifdef DEBUG_RRC
LOG_D(RRC,"[UE %d] Frame %d Filling CCCH SRB_ID %d\n",Mod_idP,frameP,Srb_id);
LOG_D(RRC,"[UE %d] Frame %d buffer_pP status %d,\n",Mod_idP,frameP, UE_rrc_inst[Mod_idP].Srb0[eNB_index].Tx_buffer.payload_size);
#endif
if( (UE_rrc_inst[Mod_idP].Srb0[eNB_index].Tx_buffer.payload_size > 0) ) {
@@ -368,6 +368,10 @@ mac_rrc_data_ind(
#endif
}
if(srb_idP == PCCH) {
LOG_D(RRC,"[UE %d] Received SDU for PCCH on SRB %d from eNB %d\n",module_idP,srb_idP,eNB_indexP);
decode_PCCH_DLSCH_Message(&ctxt,eNB_indexP,(uint8_t*)sduP,sdu_lenP);
}
if((srb_idP & RAB_OFFSET) == CCCH) {
if (sdu_lenP>0) {
LOG_T(RRC,"[UE %d] Received SDU for CCCH on SRB %d from eNB %d\n",module_idP,srb_idP & RAB_OFFSET,eNB_indexP);
@@ -648,13 +652,14 @@ void rrc_in_sync_ind(module_id_t Mod_idP, frame_t frameP, uint16_t eNB_index)
void rrc_out_of_sync_ind(module_id_t Mod_idP, frame_t frameP, uint16_t eNB_index)
{
//-------------------------------------------------------------------------------------------//
LOG_I(RRC,"[UE %d] Frame %d: OUT OF SYNC FROM eNB %d (T310 active %d : T310 %d, N310 %d, N311 %d)\n ",
Mod_idP,frameP,eNB_index,
UE_rrc_inst[Mod_idP].Info[eNB_index].T300_active,
UE_rrc_inst[Mod_idP].Info[eNB_index].T310_cnt,
UE_rrc_inst[Mod_idP].Info[eNB_index].N310_cnt,
UE_rrc_inst[Mod_idP].Info[eNB_index].N311_cnt);
if (UE_rrc_inst[Mod_idP].Info[eNB_index].N310_cnt>10)
LOG_I(RRC,"[UE %d] Frame %d: OUT OF SYNC FROM eNB %d (T310 active %d : T310 %d, N310 %d, N311 %d)\n ",
Mod_idP,frameP,eNB_index,
UE_rrc_inst[Mod_idP].Info[eNB_index].T300_active,
UE_rrc_inst[Mod_idP].Info[eNB_index].T310_cnt,
UE_rrc_inst[Mod_idP].Info[eNB_index].N310_cnt,
UE_rrc_inst[Mod_idP].Info[eNB_index].N311_cnt);
#if defined(ENABLE_ITTI)
{
MessageDef *message_p;
openair2/RRC/LITE/defs.h
+1
View File
@@ -337,6 +337,7 @@ typedef struct eNB_RRC_UE_s {
#endif
uint32_t ul_failure_timer;
uint32_t ue_release_timer;
uint32_t ue_release_timer_thres;
} eNB_RRC_UE_t;
typedef uid_t ue_uid_t;
openair2/RRC/LITE/proto.h
+6
View File
@@ -342,6 +342,12 @@ int decode_BCCH_DLSCH_Message(
const uint8_t rsrq,
const uint8_t rsrp );
int decode_PCCH_DLSCH_Message(
const protocol_ctxt_t* const ctxt_pP,
const uint8_t eNB_index,
uint8_t* const Sdu,
const uint8_t Sdu_len);
void
ue_meas_filtering(
const protocol_ctxt_t* const ctxt_pP,
openair2/RRC/LITE/rrc_UE.c
+39 -5
View File
@@ -30,6 +30,7 @@
#include "UL-DCCH-Message.h"
#include "DL-DCCH-Message.h"
#include "BCCH-DL-SCH-Message.h"
#include "PCCH-Message.h"
#ifdef Rel10
#include "MCCH-Message.h"
#endif
@@ -2435,6 +2436,39 @@ int decode_BCCH_DLSCH_Message(
return 0;
}
//-----------------------------------------------------------------------------
int decode_PCCH_DLSCH_Message(
const protocol_ctxt_t* const ctxt_pP,
const uint8_t eNB_index,
uint8_t* const Sdu,
const uint8_t Sdu_len)
{
PCCH_Message_t *pcch_message = NULL;
int i;
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_UE_DECODE_PCCH, VCD_FUNCTION_IN );
asn_dec_rval_t dec_rval = uper_decode_complete( NULL,
&asn_DEF_PCCH_Message,
(void **)&pcch_message,
(const void *)Sdu,
Sdu_len );
if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) {
LOG_E( RRC, "[UE %"PRIu8"] Failed to decode PCCH_MESSAGE (%zu bits)\n",
ctxt_pP->module_id,
dec_rval.consumed );
for (i=0;i<Sdu_len;i++)
printf("%02x ",Sdu[i]);
printf("\n");
// free the memory
SEQUENCE_free( &asn_DEF_PCCH_Message, (void*)pcch_message, 1 );
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_UE_DECODE_PCCH, VCD_FUNCTION_OUT );
return -1;
}
return(0);
}
//-----------------------------------------------------------------------------
static int decode_SIB1( const protocol_ctxt_t* const ctxt_pP, const uint8_t eNB_index, const uint8_t rsrq, const uint8_t rsrp )
@@ -3439,7 +3473,7 @@ void ue_meas_filtering( const protocol_ctxt_t* const ctxt_pP, const uint8_t eNB_
UE_rrc_inst[ctxt_pP->module_id].rsrp_db[eNB_offset] =
(dB_fixed_times10(mac_xface->get_RSRP(ctxt_pP->module_id,0,eNB_offset))/10.0) -
mac_xface->get_rx_total_gain_dB(ctxt_pP->module_id,0) -
dB_fixed(mac_xface->lte_frame_parms->N_RB_DL*12);
dB_fixed(mac_xface->frame_parms->N_RB_DL*12);
UE_rrc_inst[ctxt_pP->module_id].rsrp_db_filtered[eNB_offset] =
(1.0-a)*UE_rrc_inst[ctxt_pP->module_id].rsrp_db_filtered[eNB_offset] +
a*UE_rrc_inst[ctxt_pP->module_id].rsrp_db[eNB_offset];
@@ -3450,7 +3484,7 @@ void ue_meas_filtering( const protocol_ctxt_t* const ctxt_pP, const uint8_t eNB_
LOG_D(RRC,"RSRP_dBm: %3.2f \n",(dB_fixed_times10(mac_xface->get_RSRP(ctxt_pP->module_id,0,eNB_offset))/10.0));
LOG_D(RRC,"gain_loss_dB: %d \n",mac_xface->get_rx_total_gain_dB(ctxt_pP->module_id,0));
LOG_D(RRC,"gain_fixed_dB: %d \n",dB_fixed(mac_xface->lte_frame_parms->N_RB_DL*12));
LOG_D(RRC,"gain_fixed_dB: %d \n",dB_fixed(mac_xface->frame_parms->N_RB_DL*12));
LOG_D(PHY,"[UE %d] Frame %d, RRC Measurements => rssi %3.1f dBm (digital: %3.1f dB)\n",
ctxt_pP->module_id,
ctxt_pP->frame,
@@ -3708,7 +3742,7 @@ static uint8_t check_trigger_meas_event(
TimeToTrigger_t ttt )
{
uint8_t eNB_offset;
uint8_t currentCellIndex = mac_xface->lte_frame_parms->Nid_cell;
uint8_t currentCellIndex = mac_xface->frame_parms->Nid_cell;
uint8_t tmp_offset;
LOG_I(RRC,"[UE %d] ofn(%d) ocn(%d) hys(%d) ofs(%d) ocs(%d) a3_offset(%d) ttt(%d) rssi %3.1f\n",
@@ -3741,9 +3775,9 @@ static uint8_t check_trigger_meas_event(
LOG_D(RRC,"[UE %d] Frame %d eNB %d: Handover triggered: targetCellId: %d currentCellId: %d eNB_offset: %d rsrp source: %3.1f rsrp target: %3.1f\n", \
ue_mod_idP, frameP, eNB_index,
UE_rrc_inst->HandoverInfoUe.targetCellId,ue_cnx_index,eNB_offset,
(dB_fixed_times10(UE_rrc_inst[ue_mod_idP].rsrp_db[0])/10.0)-mac_xface->get_rx_total_gain_dB(ue_mod_idP,0)-dB_fixed(mac_xface->lte_frame_parms->N_RB_DL*12),
(dB_fixed_times10(UE_rrc_inst[ue_mod_idP].rsrp_db[0])/10.0)-mac_xface->get_rx_total_gain_dB(ue_mod_idP,0)-dB_fixed(mac_xface->frame_parms->N_RB_DL*12),
(dB_fixed_times10(UE_rrc_inst[ue_mod_idP].rsrp_db[eNB_offset])/10.0)-mac_xface->get_rx_total_gain_dB(ue_mod_idP,
0)-dB_fixed(mac_xface->lte_frame_parms->N_RB_DL*12));
0)-dB_fixed(mac_xface->frame_parms->N_RB_DL*12));
UE_rrc_inst->Info[0].handoverTarget = eNB_offset;
//LOG_D(RRC,"PHY_ID: %d \n",UE_rrc_inst->HandoverInfoUe.targetCellId);
return 1;
openair2/RRC/LITE/rrc_common.c
+15 -2
View File
@@ -496,6 +496,19 @@ rrc_rx_tx(
// check for UL failure
RB_FOREACH(ue_context_p, rrc_ue_tree_s, &(eNB_rrc_inst[ctxt_pP->module_id].rrc_ue_head)) {
if ((ctxt_pP->frame == 0) && (ctxt_pP->subframe==0)) {
if (ue_context_p->ue_context.Initialue_identity_s_TMSI.presence == TRUE) {
LOG_I(RRC,"UE rnti %x:S-TMSI %x failure timer %d/20000\n",
ue_context_p->ue_context.rnti,
ue_context_p->ue_context.Initialue_identity_s_TMSI.m_tmsi,
ue_context_p->ue_context.ul_failure_timer);
}
else {
LOG_I(RRC,"UE rnti %x failure timer %d/20000\n",
ue_context_p->ue_context.rnti,
ue_context_p->ue_context.ul_failure_timer);
}
}
if (ue_context_p->ue_context.ul_failure_timer>0) {
ue_context_p->ue_context.ul_failure_timer++;
if (ue_context_p->ue_context.ul_failure_timer >= 20000) {
@@ -507,8 +520,8 @@ rrc_rx_tx(
}
if (ue_context_p->ue_context.ue_release_timer>0) {
ue_context_p->ue_context.ue_release_timer++;
if (ue_context_p->ue_context.ue_release_timer >= 100) {
// remove UE after 10 frames after RRCConnectionRelease is triggered
if (ue_context_p->ue_context.ue_release_timer >=
ue_context_p->ue_context.ue_release_timer_thres) {
LOG_I(RRC,"Removing UE %x instance\n",ue_context_p->ue_context.rnti);
ue_to_be_removed = ue_context_p;
break;
openair2/RRC/LITE/rrc_eNB.c
+20 -11
View File
@@ -164,7 +164,7 @@ init_SI(
eNB_rrc_inst[ctxt_pP->module_id].carrier[CC_id].sizeof_SIB1 = do_SIB1(
ctxt_pP->module_id,
CC_id,
mac_xface->lte_frame_parms,
mac_xface->frame_parms,
(uint8_t*)eNB_rrc_inst[ctxt_pP->module_id].carrier[CC_id].SIB1,
&eNB_rrc_inst[ctxt_pP->module_id].carrier[CC_id].siblock1,
&eNB_rrc_inst[ctxt_pP->module_id].carrier[CC_id].sib1
@@ -194,7 +194,7 @@ init_SI(
eNB_rrc_inst[ctxt_pP->module_id].carrier[CC_id].sizeof_SIB23 = do_SIB23(
ctxt_pP->module_id,
CC_id,
mac_xface->lte_frame_parms,
mac_xface->frame_parms,
eNB_rrc_inst[ctxt_pP->module_id].carrier[CC_id].SIB23,
&eNB_rrc_inst[ctxt_pP->module_id].carrier[CC_id].systemInformation,
&eNB_rrc_inst[ctxt_pP->module_id].carrier[CC_id].sib2,
@@ -360,7 +360,7 @@ init_MCCH(
mac_xface->macphy_exit("[RRC][init_MCCH] not enough memory\n");
} else {
eNB_rrc_inst[enb_mod_idP].carrier[CC_id].sizeof_MCCH_MESSAGE[sync_area] = do_MBSFNAreaConfig(enb_mod_idP,
mac_xface->lte_frame_parms,
mac_xface->frame_parms,
sync_area,
(uint8_t *)eNB_rrc_inst[enb_mod_idP].carrier[CC_id].MCCH_MESSAGE[sync_area],
&eNB_rrc_inst[enb_mod_idP].carrier[CC_id].mcch,
@@ -542,7 +542,7 @@ rrc_eNB_ue_context_stmsi_exist(
m_tmsiP, mme_codeP, ue_context_p,
ue_context_p->ue_context.rnti);
if (ue_context_p->ue_context.Initialue_identity_s_TMSI.presence == TRUE) {
printf("S-TMSI %x, MME %x\n",
printf("=> S-TMSI %x, MME %x\n",
ue_context_p->ue_context.Initialue_identity_s_TMSI.m_tmsi,
ue_context_p->ue_context.Initialue_identity_s_TMSI.mme_code);
if (ue_context_p->ue_context.Initialue_identity_s_TMSI.m_tmsi == m_tmsiP)
@@ -1084,7 +1084,8 @@ rrc_eNB_generate_RRCConnectionRelease(
size = do_RRCConnectionRelease(ctxt_pP->module_id, buffer,rrc_eNB_get_next_transaction_identifier(ctxt_pP->module_id));
// set release timer
ue_context_pP->ue_context.ue_release_timer=1;
// remove UE after 10 frames after RRCConnectionRelease is triggered
ue_context_pP->ue_context.ue_release_timer_thres=100;
LOG_I(RRC,
PROTOCOL_RRC_CTXT_UE_FMT" Logical Channel DL-DCCH, Generate RRCConnectionRelease (bytes %d)\n",
PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP),
@@ -2708,11 +2709,11 @@ rrc_eNB_generate_RRCConnectionReconfiguration_handover(
physicalConfigDedicated2->schedulingRequestConfig->present = SchedulingRequestConfig_PR_setup;
physicalConfigDedicated2->schedulingRequestConfig->choice.setup.sr_PUCCH_ResourceIndex = ue_context_pP->local_uid;
if (mac_xface->lte_frame_parms->frame_type == 0) { // FDD
if (mac_xface->frame_parms->frame_type == 0) { // FDD
physicalConfigDedicated2->schedulingRequestConfig->choice.setup.sr_ConfigIndex = 5 + (ue_context_pP->local_uid %
10); // Isr = 5 (every 10 subframes, offset=2+UE_id mod3)
} else {
switch (mac_xface->lte_frame_parms->tdd_config) {
switch (mac_xface->frame_parms->tdd_config) {
case 1:
physicalConfigDedicated2->schedulingRequestConfig->choice.setup.sr_ConfigIndex = 7 + (ue_context_pP->local_uid & 1) + ((
ue_context_pP->local_uid & 3) >> 1) * 5; // Isr = 5 (every 10 subframes, offset=2 for UE0, 3 for UE1, 7 for UE2, 8 for UE3 , 2 for UE4 etc..)
@@ -3706,6 +3707,7 @@ rrc_eNB_generate_RRCConnectionSetup(
SRB_ToAddModList_t **SRB_configList;
SRB_ToAddMod_t *SRB1_config;
int cnt;
LTE_DL_FRAME_PARMS *fp = mac_xface->get_lte_frame_parms(ctxt_pP->module_id,CC_id);
T(T_ENB_RRC_CONNECTION_SETUP, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame),
T_INT(ctxt_pP->subframe), T_INT(ctxt_pP->rnti));
@@ -3715,9 +3717,9 @@ rrc_eNB_generate_RRCConnectionSetup(
do_RRCConnectionSetup(ctxt_pP,
ue_context_pP,
(uint8_t*) eNB_rrc_inst[ctxt_pP->module_id].carrier[CC_id].Srb0.Tx_buffer.Payload,
(mac_xface->lte_frame_parms->nb_antennas_tx_eNB==2)?2:1, //at this point we do not have the UE capability information, so it can only be TM1 or TM2
(fp->nb_antennas_tx_eNB==2)?2:1, //at this point we do not have the UE capability information, so it can only be TM1 or TM2
rrc_eNB_get_next_transaction_identifier(ctxt_pP->module_id),
mac_xface->lte_frame_parms,
fp,
SRB_configList,
&ue_context_pP->ue_context.physicalConfigDedicated);
@@ -3802,6 +3804,10 @@ rrc_eNB_generate_RRCConnectionSetup(
PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP),
eNB_rrc_inst[ctxt_pP->module_id].carrier[CC_id].Srb0.Tx_buffer.payload_size);
// activate release timer, if RRCSetupComplete not received after 10 frames, remove UE
ue_context_pP->ue_context.ue_release_timer=1;
// remove UE after 10 frames after RRCConnectionRelease is triggered
ue_context_pP->ue_context.ue_release_timer_thres=100;
}
#if defined(ENABLE_ITTI)
@@ -4164,7 +4170,7 @@ rrc_eNB_decode_ccch(
if ((ue_context_p = rrc_eNB_ue_context_stmsi_exist(ctxt_pP, mme_code, m_tmsi))) {
//#warning "TODO: stmsi_exist: remove UE from MAC/PHY (how?)"
LOG_I(RRC," S-TMSI exists, ue_context_p %p\n",ue_context_p);
LOG_I(RRC," S-TMSI exists, ue_context_p %p, old rnti %x => %x\n",ue_context_p,ue_context_p->ue_context.rnti,ctxt_pP->rnti);
stmsi_received=1;
/* replace rnti in the context */
/* for that, remove the context from the RB tree */
@@ -4179,6 +4185,7 @@ rrc_eNB_decode_ccch(
// AssertFatal(0 == 1, "TODO: remove UE from MAC/PHY (how?)");
// ue_context_p = NULL;
} else {
LOG_I(RRC," S-TMSI doesn't exist, setting Initialue_identity_s_TMSI.m_tmsi to %x => %x\n",ue_context_p,m_tmsi);
ue_context_p = rrc_eNB_get_next_free_ue_context(ctxt_pP, NOT_A_RANDOM_UE_IDENTITY);
if (ue_context_p == NULL)
LOG_E(RRC, "%s:%d:%s: rrc_eNB_get_next_free_ue_context returned NULL\n", __FILE__, __LINE__, __FUNCTION__);
@@ -4250,6 +4257,7 @@ rrc_eNB_decode_ccch(
LOG_I(RRC, PROTOCOL_RRC_CTXT_UE_FMT" Can't create new context for UE random UE identity (0x%" PRIx64 ")\n",
PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP),
random_value);
rrc_mac_remove_ue(ctxt_pP->module_id,ctxt_pP->rnti);
return -1;
}
}
@@ -4599,6 +4607,7 @@ rrc_eNB_decode_dcch(
}
}
ue_context_p->ue_context.ue_release_timer=0;
break;
case UL_DCCH_MessageType__c1_PR_securityModeComplete:
@@ -4608,7 +4617,7 @@ rrc_eNB_decode_dcch(
#ifdef RRC_MSG_PRINT
LOG_F(RRC,"[MSG] RRC Security Mode Complete\n");
for (i = 0; i < sdu_sizeP; i++) {
for (i = 0; i < sdu_sizeP; i++) eNB->pusch_vars[UE_id]{
LOG_F(RRC,"%02x ", ((uint8_t*)Rx_sdu)[i]);
}
openair2/UTIL/LOG/vcd_signal_dumper.c
+39 -33
View File
@@ -46,16 +46,24 @@ struct vcd_module_s {
} vcd_module_s;
const char* eurecomVariablesNames[] = {
"frame_number_TX_eNB",
"frame_number_RX_eNB",
"frame_number_TX0_eNB",
"frame_number_TX1_eNB",
"frame_number_RX0_eNB",
"frame_number_RX1_eNB",
"subframe_number_TX0_eNB",
"subframe_number_TX1_eNB",
"subframe_number_RX0_eNB",
"subframe_number_RX1_eNB",
"runtime_TX_eNB",
"runtime_RX_eNB",
"frame_number_TX_UE",
"frame_number_RX_UE",
"slot_number_TX_UE",
"slot_number_RX_UE",
"subframe_number_TX_UE",
"subframe_number_RX_UE",
"frame_number_TX0_UE",
"frame_number_TX1_UE",
"frame_number_RX0_UE",
"frame_number_RX1_UE",
"subframe_TX0_UE",
"subframe_TX1_UE",
"subframe_RX0_UE",
"subframe_RX1_UE",
"missed_slot_enb",
"daq_mbox",
"rx_offset_mbox",
@@ -152,28 +160,13 @@ const char* eurecomFunctionsNames[] = {
"rt_sleep",
"trx_read",
"trx_write",
"eNB_thread_tx0",
"eNB_thread_rx0",
"eNB_thread_tx1",
"eNB_thread_rx1",
"eNB_thread_tx2",
"eNB_thread_rx2",
"eNB_thread_tx3",
"eNB_thread_rx3",
"eNB_thread_tx4",
"eNB_thread_rx4",
"eNB_thread_tx5",
"eNB_thread_rx5",
"eNB_thread_tx6",
"eNB_thread_rx6",
"eNB_thread_tx7",
"eNB_thread_rx7",
"eNB_thread_tx8",
"eNB_thread_rx8",
"eNB_thread_tx9",
"eNB_thread_rx9",
"ue_thread_tx",
"ue_thread_rx",
"trx_read_if",
"trx_write_if",
"eNB_thread_rxtx0",
"eNB_thread_rxtx1",
"ue_thread_synch",
"ue_thread_rxtx0",
"ue_thread_rxtx1",
/* RRH signals */
"eNB_tx",
@@ -195,8 +188,13 @@ const char* eurecomFunctionsNames[] = {
"lte_ue_measurement_procedures",
"lte_ue_pdcch_procedures",
"lte_ue_pbch_procedures",
"phy_procedures_eNb_tx",
"phy_procedures_eNb_rx",
"phy_procedures_eNb_tx0",
"phy_procedures_eNb_tx1",
"phy_procedures_eNb_rx_common0",
"phy_procedures_eNb_rx_common1",
"phy_procedures_eNb_rx_uespec0",
"phy_procedures_eNb_rx_uespec1",
"phy_eNB_slot_fep",
"phy_procedures_ue_tx",
"phy_procedures_ue_rx",
"phy_procedures_eNB_lte",
@@ -245,6 +243,7 @@ const char* eurecomFunctionsNames[] = {
"phy_ue_ulsch_scrambling",
"phy_eNB_dlsch_modulation",
"phy_eNB_dlsch_encoding",
"phy_eNB_dlsch_encoding_w",
"phy_eNB_dlsch_scrambling",
/* MAC signals */
@@ -266,6 +265,7 @@ const char* eurecomFunctionsNames[] = {
"macxface_out_of_sync_ind",
"macxface_ue_decode_si",
"macxface_ue_decode_pcch",
"macxface_ue_decode_ccch",
"macxface_ue_decode_bcch",
"macxface_ue_send_sdu",
@@ -311,7 +311,13 @@ const char* eurecomFunctionsNames[] = {
"itti_dump_enqueue_message",
"itti_dump_enqueue_message_malloc",
"itti_relay_thread",
"test"
"test",
/* IF4/IF5 signals */
"send_if4",
"recv_if4",
"send_if5",
"recv_if5"
};
struct vcd_module_s vcd_modules[VCD_SIGNAL_DUMPER_MODULE_END] = {
openair2/UTIL/LOG/vcd_signal_dumper.h
+38 -31
View File
@@ -18,16 +18,24 @@
/* WARNING: if you edit the enums below, update also string definitions in vcd_signal_dumper.c */
typedef enum {
VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_TX_ENB = 0,
VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_RX_ENB,
VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_TX0_ENB = 0,
VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_TX1_ENB,
VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_RX0_ENB,
VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_RX1_ENB,
VCD_SIGNAL_DUMPER_VARIABLES_SUBFRAME_NUMBER_TX0_ENB,
VCD_SIGNAL_DUMPER_VARIABLES_SUBFRAME_NUMBER_TX1_ENB,
VCD_SIGNAL_DUMPER_VARIABLES_SUBFRAME_NUMBER_RX0_ENB,
VCD_SIGNAL_DUMPER_VARIABLES_SUBFRAME_NUMBER_RX1_ENB,
VCD_SIGNAL_DUMPER_VARIABLES_RUNTIME_TX_ENB,
VCD_SIGNAL_DUMPER_VARIABLES_RUNTIME_RX_ENB,
VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_TX_UE,
VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_RX_UE,
VCD_SIGNAL_DUMPER_VARIABLES_SLOT_NUMBER_TX_UE,
VCD_SIGNAL_DUMPER_VARIABLES_SLOT_NUMBER_RX_UE,
VCD_SIGNAL_DUMPER_VARIABLES_SUBFRAME_NUMBER_TX_UE,
VCD_SIGNAL_DUMPER_VARIABLES_SUBFRAME_NUMBER_RX_UE,
VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_TX0_UE,
VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_TX1_UE,
VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_RX0_UE,
VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_RX1_UE,
VCD_SIGNAL_DUMPER_VARIABLES_SUBFRAME_NUMBER_TX0_UE,
VCD_SIGNAL_DUMPER_VARIABLES_SUBFRAME_NUMBER_TX1_UE,
VCD_SIGNAL_DUMPER_VARIABLES_SUBFRAME_NUMBER_RX0_UE,
VCD_SIGNAL_DUMPER_VARIABLES_SUBFRAME_NUMBER_RX1_UE,
VCD_SIGNAL_DUMPER_VARIABLES_MISSED_SLOTS_ENB,
VCD_SIGNAL_DUMPER_VARIABLES_DAQ_MBOX,
VCD_SIGNAL_DUMPER_VARIABLES_UE_OFFSET_MBOX,
@@ -126,28 +134,13 @@ typedef enum {
VCD_SIGNAL_DUMPER_FUNCTIONS_RT_SLEEP=0,
VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_READ,
VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_WRITE,
VCD_SIGNAL_DUMPER_FUNCTIONS_eNB_PROC_TX0,
VCD_SIGNAL_DUMPER_FUNCTIONS_eNB_PROC_RX0,
VCD_SIGNAL_DUMPER_FUNCTIONS_eNB_PROC_TX1,
VCD_SIGNAL_DUMPER_FUNCTIONS_eNB_PROC_RX1,
VCD_SIGNAL_DUMPER_FUNCTIONS_eNB_PROC_TX2,
VCD_SIGNAL_DUMPER_FUNCTIONS_eNB_PROC_RX2,
VCD_SIGNAL_DUMPER_FUNCTIONS_eNB_PROC_TX3,
VCD_SIGNAL_DUMPER_FUNCTIONS_eNB_PROC_RX3,
VCD_SIGNAL_DUMPER_FUNCTIONS_eNB_PROC_TX4,
VCD_SIGNAL_DUMPER_FUNCTIONS_eNB_PROC_RX4,
VCD_SIGNAL_DUMPER_FUNCTIONS_eNB_PROC_TX5,
VCD_SIGNAL_DUMPER_FUNCTIONS_eNB_PROC_RX5,
VCD_SIGNAL_DUMPER_FUNCTIONS_eNB_PROC_TX6,
VCD_SIGNAL_DUMPER_FUNCTIONS_eNB_PROC_RX6,
VCD_SIGNAL_DUMPER_FUNCTIONS_eNB_PROC_TX7,
VCD_SIGNAL_DUMPER_FUNCTIONS_eNB_PROC_RX7,
VCD_SIGNAL_DUMPER_FUNCTIONS_eNB_PROC_TX8,
VCD_SIGNAL_DUMPER_FUNCTIONS_eNB_PROC_RX8,
VCD_SIGNAL_DUMPER_FUNCTIONS_eNB_PROC_TX9,
VCD_SIGNAL_DUMPER_FUNCTIONS_eNB_PROC_RX9,
VCD_SIGNAL_DUMPER_FUNCTIONS_UE_THREAD_TX,
VCD_SIGNAL_DUMPER_FUNCTIONS_UE_THREAD_RX,
VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_READ_IF,
VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_WRITE_IF,
VCD_SIGNAL_DUMPER_FUNCTIONS_eNB_PROC_RXTX0,
VCD_SIGNAL_DUMPER_FUNCTIONS_eNB_PROC_RXTX1,
VCD_SIGNAL_DUMPER_FUNCTIONS_UE_THREAD_SYNCH,
VCD_SIGNAL_DUMPER_FUNCTIONS_UE_THREAD_RXTX0,
VCD_SIGNAL_DUMPER_FUNCTIONS_UE_THREAD_RXTX1,
/* RRH signals */
VCD_SIGNAL_DUMPER_FUNCTIONS_eNB_TX,
@@ -170,7 +163,12 @@ typedef enum {
VCD_SIGNAL_DUMPER_FUNCTIONS_UE_PDCCH_PROCEDURES,
VCD_SIGNAL_DUMPER_FUNCTIONS_UE_PBCH_PROCEDURES,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_ENB_TX,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_ENB_RX,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_ENB_TX1,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_ENB_RX_COMMON,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_ENB_RX_COMMON1,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_ENB_RX_UESPEC,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_ENB_RX_UESPEC1,
VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_SLOT_FEP,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_RX,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_ENB_LTE,
@@ -219,6 +217,7 @@ typedef enum {
VCD_SIGNAL_DUMPER_FUNCTIONS_UE_ULSCH_SCRAMBLING,
VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_MODULATION,
VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING,
VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING_W,
VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_SCRAMBLING,
/* MAC signals */
@@ -240,6 +239,7 @@ typedef enum {
VCD_SIGNAL_DUMPER_FUNCTIONS_OUT_OF_SYNC_IND,
VCD_SIGNAL_DUMPER_FUNCTIONS_UE_DECODE_SI,
VCD_SIGNAL_DUMPER_FUNCTIONS_UE_DECODE_PCCH,
VCD_SIGNAL_DUMPER_FUNCTIONS_UE_DECODE_CCCH,
VCD_SIGNAL_DUMPER_FUNCTIONS_UE_DECODE_BCCH,
VCD_SIGNAL_DUMPER_FUNCTIONS_UE_SEND_SDU,
@@ -289,6 +289,13 @@ typedef enum {
VCD_SIGNAL_DUMPER_FUNCTIONS_ITTI_DUMP_ENQUEUE_MESSAGE_MALLOC,
VCD_SIGNAL_DUMPER_FUNCTIONS_ITTI_RELAY_THREAD,
VCD_SIGNAL_DUMPER_FUNCTIONS_TEST,
/* IF4/IF5 signals */
VCD_SIGNAL_DUMPER_FUNCTIONS_SEND_IF4,
VCD_SIGNAL_DUMPER_FUNCTIONS_RECV_IF4,
VCD_SIGNAL_DUMPER_FUNCTIONS_SEND_IF5,
VCD_SIGNAL_DUMPER_FUNCTIONS_RECV_IF5,
VCD_SIGNAL_DUMPER_FUNCTIONS_LAST,
VCD_SIGNAL_DUMPER_FUNCTIONS_END = VCD_SIGNAL_DUMPER_FUNCTIONS_LAST,
} vcd_signal_dump_functions;
openair2/UTIL/OCG/OCG.h
+3
View File
@@ -15,6 +15,7 @@
#ifndef __OCG_H__
#define __OCG_H__
#include "PHY/defs.h"
#include "PHY/impl_defs_top.h"
#include "platform_types.h"
@@ -678,6 +679,8 @@ typedef struct {
// phy related params
unsigned int n_frames;
unsigned int n_frames_flag; // if set, then let the emulation goes to infinity
eNB_func_t node_function[MAX_NUM_CCs];
eNB_timing_t node_timing[MAX_NUM_CCs];
unsigned char frame_type[MAX_NUM_CCs]; //! LTE frame type (TDD=1, FDD=0). \note this should be converted to \ref lte_frame_type_t (header file reorganization needed)
char * frame_type_name[MAX_NUM_CCs];
unsigned char tdd_config[MAX_NUM_CCs];