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Merge remote-tracking branch 'origin/393-dlsch-scheduler-optimization' into develop_integration_2019_w08

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This commit is contained in:
Raphael Defosseux
2019-02-22 12:14:00 +01:00
parent 9286b58fb6 db51a61c2e
commit 7caea35158
5 changed files with 2861 additions and 2029 deletions
Download Patch File Download Diff File Expand all files Collapse all files
openair2/LAYER2/MAC/eNB_scheduler_dlsch.c
+851 -528
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File diff suppressed because it is too large Load Diff
openair2/LAYER2/MAC/eNB_scheduler_fairRR.c
+17 -9
View File
@@ -295,7 +295,8 @@ void dlsch_scheduler_pre_ue_select_fairRR(
CC_id, CC_id,
UE_id, UE_id,
subframeP, subframeP,
S_DL_NONE); S_DL_NONE,
rnti);
end_flag[CC_id] = 1; end_flag[CC_id] = 1;
break; break;
} }
@@ -418,7 +419,8 @@ void dlsch_scheduler_pre_ue_select_fairRR(
CC_id, CC_id,
UE_id, UE_id,
subframeP, subframeP,
S_DL_NONE); S_DL_NONE,
rnti);
end_flag[CC_id] = 1; end_flag[CC_id] = 1;
break; break;
} }
@@ -541,7 +543,8 @@ void dlsch_scheduler_pre_ue_select_fairRR(
CC_id, CC_id,
UE_id, UE_id,
subframeP, subframeP,
S_DL_NONE); S_DL_NONE,
rnti);
end_flag[CC_id] = 1; end_flag[CC_id] = 1;
break; break;
} }
@@ -810,7 +813,8 @@ schedule_ue_spec_fairRR(module_id_t module_idP,
unsigned char ta_len = 0; unsigned char ta_len = 0;
unsigned char sdu_lcids[NB_RB_MAX], lcid, offset, num_sdus = 0; unsigned char sdu_lcids[NB_RB_MAX], lcid, offset, num_sdus = 0;
uint16_t nb_rb, nb_rb_temp, nb_available_rb; uint16_t nb_rb, nb_rb_temp, nb_available_rb;
uint16_t TBS, j, sdu_lengths[NB_RB_MAX], rnti, padding = 0, post_padding = 0; uint16_t TBS, j, sdu_lengths[NB_RB_MAX], padding = 0, post_padding = 0;
rnti_t rnti = 0;
unsigned char dlsch_buffer[MAX_DLSCH_PAYLOAD_BYTES]; unsigned char dlsch_buffer[MAX_DLSCH_PAYLOAD_BYTES];
unsigned char round = 0; unsigned char round = 0;
unsigned char harq_pid = 0; unsigned char harq_pid = 0;
@@ -1215,8 +1219,11 @@ schedule_ue_spec_fairRR(module_id_t module_idP,
} }
add_ue_dlsch_info(module_idP, add_ue_dlsch_info(module_idP,
CC_id, UE_id, subframeP, CC_id,
S_DL_SCHEDULED); UE_id,
subframeP,
S_DL_SCHEDULED,
rnti);
//eNB_UE_stats->dlsch_trials[round]++; //eNB_UE_stats->dlsch_trials[round]++;
UE_list->eNB_UE_stats[CC_id][UE_id]. UE_list->eNB_UE_stats[CC_id][UE_id].
num_retransmission += 1; num_retransmission += 1;
@@ -1678,10 +1685,10 @@ schedule_ue_spec_fairRR(module_id_t module_idP,
if (opt_enabled == 1) { if (opt_enabled == 1) {
trace_pdu(DIRECTION_DOWNLINK, (uint8_t *)UE_list->DLSCH_pdu[CC_id][0][UE_id].payload[0], trace_pdu(DIRECTION_DOWNLINK, (uint8_t *)UE_list->DLSCH_pdu[CC_id][0][UE_id].payload[0],
TBS, module_idP, WS_RA_RNTI, UE_RNTI(module_idP,UE_id), TBS, module_idP, WS_RA_RNTI, UE_RNTI(module_idP, UE_id),
eNB->frame, eNB->subframe,0,0); eNB->frame, eNB->subframe,0,0);
LOG_D(OPT,"[eNB %d][DLSCH] CC_id %d Frame %d rnti %x with size %d\n", LOG_D(OPT,"[eNB %d][DLSCH] CC_id %d Frame %d rnti %x with size %d\n",
module_idP, CC_id, frameP, UE_RNTI(module_idP,UE_id), TBS); module_idP, CC_id, frameP, UE_RNTI(module_idP, UE_id), TBS);
} }
T(T_ENB_MAC_UE_DL_PDU_WITH_DATA, T_INT(module_idP), T_INT(CC_id), T_INT(rnti), T_INT(frameP), T_INT(subframeP), T(T_ENB_MAC_UE_DL_PDU_WITH_DATA, T_INT(module_idP), T_INT(CC_id), T_INT(rnti), T_INT(frameP), T_INT(subframeP),
@@ -1691,7 +1698,8 @@ schedule_ue_spec_fairRR(module_id_t module_idP,
CC_id, CC_id,
UE_id, UE_id,
subframeP, subframeP,
S_DL_SCHEDULED); S_DL_SCHEDULED,
rnti);
// store stats // store stats
eNB->eNB_stats[CC_id].dlsch_bytes_tx+=sdu_length_total; eNB->eNB_stats[CC_id].dlsch_bytes_tx+=sdu_length_total;
eNB->eNB_stats[CC_id].dlsch_pdus_tx+=1; eNB->eNB_stats[CC_id].dlsch_pdus_tx+=1;
openair2/LAYER2/MAC/eNB_scheduler_primitives.c
+1899 -1423
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File diff suppressed because it is too large Load Diff
openair2/LAYER2/MAC/mac_proto.h
+5 -5
View File
@@ -441,7 +441,7 @@ void init_ue_sched_info(void);
void add_ue_ulsch_info(module_id_t module_idP, int CC_id, int UE_id, void add_ue_ulsch_info(module_id_t module_idP, int CC_id, int UE_id,
sub_frame_t subframe, UE_ULSCH_STATUS status); sub_frame_t subframe, UE_ULSCH_STATUS status);
void add_ue_dlsch_info(module_id_t module_idP, int CC_id, int UE_id, void add_ue_dlsch_info(module_id_t module_idP, int CC_id, int UE_id,
sub_frame_t subframe, UE_DLSCH_STATUS status); sub_frame_t subframe, UE_DLSCH_STATUS status, rnti_t rnti);
int find_UE_id(module_id_t module_idP, rnti_t rnti); int find_UE_id(module_id_t module_idP, rnti_t rnti);
int find_RA_id(module_id_t mod_idP, int CC_idP, rnti_t rntiP); int find_RA_id(module_id_t mod_idP, int CC_idP, rnti_t rntiP);
rnti_t UE_RNTI(module_id_t module_idP, int UE_id); rnti_t UE_RNTI(module_id_t module_idP, int UE_id);
@@ -1209,7 +1209,6 @@ void fill_nfapi_dlsch_config(eNB_MAC_INST * eNB,
void fill_nfapi_harq_information(module_id_t module_idP, void fill_nfapi_harq_information(module_id_t module_idP,
int CC_idP, int CC_idP,
uint16_t rntiP, uint16_t rntiP,
uint16_t absSFP,
nfapi_ul_config_harq_information * nfapi_ul_config_harq_information *
harq_information, uint8_t cce_idxP); harq_information, uint8_t cce_idxP);
@@ -1221,9 +1220,10 @@ void fill_nfapi_ulsch_harq_information(module_id_t module_idP,
sub_frame_t subframeP); sub_frame_t subframeP);
uint16_t fill_nfapi_uci_acknak(module_id_t module_idP, uint16_t fill_nfapi_uci_acknak(module_id_t module_idP,
int CC_idP, int CC_idP,
uint16_t rntiP, uint16_t rntiP,
uint16_t absSFP, uint8_t cce_idxP); uint16_t absSFP,
uint8_t cce_idxP);
void fill_nfapi_dl_dci_1A(nfapi_dl_config_request_pdu_t * dl_config_pdu, void fill_nfapi_dl_dci_1A(nfapi_dl_config_request_pdu_t * dl_config_pdu,
uint8_t aggregation_level, uint8_t aggregation_level,
openair2/LAYER2/MAC/pre_processor.c
+89 -64
View File
@@ -460,7 +460,12 @@ void decode_slice_positioning(module_id_t Mod_idP,
// This fuction sorts the UE in order their dlsch buffer and CQI // This fuction sorts the UE in order their dlsch buffer and CQI
void sort_UEs(module_id_t Mod_idP, int slice_idx, int frameP, sub_frame_t subframeP) { void
sort_UEs(module_id_t Mod_idP,
int slice_idx,
int frameP,
sub_frame_t subframeP)
{
int i; int i;
int list[MAX_MOBILES_PER_ENB]; int list[MAX_MOBILES_PER_ENB];
int list_size = 0; int list_size = 0;
@@ -468,16 +473,13 @@ void sort_UEs(module_id_t Mod_idP, int slice_idx, int frameP, sub_frame_t subfra
UE_list_t *UE_list = &RC.mac[Mod_idP]->UE_list; UE_list_t *UE_list = &RC.mac[Mod_idP]->UE_list;
for (i = 0; i < MAX_MOBILES_PER_ENB; i++) { for (i = 0; i < MAX_MOBILES_PER_ENB; i++) {
if (UE_list->active[i] == FALSE) continue;
if (UE_RNTI(Mod_idP, i) == NOT_A_RNTI) continue; if (UE_list->active[i] == TRUE &&
UE_RNTI(Mod_idP, i) != NOT_A_RNTI &&
if (UE_list->UE_sched_ctrl[i].ul_out_of_sync == 1) continue; UE_list->UE_sched_ctrl[i].ul_out_of_sync != 1 &&
ue_dl_slice_membership(Mod_idP, i, slice_idx)) {
if (!ue_dl_slice_membership(Mod_idP, i, slice_idx)) continue; list[list_size++] = i;
}
list[list_size] = i;
list_size++;
} }
decode_sorting_policy(Mod_idP, slice_idx); decode_sorting_policy(Mod_idP, slice_idx);
@@ -1170,12 +1172,15 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id,
uint8_t CC_id; uint8_t CC_id;
uint16_t i, j; uint16_t i, j;
int min_rb_unit[NFAPI_CC_MAX]; int min_rb_unit[NFAPI_CC_MAX];
slice_info_t *sli = &RC.mac[Mod_id]->slice_info;
eNB_MAC_INST *eNB = RC.mac[Mod_id];
slice_info_t *sli = &eNB->slice_info;
uint16_t (*nb_rbs_required)[MAX_MOBILES_PER_ENB] = sli->pre_processor_results[slice_idx].nb_rbs_required; uint16_t (*nb_rbs_required)[MAX_MOBILES_PER_ENB] = sli->pre_processor_results[slice_idx].nb_rbs_required;
uint16_t (*nb_rbs_accounted)[MAX_MOBILES_PER_ENB] = sli->pre_processor_results[slice_idx].nb_rbs_accounted; uint16_t (*nb_rbs_accounted)[MAX_MOBILES_PER_ENB] = sli->pre_processor_results[slice_idx].nb_rbs_accounted;
uint16_t (*nb_rbs_remaining)[MAX_MOBILES_PER_ENB] = sli->pre_processor_results[slice_idx].nb_rbs_remaining; uint16_t (*nb_rbs_remaining)[MAX_MOBILES_PER_ENB] = sli->pre_processor_results[slice_idx].nb_rbs_remaining;
uint8_t (*MIMO_mode_indicator)[N_RBG_MAX] = sli->pre_processor_results[slice_idx].MIMO_mode_indicator; uint8_t (*MIMO_mode_indicator)[N_RBG_MAX] = sli->pre_processor_results[slice_idx].MIMO_mode_indicator;
UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list;
UE_list_t *UE_list = &eNB->UE_list;
UE_sched_ctrl *ue_sched_ctl; UE_sched_ctrl *ue_sched_ctl;
// int rrc_status = RRC_IDLE; // int rrc_status = RRC_IDLE;
#ifdef TM5 #ifdef TM5
@@ -1191,7 +1196,10 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id,
// Initialize scheduling information for all active UEs // Initialize scheduling information for all active UEs
memset(&sli->pre_processor_results[slice_idx], 0, sizeof(sli->pre_processor_results[slice_idx])); memset(&sli->pre_processor_results[slice_idx], 0, sizeof(sli->pre_processor_results[slice_idx]));
// FIXME: After the memset above, some of the resets in reset() are redundant // FIXME: After the memset above, some of the resets in reset() are redundant
dlsch_scheduler_pre_processor_reset(Mod_id, slice_idx, frameP, subframeP, dlsch_scheduler_pre_processor_reset(Mod_id,
slice_idx,
frameP,
subframeP,
min_rb_unit, min_rb_unit,
nb_rbs_required, nb_rbs_required,
rballoc_sub, rballoc_sub,
@@ -1199,44 +1207,63 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id,
mbsfn_flag); // FIXME: Not sure if useful mbsfn_flag); // FIXME: Not sure if useful
// STATUS // STATUS
// Store the DLSCH buffer for each logical channel // Store the DLSCH buffer for each logical channel
store_dlsch_buffer(Mod_id, slice_idx, frameP, subframeP); store_dlsch_buffer(Mod_id,
slice_idx,
frameP,
subframeP);
// Calculate the number of RBs required by each UE on the basis of logical channel's buffer // Calculate the number of RBs required by each UE on the basis of logical channel's buffer
assign_rbs_required(Mod_id, slice_idx, frameP, subframeP, nb_rbs_required, min_rb_unit); assign_rbs_required(Mod_id,
slice_idx,
frameP,
subframeP,
nb_rbs_required,
min_rb_unit);
// Sorts the user on the basis of dlsch logical channel buffer and CQI // Sorts the user on the basis of dlsch logical channel buffer and CQI
sort_UEs(Mod_id, slice_idx, frameP, subframeP); sort_UEs(Mod_id,
slice_idx,
frameP,
subframeP);
// ACCOUNTING // ACCOUNTING
// This procedure decides the number of RBs to allocate // This procedure decides the number of RBs to allocate
dlsch_scheduler_pre_processor_accounting(Mod_id, slice_idx, frameP, subframeP, dlsch_scheduler_pre_processor_accounting(Mod_id,
min_rb_unit, slice_idx,
nb_rbs_required, frameP,
nb_rbs_accounted); subframeP,
min_rb_unit,
nb_rbs_required,
nb_rbs_accounted);
// POSITIONING // POSITIONING
// This procedure does the main allocation of the RBs // This procedure does the main allocation of the RBs
dlsch_scheduler_pre_processor_positioning(Mod_id, slice_idx, dlsch_scheduler_pre_processor_positioning(Mod_id,
min_rb_unit, slice_idx,
nb_rbs_required, min_rb_unit,
nb_rbs_accounted, nb_rbs_required,
nb_rbs_remaining, nb_rbs_accounted,
rballoc_sub, nb_rbs_remaining,
MIMO_mode_indicator); rballoc_sub,
MIMO_mode_indicator);
// SHARING // SHARING
// If there are available RBs left in the slice, allocate them to the highest priority UEs // If there are available RBs left in the slice, allocate them to the highest priority UEs
if (RC.mac[Mod_id]->slice_info.intraslice_share_active) { if (eNB->slice_info.intraslice_share_active) {
dlsch_scheduler_pre_processor_intraslice_sharing(Mod_id, slice_idx, dlsch_scheduler_pre_processor_intraslice_sharing(Mod_id,
min_rb_unit, slice_idx,
nb_rbs_required, min_rb_unit,
nb_rbs_accounted, nb_rbs_required,
nb_rbs_remaining, nb_rbs_accounted,
rballoc_sub, nb_rbs_remaining,
MIMO_mode_indicator); rballoc_sub,
MIMO_mode_indicator);
} }
#ifdef TM5 #ifdef TM5
// This has to be revisited!!!! // This has to be revisited!!!!
for (CC_id = 0; CC_id < RC.nb_mac_CC[Mod_id]; CC_id++) { for (CC_id = 0; CC_id < RC.nb_mac_CC[Mod_id]; CC_id++) {
COMMON_channels_t *cc = &RC.mac[Mod_id]->common_channels[CC_id]; COMMON_channels_t *cc = &eNB->common_channels[CC_id];
int N_RBG = to_rbg(cc->mib->message.dl_Bandwidth); int N_RBG = to_rbg(cc->mib->message.dl_Bandwidth);
i1 = 0; i1 = 0;
i2 = 0; i2 = 0;
@@ -1244,35 +1271,25 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id,
for (j = 0; j < N_RBG; j++) { for (j = 0; j < N_RBG; j++) {
if (MIMO_mode_indicator[CC_id][j] == 2) { if (MIMO_mode_indicator[CC_id][j] == 2) {
i1 = i1 + 1; i1++;
} else if (MIMO_mode_indicator[CC_id][j] == 1) { } else if (MIMO_mode_indicator[CC_id][j] == 1) {
i2 = i2 + 1; i2++;
} else if (MIMO_mode_indicator[CC_id][j] == 0) { } else if (MIMO_mode_indicator[CC_id][j] == 0) {
i3 = i3 + 1; i3++;
} }
} }
if ((i1 < N_RBG) && (i2 > 0) && (i3 == 0)) { if (i1 < N_RBG) {
PHY_vars_eNB_g[Mod_id][CC_id]->check_for_SUMIMO_transmissions = if (i2 > 0 && i3 == 0) {
PHY_vars_eNB_g[Mod_id][CC_id]-> PHY_vars_eNB_g[Mod_id][CC_id]->check_for_SUMIMO_transmissions = PHY_vars_eNB_g[Mod_id][CC_id]->check_for_SUMIMO_transmissions + 1;
check_for_SUMIMO_transmissions + 1; } else if (i3 > 0) {
PHY_vars_eNB_g[Mod_id][CC_id]->check_for_MUMIMO_transmissions = PHY_vars_eNB_g[Mod_id][CC_id]->check_for_MUMIMO_transmissions + 1;
}
} else if (i3 == N_RBG && i1 == 0 && i2 == 0) {
PHY_vars_eNB_g[Mod_id][CC_id]->FULL_MUMIMO_transmissions = PHY_vars_eNB_g[Mod_id][CC_id]->FULL_MUMIMO_transmissions + 1;
} }
PHY_vars_eNB_g[Mod_id][CC_id]->check_for_total_transmissions = PHY_vars_eNB_g[Mod_id][CC_id]->check_for_total_transmissions + 1;
if (i3 == N_RBG && i1 == 0 && i2 == 0) {
PHY_vars_eNB_g[Mod_id][CC_id]->FULL_MUMIMO_transmissions =
PHY_vars_eNB_g[Mod_id][CC_id]->FULL_MUMIMO_transmissions +
1;
}
if ((i1 < N_RBG) && (i3 > 0)) {
PHY_vars_eNB_g[Mod_id][CC_id]->check_for_MUMIMO_transmissions =
PHY_vars_eNB_g[Mod_id][CC_id]->
check_for_MUMIMO_transmissions + 1;
}
PHY_vars_eNB_g[Mod_id][CC_id]->check_for_total_transmissions =
PHY_vars_eNB_g[Mod_id][CC_id]->check_for_total_transmissions +
1;
} }
#endif #endif
@@ -1283,22 +1300,30 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id,
for (i = 0; i < UE_num_active_CC(UE_list, UE_id); i++) { for (i = 0; i < UE_num_active_CC(UE_list, UE_id); i++) {
CC_id = UE_list->ordered_CCids[i][UE_id]; CC_id = UE_list->ordered_CCids[i][UE_id];
//PHY_vars_eNB_g[Mod_id]->mu_mimo_mode[UE_id].dl_pow_off = dl_pow_off[UE_id]; //PHY_vars_eNB_g[Mod_id]->mu_mimo_mode[UE_id].dl_pow_off = dl_pow_off[UE_id];
COMMON_channels_t *cc = &RC.mac[Mod_id]->common_channels[CC_id]; COMMON_channels_t *cc = &eNB->common_channels[CC_id];
int N_RBG = to_rbg(cc->mib->message.dl_Bandwidth); int N_RBG = to_rbg(cc->mib->message.dl_Bandwidth);
if (ue_sched_ctl->pre_nb_available_rbs[CC_id] > 0) { if (ue_sched_ctl->pre_nb_available_rbs[CC_id] > 0) {
LOG_D(MAC, "******************DL Scheduling Information for UE%d ************************\n", UE_id); LOG_D(MAC, "******************DL Scheduling Information for UE%d ************************\n",
LOG_D(MAC, "dl power offset UE%d = %d \n", UE_id, ue_sched_ctl->dl_pow_off[CC_id]); UE_id);
LOG_D(MAC, "***********RB Alloc for every subband for UE%d ***********\n", UE_id); LOG_D(MAC, "dl power offset UE%d = %d \n",
UE_id,
ue_sched_ctl->dl_pow_off[CC_id]);
LOG_D(MAC, "***********RB Alloc for every subband for UE%d ***********\n",
UE_id);
for (j = 0; j < N_RBG; j++) { for (j = 0; j < N_RBG; j++) {
//PHY_vars_eNB_g[Mod_id]->mu_mimo_mode[UE_id].rballoc_sub[UE_id] = rballoc_sub_UE[CC_id][UE_id][UE_id]; //PHY_vars_eNB_g[Mod_id]->mu_mimo_mode[UE_id].rballoc_sub[UE_id] = rballoc_sub_UE[CC_id][UE_id][UE_id];
LOG_D(MAC, "RB Alloc for UE%d and Subband%d = %d\n", UE_id, j, ue_sched_ctl->rballoc_sub_UE[CC_id][j]); LOG_D(MAC, "RB Alloc for UE%d and Subband%d = %d\n",
UE_id, j,
ue_sched_ctl->rballoc_sub_UE[CC_id][j]);
} }
//PHY_vars_eNB_g[Mod_id]->mu_mimo_mode[UE_id].pre_nb_available_rbs = pre_nb_available_rbs[CC_id][UE_id]; //PHY_vars_eNB_g[Mod_id]->mu_mimo_mode[UE_id].pre_nb_available_rbs = pre_nb_available_rbs[CC_id][UE_id];
LOG_D(MAC, "[eNB %d][SLICE %d]Total RBs allocated for UE%d = %d\n", LOG_D(MAC, "[eNB %d][SLICE %d]Total RBs allocated for UE%d = %d\n",
Mod_id, RC.mac[Mod_id]->slice_info.dl[slice_idx].id, UE_id, Mod_id,
eNB->slice_info.dl[slice_idx].id,
UE_id,
ue_sched_ctl->pre_nb_available_rbs[CC_id]); ue_sched_ctl->pre_nb_available_rbs[CC_id]);
} }
} }