Modification of TA update procedure
This commit is contained in:
committed by
Robert Schmidt
parent
fd3d49bbe7
commit
8363849c3f
@@ -634,24 +634,15 @@ void nr_schedule_ue_spec(module_id_t module_id,
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NR_UE_info_t *UE_info = &gNB_mac->UE_info;
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NR_UE_info_t *UE_info = &gNB_mac->UE_info;
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const int CC_id = 0;
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const int CC_id = 0;
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/* calculate number of slots since last DL scheduling, since the scheduler is
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* not called in every slot. */
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const NR_COMMON_channels_t *cc = gNB_mac->common_channels;
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const NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
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const NR_TDD_UL_DL_Pattern_t *tdd_pattern = &scc->tdd_UL_DL_ConfigurationCommon->pattern1;
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const int slot_diff =
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(slot % num_slots_per_tdd) == 0 ? tdd_pattern->nrofUplinkSlots + 1 : 1;
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NR_UE_list_t *UE_list = &UE_info->list;
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NR_UE_list_t *UE_list = &UE_info->list;
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for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
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for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
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NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
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NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
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/* update TA and set ta_apply upon expiry. If such UE is not scheduled now,
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/* update TA and set ta_apply every 10 frames.
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* it will be by the preprocessor later. If we add the CE, ta_apply will be
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* Possible improvement: take the periodicity from input file.
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* reset */
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* If such UE is not scheduled now, it will be by the preprocessor later.
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if (sched_ctrl->ta_timer > 0)
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* If we add the CE, ta_apply will be reset */
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sched_ctrl->ta_timer -= slot_diff;
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if (frame >= (sched_ctrl->ta_frame + 10) % 1023)
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else
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sched_ctrl->ta_apply = true; /* the timer is reset once TA CE is scheduled */
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sched_ctrl->ta_apply = true; /* the timer is reset once TA CE is scheduled */
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if (sched_ctrl->rbSize <= 0 && !get_softmodem_params()->phy_test)
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if (sched_ctrl->rbSize <= 0 && !get_softmodem_params()->phy_test)
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@@ -751,15 +742,6 @@ void nr_schedule_ue_spec(module_id_t module_id,
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/* reserve space for timing advance of UE if necessary,
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/* reserve space for timing advance of UE if necessary,
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* nr_generate_dlsch_pdu() checks for ta_apply and add TA CE if necessary */
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* nr_generate_dlsch_pdu() checks for ta_apply and add TA CE if necessary */
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const int ta_len = (sched_ctrl->ta_apply) ? 2 : 0;
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const int ta_len = (sched_ctrl->ta_apply) ? 2 : 0;
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if (sched_ctrl->ta_apply) {
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LOG_I(MAC,
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"%d.%2d UE %d TA scheduled, resetting timer to 100\n",
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frame,
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slot,
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UE_id);
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sched_ctrl->ta_apply = false;
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sched_ctrl->ta_timer = 100;
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}
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/* Get RLC data TODO: remove random data retrieval */
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/* Get RLC data TODO: remove random data retrieval */
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int header_length_total = 0;
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int header_length_total = 0;
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@@ -803,7 +785,6 @@ void nr_schedule_ue_spec(module_id_t module_id,
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sdu_length_total += sdu_lengths[num_sdus];
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sdu_length_total += sdu_lengths[num_sdus];
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header_length_last = 1 + 1 + (sdu_lengths[num_sdus] >= 128);
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header_length_last = 1 + 1 + (sdu_lengths[num_sdus] >= 128);
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header_length_total += header_length_last;
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header_length_total += header_length_last;
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num_sdus++;
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num_sdus++;
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//ue_sched_ctl->uplane_inactivity_timer = 0;
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//ue_sched_ctl->uplane_inactivity_timer = 0;
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@@ -867,6 +848,17 @@ void nr_schedule_ue_spec(module_id_t module_id,
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retInfo->mcs = sched_ctrl->mcs;
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retInfo->mcs = sched_ctrl->mcs;
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retInfo->numDmrsCdmGrpsNoData = sched_ctrl->numDmrsCdmGrpsNoData;
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retInfo->numDmrsCdmGrpsNoData = sched_ctrl->numDmrsCdmGrpsNoData;
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// ta command is sent, values are reset
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if (sched_ctrl->ta_apply) {
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sched_ctrl->ta_apply = false;
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sched_ctrl->ta_frame = frame;
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LOG_D(MAC,
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"%d.%2d UE %d TA scheduled, resetting TA frame\n",
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frame,
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slot,
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UE_id);
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}
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T(T_GNB_MAC_DL_PDU_WITH_DATA, T_INT(module_id), T_INT(CC_id), T_INT(rnti),
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T(T_GNB_MAC_DL_PDU_WITH_DATA, T_INT(module_id), T_INT(CC_id), T_INT(rnti),
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T_INT(frame), T_INT(slot), T_INT(current_harq_pid), T_BUFFER(buf, TBS));
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T_INT(frame), T_INT(slot), T_INT(current_harq_pid), T_BUFFER(buf, TBS));
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@@ -1784,9 +1784,9 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){
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memset((void *) &UE_info->UE_sched_ctrl[UE_id],
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memset((void *) &UE_info->UE_sched_ctrl[UE_id],
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0,
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0,
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sizeof(NR_UE_sched_ctrl_t));
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sizeof(NR_UE_sched_ctrl_t));
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UE_info->UE_sched_ctrl[UE_id].ta_frame = 0;
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UE_info->UE_sched_ctrl[UE_id].ta_timer = 100;
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UE_info->UE_sched_ctrl[UE_id].ta_update = 31;
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UE_info->UE_sched_ctrl[UE_id].ta_update = 31;
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UE_info->UE_sched_ctrl[UE_id].ta_apply = false;
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UE_info->UE_sched_ctrl[UE_id].ul_rssi = 0;
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UE_info->UE_sched_ctrl[UE_id].ul_rssi = 0;
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UE_info->UE_sched_ctrl[UE_id].sched_pucch = (NR_sched_pucch **)malloc(num_slots_ul*sizeof(NR_sched_pucch *));
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UE_info->UE_sched_ctrl[UE_id].sched_pucch = (NR_sched_pucch **)malloc(num_slots_ul*sizeof(NR_sched_pucch *));
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for (int s=0; s<num_slots_ul;s++)
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for (int s=0; s<num_slots_ul;s++)
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@@ -361,6 +361,8 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP,
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current_rnti,
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current_rnti,
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UE_id,
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UE_id,
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ra->rnti);
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ra->rnti);
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// re-initialize ta update variables afrer RA procedure completion
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UE_info->UE_sched_ctrl[UE_id].ta_frame = frameP;
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}
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}
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return;
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return;
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}
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}
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@@ -372,7 +372,7 @@ typedef struct {
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/// Retransmission-related information
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/// Retransmission-related information
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NR_UE_ret_info_t retInfo[NR_MAX_NB_HARQ_PROCESSES];
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NR_UE_ret_info_t retInfo[NR_MAX_NB_HARQ_PROCESSES];
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uint16_t ta_timer;
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uint16_t ta_frame;
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int16_t ta_update;
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int16_t ta_update;
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bool ta_apply;
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bool ta_apply;
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uint8_t tpc0;
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uint8_t tpc0;
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