From 857af54015d4749385e912f8d067bb25cc4d7f96 Mon Sep 17 00:00:00 2001
From: Raymond Knopp <knopp@eurecom.fr>
Date: Mon, 8 Aug 2016 00:08:43 +0200
Subject: [PATCH] usrp 20 MHz on 30.72 master clock. fixed memory leak in
 prach.c for 20 MHz with 3/4 sampling. added default attributes to threads in
 lte-enb.c

---
 openair1/PHY/LTE_TRANSPORT/prach.c           | 26 +++++++++++++++-----
 targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp |  2 +-
 targets/RT/USER/lte-enb.c                    |  8 ++++++
 3 files changed, 29 insertions(+), 7 deletions(-)

diff --git a/openair1/PHY/LTE_TRANSPORT/prach.c b/openair1/PHY/LTE_TRANSPORT/prach.c
index b24535c43a..cab6544b62 100644
--- a/openair1/PHY/LTE_TRANSPORT/prach.c
+++ b/openair1/PHY/LTE_TRANSPORT/prach.c
@@ -1161,6 +1161,9 @@ void rx_prach(PHY_VARS_eNB *eNB,
     break;
   }
 
+  if (eNB->frame_parms.threequarter_fs == 1)
+    Ncp=(Ncp*3)>>2;
+
   switch (eNB->frame_parms.N_RB_UL) {
   case 6:
     Ncp>>=4;
@@ -1258,13 +1261,24 @@ void rx_prach(PHY_VARS_eNB *eNB,
 	break;
 	
       case 100:
-	if (prach_fmt == 4) {
-	  dft4096(prach2,rxsigF[aa],1);
+	if (eNB->frame_parms.threequarter_fs==0) {
+	  if (prach_fmt == 4) {
+	    dft4096(prach2,rxsigF[aa],1);
+	  } else {
+	    dft24576(prach2,rxsigF[aa]);
+	    
+	    if (prach_fmt>1)
+	      dft24576(prach2+49152,rxsigF[aa]+49152);
+	  }
 	} else {
-	  dft24576(prach2,rxsigF[aa]);
-	  
-	  if (prach_fmt>1)
-	    dft24576(prach2+49152,rxsigF[aa]+49152);
+	  if (prach_fmt == 4) {
+	    dft3072(prach2,rxsigF[aa]);
+	  } else {
+	    dft18432(prach2,rxsigF[aa]);
+	    
+	    if (prach_fmt>1)
+	      dft18432(prach2+36864,rxsigF[aa]+36864);
+	  }
 	}
 	
 	break;
diff --git a/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp b/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp
index fc4f8d5d39..b8e9b21866 100644
--- a/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp
+++ b/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp
@@ -610,7 +610,7 @@ extern "C" {
 
     switch ((int)openair0_cfg[0].sample_rate) {
     case 30720000:
-      s->usrp->set_master_clock_rate(61.44e6);
+      s->usrp->set_master_clock_rate(30.72e6);
       openair0_cfg[0].tx_sample_advance     = 115;
       openair0_cfg[0].tx_bw                 = 20e6;
       openair0_cfg[0].rx_bw                 = 20e6;
diff --git a/targets/RT/USER/lte-enb.c b/targets/RT/USER/lte-enb.c
index e1129edb20..51ea3709e1 100644
--- a/targets/RT/USER/lte-enb.c
+++ b/targets/RT/USER/lte-enb.c
@@ -1371,6 +1371,14 @@ void init_eNB_proc(int inst) {
     pthread_cond_init( &proc->cond_prach, NULL);
     pthread_cond_init( &proc->cond_FH, NULL);
     pthread_cond_init( &proc->cond_asynch_rxtx, NULL);
+
+    pthread_attr_init( &proc->attr_FH);
+    pthread_attr_init( &proc->attr_prach);
+    pthread_attr_init( &proc->attr_asynch_rxtx);
+    pthread_attr_init( &proc->attr_single);
+    pthread_attr_init( &proc->attr_fep);
+    pthread_attr_init( &proc_rxtx[0].attr_rxtx);
+    pthread_attr_init( &proc_rxtx[1].attr_rxtx);
 #ifndef DEADLINE_SCHEDULER
     attr0       = &proc_rxtx[0].attr_rxtx;
     attr1       = &proc_rxtx[1].attr_rxtx;